1996_Sumitomo_Metals_Image_Processing_LSI_and_Modules 1996 Sumitomo Metals Image Processing LSI And Modules

User Manual: 1996_Sumitomo_Metals_Image_Processing_LSI_and_Modules

Open the PDF directly: View PDF PDF.
Page Count: 771

Download1996_Sumitomo_Metals_Image_Processing_LSI_and_Modules 1996 Sumitomo Metals Image Processing LSI And Modules
Open PDF In BrowserView PDF
1996

<8>
SUMITOMO
METALS

Sumitomo Metal Industries

IMPORTANT NOTICE
While Sumitomo Metal Industries, Ltd. (hereinafter "SMI") believes that this manual is accurate and complete
as of its date of issuance, SMI assumes no liability for damages or injuries resulting from any errors or omissions
in this manual, or from the use of information contained in this manual. SMI reserves the right to revise this manual and to make changes from time to time in the content hereof without having any obligation to notify any person,
including without limitation purchasers of the products described herein, of such revision or changes. SMI also
reserves the right to make changes in the products or to discontinue any such product without notice and advises
purchasers to obtain the latest version of relevant information before placing any order, to verify that the information being relied on is current.
The circuit diagrams described herein are shown merely as typical examples of product applications and are
not intended to guarantee operation of any circuit designed by the purchaser. SMI makes no warranty of any kind
as to user support in the application of this product, nor assumes any responsibility for customer designs, or
infringement of any of their party's patents, copyrights or other intellectual property rights resulting from the use of
the products described in this manual.
Use of the products described herein in certain applications ("Critical Applications") may involve potential
risks of death, personal injury or severe property or environmental damage.
THE PRODUCTS DESCRIBED HEREIN ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Use of the products described in this manual in any Critical Application requires the prior written approval of
an authorized representative of SM!. In order to minimize risks associated with the purchaser's applications, adequate design and operating safeguards should be established by the purchaser to minimize inherent or procedural hazards.
The products described herein generate, use and can radiate radio frequency energy. Operation of such
product in a residential area is likely to cause radio interference, in which case the purchaser, at his own expense,
will be required to take whatever measures may be required to correct the interference.
SMI makes no representation or warranty that any license, either express or implied, is granted under any
patent right, copyright, mask work right or other intellectual property right of SMI covering or relating to any combination, machine or process in which the products described in the manual might be or are used.
No part of this manual may be copied or reproduced in any form, or by any means, without the prior written
approval of SMI.

© Copyright 1995
All rights reserved
Sumitomo Metal Industries, Ltd.
The company names and products names which appear in this manual are the
trademarks or registered trademarks of their respective companies.

WARNING
Use of the products in certain applications ("Critical Applications") may involve potential risks of death, personal injury or severe property or environmental damage.
THE PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE
FOR USE IN LIFE SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Use of the products in any Critical Application requires the prior written approval of an authorized representative of Sumitomo Metal Industries, Ltd. In order to minimize risks associated with the purchaser's applications,
adequate design and operating safeguards shouldbe established by the purchaser to minimize inherent or procedural hazards.
.

Sumitomo Metal Industries
REAL-TIME IMAGE PROCESSING LSIs/MODULES
DATA BOOK
Table of Contents

LSI Chips
IP90C01

(HIST) Histogramming Processor ... TM VER. E 3.1

..............................

High-performance histogramming processor for 8-bit gray scale images. Max freq of
50 MHz or 20 MHz (IP90COI-LC). QFP 64-pin plastic package.

IP90C05A

(proJ) Projection Processor ... TM VER. E 2.2 . ................................... 1!111~

X-y axes projection processor for 8-bit gray scale images. Max freq of 20 MHz or
30 MHz (IP90C05A-HS). QFP 64-pin plastic package.

IP90C08

_i,

(templa) Template Matching Processor ... TM VER.

'
,'.

E 1.3 .........................

_~

Two-dimensions template matching processor for 8-bit 16X7 template size.
Max freq of 30 MHz. QFP 160-pin plastic package.

IP90C10

!

(LABop) Labeling Accelerator ... TM VER. E 1.4 . ................................. _~

High-speed automatic labeling accelerator for whole labeling processes.
Max 4094 labels. Max freq of 40 MHz. QFP 120-pin plastic package.

IP90C11

(LABop1 K) Labeling Accelerator ... TM VER.

E 1.5 ............................... _ _

High-speed automatic labeling accelerator for whole labeling processes.
Max 1022 labels. Max freq of 20 MHz. QFP 120-pin plastic package.

IP90C15

(Sketch) Image Data Reduction Processor by Averaging ... TM VER. E 1.4

.. ..... ..

Real-time image data reduction processor by summing and averaging.
Max freq of 40 MHz. QFP 64-pin plastic package.

IP90C18

(Feature) Features Extracting Processor ... TM VER. E 1.1

. ....................... _

High-performance features extracting processor.
Max freq of 20 MHz or 40 MHz (IP90CI8-HS). QFP 160-pin plastic package.

IP90C20

(RKFiI) Rank Value Filter ... TM VER. E 1.4 . ..................................... .
High-speed rank value filter for computing median, minimum
or maximum value. Max freq of 50 MHz. QFP 44-pin plastic package.

IP90C25

(SLFC) Spatial & Logical Filter ... TM VER. E 2.3

................................ .

(MAC4) Multiplier & Accumulator with 4 Multipliers ... TM VER.

E 1.4 . ............ .

High-speed single processing multiplier and accumulator. Max freq of 30 MHz.
QFP 160-pin plastic package.

IP90C32

(CAROL) Configurable Arithmetic Operator ... TM VER. E 1.5

.

I:I1II
.

Programmable high-speed spatial and logical filter. Max freq of 25 MHz or 50 MHz.
(IP90C25-HS) PLCC 84-pin plastic package.

IP90C31

1iIII

111
111

..................... _

Floating point operator with configurable data bus architecture.
Max freq of 30 MHz. QFP 160-pin plastic package.

IP90C51

(IMBC) Image Data Bus Controller ... TM VER. E 1.2 . ............................ . _
Interface controller for digital image data bus. Max freq of 36 MHz.
QFP 64-pin plastic package.

IP90C55

(IMSC) Image Data Stream Controller ... TM VER. E 1.3 . .......................... _
Digital image data stream switcher. Max freq of 20 MHz, QFP 184-pin
plastic package or 40 MHz. PCA 181-pin ceramic package (IP90C55C).

SIDIP Modules
IP90MD08

IP90MD10

Template Matching Module ... PM VER. E 1.1 .................................... _
Template matching module with core template matching chip (IP90C08) and
peripheral circuitry. Single size. (48.8mm x 127.0mm)

---.J,

Labeling Module ... PM VEA. E 1.3 . ............................................. ~,
Entire labeling module with LABop (IP90ClO) chip and peripheral circuitry.
i
Double size. (98.6mm x 127.0mm)
!

IP90MD15

Sketch Module ... PM VER. E 1.2 ................................................
Averaging image data reduction and simple image data expansion module with
Sketch (IP90C15) chip and peripheral circuitry. Double size. (98.6mm x 127.0mm)

IP90MD20

Rank Value Filter Module ... PM VER. E 1.2 . .....................................
Rank value filter module with RKFil (IP90C20) chip and peripheral circuitry.
Single size. (48.8mm x 127.0mm)

IP90MD25

Spatial & Logical Filter Module ... PM VER. E 1.1 .. .............................. .
Spatial and logical filter module with SLFC (IP90C25) chip and peripheral circuitry.
Single size. (48.8mm x 127.0mm)

IP90MD811 Histogram 1 Projection Module ... PM VER. E 1.2 . ................................
Five types offered. They have one or two functions in 8-bit value histogramming (IP90COl)
01/05
and / or X-Y axes gray level projection (IP90C05A-HS). Single size. (48.8mm x 127.0mm)

IP90MD100 Frame Memory Module ... PM VER. E 1.1 ....................................... .
Expansion frame memory for image processing systems which has
two frames capability. Single size. (48.8mm x 127.0mm)

Baseboards
IP90BD301

IP90BD351

i

Baseboard for ISA bus (PC/AT) ... PM VER. E 2.1 ................................
Gray scale frame grabber board with two image stream exchange chips
(IP90C55). 3 slots for SIDIP modules.
Expansion Board for ISA bus (PC/AT) ... PM VER. E 2.1
3 slots for SIDIP modules.

~

m

I

i

1iIIII
IEIII~
,

liIIi'

l

I!II
,
!

IP90BD550 Baseboard for VME bus (6U) ... PM VER. E 1.3 ................................... _
Expansion board with two image stream exchange chips (IP90C55).
4 slots for SIDIP modules.

1
i

IndustryPack
IP90MS800 Area Sensor Image Frame Grabber ... PM VER. E 1.2 ............................. _
An 8-bit monochrome frame grabber for area sensors with IndustryPack standard.
IndustryPack double wide.
IP90MS803 Line Sensor Image Frame Grabber ... PM VER. E 1.2 . ............................
An 8-bit monochrome frame grabber for line sensors with IndustryPack standard.
IndustryPack double wide.

EII~

SMIASSP
Image Processing LSI Series

IP90COI
Histogramming Processor (HIST)
Sumitomo Metal Industries, Ltd.
Technical Manual Ver. E 3.1

•

Sumitomo Metal Industries, Ltd.

...

~

~,.•.

Table of Contents
Section 1:
1.1
1.2
1.3

Section 2:
2.1
2.2
2.3

Section 3:
3.1
3.2
3.3

Section 4.
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9

Section 5:
5.1
5.2
5.3
5.4

Overview
Product Overview.......................................................................................................
Basic Specifications.. ...................... ........ ...... ................ .......... .......... .........................
Block Diagram...........................................................................................................

1
1
2

Pin Functions
Pin Placement and Pin Assignments... ............... ....................... ...................................
Pin Descriptions.........................................................................................................
External Dimensions...................................................................................................

3
5
6

Registers
Register List (Write Only).........................................................................................
Mode Register (2-bit)..................................................................................................
Vertical, Horizontal Processing Width Register.........................................................

7
7
7

Operating Description
Overview of Operation..............................................................................................
Histogram Processing .................................... ,..... ... ............ ... ...... ...... ......... ..... ..... .... ...
Reading of Histogram Processing Results....................................................................
Clearing the Results of Histogram Processing.............................................................
Operating Flow .................... ;.....................................................................................
System Operation Timing Charts ....... ............. ................ ....................... ....................
Dummy Cycle HS and VS Input..................................................................................
Image Clock Input (CLK)............................................................................................
HS*, VS* Signal Input at Start of Field.....................................................................

8
8
8
9
9
10
11
11
11

Electrical Characteristics
Absolute Maximum Ratings ........................................................................................
Recommended Operating Conditions ...........................................................................
DC Characteristics................... ..................................................................................
AC Characteristics.....................................................................................................

A-i

13
13

13
14

Section 6:
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8

Sample Applications

6.9

Basic Histogram ........................................................................................................ .
Sample Connections to the IP90C51 (non-interlaced mode) ......................................... .
Histogram Processing of Interlaced Image Input: 1. .................................................... .
Histogram Processing of Interlaced Image Input: 2 ..................................................... .
Circuit Diagram: 12-Gradient Grayscale Image Data ................................................ .
Pixel Control During Histogram Processing with Clock Signal Stopped ..................... .
Histogram Processing of Designated Shapes .............................................................. .
Histogram Processing of Separate Local Areas .......................................................... .
Area Measurement. .................................................................................................... .

6.10
6.11

Area Measurement of Linked Areas ........................................................................... . 33
Sample Applications Outside of Image Processing ..................................................... . 34

A-ii

19
20
21
24
28

llIi
bJ:l

.S

29
30

.o ~ '"
~
0" ~

31
32

Q. 0 '"
-tl~

~ ~g

:E

Section 1. Overview
1.1

Product Overview
The IP90COI is a single-chip LSI processor for grayscale histogram processing. The IP90COI is
manufactured using the latest CMOS processes and high-speed circuit technology. The IP90COI has
a maximum operating speed (input image data transfer rate) of 50 MHz, and can process both noninterlaced and interlaced image data. The IP90COl can process 8-bit grayscale pixel images in realtime, up to a maximum size of 1023 x 1023 pixels.

1.2

Basic Specifications

Histogram Processing Functions
•

•

•
•
•

Histogram processing of 8-bit grayscale images
Maximum image processing area: 1023 x 1023 pixels
Maximum operating frequency:
50 MHz (IP90COI without rank code)
20 MHz (IP90COl-LC)
Horizontal and vertical dimensions of the processing "window" can be set using a
programmable lO-bit counter.
Synchronized with external horizontal and vertical synchronization signals
One-shot clearing of histogram data

External Interfaces
•
•

•

General interface through 16-bit bus
Mode register for operating mode settings:
Histogram processing mode
Histogram processing results read mode
Memory clear mode
Data readout by word:
20-bit data upper-word/lower-word selection (selected by DSI *, DSO* pins)

Other
•
•
•
•

Process:
Power supply:
Input/ output interface level:
Package:

CMOS
5V single power supply
TTL compatible
QFP 64-pin (plastic)

A-I

.'
•

,i,·.

1.3

Block Diagram
ID7-IDO
VS*
VS*
CLK

IMAGEOATA
EXTERNAL
SYNCHRONOUS ~
INTERFACE

COUNTING
MEMORY

MUX

AS-AO
AS'
OSO'
OSI'

PROCESSOR
INTERFACE

BUSY'
WR'
015-00·~

RST'

T2-TO

IP90COl Block Diagram

A-2

@+ INTERFACE
MEMORY

Section 2.
2.1

Pin Functions

Pin Placement and Pin Assignments

IP90COl

"O~6* * * "O~~~~r-"O~'Dtr)

~ cns~ ~:fl~ 0 00 p:8~0 8 8
48

.15

o
T- ~ 0
~

49

32

GNO

u

ill

a: 50 ~
Q. 0

WR'
T2
Tl

TO

:E

IP90COI

Vdd

BUSY'

00

Japan

Dl

02

XXXXXX

GNO

03
04
05

Vdd

17
16
ooaoooo«oaooo~<

~~600~O=~~NS~~~oE

IP90COI-LC
48

33

49

32
=:=J
==:=!
==:=!

+SUMITOMO
METALS©

=
=
=
=

IP90COI
Japan

==:=!

=:=J
=:=J
=:=J

xxxxxx

LC

==:=!
==:=!

=
=

==:=!

64

17
16

The IP90COl and IP90COl-LC have different markings, but have identical pin
assignments.
A-3

~

-t1~

.SUMITOMO
METALS©

GNO

Note:

0.0

33

Pin Assignment Table
Pin No.

Name

Pin No.

Name

Pin No.

Name

1

D6

23

A6

45

AS*

2

D7

24

A7

46

DSO*

3

GND

25

A8

47

DSl*

4

D8

26

GND

48

Vdd

5

D9

27

Vdd

49

GND

6

D10

28

IDO

50

WR*

7

D11

29

IDI

51

T2

8

Vdd

30

ID2

52

T1

9

Vdd

31

ID3

53

TO

10

D12

32

ID4

54

GND

11

GND

33

ID5

55

Vdd

12

D13

34

ID6

56

BUSY*

13

D14

35

GND

57

DO

14

D15

36

Vdd

58

Dl

15

AO

37

ID7

59

D2

16

Vdd

38

RST*

60

GND

17

GND

39

eLK

61

D3

18

Al

40

GND

62

D4

19

A2

41

GND

63

D5

20

A3

42

Vdd

64

Vdd

21

A4

43

HS*

22

A5

44

VS*

A-4

2.2

Pin Descriptions
Description

Pin Group

Pin Names

Image input bus

CLK

1

I

Pixel sync clock signal

ID7-IDO

S

I

S-bit pixel data bus

HS*

1

I

Horizontal sync signal

VS*

1

I

Vertical sync signal

WR*

1

I

Register write signal

CPU bus

No. of Pins/(I/O)

AS*

1

I

Address signal

DSl*

1

I

Memory data upper-word select signal

DSO*

1

I

Processor data verify signal and
memory data lower-word select signal

AS-AO

9

I

9-bit address bus

DIS-DO

16

I/O

BUSY*

1

0

BUSY* signal; BUSY* is low during
histogram processing

RST*

1

I

System reset: clears memory and
registers

Power supply,

Vdd

9

PW

SV power supply

ground

GND

10

PW

Ground

Other

T2-TO

3

I

Total pins

64

A-S

16-bit processor data bus

Test signal (set high when in use)

2.3

External Dimensions
10+--------17.2 ± 0.3-------~
o00

~---'---14.0 - - - - - - O O..i1

48

o

33
I
I

49

o00

32

o

I

I

I

I
I
I
I
I

I

o

;!

I

I

--------------+-------------I

~~ITTnnTnTn~~ITnTr~nTrrr.-~=17~--~
I
I
I

16

~L<>,'ol5l@

JI-

I

units: mm

0.10

~::C2::==~--j

A-6

0.lS±0.05

Section 3: Registers
3.1

Register List (Write Only)
Table 1 shows the address of each register. Registers are selected by the address signal pins A8AO, and register settings are made through the processor data bus. Write access to registers requires
enabling the register write signal WR* and the processor data bus verify signal DSO*.

III

Bi t
Register

Address

15 14 13 121110
3 2

9 8 7 6 5 4

Always 0

I

1

0

Start histogram
processing

Clear memory

Mode register

001h

V register

002h

Always 0

Vertical size of processing area

H register

004h

Always 0

Horizontal size of processing area

Table 1: Register List

3.2

Mode Register (2-bit)
The mode register has a 2-bit configuration and controls the IP90C01's operating mode (histogram
processing mode or memory clear mode). The mode register is set through bits D1-DO of the data
bus. (The upper 14 bits D15-D2 are not used and should be set to 0, but are available for upwardlycompatible products.)

(1) Memory Clear Mode
bit 0:

Write 1 to this bit to clear the IP90COl's memory. The time required to clear the memory
is the same as the system reset pulse width. To release the clear setting, write 0 to this
bit.

(2) Histogram Processing Mode
bit 1:

3.3

Write 1 to this bit to put the IP90COl in histogram processing mode. The chip then
begins histogram processing at the next VS* pulse. When histogram processing is
finished, this bit is automatically reset to 0 (so there is no need to write 0 to this bit).

Vertical and Horizontal Processing Width Registers
(1) V Register (10 bits)
This register controls the vertical size of the processing area (from 1-1023), using processor data
bus bits D9-DO.

(2) H Register (10 bits)
This register controls the horizontal size of the processing area (from 1-1023), using processor data
bus bits D9-DO.

A-7

Section 4. Operating Description
4.1

Overview of Operation
The IP90COI performs real-time histogram processing on screen units of S-bit grayscale image data,
at processing speeds (input image data transfer rates) from 500 kHz to 50 MHz. The IP90COl can
handle image types from NTSC-format to high-density image format. In addition, it provides
independent vertical and horizontal register settings to set the processing area to any size from 1 x
1 to 1023 x 1023 pixels.

4.2

Histogram Processing
Histogram processing on the IP90COI uses a special memory designed exclusively for histogram
processing, along with the proprietary Dynamic Allocated Computing Method developed by
Sumitomo. Once bit 1 in the mode register is set to 1, histogram processing begins when eLK falls
after the next VS' pulse. The vertical dimension of the processing area is controlled by counting
the number of HS' pulses according to the setting of the V register. Similarly, the horizontal
dimension is controlled by counting CLK signals according to the setting of the H register. Once the
IP90COI has processed the area set by the V and H registers, it resets bit 1 of the mode register,
and histogram processing ends.
Once bit 1 of the mode register is set to 1, the IP90COI sets BUSY' low. After histogram processing
is completed, BUSY' is reset to high at the next VS' pulse. For the relationship of the I/O
signals used in histogram processing, see Section 4.6, "System Operation Timing Charts."

4.3

Reading Histogram Processing Results
The results of histogram processing can be read from a special memory table. Giving the MSB of
the address the value 1, the lower S bits can be read as 20-bit histogram data values,
corresponding to each bit in the S-bit grayscale image. Table 2 shows how memory space is
assigned.
AS

A7

I

A6

1

I

I

AS

A4

I

A3

I

A2

I

Al

I

AD

S-bit grayscale data
Table 2: Memory Space Assignment

To read the lower 16 bytes of the histogram data, the address verification signal AS' must be
enabled while DSO* is enabled. To read the upper 4 bits, DSI * must be enabled. However, AS'
must be enabled for every word. Table 3 shows the relation between address and grayscale values.
Grayscale Value

Address AS-AO

Histogram data (20-bit)

0

100h

D3-DO, DIS-DO

15

10Fh

(upper word), (lower word)

255

1FFh

Table 3: Relation Between Addresses and Grayscale Values
in Reading Results of Histogram Processing

A-S

4.4

Clearing Histogram Processing Results
The results of histogram processing can be cleared from memory by sending a low-level reset signal
RST*, or by writing 1 to bit 0 of the mode register.

4.5

Operating Flow
The following chart shows the flow of IP90COl operation.

A minimum 200-ns low-level pulse is applied.
(The IP90COI-LC requires a minimum 300-ns
low-level pulse.)

Write memory
clear bit

The CPU writes the value OOOI(h) to the mode
register to clear memory. (The value OOOO(h) cancels
the clearing operation.)

Set V, H registers

The CPU sets the horizontal and vertical dimensions
of the processing area.

Write histogram
processing start bit

The CPU writes the value 0002(h) to the mode register.
(The IP9OCO 1 chip automatically resets the histogram
processing start bit to 0 after the process ends.)

Execute histogram
processing

Is BUSY*
low?

When the histogram processing start bit (described above)
is set, the IP90COI chip does the following:
(I) Sets BUSY* low.
(2) Starts histogram processing simultaneously with VS*.
(3) Stops processing after the number of CLK signals
determined by the horizontal processing width register,
and the number of HS* pulses determined by the vertical
processing width register.
(4) With the next VS*, BUSY* returns to high.
Yes

No

Read processing results

The CPU verifies that BUSY* is high, then reads
the memory contents.

A-9

4.6

System Operation Timing Charts
Figure 4-1 shows the signals and timing relationships necessary for IP90C01 system operation. The
figure also shows the signals and dummy cycles used for histogram processing.
(1) First row of field

ff~--'

eLK

,--------ff----------------------ff----------------

VS*
HS*

"""_"'".
"'"
..... _!'''''''.---~--'----'----'Iff

ID

not valid

(l,I)

(l,2)

(l,3)

(l,4)

I-~~~~~~~~~~~~~

I
(l,m-I)

(l,m)

BUSY* - - - - - - - - - - - - - ( ( - - - - - - - - - - - - - - - - Low

))

(2) Second row

eLK

ff~--

VS*

- - H - i g - h - - - - - - - - - - - f f - - - - - ------------

HS*

~--------ff-----------------

ID

~=.
-.-·-c:----l-:----'---,--'--~Iff-.J.--..J.I
..
~~~~~~~~~~~=~~
\

not valid

(2,1)

(2,2)

(2,3)

(2,4)

(2,m-l)

(2,m)

last data from I st line

BUSY* -----~------((----------------Low

))

(3) nth row (last row of valid data)

eLK

ff~--'

VS*

--H-,-i-gh-----------JJ------------------

HS*

~r---------fJ-----------------

ID

'-I':-'-"'-"'.,-·"'.""'·"""-----'----'----'-----'Iff--'---~I
=~~==~~=~~===~
\
not valid (n,1)
(n,2)
(n,3)
(n,4)
(n,m-I) (n,m)
last data from n-Ith line

BUSY* -----~------((----------------Low

))

(4) n+lth row (terminator row)

eLK
VS*
HS*

JJ~

-~----------«----.
,-High
))
L----J

~--------JJ~

ID
(n+I,mJ

BUSY*

line

- - - - - - - : Low
- - - - - - - - f - -) - - - - '

Note:

At the next VS', BUSY' goes high and the IP90C01 switches into a
mode that allows processing results to be read.
Figure 4-1: Histogram Processing Timing Charts

A-10

4.7

Dummy Cycle HS and VS Input
Figure 4-1 (4) shows cycles that are required for reasons other than data input. These cycles are
defined in units of one clock pulse width. This means that an HS' cycle is a cycle of one clock
pulse width in which HS' goes low, and a data input cycle is one clock cycle in which one set of
grayscale values is input. The dummy cycle required at the end of a field includes the VS' cycle
that indicates the start of a field, the HS' cycle that marks the start of a line, and the data
input cycle. This dummy cycle follows the input of the last row of data and includes one cycle
beyond the width of the H register, as well as the following VS' cycle. In effect, the HS' cycle
introduces one row of dummy input data followed by a VS' cycle, as shown in Figure 4-1 (4).
Images from CRT screens and CCD camera devices use blanking, and normally present no problem
as input. However, images transferred from CPU space or DMA transfer may come without
blanking or in compressed format.

4.8

Image Clock Input (ClK)
The image clock signal is normally present, and systems should be designed accordingly.

4.8.1

Conditions for Stopping the Clock While the CPU Reads Results

The image clock signal is not involved in reading histogram processing results, and so can be
stopped while results are read. To assure control stability, however, observe the same conditions
as for histogram processing without the clock signal, as described below.

4.8.2

Stopping the Clock Signal During Histogram Processing

Histogram processing at high speeds is made possible by incorporating dynamic circuits into the
IP90COl. For this reason, the technical documentation places maximum limits on the clock signal
frequency (Tcc). To ensure circuit stability, input the image clock signal at all times. When this is
not possible, or when operating close to the maximum frequency, make sure the image clock signal
CLK remains high.

4.9

HS* and VS* Input at Start of Field
4.9.1

Basic Timing Pattern - Figure 4-2 (1)

The basic timing pattern (as described in Figure 4-2 (1) and Section 5.4, "AC Characteristics")
assumes that a field's first VS' and HS' pulses are input in the same cycle of the clock signal.

4.9.2

VS* Pulse and HS* Pulse Not Timed Together - Figure 4-2 (2)

Note the timing of the VS* and HS* pulses in Figure 4-2 (2). When the VS' pulse is input at the
start of a field, but the HS' pulse is not input at the same time, the V counter that determines the
vertical size of the image area is 1 higher than in the basic pattern described in Section 4.9.l.
This affects the sequence of internal processing like this: Histogram processing starts with the
data that accompanies the next clock signal received after the HS* pulse input following the VS'
pulse. By the time this delayed HS* pulse is detected, however, the V counter has already
recorded one pulse count. To allow for this, the setting written into the V register must be increased
by one. In comparison, the basic pattern described in Section 4.9.1 (in which the VS* and HS*
pulses arrive together) allows the loading of data from the V register to take priority over the V
counter cycle, so that no V counter value is recorded before the cycle starts.

A-ll

(1) Standard HS*, VS* pulse input timing (start of field)
Example: timing when VS* and HS* are input simultaneously

CLK

r~--

VS*

---------------%--------------

HS*

-------jj

~--

DI.R..•R.~m2R.
. ~mr---,----,---.----,Irr

ID

invalid data

(1,1)

(1,2)

(1,3)

(1,4)

~~.
(1,m-l)

(I,m)

t

V counter: n preset
V count: n

(2) Timing When VS* and HS* are offset (start of field)

CLK
VS*
HS*
ID
(1,1)

V counter: n preset
V count: n

Note:

t

V count: n-I

An asterisk following a signal name indicate inverse logic.
Figure 4-2: VS*, HS* Pulse Input Timing

A-12

V count: n-I

Section 5. Electrical Characteristics
5.1

Absolute Maximum Ratings
Item
Power supply voltage

5.2

Min.

Vdd

-0.5

Max.

Unit

-

6.5

V

Vdd + 0.5

V

80

°C

Typ.

Input voltage

Yin

-0.5

-

Storage temperature

Tstg

-10

-

Recommended Operating Conditions
Symbol

Min.

Typ.

Max.

Unit

Power supply voltage

Vdd

4.75

5.0

5.25

V

Input voltage

Yin

0

-

Vdd

V

Ambient temperature

Ta

0

-

70

°C

Item

5.3

Symbol

DC Characteristics
Item

Symbol

Conditions

Min.

Max.

Unit

2.4

-

V

Voh

Vdd = Min., Ioh = 0.4 rnA

Low level output voltage

Vol

Vdd = Min., 101 = 4.0 rnA

-

0.4

V

High level input voltage

Vih

-

2.4

Vdd

V

Low level input voltage

Vil

-

0

0.8

V

10

~

High level output voltage

Input leak voltage

Iix

GND :;; Yin :;; Vdd

-10

Output off- leak voltage

Ioz

Vdd = Max.

-25

25

~

Operating current

Ice

Tee = 20 ns (IP90C01)

-

200

rnA

Tee = 50 ns (IP90C01-LC)

-

100

-

A-13

5.4

AC Characteristics
Image data input timing
TcpH
TcpL
f...--TcC~t:~ ~

eLK

Xl
Tis:

IDG-ID7

~~_INV_A_L_ID_--,X

: [NV ALID

: Tih
VALID

~x

'------

,
: Tvh ,
- - - - ' \ - - - Tvs ----,~ r c - - - - - - - - - - - - - - - -

:

VS*

'!

~Tvp---:

_ _ _ _ _ _ _, :-- Thtv---:
\_-ThS

HS*

.

~

• Thh

~/

: _ Thp ---~~:

Units: ns
IP90COI
Item

IP90COl-LC

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Tcc

20

-

2000

50

-

2000

High level

Tcph

8

-

120

15

-

120

Low level

Tcpl

8

-

120

15

-

120

IDO to ID7 set-up time to clock fall

Tis

0

-

-

Tih

4

-

0

IDO to ID7 hold time from clock rise

-

4

-

-

VS* fall set-up time to clock fall

Tvs

11

-

Tcc

11

-

Tee

VS* rise hold time from clock fall

Tvh

3

-

Tcc

3

-

Tcc

Clock cycle
Clock pulse width:

VS* pulse width

Tvp

18

30

-

-

Ths

12

-

-

HS* fall set-up time to clock rise

Tcc

12

-

Tcc

HS* rise hold time from clock rise

Thh

0

-

Tcph

0

-

Tcph

HS* pulse width

Thp

18

-

-

30

-

-

HS* fall hold time to VS* rise

Thtv

4

-

-

4

-

-

Note 1:
Note 2:

VS* and HS* should be low, with a width equivalent to one width of the CLK (Tcc)
signal.
The maximum limit on clock cycle length applies during operation. When not in
operation, this value can be greater. If the clock is stopped during histogram processing,
the clock signal CLK should be fixed at thigh level. For details, see Section 4.6, "System
Operation Timing Charts."

A-14

BUSY Signal Timing

AO-AS

AS*

DI5-DO

DSO*

Valid address

-

/

\
Write data

u

WR*

v-\\v

VS*

BUSY*

Tb~~-

~?
Units: ns

IP90COI

Item

IP90COl-LC

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Delay from WR* rise to BUSY* fall

Ths

-

-

-

20

Delay for VS* fall to BUSY* rise

Tbh

-

20

-

20

-

-

20

A-IS

I

I
I

Data Read Cycle

A8-AO

Valid address

,

,

Tads-,

:...- Tadh
: '-- Taswh~

~, ,

,

L

\:":~~~~_-_-_T_a_sw_========~~-1/

AS*

Tasd ,~

Tasd ~

f.-

Valid data

DO-DIS

Tdbd ~
DSl*, DSO*

\

(Note)

:-- Tdbz-':

~
.....1---'--

Tdsw

'

~V

- - - - I..

,
I

WR*

Note:

]

DSl' represents upper word selection, and DSO' represents lower word selection
Units: ns
IP90COl-LC

IP90COI
Symbol

Min,

AO to A8 set-up time to AS' fall

Tads

2

-

AS' pulse width (low)

Tasw

60

-

AS' pulse width (high)

Taswh

50

-

AO to A8 hold time from AS' rise

Tadh

7

Delay time from AS* rise until DO to
D15 data becomes invalid

Tasd

Delay time from DS* fall until DO to
D15 data becomes valid

Item

Min.

Typ.

2

-

60

-

IOlls

-

50

-

-

-

-

7

-

-

5

-

55

5

-

55

Tdbd

5

-

55

5

-

55

DSO', DSl' pulse width

Tdsw

40

-

1O!lS

40

-

10lls

Delay time from DS* rise until DO to
D15 Hi-Z mode

Tdbz

5

-

20

5

-

20

A-16

Typ.

Max.
-

1O!lS

Max.

-

Register Setting Cycle
Valid address

AO-A8

:- Tas -:

:--Tah----:

\4

AS*

i~)-TaSWh~L

Tasw

BIll
"

i-- Tash

: - - Tass - - :
Valid data

00-015

: - - - - - T d s -----~~Tdh____:

WR*

\-Twrw--/
: - TddsO ----.:

DSO*

,

\-TdSOW+/
:.- TdsOs --: :-- TdsOh

The above timing chart represents a register write cycle based on the rise of WR*. In the IP90COl's
internal circuitry, AS*, DSO*, and WR* are treated the same, and the cycle is defined by the
rising edge of whichever signal rises first.
Units: ns
IP90COI

IP90COl-LC

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

AO to AS set-up time to AS* fall

Tas

10

-

-

10

AO to A8 hold time from WR* rise

Tah

2

-

-

2

-

-

AS* pulse width (low)

Tasw

50

-

AS* pulse width (high)

Taswh

50

-

Tass

50

Item

AS* fall set-up time to WR* rise

50

-

-

50

-

-

-

-

50

-

1

-

1000

1000

AS* rise hold time from WR* rise

Tash

1

DO to DIS set-up time to WR* rise

Tds

50

-

-

50

-

DO to DIS hold time from WR* rise

Tdh

5

-

-

5

-

WR* pulse width

Twrw

50

-

1000

50

-

1000

DSO* pulse width

TdsOw

50

-

1000

50

-

1000

DO-DIS set-up time to DSO* fall

TddsO

0

-

-

-

-

DSO* fall set-up time to WR* rise

TdsOs

50

-

-

50

-

-

DSO* rise hold time from WR* rise

TdsOh

0

-

-

0

-

-

A-17

-

-

System Reset Cycle
Trp -------~/

RST*

Units: ns
IP90COI

Item
RST* pulse width

IP90COI-LC

Symbol

Min.

Typ.

Max.

Min.

Typ.

Max.

Trp

200

-

-

300

-

-

A-IS

Section 6. Sample Applications
6.1

Basic Histogram
Histogram processing measures the grayscale gradient value of every pixel in the target image.
Im age bus

n bit

I
I

Histogram Module

I

I

Am

Measurement results

AD
Al
A2
2° entries (m)

Am: the number of pix els in the image
that have a given grays cale gradient n
Am-l

Sample Application
This process makes it possible to obtain s-tandards for quantifying the grayscale values of an
image, for use in image conversion (such as binary conversion) or enhancement processing.
No. of pixels

Taking this level as a threshold value
allows clear extraction of the circle
in the figure at left.

Dark
Target image (grayscale)

Light
Grayscale gradient values

A-19

6.2

Sample Connections to the IP90C51 (non-interlaced mode)
The IP90COI chip can be connected to an IP90C51 chip to provide simple control functions.
IP90C51
-

ID

-

HS*

HEN'

-

VS'

VEN*

--

CLK

ACT*

IP90COI

OD

ID

D

Q

HS*
,---

CLK

-

-

F QJ

vs'
CLK

D PRo
CLK

CV

'---

-D=-D
eLK

Q
-

(a) Sample Circuit

CLK

ID
(IP90C51)
ID
(IP90COl)

~~

VEN*
(IP9OC51)
ACT'
(IP9OC51)
HEN'
(IP90C51)
VS*
(IP90C01)
HS*
(IP9OCOI)

0'-------I~Lr-

f--------iU

LJ
LJ

~~

~~
~~

(b) Signal Timing

Figure (a) shows a sample connection in non-interlaced mode, and Figure (b) shows the signal timing for the
example. The design should provide for pulse VEN* and HEN* output from the IP90C51.
If the horizontal and vertical dimensions of the IP90COl processing area are H and V respectively, then the

Hsize and Vsize settings for the IP90C51 are H+2 and V+ 1. (An additional line of HS* pulses is required to
accommodate a dummy cycle. See the system timing charts in Section 4.6.) Adjust the image input timing to
suit the circuits used. For other IP90C51 settings, see the IP90C51's technical documentation. The above
circuit is for reference only, and should not be used in applications without carefully considering all relevant
conditions, connections, and timing requirements.

A-20

6.3

Histogram Processing of Interlaced Image Input: 1
Adding the circuits described below allows the IP90COl to be connected to an IP90C51 LSI chip to
handle interlaced image input. The additional circuits mask the second VS*, which enables
continuous histogram processing.
Example: 1 field, 5x5 pixels
• IP90COl register settings:
H register: OlOOh
V register: If VS* and HS* arrive simultaneously, OOOAh
If VS* and HS* do not arrive simultaneously (IP90C51 HOFS~l), OOOBh
(For more information, see Section 4.9 of the IP90COl technical documentation.)
•

btl

.S
... E ....

Os @
o0 ....'" u~
01 btl 0

11.

0 ....
-tl~

:E

IP90C51 register settings:
SMOD register: Olh, HWID register: OOOOh

=> Outputs a pulse of 1 clock-cycle width from its ACT* pin, and inputs this pulse at the
IP90COl HS* pin.
VWIDO,l registers:
To the VWID register corresponding to the field with the input VS*: 0005h
To the VWID register corresponding to the field with the masked VS*: 0006h
=> This is because the IP90COl requires a dummy line.
•

The third-field VS* is input to the IP90COl, allowing BUSY* to rise and processing results to
be read.
IP90C51

CLK

1

IP90COl

I

CLK

CLK

ACT*
VEN*

HS*

LD
ID7-IDO

Note:

""m_

~

CK

)

QQ*

U

)----- vs*
f~k

BUSY*

f---

ID7-IDO

-

The above sample circuits are provided for reference only. Thoroughly study all circuits
before attempting to use them in actual applications.

A-21

Ell
I

Interlace Mode Histogram Processing Example 1: IP90C01 VS* and HS*
(Note:

The IP90C51 HOFS register is set to 4, and VS* and HS* are not input simultaneously.)

First field (VS" input)
VS*

HS*--+-~~--~~
HS*--+--r~--+-,

HS*--+--r~--+-,

HS* -+-7:-"':-"':~-71:

:: :[:::~:::r:;:::1---j---j---r---i---( -i --Note:

The values B-1 in the illustration
represent IP90C01 V counter values.

Second field (VS* masked, dummy data row input)

HS* --+--i---i----;----t
HS * --+--i-->--';"---iHS* --+-+--+--+-+
HS* --+-+--+--+--h
HS*--+-~--c--+-~

Dummy data row ----... HS* --t-_-__-ci_-_-_-;~------":-:-----;~:---~---f---t---~---~---~--+--

:

:

: : :

: : : : : : :

:

:

:

:

I

I

I

I

I

:

:

: :

:

:

Third field (VS* input, BUSY" rises from low to high)
VS*
BUSY* rises ----...

~

---i----:---: ---: ---1---t---t ---t---: ---: ---:--I

I

I

I

I

I

HS*·· -- ::-~-:~=:~~~l~~J~~~l~~~l-~~~·l~~-~~~-~~:-~~~:~~·l~~
HS*-+-;":-';':-";:-~: : : : : : : :
- - -1-- -..,- - - , - - - , - - T - - - T - - - r - - - r - - -r - - -,-HS*
j- - -

--t ---1- --"i---: ---i---~ ---t ---: ---: ---:----i--I

HS*
HS*

I

I

I

I

I

I

I

I

I

I

I ___ IL ___ IL. ___ IL. __
___ j1___ -.1I ___ .JI ___ .JI ___ J.I ___ ..lI ___ ..I.I ___ L

:

:

:

:

:

:

:

: : : :

-- -:- - - -:- - - ~ - -- i - - - i - -- ~ - -- ~ - - - ~ -- - ~ - - -i -- -:- --

---:---J---J---J---J---1---1---t---l---l---L -: i

l

A-22

i

:

1

l

iii i

Interlace Mode Histogram Processing Example 1: IP90C01 VS* and HS* signals.
(Note:

The IP90C5I VEN* and ACT* signals are adjusted for simultaneous input.)

First field (VS' input)

Simultaneous
input ---.. VS*, HS* -f--c-----c--c---o
HS*-+-~~-~--o

HS*-+--r~-~--o
HS*-+--r~-+--h

HS*-+-~~-7--V~~~~~~~~~~1

Note:

The values A-I in the illustration represent IP90COl V counter values.

Second field (VS' masked, dummy data row input)

HS* -+~~~-fuUi:~~~~~+
HS*-+-4-~-~~

HS*-+-4-~-~-h

HS*-+--r~-~-h
HS*-f-~-T~-~·

Dummy data row -------.. HS* - f -__-_c-i__-_~J_----,c-:----',----J---L--L--L--~---L---L-I
I
I

I
I
I

I
I
I

I
I
I

Third field (VS' input, BUSY' signal rises from low to high)
_

I
I
' I

I

I

I
I
,

I
I
I

I
I
I

I
I
I

I
I
I

I
___ 1___ -i _ _ _ -1 _ _ _ ... _ _ _ ... _ _ _ -I- _ _ _

BUSY* rises -------.. VS*, HS*
HS*
HS*
- - -,- - - -,- - - -,- - - -, - -HS*
HS* -r-o-,-,C--7",---;"

- -1- - -""1- - - -1 - - - -t

I

,

___ 1___ ..1

___ 1I ___

,

,

I

I

I

I

I

I
I
,

I
I
I

+ ___

I
I
I
I
I
I
I
I
I
i.- _ _ _ I- ___ I- ___ 1___ _

I

I

I

I
1
I
I
- - 1" - - - 1" - - - 1- - - - 1- - -

.

-; - - -;
,
,
,

,

-

L

I
-

r - -

-- ~---~---~--

I
-1- - - -

-:- - _.

,

,

,

,

,

,

L

I

I

I

,

- - -1- - - T -- - i" - - - , - - -,- ---,- - --

I
I
__ ..I ___ ..l _ _ _ _ _ _ l. ___ l. ___ l.

I

___ L ___ L ___ I___ _

""

I ___ ....I ___ ....I _ _ _ _ _ _ I ___ LI ___ L
I ___ IL ___ II ___ 1
I___ _

~

~

I
I
- - -.,- - - ; - - -

I
I
I
I
I
I
I
I
I
I
- - - 1 " - - - ... - - - . . - - - - , . . - - -,...

I
I
---1----

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

A-23

I

I
I
I
_.1 ___ J.I ___ L
___ L ___ l. ___ ,___ _

_1 ___ ..1 ___ .J ___ .J ___ .J _

I

6.4

Histogram Processing of Interlaced Image Input: 2
Adding the circuits described below allows the IP90C01 to be connected to an IP90C51 chip to
handle interlaced image input. The additional circuits mask the second and third VS* pulses,
enabling continuous histogram processing.

Example: 1 field, 5x5 pixels
• IP90C01 register settings:
H register: 0100h
- V register: If VS* and HS* arrive simultaneously, OOOAh
If VS* and HS* do not arrive simultaneously (IP90C51 HOFS ;:: 1), OOOBh
(For more information, see Section 4.9 of the IP90C01 technical documentation.)
IP90C51 register settings:
SMOD register: 01h, HWID register: OOOOh
~

Outputs a pulse of 1 clock-cycle width from its ACT* pin, and inputs this pulse at the
IP90C01 HS* pin.
VWIDO,1 registers: 0005h
The third-field VS* is masked, so that the IP90COl enters a dummy data line instead of VS*.
The fourth-field VS* is input to the IP90COl, allowing BUSY* to rise and histogram processing
results to be read.

l

IP90C51
CLK

1

CLK

IP90COl
CLK

ACT*
VEN*

LD
ID7-IDO

f--

-

CK

LD
Note:

CK

-.

J )-QQ* -

HS*
vs*

BUSY*

ID7-IDO

Q'- Q*

I-

The above sample circuits are provided for reference only. Thoroughly study all circuits
before attempting to use them in actual applications.

A-24

Interlace Mode Histogram Processing Example 2: IP90COI VS* and HS*
(Note:

The IP90C5I's HOFS register is set to 4, and VS* and HS* are not input simultaneously.)

-

First field (VS* input)
VS*
HS)=·--"!\---+,,-,=:;:..:..:..:..:
HS*--+-~~--~~

HS * --+--i--+--i---n
HS * --+--i--+--i---n
HS*--+-~~--~~

Note:

The values A-I in the illustration represent
IP90COI V counter values.

Second field (VS* masked)

HS*-F::'::"::;:"::;'::":c:..:;.c.:.c.:;,

~~~~~~~~~~

HS*

HS*--+--i--+--i---n
HS * -f--+--+--+---h
HS* -+-~~--~~

Third field (VS* masked, dummy data row input)
I
I

Dummy data row - - . . . HS*

I
I

I
I

I
I

I
I

I

I
I

~ ~I~~I~~I~ ~J~ ~~J ~~ ~ 1~~~1 ~ ~~ 1~~~
I

I

I

I

I
I

-r - -

I

I

I

I

I

(

I
I

I

I

I

I

-1' - - - .. - - - t-- - - t-- - -I- - - -t- - - -

HS*

- - -1- - - 4 - - -..,- - - -1 - - -

HS*

- - -1- - - -,- - - -,- - - , - - -.., - - - T - - - T - - -

HS*

I
I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

r - - - r - - -r - - -,- --

---!----!---1---i---1---t---t---i---i---1- ---:- --I

I

I

I

I

I

I

I

I

I

I

___ L __ ..J- __ ..J ___ .J ___ J ___ .J. ___ .I. ___ L ___ L ___ L ___ L __ _

HS*

--+-- +--+- -1- --i ---1---r ---r---f---f --+---

i---~- --i---i---~ ---i---i---i---~ ---i ---

---!---

A-25

Fourth field (VS* input, BUSY* signal rises from low to high)

vs*
BUSY* rises - - . . .

:::::::::::

::-:I~-I~~EI~-I-~~E:-~~~-I~~f-~~~E-~~~-~- -

HS)-HS* -+-"":-"":-...;:--.,,:
HS*

:

:

:

:

_ .. -,-- - , - - - , - - - , - - -"T - - -T - - - T - - -T - - -

:

:

:

r - - -r - - -r--

HS*
t

I

I

I

I

I

I

I

I

I

(

I ___ I ___ -1I ___ -1I ___ •I ___ '"
I ___ ..
I ___ I-I ___ II ___ II __
~

!

I
- - -1-_

~

HS*

I

I

I

I

I

I

I

I

I

I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
1
- - -1- - - -;- - -""1- - -"1 - - - of - - -1" - - -1' - - - 1- - - -I'" - - -I'" - - -I- - I
j
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I

I

I

I

1

I

I

I

I

I

Interlace Mode Histogram Processing Example 2: IP90COI VS* and HS* signals
(Note: The IP90C51 VEN* and HEN* signals are adjusted for simultaneous input_)
First field (VS* input)

--+--1- --1---1---1--- f---t---t---~ ---~ --+--I

I

I

j

I

Simultaneous
input ------- VS*,HS*
HS* -t-....;--r-i----.;,

1
1
1
1
1
- - -1- _ - -1- __ -1- - - -1- __ .......

HS * -!---i----i-----r----;,

1

1

1

1

1

1

1

j

1

1

---r---

Q- rii++--::::::::-::-:-==-,

,

---:---,
___ L __ _

---1----1----1----1----1
I
I
I

--

,
---1--,,

HS* -+=~:=~:=-::;:=:..::,,I
I
I

1

--,-I- - - -I- -

HS* -!---i----i--+---;,
I
I
I

1

I
I
I

I
I
I

___ 1- __
I

I

I

I

I
I
I

I

- - -1- - - -;- - - -1- - - 4- - - 1" - - -1" - - -1" - - - 1"" - - - t- - - -I- - - -I- - I
I
I

Note:

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
I
I

I
1
I

I
I
I

The values A-9 in the illustration represent
IP90COl V counter values_

Second field (VS* masked)
1
I

I
I

II

1
1

1
1

~ ~ ~ ~ ~ ~'J~ ~~ J~ ~ ~
HS*

r--r---r---r---; ---; I
1
1

1
1

1
1

I
I

I
I

1
I

1
1

~~ ~ ~
,,

HS * -+--....;----;.-;.-...;,

-- -~ - -

HS* -+-i---+-+-;'

---:---

HS* -+---+--+-f---h

---:---

,

___ L __

HS * -+_-_~_7-:-----.-;-:- - -. .,~- ----;'1- ~ - ,

,

,

,

,

, --

- - -1-- -"'"1- - - -1- - - -1 - - - . , - - -1" - - - 1 ' - - - 1"- - -'I" - - - I"" - -

-i --I"" - -

I
I

I
1

I
I

I
1

I
I

I
1

I
I

I
I

I
I

1
I

1
I

\

I

1

I

1

I

1

,

I

I

I

A-26

Third field (VS .. masked, dummy data row input)
I

I

I

I

I

I

I

I

I

I

I

I '

I

---r --1---~- --i---1---1---r--Dummy data row ----.. HS*
HS*
HS*

-- ---;- --I

I

-~

~ ~ ~i~ ~ ~ J~~ ~ J~ ~ ~ J~ ~ ~"'J-~~-:~;-:-:-~:~:~-:-:~l-----~l-:-:-:~:-~~-:~:-:-:-I:I
I
I
I
I
I
I
I
I
I
I
T
I
I
I
I
- - -1- - - , - - - , - - -., - - - l' - - - T - - - T - - - r

I
I

I
I

I
I

- - - r - - -r - - -r ---

HS*
HS*

I

I

I

I

___ 1I ___ -1I ___ -1I ___ ".jI
1

I

I

I

I

I _ _ _ .,jI _ _ _ ",-

I

I

I

I

I _ _ - , jI. _ _ _
_ _ '"

I

I

I

I
I

~

I

I
___

r

~

___

I

I
I __ _
II

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
- - -1- - - -1- - - -1- - -.., - - -.., - - -.,. - - - 1" - - - t- - - - t- - - -I- - - -I- - - I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

I

I

I

I

I

I

I

I

I

I

I
I

t
I

I
I

I
I

Fourth field (VS* input, BUSY" signal rises from low to high)
I
I

I
I

I
I

I
I

I
I

I
I

---(---;---1---;---1---1-- -r---r ---i---i ---i --___ 1___ -1 ___ -1 ___ -1 ___ 4 ___ • ___ o4. ___ o4. ___ 1- ___ 1- ___ 1- __ _

BUSY* rises ----.. VS*, HS*
HS*
HS*
HS*
HS*

1
1

1
I

1
1

- - -1- - - -;- - -.0;- -

1

1

1

I

I

I

1
1
-..., -

1
1
-

-., -

1
1
-

-., -

-

1
1
1
1
1
1
I
1
1
1
-1" - - - to - - - I"" - - -I'- - --I'- - - -

1

1

1

1

1

I

I

I

I

1

1

I

1

- --:- -- -:- - ~ ~- - - ~ - -- ~ - -- i- -- i - -- ~ -- - ~ - - -~ - - -~ --I

I

I

I

I

I

I

I

I

I

I
r- -,-I - -

I

I

I

I

I

I

I

I

I

- - -,- - - - - - - - - - -1- - -1- - - T - - - T - - - , - - -

I

I
I
-1- - -

I

I ___ L
I ___ IL. ___ IL ___ 1
I__ _
___ 1I ___ ...1I ___ ...JI ___ ...JI __ _ .lI ___ .1I ___ 1.

1
1
1
1
1
1
1
1
1 ___ j..
1
___ 1
1___ -11___ -11___ -1I ___ 41 ___ •1 ___ +
1
1
1

1
1
1

1
J
I

1
1
1

1
1
1

___

1
1
1
1
1
I
1
1
I
I
1
1
1
1
1
- - -1- - - -;- - - 4 - - -..., - - - . , - - - . , - - - to - - - to - - - I"" - - -I"" - - -I- - - I
1
1
1
1
1
1
1
1
1
I
1
1
1
I
1
1
1
1
I
I
1
1
1
I
I
1
1
I
1

A-27

1
1
1

1
1
1
1I- ___ I1 ___ I1 __

en

en

o::;"

n
c
;:;:

T2"{)

HS*

eLK

J

:

-8:

1D10-8

,
, _

~

:8

J, 1

FI37

'---- so

IX!

,

SI

:

DSl*

~__JR~S~T:*~W~R~*}-----~_r_t_t_i_1-i~~._------~~~--~~----------~VfR~~*
I
IfAI~5,----------~HI(i-line-d~CQ4~~--- --------

T

I-

VS*

1-1- HS*

I

~~
LL.-/

I

1-1-

eLK

;3
U
o

A7..{)
Dl5..{)

I

:
:
F137
8

1

YA8:
, Y7-O S2-O

6

AS*I---I-+-+-+-4
8::
_OSO*

: AI2
,
:

AI0-8

: All -8

J

1'--_____

LS139

YO

'

2-4 decoder
S2-O Y7-O

+

EN EN EN

J, l:
L

1

~Y7

T

YO

T2..{)
1-'- ID7..{)

'-

2

:
:

------------- -------------------- -:

§ D~
8::
-

eLK RST*

DSO*

~~:,--I-

!.

~

A8
A7..{)
'0""""4

vs*

'----- HS*
32

~o

3;,'

YAO :
8:
16

I

i
:
:

C;"
j

CD

Y7-O

C

~

S2-O

JelEN EN EN
L

1

2

.---- --------- -----------------------

A7-C

RST*

Memory assignment
Each IP90CO I chip requires an enable circui t

II)

3
II)
ce

.~

FI37

T

1D7--D

"
-...
...

Q.

CD

,----c YO

YA7

I\)

II)

EN

F137

3
.....

n

SO
SI ~

YI

~

II)

~
Ul

Ll2

DSl*
RST* WR* - f - - <

iii"
ce
...

C)

EN EN EN

YI

EN

~

DSI*

T2..{)
1-1- ID7..{)

Y8

D15--D

16

A8

: ~Y15
S2-O:
Y7-O 0-+'
L12

16

AS*~----------~-t-+-t----------------------------------~~
DSO*
DSO'

e;

:
F137
:

EN EN EN

:_

Dl5-D

I-~ eLK

I

:
:
ID

}-

~

---- - _____ yl_~-}\'!ed''_c_''-

byte
address

~DO
r----~>CLK

-----.I HS*

BUSY*

-----.I VS*

-------------.""II07-IDO
IP90COI

Operating Description
Shape mask data previously stored in RAM is read using the IP90C51 frame address generator
function. The IP90COl input clock can be controlled by the RAM output data, so that while the
mask data stored in RAM is being read, the IP90COl input clock is stopped at high level, and
histogram processing is skipped. Thus, by applying histogram processing only to the non-masked
RAM data, histogram processing can be performed on selected areas of any shape. (See Section 6.6
for information about clock stopping.)
Note:

The above example is not an actual sample circuit, and is intended for reference only.
The diagrams above are conceptual diagrams only. Be sure to thoroughly study all
circuits before attempting to use them in actual applications.

A-30

6.8

Histogram Processing of Separate Local Areas
In interlace mode, a screen can be divided into multiple local areas, and histogram processing
applied to each of these areas separately. An IP90C51 can be set up to partition the image signal
into even- and odd-numbered fields, so that histogram processing can then be applied to each local
area.
Example 1: Histogram processing of 8 of 16 areas

First field: A. B. C, D
Second field: E, F. G, H

IP90OC51 x 1
IP90COI x I

Example 2: Histogram processing of 8 of 16 areas

First field: A, B. C, D
Second field: E. F, G. H

IP900C51 x I
IP90COI x I

Example 3: Histogram processing of all 16 areas

First field: A, C, E, G
First field: B, D, F, H
Second field: I, K. M, 0
Second field: J. L. N, P

IP900C51 x 2
IP90COI x 2

A-31

6.9

Area Measurement
Histogram processing of binary images can be used to measure the area of the subject image.
Image bus

Histogram module

1 bit

Measurement results

2-entry

AO
Al

Sample Applications
Histogram processing can allow detection of form defects, surface scratches, and flaws, as well as
presence or absence of items, by measuring the surface area of the subject item and comparing the
result to a predetermined standard value.
Binary images

-

o

o

-

(Flaw or missing item)

(Good item)

A-32

6.10

Area Measurement of Linked Areas
Histogram measurement of labeled images (images after label processing, in which different
gradient values are assigned to each linked area) can be used to measure the surface area (in
pixels) of each linked area in the image.
Histogram Module

8

V

QJ

Sn

~

Sl
S2

~8

S3

Measurement
results

I
Sn-I
Sn

Sn: number of pixels in each label area

Sample Applications
Histogram processing can enable analysis of particle size and definition in metal composition,
counting spherical bodies, noise reduction by threshold area value, etc.
Image after noise reduction

Labeled images
(100)
(500)

Q

~

Q

CJ

(300)

Histogram Module

--l

I

(200)

0

~

Si

100
500
2000
300

Example: elimination of linked areas
of 200 pixels or fewer

200
1000

A-33

Si: total pixels in labeled area

6.11

Sample Applications Outside of Image Processing
The IP90COl is a general-purpose statistical histogram processor, and as such can naturally be used
in applications other than image processing.

Measurement of Distribution of External Pipe Diameters

--f--, ----u

u

-

-

-

-

-

-

-

-

-

.:,, ,,

-

-- -

u

-

-

-

-

-

-

-

-- -

fJ ~otation

Subject (pipe)
Laser distance measurement

DO
Dl

NO

T

~

converter

H

I

Histogram Module

~-------. --~------~I
Dn: results of measurement of variations f - - - - - - - - j
from a theoretical perfect circle L-_-'-'D::...:::::n-..:l'--_--'

V
,

Normal value

,
Input signal variation

OK (slight variation)

Reject (large variation)

*Display of results of measurement
and calculation

Reject (central deviation)

A-34

SMIASSP
Image Processing LSI Series

IP90C05A
Projection Processor (proJ)
Sumitomo Metal Industries, Ltd.
Technical Manual Ver. E 2.2

•

Sumitomo Metal Industries, Ltd.

Table of Contents
Section 1: Overview
1.1

Functional Outline and Features .................................................................................

1

Section 2: Pin Assignment
2.1

Pin Configuration Diagram.........................................................................................

2

2.2

Pin Descriptions ....................... ......... ..................................... ....... ..... ....... .... ..... ........

4

2.3

Logic Pin Diagram.......... ..... ........................ ....... ...... ..................................................

5

2.4

Package Dimensions.. .................... ................ ... ............... .......... .... ..... ................... .....

6

Section 3: Block Diagram
3.1

Block Diagram...........................................................................................................

7

Section 4: Registers
4.1

Outline of Registers....................................................................................................

8

4.2

Mode Register ...... ..... .............. ............. .......................... ..... ............ ........ .... ...............

9

4.3

Control Register ..................... .... ............... ........ ................ ..... .... .......... ..... ... ..............

11

4.4

Mask Value Register ................. ..... .......................... ....... .......... ..... .... ..... .... .... ...........

12

Section 5: Circuit Operation and Control Method
5.1

Operation Outline......................................................................................................

13

5.2

Projection Processing in Non-Interlace Mode ................................................................

14

5.3

Projection Processing in Interlace Mode ........... ................................. ...... ..... ... .... ...... ....

16

5.4

Overflow ...................................................................................................................

23

5.5

Reading Processing Results ...... ...... .............................................................. ..... ..........

24

5.6

Control Method..........................................................................................................

28

Section 6: Electrical Characteristics
6.1

Absolute Maximum Ratings ........................................................................................

29

6.2

Recommended Operating Conditions ........... ...................... ..... ....................... ..............

29

6.3

Pin Capacitance ........ ..... ............. ............. .................. ..... ................... ....... .................

29

6.4

DC Characteristics ........... ....... ............................. ........... .................. .................. ......

29

6.5

AC Characteristics ........... ....... ........................................ ............... ................ ...........

30

Section 7: Sample Applications
7.1

Connecting the IP90C05A and IP90C51........................................................................

35

7.2

Expanding the Processing Range..................................................................................

37

7.3

Character Area Recognition .......................................................................................

38

7.4

High-Speed Character Recognition by Encoding and a Recognition Table Search.... ......

39

B-i

Section 1: Overview
1.1

Functional Outline and Features
The IP90C05A performs horizontal and vertical gray-level projection processing of 8-bit grayscale
raster-scanned images, and simultaneously stores the results in its horizontal and vertical projection
memories. The IP90C05A can process areas of up to 512 x 512 pixels; this area can be expanded by using
multiple chips, since the IP90C05A uses 18-bit-wide memory.
•

Projection processing function
Simultaneously executes vertical and horizontal gray-level projection processing of rasterscanned input images.
Performs projection processing of 8-bit grayscale image data (256 gray levels).
Contains two 18-bit x 512-pixel memories.
Mask processing can replace any pixel with any mask data.
Interlace/non-interlace compatible.
The processing area can be expanded by using multiple chips.

•

Maximum clock frequency:

30 MHz (IP90C05A-HS)
20 MHz (IP90C05A without rank code)

Note:

•

External interface
--

•

The clock duty ratio of the IP90C05A-HS is not 50% due to its
high-speed operation. Please see Section 6.5, "AC
Characteristics. "

The CPU data bus is 8/16 bits wide.

Other
Process:
Power supply:

CMOS
5V single power supply

Input/output level:

TTL compatible

Package:

64-pin QFP
Molded section (14 mm square; pin pitch = 0.8 mm)

Application examples
Detecting positions
Recognizing shapes
Detecting centers of gravity
Recognizing box frames
Performing multiwindow-based processing when connected to the IP90C51

B-1

DIll

ii

Section 2: Pin Assignment
2.1

Pin Configuration Diagram
IP90C05A

Vdd
DB7
DB6
DB5
DB4

GND
Vdd
DB3
DB2
DBl
DBO
TEST!
TEST2
Vdd

+
IP90C05A
Sumitomo
Metals ©

XXXXXX JAPAN

CE*
WR*
RD*
ADl2
ADll
AD 10
AD9
AD8
AD7
AD6
AD5

AD4

GND

AD3
AD2
ADl

CLK

ADO

64-pin QFP package (molded section = 14 mm square; pin pitch = 0.8 mm)

IP90C05A-HS

+
IP90C05A

32

Sumitomo
Metals©

XXXXXX JAPAN

HS
64-pin QFP package (molded section =14 mm square; pin pitch = 0.8 mm)
Note:

The IP90C05A and IP90C05A-HS have the same pin aSSignments. The only difference in
their appearances is the marking stamped on each. .

B-2

Table of Pin Assignments

Notes:

Pin No.

Name

Pin No.

Name

Pin No.

Name

1

FLDi

23

AD6

45

DBI0

2

IDO

24

AD7

46

DB9

3

IDI

25

AD8

47

DB8

4

ID2

26

AD9

48

GND

5

ID3

27

ADlO

49

Vdd

6

ID4

28

ADlI

50

DB7

7

ID5

29

AD12

51

DB6

8

GND

30

RD*

52

DB5

9

Vdd

31

WR*

53

DB4

10

ID6

32

CE*

54

GND

11

ID7

33

GND

55

Vdd

12

HEN

34

OVF

56

DB3

13

VEN

35

BUSY*

57

DB2

14

IDMK

36

FFLD

58

DBI

15

RST*

37

Vdd

59

DBO

16

Vdd

38

GND

60

TESTl

17

ADO

39

DB15

61

TEST2

18

ADI

40

DB14

62

Vdd

19

AD2

41

DB13

63

GND

20

AD3

42

DB12

64

CLK

21

AD4

43

GND

22

AD5

44

DBll

1.

The IP90C05A and IP90C05A-HS have the same pin assignments. The only difference in
their appearances is the marking stamped on each.

2.

An asterisk following a signal name indicates negative logic.

B-3

2.2

Pin Descriptions
No. of
Pins/Type

Pin group

Symbol

Image bus

CLK

1

I

Image Clock

Function

Description

IDO-ID7

8

I

8-bit image data input

HEN'

1

I

Horizontal data enable signal

MSB: ID7; LSB: IDO

VEN'

1

I

Vertical data enable signal

IDMK

1

I

Masking signal

Masks image data: When this pin is high,
data is replaced by the mask value
(Note 1).

FLDi

1

I

Field discriminator signal

In interlace mode, this pin must input the
discriminator signal of the currently
processed field (Note 2).

WR'

1

I

Write signal

RD'
CEo

1

I

Read signal

1

I

Chip enable

ADO-AD12

13

I

Address bus

DBO-DB15

16

I/O

FFLD

1

OVF
BUSY'

High: odd field; Low: even field.
Control bus

MSB: AD15, LSB: DBO

0

Field discriminator signal
retention output at the start
of processing

In interlace mode, this pin outputs the
discriminator signal of the field to which
the first line belongs (Note 3).
This pin is high in non-interlace mode
and after a reset.

1

0

Overflow signal

This pin is high whenever an overflow
occurs (Note 4), and is low after a reset.

1

0

Processing execution flag

This pin is low during processing and high
after a reset.

RST'

1

I

Reset

TESTl,2

2

I

Test pin

Power supply

Vdd

6

PW

5V

and GND

GND

7

PW

Ground

Other

MSB: AD12, LSB: ADO

Data bus

This signal must remain high when in use
(Note 5).

54

Note 1:
Note 2:
Note 3:

Note 4:

Note 5:

Image data replacement can be controlled pixel by pixel. For details, see Section 4.4, "MaskValue Registers."
Inputs a high signal in non-interlace mode.
This pin retains the FLDi signal for the field (1st field) input immediately after projection
processing is initiated in interlace mode. If this FLDi signal is high, the FFLD signal also
goes high; if FLDi is low, the FFLD signal also goes low. For details, see "7) FFLD Pin
Output" in Section 5.3.
If the processing range in the horizontal or vertical direction exceeds 512 pixels, the device
may run out of memory, driving OVF high. For processing in only one direction, see Section
5.4, "Overflow."
This pin is used to test the device's internal logic, and must be kept high during normal use.

B-4

2.3

Logic Pin Diagram

Image bus

Control bus

CLK

RD*

IDO-ID7

WR*

HEN*

CE*

VEN*

ADO-AD12

IDMK

DBO-DB15

FLDi

RST*

OVF
BUSY*
FFLD
TEST!
TEST2
VDD
GND

B-5

2.4

Package Dimensions
The IP90C05A has a 64-pin plastic QFP package, as shown below.

~------17.2±0.3

------...-J
00

~------

14.0

0-5°

-----_~~I

33 .
1

I
49

'"
o
+1

N

t

,

o

:!

64

16

units: mm

i

~QIO.IOI

B-6

o

Section 3: Block Diagram
3.1

Block Diagram

Image bus

.--

YEN' __

Horizontal
direction
accumulator

HEN' ___

DIll

,

CLK __

-

OAR

OAR

>-

OAR

OAH

04H

>-

05H

OAR

OIR

04H

>-

OAR

OAH

t

t
06H

09H

lOH

04H

08H

OCH

lOH

Masking
applied
Masking
not a lied

Results of vertical projection processing

B-12

r/)

N u
~
._

.... 0
0 ....

..co..

.......

~

00

OIR

04H

cagf
="c;j
o

",''''

~t)
::l .g,
r/)
0

~!5.

Section 5: Circuit Operation and Control Method
5.1

Operation Outline
The IP90C05A performs horizontal and vertical gray-level projection processing of raster-scanned
8-bit grayscale images, and simultaneously stores the results in its horizontal and vertical projection
memories.

= Lf(x, y)

Gray level projection in the horizontal direction (Y-axis):

HPR(y)

Gray level projection in the vertical direction (X-axis):

VPR(y) =

Lf(x, y)
x

When the control register's execute bit (exec) is set to 1, the IP90C05A starts projection processing the
grayscale image data of the effective area (rectangular) indicated by VEN* and HEN* after the first
fall of VEN* (detected at the falling edge of image clock CLK).

B-13

5.2

Projection Processing in Non-Interlace Mode

1) Projection Processing

=0), each frame is configured with a single field, and the IP90C05A
processes one field of image data at a time.
In non-interlace mode (scan

The diagram below shows the timing relationships between the VS*, VEN*, HEN*, and BUSY*
signals and the execute bit (exec) in non-interlace mode. When VEN* goes low after the execute bit
(exec) is set to 1, the IP90C05A drives BUSY* low and executes projection processing for the area of
interest in one frame. After processing is complete, the execute bit automatically resets to 0 and drives
BUSY* high. When BUSY* goes high, the results can be read from the internal memory .

...
00II(l------------

One fram"'e-----------~~

VS*U

(Note 1)

....
OOII(r--------

Vertical processing _ _ _ _ _ _ _ _-»~
enabled (one frame)

__ ____

VEN*~~.______________________________________~
(Note 2)

~

HEN*

~HHW~

~rl~.

:...c.::~ Area of ~

mterest

~ Area of

I

~I1~____~Il~.____~

_>1

mterest

.~

Area of
mterest

~

.~Areaof ~
mterest

BUSY*~~________________________________________~

Execute bit
(exec)

Note 1:

VS* is shown here to indicate the start of a field. VS* does not need to be input, since the
IP90C05A recognizes a low period with consecutive VS* pulses as a single field.

Note 2:

Make sure that the period when HEN* is high (HHW) and VEN* is low lasts at least
three cycles of the input clock.

B-14

2) Memory Mapping of Projection Processing Results
The diagram below shows the relationship between the projection processing results of a selected image area (m
x n) and the memory addresses.

iiiZ

*
1st line
2nd line
3rd line
4th line

m'hline

8~ ------------------- 8~
~

£0

Vertical projection memory

Horizontal projection memory
LBS

MSB

MSB

ADl, ADO (Note 1)

Address mapping
during external
access (Note 2)

.

10

01

W areas not processed

Address mapping
00

during external
access (Note 2)

b17 b16 b1S - - - - - b8 b7 - - - - - bO

LBS

ADl, ADO (Note 1)
10

01

00

b17 b16 b1S - - - - - b8 b7 - - - - - bO

1000

Result of the 1st line

1800

Result of the 1st column

1004

Result of the 2nd line

1804

Result of the 2nd column

1008

Result of the 3rd line

1808

Result of the 3rd column

100C

Result of the 4th line

180C

Result of the 4th column

:
1000 + HEX [4(m-1)]

1000 + HEX [4(n-1)]

Result of the m ill line

1000 + HEX (4m)

,,
,,,
,

Result of the n til column

1000 + HEX (4n)

,,
,,
,

Indeterminate data

17FC

17FC

Note 1:

ADO is ignored when memory is accessed using word units.

Note 2:

Addresses are represented in hexadecimal notation.

B-15

Indeterminate data

5.3

Projection Processing in Interlace Mode
In interlace mode (scan = 1), the IP90C05A can process either two fields (one frame) of image data or
one field. This is controlled by setting bit 1 (vmstr) in the mode register.

1) Projection Processing One Frame (Two Fields) of Image Data
To process two fields of image data, set the mode register's scan bit (bit 0) to 1, and the vmstr bit
(bit 1) to O.
The vertical projection processing results for two fields of image data consist of the vertical projection
processing results of the 1st field and 2nd field. These results are stored in the vertical projection
memory.
The horizontal projection processing results are stored in separate locations of the horizontal
projection memory: the results of the 1st field are stored in locations word 0-255, while the results of
the 2nd field are stored in locations word 256-511. These results can be read by programming bit 2
(hmru) and bit 3 (£1) of the control register to convert address mapping so that a frame of data can be
read in the order of the coordinates or in the order of inputs, field by field. For details, see
"2) Method for Reading Horizontal Projection Processing Results in Interlace Mode" in Section 5.5.
The diagram below shows the timing relationships between VS*, VEN*, HEN*, BUSY*, and the
execute bit (exec) when two fields are processed in interlace mode. When VEN* goes low after the
execute bit (exec) is set to 1, the I90C05A drives BUSY* low and executes projection processing for the
effective area within one frame (two fields). After processing is complete, the IP90C05A
automatically resets exec to 0 and drives BUSY* high. When BUSY* goes high, processing results can
be read from the internal memory.

;..:<1(---------- One frame - - - - - - - - - - 0 : >
....:

vs*[j

U(Note 2)

:>: <: VHW. :0lIl( Vertical processing ~
:
enabled (2nd field)
;-:_ __
VEN*~L____________~i
iL-____________~1
(Note 1)

~

Vertical processing
enabled (lst field)

HHW ~

i<- (Note 3)

HEN*
:~:~~

:~

:~

Area of
interest

Area of
interest

Area of
interest

Area of
interest

Area of
interest

~
Area of

interest I
BUSY*~~__________________________________~

Execute bit
(exec)

Note 1:

VS* is shown to indicate the beginning of a field. VS* does not need to be input, since the
IP90C05A recognizes a low period with consecutive VEN* pulses as a single field.

Note 2:

Make sure that the period when VEN* is high (VHW), which is between the 1st and 2nd
fields, lasts at least three cycles of the input clock.

Note 3:

Make sure that the period when HEN* is high (HHW) and VEN* is low lasts at least
three cycles of the input clock.

B-16

2) Memory Mapping the Projection Processing Results for One Frame (Two Fields)
The figure below shows an example of the relationship between the results of processing a selected image area
(2m x n) and memory addresses. For details on how to read the horizontal projection processing results, see
"2) Method for Reading Horizontal Projection Processing Results in Interlace Mode" in Section 5.5.

HEN' 1st
HEN* 2nd

2nd field 1st line

HEN* 1st

1st field 1st line

HEN* 2nd

2nd field 2nd line

HEN'lst

I st field 2nd line

HEN* 2nd

HEN' 2nd

2nd field mth line

HEN'lst

1st field mth line

HEN*2nd

areas not processed
c:

c:

E
'0

c

c

E

E

E

" '0" '0" ---- -- --- ---------- '0"
" '""c "2"
-5"
c
"" '"

Note: "VEN'" 1st" represents VEN'" for the 1st field.
"YEN'" 2nd" represents YEN'" for the 2nd field.

"HEN'" 1st" represents YEN'" for the 1st field.
"HEN'" 2nd" represents VEN'" for the 2nd field.

~

Horizontal projection memory

Vertical projection memory
LBS

MSB

AD!, ADO (Note 1)

Address mapping

MSB

LBS

Address mapping

AD!, ADO (Note 1)

during external

10

00

during external

10

access (Note 2)

b17 b16

b7-----bO

access (Note 2)

b17 b16

I
I 01
I b15-----b8 I

00
b7-----bO

1000

Result of the 1st field 1st line

1800

1004

Result of the 1st field 2nd line

1804

Result of the 2nd column

1808

Result of the 3rd column

180C

Result of the 4th column

1000 + HEX [4(m-1)]

Result of the 1st column

Result of the 1st field m th line
I
I
I
I
L

Indeterminate data
13FC

I
I
I
I

1400
1404
1800 + HEX

1400 + HEX [4(m-1)]

[4(n-1)]

Result of the nth column

1800 + HEX (4n)

,

,

Indeterminate data

I

17FC

Note 1:
Note 2:

IFFC

ADO is ignored when memory is accessed using word units.
Addresses arc represented in hexadecimal notation.

B-17

Indeterminate data

3) Single-Field Projection Processing
Execute projection processing for a single field by setting bit 1 (vmstr) of the mode register to 1 in
interlace mode (scan '" 1). More specifically, if the execute bit (exec) is not set to 1 when VEN' is high
(VHW) before starting the 2nd field (after finishing the 1st field), the device processes only the 1st
field.
The diagram below shows the timing relationships between VS*, VEN*, HEN*, BUSY*, and the
execute bit (exec). When VEN' goes low after the execute bit (exec) is set to 1, the IP90C05A drives
BUSY' low, and executes projection processing for only the area of interest within the field. After
processing is complete, the IP90C05A automatically resets the execute bit to 0 and drives BUSY'
high. When BUSY* goes high, processing results can be read from the internal memory.
"':<~---------

VS*u
(Note 1)

~

One frame

----------c:>~:

,

U(Note2)

:>!:<

Verticalareaof
interest (1st field)

VEN*~~'______________~i
HHW ~

k- (Note 3)

u---

Verticalareaof ~
interest (2nd field)
;-:_ _ __

~i______________~I

HEN*
:~:~:~
Area of

Area of

Area of

BUSY* ~L_in_te_re_s_t_ _in_te_re_st_ _i_nt_ere_s~tI
Execute bit
(exec)

Note 1:

VS* is shown here to indicate the beginning of a field. VS* does not need to be input, since
the IP90C05A recognizes a low period with consecutive VEN* pulses as a single field.

Note 2:

Make sure that the period when VEN* is high (VHW), which is between the 1st and 2nd
fields, lasts at least three cycles of the input clock.

Note 3:

Make sure that the period when HEN' is high (HHW) and VEN* is low lasts at least
three cycles of the input clock.

B-18

4) Memory Mapping of Single-Field Projection Processing Results
The diagram below shows the relationship between the results of processing the selected image area (m lines
x n pixels) and the memory addresses. For details on how to read the horizontal projection processing results,
see "2) Method for Reading Horizontal Projection Processing Results in Interlace Mode" in Section 5.5.

<
~
*

1st line
2nd line
3rd line
4th line

m'hline

c

c

c

c

a a a

a

areas not processed

" '0"u '0"u - - - - - - - - - - - - - - - - . - - '0"u

'0
u

.,,;

t:

c

N

Note: "VEN* 1st" represents VEN* for the 1st field .
"HEN* 1st" represents HEN* for the 1st field.

-sc

1::

'"

Horizontal projection memory
Address mapping

Vertical projection memory
LBS

MSB

ADl, ADO (Note I)
01
10
00
I
I
bl7 bl6 IbiS - - - - - b8 I b7 - - - - - bO

during external
access (Note 2)

MSB

Address mapping
during external
access (Note 2)

LBS

ADl, ADO (Note 1)
10
01
00
I
I
b17 b16 IbiS - - - - - b8 I b7 - - - - - bO

1000

Result of the 1st field 1st line

1800

Result of the 1st column

1004

Result of the 2nd field 1st line

1804

Result of the 2nd column

1008

Result of the 3rd field 1st line

1808

Result of the 3rd column

100c

Result of the 4th field 1st line

180C

Result of the 4th column

,
,
,
,
,
1000 + HEX [4(m-1)]
1000 + HEX (4m)

,
,
,
,
,
,

,
,
,
,
,

,
,
,
,
,
1000 + HEX [4(n-l)]

Result of the 1st field mth line
Indeterminate data

1000 + HEX (4n)

,
,
,
,
,
,

17FC

IFFC

Note 1:

ADO is ignored when memory is accessed using word units.

Note 2:

Addresses are represented in hexadecimal notation.

B-19

,
,
,
,
Result of the nth column
Indeterminate data

5) Single-Field Projection Processing (Split-Field Store Mode)
When processing only one field (of two) in interlace mode, the device can be placed in split-field store
mode by setting bit 0 (scan) and bit 1 (vmstr) of the mode register to 1.
In split-field store mode, the results of each processed field are stored separately in the horizontal

projection memory. The results of the first processed field (which is processed after the execute bit is
set following a reset) are stored in horizontal projection memory, beginning with word O. The results of
processing the 2nd field (which is processed by setting the execute bit but without resetting after the
1st field has been processed) are stored in the horizontal projection memory, beginning with word 256.
In contrast, the results of vertical projection processing are stored directly without being split into

separate locations. Therefore, these results are always stored in the vertical projection memory
beginning with word 0, and this data is overwritten for each subsequent processed field.
The diagram below shows the timing relationships between VEN*, HEN*, BUSY*, and the execute
bit (exec), when exec is set to 1 while VEN* is high (VHW) before starting the 2nd field (but after
processing the 1st field).
~:<~----------------Onefrrume----------------~~~:

U

vs* U

(Note 2)
~ Vertical processing >!< VHW>!<
:
enabled (1 st field)
VEN*~L-~__________~
HHW
~ (Note 3)
(Note 1)

Vertical processing ~
enabled (2nd field)

r :_ _ _ __

I

->:

HEN*
:~:~:~
Area of

Area of

Area of

interest

interest

interest

U,

~:~
Area of

Area of

interest

interest

~
~

Area of
interest

BUSY*~~______________~
Execute bit
(exec)

Note 1:
Note 2:
Note 3:

Execute bit (exec) is programmed" 1"

VS* is shown here to indicate the beginning of a field. VS* does not need to be input, since
the IP90C05A recognizes a low period with consecutive VEN* pulses as a single field.
Make sure that the period when VEN* is high (VHW), which is between the 1st and 2nd
fields, lasts at least three cycles of the input clock.
Make sure that the period when HEN* is high (HHW) and VEN* is low lasts at least
three cycles of the input clock.

B-20

6) Memory Mapping of the Projection Processing Results in Split-Field Store Mode
The diagram below shows an example of the relationship between the results of processing a selected image
area (2m x n) and the memory addresses. The horizontal projection processing results for the 1st field are stored
from word 0-255 in the horizontal projection memory, and the results for the 2nd field are stored from word 256511. For details on reading horizontal projection processing results, see "2) Method for Reading Horizontal
Projection Processing Results in Interlace Mode" in Section 5.5.

-<
~
N*
8..

-<
~
*
;!!.

2nd field I st line
1st field 1st line
2nd field 2nd line
1st field 2nd line

HEN'

2nd field
I st field

mth

line

line

mth

areas not processed

§

§

"
"
~

"

Note: "VEN'"
"VEN'"
"HEN'"
"HEN*'

"0 ------------------- '0

"
~

1st" represents YEN'" for the 1st field.
2nd" represents VEN'" for the 2nd field.
1st" represents VEN'" for the 1st field.
2nd" represents VEN'" for the 2nd field.

Horizontal projection memory
MSB

Vertical projection memory
LBS

MSB

LBS

AD1, ADO (Note 1)

Address mapping

Address mapping

during external

during external

10

access (Note 2)

b17 b16

01
I
I
I b15-----b8 I

00
b7-----bO

1800

Result of the 1st column

1804

Result of the 2nd column

1808

Result of the 3rd column

180C

Result of the 4th column

,
,,
,
,
,,
C

I

1800 + HEX [4(n-l)]

,
,
,
,
,,
,
I

L

Result of the nth column

1800 + HEX (4n)

,
,

,

Indeterminate data
17FC

IFFC

Note 1:

ADO is ignored when memory is accessed using word units.

Note 2:

Addresses are represented in hexadecimal notation.

8-21

Indeterminate data

7) FFLD Pin Output
In interlace mode, the IP90COSA's FFLD pin outputs the 1st field's field discrimination signal
regardless of whether the device is processing a frame (two fields) of image data or only a field. (In
non-interlace mode, the FFLD bit is always high.) After setting the execute bit (exec) to 1, the
IP90COSA monitors VEN* in the 1st field: when VEN* goes low, the device latches FLDi (field
identification) signal to the first fall of CLK. It then outputs the latched field discrimination signal
for the 1st field from the FFLD pin one clock cycle later. Even in the 2nd field, the FFLD pin holds
and outputs the field identification signal for the 1st field. The FFLD pin retains and outputs the
field identification signal for the 1st field even if BUSY* is driven high. When reset, it goes high.
The diagram below shows the timing relationships of CLK, VEN*, FLDi, FFLD, and BUSY'.

*

CLK
~ Vertical processing ~

---1

VEN*

enabled (1 st field)

11------lJf-i

Vertical processing
enabled (2nd field)

~

11------

(Note 1)

FLDi~

FFLD

fJfJf----------------

Unknown Value

-----------------1j------------------------

BUSy*~~__________________~Jl~------------------~rJJ

(Note 2)

BUSY*~

~j~-------------------

(Note 3)

BUSY*~

~~~______________~r_

(Note 4)

Note 1:

U =unknown value

Note 2:

This shows one frame (two fields) of image data being processed.

Note 3:

This shows only one field being processed.

Note 4:

This shows fields of data being processed in split-field store mode.

B-22

5.4

Overflow

1) Overflow During Projection Processing in Both Directions (hproj

= 0, vproj = 0)

If the horizontal or vertical processing range exceeds 512 pixels, the IP90C05A drives the OVF signal
high to indicate overflow status. It also simultaneously resets the execute bit to 0 to stop processing

and drive BUSY* high. The results of processing performed before the overflow are still valid, and
can be read from the internal memory. Overflow status can be cleared by resetting the device, which
sets OVF back to low. The timing charts below show typical overflow conditions in the horizontal
and vertical directions.

2) Overflow In Vertical Processing Area Expanded Mode (hproj = 1, vproj = 0)
Setting bit 2 (hproj) of the mode register to 1 and bit 3 (vproj) to 0 puts the device into vertical
processing area expanded mode (with a maximum range of 1024 pixels). In this mode, OVF does not
output overflow status even if the vertical processing range exceeds 512 pixels; instead, it stays low,
as it was when processing began. It also does not output overflow status when the horizontal
processing range exceeds 512 pixels.

3) Overflow In Horizontal Processing Area Expanded Mode (hproj = 0, vproj =1)
Setting bit 2 (hproj) of the mode resister to 0 and bit 3 (vproj) to 1 puts the device into horizontal
processing area expanded mode (with a maximum range of 1024 pixels). In this mode, OVF does not
output overflow status even if the horizontal processing range exceeds 512 pixels; instead, it stays
low, as it was when processing began. It also does not output overflow status even when the horizontal
processing range exceeds 1024 pixels. Note, however, that it does output overflow status when the
vertical processing range exceeds 512 pixels.
Overflow in the horizontal direction
CLK
IDO-ID7

~I~__- J '_ _-J~~'~~J~~~_ _- A_ _-J~~~

YEN*

~~--------------«~---------------------------

\~---------«~------------~=========
-----------------«~---------------J!r----------\
«,_________-J!

HEN*

ow

BUSY*

Overflow in the vertical direction
CLK
YEN*

~f

~~--------~~-----------------\

HEN"

HEN* for 1st line

,-ff--,. HEN* for 5 13th line " - - - - - - - - - -

ow _____________________-;"________~!
BUSY.

\

"/r---------------~---------

B-23

5.5

Reading Processing Results

1) Setting the Address Bus
The diagram below shows the IP90C05A's memory mapping.
Address
(AD 12-ADO)

Note: Register addresses are decoded only for
AD2 and AD3. (Register addresses are
not fully decoded.) Do not use addresses
000lh-0003h, 0005h-0007h, or 0009hOFFFh.

Mode register

OOOOh
OOOlh
0002h
0003h
0004h
0005h
0006h
0007h
0008h
0009h

Reserved
Control register
Reserved
Mask-value register

~~

Reserved

~

OFFFh
lOOOh

If.

Horizontal projection memory

If. J.

17FFh
1800h

r::

r..

When reading projection processing results from memory, each bit in control address bus AD12-ADO
has the following settings:
AD12:

Chooses between memory access and register access:
AD12 =1: Memory access
AD12

= 0: Register access

B-24

Specifies whether horizontal or vertical projection results are read:

ADll:

ADll

= 1: Reads vertical projection results

ADll = 0: Reads horizontal projection results
ADI0-AD2: Internal memory word addresses
The control address bus, when bits ADO and ADI are ignored, consists of the IS bits in
the combined horizontal and vertical projection memories. (Data for addresses outside
the processing area are indeterminate and not guaranteed.)

Control address bus
ADlO

AD9

ADS

AD7

AD6

ADS

AD4

AD3

AD2

0

0

0

0

0

0

0

0

0

a

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

1

1

1

1

1

1

1

1

ADI-ADO:

Word addresses in
Word addresses in
horizontal projection the vertical projection
memory (hex)
memory (hex)
OOOh

OOOh

1

OOlh

OOlh

0

002h

002h

1

1

003h

003h

a

0

004h

004h

0

1

OOSh

OOSh

1

1

1

OOFh

OOFh

0

0

0

0

OlOh

OlOh

1

1

1

1

0

lFFh

lFFh

1

1

1

1

1

IFFh

IFFh

Identifies IS-bit memory data for word or byte access.

For word access
Control
address bus
ADI

ADO

a

x

1

x

Data bus
OBIS OB14 DB13 OB12 DBll DBIO

Note:

DB9

DB8

DB7

OB6

OB5

OB4

DB3

0

0

0

DBIIDBO

Sixteen low-order bit are output
0

0

a

0

0

0

0

0

0

0

x means "Don't care;" it may be logic or O. ADO is ignored.

B-25

Two highorder bits
are output

For byte access
Control
address bus

Data bus

AD1

ADO

0

0

x

x

0

1

x

1

0

x

1

DB15 DB14 DBl3 DB12 DBll DB10

DB9

DB8

J DB4 J DB31

DB1 lOBO

x

x

x

x

x

Eight low-order bits are output

x

x

x

x

x

x

x

Eight middle-order bits are output

x

x

x

x

x

x

x

1

Note:

DB71 DB61 DB5

x

Inhibited

I I I I

I

Two high-

order bits
are output

x = Unknown. Values cannot be guaranteed. Logic 0 or 1 is output.

The access mode (word access or byte access) is determined by bit 4 (mdru) of the control register.

2) Method for Reading Horizontal Projection Processing Results in Interlace Mode
The following describes how to read the results of processing two fields of image data in interlace
mode as described in Section 5.3, "Projection Processing in Interlace Mode."
Horizontal projection processing results are stored in the horizontal projection memory, as shown in
Section 5.3. To read these results, set bit 0 (scan) of the mode register to 1, then set bit 2 (hmru) of
the control register to 0 or 1 to map the addresses in horizontal projection memory in either
(respectively) the order of the frame coordinates or of the inputs for each field, as shown below.
a) Addresses in order of the frame coordinates
In this mode, the horizontal projection processing results for the 1st and 2nd fields are alternately
mapped in the read address space of the horizontal projection memory. To enter this mode, set bit
o (scan) of the mode register to 1, and bit 2 (hmru) of the control register to O. Then, to arrange the
addresses in order of the frame coordinates, set bit 3 (fl) of the control register to specify whether
the first line to be projection processed in the horizontal direction is on an even field or an odd
field. The IP90C05A then maps the results on the memory addresses as shown below.
Horizontal projection memory
MSB

Address mapping
during external
access (Note 2)

10
b17-b16

01
b15----b8

00
b7 - - - -bO

1000
1004

~
~

1st line of the field specified by the fl-bit
1st line of the field not specified by the fl-bit

1008

~

2nd line of the field specified by the fl-bit

100C

~

2nd line of the field specified by the fl-bit

17F8

~

256th line of the field specified by the fl-bit

17FC

~

256th line of the field not specified by the fl-bit

,
,
,
,
,
,
,
,,

Note 1:
Note 2:

LBS

ADl, ADO (Note 1)

,
,
,
,,
,,
,,

ADO is ignored when memory is accessed using word units,
Addresses are represented in hexadecimal notation.

B-26

b) Addresses in the order of the inputs for each field (scan

= 1, hmru = 1)

In this mode, horizontal projection processing results are mapped in read address space of the

horizontal projection memory in the order in which processing is performed, and the results are
stored. To enter this mode, set bit 0 (scan) of the mode register to 1 and bit 2 (hmru) of the control
register to l. Bit 3 (£1) of the control register does not affect this mode.
First half of the memory:
Second half of the memory:

results of the 1st field
results of the 2nd field

Horizontal projection memory
MSB
LBS
ADl, ADO (Note 1)

Address mapping
during external

00

10

access (Note 2)
1000

1004
Results of the 1st field

13FC

1400
1404
Results of the 2nd field

17FC

Note 1:
Note 2:

ADO is ignored when memory is accessed using word units,
Addresses are represented in hexadecimal notation.

B-27

5.6

Control Method
The following flowchart shows the IP90C05A's control method.

Select the desired mode.

Select the execute bit (exec). (The IP90C05A automatically
clears exec to 0 after processing is finished.

Execute projection processing

BUSY*
Low?

After exec is set, do the following:

YES

1. When VEN* goes low, it drives BUSY* low.
2. The image data is processed in the area of interest marked
by VEN* and HEN*, and the results are stored in memory.
3. Processing ends three clock cycles after VEN* goes high
in interlace or I-field interlaced mode, and B USY* is
driven high. In I-frame (2-field) interlaced mode, the
device ends processing three clock cycles after VEN*
indicates that the 2nd field becomes high, and drives
BUSY* high.

NO

Read the processing results

After confirming that BUSY* is high, read the results from
memory.

B-28

Section 6. Electrical Characteristics
6.1

Absolute Maximum Ratings
Max.

Unit

-0.5

6

V

Vin/Vout

-0.5

Vdd+O.5

V

Operating temperature

Topt

0

70

°C

Storage temperature

Tstg

-10

80

°C

Item
Supply voltage
Input/ output voltage

6.2

Vdd

Typ.

Symbol

Min.

Typ.

Max.

Unit

Supply voltage

Vdd

4.75

5.0

5.25

V

Input voltage

Yin

0

Vdd

V

Ambient temperature

Ta

0

70

°C

Input rise time

Tri

0

50

ns

Tfi

0

50

ns

Input fall time

Pin Capacitance (Vdd = Vin = 0 V)
Item
Input capacitance
Output capacitance

6.4

Min.

Recommended Operating Conditions
Item

6.3

Symbol

Typ.

Max.

Unit

f=lMHz

10

25

pF

Cout

f=lMHz

10

25

pF

Symbol

Conditions

Symbol

Conditions

Cin

Min.

DC Characteristics
Item

Min.

Typ.

Max.

Unit

Input high voltage

Vih

2.4

Vdd

V

Input low voltage

ViI

0

0.8

V

Output high voltage

Voh

Vdd = 4.75,
Ioh = -0.5 rnA

Output low voltage

Vol

Vdd = 4.75 V,
Iol=4.0mA

0.4

V

Output shorting current
(Note 1)

los

Vout = OV

250

rnA

Input leakage voltage

Iix

GND:;:; Vin:;:; Vdd

20

J.LA

2.4

-20

V

GND:;:; Vout:;:; Vdd
Output off leakage voltage
Ioz
-25
25
IlA
Note 1: The output shorting current shown above IS the absolute maXlffium voltage that can be
applied to one pin for one second without causing a short.

8-29

6.5

AC Characteristics (load capacitance 30 pF)

1) Image Input Signal
I-tcyc~ f--tcpl-l

;---,.,

eLK

'
i

IDO-ID7 ~

VEN*

I

. :.

f--tcph-l

,.

I

(Note!)

i

E

~ D(~,O) 8~D_(O+I'1_)---.J)0 D(~,m)

:
:
,
,
~~+I----------~I
I ----------~I--~
I

~:-"',
tvs Ii

i

(Note 2)

~;-

It---+--Y
I'

i
i

HEN*

i

\A
:

i

!

, tfis i tfih ,

I

i

(Note3)

~;-

i
i

I)----------L-V
i i '

~,

IDMK

;-l--~

.i
I(Note4)

\(_,j4us"14U ... :

I

FLDi

I

I\!

~
Unknown va+
i
I
I
, i '~-----+i------'~-mk-~--il-~-~-:-1\1------+:-----

~!

-------1--:___________
i

: \\

:

if.-i____
i i

I

(units: ns)
IP90C05A
Typ.
Max.

IP90C05A-HS
Min.
Typ.
Max.

Parameter

Symbol

Min.

CLK cycle

tcyc

50.0

33.3

CLK high period

tcph

20.0

11.0

CLK low period

tcpl

20.0

16.0

IDO-ID7 setup time

tis

2.0

1.0

IDO-ID7 hold time

tih

7.5

7.0

VEN' setup time

tvs

2.0

1.0

VEN' hold time

tvh

7.5

7.0

HEN' setup time

ths

2.0

1.0

HEN' hold time

thh

7.5

7.0

FLDi setup time

tfis

2.0

1.0

FLDi hold time

tfih

7.5

7.0

IDMK setup time

tmks

2.0

1.0

IDMK hold time

tmkh

7.5

7.0

Note 1:
Note 2:
Note 3:
Note 4:

U =unknown value
The VEN' recovery period (time between the 1st and 2nd fields when VEN' is high) must be at
least three CLK cycles.
The HEN' recovery period (time when HEN' is high and VEN' is low) must be at least three CLK
cycles.
Data D (0,1) are overwritten by the value of the mask-value register because IDMK is high during
this period.

B-30

2) CPU Interface Timing (Write to the Register)
,
_ _ _ _ _~ I:

twcs

'..
CE*

DBO-DB15

:1

~-W-l

WR*

ADO-AD12

, : - twh -----:

t 1

\

1

1

-I

i
i

ii

-

twch

twah

1"Valid address

-------7------'x .

twds

i
1

Valid data -:..

twrs 1
~

RD*

-

1"-

twas j
~

___--'X

r - - - :-

-

-

-

L

\

n'----X~____

twdh

XL------

-

twrh
~

1

/:

:

\
(units: ns)

Min.

Typ.

Max.

twl

1.5tcyc

-

-

Parameter

Symbol

WR* low period
WR* high period

twh

O.5tcyc

-

-

CE* setup time relative to the fall of WR*

twcs

3

-

-

CE* hold time relative to the rise of WR*

twch

3

-

-

AD setup time relative to the fall of WR*

twas

3

-

-

AD hold time relative to the rise of WR*

twah

3

-

-

DB setup time relative to the rise of WR*

twds

1.5tcyc

-

-

DB hold time relative to the rise of WR*

twdh

3

-

-

RD* setup time relative to the fall of WR*

twrs

3

-

-

RD* hold time relative to the rise of WR*

twrh

3

-

-

Note 1:
Note 2:

Although the CPU need not write to each register in synchronization with the image
data clock (CLK), make sure that CLK is input even during write cycles.
Values internally set in the register require at least three CLK cycles after WR* goes
high to become valid.

B-31

3) CPU Interface Timing (Memory Read)

Jr-----

-----.N

!:'--trl~!

RD*

:
:--- trcs

CE*

\

t

I:

:I

:

i

i

/

i--- trch --:

i~

X II
r--

ADO-ADI2

~

Valid address

----~,

DBO-DBIS

High-Z
:-- trws

WR*

I~

trdd 1 +:

: (

I~~~d X

-..i

i

I

X' - - - - - - -

r- trdd2':

valid data

)

High-Z

i.- trwh --:

I
I
iI '\'

(units: ns)
Parameter

Symbol

RD* low period

Min.

Typ.

Max.

trl

1.5tcyc

-

CE* setup time relative to the fall of RD*

trcs

3

-

CE* hold time relative to the rise of RD*

trch

3

-

-

AD setup time relative to the fall of RD*

tras

3

-

-

AD hold time relative to the rise of RD*

trah

3

-

-

DB setup time relative to the fall of RD*

trddl

-

-

1.Otcyc+30

DB hold time relative to the rise of RD*

trdd2

5

-

O.5tcyc+30

WR* setup time relative to the rise of RD*

trws

3

-

-

WR* hold time relative to the fall of RD*

trwh

3

-

-

-

Note 1:

Although the CPU need not write to each register in synchronization with the image
data clock (CLK), make sure that CLK is input even during write cycles.

Note 2:

When RD* or CE* is high, the IP90C05A's data bus lines DBO-DB15 are placed in a
high-impedance state.

B-32

4) CPU interface timing (reset)
Trstl

-----~~ /

RST*

(units: ns)
Parameter

Symbol

Min.

Typ.

Max.

RST* low period

trstl

3tcyc

-

-



0

0
0

u:0
:5
0
0

0

.. ·1·· ·1····
::: !::: :-::: :

•t

'"'
E
u
o:!
o:!

'"'
.<::
U

t

:::i::::(:::
... 1....1....
···1····1····

::: !::: :-::: :
900~~~~.~
..~.~.~.~.~~~~~~~~~
600
300
0 ..........- .....1 - - - - - Shaded area

..

~

First
character

..

~

Second
character

------I~~

..

~

Third
character

B-38

"0

To external data

"g

expansion unit

!l

~

is
IHline eay

IE

ODEN* .....1---- 00 output
control
IHline elay

IF

IHline dela

IG

18bit

EXin

From sum-of-differences -~"+--------'

output from other templa
chips in cascade connection

9bit

RD*
WR*
CS*

BUSY*

AD<8 .. D>

CPU Bus
16bit

DB<15 .. 0>
8 or 16 bit
bus width

BUS8
RST*

Note 1:

An asterisk (*) following a pin symbol indicates negative logic.

Note 2:

This block diagram does not include all functions of the IP90C08. Refer to appropriate sections
of this manual for information on specific functions, timing, etc.

C-4

2.2

Operating Overview

2.2.1

Image Synchronization and Control Signals (VS*, HS*, ACT*)

This section outlines the operation of the image synchronization and control signals as used by the
IP90COS's image input and output systems. For specific details about timing, see Section 7.5, "AC
Characteristics." For an overview of pin functions, see Section 4, "Pins and Functions."
2.2.1.1

Operations Synchronized with the Pixel Clock

The IP90COS's template-matching circuits are designed to operate in synchronization with the pixel
clock signal (iCLK). Other functions, however, are not synchronized with the pixel clock: these include
selection of template data settings and CPU bus signals for internal processing settings.
The image data input signal (IA<7 .. 0> through IG<7 .. 0», the image synchronization and control
signals (HS*, VS*, VSEN*, ACT*, TMPSEL, RST*), and any expanded-area sum-of-differences input
(EXin<17 .. 0» are latched with an input flip-flop at the rise of the pixel clock signal. The sum-ofdifferences output signal (OD<17 .. 0>, which is the output signal for image data) and the control signal
(BUSY*) output are timed to the rise ofthe pixel clock signal, with a delay for external load drive.
An asterisk (*) after a signal name indicates inverse logic.
2.2.1.2

Raster Scan Input

Image data is input to the IP90COS as a simultaneously scanned signal of 7 rows of S-bit image data,
timed to the pixel clock, oriented in the direction of the raster scan, and input through the image data
input pins (IA<7 .. 0> through IG<7 .. 0». This signal enters the pipeline configuration of the IP90COS for
throughput processing in real time, where it can be used for template matching processing.
2.2.1.3

Image Synchronization Signals for Frame Recognition (VS*, HS*)

Image data entering as raster scan signals must be reconstructed in two dimensions to provide a frame
from which patterns can be recognized. This process uses the vertical and horizontal synchronization
signals VS* and HS*. VS* initiates the frame, and functions much like the vertical sync (VS) signal in
a television system (and thus its name). HS* is the line initiating signal, and functions much like the
horizontal sync (HS) signal in a television system.
The composition of a frame of image data begins when VS* cycles low, and each line within the frame
begins when HS* cycles low. A frame of image data consists of the data input during the pixel clock
cycles from one VS* signal to the next. Similarly, a line of data consists of the data input during the
pixel clock cycles from one HS* to the next. Note that in this system, any data input simultaneously
with VS* or HS* (data latched with the rising edge of the same pixel clock cycle as VS* or HS*) is
invalid, and the data latched with the next cycle is considered as the first image data in that
respective frame or line.
For internal processing, the IP90COS uses VS* and HS* as the initial loading signals for the Vent and
Hcnt counters, respectively. Vcnt and Hcnt recognize the vertical and horizontal coordinates of an
image. VS* acts as the initial loading signal for the vertical-axis coordinate counter (Vcnt), setting the
initial value of Vent with respect to the initial vertical base coordinate of the frame (Vbase). Together
with the active area signal (ACT*, described in the following section), this VS* controls the start of
the template matching process. HS* is not used to recognize image area, but acts as the initial loading
signal for the horizontal-axis coordinate counter (Hent), setting the initial value of Hcnt with respect
to the initial horizontal base coordinate of the row (Hbase). The processing area is controlled by ACT*.
For further description of the IP90COS's internal configuration, see Section 3, "Internal Configuration."

C-s

VS* and HS* are inverse logic signals, and are recognized at the rise of the pixel clock. Both are
simultaneously differentiated within the IP90C08, and become effective when a low-level signal on
the clock rise is detected following a high-level signal. Because of this simultaneous differentiation,
the low phase (low pulse width) of VS* and HS* can be any length, as long as they return to a high
level before the next active phase. System timing is described further in the following section.
2.2.1.4

Active Area Signal (ACT*)

The ACT* signal indicates that data entering the IP90C08 is valid for processing. The first VS* signal
that enters after the start of template matching (indicated by the internal execute register having been
set) is interpreted as the start of a frame to be processed. (VSEN* is also low at this time.) ACT* is used
when this frame enters the IP90C08 system, and indicates whether the local area is to be used for pixelto-pixel template matching. The IP90C08 applies template matching processing to the 16 x 7-pixel
template matching area that ends with the pixel column that is input when ACT* is taken low. Pixels
entering while ACT* is high are ignored, and no record is kept of match coordinates for 16 x 7-pixel
template matching areas that end with pixel columns input while ACT* is high. However, pixels
entering while ACT* is high are still considered constituents of 16 x 7-pixel template matching areas,
and are retained in internal shift registers until ACT* cycles low, at which time they are used for
template matching.
The IP90C08 does not send VS* at the end of a frame. Frame processing should be executed continuously
by switching between templa register sets A and B. To end processing after the input of one frame only,
set the field control flag 'fl' at bit 1 of the execute register to 1 before execution, or configure the logic
circuits to hold ACT* high after the input of one frame. The IP90C55 (IMSC) chip has a function that
sends a rectangular-area-valid signal (AOI-n*) for one frame only within the image space; this
function can also be used in combination with these features.
HS* has no effect on whether incoming data is processed.

C-6

2.2.2

The VS*, HS*, and ACT* Signals, and Spatial Coordinates

The following figure shows the relationship between VS*, HS*, and ACT*, and the coordinates of
individual pixels.
The incoming image (M x N) is input as pixel data in a raster scan image synchronized by iCLK.

Raster scan direction

•

VS', HS'
HS'
HS'

HS'

HS'
HS'
HS'

Hb: horizontal coordinate base register value (Hbase)
Vb: vertical coordinate base register value (Vbase)

•

Horizontal Coordinates
The change of HS' from high to low is detected during the rise of iCLK, and the internal
synchronous differentiation process generates a pulse signal HSpis having one clock width. HSpis
becomes the loading signal for Hcnt (which generates horizontal coordinates), and the Hbase
coordinate becomes the horizontal coordinate of the image data IA acquired on the iCLK rise
following the rise at which the change of HS* from high to low was detected. Hcnt then begins to
count upward with each iCLK signal.

•

Vertical Coordinates
The change of VS* from high to low is detected during the rise of iCLK, and the internal
synchronous differentiation process generates a pulse signal VSpis having one clock width. VSpis
becomes the loading signal for Vcnt (which generates vertical coordinates), and the Vbase
coordinate becomes the vertical coordinate of the image data IA acquired on the next iCLK rise
following the rise at which the change of VS* from high to low was detected. Hcnt then begins to
count upward with each HSpls.

•

The IP90C08 processes image data that is input while ACT* is low (when its execute flag is
enabled).

•

As shown above, ACT* should cycle to active (low) to define the active portion of each line in the
processing area. ACT* should remain high for areas not intended for processing.

C-7

2.2.3 Incoming Image Data Transfer Format

iCLK
(pixel clock)

IAto IG
(image data)
*note 2

VS(EN*

~'-rT~~--------~~tr-----~{~--------------

" - - - 1 )

~/~ ~ Jj_~ !.' __________ ,'

1)

note 1
*note 3 *note 4

VS*

(note 1)

I

I

I

*note 4

HS*

~~------~!r----~~~
I
I
I
I

--------------1 row 01 data

ACT*
(note 5)

'------lf~

l.- valid
1 row 01
data

:

/I

))

L

~

Note 1:

An asterisk (*) following a signal name indicates negative logic. VS* starts the definition of
an image field, VSEN* validates the VS* input, and HS* starts each row in the image.

Note 2:

VS* is validated if VSEN* is low during the rise of iCLK one clock cycle before VS* changes
to low. VSEN* facilitates synchronization with other image processing LSIs, image
sequencers, and similar devices, and should always be kept low when synchronization with
other devices is not needed.

Note 3:

VS* and HS* need not be input simultaneously. If HS* precedes VS*, it will be ignored. If HS*
is input simultaneously with VS*, it will be recognized.

Note 4:

Because VS* and HS* are synchronously differentiated by the internal clock signal, they
need not be input in pulse form. Any time VS* or HS* is detected at the rise of iCLK, the
system operates as though VS* or HS* has been input. After a VS* or HS* low is detected, the
signal must return to high until the next VS* or HS*.

Note 5:

ACT* should remain low throughout the valid data interval on each row.

C-8

2.2.5

Processing Delay
DIFF:
absolute value of
differences circuit

The diagram below illustrates the internal processing
delay interval. Signals enter through the image input pins
(IA through IG) and, after sum-of-differences calculation
and a minimum of 4 clock cycles, are ouput at the sumof-differences output pin (OD).
Note:

'~~:rl:-=

This clock diagram illustrates processing delay,
and does not represent all functions of the
IP90C08. See the relevant sections of this
manual for descriptions of funcitons and
timing.

: Reg.

//
/
//

one row (16

x 1 step x 8 bit) absolute value of differences

i

,
: absolute
:'' ____ ",,: value of
differences
output

~'

;'r ;

/
/
/

IA

IG

summation calculator #2
summation
calculator #3

,. ...... delay tuning circuit .......,
Ot04delay
:

:
,,

,,
,

,

FIF

F/F

i
1,,

~-,--~'~

I

L
F/F#A

D

,

:

F/F#C

I

t~. ~.~.r

F/F#B

...................

.................... " ........ ;

F/F#F
EXin

F/F#E
output
compensation bias - - - - - '
value register

C-IO

2.2.6

The Active Area Signal (ACT*) and Measurement Areas

The following illustrations show examples of how the active area signal (ACT') can be used to select
areas of the input image for matching coordinate measurement. Each example (sequence a) through
(sequence n) assumes that image data enters as raster scan input, and shows the scanning pattern of a 16
x 7 image area as well as the time sequence of signals used to validate the matching coordinate
measurement area. Thin diagonal lines indicate the measurement area (the area of the input image in
which measurements are valid), and thick diagonal lines indicate the image area being scanned (the
area stored in the internal shift register). The IP90C08 accepts simultaneous external feed of seven
pixels of data (one column of seven rows), and stores this data in an internal shift register as an 'image
area.' The IP90C08 then compares this 16-column x 7-row x 8-bit image data in the shift register with a
previous set of template data, and performs differential, absolute value, and sum-of-difference
calcula tions.
Remember the following points when referring to these examples:
•

The IP90C08 constantly accepts input data and makes sum-of-differences calculations.

•

ACT' is set low to control matching coordinate measurement.

•

The relationship between ACT' and matching coordinate measurement is as follows. When ACT'
low is detected, matching coordinate measurement is performed on the image area stored in the
internal shift register. Thus, the valid data for this measurement includes not only the 7-row data
input at the time ACT' low is detected, but also the previous 15 columns of 7-row data that was
input to the internal shift register before ACT' low was detected. The single column input when
ACT' low is detected is then added to the previous 15 columns of data, and matching coordinate
measurement is performed on all 16 columns.

Sequence A

IA: 0-1,1-1). This image area does not fall within rows in which matching coordinate measurement can
be applied.
One portion of the image area (the top row and left-hand column of the image area, shown in heavy
diagonal lines) is located outside the measurement area, so ACT' (the solid horizontal lines) remains
high. ACT' corresponding to the position of the black dot 0-1,1-1), is high.

m

C-ll

at
I

SequenceB

IA: 0,1-1). This image area does not fall within rows in which matching coordinate measurement can be
applied.
One portion of the image area (the top row of the image area, shown in heavy diagonal lines) is
located outside the measurement area, so ACT* remains high.
iCLK

HS'
IA

__•

IlfUUUUUUUUUUUU

-U

m:::xx:xx::xxxx

i~_.j

IE

ID

C
18
IA

_L.J

_'_.J _,_

--'_I
I

1_1- _,_ 1- _I_.L _1_"-_1
I,

.l_L.L _1_ "-_1_"--"
I

I

I

I

,

I

I

I

-~------------------------~~-

SequenceC

IA: 0-1,1). The image area falls within rows covered by the measurement area.
The image area is scanned within the rows in which matching coordinate measurement is feasible, but
is still not entirely within it. One portion (the left edge of the image area, shown in heavy diagonal
lines) still lies outside the measurement area, so ACT* remains high.
iCLK

n.nn.nn.nnJ1MMI

HS'-U
IA

X::X::X:X:X:X::j

C-12

SequenceD

IA: (j,1). The image area falls completely within the matching coordinate measurement area.
The entire image area is within the measurement area, and ACT* is asserted low. The image area
(shown in heavy diagonal lines) having this pixel in its lower right comer is stored in the internal
shift register, and the result of a sum-of-differences calculation for this area is used for matching
coordinate measurement. The matching coordinate measurement circuit takes the sum-of-differences
value from this first measurement as the best available match (the lowest sum-of-differences), and
enters the sum-of-differences value and the coordinates (j,1) in the register MINPOS(O).

IG._ _

iCLKI1flf1.fl1lI11l

HS'-U
IA

x::x:x:r:x:x:II

~

':~~~

18
IA

SequenceE

IA: (k,1). The image area is at the right edge of the matching coordinate measurement area.
Here, the image area is moved to the right edge of the area of the frame, but is still entirely within
the measurement area. Therefore, ACT* is asserted low.

C-13

SequenceF

IA: (k+I,I). The image area extends beyond the matching coordinate measurement area.
The image area extends beyond the right edge of the area of the frame and outside the measurement
area. ACT* is therefore de-asserted and remains high.
iCLK

HS' IUr~-------------------------------------------IA~

11_ _
k

j

19IED
C

IB

IA

m

SequenceG

IA: G-I,m). The image area falls within the last rows of the matching coordinate measurement area.
The image area has moved to the lowest row of the matching coordinate measurement area. Because
measurements can still be made in this row, the position is valid for vertical measurement; however,
since not all of the image area fits horizontally within the measurement area, ACT* is de-asserted and
remains high.
iCLK

flllJ1J1J1JUlfU

HS·I.J
IA

rx::x:rx:rx::o:.

J

y; /Y'/;
'/'

IE
D

C

IB
IA

C-I4

'/ y:/,

~

'7":, ,(1"'"""
y:/,

Y'-/-Y~-/c

t+

' ' / : / ' / r--:-'

SequenceR
IA: O,m). The image area falls within the last rows of the matching coordinate measurement area.
The image area is scanned within the lowest rows in which matching coordinate measurement is
feasible. In this position, the entire image area falls within the measurement area, so ACT* is asserted
low.
iCLK

IlI1/UUlJUUU1Jl

HS'LJ
IA~

j

-

}f,

"7':

-

'/y0:;'(;(y~;

'y'7:';f/;/;/r;4-1
--

"

Sequence I

IA: (k,m). The image area is located at the last pixel of the matching coordinate processing area.
Here, the image area has moved to the last pixel at the lower right corner of the measurement area.
This area is still measurable, so ACT* is asserted low.
iCLK

HS'LJr~~~~~~~~~~~~~~~~~~~~~

IAX:XX::XX::XX:XX

j

C-lS

k

SequenceJ

IA: (k+l,m). The image area attempts to measure the entire matching coordinate measurement area.
The image area is positioned after the last pixel in the lower right corner of the measurement area.
This requires scanning areas not previously measured, so ACT* is de-asserted and remains high.
iCLK

-U----------------------------

HS'
IA~
j
k

_' I

IG

I~

8

SequenceK

IA: G-l,m+l). The image area is located on the row following the last row of the matching coordinate
measurement area.
The image area is positioned on the row following the last row of the measurement area. This requires
data input from a line not previously measured, and therefore ACT* is de-asserted and remains high.
iCLK
HS'
IA

IUUI..Jlf1.J1fL
I..J

x::x::x:x::xx:: j

C-16

SequenceL

IA: O,m+l). The image area is located on the row following the last row of the matching coordinate
measurement area.
The image area is positioned on the row following the last row of the measurement area. The data
simultaneously input through pins IB-IG still falls within the measurement area, but the entire image
area involves areas not previously measured, so ACT' is de-asserted and remains high.
iCLK f1lUl.flIlMIl.J
HS' LJ
IA lCXXXXD

x:x:x:x:xx:x:x:
j

k

m

SequenceM

IA: (k,m+l). The image area is located on the row following the last row of the matching coordinate
measurement area.
The image area is positioned on the row following the last row of the measurement area. The data
simultaneously input through pins IB-IG still falls within the measurement area, but the entire image
area involves areas not previously measured, so ACT' is de-asserted and remains high.
iCLK

HS'-U-''=:'=::':';::'::';::''='':::'=''::''::'''::''=''::=''::'::'':'=''::'::'':=-====::':';::''::':::''='':::':''::'':
IAa:x:x::n.~

j

k

.. 1

IE
ID

IC

18

IA

__ -<;&.L
1_+--<

%

££

l'1""

>- __ 1-+_1_,..-<_>- .... _1_

'~. ~}.lltlll~l(l(Nl ;:1
I

C-17

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

m

SequenceN

IA: (k+l, m+l). The image area is located on the row following the last row of the matching coordinate
measurement area.
The image area is positioned on the row following the last row of the measurement area. The data
simultaneously input through pins IB-IG still falls within the measurement area, but the entire image
area involves areas not previously measured, so ACT* is de-asserted and remains high.
iCLK

HS' --U
IAX::XXX:X::XX::X
j
k

c,r: ,- ,.Y~;{;rY~;;'77:""
)'y~/y'

'V),

"7/77'/,

V. Y' y y / ' / /

*

I

7'i

IG
IF
IE

m

C-18

2.3

Operating Setup Procedures
2.3.1 One-Time Setup

o.

Power ON.
J,

1.

Hardware reset.
Set RST* pin input low, then return to high and remain high.
J,

2. Set operating mode (note 1).
J,
3. Set template registers.
• Template area enable register (xTMPEN) settings
• Template data register (xTMP) settings
J,
4. Clear matching coordinate register (note 2).
J,
5. Write 1 to execute register execute flag, start execution of matching coordinate measurement.
Load base coordinate into V coordinate counter Vcnt from VS*, and load base coordinate into H
coordinate counter Hcnt from HS*.
J,
6. Input image data (while ACT* is low).
Process image data input for template matching while ACT* is low.
-J,
7. Verify the end of the first image data input.
After the image is inputted, verify the internal processing delay cycle (or verify that BUSY* is
high, indicating the end of processing).
-J,
8. Write 0 to the execute register execute flag, and end execution of coordinate matching.
-J,
9. Read the match coordinate register.
-J,
10. End or repeat.
To repeat processing, repeat from step 2 (or 3 if the mode is unchanged). If template data is
unchanged, repeat from step 4.
-> To step (2), (3) or (4)
Note 1:

Operating mode settings:

• Soft reset from reset register

• Template selection register

• I/O control register

• Output compensation bias
register
• Output compensation shift register. Horizontal base coordinate register • Vertical base coordinate register
• Shifter connection register

Note 2:

• Sum-of-differences delay register

The matching coordinate clear register clears the matching coordinate register. (To the "cla"
or "clb" flag, write 1 after clear, write 0 to cancel clear.) The previous match coordinates
remain in memory until the clear procedure is executed, so results can be read any time.
Always clear the register before making new measurements.

C-19

2.3.2 Setup for Continuous Processing with New Templates at Each Measurement
o. Power ON.
,/,
1.

Hardware reset.
Set RST* pin input low, then return to high and remain high.
,/,

2.

Set operating mode (note 1).
,/,

3. Set up template register set A.
•

Template area enable register set A (ATMPEN) settings

•
,/,

Template data register set A (ATMP) settings

4.

Clear matching coordinate register set A.
The matching coordinate clear register clears the matching coordinate register.
To the "cla" flag, write 1 after clear, write a to cancel clear.
,/,

5.

Execute.

6.

7.

8.

9.

10.

11.
12.

• Write 1 to execute register to start execution
,/,
Input the first image data, run template matching processing.
Process template register set A, only while ACT* is low.
,/,
Set up template register set B during template matching processing with template register set A
(note 2).
• Template area enable register set B (BTMPEN) settings
• Template data register set B (A TMP) settings
,/,
Verify the end of the first image data input.
After the image is inputted, verify the internal processing delay cycle (or verify that BUSY' is
high, indicating that processing has ended).
,/,
Switch template register sets.
Using the template selection register or the TMPSEL pin, switch the template register set used for
processing from set A to set B.
,/,
Input the second image data, and run template matching processing (set B).
Process template register set B, only while ACT* is low.
,/,
Read matching coordinate register set A during processing with template register set B.
,/,
Clear matching coordinate register set A.
• The matching coordinate clear register clears the matching coordinate register.
To the "cia" flag, write 1 after clear; to the "cla" flag, write a to cancel clear.

C-20

13. Set up template register set A
Set up template register set A, during template matching processing with template register set B.
• Template area enable register set A (ATMPEN) settings
Template data register set A (ATMP) settings

t
14. Verify the end of the second image data input.
After the image is inputted, verify the internal processing delay cycle (or verify that the BUSY*
pin signal is high, indicating that processing has ended).

t
15. Switch template register sets.
Using the template selection register or the TMPSEL pin, switch the template register set used for
processing from set B to set A.

t
16. To repeat, continue from step 17.
~ To end, go to step 24.
t To continue processing, go to step 17.
17. Input the third image, and run template matching processing.
Process template register set A, only while ACT* is low.

t
18. Read matching coordinate register set B (BMATCH) during template matching processing with
template register set A.

t
19. Clear matching coordinate register set B.
• The matching coordinate clear register clears the matching coordinate register.
To the "clb" flag, write 1 after clear, write a to cancel clear

t
20. Set up template register set B during template matching processing with template register set A.
• Template area enable register set B (BTMPEN) settings
• Template data register set B (BTMP) settings

t
21. Verify the end of the third image data input.
After the image is inputted, verify the internal processing delay cycle (or verify that BUSY* is
high, indicating the end of processing).

t
22. Switch template register sets.
Using the template selection register or the TMPSEL pin, switch the template register set used for
processing from set A to set B.

t
23. To repeat, return to step 10. To end, go to step 24.
~ To repeat, go to step 10.
t To end, go to step 24.
24. End processing.
• Write a to the execute register to end processing.

t

C-21

25. Read matching coordinate register set A.
.j,
26. End Processing.
For power-saving mode, write 1 to the appropriate flags in the I/O registers.
Note 1

Operating mode settings:

• Soft reset from reset register

• Template selection register

• Shifter connection register

• Sum-of-differences delay register

• Output compensation shift
register
Note 2

• I/O control register

• Output compensation bias
register
• Horizontal base coordinate register. Vertical base coordinate
register

Switching between template register sets A and B.
The IP90C08 provides two built-in template register sets (the registers on which template
matching is based). Template matching can proceed while switching between these two
register sets as needed. For further information on the registers, see Section 5, "Registers."
Register sets A and B function equivalently, and provide an efficient way to frequently switch
template data during template matching, as illustrated in the above procedure.
Register sets A and B can be accessed independently, and so offer independent address
mapping for reading and writing. Similarly, the matching coordinate registers AMATCHOAMATCH3 and BMATCHO-BMATCH3 have different addresses, and can be accessed
independently.
Switching between template registers sets is done through the contents of the template
selection register (TMPSEL) and the TMPSEL pin. For information on the template selection
register, see Section 5.12, "Template Select Register."

C-22

2.4

Sample Expanded System Configurations
This section gives an example of using multiple IP90C08 chips for processing expanded image areas.
Note:

The operation and functions of these sample systems are not warranted for actual use.

2.4.1 Template Matching and Match Filter Processing of a 16 x 7-Pixel Template
raster
scan
input

IA
19
IC
ID
IE
IF
IG

15 bit

00

matched
filter
output

IOCTRL
se=O
od=1
eid=O

2.4.2 Template Matching and Match Filter Processing of an Expanded 16 x 14-Pixel
Template
tern la#1
raster
8 bit
scan -~I-;;;:;::;;::;;:;::::;-~ IA
19
input
1H line dela
1H line del a
1H line dela
1H line dela
1H line del a
1H line dela

IC
ID
IE
IF
IG

expanded matched
filter input

16bit

00

OLY=2
IOCTRL
se=1
ad=1

tern la#2
1H line dela
1H line dela
lH line del a
1H line del a
1H line dela
1H line dela

IA
19
IC
ID
IE
IF
IG

matched
filter
output

matched
filter
output

OLY=O
IOCTRL
se=O
od=1
eid=O

Matching coordinates are stored in the register of the templa#l chip. In this example, the matching
coordinate register of the templa#2 chip is ignored.
In the templa#2 chip, the output compensation circuit enable flag (se) in the I/O control register
(IOCTRL) is set to O. This reduces the output delay for sum-of-differences calculations in the templa#2
chip, and transfers the partial sum-of-differences value for its seven lines (16 x 7 pixels) to the
templa#l chip. In the templa#l chip, this partial sum-of-differences value received from the
templa#2 chip is added to the partial sum-of-differences value calculated by the templa#l chip. The
result is a total sum-of-differences value that is the result of template matching for the 16 x 14-pixel
image area, and shows how closely the image matches the template.

The connection between the two IP90C08s delays the transfer of the partial sum-of-differences
calculation from the templa#2 IP90C08 by two clock cycles, so the system must include a way to absorb
this phase differential. This can be done by entering 2 in the sum-of-products delay register (DLY) to
compensate for the delay in input from the expansion unit.

C-23

2.4.3 Template Matching and Match Filter Processing of an Expanded 16 x 21-Pixel
Template
raster
scan
input

8 bit

tern la#1
IA
IB

OD

IC

17 bit

10
IE
IF
IG

matched
filter
output

DLY=4

expanded matched
filter input

tern la#2

IOCTRL
se=1
od=1
eid=1

matched
filter
output

IA
IB

IC

16 bit

ID
IE

16x?

IF

template

DLY=2

IOCTRL

5e=1

IG

od=1
eid=1

la#3

matched
filter
output

IA
IB

IC
ID
IE
IF

IG

15 bit
DLY=O IOCTRL
5e=0
od=1
eid=O

Matching coordinates are stored in the register of the templa#l chip. In this example, the matching
coordinate registers of the templa#2 and templa#3 chips are ignored.
The output compensation circuit enable flag (se) in the templa#3 chip's I/O control register (IOCTRL) is
set to 0, reducing the output delay for sum-of-differences calculations in that chip, and transferring the
partial sum-of-differences value for its seven lines (16 x 7 pixels) to the templa#2 chip. In the templa#2
chip, this partial sum-of-differences value is then added to the partial sum-of-differences value
calculated by the templa#2 chip. This gives the result of template matching for a 16 x 14-pixel image
area, which is then transferred to the templa#l chip and added to the partial sum-of-differences
value calculated by the templa#l chip. The final value is the result of template matching for the 16 x
21-pixel image area, and indicates how closely the image matches the template.
The delay caused by using a cascade connection of multiple IP90C08s can be reduced by using the sum-ofproducts delay register (DL Y). In the example above, the templa#3 chip's DLY would be set to 0, the
templa#2 chip's DLY to 2, and the templa#l chip's DLY to 4. This absorbs the phase differential
between the respective sum-of-products calculations. Phase delay can also be reduced on the input side
by using line memory or FIFO settings to change the length of the input line delay.

C-24

2.4.4 Template Matching and Match Filter Processing of an Expanded 32 x 21-Pixel
Template
Matching coordinates are stored in the templa#OO chip.

ras er scan mpu

t emDla
I #00

\.

8 bit L 1H line delay -

-

1H line delay
1H Ine e ay
1H line delay
1H line delay r-1H line delay I - -

IA
IB
IC

~ coordinates
Match __~ OD

- :~ I
IF
IG

templa#10

I
I
I
I

-

16 pixel
delay
7pcs

r-

IAto IG

OD

J

16x7
template

I

\

15 bit

EXin

L-

I
I

-

32 x 21 matched filter output

\

--

16x7
template

expanded matched
filter input

I
I

..

18 bit

templa#11

templa#01
1H line
delay
7pcs

IAto IG

I

OD

16x7
template

I

templa#02
1H line
delay
7pcs

IAto IG

I

--

Pr15 bit
15 bit

--

OD ~

16x7
template

I

16 pixel
delay
7pcs

-

IAto IG

I

OD ~

16x7
template

I

15 bit

templa#12
15 bit
16 pixel
,.- IAto IG
OD ~
delay
7pcs
16x7
template

I

I

,--r--

L

CL--Note:

~

18 bit

Image areas can be expanded horizontally by connecting the delay shift registers to the
input pins (IA-IG) as shown above. However, the sum-of-differences output pins (OD) can
also be connected to adjust for phase differential. The best method to use depends on the
particular devices and applications.

C-2S

2.4.5

Template Matching and Matching Filter Processing of an Expanded 48 x21 Pixel
Template

Matching coordinates are stored in the templa#OO chip.
raster scan input

tem la#OO
18 bit

IA
IS

8 bit
1H line
dela

IC
ID
IE
IF

48

X

21 matched filter output

OD~~----------------------~

IG
expanded matched
filter input

C-26

Section 3. Internal Configuration
3.1

Internal Block Diagram
The following block diagram shows the configuration of the IP90C08.

Image data
raster scan
input

Output value
compensation
circuit

7xl6local area shift
register array

8-bit
7 input

circuit

difference circuit

circuit
(degree of
match)

,c:=±====;--'B

TMPSEL
CPU Bus

se flag

A

7xl6 template
register sets

,

Matching coordinate
register sets

Sum-ofdifferences
(matched
filter output)

----,---+--Top 4 matched
. H, V coordinates

,

,

----,---1"--ISbit ' 16bit ' 16bit

Coordinate Counter
VS* ----.
VSEN* ----.
HS*
ACT*

Hent l6bit

Vent l6bit

iCLK-.

Base Coordinate Register

Note:

This block diagram does not show all functions of the IP90C08. For information on particular
functions or other aspects of the IP90C08, see the appropriate sections of this manual.
C-27

3.2

Shift Registers and Template Data Registers
The illustration below shows the relationship between the shift register array, which holds the
incoming image area data, and the template data registers.

IA_,--_~

r...--- ......... .

.-------------_ ........... - - - - - - - - - - - - - - '
Shift register

r...--- ......... .

IB

. - - - - - - - - - - - - - -.......... ---------------1
Shift register

.....- - _ ......... .

IF

.--------------_ .......... - - - - - - - - - - - - - - '
~hift register

1-111---- ......... .

IG

Note:

This block diagram does not show all functions of the IP90COS. For information on particular
functions or other aspects of the IP90COS, see the appropriate sections of this manual.

C-2S

Section 4. Pins and Functions
4.1

Pin Lists and Functional Descriptions
I/O

1
1

I
I
I

Pixel clock
Horizontal sync signal input
Vertical sync signal input

VSEN*

1

I

Vertical sync enable signal

Starts every field
Enables VS* input

ACT*

1

Active area signal

L signal for processing

IA<7 .. 0>

8

I
I

8-bit input A, nth line

IB<7 .. 0>

8

I

Input B, n+ 1 line

IC<7 .. 0>

8

I

Input C, n+2 line

Simultaneous input of

ID<7 .. 0>
IE<7 .. 0>

8
8

Input 0, n+3 line
Input E, n+4 line
Input F, n+5 line

7 pixels of data, as one
column of 7 rows.

Pin symbol

1

Image sync signals

iCLK
HS*
VS*

Image data input

Expanded sum-ofdifference input

Sum-oE-differences
(matched filter)
output

Template register
select

Function

IF<7 .. 0>

8

I
I
I

IG<7 .. 0>
EXin<17 .. 0>

8
18

I
I

Input G, n+6 line
Expanded sum-of-differences
input

00<17 .. 0>

18

0

Sum-of-differences (matched
filter) output

ODEN'

1

I

00 output enable

Starts every row

Expanded sum-of-differences
input for template matching of
up to 1024 total pixels. (note 1)
Sum-of-differences (matched
filter) output based on sum-afdifferences i"put
Enables 00<17.0> output:
If ODEN*=H:
OD<17 .. 0> is High-A (note 2)
If ODEN*=L:
-OD<17 .. 0> is drive (enable)
TMPSEL=L: (set A)
TMPSEL=H: (set B) (note 3)

--

TMPSEL

1

I

RD*

1

WR*

1

I
I

CS*

1
9

AO<8 .. 0>
DB<15 .. 0>
CPU bus

Description/ Remarks

No.

Signal group

I

Selects template register set for
processing
Read signal
Write signal
IP90C08 select
Address bus

(note 11)

BUS8

16
1

I
I/O
I

RST*

1

I

Reset

Requires at least 4 clock cycles.
Schmitt trigger input with pull-

BUSY*

1

0

Output busy signal

Operates with ACT* control,
indicates internal processing in
progress.

TESTO,I,2,3
TEST4*,5*

4

0
I

Test signal
Test Signal

Test pin. Normally High-Z.

2

Vdd

12

PW

GND

12

PW

Data bus
8-bit bus width

BUS8=H: (DB<15 .. 8> disable)
(note 10)
BUS8=L:(DB<15 .. 8>enable)

up resistance.

Test
(note 4)
Power supply, GND
(note 5)
Total pins

5V
Ground

160

C-29

Test pin. Schmitt trigger input
with pull-up resistance.
Normally always high

Note 1:
Note 2:

In LSI internal test mode, TEST4*=L may put the IP90C08 in output mode.
When the template select register bit 1 (pr flag) is 0, this pin is enabled. When the pr
flag is 1, selection of a template register during execution depends on the value of the
template select register bit 0 (ab flag).
Note 3: The LSI test pins (TESTO, TEST!, TEST2, TEST3, TEST4*,and TESTS*) are only for LSI
testing before shipment. In normal use, the input should be high and output should be
open.
Note 4: To reduce noise, all power supply pins should be connected while the IP90C08 is in use.
Note S: Pins with pull-up resistance are connected to Vdd through internal high-resistance
transistors. Pay careful attention to their electrical characteristics.
Note 6: The RST*, TEST4*, and TESTS* pins have Schmitt trigger input with pull-up resistance.
Note 7: An asterisk (*) following a pin symbol indicates inverse logic.
Note 8: The package is 160-pin QFP (molded body 28-mm square, with 0.6S-mm pin pitch).
Note 9: Unused input pins should be constantly set high or low.
Note 10: When BUS8=High to select 8-bit access mode, the upper 8 bits of the data bus (DB, as
well as data input from image data input pins IA-IG, and expanded sum-of-differences data input
EXin<17.. 0> ).
After reset, all values in this register are set to

~Oh.

IOCTRL
The diagram below illustrates the input/ output control register.
MSB

se:

od:

id:

LSB

W7

W6

W5

W4

W3

W2

WI

WO

o

0

0

0

eid

id

od

se

the output compensation circuit enable flag. This determines whether sum-of-differences output
is sent directly from the sum-of-differences circuit or through the output compensation circuits
(see Section 3.1, "Internal Block Diagram").
se=!:

enable output compensation circuits (enables expanded input, delay register, and
output barrel shifter)

se=O:

disable output compensation circuits

the sum-of-differences output enable flag.
od=l:

output sum-of-differences output

od=O:

sum-of-differences output pin OD<17..0> signal set high

the input image data reset flag.
id=l:

set image input data signal to 0, regardless of pins IA-IG (note 1)

id=O:

process image input data from pins IA-IG

eid: the expanded input image data reset flag.
eid=l: process expanded sum-of-differences input data from expanded sum-of-differences
input pins EXin<17.. 0> (Note 1)
eid=O: set expanded sum-of-differences input data signal to 0, regardless of expanded sumof-differences input pins EXin<17..0>
Note 1:

This option represents a power-saving mode, reducing chip power consumption.

The register address is either OFAh or IFAh. Values are mapped for either address.

C-46

5.12 Template Select Register
The template select register selects one of the template register sets (A or B) to be enabled for
template matching processing.
When a template register is accessed directly from the CPU bus, it is mapped with a difference
address, so that reading and writing are both enabled regardless of the settings in the template select
register.
After reset, all values in this register are set to OOh.

TMPSEL
The diagram below illustrates the template select register.
MSB

ab:

pr:

LSB

~7

~6

~5

~4

~3

~2

~1

~O

o

0

0

0

0

0

pr

ab

This flag selects a template register set for template matching. This flag is enabled when pr=l.
(When pr-O, the TMPSEL pin is enabled.)
ab=O:

enables template register set A

ab=1:

enables template register set B

This flag determines the method of selecting the template register set for processing.
pr=O:

template register set is selected by the TMPSEL pin

pr=1:

template register set is selected by ab

The register address is either OFCh or IFCh. Values are mapped for either address.

C-47

5.1 3 Execute register
The execute register controls the execution of matching coordinate measurements in the template
matching process. The register creates a logical product with ACT*. Although this register controls
matching coordinate measurement, sum-of-differences calculation is performed constantly. To conserve
power, use the input data rest flag id in the I/O control register (IOCTRL) to reset input data and
enter power-saving mode.
When 1 is written to the execute flag (ex), ex enables the internal chip functions, which then become
effective immediately after the input of the first valid VS* following a VSEN*. This initiates
matching coordinate measurement.
In actual use, 1 is written to ex by a software procedure, after which VS* is latched low upon the rise
of the clock signal, and an image field is thereby opened (by loading the vertical coordinate base
register value as the initial value for the vertical coordinate counter Vent). Matching coordinate
measurement is then performed on an area of the raster scan input, defined as an image area by the
pixels that are input during the low phase of ACT* and that determine the lower right comer of the
image area.
If 0 is written to ex, ex takes effect internally within two clock cycles, and matching coordinate

measurement processing is terminated.
The field control flag (fl) is effective for the duration of one field only, specifically from the opening
of a field by VS* until the next VS*, and executes matching coordinate measurement for that frame
only. If fl is set to 1 when 1 is written to ex, matching coordinate measurement begins normally with
the next VS*, but ex is cleared when the second VS* arrives. This feature enables a single field to be
measured without needing an external means of holding ACT* high.
After reset, all values in this register are set to OOh.

EXEC
The diagram below illustrates the execute register.
MSB

ex:

fl:

LSB

~7

~6

~5

~4

~3

~2

~l

~O

o

0

0

0

0

0

fl

ex

the start-execution flag.
ex=l:

start template matching

ex=O:

stop template matching

the field-control flag.
£1= l:

enable field control circuit

£1=0:

disable field control circuit

The register address is either OFEh or lFEh. Values are mapped for either address.

C-48

5.14 LSI Internal Test Register
This register is used for testing before shipment, and is not for other use. 0 should be written to all bits
in the register, or the IP90C08 should be reset and used with all bits reading OOh. If any bit contains 1,
the chip goes into shipment test mode, and normal operation cannot be assured.
The register address is lAOh-lEBh.

C-49

Section 6. External Dimensions
6.1

Dimensions (160-Pin QFP)
0.20X45"
TYP(3 PLCS)

I
I

I
I

~

~
1;<".

VENT PLUG

-------4[-~~-

~

~~

I
I
I

I
I
I

=:::.:::--f-.~/'m1TTT1T1TTT1TmrrnTITITT1TTT1TnnnilmrrnTITITTmm1TTT1TmrrnTITITTrr-f=t--- G

--,-_8-,=16,,--0

0.89
x45°
27.64±0.08

31.2±0.20
M

t~~:
1

' 0.58----,
Iy----

JL
0.8±O.l3

C-50

Section 7. Electrical Characteristics
7.1

Absolute Maximum Ratings
Item

Symbol

Power supply voltage

Vdd

-0.3 to 6.5

V

Vi

-0.3 to Vdd+0.3

V

Input current

Ii

±10

rnA

10

10

rnA

Operating temperature

Topt

Ot070

°C

Storage temperature

Tstg

-10 to SO

°C

Recommended Operating Conditions (GND=OV, Ta=O° to 70°C)
Item

Symbol

Power supply voltage

Vdd

High-level input voltage

Conditions

Vih

TTL level

Low-level input voltage

Vii

normal input

High-level input voltage

Vih

SCHMITT

Low-level input voltage

Vii

Input rise time
Input fall time
Input rise time
Input fall time
Note 1:

7.3

Unit

Input voltage

Output current

7.2

Rating

Min

Typ

Max

Unit

4.75

5.0

5.25

V

Vdd

V

2.0
0

O.S

V

2.25

Vdd

V

input (note 1)

0

O.S

V

Tri

TTL level

0

100

ns

Tfi

normal input

0

100

ns

Trisch

SCHMITT

0

1000

ns

Tfisch

input (note 1)

0

1000

ns

Max

Unit

The three Schmitt trigger input pins are RST*, TEST4*, and TEST5*.

Input/Output Pin Capacity (Vdd=Vi=OV)
Item

Symbol

Conditions

Min

Typ

Input pins

Cin

f=l MHz

10

pF

Output pins

Cout

f=l MHz

10

pF

I/O pins

Cin

f=l MHz

10

pF

C-51

7.4

DC Characteristics (Vdd=5V±5%, GND=OV, Ta=O° to 70°C)
Item

Symbol

Conditions

Min

Typ

Max

Unit

200

IlA
rnA

Static current consumption
(note 1)

II

Vi=VDD or GND

Output short current (note 2)

los

VDD=Max,
Vo=VDD

15

50

130

VDD=Max, Vo=O

-5

-25

-100

(all output and I/O pins)
Low-level input leak current
Normal I/O pins

Iil

Vi=GND

-10

±l

10

IlA

Pins with pull-up
resistance (note 3)

lipl

Vi=GND

-35

-115

-350

IlA

High-level input leak current
(all input and I/O pins)

Iih

Vi=VDD

-10

±1

10

IlA

Low-level output voltage

Vol

101=4mA

0.2

0.4

V

High-level output voltage

Voh

10h=-0.5 rnA

4.5

VDD

V

(note 4)

Voh

101=-4 rnA

2.4

VDD

V

SCHMITT hysteresis voltage

Vsch

ViI to Vih

0.4

Note 1:

Excluding static current consumption to pull-up resistors.

Note 2:

Output short current for one second or less, at one LSI pin.

Note 3:

The three pins pull-up resistors are RST*, TEST4*, and TEST5*.

Note 4:

Output is CMOS level (TTL level).

C-52

0.8

V

7.5

AC Characteristics (Pin load capacitance 30pf)

a) Data Timing at Frame Start
I

tcph

I

I4---tcyc~ ~
,

I

t

I

tcpll

~

I

I

iCLK

-1"--'

Image data input

IxO to Ix7
(x: A to G)
I

,.tves

~!..

I

tveh

I

I

~I

,

I

I

oJ1-___ -1- _____________________________ _

VSEN* \1\.,.:_ _ _ _

*note 1

I
'

I

t vh

~tvs~
I I

I

~

VS*

i

I

I

v.. -*note 2 -- -- -- -- -- -- - -- -- -- - -- I

I

~ths~
\

HS*

: thh

V*note 2 _____________________ _

Note 1:

VS* is enabled when VSEN* of the previous clock cycle is low.

Note 2:

VS* and HS* need not be pulses, but can extend as shown by the dotted lines. However, a
high-level input signal is required at least two clock cycles before the next sync signal is
input.
Unit: ns
Symbol

Min

iCLK cycle period

Item

tcyc

33.0

iCLK high level period

tcph

13.0

iCLK low level period

tcpl

13.0

Image data IA-IG setup time

tis

8.0

Image data IA-IG hold time

tih

3.0

VSEN* signal setup time

tves

8.0

VSEN* signal hold time

tveh

3.0

VS* signal setup time

tvs

8.0

VS* signal hold time

tvh

3.0

HS* signal setup time

ths

8.0

HS* signal hold time

thh

3.0

C-53

Typ

Max

,

b) Image Data Input Control Timing
I~

\

iCLK

Unknown
Value

Image data

IxO to Ix7
(x: A to G)

,

~I

tcyc

\

1

1

I

' I

~tis~tih~

1

I
I

Valid Position

i teh

I..

ACT*

--------X

i'

tes----1•.:I....-

Data Enable

....+OI..l - - - - - - t e s - - -....+Oi..l----1~~!

tffi

~r-------------+'--~~

Ii

Data Disable

i

i\...--

1

1

;..-tbd~

L

BUSY*

Unit: ns
Item

Symbol

Min

tcyc

33.0

Image data IA-IG setup time

tis

8.0

Image data IA-IG hold time

tih

3.0

ACT' signal setup time

tes

8.0

ACT* signal hold time

teh

3.0

BUSY* delay time

tbd

2.0

iCLK cycle length

C-S4

Typ

Max

20.0

c) Expanded Sum-of-Differences Input Timing

iCLK
'-_..J 1
1
texs Ite~
I
rOil
~I"~

Expanded sum-ofdifferences input

EXinO to EXinl7
Unit: ns
Symbol

Item

Min

EXinO to EXin17 setup time

texs

8.0

EXinO to EXin17 hold time

texh

3.0

Max

Typ

HI
!

d) Matched Filter Output Control Timing
Matched Filter Output Enable

iCLK
'----I
1
1<111

Filter output

toed

1

:

~I

tad

I

1

--------+---(GD(m,n~

X-

toez

OD(m+l,n)

XOD(m~2,n)

ODO to OD17
1

ODEN*

~~

_________________

-J~
1

Unit: ns
Item

Symbol

Min

Typ

Max

Delay time from ODEN* signal fall to filter
output OD enable

toed

15.0

Delay time from ODEN* signal fall to filter
output OD disable

toez

15.0

Filter output OD delay time

tod

C-55

I

~

~I

2.0

20.0

),..:- - - -

e) CPU Interface Timing
Write Cycle

CS*

tcws

tcwh

~

J.-.:

i
! 1"---~\,--____
I
------,. !.-twrw-----.- r---------.,

--'""~

1

WR*

'

1

IJ

~

,r~1

,

I

7:

RD*

1

i

taws '

itawlj

~

ADO to ADS,BUSS

\

~

X,.-------,. '--_____
I· ...i .,X~---_...J ~_____
--U-nkn-o-w-n-"'~

U~

i

AD(m)
1

DBOtoDB15

,'--_. . . ,.

rtrwh

tdbs

:
I'

tdbh

1

DB(m)

Item

Symbol

Min

CS* signal setup time (from WR* fall)

tcws

3.0

CS* signal hold time (from WR* rise)

tcwh

3.0

RD* signal setup time (from WR* fall)

trws

3.0

RD* signal hold time (from WR* rise)

trwh

3.0

WR* low pulse width

twrw

20.0

ADO to AD8, BUS8 setup time (from WR*
fall)

taws

8.0

ADO to ADS, BUSS hold time (from WR* rise)

tawh

3.0

DBO to DB15 setup time (from WR* fall)

tdbs

15.0

DBO to DB15 hold time (from WR* fall)

tdbh

3.0

C-56

Typ

Max

Read Cycle
tcrs

CS*

f

twrs I

I twrh

-

\....._ - - -

~

~

i

- ___"" i----trdw ------.i r--'- - - - - " " ' \

\

,

ti

tars

~,,, ~:

AD(m)

I tdbd l
:~I

__--!---<<<<<

\

tarh

'..

-~Unkn~ow-n--+:"'X
,

DBOtoDB15

i

i

I

ADO to ADS,BUSS

Y

~

----~\ i

WR*

RD*

tcrh

~

i

~

Unknown

I

X

AD(n)

i tdbz,
~,
,"
DB(m)

:)>-_ _ _ _-<«(( DB(n)
Unit: ns

Item

Symbol

Min

CS* signal setup time (from RD* fall)

tcrs

3.0

CS* signal hold time (from RD* rise)

tcrh

3.0

WR* signal setup time (from RD* fall)

twrs

3.0

WR* signal hold time (from RD* rise)

twrh

3.0

Typ

Max

RD* low pulse width

trdw

20.0

ADO to ADS, BUSS setup time (from RD* fall)

tars

15.0

ADO to ADS, BUSS hold time (from RD* rise)

tarh

3.0

Delay time until DBO-DB15 disable (from
ADO to ADS verification)

tdbd

30.0

Delay time until DBO-DB15 disable (from
RD* rise)

tdbz

15.0

C-57

f) Reset Timing

iCLK
I
I

trsw--------------.,~:;

RST*
i

The minimum reset signal input period should be three clock cycles. An internal reset is executed when
a low RST* is detected on two consecutive clock rises. RST* rise is detected by clock rise, reset will be
released after three clocks.
Unit: clock cycles
Item

Symbol

Low pulse duration of RST*

trsw

Min

Typ

Max

3.0

g) Template Register Switching Control

iCLK

J

~1
..----tcyc-----i.~1

I..
TMPSEL -----'\l~

\,--_1

\'---~,

1

1

1

1

i
! tth
..
I----tts----I.*!..---.~!
i, tth Ii,------~I~\J.
.
B set select
i
~

tts---t.~i4--..toIl
..

A set select

1

'

:

I

I
Unit: ns

Item

Symbol

Min

tcyc

33.0

TMPSEL setup time

tts

8.0

TMPSEL hold time

tth

3.0

iCLK cycle

C-58

Typ

Max

Section 8. Sample Applications and Reference
Information
8.1

16 x 7 Averaging Filter Processing
As described in Section 1.2, "Algorithms," template matching operates on image areas of 16 x 7 pixels
by calculating the differences between the template and pixel data from the 16 x 7-pixel area, then
summing these differences. One application of this process is the most general type of spatial filter,
known as an averaging filter. This filter calculates the average value within the image area and
outputs that value as the median pixel value. This is used in noise reduction and similar applications.
The IP90C08 uses a template in which all data values are OOh, sets the template area enable register
(TMPEN) for any desired image area, and selects an output value range using the output shift register
and output compensation bias register.
For example, for averaging filter processing of a 7 x 7-pixel area, all pixels in the template register
set should remain at ~Oh, and template enable register values should all be EOOOh.
Because the maximum value will be the sum of differences of 7 x 7 = 49 pixels, or

a 5-bit shift is needed to express the output as an 8-bit value. The output shift register should
therefore be set to 5.
Note:

This example is intended only as a conceptual sketch of the use of the IP90C08, and requires
further refinement before it can actually be used.

Template Data in a 7 x 7-Pixel Averaging Filter

o

o

2

3

4

5

6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

2

0

0

0

0

0

0

0

3

0

0

0

0

0

0

0

4

0

0

0

0

0

0

0

5

0

0

0

0

0

0

0

6

0

0

0

0

0

0

0

ValId

7

8

9

10

11

12

Not valId

C-59

13

14

15

8.2

Sample System Configuration for Measurement of Movement Vectors in
a Grayscale Image Area
Note:

This example is intended only as a conceptual sketch of the use of the IP90C08, and requires
further refinement before it can actually be used.

8.2.1 Input Image Area
The total input image area is 512 x 256 pixels, of which movement vectors within an area of 128 x 84
pixels are to be identified in units of 16 x 7-pixel image areas.

512x256 pixels

I

128x84

I

8.2.2 Movement Vector Measurement Area
Movement vectors are to be measured in 8 x 14 =112 areas.

8x 16= 128 pixels
16x7

Template area
128x84 pixels

Scan area 160x98 pIxels

8.2.3 Range of Movement Vector Identification in Each Image Area

f. . . . . --.. ' . . r. . . . . . . . . . . -r--.. . . ----;
f.........................

r'mm]i

,

j

r-

,

•
m

"'116x7
•

I

j

,

.....................

,

~ ... ---............ ! ...... ----...... !.-......... --... -~

The scan area is 48 x 21 pixels.
Each 16 x 7 image area is taken as the center of a 48 x 21-pixel area, and scanned after movement has
taken place. The coordinates with the best closeness-of-fit on a pixel-to-pixel basis are identified,
and the distance of those coordinates from the base point is taken as the movement vector.

C-60

8.2.4 Image Data Scanned and Transferred Using 16 IP90C08 Chips
Input image data (image after movement).
Data transferred at one scan: 160 x 28 = 4480 pixels.
16 x (8+2) = 160 pixels

~,uu/u

////f// //////// /r////f/ //////// //////// //////// ///////J

n6x7
/
~

r/////'/

a

..... .,........

./

/ / / / / ' / / / / / / / / / . / / / / / / / / / / / / / / / / / / / / / / / / / ////Jil///

~

7x(2+2)=
28 pixels

,nnn/i

Template image (base image) 16 x 8 = 128 pixels

I
8.2.5

*

I

Ii~;xels

System Configuration for Processing of a Continuous Area
Raster scan
image input

8bit x 7lines

.. -.
•

Address

......-........
• ••

••• 1

A0I6*
A0I7*

...

•~ ...•......................•..........•••

Prg.RAM
Data RAM

C-61

8.2.6 Area Signal Generation in Each templa Chip
Because the row setting for template matching must be moved with every scan, and the column
coordinates for the start of the template matching area must be able to be changed as needed, an IMSC
or similar system with AOI function for programmable coordinate selection is advised. Because the
column setting for the area is fixed in terms of widths from the starting pOint, it is possible to make
this setting by decoding counter values.
1)

Example of Horizontal Area Selection and Vertical Starting Coordinate (Image Area
Coordinate) Selection

16 X (8 + 2) = 160 pixels
7x(2~2)=

28 pIxels

Area signal using A0I6* signal
Area signal using A0I7* signal

2) Column Area Designation
Using an 8-bit binary counter, select the column setting for the image area by decoding the counter
value.
3) Example of Active Area Signal (ACT*) Setting

When looking for movement in each of the image areas in 8 directions surrounding the shaded area,
assert ACT* low for the area enclosed in the heavy line.

C-62

8.3

Template Data Notation Format
The following charts show the format used for template notation. Refer to them when preparing
template data manually.

Address
Upper 5 bits Lower 4 bits
Ase!

00
01
~ 02
.",

'" 03
Cd
"is.
S 04
'"

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

000

001

002

003

004

005

006

007

OOB

009

OOA

OOB

OOC

OOD

OOE

OOF

010

011

012

013

014

015

016

017

01B

019

01A

01B

01C

OlD

OlE

01F

020

021

022

023

024

025

026

027

028

029

02A

02B

02C

02D

02E

02F

030

031

032

033

034

035

036

037

03B

039

03A

03B

03C

03D

03E

03F

040

041

042

043

044

045

046

047

048

049

04A

04B

04C

04D

04E

04F

050

051

052

053

054

055

056

057

058

059

05A

05B

05C

05D

05E

05F

060

061

062

063

064

065

066

067

06B

069

06A

06B

06C

06D

06E

06F

070

071

072

073

074

075

076

077

078

079

07A

07B

07C

07D

E-<

05
06
07

/
Valid

Address
Upper 5 bits Lower 4 bits
Sse!

10
11

'"
Cd
.",

12

'" 13
Cd
"is.
8 14

0

1

2

3

4

5

6

7

8

9

A

B

C

0

E

F

100

101

102

103

104

105

106

107

108

109

lOA

lOB

10C

10D

10E

10F

110

111

112

113

l14

115

116

117

118

119

11A

11B

11C

11D

l1E

11F

120

121

122

123

124

125

126

127

128

129

12A

12B

12C

12D

12E

12F

130

131

132

133

134

135

136

137

138

139

13A

13B

13C

13D

13E

13F

140

141

142

143

144

145

146

147

148

149

14A

14B

14C

14D

14E

14F

150

151

152

153

154

155

156

157

158

159

15A

15B

15C

15D

15E

15F

160

161

162

163

164

165

166

167

168

169

16A

16B

16C

16D

16E

16F

170

171

172

173

174

175

176

177

178

179

17A

17B

17C

17D

'"

E-<

15
16

/

17

Valid
When writing in 16-bit bus width, the lower values at the LSB end are placed in the lower addresses,
and the higher values at the MSB end are placed in the higher addresses.

C-63

SMIASSP
Image Processing LSI Series

IP90CIO
Labeling Accelerator (LABop)
Sumitomo Metal Industries, Ltd.
Technical Manual Ver. E 1.4

~
~
...

bOB
[;.S ::l
o

o]~

cntd~

!!:...J";:

•

Sumitomo Metal Industries, Ltd.

I

!

Table of Contents
Section 1:

Overview

1.1
1.2

Product Overview ..................................................................................................... 1
Features ................................................................................................................... 1

1.3

System Block Diagram ............................................................................................. 2

Section 2:
2.1
2.2
2.3

Section 3:
3.1
3.2

Section 4:

Pin Descriptions
Pin Configuration Diagram ....................................................................................... 3
Pin Descriptions ....................................................................................................... 4
Package Dimensions ................................................................................................. 5

Registers
Register List. ............................................................................................................ 6
Register Configuration .............................................................................................. 7

Functional Description

4.1
4.2
4.3

Description ............................................................................................................... 14
Device Operation ..................................................................................................... 14
Control Sequence ....................................................................................................... 16

4.4
4.5

Algorithm (Primary Labeling Processing) ................................................................. 19
Label Table Format .................................................................................................. 20

Section 5:

System Timing

5.1

CPU Interface ........................................................................................................... 21

5.2
5.3
5.4
5.5

Primary Labeling Processing ..................................................................................... 22
Linked Data Combination Processing ........................................................................ 23
Secondary Labeling Processing .................................................................................. 24
Status Output ........................................................................................................... 25

Section 6:
6.1
6.2
6.3
6.4
6.5

Section 7:

Electrical Characteristics
Absolute Maximum Ratings ...................................................................................... 26
Recommended Operating Conditions ......................................................................... 26
Input/Output Capacitance ........................................................................................ 26
DC Characteristics ................................................................................................... 27
AC Characteristics ................................................................................................... 28

Sample Application

7.1

Sample Labeling Result ............................................................................................ 35

7.2
7.3
7.4

Real-Time Parallel Processing .................................................................................. 36
Sample Application Using an Image-Processing Device ............................................ 36
Reference Circuits (Labeling Processing + Feature Extraction Processing) ................... 37

D-i

Section 1: Overview
1.1

Product Overview
The IP90ClO (LABop) is a single-chip, image-link component labeling processor that uses a
proprietary algorithm and high-speed circuit technology. It can process up to 4,094 temporary
labels using either a 4-connectedness or an 8-connectedness labeling operation. Labeling can be
processed in real time using three chips in parallel.

1.2

Features
•

Labeling processing functions
Labeling processing of non-interlaced raster-scanned binary input data
Maximum number of labels:
Maximum number of temporary labels: 4,094
Maximum number of label linkage information entries: 4,095
4-connectedness / 8-connectedness labeling
Wide range of image input. The IP90C10 processes up to 512 run labels in a horizontal line.
(This does not represent the maximum number of pixels in the horizontal direction. See
Section 4.4, "Algorithm," for details.)
Practical real-time labeling. Labeling can be processed in real time using three chips in
parallel.
Automatic labeling function without CPU assistance. The IP90ClO executes a series of
processes automatically:
1. Primary labeling
2. Linked data combination
3. Secondary labeling

•

External interface
Labeling information read out:
Number of temporary labels
Number of label linkage information entries
Number of final labels
Built-in timer counter for linked data combination processing
Status output to CPU:
Execution status for primary labeling, linked data combination, and secondary labeling
Interrupt generation for overflow (e.g., number of temporary labels) or time-out in each
stage of processing (interrupts can be masked as necessary)
General-purpose interface using 8-bit data bus

•

Maximum operation frequency: fmax = 40 MHz
Power supply: +5V single power supply
Input/ output: TTL-level compatible
Package: 120-pin QFP

•
•

D-1

1.3

System Block Diagram
Data

--~

HS* ----~
VS* --a-+-J_~

IMBC

~CLK

Line Delay

~HS*

IP90C51

CLK ___+-+-J~IO>I

* *

- ~ ~,
Q

1

1

1

i:l..

1

AD 4,
," DB 8/

CS*
WR*

IP90CIO

RD*

CPU

LABop

RST*

-

PLEXE*

---

LUEXE*

--

CLA 13

LBERR*
Label table
CLCE*
CLWR*

SLEXE*

Final label
output

LBD

Frame memory

I

I

I--

--

SRAM
8Kx24

Section 2: Pin Descriptions
2.1

Package Dimensions
3.35 ± 0.10
1 - - - - - - - - - - 32.00 ± 0.40 - - - - - - - - - - - - <.....1

1.60 ± 0.05

90"1....~------ 28.00 ± 0.10 ------~
61

I

91

60

o00

o

_J
--------------------------------r

31

o

N

o

+1

~

o

""

120 Pin QFP

D-3

units: mm

13'\

2.2

Pin Descriptions

Pin group

Symbol

Image data input

ID

HEN*
VEN*
HS*
VS*
PI
CLK
Label table interface
CLD23-CLDO
CLAI2-CLAO
CLCE*
CLWR
Frame memory interface FMD11-FMDO
FMOE*
FMWR*
FMVEN*
FMHEN*
Final label output
LBDll-LBDO
LBOE*
Status
LBERR*
PLEXE*
LUEXE*

CPU interface

Test
Power supply
Total pin count

SLEXE*
AD3-ADO
DB7-DBO
CS*
WR*
RD*
RST*
TSTENO
TSTEN1
Vdd
GND

No. of
Pins

Type

1
1
1
1
1
1
1
24
13
1
1
12
1
1
1
1
12
1
1
1
1

I
I
I
I
I
I
I
I/O
0
0
0
I/O
I
0
0
0
0
I

0
0
0
0
I
I/O
I

1
4
8
1
1
1
1
1
1
8
15

I
I

I
I
I
PW
PW

Description
Image data input
Horizontal input image enable signal
Vertical input enable signal
Horizontal synchronization signal
Vertical synchronization signal
I-line delayed image data input
Clock
Label table data bus
Label table address bus
Label table chip enable
Label table write enable
Temporary label data bus
Temporary label output enable
Frame memory write enable
Frame memory vertical enable signal
Frame memory horizontal enable signal
Final label data bus
Final label output enable
Labeling errors
Primary labeling execution frame status
Linked data combination processing
execution status
Secondary labeling execution frame status
Address bus
Data bus
Chip select
Write enable
Read enable
System reset (Note 1)
Test signal, normally low (Note 2)
Test signal, normally low (Note 2)
5V
Ground

120

Note 1:

RESET must stay low for at least three clock cycles. This pin is provided with a pull-up resistor.

Note 2:

The test pins TSTENO and TSTEN1 test the LSI's internal logic, and must normally be held low. Note that
these pins are provided with pull-down resistors.

Note 3:

An asterisk (*) after a pin name indicates negative logic.

D-4

2.3

Pin Configuration

+

SUMITOMO
METALS ©

IP90CIO

XXXXXXX Japan
XXXX

Pin No.
1
2
3
4
5
6
7
8
9
10

11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

Name Type
PW
GND
ADO
I
AD1
I
AD2
I
AD3
I
PW
GND
DBO
I/O
DB1
I/O
DB2
I/O
DB3
I/O
DB4
I/O
DB5
I/O
DB6
I/O
DB7
I/O
Vdd
PW
GND
PW
LBERR*
0
PLEXE*
0
LUEXE*
0
SLEXE*
0
LBDO
0
LBD1
0
GND
PW
LBD2
0
LBD3
0
LBD4
0
LBD5
0
LBD6
0
LBD7
0
Vdd
PW

Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

Name
LBOE*
GND
LBD8
LBD9
LBD10
LBD11
FMHEN*
FMVEN*
FMWR*
GND
FMDO
FMD1
FMD2
FMD3
GND
FMOE*
Vdd
FMD4
FMD5
FMD6
FMD7
FME8
FMD9
FMD10
FMDll
GND
CLDO
CLDl
CLD2
Vdd

Type
I
PW
0
0
0
0
0
0
0

Pin No.
61
62
63
64

65
66
67
68
69
70

PW
I/O
I/O
I/O
I/O
PW
I
PW
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PW
I/O
I/O
I/O
PW

71
72

73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

D-5

Name
GND
CLD3
CLD4
CLD5
CLD6
CLD7
CLD8
GND
CLD9
CLDlO
CLD11
CLDl2
CLDl3
CLDl4
GND
Vdd
CLDl5
CLDl6
CLD17
CLD18
CLDl9
GND
CLD20
CLD21
CLD22
CLD23
GND
CLCE*
CLWR*
Vdd

Type
PW
I/O
I/O
I/O
I/O
I/O
I/O
PW
I/O
I/O
I/O
I/O
I/O
I/O
PW
PW
I/O
I/O
I/O
I/O
I/O
PW
I/O
I/O
I/O
I/O
I/O
0
0

PW

Pin No.
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111

112
113
114
115
116
117
118
119
120

Name
CLAO
CLA1
CLA2
CLA3
CLA4
CLAS
GND
CLA6
CLA7
CLA8
CLA9
CLAlO
CLA11
CLA12
Vdd
CLK
GND
ID

PE
HEN*
VEN*
HS*
VS*
RD*
RST*
WR*
CS*
TSTENO
TSTEN1
Vdd

Type
0
0
0
0
0
0

PW
0
0
0
0
0
0
0

PW
I
PW
I
I
I
I
I
I
I
I
I
I
I
I
PW

Section 3: Registers
3.1

Register List
Address (hex)

Symbol

Read/Write

Description

0

CMD

Read/Write

Control command register

1

STAT

Read only

Execution status register

2

ERRM

Read/Write

Error interrupt mask register

3

ERRS

Read/Write

Error status register

Read/Write

Linked data combination processing timer-count
setup register

4

TIME

5

Low
High

6

Reserved

-

Reserved for system usei do not use

7

Reserved

-

Reserved for system usei do not use

8

TLBN

9

A

RLBN

F

Temporary label count register

Low

Read only

Final count register

Read only

Error line register

Read only

Linked data combination information count
register

High
ERLN

D
E

Read only

High

B
C

Low

Low
High

CMBN

Low
High

D-6

3.2

Register Configuration

Control Command Register CMD
Address Oh
Hardware reset:

Read/Write
OOh

°

Software reset:

except the RESET bit

This register provides the commands necessary to control the LABop.
7

6

5

4

3

2

1

4/8D

RESET

LEVEL

IRM

EXE4

EXE3

EXE2

°

EXE1

4/8D:
RESET:

Selects 4-connectedness (when set to 1) or 8-connectedness (when set to 0) processing.
Performs a reset. When set to 1, the LABop resets the entire register to 0, except the
RESET bit. To clear the reset, write to this bit. When setting the control command
register after a reset from the RESET bit, first clear the RESET bit to 0, then write
the desired value.

LEVEL:

Sets a frame-memory control signal. When set to 0, the LABop selects one clockpulsed output of the FMVEN* and FMHEN* signals, which indicate the framememory-enable period. When pulsed output is selected, the output signal is
accompanied by a single pulse immediately preceding and another immediately
following the enable period.
When set to 1, the LABop selects level output of FMVEN* and FMHEN*, which
holds output held low during the enable period.
(For details, see Section 5, "System Timing." Pulsed signal waveforms are indicated
by dotted lines.)
Disables interrupts. When set to 0, the LABop prevents LBERR* from going low
regardless of which type of error occurs.
Sets continuous execution of secondary labeling. When the EXE4 and EXE3 bits are
set to 1, and EXE2, EXE1, and the STAT register'S STAT2 bit are also 0, the LABop
starts secondary labeling when the next VS* signal is asserted. The LABop continues
executing secondary labeling until EXE4 is cleared to 0.
Sets the execution of secondary labeling. When set to 1, and EXE2, EXE1, and the
STAT register'S STAT2 bit are 0, the LABop starts secondary labeling when the next
VS* is asserted. EXE3 is reset to immediately after secondary labeling starts.
Sets the execution of linked data combination processing. When set to 1 while
primary labeling is not being executed, the LABop immediately starts linked data
combination processing. EXE2 is reset to immediately after linked data
combination processing starts.
Sets the execution primary labeling. When set to 1, the LABop starts primary
labeling when the next VS* is asserted. EXE1 is reset to immediately after
primary labeling starts.

IRM:
EXE4:

EXE3:

°

°

EXE2:

°

EXE1:

°

D-7

Execution Status Register STAT
Address 1h
Reset:

Read-only

XXXXXOOOh

This register reads the LABop status.

7

6

5

4

3

x

x

x

x

x

210
STAT3

STAT2

STATl

STAT3:

Indicates secondary labeling status. When set to 1, the frame is a secondary labeling
execution frame.

STAT2:

Indicates linked data combination processing status. When set to 1, the LABop is
executing linked data combination processing.
Indicates primary labeling execution status. When set to 1, the frame is a primary
labeling execution frame.
Reserved. (This bit is undefined when read by the CPU.)

STATl:

X:

D-8

Error Interrupt Mask Register ERRM
Address 2h
Reset:

Read/Write
OOh

°

This register masks interrupt requests caused by errors. Setting a bit to prevents the LBERR* pin
from going low even when an error occurs. Interrupts can also be disabled by setting the CMD
register'S IRM bit to 0. This prevents the LBERR* pin from going low regardless of what type of
error occurs.
7

6

5

4

3

2

1

°

IRLOFM ITMOVM ICMOFM31 CMOFM2 1 CMOFMl ITLOFM31 TLOFM21 TLOFMl I
RLOFM:

TMOVM:

CMOFM3:

CMOFM2:

CMOFMl:

TLOFM3:
TLOFM2:
TLOFMl:

Masks a run-label overflow error. The LABop memory stores up to 512 run labels per
line (see Section 4.4, "Algorithm"). If the RLOFM bit is set to 0, LBERR* cannot go
low even when the number of run labels per line exceeds 512.
Masks label linkage information processing overtime error. If set to 0, LBERR*
cannot go low even when the label linkage information process exceeds the preset
time (see the TIME register).
Masks a label linkage information overflow error 3. If set to 0, LBERR* cannot go
low even when the number of label linkage information entries exceeds 4,095
(register CMBN value = FFFh).
Masks label linkage information overflow error 2. If set to 0, LBERR* cannot go low
even when the number of label linkage information entries exceeds 1,023 (register
CMBN value = 3FFh).
Masks label linkage information overflow error 1. If set to 0, LBERR* cannot go low
even when the number of label linkage information entries exceeds 255 (register
CMBN value = OFFh).
Masks temporary label overflow error 3. If set to 0, LBERR* cannot go low even
when the number of temporary labels exceeds 4,094 (register TLBN value = FFFh).
Masks temporary labels overflow error 2. If set to 0, LBERR* cannot go low even
when the number of temporary labels exceeds 1,022 (register TLBN value = 3FFh).
Masks temporary labels overflow error 1. If set to 0, LBERR* cannot go low even
when the number of temporary labels exceeds 254 (register TLBN value = OFFh).

D-9

Error Status Register ERRS
Address 3h
Reset:

Read/Write
OOh

This register reads the status of errors occurring during labeling. If an error occurs during labeling
execution, the bit corresponding to the error is set to 1, and remains at 1 unless the CPU writes to
it. When a bit in the ERRS register and the CMD register'S IRM bit are set to 1, and the ERRM
register bit corresponding to that error is 1, LBERR* is pulled low, and the LABop stops processing.
(See Section 4.3, "Error Handling Sequence," for details.)

°

7

6

5

I RLOFS I TMOVS I CMOFS3
RLOFS:
TMOVS:

CMOFS3:
CMOFS2:
CMOFS1:
TLOFS3:
TLOFS2:
TLOFS1:

4

3

CMOFS2

CMOFSI

2

1

°

I TLOFS3 I TLOFS21 TLOFSI

Indicates run-label overflow status. Set to 1 when the number of run labels per line
exceeds 512.
Indicates label linkage information processing overtime status. Set to 1 when the
time required for linked data combination processing exceeds the preset time (see
the TIME register).
Indicates label linkage information overflow status 3. Set to 1 when the number of
label linkage information entries exceeds 4,095 (register CMBN value = FFFh).
Indicates label linkage information overflow status 2. Set to 1 when the number of
label linkage information entries exceeds 1,023 (register CMBN value = 3FFh).
Indicates label linkage information overflow status 1. Set to 1 when the number of
label linkage information entries exceeds 255 (register CMBN value = OFFh).
Indicates temporary labels overflow status 3. Set to 1 when the number of temporary
labels exceeds 4,094 (register TLBN value = FFFh).
Indicates temporary labels overflow status 2. Set to 1 when the number of temporary
labels exceeds 1,022 (register TLBN value = FFFh).
Indicates temporary labels overflow status 1. Set to 1 when the number of temporary
labels exceeds 254 (register TLBN value = FFFh).

D-10

Linked Data Combination Processing Timer-Count Setup Register TIME
Address 4h/Sh
Reset:

Read/Write
OOh

The time required for linked data combination processing is proportional to the number of
temporary labels or label linkage information entries involved. If the system processes labeling in
real time, and noise or a similar problem causes the number of temporary labels or label linkage
information entries to be excessively large, processing may need to be stopped. This register sets a
time limit (in clock cycles) after which label linkage information processing is stopped.
After label linkage information processing starts, the time-out counter begins counting clock cycles.
When the count exceeds the value set by the TIME register multiplied by 2S6, a time-out error is
assumed and the ERRS register's TMaVS bit is set to 1.
S

4

Sh I TIME1SI TIMEI4

TIME13

TIMEI2

4h I TIME7 I TIME6

TIMES

TIME4

7

TIMEO-IS:

6

3

2

I

I TIMEll I TIMEIO I TIME9
TIME3

TIME2

TIME I

o
TIME8
TIMEO

Sets the time to discontinue label linkage information processing.

Temporary Label Count Register TLBN
Read-only
XOOOh

Address 8h/9h
Reset:

This register reads the number of temporary labels. (The value in this register exceeds the
generated temporary labels by one.) This register resets each time the LABop starts primary
labeling, then counts the temporary labels.

9h
8h

6

S

4

x

x

x

x

TLBNS

TLBN4

I TLBN71 TLBN61

TLBNO-ll:
X:

7

3

2

I

0

I TLBNll I TLBNIO I TLBN9 I TLBN81

I TLBN3 I

TBN2

I TLBNI I TLBNO I

Indicates the number of temporary labels.
Reserved. (This bit is undefined when read by the CPU.)

D-ll

Final Label Count Register RLBN
Read-only
XOOOh

Address Ah/Bh
Reset:

This register reads the number of final labels. (The value in this register exceeds the generated
final labels by one.) This register resets each time the LABop starts primary labeling, then counts
the final labels.

Bh

7

6

5

4

X

X

X

X

Ah I RLBN71 RLBN61 RLBN5
RLBNO-ll:
X:

3

2

1

0

I RLBNll I R.LBNIO I RLBN91 RLBNSI

RLBN4 I RLBN31 RLBN2 I RLBNl I RLBNO I

Indicates the number of final labels.
Reserved. (This bit is undefined when read by the CPU.)

Error Line Register ERLN
Read-only
XOOOh

Address Ch/Dh
Reset:

This register reads the number of horizontal lines when an error occurs. This register resets each
time the LABop starts primary labeling, then counts the horizontal lines.

Dh

7

6

5

4

X

X

X

X

Ch I ERLN71 ERLN6
ERLNO-ll:
X:

3
I ERLNll

I

2

ERLNIO

I

1

0

ERLN91 ERLNSI

ERLN5 I ERLN41 ERNL3 I ERLN2 I ERLNI I ERLNO

Indicates the value of the vertical address at the time an error occurs.
Reserved. (This bit is undefined when read by the CPU.)

D-12

I

Linked Data Combination Count Register CMBN
Read-only
XOOOh

Address Eh/Fh
Reset:

This register reads the number of label linkage information entries. This register is reset each time
the LABop starts primary labeling, then counts the label linkage information entries.

Fh

7

6

5

x

x

x

Eh I CMBN7 1 CMBN61 CMBNSI
CMBNO-ll:
X:

4

3

2

1

0

I CMBNll I CMBN10 ICMBN91 CMBNSI
CMBN41 CMBN3 I CMBN2 I CMBN11 CMBNO I
x

Indicates the number of label linkage information entries.
Reserved. (This bit is undefined when read by the CPU.)

D-13

Section 4: Functional Description
4.1

Description
The LABop labels raster-scanned
binary image data, and includes
these three functions in a single
chip:
1. Primary labeling
2. Linked data combination
3. Secondary labeling

IP90ClO (LABop)

Registering
label linkage
information

Reference

The LABop provides individual
command and status bits for these
three functions. This allows each
function to execute independently,
and to run automatically and
continuously by simultaneously
applying the executing commands.

Final label

values data

Internal Processing Block Diagram

4.2

Device Operation

Primary Labeling Processing
The LABop performs primary labeling on raster-scanned binary image data. When the CPU sets
the CMD register EXE1 bit to 1, the LABop enters primary labeling mode when the next VS*
signal is asserted.
When in primary labeling mode, the LABop receives image data for the effective area defined by
the VEN* and HEN* signals, and simultaneously outputs temporary labels to the frame memory
and label linkage information to the label table. After starting processing, the LABop terminates
primary labeling mode when the next VS* is asserted. The effective area must contain at least two
lines (i.e., there must be two HEN* periods during the VEN* period). Also, an additional HEN*
period is required to process the last line of the effective area. The LABop operation is not
affected by disabling VEN*. (For details, see Section 5, "System Timing.")
Note that the LABop minimizes the number of temporary labels required, by using a proprietary
algorithm for handling large images. (For details, see Section 4.4, "Algorithm.")
The LABop outputs the value 0 (background value) for all input data that falls outside the
effective area, regardless of the input data value.

D-14

Linked Data Combination Processing
The LABop enters label linkage information processing mode when the CMD register's EXE2 bit is
set to 1. If this occurs when the EXE1 bit is 1 or primary labeling is under way, the LABop enters
label linkage information processing mode only after primary labeling processing of the effective
area is done. Otherwise, the LABop enters the mode immediately.
In this mode, the LABop processes the label linkage information in the label table. This creates a
conversion table (look-up table) used to convert between final and temporary labels.
The LABop ends label linkage information processing mode after all processing is done.

Secondary Labeling Processing
The LABop enters secondary labeling processing mode when the CMD register's EXE3 bit is set to 1.
If this occurs when label linkage information processing is underway, secondary labeling processing

mode is entered only after the current processing is completed and the next VS* is asserted.
Otherwise, the mode is entered immediately after the next VS* is asserted.
In this mode, the LABop executes secondary labeling for the temporary label data in the frame
memory by referring to the look-up table in the label table.
The LABop ends this mode when the next VS* signal is asserted. Note that if the EXE4 bit is set
to 1, the LABop continues processing even if VS* is asserted. If the EXE4 bit is set to 0, the LABop
ends secondary labeling processing mode when the next VS* is asserted.

Error Handling
If an error occurs while the CMD register's IRM bit and the error mask bit corresponding to the

error are both set to 1, the LABop asserts the LBERR* signal and stops operation. Refer to the
ERRS register to find the cause of the error. Restart the LABop by applying a system reset.

Reset
This operation initializes the LABop's registers and internal status. Bi-directional pins are placed
in high-impedance state.
The final label output LBDs are set to output (FFFFh) when the LBOE* signal is low, and to highimpedance state when LBOE* is high. Status outputs are deasserted. During a reset, all inputs
except RST* are invalid.

D-15

4.3

Control Sequence
Internal Register Write Sequence

Set the ERRM and ERRS registers to their
designated states.

Set error-related registers

Set the timer-counter register for
linked data combination processing

Set the TIME register to the designated value.

Set the CMD register to its designated state.

Set the control-command register

If the CMD register is set to 07h, for example,
a series of operations from primary labeling to
secondary labeling is automatically executed
using 8-connectedness labeling operation.

D-16

Labeling Execution Sequence

Hardware reset

Software reset

Setting internal registers

The LABop begins primary labeling when VS'
is asserted, and outputs temporary label data to
the frame memory and label linkage information
to the label table.

Execute primary labeling

Immediately after primary labeling finishes, the
LABop begins linked data combination to create a
look-up table (in the label table) that shows the
relationship between temporary and fmallabels.

Execute linked data combination

When linked data combination is complete,
the LABop begins secondary labeling when
the next VS' is asserted, and converts temporary
labels to final labels.

Execute secondary labeling

Output final labels

Final labels are output.

D-17

Error-Handling Sequence

Error

If an error occurs, the LABop asserts status output
signal LBERR * by pulling it low, then stops processing.

Read ERRS register

Reading the ERRS register shows the cause of the error.

Reset ERRS register

Clear the error by writing 0 to the ERRS register.

System reset

Reset the system using a hardware or software reset.

Set internal registers

D-18

4.4

Algorithm (Primary Labeling Processing)

Assigning Temporary Labels
The IP90CI0 minimizes the number of temporary labels required. For example, if the target image
shown in (a) below is read into the system from a camera, the pixels in the data do not always
form a smooth-edged line (due to jags or noise) as shown in (b). In such a case, a conventional
algorithm generates varying temporary labels, as shown in (c). However, the LABop applies the
single label shown in (d) by recognizing that the pixels of the object to be read from a camera are
connected.

(a)
Target image

(b)
Entered data
(binary image)

••••••••••
•
••••
•
•••
0
0
0
0

00000 0
0000
000
00
00000
0
000000
I

(c)
Example of temporary
labels by conventional
simple raster-scan
operation

I

4

4
4

I

I

0

000
0
00000
00000
00000

2

I

I

1

1

3

I

I

1

1

I

I

5 4 4
1
(d)
Temporary
labels by the
LABop

1
1
I
1

1

1

1

1

1
1

1

1

1

Run Label
The LABop uses a "run label" to minimize the temporary labels during primary processing. A row
of consecutive logical Is of input data is called a "run," and the preliminary label information
assigned to each run is called a "run label." The LABop incorporates 512 run label buffers, and so
can process up to 512 runs per line.
The thick line portions of the line in the figure to the
left indicate runs. The line contains six runs.
Therefore, in practical application, the maximum number
of processed pixels in the horizontal directions is much
greater than the worst case for alternating logical Is and
Os, which is 512 x 2 = 1024 pixels.

D-19

4.5

Label Table Format
bit
19

o

10 9

Adr. OOOh
OOlh

aO

bO

al

bl

002h

a2

b2

003h

a3

b3

.

I

1\

Label Linkage Information
Each pair of temporary labels
(aO, bO), (ai, bl), and (a2, b2)
represents label linkage information.
This information is stored in memory
(beginning at address OOOOh) in the
order in which it is generated during
primary labeling. Information is then
read from memory for linked data
combination .

.

I

3FFh
400h
40lh

to

402h

t2
t3

1<

tl

Look-up table used to convert
temporary labels to final labels.
Unused
Address: Temporary label value
Content: Final label value

i
7FFh

../

To store label linkage information, memory space equivalent to the number of label linkage
information entries is allocated, beginning with address OOOOh. Memory space equivalent to the
number of temporary labels is allocated in the look-up table, beginning with address lOOOh. The
contents of the unused addresses in the label linkage information and look-up-table memory spaces
are undefined.

D-20

Section 5: System Timing
5.1

CPU Interface

Read Cycle Timing
AO to 3, CS*

_ _---1xL-_ _ _ _ _ _ _ _ _ _ _ _----' '--_ _

RD*

DBOt07

Hi-Z

Write Cycle Timing
AO to 3, CS*

WR*

DBOto 7

Note:

X\. .____________________~X'_____

\'---_ _ _1
____________x\...____W_rit_e_da_ta_ _ _ _~X\..._________
The CPU interface signals are not synchronized with the image clock.

D-21

C1I

N

j! -

..,.

"3"

HEN*

CLK

\r-------r:

~------------~'r___+_

-- 10(0,0) 10(0,1) 10(0,2) 10(0,3)

((

;;

ID

IO(O,n)
PI

10(1,0) 10(1,1) 10(1,2) 10(1,3)

::

ID(1,n)

10(2,0) ID(2,1) 10(2,2) 10(2,3)

((

ID(2,n)

VEN·

1-~

CI-IO-~-m-,0-1~"IO(-m-'I')_-ID-(m-~-2~t~-m-'3":)H~]ID(mJ

HEN'

D)

~~~

-.L-J~I...~'-",'~~

~i

~~~~~~

LBD

~i

Conversion with look-up table

CLCE*

"... Final label output

I

=====(((::::::(=~~~I

VEN*
HEN*

FMVEN*
FMHEN*

CLK

VS'
SLEXE*
FMD

CLA

CLCE*
CLD

LBD

VEN*

HEN*
FMVEN*
FMHEN*

Note 1:
Note 2:

\

Ir--l
I:

rl

rl

~:

The dotted lines for FMVEN* and FMHEN* indicate the respective waveforms when
these signals are output in pulses.
For high-speed systems that may require two clock cycles for converting temporary labels
to final labels using the look-up table (with an external latch provided for CLA to
extend SRAM access time), an additional operating cycle to latch CLD and output it to
LBD is provided here.

D-24

UI

en

!!.!
a) Linked data combination processing is not completed within the primary labeling execution frame interval.

ac
til

oC

--

"C

I I I

VS

\

~

\

-

II /I

rTf

-J
I

1

~

\
Third frame _

Second frame

.....-- Primary labeling execution frame

\

I /I I

\

First frame

)~

FMVEN'

PLEXE'

\

Linked data combination period

LUEXE'

4
k- Secondary labeling _

~

\

SLEXE'

I

1

execunon frame

Three frames

b) Linked data combination processing is completed within the primary labeling execution frame interval.

CLK~~~~~
;\

VS

I..

Ir--l~'

First frame

~l-ll

FMVEN*

_I..
I

Description of status signals

llJ

PLEXE * is asserted and held low during the
primary labeling execution frame interval.

Second frame -

Secondary labeling
Primary labeling execution frame - -_____~""..
e-- execution frame ----.

PLEXE'

\1-----11'\-1\
~

I

Linked data combination period

\l~~l\

LUEXE'

I

LUEXE* is asserted immediately after primary labeling
of the effective area is completed. and is de-asserted
when linked data combination is complete.

II

SLEXE* is asserted and held low during the secondary
labeling execution frame interval.

11\-

II-----I~'~'rl--~

SLEXE*

I"

Two frames

~I

IP90C10j
Labeling

_~ccelerator

•

C

Section 6: Electrical Characteristics

6.1

Absolute Maximum Ratings
(Referenced to GND, Ta

= 25 DC unless otherwise specified)

Parameter

6.2

Symbol

Rating

Unit

DC supply voltage

Vdd

-0.3 to 6.5

V

Input/ output voltage

VIN

-0.3 to Vdd + 0.3

V

Operating temperature

TOPT

o to 70

DC

Storage temperature

TSTG

-10 to 80

DC

Recommended Operating Conditions
(Ta
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vdd

4.75

5.0

5.25

V

Range

VI

0

Vdd

V

High
level

VIH

2.2

Vdd

V

Low level

VIL

Power-supply voltage

Input voltage

6.3

Condition

= 0 to 70DC)

TTL level
normal input

0

0.8

V

Input rising time

TRI

TTL level

0

200

ns

Input falling time

TFI

normal input

0

200

ns

Input/Output Capacitance
Parameter
Input capacitance
Output capacitance
Note 1:

Symbol
CIN
COUT

Condition

Typ.

Unit

Any input (see Note)

10

pF

Any output

10

pF

Does not apply to bi-directional buffers.

D-26

6.4

DC Characteristics
Vdd
Ta
Symbol

Parameter

Condition

Low level input voltage

VIH

High level voltage

lIN

Input
Without pull-up resistor
VIN
current Without pull-down resistor

With pull-up resistor
VOH

High level output voltage
(Note 1)

VOL

Low level output voltage
(Note 1)

Typ.

Max. Unit
0.8

VIL

With pull-down resistor

Min.

= 5 V±5%
= 0 to 70°C
GND = OV

2.0

= Vdd or GND

= Vdd
= GND
IOH = -4 rnA
IOH = -6 rnA
IOL = 4 rnA

-10

V
±1

10

IlA
IlA
IlA

VIN

35

110

335

VIN

-35

-115

-350

2.4

4.5

2.4

4.5

IOL = 6mA

V

V
V

0.2

0.4

V

0.2

0.4

V

IOZ

Off-state leakage current

VOH

±l

10

IlA

Output short circuit current

Vdd
Vdd

= Vdd or GND
= Max, Vo =

-10

lOS

15

50

130

rnA

(Note 2)

Vdd

= Max, Vo = 0 V

-5

-25

-100

rnA

Note 1:
Note 2:

IOL = 6 rnA and IOH = -6 rnA for the FMDll-O and LBDll-O pins; 4 rnA for other pins.
When referring to the 4-mA buffers in Note 1, this parameter defines the current that
flows when a high output is shorted to GND. Make all efforts to ensure that two or more
outputs are never shorted to GND simultaneously. If this nevertheless occurs, the
shorting time must be no more than 1 second.

D-27

6.5

AC Characteristics
(Note:

The load capacitance of all output pins is assumed to be 30 pF.)

CPU Interface
Read Cycle
AOto 3
CS*

RD*

DB 0 to 7

unit: ns
Parameter

Symbol

Min.

Typ.

A and CS* setup times to RD* falling

tAR

5

-

A and CS* hold times to RD* rising

tRA

0

-

RD* pulse width

tRP

30

Delay time from RD* falling to DB enable

tRD

5

Delay time from RD* rising to DB placed in Hi-Z

tOF

3

-

Max.

-

20

15

Write Cycle
AOto 3
CS*

WR*

DB 0 to 7
~---

tDW

----~--

tWD

unit: ns
Symbol

Min.

Typ.

A and CS* setup times to WR* falling

tAW

5

-

-

A and CS* hold times to WR* rising

0

WR pulse width

tWA
twp

30

DB setup time to WR* rising

tow

15

-

DB hold time to WR* rising

two

0

-

-

Parameter

D-28

Max.

Image Data Input

eLK

ID, PI

VS*

HS*

t VES

VEN*

HEN*

unit: ns
Parameter

Symbol

Min,

Typ.

eLK cycle

tcc

25

-

High-level period of eLK

Max.

tcc-lO

tcp

10

ID and PI setup times to eLK rising

tIDS

8

-

-

ID and PI hold times to eLK rising

tIDH

5

-

-

VS* falling setup time to eLK rising

tyS

8

-

-

VS* rising hold time to eLK rising

tYH

5

-

-

HS* falling setup time to eLK rising

tHS

8

-

-

HS* rising hold time to eLK rising

tHH

5

-

-

VEN* falling setup time to eLK rising

tYES

8

-

-

tcc/2

VEN* rising hold time to eLK rising

tYEH

5

-

HEN* falling setup time to eLK rising

tHES

8

-

-

HEN* rising hold time to eLK rising

tHEH

5

-

-

D-29

Label Table Interface
Read Cycle 1 (label linkage information processing)
I ..

>.

CLAOto 12

CLCE*

t Re

>(
tAA

~~"\ I~"f

tAH
t eEP

/

////

K=

)<

CLDO to 23

unit: ns
Parameter

Max.

Symbol

Min.

Typ.

Read cycle time

tRC

2tcc-5

2tcc

CLA access time to CLCE* rising

tAA

30

-

-

CLA hold time to CLCE* rising

tAH

5

-

-

CLCE* pulse width

tCEP

2tcc-1O

CLD setup time to CLCE* rising

tRDS

4

-

-

CLD hold time to CLCE* rising

tRDH

5

-

-

2tcc

-

-

Read Cycle 2 (secondary labeling)
CLK
CLAOto 12
CLCE

CLDOto 11
t eDs

teDH

unit: ns
Symbol

Min.

CLA hold time to CLK rising

tDAH

5

Delay time from CLK rising to CLA enable

tDAS

Delay time from CLK rising to CLCE* falling

Parameter

Typ.

Max.

-

-

-

-

20

tDCL

-

-

20

Delay time from CLK rising to CLCE* rising

tDCH

-

-

20

CLD setup time to CLK rising

tCDS

4

-

-

CLD hold time to CLK rising

tCDH

5

-

-

D-30

Write Cycle

CLAO to 12

-d~"------

- -

wc

_ ...
t

-~b-

tAC

CLCE*

CLWR*

t CEP

""

L

""

t wRP

L

V

V

-

- - t WDD - - -

CLDO to 23

tCA

tWDH

unit: ns
Parameter

Symbol

Min.

Typ.

Write cycle time

twc

2tcc-5

2tcc

-

CLA setup time to CLCE* and CLWR* falling

tAC

5

-

CLCE* pulse width

tCEP

tcc-5

tee

-

CLA hold time to CLCE* and CLWR* rising

tCA

5

-

-

CLWR* pulse width

tWRP

tcc-5

tcc

-

Delay time from CLCE* and CLWR* falling to
CLD

tWDD

-

-

17

CLD hold time to CLCE* and CLWR* rising

tWDH

5

-

-

D-31

Max.

Frame Memory Interface
Read Cycle

eLK

FMVEN*

FMHEN*

FMDO to 11

unit: ns

Parameter

Symbol

Delay time from CLK rising to FMVEN* falling

Min.

Typ.

Max.

tpVLD

-

-

20

Delay time from CLK rising to FMVEN* rising

tpVHD

-

-

20

Delay time from CLK rising to FMHEN* falling

tpHLD

-

20

Delay time from CLK rising to PMHEN* rising

tpHHD

-

-

20

PMD setup time to CLK rising

tPDS

4

-

-

PMD hold time to CLK rising

tpDH

5

-

-

D-32

Write Cycle

eLK
FMVEN*

FMHEN*
tFWLD

FMWR*

FMDOto 11

FMOE*

unit: ns
Symbol

Min.

Typ.

Max.

Delay time from CLK rising to FMVEN* falling

tFVLD

-

-

20

Delay time from CLK rising toFMVEN* rising

tFVHD

-

-

20

Delay time from CLK rising to FMHEN* falling

tFHLD

-

-

20

Delay time from CLK rising to FMHEN* rising

tFHHD

-

-

20

Delay time from CLK rising to FMWR* falling

Parameter

tFWLD

-

-

20

Delay time from CLK rising to FMWR* rising

tFWHD

-

-

20

Delay time from CLK rising to FMD* enable

tFDZD

-

-

20

Delay time from CLK rising to FMD* placed in Hi-Z

tFDDZ

-

-

20

FMD hold time to CLK rising

tFDH

4

-

-

Delay time from CLK rising to valid FMD

tFDD

-

-

20

Delay time from FMOE* rising to FMD placed in HiZ

tFODZ

-

-

20

Delay time from FMOE* falling to valid FMD

tFOZD

-

-

20

D-33

Secondary Labeling

CLK
LBDOto 11

LBOE*

unit: ns
Parameter

Symbol

Min.

Typ.

tLBH

4

-

15

tLBD

-

Delay time from LBOE* rising to LBD* placed in HiZ

tLDDZ

-

-

Delay time from LBOE* falling to valid LBD

tLDZD

-

-

LBD hold time to CLK rising
Delay time from CLK rising to valid LBD

Max.

15
15

Reset Timing
CLK

~~_________________ -_-_-_-_-_~~~~~~~~===~~~~

RST*

t_R_SW
__

The reset signal must be held active for at least three clock cycles.

unit: clock cycles
Parameter
RST* pulse width (Low period)

D-34

Symbol

Min.

Typ.

Max.

tRSW

3

-

-

Section 7: Sample Application
7.1

Sample Labeling Result
The LABop executes primary and secondary labeling in real time. However, the time required for
label linkage information processing depends on the input image data and the clock rate. The
table below lists the clock cycles required for label linkage information processing, as well as the
time required (in ms) for the LABop to execute label linkage information processing on the sample
images in Photos 1 through 3.

Example of Labeling Results

Image

No. of
temp.
labels

Number of
final labels

Number of label
linkage information
entries

Photo 1
Photo 2
Photo 3

3234
650
BOO

2227
366
50

1285
297
750

Linked data combination
Required
Required time (ms)
clock cycles

39.5k
8.5k
15k

15 MHz
2.63
0.57
1.03

20 MHz
1.98
0.43
0.77

m!j:.Jfv")~fr1lfpl!:/ 7,

40 MHz
0.99
0.21
0.38

'T t. i-,&!;j<

T Gf',W(jI:: J;: "5 '<" <:f.tl)51 L- t:. til"
') l t~Rl'·lit.J:~ '"
{t~k&'I1'Ij\~I::l\1tf,-(J']t.J:1rHtb/ 7,

10 ft11:n'
S I tHf~O)'fY1J
tJ11~IJIiI,!lllm~.!(7)::1 /' t' ~ - -7 :/
7,'Tf..(":&!Qo fl~I;t771 ~trl
of O)fl!!(7)I~JRi~.ffiIJt(1f~lf'ltr.j~
Tf...>d:~:JliJtt"Q(7);I;IS

G1:1lf,j~fj;*Jd! ttt:.

m

:/ 7, 'T f,.(l)UIf~ai"i-89il'-'::'~rl.o

IIIIjl1Jl'lilllJj'i'~~llIUWI:1lJj'i

Photo 1: Crystal surface

L-, of(7)

Photo 2: Text data
Note: The diagram below is from T. Hattori,
"New Regional Labeling Algorithm for Pipeline
Image Processors and Proof of Correctedness", in
proc. IECON '91, pages 2005-2010, 1991.
1

1
1

1
1
1 1 1
11
1
1
11 111 111111 1
1
1 1 1
11
1 1
1 1
1
1 1 1
111
11
11
1
11
1
111
11
11
11
11
1
1 1 1
11
11
11
1 1
1
1111111
111111
11
11
111
1
11
11
111
1
1
1 1 1 1 111
11
11
1
1
11
1111111
1 1 1 1
1 1 1
111
11
11
11111111 1
1
11
1
1
1 1 111
11
11 1 1
1 1
1 1 1 1
11 1
11
11
1 1 1 111 1 1
1 1
1 1
1 1 1
1 1
111111
11
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 1 1 1 111
11 1 1 1 1 1 1
1
1
1
1
, 1 1 1 1 111
11 1 1 1 1 1 1
1
1
1 1 1 1 111
11 1 1 1 1 1 1
1
11
1 1 1 1
1 1
1 1
1 1 1 1 1
1 1
1 1 1
1
1 1 111 1 1
1
111111111111111
1 1111111
1

Photo 3: Hattori Pattern, in a 5 x 10 Array (Note)

D-35

7.2

Real-Time Parallel Processing

Frame number

LABop
ID (Seq.)

o

2

3

4

A (3n)
B (3n+l)
C (3n+2)

7.3

Sample Application Using an Image-Processing Device

Note: The IP90MDlO is a daughter-board
module that integrates the IP9OClO
and its peripheral circuits. It can be
used as a convenient tum-key system
with provided control software.
Post-processing

D-36

7.4

Reference Circuits (Labeling Processing + Feature Extraction Processing)
IP90C51 + IP90C10 + IP90C18

12

5K word x 16-bit
line buffer (Note 1)

"P0485506-35

(NEC)

(NEC)

HS'
ICLK

HS'

HS'
ICLK

HS'
ICLK
HEN'

Input image
data -----,4---1
VS'
HS'
ICLK

ICLK: 25 MHz (max.)
Horizontal effective data: 1135 words
(controlled by IlPD42102G-3)

1135 word x 8-bit
line buffer
>JP042102G-3

ICLK

,

--i

12

Label data

(NoteS)
VS*

Feature

----..!
~

HS*
ICLK -...l
VEN*

HEN'"

---i

-----i

IP9OCI8-HS
FRAME

MEMORY
(Note 3)

IDO-7

LO-II
OLO-II

000-23

24

Image data
(LUT output,
run coord.
measurement)
Run detection

iCLK

signal

!DEN"'
DIDEN'"

Status output

FEN*
VEN'"

TC5588J-15
(Toshiba)
74ACTOO

Note 1:
Note 2:

Note 3:
Note 4:

Note 5:

ICLK
VEN'"
HEN'"

HEN*

SRAM 8KB x3

This line buffer is used as a IH line delay for the IP90CI0 and IP90C18.
The IP90CI0 requires a frame memory design that generates a horizontal pixel delay
factor. This line buffer is required to absorb that pixel delay factor. The delay value (n)
depends on the frame memory design.
This is the frame memory required by the IP90ClO.
This determines the processing area for the IP90C18. Use IP90C51s as necessary. In
certain cases where the IP90CI0 executes secondary labeling only, the circuit can be
designed to function as if only the IP90C18 were operating.
Frame memory should be controlled so that the input image data and label data appear
on the same horizontal line (with no I-line delay differential).

D-37

-...

~ ~.8

0.5 ::l
O]~
en (Q ~

!!:...J.<

Appendix A: Functional Description and Algorithms for
LABop
New Approach to and Implementation of an LSI for High-Speed Image Labeling
Nobuo Hayashi, Hiroshi Nittaya, Masahiro Kohno, and Masahiro Kato
Sumitomo Metal Industries, Ltd.
1-8 Fuso-cho Amagasaki Hyogo 660 Japan
Abstract: Image labeling plays an important role
in image analysis and pattern recognition. This
paper presents the use of a single accelerator LSI
chip for image labeling, and proposes a new
primary labeling algorithm suitable for hardware
implementation. The algorithm determines
primary labels by using a simple 2 x 2 matrix
window. The LSI performs all labeling processes,
including primary labeling, labeling unification,
and secondary labeling. It runs at 40 MHz, and can
generate up to 4094 primary labels for use in 4- or
8-connectivity.

A.1

Introduction

High-speed labeling of connected components in a
binary image is one of the most fundamental
problems in image analysis and pattern
recognition.
Many algorithms and hardware designs have
attempted to achieve high-speed labeling ([1][4]). Labeling connected components based on raster
scanning consists of three stages: primary labeling,
labeling unification, and secondary labeling. In
primary labeling, a two-dimensional binary image
is scanned from upper left to lower right to
generate temporary labels. When the primary
labeling process generates different temporary
labels on a connected component and later
recognizes them to be linked or part of the same
connected pattern, the process then generates label
linkage information that represents two temporary
labels to be linked. In the linked data combination
stage, a look-up table is generated by unifying
label linkage information, which represents the
relationship between temporary labels and final
labels. Finally, secondary labeling generates final
labels by referring to the look-up table and
relabeling temporary labels accordingly.

This appendix presents a method of using a single
LSI chip for high-speed image labeling, and
proposes a new algorithm for primary labeling.
Section A.2.1, "Primary Labeling," discusses this
new algorithm, which determines temporary
labels by using a simple 2 x 2 matrix window to
simplify the hardware and achieve high-speed
processing, while still using the same number of
temporary labels as conventional methods. Section
A.2.2, "Linked Data Combination," then presents
the linked data combination algorithm, which
requires one-dimensional memory and is suitable
for use in hardware. Finally, Section A.3,
"Hardware Architecture," describes the hardware
and specifications of the labeling LSI.

A.2
Algorithms
A.2.1 Primary Labeling
In this discussion, two-dimensional image input is

represented by a binary number in which pixels
marked 1 denote the target, and the O-pixels
denote the background. In primary labeling, a
matrix window scans a binary image from upper
left to lower right to generate temporary labels
and label linkage unification. The primary
labeling algorithm uses a simple 2 x 2 matrix
window (see Figure A-I) to recognize the target
image and its connectivity, and then determines
temporary labels according to the 16 conditions of
the matrix window shown in Figure A-2.
i+1

__.-- __

-- - - - ~ -.- --- - - - - -~- -- - --- --- - ------- --- ---- - - --:- - - --

---------------1
j + 1 ---------------,

Conventional algorithms for primary labeling
concentrate mainly on achieving high-speed label
unification by reducing the number of temporary
labels and using relatively large matrix windows
([1], [2]). Previous papers have focused on the
label unification process, though they dealt
mainly with processing using software, which
requires a large two-dimensional memory or
complicated memory access to obtain a look-up
table ([3], [4]).

~

P(i.j)

I p(i+ l,j) I

p(i,j + I)

1pCi +l,j + 1)1

Figure A-I: Raster Scanning a 2 x 2 Matrix
Window

D-38

The operations "R<-f(RLB)" and "R<- g(R, RLB)"
determine temporary labels (the notation "<--"
represents a substitution):
R <-- f(RLB):
X <-- RLB
if X = 0 then R <-- LC and LC <-- LC + 1
else R <-- X
R <-- g(R, RLB):
X <-- RLB
(1) if X = 0, R = 0, then R <-- LC and LC <-LC+l
(2) if X 'I- 0, R = 0, then R <-- X
(3) if X 'I- 0, R 'I- 0, then do nothing
(4) if X 'I- 0, R 'I- 0, X = R, then do nothing
(5) if X 'I- 0, R 'I- 0, X 'I- R, then LIB <-- X, R
and R <-- min(X, R)
where:
R:
Temporary label register value.
X:
Run label register value.
RLB: Run label buffer value. This buffer
stores run labels and works as FIFO
memory.
LIB:
Linkage information buffer value. This
buffer stores label linkage information.
LC:
Label counter value that represents the
number of temporary labels.

[]]]]
[ill]
[]]]]
[]]JJ

PM <-- 0
8-point connectivity
4-point connectivity
R <-- 0
R <-- 0
RLB <-- R

RLB <-- R

[]]]]
[]]]]
[]]]]

IT.IIl
[ill]
[ill]
[ill]
[]]JJ

R <-- (RLB)

R <-- (RLB)

R <-- (RLB)

R <-- (RLB)

[ill]
[]]]]
[ill]

R <-- g(RLB)
RLB <-- R

RLB <-- R
R <-- f(RLB)

R <-- g(RLB)

R <-- g(RLB)

IT.IIl

The temporary label register value R is
terminated according to the procedures shown in
Figure A-2. When the value in the upper-left of
the matrix window is 0 (background), 0 is stored in
frame memory; when the value in the upper-left
of the matrix window is 1 (1 indicates the target
image), R is stored in frame memory as a
temporary label. Label linkage information is also
stored in the linkage information buffer when it is
generated.
This algorithm recognizes connectivity, and gives
a temporary label for the image that has a
depression I-pixel depth or diagonal pattern,
thereby reducing the number of temporary labels
generated. The algorithm corresponds to both 4and 8-point connectivity by slightly modifying the
procedure shown in Figure A-2.

A.2.2 Linked Data Combination
The linked data combination process unifies the
label linkage information in the linkage
information buffer, and generates a look-up table
that determines how temporary and final labels
correspond. The linked data combination
algorithm generates a chain label information
table that represents the connectivity chain of
temporary labels based on the label linkage
information before the look-up table is generated.

[jJ]J
[]]]]
[jJ]J
[]]JJ
[jJ]J
IJJ]]
[jJ]J
[ill]
IJJI]
[]]]]
IJJI]
[]]JJ
IJJI]
IJJ]]

PM <-- R
8-point connectivity
4-point connectivity
R <-- 0
RLB <-- R

RLB <-- R

RLB <-- R

RLB <-- R

IJJI]
[ill]

Case 1: When the upper-left value of the window is Case 2: When the upper-left value of the window is
0,0 is written to the frame memory (PM).
1, R is written to the frame memory (PM).

Figure A-2: Definition of Primary Labeling Operation

D-39

The algorithm consists of the three steps shown in
Figure A-3: clear, chain, and table generation.
Assume the label table is a one-dimensional
memory. In the clear and chain steps, the label
table works as a chain label information table; in
the table generation step, it works as a look-up
table. In the chain label information table the
notation "(m) = n" means that n represents the
contents of the label table denoted by address m,
in which m must be greater than n (every
temporary label m has chain information with a
smaller-numbered temporary label n). When n = 0,
temporary label m has no chain information with
smaller temporary labels.

address number, the look-up table is generated
from the label table.
Since the algorithm requires one dimensional
memory and consists of simple memory access and
data comparison, this algorithm is suitable for
hardware implementation.
(Step 1) Clear

°

(1) k <-(2) (k) <-- 0

(3) k <-- k+1
(4) if k < LC then go to (2)
(5) end
where (k) represents contents of label
table denoted by address k, and LC is
the final number of temporary label.

The clear step initializes the label chain table by
clearing its contents (i.e., any temporary label has
no chain information with smaller-numbered
temporary labels).

(Step 2) Chain

The chain step then generates a chain label
information table in which each temporary label
has connectivity with only one smaller-numbered
temporary label. This table is generated by
reading label linkage information (label AO
connects with label BO) from the label linkage
buffer, and searching for connectivity for each Ao
and BO in the chain label information table in the
direction of smaller-numbered temporary labels.
Let Ai and Bi be the smallest number of temporary
labels that connect with AO and BO, respectively.
(Ai) = Bi is written in the chain label information
table when Ai > Bi' and (Bi) = Ai is written in the
chain label information table when Ai < Bi' As a
result, temporary labels AO and BO are connected
with each other on the chain label information
table through Ai and Bi connectivity. By applying
these operations to all label linkage information
in the linkage information buffer, every temporary
label either has connectivity with only one
smaller-numbered temporary label, or has no
connectivity with smaller-numbered temporary
labels.

(1) k <-- 0

(2) m, n <-- LIB(k)
(3) if (m) # 0 then m <-- (m) and go to (3)
(4) if (n) # 0 then n <-- (n) and go to (4)
(5) if m < n then (n) <-- m
else if n < m then (m) <-- n
(6) k <-- k + 1

(7) if k1lJl
I'Mtil
rMU'1
u
own
pu I down
,NL
LLU1
LLUL
Vdd

'w

Pin No.
61
62
63
64

U

YW

6
66
6
68
6'1
IU
72

Name
GNU
L03
LU4
LLU:
LL

TYI e
'W

U

LUI
LLU~.

GNI
LLU'1
YUU(1own
pull down
1

l<-J.
'W
U

.J:'l.ote.L
Note

[L
'W
PW
IL
IL
LL
IL
IL
Note
Note 2
P
IIC

4
10
6
III

''1
IlU
III

112
113
~4

115
116
~I

Illl
~'1

PW

90

LL12
GN.
Y
LLl3
LL14
1
LL 6
1
GN
_LL1~

LL 1'1
pull own
ull(10wn
GN
LLt'
L ,WKVdd

I'W
'W

Pin No.
91
lJ2
'13
'14
95

Name
LAO
LA1
LLAL
LA3
LA'!
LLA5
GNU
LA6
LA.

':16
'j/

'!Il


~----~----------------~--------~------------~\

_llll--~--"--j~~

~:

~~~~~~

LBO

VEN*'

HEN'

" " Final label output

CLK

110
------II~r\'-----___lIV
'---,1-11

11

(Note I)

qi.. mmm.mmm.mmmil
-;-L.-..-..Wr--···· .. ·--· ....·.. ···: r l
L....

1'r---1'r---J,,\-1-------(N.,....ote-j,,-)

~~~I

I~\

VS'

SLEXE*

\

====:::«:::::«=~~~\

FMVEN*
FMHEN*

~:

IlecondarY labeling (look-up table conversion) COliiPletiOn ----.

,,.---------11:

FMD
Temporary label read
CLA

CLCE*
CLD
". (Note2)

LBO

VEN'"

HEN' ~L__________~II~
FMVEN*

FMHEN*

Note 1:
Note 2:

r
C::WI-I_ _ _--'---'r
Ii

l

l

The dotted lines for FMVEN* and FMHEN* indicate the respective waveforms when
these signals are output in pulses.
For high-speed systems that may require two clock cycles for converting temporary labels
to final labels using the look-up table (with an external latch provided for CLA to
extend SRAM access time), an additional operating cycle to latch CLD and output it to
LBD is provided here.

E-24

(11

(n

--(J)

a) Linked data combination processing is not completed within the primary labeling execution frame interval.
CLK

I II
I:
til

oI:

~rfl-Il,

"C

I:

VS

I"

I

~ OIl

First frame

LJ11

FMVEN*

I

~ OIl

Second frame

Primary labeling execution frame-Jf-i- - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 - - - - PLEXE*

;~ Linked data combination period ~
LUEXE*

YI
I
Secondary
----j-----1\------1\------------------------!~
I
executionlabeling
frame

SLEXE*

~

I..

~

Three frames

I

b) Linked data combination processing is completed within the primary labeling execution frame interval.
CLK

vs

~rfl-Il,~~n-n-fl-JLJL
\

LUJ

~

FMVEN*

)\----\~ I rTT"

,I

First frame

~
I
------I~~

(,----1\----\1

J------J

Primary labeling execution frame

~--~)'\----\I

PLEXE*

~

PLEXE* is asserted and held low during the
primary labeling execution frame interval.

)
Secondary labeling
execution frame

~----~%~-----+---------

,I

SLEXE* is asserted and held low during the secondary
labeling execution frame interval.

I

,~----~I\----\~\------~
SLEXE*

I"

LUEXE* is asserted immediately after primary labeling
of the effective area is completed, and is de-asserted
when linked data combination is complete.

Linked data combination period

'~~\

LUEXE*

..
---

Description of status signals

Two frames

•

I

IP90Cll

I

Labeling
Accelerator (lK)_

Section 6: Electrical Characteristics
6.1

Absolute Maximum Ratings
(Referenced to GND, Ta

= 25°C unless otherwise specified)
Symbol

Rating

Unit

Vdd

-0.3 to 6.5

V

Input! output voltage

VIN

-0.3 to Vdd + 0.3

V

Operating temperature

TOPT

o to 70

°C

Storage temperature

TSTG

-10 to 80

°C

Parameter
DC supply voltage

6.2

Recommended Operating Conditions (Ta
Parameter

Symbol

6.3

Condition

Min. Typ.

Unit

Vdd

4.75

5.25

V

VI

0

Vdd

V

High
level

VIH

2.2

Vdd

V

Low level

VIL

0

0.8

V

TTL level
normal input

5.0

Max.

Range

Power-supply voltage

Input voltage

=0 to 70°C)

Input rising time

TRI

TTL level

0

200

ns

Input falling time

TFI

normal input

0

200

ns

Input/Output Capacitance
Parameter
Input capacitance
Output capacitance
Note 1:

Symbol
CIN
COUT

Condition

Typ.

Unit

Any input (Note 1)

10

pF

Any output

10

pF

Does not apply to bi-directional buffers.

E-26

6.4

DC Characteristics
Vdd = 5V ± 5%
Ta = 0 to 70 C
GND = OV
D

Symbol Parameter

Min.

Condition

Typ.

Max. Unit

VIL

Low level input voltage

VIH

High level voltage

2.0

lIN

Without pull-up resistor
VIN = Vdd or GND
Input
current Without pull-down resistor

-10

±1

10

J.lA

VIN = Vdd

35

110

335
-350

J.lA
J.lA

With pull-down resistor

O.S

V
V

VIN = GND

-35

-115

High level output voltage
(Note 1)

IOH = -4 rnA

2.4

4.5

V

IOH = -6 rnA

2.4

4.5

V

Low level output voltage
(Note 1)

IOL =4mA

0.2

0.4

V

IOL = 6 rnA

0.2

0.4

V

IOZ

Off-state leakage current

VOH = Vdd or GND

-10

±1

10

J.lA

lOS

Output short circuits current
(Note 2)

Vdd=Max, Vo=Vdd

15

50

130

rnA

-5

-25

-100

rnA

With pull-up resistor
VOH

VOL

Note 1:
Note 2:

Vdd = Max, Vo

= OV

IOL = 6 rnA and IOH =-6 rnA for the FMDll-O and LBDll-O pins; 4 rnA for other pins.
When referring to the 4-mA buffers in Note I, this parameter defines the current that
flows when a high output is shorted to GND. Make all efforts to ensure that two or more
outputs are never shorted to GND simultaneously. If this nevertheless occurs, the
shorting time must be no more than 1 second.

E-27

6.5

AC Characteristics
(Note:

The load capacitance of all output pins is assumed to be 30 pF.)

CPU Interface
Read Cycle
AOto 3
CS*
tRP-

r----j---

RD*

DB 0 to 7

unit: ns
Parameter

Symbol

Min.

Typ.

Max.

A and CS* setup times to RD* falling

tAR

5

-

-

A and CS* hold times to RD* rising

tRA

2

-

RD* pulse width

-

tRP

40

Delay time from RD* falling to DB enable

tRD

5

Delay time from RD* rising to DB placed in Hi-Z

tDP

3

30
20

Write Cycle
AOto 3
CS*

WR*

DB Oto 7
~--- tDw ----~-- tWD

unit: ns
Parameter

Symbol

Min.

A and CS* setup times to WR* falling

tAW

5

-

-

A and CS* hold times to WR* rising

tWA

2

-

WR pulse width

twp

40

DB setup time to WR* rising

tDW

20

DB hold time to WR* rising

tWD

2

-

-

E-28

Typ.

Max.

-

Image Data Input

eLK

m,PI

Vs*

HS*

VEN*

HEN*
unit: ns
Parameter

Symbol

Min.

Typ.

eLK cycle

tee

50

-

-

High level period of eLK

tePH

15

-

Low level period of eLK

tePL

15

-

-

ID and PI setup times to eLK rising

tms

12

-

-

-

-

Max.

tIDH

5

VS* falling setup time to eLK rising

tyS

12

-

-

VS* rising hold time to eLK rising

tYH

5

-

-

HS' falling setup time to eLK rising

tHS

12

-

-

HS' rising hold time to eLK rising

tHH

5

-

-

VEN* falling setup time to eLK rising

tYES

12

-

-

VEN* rising hold time to eLK rising

ID and PI hold times to eLK rising

tYEH

5

-

-

HEN* falling setup time to eLK rising

tHES

12

-

-

HEN* rising hold time to eLK rising

tHEH

5

-

-

E-29

Label Table Interface
Read Cycle 1 (label linkage information processing)
t RC

)<

CLAO to 10

CLCE*

CLDO to 19

""""""

>(

.

tAA

tAH
t CEP

"""{

/

I

////

C

)<

unit: ns
Parameter
Read cycle time
CLA access time to CLCE* rising
CLA hold time to CLCE* rising

Symbol

Min.

Typ.

Max.

tRC
tM

2tcc-5

2tcc

30

-

tAH

5
2tcc-lO

2tcc

4

-

5

-

CLCE* pulse width
CLD setup time to CLCE* rising

tCEP
tRDS

CLD hold time to CLCE* rising

tRDH

-

Read Cycle 2 (secondary labeling)
CLK

CLAO to 12
CLCE

CLDO to 11
t CDS

tCDH

unit: ns
Parameter

Symbol

Min.
5

Delay time from CLK rising to CLA enable

tDAH
t DAS

Delay time from CLK rising to CLCE* falling
Delay time form CLK rising to CLCE* rising

tDCH

CLD setup time to CLK rising
CLD hold time to CLK rising

tCDS
tCDH

CLA hold time to CLK rising

tOCL

E-30

-

Typ.

-

4

-

5

-

Max.

20
20
20
-

Write Cycle

CLAOto 10

_d~4_:
_twe-=~_

--

-

t AC

CLCE*

CLWR*

"-,,-

t CEP

"-

t WRP

L

tCA

V

/

/

"-

-

- - t WDD

CLDOto 19

tWDH

unit: ns
Symbol

Min.

Typ.

Write cycle time

twc

2tcc-5

2tcc

-

CLA setup time to CLCE* and CLWR* falling

tAC

5

-

-

CLCE* pulse width

tCEP

tee-5

tee

-

CLA hold time to CLCE* and CLWR* rising

tCA

5

-

-

Parameter

Max.

tWRP

tec-5

tee

-

Delay time from CLCE* and CLWR* falling to
CLD

tWDD

-

-

17

CLD hold time to CLCE* and CLWR* rising

tWDH

5

-

-

CLWR* pulse width

E-31

-I

Frame Memory Interface
Read Cycle

eLK

FMVEN*

FMHEN*

FMDOto 11

unit: ns
Parameter

Symbol

Min.

Typ.

Max.

-

25

-

25

tpVLD

-

Delay time from CLK rising to FMVEN* rising

tpVHD

-

Delay time from CLK rising to FMHEN* falling

tpHLD

Delay time from CLK rising to FMHEN* rising

tPHHD

-

FMD setup time to CLK rising

tpDS

4

-

-

FMD hold time to CLK rising

tPDH

5

-

-

Delay time from CLK rising to FMVEN* falling

E-32

25
25

Write Cycle

eLK
FMVEN*

FMHEN*
tFWLD

FMWR*

FMDOto 11

FMOE*

unit: ns
Symbol

Min.

Typ.

Max.

Delay time from CLK rising to FMVEN* falling

tpVLD

-

-

25

Delay time from CLK rising to FMVEN* rising

tpVHD

-

-

25

Delay time from CLK rising to FMHEN* falling

tpHLD

-

-

25

Delay time from CLK rising to FMHEN* rising

tpHHD

-

-

25

Delay time from CLK rising to FMWR* falling

tpWLD

-

-

25

Delay time from CLK rising to FMWR* rising

tpWHD

-

-

25

Delay time from CLK rising to FMD* enable

tPDZD

25

tPDDZ

-

-

Delay time from CLK rising to FMD* placed in Hi-Z

-

25

FMD hold time to CLK rising

tPDH

4

-

-

Delay time from CLK rising to valid FMD

tPDD

-

25

Delay time from FMOE* rising to FMD placed in HiZ

tpODZ

-

-

30

Delay time from FMOE* falling to valid FMD

tpOZD

-

-

20

Parameter

E-33

Secondary Labeling

CLK
LBDOto 11

LBOE*

unit: ns
Parameter

Symbol

Min.

Typ.

Max.

tLBH

4

-

-

tLBD

-

-

20

Delay time from LBOE* rising to LBD* placed in HiZ

tLDDZ

-

-

20

Delay time from LBOE* falling to valid LBD

tLDZD

-

-

20

LBD hold time to CLK rising
Delay time from CLK rising to valid LBD

Reset Timing
CLK

--r--

~r-..~o--_~-_-_~~~~~~======_t_R_SW_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-

RST*

The reset signal must be held active for at least three clock cycles.

unit: clock cycles
Parameter
RST* pulse width (Low period)

E-34

Symbol

Min.

Typ.

Max.

tRSW

3

-

-

Section 7: Sample Application
7.1

Sample Labeling Result
The LABoplK executes primary and secondary labeling in real time. However, the time required
for label linkage information processing depends on the input image data and the clock rate. The
table below lists the clock cycles required for label linkage information processing, as well as the
time required (in ms) for the LABop1K to execute label linkage information processing on the
sample images in Photos 1 through 3.

Example of Labeling Results

Image

No. of
temp.
labels

Number of
final labels

Number of label
linkage information
entries

Photo 1
Photo 2

650
800

366
50

297
750

Linked data combination
Required
Required time (ms)
clock cycles
15 MHz
0.57
1.03

8.5k
15k

20 MHz
0.43
0.77

$I/tJm")~fr'1fflJ!~ AT P. :a-~*

i- ~ ~~,tI~r'i' I: J;. -'j ~  Bi' and (Bd = Aj is written in the
chain label information table when Ai < Bj. As a
result, temporary labels AO and BO are connected
with each other on the chain label information
table through Ai and Bj connectivity. By applying
these operations to all label linkage information
in the linkage information buffer, every temporary
label either has connectivity with only one
smaller-numbered temporary label, or has no
connectivity with smaller-numbered temporary
labels.

(1) k <-- 0

(2) m, n <-- LIB(k)
(3) if (m) ot 0 then m <-- (m) and go to (3)
(4) if (n) ot 0 then n <-- (n) and go to (4)
(5) if m < n then (n) <-- m
else if n < m then (m) <-- n
(6) k <-- k + 1

(7) if k-'

m

'<

NoteS

TI

OOACT'"

(J1

Note 1: When VEN* changes level, VCASO* changes to the same level five clock cycles later.
Note 2: If either VEN* or HEN* is not low (that is, if the Sketch chip is not perfoming average value reduction processing), data is output from 1D to 00
five clock cycles after the data is input.
Note 3: If either VEN* or HEN* is not low (that is, if the Sketch chip is not performing average value reduction processing), ODACf* outputs the input value
of ACASI* five clock cycles after the value is input. If Sketch is processing, ODACf* outputs a low during cycles in which valid data is output to 00,
and a high otherwise.
Note 4: If VEN* and HEN* both go low, Sketch immediately starts (or continues) average value reduction processing.
Note 5: If the number of pixels in the horizontal direction exceeds 512, Sketch suspends average value reduction processing, outputs data from ID to OD five
clock cycles after the data is input, and pulls HCASO* low. If multiple Sketch devices are cascaded, the next Sketch stage is activated and starts processing.
Note 6: If HCASO* is low when HEN* goes high, HCASO* also goes high five clock cycles later.
Note 7: HEN* must be deasserted (kept inactive) for at least three clock cycles.

Note: Asterisks (*) after the signal names denote that these signals use negative logic (active low).

~1iI
Image IP90C15
Data Reduction
Processor~y ~veraging . _

==r-

3

::s

CQ

0)

~

3'

I»

ea
CD

o

!....

CLK

3'

3'
ea

100t07

YEN'

HM' ~~______________~!
ACASI*

Ftve c1ock-cycles (Note 1)

Five clock-cycles (Note 1)

ODOI07*

~

0\

VCASO·

HCASO'

ODACI"

____________________~,__IIr----------------N-ote~2\

Note 1:

If the local area size isj x k, OD{O,O)

Note 2 ,L _-+______________

=DD{x, y)l2d is output five clock cycles after lOG-I, k-l) is input (d is the divisor set to the DlV register).
x=O-}l

y=O-k-1

After the above, valid data for this line is output to OD every j clock cycles. The same operation is performed for alI n x k-J th lines
(n is a positive integer).
Note 2:

During average value reduction processing, ODACT* is low during cycles in which valid data is output to OD, and is high otherwise.

Note:

The asterisks (*) after the signal names denote that these signals use negative logic (active low).

Section 7: Electrical Characteristics
7.1

Absolute Maximum Ratings
(Referenced to GND, Ta

= 25

D

C unless otherwise specified)

Parameter

Symbol
Vdd

-0.3 to 6.5

V

VIN

-0.3 to Vdd + 0.3

V

Operating temperature

TOPT

o to 70

DC

Storage temperature

TSTG

-10 to

Recommended Operating Conditions (Ta
Parameter

Symbol

Power-supply voltage

Condition

VIH

Low level

VIL

Min.

Typ.

Max.

Unit

4.75

5.0

5.25

V

0

Vdd

V

2.2

Vdd

V

normal input

0

O.S

V

VI

High
level

DC

so

=0 to 70°C)

Vdd

Range
Input voltage

7.3

Unit

Input/Output voltage

DC supply voltage

7.2

Rating

TTL level

Input rising time

TRI

TTL level

0

200

ns

Input falling time

TFI

normal input

0

200

ns

Input/Output Capacitance
Parameter
Input capacitance
Output capacitance
Note 1:

Symbol
CIN
COUT

Condition

Typ.

Unit

Any input (Note 1)

10

pF

Any output

10

pF

Does not apply to bidirectional buffers.

F-17

7.4

DC Characteristics
Vdd = 5 V±5%
Ta = 0 to 70°C
GND=OV
Symbol

Parameter

VIL

Low-level input voltage

VIH

High-level voltage

2.0

lIN

Input Without pull-up resistor
VIN = Vdd or GND
current Without pull-down resistor

-10

With pull-down resistor

Condition

Min.

V
V

±1

10

~

VIN = Vdd

35

110

335

~

-115

-350

~

4.5

VIN =GND

VOH

High level output voltage

IOH =-4mA

2.4

VOL

Low level output voltage

IOL = 4mA

IOZ

Off-state leakage current

VOH = Vdd or GND

lOS

Output short-circuit current
(Note 1)

Note 1:

Max. Unit
0.8

-35

With pull-up resistor

Typ.

V

0.2

0.4

V

-10

±l

10

~

Vdd = Max,Vo=Vdd

15

50

130

rnA

Vdd = Max, Vo = 0 V

-5

-25

-100

rnA

lOS designates current that flows out when the output is shorted to GND in a high state.
However, simultaneous shorting of two or more outputs is not allowed. Shorting time is
one second or less.

F-18

7.5

AC Characteristics

CPU Interface
Read Cycle
ADOtol
CS*----J

RD*

~--tAR ---1~

'------~

DB 0 to 3

unit: ns
Symbol

Min.

Typ.

Max.

AD and CS* setup times to RD* falling

Parameter

tAR

AD and CS* hold times to RD* rising

tRA

-

20
15

RD* pulse width

tRP

Delay time from RD* falling to DB enable

tRD

Delay time from RD* rising to DB disabled (Hi-Z)

tDF

5
0
30
5
3

.

tWA--.

-

Write Cycle
ADOto 1
CS*

"xl

..-

tAW

"

twp

~

K

WR*
DB Oto 3

>C

)<

-

tow

~

....

tWD--'

unit: ns
Parameter

Symbol

Min.

Typ.

AD and CS* setup times to WR* falling

tAW
tWA

WR* pulse width

twp

DB setup time to WR* rising

tDW

DB hold time to WR* rising

tWD

5
0
30
15
0

-

AD and CS* hold times to WR* rising

F-19

Max.

-

-

-

-

-

-

-

-

-

Image Data Input

CLK

ID
Oto7
tVES

tVEH

tHES

tHEH

tCIS

tCIH

VEN*

HEN*

ACASI*

unit: ns
Parameter

Symbol

CLK cycle

Max.

Min.

Typ.

-

-

tcc

25

High level period of CLK

tCPH

10

Low level period of CLK

tCPL

10

ID setup time to CLK rise

tIDS

8

-

-

ID hold time to CLK rise

tIDH

5

-

-

VEN* low setup time to CLK rise

tYES

8

-

VEN* low hold time to CLK rise

tYEH

5

-

-

HEN* low setup time to CLK rise

tHES

8

-

-

HEN* low hold time to CLK rise

-

-

tHEH

5

ACASI* low setup time to CLK rise

tCIS

8

ACASI* low hold time to CLK rise

tCIH

5

F-20

Image Data Output

CLK

OD Oto 15

VCASO*

HCASO*

ODACT*

ODOE

unit: ns
Symbol

Min.

Typ.

Max.

Delay time from CLK rise to OD enabled

tODD

-

-

20

OD hold time to CLK rise

Parameter

tODH

5

-

-

Delay time from CLK rise to VCASO* low

tvCLD

-

-

20

Delay time from CLK rise to VCASO* high

tVCHD

-

-

20

Delay time from CLK rise to HCASO* low

tHCLD

-

-

20

Delay time from CLK rise to HCASO* high

tHCHD

-

-

20

Delay time from CLK rise to ODACT* low

tOALD

-

-

20

Delay time from CLK rise to ODACT* high

tOAHD

-

-

20

Delay time from ODOE* rise to OD disabled (Hi-Z)

tODDZ

-

-

15

Delay time from ODOE* fall to OD enabled

tODZD

-

-

15

F-21

Reset Timing

eLK

RST*

The reset signal must be held active for at least 3 clock cycles.

Parameter
RST* pulse width (low period)

F-22

Symbol

Min.

tR5W

3

Um't [1
e oe k eye1es1
Max.
Typ.

-

-

Section 8: Sample Applications
8.1

Applied Images
1.

Multimedia: High-speed display similar to strobe photography.

2.

Security: Simultaneously displaying a large number of monitoring camera shots on a screen.

3. FA: Comparing actual products with good products during an in-process
inspection.

Products to be inspected

Good products or
standard samples

Inspection spot 1

Inspection spot 2

F-23

8.2

Division Operation Using External ROM
The Sketch chip allows the height and width of a local area to be independently set to any value
from 1 to 16. For example, if the width of the local area is set to 5 (LH = 4) and the height to 3
(VL = 2), the number of pixels in this local area is 5 x 3 = 15. However, because average values are
calculated using a shift operation, the divisor is limited to integral powers of 2. This means that
in the above case, the device could not produce an exact average value reduction image.
For applications that can tolerate some degree of error and so do not require precise average value
compressed image output, the divisor 24 = 16 (DIV = 4) could be used as an alternative in the
above example.
If applications require an exact average value reduction image, use a ROM conversion table like
the one shown below to perform the division operation.

In this case, the divisor is left set to 1 (DIV = 0) so that the OD pin outputs the sum of the gray
level values of the pixels in the local area. This output is sent to a given ROM address, where it
is divided by the specified divisor and output to ROM data. The ROM output data thus contains
the results of dividing the address data by the specified divisor.
The disadvantage of this method is that the divisor is a fixed value. If multiple divisors are
required, use a ROM of a capacity that can accommodate multiple conversion tables, and pins
above A16 for selecting the divisor.

Sketch

8 bit

16 bit

ADR

OD

----:f--. . ID

Vertical enable

- - - - - 1 M VEN*

Average value
reduction 8-bit
image output

512-KbROM

8-bit grayscale
image input
8 bit

0

PIP f - - - " ,

CS*
OE*

VCASO*

Horizontal enable

- - - - - 1 M HEN*

VDD

HCASO*

' - - - - - ; ACASI*

FIF r - - - - - - - - - - l - - . J PIF 1-----.

ODACT*

r----IODOE*

CLK
Image
data
clock

AD, RD*, CS*
DB,WR*, RST*

CPU bus

Note:

Average value
reduction 8-bit
image output
enable

An asterisk (*) after the signal name indicates inverse logic (active low).

F-24

8.3

Sample Configuration for Data Width Expansion (16 Bits)
The diagram below shows an example of data width expansion using a parallel processing
configuration. A single Sketch device limits the data width of the processed image to 256 gray
levels (8 bits). The Sketch device can also output in 16 bits the sum of gray levels of an 8-bit input
image in a unit area, without omitting any bit. This capability divides the image input into units
of 8 bits, sums the gray levels in each unit using multiple Sketch devices, then uses an external
adder to expand the required gray level portion to any desired data width. This provides greater
flexibility in handling the complicated summing operation in unit areas by average value
compression processing. Furthermore, a division calculation to obtain average values can then be
done by dropping the required number of bits from the MSB portion of the data. ROM-based table
conversion is recommended for division operations that use arbitrary divisors.
The figure below shows an example of data width doubling (to 16 bits) using two Sketch devices.

16-bit grayscale
image input
16 bit

8-bit grayscale
image input

Average value reduction
image output

8 highorder bits

16 bit
0D15-0 I-+.....~

ID7-0

VEN*
8 low-order bits

Processing of 8
high-order bits

HEN*
CLK

Sketch #1

8 high-order bits

16 bit
8 low-order bits
0D15-0 1--1-....1--+------1

ID7-0

Vertical enable
Horizontal enable
Image
data clock

VEN* Processing of 8
low-order bits
HEN*
CLK

Sketch #0

CS*
RD*
Common control bus AD DB WR* RST*
Address bus
Data bus
Control bus
System reset
Note:

.. J~ .4~

J~

An asterisk (*) after the signal name indicates inverse logic (active low).

F-25

8.4

Sample Extraction of Average Value Without Designating a Rectangular
Processing Area

CLK

ID

HEN"', VEN'"

OD
ODACT*
VCASO'
HCASO*

Register Setting Values:
LH = 3h, LV =Oh, DIV = 2h
Note 1: OD(O)={ID(O)+ID(I) ... +1D(3»)!4

The above example shows signal timing in a situation in which the average value is extracted
from four data groups input in sequence from the ID signaL Processing is executed using a local area
setting of 1 x 4 pixels. By setting the local area to 1 x n pixels (where n is the value of register LH
plus one, and register LV = 0), the processing area is viewed not as a rectangle but as a line, and
the vertical and horizontal enable signals VEN* and HEN* no longer need to designate a
rectangular area for processing, Thus, while both VEN* and HEN* are at low level, average
values are extracted from every group of data input in sequence from the ID signal, the size of
each group being determined by the value of the LH register plus one. The number of data values
taken for averaging is then determined by the setting range of the LH register plus one, and so can
range from 1 to 16.
Also, after both YEN* and HEN* go low, once the number of data values input from the ID signal
exceeds 512 x n (where n = the value of the LH register plus one), the Sketch chip stops processing.
To continue processing at this point, set VEN* and HEN* high again, then change them back to
low to restart the process.

F-26

SMIASSP
Image Processing LSI Series

IP90C18
Features Extracting Processor (Feature)
Sumitomo Metal Industries, Ltd.
Technical Manual Ver. E 1.1

I

I

mil

•

Sumitomo Metal Industries, Ltd.

Table of Contents
Section 1:
1.1

1.2

Section 2:
2.1
2.2
2.3
2.4
2.5
2.6

2.7
2.8
2.9
2.10

Section 3:
3.1
3.2

3.3

Section 4:
4.1
4.2

4.3
4.4
4.5

4.6

Section 5:
5.1
5.2
5.3

Features and Functions
Overview of Product Functions ........................................................................ .
Features and General Specifications ................................................................ .

1
4

Measurement Processing Algorithms
Cumulative Summation by Area (Grayscale-Weighted Surface Area
Measurement) ............................................................................................... .
Pixel Count Measurement (Histogram Measurement) .......................................... .
Measurement of Diagonal Axis of a Circumscribed Rectangle .............................. .
Area Boundary One-Point Coordinate Measurement .......................................... ..
Perimeter Measurement by Area ................................................. '" ................. .
Run Coordinate Detection .............................................................................. .
Measuring Moments ....................................................................................... .
Grayscale Projection Processing (Peripheral Distribution Measurement)
Algorithms ............................................................................ , ..................... .
Table Conversion (LUT) Processing .................................................................. .
Cumulative Histogram Processing ................................................................... .

11

13
16
17
18
26

27
32

33
34

Pin Functions
Pin Lists and Function Descriptions ................................................................ ..
Pin Assignments ............................................................................................ .
Pin Placement Diagram ................................................................................. .

35
38

39

Sample System Configuration and Operation
Sample Configuration: Basic System .............................................................. ..
Operating Description ................................................................................... .
Sample Configuration: Expanded System.". . . " .......................................... ..
Operating Timing Charts.... .................. ..........................................................
Processing on the Area of Interest Boundary ......................................................
Setup Sequences.............................................................................................

41
42
48
57
60

64

Internal Configuration
Internal Block Diagram................................ ..................................................
External Signal Connections and LSI Internal Connections for Each Type
of Processing ................................ . ... . .. . .. . . . . . . . .. . ... . . .. . . . . . .. . . .. . ... . . . .. . .. . . . . . . . . .. . .. . .
Sample Register Settings for Each Measurement ................................................

G-i

67
68

70

Section 6:
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19

Section 7:
7.1

Section 8:
8.1
8.2
8.3
8.4
8.5

Address Maps And Registers
Address Map and Register List.. .................................................................... ..
Execute Register ........................................................................................... .
Reset Register .............................................................................................. .
Mode Register .............................................................................................. .
Area Extension Mode Register ....................................................................... ..
Results Memory Address Selection Register ...................................................... .
Results Memory Data Selection Register .......................................................... .
Adder Selection Register ............................................................................... .
Input/Output Control Register ....................................................................... ..
Overflow Status Register ............................................................................... .
Overflow Flag Mask Register ......................................................................... .
Results Memory Clear Register ....................................................................... .
Field Count Control Register .......................................................................... .
Constant Register.......................................................................................... .
Origin Area Number Register ......................................................................... .
LSI Internal Test Registers ............................................................................ ..
Results Memory Address Maps ....................................................................... .
Results Data Storage Formats ....................................................................... ..
Detailed Sample Address Maps for Measurement Results Data .......................... ..

91
92
94
95
98
100
101
102
103
104
105
107
108
109
109
110
110
112
113

External Dimensions
160-pin Plastic QFP Package .......................................................................... .

121

all
0I:i

C

Electrical Characteristics

:jj

Absolute Maximum Ratings ............................................................................ .
Recommended Operating Conditions ................................................................ .
Input/Output Pin Capacitance ........................................................................ .
DC Characteristics ....................................................................................... .
AC Characteristics ....................................................................................... .

G-ii

122
122
122
123
124

co

~

1-1

o~~
o~OJ
en
i5
rf}

0. ~
-.ep..
1-1

oJ
OJ

~

Section 9:
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11

Sample Applications and Reference Materials
Detecting Defective or Missing Objects Using Binary Image Area Measurement ......
Surface Area Measurement of Labeled Images.................... ................................
Data Analysis by Histogram (Histogram Measurement of Non-Image Data)..........
Detecting Missing or Misaligned Objects by Cumulative Addition
Processing of Separate Areas...........................................................................
Dumping the Contents of Results Memory...... ....................................................
Perimeter Measurements ................................ .................................................
Measuring Roundness ................... ............. ....................... .......................... .....
Grayscale Projection Processing ............ ........... ......... ............................... .........
Compensation of Moment Characteristics for Screen Partition
or Origin Movement................................ .......................................................
Maximum Values For Which Moment Characteristics Can Be Derived .................
Sample Circuit (Labeling Processing + Feature Extraction Processing)
IP90C51 + IP90ClO + IP90C18 ........ ........................ .............. .................. ..........

131
132
133
134
135
136
137
138
139
141
144

Section 10: Guidelines for Avoiding Overheating
10.1

Guidelines for Avoiding Overheating...............................................................

145

Appendix A: Reference Bibliography
A.1

Reference Bibliography................................ ..................................................

Appendix B:
B.1

146

Handling CMOS LSI Devices

Precautions ................................ ...................................................................

G-iii

147

Section 1: Features and Functions
1.1

Overview of Product Functions
The IP90C18 feature extraction ("Feature") chip can perform the following processes in real time.
The processes performed are selected by register settings.
•

Cumulative addition processing by area
Weighted area measurement using 12-bit grayscale values (0-4095) for multiple areas (4096 or
2048 labeled areas).

•

Histogram processing
Grayscale histogram measurement (distribution of frequency of occurrence) of input in 12-bit
grayscale resolution (values 0-4095). Uses the input value from cumulative grayscale addition
processing as a constant for each area. Suitable for grayscale histogram measurement in
applications requiring high precision, such as medical imaging devices. Also performs pixel
count (area) measurement of up to 4096 separate labeled areas using 12-bit labeled image input.

•

Diagonal coordinate measurement of circumscribed rectangles
Measures the diagonal coordinates of rectangles circumscribed around all labeled areas (up to
4096 or 2048 labeled areas).

•

Perimeter measurement
Measures the perimeter for each of up to 2047 labeled areas in a labeled image, in vertical,
horizontal, and diagonal directions. Suitable for evaluating complexity of shapes, roundness,
etc. Also operates in extended perimeter measurement mode, in which it measures only one of
the three elements for up to 4095 labeled areas. Functions with either 8-connection or 4connection labeling logic.

•

Area boundary one-point coordinate measurement
Measures the coordinates of the first pixel input on the boundary of a given area in a raster
scan image. Suitable for measuring starting points for image-processing functions that use
software for boundary tracking.

•

Run coordinate detection
Detects the coordinates of each end of a run, and outputs these coordinate along with signals
indicating the start and end points of runs in the direction of the raster scan.

•

Primary moment measurement
Calculates Lh. d(h, v) or LV' d(h, v) for each of up to 2048 labeled areas (where d(h, v) = 0 or
1, and all areas can be handled as binary images). These results, together with the above
histogram measurement (surface area measurement), can be used as input for an external CPU to
make center-of-gravity calculations for each labeled area.

G-l

•

Secondary moment measurement
Calculates Lh. h. d(h, v), Lh.v. d(h, v), or LV. v.d (h, v) for each of up to 2048 labeled areas
(where d(h, v) = 0 or 1, and all areas can be treated as binary images). These results, together
with the above histogram measurement (surface area measurement) and primary moment
measurement functions, can be used as input to an external CPU to calculate the angle of the
principal axis of each labeled area.
H-axis, V-axis grayscale projection processing
12-bit grayscale projection processing (perimeter distribution measurement) on large areas up to
2048 x 2048 pixels for two-axis simultaneous processing, or 4096 x 4096 pixels for one-axis
processing.

•

Cumulative grayscale histogram processing
After grayscale histogram processing, converts the histogram results into cumulative histogram
data.

•

Table conversion (LUT: Look-up table) function
The internal high-speed memory can perform 12-bit table conversions of area numbers or
grayscale data values.

The table on the following page lists the quantitative measurements the IP90C18 chip can make
from grayscale or labeled image data.

G-2

Quantitative Features and Measurement Algorithms
Feature

Symbol

Grayscale value histogram
Surface area measurement
(zero-degree moment)
Grayscale-weighted surface
area measurement

Diagonal coordinate
measurement of
circumscribed
rectangle
(Ferrer axis)

Lower
left
Upper
right

Perimeter

One-point boundary coordinate
measurement
Run coordinate detection

Primary moment

H

Value measured, extraction method, etc.
Measures how often each grayscale value occurs.

Counts the number of pixels of each area (label) number.
Histogram processing indicates the size of each area.
Calculates the total of grayscale values of pixels for each
Sw
area (label) number. Cumulative addition of grayscale
values f 216, or a maximum of 65K
pixels. In this case, therefore, the input image size can be up to 4096 pixels (measurement
direction length or projection axis length) x 65K pixels (projection pixel count or projection
direction length) without overflow.

G-7

[One-axis projection mode (2K area measurement mode)]
This mode performs grayscale projection on the H-axis or V-axis. The entire 96 Kbits of results
memory can be used to store the results of projection processing on one axis. By using a results
memory configuration of 2048 words x 48 bits/word, measurement capability is extended to
projection values of up to 48 bits for each of 2048 pixel values.
•

Maximum processing screen size: 2048 pixels in the direction measured
If the grayscale input uses the maximum bus width of 12 bits (4096 gradient values), the
maximum number of pixels (depth) in the summation process is only limited by the condition
(2 48 _1)/{2 12_1) > 236 pixels, and therefore the maximum is on the order of 64G pixels. In
addition, with the commonly used 8-bit (256-gradient value) grayscale input, the maximum
number of pixels (depth) is increased to (248_1)/(2 8-1) > 240, or a maximum of 1 trillion pixels,
enough to prevent overflow in virtually any application. Note that at 40 MHz the amount of
time required to input 2048 x 1T pixels is (2 x 103 x 1012)/(40 x 106 ) = 5 x 107 seconds, which is
equivalent to 575 days, or roughly
1-1/2 years of continuous measurement.

•

Maximum operating frequency limitations
To prevent excessive power use and resulting high temperatures from affecting reliability,
keep the maximum operating frequency at or below 25 MHz when using one-axis projection
mode with 2K area measurement mode and projection on the H-axis only.

o Table Conversion (Look-Up Table) Function
The IP90C18 chip's internal memory (in 4096 x 24 bits/word configuration) can be used for look-up
table (LUT) conversion. The grayscale input signal pins (IDO-ID11) or the area number input signal
pins (LO-L11) can be used to identify addresses in results memory, and the read-out data can be
output from the image output signal pins (ODO-OD23). This configuration can also be used to dump
the contents of results memory.
1.
First, values previously assigned to corresponding 12-bit (4096-value) input values are written
from the CPU interface (DBO-DB23). This enables the values stored in the corresponding
addresses to be output from the image data output pins (ODO-OD23). This function is used in
compensation of grayscale input values, conversion of area (label) numbers, and computations
involving one-to-one input/output functions (square root, 2/3, shift calculation, code extension,
etc.).
2. Following the end of a separate calculation process, the values stored in results memory can be
dumped as output from the image data output pins (ODO-OD23). Alternatively, the results
can be used as they are as conversion coefficients in a conversion table: this could provide a
memory table of compensation coefficients for use with line sensor data.
•
•

Input data (grayscale or label values) width: 12 bits (0-4095 gradients or area numbers)
Output data width: 24 bits (16.7 M values)

G-8

1.2.2 Peripheral Functions
In addition to the functions described in Section 1.2.1, "Overview of Image-Processing Functions,"
the IP90C18 Feature chip provides a number of peripheral functions designed to facilitate imageprocessing measurements. This section describes these peripheral functions.

o Cumulative Histogram Processing Function
•
•

•

The internal addresses of results memory are connected to the internal counter (up/down
counter), and selected sequentially.
The data from each selected address is added to the data from that address on subsequent
cycles, so that data values are cumulatively increased at each address. At the end of the
process, the contents of results memory represent a cumulative frequency-of-occurrence
distribution pattern.
The range of cumulative addition is:
4K area measurement mode: 0--4095
2K area measurement mode: 0-2047

•

Automatic execution from histogram measurement
Automatic cumulative histogram measurement can begin automatically when histogram
measurement processing is complete.

•

Power-saving cumulative histogram mode
If 2K area measurement mode is used at clock (iCLK) frequencies greater than 25 MHz,
excessive power use and the resulting high temperatures can damage the chip. To avoid this,
write 1 to the power-saving cumulative histogram mode flag in the mode register (MOD): this
flag reduces processing speed by half, thereby reducing power consumption by approximately
half and preventing damage to the chip.

o Processing Field Count Control Function
Processing field count controls are designed to automatically stop processing after a designated
number of fields (input screens) have been processed. This function uses an 8-bit counter, and can
designate any number of fields from 1 to 255.
This function can be set to stop automatically after n fields (n
continuous execution until 0 is written to the exec flag.

= 1 to 255) are

measured, or to allow

o Pixel-by-Pixel Data Enable Function (Pixel Control)
The data enable control pin (IDEN*) can control whether each individual pixel is included in
measurement. Because the coordinate counter does not stop, this function can extend the data width
of the area measured. For details, see Section 4.3, "Sample Configuration: Extended Systems."

o One-Shot Memory Clear Function
Results memory must always be cleared before executing the next measurement. The IP90C18 chip
can clear all bits in results memory at once (in 1 /-!s) by means of a setting in the memory clear
register.

G-9

o Background Designation Function
Perimeter measurement and run coordinate detection differ from other feature extraction processes
in that they require a background area number to be designated. Area boundaries are recognized by

using the number 0 to represent background area.
The data enable control signals (IDEN* and DIDEN*) can designate background area on a pixel-bypixel basis. IDEN* designates background for signal pins L<11..0>, and DIDEN* designates
background for signal pins DL<11..0>.

o Overflow Flag Function for Cumulative Addition by Area, or for Grayscale Histogram Values
A selection of register settings is available to use either the MSB of the results memory data
value or an overflow flag. If the overflow flag function is used, the width of the data in results
memory is decreased by 1 bit.

o Vertical Enable Signal (VEN*) Enabled by the FEN* Function
This signal serves as an internal enable/disable control for the vertical enable signal (VEN*) on a
field-by-field basis, synchronizes multiple processing circuits (LSIs) with the field signal, and
selects the field in which to start processing.

o External Interface
•

•
•
•

•

Allows status output to the CPU:
1) Busy status output (BUSY*)
2) Overflow output (OVF*)
Cumulative addition, area overflow.
Can be used to mask the overflow signal (OVF*) from any or all overflow sources (use with
CPU-side interrupt control).
Allows the CPU to verify execution status, overflow source, etc. by reading the appropriate
registers.
Allows direct connection to an 8/16/24(32)-bit CPU bus.
Note that because the Feature chip has a bus width of 24 bits, connection to a 32-bit bus
interface requires that the highest 8 bits be pulled up or otherwise protected on the external
interface side.
Input/output interface level: TTL level compatible

o Low Power Demand
CMOS process technology

o Power Supply
+5V single source

o Package
160-pin plastic QFP

G-IO

Section 2: Measurement Processing Algorithms
2.1

Cumulative Summation by Area (Grayscale-Weighted Surface Area
Measurement)
•

•
•

This function uses number input (L<11..0» to measure the cumulative sum of grayscale data
values (ID<11..0» for each designated area (cumulative addition processing). The result is the
zero-degree moment of an area expressed in grayscale values.
Performing cumulative summation of values for each area makes it possible to derive a
grayscale-weighted surface area measurement.
Summation by area is the Feature chip's most basic function. The first step in this process is to
clear all values in results memory to 0 using the memory clear function. The chip then reads
the value at each memory address designated by the area number input signal L<11..0>, adds
the grayscale data input value ID<11..0>, and stores the result at the same address. This
process is illustrated below.

Note:

The diagram below is intended only as a basic illustration of the process described
above, and does not accurately represent all operations or timing of the Feature chip. For
details about functions or timing, see the appropriate sections of this manual.

Area number input
L<1l..0>

Read data
Din

Write data
Grayscale value input
ID

Adder

G-U

2.1.1
•
•

Basic Applications of Summation by Area
Calculates the sum of grayscale values for each pixel in any given area. This provides basic
data for measuring the surface area of objects, as well as determining the location of an object.
Example 1: Starting with an image that has been labeled by linked component labeling, the
input data (which consists of image area numbers and corresponding grayscale values) is used
to calculate the sum of grayscale values for each separate area number.
This enables the grayscale-weighted surface area to be calculated for each area.

•

Example 2: Area numbers are read sequentially from values previously stored in frame memory,
and the sum of grayscale values is calculated for each area number.
This enables simple pattern matching processes.

Designated area within frame memory
Area Parameter Table (APT)

area 1:

sum =198

area 5:

sum =764

66
66
38

o
o

G-12

2.2

Pixel Count Measurement (Histogram Measurement)
Histogram measurement processing is an application of the Feature chip's most fundamental
process: summation by area. Figure A below illustrates how the Feature chip measures the
frequency of occurrence of grayscale values (histogram measurement). The first step is to clear all
values in results memory to 0 using the memory clear function. The chip then reads the value at
each memory address designated by the grayscale value input signal ID<11..0>, adds a constant
(normally 1), and stores the result at the same address. Grayscale histogram measurement can be
performed by processing a single screen of grayscale image input.
Measuring pixel count (surface area) by area can also be thought of as a frequency-of-occurrence
distribution of area numbers. This process is illustrated in Figure B, below. Again, the first step is
to clear results memory using the memory clear function, then to read the value at each memory
address designated by the area number input signal L, add a constant (normally 1), and
store the result at the same address. Measuring pixel count by area can be performed by processing
a single screen of labeled (area number) image input.
Note:

The diagrams below are intended only as basic illustrations of the processes described
above, and do not accurately represent all operations or timing of the Feature chip. For
details about functions or timing, see the appropriate sections of this manual.
Read data
Results memory
Grayscale input
I"'D-<..!.I-I-..-:-0->-'---~ Address
Dout
Write data

Din

Constant register

(CONST)

Figure A: Grayscale Histogram Measurement

Read data
Results memory
Area number input

L<11..0>

Address
Dout

Write data

Din

Constant register

(CONST)

Figure B: Labeled Image Surface Area Measurement

G-13

2.2.1 Grayscale Histogram Processing
The Feature chip's grayscale histogram process can measure how often 4096 separate grayscale
values occur on an input screen. The chip measures grayscale values input through the grayscale
value input signal ID<11..0>. By changing register settings, this process can also count values input
on the L<11..0> input signal.
Image bus
12-bit

J
[

Histogram module

Measurement
results

I

A(O)
A(1)
A(2)
212 entries: 4096 grayscale gradients
A( n): Frequency of occurence of grayscale
value n in the image
A(212_1)


The grayscale histogram process can quantify the grayscale value composition of images for such
applications as image-quality compensation or enhancement, or for binary conversion.
Pixel

Threshold value is set here
to produce a clear extraction
of the image at left

light

Subject image (grayscale)

Grayscale gradient value

G-14

2.2.2

Histogram Processing of Area Numbers

The Feature chip can calculate how often each of 4096 separate area numbers occurs in an input
screen. The chip measures area numbers input through the area number input signal L<11..0>.
Counting area number values for each numbered area can be considered equivalent to measuring its
surface area. This is also the same process used to calculate the zero-degree moment of an area. By
changing register settings, this process can also count values input on the ID<11..0> input signal.
Histogram Processing Example
Result of measurement

Input area number image
(labeled image)
0 5 0 5
0 0 5 5
0 0 0 5
o 0 0 0
011 0 0
011 0 0

0
0
0
0
0
0

0
0
0
0
0
0

0 o 0
0 9 0
o 9 0
9 0 0
9 9 0
000

0
0
0
0
0
0

Area no.

Pixel count

0

48

I

/'
/'0

lJ

:/'lJ

/ ' lJ

/'or-"

"'r-"

I

5

5

6

0

7

0

8

0

9

5

10

0

11

2

I

/'J

G-1S

:

/......J

/'lJ

2.3

Measurement of Diagonal Axis of a Circumscribed Rectangle
(Feret's Diameter)
This process can measure specific areas existing within a given area within an image, calculate
the approximate location of a given area, and obtain basic data about specific areas of interest
(AOls) within an image. The process circumscribes a rectangle around each given area, measures
the coordinates of the lower left and upper right corners of the rectangle, and stores the results in
memory. Each pixel within the area can then be identified as a pair of horizontal and vertical
coordinate values. The process thus gives four values for each area measured: P(HO, VOl,
P(HI, VI), Hf, and Vf.

o ~ 0 0 0 0 0 0 0 0 ~P(H1, VI)
--~-1-~-~-~-1-1-1-~-1-1-~-1-o &0 003 3 3 3 3 0

!

! oj

OQl30330333QlO
oo 3
3 0 3 3 0 0 3 3
0 Vf
33000330
33303333
o Ql 3 033 3 3 0 0 Ql 0

o

--~-~-~-~-~-~-~-~-~-~-1-~Hf
..

P(HO, VOl ..
I

--

I

This process measures the coordinates of the lower left corner P(HO, VOl and upper right corner
P(HI, VI) of the rectangle around each area. The horizontal Ferrer axis (Hf) and vertical Ferrer
axis (Vf) are computed separately using these diagonal coordinates.
This process can measure the coordinates of the diagonal vertices of the circumscribed rectangle for
each area in the image in two ways: measuring the coordinates of the lower left and upper right
vertices simultaneously, or measuring the coordinates of either vertex by itself.
[Measuring lower left and upper right coordinates simultaneously: 2K area measurement mode)
Simultaneously measures the coordinates of the lower left and upper right vertices of the
circumscribed rectangle about each area.
•
•

Number of areas (label values):
Maximum size of area measured:

2048 (0-2047)
4096 x 4096 pixels (coordinate values to I2-bit width)

[Measuring the lower left or upper right coordinates alone: 4K area measurement mode)
Measures the coordinates of either the lower left or upper right vertex of the circumscribed
rectangle about each area.
Number of areas (label values):
4096 (0-4095)
• Maximum size of area measured: Either height or width of 4096 pixels (coordinate values to
12-bit width)

G-16

2.4

Area Boundary One-Point Coordinate Measurement
This process measures the coordinates of pixels that fall on the boundary between background and
area data values of each area. Using a raster-scan input image, the process measures the
coordinates of the first pixel input with each given area number (label value), and writes the
results to memory. In addition, the process stores the area number of the pixel in the origin (0, 0)
(at the upper left corner of the input image) in the origin area number register (LBLOO).
By using this process to detect the coordinates of one pixel on the boundary of each area, the chip
obtains a starting point for CPU processing using boundary tracking algorithms without having to
scan the image. Image processing involves a wide variety of processing algorithms, using a
different algorithm for practically every application. When the CPU or DSP accesses frame
memory to search an image, such a load is placed on the system that nearly all the time required
for image processing is consumed in accessing memory. The Feature chip reduces this load by
offering functions such as the area boundary one-point coordinate measurement described here, the
measurement of the diagonal axis of circumscribed rectangles described previously, and the run
coordinate detection function described later. These functions reduce the load on the CPU or DSP,
and enable the CPU to focus on the essential problems of image recognition and decision processing.
Example:

Input area number image (labeled image)
Horizontal coordinate

o
"

t;;

0

'6'"
I..;

0
0

u

'"

.€u
:>" 5

5

10

4 0 0 5 0 0 0 o 0 0
4 0 5 5 5 0 0 9 0 0
0 0 0 5 0 0 0 9 0 0
0 0 0 0 0 0 9 0 0 0
0 0 0 0 0 0 9 9 0 0
0 0 0 0 0 0 0 0 0 0

iii

One-point coordinate measurement by area (area start point coordinates)
Measurement result:
start point coordinates

R

Area no.

V

4

0

0

5

3

0

9

7

1

Value in origin area number register (LBLOO): 04h

G-17

2.4.1 Images Subject to Diagonal Axis of Circumscribed Rectangle, and Area
Boundary One-Point Measurement
The following example illustrates the type of filled-in image that can be used in processes such as
measuring the diagonal axis of a circumscribed rectangle, or area boundary one-point measurement.
Labeled images are naturally suitable for this type of measurement. Whether the results of each
process are meaningful or not depends on the specific application; however, these procedures can
handle difficult situations such as the so-called "four-color problem," in which areas of four filledin images all come into contact at the same point with no background values present. They can also
process scattered areas such as the areas labeled 4 in the illustration below, by using a single
rectangle to circumscribe the two separate areas.
Sample image:

555
555 5
555 5
5 5 5 5
5 555
5 5 5 5
5 5 5 5
5 5 5 5
5 5 5 5
5 555
555 5
5 555
5 555
5 5 5 5
5 5 5 5

2.5

Perimeter Measurement by Area
This process examines 2 x 2-pixellocal areas of 8-way or 4-way connected raster scan images, and
applies the algorithms described below to combinations of local areas to measure the perimeter.
Perimeter measurements are made up from three separate measurements of vertical, horizontal,
and diagonal components, a breakdown that also aids in measuring aspect ratios.
Simplified example of a perimeter measurement:
determining the length of the perimeter of the
area at left with area number (label value ) 5.
Vertical:

4

Horizontal: 4
Diagonal:

4

Perimeter:

4 + 4 + 4~2 ~ 13.66

The above illustration shows how the perimeter of area number (label number) 5 would be
measured. All values outside this area are considered to be background (label number 0). The
aspect ratio is 1, and the measurement application assumes that diagonal distances are multiplied
by ~2. The Feature chip measures the perimeter in terms of three components: vertical, horizontal,
and diagonal. The CPU or DSP can then total the three components, as well as perform any
supplementary processing using aspect ratio, etc.

G-18

Note that the algorithm for this process determines a perimeter length of 0 for any area that
consists of only one pixel.
[Reference 1: 4-Way and 8-Way Connectedness Labeling]
The following is a general explanation of labeling processing with respect to image resolution and
measurement. (For details, consult a textbook on image processing.) Labeling (also called linked
component labeling) is the process of attaching a particular value to adjoining pixels so that
adjacent points can be seen as belonging to a continuous area. Labeling normally accepts binary
images as input, and outputs a labeled image with area numbers (label values) allocated to each
pixel on the screen.

4-connectedness labeling: search for
connections in 4 directions from the central
point

G-19

8-connectedness labeling: search for
connections in 8 directions from the central
point

Figure (A) below shows a binary image input for labeling processing. Figures (B) and (C) represent
the resulting output images.

· ............. 1. 1. .
· .............. 1. ..
...... 1. ...... 1.1..
· .... 111. ......... .
· ..... 1. .......... .

· ............. 1.2 ..
· .............. 3 .. .
· ..... 4 ....... 5.6 ..
· .... 444 .......... .
· ..... 4 ........... .

· ............. 1. 1. .
· .............. 1. ..
. ..... 2 ....... 1.1..

· ... 11. ...........
· ... 11. ...........
· ..... 11. .........
· ..... 11. .........

· ... 77 ............
· ... 77 ............
· ..... 88 ..........
· ..... 88 ..........

· ... 33 ............
· ... 33 ............
· ..... 33 ..........
· ..... 33 ..........

.
.
.
.

(A) Binary image before labeling

.
.
.
.

(B) Result of 4-connection
labeling

· .... 222 .......... .
· ..... 2 ........... .
.
.
.
.

(C) Result of 8-connection
labeling

[Reference 2: Treatment of Pixels1
Texts on the subject of image processing point out that there are two ways of defining the concept
of a pixel for use in digital image processing. One approach is to treat the pixel as a point at the
vertex of coordinates X and Y: that is, as having no area of its own. The other approach is to treat
the pixel as a minimum unit of planar space having a surface area defined as 1 because it exists
across a given unit of length along both the X and Y axes (an inter-pixel length). In discussing
feature extraction in this section, pixels are referred to as "point pixels" when treated as points,
and as "plane pixels" when treated as units of surface area.

Binary image viewed as pixel dots
in a lattice network

Binary image viewed as pixel planes
in a grid

G-20

Now consider an area one pixel in size and an area of four pixels in a 2 x 2 square configuration as
applied to measuring perimeters and surface areas. The diagrams below illustrate both cases
viewed as point pixels and also as plane pixels. The accompanying table indicates (with an "F")
which concepts the Feature chip uses in which measurement process.

Image of one pixel
in a point array

Image of one pixel
in a plane array

Subject image

Image of four
pixels in a point
array

Image of four
pixels in a plane
array

Four-pixel square

One pixel

Pixels viewed as:

Point

Plane

Point

Plane

Perimeter:

o (F)

4

4 (F)

8

0

1 (F)

1

4 (F)

Surface area (histogram):

The Feature chip uses point pixels to measure perimeters, and plane pixels to measure surface area
when calculating in terms of the frequency of occurrence of pixel values within a given area
(histogram measurement). In theory, all pixels (both point pixels and plane pixels) should be
treated identically; however, the difference between the point and plane concept is only
significant when dealing with extremely small areas, and in practice these small areas are most
frequently ignored when eliminating noise. Therefore, there are few if any problems with using
both concepts at the same time. Furthermore, no clear mathematical distinction has been made as
to the correctness of one concept or the other, and no particular problems are posed by using
whichever concept works best for realizing particular continuous (analog) phenomena in terms of
discrete mathematics (sampling values, digital values). For example, although the Feature chip
uses the point pixel concept for measuring, perimeter measurement could also be seen in terms of
plane pixels by thinking of the distance between the centers of plane pixels.

G-21

2.5.1 Algorithm for Perimeter Measurement of Images Labeled with 8-Way
Connection Labeling
The following section describes the algorithm used for perimeter measurement in raster-scan images
that have been labeled using 8-way connection labeling. This algorithm detects the boundary
between continuously labeled areas and the background by looking at 2 x 2-pixellocal areas, and
counts vertical, horizontal, and diagonal perimeter lengths independently.
Input data local area:

p3

p2

pI

pO

0

0

0

0

0

0

0

1

0

0

1

0

~
~
Local area
label data

Perimeter
V H D p3

tffij
o

0

0

0

EHB

0

0

0

tffij

0

BId

0

0

0

1

1

0

0

ffij
o
tBij

1

0

0

1

1

0

1

0

0

2

1

1

1

0

EHB

0

0

1

1

1

1

1

p2

pI

pO

1

0

0

0

0

1

0

0

1

0

0

1

0

1

0

0

0

0

1

1

0

1

1

0

1

0

1

1

0

o

0

1

0

1

0

1

1

0

0

0

1

1

1

*

0

0

0

0

2

1

0

0

0

0

1

0

1

0

0

0

1

0

0

1

0

0

0

•

•

0

*

*

tttE
tili3
8E
BE

0

o

o •
*

Perimeter
V H D

o

0

tHE

Local area
label data

0

*

0

*

tffij

rna
o •

ffij
ffij
*

0

•

•

0

*

Notes:
1)
2)
3)
4)

In the above table, whenever a given pixel Px (where x = 0 to 3) has the value 0, that pixel is considered
background. A 1 indicates a non-background value.
In the local areas in the above table, pixel values of 0 indicate that the pixel contains background. Pixels
marked with an asterisk (*) have non-background values.
Linked areas consisting of a single pixel have a perimeter of O.
If an area contains an enclosed "hole," the interior perimeter of the hole is included in the perimeter
calculation.
To find only the external perimeter, use this procedure: perform labeling using inverted binary image
data, then set all labels other than background to 0 before performing perimeter measurement.

G-22

2.5.2 Example: Perimeter Measurement of Images Labeled with 8-Way Connection
Labeling
Input Image

1

2-2-2~ ~2~

1

1

. ~f
1
.

1 1~
. 1

I
II
1 "'1
1
I 1 ""1 /11
1

1/1
. "" 1
I
1

I
1
I
1
I
1
11

I
1
I
1

1/1
11

-

1

12 "'2/2 "2/2
2
12 "2/2 2 2 2 2

-

1/.
1

3

-

13

31

13

31

13

1

-

I
1
I
1
I
1
I

4~'
~
. 4~.

3

2

2

. "" 2
12

2

2/

2

21

-

21
21

2 - 21

2

."" 2 - 2

I

I
1
I
1
I
1
I

2

~2;/ ~2/21

."'2/

."2 ""2

'~4

."21

31
5-5=5=5

I

5/'
5/5 1

1
11

5/5

7

II
7
II

'''1 1

7

15/'''51
15 ~5~51

8

6

II

51

6

6 ~~ 6

II

6~J

6

Measurement Results

Label value

Vertical

Perimeter
Horizontal

1
2
3
4
5
6
7
8

24

2

9
6
0
7
5
4
0

5

G-23

2

0
7
1
0
0

Diagonal
16
21
0
4
7
5
0
0

2.5.3 Algorithm for Perimeter Measurement of Images Labeled with 4-Way
Connection Labeling
The following section describes the algorithm used for perimeter measurement in raster-scan images
that have been labeled using 4-way connection labeling. This algorithm detects the boundary
between continuously labeled areas and the background by looking at 2 x 2-pixellocal areas, and
counts vertical, horizontal, and diagonal perimeter lengths independently.
Input data local area:

p3

p2

pI

pO

0

0

0

0

0

0

0

1

~
~
Local area
label data

Perimeter
V H D p3

tHE

0

0

0

Effij

0

0

0

tHE

0

o
o

0

0

1

0

*

0

0

1

1

0

1

0

0

0

1

0

1

0

1

1

0

1

1

0

0

0

1

0

0

1

0

0

1

0

1

0

tHE
taB
EB3
8±E

0

0

0

0

0

0

1

0

0

0

0

1

ffiij

0

1

0

tiE
EEt3

0

0

1

0

0

1

0

0

0

*

0

tHa

0

0

1

1

0

0

1

0

0

1

1

0

1

tBij

0

0

0

1

1

1

0

EHB

0

*

Perimeter
V H D

o

*

1

0

1

0

1

1

*

0

BIB

Local area
label data

o

0

0

*

1

pO

0

o

1

pI

tffij
o

0

p2

o

*

*

0

0

1

1

1

1

1

*

0

*

*

0

EEEj
*

*

0

•

Notes:
1)
2)

In the above table, whenever a given pixel Px (where x = 0 to 3) has the value 0, that pixel is considered
background. A 1 indicates a non-background value.
In the local areas in the above table, pixel values of 0 indicate that the pixel contains background. Pixels
marked with an asterisk (*) have non-background values.

3)

Linked areas consisting of a single pixel have a perimeter of o.

4)

If an area contains an enclosed "hole," the interior perimeter of the hole is included in the perimeter
calculation.

To find only the external perimeter, use this procedure: perform labeling using inverted binary image
data, then set all labels other than background to 0 before performing perimeter measurement.

G-24

2.5.4 Example: Perimeter Measurement of Images Labeled with 4-Way Connection
Labeling
Input Image

2-2-2
1

1

II

12 ""2 -2 -2/2
2
1",,/
222 2 2 2 2

1
11 "" 1
11 1 ~1/11
1/1

I
1
I
1
I

I
1
I

I
1
I

. "" 1

1

1

I
1
I
1

1/1

I

1

1

.~2

1/'

I
1
I
1
I
1
I
1

2
2/21

.""2/.

2

2

2

2

'~2

2

2/'

2

2

2

I

2

3
31

. ""2 ""2

13

31

."" 21

13

31

1

21
21

I

3
13

4

21

5-5=5=5

I
1
I
1
I
1
I

15/'
5/5 1
5/5

7

15/ "" 51

1

15 ~5~51

. ""11

a

6

II

51

6

8

gf

9

II

8~J

9

CI)~"
./j~
o....
><
or,IlClJ
(/J

en
Q.

rJ'J

<0
ClJ

~

Measurement Results
Label value

Vertical

Perimeter
Horizontal

Diagonal

1
2
3
4
5
6
7
8
9

24
9
6
0
7

2
7
2
0
7

8
13
0
0
7

2
0
1
2

0
0
1

0
0
1
0

G-25

0

~

-.eo.. .
ClJ ..

2.6

Run Coordinate Detection
•
•

•

•

This process operates on any labeled image that uses a background value of O.
For any area (with area number ~ 1) designated using the area number input signal (L<11..0»,
this process outputs a run start signal (RUNST*) and run end signal (RUNEND*), along with
the coordinates of both ends of all runs on every line over the output signal pins OD<23 .. 0>.
Note that the run coordinate detection and measurement process differs from other
measurement processes in that the resulting data is of variable length and can therefore only
be output to external circuits, and cannot be stored in results memory. The process includes a
delay of two clock cycles before the output of the run start and run end signals.
This function can be used as a preliminary step for binary image run length processing, by
beginning with the starting point for the area of interest and measuring the length of each run
of 0 and each run of 1. Also, because it can operate on all areas simultaneously, this function
provides an effective way to detect and measure boundary pixels. It can locate the smallest
unit of data having two-dimensional coordinates. This function can be used as a preliminary
step for special measurements of individual areas by an external DSP.
Run coordinate detection can be applied in combination with other measurement processes.
Note, however, that this requires the load capacity of the OD<23 .. 0> signal pins to be kept at
30 pF or lower.

[Sample processing]
The area below represents an input image with background value 0 and area number 8:
h
v

h+1

h+2

h+3

h+4

h+5

+: I-I-~-+--:--I--~-r---:-+--:--I--~--I

G-26

Sample output line V

h

h+!

h+4

h+3

h+2

h+5

h+6

h+7

h+8

iCLK
Area no.
input

L<11..0>

x-coordinate

OD<11..0>

y-coordinate

OD<23 .. !2>

start

RUNsr*

end

RUNEND*

,
v

, 1
\1

\,

,,
,

l'.~

Sample output line V +I

!I

"----J

i
i
1
\(
1\

.""----J
!

h

h+l

h+2

h+3

h+4

h+5

h+6

h+7

h+8

iCLK
Area no.
input

L<11..0>

x-coordinate

OD<11..0>

y-coordinate

OD<23 .. !2>

i
v+l

1

2.7

start

RUNSr*

end

RUNEND*

1

1
1

iL!f\--V

i "----J i
i "----J
iii

Measuring Moments
The IP90C18 can measure the zero-degree moment, the primary moment, and the secondary moment
about the origin of any two-dimensional image in real time. Using multiple IP90C18 chips enables
a system to calculate all three moments at the same time. Anyone of the three moments can be
calculated for up to 2048 areas (with 48-bit results data width) or 4096 areas (with 24-bit results
data width) simultaneously. Using two IP90C18 chips makes it possible to expand the number of
simultaneous measurements up to 4096 areas with a 48-bit results data width, without requiring
special external circuits. The number of areas can be expanded still further by using a simple
decoder circuit plus additional IP90C18 chips.
Although the IP90C18 can directly measure zero-degree moments, primary moments, and secondary
moments about the origin, a separate DSP or CPU is required when calculating center of gravity, or
primary or secondary moments about the center of gravity or the principal axis.

G-27

2.7.1 Moment Characteristics
If the grayscale value f(x, y) of any given point (x, y) in a two-dimensional image f represents the
mass of point (x, y), then the moment of inertia and center of gravity of the particular area in
which that point lies represent moment quantities and moment characteristics with respect to that
area. These moment characteristics can provide information about the location and shape of the
area.

Equation (1) is the general formula for the p- and q-order moments of two-dimensional image f
about its center of gravity (Xg, Yg).

Mpq=LL(x-Xgy.(y-yg)q.j(x,y)
x

(1)

y

In the following discussion, a capital M represents a moment characteristic about the center of
gravity, while a small m represents a moment characteristic about the origin. The Feature chip's
direct measurement capability is limited to binary images with respect to each area, artd to the
following six types of moment characteristic measurement, representing zero-order up to secondary
moments about the origin point: moo, mID, mOl, m20, mll, m02. The following sections describe each
of these measurement functions.

2.7.2 Zero-Order Moment Characteristics and Surface Area
The zero-degree moment is here considered a representation of weight, using grayscale values as
mass, and is calculated using this formula:

Moo

(2)

= moo = L Lj(x, y)
x

y

Equation (2) can be used to calculate a grayscale-weighted surface area. Here f(x, y) represents the
grayscale value of the pixel located at coordinates (x, y). Equation (3) below can be used to
calculate the surface area for areas in a labeled image. Here, because the nth object is represented
in binary values, the quantity d(x, y) must equal a or 1.

Moo

(3)

= moo = LLd(x,y)
x

y

The Feature chip can calculate in real time, simultaneously with the input of the raster-scanned
image, the moment moo described by equation (2) for the zero-degree moment of a grayscale image,
or the moment moo described by equation (3) for the zero-degree moment of a binary image.
However, the primary moment and secondary moment characteristics described below can only be
calculated for areas within binary images. This means that area number (labeled image) input is
valid for all three types of moment characteristic calculations, although grayscale image input is
only valid for zero-degree moment grayscale-weighted surface area measurement.

G-28

2.7.3

Primary Moment Characteristics and Center of Gravity

Equations (4) and (5) give the definition of the primary moment used by the Feature chip. The
chip uses an internal coordinate counter to calculate the sum of the coordinates of pixels in each
area, which allows it to calculate the primary moment about the origin. For any given input
image, this calculation can be performed using either of these equations:

MlO

= L LX. d(x, y)

(4)

MOl

=

LLy·d(x,y)

(5)

x

y

From this calculation and the zero-degree moment, an external DSP or CPU can calculate the
moment of any given area about its center of gravity using equations (6) and (7):
MIO = L.L.(x-Xg).d(x,y) =L.L.x.d(x,y)-Xg .L.L.d(x,y) = mlO -Xg . moo
x

MOl

y

x

= L. L. (y x

Y g ). d(x, y)

y

x

=L. L. y. d(x, y) -

y

x

Yg .L. L. d(x, y)

y

x

(6)

y

= mOl

-

Yg . mOO

(7)

y

Here Xg and Yg represent the X and Y axis coordinates of the center of gravity. Because the center
of gravity is defined as the point at which the primary moment is 0, these coordinates can be
represented by equations (8) and (9). Because the values mOO, mlO, and mOl calculated by the
Feature chip are measured in real-time, virtually simultaneously with the input of the rasterscanned image, these quantities can be derived by simple calculations using an external CPU or
DSP.
(8)

LLx.d(x,y)
Xg

= mlO =

x

y

LLd(x,y)

moo

x

Yg

= mOl =
mOO

y

LLy· d(x,y)
x

(9)

y

LLd(x,y)
x

y

G-29

2.7.4 Secondary Moment and Angle of Primary Axis
Equations (10, (11), and (12) give the definition of the secondary moment used by the Feature chip.
The chip uses an internal coordinate counter to calculate the sum of the coordinates of pixels in
each area, which allows it to calculate the primary moment about the origin. For any given input
image, this calculation can be performed using any of these equations:

M 20

y

x
M02

(10)

= LLx 2 • d(x,y)

(11)

= LLy2. d(x,y)
y

x

(12)

Mll = L LX' y . d(x, y)
x

y

From this calculation, an external DSP or CPU can calculate the moment of each area about its
center of gravity using these equations:
(13)
x

=

x

y

y

LLx2 .d(x,y)-2XgLLx.d(x,y)+X/LLd(x,y)
x

y

x

x

y

y

(14)
x

y

x

y

= LLy2. d(x,y) - 2YgL LY' d(x, y) + Y/LLd(x,y)
x

y

x

m

= m02 - 2 -.ill.. m01

moo

y

x

2

m ) m - m
+ ( -.ill..
0002

m

y

2

_-.QL

moo

moo

Mll = LL(x-Xg)(y-Yg).d(x,y)
x

(15)

y

= L LX' y. d(x,y) - YgL LX' d(x,y) - Xg LLY' d(x, y) + XgYgLLd(x, y)
xy

xy

xy

G-30

xy

From this secondary moment about the center of gravity, the chip can calculate an important
indicator of the orientation of an area (or object): its primary axis of inertia. The primary axis of
inertia can be described in terms of the angle q between the direction in which an area is growing
(its primary axis) and the X axis, here called the angle of the primary axis. Because the values
mOO, mlO, mOl, m20, mn, and mQ2, calculated by the Feature chip, are measured in real-time,
virtually simultaneously with the input of the raster-scanned image, the value of the angle q can
be derived by simple calculations using an external CPU or DSP.
(16)

The primary axis can be represented by equation (17):
(17)

G-31

2.8

Grayscale Projection Processing (Peripheral Distribution Measurement)
Algorithms
Grayscale projection processing, sometimes called peripheral distribution, contributes to higher
speeds in image-processing functions. This process is often featured in texts and articles on image
processing, because it can provide a simple, clear measurement of the characteristics of processes
image areas.
Because of limits on circuit size, projection processing in previous systems has for the most part
been practical only for binary images. Projection processing of binary images, however, does not
permit sufficient accuracy or provide enough information to be of much use as a short-cut in image
processing. These objectives require the use of grayscale projection processing, a function that has
been difficult to realize. The IP90C18 Feature chip meets this demand, however, and provides
projection processing of 12-bit grayscale values (1096 gradients).
Vertical (H-axis) projection processing is the process of measuring the sum of the grayscale values
of all pixels on the screen having a given H-axis coordinate. Similarly, horizontal (V-axis)
projection processing is the process of measuring the sum of the grayscale values of all pixels on
the screen having a given V-axis coordinate. The Feature chip can perform H- and V-axis
projection processing simultaneously, or on either axis separately.

o -------

------- n-l

Vproj(v)

o

--~~--------~~~------~~------~

rn-l~~+-----~~~----~~----~

Horizontal (V-axis) grayscale projection:

Vproj(V)

= "Lf(h,v)
h

Vertical (H-axis) grayscale projection:
f(h, v)

= grayscale

Hproj(h)

value of pixel (h, v)

G-32

= "Lf(h,v)

2.9

Table Conversion (LUT) Processing
•

•

•

•

The Feature chip includes a 12-bit input, 24-bit output look-up table (LUT) conversion function
that can be used for a wide variety of processes. For each address in results memory input
through the area number input signal (L<11..0» or grayscale value input signal (ID<11..0), the
LUT function outputs the corresponding value over the image data output (OD<23 .. 0» signal.
Note that table conversion processing differs from other measurement functions in that the
results of conversion can only be output to external circuits, and cannot be written to results
memory. The process includes a delay of four clock cycles from input of grayscale values or area
number values to the output of image data.
This function is convenient for converting incoming area number values to new area numbers. For
example, after area numbers (label values) are assigned to each area in an image and the
surface area of each area measured using histogram processing, the smallest areas can be
deleted (converted to background) by writing the background value to the corresponding
addresses in memory. The same function can naturally be used to renumber any or all areas.
Because this function can produce 24-bit output from 12-bit input data, it can be used to extend
an area between labeled images, or to change label numbers. It provides a convenient way to
perform a variety of procedures ranging from pixel-by-pixel to full-screen conversion, such as
deleting all areas that include boundary pixels from the coordinates of a rectangle
circumscribed about a given area, or merging overlapping areas by assigning them the same
area number.
This function can also convert grayscale input values to other values. This enables binary
conversion or contrast enhancement of the results of grayscale histogram processing, or gammacompensation. Because this function can produce 24-bit output from 12-bit input data, it can be
used to expand the dynamic range of grayscale images, and is convenient for processes ranging
from pixel-by-pixel conversion to full-screen conversion.
The one-to-one replacement of input values by output values is ideal for constant-value
calculations. Thus, expected measurement values can be written into results memory, for use in
one-to-one calculation of sums, differences, products, dividends, etc., with respect to actual
measurement results. Other uses include bit positioning (bit-shift and bit-rotation calculations),
bit-masking calculations (conversion of selected bit positions to 0 or 1), and bit inversion
processing.
Input/ output example:
iCLK
L<11..0>,
ID<11..0>
OD<23 .. 0>

G-33

Processing example

Example:

Conversion table
(hexadecimal values)

y = 2x+l
LUT conversion
processing

Address

Conversion
value

000

00001

001

00003

002

00005

003

00007

Input x

r
2.10

y = 2x+l

00009

004

r

rJ

Output

r l.;

V

~
3FF

I

~
00800

I

Cumulative Histogram Processing
This function sequentially selects each address in results memory by means of an internal counter.
The data in each selected address is then added to the data in that address oIl. subsequent cycles,
and the results are written again to that address. When the operation is ended, results memory
thus contains a cumulative histogram distribution. The starting address is 0, and the ending
address is 2047 in 2K area measurement mode and 4095 in 4K area measurement mode.
Cumulative histogram H(i):
(1)

i

Hi = Lh(k)
k-O

where h(k) is the histogram of gradient value k (in results memory address).
Processing example (4096 gradients, 224_1 pixel processing)
Memory address
(grayscale values)

Histogram results

Memory address
(grayscale values)

a

3

a

3

1

4

1

7(",3+4)

Histogram results

2

1

2

8 (= 7 + 1)

3

a

3

8(=8+0)

4

71

4

79 (=8 + 71)

..
h(i)

4095

H(i) (= H(i-1)+ h(i»

4095

6

G-34

224_1

Section 3: Pin Functions
3.1

Pin Lists and Function Descriptions

Pin group
Image data input

Image timing

Image data
output

Status output

Function

Remarks

Image area no. input
(no delay)
Image area no. input
(one-line delay)

Input of labeling area

Pin

I/O

No.

LO-ll

I

12

OLO-ll

I

12

IDO-ll

I

12

iCLK
VEN'

I

1

HEN'
FEN'

I
I
I

1
1
1

!DEN'

I

1

OlDEN'

I

1

Extended background setting
signal for OLO-OL11

L: Set background pixel value
H: Use image data value
(Notes 2, 3, and 5)

000-23

0

24

Image data output

OOEN'

I

1

00 output enable

RUNSI'

0

1

Run start signal

RUNEND

.

0

1

Run end signal

Output LUT, run coordinates, results
memory dump
OOEN' = H: 000-0023 High-Z
OOEN' = L: 000-0023 drive enabled
Run coordinate detection, start
boundary pixel detection signal
Run coordinate detection, end
boundary pixel detection signal

BUSY'

0

1

Processing 'busy' flag

L: Processing

OVP

0

1

Overflow flag

L: Overflow condition

R/M'

I

1

Register / memory selection

L: Results memory
H: Register (Note 6)

I

14
24

Control bus address input
Control bus data input/ output

CPU address bus
CPU data bus (Note 7)

1
1

Chip select signal
Write enable signal
Read enable signal
Bus width: 8, 16, or 24
(Note 7)

Pixel grayscale data input
Clock signal
Vertical data enable signal
Horizontal data enable signal
Field enable/ disable control
for VEN' signal
Input data enable

Labeling area input, delayed by one
line; pull-up resistance (Note 2)
Input of grayscale-value image
fmax = 20/40 MHz
L: Enable, H: ~isable
L: Enable, H: Disable
L: Enable
H: ~isable (Note 3)
L: Enable, H: Disable. Can be
controlled by individual pixel (Note 3).

H: Not processing
H: Normal (Note 4)
CPU Interface

ADO-13
DBO-23
CS'
WR'

I/O
I
I

RD'

I

BUSWO,
BUSWI

I

RSI'

I

1
1
19

Test pin

TESI'

I

Power source

Vdd
GND

PW
PW

Total pin count:

1
2

24

(BUSW1,
access
(BUSW1,
access
(BUSW1,
(BUSW1,

BUSWO)

= (0,

0): 24-bit

BUSWO)

= (0,

1): 16-bit

BUSWO)
BUSWO)

= (1,
= (1,

0): 8-bit access
1): (reserved)

System reset

Does not clear memory; pull-up
resistance connected

LSI internal test pin

Set high for normal use
(Note 8)

5V
Ground

(Note 8)

160

G-35

Note
Note
Note
Note
Note

1:
2:
3:
4:
5:

An asterisk (*) following a pin name denotes inverse logic.
Used only when calculating the circumference.
Set to low for normal use.
Processing continues regardless of overflow conditions.
The DIDEN* signal is the data/background ID signal for area signals DLO-DL11.
DIDEN* is used as an extension (background recognition) of the number of processing
areas for perimeter measurement.
Note 6: Functions as a control bus address input signal (AD14) during access through the CPU bus.
Set this bit low for access to internal results memory, or high for access to internal
registers. To access internal results memory, designate the memory address as a byte
address (regardless of bus width) and send it through control bus address input (ADOAD13). The number of registers is limited to 16, but each register is mapped in 32-bit
word units of 4 bytes each, as designated through control bus address input bits AD2,
AD3, AD4, and AD5. For register access, control bus address bits AD6-AD13 are not
decoded. For details, see Section 6.1, "Register Lists and Address Maps."
Note 7: According to the settings of the BUSWO and BUSW1 pins, unused bits beginning at the
high bit (MSB) end are placed in high-impedance status. Therefore, pull any unused
input or I/O pins up or down, as appropriate. If any CMOS-LSI input pins are left
unconnected, abnormal currents may occur in the LSI chip.
Note 8: Connect all power supply pins. This will help prevent abnormal operation due to pulse
noise, etc.

G-36

3.1.1

Schematic Pin Diagram

The diagram below shows pin placement and function on the IP90C18 chip.

Feature
Image bus
output
OD<23 ..0>

Image bus input

..

...

iCLK

ODEN*

L
DL

RUNST*

ID

RUNEND*

IDEN*

Status

DIDEN*

BUSY*

VEN*

OVF*

HEN*
FEN*

CPU interface
RIM*
AD<13 .. 0>

Direct control
input

DB<23 ..0>

RST*

CS*
RD*
WR*

Vdd

BUSWO

GND

BUSWl

G-37

---

3.2

Pin Assignments
The IP90C18 and IP90C18-HS have identical pin assignments.

Pin No.

Name

Type

Pin No.

Name

Type

Pin No.

Name

Type

Pin No.

;\;ame

[vpe

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

GND
LD
U
1.2
L3
1A
15
16
17
18
19
LID
L11
DLO
DLI
DL2
DL3
DL4
DLS
GND
Vdd
DL6
DL7
DL8
DL9
DLIO
DL11
IDO
IDI
ID2
ID3
ID4
ID5
ID6
ID7
ID8

PW

41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70

GND
IDEN'
DIDEN'
FEN'
VEN'
HEN'
ODENB
Vdd
GND

PW

121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160

Gt-.:D
Vdd
Gt-.:D
DBO
DBI
DB2
DB3
Vdd
GND
DB4
DB5
DB6
DB7
Vdd
GND
DB8
DB9
Vdd
GND
DBI0
DBll
DB12
DB13
GND
DB14
DB15
DB16
Vdd
GND
DB17
DBIB
DB19
DB20
Vdd
GND
DB21
DB22
DB23
Vdd
GND

P\V

a
a
a

GND
OD20
0D21
OD22
OD23
Vdd
GND
RUNST'
RUNEND'
BUSY'
OVF'
Vdd
GND
TEST'
BUSWO
BUSWI
Vdd
GND
iCLK
GND
RST'
CS'
WR'
RD'
ADO
ADI
AD2
A03
AD4
ADS
AD6
AD7
AD8
AD9
A010
A01l
AD12
A013
R/M'
Vdd

PW

aDO
aD!

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

ID9

!DID
!Dll
Vdd

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PW
PW
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
PW

71

72

73
74
75
76
77
78
79
80

0D2
Vdd
GND
003
0D4
ODS
GND
0D6
0D7
Vdd
GND
OD8
0D9
ODlO
Vdd
GND
OD11
0012
OD13
Vdd
GND
OD14
0015
OD16
GND
OD17
OD18
OD19
Vdd

I
I
I
I
I
I

PW
PW

PW
PW
0
0
0
PW
0
0
PW
PW
0
0
0
PW
PW
0
0
0
PW
PW
0
0
0
PW
0
0
0
PW

G-38

a
0

a
a
PW
PW

a
a
a
a
PW
PW
I
I
I

PW
PW
I

PW
I
I
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
PW

PW
PW
I/O
l/O
[(0
I/O
PW
PW
I/O
l/O
I/O
I/O
PW
PW
I/O
I/O
PW
PW
I/O
I/O
I/O
I/O
P/W
I/O
I/O
I/O
PW
PW
I/O
I/O
I/O
I/O
PW
PW
I/O
I/O
I/O
PW
PW

3.3

Pin Placement Diagram

3.3.1

The IP90C18
_0

*~~=~~OO~~~Q~N_O**
*O~O ~~~o ~~
:g~ooooooooo
OOQOO~~~Z~z~~~~z:g>~

>

«««««««~~u~o~o>~~~o>o~

~:g§§§S~

0>00000

120
GND
Vdd
GND
DBO
DB1
DB2
DB3
Vdd
GND
DB4
DB5
DB6
DB7
Vdd
GND
DB8
DB9
Vdd
GND
DB 10
DB 11
DB12
DB13
GND
DB14
DB15
DB16
Vdd
GND
DB 17
DB18
DB19
DB20
Vdd
GND
DB21
DB22
DB23
Vdd
GND

80

+SUMITOMO
METALS ©

IP90C18
YYWWXXXXXXXXXXX
VY06985
SUMITOMO METALS
IP90C18

0

Vdd
0D!9
OD18
OD17
GND
OD16
OD15
0D!4
GND
Vdd
OD13
OD12
ODll
GND
Vdd
ODlO
OD9
OD8
GND
Vdd
OD7
OD6
GND
OD5
004
OD3
GND
Vdd
OD2
OD!
ODO
GND
Vdd
ODEN'
HEN'
YEN'
FEN'
DIDEN'

IDEN*
GND
40

160-pin QFP package (molded area 28 mm2 , pin pitch
Note:

= 0.65 mm)

The IP90C18 and IP90C18-HS have identical pin placements; only the embossed label is
different.

G-39

BI
bO

.ij

co
~ ~
_.!:10

o
>< ~
o~Q)

g

(.1) Vl
Q) ....

0..
-EP-.

'"
Q)

""

3.3.2 The IP90C18-HS
i:g§8§§~

0>00000

120
GND
Vdd
GND
DBO
DB1
DB2
DB3
Vdd
GND
DB4
DBS
DB6
DB7
Vdd
GND
DB8
DB9
Vdd
GND
DB10
DBll
DB12
DB13
GND
DB14
OBIS
DB16
Vdd
GND
DB17
DB18
DB19
DB20
Vdd
GND
DB21
DB22
DB23
Vdd
GND

80

+SUMITOMO
METALS©

IP90C18

YYWWXXXXXXXXXXX
VY06985
SUMITOMO METALS
IP90C18
HS

0

IDEN*
GND

160-pin QFP package (molded area 28 mm2 , pin pitch
Note:

Vdd
0D19
OD18
0D17
GND
OD16
OD1S
OD14
GND
Vdd
OD13
OD12
ODll
GND
Vdd
ODlO
OD9
OD8
GND
Vdd
OD7
OD6
GND
ODS
004
003
GND
Vdd
002
001
000
GND
Vdd
ODEN'
HEN'
YEN'
FEN'
DIDEN'

= 0.65 mm)

The IP90C18 and IP90C18-HS have identical pin placements; only the embossed label is
different.

G-40

Section 4: Sample System Configuration and Operation
4.1

Sample Configuration: Basic System
The diagram below shows the configuration of a basic system using the IP90C18 Feature chip. The
grayscale data and the area number (label) image for the items to be measured are input
sequentially, in the direction of the raster scan. In this example, the grayscale and area number
(label) images are connected together, and a delay of one line is applied to the perimeter
measurement: this would allow the chip to perform all basic measurements.

r

r--

1H line delay

IP90MDI0 labeling
processor module
Image data

IP90C 18 Feature chip
12-bit
~ DL<11..0>

IP90C51 b~nary
conversIOn
IP90ClO
labeling
Area number input

12-bit
L<11..0>
OD<23 ..0>
ODEN*

Grayscale value output

I

I

24-bit

1mage bus output
(L UToutput,
run coordinate
me asurement)

12-bit

Frame
memory

ID<11..0>
~

Image timing
input

iCLK
FEN*, VEN*,
HEN*
IDEN*

RUNST*
RUNEND*

Run detection
signal

DIDEN*

I

BUSY*

Low

OVF*
Direct control input

Status output

RST*
RIM*
14-bit

CPU
interface

24-bit

AD<13 .. 0>
DB<23 .. 0>
CS*, RD*, WR*
BUSWO, BUSWI

Note 1:
Note 2:

An asterisk (*) after a signal name denotes inverse logic.
This block diagram is intended only as a functional description, and does not show all
functions of the IP90C18 Feature chip. For full descriptions of functions, timing, and other
information, see specific sections of this manual.

G-41

4.2

Operating Description

4.2.1 Image Synchronization and Control Signals (VEN*, HEN*)
This section gives a general description of the image synchronization and control signals used in
the IP90C18's image input/output system. For details about signal timing, see Section 8.5,
"AC Characteristics."
Note:

Throughout this section, an asterisk (*) following a signal name denotes inverse logic.

4.2.1.1

Image Clock Synchronization

The IP90C18's processing circuits are synchronized with the image clock signal (iCLK). Note,
however, that some functions (such as addresses for results memory, and the CPU bus signals that
set the chip's internal modes) are synchronized with the CPU bus control signals (CS*, RD*, WR*)
rather than with iCLK.
On the rise of iCLK, an input flip-flop latches the following input signals:
•
•
•

area number signals (L<11..0>, DL<11..0»
} these make up the input signal
for the image system
pixel grayscale data signals (ID<11..0»
image synchronization and control signals (FEN*, VEN*, HEN*, !DEN*, DIDEN*, RST*)

The status output signals (BUSY*, OVF*) and measurement signal output (OD<23 .. 0>, RUNST*,
RUNEND*) are output when iCLK rises after an external load drive delay.
4.2.1.2

Raster Scan Input

Image data is input in synchronization with the pixel clock and in the direction of the raster scan,
and is input simultaneously through the area number signals (L<11..0>, DL<11..0» and the pixel
grayscale data signals (ID<11..0» corresponding to L<11..0>. The Feature chip's internal circuits
have a pipeline configuration that allows real-time throughput, during which feature extraction
is performed and the results stored in memory. The area number input signals (L<11..0>, DL<11..0»
and pixel grayscale data input signals (ID<11..0» include some signals not required for feature
extraction. For details, see Section 5.2, "External Signal Connections and LSI Internal Connection
Settings for Measurement Processes."
4.2.1.3

Frame Recognition Image Synchronization Signals (VEN* and HEN*)

Image data entering in raster scan format is put into two-dimension format using the vertical data
enable signal VEN* and the horizontal data enable signal HEN*. The Feature chip defines a
field of data as a cycle that begins when VEN* goes low, and ends when VEN* goes high again.
The chip also defines each line in the field as a cycle that begins when HEN* goes low and ends
when HEN* goes high again. Thus, a field of data is the data input while VEN* is low, and a
line of data is the data input while HEN* is low. With non-interlaced data, each frame of the
image consists of a single field, but with interlaced data, each frame consists of two fields. Thus, a
frame of interlaced data consists of a first field defined by the first VEN* and a second field
defined by the second VEN*.
A frame to be processed by the Feature chip starts when the execute flag in the execute register is
set to "start feature extraction," followed by the input of a low-level VEN* signal (while FEN*
has been low for at least one clock cycle).
The Feature chip has a field count control function that stops feature extraction automatically
after processing a designated number of fields. This function is controlled by a register setting that
can designate an automatic stop after processing 1-255 fields, or disable the count function to allow
continuous processing (until stopped by the execute flag).

G-42

To input and measure a particular number of fields, designate the number (1-255) by setting the
field count control register, then start execution by writing a 1 to the exec bit in the execution
register.
Field count controls can also be applied from external circuits. For example, a logical circuit can be
added to hold FEN* high after the input of a field: this is convenient for use with the IP90C55
image data stream controller chip (IMSC), which has a function that outputs one or two
rectangular areas of interest (AOI-n*) from an image space.
When disabling the field count control function to allow continuous processing, set the field count
control register to OOh, and start execution by writing 1 to the exec bit in the execution register. (To
stop execution, write 0 to the exec bit.)
The Feature chip uses VEN* and HEN* internally as reset and start-count signals for the Vcnt and
Hcnt counters, which are used to recognize vertical and horizontal image coordinates, respectively.
When the change of VEN* to low is detected at the rise of iCLK, a VENpls pulse of one clock
width is generated by synchronized differentiation within the chip. This pulse resets Vcnt to 0 at
the start of the field. Then, when the change of HEN* to low is detected at the rise of iCLK, an
HENpls_hl pulse of one clock width is generated by synchronized differentiation within the chip.
HENpls_hl resets Hcnt to 0 at the start of each line.
4.2.1.4

Effective Area Enable Signals (VEN', HEN')

VEN' is the vertical data enable signal and the enable signal for Vcnt. It works with HEN',
which is the horizontal data enable signal and the enable signal for Hcnt. The IP90C18 performs
feature extraction processing on image data that is input when VEN* and HEN' are both low.

G-43

4.2.2 VEN* and HEN* Signals and Spatial Coordinates
The following diagram illustrates the relation between the VEN* and HEN* signals and the
coordinates of each pixel in an image.
•
•

Input image (M x N): Raster scan input of pixel data values, synchronized with the iCLK
signal.
Processing area (m x n): m = 0-4095 pixels, n = 0-4095 pixels.
Raster scan direction
VEN*

v

HEN*

Horizontal Coordinates
When the change of HEN* to low is detected at the rise of iCLK, an HENpls_hl pulse of one clock
width is generated by synchronized differentiation within the chip. This pulse is the reset and
start-count signal for the horizontal coordinate counter Hcnt. Thus, the horizontal coordinates (Ln)
of image data point IDn (which are picked up at the rise of iCLK when the change of HEN* to
low is detected) become the 0 point. Hcnt then starts counting iCLK signals as long as HEN* is
low.
Vertical Coordinates
When the change of VEN* to low is detected at the rise of iCLK, a VENpls pulse of one clock
width is generated by synchronized differentiation within the chip. VENpls is the reset and
start-count signal for the vertical coordinate counter Vcnt. Thus, the vertical coordinates (Ln) of
image data point IDn (which are picked up at the rise of iCLK when the change of VEN* to low
is detected) become the 0 point. Vcnt then starts counting the number of times HEN* goes high
while VEN* stays low.
Also note these points:
• Processing is performed on image data input while VEN* and HEN* are both low. (The chip's
exec flag must also be set.)
• As shown above, set HEN* low for each line, and high for areas not to be processed .

G-44

4.2.3

Input Image Data Transfer Format

iCLK~
IDn,Ln,
DLn
(image data)

FEN *
Note 1,2

VEN*
Note 1, 3

~L-----------~§I~------~§----------~§f--------~§---

HEN*
Note 1,4

Note 1:
Note 2:

Note 3:
Note 4:

An asterisk (.) following a signal name denotes inverse logic.
VEN' is enabled one clock count before the next rise of iCLK after VEN' falls while
FEN' is low. FEN' facilitates synchronization with other image-processing LSI devices
and sequencers. Keep FEN' low whenever synchronization with other LSI devices is not
needed (this is normal).
Keep VEN' low while the data that makes up a field is being input (since the deassertion of VEN' from low to high marks the end of a frame of valid data).
Keep HEN' low while the data that makes up a line is being input.

G45

4.2.4 IDEN* and Feature Extraction
The IDEN* signal pin enables and disables pixel-by-pixel processing of input image data (IOn, Ln,
DLn). When IDEN* is set high to disable image data in the rectangular processing area defined
by VEN* and HEN*, the IP90C18's feature extraction functions operate as shown in the following
table.
Note that IDEN* functions independently of the coordinate counters Hcnt and Vcnt, so that the
coordinate count does not stop when IDEN* goes high. When stopping the coordinate counters, take
care to avoid causing glitches in iCLK.
IDEN* Signal and Feature Extraction
Change in chip operation when IDEN* is
high (VEN* and HEN* are active low)

Feature Extraction Process
Grayscale histogram
Surface area measurement
Grayscale-weighted area measurement

Adds 0 to current grayscale values
Adds 0 to current area values
Sets current pixel grayscale value to 0 (adds 0
to current area values)
Ignores current coordinate values (coordinate
counter output); existing diagonal coordinates
are unchanged
Adds 0 to current area values
Adds 0 to current area values
Even if the current area value is for a
boundary pixel, the RUNST* and RUNEND*
signal outputs remain high
Any perimeter measurement of current 2x2
pixel local areas is not counted (adds 0)
Sets current pixel grayscale value to 0 (adds
0)
No effect
No effect

Coordinates of circumscribed rectangles

Area end I-point coordinates
Primary and secondary moments
Run coordinate extraction

Perimeter measurement
Grayscale projection
Table conversion
Cumulative histogram
Sample Uses of the IDEN* Signal
•

Feature extraction from areas of any shape:
IDEN* can enable feature extraction from an area of any shape that lies within a rectangular
processing area defined by the VEN* and HEN* signals.

•

Expansion of processing data width across multiple chips:
When performing histogram processing of more than 4096 values, the data width can be
expanded by decoding the high bit and assigning its value to the IDEN* signal pin. Thus, for
example, 16-bit histogram processing could be done by a system containing 16 Feature chips.
The lower 12 bits are used as the measurement value for each chip, and the upper 4 bits are
decoded and assigned to the IDEN* signal. A single-chip configuration could provide the same
results by using 16 measurement iterations.
This type of arrangement can also be used to expand the range of area numbers, as shown in
Section 4.3, "Sample Configuration: Expanded System," or to expand the range of grayscale
pixel values (the dynamic range).

G46

4.2.5

Background Identification Signals (IDEN* and DIDEN*)

4.2.5.1

Background Identification Signals (IDEN* and DIDEN*)

Perimeter measurement differs from other feature extraction measurements in that it involves the
area boundary detection process, which requires the use of a distinct background area number for
boundary recognition. The background area is designated not by area number input value (L<11..0>,
DL<11..0», but by pixel units determined by the background identification signals IDEN* (the
background identification signal for L<11..0» and DIDEN* (the background identification signal
for DL<11..0». When measuring a perimeter, if a 2x2-pixellocal area includes a boundary of a
labeled area, the chip has to determine which linked areas (area numbers) the 2x2-pixel area
belongs to. This requires inputting the area number signal L<11..0> and applying a one-line delay
to the area number signal DL<11..0>. Thus, for perimeter measurement, identifying background
areas pixel-by-pixel requires IDEN* (delayed by one line) and DIDEN*.
4.2.5.2

Example of Using the Background Identification Signals

As an example of how IDEN* and DIDEN* can be used, consider a system that expands the
maximum number of areas (maximum number of labels) using multiple Features chips.
When a Feature chip measures a perimeter in three directions simultaneously, the maximum
number of areas per chip (excluding the area number for background values) is 2047. However, by
connecting several chips, each chip can measure the perimeter of each area (excluding the area
number for background values) in three directions simultaneously. For details, see Section 4.3,
"Sample Configuration: Expanded Systems."

G-47

4.3

Sample Configuration: Expanded System
The IP90C18 Feature LSI chip can process areas and grayscale values in much greater quantities12 bits (4096) or 11 bits (2048)-than previous devices. Its image-processing field can be used in a
particularly wide range of specifications, and provides a wide variety of capabilities for various
applications. The Feature chip is designed for systems that process expanded numbers of areas,
pixel value resolutions, processing area sizes, or other characteristics.
This section provides several sample configurations to show how multiple Feature chips can be
used for real-time processing in expanded systems. These examples are intended as conceptual
sketches only: thoroughly check timing, processing constraints, system requirements, and
environmental factors before adapting any of these concepts to actual applications.

4.3.1 Sample System: Expanding the Number of Areas for Cumulative Processing by
Area
(B) Grayscale-weighted average area measurement
for 8192 separate areas (4096 x 2-area expanded
system configuration)
Area number 0-4095

(A) Grayscale-weighted average area
measurement for 4096 separate areas
(basic system configuration)

Feature#O
IDEN'
L - ' - - t - - -.....p; L
10<11..0>
10<11..0>

Area number 0-4095

L

Feature#O
Low
IDEN'
L - - - - P i L
10<11..0>
10<11..0>

Area number 4096-8191
)O++~

(e) Grayscale-weighted average area measurement

for 16K separate areas (4096 x 4-area expanded
system configuration)

Area number 0-4095

L - - - . , . - - - - - - I -....~

Feature#O
!DEN'
L
!D

Area number 4096-8191

10<11..0>

-------++-......+~

Feature#l
!DEN'
L
!D

Area number 8192-12287

Feature#2
!DEN'
L
!D<11..0>
Area number 12288-16383

Feature#3
!DEN'
L
!D

G-48

Feature#l
IDEN'
L
!D

4.3.2 Sample System: Expanding the Number of Grayscale Pixel Gradients for
Grayscale Histogram Processing
(A)

Histogram measurement of 4096 grayscale
gradient values (basic system configuration)
Grayscale values 0-4095

(B) Histogram measurement of 8192 grayscale gradient values
(4096 x 2-gradient expanded system configuration.
13-bit histogram processing)
Grayscale values 0-4095

Feature#O
IDEN'
ID<11..0>

Low
ID<11..0>

ID<12>
ID<12 .. 0>

-...L.-+----e..~

Feature#O
IDEN'
ID

Grayscale values 4096-8191
Feature#l
IDEN'
ID<11..0>
(C) Histogram measurement of 16K grayscale gradient values
(4096 x 4-gradient expanded system configuration.
14-bit histogram processing)

ID<13 .. 0>

ID<11..0>

"\

....

Grayscale values 0-4095
Feature#O
IDEN'
ID<11..0>

roEC

~ ~~
?~

Grayscale value s 4096-8191

ID< 13 .. 12>

...

.....

Feature#l
IDEN'
ID

a

g

en

0

Vl

i': ~,

'"

Q)

~

.....

Grayscale values 12288-16383

~

G49

Feature#3
IDEN"
ID<11..0>

i

Vl

o~S

Q.

Feature#2
IDEN'
ID<11..0>

'

~.§
U ><

-.8

Grayscale value s 8192-12287

I

bIl

.~

4.3.3 Sample System: Expanding the Number of Areas for Surface Area
Measurement
(A)

Surface area measurement for 4096
separate areas (basic system configuration)

(B) Surface area measurement for 8192 separate areas
(4096 x 2-area system configuration)
Area number {}-4095

Area number 0-4095

Feature#O
!DEN"
Low
L - - - -___~ L<11..0>

....

L<12>
L<12 .. 0>

/

Feature#O
!DEN"
L<11..0>

Area number 4 096-8191

'V

(C)

Area number {}-4095

L<13 .. 0>

"-

.

...

Feature#O
!DEN"
L<11..0>

DEC
0
1

'---

L<13 ..l2>

-

~~

Area number 4096-8191

...

Feature#l
!DEN"

~ L

Area number 81 92-12287

..

4~

Feature#2
!DEN"
L<11..0>

Area number 12288-16383

....

Feature#3

!DEN"
~ L<11..0>

G-50

Feature#l

!DEN"
~ L<11..0>

Surface area measurement for 16K separate areas
(4096 x 4-area system configuration)

L<11..0>

.

4.3.4 Sample System: Expanding the Number of Areas for Diagonal Coordinate
Measurement of Circumscribed Rectangles
(B) Diagonal coordinate measurement for 4096
circumscribed rectangular areas (4096-area
expanded system configuration)

(A) Diagonal coordinate measurement for 2048
circumscribed rectangular areas (basic
system configuration)
Area number 0--2047

Area number 0-4095

Feature#O
L

L

..

L

HO,VO

Feature#O
L
HO,VO

Hl,Vl
Area number 0-4095

Area expansion mode
register settings:
cmpll = I
bllsel=O
datall = 0

Feature#O

~ L
Hl,Vl

(C) Diagonal coordinate measurement for 8192

circumscribed rectangular areas (4096 x 2-area
expanded system configuration)

L<12 .. 0>

Area number 0-4095
Feature#O
IDEN'
L

L

HO,VO

Area number 0-4095

L< 12>

~

Feature#l
IDEN"
L
Hl,Vl

Area number 409 6-8191
Feature#2

~

IDEN'
L

HO,VO

Area number 409 6-8191
Feature#3
IDEN"

~ L
Hl,Vl

G-51

•

I

4.3.5 Sample System: Expanding the Number of Areas for One-Point Boundary
Coordinate Measurement
(A) One-point boundary coordinate
measurement for 4096 separate areas
(basic system configuration)

(B)

One-point boundary coordinate measurement for
8192 separate areas (4096 x 2-area expanded
system configuration)
Area number 0-4095

Area number 0-4095

Feature#O
Low
L<11..0>

-------l~

IDEN*
L<11..0>

..

L<12>
L<12 .. 0>

...

/

Feature#O
IDEN*
L<11..0>

Area number 409 6--8191

Feature#l

Y>
(C) One-point boundary coordinate measurement for
8192 separate areas (4096 x 4-area expanded
system configura·hon )

L<13..0>

L<11..0>

\

IDEN*

~ L

Area number 0-4095

..

:.

Feature#O
IDEN*
L<11..0>

DEC

'-- ?K
~

L <13 ..12>

-

8==;-

Area number 409 6-8191

.

~

Feature#l
IDEN*
L<11..0>

Area number 819 2-12287

Feature#2
~

~

IDEN*
L

Area number 12288-16383

..

Feature#3
IDEN*

~ L<11..0>

G-52

4.3.6 Sample System: Expanding the Number of Areas for Run Coordinate Detection
by Area
(A) Run coordinate detection for 4096 separate
areas (basic system configuration)

Low
L

(B) Run coordinate detection for 8192 separate areas
(4096 x 2-area expanded system configuration)

Area number 0--4095
Feature#O
!DEN*
L

Area number 0--4095
Feature#O
!DEN'
L

L<12>
L<12 .. 0>

/
L

OD<23 .. 0>
RUNST*

Run coordinates
Run start detection
signal
RUNEND*
Run end detection
signal
Area expansion mode register
(EXT) settings: cmp l! = 0
bl!sel = 0
datal! = 0
zd=O

Area expansion
mode register
(EXT) settings:
cmpll = 0
bllsel = 0
datall = 0
zd=O

Area number 4096-8191

Y>

.
-.-

Feature#l
!DEN'
L

cmpll = 0
bllsel = 0
datall = 0
zd = 1

(C) Run coordinate detection for 16K separate areas

(4096 x 4-area expanded system configuration)

L

L

"-

..
...

Area number 0--4095
Feature#O
!DEN'
L

Area expansion mode
register (EXT) settings:
cmpll = 0
bl!sel = 0
datall = 0
zd=O

rnEC
0:r-L<13-.. 12>

g::=--

19l
~

Area number 4096-8191
Feature#l
!DEN'
~ L

.

gp

..t::

cmpll = 0
bllsel = 0
datall = 0
zd = 1

CO .J:j0
~ ""
...

o

x ill
rJ) (5

o~OJ

0)

c..

OJ

to
OJ
r.L;

Area number 819 2-12287

...
~

Feature#2
!DEN'
L

cmpll = 0
bllsel=O
datall = 0
zd= 1

Area number 12288-16383
Feature#3
cmpll = 0
!DEN'
bllsel = 0
~ L
datal! = 0
zd= I

G-53

....

-.aD.

4.3.7 Sample System: Expanding the Number of Areas for Primary Moment
Measurement by Area
(A) Primary moment measurement for 2048

separate areas (basic system configuration)

(B) Primary moment measurement for 4096 separate areas
(4096-area expanded system configuration)

Area number 0-2047
Feature#O
L

L

L

Area expansion mode
register (EXT) settings:

L

Feature#l
~ L

Primary moment measurement for 8192 separate areas
(4096 x 2-area expanded system configuration)

L

-

Area number 2048-4095

cmpll = I
bllse} = 0
datall = 0

(C)

L

'\

Area expansion mode
regiSter (EXT) settings:
cmpl! = I
bllsel=O
datal I =0

Area number 0-2047
Feature#O

...

..

Area number 0-2047
Feature#O
IDEN"
L

cmpll = I
bllse} = 0
datall = I

Area expansion mode
register (EXT) settings:
cmpll = I
bllse}=O
datal I =0

L< 12>
Area number 2048-4095

...

4~

Feature#l
IDEN"
L

cmpll = I
bllsel = 0
datall=1

Area number 4096-6143
."....

...

~

..

~

G-54

Feature#2
IDEN'
L

cmpll = I
bllse} = 0
datal I = 0

Area number 61 44-8191
Feature#3
WEN'
L

cmpll = I
bllsel=O
datal I = I

4.3.8 Sample System: Expanding the Number of Areas for Secondary Moment
Measurement by Area
(B) Secondary moment measurement for 4096 separate areas
(4096-area expanded system configuration)

(A) Secondary moment measurement for 2048
separate areas (basic system configuration)
Area number 0-2047

Area number 0-2047

Feature#O
L<11..0> ...

Feature#O
L<11 ..0> ....

L

~

Area expansion mode
register (EXT) settings:

Area expansion mode
register (EXT) settings:
cmpll = I
bllsel = 0
datall = 0

L

Area number 2048-4095
Feature#l

cmpll = I
bllsel = 0
datall = 0

cmpll = I
bllsel = 0
datall=1

~ L<11..0>

(e) Secondary moment measurement for 8192 separate areas

(4096 x 2-area expanded system configuration)
Area number 0-2047

L<12 .. 0>

L<11..0>

\

..

Feature#O
IDEN*
L<11..0>

--

Area expansion mode
register (EXT) settings:
cmpll = I
b1lsel=0
datal I = 0

L< 12>
Area number 204 8-4095

...
..

Feature#l
IDEN*
L<11..0>

cmpll = I
bllsel=O
datal 1 = I

Area number 409 6--6143

-1)

...

Feature#2
IDEN*
L

cmpll = I
bllsel = 0
datall = 0

Area number 6144-8191

~

Feature#3
IDEN"
L

G-55

cmpll = 1
bllsel=O
datall = I

4.3.9 Sample System: Expanding the Number of Areas for Three-Way Simultaneous
Perimeter Measurement
(A) Three-way simultaneous perimeter
measurement for 2048 separate areas
(basic system configuration)

(B) Three-way simultaneous perimeter measurement for 4096
separate areas (4096-area expanded system configuration)

Area number 0-2047

Feature#O
L
--<~;====;:~ L
DL

Area number 0-2047
Area expansion mode
Feature#O
register (EXT) settings:
L
cmpll = I
bllsel = 0
-tr,;~=~~~t:J L
datall = 0
DL
zd=O
Area number 2048-4095

Area expansion mode
register (EXT) settings:
cmpll =0
bllsel =0
datal I =0
zd = 0

Feature#l
L
DL

cmpll = I
bllsel = 0
datal I = I
zd= I

(C) Three-way simultaneous perimeter measurement for 4096

separate areas (4096-area expanded system configuration)
L<12 .. 0>

-L
L

L

H

DL
1H line delay

"-

DL<12>

-

.
~
.

Area number 0-2047
Area expansion mode
Feature#O
register (EXT) settings:
L
cmpll = I
!DEN*
bllsel=O
DL
datal I = 0
DIDEN*
zd=O

Area number 204 8-4095

~
~

Feature#l
L
!DEN'
DL
D!DEN*

cmpll=1
bllsel = 0
datall=1
zd = I

Area number 4096-6143

-f'x-l.

..

~
~

Feature#2
L
!DEN'
DL
DIDEN'

cmpll = 1
bllsel = 0
datall = 0
zd= I

Area number 61 44-8191
Feature#3

~
~

G-56

L
!DEN*
DL
D!DEN*

cmpll = I
bllsel=O
datall = I
zd = 1

f>'
~

o~
.;j

L<11..0>'~'"~ffJLf1IULJlrrJLflSlJLf'
7--\,-v--v-"ff---.,~r-v-/J
LJ

f.----A---A---Aff~

j

Os-

II

II

LJ

L

FEN'~
!!i
\
-;;~--------~m--m--------------ff---------------------------ff-----------------------------------------------------------~\~1\ ,,___ ,1f--11
';. ~
~ f!rr--.l
..
.iL--ff~r----.!r---------

10<11..0>

,,'

VEN'

HEN'

Note 2

'~f,f-------ff-

BUSY'

re

ff----------(Continued below)

0"

"g .... ~

... I1l s'
po n5

~

8
Sf
aq

go~~ ~

::l p..

§......

tn·

p.. po st:+! cr"OQ
~.

~ro(")

g"
po PO'"
00 I)Q....

Y' i:!:l

~p:~

01-'00
~ 00 ~
::l >00

g,gg

.... 00
::r
I1l s
l1l ....

::l

....

'"0

>Tj

tTl

Z
,

Jf.

<
tTl

Z
"

0...

I1l
::r:
S
tTl
1ti~ Z

Z

~;
~t-ot
o

HEN'

\

~----i

BUSY'

rr

;,

aq
::l

§'I)Q

til

~.~

tTl
::l
~
a"

Note 1: When the exec flag is set to I to begin execution, it becomes internally valid two clock cycles later. After this, when a valid VEN* signal
goes low (as detected at the rise of iCLK), one clock cycle elapses, then the BUSY' signal also goes low to show that internal processing
bas begun.

...o~e:-

Note 2: HEN* must be inactive for at least two clock cycles

I1l ~
I1l ....

::F-~

...

Note 3: When field count control is in effect and a value n (~ 1) is written to the field count control register, when the nIh valid VEN* signal goes
high (as detected at the rise of iCLK), four clock cycles elapse, then the BUSY' signal also goes high to show that internal processing has ended.

During continuous histogram processing, however, BUSY* goes high when processing ends. When processing is stopped by writing 0 to the
exec flag, and the exec flag becomes internally valid two clock cycles later, BUSY' goes high to show that internal processing has ended.
Once BUSY* goes high, results can be read from results memory. though results memory cannot be written to until the following cycle.

~.

oo::r

Ssor",

SS
'"
0
sp..

o ...
'"
...

,<:'"
I)Q
p..

~.

~ ;!l.

S~

'"0

IP90C18
Features Extracting
Processor

I

t"'~

~
U'J
.....

S:-8
I1l 00

00
.... s'

CD
III

....

=:.
::l
ca
-I

t+

(1)

po 0

~

0

'lJ

3"
!f 5"
::r- ca

ere §

~ ? ...
~

£

.......

I1l

~

(Continued from above)

~

;l

a a.[

iCLK~

DL<1I..O>,

po
...

~

~

rr:
0...

0

::r

III

....

UI

Hent

2

0

4

5

6

9

7

IO

II

12

13

14

15

16

~

~

17

iCLK

f
\:j\i======~==~~~~=:~~~~~~~~~~~~~~~ I~

FEN*

~

YEN*
HEN*

~

OD<23 ..0:>

I ,

1\ Note I

BUSY*

ff-

(Continued below)
(Continued from above)
Hent

Cl

4084

4085

4086

4087

4088

4089

4090

4091

4092

4093

4094

4095

4095

4095

4095

4095

4095

4095

4095

4095

4095

iCLK

0,
()O

FEN'
VEN'
HEN'
OD<23 ..0>
BUSY'

"""

________________________________-1/ . ---. --- - - "-"""r-------------~~----------------------

,

"I Note 3
Note I: Once the exec flag is set to I, it becomes internally valid two clock cycles later. Then, when a rise of iCLK detects the change of the first
valid VEN' signal from high to low, one clock cycle elapses, then the BUSY' signal also goes low to indicate that internal processing has begun.
Note 2: The change of HEN' from high to low is detected at the rise of iCLK, and the Hcnt coordinate counter is reset. Hent then counts iCLK signals
as long as HEN' stays low. The Hcnt output value is taken as the address for results memory, and four clock cycles later data can be read
through the OD<23 .. 0> signal pin.
Note 3: When a value n ( 1) has been written to the field count control register and field count control is in effect, then beginning with the rise of iCLK
that detects the change of the nth valid YEN' signal from low to high, four clock cycles elapse, then BUSY' also goes high to indicate that internal
processing has ended.

~

~

;p.
iv

;r.~;l

'" ro ro

8"

~....,

~

",. 0"

>--1

oq
0 0
'"1 ........ _

9 ~~
;:; ~ S'

Look-Up Table Conversion Processing

~ ~

s" ::;:

S· reo s·
oq o"oq
~....
oq...,.

OD<23 .. 0>

p:~
Note 3

~

'!:>

Note 2:

ff~----------/

\ Note 1

Once the exec flag is set to 1 and becomes internally valid two clock cycles later, the BUSY' signal goes low, and data input is accepted
over L or ID. This is how data input on the cycle after BUSY' goes low becomes valid. Therefore, the value of 00<23 .. 0>
is undefined for data input up to the cycle in which BUSY' goes low.

~.

0

>~
Q::r

~o

~~

:::9
o re
......~

The delay from L
  • or ID
  • to 00<23 ..0> is four clock cycles. --.. "'"I Note 3: Once the exec flag is set to 0 and becomes internally valid two clock cycles later, BUSY' goes high, and data input is no longer accepted over L or 10<11 .. 0>. Therefore, the value of 00<23 .. 0> is undefined for data beginning with the cycle in which BUSY' goes high. ~ III ~ P. 'rj , S·'" "Ooq g.o iCLK _"0 (f \ (Note 1) / (Note 2) Note I: Once the exec flag is set to I and becomes internally valid two clock cycles later, BUSY' goes low, and cumulative histogram processing begins. Note 2: When cumulative histogram processing ends, BUSY' goes high. In 4K measurement mode, or 2K measurement mode with power-saving cumulative histogram processing, the BUSY' low period is approximately 4K cycles. In 2K measurement mode with normal cumulative histogram processing, the BUSY' low period is approximately 2K cycles. ro .... ro ~ o ...,. ::l ro < '" ro ~. ~ .... Cl S· g:. ::l § g:. ro p.9 Cl 0 9 III ~p. ~ ~ -oq ~ ~. ~.~ ro ~ i IP90C18 Features Extracting __ Processor 'f- -< t'I1 Z ,'f- ::r: zt'I1 'f- Cfl ..... ()q 9 ;:s llJ 00- O'a _"0.... .... ~ , III o 0 o?;"ro Cl Cumulative Histogram Processing BUSY' ::r ':-'" ro n t"I"j i:!l g- Z L, ID Note I: sr ()q g ~~ ~ iCLK BUSY' .... t:j ' ;J 9- 00 ~ >-' ro 0... 4.5 Processing on the Area of Interest Boundary When measuring area perimeters, the Feature chip examines 2x2-pixel local areas to find the boundary between the area containing continuous data and the background, then counts the vertical, horizontal, and diagonal perimeter lengths independently. Also, in run coordinate detection, the Feature chip looks at 2xl-pixellocal areas to find the start and run points of the run. Thus, in processing these two-dimensional local areas, the boundary of the AOI itself occasionally appears within a local area. This section describes processing on AOI boundaries. 4.5.1 Perimeter Length Measurement on the Area of Interest Boundary When measuring area perimeters, the area number (label number) is input through L<11..0>, and the area number of the previous line is input through DL<11..0>. If HEN' and VEN' are both low when data is input through L, a 2x2-pixellocal area is created from the data values input through L<11..0> and DL and from the data values input through L and DL<11 .. 0> on the previous clock cycle. This 2x2-pixel local area is then used for perimeter measurement. However, if HEN' or VEN' is high when data is input through L, perimeter measurement is not performed on the 2x2-pixellocal area created from the same data. The following diagram shows an example using a labeled input image, and the resulting measurements. The following pages show the timing charts for input through L of label value data for lines 1, 22, and 23 in the labeled image. Sample Labeled Input Image I HEN*""l '";im" V 1-", 0 1 1;1 4 10 11 Note: 2 2 3 3 6_ 6 3 3 4 4 4 Input image 4 4 : It- 10 10 9 11 11 ::1 : I:; :; 13 14 13 14 :--- area of interest 14 13 15 151 15 15' ~ (8-connection labeling) 17 7 18 8 12 13 14 15 16 17 18 19 20 21 22 23 1-1-1 1 : I:~ 1~ • 116 16 I~ 17 17 17 17 17 '-19 19-19-19 19 19 20 20 18 18 18 18 18 21-21 21 21 21 22 22 18 Numerals indicate non-background pixel label values, and dots (.) indicate background pixels (label value 0). Measurement Results Label value 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Hperi Vperi Dperi 1 0 6 0 2 0 1 2 0 2 0 2 0 2 0 2 0 0 0 1 0 0 1 0 0 0 0 2 0 0 G-60 2 1 0 0 1 0 0 0 4 0 0 0 2 2 2 0 2 0 1 0 2 0 0 0 3 0 0 0 0 0 1 0 0 0 0 0 (A) Line V =1 iCLK YEN' \ HEN' \ ~ I DL L '-----r' /---t' ---' "'--_JL_J Because the data values with the # mark lie inside the AOI, perimeter measurement is performed on the local area bounded by the dotted lines. Because the data values with the ';;;::k lie inside the AOI, perimeter measurement is performed on the local area bounded by the dotted lines, /- - ~ Because the data values with the' mark lie outside the AGI, perimeter measurement is not performed on the local area bounded by the dashed lines. (8 ) Line V = 22 iCLK I I YEN' \ HEN' DL L , '-----r' Because the data values with the # mark lie inside the AOI, perimeter measurement is performed on the local area bounded by the dotted lines. Because the data values with the % mark lie inside the AOI, perimeter measurement is performed on the local area bounded by the dotted lines. Because the data values with the' mark lie outside the ADI, perimeter measurement is not performed on the local area bounded by the dashed lines. (C) Line V = 23 iCLK YEN' HEN' DL L Because the L<11..0> input data for this line lies outside the AOI area (YEN' = high), no perimeter length measurement is performed. G-61 4.5.2 Run Coordinate Detection on the AOI Boundary When performing run coordinate detection, area numbers outside the AOI boundary (input through L<11..0» are treated as 0, the same as background values. The following diagram shows an example using a labeled input image and the resulting measurements, including timing charts. Sample Labeled Input Image ~--------------~~ HEN*l <: m [ V 0 1 2 3 4 Note: 2 2 2 3/3 3 • • 3 ~ :/: . 5 5 4 . r--- 5 Input image (8-connection labeling) ~----~~~--------------~ area of interest Numerals indicate non-background pixel label values, and dots (.) indicate backgrou'nd pixels (label value 0). (A) Line V =0 iCLK VEN* HEN* \ ' -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J/ L<11..0> RUNST* RUNEND* Note: Because the L<11..0> input data for this line lies outside the AOI (VEN* = high), no run coordinate detection is performed. (B) Line V = 1 iCLK VEN* \ HEN* ~--------------------------------------------- \~______________________________~/ L<11..0> RUNST* RUNEND* Note: Because the areas labeled 3# and 4# lie outside the AOI, they are processed as background values, and RUNST* and RUNEND* signals are output in relation to the areas labeled 3* and 4*. G-62 (C) Line V =2 iCLK VEN* ~ / \~.------------------------~ HEN* L RUNST* RUNEND* Note: Note: (D) Line V Because the area labeled 3# lies outside the AOI, it is processed as a background value, and RUNST* and RUNEND* signals are not output. RUNST* and RUNEND* signals are output in relation to the area labeled 4*, which lies inside the AOI. =3 iCLK VEN* ____________________________________________~ HEN* ~~__________________________~/ L RUNST* RUNEND* Note: Note: RUNST* and RUNEND* signals are output in relation to the area labeled 3*, which lies inside the AOI. Because the area labeled 4# lies outside the AOI, it is processed as a background value, and RUNST* and RUNEND* signals are not output. (E) Line V = 4 iCLK VEN* HEN" ~~__________________________~/ L RUNST* RUNEND* Note: Because the L<11..0> input data for this line lies outside the AOI (VEN* = high), no run coordinate detection is performed. G-63 4.6 Setup Sequences 4.6.1 Setup for Continuous Extraction of Quantitative Image Characteristics Power ON RST' signal input set low. then returns to high and remains high. Use reset register rst flag to initiate software reset: • I: to execute reset • 0: to cancel reset Use results memory to clear results memory register (aU values to 0). Write the number of clear cycles to the lower 6 bits, then set the clear flag (bit 7) to 1 to clear for the designated number of cycles. Clearing in progress Clearing ended? Verify the end of clearing through the BUSY' signal or busy flag. Set registers for operating mode according to type of measurement desired: For sample settings for various operating modes using the memory address selection register, memory data setting register, adder setting register, etc., see Section 5.3. Write 1 to the exec flag of the execute register to indicate the start of measurement processing. Perform measurement of areas designated by the IDEN', VEN', and HEN' signals. Input in progress Input data ended? After data input for measurement has ended, verify the end of internal processing by the BUSY' signal or busy flag. Write 0 to the exec flag to indicate the end of measurement. This initiates switching to allow the control bus to access results memory. Access results memory from the control bus, and read the results of measurement. L.._ _ _ _ _ _-, as well as data input through image data input pins L, DL, and ID<11..0>. Set all undefined bits to zero. At reset, all values become OOh. Register address lCh (all bits read/write enabled) Reset: OOh IOCTRL Input/Output Control Register MSB M7 dl LSB M6 M5 id M4 M3 M2 Ml MO sod! oden3! aden2! adenl! odenO! dl: Delay area number input reset flag dl = 1: Reset delay area number input data to 0 regardless of the delay area number input pins DL<11 .. 0> (Note 1) Input and process delay area number input data from dl = 0: delay area number input pins DL I: Area number input reset flag I = 1: Reset area number input data to 0 regardless of the area number input pins L (Note 1) I = 0: Input and process area number data from area number input pins L id: Grayscale value input reset flag id = 1: Reset grayscale input data values to 0 regardless of the grayscale input pins ID<11..0> (Note 1) id = 0: Input and process grayscale data from grayscale input pins ID sad: Image data output select flag This flag selects which type of data is output from image data output pins OD<23 .. 0>: sod = 1: Output coordinate data from coordinate counters sod = 0: Output read data from results memory G-103 odenO, oden1, oden2, oden3: Results output enable flags These flags determine whether the output from the image data output signal pins 00<23 .. 0> is fixed at high level or enabled. However, the drive or hi-Z signal from the OOEN* signal pin takes priority over this setting. The odenO flag controls the 8-bit signal 00<7..0>, oden1 controls the 4 bits 00<11 .. 8>, oden2 controls the 4 bits 00<15 .. 12>, and oden 3 controls the 8 bits 00<23 .. 16>. odenn = 1: Image data output is enabled odenn Note 1: 6.10 = 0: Image data output pins 00<23 ..0> are fixed at high level output (note 1) These settings are used in power-saving mode to reduce the power consumed by the chip. Each of these selections creates a logical gate on input pin routes to eliminate unnecessary switching and thereby reduce power consumption. This is also effective in controlling noise on output pins, so when a particular output pin is not used, leave the pin open or use the appropriate flags to prevent switching. Because input voltage to each input pin is not clipped at that pin's connection level, note that similar prohibitions apply to pin status that are not allowed in CMOS logic, such as input pin signals in intermediate (indeterminate) or floating state. Overflow Status Register The overflow status register reads the status of overflow conditions that occur during processing. When an overflow occurs during processing, the bit corresponding to that type of overflow is set to 1. However, if the corresponding mask flag in the overflow flag mask register has been set to 1 (masked), the overflow signal OYP* is not asserted, but remains high. Whenever any of the bits in the overflow status register is set to 1, and the corresponding mask flag is 0 (unmasked), the OYP signal is asserted (low-level output). The overflow status register must by forcibly cleared by writing 0 to it, except for hardware resets initiated by the RST* signal or software resets by the reset register. OYPSTAT Overflow Status Register Register address 20h (all bits read/write enabled) Reset: OOh MSB LSB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ovfdp ovfvp ovfhp ovfad ovfvw4K ovfvw2K ovfhw4K ovfhw2K ovfdp: Perimeter diagonal component 16-bit adder output overflow flag ovfdp = 1: Overflow ovfdp = 0: No overflow ovfvp: Perimeter vertical component 16-bit adder output overflow flag ovfvp = 1: Overflow No overflow ovfvp = 0: G-104 I ovfhp: Perimeter horizontal component 16-bit adder output overflow flag ovfhp = 1: Overflow ovfhp = 0: No overflow ovfad: Adder output overflow flag ovfad = 1: Overflow No overflow ovfad = 0: ovfvw4K: Vcnt overflow flag for vertical processing screen size in 4K area mode ovfhw4K = 1: Overflow: set when Vent exceeds FFFh ovfhw4K = 0: No overflow ovfvw2K: Vcnt overflow flag for vertical processing screen size in 2K area mode ovfhw2K = 1: Overflow: set when Vcnt exceeds 7FFh ovfhw2K = 0: No overflow ovfhw4K: Hcnt overflow flag for horizontal processing screen size in 4K area mode ovfhw4K = 1: Overflow: set when Hcnt exceeds FFFh ovfhw4K = 0: No overflow ovfhw2K: Hent overflow flag for horizontal processing screen size in 2K area mode ovfhw2K = 1: Overflow: set when Hcnt exceeds 7FFh ovfhw2K = 0: No overflow I 6.11 Overflow Flag Mask Register The overflow mask register contains bits that can be set to 1 to mask the overflow signal OVF* in the event of overflows of particular types. Thus, when an overflow occurs of a type that corresponds to a given bit in the overflow flag mask register and that bit is set to 1 (masked), the corresponding flag in the overflow status register is set to 1 to indicate the overflow, but the overflow signal OVF* is not asserted and remains high. Set all undefined bits to zero. At reset, all values become OOh. Register address 24h (all bits read/write enabled) Reset: OOh OVFMASK Overflow Flag Mask Register LSB MSB bit 7 movfdp: bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Perimeter diagonal component 16-bit adder output overflow mask flag movfdp = 1: Masked movfdp = 0: Unmasked G-105 BII~ movfvp: Perimeter vertical component 16-bit adder output overflow mask flag movfvp = 1: Masked Unmasked movfvp = 0: movfhp: Perimeter horizontal component 16-bit adder output overflow mask flag movfhp = 1: Masked movfhp = 0: Unmasked movfad: Adder output overflow mask flag movfad = 1: Masked Unmasked movfad = 0: movfvw4K: Vcnt overflow mask flag for vertical processing screen size in 4K area mode movfhw4K = 1: Masked Unmasked movfhw4K = 0: movfvw2K: Vcnt overflow mask flag for vertical processing screen size in 2K area mode movfvw2K = 1: Masked Unmasked movfvw2K = 0: movfhw4K: Hcnt overflow mask flag for horizontal processing screen size in 4K area mode Masked movfhw4K = 1: Unmasked movfhw4K = 0: movfhw2K: Hcnt overflow mask flag for horizontal processing screen size in 2K area mode Masked movfhw2K = 1: Unmasked movfhw2K = 0: G-I06 6.12 Results Memory Clear Register The results memory clear register clears the contents of results memory. This differs from hardware resets initiated by the reset signal (RST*) or software resets from the reset register, in that no registers other than results memory are cleared. Set all undefined bits to zero. At reset, all values become OOh. Register address 28h (all bits read/write enabled) Reset: OOh CLRmem Results Memory Clear Register LSB MSB bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 I CLRexec I 0 CLRS CLR4 CLR3 CLR2 CLR1 CLRO CLRexec: Results memory clear flag This flag clears the contents of results memory. After CLRexec is set, results memory is cleared for the number of clock cycles specified in bits CLRO-CLR5. After results memory is cleared, CLRexec is automatically reset to O. Clearing can be stopped while in process by writing 0 to the results memory clear flag, but this can affect the accuracy of the contents of results memory. The results memory clear flag differs from the soft reset flag rst in that it does not clear other registers. CLRexec = 1: Clear results memory CLRexec = 0: Cancel clearing of results memory, or end automatically CLRO-CLR5: Results memory clear cycle selection flags Clearing results memory takes one microsecond, so this register must designate the number of image clock cycles that elapse in a microsecond. After the designated number of clock cycles is counted (and thus a microsecond elapses), the results memory clear flag CLRexec is reset to 0 and the clearing process canceled. Note, however, that using a results memory clearing function with the value 0 in all bits CLRO-CLR5 represents a special case, and causes the clearing process to be executed for 64 clock cycles, just as if the register had been set to the decimal value 64. For example, at 40 MHz, the Feature chip's maximum operating frequency, 40 clock cycles are required to provide the minimum of one microsecond needed to clear the register. Therefore, the bits CLRO-CLR5 would be set to the equivalent of the decimal value 40 (28h). Even with CLRO-CLR5 at their reset values of OOh, the memory clear time is 1.6 microseconds. Also, if the operating frequency is 12.5 MHz, memory clears in 5.12 microseconds at the default reset value of OOh. To set the minimum clearing time, write the equivalent of the decimal value 13 (ODh) to bits CLRO-CLR5. In the absence of critical factors such as clock delays from line sensors or scanners, or stopping of clock counts, it is generally best to use the default setting of OOh. G-107 6.13 Field Count Control Register The field count control register establishes controls over execution based on the number of fields processed. If this register is used, the necessary settings must be entered before setting the exec bit. After a reset, all values are OOh. Note that because labeled image data is the input for several processes (including circumscribed rectangle diagonal coordinate measurement, area boundary onepoint coordinate measurement, primary moment measurement, secondary moment measurement, and perimeter length measurement), these processes deal with non-interlaced images: therefore two-field processing settings have no meaning. FLD Field Count Control Register Register address 2Ch (all bits read/write enabled) Reset: OOh MSB LSB ~7 ~6 ~S ~4 ~3 ~2 ~l ~O fld7 fld6 fldS fld4 fld3 fld2 fldl fldO fldO-fld7: Field count flag set The field control register consists of flags that designate a number of fields that are counted using the processed field count control circuit. The MSB is fld7 and the LSB is fldO, and together the eight flags control the field count (from Olh to FFh). Note that if the fld flags are set to OOh, processed field count controls are not applied. When any bit in the field count control register (n 0) is set to 1 and the exec flag is set to 1 execute processing, the chip performs feature extraction processing for the duration of the designated number (n) of fields only, that is, for n periods in which the VEN* signal remains active (at low level). When these n fields are processed, the exec flag automatically clears to O. When 0 is written to the field count control register and then 1 is written to the exec flag to execute processing, processing field controls are not applied, and processing continues until 0 is written to the exec flag. * G-I08 6.14 Constant Register The constant register contains 48 bits and is used to represent the value of an external signal as a constant value. For example, using constants from the constant register to weight grayscale values for cumulative weighted grayscale measurement by area makes it possible to measure the number of pixels in each area. In this case, using the value 1 from the constant register produces normal histogram processing. In cumulative histogram processing, the fields near the end are sometimes given increased weightings. This technique can be used to create a time axis in a histogram of multiple fields, by adding a smaller weight from the constant register to the fields that are input first, then using increasingly larger weightings up to the last field to be input. This can also be used in measuring moving images to weight the most recent measurements. The illustration below shows the address mapping of the constant register, in which the lowest 24 bits (CO-C23) are in address 30h-32h, and the highest 24 bits (C24-C47) are divided between address 34h-36h. This mapping arrangement allows for the writing of values from a 24-bit bus; however, in normal image measurement the higher 24 bits are seldom written, so there is no difficulty in using a 16-bit control bus. (all bits read/write enabled) Reset: OOOOOOOOOOOOh CONST Constant Register (48-bits) MSB address 37h 00 6.15 LSB 36h 35h 34h I C47..40 I C39 .. 32I C31..24 I 33h 32h 31h 30h 00 I C23.. 16I C15 .. 8 C7 .. 0 Origin Area Number Register The origin area number register stores the number of the area that contains the origin (0, 0) located at the upper left corner of the image being measured. Use the area number assigned to the origin when extending processing areas for software processing, as well as for identifying the area assigned to the origins for area boundary one-point coordinate measurement. In area boundary onepoint coordinate measurement, the one-point coordinate result in results memory can be 0 when the area containing the origin is measured. The origin area number register provides a means of distinguishing a processing result of 0 from a 0 remaining from the last memory clear cycle. Values in this register are reset to LBLOO Origin Area Number Register address ~Oh. (all bits read-only) Reset: OOh 39h 38h MSB bit 11 bit 10 LSB bit 9 bit 8 bit 7 Ib8 Ib7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Origin area number value lb (lbO-Ib11): This field holds the area number of the area containing the first pixel (0, 0) in the effective input image. G-109 I I 6.16 LSI Internal Test Registers These registers are used to test the Feature chip before shipment, and should not be used for normal operation. Set all bits to 0, or leave them with DOh after a reset. If a 1 is written to any bits in this register, the chip enters test mode and may not function normally. TES1M1 LSI Internal Test Register 1 (all bits read/write enabled) Reset: DOh MSB LSB ~7 ~6 ~5 ~4 ~3 ~2 ~1 ~O Register address: 3Ch TES1M2 LSI Internal Test Register 2 (all bits read/write enabled) Reset: DOh MSB LSB ~7 T7 ~6 I T6 I ~5 ~4 ~3 ~2 ~1 ~O T5 T4 T3 T2 T1 TIl Register address: 3Dh 6.17 Results Memory Address Maps In 2K or 4K area measurement mode, the configuration of results memory as seen from the CPU interface is 4096 words x 24-bits. AD13-AD2 00 0000 0000 00 00 0000 0000 01 000000000010 00 0000 0000 11 00 0000 0001 00 10 ADl-ADO 01 b23 b16 00 0000 0000 00 10 00 0000 0000 01 10 00000000001010 00 0000 0000 11 10 00 0000 0001 00 10 b15 b8 00 0000 0000 00 01 00000000000101 00 0000 0000 10 01 00 0000 0000 11 01 0000000001 00 01 00 b7 bO 00 0000 0000 00 00 00 0000 0000 01 00 00 0000 0000 10 00 00 0000 0000 11 00 00 0000 0001 00 00 111111111110 01 111111111111 01 MIddle 8 bIts 111111111110 00 111111 111111 00 Low 8 bIts -. 111111111110 111111111111 111111 1111 10 10 11111111111110 HIgh 8 bIts G-110 8-bit access (BUSW1 = 1, BUSWO = 0) Control address bus Data bus DB23-DB16 DB15-DB8 DB7-DBO 0 High-Z (Note 1) High-Z (Note 1) Low 8 bit 0 1 High-Z (Note 1) High-Z (Note 1) Middle 8 bit 1 0 High-Z (Note 1) High-Z (Note 1) High 8 bit High-Z (Note 1) High-Z (Note 1) OOh constant ADl ADO 0 1 Note 1: 1 DB23-DB8 should be pulled up or pulled down. 16-bit access (BUSW1 = 0, BUSWO = 1) Control address bus DB23-DB16 DB15-DB8 DB7-DBO * High-Z (Note 2) Middle 8 bit Low 8 bit * High-Z (Note 2) OOh High 8 bit ADl ADO 0 1 *. Note 2: Data bus Ignored DB23-DB16 should be pulled up or pulled down. 24-bit access (BUSW1 = 0, BUSWO = 0) Control address bus *. Data bus ADl ADO DB23-DB16 DB15-DB8 DB7-DBO * * High 8-bit Middle 8 bit Low 8 bit Ignored G-111 6.18 Results Data Storage Formats This section shows the formats used to store various types of image-processing results in results memory. 6.18.1 Circumscribed Rectangle Diagonal Coordinate Measurement Results 6.18.1.1 Results of Lower-Left, Upper-Right Simultaneous Coordinate Measurement (2K area measurement mode) Word bit 6.18.1.2 Measurement results VI Address ADn+6 I I va HI ADn+5 WDn 12111 24 23 I ADn+4 ADn+2 a I I HO ADn+l I ADn Results of Measurement of Lower-Left Coordinate Only (4K area measurement mode) Word bit WDn 23 Address a 12111 va Measurement results 6.18.1.3 WDn+l 36135 47 J HO ADn+2 I ADn+l I ADn Results of Measurement of Upper-Right Coordinate Only (4K area measurement mode) Word bit WDn 23 a 12111 Measurement results VI Address ADn+2 I J HI ADn+l I ADn 6.18.2 Area Boundary One-Point Coordinate Measurement Results Word bit WDn 12111 23 Measurement results Va Address ADn+2 I a J Ha ADn+l I ADn 6.18.3 Perimeter Length (Three-Direction Simultaneous) Measurement Results Word bit Measurement results Address WDn WDn+l a a 24 23 47 47 32 31 Dperi ADn + 6 I ADn + 5 G-112 16 15 Vperi ADn+4 I ADn+2 Hperi ADn + 1 I ADn 6.19 Detailed Sample Address Maps for Measurement Results Data 6.19.1 Circumscribed Rectangle Diagonal Coordinate Measurement Results 6.19.1.1 Results of Lower-Left, Upper-Right Simultaneous Coordinate Measurement (2K area measurement mode) ADI to ADO 10 6.19.1.2 AD13 to AD2 b23 - - - - - - b16 blS - - - - - b12 01 b11 - - - - - - b8 00 b7 - - - - - - bO Area number 00 0000 0000 00 va high 8 bits va low 4 bits HO high 4 bits HO low 8 bits OOOh 00 0000 0000 01 VI high 8 bits VI low 4 bits HI high 4 bits HI low 8 bits 00 0000 0000 10 va high 8 bits va low 4 bits HO high 4 bits HO low 8 bits 00 0000 0000 11 VI high 8 bits VI low 4 bits HI high 4 bits HI low 8 bits 0111111111 11 VI high 8 bits VI low 4 bits HI high 4 bits HI low 8 bits 3FFh 10 0000 0000 00 10 0000 0000 01 va high 8 bits va low 4 bits VI low 4 bits HO low 8 bits HI low 8 bits 400h VI high 8 bits HO high 4 bits HI high 4 bits 11 1111 111110 11 1111 1111 11 va high va low 4 bits HO high 4 bits HI high 4 bits HO low 8 bits HI low 8 bits 7FFh 8 bits VI high 8 bits VI low 4 bits 001h Results of Measurement of Lower-Left Coordinate Only (4K area measurement mode) ADI to ADO AD13 to ADZ 00 0000 0000 00 00 0000 0000 01 00 0000 0000 10 00 0000 0000 11 01 11111111 11 10 0000 0000 00 10 0000 0000 01 11 1111111110 11 1111 111111 10 01 bZ3 - - - - - - b 16 blS - - - - - bIZ b11 - - - - - - b8 00 b7 - - - - - - bO va high 8 bits va high 8 bits va high 8 bits va high 8 bits Area number va low 4 bits va low 4 bits va low 4 bits va low 4 bits HO high 4 bits HO low 8 bits OOOh HO high 4 bits HO low 8 bits 001h HO high 4 bits HO high 4 bits HO low 8 bits HO low 8 bits 002h 003h va high 8 bits va low 4 bits va high 8 bits va low 4 bits va high 8 bits va low 4 bits HO high 4 bits HO low 8 bits 7FFh HO high 4 bits HO high 4 bits HO low 8 bits HO low 8 bits 800h va high 8 bits va low 4 bits va high 8 bits va low 4 bits HO high 4 bits HO low 8 bits FFEh HO high 4 bits HO low 8 bits FFFh G-113 801h 6.19.1.3 Results of Measurement of Upper-Right Coordinate Only (4K area measurement mode) AD13 to AD2 ADI to ADO 10 01 b23 - - - - - - b16 b15 - - - - - b12 b11 - - - - - - b8 00 b7 - - - - - - bO 00 0000 0000 00 00 0000 0000 01 00 0000 0000 10 00 0000 0000 11 VI VI VI VI HI HI HI HI 011111111111 10 0000 0000 00 10 0000 0000 01 VI high 8 bits VI high 8 bits VI high 8 bits VI low 4 bits VI low 4 bits VI low 4 bits 111111111110 111111111111 VI high 8 bits VI high 8 bits VI low 4 bits VI low 4 bits high high high high 8 8 8 8 bits bits bits bits VI VI VI VI low low low low 4 bits 4 bits 4 bits 4 bits 8 bits 8 bits 8 bits 8 bits OOOh 001h 002h 003h HI high 4 bits HI high 4 bits HI high 4 bits HI low 8 bits HI low 8 bits HI low 8 bits 7FFh 800h 801h HI high 4 bits HI high 4 bits HI low 8 bits HI low 8 bits FFEh FFFh HI HI HI HI high high high high 4 bits 4 bits 4 bits 4 bits low low low low Area number 6.19.2 Area Boundary One-Point Coordinate Measurement Results (4K area measurement mode) AD13 to AD2 ADI to ADO 10 01 b23 - - - - - - b16 b15 - - - - - b12 b11 - - - - - - b8 00 b7 - - - - - - bO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 Va Va Va Va Ha Ha Ha Ha 00 01 10 11 high high high high 8 8 8 8 bits bits bits bits Va Va Va Va low low low low 4 bits 4 bits 4 bits 4 bits Ha Ha Ha Ha high high high high 4 bits 4 bits 4 bits 4 bits low low low low 8 8 8 8 Area number bits bits bits bits OOOh 001h 002h 003h 011111111111 100000 0000 00 10 0000 0000 01 Va high 8 bits Va high 8 bits Va high 8 bits Va low 4 bits Va low 4 bits Va low 4 bits Ha high 4 bits Ha high 4 bits Ha high 4 bits Ha low 8 bits Ha low 8 bits Ha low 8 bits 7FFh 800h 801h 111111111110 11 1111111111 Va high 8 bits Va high 8 bits Va low 4 bits Va low 4 bits Ha high 4 bits Ha high 4 bits Ha low 8 bits Ha low 8 bits FFEh FFFh G-114 6.19.3 Perimeter Length (Three-Direction Simultaneous) Measurement Results (2K area measurement mode) AD13 to AD2 ADl to ADO 01 10 b23 - - - - - - - - b16 b15 - - - - - - - - - b8 00 0000 0000 00 000000000001 00 0000 0000 10 00 0000 0000 11 Vperi low 8 bits Dperi high 8 bits Vperi low 8 bits Dperi high 8 bits 011111111111 100000000000 10 0000 0000 01 Dperi high 8 bits Dperi low 8 bits Vperi high 8 bits Vperi low 8 bits Hperi high 8 bits Hperi low 8 bits Dperi high 8 bits Dperi low 8 bits Vperi high 8 bits 3FFh 400h 111111111110 111111111111 Vperi low 8 bits Hperi high 8 bits Hperi low 8 bits Dperi high 8 bits Dperi low 8 bits Vperi high 8 bits 7FFh Hperi high 8 bits Dperi low 8 bits Hperi high 8 bits Dperi low 8 bits G-115 00 b7---------bO Hperi Vperi Hperi Vperi low 8 bits high 8 bits low 8 bits high 8 bits Area number OOOh OOlh 6.19.4 Grayscale Projection Processing Results 6.19.4.1 Two-Axis Simultaneous Projection Measurement Results (Normal measurement) The address map below applies to results data from two-axis simultaneous projection processing when the disVcnt flag in the mode register is set to O. The results of vertical projection processing (H-axis projection) are stored in addresses OOOOh-lFFFh, and the results of horizontal projection processing (V-axis projection) are stored in addresses 2000h-3FFFh. When processing multiple fields using processing field count controls, each address stores the cumulative sum of grayscale values from the corresponding row/column of the number of fields processed. AD1 to ADO 10 AD13toAD2 01 00 b23 - - - - - - - - b16 b15 - - - - - - - - - b8 b7 - - - - - - - - - - bO Coordinate value 00 0000 0000 00 h= OOOh 00 0000 0000 01 h=OO1h 00 0000 0000 10 h= OOZh 00 0000 0000 11 h=003h 011111111111 h= 7FFh 10 0000 0000 00 v= OOOh 10 0000 0000 01 v = 001h H-axis projection results V-axis projection results 111111111110 v = 7FEh 111111111111 v= 7FFh G-1l6 6.19.4.2 Two-Axis Simultaneous Projection Measurement Results (Field-By-Field Measurement) The address map shown below applies to results data from two-axis simultaneous projection processing when the disVcnt flag in the mode register is set to 1. The results of vertical projection processing (H-axis projection) are stored in addresses OOOOh-1FFFh, and the results of horizontal projection processing (V-axis projection) are stored in addresses 2000h-3FFFh. When processing multiple fields using processing field count controls, the H-axis projection results contain the cumulative sum of grayscale values for each column of the number of fields processed. The V-axis projection results, however, are stored by individual field, as shown below. This is because the start points of the second and all subsequent fields are not reset by the vertical coordinate counter Vcnt when the disVcnt flag is set to 1. ADI to ADO 01 00 b23 - - - - - - - - b16 blS---------b8 b7----------bO Coordinate value 10 AD13toAD2 00 0000 0000 00 00 0000 0000 01 00 0000 0000 10 00 0000 0000 11 h=OOOh h = 001h h= 002h h= 003h 011111111111 10 0000 0000 00 10 0000 0000 01 H-axis projection results h= 7FFh V=OOOh} v = 001h • · 1st field v =xxxh V=OOOh} v = 001h · 2nd · field v =xxxh V=OOOh} v = 001h · 3rd • 111111111111 G-117 field V-axis projection results 6.19.4.3 Vertical One-Axis Projection Processing Results (4K area measurement mode) AD13 to AD2 ADl to ADO 10 01 b23 - - - - - - - - b16 blS - - - - - - - - - b8 00 b7---------bO Area number 00 0000 0000 00 00 0000 0000 01 00 0000 0000 10 00 0000 0000 11 h h h h = OOOh = 001h = 002h = 003h 011111111111 100000000000 10 0000 0000 01 h h h = 7FFh = 800h = 801h 111111111110 111111111111 h h = FFEh = FFFh 6.19.4.4 Horizontal One-Axis Projection Processing Results (Normal measurement, 4K area measurement mode) The address map below applies to results data from one-axis projection processing in the horizontal direction only (V-axis projection only) when the disVcnt flag in the mode register is set to O. When processing multiple fields using processing field count controls, each address contains the cumulative sum of grayscale values from the corresponding row of the number of fields processed. This is because the start points of the second and all subsequent fields are reset by the vertical coordinate counter Vcnt when the disVcnt flag is set to O. ADl3 to AD2 ADl to ADO 10 01 b23 - - - - - - - - b16 blS---------b8 00 b7---------bO Area number 00 0000 0000 00 00 0000 0000 01 000000000010 00 0000 0000 11 v = OOOh v = OOlh v = 002h v = 003h 011111111111 10 0000 0000 00 10 0000 0000 01 v = 7FFh 111111111110 111111111111 v = FFEh v = FFFh v v G-118 = 800h = 801h 6.19.4.5 Horizontal One-Axis Projection Processing Results (Field-By-Field Measurement, 4K Area Measurement Mode) The address map below applies to results data from one-axis simultaneous projection processing in the horizontal direction only (V-axis projection) when the disVcnt flag in the mode register is set to 1. When processing multiple fields using processing field count controls, the results are stored by field as shown below. This is because the start points of the second and all subsequent fields are not reset by the vertical coordinate counter Vcnt when the disVcnt flag is set to 1. ADI to ADO 01 10 AD13toAD2 00 b23--------bI6 blS - - - - - - - - - b8 b7----------bO Coordinate value 00 0000 0000 00 v =OOOh 00 0000 0000 01 v=OO1h 1st field v = xxxh v = OOOh v=OO1h 2nd field v = xxxh v = OOOh v = 001h 3rd field v = xxxh 111111111111 G-119 6.19.5 Measurement Results Using the 24/4S-bit Adder Measurement processes using the 24/4S-bit adder (in which output from the 24/4S-bit adder is designated as data input to results memory) include cumulative grayscale value processing by area, histogram processing, primary moment measurement, secondary moment measurement, perimeter measurement in one-direction mode, and grayscale projection processing. The address maps for measurement data from these processes are shown below, for 4K area measurement mode and 2K area measurement mode respectively. (For grayscale projection processing, see also Section 6.19.4, "Grayscale Projection Processing Results.") 6.19.5.1 4K Area Measurement Mode AD13 to AD2 6.19.5.2 ADl to ADO 10 01 b23 - - - - - - - - b16 b15 - - - - - - - - - bS 00 b7---------bO Area number 00 0000 0000 00 00 0000 0000 01 000000000010 00 0000 0000 11 OOOh 001h 002h 003h 011111111111 10 0000 0000 00 10 0000 0000 01 7FFh SOOh SOlh 111111111110 111111111111 FFEh FFFh 2K Area Measurement Mode ADl3 to AD2 ADl to ADO 10 01 b23 - - - - - - - - b16 b15 - - - - - - - - - bS 00 b7---------bO Area number 00 0000 0000 00 00 0000 0000 01 00 0000 0000 10 00 0000 0000 11 Low 24-bits High 24-bits Low 24-bits High 24-bits 011111111111 10 0000 0000 00 10 0000 0000 01 High 24-bits Low 24-bits High 24-bits 3FFh 400h 111111111110 111111111111 Low 24-bits High 24-bits 7FFh G-120 OOOh 001h Section 7: External Dimensions 7.1 160-pin Plastic QFP Package 30.80-32.15 28.0 ± 0.10 ,~ ~~~~~~~ ~~~~~~~~~ ~~~I~ ~~~~~~~~~~~~ ~~~~~~~ I +-+-------.--- ~INDEX --- rDetail-A- 4.0'7.'max-.--'-----------:/"..:..---,', ,: , 1.350-2.125 j 0.88 ± 0.15 Detail-A- G-121 -' , Units:mm 3.42 ± 0.25 ~ , Section 8: Electrical Characteristics 8.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Vdd -0.3 to 6.0 V Input voltage Vi -0.3 to Vdd + 0.3 V Input current Ii ±1O rnA Supply voltage 10 10 rnA Operating temperature Topt o to 70 °C Storage temperature Tstg -10 to 80 °C Output current 8.2 Recommended Operating Conditions (GND = 0 V, Ta = 0 to 70°C) Parameter Symbol Condition Power-supply voltage Vdd High-level input voltage Vih Low-level input voltage Vii High-level threshold voltage Low-level threshold voltage Input rise time Tri Tfi Input rise time Tris Input fall time Tfis Typ. Max. Unit 4.75 5.0 5.25 V 2.0 - Vdd V 0 - 0.8 V Schmitt input Vdd = 4.75 V 2.5 (Note 1) Vdd = 5V, Ta = 25°C Vil- Input fall time Note 1: 8.3 Vih+ TTL level, normal input Min. 3.2 V - 3.1 - V Vdd = 5.25 V 3.0 - 3.7 V Vdd = 4.75 V 1.2 - 1.9 V Vdd = 5V, Ta = 25°C - 1.7 - V Vdd = 5.25 V 1.5 2.3 V 100 ns 0 - 100 ns 0 - 1000 ns 0 - 1000 ns TTL level, normal input 0 Schmitt input (Note 1) The Schmitt input pins are the RST* and TEST* pins. Input/Output Pin Capacitance (Vdd = Vi = 0 V) Parameter Symbol Condition Min. Typ. Max. Unit Input pins Cin f=lMHz - 10 - pF Output pins Cout f=lMHz - 10 pF I/O pins Cin f=lMHz - 10 - G-l22 pF 8.4 DC Characteristics Vdd = 5 V±5% Ta = 0 to 70°C GND = OV Parameter Symbol Static power consumption (Note 1) Ii Output short circuit current (all output and I/O pins) (Note 2) los Condition = Vdd or GND Vdd = Max, Vo = Vi Min. Typ. Max. Unit - - 200 !lA 15 50 200 rnA -5 -25 -100 rnA Vdd Vdd = Max, Vo = 0 V Low level input leak current -10 ±1 10 Vi = GND = GND -140 - -410 !lA !lA lih Vi = Vdd -10 ±1 10 !lA Low-level output voltage Vol 101 - - 0.4 V High-level output voltage Voh Ioh 2.4 - - V Schmitt hysteresis voltage Vsch 0.9 - - V - 1.4 - V 1.5 - - V Normal I/O pins IiI Vi Pins with pull-up resistance (Note 3) lipl High-level input leak current (all input and I/O pins) (Note 4) Note Note Note Note 1: 2: 3: 4: = 8 rnA = 8 rnA Vdd = 4.75 V Vdd = 5 V, Ta = 25°C Vdd = 5.25 V Excluding static current dissipation to pull-up resistors. Output short current is for one second or less, applied only to one LSI pin at a time. Pins with pull-up resistance are the RST*, TEST*, and DL<11..0> pins. The Schmitt input pins are the RST* and TEST* pins. G-l23 8.5 AC Characteristics All specifications in this section assume a load capacity of 30 pF on all output pins. a) Data timing at frame start point , tcphw, ~tcyc~,~ I 'I I Image clock iCLK Image data input L<11..0>, DL<11..0>, ID<11..0> I Unknown Value :.. tves --';'tveh': , FEN* ~ , I ' i~------T--------------------------------------------1------. (Note 1) : , : I I . ~~~ VEN* (Note 2) \ I I Note 1: Note 2: Note 3: \ V- I I........ : I ithh:j ~ths., HEN * (Note 3) , ~~ ~ ~,------------------------------------------------~V The start of a field is recognized when the change (assertion) of the VEN* signal from high to low is detected at the rise of iCLK. Each field defined by a VEN* signal can be enabled or disabled by the FEN* signal. If FEN* is low one clock cycle before the assertion of the VEN* signal is detected, the field defined during that assertion of VEN* is enabled for execution and processing. If, on the other hand, FEN' is high one clock cycle before the assertion of VEN' is detected, that VEN* assertion is disabled, and execution must wait for the start of the next enabled field. During a disabled VEN* assertion cycle, FEN* can be high or low, but will not be referred to again until immediately before the entry of the next field. In this sense, the field enable/disable decision is not made while data for the field is being input. VEN* must remain high for at least five clock cycles before the next synchronous input. HEN* must remain high for at least two clock cycles before the next synchronous input. G-124 units: ns IP90C18-HS IP90C18 Symbol Min. Typ. Max. Min. Typ. Max. tcyc 25.0 - - 50.0 - - iCLK signal high time tcphw 9.0 - - 20.0 - - iCLK signal low time tcpJw 9.0 - - 20.0 - Image data L<11..0>, DL<11..0>, 10<11..0> setup time tis 8.0 - - 10.0 - - Image data L<11..0>, DL<11..0>, 10<11..0> hold time tih 3.0 - - 3.0 - - FEN* signal setup time tves 8.0 - - 10.0 - - FEN* signal hold time tveh 3.0 - 3.0 - VEN* signal setup time tvs 8.0 - - 10.0 VEN* signal hold time tvh 3.0 - - 3.0 - - ths 8.0 - - 10.0 - - thh 3.0 - - 3.0 - - Item iCLK signal cycle time HEN* signal setup time HEN* signal hold time G-125 - b) Im.age data input control system timing ,-------\'--_--1, ~I foII!..f - - - - - tcyc iCLK -' \ I I, 1 1 ~tis~tih_.: 1 , Image data L<11..0>, DL<11..0>, ID Invalid Po~ition : Valid Position U = Unknown value 1 teh 1 teh foIIl ..r _ _ - - tes ---~....r---I~~I.. 4----tes ---"~"'i"I----i~~! Process control signals IDEN*, DIDEN* ~!1\ i.. i Y.',~-------+i~L' Data Enable,. Data Disable' 1 ~----------~I--~ I I i r.-tbd~ BUSY* , i I : 1 ------------------~t I 1 i,.. tovd~1, L OVF* I units: ns IP90C18-HS Item IP90C18 Symbol Min. Typ. Max. Min. Typ. Max. tcyc 25.0 - 50.0 - - Image data L<11..0>, DL<11..0>, ID<11..0> setup time tis 8.0 - - 10.0 - - Image data L<11..0>, DL<11..0>, ID<11..0> hold time tih 3.0 - - 3.0 - - IDEN*, DIDEN* signal setup time tes 8.0 - - 10.0 - - IDEN*, DIDEN* signal hold time teh 3.0 - - 3.0 - BUSY* signal delay time tbd 3.0 - 20.0 3.0 OVF* signal delay time tovd 3.0 - 20.0 3.0 - iCLK signal cycle time G-126 25.0 25.0 c) Measurement results output control system timing iCLK ,tod, I~ ~toed~ ,toez, ~ J - - - - -__ ,-----'-__ : OD<23 .. 0> - - - - - - ' - - - - { OD(m+l,n) \1...---.-,_ _----'I ODEN* , : trsd ' ~ RUNST* , \\.--: ~I ' _ _---11 , , tred , RUNEND* ~ ,;r-i~\'---_ _ \ units: ns IP90C18-HS IP90C18 Symbol Min. Typ. Max. Min. Typ. Max. Delay from ODEN* signal fall to image data output OD<23 ..0> enable toed - - 15.0 - - 20.0 Delay from ODEN* signal rise to image data output OD<23 .. 0> disable toez - - 15.0 - - 20.0 OD<23 .. 0> delay tod 3.0 20.0 3.0 - 25.0 RUNST* signal delay trsd 3.0 20.0 3.0 tred 3.0 20.0 3.0 - 25.0 RUNEND* signal delay - Item G-127 25.0 d) CPU interface system timing Write Cycle CS* ~ ~ : ' 1 . \ \ I , :' / C -_ __ 1 ".....---twrhw---~~: 1 . ~~twrJwiJ WR* tnvs . ~ RD' (Note 1) :~ ~trwh j: : taws 1 I, ~l" ~, ~ . ~tawh AD(m) :X 1 ~-r----rl~, , 1 Unknown X AD(n) L -_ _ _ __ _ tdbh , .-tdbs~ DB<23 .. 0> Unknown l::X DB(:m) 1 Unknown X DB(n) ' ~ tbwws -.i BUSWO,l ~X ~tbwWh': ===XL;____B_U_S_W_(m_)_ _ _~:XL---------units: ns Symbol Min. Typ. Max. CS* signal setup time (from WR* fall) tcws 20.0 CS* signal hold time (from WR* rise) tcwh 3.0 RD* signal setup time (from WR' fall) trws 3.0 RD' signal hold time (from WR' rise) trwh 3.0 WR* signal low pulse width twrh 20.0 ------ WR* signal high pulse width tWlW 15.0 -- ------- AD<13 ..0>, R/M* setup time (from WR* fall) taws 20.0 -- -- AD<13 .. 0>, RIM' hold time (from WR* rise) tawh 3.0 -- -- DB<23 .. 0> setup time (from WR* rise) tdbs 24.0 DB<23 .. 0> hold time (from WR* rise) tdbh 3.0 BUSWO, 1 setup time (from WR* fall) ~wws 50.0 BUSWO, 1 hold time (from WR* rise) ~wwh 20.0 ----- ----- Item G-128 Read Cycle , I I tcrh , \: " I I i I: ~~twrs ~ ~tcrs CS' WR* ~ I 7:i Note 1 i i I I AD(m) i ~trdd~ I tdbd : i ~ _N_ote_2 _----;:_<\\~ , =:x ~x Unknown X AD(n) i I ~tdbz* DB\m) :)c----<@.,, --U-nkn-ow-n---1i~~ BUSWO, I \'------ ~trdW:J RD' DB<23 .. 0> :/ I twrh ' x,-------- ~, tbwrh BUSW(m) While the WR* signal is low, the RD* signal should be high. Make sure both signals are never low at the same time. Similarly, when the RD* signal is low, the WR* signal should be high. The above illustrations are for 24-bit access (BUSWO = BUSW1 = 0). For 16-bit access (BUSWO = 1, BUSW1 = 0), signal pins DB<15 .. 0> are in output status, and BS<23 .. 16> are in high impedance status and should be internally pulled up or pulled down. For 8-bit access (BUSWO = 0, BUSW1 = 1), signal pins DB<7.. 0> are in output status, and DB<23 .. 8> are in high impedance status and should be internally pulled up or pulled down. units: ns Symbol Min. Typ. Max. CS* signal setup time (from RD* fall) Item tcrs 20.0 - CS* signal hold time (from RD* rise) tcrh 3.0 - WR* signal setup time (from RD* fall) twrs 3.0 - 45.0 - 16.0 - 16.0 WR* signal hold time (from RD* rise) twrh 3.0 RD* signal low pulse width trdw 25.0 AD<13 .. 0>, R/M* setup time (from RD* rise) tars 20.0 AD<13 ..0>, R/M* hold time (from RD* rise) tarh 3.0 Delay until DB<23 ..0> enabled (from AD<13 .. 0>, R/M* signal) tdbd - Delay until DB<23 .. 0> enabled (from RD* fall) trdd tdbz - BUSWO, 1 setup time (from RD* fall) tbwrs 50.0 BUSWO, 1 hold time (from RD* rise) tbwrh 20.0 Delay until DB<23 .. 0> high-Z state (from RD* rise) G-129 - - L22~. --- e) Reset system timing iCLK RST* Note: The reset signal input cycle must be at least three clock cycles long. The internal circuits are reset when a low-level RST* signal is detected at the rising edge of two successive clock cycles. The reset condition is canceled three clock cycles after the rise of RST* is detected at the rise of iCLK. units: clock cycles Item RST* signal low pulse width Note: Symbol Min. Typ. Max. trsw 3.0 - - The system reset function is enabled when RST* is low (asserted) for two clock cycles. The reset condition is released three clock cycles after the rise of RST* is detected at the rise of iCLK. G-l30 Section 9: Sample Applications and Reference Materials 9.1 Detecting Defective or Missing Objects Using Binary Image Area Measurement Image bus Histogram module I bit Using 2 entries only Measurement results AO Al Sample Applications Defects in shape, surface flaws, and missing items or pieces can be detected by using surface area measurement and comparing the results with a standard. o (Acceptable item) (Defective or missing item) 1 count: n-m The 1 count is decreased by the surface area of the defective or missing piece. G-131 9.2 Surface Area Measurement of Labeled Images The surface areas of multiple labeled images can be obtained by using histogram processing to find how often each label value occurs in the whole image (by performing a pixel count for each area). Histogram Module G V ~ Sn ~ Sl S2 GD8 S3 !!, Measurement results Sn-l Sn: number of pixels in each labeled area Sn Sample Applications This procedure can be used for analyzing metal composition or particles in liquid solution, counting spherical objects, or eliminating noise by using a threshold area value, as shown below. Labeled images Image after noise reduction (100) a a (500) C) ~ C:J (300) (500) Histogram Module ~ C:J I (300) (200) 0 ~ Si 100 500 2000 300 200 1000 J Example: eliminate linked areas of 200 pixels or fewer Si: total pixels in labeled area G-132 9.3 Data Analysis by Histogram (Histogram Measurement of Non-Image Data) Histogram measurement is a general statistical calculation process that has many applications other than image processing. In the example below, laser distance measurement is used to examine the external diameter of a cylindrical object (such as a pipe). The resulting data passes through an AID converter, and is input in digital form to a histogram measurement system that produces a statistical analysis of variability in the pipe diameter. __________________________ fJ~otation Subject (pipe) : Laser distance measurement DO Dl AID L-- converter H Histogram Module I I Di: results of measurement of variations from a theoretical perfect circle Dn-l - Input signal variation o V *Measurement results: frequency of occurence display Normal value OK (slight variation) Reject (large variation) G-133 Reject (central deviation) " 9.4 Detecting Missing or Misaligned Objects by Cumulative Addition Processing of Separate Areas Area 2 Area setup image Area 1 Area 0 Flaw or missing piece Input image A #0 ------------------------------ !!S ~ ----------------------f-,Flaw ~ Q) > -------------- .~ ] ::l U #0 #1 #2 #0 Area #1 #2 Area Cumulative results for input image A Cumulative results for input image B PASS FAIL G-134 9.5 Dumping the Contents of Results Memory After processing is complete, the values stored in results memory can be output over the image data output pins (OD<23 .. 0» by selecting the value of the horizontal coordinate counter as the results memory address input value. For specific examples of register settings, see Section 5.3.14, "Results Memory Dump." For timing charts, see Section 4.4, "Operating Timing Charts." Memory address o 1 2 3 4 Measurement results D(O) D(l) D(2) D(3) D(4) , , D(i) , 4095 D(4095) iCLK OD<23 .. 0> G-135 9.6 Perimeter Measurements Perimeter measurements are executed after the enclosed area is filled in. In Figure (1) below, the white areas are treated as background 114 Atoll Circular island with lake inside cicular island (I) Island inside lake ------r---inside island Rectangular island with lake LUT to convert all label I Use values other than #0 and #1 Circular lake inside rectangular island , to #0 (5) ~ Image area extension (2) I after Labeling processing inversion , (6) I , Circular island area: label value #2 Binary conversion and inversion (3) Square island area: label value #3 (7) Perimeter measurement (4) Island, island in lake, and rectangular island are created as background: label value #0 Lake in rectangular island: image value #3 Original background: label value # 1 G-136 9.7 Measuring Roundness The characteristics of the external shape of each area in an image can be discovered by making individual surface area and perimeter measurements. When an object's surface area remains constant but its perimeter increases, the object can be considered to have increasing degrees of deformation. Conversely, among objects with the same area, the one with the smallest perimeter is closest to a perfect circle, so that the length of an area's perimeter can be considered inversely proportional to the area's roundness. In the example below, areas 5 and 9 have the same surface area, but area 9 has a longer perimeter, and area 9 therefore has a greater degree of deformation. When measuring roundness, the higher the degree of roundness, the less the area's shape differs from a perfect circle (which has a roundness of 1). In digital images, however, the use of discrete values introduces an element of error. This example produces a value greater than the theoretical limit of 1 because the area of measurement is very small, which increases the magnitude of the contradiction between definitions of perimeter length and area: perimeter length is measured by considering each pixel as a point without size, while area is measured by considering each pixel as a unit of area. Example: Screen with input area numbers (labeled image): o0 0 o 0 o 0 5 0 o 0 0 0 0 5 5 5 009 0 0 0 5 0 009 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 o 9 9 0 0 o 0 0 0 0 000 0 0 Measurement results Pixel count Calculation results Perimeter Roundness Area no. (area) Vertical Horizontal Perimeter Diagonal V+H+D+2 41tS/L2 5 5 0 0 4 4+2"" 5.7 1.96 9 5 4 1 3 5+3+2",,9.2 0.74 G-137 9.8 Grayscale Projection Processing 9.8.1 Character Recognition One use of projection processing is recognizing simple character areas and symbols. \.h 0 0 0 (3 u; 0 0 0 0 ... \ ....\.... :::r::r::: •t ... B ...~ til 'D 0) til 'D til .c .c (/) U t ... \ ....\.... ~ til ! ... \ ....\.... :::C:C: 900~~~~~~~~~~~~~~f 600 300 .. 0-'--...... 11----- Shaded area - - - - - - - 1..~ .. .. First Second Third character character character 9.8.2 License Plate Number Recognition The example below shows the use of projection processing on an automobile license plate. G-138 9.9 Compensation of Moment Characteristics for Screen Partition or Origin Movement The Feature chip can process measurements of moment characteristics on large input screens. In cases where the screen is partitioned into two or more smaller screens, or when the origin moves, it is still practical to use the chip's high-speed processing capability to make repeat measurements, though the movement of coordinate points can also be compensated through simple calculations. Consider using the following compensation techniques when using parallel processing with multiple chips for large-area images obtained from scanners or line sensors, or when handling images that have already been partitioned during labeling or other processes. Although the examples shown here are taken from studies by Sumitomo, keep in mind that Sumitomo cannot assume responsibility for the consequences of any mistakes in the formulas presented. Always thoroughly verify the accuracy of all compensating formulas before using them. 9.9.1 Zero-Degree Moment Calculation (Area) The zero-degree moment expresses surface area. Because this value is not related to image coordinates, no compensation is required when the origin is moved. In a partitioned screen, some object areas may extend into two or more partitioned sections. It is then necessary to deduce which parts of these object areas belong to the same object, by using the values of pixels on the partition boundaries of the labeled image. This requires a process that searches for and matches portions of areas that straddle the partitions in the image. This procedure is also applied in grayscale-weighted area measurement, so that area measurement results can be totaled and weighted for objects that extend into two or more areas in partitioned screens. 9.9.2 Primary Moment Calculation If the calculation of primary moment characteristics about the origin (0, 0) is represented by mlO, mOl, then from the definitions of zero-degree moment and primary moment, the primary moment m'lO, m'Ol about the origin after it has moved some distance (Dx, Dy) can be determined by equations (9-1) and (9-2): m'JO = mJO - AxmQ{) (9-1) m' 01 = (9-2) mOl - i1ymoo This shows that for each object area contained on the screen, compensation for the primary moment after movement of the origin can be derived by simple calculations from the zero-degree moment and the primary moment before moving the origin, plus the coordinates of the new origin. Object areas that straddle two or more boundaries in a partitioned screen require a process that searches for and matches portions of areas, as is done in zero-degree moment calculations. G-139 9.9.3 Secondary Moment Calculation If the calculation of secondary moment characteristics about the origin (0, 0) is represented by (m20, m1l, m02), then from the definitions of zero-degree moment, primary moment and secondary moment, the secondary moment (m'20, m'n, m'02) about the origin after it has moved the distance (Dx, Dy) can be determined by equations (9-3), (9-4), and (9-5): m'20 = m 20 - 2· Lix· mlO m'02 = m02 - 2·.iy· mOl + .ix2 . moo (9-3) + .iy2 . mOO (9-4) m'l1 = m11 - .iy . mlO - Lix . mOl + Lix . .iy . mOO (9-5) These equations show that for each object area contained on the screen, compensation for the secondary moment after movement of the origin can be derived by simple calculations from the zero-degree moment, primary moment, and secondary moment before moving the origin, plus the coordinates of the new origin. Object areas that straddle two or more boundaries in a partitioned screen require a process that searches for and matches portions of areas, as described for zerodegree and primary moment calculations. 9.9.4 Partitioning the Screen into Four Areas The following procedure measures moment characteristics with the screen partitioned into four areas. (0,0) (Xc, 0) 0 1 /(Xc, Yc) (0, Yc) 3 2 In this example, consider a screen partitioned into four areas around a central point (Xc, Yc) for calculating moment characteristics in which the upper left corner of each of the four screen areas is used as the origin (0, 0) of that area. As shown in the illustration, the four areas are labeled 0, 1, 2, and 3. Moment characteristics measured in each of these areas is represented by m(O}xx, m(l}xx, m(2}xx, and m(3}xx. Thus: m(0)Xx represents moment characteristics measured with respect to the original origin. • m(l>Xx represents moment characteristics measured using (Xc, 0) as the origin in area 1. • m(2)Xx represents moment characteristics using (0, Yc) as the origin in area 2. • m(3}xx represents moment characteristics using (Xc, Yc) as the origin in area 3. G-I40 In this case, moment characteristics with respect to the full screen can be expressed using the following equations (9-6) through (9-11): moo = m(O)OO + m(l)oo + m(2)oo + m(3)oo (9-6) mlO = m(O)IO + m(l)IO - Xc· m(l)oo + m(2)IO + m(3)IO - Xc· m(3)oo (9-7) mOl = m(O)OI + m(l)01 + m(2)OI - Yc· m(2)oo + m(3)IO - Yc . m(3)oo (9-8) m20 = m(O)20 + m(1)2o + m(2)20 - 2Xc . m(l)lo + Xc 2 . m(l)oo + m(3)20 -2Xc . m(3)JO + Xc 2 . m(3)oo (9-9) m02 = m(O)02 + m(1)o2 + m(2)02 - 2Yc· m(2)OJ + Yc 2 . m(2)oo + m(3)02 -2Yc· m(3)OJ + Yc 2 . m(3)oo (9-10) ml1 = m(O)n + m(l)n - Xc· m(l)ol + m(2)JJ - Yc· m(2)IO + m(3)11 (9-11) -Yc· m(3)JO - Xc· m(3)JO + Xc· Yc' m(3)oo 9.10 Maximum Values For Which Moment Characteristics Can Be Derived The process of measuring moment characteristics requires the Feature chip to store intermediate results and final measurement results in its internal results memory. Zero-degree moment characteristics (surface area) are measured in 48-bit width (4096 words). Grayscale-weighted area, as well as primary and secondary moment characteristics are measured in either 24-bit width (2048 words) or 48-bit width (4096 words). This section presents the results of studies by Sumitomo as a guide for estimating the maximum values for which moment characteristics can be calculated. In using the following formulas, be aware of the possibility of errors, for which Sumitomo cannot assume responsibility. Always thoroughly verify the accuracy of all formulas before using them. 9.10.1 Zero-Degree Moment Characteristics and Surface Area Measurement of binary zero-degree moment characteristics is expressed in terms of a surface area (pixel count) for each object. Thus the maximum pixel count possible in 24-bit width without overflow is (224 -1), or 16M pixels. Assuming a square input image, the size of a 4095 x 4095-pixel image is less than 224 -1, so that even in the worst case in which the entire area of a 4095 x 4095pixel image is a single object area, no overflow can result. Thus, even with input of a 4095 x 4095pixel area, the surface area of 4096 separate objects can be counted. Similarly, in a grayscale histogram the horizontal axis of the histogram can be the area number or grayscale value, but the maximum pixel count (vertical axis) is the same in either case. These conclusions assume a square input image, though zero-degree moment characteristics do not depend on the aspect ratio of the input screen, and so the same conclusions apply to a screen of, for example, 16K x 1K pixels. The case of grayscale-weighted area measurement is similar, though, because binary images are not involved, the limiting factor is not pixel count but the total of grayscale values of the pixels in each object area. 4K area measurement mode has 8 bits (or 256 grayscale gradients), and so can add a total of (224 _1)/(2 8 -1) = (2 16 +28 +1) pixels. Assuming a square input screen, the total of 256 x 256 is less than (216 +2 8 +1), so that even in the worst case (entire screen is a single object area, with all values OFFh), no overflow can result. Because there are 12 bits (or 4096 gradients), a total of (224_ 1)/(212_1) = (212+1) pixels can be added. Again assuming a square input image, the total of 64 x 64 is less than (212 +1), so that with 64 x 64 pixels, even in the worst case in which the entire screen is one object area and all values are 7FFh, no overflow can result. G-141 2K area measurement mode limits the number of object areas to 2048, so that each area can have a value ranging from 0 to 248 _1. If the number of §rayscale fradient values is 12 bits or 4096, then it is possible to measure totals for ulE to (248_1)/(2 1 -1) = (23 +224+212+1) pixels. Assuming a square input screen, the total of 218 x 2 8 is less than (236+224+212+1), so that with a total of 218 x 218 pixels, no overflow can result even in the worst case in which the entire screen is a single area and all pixel values are 7FFh. 9.10.2 Primary Moment Characteristics The maximum value of primary moment characteristics is determined by input screen size. The maximum value occurs in the case where one screen is occupied by one object area, and the vertical or horizontal size of the screen is large. If the input screen size is (Xw, Yx) and the upper left comer is the origin (0, 0), the maximum value of the primary moment around the origin can be expressed by the following formulas: m10(max) = Yw· {O + 1 + 2+ ... +(Xw -I)} = 2"1 Yw· Xw· (Xw -1) m01(max) = Xw· {O (9-12) 1 (9-13) + 1 + 2+ ... +(Yw -I)} = 2"Xw. Yw· (Yw -1) Example: Input screen size and maximum measurement value for primary moment characteristics: Input screen size Maximum value of primary moment characteristics 256 x 256 pixels 28 x 28 x (28_1)/2<223 23 bits 512 x 512 pixels 29 x 29 x (2 9 -1)/2<226 26 bits 4096 x 4096 pixels 212 x 212 x (212_1)/2<235 35 bits Maximum bit width 9.10.3 Secondary Moment Characteristics The maximum value of secondary moment characteristics is determined by input screen size. The maximum value occurs in the case where one screen is occupied by one object area, and the vertical or horizontal size of the screen is large. If the input screen size is (Xw, Yw) and the upper left corner is the origin (0, 0), the maximum value of the secondary moment (m2o, m11, m02) around the origin can be expressed by the following formulas: = Yw· W + 12 + 22+ ... +(Xw _1)2} ="61 Yw· Xw· (Xw -1)· (2Xw -1) (9-14) 1 m02 (max) = Xw· {02 + 12 + 22+ ... +(Yw _1)2) = - Xw· Yw· (Yw -1)· (2Yw -1) 6 (9-15) m20 (max) The maximum value of the ml1 moment for the yth line only is this: 1 m1!(max[y]) = y. {O + 1 + 2+ ... +(Xw -I)} = 2"Y· Xw· (Xw -1) G-142 (9-16) Therefore, the maximum value of the mll moment for the screen as a whole is this: ml1 (max) = "21 Xw· (Xw -1)· {O + 1 + 2+ ... +(Yw - I)} = 4"1 Xw· (Xw - 1)· Yw . (Yw - 1) (9-17) Example: Input screen size and maximum measurement value for secondary moment characteristics: Input screen size Maximum value of secondary moment characteristics 64 x 64 pixels 26 x 26 x (2 6 -1) x (2 7 -1) /6<224 24 bits 128 x 128 pixels 27 x 27 x (27 -1) x (28 -1) / 6<227 27 bits 256 x 256 pixels 28 x28 x (28 -1) x (29 -1) / 6 <230 31 bits 512 x 512 pixels 29 x29 x (29 -1) x (210-1) / 6 <235 35 bits 4096 x 4096 pixels 212 x 212 x (212_1) x (213_1) / 6 < 247 47 bits G-143 Maximum bit width 9.11 Sample Circuit (Labeling Processing + Feature Extraction Processing) IP90C51 + IP90C10 + IP90C18 ICLK: 25 MHz (max.) 12 1135 word x. 8-bit line buffer ~PD42 I02G-3 5K word x 16·bit line buffer (Note 1) ~PD485506-35 Horizontal effective data: 1135 words (controlled by ~PD42102G-3) (NEC) (NEC) HS' ICLK Input image data --~4-~ 12C - _ z~~~~ta f-_ _i---C_ _ _ _ _ _ _.--t-_ _ _ _ _----r VS' Feature HS' ICLK IP90CI8-HS FRAME MEMORY (Note 3) ! i . Image data (LUT output, run coord. measurement) Run detection signal Status output 74AC11l0 Note 1: Note 2: Note 3: Note 4: Note 5: SRAM8KB .3 This line buffer is used as a IH horizontal line delay. It can also function as a line delay for the IP90ClO and IP90C18 chips. The frame memory configuration required by the IP90CI0 generates a pixel delay in the horizontal axis. This line buffer is required to absorb that pixel delay. The delay value N is determined by the frame memory's design configuration. The frame memory is required by the IP90CIO. Determines the processing area of the IP90C18. An IP90C51 can be used if necessary. Also, in some cases the circuit can be designed so that the IP90C18 operates while the IP90ClO executes two-dimensional labeling. The frame memory should be controlled so that the input image data and label data appear on the same horizontal line (without a I-line delay). G-l44 Section 10: Guidelines for Avoiding Overheating 10.1 Guidelines for Avoiding Overheating The heat generated by power consumption in an electronic device must not exceed the device's maximum allowable junction temperature. Temperatures exceeding this limit will reduce the device's reliability, sometimes dramatically, and can cause it to fail completely. The maximum junction temperature is determined by the heat relief properties of the device package; therefore, the maximum junction temperature and heat relief properties of the package determine how much power the device can use. The IP90C18 requires no special precautions when operating at image clock frequencies of 25 MHz or less. However, if the device is used at frequencies above 25 MHz, the following precautions are necessary: For all image processing other than table conversion run coordinate detection and results memory dump output, set the I/O control register (IOCTL) results output enable flag (odenN) to 0, and set the output from the image data output (aD) pins to high leveL • For all image processing other than table conversion and results memory dump output, as well as for simultaneous execution of run coordinate detection (or when the I/O control register [IOCTL] results output select flag [sod] is set to 1 to output coordinate data from the coordinate counters through the image output [aD] pins), increase the load capacitance of the image output (aD) pins to 30 pF. When performing cumulative histogram processing in 2K area measurement mode, set the lowpower cumulative histogram processing mode flag (HaccLP) in the mode register to 1. • Grayscale projection processing in 2K area measurement mode using one-axis projection (H-axis projection only) should not be performed at frequencies over 25 MHz. The device may not be reliable if these precautions are not followed. G-l45 Appendix A: Reference Bibliography A.1 Reference Bibliography The IP90C18 Feature LSI chip has been researched and developed to provide image processing and measurement through algorithms that determine the characteristics considered most important, such as area and center of gravity. The development objective has been to provide processing (1) from large-scale image screens, (2) for multiple object areas, (3) in real time simultaneously with raster-scan input, and (4) using accelerated processing of camera signals to the greatest extent possible. Some characteristics with mathematically vague definitions (such as perimeter measurement) had to be defined for this purpose. However, virtually all characteristics used have definitions that are well accepted at the research level, and mathematically sound definitions were researched and incorporated into the final specifications. The following list includes those reference materials used in this study that are generally available. The researchers would also like to take this opportunity to express deepest appreciation for the efforts of these researchers in developing the field of image processing through research and instruction, as well as through the development of texts. Because the IP90C18 Feature chip is intended to provide real-time processing through optimization of hardware, this chip has significantly different architecture than the examples used in these reference materials. For descriptions of the Feature chip's internal processing, as well as limiting factors and other information, see the text of this manual. A.l.I Digital Image Processing - General • A. Rosenfeld and A. C. Kak, (Japanese translation by Nagao Makoto), "Digital Image Processing," Kindai Kagakusha, 1978. G-l46 Appendix 8: Handling CMOS LSI Devices B.1 Precautions Sumitomo CMOS devices are designed and manufactured with the ability to withstand normal levels of stress during normal use and handling. However, failure to follow good usage procedures can reduce the device's reliability. To help ensure best results, always follow the precautions below in system design, handling, and storage. (1) Ratings Make sure the system is always within its established range of operating ratings, including operating voltage, input/output voltage, current, and temperature. Operating outside these ranges can increase failure rates quickly and dramatically, reducing reliability even though the device may appear to function normally. Also, when designing systems, keep in mind that failure rates vary according to operating voltage and temperature levels, even within the range of established ratings. (2) Latch-Up CMOS LSI devices are subject to a condition known as latch-up, which can occur when excessive extraneous noise is applied at the power supply or I/O signal pins, and which can eventually destroy the LSI. Because latch-up is a thyristor phenomenon, its effects remain in the device until the power supply is switched off. If latch-up occurs, shut off the power supply immediately, and do not restart the system until the cause of the problem has been eliminated. (3) External Force Always avoid exposing the system to vibration, shock, continued stress, or rapid temperature changes. These can damage the device's semiconductor chip, or break wire connections inside its plastic package. (4) Static Electricity Even though all signal pins are internally connected to anti-static protective circuits, exposure to static charges exceeding the voltage tolerance of these circuits can damage the device. Therefore, do not use insulating material in packaging and shipping containers, and make sure all materials used are electrically conductive and clearly labeled "anti-static." (5) Temperature and Humidity Make sure the device's physical surroundings stay within its temperature and humidity limits. Exposing the device to dust, salts, or corrosive gases such as S02 can cause leakage between pins, corrosion, and other problems. If the device must be used in a dirty, damp, or corrosive environment, coat the device's pins to prevent direct contact with corrosive gases or other contaminants. (6) Frost Protection and Storage Use and store the device in an environment that is controlled to prevent frost formation in case of rapid temperature changes. When storing the device, keep it in a tray in a horizontal position, and protect it from unnecessary loads. G-147 SMIASSP Image Processing LSI Series IP90C20 Rank Value Filter (RKFil) Sumitomo Metal Industries, Ltd. Technical Manual Ver. E 1.4 • Sumitomo Metal Industries, Ltd. Table of Contents Section 1: Features and Functions ..................................................................................... 1 Section 2: Basic System Configuration and Operation 2.1 2.2 Section 3: 3.1 Section 4: 4.1 4.2 4.3 Section 5: 5.1 5.2 5.3 Section 6: 6.1 Section 7: 7.1 7.2 7.3 7.4 Section 8: 8.1 8.2 8.3 Basic System Configuration ...................................................................................... 2 Operating Description .............................................................................................. 3 Internal Configuration Internal Configuration Diagram .............................................................................. .4 Mode Setting Basic Filter Mode Settings (MIN, MED, MAX, TP) ................................................... 5 Mode Settings for 3xl and lx3 Median Filter Processing ............................................ 6 Sample Connections for Mode Selection .................................................................... 8 Pin Description Signal Pin Descriptions ............................................................................................ 12 Pin Description ......................................................................................................... 13 Pin Configuration ..................................................................................................... 15 External Dimensions External Dimensions: 44-pin QFP .............................................................................. 16 Electrical Characteristics Absolute Maximum Ratings ...................................................................................... 17 Recommended Operating Conditions ......................................................................... 17 DC Characteristics ................................................................................................... 18 AC Characteristics ................................................................................................... 19 Sample Processing and Applications Noise Elimination by Median Filtering .................................................................... 21 Sample Median Filtering Process .............................................................................. 22 Creation of Basic Screens for Shading Compensation ................................................ 23 H-i Section 1: Features and Functions • The IP90C20 rank filter (RKFil) LSI chip sorts the 9 values contained in a 3x3-pixel local area, and outputs the maximum, median, and minimum values of those pixels in real time. The RKFil chip has a maximum processing rate (image data input rate) of 50 MHz, which enables it to be used with high-speed, high-density image data. Operating modes can be selected by level settings entered through the mode select signal pin on the chip, or by register settings entered through a CPU bus. The RKFil includes median filter processing of lx3 or 3xl local areas, using expanded mode settings made through a push-down register. It also provides a transparent mode that passes data through without filter processing. The chip also provides these features, designed to make it easy to use: Low power demand, CMOS process 5V single power source TTL level input I output Plastic QFP 44-pin package (molded area 10 mm2, pin pitch 0.8 mm) • • • The following figure shows how the IP90C20 processes data: (00) , h-l 9-value sorting h h+l maximum value - raster scan direction v-I v v+l , '- , '- " - - - - - - --- - - - - - --- , \ '- ,~ .... --- median value f''''' , '\ '- ~(h,v) minimum value (Wh,Wv) 0 0 0 0 0 0 0 0 0 8 7 -MAX(h,v)~ maximum filter output 6 5 4 3 -MED(h,v)~ median filter output o!!l C\lca~ 0>1: 0 -MIN(h,v)~ minimum filter output Figure 1: IP90C20 Rank Filter (RKFil) LSI: Input Data and Processing The IP90C20 ranks the pixels in the 3x3-pixel local area in order of size, and identifies their locations using coordinates relative to the central pixel (h, v). The maximum value in the local area then becomes the maximum filter output MAX(h, v), the median value becomes the median filter output MED(h, v), and the minimum value becomes the minimum filter output MIN(h, v). H-l CIIIi " 2 g~~ c..", -;:.:: Section 2: Basic System Configuration and Operation 2.1 Basic System Configuration MIN, MAX, MED mode settings Mode setting signal pins 8-bit grayscale image input RKFil MD2 MDO MDl WR* lAO to IA7 1mage data 8-bit gray scale image output ODOto OD7 y 1 Line delay I I mOtom7 I Y 1 Line delay I ICO to IC7 I CLK 1mage dot clock RST* I Re set input Note 1: An asterisk (*) after a signal name denotes inverse logic. Note 2: The most and least significant bits (MSBs and LSBs) of the chip's grayscale image I/O signal pin sets are shown below: Pin sets MSB LSB IAO-IA7 IA7 lAO IBO-IB7 IB7 IBO ICO-IC7 IC7 ICO ODO-OD7 OD7 ODO H-2 2.2 Operating Description local region - - - - - - - r - - -I lAO to 7 IBO to 7 ICO to 7 L _________ _ CLK ""<~~~~~- ODD to 7 8 clock pulses ~~~~~~ _~~____'__~~~~~~_u~nk_n_o_w_n_ _ _ _ _ _ _ _ _ _ ______'·~ ~trsr Note 1: Note 2: t: Image data is latched at the rising edge of the CLK signal. t rsr : RST* signal release time is 15 ns. The IP90C20 (RKFil) LSI chip generates a delay of 8 clock cycles between the input of 3x3 local area image data and the output of results. The RKFil chip's pipeline configuration provides realtime processing, producing the filtered output of one 3x3 local area with every clock cycle. In 3xl local area median filter mode, the RKFil chip outputs the median value of the three data points (IBt-1, IBW, IBtl) with the same timing as the output of ODW in 3x3 local area processing. In lx3 local area median filter mode, the RKFil chip outputs the median value of the three data points (lAW, IBW, ICW) with the same timing as the output of ODW in 3x3 local area processing. In transparent data mode, the IP90C20 outputs the value of the center pixel in a 3x3 local area, corresponding to IBW in the above diagram. The latency from data input to output is the same as that shown above for max/mean/min filter mode, and the value of IBW is output with the timing of value ODtQ. H-3 Section 3: Internal Configuration 3.1 Internal Configuration Diagram 8-bit value Line input h+l h h-l v-I IAO-IA7 Sorting machine MAX .... B II ..0 B !l v IBO-IB7 MED :;p, -'" ~on B c<) Output 8-bit value Output latch ODO-OD? MIN v+l ICO-IC7 3x3 Array latch Note 1: Note 2: Mode select An asterisk (*) after a signal name denotes inverse logic. The above block diagram is intended as a functional description only, and does not indicate all the functions of the IP90C20 (RKFil) LSI chip. For descriptions of functions and timing, see the related sections of this document. H-4 Section 4: Mode Settings 4.1 Basic Filter Mode Settings (MIN, MED, MAX, TP) The available basic filtering modes include the three rank filter functions of the RKFil LSI, maximum filtering (MAX), median filtering (ME D), and minimum filtering (MIN), plus a transparent mode (TP) in which no filter processing is performed. Select a basic filtering mode by using the signal pin input level (level setting) or by writing to registers using the write pulse signal (WR*) (register setting). Level setting is designed for built-in image processing devices in automated equipment systems where rank filter functions are fixed. By entering high- or low-level signals at the MDl, MDO, and WR* pins as shown in the table below, the chip can be switched among MIN, MED, MAX, and TP mode as needed. Fixing WR* at low level eliminates the need to generate a write pulse, and thus also the need to connect to a CPU bus. Register setting is designed for dynamic switching of general-purpose image processing devices and processing functions. In this case, the IP90C20 chip is connected to a CPU bus, and functions as a peripheral LSI with mode switching capability. The IP90C20 chip decodes address signals and uses the WR* signal input as a write pulse. The values of the MDI and MDO signals are latched in the mode register at the rise of the WR* signal, and can be used to switch functions according to the table below. When using the IP90C20 chip in a basic filter mode, fix the MR2 signal low. Mode Setting Signal Pins Filter mode MD2 MD1 MDO MIN Low Low Low MED Low Low High MAX Low High Low TP Low High High Control pin WR* Low level or pulse ~ -..-'1 . . . . .'.·,.i. MD2-MDO WR* 001 low level Signal Pin Level Settings for MED Filter Mode MD2-MDO ==><~ __01_0_~><= t Register Settings for MAX Filter Mode H-5 4.2 Mode Settings for 3x1 and 1x3 Median Filter Processing In addition to the basic mode settings described on the previous page, the IP90C20 has two expansion modes: one for filter processing to output median values from 3xl areas (MED3Xl), the other for filter processing to output median values from lx3 areas (MEDIX3). MEDlx3 MED3xl IA--~ IB--~ IC--~ Raster scan direction ~ As shown above, median filter processing of 3xl-pixel areas outputs the median value of the three pixels in a local area measuring 3 pixels horizontally by 1 pixel vertically, and median filter processing of lx3-pixel areas outputs the median value of the three pixels in a local area measuring 1 pixel horizontally by 3 pixels vertically. H-6 Select an expansion mode by writing into the mode register in a sequence of four cycles. The mode register is configured as a push-down shift register with a depth of four bits. In the basic modes, the push-down register values are ignored, but when the sequences shown in the following tables are used, the push-down register can be used to select the expansion modes. Glitches in WR* can result in incorrect push-down signals, resulting in abnormal operation. When this occurs, the image output signal (ODO-OD7) is not necessarily accurate. Selection settings remain valid until the next reset signal. Switching between the 3xl and lx3 modes and among the basic filter modes (MAX, MED, MIN) is controlled by a high-level signal latched in the first level of the MD2 signal pin in the internal shift register. For this reason the MD2 signal in the fourth cycle of the write sequence for both expansion modes is a high-level signal. 3xl Median Filter (MED3Xl) Mode setting signal pins Write sequence MD2 MDl MDO 1st Low High High 2nd Low Low High 3rd High Low High 4th High Low High lx3 Median Filter (MEDlx3) Write sequence Mode setting signal pins MD2 MOl MDO 1st Low Low High 2nd Low Low High 3rd Low Low High 4th High Low High MED3xl mode MD2-MDO WR* MEDlx3 mode MD2-MDO WR* Example: Mode Selection by Writing to Push-Down Register (four write cycles) H-7 4.3 Sample Connections for Mode Selection Section 4.1, "Basic Filter Mode Settings," described the two methods for switching between the MIN, MED, and MAX filter modes. The level setting method uses signals sent to the mode setting signal pins. The register setting method uses instructions sent on the write pulse signal (WR*) like a peripheral LSI chip. Note that the examples given below are for illustration only, and are not intended to serve as specific applications. Actual applications should be designed with careful attention to the environment in which the device will operate, as well as to system specifications and timing requirements. 4.3.1 Selecting Basic Filter Modes Using Signal Pin Level Settings If only median (ME D) filtering is to be applied, the mode can be set relatively easily using wiring. To select maximum (MAX) filtering, change the level of the MD1 pin; to select minimum (MIN) filtering, change the level of the MDO pin. When selecting a basic filter mode by level setting, the MD2 and WR* signals must always be held low. a) Median filter selected IP90C20 (RKFil) Image input ID aD Image output MED MD2 MDI MDO WR* b) Maximum filter selected IP90C20 (RKFil) Image input Image aD -output ID MAX MD2 MDI MDO WR* VDD H-8 c) Minimum filter selected IP90C20 (RKFil) Image input Image 00 -output ID MIN WR* GNO d) Switching, etc. selected IP90C20 (RKFil) Image input ID 00 M02 MDl MOO WR* GNO VDD H-9 Image output 4.3.2 Selecting Basic Filter Modes Using Mode Register Settings A basic filter mode (3x3 MAX, MED, MIN filtering) can be selected dynamically from the CPU by latching the mode signals (MDO, MDl, MD2) at the rise of the WR* signal. This type of mode selection is maintained until the WR* signal decreases for the next mode selection, or until a reset signal is received. Output data becomes valid when mode switching ends. A minimum of 10 clock cycles are required for the new input data to fill the 3x3 local area, the data to be filtered, and the results to be output. IP90C20 (RKFil) Image output Image input CPU address bus f------- WR * Lower 2 bits - - - -.......;;.;;.;.;.;;;;...;;..;;.;;,;;...~ CPU data bus Values in the mode register are latched at the rise of the WR* pulse. Glitches in WR* can cause abnormal operation. H-lO 4.3.3 Sample Circuits for 3xl and lx3 Median Filtering Mode Settings Select an expansion mode (3xl median filtering (MED3xl) or Ix3 median filtering (MEDIx3» by using the mode register as a push-down shift register with a depth of four bits. MD2 ~l~ MDO WR* Internal Push-Down Register Configuration The circuit connections are almost the same as for selecting basic filtering modes by register setting. However, the mode selection must use the MD2 signal pin, which classifies the setting as an expansion filtering mode. The combination of values written in the past determines the mode of operation. IP90C20 (RKFil) Image output Image input CPU address bus I----WR* Lower 3 bit _ - - - - ' - - - - - - . - CPU data bus H-ll Section 5: Pin Descriptions 5.1 Signal Pin Descriptions The package is a 44-pin QFP (molded area 10 mm2 , pin pitch 0.8 mm). I/O No. of Pins IAO-IA7 I 8 IBO-IB7 I 8 I-line delay data input ICO-IC7 I 8 2-line delay data input ODO-OD7 0 8 Image output data Pin group Pin Image bus Mode setting Power supply Total pin count Description Image input data (0 delay) CLK I 1 Clock signal MDO--MD2 I 3 Data bus 2-bit/mode input WR* I 1 Register write enable (Note 1) RST* I 1 System reset (Note 2) Vdd PW 2 5V power supply GND PW 4 GND 44 Note: An asterisk (*) following a signal name indicates inverse logic. Note 1: See the explanation of mode settings for methods of selecting filter modes (MAX, MED, MIN, TP). The reset signal pin (RST*) uses Schmitt trigger input with pull-up resistance. Note 2: H-12 5.2 Pin Description Pin group Pin I/O Pin No. Image input bus CLK I 42 IA7 I 31 IA6 I 30 lAS I 29 IA4 I 28 IA3 I 27 IA2 I 26 Description MSB IAI I 25 lAO I 24 LSB IB7 I 41 MSB IB6 I 38 IB5 I 37 IB4 I 36 IB3 I 35 IB2 I 34 IBI I 33 IBO I 32 LSB MSB IC7 I 6 IC6 I 5 IC5 I 4 IC4 I 3 IC3 I 2 IC2 I 1 ICI I 44 ICO I 43 H-13 LSB To prevent abnormal operation due to noise, connect all pins to the power supply or GND level. Pin group Pin I/O Pin No. Image output bus OD7 0 12 OD6 0 13 OD5 0 15 OD4 0 16 OD3 0 19 Mode selection Power supply and GND OD2 0 21 om 0 22 ODO 0 23 WR* I 11 MD2 I 10 MDI I 9 MDO I 8 RST* I 7 Vdd PW 18 Vdd PW 39 GND PW 14 GND PW 17 GND PW 20 GND PW 40 Description MSB Note 1 LSB Note 2 Note 1: Output current 101 = 9 mA Note 2: Note 3: Schmitt-trigger input terminal with pull-up resistance 50 kW . An asterisk (*) following a signal name indicates inverse logic. All input terminals are TTL level. The most and least significant bits (MSBs and LSBs) of the chip's grayscale image I/O signal pin sets are shown below: Pin sets MSB LSB IAO-IA7 IA7 lAO IBO-IB7 IB7 IBO ICO-IC7 IC7 ICO OD7 ODO ODO-OD7 H-14 5.3 Pin Configuration 0 S:l S:l :.; ...l U oZ t- ~ 0 "0 "0 > ""~ 'I"l ~ ~ ~ <:'"l ~ N ~ 44 10 IC2 IC3 .-. IC4 ICS IC6 IC? 6 IBI IBO IA? IA6 SUMITOMO METALS JPN lAS IA4 28 RST* XXXXXXX IA3 MDO IP90C20 IA2 MDt IAI MD2 lAO WR* aDO 23 22 t- 0 0 ~ 0 0 '"00 G 0 'I"l 0 0 0 "0 <:'"l 0 z N 50 0 z ~ 0 0 Pin Name Type Pin Name Type 0 34 IB2 I 0 0 0 Pin Assignments Pin Name Type Pin Name Type 1 IC2 I 12 OD7 0 23 ODD 2 IC3 I 13 D06 0 24 lAO I 35 IB3 I 3 IC4 I 14 GND PW 25 IAI I 36 IB4 I 4 ICS I 15 OD5 0 26 IA2 I 37 IBS I 5 IC6 I 16 OD4 0 27 IA3 I 38 IB6 I 6 IC7 I 17 GND PW 28 IA4 I 39 Vdd PW 7 RST* I 18 Vdd PW 29 lAS I 40 GND PW 8 MDO I 19 OD3 0 30 IA6 I 41 IB7 I 9 MDI I 20 GND PW 31 IA7 I 42 CLK I 10 MD2 I 21 OD2 0 32 IBO I 43 ICO I 11 WR* I 22 om 0 33 IBI I 44 ICI I H-15 Section 6: External Dimensions 6.1 External Dimensions: 44-pin QFP 44-pin plastic QFP r - - - - - - - - 1 3 . 6 ± 0.4 -------l~ ~~10~.0~±~0~.2~~~~-+ 33 I 34 : __+-__ ~ 23 22 I I I I I I I I I I --------------T-------------I I Lo-JL '"o+1 o ---'- 0.35± 0.10 1-$-1 0.15 1@' 11~.80 1 Detail: Pin lead configuration o +I:;:==~ o H-16 Section 7: Electrical Characteristics 7.1 Absolute Maximum Ratings Symbol Rating Unit Vdd -0.5 to 6.5 V Input voltage Vi -0.5 to Vdd + 0.5 V Output voltage Vo -0.5 to Vdd + 0.5 V rnA Parameter DC supply voltage Output current 7.2 10 20 Operating temperature Topt o to 70 DC Storage temperature Tstg -10 to SO DC Recommended Operating Conditions (Ta = 0 to 70°C) Parameter Symbol Power-supply voltage Vdd Input voltage Vdd Max. Unit 4.75 5.0 5.25 V 0 - Vdd V 0 O.S V Vdd V V 2.2 Vp 1.2 - 2.4 Vn Schmitt 0.6 - 1.S V Vhys trigger 0.3 - 1.5 V 0 - 200 ns 0 - 200 ns High level input voltage Vih Hysteresis voltage Typ. TTL level Vi! Negative trigger voltage TTL level Min. - Low level input voltage Positive trigger voltage Condition Input rising time Tr Input falling time Tf Input rising time Tr Schmitt 0 - 10 ms Input falling time Tf trigger 0 - 10 ms Note 1: TTL level The reset signal pin RST* is a Schmitt-trigger input pin. H-17 7.3 DC Characteristics Vdd = 5 V ± 5% Ta = 0-70°C Parameter Symbol Quiescent supply current (Note 1) II Input ground voltage Vic Output OFF leakage current (Note 2) los Input Normal leak With pull-up resistor current (50 ill equivalent, note 3) Output current Ii Min. Condition Vi = Vdd or GND 0.1 -45 Low level 101 Vol = 0.4 V 9.0 High level Ioh Voh = 2.4 V -0.5 Low level High Level Vol Vah 250 rnA 10pA 10 !lA -131 -320 !lA rnA rnA 0.1 101 = 0 rnA 2.6 Iah = OmA !lA V Vo = 0 V Vi = Vdd or GND Vi = GND voltage 200 -1.2 Ii = 18 rnA Ii-Pu Output Max. Unit Typ. 3.4 V V Note 1: Note 2: Values exclude quiescent supply current to pull-up and pull-down resistance. Output OFF-state leakage current is the absolute value of current to one LSI terminal for 1 second or less. Note 3: Only the reset signal pin RST* has pull-up resistance (50 ko. equivalent). Switching Characteristics (Vdd = 5 V ± 5%, Ta Item = 0-70°C) Symbol Condition Min Typ Max Unit Output rise time tr Output pins CL = 15 pF - 1.54 - TIS Output fall time t£ Output pins CL = 15 pF - 1.42 - TIS Input/Output Pin Capacitance (Vdd = Vi = 0 V) Item Symbol Condition Min Typ Max Unit Input signal pins Cin f=lMHz - 10 20 pF Output signal pins Caut f=lMHz - 10 20 pF H-18 7.4 AC Characteristics Image Data Input Timing tcpJ ----------, eLK ,, ,, \.._---- I.......I----tcyc ---~ tis Image data lAO to IA7, IBO to IB7, leo to le7 tih ,----------~\ Ix(m) U Ix(m+l) ,---\ /"-- ~{ Ix(m+2) ' - -_ _ _ _ _ _ _ _ ..J' ~< , __ _ \~' U: Unknown value units: ns Parameter Symbol Min. Typ. Max. Video clock cycle tcyc 19 - - Video clock H level pulse tcph 8 - - Video clock L level pulse tcpJ 8 - - Image data input setup time tis 2 - - Image data input hold time tih 4 - - Image Data Output Timing Load Capacitance, CL = 30 pF ----------,, ,, ,, eLK '------ , ,,.----------- ODOto OD7 OD(m-l) OD(m) ------t-....J }-------t--v X OD(m+l) '---------~' '~----------- units: ns Parameter Symbol Min. Typ. Max. Delay time from CLK rise to data output tad 3.5 - 13 Hold time from CLK rise to data output toh 3.5 - 13 H-19 Mode Set, Reset Cycle Timing ~----- twm ------I~ twrwWR* tmds MDOtoMD2 Unknown value -I~-I~ ValidMD(m) tmdh Unknown value MD(m+l) Writing from the CPU to the mode register need not be synchronized with the image data clock signal (CLK). WR* functions as a write clock from the CPU, and values can be written to the register at the rise of WR*, as shown above. However, after writing to the mode register, accuracy of internal operations is not assured for a certain period (twrn ). Output data becomes valid after mode setting and after the fixed period (twrn ), when the input data forms a 3x3 local area, is filter-processed, and is output a minimum of 8 clock cycles later. units: ns Symbol Min. Typ. Max. WR* pulse width (low period) tWlW 8.0 - - WR* pulse interval twm 16.0 - - MD2, MD1, MDO setup time for WR* signal rise trnds 8.0 - - MD2, MDl, MDO hold time for WR* signal rise trndh 3.0 - - Parameter Reset Timing trsr RST* Reset signal pin The reset signal can be input without regard to the timing of the image clock or the register write signal (WR*). However, image data input and values written to the register become valid beginning with the first image input cycle or register write cycle after the rise of the reset signal and after the reset release period (t rsr ). Therefore, output data does not become valid until after the rise of the reset signal and after the reset release period, when the next set of input data forms a 3x3 local area, is filter-processed, and is output a minimum of 8 clock cycles later. units: ns Parameter Symbol Min. Typ. Max. RST* pulse width (low period) trsw 8.0 - - RST* release time t rsr 15 - - H-20 Section 8: Sample Processing and Applications 8.1 Noise Elimination by Median Filtering Figure 1 shows the rear license plate of an automobile in an image that includes Gaussian noise. This original image is then subjected to median filtering, with the result shown in Figure 2. The binary conversion process, frequently used in image measurement applications, is applied to both Figure 1 and Figure 2, with the results shown in Figure 3 and Figure 4. The results show that filtering has virtually eliminated the individual pixels of spike-type noise. Figure 1: Original image, 140x140 pixels Figure 3: Binary conversion performed directly on original image Binary conversion: ~4"""" ', ..............,.' Figure 2: After median filtering -I".. Figure 4: Binary conversion performed on median-filtered image Binary conversion: Noise Elimination By Median Filtering H-21 8.2 Sample Median Filtering Process The following example of median filtering illustrates the typical operation of a rank filter. Photo 1 shows an image of a printed letter "e" approximately 60 x 60 pixels in size, obtained by sampling. Figure 1 shows a 3-dimensional graph of this image, using grayscale values as the vertical axis. Photo 2 shows the original image from Photo 1 with artificial Gaussian noise added. Figure 2 shows a 3-dimensional graph of Photo 2. Each 3x3-pixellocal area of the image from Photo 2 is passed through median filtering. The results are shown in Photo 3 and the 3-dimensional graph in Figure 3. The result is a fairly effective elimination of noise, which retains the boundary between character and background, demonstrating the effectiveness of median filtering. Photo 1: Original Image Figure 1: Three-Dimensional Graph of Original Image Photo 2: Noise-Added Image Figure 2: Three-Dimensional Graph of Noise-Added Image Photo 3: Median Filter Processed Image Figure 3: Three-Dimensional Graph of Median Filter Processed Image H-22 8.3 Creation of Basic Screens for Shading Compensation The median filter's excellent noise-elimination characteristics can be used to generate basic images from sampled images, using this general process: 1. Data is sampled for the basic image (point A in the figure below). 2. 3. The data is then subjected to median filter processing (BO). Step 2 is repeated as necessary to obtain a basic image with the desired resolution (Bn). 4. 5. 6. Image data is sampled for processing (C). The difference between the sampled and processed images is calculated (D = C - Bn). The resulting image composed of differences is output (D). Output image composed of differences 1 - - - - - - - - - -. . (0) Sampling image input (A) or (C) IP90C55 IMSC LSI chip with built in 12-port, ALU ~(::B~O~)- - - - - f - - - - - , IP90C20 RKFil Line delays Frame memory o (C) Rank filter output (Bn) Frame memory I (Bn) Overview of the IP90C55 IMSC (Image Data Stream Controller) LSI Chip This is a 12-port data stream switching LSI with 8-bit I/O signal pin (digital image bus) ports. • • The chip has twelve 8-bit image data I/O ports allowing image data stream bus configurations between each set or ports. On-chip 16-bit ALU and barrel shifter enable inter-frame computations (and can be partitioned into two 8-bit ALU-plus-barrel shifter units). • Eight internal area of interest (AOI) functions allow an image area of up to 64Kx64K-pixels to be designated. • • The chip has a maximum operating frequency of 40/20 MHz. The chip is contained in a PGA-181/QFP-184 package. H-23 SMIASSP Image Processing LSI Series IP90C25 Spatial & Logical Filter (SLFC) Sumitomo Metal Industries, Ltd. Technical Manual Ver. E 2.3 III • Sumitomo Metal Industries, Ltd. Table of Contents Section 1: Overview 1.1 Product Overview ..................................................................................................... 1 1.2 Features and Applications ........................................................................................ 1 Section 2: Pins and Functions 2.1 Package Dimensions ................................................................................................. 3 2.2 Pin Descriptions ....................................................................................................... 4 Pin Functions ............................................................................................................ 5 Pin Configuration ..................................................................................................... 7 Pin Assignments ........................................................................................................ 8 2.3 2.4 2.5 Section 3: 3.1 3.2 3.3 3.4 Internal Block Functions Block Diagram ......................................................................................................... 9 Input Pixel Scan Register .......................................................................................... 10 Computation Block ................................................................................................... 10 Output Pixel Selector Block. ..................................................................................... 10 3.5 RAM/Register Control Block .................................................................................... 10 3.6 RAM Look-Up Table (LUT) ...................................................................................... 10 Host Access Control Block ........................................................................................ 10 3.7 Section 4: 4.1 4.2 4.3 4.4 4.5 Section 5: 5.1 5.2 5.3 5.4 5.5 5.6 5.7 Registers Address Map ............................................................................................................ 11 Control Register ....................................................................................................... 12 Bias Value Register ................................................................................................. 12 Shift Value Register ................................................................................................ 12 Coefficient Registers ................................................................................................ 12 Operating Description Mode Summary ........................................................................................................ 13 Spatial Filtering: Direct Mode ................................................................................. 13 Spatial Filtering: LUT Mode .................................................................................... 16 Logical Filtering: Direct Mode ................................................................................. 16 Logical Filtering: LUT Mode .................................................................................... 16 Startup Sequence ...................................................................................................... 17 Relation of NLI and NLO ........................................................................................ 17 I-i Section 6: Electrical Characteristics 6.1 6.2 Absolute Maximum Ratings ........................................................................................ 19 Recommended Operating Conditions ........................................................................... 19 6.3 DC Characteristics ..................................................................................................... 19 6.4 Pin Capacitance ......................................................................................................... 19 6.5 AC Characteristics ..................................................................................................... 20 III I-ii Section 1· Overview 1 .1 Product Overview The IP90C25/IP90C25-HS LSI chip performs filtering processes on 3 x 3-pixellocal image areas at speeds up to 25 MHz (IP90C25) or 50 MHz (IP90C25-HS). The chip's high-speed capabilities make it suitable for use with high-definition television, as well as in industrial applications. The IP90C25's operating modes can be broadly grouped into spatial filter modes, which process 8-bit grayscale image data, and logical filter modes, which process binary image data. In spatial filter mode, the IP90C25 performs spatial filtering on 8-bit grayscale image data input, using a filtering coefficient that can be programmed using 8-bit two's-complement format. In logical filter mode, the IP90C25 performs logical filtering on binary image data input. Logical formulas can be defined by writing truth-table values into a look-up table (LUT). Thus, a wide variety of logical filter processes can be executed by rewriting the LUT contents. The LUT can also be used for grayscale conversion in spatial filter mode. 1.2 Features and Applications Features • Spatial filter mode: Programmable coefficient strings Sum-of-products calculation eliminates overflow Right bit-shifter and adder for output compensation LUT for grayscale conversion • Logical filter mode: -- • LUT allows input of logical formulas Maximum operating frequency (pixel clock): IP90C25: fmax =25 MHz IP90C25-HS: f max • = 50 MHz Local area size: 3 x 3 pixels • Process: CMOS • Power supply: 5V single source • Package: 84-pin PLCC I-I Sample Applications • Spatial filtering Noise reduction Edge emphasis Edge extraction Density conversion • Logical filtering Expansion Reduction Fine-line drawing Outline extraction Feature extraction: end points, intersections, lines (horizontal, vertical, diagonal), etc. Elimination of single points 1-2 Section 2: Pins and Functions 2.1 Package Dimensions 74 54 53 75 Index 84 1 o o'" ----------------------;------------------------ ._ +1 I 33 11 12 units: mm so +1 ---II . . 0.46±0.1O 28.45 ± 0.38 84-pin PLCC package 1-3 2.2 Pin Descriptions Pin group Symbol Image input bus PIXlIN7-0 Image output bus CPU bus Test signals Power supply and GND Unconnected Total number of pins Note: No. of Pins Type Description 1st line of pixel input (Previous) 8 I PIX2IN7-0 8 I 2nd line of pixel input (Current) PIX3IN7-0 8 I 3rd line of pixel input (Following) PIXCLKI 1 I Pixel clock input NLI 1 I New line in PIXOUT7-0 8 0 Pixel output PIXCLKO 1 0 Pixel clock output NLO 1 0 New line out AB9-0 10 I Address bus DB7-0 8 I/O WE* 1 I Write enable RE* 1 I Read enable CE* 1 I Chip enable TEST RESET 1 I Test input signal TEST RAM 1 I Test input signal TESTR/W 1 I Test input signal TESTING2 1 0 Test output signal TESTINGI 1 0 Test output signal Vddi 5 PWR Internal cell power supply Vddo 5 PWR I/O buffer power supply VSSi 5 PWR Internal cell ground VSSo 5 PWR II 0 buffer ground NC 2 NC Data bus 84 Make sure the sync/force current for PIXOUT7-O, PIXCLKO, and NLO does not exceed 4 rnA, and the load capacity does not exceed 20 pF. Also, make sure the sync/force current for DB7-O does not exceed 2 rnA, and the load capacity does not exceed 40 pF. 1-4 2.3 Pin 2.3.1 Functions Clock Power and Test Pins PIXCLKI Main clock for the device. Pixel data input through pins PIXlIN7-O, PIX2IN7-0, and PIX3IN7-0 is sampled at the rising edge of the PIXCLKI signal. PIXCLKO (2 rnA, 20 pF load max) Output clock for the device. Output pixel data is latched in synchronization with the rising edge of this signal. TEST RESET (Level = TTL) Used for pre-delivery testing of the IP90C25. Connect this pin to Vdd during normal operation. TEST RAM (Level = TTL) Used for pre-delivery testing of the IP90C25. Connect this pin to Vdd during normal operation. TEST R/W (Level = TTL) Used for pre-delivery testing of the IP90C25. Connect this pin to Vdd during normal operation. TESTSIGI (Level = TTL) Used for pre-delivery testing of the IP90C25. Leave this pin unconnected during normal operation. TESTSIG2 (Level = TTL) Used for pre-delivery testing of the IP90C25. Leave this pin unconnected during normal operation. VSSi (Device ground) Ground pin for internal logic cells and input buffer. Vddi (Device power) Power supply (5V) for internal logic cells. VSSo (Device ground external power) Ground pin for the output buffer. Vddo (Device power external power) Power supply pin for the output buffer. Note: Make sure the power pins (VSSi, Vddi, VSSo, Vddo) are electrically connected to the outside. 1-5 2.3.2 Host Interface Pins CE* (Chip Enable) (Level = TTL) Enables host computer access (including read and write cycles) when a low-level signal is received. RE* (Read Enable) (Level = TTL) Functions with the CE* pin to enable the read cycle when both signals are low. WE* (Write Enable) (Level = TTL) Functions with the CE* pin to enable the write cycle when both signals are low. Note: If the RE* and WE* signals are both low at the same time, the chip may not function normally. AB9-O (Address Bus) (Level = TTL) Address bus for LUT and register addresses. DB7-O (Data Bus) (Level = TTL, 2 mA, 40 pF) Data bus that transfers data to and from the host computer during read and write cycles. In a read cycle, data is read through the DB bus from the designated LUT or register. In a write cycle, data is sent to the chip through the DB bus and written into the designated LUT or register addresses. 2.3.3 Pixel Data Interface Pins PIXlIN7-0 (Pixel Line 1 Input) (Level = TTL) Receive input of the first line of pixel data, which is latched by the rising edge of the PIXCLKI clock signal. The first line of pixel data represents the line immediately above the current scan line. PIX2IN7-O (Pixel Line 2 Input) (Level = TTL) Receive input of the second line of pixel data, which is latched by the rising edge of the PIXCLKI clock signal. The second line of pixel data represents the current scan line. PIX3IN7-O (Pixel Line 3 Input) (Level = TTL) Receive input of the third line of pixel data, which is latched by the rising edge of the PIXCLKI clock signal. The third line of pixel data represents the line immediately following the current scan line. NLI (New Line In) (Level = TTL) Carries the signal indicating that the current pixel data input is valid. This signal must be low whenever valid data input is being received. PIXOUT7-O (Pixel Out) (Level = TTL, 2 rnA, 20 pF load max) Carry data output after filter processing. If this data is latched by the system, its should be latched to the rising edge of the PIXCLKO clock signal. NLO (New Line Out) (Level = TTL, 2 mA, 20 pF load max) Carries the signal indicating that the current pixel data output is valid. The NLO signal is delayed with respect to the NLI signal by the length of time required for filter processing. 1-6 N ~ -c >-l >-l;lt;l t'r1",,>-l::S >-l m R cn~~ y ::::J (") o ~~~~ ~1--0("""1--0( ><><><>< »»»>-l_~_._.O-NW CO .., C III nO ;::; AB2=:§~ I ABI ABO Vddo VSSo PIXOUT7 PIXOUT6 PIXOUT5 PIXOUT4 PIXCLKO Vddo VSSo NLO PIXOUT3 PIXOUT2 PIXOUTI PIXOUTO Vddo VSSo DB7 DB6 , "I oooooo«~~n«~~z«::s::s::s ~~~~~~~""mt'r1t'r1~""'<=>C See "Image Interface Timing" on page 21 for the values of tnis and tnos. Relation of Rising Edge of NLI and NLO NLI-to-NLO Delay Mode Delay (ted) Spatial filtering: Direct 32 cycles Spatial filtering: LUT 38 cycles Logical filtering: Direct 8 cycles Logical filtering: LUT 14 cycles 1-18 Section 6. Electrical Characteristics 6.1 Absolute Maximum Symbol Rating Unit Supply voltage Vdd -0.3 to 6.5 V Input voltage Vin -0.3 to Vdd + 0.3 V Operating temperature Topt Oto70 °C Storage temperature Tstg -10 to 80 °C Item 6.2 Recommended Operating Conditions Symbol Conditions Min. Supply voltage Vdd - 4.75 - H level input voltage VlH 2.0 - - V L level input voltage VIL - - - 0.8 V Item 6.3 DC Typ. Max. Unit 5.25 V Characteristics Item Input leak current Symbol Conditions Min. Typ. Max. Unit lIN - -10 - 10 Il A H level output voltage VOH IOH =-2mA 2.4 - - V L level output voltage VOL IOL=2mA - - 0.4 V Off-state leak current IOZ -10 - 10 Il A Note: 6.4 Ratings Pin - The output shorting current is the absolute maximum voltage that can be applied to a pin for one second without causing a short. Capacitance Item Input capacitance Output capacitance 1/0 capacitance Symbol Conditions Min. Typ. Max. Unit CIN - - - 7 pF COUT - - - 10 pF CIO - - - 10 pF 1-19 6.5 AC Characteristics Load capacitance = 30 pF. Host Computer Interface Timing 4.75 V ::; Vdd ::; 5.25 V VSS=OV Ta = 0 to 70°C Symbol Min. CE* setup time tcs Ons Ons CE* hold time tch Ons Ons Address setup time tas IOns IOns Address hold time tah Ons Ons Data setup time tds IOns IOns Data hold time tdh lOns lOns Data float delay tdhz - 20ns 20ns Data bus active delay tdJz 20ns tacc 20ns Data delay tacc 40 ns + Iltcyc 260ns RE* pulse width tr 40 ns + lltcyc 260ns Read cycle time trc 50 ns + 13tcyc 3l0ns WE' pulse width tw lOns + 2tcyc SOns Write cycle time twc 20 ns + 10tcyc 220ns WE' high period tcdww 10 ns + Stcyc 170ns Write/read interval time tcdwr IOns + Stcyc l70ns Read/write interval time tcdrw 10 ns + 2tcyc SOns RE* high period tcdrr IOns +2tcyc SOns Parameter I-20 Max. SO MHz Image Interface Timing 4.75 V s Vdd s 5.25 V VSS = OV Ta =0 to 70°C Max. Symbol Min. IP90C25 cycle time teye 38.0 ns IP90C25-HS cycle time teyc 18.4 ns NLI minimum signal width tnl 10 ns + I1tcye ns NLI setup time tnis 4.0 ns NLI hold time tnih 8.0 ns Image input setup time tpis 4.0 ns Image input hold time tpih 8.0 ns Clock signal rise time teir 2 ns Clock signal fall time teif 2 ns NLI input rise time tnir 2 ns NLl input fall time tnif 2 ns NLO output setup time tnos 4.0 ns NLO output hold time tnoh 4.0 ns Pixel output setup time tpos 4.0 ns Pixel output hold time tpoh 4.0 ns NLO output delay tnod 2.0 20 ns Pixel output delay tpod 2.0 20 ns Clock output delay teod 1.5 15 ns Clock output rise time teor 2 ns Clock output fall time teof 2 ns NLO output rise time t nor 2 ns NLO output fall time tnof 2 ns Parameter 1-21 50 MHz Host Computer Write Cycle CEO RE* ~------tw------~~ WE* las AB [9-0] DB [7-0] Host Computer Read Cycle CEO RE* kdwr~~~--------------- WE* AB [9-0] DB [7-0] ----------------+----< tdlz Note: See "Host Computer Interface Timing" on page 20 for the values of the parameters shown above. 1-22 Image Input Timing tcir PIXCLKI tpis BUF PIXxL7-0 BUF ~-+-------tnl-----------.J NLI tnif tnir tnis Image Output Timing PIXCLKO PIXOUT NLO III~ Note: See "Image Interface Timing" on page 21 for the values of the parameters shown above. I-23 Image Output Timing (from PIXCLKI) PIXCLKI PIXCLKO PIXOUT NLO Note: See "Image Interface Timing" on page 21 for the values of the parameters shown above. 1-24 SMIASSP Image Processing LSI Series IP90C31 Multiplier & Accumulator with 4 Multipliers (MAC4) Sumitomo Metal Industries, Ltd. Technical Manual Ver. E 1.4 • Sumitomo Metal Industries, Ltd. Table of Contents Section 1 1.1 1.2 1.3 Section 2 2.1 2.2 2.3 Section 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Section 4 4.1 4.2 4.3 4.4 Section 5 5.1 5.2 5.3 5.4 5.5 Section 6 6.1 6.2 6.3 6.4 Overview Functional Overview and Characteristics..................................................................... 1 Floating-Point Format................................................................................................... 1 Block Diagram............................................................................................................. 2 Pins and Functions Pin Lists and Functional Descriptions.... ...................... ...................... ................ ............ 3 Pin Assignments........... ................. .......... ........ .................................. .... ... ........ ........... .. 4 External Dimensions..................................................................................................... 6 Operating Description Overview of Operations............................................................................................... Multiplication.............................................................................................................. Cumulative Adder-Subtractor Blocks............................................................................ Sample Register........................................................................................................... Cascade Connections.......... ... ...... ........ ........... ................ ............... ........ ... ..................... Floating-Point Output................................................................................................... Fixed-Point Output....................................................................................................... Number of Steps in Pipeline Processing......................................................................... Overflow Flag.............................................................................................................. 7 7 7 7 7 8 8 8 8 Programmable Resources The Control Register and IFMD Pin.............................................................................. 9 Parameter Descriptions................................................................................................. 9 Status After Reset ........................................................................................................ 11 List of Parameters ........................................................................................................ 11 Electrical Characteristics Absolute Maximum Ratings ........................................................................................... Recommended Operating Conditions............................................ ............................... .. Input/Output Pin Capacity ........................................................................................... DC Characteristics....................................................................................................... AC Characteristics ....................................................................................................... 12 12 12 13 14 Sample Applications Center of Brightness..................................................................................................... Center of a DeSignated Labeling Area.......................................................................... Moving Normalized Correlation Calculation ................................................................ Audio FIR Filter ........................................................................................................... J-i 17 18 19 20 Section 1. Overview 1.1 Functional Overview and Characteristics The IP90C31 LSI chip is designed for high-speed product-sum calculations. It contains four 8-bit x 8bit multipliers and a 40-bit accumulator, and has an optional setting that allows it to perform 16bit x 16-bit multiplication and product-sum calculations. The chip outputs data in 16-bit floating decimal-point (floating-point) format, and includes a selector that enables access to any 20 bits on the 40-bit bus. The IP90C31 also includes a setting for rounding processing. Multiple IP90C31 chips can be connected through the sample register block to form a cascade connection. The IP90C31 has the following characteristics: I-bit sign, 6-bit exponent, 9-bit mantissa • Floating-point format 40 bits • Accumulator bit width CPU interface or direct terminal connection • External interface 30 MHz • Maximum operating frequency 5-V single source • Power supply CMOS • Process TTL-level compatible • I/O interface 160-pin plastic QFP • Package 1.2 Floating-Point Format The IP90C31 output block includes a floating-point conversion circuit, which allows output from the IP90C31 to be passed directly to an IP90C32 chip. • Total width 16 bits (bit IS-bit 0). bit 15: 1 bit sign bit exponent bit 14-bit 9: 6 bits S o= pos, 1 = neg e 0-63 The actual exponent value is e-b, where b is the bias value. bit 8-bit 0: 9 bits mantissa m Positive binary values (offset binary) indicate values after the decimal point, and do not include integer components. • The integer component is determined by the exponent. e 1'- 0 -> integer component I = 1 e =0 -> integer component I = 0 • Zero (0) is expressed as e = 0 and m = O. Non-normal data (de-normalized values) are not handled, so that values with e = 0 are always processed as m = O. • In equation form, (_I)S x Lm x 2(e-b). Decimal position \l Sign bit s Note: Iexponent e (6-bit) I mantissa m The IP90C31 always has a bias value b of 1. J-l (9-bit) 1.3 Block Diagram ..........~ ~~I---{ -=S 1,0':: SMPL ADC3 PA Delay stages (0-3 steps) PB CSUM -+- PC .~ ~ :.a .0I ..... ..... 00] PD ADCO cI(!"O .;::= :Ea rI) PE ~ ~:.= ..... c.. .0I ..... ..... ADC2 00"3 S PF I/F & Control PO - .....~ ..... c.. ..... .0I ..... ..... 00"3 8 PH Note: the ADCl CSDI(19:0) "0" symbol indicates pipeline registers. J-2 IFMD Section 2. 2.1 Pins and Functions Pin Lists and Functional Descriptions Signal group Pin symbol Control signals Input ports Function No. Type RST* 1 I Reset ICLK 1 I Clock input RD* 1 I Read signal WR* 1 I Write signal CS* 1 I Chip select signal DB(15:0) 16 I/O IFMD 1 I Interface mode select pin ACC(1:0) 2 I Accumulator control signal Data bus SMP 1 I Simple register control signal MOZ(3:0) 4 I Sets multiplier output to zero ODEN* 1 I Output port OD enable pin TEST* 1 I Test signal, normally 1 PA(7:0) 8 I Input port PA PB(7:0) 8 I Input port PB PC(7:0) 8 I Input port PC PD(7:0) 8 I Input port PD PE(7:0) 8 I Input port PE PF(7:0) 8 I Input port PF PG(7:0) 8 I Input port PG PH(7:0) 8 I Input port PH CSDI(19:0) 20 I Cascade input port Output ports OD(19:0) 20 0 Output port OD OVF 1 0 Power & Vdd 12 Power 5V Ground GND 12 Ground OV Note: Overflow flag output An asterisk (*) after a signal name denotes that signal uses negative logic (active low). J-3 2.2 Pin Assignments Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Symbol GND PAO PAl PA2 PA3 PA4 PAS PA6 PA7 PBO PB1 PB2 PB3 PB4 PBS PB6 PB7 PCO PC1 (I/O) PW Vdd PW PW GND PC2 PC3 PC4 PC5 PC6 PC7 PDO PD1 PD2 PD3 PD4 PD5 PD6 PD7 PEO PEl PE2 PE3 Vdd I " " " " " " " " " " " " " " " " " I " " " " " " " " " " " " " " " " " PW Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Symbol GND PE4 PES PE6 PE7 PFO PF1 PF2 PF3 PF4 PF5 PF6 PF7 PGO PGl PG2 PG3 PG4 PG5 Vdd GND PG6 PG7 PHO PHI PH2 PH3 PH4 PHS PH6 PH7 CSDIO CSDIl CSDI2 CSDI3 CSDI4 CSDI5 CSDI6 CSDI7 Vdd J-4 (I/O) PW I " " " " " " " " " " " " " " " " " PW PW I " " " " " " " " " " " " " " " " " PW Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Symbol GND CSDI8 CSDI9 CSDI10 CSDl11 CSDIl2 CSDIl3 CSDIl4 CSDIl5 CSDIl6 CSDIl7 CSDIl8 CSDI19 Vdd GND ODO 0D1 OD2 OD3 Vdd GND OD4 ODS OD6 OD7 OD8 OD9 0D10 0D11 Vdd GND 0D12 OD13 0D14 0D15 OD16 0D17 0D18 0D19 Vdd (I/O) PW I " " " " " " " " " " " PW PW 0 " " " PW PW 0 " " " u " " " PW PW 0 " " " " " " " PW Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin Symbol GND OVF Vdd ODEN* ACCO ACC1 MOZO MOZI MOZ2 MOZ3 SMP IFMD TEST* RST* CS* WR* RD* GND ICLK Vdd GND DBO DBI DB2 DB3 DB4 DB5 DB6 DB7 Vdd GND DB8 DB9 DB10 DBll DB12 DB13 DB14 DB15 Vdd (I/O) PW 0 PW I u u u u u u u u u u Note 1: Note 2: Note 3: The IFMD pin is a Schmitt input. The TEST* pin is a Schmitt input, with pull-up resistance. The RST* pin is Schmitt input, with pull-up resistance. u u u PW I PW PW I/O u u u u u u u PW PW I/O III u u ! u u u u u PW J-5 2.3 External Dimensions 32.0±0.4 28.0±O.l O.lS±O.OS INDEX 3.3S±0.1 2S.3S±0.lS 304 . ± 02 . (30.2) r o°;£8;£7° 1 1. -- - 0.8±0.2 - r-- - V) 0 +1 V) 0 J-6 \ ~ 0.S3MAX Units: mm Section 3. Operating Description 3.1 Overview of Operations The IP90C31 LSI chip is designed for high-speed product-sum calculations. It contains four 8-bit x 8bit multipliers and a 40-bit accumulator, and has an optional setting that allows it to perform 16bit x 16-bit multiplication and product-sum calculations. The chip outputs data in 16-bit floating-point format, and includes a selector that enables access to any 20 bits on the 40-bit bus. The IP90C31 also includes a setting for rounding. Multiple IP90C31 chips can be connected through the sample register block to form a cascade connection. 3.2 Multiplication The IP90C31 contains four 8-bit x 8-bit multiplication units. These units pair input from ports P A through PH for multiplication as follows: PAx PB, PC x PD, PE x PF, and PG x PH. When 16-bit multiplication mode is selected, P A and PB are combined as 16-bit data with PA as the upper byte, and PC and PD are likewise combined as 16-bit data with PC as the upper byte (input from PE through PH is ignored). The input data can be expressed in two's-complement or unsigned binary. After the multiplication, data is expressed in two's complement form. 3.3 Cumulative Adder-Subtractor Blocks The adder-subtractor blocks take the input values PA x PB, PC x PD, PE x PF, and PG x PH from the multiplication block, and add or subtract in the following form according to designated parameters: SUM = SUM ± [ { (PA x PB) ± (PC x PD)} ± {(PE x PF) ± (PG x PH) } 1 In 16-bit multiplication mode, the processing is in this form: SUM = SUM ± (PAPB x PCPD) where PAPB represents 16-bit data in which PAis the upper byte and PB the lower byte, and PCPD represents 16-bit data in which PC is the upper byte and PD is the lower byte. The resulting SUM is expressed in two's-complement form, in 40-bit width. 3.4 Sample Register When load is enabled by the signal SMP, the SUM output by the cumulative adder-subtractor blocks is loaded into the sample register. When load is disabled, the value in the sample register is held until load is enabled again. 3.5 Cascade Connections When the cascade connection feature is enabled, values in the sample register are added to values that are determined by taking the values of the cascade data input CSDI and applying a shift value defined by OSL parameter selections. Cascade data input can be synchronized with internally generated data by adjusting the internal delay parameter. CSUM = SMPL + shift(CSDI) When the cascade connection feature is disabled, CSUM J-7 = SMPL. 3.6 Floating-Point Output When floating-point output format is used, CSUM is converted to floating-point format and output at OD15-ODO. In this case, OD19 through OD16 are set low. 3.7 Fixed-Point Output When fixed-point output format is selected, 20 bits (selected from the 40-bit CSUM by the output selection parameter OSL) are output in fixed-point format at OD19-0DO. The output is rounded according to a rounding-cutoff parameter (RCO). 3.8 Number of Steps in Pipeline Processing Input sampling Multiplication Cumulative addition - sample Delay steps CSDI input sample Cascade addition Floating-point conversion Output 1 step 1 step 1 step 0-3 steps 1 step 1 step 1 step (0 if fixed-point output is used) 1 step Total 6-10 steps Note that if fixed-point format is used, output does not go through the floating-point conversion circuit, but instead passes from cascade addition directly into the output register, reducing the number of steps by one. The number of steps is internally adjusted for direct and real-time parameters, so that as the parameters are sampled, they are simultaneously applied to the sampled data. 3.9 Overflow Flag The overflow flag is set if an overflow occurs during cumulative or cascade addition. • Accumulator (cumulative addition) overflow When an overflow occurs during cumulative addition, the overflow signal is sent when the overflow data output occurs. If the sample register is in standby, the overflow signal is held internally, and output once the sample register returns to sample status and begins to output the overflow data. • Cascade addition overflow When an overflow occurs during cascade addition, the overflow signal is output at the same time as the overflow data. The OVF output value is the logical OR of these two overflow conditions. J-8 Section 4. Programmable Resources 4.1 The Control Register and IFMD Pin The IP90C31 uses three types of parameters: direct, real-time, and fixed. Direct parameters are control signals that are input directly from pins, and used to process data that is sampled simultaneously from ports PA through PH at every clock cycle. Real-time and fixed parameters can be set using control registers through the CPU interface. However, when the IFMD pin is set to 1, pins DBIS-DBO are used for direct parameter input. In this case, the real-time parameters are sampled simultaneously with data from ports P A through PH at every clock cycle, and used to process this data. Also, when IFMD = 1, the WR* and C5* signals should be set high. Because fixed parameters are sampled at every clock cycle, they should be used to enter necessary constant parameter values. When fixed parameters have been altered, use the ACC parameter to reset the accumulator or to load valid values. When IFMD = 0, each write cycle invalidates earlier parameters, and a new set of parameters is written and becomes valid two clock cycles after the write operation is finished. The following illustration shows the relation between each parameter, pin, and register. Because the control register is only 16 bits wide, the position of each parameter bit is the same as the position (bit) of that parameter when the IFMD pin is set to 1. After a reset, all bits in the register are set to O. bit 15 <--------------------------- Control register bit position ----------------------------> bit a IADC31ADC21ADCIIADCO 1 IDCII IDCO 1 C5D 1 05L4 1 05L31 05L21 05Ll 1 05LO 1 RCO 1 OPO IMPCIIMPCol D1S <--------------------------- Pin position when IFMD = 1 --------------------------> DO 4.2 Parameter Descriptions MPC Multiplication mode control: 2 bits, fixed parameter MPCl MPCO 0 0 Operation Two's-complement format 8-bit x 8-bit 4-multiplier mode 0 1 1 Positive binary format 8-bit x 8-bit 4-multiplier mode 0 Two's complement format 16-bit x 16-bit I-multiplier mode 1 1 Positive binary format 16-bit x 16-bit I-multiplier mode OPO Output format selection: 1 bit, fixed parameter OPO Operation 0 Floating-point format output 1 Fixed-point format output RCO Round/truncate selection: 1 bit, fixed parameter RCO Operation 0 Round 1 Truncate J-9 OSL Output select: 5 bits, fixed parameter This is valid when OPO = 1. On the internal bus (CSUM), the 20 bits beginning with the bit position corresponding to the values of OSL4-OSLO are output to the OD pin. This parameter is also used with a code to shift the cascade input CSDI (20 bits), and connect it to a cascade adder. All IP90C31s used in cascade connection should be set to the same value. Examples: OSL = 0 - > OD = CSUM(19:0) OSL = 5 - > OD = CSUM(24:S) OSL = 20 - > OD = CSUM(39:20) OSL > 20 - > Output value not assured CSD Cascade input enable: 1 bit, fixed parameter CSD IDC Operation 0 Enable cascade input 1 Disable cascade input Internal delay step control: 2 bits, fixed parameter IDCl IDCO Delay 0 0 None 0 1 One clock cycle 1 0 Two clock cycles 1 1 Three clock cycles ADC Add/subtract control: 4 bits, real-time parameter The cumulative adder result SUM is determined as follows. • 8-bit multiplication mode: SUM • = SUM + (_1)ADc3 [ { (PA*PB) + (_l)ADCO (PC*PD) } +(_1)ADc2 { (PE*PF) + (_l)ADCl (PG*PH) } 1 16-bit multiplication mode SUM = SUM + (_1)ADc3 (PAPB) * (PCPD) PAPB represents 16-bit data in which PAis the upper byte and PB is the lower byte. PCPD represents 16-bit data in which PC is the upper byte and PD is the lower byte. ACC Accumulator control: 2 bits, direct parameter ACCl ACCO 0 0 Operation Cumulative addition/subtraction 0 1 Save value 1 0 Load value from multiplier (add/subtract control from ADC3 is valid) 1 1 Reset (set cumulative add/subtract SUM to 0) J-10 SMP Sample register control: 1 bit, direct parameter SMP Operation 0 Save sample register value 1 Load accumulator input value to sample register MOZ Multiplier zero control: 4 bits, direct parameter MOZn Operation 0 Normal operation 1 Set nth multiplier input to zero MOZO = 1: Fix P A and PB input at zero. MOZ1 = 1: Fix PC and PD input at zero. MOZ2 = 1: Fix PE and PF input at zero. MOZ3 = 1: Fix PG and PH input at zero. In addition to controlling calculations, MOZ can be used to reduce power consumption when the IP90C31 is not in use. 4.3 Status After Reset After reset, all control registers are set to O. The values in the accumulator, sample register, and output registers are undetermined. 4.4 List of Parameters Parameter Type Description 1:0 Fixed Multiplication mode control 2 Fixed Floating/fixed-point output format Bits Bit location MPC 2 OPO 1 RCO 1 3 Fixed Round/ truncate selection OSL 5 8:4 Fixed Output select CSD 1 9 Fixed Cascade input enable IDC 2 11:10 Fixed Internal delay step control ADC 4 15:12 Real-time Add/ subtract control ACC 2 Direct Direct Accumulator control SMP 1 Direct Direct Sample register control MOZ 4 Direct Direct Multiplier zero control J-ll DI Section 5. 5.1 Electrical Characteristics Absolute Maximum Ratings Symbol Rating Unit Vdd -0.3 to 6.5 V Input voltage Vi -0.3 to Vdd+0.3 V Input current Ii ±10 rnA Item Power supply voltage 10 10 rnA Operating temperature Topt o to 70 Storage temperature Tstg -10 to 80 DC DC Output current 5.2 Recommended Operating Conditions (GND = OV, Ta = 0° to 70°C) Item Conditions Vdd High-level input voltage Vih TTL level Low-level input voltage ViI normal input Min Typ Max Unit 4.75 5.0 5.25 V 2.0 Vdd V 0 0.8 V High-level input voltage Vih SCHMITT 2.25 Vdd V Low-level input voltage Vil input (note 1) 0 0.8 V Input rise time Tri TTL level 0 100 ns Input fall time Tfi normal input 0 100 ns Input rise time Tri SCHMITT 0 1000 ns Input fall time Tfi input (note 1) 0 1000 ns Max Unit Note 1: 5.3 Symbol Power supply voltage The three Schmitt trigger input pins are RST*, TEST*, and IFMD. Input/Output Pin Capacity (Vdd Item = Vi =OV) Symbol Conditions Min Typ Input pins Cin f=lMHz 10 pF Output pins Cout f=lMHz 10 pF I/O pins Cin f=lMHz 10 pF J-12 5.4 DC Characteristics (Vdd = 5V±5%, GND = OV, Ta = 0° to 70°C) Symbol Item Conditions Static current consumption (note 1) II Vi = Vdd or GND Output short current (note 2) los Vdd = Max, Vo = Vdd (all output and I/O pins) Vdd = Max, Vo = 0 Min Typ Max Unit 200 JlA rnA 15 50 130 -5 -25 -100 Low-level input leak current -10 ±1 10 Vi = GND = GND -35 -115 -350 JlA JlA Iih Vi = Vdd -10 ±1 10 JlA Low-level output voltage Vol 101 = 4 rnA High-level output voltage (note 4) Voh loh Voh 101 = -4 rnA 2.4 SCHMITT hysteresis voltage Vsch ViI to Vih 0.4 Normal I/O pins Iil Pins with pull-up resistance (note 3) lipl High-level input leak current (all input and I/O pins) Note Note Note Note 1: 2: 3: 4: Vi = -0.5 rnA 0.2 4.5 0.8 Excluding static current consumption to pull-up and pull-down resistors. Output short current for one second or less, at one LSI pin. The two pins' pull-up resistors are RST* and TEST*. Output is CMOS level (TTL level). J-13 0.4 V Vdd V Vdd V V 5.5 AC Characteristics Write cycle: CS* WR* I t - tds DB(15:0) _ _ _ _ _---'~ Note: -~I--~ valid data tds and twrh are determined by the rising edge of CS* or WR*, whichever is faster. Writing occurs when both CS* and WR* are low. Read cycle: CS* RD* DB(15:0) - - - - - - - 1 valid data \J High impedance r--- --"'---..!..-----<'-- ;'1-. : "H"or"L" Note: trdd is determined by the falling edge of CS* or RD', whichever is slower. tzd is determined by the rising edge of CS* or RD*, whichever is faster. Reading occurs when both CS* and RD* are low. J-14 2) Clock Reset Timing ICLK 1 1 \--tckc--j t+--+i I 1 1 tckl I ·V 1 t·1- \ 1 ~tdis 1 Input datal control signals tckh 1 1 1 ICLK I I trsw ~- RST* 1 1 1 ~ 1 1 valid data \ 1 r i 1 tdod I- OD(19:0) OVF I tdih-' .1 ~ valid data Ports related to input datal control signal when ACC, SMP, MOZ, IFMD = 1: DB(15:0), PA,PB,PC,PD,PE,PF,PG,PH,CSDI 3) Control/Data Signal Timing ODEN* 1 1 tdod. 1 I- OD(l9:0)- \'---~/ 1---f 1tzod l I-+--+!I ~ ----~~I valid data 1. ~I-II----------« . J-15 High Impedance 1 - .- - - Timing Table Load capacity for all output pins is 30 pF. Unit: ns Item Symbol Min CS* pulse width tcsw 20 WR* pulse width twrw 20 Data setup time tds 15 Data hold time twrh 3 RD* pulse width trdw 20 Data delay trdd Data delay to HiZ tzd Clock cycle time tckc 33 Clock high time tckh 13 Clock low time tckl 13 Input! control signal setup time tdis 8 Max 20 15 Input! control signal hold time tdih 3 Output delay tdod 3 Output delay to HiZ tzod J-16 Typ 20 15 Section 6. Sample Applications The IP90C31 and IP90C32 are designed to perform arithmetic calculations, and can therefore be used in a wide variety of fields. This section introduces one possible application, calculating the center of an image, which involves normalized correlation calculations. 6.1 Center of Brightness Used in combination, the IP90C31, IP90C32, and IP90C51 can calculate the center of brightness of an image using hardware functions alone, induding the IP90C31's 40-bit accumulator and the IP90C32's floating-point calculation functions. Image data B Synchronization signal E:::;::':::"-'~::':'::7-I~1 Hxof(x,y) Horizontal center of brightness Hf(x,y) IP90C32 Vertical center of brightness Hyof(x,y) Hf(x,y) Vertical addresses About Centers of Brightness A two-dimensional image has a quantitative measurement of brightness at any point (x, y), which can be represented by f(x, y). From this can be calculated a primary moment and center of gravity, referred to respectively as the primary moment of brightness and the center of gravity of brightness. The coordinates of the center of gravity of brightness can be expressed as the horizontal primary moment of brightness and the vertical primary moment of brightness divided by the sum of brightness values (the O-order moment of brightness) , thus: Sum of Brightness Values The sum of brightness values, which can also be thought of as the O-order moment of brightness, are expressed by the following formula: Moo = moo = L.LJ(x,y) y where f(x, y) is the brightness (grayscale value) of the pixel at coordinates (x, y). J-17 Primary Moment of Brightness The primary moment of brightness is defined by the following equations. The IP90C51 provides horizontal and vertical coordinates and grayscale values. The IP90C31 then calculates the sum of the products of these coordinates and grayscale values, and calculates the primary moment of brightness around the origin. mOl = L.L.yef(x,y) y mlO = L. L. x e f( x, y) y Using these measurements and the sum of brightness values, the IP90C32 determines the center of gravity of brightness by division. 6.2 Center of a Designated Labeling Area The IP90C31, IP90C32, and IP90ClO (or IP90Cll) in combination can determine the center of a designated labeling area using hardware functions alone. The IP90CIO labels incoming binary image data and passes it to the IP90C51, which uses ternary functions to extract an area designated by label numbers. The data for this area then goes to the center-of-gravity calculation circuits of the IP90C31 and IP90C32. The center-of-gravity circuits in this example function in the same way as in the center of brightness example above, except that they handle binary data. Image data Horizontal center of gravity Synchronization signal t-==""--+1 IP90C32 Vertical center of gravity Vertical addresses J-18 6.3 Moving Normalized Correlation Calculation The formula below can be used to provide real-time calculation of moving normalized correlation, without subtracting average values. This type of calculation is used in a wide variety of fields, including measuring signal delays with distance measurement equipment, finding pitch in harmonic analysis, detecting synchronization in communications, and reducing noise. j+w~l ,:E (XtYj) 1=J j+w~l j+w-l l=J I=J Where w is the width of the area (window) for normalized processing ,:E x? ~ Y? • Direction • • of movement • • • • • • • --.. x·J • Yj • I• I- • Direction • • of movement • • • • • • I --.. - -I W j+w·l x·J 4w-step delay~ :E X21 IP90C31 i=j j+w·} ~ IP90C31 I=J (xj"Yj) rw-step delay! IP90C31 j+w·l ~ yj2 I=J J-19 --. --. j+w-l Cj IP90C32 f--+- ~ (xj"Yj) I=J j+w-l j+w-l I=J l=J ~ Xj2 ~yj2 III i 6.4 Audio FIR Filter The IP90C3I's high speed and wide processing capability make it well suited for use in high-order audio FIR filters. The general FIR filter function is expressed by the following formula: N y[ n] = L h[ k] . x[ n - k] k=O The various tap coefficients h[k] are written to coefficient ROM, and the past N cycles of audio data, x[n-k], are stored in the shift register. The IP90C31 multipliers are used in time multiplex scheme, and the tap coefficients and past sampling values from the shift register are taken as input to a sum-of-products calculation. Because each sum-of-products calculation must be completed before new audio data is sampled, theoretically the filter has a maximum level of taps (in I6-bit, I-multiplier mode) equal to the ratio between the IP90C31's operating frequency and the sampling frequency of the audio signal. If 8-bit, 4-multiplier mode can be used, the above ratio is extended by a factor of four, which is effective for simulations. Also, the IP90C3I's ability to use cascade connections makes it easy to link several IP90C31s for still higher order filtering. Data input _ M U X Shift register IP90C31 Timing signal ---4....---I~ Address counter Coefficient ROM J-20 Filter Output SMIASSP Image Processing LSI Series IP90C32 Configurable Arithmetic Operator (CAROL) Sumitomo Metal Industries, Ltd. Technical Manual Ver. E 1.5 • Sumitomo Metal Industries, Ltd. Table of Contents Section 1 1.1 1.2 1.3 Section 2 2.1 2.2 2.3 Section 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 Section 4 4.1 4.2 4.3 4.4 4.5 Section 5 5.1 5.2 Overview Functional Overview and Characteristics..................................................................... Floating-Point Format................................................................................................... Block Diagram.... .............................. ............ ... ....... ..... ................................................ 1 1 2 Pins and Functions Pin Lists and Functional Descriptions............................................................................ 3 PinAssignments ............................................................................................................ 4 External Dimensions................................................... ..... ............................................. 6 Operating Description Overview of Operation...... ....... ..... ..... .... ..... ... ..... ... ....... ..... ......... ........ ......... .... ........ .... Input Format..... ............................................................................................................ Input Data.......................... .......... ..................................... ........................................... Pipeline Synchronization.............................................................................................. Constant Register.......................................................................................................... Main Calculator ......................................... ......................... ............................... .......... Main Calculator Input/Output Optional Circuits.......................................................... Fixed-point Circuits...................................................................................................... Addition Circuits.................................................................... ...................................... Shift and Rounding Circuits.......................................................................................... Output Clipping ........................................................................................................... Number of Steps in Pipeline Processing......................................................................... Zero Division Flag ....................................................................................................... Power-Saving Mode ...................................................................................................... 7 7 7 7 7 7 7 8 8 8 8 9 9 9 Programmable Resources IFMD Pin ...................................................................................................................... Signal Names Used in Descriptions .................................................. ,........................... Parameter Descriptions ................................................................................................. Default Values ............................................................................................................. List of Parameters........................................................... ............................................. 10 10 11 17 18 Variable Bit-Width Mode Pin Correspondence............................. ....... ................................................................... 19 Internal Hardware ....................................................................................................... 20 K-i Section 6 6.1 6.2 6.3 Electrical Characteristics 6.4 Absolute Maximum Ratings ........................................................................................... Recommended Operating Conditions............................................................................. Input/ Output Pin Capacity........................................................................................... DC Characteristics ....................................................................................................... 6.5 AC Characteristics ....................................................................................................... 24 Section 7 7.1 7.2 7.3 7.4 22 22 22 23 Sample Applications Center of Brightness ..................................................................................................... Center of a Designated Labeling Area.......................................................................... Moving Normalized Correlation Calculation ................................................................ floating-Point Conversion Circuit ................................................................................. K-ii 27 28 29 30 Section 1. Overview 1.1 Functional Overview and Characteristics The IP90C32 LSI calculator chip is designed to perform a variety of calculations on floating-point data. It does this using internal bus switching and on-chip functions that include three multipliers, and inverse value, square root, and inverse square root calculators. The IP90C32 also includes an adder to sum computation results, and external connections for registers and shift registers for cumulative addition. A shifter is placed at the readout for results of cumulative addition. The IP90C32 is designed to be used with the IP90C31 chip for high-speed execution of normalized correlation calculations. I-bit code, 6-bit exponent, 9-bit mantissa • Input floating-point format I-bit code, 8-bit exponent, 9-bit mantissa • Internal floating-point format Multiplication, division, square root, etc. • Types of calculation Output Fixed or floating-point format 30 MHz • Maximum operating frequency 5-V single source • Power supply Process CMOS TTL-level compatible • I/O interface 160-pin plastic QFP • Package 1.2 Floating Decimal Point Format The IP90C32 accepts data in the following format (the same as for the IP90C31): • Total width 16 bits (bit IS-bit 0). bit 15: 1 bit code bit S o =pos, 1 =neg bit 14-bit 9: 6 bits exponent e 0-63 The actual exponent value is e-b, where b is the bias value. bit 8-bit 0: 9 bits mantissa m Positive binary values (offset binary) indicate values after the decimal point, and do not include integer components. • The integer component is determined by the exponent. ei'O -> e = 0-> • • integer component integer component I= 1 1=0 Zero (0) is expressed as e = 0 and m = O. Non-normal data (de-normalized values) are not handled, so that values in which e always processed as m = o. In equation form, (-1)3 x Lm x 2(e-b). In the IP90C32 chip, the bias value b can be set to 1 or 32. Decimal position Code set s \l I exponent e (6-bit) I mantissa m K-l (9-bit) = 0 are 1.3 Block Diagram * ZA '50 ~ ~ U c:l .~ XR 0.. ~ ~ " :E :E 0 U -< FA(l5:0) Fixed decimal point circuit A il XAB YB il " <1.) Fixed decimal point circuit B :§. "§ :E " 0.. FB(15:0) .... <1.) :a YA <1.) ';:l :; :E FC(l5:0) FD(l5:0) ~-------+------------+-+-~RZDF ~-----------+------------+-+-~DZDF FE(15:0) ADA -< QC OA(15:0) QE SFEN c:l IfF & Control t WR*. t IFMD t AD t QF DB RD'. CS* ADB K-2 OB(15:0) Section 2. 2.1 Pins and Functions Pin Lists and Functional Descriptions No. Type 1 I Reset ICLK 1 I Clock input RD* 1 I Read signal WR* 1 I Write signal CS* 1 I Chip select signal DB(3:0) 4 I/O Data bus Address bus Signal group Pin symbol Control signals RST* Input ports Output ports Function AD(4:0) 5 I/O IFMD 1 I Interface mode select pin ADA(1:0) 2 I Adder A control signal ADB(1:0) 2 I Adder B control signal SF EN 1 I Shift enable signal TEST* 1 I Test signal, normally 1 FA(15:0) 16 I Input port FA FB(15:0) 16 I Input port FB FC(15:0) 16 I Input port FC FD(15:0) 16 I Input port FD FE(15:0) 16 I Input port FE OA(15:0) 16 0 Output port OA OB(15:0) 16 0 Output port OB DZGF 1 0 Zero division flag RZDF 1 0 Power & Vdd 12 Power 5V Ground GND 13 Ground OV K-3 Inverse root zero division flag 2.2 Pin Assignments Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Pin Symbol GND FAO FA1 FA2 FA3 FA4 FA5 FA6 FA7 FA8 FA9 FA10 FAll FA12 FA13 FA14 FA15 FBO FBI (I/O) PW I " Vdd PW PW I GND FB2 FB3 FB4 FB5 FB6 FB7 FB8 FB9 FB10 FBll FB12 FB13 FB14 FB15 FeO Fe1 Fe2 FC3 Vdd " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " PW Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Pin Symbol GND FC4 FC5 FC6 FC7 FC8 FC9 FC10 FCll FC12 FC13 FC14 FC15 FDO FD1 FD2 FD3 FD4 FD5 (I/O) PW I Vdd PW PW I GND FD6 FD7 FD8 FD9 FD10 FD11 FD12 FD13 FD14 FD15 FEO FE1 FE2 FE3 FE4 FE5 FE6 FE7 Vdd K-4 " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " PW Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Pin Symbol GND FE8 FE9 FElO FEll FE12 FE13 FE14 FE15 (I/O) PW I Vdd PW PW GND OAO OA1 OA2 OA3 OA4 OA5 OA6 OA7 Vdd GND OA8 OA9 OA10 OAll OA12 OA13 OA14 OA15 Vdd GND OBO OBI OB2 OB3 OB4 OB5 OB6 OB7 Vdd " " " " " u u 0 u u u u u u u PW PW 0 u u u u u u u PW PW 0 u u u u u u u PW 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 Pin Symbol GND OB8 OB9 OB10 OB11 OB12 OB13 OB14 OB15 RZDF DZDF GND Vdd SFEN ADAO ADAl ADBO ADB1 GND ICLK Vdd TEST* RST* IFMD CS* WR* RD* GND Vdd ADO ADl AD2 AD3 AD4 GND DBO DB1 DB2 (I/O) PW 0 159 DB3 u 160 Vdd PW u u u u u u u u u PW PW I u u u u PW I PW I u u Note 1: Note 2: Note 3: The TEST* pin is Schmitt input, with pull-up resistance. The RST* pin is Schmitt input, with pull-up resistance. The IFMD pin is Schmitt input. u u u PW PW I/O u u u u PW I/O u u K-5 2.3 External Dimensions 32.0±0.4 28.0±0.1 0.15±0.05 120 81 -.-----+--+-0 I I I 121 I I I ------+----I I I I I I 41 INDEX 3.35±0.1 23.35±0.15 304+02 .- . (30.2) ( j 7 f- f-- V. \ If) 0.8±0.2 I- \ -+ ci +1 If) ci K-6 0.53MAX Units: mm Section 3. Operating Description 3.1 Overview of Operation The IP90C32 LSI calculator chip is designed to perform a variety of calculations on floating-point data. It does this using internal bus switching and on-chip functions that include three multipliers, and inverse value, square root, and inverse square root calculators. The IP90C32 also includes an adder to sum computation results, and external connections for registers and shift registers for cumulative addition. A shifter is placed at the readout for results of cumulative addition. 3.2 Input Format The IP90C32 accepts input in the floating-point format described earlier, with a bias value of 1 or 32. Note that data input to the FD or FE port is in fixed-point notation. 3.3 Input Data Input data passes through format conversion, in which the exponent is expanded to 8 bits to enhance the dynamic range for multiplication and division. This conversion enables the IP90C32 to perform calculations with a dynamic range from 2- 126 to 2126. 3.4 Pipeline Synchronization The IP90C32 can be set up to perform a wide variety of calculations using pipeline processing. Therefore, the resulting data must be synchronized. To do this, two clock count programmable delay steps are provided for input data at ports Fe, FD, and FE, and at the input side of fixedpoint circuit B. 3.5 Constant Register The IP90C32 has a 1 data-unit (16 bits) constant register. Data in this register is written in floating-point format. The bias is selected by parameter setting. 3.6 Main Calculator The IP90C32's main calculator includes multiplier B, an inverse value calculator, a square-root calculator, and an inverse square-root calculator. 3.7 Main Calculator Input/Output Optional Circuits In addition to multiplier A and multiplier C, optional circuits are provided at both the input and output sides of the main calculator. These circuits can be switched and combined as needed to perform a wide variety of calculations. K-7 3.8 Fixed-Point Circuits Calculation results are output through the fixed-point circuits, with the decimal point's position controlled by a parameter setting. Results can be output in floating-point format; however, the output is limited to 16-bit width, so that the result must be within the limits of 16-bit fixed-point format. The output format selection parameters allow a choice of two's-complement or positive binary format. If an overflow condition in fixed-point format occurs at this point, the output value is clipped. Clipping is applied to the mantissa portion in floating-point format, which is then converted to two's-complement format, so that the smallest negative value will be one greater than the least value expressible in two's-complement format. 3.9 Addition Circuits Calculation results can be output directly. In addition, the IP90C32's design also allows results to be added to data input from ports FE or FF. (See the calculator connections shown in the block diagram in Section 1.3.) In this case, the data input at ports FE or FF must have the same fixedpoint format as the data output from the fixed-point circuits. 3.10 Shift and Rounding Circuits The calculation results described above are sent to the shift and rounding circuits. The maximum right-shift is 4 bits. Data in two's-complement format is shifted arithmetically, and data in positive binary format is shifted logically. The shift and rounding functions round results to multiples of 2, 4, 8, or 16 places. 3.11 Output Clipping Overflow output from adding or rounding operations can be clipped. Clipping is applied when the IP90C32 detects an overflow before executing a shift in the shift circuit. For example, if an addition creates the result FFFFh in positive binary format, a 4-bit shift would produce the result OFFFh. This value would normally be rounded to the next highest digit (IOOOh), but enabling the clipping function keeps the result at OFFFh. This is because when a 4-bit reverse shift is applied to 1000h, the result is outside the original 16-bit range. Alternatively, if the 4-bit shift is applied to the sum 8000 + 8000, an overflow occurs in the sum before shifting, so the output is written as OFFFh. In two's-complement mode, the highest bit is the code bit, so that positive or negative overflow conditions are detected at the 15th bit. If a 4-bit shift is applied to the sum 7FFFh + 0001h, the result with the clipping function enabled is 07FFh. If the 4-bit shift is applied to the sum 7000h + OFFFh, rounding normally produces 0800h. However, enabling the clipping function keeps the result at 07FFh, because applying a 4-bit shift to 0800h before clipping would give 0800h and cause an overflow. K-8 3.12 Number of Steps in Pipeline Processing The following shows the number of steps in each circuit. Stage Floating-point input sampling Floating-point internal format conversion Multiplier A Multiplier B Multiplier C Inverse value calculator Square-root calculator Inverse square-root calculator Fixed-point circuit Addition, shift, and rounding Output FD, FE addition input sampling Steps 1 step 1 step 1 step 1 step 1 step 1 step 1 step 1 step 1 step 1 step 1 step 1 step ( ... connected to add, shift and rounding circuits) The addition control and shift enable signals simultaneously control the addition and shift of data input from ports FD and FE. 3.13 Zero Division Flag The inverse value calculator and inverse square-root calculators are equipped with zero division flags. The flag signal output is timed to the same clock count as is the placement of these calculator's results in their respective registers. When a division by zero occurs, the result is zero. 3.14 Power-Saving Mode The IP90C32 is equipped with a power-saving mode, which reduces power consumption when no calculations are required. In this mode, data from each input port FA through FE is internally reset to zero, thus reducing power consumption. K-9 Section 4. 4.1 Programmable Resources IFMD Pin The IFMD pin signal is set to 0 for normal CPU interface functions. When this signal is 1, the IP90C32 automatically generates address AD(4:0) for sampling data input at DB(3:0). Parameters can be set without depending on the CPU by decoding the address through PLD or another external resource, generating the necessary parameters for that address and returning them to DB(3:0). This can only be done once per reset. Each parameter is valid for two clock cycles after it is written. 4.2 Signal Names Used in Descriptions The following table lists the signals used in parameter descriptions. See also the block diagram in Section 1.3. Signal Description XR Constant register output XAB Multiplier A output XC Input from FC through a delay circuit XD Input from FD through a delay circuit XE Input from FE through a delay circuit XF Return data from calculator output YA Multiplier B output YB Square-root calculator output YC Inverse square-root calculator output YD Reciprocal calculator output ZA, ZB Multiplier C input ZC Fixed-point conversion circuit B input QA Fixed-point conversion circuit A output QB Fixed-point conversion circuit B output QC Addition circuit A output QD Addition circuit B output QE Shift & round circuit A output QF Shift & round circuit B output K-lO 4.3 Parameter Descriptions • DL YC(I:0): Address 0 bit 1 bit 0 Delay 0 0 1 x None 0 1 • • • • FC input delay step selection parameter bit 1:0 DL YD(I:0) Address 0 FD input delay step selection parameter bit 3:2 bit 3 bit 2 0 0 1 0 1 x DL YE(I:0) Address 1 bit 0 0 0 1 0 1 x None 1 clock cycle 2 clock cycles Delay None 1 clock cycle 2 clock cycles Fixed-point conversion circuit B input delay selection bit 3:2 bit 3 bit 2 0 0 1 0 1 x SMPYBl(2:0) Address 2 Delay FE input delay step selection parameter bit 1:0 bit 1 DL YF(I:0) Address 1 1 clock cycle 2 clock cycles Delay None 1 clock cycle 2 clock cycles Multiplier B input selection 1 bit 2:0 bit 2 bit 1 bit 0 Signal selected 0 0 0 0 0 1 1 0 XR XAB 0 0 1 0 1 x 0 1 1 1 1 0 1 XC XD XE XF Prohibited K-ll • SMPYB2(2:0) Address 3 bit 2 bit 1 bit 0 Signal selected 0 0 0 0 0 1 1 0 0 1 0 1 0 1 0 XR XAB XC XD XE XF Prohibited 0 1 1 1 • SRT(2:0) Address 4 1 x Square-root calculator input selection bit 2:0 bit 2 bit 1 bit 0 Signal selected 0 0 0 1 1 0 0 1 0 1 0 1 0 1 XR XAB XC XD XE XF Prohibited 0 0 0 1 1 1 • Multiplier B input selection 2 bit 2:0 SIRT(2:0) Address 5 x Inverse square-root calculator input selection bit 2:0 bit 2 bit 1 bit 0 Signal selected 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 XR XAB XC XD XE XF Prohibited x K-12 • SINV(2:0) Address 6 bit 2 bit 1 bit 0 Signal selected 0 0 0 0 1 1 0 0 1 0 1 XR XAB 0 1 0 1 x XC XD XE XF Prohibited 0 0 1 1 1 • • • Inverse calculator input selection bit 2:0 SMPYC1(1:0) Address 7 Multiplier C input selection 1 bit 1:0 bit 1 bit 0 Signal selected 0 0 1 1 0 1 YA YB YC SMPYC2(1:0) Address 7 0 1 YD Multiplier C input selection 2 bit 3:2 bit 3 bit 2 Signal selected 0 0 1 1 0 1 0 1 YA YB YC YD SFPB(1:0) Address 8 Fixed decimal conversion circuit B input selection bit 1:0 bit 1 bit 0 Signal selected 0 0 1 1 0 YA YB YC YD 1 0 1 K-13 • SFDB(1:0) Address 8 Return data selection bit 3:2 bit 3 bit 2 Signal selected 0 0 1 1 0 1 0 1 YA YB YC YD • FXPAH Address 9 Fixed-point conversion circuit A decimal-point position (7:4) bit 3:0 • FXPAL Address A Fixed-point conversion circuit A decimal-point position (3:0) bit 3:0 The location of the l's position in positive binary mode is designated by setting the highest bit of the output from the fixed-point conversion circuit to 0, and the second highest bit to 1, in two'scomplement format. In two's-complement mode, the highest bit of the output is a code bit, so that the second highest bit is set to 0 and the third highest bit to 1. Alternatively, by designating the number -128, the output can be left in floating-point format. In this case the bias value is the same as the FBS floating-point bias setting. • FXPBH Address B Fixed-point conversion circuit B decimal-point position (7:4) bit 3:0 • FXPBL Address C Fixed-point conversion circuit B decimal-point position (3:0) bit 3:0 The location of the 1's position in positive binary mode is designated by setting the highest bit of the output from the fixed decimal conversion circuit to 0, and the second highest bit to 1, in two'scomplement format. In two's-complement mode, the highest bit of the output is a code bit, so that the second highest bit is set to 0 and the third highest bit to 1. Alternatively, by designating the number -128, the output can be left in floating-point format. In this case the bias value is the same as the FBS floating-point bias setting. Note: • The mantissa is expanded internally for use in calculations. However, the mantissa of floating-point output is limited to 6 bits. Be aware that no overflow control is applied. SFTA(2:0) Address D Addition circuit A shift bit 2:0 This parameter designates the degree of shift applied by shift circuit A. SFTA must be in the range 0 to 4. K-14 • SFTB(2:0) Address E Addition circuit B shift bit 2:0 This parameter designates the degree of shift applied by shift circuit B. SFTB must be in the range 0 to 4. • FXMDA Fixed-point conversion circuit A operating mode Address F bit 0 FXMDA = 0 - > two's-complement output FXMDA = 1 - > positive binary output • FXMDB Fixed-point conversion circuit B operating mode Address F bit 1 - > two's-complement output FXMDB = 0 FXMDB = 1 - > positive binary output • FBS Address F FBS FBS =0 =1 Floating-point bias bit 2 -> bias value: 32 - > bias value: 1 This parameter affects only the floating-point format for input and output from the IP90C32 chip, and has no effect on fixed-point notation or on internal calculations. • Round/truncate option A COA Address 10 bit 0 Valid only when shift is enabled. COA : 0 - > round COA: 1 - > truncate • Round/truncate option B COB Address 10 bit 1 Valid only when shift is enabled. COB = 0 - > round - > truncate COB = 1 • OACRPEN Address 10 OACRPEN OACRPEN Output clip A enable bit 2 : 0 - > disable : 1 - > enable K-15 • OBCRPEN Output clip B enable Address 10 bit 3 OBCRPEN = 0 - > disable OBCRPEN = 1 - > enable • Constant register 15:12 CNSTHH bit 3:0 Address 11 This parameter writes to bit 15:12 of the constant register. • Constant register 11:8 CNSTHL Address 12 bit 3:0 This parameter writes to bit 11:8 of the constant register. • Constant register 7:4 CNSTLH Address 13 bit 3:0 This parameter writes to bit 7:4 of the constant register. • Constant register 3:0 CNSTLL Address 14 bit 3:0 This parameter writes to bit 3:0 of the constant register. • PSV Address 15 PSVn = 0 PSVn = 1 • Bit position n corresponds to the following ports. n = 0: FA, FB input n = 1: FC input n = 2: FD input n = 3: FE input • VBW Address 16 VBW VBW • =0 =1 Power saving mode select 3:0 bit 3:0 - > normal operation - > power saving mode: set input to 0 Variable bus width enable bit 0 - > disable - > enable Reserved Address 16 bit 3:1 This parameter should always be set to O. K-16 • • • ADA(1:0) Pin direct Addition circuit A control ADAl ADAO 0 0 1 1 0 ADB(1:0) Pin direct 1 0 1 Addition operation. Output fixed-point conversion circuit output with no changes. Output FD input with no changes. Output 0 (zero). Addition circuit B control ADBI ADBO 0 0 0 1 0 Addition operation. Output fixed-point conversion circuit output with no changes. Output FE input with no changes. 1 1 Output 0 (zero). SFEN Pin direct Operation 1 Shift enable SFEN = 0 SFEN = 1 4.4 Operation -> -> shift disable shift enable Default Values After a reset, all parameter values are zero. K-l7 4.5 List of Parameters Address Bit(s) 00 00 01 01 02 03 04 05 06 07 07 08 08 09 OA OB OC OD OE OF OF OF 10 10 10 10 11 12 13 14 15 16 16 1:0 3:2 1:0 3:2 2:0 2:0 2:0 2:0 2:0 1:0 3:2 1:0 3:2 3:0 3:0 3:0 3:0 2:0 2:0 0 1 2 0 1 2 3 3:0 3:0 3:0 3:0 3:0 0 3:1 Symbol Description DLYC DLYD DLYE DLYF SMPYB1 SMPYB2 SRT SIRT SINV SMPYC1 SMPYC2 SFPB SFDB FXPAH FXPAL FXPBH FXPBL SFTA SFTB FXMDA FXMDB FBS COA COB OACRPEN OBCRPEN CNSTHH CNSTHL CNSTLH CNSTLL PSV VBW Reserved FC input delay step selection parameter FD input delay step selection parameter FE input delay step selection parameter Fixed-point conversion circuit B input delay selection Multiplier B input selection 1 Multiplier B input selection 2 Square-root calculator input selection Inverse square-root calculator input selection Inverse calculator input selection Multiplier C input selection 1 Multiplier C input selection 2 Fixed-point conversion circuit B input selection Return data selection Fixed-point conversion circuit A decimal-point position 7:4 Fixed-point conversion circuit A decimal-point position 3:0 Fixed-point conversion circuit B decimal-point position 7:4 Fixed-point conversion circuit B decimal-point position 3:0 Addition circuit A shift Addition circuit B shift Fixed-point conversion circuit A operating mode Fixed-point conversion circuit B operating mode Floating-point bias Round/truncate option A Round/truncate option B Output clip A enable Output clip B enable Constant register 15:12 Constant register 11:8 Constant register 7:4 Constant register 3:0 Power-saving mode select Variable bus width enable Set to 0 K-18 Section 5. Variable Bit-Width Mode The IP90C32 chip is equipped with a variable bit-width mode that allows variable use of output ports OA and OB and input ports FD and FE. For simplification, the following description uses the designations VOA and VOB for the output ports, and VFD and VFE for the input ports. 5.1 Pin Correspondence VOA and VFD are 20 bits wide, and VOB and VFE are 12 bits wide. In normal mode they correspond to pins as follows: = OA(15:0), VOA(19:16) = OB(15:12) = OB(11:0) = FD(15:0), VFD(19:16) = FE(15:12) • VOA(15:0) • • VOB(11:0) VFD(15:0) • VFE(11:0) = FE(11:0) Normal Operation FA(15:0) . FB(l5:0) FC(15:0) FD(l5:0) FE(15:0) OA(l5:0) A2 .. .. .. OB(l5:0) t IfF & Control Variable Bit-Width Mode FA(l5:0) .. FB(15:0) . FC(l5:0) VFD(l9:0) VOA (19:0) A2 .. VFE(11:0) t UF & Control K-19 ... VOB (11 :0) 5.2 Internal Hardware 5.2.1 Fixed-Point Conversion Circuits The fixed-point conversion circuits work the same way in normal and variable bit-width modes. Output is always in 16 bits, and clipping is always limited to 16-bit width. 5.2.2 Addition Circuits In normal mode, addition circuits A and B operate in 16 bits. In variable addition circuit VOA basically operates in 20 bits. Addition circuit VOB though its output is immediately clipped to 12 bits. All shift, round, and the addition circuits must correspond to the appropriate bit widths. The conversion circuits are aligned with respect to the lowest bit value. 5.2.3 bit-width mode, however, operates in 16 bits, clip circuits connected to addition and fixed-point Operation During Bit Width Changes In variable bit-width mode, the bit width of the input to the addition circuits may differ from the bit width actually assigned. The procedure used to compensate depends on whether the operation uses two's-complement or positive binary data, and is designated by the fixed decimal conversion circuit operating mode selection parameter. In power-saving mode, parameters PSV2 and PSV3 use the variable bit-width ports VFD and VFE. 5.2.4 Clipping Operations Clipping circuits are affected along with the addition circuits (see above), in that the overflow detection bit count is changed from 16 bits to 20 bits for addition circuit VA, and to 12 bits for addition circuit B. For example, assume a 20-bit bus width from fixed-point conversion circuit A to addition circuit A to output port VOA. A positive binary output from the addition circuit of FFFFFh becomes OFFFF after a 4-bit shift. Rounding-up adds one more digit: if clipping is disabled, the outcome is 10000h, but if clipping is enabled the result is OFFFFh (because when a 4-bit reverse shift is applied, the value 10000 exceeds the original 20-bit range). Also, if a 4-bit shift is applied to the value F8000+08000, the addition before the shift causes an overflow, so that the output becomes OFFFFh. In two's-complement mode, the upper bit is a code bit, so that positive/negative overflows are determined at the 19th bit. For example, if a 4-bit shift is applied to 7FFFFh+00001h, the result with clipping enabled is 07FFFh. Also, if a 4-bit shift is applied to 70000h+OFFFFh, rounding-up yields 08000h, but if clipping is enabled the result is 07FFFh (because the result before clipping is 08000h, which with a 4-bit left shift becomes 80000h, an overflow value). K-20 Overview of Output in Variable Bit-Width Mode 20-bit overflow detection VFD(19:0) Fixed decimal-point circuit output VOA (19:0) 16 bit t Clip enable Shift parameters and shift enable 12-bit overflow detection Fixed decimal-point circuit output VOB (11:0) VFE(lI:0) 12 bit *Note 2 t Clip enable *Note 1 Extract lower 12 bits Shift parameters and shift enable Note 1: Note 2: "Bus conversion" refers to matching input bit width to addition circuit input bit width. "Variable rounding" refers to rounding with respect to the size of the shift applied. For a shift of n bits (with n=l as the LSB), a value of 1 is added to the nth bit. K-21 Section 6. Electrical Characteristics 6.1 Absolute Maximum Ratings Item Unit V Vdd Input voltage Vi -0.3 to Vdd+0.3 V Input current Ii ±10 rnA Output current 10 10 rnA Operating temperature Topt o to 70 Storage temperature Tstg -10 to 80 °C DC Recommended Operating Conditions (GND = OV, Ta = 0° to 70°C) Item Symbol Conditions Power supply voltage Vdd High-level input voltage Vih TTL level Low-level input voltage ViI normal input High-level input voltage Vih SCHMITT Min Typ 4.75 5.0 2.0 Max Unit 5.25 V Vdd V 0 0.8 V 2.25 Vdd V Low-level input voltage Vil input (note 1) 0 0.8 V Input rise time Tri TTL level a 100 ns Input fall time Tfi normal input 0 100 ns Input rise time Tri SCHMITT 0 1000 ns Input fall time Tfi input (note 1) 0 1000 ns Max Unit Note 1: 6.3 Rating -0.3 to 6.5 Power supply voltage 6.2 Symbol The three Schmitt trigger input pins are RST*, TEST*, and IFMD. Input/Output Pin Capacity (Vdd Item = Vi = OV) Symbol Conditions Min Typ Input pins ein f=lMHz 10 pF Output pins Cout f= 1 MHz 10 pF I/O pins Cin f= 1 MHz 10 pF K-22 6.4 DC Characteristics (Vdd Item =5V±5%, GND =OV, Ta =0° to 70°C) Symbol Conditions Typ = Vdd or GND Static current consumption (note 1) II Vi Output short current (note 2) los Vdd = Max, Vo = Vdd (all output and I/O pins) Min Vdd = Max, Vo = 0 Max Unit 200 ~ rnA 15 50 130 -5 -25 -100 Low-level input leak current -10 ±1 10 ~ Vi = GND = GND -35 -115 -350 ~ Iih Vi = Vdd -10 ±1 10 ~ Low-level output voltage Vol Iol V Voh Ioh 4.5 Vdd V (notes 4 and 5) Voh = 4 rnA = -0.5 rnA Iol = -4 rnA 0.4 High-level output voltage 2.4 Vdd V SCHMITT hysteresis voltage Vsch ViI to Vih 0.4 Normal I/O pins IiI Pins with pull-up resistance (note 3) lipl High-level input leak current (all input and I/O pins) Note Note Note Note Note 1: 2: 3: 4: 5: Vi 0.2 0.8 Excluding static current consumption to pull-up and pull-down resistors. Output short current for one second or less, at one LSI pin. The two pins pull-up resistors are RST* and TEST'. Output is CMOS level (TTL level). Maximum external load capacity: less than 25 MHz: 50 pF 25 MHz or greater: 30 pF K-23 V 6.5 AC Characteristics 1) CPU Interface Timing Write cycle: tac 1~ AD(4:0) ------.~ 1 ~ 1 ~ valid address I~--------------- tas I - tah---, ~ 1 1 1 1 CS* WR* 1 ~ DB(3:0) _________...J~ Note: tds ---I~-: valid data twrh is determined by the rising edge of CS* or WR*, whichever is faster. Writing occurs when CS* and WR* are both low. Read cycle: ~---------tac----------------~.I AD(4:0) _ _ _---J r-------------------------~~================ I CS* RD* 1 trdd 1 ~I I DB(3:0) 1 ~<<< 1 1 I-- tzd - t 1 1 High impedance valid data )! 1 1 ---l Note: r-- unknown C : "H"or"L" trdd is determined by the falling edge of CS* or RD*, whichever is slower. tzd is determined by the rising edge of CS* or RD*, whichever is faster. Reading occurs when CS* and RD* are both at low level. K-24 2) Clock Reset Timing ICLK 1 1 1 1 1 t+--i tckl I I-tckC--j 1 '--l I tckh I I 1 1 I I \J"""~------trsw -------I-~V RST* ~I--------------------------~I The minimum reset signal input period is four clock cycles. 3) Control! Data Signal Timing Input datal control signal related. l ICLK - - - - - , \ 1 t---tdis -I'" 1 Input data! control signals _ _ _-' 1 valid data \'--_------'1 tdih-' 1 ~ ! 1 1~ tdod ADA, ABD, SFEN, FA, FB, FC, FD, FE 4) Timing when IFMD = 1 ICLK AD(3:0) ~-------~ I ~tpad 16 clock pulses : -: I'" ~ n !! X,-_n_+_1__ n-1 -----------~~ 1 I. tpps+4-tpph-' DB(7:0) --------,~ , i t ~'---- ' Sampled at the rising edge of the 16th clock pulse K-25 Timing Table Load capacity for all output pins is 30 pF. Unit: ns Item Symbol Write cycle time tac 60 AD(4:0) setup time tas 15 AD(4:0) hold time tah 3 CS* pulse width tcsw 20 WR* pulse width twrw 20 Data setup time tds 15 Data hold time twrh 3 RD* pulse width trdw 20 Data delay trdd 20 Data delay from address tadd 25 Data delay to HIZ tzd Clock cycle time tckc 33 Clock high time tckh 13 Clock low time tckl 13 Input/control signal setup time tdis 8 Input/ control signal hold time tdih 3 Output data delay tdod 3 = 1 address delay IFMD = 1 data setup time IFMD = 1 data hold time tpad IFMD Min Typ Max 15 20 30 tpps 30 tpph 10 Load Capacity for Output Pins OAf OB The IP90C32 has 32 output pins (including the OA and OB pins) that operate at high speed. The load capacities of these pins can lead to problems with ground balance and EM!. Therefore, use output pins OA and OB with loads of no more than 50 pF. Also, using large loads greatly increases power consumption and raises transistor junction temperatures. Calculating from the highest allowable transistor junction temperature, at operating frequencies of 25 MHz and higher, the load capacities of OA and OB should be no more than 30 pF. (The IP90C32's maximum allowable output load is 30 pF at 30-MHz operating frequency, 5.25-volt power supply, and ambient temperature of 70°C) Power consumption can be reduced by connecting circuits not needed for internal calculations to circuits whose signals do not vary (such as the constant register). If heat generation appears to affect peripheral circuits, reduce power consumption to the lowest possible leveL K-26 Section 7. Sample Applications The IP90C31 and IP90C32 are designed to perform arithmetic calculations, and can therefore be used in a wide variety of fields. This section introduces one possible application, calculating the center of an image, which involves normalized correlation calculations. 7.1 Center of Brightness The IP90C31, IP90C32, and IP90C51 can combine to calculate the center of brightness of an image using hardware functions alone. Using the IP90C31's 40-bit accumulator, and the IP90C32's floatingpoint calculation functions, this chip set has the wide range of calculation capacity needed to perform this calculation. Accumulator Image data B Synchronization signal E;::::::"::':~::::::-::::-~I ,, ~~x·f(x,y) Horizontal center of brightness IP90C32 Vertical center of brightness ~~f(x,y) " ~~y.f(x,y) - '-'- - - - ,, ~~f(x,y) Vertical addresses About Centers of Brightness A two-dimensional image has a quantitative measurement of brightness at any point (x, y), which can be represented by f(x, y). From this can be calculated a primary moment and center of gravity, referred to respectively as the primary moment of brightness and the center of gravity of brightness. The coordinates of the center of gravity of brightness can be expressed as the sum of brightness values (the O-order moment of brightness) divided by the horizontal primary moment of brightness and the vertical primary moment of brightness, thus: Sum of Brightness Values The sum of brightness values, which can also be thought of as the O-order moment of brightness, is expressed by the following formula: Moo = moo = LLf(x,y) y where f(x, y) is the brightness (grayscale value) of the pixel at coordinates (x, y). K-27 Primary Moment of Brightness The primary moment of brightness is defined by the following equations. The IP90C5l chip provides horizontal and vertical coordinates and grayscale values. The IP90C31 LSI chip calculates the sum of the products of these coordinates and grayscale values, and calculates the primary moment of brightness around the origin. x Using these measurements and the sum of brightness values, the IP90C32 determines the center of gravity of brightness by division. 7.2 Center of a Designated Labeling Area The IP90C31, IP90C32, and IP90CI0 (or IP90Cll) LSI chips in combination can determine the center of a designated labeling area by hardware functions alone. The IP90ClO labels incoming binary image data, which then passes to the IP90C5l, which uses ternary functions to extract an area designated by label numbers. This data then goes to the centerof-gravity calculation circuits of the IP90C31 and IP90C32. The center-of-gravity circuits in this example function in the same way as in the center of brightness example above, except that they handle binary data. Image data Horizontal center of gravity Synchronization signal 1-"'-'=""--+1 IP90C32 Vertica! center of gravity Vertical addresses K-28 7.3 Moving Normalized Correlation Calculation The formula below can be used to provide real-time calculation of moving normalized correlation, without subtracting average values. This type of calculation is used in a wide variety of fields, including measuring signal delays with distance measurement equipment, finding pitch in harmonic analysis, detecting synchronization in communications, and reducing noise. Where w is the width of the area (window) for normalized processing x·J • Yj • • • of movement • • • • • • • • • Direction ~ 1 14 • • • • •1 • ~ • • • • • Direction of movement -I W j+w~l ~ (x?) 4w-step delay! IP90C3l I=J j+w~l ~ IP90C31 (xj.y) I=J j+w-l ~ Cj IP90C32 ~ r--+ L (Xi"Y) I=J j+w-l rw-step delayl IP90C31 j+w-l L (Yi2) i=j K-29 j+w-l LX? I=J L.Y? I=J 7.4 Floating-Point Conversion Circuit This section introduces an overview of circuits used to externally generate floating point format data for input to the IP90C32 chip. Coded bit Exponent extraction circuit Adder Coded bit MSBof A Bias 6 C 6 E E Exponent OVF E 40 A Two's complement --j'-.L..+--J A 40 40 B Inverter OVF 10 C D Shifter +1 +1 Overflow from rounding 9 F Mantissa Rounder Two's complement -+ absolute value Operating Description Step 1: Extract all coded bits. The MSB of data in two's-complement format is the coded bit. Step 2: Convert data from two's-complement format to absolute value. If the coded bit is zero, use the data as it is. If the coded bit is 1, convert the data to absolute value using this process: 1. Invert all data bits: B = A (Example: A = 010101, B = 101010). 2. Add 1 to B: C = B + 1. Step 3: Extract the exponent (E). The exponent is determined by the position of the highest 1 in the absolute value (C). (Examples) Absolute value: Absolute value: Absolute value: 0100010001 0010010001 0000000001 Exponent =8 Exponent = 7 Exponent =0 K-30 Step 4: Extract the mantissa. The mantissa is the nine bits following the position of the highest 1 in the absolute value (C). (Examples) Absolute value: Shifter output D: Mantissa: 001000010100100000111 0000101001 000010101 (rounded) Absolute value: Shifter output D: Mantissa: 000000000000000010111 0111000000 011100000 (rounded) If the shifter output D consists entirely of Is, the carry value generated by the round function is transferred to the MSB, 1 is added to the exponent, and the mantissa is set to O. Step 5: Add the bias value. The bias value is added to the exponent. The IP90C32 can switch between bias values of 1 and 32, using a register setting. Note: Zero expressions are a special case. A circuit is added to handle input that consists of all zeros, and produces an output of all zeros. K-31 SMIASSP Image Processing LSI Series IP90C51 Image Data Bus Controller (IMBC) Sumitomo Metal Industries, Ltd. Technical Manual Ver. E 1.2 • Sumitomo Metal Industries, Ltd. Table of Contents Section 1: 1.1 Section 2: 2.1 2.2 Section 3: 3.1 3.2 3.3 3.4 Section 4: 4.1 Section 5: 5.1 5.2 5.3 5.4 Section 6: 6.1 6.2 6.3 6.4 Section 7: 7.1 7.2 7.3 7.4 7.5 Section 8: 8.1 8.2. 8.3 Overview Functional Overview and Features .......................................................................... . 1 Image Data Configuration Sample Input Image ................................................................................................ . Image Data Configuration ....................................................................................... . 2 3 Pin Descriptions Pin Placement. ......................................................................................................... . Pins and Their Functions .......................................................................................... . Schematic Pin Diagram ........................................................................................... . Package Dimensions ................................................................................................ . 4 5 6 7 Block Diagram Block Diagram ........................................................................................................ . 8 Registers Register List ............................................................................................................ . Area of Interest Setting Registers ........................................................................... .. Output Data Setting Registers ................................................................................ .. Operating Mode Select Registers ............................................................................. . 9 10 12 13 Operating Description and Control Methods Programmable Area Definition ................................................................................ . Comparator Output ................................................................................................. . Frame Memory Addresses ........................................................................................ . Control Method ....................................................................................................... . 15 16 17 19 Electrical Characteristics Absolute Maximum Ratings ...................................................................................... Recommended Operating Conditions......................................................................... DC Characteristics................................................................................................... Input/Output Pin Capacitance.................................................................................. AC Timing................................................................................................................ 20 20 21 21 22 Sample Applications Image Data Bus Interface......................................................................................... Frame Memory Interface............................................................................... ............ IP90C-Series Interfaces............................................................................................. L-i 29 34 37 Section 1: Overview 1.1 Functional Overview and Features The IP90C51 is a programmable image data bus controller (IMBC) that controls high-speed transmission and processing of image data. It is compatible with all image transfer standards for standard television and high-definition television (HDTV). The IP90C51 incorporates a digital image data bus interface and basic image data processing functions into a single chip, and is ideal for image data blanking with NTSC-standard image signals. Features • • • • • • • • Uses standard horizontal and vertical synchronization pulses. Supports 8-bit, 256-level grayscale data. Supports 24-bit full-color data when used with three IP90C51 chips. Supports high-speed, high-density parallel processing for HDTV. Generates output frame memory addresses for high-speed memory access. Supports both interlaced and non-interlaced scanning. Interfaces directly with all image processor ASSPs made by Sumitomo Metal Industries, Ltd. Can process image areas as large as 4095 x 4095 pixels, enough to handle large images, or highresolution images from scanners or HDTV systems. Functions • Digital image data bus interface controller Programmable image field clipping (area of interest [AOI] function) Frame memory address generation • Image data processing Bi-level/window compared bi-level output Ternary conversion function Data enable control for each pixel Background processing L-1 Section 2: Image Data Configuration 2.1 Sample Input Image NTSC Image Data 1r=~----------------------, 263 2 / 264 3 r r Odd-numbered field scan line Even-numbered field scan line / , - -''5 - - - -- ------------------- . .. ---_ ... -------- -'... ---- _....... ;: ----261 525 262 --------- ,~ 1 fH - 63.5 liS Non-interlaced scanning " NTSC Scanning Line (interlaced) HEN*---------------------------, ~ 760 to 950 pixels for NTSC Input signal region Approx. 126 pixels 'I t Approx. 116 lines vertical blanking Approx. 126 pixels horizontal • horizontal blanking r-E-ff-e-cn-·v-e-im--ag-e-ar-e-a-'-------f-----------;.--' blanking (512 x 512 pixels for NTSC) t - - - - - t - - - - Hoffset - - - - - . Hoffset is counted in clock cycles, Voffset is counted in HS' signal cycles. Approx. 116 lines vertical blanking IMBC specifications: Hoffset 4095 Voffset 4095 Hwidth 4095 Vwidth 4095 Image data enters as an NTSC signal, undergoes AID conversion, and becomes the input signal area transferred over the image bus. In the above illustration, the effective image area is the 512 x 512pixel rectangular area shown in the example above. Image processing applications commonly extract and process only a portion of an image, such as the area of interest (AOI) shown above. The IP90C51 allows the user to define the AO! within the effective image area of the incoming image signal. L-2 2.2 Image Data Configuration 1) Pixel Data Configuration /I D(O,I) D(O,O) D(O,2) II D(O,3) D(1,O) D(1,I) D(I,2) D(1,3) D(2,O) D(2,1) D(2,2) D(2,3) D(O,n) (( » D(1,n) /I )) -~ -~ D(2,n) (( '=' T T T T T~~ D(m,O) D(m,l) -"" D(m,2) » D(m,3) 2) Image Data Format for Transmission: Single Line ----~ -::~ vs· ~___________________________________________________________________________________ _ HS'~m------------------;~~~~;~~t~--------------:;'~ Note 1: Note 2: The VS* and HS* signal pulses need not enter the IP90C51 simultaneously. HS* pulses preceding a VS* pulse are ignored, while HS* signals that enter simultaneously with or following the VS* pulse are recognized. The VS* and HS* signals do not need to be input as pulses, because they are differentiated internally by clock synchronized circuits. VS* or HS* input is assumed whenever a low-level VS* or HS* is detected at the rising edge of the clock signal. VS* or HS* must go high again before the next VS* or HS* assertion (low level). 3) Effective Area Along the Time Axis --~ ----.....Nextframe vs*U===;: First frame u u First line of active region I Active region I Image data Vertical retrace time ~ j Active region I f Horizontal retrace HEN* ---L~ VEN* ACT' L-3 f Horizontal retrace Vertical retrace time Section 3: Pin Descriptions 3.1 Pin Placement FAll FA 10 FA9 FA8 FA7 FA6 FA5 GND Vdd FA4 FA3 FA2 FAI FAO HFAS' GND DBI DB2 DB3 DB4 DB5 DB6 DB7 GND IP90C51© SUMITOMO METALS JAPAN XXXXXXXXX Vdd CE* WR* AD4 AD3 AD2 0 AD! ADO 64-Pin QFP Package (molded area: 14 mm2 , pin pitch: 0.8 mm) Pin Assignments Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note: Name FAOE' FLDi VS' HS' IDEN' CLK IDO IDl GND Vdd ID2 ID3 ID4 ID5 ID6 ID7 Pin 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name ADO ADl Am AD3 AD4 WR' CEo Vdd GND DB7 DB6 DB5 DB4 DB3 DB2 DB1 Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Name DBO RST* ACT* VEN' HEN' OD7 OD6 Vdd GND OD5 OD4 OD3 OD2 OD1 ODO GND Pin 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Name FAll FAlO FA9 FA8 FA7 FA6 FA5 GND Vdd FA4 FA3 FA2 FAI FAO HFAS* GND An asterisk (*) after the signal name indicates inverse logic (active low). L-4 3.2 Pins and Their Functions Pin group Symbol Image input bus CLK No. of Pins Type 1 IDO-ID7 HS* 8 1 1 I I 1 I I I FLDi 1 I Image output bus ODO-OD7 HEN* VEN* ACT* 8 1 1 1 0 0 0 0 Image address FAO-FAll 12 0 HFAS* FAOE* 1 1 0 I WR* CE* ADO-AD4 DBO-DB7 RST* 1 1 I 5 8 1 I Vdd GND 4 6 PW PW VS* IDEN* CPU bus Power supply GND Total number of pins Note 1: Note 2: Note 3: Note 4: I I I Description Clock input fmax = 36 MHz 8-bit image data input Line strobe input Frame strobe input Direct enable input: activates internal counter when low (Note 1). Input field discriminator signal input: high for odd-numbered fields, low for even-numbered fields. Set high for non-interlaced scanning. 8-bit image data output Horizontal data enable output Vertical data enable output Active area signal or output field discriminator signal output: function is specified in register SMOD. Frame memory address outputs. HCNT's value is output when HEN* is low. The upper-field address is output when HEN* is high (Note 2). Upper-field address strobe output Image address output enable input. Enabled when low. FAO-FAll are high impedance when FAOE* is high. Write enable input Chip enable input Register select address bus inputs Data bus inputs Reset input. Resets on pulse widths of 3 clock cycles or greater (Note 3). 5V Ground 64 If the effective area output signals (VEN*, HEN*) are in pulse form, the width of the signal can not be expanded. The signals are operative at low level. At high level, the counter stops and the data shift register remains on hold. This signal should remain at low level in normal use. FAO-FAll frame memory output pins have high-Z state with pull-up resistors. The RST* pin has Schmitt-trigger input with pull-up resistor. An asterisk (*) after the signal name indicates inverse logic (active low). L-5 3.3 Schematic Pin Diagram Image bus Control bus CLK IDO-ID7 ODO-OD7 HS* HEN* VS* VEN* IDEN* ACT* .. FLDi CPU bus Frame memory address bus WR* FAa-FAll CE* HFAS* ADO-AD4 .. FAOE* DBO-DB7 RST* Vdd GND When pins ODO-OD7 are used for comparator output with binary conversion, extended numerical values are used: • When the value is 0, ODO-OD7 output the value OOH. • When the value is 1, ODO to OD7 output the value FFh. With ternary value conversion, only the three least significant bits (ODO-OD2) are used: • When the value is 0, ODO-OD7 output the value 01h. • When the value is 1, ODO-OD7 output the value 02h. • When the value is 2, ODO-OD7 output the value 04h. L-6 3.4 Package Dimensions 17.6 ± 0.4 - - - - - - • 14.0±0.2 t_ ----~-I f 0.8 ± 0.2 f J 1.0 ± 0.10 units: mm 0.1 ± 0.1 L I 64-Pin Plastic QFP P ac k age L-7 Section 4: Block Diagram 4.1 Block Diagram DFIF r--IDO-ID7 DFIF r--- ..... ~ FLDi - II!... Ii'" ~ DFIF r--- OUTMUX -+> Output selection ~ circuit Image data outp ut bus K+- ~ [>CLK [>CLK [>CLK '--- '--- '--- ODO-OD7 ACT* r - - - LTE FIF ~ ~ ...." Comparator ~ D LTE ~ GTE ---- Clock Driver CLK IDEN* GTE To counters and flip-flops Area definition Horizontal starting position counter HS* Trig Horizontal width counter ACT CRY ~ Trig Q " Trig I--- " EN VS* HEN* EN CRY ~ Trig Vertical starting position counter VEN* ACT Vertical width counter CPU IIF - 8-bit bus Register file WR*, CEO Address bus ADO-AD4 Data bus DBO-DB7 RST* Note: II!... p VWIDn HWID VOFSn HOFS FAOFSn LTE GTE BG MMOD SMOD , , To each counter Flag data from mode register FAMUX . ... FAO-FAll Frame memory address multiplexer Offset address This block diagram only illustrates the functions of the IP90C51, and does not represent all the chip's circuits and functions. For descriptions of functions and timing, refer to the appropriate sections of this manual. L-8 Section 5: Registers 5.1 Register List All registers are write-only. Address Name OOh HWID Low 8 High 4 VWIDI Low 8 Odd-numbered field height High 4 Non-interlaced image height Low 8 Even-numbered field height High 4 Olh 02h 03h 04h VWIDO OSh 06h HOFS 07h 08h VOFSI 09h OAh VOFSO OBh OCh FAOFSI ODh OEh FAOFSO OFh Bits Description Screen data width Screen data horizontal offset Low 8 High 4 Low 8 Odd-numbered field data vertical offset High 4 Non-interlaced image vertical offset Low 8 Even-numbered field data vertical offset High 4 Low 8 Base address value for frame memory address for odd- High 4 numbered field data and interlaced image addresses Low 8 Base address value for frame memory address of High 4 even-numbered field data IOh GTE 8 Greater than or equal comparison data 1Ih LTE 8 Less than or equal comparison data 12h BG 8 Background data 13h - Reserved 14h - Reserved ISh - Reserved 16h SMOD 8 Slave mode register 17h MMOD 8 Master mode register Note: All registers are reset to OOh following a hardware or software reset. L-9 5.2 Area of Interest Setting Registers The following registers contain settings related to the area of interest (AOI). Parameter Register Width HWID Description LSB MSB Low High I I 0 I I I I I I I I I0 I0 I0 I I I I I Address Width OOh 12 bits 01h The setting must be one less than the AOI width VWID1 MSB Low High LSB I I I I I I I I I I0 I0 I0 I0 I I I I I 02h 12 bits 03h The odd-field AOI height for interlaced scanning, or the odd-field AOI height for non-interlaced scanning. This register is used when FLDi is high. VWIDO LSB MSB Low High I I I I I I I I I I0 I0 I0 I0 I I I I I 04h 12 bits OSh The even-field AOI height for interlaced scanning. Ignored in non-interlaced mode. This register is used when FLDi is low. Horizontal offset HOFS MSB Low High I I 0 LSB I I I I I I I I I0 I0 I0 I I I I I The AOI screen data horizontal offset. When a low HS* signal is detected at the rise of CLK, the data input at the rise of the next CLK is considered D(O), and successive values are then input as D(l), D(2), etc. When the HOFS register is set to m, the first m values D(O) through D(m-1) are ignored, and output begins with D(m). L-10 06h 07h 12 bits Parameter Register Vertical offset VOFSI Description LSB MSB Low High I I 0 I I I I I I I I I I I I I I I I 0 0 Address Width OSh 12 bits 09h 0 The odd-numbered field AOI data vertical offset for interlaced scanning, or the AOI field data vertical offset for non-interlaced scanning. The vertical offset is defined as the number of high-to-Iow transitions of HS* that enter after a low VS* is input. Thus, when the VOFS register is set to the m, the first m-l lines of data counted in the HS* low-level pulse input circuit after the low VS* pulse are ignored, and the mth line of data is counted. If the falling edges of VS* and HS* occur simultaneously at the rising edge of eLK, the HS* pulse is counted normally. VOFSO MSB Low High I I 0 LSB I I I I I I I I I I I I I I I I 0 0 0 The even-numbered AOI field data vertical offset for interlaced scanning. This register is used when FLDi is low. L-11 OAh OBh 12 bits 5.3 Output Data Setting Registers Parameter Register Base address setting FAOFS1 Description LSB MSB Low High I I I I I I I I I Ia Ia Ia Ia I I I I I Address Width OCh 12 bits ODh The base address for the high-byte frame memory address for odd-numbered field data in interlaced mode, or the base address for the high-byte frame memory address in non-interlace mode. This register is used when FLDi is high. FAOFSO MSB Low High LSB I I I I I I I I I Ia Ia Ia Ia I I I I I OEh 12 bits OFh The base address for high-byte frame memory data for even numbered field data in interlaced mode. Ignored in non-interlace mode. This register is used when FLDi is low. Comparator GTE Register MSB LSB 10h 8 bits llh 8 bits 12h 8 bits I I I I I I I I I The minimum comparator data value for comparison (greater than or equal). LTE Register MSB LSB I I I I I I I I I The maximum comparator data value (less than or equal). Background BG Register LSB MSB I I I I I I I I I Data value for all areas (background) outside the AOI defined by HOFS, VOFSn, HWID, and VWIDn. L-12 5.4 Operating Mode Select Registers Set the IP90C51's operating modes with the main mode (MMOD) and secondary mode (SMOD) registers. 5.4.1 Main Mode Register (MMOD) Reset value: OOh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Address L-_t~p__~~p__~_v_s__L -____L-_c_3~~_c__~__e__~__~117h bO: Reset. Write 1 to this bit for reset. After reset, this bit automatically returns to 0 (so it is not necessary to write 0 to clear the reset condition). bl: Execute. Write 1 to this bit to execute processing, 0 to stop. bi = 1: Execute bO = 0: Stop Execution occurs when the IDEN* (input data enable signal) is enabled and this bit is set to 1. b2: Comparator enable. Comparator output b2 = 1: b2 = 2: 8-bit data output (input 8-bit data is output as 8-bit data in transparent mode) b3: Binary /ternary conversion switch. Ternary output (Olh, 02h, 04h) b3 = 1: b3 = 0: Binary output (OOh, FFh) b4: Frame memory address. Controls ON/OFF setting of frame memory address output pins FAO-FAIL b4 = 1: Frame address output b4 = 0: Frame address pin OFF (high-impedance output) Has the same function as the FAOE* pin, so the frame memory address signal is enabled when b4 = 1 and FOAE* = low (the frame memory is in high-impedance state at all other times). Note that frame memory address output pins are pulled up so that they are not floating when the next data values arrive. L-13 b5: VS resistor sync. Sets the VS sync mode, which determines whether changes written to register values become valid at the start of the next field. Only this bit (VS_bit) and the bO bit (reset bit) are not affected by the VS_bit changes. They become valid when new values are written. b5 = 1: VS synchronous mode (changes written to registers become valid at the start of the next field) b5 b6: = 0: VS asynchronous mode (changes written to registers become valid as soon as they are written) Pulse output enable. Switches pulse and level output of the HEN* and VEN* signals. b6 = 1: b6 = 0: Pulse output mode (outputs a pulse of one clock-cycle width at the start of the area of interest) Level output mode (remains active throughout the area of interest) Transparent. Sets data values other than area of interest (AOI). b7: b7 = 1: Transparent mode (input data is output unchanged) Background data fill-in mode (outputs value from the BG register) b7= 0: 5.4.2 Secondary Mode Register (SMOD Register) Reset value: DOh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 o 0 0 0 0 0 0 fo bO: Note 1: Note 2: Address 116h Field output bit. Determines whether the ACT* signal pin outputs the ACT* signal or the output field ID signal FLDO. The ACT* signal is low only when the VEN* and HEN' signals are both low. Output field ID signal bO = 1: Output ACT' signal bO = 0: Write 0 to bits b1-b7. The output field ID signal FLDO is output with a delay of three clock cycles relative to the input field ID signal FLDi. This is the same as the delay between input and output of the digital image data itself. This is an effective way to match the delay of the field ID signal to synchronize it with the delay of the data signal when handling images with short blanking periods in interlaced mode. L-14 Section 6: Operating Description and Control Methods 6.1 Programmable Area Definition The size and location of the area of interest (AOI) are determined by programmable offset and size settings in the VOFS, HOFS, VWID, and HWrD registers. Output signals can be synchronized by using the VEN", HEN", and ACT" signals. VEN" and HEN" signal output can be switched between level output or pulse output (with a width of one clock cycle) using bit 6 of the MODE register (plsen-bit). The example below uses the following values: VOFS = Voffset, HOFS = Hoffset, VWID = Vwidth, HWID = Hwidth-l. Pulse output (1 clock cycle): plsen-bit = 1 Interval level output: plsen-bit = 0 I VEN * H offset V offset HS r- j - - H width ----j V offset • ~~ 1 I HS i HS 1 i ~~~~~~~~~~~~ V width Gjj:t!ttjj:tIE[J I ~J!" HS I I H offset -r- ! • HS:- HS HS HS offset I HS HS H offset HS HS - - - - Note 1: Note 2: • ~ _ HS . HS • r- .f7 . . F.-:• ~ • • IF. . - ~t~ VS/HS ~ HS . H offset ~~- ~F. ~ . F~ ..1"'.¥t=!~~."jI.F. : HS i V offset • H S - - . C 7 • • F.~ HS j - - H width ------j HS j - - H width ----j +---i*- ; = :1-:" : i H offset ~ ~~ r- V width HS I V width ~7 . . r:"~ vsmsr.'-~~-'-r'-~~-'-r-r, HS • ~: HS--~~· V offset -.'~~=F~T=~=4=F=F~~ F.'"FT=H=4=F=FT=T=H=4=F=I r- HS I HS fVsiHS V HS ~ ACT" ~~ H Width----j =- +----ifs : V width I • HS Hs~=4=F=F4=HF4~=F~T=H HS rfVsiHS V offset HS HS ~~=4=F=F4=HF4~=F~4=H HS HEN" j - - H width ------j ~~ HS~·~~~~~~~~~~~~ HS~~~~~~~~~~~~ V width H offset _____ _ fVsiHS~ j - - H width ------j 1 HS· - I HS - ~~_1".;71-<';".1=I~"'F+=Wc~ Vwidlh HS ! HS - ~-k=:".f·~t=t'=I~""I.;J.~ - ~ =~:.I"'~~-~8==-d· ~~ HS HS - • The VS" signal input and the first HS" signal need not be synchronized. The ACT" signal is not related to the value of the plsen-bit. To set this signal to width 1, set the HWrD register to o. L-15 6.2 Comparator Output The IP90C51's two comparators can output two-value or three-value data for clipped regions of the image data input, or delay the output. The function of the comparators is set by bits b2 and b3 in register MMOD, as shown in the following table. MMOD b2 b3 Clipping region output mode 0 * Input data 1 0 Two-value output (OOh, FFh) 1 1 Three-value output (Olh, 02h, 04h) The following figures show examples of these modes. Two-Value Mode Using a Single Comparator This mode uses register GTE for comparison when register LTE contains FFh, and uses register LTE for comparison when register GTE contains OOh. ID .~, ~:: "~._-;:-: :- G-I I~n,~nc,:r ~ t _ _ ... OOb output value Two-Value Mode Using Window Comparators GTE register ID input value LTE register 0 255 FFh OUT output value OOb OOb Three-Value Mode For Individually Specified Regions GTE register ID input value LTE register 0 255 02b OUT output value 04h Olb bin 0000 00 I 0 bin 0000 000 I L-16 bin 0000 OJ 00 6.3 Frame Memory Addresses The IP90C51 outputs low and high addresses on a 12-bit multiplexed address bus using the address strobe signal HFAS*, as shown in the figure below. 1) Full Use of Maximum Memory Capacity: 24-Bit Addresses The IP90C51 can output frame memory addresses for image sizes up to 4095 x 4095 pixels, using a 24-bit address format. Though the chip generates addresses, it does not handle memory read/write timing signals (see illustration below). Frame memory IP90C51 p ....................."""'''''''..Lo"W 12 bits Address 24 bits FAD-FAll HFAS* f - - - - - I > C L K Data can pass through the IP90C51 in either direction, either as data output from frame memory to the image data bus, or as data written from the image data bus to frame memory. Two IP90C51 chips are required to handle both directions simultaneously. 2) Using Interlaced Images and Narrower Address Space Areas of interest defined with sizes less than 4095 pixels (12 bits) can be easily handled by reducing the value of the low address bit for the width and the value of the high address bit for the height. For example, an AOI of 640 x 4S0 pixels can be handled using a high address of 9 bits (FAO-FAS) and a low address of 10 bits (FAO-FA9). Frame memory IP90C51 W"'....."""...................L"OW 10 bits Address 19 bits FAD-FAll , - - " High 9 bits HFAS* f - - - - - I > C L K Address Generation for a 640 x 4S0-Pixel Area of Interest When interlaced images are written to or read from frame memory, data from odd numbered fields is merged line by line with data from even numbered fields. To access memory space, the field . signal should be inserted between the high address and low address, and handled as part of the address signaL L-17 Field signal IP90C51 Frame memory Low address FAG-FAll ri==~-=)"''''t1"1"................1 Address (high address ' - - - - - - I + field signal + low address) High address (maximum 12 bits) HFAS* f------..I)CLK Memory Mapping of Interlaced Images by Merging Odd/Even Fields Line By Line 3) Sample Frame Memory Address Output Format The illustration below shows the address strobe signal HFAS*, as well as the high and low address output signals. This example uses the following register settings: • VOFSO (vertical offset for even field data) and VOFSI (vertical offset for odd field data) are set to Voff. • VWIDO (vertical size for even fields) and VWIDI (vertical size for odd fields) are set to Vw. • HOFS (horizontal offset) is set to Hoff. • HWID (horizontal width of screen data) is set to W. FAOFSO (base address value for even field data) and FAOFSI (base address value for odd field data) are set to Base. Thus, the settings for even-field data are made in the VOFSl, VWIDl, and FAOFSI registers, and settings for odd-field data are made in the VOFSO, VWIDO, and FAOFSO registers. CLK HFAS* lJUU1.JL ____ J1JlJUUL ____ JlJlfL -U r-- HEN* High address Voff Voff+l Voff + (Vw· I) Low address X Base+O X ---*--X Base+l X . -..*.. -.. XBaSC+VW-IX ~ __ n' ~ ~--- ... ~ ---*. -.. ~---"'~ * After a low HS* is detected at the rise of the eLK, the chip counts the number of clock cycles designated in the HOFS register. For details of signal timing, see Section 7.5, "AC Timing." L-18 6.4 Control Method Start Write Olh into the main mode register (MMOD). Yes Synchronized to VS* MMOD - - 20h 2}----~No Set the desired values in HWID, VWIDO, VWIDI, HOFS, VOFSI, and VOFSO. Window register Set desired values in registers FAOFS I, FAOFSO, GTE, LTE, and BG. Write the logical sum of the desired mode setting. plus 02h. (This effectively writes the desired mode register value to the execute bit [bit 2].) Execute Internal Register Write Sequence Note: • • Change register settings as follows: To change the VS* synchronization mode (synchronous to asynchronous or asynchronous to synchronous), start at point M- P> .g ~ M- ......... eLK ~ >-8" S. n HS* '-;:; t:I III S" ro Input data IDO-ID7 Unknown value 5" '0 .... '~ t;""' N 01 ODO-OD7 ~ - - - - + - - - - - + - - - - . L . . . . .__.: . \:--thedHL oq Unknown >_j:__- thedLH --: m (Note 2) __: ________________________ ; __ j:__ thedLH HEN* >-3 S· ...: oq VEN* ...,0' m III FAO-FAll ------+:--X --: , HFA : (Note 3) : thsHL ' ____________'~~~~' \ , :-- tad2 X ." _ 000 X DOl X 002 I1nknown X'-__ _ ' ~~'t~hs=L=H~-------------------------------------------- ) Note I: Note 2: Note 3: Note 4: I :-- tvedLH (Note 2) :...-! tvedLH i___ ~mm-----------mm----------r- :--tvedHL --: ------+----'-----~\ :--:tadl HFAS* IP90C51 Image Data ~~ C~ntroller S· :--tod - - - - - - - + - - - - - + - - - - - - - - - ! > !\ ~D(O,O) Unknown value S· ~ro §. --: -B" S. & >-l Unknown U = Unknown value. Dotted lines show timing in pulse output mode. HFA = high address output. The YEN* signal is output three or four cycles after the HEN* signal. Unit: ns Symbol Min. IDO-ID7 setup time tts 2.1 IDO-ID7 hold time tih CDO-CD7 transition delay time Parameter Typ. Max. 2.6 - - ted 4.0 - 12.5 HEN* delay time thedHL thedLH 5.0 - 15.5 VEN* delay time tvedHL tvedLH 5.0 - 15.5 FAO-FAll high-byte data delay time tadl 4.5 - 16.0 FAO-FAll low-byte data delay time tad2 4.5 - 16.0 thsHL thaLH 4.5 - 13.0 HFAS* delay time L-26 5) CPU Interface Timing , ~i'" ~:tceh :~"'---tces CE* WR* ~~----~/~--~\~--- - *- twrw -----~~i....- - - - t w m ------I~~i ______\'---~!r----~\~_________'! ~: :... tcadh i,.....~-- tcads ------.: ADO-AD4 u_n_kn_o_w_n~X Valid i iX~_U_nkn_o_w_n_v_a_lu_e_-,X,--___A_D_(n_)_ _ __ AD(m) ~tdbs DBO-DB7 Note 1: Note 2: Note 3: Unknown Value Valid Unknown Value DB(m) DB(n) Writing to registers from the CPU does not have to be synchronized to CLK. The WR* signal pin acts as a write clock signal from the CPU, so that the written data is synchronized with the rising edge of CLK as shown. Register data become internally valid two clock cycles after the rising edge of WR*. Register values can be changed during operation by writing 01h to register MMOD: this causes a soft reset, which requires all register values to be re-entered. Note that performing a soft reset before writing to a register prevents any incorrect counter operation caused by previous counter status or register values. Unit: ns Parameter Symbol Min. CE* setup time (from WR* rise) tees 15 - - CE* hold time (from WR* rise) Typ. Max. teeh 0 - - WR* low-level pulse width (low period) tWlW 15 - - WR* high-level pulse interval twrm 50 - - ADO-AD4 setup time from WR* rise teads 15 - - ADO-AD4 hold time from WR* rise tcadh 0 - - DBO-DB7 setup time from WR* rise tdbs 15 - - DBO-DB7 hold time from WR* rise tdbh 0 - - L-27 I!II 6) Reset Timing eLK ,, , ------~1\~:~~----------------------hSW ----------------------~~~ RST* Note: , ~------------------------------------------------~, The minimum reset signal pulse width is three cycles. Unit: ns Parameter RST* low-level pulse width (low period) L-28 Symbol Min. Typ. Max. trsw 3 -- -- Section 8: Sample Applications 8.1 Image Data Bus Interface 1) Image Data Bus Common Input/Output Controller Image data bus Image processor (processor A) Camera IP90CIO labeling processor (processor B) IP90COI histogram processor and IP9OC05 projection processor (processor C) Frame or graphics memory Input/output devices Camera CPU bus L-29 Bus input devices 2) Image Data Transmission Using Multiple Processors 2-1) High-Speed, High-Density Parallel Image Processing IDO-ID7 HS* Area select VS* signal Clock 1024 x 1024-pixel high-density image divided into four processing areas I ~ IDEN* ::::::1 IDEN" Area 00 Area 00 CPUl IMBC I Area 01 ... ... IIMBC I ~ • IDEN" Area 10 IMBC • ~ IDEN" ~ Area 01 CPU2 Area 10 CPU3 Area 11 Area 11 CPU4 Ii!. IMBC L-30 2-2) High-Speed, High-Density, Dual Bidirectional Image Processing IDO-ID7 HS* VS* CLK Image address (Area select signal) 1024 X 1024-pixel high-density image divided into four processing areas Area 00 Area 01 Area 00 Area 01 CPUl CPU2 Area 10 Area 11 CPU3 CPU4 Area 10 Area 11 Note: Individual areas can be selected by software using the screen offsets, or by hardware connected to the data enable input. L-31 3) Data Transmission Control for Real-Time Image Processors Camera IP90COl Histogram processor Image data bus IP90C05 Projection processor Frame memory Two-value threshold decision logic Area decision data CPU Forward processing control IP90C20 Rank filter Change to two-value data 1 frame delay Two-value threshold and area indicator IP90ClO Labeling processor Frame memory 2 frame delays Frame memory address Characteristic sampling 3 frame delays CPU DSP L-32 Decision processing 4) Multiple Window Overlap High-Speed Processor and Display Tuner CRTC ~~",,"IMUXp-.mllI> Digital Video Output Frame memory Graphics processor Camera L-33 8.2. Frame Memory Interface 1) Frame Memory Input Controller IDO-ID7 IMBC HS* VS* Clock I---~ HS* VS* CLK Data MUX ODO-OD7 Frame Memory HighFAD-FAll . _• • Address Latch, Address CPU bus MUX Digital image data from video camera or other device Data Bus Address Bus CPU L-34 2) Frame Memory Address Output Upper Field Latch To lower field address IMBC 74ALS574 x 2 Image address FAO-FAII 6_."""1 ~_ _ DO-Dll To upper field address QO-Qll~_"'" HFAS* 1 - - - - - , FAOE* eLK Three-state control for address multiplexer Frame memory address control line L-35 3) Data Extraction for Designated Shapes IP90C51 VS*, HS*, eLK IDO-ID7 stOrage RAM -...,t> eLK IDO-ID7 low field address FAGFAll Latch Q D HFAS* 1 - -.....10-1> eLK ODO-OD7 L-36 Ia-_-+++high field address L..I...J-'-I-ly-J-'-I-'-I-"-I 8.3 IP90C·Series Interfaces The IMBC chip uses the standard interface for the Sumitomo image processing ASSP series. Programmable settings can be made for easy configuration of interfaces to any chip in the ASSP series. ID HS* VS* Histogram Processor CLK IP90COl f--- vs* VEN*f- t-- ~ vs* ...... HS* HEN* f- t- IMBC HS* CLK I- ~ CLK nnJUlsuuul.nJuu CLK IMBCVEN* ~,,; , IMBC HEN*: : , :I''''; :. , , , , , , , ;,.....;---'----'--...:.-",--,--,- L.J : HIST~~ ID , , , , , , , , , , , , ID ~ ~ Start measurement ~ I. IP9OCOI VS* and HS* signal input (IMBC VEN* and HEN* signals) should be input at intervals of one clock pulse. 2. The effective area is defined by the horizontal and vertical axis settings -. in effect on the IP90COI at the rise of VS* and HS', M_W_~_M ___ • ------Projection Processor IP90C05 f-r- vs* VEN*I-- t-- ~ VEN* f-- HS* HEN* f- t- IMBC HEN* CLK l- t- CLK 1-1- r+ CLK IMBCVEN*~~,-+~--T-+--r-+~--r-+-~r IMBC HEN' -Tl ~ PROJ-',r-,r-"--\r-'r--\r-~r~'r-~r~,r-~r-', ID ODi- T-ID ID ~ ---C~~~>-~C~~~>-C~~y->--t~~~~YTTCI~Y~-~~~-C~------ Bo ~~·~r~~r~)-yD-oy-~(~OY~4~~y·~~~~~~~I~y~r-----co ~~>-o-~~-~I~-o~~J~-C~~~~'-O~-4~-4~J+c,~~>-------DO ~~~~~~J-o-~o-~~;~~~~~~~~.~~o-j+-{~J~~~~~~r~------Eo T ~~~y~~~orx~y~~~~y~~~~+-~O-Oy~~~~y~T~-----FO ~~r~~-~o-~~~~~~~o-U~~~~~J-)O-~~~~~~~~)O-------GO ~~~r~~I~I~)~)-~(~cr-~.~y~~.~y:~~~r-{~}~~:r~------HO ~~y:}'4~~()~-OiI~r~~~~~~~~o-~o-Oy~~~~~~~~-----IO X ~-U-~~~~~J-~~H,~-+~~~J-~~~-~~~~~~J-~~~~J-------JO ~ ~I-')..~ L r--y- -+- y Ko ~~~) taMi 00 ~ lALU ~ ~ Po~ #1 y T Sample Setting for the Image Data Stream Switching Block M-3 toNi Sample Connection Settings I10Assign Input PORT: PB, PC, PF, PG, PL Output PORT: PA, PD, PE, PH, PI, PJ, PK 2.2 Image Datastream --. --. Ao,Io Gi Eo Oi Fi --. Do Li --. Ko Bi Ci --. Mo Gi --. --. 00 Pi --. Po No }--. 1 } --. I ALU 1--. Mi--. Ho ALU I --. Ni --. Jo Connection to Internal Ports and Functional Outline of the ALUs The ALUs are connected to the image data stream switching blocks as follows: • The IP90C55 contains ALU#O and ALU#l, and has basic functions equivalent to an 8- or 16-bit 74L5181 processor. • Ports Mo and No are connected to the input ports of ALU#O (8 bits) • Ports 00 and Po are connected to the input ports of ALU#l (8 bits). • Output from ALU#O and ALU#1 are connected to ports Mi and Ni, respectively, • ALU#O and ALU#1 can be connected together to function as a 16-bit ALU. This coupling can be used to perform cumulative additions. When using the ALUs together as a 16-bit unit (ALUEXT flag hd == 1), make sure that ALU#O's function register ALUMODO is set to the same value as the ALU#l function register ALUMODl. Also, make sure that ALUEXT flags are set with satl == satO and fixl == fixO. The ALUs' have these functions: • ALUs are equivalent to an 8- or 16-bit 74L5181 processor. • ALUs perform logic operations such as NOT, NOR, zero clear, NAND, exclusive OR, exclusive NOR, through, AND, and OR. • ALUs perform arithmetic operations such as two's-complement addition (subtraction), decrement, increment, and others. The ALUs also have the following extended functions of the 74L5181 processor: • Operation to shift bits right (I-clock shift) (0-8 or 0-16 bits, including the carry bit). This calculation can be performed in combination with 74L5181-equivalent ALU operations, and so allows bits to be shifted 16 bits to the right after an addition to obtain the carry signal in a single path. • • • MAX(A, B) calculation to choose the larger of two input values. MIN (A, B) calculation to choose the smaller of two input values. Limiter function to limit addition! subtraction results to the maximum or minimum value within the bit range. If an add operation overflows and generates a carry, this function outputs the maximum value within the range (FFh for an 8-bit operation, FFFFh for a 16-bit operation). If a subtract operation underflows and generates a borrow, this function outputs the minimum value within the range (OOh for an 8-bit operation, OOOOh for a 16-bit operation). M-4 Logic Operations 2.3 AND OR NOT EXOR Arithmetic operations +(add), - (subtract) operations with carry Iborrow Shift operation Shift 0-8 or 0-16 bits right Choose by comparison MAX (A, B), MIN (A, B) Specifying a Rectangular Image Area (AOI Function) Image processing systems often process an area extracted from an image rather than the entire image. This extracted area is called the effective area, or the area of interest (AOI), as shown in the figure below. The IP90C55 can be programmed to clip selected rectangular AOls from the input image. The upper-left coordinates of the AOI shown below are labeled HSTART and VSTART, and the lower-right coordinates are labeled HEND and VEND. AOI location within image space HEN* 1----_1 -< ~ * HSTART and HEND count image clock (eLK) pulses. VSTART and VEND count HS* signal pulses. As shown above, the HEN* and VEN* signals demarcate the AOI: HEN* sets the AOI's width, and VEN* sets its height. The IP90C55 sets the HSTART, HEND, VSTART, and VEND registers to output the HEN* and VEN* signals. Specifically, the IP90C55's AOI function block contains an H counter to specify the area in the horizontal direction and a V counter to specify the area in the vertical direction. The H counter is reset by an HS* pulse (derived from the HS* signal by differentiating it using ICLK) to start counting ICLK cycles. The V counter is reset by a VS* pulse (derived from the VS* signal by differentiating it using ICLK ) to start counting HS* pulses. The AOI* signals (HEN*, VEN*, and ACT*) are generated by comparing these counter values against the register values. (ACT* is the logical AND product of the HEN* and VEN* signals.) If the configuration of input image data is expressed by a two-dimensional array, as shown in Figure A, the data is transferred using the raster-scan transfer format shown by the timing chart in Figure B. For comparison, Figure C shows a field of image data with vertical and horizontal blanking periods included. M-5 D(O,I) D(O,O) D(!,O) D(!,l) D(2,O) :::~ D(I,3) D(2,2) D(2,3) ~" "e D(m,l) D(O,3) D(l,2) D(2,1) " D(m,O) D(O,2) D(m,2) II D(O,n) II ii D(l,n) II II D(2,n) {( ~":~ D(m,3) ); D(m,n) Figure A: Data Configuration With Pixels Mapped as a Two-dimensional Array ICLK Image data (Note 2) VSEN* (Note 1) '\ / 777777 7 (Note 3) (Note 4) VS* (Note 1) ~ / 777 7 (Note 4) HS* (Note 1) ~ L ZZZ I· 7 One line of data § § § § S §~ ·1 Figure B: Input Image Data Transfer Format Note 1: Note 2: Note 3: Note 4: Signals with names followed by an asterisk (*) are active low. VS* is a field start signal. VSEN* enables VS* input. HS* is a start signal input for each line. The VS* signal is enabled if the VSEN* signal is low at the leading edge of the ICLK signal one clock cycle before the clock signal at which the change of VS* to low is detected. VSEN* allows the IP90C55 to easily be synchronized with other imageprocessing LSIs or programmable controllers. Set VSEN* low when the IP90C55 does not need to be synchronized with other LSls (i.e., when in normal operation). The VS* signal need not always be input simultaneously with HS*. HS* pulses entered before VS* is input are ignored, though HS* pulses entered simultaneously with VS* are recognized. Because the VS* and HS* signals are sampled by the internal clock, they need not always be pulse inputs. VS* or HS* is recognized when it is first found to be low when ICLK rises: the system interprets this as a VS* or HS* input. Once detected low in this way, VS* or HS* must go high again before the next VS* or HS* is input. M-6 Vs* II lJ .... Field in first sheet HS* Image data L111 u u Vertical retrace interval Vertical retrace interval '--------1r----1))--- HEN* VEN* ACT* II II '----_ _----'I )) L~) Figure C: Area of Interest on Time Axis of Image Data The IP90C55 can output three kinds of AOI signals from its AOIn* pins: HEN*, VEN*, and ACT*. HEN* marks the AOI's width, VEN* marks its height, and ACT* is the logical AND product of HEN* and VEN*. M-7 2.4 Example of Outputting Signals to Specify Rectangular Image Areas The following figure shows the AOI pin output timings in various AOI output modes for the image sizes and AOI registers set values listed below. The HEN*, VEN*, and ACT* signals each can occur in four different waveforms: Level, Single Pulse, Double Pulse, and Corner Pulse. (Corner Pulse is used only when ACT* is selected.) The Level waveform level is asserted (active) during the AOI period. The Single-Pulse waveform outputs a pulse one clock-cycle wide at the beginning of the AOI period. The Double-Pulse waveform outputs a pulse one clock-cycle wide at the beginning and the end of the AOI period. Corner Pulse generates a pulse one clock-cycle wide at the beginning of the first line of ACT*, and at the end of the last line. Window size 14 x 10 VSTARTod - n = 0003h VENDod - n = 0008h Setting value: HSTART - n = 0003h HEND - n = 0009h Figure 1: Level. HEN* .. .. : , '1" • • J. HS . I' · -:- L~HS · · . J. j r,- • -;- • r;- . Figure 3: Level. ACT* .. .j. ·8· ~~F=j:::'=F1·=F=F=F.=lI=:i=:=lI=.=I=I='=1=' =:i:=:i: -l-Y--S-T-fA-R-VTSiHH-SS- YEND j =I: =1=' Hs~~~~~~_·~!_·~i_·~i_·_· '1' ___·__·_I_·d Figure 4: Single Pulse. HEN* HEND HEND "HSTART HSTART: 'III . I. HS~~~r-r4~_·~I_·+-·~j_·+-+-~I_.+-.~ . i' -;- • i. HS _ __________ . i' •• Hsr=F(·=F=F=F·~!=·=I·=·=li='i=i==I==I==I=t=1 VEND r,- • . -;- HS 1 • r,- • .-:- . , -1-~-~~~~~~: I, : : : I· : :: J ____ ~~~~=:=~.~I~.:I=.:=~.~I=.:=~'~I=.:l=.:~ I· I· ·n·!·!· ·n·', . • 1-:- ~~ ·1· .-:- HEND iI'"HSTART,-'1 ., I Fs~~t: J____ YEND Figure 2: Level, YEN* :.. , .. HSTART:HEND "I, .. • j. • . -1-~-~~~~~/:: 1 •. . . i' . . ! .j .. J _____H..s.~~=.~!=.!.:.:'=!~'~='1'=':J=.~~:~=:=.~I'~ HS 1-·~I~·-1i~·-+J-:-~.J'h=•• :j:::':'tJ ='j:::'·='F·*·=I~r.-·±i~ .~.q HS . 1 • i • 1-:- • J. YEjND • ,.... J • . I· . i l1li1 , ~. : :: J ____ !1~s:r~;~;'~::':b~'~;;'!1='::::=I=F~~::::=~=~=I;::::::':i~'~~'~i~.:-I :~~'r..~lr.:~~~:~~~:~~~~~~~:tl~:tlI~: '_!~I·~!b-:-·~·~i='**'=li='=1='~·"'~'±-'+!_'~ HSHSI-'~! .!. ___________ ~~~t-:-r::-1'-:-f=:=l~=:=f==F=F=l=. =.=l=t,-: t-::tt:~_: .!. . 1-:. i '!' ___________ ~s_ =1=1 I· .: .... HS~~_4_+_+_+~·-~I·4_4-+-+-~ HS~~~~~~·~!_·~I·~I_·~·~·~·.I~· M-8 HS~~r'~~f='~~~'~=I'~'~~=lj7'=l17'~'tl~'tl~' HS~__~'_~~'~'~'~I_'~I_'________ ' __ '~I~' Figure 5: Single Pulse, VEN' ,. ~END , HSTART' II Figure 6: Single Pulse. ACT' .. HEND , HSTART: .. .. .. : 'l'~;;l~~::""!"'I""""'I';""'I""""'i"""·1···j·I·1 VEND --1 '·1 ,L,!IS'H=!==1==I=r=l==l==1=R=i==1=8 HS~~~~~7f~~~~~~~ "I ~~T1~~;~ VEND HS Hst,I--I-i~~~~~~~~i-i-1 JjF.+":'+":'+":'+":'+":'+":'i"':"i"':"HHH."'. . ;;;;;"':"I J_ _ ,_ _ ~~hH--:-i~=j:~=F=+=~*=t-:i-i-1 HS~~'~·~i_·~~~~~~~~~;._·~ HS~~~~~~~~~~~~~~1 HS~_·.I_·~!·~~~~~~~~i~. HS~~~~~~~~~~~~~~ Figure 8: Double Pulse, VEN' :.. HEND : HSTART: Figure 7: Double Pulse, HEN' HEND .. .. r~"+~~ H-:i,-:t f~::=.F:*=F='f1 F·=jf..:...P·'l=rH i: VEND j =: =' HS '!'L..:...1"!-!'f..:... HHSS '. ... ' :. ;- I::::::l •....•....••.....:. .1 . :....:., .:":1'7' b . ,: • . .· . ., . . , ______ ,____HS~~~_. ~-t~-L~~c: _ :,~.. f..:.... . L..:. .1 . ; ::-tF;!; I' HS • i• , .. . , . . .-f. . . Figure 10: Comer Pulse, ACT' • HEND : HSTART: Figure 9: Double Pulse, ACT' ," HEND , HSTART' • -I I" i i ! I I , f-!......... I::.':: i i f-!- '7' to' . .i . VS~j~~~~:.~~_:~:_L:~_~t:.~,;=::::::~~:·:':·::~:~l::. HS . . . --l----'T~s/iis. ! i ! I T~t=.: :_Fj: :_rF~: :;_~;: .~: :;_ =i=i=i=i:::::j:::::j-:-j:::::j:::::j':::'::! HS . . I • : • Note: The vertical counter is reset at the falling edge of each VS', regardless of whether HS' is active, and counts the number of HS' inputs. The vertical counter is also reset when VS* and HS* are asserted simultaneously. When VS' alone is asserted, the counter is set to line 0, then increments to 1 several counts later when HS* is asserted. Note that the line count is 0 if HS* and VS' are asserted simultaneously. The figures above show examples of register settings and signal output. When HS' and VS* are asserted simultaneously, the above sample signal outputs can be obtained from these register settings: HSTART - n = 0003h VSTARTod - n = 0002h HEND - n = 0009h VENDod - n = 000711 M-9 2.5 Delays Between Ports 2.5.1 Delays Between Image Data Input/Output Ports The IP90C55 introduces a delay of two clock cycles when input image data is fed from the input port through to the output port. The following figure shows this delay in image data streams. (For more information see Section 3.2, "Internal Configuration of Image Data Stream Switching Block.") Ai ,.-----, Bo 16 to 1 D Q PortPA D ... Q FIF ~ FIF CLK "il CLK " CZl PortPB ICLK (Output port latch) (Second stage) (Input port latch) (First stage) ICLK PortPA (set for input) V y., : n X! n+l X n+2 X n+3 X ------v Port PB X:: (set for output) --A--~. . (Input port latch) (First stage) (Internal switch input latch) n .X. n+ I ~ ~ (Output port latch) (Second stage) (Internal switch output latch) 2.5.2 Delays Between Image Data Input/Output Ports When Using ALUs The ALU blocks connected to the internal output ports of the IP90C55's image data stream switching block consist of two stages: an ALU unit and a barrel shifter section. Outputs from these ALU blocks are connected to the internal input ports of the switching block. Consequently, a three clock-cycle delay is added here to the two-cycle delay previously described in Section 2.5.1. M-10 The following figure shows delays in image data streams when using the ALU units. (For more information see Section 3.2, "Internal Configuration of the Image Data Stream Switching Block.") r--- Data stream switch section ~ Ai Mo FIF lCLK OUT = f(Mo,No) D Q eLK FIF 8 " en () (Input port latch) eLK " ALU #0 D Q F/F eLK ICLK (ALU operation results latch) (Third stage) ICLK (Second stage) (First stage) Port PC FIF r eLK lCLK ICLK (Barrel shifter output latch) (Fourth stage) (Output port latch) (Fifth stage) ICLK Port PA (Input setting) Port PB (Input setting) Port PC (Output setting) -:x m X :m+l ~ n X :n+1 =x Input port latch X ;\ X X ,m+2 :n+2 X Internal switch ALU output latch operation (ALUinput results latch latch) M-ll X X jm+3 :n+3 X X :m+4 :n+4 X X X X f(m,n) Barrel shifter output latch :m+5 X n+5 X ~+1) Output port latch (Internal switch (Internal switch input latch) output latch) 2.5.3 Output Delays of AOIn* Relative to HS* If zero-start is specified (by setting HZSTART, VOZSTART, and VEZSTART to 1), AOIn* goes low two clock cycles after HS* is found to be low on the rising edge of ICLK. The output image data begins with pixel O. ICLK VSEN* I!!I! \ VS* \ Li/27 HS* \ ~ AOIn* (When set for zero-start) \'---- 2.5.4 Processing Image Data Using AOI Signals The IP90C55's AOI signals (which specify rectangular areas of interest within the image) operate independently of the IP90C55's image data switches, and so can respond flexibly to each system configuration. Therefore, control using AOI signals does not affect the image data switches or change the image data. In addition, the chip can divide the rectangular AOI into inside and outside parts and apply image data stream path switching or image data masking to the parts individually. This can be done either of two ways: • by entering the AOIn* signal to any of the ports P A-PL so it will be handled as image data and processed with other signals by the ALU • by connecting the AOIn* signal directly to OEx* (where x = A, B, C, ... L) to control the output M-12 Sample Circuits 2.5.4.1 Switching ports using the AOIn* signal IMSC AOIO PA (Wired OR) PB PA and PB Set for Output Image data for PAis selected in the area specified by the AOIO* signal; image data for PB is selected in other areas. 2.5.4.2 Operating on image data with the AOIn* signal (e.g., for masking) (AND) PA and PB Set for Input, PC Set for Output. Inputs are AND'ed by the ALU, so that data is masked in the AOI-specified area and PC outputs DOh. M-13 2.5.5 Delay from Internal Image Space Address Counter Section 3.2, "Internal Configuration of Image Data Stream Switching Block," describes how to set flags Mm-Pm of port select registers PTSEL-M through PTSEL-P to 1 so that they output the values of the internal image space address counters (horizontal counter HCNT, vertical counter VCNT) to Mi-Pi, and also through a switch to external output ports PA-PL. (To reduce power consumption, the counters are disabled when all AOI areas are counted.) These functions can be used to produce test signals to debug a board or system, or to generate gradation in a picture. They can also be combined with the ALUs to generate striped patterns, thus adding greater versatility to applications. ICLK HS*~ HCNToutput Port Px output VSEN* Vs* VCNToutput Port Px output Note 1: Note 2: Note 3: Note 4: "'--!lJJ II ~ II 0 X~____ ~(~~__ O~X~____ X X 0 '-------=----\~~~ X _ _---"-0_ _ ~X=:=C= HCNT is reset at the falling edge of HS* regardless of whether VS* is active. VCNT is reset at the falling edge of VS* regardless of whether HS* is active; that is, VCNT is reset when VS* and HS* are simultaneously asserted. Also, if HS* is pulsed low c;>ne or more clock cycles after VS* goes low, VCNT is incremented from 0 to l. Px is one of the image input/output ports PA-PL. Signal value X in the above diagram depends on the preceding status of the signal. M-14 2.6 Controlling Image 1/0 Port Bidirectional Switching 2.6.1 Bus Conflict of Image Input/Output The IP90C55's image input/ output ports are protected against bus conflicts with external LSls on the interface when the ports are switched between input and output. Input data III""'---Delay circuit ..............'" PTSELx register (Xd flag) D Q FIF FIF eLK ICLK PTSEL-x register output INTDIR _ _ _ \'----+---+-\'----+--\C-.-- ~~----,I -J! DIRx _ _ _ _ Note: Px represents one of the image input/ output ports PA-PL. However, DIRx signals pins are not provided for ports PI-PL. M-15 2.6.2 Sample Connections 2.6.2.1 Using the IP90C55 as a Master and a Standard Logic Transceiver (74LS245) as a Slave 245 (Tranceiver) INTDIR G (Master) 2.6.2.2 DIR (Slave) Using the IP90C55 as a Slave 245 (Tranceiver) INTDIR Control M-16 2.6.2.3 Connecting Two IP90C55s Together IMSC #1 2.6.2.4 Port Px Port Px OEx* OEx* IMSC #2 Connecting Three IP90C55s Together IMSC #1 Port Px PortPx PortPx IMSC IMSC #2 #3 M-17 2.6.3 Synchronized Port Switching Using the Vertical Synchronization Signal (VS*) The IP90C55's registers are configured with dual latches. Data written from the CPU (host bus) to specify a port is first latched in the register latch on the CPU side. An internal register latch (a "through" latch) is provided between the internal circuit and the CPU-side register latch: the gate of this latch is opened (and the data latched) by a combination of three inputs: the REGVDIS register'S rgd flag, the SMOD register'S VS flag, and the VS* pulse (derived from the VS* field start signal by synchronizing it with the image clock). i1"""'--CPU data bus -+----i D CS* WR* ADn Register ---""""t Qr-----iD Q r---i--l'" r-+----iG To internal circuits G CPU-side register latch Internal register latch vs flag VS* pulse Ports can be switched by fields by setting the REGVDIS register's RGD flag to 0 and the SMOD register'S VS flag to 1. This enables the value to be set by the CPU (or PTSELO-x register for input/ output port switching) at the beginning of the next field (i.e., at the rising edge of ICLK immediately after VS* is pulsed low). M-lS Section 3: Internal Configuration 3.1 Internal Block Diagram AOI Pointer Block AOlO* AOI pointer No.O ICLK HS* VS* CSEN* ·· ...... Timing Gen. HENO* A013* AOI pointer No.3 FLDI* -- -. Address bus --"" Data bus - AOI pointer No.4 A014* ·· REG RD* WR* CS* RST* HEN3* - AOI pointer No.7 AOI7* Image Data Stream Selector ~ ';hl' lConstant IJlConstant 1 reg. reg. LEi ~ Mi .-- r-r-Ni I I I Note 1: Note 2: I I I I I I OEA* DIRA CiBi Ai Li ~Ao I I PA (PAO-PA7) I I I I I I ~ ~o ~o I I I ~ D I I 8-bit ~I PI (PIO-PI7) SEL,19 ALU F= SEL~ r- ~~ I- F=OO··· ~I-"-"- SEL~ L- '-- OEI* ~ Delay ~ I I I ~ r;- PL LO-PL7) ~ t-- OEL* An asterisk (*) following a signal name denotes inverse logic. This block diagram is shown only for functional description, and does not depict all of the IP90C55's functions. For details on its functions and timings, see the relevant sections in this manual. M-19 3.2 Internal Configuration of the Image Data Stream Switching Block r---------, I I I r----:====tj~~~~~; ! I I I I ---------_ .. Ci The image data stream switch consists of an input flip-flop, a switching selector, and an output flip-flop. Switching can be specified using a programmable port select register. The horizontal and vertical counter outputs for AOI control can be fed to the internal input ports Mi, Ni, Oi, and Pi of the image data stream switch. Outputs can also be controlled using a port select register. Bi Ai 8 bit Pi Oi Ni 16 to I selector Mi m······I·······j·········I············I······· ········r······Pl ~ lY- ............................... ·············1····,····===!===1=~=1 ... I : PL :PLO to PL7 ~ --~ Lo OEL* ALU-~ ············································H········~=.~ Mo #0 OUTU #1 OUTL ['No '''00 Po Note 1: Note 2: An asterisk (*) following a signal name denotes inverse logic. This block diagram is shown only for functional description, and does not depict all the IP90C55's functions. For details on its functions and timings, see the relevant sections in this manual. M-20 3.3 Internal Configuration of the ALU Block The ALUs have these basic functions (equivalent to those of an 74L5181 processor): • Arithmetic operations: addition, subtraction • Logic operations: AND, OR, XOR, NOT Right shift, left shift, MIN/MAX selection, 8/16-bit process switching r-----I~>:: ~f-+8-~ ALUEXT thO, satO (limiter setting 8 ,-----~ (maximin select control) calculation unit Internal input port Mo ---,;L-"+-_~ 8 ALUMODO register cpO-bit co it 8 8 Internal input port No 8 ;~;~l SHIFT #0 register shift settings ALUMODO register (ALU #0 function settings) it 16-bit processing ALUEXT register hd-bit Internal input port 5 calculation unit [f.;t~;l SHIFT #0 register shift settings 00 - -....-+--j~ co 8 8 Internal input port Po ALUMODI cpl-bit : ALUMODI register I (ALU #1 function settings) (max/min select control) (limiter setting) ALUEXT fixl, sat! 8 8 M-21 Section 4: Pin Functions and Packages 4.1 Pin Assignment and Functional Description No. I/O VS* VSEN* 1 1 1 1 I I I FLDI 1 I PA<7 .. 0> PB<7 .. 0> PC<7 .. 0> 8 8 8 8 8 8 8 8 8 8 8 8 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O Pin group Symbol Image sync signals ICLK HS* Image input/output bus PD<7 .. 0> PE<7 .. 0> PF<7 .. 0> PG<7 .. 0> PH<7 .. 0> Pl<7 .. 0> PJ<7 .. 0> PK<7 .. 0> PL<7 .. 0> OEA* OEB* OEC* OED* OEE* OEF* OEG* OEH* OEI* I I/O I/O I/O I/O I/O I/O I/O I I I I I I I Function Vertical sync signal input Vertical sync enable signal input Field-identifying signal input 8-bit input/ output port A 8-bit input/output port B 8-bit input/ output port C 8-bit input / output port D 8-bit input/ output port E 8-bit input/output port F 8-bit input/ output port G 8-bit input/output port H 8-bit input/output port I 8-bit input / output port J 8-bit input/ output port K 8-bit input/ output port L PA output enable PB output enable PC output enable PD output enable PE output enable PF output enable PG output enable PH output enable I I I I I I DIRA 1 0 PI output enable PJ output enable PK output enable PL output enable PA input/ output direction DIRB DIRC DIRD DIRE DIRF DIRG DIRH 1 0 0 0 0 0 0 0 PB input/output direction PC input/output direction PD input/output direction PE input/output direction PF input/output direction PG input/output direction PH input/ output direction OEJ* OEK* OEL' I 1 I I 1 I I Description Image clock input Horizontal sync signal input M-22 VS* input is enabled when VSEN' is low (Note 2). High = odd field, (used with noninterlaced) low = even field. 8-bit grayscale image data I/O These image data port pins have pull-up resistors. I/O pins (ports) are enabled for output in 8-bit units. Pins are set low for output or high for highimpedance status. These indicate the 1/0 status of I/O signal pins (ports) in 8-bit units: a high signal indicates output, and a low signal indicates input. These signals can be used as external bus buffers or transceivers, or for bidirectional communication between IP90C55 chips. These pins represent ports PA-PH (no pins for PI-PL). Pin group Symbol Image timing AOIO* HENO* AOn* HEN1" AOI2* HEN2* AOI3* HEN3" AOI4" AOIS" AOI6" AOI7* RD' WR* CS* AD<7 .. 0> DB<7 .. 0> RST' CPU bus Power supply GND Total number of pins Packages: Vdd GND No. I/O 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 I I I I 1 1 1 1 1 1 1 1 8 1 8 23 (19) Function Description AOI* output for AOI No. 0 HEN* output for AOI No. 0 AOI" output for AOI No.1 HEN" output for AOI No.1 AOI* output for AOI No.2 HEN" output for AOI No.2 AOI* output for AOI No.3 HEN" output for AOI No.3 AOI* output for AOI No.4 AOI* output for AOI No.5 Selects VENO*, HENO*, or ACTO*. I/O I AOI" output for AOI No.6 AOI* output for AOI No.7 Read signal Write signal Chip select Address bus Data bus Reset PW PW SV Ground 184 (180) Selects VEN1", HEN1", or ACTl". Selects VEN2*, HEN2", or ACT2". Selects VEN3', HEN3*, or ACT3*. AOI signal types can be HEN", VEN", or ACT*. Register selection address. Must be three clock cycles long or more (Note 3). (19) is for the PGA 18I. (180) is for the PGA 181. Pin 1 on the 181 is a locating (EXTRA) pin. l84-pin QFP (mold section 32 x 32 mm2 , pin pitch 0.65 mm). l8l-pin PGA (floor area 40 x 40 mm2 , pin pitch 2.54 mm) Note that the EXTRA pin is a locating pin. Notel: Note 2: Note 3: An asterisk following a pin name indicates inverse logic. VS* can only be detected as low when the VSEN* signal is low one or more clock cycles before VS* goes low. Use VSEN* to synchronize fields using control signals (e.g., processing a start signal from a DSP) that are not synchronized with the image clock, or to establish field synchronization between image-processing circuit blocks. VSEN* must be held low in normal operation (i.e., when the pin's function is not required). Schmitt-trigger input, with a pull-up resistor. M-23 4.2 Selecting a Package The IP90C55 is available in IS4-pin plastic QFP and lSI-pin ceramic PGA packages. When deciding which package to use in a particular device, keep in mind the IP90C55's junction temperature limit. The device must be able to dissipate enough of the heat it generates to keep its internal temperature below the IP90C55's junction temperature limit. Otherwise, the device will not operate reliably. As an approximate guide to selecting a package, the amount of heat the device generates can be estimated assuming the device operates as follow: 1. The heat generated (and power consumed) by CPU access to the internal registers is negligible compared to the heat generated by driving image data signals. 2. The average rate of change for image data is 50%. 3. Heat radiates under normal conditions (the device mounted on a board with no special heat sink). 4. Approximately S of the 12 ports on the image data bus are driven when image data is output (that is, eight ports consume power). 5. The output load capacitance is about 30 pF. Under these assumptions, the plastic QFP can be used for image clock speeds up to 20 MHz, while the ceramic PGA can be used for clock speeds from about 20 MHz to 40 MHz. If the device will be used outside the above conditions, it must include a heat sink or air-cooling unit to increase heat radiation; even with a heat sink or cooling unit, however, the device still may not operate reliably. If operating conditions differ from the above assumptions, see Section 4.3, "Estimating the Approximate Amount of Power Consumption." If the output pins have a large load capacitance, for example, the device's power consumption increases, and so must use a lower clock frequency. Conversely, if fewer output ports are driven, the device can operate at a higher clock frequency. The ceramic PGA package has better heat radiation characteristics than the plastic QFP, and can therefore be used in high-performance, high-reliability systems. If the system requires wiring changes in prototype production, or if its power consumption or heat-radiation characteristics cannot be estimated, use the ceramic PGA. Verify power consumption after the prototype is complete and mass production is under way, and then use the plastic QFP if the device meets the above conditions, or if the system will always operate at clock speeds of 20 MHz or less. [References] The IP90C55's operational limits with respect to temperature are actually determined by the temperature (technically known as the "junction temperature") at which the transistors can operate safely without reducing their performance and reliability. This temperature is estimated from the heat generated by the device's power consumption and its heat radiation characteristics, which are affected by the package material and heat radiation design features. The heat generated is the sum of various heat-generating sources: power consumed for internal operation, which is proportional to the clock frequency and operating rate; the drive current on each output pin; the through current that flows when an intermediate voltage is applied to an input pin; the power consumed in each pull-up or pull-down resistor; and each transistor's leakage current. The device's heat radiation characteristics are affected by the ambient temperature, air-cooling flow rate, presence of a heat sink, ability to radiate heat to the circuit board, and the shape and thermal resistance of the package material used. M-24 4.3 Estimating the Approximate Amount of Power Consumption A device's power consumption is determined by such factors as the number of output ports, operating frequency of the image clock (ICLK), load capacitance of output pins, and operating rate (change rate of image data signal). The graphs on the following pages show the approximate amount of power consumed by the IP90C55 under different output pin load capacitances: a) 30 pF, b) 40 pF, c) 50 pF, and d) 60 pF. Note, however, that this does not include the device's own pin capacitance of 10 pF. These approximations assume that the device is driven at 50% of the operating rate. In cases where the blanking period is long and the average operating rate is low, or where the average operating rate is higher than 50% (as occurs with a clock's frequency-divided waveform), power consumption must be recalculated accordingly. The power consumed by access to the CPU buses is minimal and can be included in the calculation errors because the access frequency is much lower than the operating rate. In special applications where registers are accessed to perform reads almost constantly and the CPU buses are frequently driven, the power consumed by CPU access can be considered equivalent to that of one image data port. The l8l-pin ceramic PGA and l84-pin plastic QFP packages have allowable limits of 1500 mW and 1000 mW, respectively. When using the devices, make sure these limits are not exceeded. M-25 a) Output Pin Load Capacitance = 30 pF 2000,..---_r--~--_,r_--._--._--_r--_.----r_--,_--, 181 PGA Allowable power consumption ......L..... ~............................................... ~ '1 184 QFP Allowable power consumption 40 MHz 35 MHz 30 MHz 1000 '"<= 25 MHz u 20 MHz 0 l; ~ ~ 10 MHz (ICLK operating frequency) 3 5 7 9 11 Number ofI/O ports (PA-PL) used as output ports b) Output Pin Load Capacitance = 40 pF 2000 -,----r----.-------.----,,.---r---r----,---,---..., 181 PGA Allowable power consumption 40 MHz ...... 1. .... .1 ............................................. 35 MHz 184 QFP Allowable power consumption 30 MHz 25 MHz 20 MHz 10 MHz (lCLK operating frequency) 7 3 9 5 Number of 110 ports (PA-PL) used as output ports M-26 11 c) Output Pin Load Capacitance = 50 pF 2000 .---,----r-----.----r---,--~--~-_._-~ 181 PGA Allowable power consumption 40 MHz -----J-----~-------- -------------- 35 MHz 30 MHz 184QFP Allowable power consumption ~ 5 <= 25 MHz 0 '.::I S' ;; 20 MHz 1000 '"<= 0 u ~ ~ 0 10 MHz (lCLK operating frequency) p.. OT--~--r--,---+-_4--~-~-+--4_~ 3 7 5 9 11 Number of I/O ports (PA-PL) used as output ports d) Output Pin Load Capacitance = 60 pF Woo.---.--.----r--,---,--.--r--r-~ 181 PGA Allowable power consumption 35 MHz ------l------~--------------------184 QFP ~ 30 MHz 25 MHz Allowable power consumption <= 0 40 MHz 20 MHz 'g, S ;; 1000 <= '" 0 u ~ ~ 0 10 MHz (ICLK operating frequency) p.. OT--~--+--.--+-~~-~-+--4_-~-~ 3 5 7 9 Number of I/O ports (PA-PL) used as output ports M-27 11 4.4 Table of Pin Assignments for the 184-Pin Plastic QFP No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Symbol GND OEA' DIRA PAO PAl PA2 PA3 PA4 PAS PA6 PA7 GND OEB* DIRB PBO PB1 PB2 PB3 PB4 PBS PB6 GND Vdd GND PB7 OEC* DIRe PCO PC1 PC2 PC3 PC4 PC5 PC6 GND PC7 OED* DIRD PDO PD1 I/O PW I 0 I/O I/O I/O I/O I/O I/O I/O I/O PW I 0 I/O I/O I/O I/O I/O I/O I/O PW PW PW I/O I 0 I/O I/O I/O I/O I/O I/O I/O OW I/O I 0 I/O I/O No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Symbol PD2 PD3 PD4 PD5 PD6 Vdd GND PD7 OEE' DIRE PEO PEl PE2 PE3 PE4 PES PE6 GND PE7 OEF* DIRF PFO PFI PF2 PF3 PF4 PF5 GND Vdd GND PF6 PF7 OEG* DIRG PGO PG1 PG2 PG3 PG4 PG5 M-28 I/O I/O I/O I/O I/O I/O PW PW I/O I 0 I/O I/O I/O I/O I/O I/O I/O PW I/O I 0 I/O I/O I/O I/O I/O I/O PW PW PW I/O I/O I 0 I/O I/O I/O I/O I/O I/O No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 Symbol GND PG6 PG7 OEH* DIRH PHO PHI PH2 PH3 PH4 PHS Vdd GND PH6 PH7 OEl* PIO PIl PI2 PI3 PI4 PIS GND PI6 PI7 OEJ* PJO PJl PJ2 PJ3 PJ4 PJ5 PJ6 GND Vdd GND PJ7 OEK* PKO PK1 I/O PW I/O I/O I 0 I/O I/O I/O I/O I/O I/O PW PW I/O I/O I I/O I/O I/O I/O I/O I/O PW I/O I/O I I/O I/O I/O I/O I/O I/O I/O PW PW PW I/O I I/O I/O No. Symbol I/O No. Symbol I/O No. Symbol I/O 121 122 123 124 PK2 PK3 PK4 PK5 PK6 PK7 OEL' GND PLO PLl PL2 P13 PIA PLS PL6 PL7 GND Vdd GND AOIO* HENO* AOIl* 1/0 I/O I/O I/O I/O I/O I PW I/O I/O I/O I/O 143 144 145 146 147 148 149 150 151 152 153 154 HEN1' GND AOI2* HEN2* AOI3* HEN3* GND AOI4* AOI5* A0I6* 155 156 157 158 159 160 161 162 163 164 VSEN* VS* HS* 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 WR* RD* ADO AD1 AD2 AD3 AD4 ADS AD6 AD7 GND DBa DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vdd I I I I I I I I/O I/O I/O I/O PW PW PW 0 0 0 0 PW 0 0 0 0 PW 0 0 0 0 PW I I I I PW I PW PW I I 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 AOI7* GND FLDI GND ICLK Vdd GND RST* CS* 138 93 + Sumitomo Metals IP90C55 XXXXXJapan 184 M-29 I I I PW I/O I/O I/O I/O I/O I/O I/O I/O PW 4.5 Table of Pin Assignments for the 181-Pin Ceramic PGA No. Symbol I/O No. Symbol 1 2 3 4 5 6 7 8 9 10 Vdd PW PW 41 42 43 44 45 46 47 48 49 50 51 52 53 54 DB6 DB7 Vdd PAO PAl PA2 PA3 PA4 PAS PDO PD1 PD2 PD3 PD4 PD5 PD6 DIRD PE3 PE4 PES PE6 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 GND PD7 OEE* Vdd OEI' PIO PIl PI2 PI3 PI4 PI2 PL3 PIA I/O I 0 I/O I/O I/O I/O I/O I/O I/O I/O I/O PW I I/P I/O I/O I/O I/O I/O I/O I/O PLS PL6 PL7 GND Vdd GND AOIO' HENO* AOIl' HEN1' AOI2* HEN2* I/O I/O I/O PW PW PW 0 0 0 0 0 0 DB2 DB3 I/O I/O DB4 DB5 I/O I/O DIRE PEO PEl PE2 PHO PHI PH2 PH3 PH4 PH5 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 GND PE7 PG5 GND PG6 PG7 OEH' DIRH PIS GND PI6 PI7 OEJ* PK5 PK6 PK7 OEL* GND PLO M-30 I/O No. Symbol I/O I/O I/O PW 81 82 83 PLl AOI3* HEN3* 84 GND A014* AOI5* AOI6' AD5 AD6 AD7 GND DBO DB1 PA6 PA7 GND OEB* DIRB PC4 PC5 PC6 GND PC7 OED* I/O 0 0 PW 0 0 0 I I I PW I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 0 I/O I/O I/O I/O PW I/O I/O PW I/O I/O I 0 I/O PW I/O I/O I I/O I/O I/O I PW I/O 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 PC3 OEF* DIRF PFO PF1 PF2 PGO PG1 PG2 OG3 PG4 PJO PJ1 PJ2 PJ3 OEK* I/O I/O I/O I/O PW I 0 I/O I/O I/O PW I/O I I/O I 0 I/O 1.0 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I No. Symbol I/O No. Symbol I/O No. 121 122 123 124 125 PKO PK1 PK2 PK3 PK4 A0I7* 1/0 I/O I/O I/O I/O 0 PW I I I I I I I I 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 PCO PC1 PC2 PB7 PF3 PF4 PF5 Vdd PF6 PF7 OEG* DIRG GND PH6 PH7 I/O I/O I/O I/O I/O I/O I/O PW 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 Pin 181 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 GND VSEN* VS* HS* ADO AD1 AD2 AD3 AD4 PBO PB1 PB2 PB3 OEC* 141 DIRC I/O I/O I/O I/O I I/O I/O I 0 PW PJ4 PJ5 PJ6 Vdd I/O I/O I/O I/O I/O PW PJ7 I/O Symbol I/O FLDI GND ICLK Vdd RST* I PW I PW I I I I PW I 0 CS* WR* RD* GND OEA* DIRA PB4 I/O PBS I/O PB6 I/O Vdd PW GND PW GND PW GND PW GND PW is an extra pin. 0 @@@@@@@@@@@@@@@ @5~ @@@@@@@@@@@@J@ @@Il0@@@@@@@@@@/@@ @@ @@(O)(O)@@@@@@F@@@ ~RA @@@@\0 @ @@@@ 177 @@@@ @@@@ @@@@ @@@@ @@@@@180 178@@@@@ @@@@ @@@@ @@@@ 179 @@@@ @@@@ @ @@@@ @ @ @1~ @@ @@@@ @ @M~ @@ @@ @ @ @ @ @ @ @ @ @ @s@ @ Jw @l~@@@@@@@@@@@@@ .@)@@@@@@@@@@@@@® Bottom View M-31 4.6 Outline Dimensions of the 184-Pin Plastic QFP 32.5 ± 0.4 l.375TYP -H4--[-$-[0.13 @ [ ~~:ll 33.6 ± 0.4 0 units: mm M-32 4.7 Outline Dimension of the 181-Pin Ceramic PGA 40.0 ± 0.51 ~ I ~ I , - - - - - - - - - - - - - - . . ------.- -o on +1 o o ..;- D M o +1 ..;~ M o +1 M M @©©©©©©©©©©©©©@ ©'@ © © © © © © © © © © © c§) © ©©'@)©©©©©©©©©@'©© © © © @ @ @ © © © © © @J3© © © ©©©©~A © ©©©© ©©©© 117 ©©©© ©©©© ©©©© ©©©©©i80 178©©©©© ©©©© ©©©© ©©©© 279 ©©©© © ©©©© ©©©© © © ©,~ © © © © © © ©@@©© © © ,@ @ © © © © © © © © @5© © ©'<;0©©©©©©©©©©©@© @)©©©©©©©©©©©©©@ Bottom View M-33 unit: mm Section 5: Registers 5.1 Table of Registers (Address Map) All registers are read/write except the wrf flag of the SMOD register. Address (hex) 00 01 02 03 04 05 06 07 OS 09 OA OB OC-OE OF 10-1F 20-2F 30-3F 40-4F 50-5F 60-6F 70 -7F 80-82 83-SF 90-9F AO,A1 A2,A3 A4 A5,A6 A7-FB FC FO FE FF Note 1: Width in bits Abbreviation AOI-O HSTART-n HENO-n (Low) (High) 8 8 (Low) 8 8 (High) VSTARTod-n 8 8 8 8 8 8 8 8 (Low) (High) VENOod-n (Low) (High) where VSTARTev-m (Low) (High) n=O VENOev-n (Low) (High) (Reserved) (Note 1) AOIMOO-n AOI-1 Similar to AOI-O, where n AOI-2 Similar to AOI-O, where n AOI-3 Similar to AOI-O, where n AOI-4 Similar to AOI-O, where n AOI-5 Similar to AOI-O, where n AOI-6 Similar to AOI-O, where n AOJ-7 Similar to AOI-O, where n ZEROSTART (Reserved) PTSEL-A to P CONSTO, CONSTl ALUMOOO, ALUMODl ALUEXT SHIFTO, SHIFTl (Reserved) TESTM REGVDIS SMOO MMOO 7 =1 =2 =3 =4 =5 =6 =7 - - - 5 8 8 5 5 - 1 2 2 Functional outline AOI-n odd/even image data Start point of area of interest in horizontal direction AOI- odd/even image data End point of area of interest in horizontal direction AOI-n odd image data Start point of area of interest in vertical direction AOI-n odd image data End point of area of interest in vertical direction AOI-n even image data Start point of area of interest in vertical direction AOI-even image data Endpoint of area of interest in vertical direction AOI-n even image data Chooses the AOI-n signal and output waveform AOI-1 pointer register set AOI-2 pointer register set AOI-3 pointer register set AOI-4 pointer register set AOI-5 pointer register set AOI-6 pointer register set AOI-7 pointer register set Sets the AOI zero-start flag (Unused address) Port-select register Constant registers (Oi, Pi ports) ALU function registers ALU extended function register Right bit shifter shift-setting registers (Unused address) Test the device's internal logic Register data disable Sub-mode register Main mode register The IP90C55 has eight pairs of AOI register sets: these are represented above by AOI-O, though the information also applies to register sets AOI-l through AOI-7. M-34 5.2 AOI Pointer Register Sets These register sets specify the coordinates of the area of interest. Coordinates in the vertical and horizontal directions are each specified with 16 bits. The IP90C55 has eight pairs of AOI pointer register sets. Note: The AOI pins (HEN-n*, AOI-n*) corresponding to each of the AOI pointer register sets have a numerical suffix 0-7. In the following descriptions, a given AOI pointer register set is represented by a suffix "n," where n equals 0, 1, 2, 3, 4, 5, 6, or 7. The suffix "n" is attached to the corresponding AOI pin (HEN-n*, AOI-n*) for the given AOI pointer register set. For example, when specifying coordinates for AOI-3 (HEN3*, A013*), the starting coordinate in the horizontal direction is HSTART-3, and is allocated at addresses 30h and 31h. HSTART-n odd/even screen Horizontal area of interest start-point setting register. Specifies the AOI's first horizontal coordinate value-I. ~7 ~O I I I I I I I I Reg. name Address HSTART-n low nOh I HSTART-n high nIh The data entering at the rising edge of ICLK immediately after HS* is detected low by a rising edge of ICLK is named D(O), and successive data is sequentially named D(I), D(2), D(3), ... , D(m). If N-l is set in the HSTART-n register, the AOI begins with data D(N). However, if the area of interest to is to begin from data D(O), set bit-n in HZSTART (SOh) to 1. In this case, the value of the HSTARET-n register is ignored. HEND-n odd/even screen Horizontal area of interest end-point setting register. Specifies the AOI's last horizontal coordinate. ~7 ~O I I I I I I I I I Reg. name Address HEND-n low n2h HEND-n high n3h The data entering at the rising edge of ICLK immediately after HS* is detected low by a rising edge of ICLK is named D(O), and successive data is sequentially named D(l), D(2), D(3), ... , D(m). If N is set in the HEND-n register, the AOI is valid up to data D(N) and becomes invalid beginning with data D(N+l). M-35 VSTARTod-n odd screen Vertical area of interest start-point setting register. For interlaced operation, this register specifies the AOI's first vertical coordinate value-1 in an odd field. For non-interlaced operation, this register specifies the AO!' s first vertical coordinate value-I. This register value is used when the FLDI input is high. ~7 ~o I I I I I I I I I Reg. name Address VSTARTod-n low n4h VSTARTod-n high n5h The first vertical coordinate determines the number of high-to-Iow transitions of HS* pulses counted by the rising edge of ICLK after VS* is asserted low. For example, if M-1 is set in the VSTARTod-n register, low HS* pulses occurring after VS* is asserted low are counted as the 1st, 2nd, 3rd, ... , and M_lth lines, with the AOI beginning from the Mth line of data. If VS* and HS* are simultaneously asserted low at the rising ed~e of ICLK, the HS* pulses are counted as the Oth, 1st, 2nd, 3rd, ... , and M-1t . If the AOI is to begin from the Oth line of data, set bit-n in the VOZSTART register (81h) to l. VENDod-n odd screen Vertical AO! end-point setting register. For interlaced operation, this register specifies the AOI's last vertical coordinate in an odd field. For non-interlaced operation, this register specifies the AOI's last vertical. This register is used when the FLDI input is high. bit 7 bit 0 I I I I I I I I I Reg. name Address VENDod-n low n6h VENDod-n high n7h The last vertical coordinate determines the number of high-to-Iow transitions of HS' pulses counted by the rising edge of ICLK after VS* is asserted low. For example, if M is set in the VENod-n register, low HS* pulses occurring after VS* is asserted low are counted as the 1st, 2nd, 3rd, ... , and M-1th lines, with the AOI becoming invalid beginning from the M+1th line of data. If VS* and HS* are simultaneously asserted low at the rising edge of ICLK, the HS* pulses are counted as the Oth, 1st, 2nd, 3d, ... , and M_1th. M-36 VSTARTev-n even screen Vertical AOI start-point setting register. For interlaced operation, this register specifies the AOI's first vertical coordinate value-1 in an even field. For non-interlaced operation, this register is ignored. This register is used when the FLDI input is low. W7 WO I I I I I I I I I Reg. name Address VSTARTev-n low n8h VSTARTev-n high n9h If VS* and HS* are simultaneously asserted low at the falling edge of ICLK, the HS* pulses are counted as the Oth, 1st, 2nd, 3rd, ... , and M-1 th lines. To start the AOI from the Oth line of data, set bit-n in VEZSTART (82h) to 1. VENDev-n even screen Vertical AOI end-point setting register. For interlaced operation, this register specifies the AOI's last vertical coordinate in an odd field. For non-interlaced operation, this register is ignored. This register value is used when the FLDI input is low. W7 WO I I I I I I I I I M-37 Reg. name Address VENDev-n low nAh VENDev-n high nBh AOI mode register AOIMOD-n (n = 0, 1, 2, ... , 7) This bit selects the waveform (Level, Single, Double, or Corner) of the AOI signal output from the AOIn* signal pin, as well as the type of the AOI signal (HEN*, VEN*, ACT*). The setting also controls whether AOI signal output is enabled, or output remains at high level. The HENn* (n=O, 1, 2, 3) signal pins carry only those output signals that can be output from the AOIn* (n=O, 1, 2, 3) signal pins. bit 7 bit 6 bit 5 bit 2 bit ° Reg. name '--_O--'-I_A_O_I_ex_e_-_n....I_ _ _A_O_I..;;.p_-n_ _ _.....1A_O_Is_-n .......1 AOIMOD-n Address nFh, 1Fh, 2Fh, 3Fh, 4Fh, 5Fh, 6Fh, 7Fh AOIs-n: AOI signal-select flag When n = 0, 1, 2, 3: This flag chooses VEN*, HEN*, or ACT* for output from the AOln* pin. For output from the HENn* pin, however, HEN* is selected directly. Thus, the HENn* pins output HEN* regardless of whether VEN* or ACT* is selected as output from the AOIn* pins. When n = 4, 5, 6, 7: This flag chooses HEN*, VEN*, or ACT* for output from the AOIn* pin. AOIp-n: AOI waveform-select flag The waveform of the AOI signal output from the AOIn* signal pins. This flag chooses the AOI waveform from Level, Single, Double, and Corner. It also chooses between 1-field[[-only?1l or 2-field-only output. The waveform of the HEN* signal output from the HENn* (n=O, 1, 2, 3) pins is the wave form selected for the AOIn* (n=O, 1, 2, 3) pins. Also, the "Corner pulse" waveform is only enabled when ACT* is selected. Thus, if the Corner pulse waveform is selected for the AOln* pins, the output from the HENn* pins is undefined. AOIexe-n: AOI output enable flag This flag enables AOI signal output from the AOln* signal pins. When output from the AOIn* pins is enabled or held at high level, output from the HENn* pins is also either enabled or held at high level, respectively. If AOIexe-n = 0, AOI is not output. It remains high. If AOIexe-n = 1, AOI is output beginning with the field next to the one in which this flag bit is set to 1. 0: Do not use this bit. Leave it set to 0. M-38 AOIs-n AOI signals output Remarks bit 1 bit 0 (Note 1) 0 0 1 1 0 1 0 1 Inactive HEN* VEN* ACT* (Note 2) Note 1: Note 2: Horizontal AOI signal Vertical AOI signal AOI signal The HENn* signal pins output only the HEN* signal. ACT = (HEN • VEN). AOIp-n Output bit 5 bit 4 bit 3 bit 2 Output mode 0 0 0 X 0 0 0 1 1 0 0 1 0 1 0 0 1 X 1 1 0 0 I-field only 1 1 1 0 1 0 0 0 1 1 1 0 2-field only I-field only 2-field only 1 1 1 1 0 1 1 1 1 0 1 1 I-field only 2-field only I-field only X X Continuous every field 2-field only waveform Remarks Level Single Pulse The output waveform described on Double Pulse the left is ou tpu t every field Corner Pulse (Note 2) Level Use this setting to output AOI for only one screen (1 or 2 fields) immediately Single Pulse after the field in which AOIexe-n is set to 1. For interlaced operation, Double Pulse one screen (i.e., one frame) consists of two fields. Corner Pulse (Note 2) After 1- or 2-field output is complete, AOI can be output every field or for either one or two fields by clearing AOIexe-n to 0 before setting it to 1 again. Combinations of AOI Output Signals and Waveforms Figures 1-10 are in Section 2.4, "Example of Outputting Signals to Specify Rectangular Image Areas." Output signal (bit 1, bit 0) Output waveform (bit 3, bit 2) Level 00 Single Pulse 01 None HEN* VEN* ACT* (Note 2) High Figure 1 Figure 2 Figure 3 Undefined (Note 3) Undefined (Note 3) Undefined (Note 3) Figure 4 Figure 7 Undefined (Note 3) Figure 5 Figure 8 Undefined (Note 3) Figure 6 Figure 9 Figure 10 (Note 4) Note Note Note Note Note 1: 2: 3: 4: 5: 00 01 10 11 Double Pulse 10 Corner Pulse 11 An asterisk (*) at the end of a signal name indicates inverse logic. Only when ACT* is selected as the AOI signal. ACT = (VEN • HEN). If described as undefined, values are not guaranteed. This pulse is output at the first falling edge of HEN* after VEN* is asserted, and again at the first rising edge of HEN* after VEN' is deasserted. M-39 5.3 Setting AOI Zero-Start Flag Set the eight sets of start coordinates for an AOI to begin from the Oth pixel or 9th line. HZSTART odd/even screen data Horizontal AOI start point zero-setting flag set. Specifies 0 as the AOl's first horizontal coordinate. bit 7 bit 0 ~--~---T--~~--~---r--~----r---~ Reg. name Address HZSTART 80h bit-n = 0: The first horizontal coordinate of AOI-n (AOI) is the value set by the HSTART-n register. bit-n = 1: The first horizontal coordinate of AOI-n (AOI) begins from the 9th pixel, and the value of the HSTART-n register is ignored. VOZSTART odd screen Vertical AOI start point zero-setting flag set. For interlaced operation, this specifies 0 as the AOI's first vertical coordinate in an odd field. For non-interlaced operation, this specifies 0 as the AOl's first vertical coordinate. bit 7 bit 0 .--.,--,-------r-----,-----.-----.----,---. bit-n = 0: bit-n = 1: Reg. name VOZSTART Address 81h The first vertical coordinate of AOI-n (AOI) is the value set by the VSTARTod-n register. If VS' and HS' are simultaneously asserted low at the rising edge of ICLK, the HS' pulses are counted as the Oth, 1st, 2nd, ... , and M_1th lines, and the first vertical coordinate of AOI-n (AOI) begins from the Oth line. M-40 VEZSTART even screen Vertical AOI start point zero-setting flag set. For interlaced operation, specifies 0 as the AOI's first vertical coordinate in an even field. For non-interlaced operation, this register is ignored. bit 7 bit 0 Reg. name Address ~~~-'--~--~---r--~--~--' VEZSTART bit-n = 0: bit-n = 1: 82h The first vertical coordinate of AOI-n (AOI) is the value set by the VSTARTev-n register. If VS* and HS* are simultaneously asserted low at the falling edge of ICLK, the HS* pulses are counted as the Oth, 1st, 2nd, ... , and M-1 th lines, and the first vertical coordinate of AOI-n (AOI) begins from the Oth line. M-41 5.4 Port-Select Registers PTSEL-x (x = A, B, ... , P) The IP90C55's internal output ports Ao-Po (8 bits each) are cormected to its internal input ports Ai-Pi (also 8 bits each). These registers specify the internal port and output ports through which data is fed. Note: PA represents external I/O pins PAO-PA7 (similarly for ports PB-PL). Ai represents internal input ports AiO-Ai7 (similarly for ports Bi-Pi). Ao represents internal output ports AoO-A07 (similarly for ports BoPo). Each 8-bit input port Ai-Li is cormected to the input side of the 8-bit external input/output pins P A-PL (that is, input port #i is connected to the input side of external I/O pin p#, where # denotes A, B, C, ... , L.) Similarly, each 8-bit output port Ao-Lo is cormected to the output side of the 8-bit external input/ output pins A-L. bit 7 0 0 0 0 0 0 0 0 0 0 0 0 Mm Nm Om Pm PSELxo: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 bit 4 Ad Bd Cd Dd Ed Fd Gel Hd Id Jd Kd Ld 0 0 0 0 bit 0 PSELAo PSELBo PSELCo PSELDo PSELEo PSELFo PSELGo PSELHo PSELIo PSELJo PSELKo PSELLo PSELMo PSELNo PSELOo PSELPo Reg. name PTSEL-A PTSEL-B PTSEL-C PTSEL-D PTSEL-E PTSEL-F PTSEL-G PTSEL-H PTSEL-I PTSEL-J PTSEL-K PTSEL-L PTSEL-M PTSEL-N PTSEL-O PTSEL-P Address 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh Port-select flag Bit 4 specifies the internal input port from which data is output. M-42 xd: External image I/O pin input/output mode setting flag Sets the PxO-Px7 8-bit external input/ output pins for input or output. xd = 0: PxO-Px7 are set for input PxO-Px7 are set for output xd = 1: where x denotes A, B, ..., L. For example, if set to Gd = 0 and Hd = 1, external image pins PGO-PG7 would be set for input, and pins PHO-PH7 would be set for output. The flag is cleared to 0 when reset, and so all image data I/O pins are set for input. This is a protective measure to prevent signal collisions at output pins when the device is reset. Mm to Pm: Input port data-select flags This flag selects the input data for internal input ports Mi, Ni, Oi, and Pi: Mm = 0: Sets the output of ALU#O to the Mi input port. Mm=l: Sets the value of the upper byte (HCNTH) of the horizontal pixel counter HCNT to the Mi input port. Nm=O: Nm=l: Sets the output of ALU#l to the Ni input port. Sets the value of the lower byte (HCNTL) of the horizontal pixel counter HCNT to the Ni input port. Om=O: Sets the CONSTO of the constant register to the Oi input port. Sets the value of the upper byte (VCNTH) of the vertical pixel counter VCNT to the Oi input port. Om=l: Pm=O: Pm= 1: Note: Sets the CONSTl of the constant register to the Pi input port. Sets the value of the lower byte (VCNTL) of the vertical pixel counter VCNT to the Pi input port. Mo and No are connected to the input of ALU#O; 00 and Po are connected to the input of ALU#1. Internal I/O ports Mi, Mo, Ni, No, Oi, 00, Pi, and Po are not connected to the IP90C55's external input/output pins. M-43 0: Not used. Write the value O. PSELxo bits 0-3 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Selected input port Input signal from Ai is selected. Input signal from Bi is selected. Input signal from Ci is selected. Input signal from Di is selected. Input signal from Ei is selected. Input signal from Fi is selected. Input signal from Gi is selected. Input signal from Hi is selected. Input signal from Ii is selected. Input signal from Ji is selected. Input signal from Ki is selected. Input signal from Li is selected. Input signal from Mi is selected. Input signal from Ni is selected. Input signal from Oi is selected. Input signal from Pi is selected. However, if ports Ao-Lo are specified so that the input-to-output path specification is looped, data FFh is set to the output port. For example, if input port Ai is specified for output port Ao, Ao is set to FFh. M-44 5.5 Constant Registers (Oi and Pi ports) These registers set constants to the Oi and Pi ports. CONSTO Oi port constant register This register sets the Oi input port to a constant value. bit 7 bit 0 Reg. name Address r-~r-~~-'~~~-r~-.~-r~, CONSTO AOh CONSTl Pi port constant register This register sets the Pi input port to a constant value. bit 7 bit 0 Reg. name Address r-~r--'~~---r---r---r--~--' CONSTl M-45 Alh 5.6 ALU Function Registers These registers set the functions of the two 8-bit ALU (arithmetic/logic) units. The ALUs functions are equivalent to those of the 74LS181 processor. ALUMODO ALU#O function register ALU#O receives input from the Mo and No output ports, and sends its output to the Mi input port (when PTSEL-M bit 7: Mm =0) through a right bit shifter (SHIFT#O). (If cpO = 1, i.e., selection between large and small, the ALU#O output is not routed through SHIFT#O.) This register sets the arithmetic processing function of ALU#O. bit 7 bit ° Reg. name Address ALUMODO A2h ALUMOD1 ALU#l function register ALU#l receives input from the 00 and Po output ports, and sends its output to the Ni input port (when PTSEL-Nbit7: Nm = 0) through a right bit shifter (SHIFT#l). (If cp1 = 1, i.e., selection between large and small, the ALU#l output is not routed through SHIFT#1.) This register sets the arithmetic processing function of ALU#1. bit 7 bit 0 Reg. name Address ALUMODl A3h fsO, 1: ALU function flag Sets the basic function. fmO, 1: Arithmetic/logic switching flag Specifies whether arithmetic or logic operation. ciO, 1: Carry input cpO,l: MAX, MIN AB function execution flag Executes large or small (MIN AB, MAX AB) select function. In this case, the values set for fsO, 1 and fmO, 1 are ignored. mgO,l: MAX, MIN select flag Specifies select large or select small in large/small (MIN AB, MAX AB) select function. M-46 The truth table for ALU#O and ALU#l is shown below. Output Input fmO, 1 = 0 (ARITHMETIC operation) fsO, 1 fmO, 1 = 1 bit 3 bit 2 bit 1 bit 0 (LOGIC function) ciO, 1 = 1 (no carry) ciO, 1 = 1 (with carry) mgO, mgl cpO, cpl X 0 0 0 0 0 Q = U* Q=U Q = U plus 1 X 0 0 0 0 1 Q = (U+V)* Q=U+V Q = (U+V) plus 1 X 0 0 0 1 0 Q = U*-V Q = U+V* Q = (U+V*) plus 1 X 0 0 0 1 1 Q=O Q = minus 1 (2'compl) Q= ZERO X 0 0 1 0 0 Q = (U-V*) Q = U plus (U-V*) Q = U plus (U-V*) plus 1 Q = (U+V) plus (U-V*) plus 1 X 0 0 1 0 1 Q = V* Q-(U+V) plus (U-V*) X 0 0 1 1 0 Q = UxorV Q = U minus V minus 1 Q=Uminus V X 0 0 1 1 1 Q = U-V* Q = (U-V*) minus 1 Q = U-V* X 0 1 0 0 0 Q = U*+V Q = U plus (U-V) Q = U plus (U-V) plus 1 X 0 1 0 0 1 Q = (UxorV)* Q = U plus V X 0 1 0 1 0 Q=V Q = (U+V*) plus (U-V) Q = (U - V*) plus (U - V) plus 1 X 0 1 0 1 1 Q = U-V Q = (U-V) minus 1 Q=U-V X 0 1 1 0 0 Q= 1 Q = Uplus U Q = U plus U plus 1 X 0 1 1 0 1 Q=U=V* Q = (U+V) plus U Q = (U+V) plus U plus 1 X 0 1 1 1 0 Q=U+V Q = (U+V*) plus U Q = (U+V*) plus U plus 1 X 0 1 1 1 1 Q=U Q=Uminus 1 Q=U 0 1 X X X X Q=MINUV 1 1 X X X X Q=MAXUV - : +: AND OR xor: EXCLUSIVE OR MIN: Denotes negative logic. Compares U and V to choose the smaller. MAX: Compares U and V to choose the larger. X: This bit is ignored. U: Denotes Mo for ALU#O; denotes 00 for ALU#1. V: Denotes No for ALU#O; denotes Po for ALU#1. M-47 Q = U plus V plus 1 5.7 ALU Extended Function Register This register limits the calculation results and perform 16-bit operations. However, if the ALU units are combined to function as a 16-bit ALU (when ALUEXT's hd flag = 1), ALU#O function register ALUMODO must be set to the same value as ALU#l function register ALUMOD1, and the ALUEXT flags must be set so that satl = satO, and fix1 = fixO. ALUEXT ALU extended function register If the result of an ALU addition or subtraction exceeds 255 (FFh) or is smaller than 0, this register sets the calculation result to 255 (FFh) or 0, respectively. It also allows the two ALU units to be combined to perform 16-bit operations. bit 7 bit 0 Reg. name Address "'--0--'-1-0----'-0-'Ir-h-d--r-Is-a-tl....l-fi-x1--rI-sa-tO-·'-1f-ix-'O1 ALUEXT fixO: satO: ALU#O arithmetic operation result limit enable flag fixO = 0: fixO = 1: = 1: When fixO = 1, if ALU#O performs an addition and the result is greater than 255 (FFh) (carry output = 1), the result is fixed at 255. ALU#l arithmetic operation result limit enable flag fix1 = 0: fix1 = 1: sat1: The result of ALU#O's arithmetic operation is output directly to SHIFT#O without modification. If the result of ALU#O's arithmetic operation exceeds 255 (FFh) (carry output = 1), the value is fixed at 255. If the result is smaller than 0 (carry output = 0), the value is fixed at O. ALU#O arithmetic operation result limit value setting flag When fixO = 1, if ALU#O performs a subtraction and the satO = 0: result is smaller than 0 (carry output = 0), the result is fixed at O. satO fixl: A4h The result of ALU#l's arithmetic operation is output directly to SHIFT#l without modification. If the result of ALU#l's arithmetic operation exceeds 255 (FFh) (carry output = 1), the value is fixed at 255. If the result is smaller than 0 (carry output = 0), the value is fixed at O. ALU#l arithmetic operation result limit value setting flag satl = 0: When fix1 = 1, if ALU#l performs a subtraction and the result is smaller than 0 (carry output = 0), the result is fixed at O. satl = 1: When fix1 = 1, if ALU#l performs an addition and the result is greater than 255 (FFh) (carry output = 1), the result is fixed at 255. Note: If hd = 1, the above value 255 (FFh) is changed to 65535 (FFFFh). M-48 hd: ALU 16-bit-processing enable flag This flag connects ALU#O and ALU#l together to perform 16-bit operations. The two bit shifts SHIFT#O and SHIFT#l (9 bits each) are also connected together to become a 17-bit shifter to handle 16-bit operation results and the carry bit. hd = 0: 8-bit processing mode (normal mode) hd = 1: 16-bit processing mode Operations are performed for Mo (upper byte) and 00 (lower byte), and for No (upper byte) and Po (lower byte). The operation result is output through the bit shifter to Mi for the upper byte, and to Ni for the lower byte. When operating in this mode, make sure ALUMODO = ALUMOD1, ALUEXT flags satl = satO and fix1 = fixO, and SHIFTO = SHIFTl. Note: If cpO in ALUMODO is 1, the operation result is not routed through the right bit shifter (SHIFT#O), and the data chosen by large/small comparison (i.e., when PTSEL-M bit 7: Mm = 0) is output to Mi (upper byte). If cpl in ALUMOD1 is 1, the operation result is not routed through the right bit shifter (SHIFT#l), and the data chosen by large/small comparison (i.e., when PTSEL-N bit 7: Nm = 0) is output to Ni (lower byte). M-49 5.8 Right Bit Shifter Shift-Setting Registers These registers set the amount of shift for the two right bit shifters (9 bits each). SHIFTO SHIFT#O shift-setting register This register specifies how much the values in ALU#O (including the carry output in MSB) are shifted to the right. The lower byte of the operation result is output to the Mi input port (when PTSEL-M bit 7: Mm = 0). ,...b_i_t_7...-_-.-_-..._--._ _.--_.....-_-.-b_it_0..., Reg. name 0 0 0 SHIFTO I I Address ASh SHIFTl SHIFT#1 shift-setting register This register specifies how much the values in ALU#1 (including the carry output in MSB) are shifted to the right. The lower byte of the operation result is output to the Ni input port (when PTSEL-N bit 7: Nm = 0). bit 7 bit 4 bit 0 Reg. name 1"--0--r"1-O-'--O~--r----'--.--..----. SHIFTl 0: Note: Address A6h Do not use this bit. Leave it set to O. If hd in the ALUEXT register is set to 1 (16-bit operation), the two bit shifts (9 bits each) can be connected together to function as a 17-bit shifter (including the carry output in ALU's 16-bit operations). In this case, make sure the registers are set so SHIFTO = SHIFTl. Also, when processing is completed (if PTEL-M, N bit 7: Mm = Nm = 0), the upper byte of the result is output to Mi and the lower byte is output to Ni. Of the bits 0-16, the MSB in bit 16 is ignored. M-SO 5.9 Mode Register Set REGVDIS Register Data Disable bit 7 o I 0 rgd: o o o o o bit 0 Reg. name Address I rgd I REGVDIS FDh Register data disable flag This flag disables the data written to the register as it is written or when VS* is asserted. Enable the data written to the register. rgd = 0: Enables the data written to the register as it is written or when VS* is asserted. Use the SMOD register vs flag to specify whether data is enabled when written to the register, or when VS* is asserted. rgd = 1: Disables the data written to the register The data written to the register is disabled until this flag is cleared to o. Do not use this bit. Leave it set to 0: o. Register configuration Read DB Register Write DB (data bus) CS* WR* First stage Second stage Q latch ----l,..--lD G Qf----1f----'l. To internal control circuit latch G D ADn vs flag VS* pulse The VS* pulse is a negative signal pulse. When a low VS* pulse occurs following a low VSEN* signal, one pulse is output at the next rising edge of ICLK. Note: Note: The SMOD register vs flag and this rgd flag are enabled once the register is written to. For a read from the register, the data in the first-stage latch is read. M-Sl SMOD Sub-mode register bit 7 bit 0 1'--0--'-1-O-'--O---'-O---'-O---'-o-'-l-w-rf""l-v--'sI vs: Address FEh Register write enable VS* sync flag This vs flag is set only when the rgd flag = O. This flag specifies the timing priority and determines whether the value written to the register is enabled when written to the register, or when the next VS* is asserted. vs = 0: Field asynchronous mode. Values entered are enabled when written to the register. vs wrf: Reg. name SMOD = 1: Field synchronous mode. Values entered are enabled when VS* is asserted immediately after the field in which the value is located is written to the register (i.e., when the next field begins). Register data enable/disable monitor flag (read-only) The IP90C55's internal registers are constructed with dual latches. When any register is written to (i.e., CS* and WR* are pulsed low), the data on DB is latched in the first-stage latch. The wrf flag is then set to 1, and is cleared when the gate to the second-stage latch is opened. The gate to the second-stage latch opens if VS* is pulsed low when rgd = 0 and vs = 1, or if rgd = 0 and vs = O. Clearing has priority so that the wrf flag can be cleared even during write operations. The written data is valid. wrf = OJ Writing in progress. wrf = 1: M-52 MMOD Main mode register bit 7 bit 0 r-o~l-o-'--o-r-o-'-O~-O-'-f-g-r1-r~ 5.10 Reg. name MMOD Address FFh r: Software reset bit r = 0: Cancels a software reset. Resets remain canceled. When 1 is written to this bit, all registers are reset to 0 r = 1: within three clock cycles beginning with the next clock cycle. At the same time, this bit is also reset to O. fg: Field identifying signal latch timing fg = 0: The field identifying signal (FLDI) is always referenced in the valid field. fg = 1: The field identifying signal (FLDI) is latched at the beginning of each field. (The FLDI level detected at the rising edge of ICLK immediately after VS* is driven low and latched.) 0: Do not use this bit. Leave it set to O. Device Test Register TESTM This register is used to test the internal logic of the device before it is shipped from the factory. Do not use this register. The chip is placed in test mode when this register is set to 1. When in test mode, the IP90C55 may not operate normally. M-53 Section 6: Electrical Characteristics 6.1 Absolute Maximum Ratings Parameter Symbol Rating Unit Vdd -0.3 to 6.5 V Input voltage Vi -0.3 to Vdd + 0.3 V Input current Ii ±10 rnA Output current 10 10 rnA Topt o to 70 'C Tstg -10 to 80 'C Supply voltage Operating temperature Storage temperature 6.2 Recommended Operating Conditions Parameter 6.3 Symbol Supply voltage Vdd HIGH level input voltage Vih Conditions Min. Typ. Max. Unit 4.75 5.0 5.25 V 2.2 Vdd V LOW level input voltage Vil Normal input 0 - 0.8 V Input rise time Tri TTL level 0 - 100 ns Input fall time Tfi Normal input 0 - 100 ns Input rise time Tri Schmitt trigger input 0 - 1000 ns Input fall time Tfi Note 1 0 - 1000 ns Min. Typ. Max. Unit - 10 25 pF 10 25 pF TTL level Input/Output Pin Capacitance Conditions Parameter Symbol Input pin Cin f=lMHz Output pin Cout f=lMHz M-54 6.4 DC Characteristics Parameter Symbol Conditions Min. Typ. Max. Unit Static current consumption (Note 1) Il Vi = Vdd or GND Off-state output leakage current (ports A-L) loz Vi = Vdd or GND Output shorting current (Note 2) (all output and input/output pins) los Vo = GND -250 Normal input pins (Except RST* and ports A to L) Iil Vi = GND -10 10 ~ Input/ output and inputs with pull-up resistors (RST* and ports A to L) lipl Vi = GND -10 -200 ~ HIGH level input leakage current (all input, all input/output pins) Iih Vi = Vdd -10 10 ~ LOW level output voltage Voll 101 0.4 V HIGH level output voltage (DBO-7) Vohl LOW level output voltage Vo12 HIGH level output voltage (output and input/ output pins except DBO-7) Voh2 Schmitt hysteresis voltage Vsch -10 200 ~ -200 ~ rnA LOW level input leakage current Note 1: Note 2: = 8 rnA loh = -8 rnA 101 = 8 rnA loh = -8 rnA 2.4 V 0.4 2.4 V V 0.5 V This value does not include static current consumption drawn in pull-up and pull-down resistors. Output shorting current is for shorting of less than 1 second, in only one pin on the device. M-55 6.5 AC Characteristics a) Data timing at the beginning of a frame : tcph: : tcpJ : I---- tcyc ~!------! ' ! - 'i IeLK Image data inp_ut_ _ _ _-+_____-f-_ _----.., i PxO to Px7 (x: A to L) i ~tves -I" i--+~ Unknown Value 1 i i i i tveh , -! --,- _-_-_-_-_-_-_-_-_-_-_ \>----i:-.......;!'--/~-=-:+-:- YSEN* 1 -_+-1-- _-_-_-_-_-_-_-_-_ Note 1 -jtvhf:..-tvs~ : , YS* I' \ i /Note2-----------;--------i : !__ ths~ \ HS* : thh :; , : I', :Note 2 tfih : :--tfis~ ______~X FLDI X~ Note 3 AOIn* ________~-----i i" (VENn* selected) (n: 0 to 7) 1 1 HENn* I" (n : 0 to 3) ! Note 1: Note 2: Note 3: Note 4: taodHL: -! :\ Note4 thedHL' \ Note 4 VS* is enabled when a low VSEN* is detected at the rise of ICLK immediately preceding the cycle that follows the low VS*. VSEN* allows the IP90C55 to be easily synchronized with other image processing LSIs or programmable controllers. If the IP90C55 need not be synchronized with other LSls (i.e., in normal operation), VSEN* must be held low. VS* and HS* need not always be pulses; they can be level-sensitive inputs, as shown above by the broken lines. In this case, however, they must be held high for at least two clock cycles before they can be driven low again. The FLDI signal must be held low or high from the time VS* is asserted until the AOI is finished. However, this restriction applies when the MMOD register'S fg = o. If fg = 1, the input level on the FLDI pin is latched at the rising edge of ICLK immediately after VS* is driven low, and is retained until VS* is driven low next time. This applies when bit-n in registers HZSTART, VOZSTART, and VEZSTART are set to 1 when specifying an AOI. M-56 Units: ns Pin load capacitance 30 pF 60 pF Symbol Min. Typ. Max. Min. Typ. Max. ICLK period tcyc 25.0 25.0 - - HIGH level period of ICLK tcph 10.0 - - - 10.0 - - Low level period of ICLK tcpl 10.0 - - 10.0 - - Ports A to L data setup time tis 5.0 - - 5.0 - - Ports A to L data hold time tih 2.0 - - 2.0 - - VSEN* setup time tves 9.0 - - 9.0 - - - Parameter tveh 2.0 - 2.0 - - VS* setup time tvs 9.0 - - 9.0 - - VS* hold time tvh 2.0 - - 2.0 - - HS* setup time ths 9.0 - - 9.0 - - HS* hold time thh 2.0 - - 2.0 - - FLDI setup time tfis 10.5 - - 10.5 - - VSEN* hold time tfih 2.0 - 2.0 - AOIn* (n = 0 to 7) delay time taodHL 3.0 - 16.0 4.0 HENn* (n = 0 to 3) delay time thedHL 3.0 - 16.0 4.0 - FLDI hold time M-57 - 20.0 20.0 ~ n-I n+1 n n+2 n+3 n+4 n+6 n+5 n+7 IC\..K ~ 5' '1j a ......... !a HS' Image data input PAO--PA7 g'5- Unknown value itoo Image data output Unknown value PBO--PB7 Image ~ ~~fti ----- ()q Unknown value et> i Unknown value $l) X PC(O.O) Yi!J., PC(~. I) Yi!J., I PC(!}.2) r- - - - - - - - - - - - i i image dt~tb: Yi!J., PC(O. 3) X,-__u-+~_no_w_n_v_a1_u_e_-+!_ _ _ _ _ _ _ _ _ __ I I 3 clock cycles --- - -------- ------- --- --- ---., I (Note 7) I(Note 2) (Note 6)1 Unknown value AOin' (ACf* select) (n: 0--7) I ~ PD(O.O) i nIi (Note 3) thedLH I ~HL ~ !'~i---------. • • (Note3) -~---------r-! ~ IthedHL AOIn* (VEN' select) (n: 0--3) iX '! thedHL F\1 HENn* (n: 0--3) § thedLH (Note 4) . , ,------------------------------ -------------------------------------~ (Note 4) I \J Ii i I :1 i Note I: PA(m. n) = PB(m,n). NOlO S: Note 2: PD(m, n) =F [pA(m. n) PC(m, n)]. where FO represents nny ALU calculation fuoctioo. The above timing chart is for the following data path setting: PA -> Ai (internal port) -> Bi (internal port) -> PB Note6: Note 3: To make the horizontal effective area setting. set HZSTART register bit-n = 1 For outpu.t le;vel setting. lIENDn register =0003h. PA -> Ai (intemnl port) -> Bi (intemal port) ->IALUIIO 1_> Mi (intemaJ port) -> Do (internal port) -> PD PA -> Ai (internal port) -> Bi (internal port)-> Note 7: NOlO 4: 11)e dotted line represents first-line Of last-line timing. The use of the ALU function creates a delay of three clock cycles relative to normal input/output timings. g. S- et> Units: ns Pin load capacitance 30 pF 60 pF Symbol Min. Ports A to L data setup time tis 5.0 5.0 Ports A to L data hold time tih 2.0 2.0 Ports A to L delay time tod 3.0 17.0 4.0 20.0 taodHL toadLH 3.0 3.0 16.0 16.0 4.0 4.0 20.0 20.0 thedHL thedLH 3.0 3.0 16.0 16.0 4.0 4.0 20.0 20.0 Parameter AOIn* (n HENn* (n = 0 to 7) delay time = 0 to 3) delay time M-59 Typ. Max. Min. Typ. Max. c) Image data output control-related timing Image data output enable ICLK Image data output PxO-Px7 (x: A toLl :--: :~ , , -----j(, PORTX+:,,n) X:, - - - HiZ -t-' OEx' , toez' , tod : : toed : :~ ' , , PORTx(m,n+i) XPORTx\m,n+2f-- HiZ- \~--------'/ (x: A toLl Port input/ output flag output ICLK VSEN* Vs* 1 ~~ Ill! ~h I \ (diLH DIRx (x:AtoH) 00 .. : I tdiHL F~~ . ' .. ~tel Note 2 Note 1: Note 2: This applies when the SMOD register vs flag (bit 0) is set to 1. (The signal becomes valid when VS' is detected low by the rising edge of ICLK immediately after the field in which the value is located is written to the register.) Ports PI to PL do not have DIR pins. Units: ns Parameter Delay time from fall of OEx' (x = A to L) to port x enabled Delay time from rise of OEx' (x = A to L) to port x placed in Hi-Z state DIRx (x = A to H) delay time Note: Pin load capacitance 30pF 60pF Max. Min. Typ. Typ. Max, Symbol Min. toed 1.0 13.0 2.0 15.0 toez 1.0 14.0 2.0 15.0 tdiLH tdiHL 3.0 3.0 1 cycle Note 3.0 3.0 1 cycle Note Synchronized with ICLK to avoid signal collisions. M-60 d) CPU interface-related timing Write Cycle 1-0..1 - - - - tcws 1 ! tcwh : ......H~~I ----I~~I ~ CS* r- i twrl 0"",000 ~ 1 AD(m) 1 k--- tdbs DBO-DBIS RD* ~_u_~_no_w_n_-.J~ ~~~--I~ ~I \ !f' 1 ~ taws ------=i! ADO-AD7 \ 1 - - - - twrh 1........ ~Ui: \1 WR* t~----~ ~tawh i ~~~~u_~_n_ow_n~~~X , 1 I AD(n) ~I .... ~I tdbh DB(m) ! :X~~u_~_n_o_w_n_~~X DB(n) ~Notel Units: ns Pin load capacitance 30 pF Parameter 60 pF Symbol Min. CS* setup time tcws 40.0 CS* hold time tcwh 4.0 4.0 Low pulse duration of WR* twrl 40.0 40.0 High pulse duration of WR* twrh 60.0 60.0 ADO-AD7 set up time taws 40.0 40.0 ADO-AD7 hold time tawh 4.0 4.0 DBO-DB7 setup time tdbs 40.0 40.0 DBO-DB7 hold time tdbh 4.0 4.0 M-61 Typ. Max. Min. 40.0 Typ. Max. Read Cycle cs· ----rI ' tCSd I I I ! I.I ' , tard~ ADO-AD7 Unknown ~ I ~D(m~ ! trdd i ~ «<1 DBO-DBI5 WR* Note 1: ~Notel \ tcsz I ! \J RD" 1! i -1 ~tard-! ~ I DB(m) r \ I i I I i i i Unknown I I I I'~, i-- trdz X AD(n) ~' ~ i I When the WR* pin is low, hold the RD* pin high to ensure that both pins are never driven low simultaneously. Similarly, when the RD* pin is low, make sure the WR* pin is high. Units: ns Pin load capacitance 30 pF Parameter Symbol Min. Delay time from valid ADO-AD7 until DBO-DB7 enabled tard Delay time until DBO-DB7 enable (relative to fall of CS*) 60 pF Max. Min. 2.0 35.0 2.0 35.0 tcsd 2.0 35.0 2.0 35.0 Delay time until DBO-DB7 enable (relative to fall of RD*) trdd 2.0 35.0 2.0 35.0 Delay time until DBO-DB7 placed in Hi-Z state (relative to rise of CS*) tcsz 2.0 20.00 2.0 2.0 Delay time until DBO-DB7 placed in Hi-Z state (relative to rise of RD*) trdz 2.0 20.00 2.0 2.0 M-62 Typ. Typ. Max. e) Reset-related timing ICLK 1 - - - - ' - - - - - - trsw - - ' - - - - - - - - - ' - - - - - 1 RST* Note: The reset signal must be held low at least three clock cycles. Units: clock cycles Pin load capacitance 30 pF Parameter Low pulse duration of RST* Symbol Min. trsw 3.0 M-63 Typ. 60 pF Max. Min. 3.0 Typ. Max. Section 7: Sample Applications and Connection Configurations 7.1 Example of Frame-to-Frame Calculation Processing (differential shading correction, binary conversion) ~ 1...(1 cameral I IAm ~ Frame memory PA Selector Matrix PB cony. : I AI Frame memoryBI Reference image (G ood product, picture for sh ading correction) I PC PD ....... ... Ai ....... Bi Jo Ci Ko Di Lo .... ... ...... Ico:~tant ~ Constant register (Binary quantization threshold value) ...... .... PJ Frame memoryC Differential image PK Pi ...... Mo No .... Mi 00 ~ Ni Po ~ M-64 PL ALU Subtraction processing and shifting 8 bits to the right (Binary-quantized data) Frame memoryD Binary-quan!'lzed " image D/A conv. #0 Subtraction processing #1 ...... ........ ~ Bi --.00 1. ALU#l performs image differentiation between the camera image and reference image A (good image) or B (image for shading correction). 2. Results are transmitted from Ni to Jo and stored as a differential image. 3. ALU#O then subtracts the binary threshold value from constant register CONST#l (reference value for binary conversion) from this differential image, and then converts the results-including the carry bit-to binary format using an 8-bit right shift. 4. The binary data is sent from Ko and stored in frame memory D as a binary image. At the same time, the image is output from Lo in analog form. '} !ALU#l! --. Ni Ci --. Po Di ~ Ni --. Jo Ai --. MO} !ALU#O! --. Mi Pi --. No Mi --. Ko Mi--. Lo M-65 7.2 Switching Image Data Streams Between Image Processing Functional Blocks NDconv. I I PL PK PB PC ~ I PJ PI IMSC:lmage Data Stream Controller PA ~ PD PE PL PH PH PG PG PF PK PJ PI IMSC:lmage Data Stream Controller PA PB PC PD PE PF I LABop Labeling processing AI EFMC hst Frame memory controller 1 Histogram processing I proJ RKFil templa Projection processing Rank filter Template matching processing A~ ~ ,, , II rmermol ,j A , If , If A~ ... ~ If H CPU BUS M-66 .. 7.3 Typical Configuration of Image Network The following shows an example of a flexible network configuration that connects image-processing blocks using multiple IP90C55s. Each image-processing module is constructed with IMSC chips, which are mounted in ring form on each board and in bus form between boards. IDl IDO Local Image Data Bus HIST Histogram processing proJ templa 1D4 Common Image Data Bus IMSCI Gray-level projection processing IMSC Template matching processing IMSC RKFil IDS 1D3 1D2 IMSC Median filter Local Image Data Bus Sketch Average value reduction/simple expansion processing EFMC IMSC IMSC Frame memory LABop IMSCI Labeling processing IMSC ~ Expansion ports M-67 Appendix Differences from the IP90C51 (IMBC) • The IP90C51 (IMBC) controls image data for a single image-processing module or chip. IMBC Input HEN', VEN', ACT' Image processing LSI AOlx 1 Comparator Camera x2 Image processing unit ddress eneration Frame memory Image processing module The IP90C51 (lMBC) controls image data (by clipping, binary-quantizing, and generating addresses) for one image processing unit, while at the same time generating frame memory addresses. • The IP90C55 (IMSC) dynamically controls (i.e., modifies) the paths of image data flows for multiple image-processing modules or chips. Gray-level histogram Frame memory The IP90C55 (IMSC) performs frame-to-frame arithmetic/logic operations between image processing units, between image processing functional modules, or between frame memories using its internal ALU units. M-68 SIDIP Image Processing Modules IP90MD08 Template Matching Module Product Manual Ver. E 1.1 • Sumitomo Metal Industries, Ltd. SIDIP Two-Dimensional Grayscale Template Matching Module IP90MD08 APPLICATIONS FEATURES AND FUNCTIONS • • • • • • • • • • • Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Industries Based on the IP90C08 LSI chip; provides two-dimensional grayscale (8-bit) template matching, including difference, absolute value, and summation processing using local image areas and templates Outputs matched filter results (sum-ofdifferences values) Stores up to four sets of coordinates in order of best match Maximum template size of 16 x 7 pixels (also handles one-dimensional templates up to 112 x 1 pixels) Two sets of template registers with external SWitching capability for continuous processing Individual enable/disable settings for each pixel in the template Input: 8-bit grayscale image Output: 16/8-bit matched filter output Maximum operating frequency of 25 MHz (image input rate of 4 ns per pixel) Maximum processing area of 4095 pixels by 4095 lines • Input image can be converted to binary format • Any rectangular area from the input image can be selected for template matching 5120-pixel x 8-bit x 6-line memory Module ID can be read out Operates on a single 5V power source All terminal signal levels are TTL level Module size of 48.8 x 127.0 mm (SIDIP single-width size) Control software reference source code list (C language) included • • • • • • • Option boards for general-purpose image analysis devices • Built-in image processing devices for factory automation (FA) and office automation (OA) equipment Built-in security devices Evaluating IP90C08 (templa) and IP90C51 (IMBC) chips • • PRODUCT DESCRIPTION The core of the IP90MD08 module is the Sumitomo Metal Industries IP90C08 twodimensional grayscale template matching LSI chip. The module also contains the peripheral circuitry necessary for interfacing with the templa chip. The IP90MD08's bus configuration is compatible with the SIDIP standard proposed by Sumitomo Metal Industries, and also with other boards and bus interfaces in the Sumitomo image processing module series. The IP90MD08 module performs twodimensional grayscale template matching in exactly the same way as the IP90C08 chip. (For further information on this processing, see" Algorithms," below.) The IP90MD08 performs template matching processing on the pixels of binary or grayscale (8-bit) raster images. These images are input along with a pixel clock synchronized with the image pixels, and the horizontal and vertical synchronization signals of the image. The module outputs the results as matched filter (sum-of-differences) data over a 16-bit bus line, with the same pixel clock and horizontal and vertical synchronization signals as the input signal. (For further description of input and output images, see "Structure and Operation," below.) In addition, the IP90MD08 can store the four best-matching sets of coordinates, in order of closeness of fit. N-1 ALGORITHMS The IP90MD08 stores template data in two sets of template registers. While template matching is being applied from one register, the other register can receive the next set of template data, thus enabling processing to continue without interruption. The IP90MD08 can handle template data up to 16 x 7 pixels in size, and can mask any pixels in the template to exclude them from processing. This section describes the template matching algorithms used by the IP90MD08 module's IP90C08 chip. Template matching is the process of searching among raster scan input image areas for the areas that most closely match the pixel values stored in the IP90C08's template registers. The IP90C08 does this by determining pixel-to-pixel matching for binary images, and expands this method to provide template matching of grayscale image data. The largest allowable input image is 4095 pixels by 4095 lines. The maximum pixel clock frequency is 25 MHz. The IP90MD08 module can accommodate binary template matching by using a built-in comparator to convert incoming grayscale images to binary format. The host computer controls the threshold value for binary conversion. The process involves calculating the sum of the absolute values of pixel-by-pixel differences between the incoming grayscale image and the template stored in the chip. This sum of differences indicates how closely the input image matches the template. Matched filter output is in 16-bit format. However, the output can also be separated into its lower 8 bits and upper 8 bits. When only the lower 8 bits are output, the module can clip output values that exceed 8 bits (overflow values) to a value of 255 (FFh). Figure 1 illustrates the processing of a local area of M x N pixels, having its lower right comer at (a, b), and a template of the same size. A pixel at (m, n) of the extracted local area is compared to (that is, subtracted from) the value of the pixel at (m, n) in the template. The absolute value of the difference indicates the closeness of the match. The IP90MD08 has an individual module ID number, which the host computer can use to verify which modules are in which slots in the base board. This provides an efficient way to configure the system automatically. The IP90MD08 module's board is the SIDIP single-width size (48.8 x 127.0 mm). f The IP90MD08 provides an easy way to perform two-dimensional grayscale template matching processing. It replaces previous lowspeed software systems and bulky hardware with a space-saving, high-speed hardware module. A real-time grayscale template matching system can be configured easily and simply by installing the IP90MD08 in a SIDIP-compatible base board. Such a system can be used in a wide variety of applications, including those requiring position detection, image alignment, or vector pursuit functions, as well as for image searching in databases and electronic filing systems. I· Input image, K x L pixels K--~·I Raster scan input I • L l~ Template data r--n t ~1 ~M~ Figure 1: Algorithm Therefore, the degree of mismatch between the local image area with its lower right comer at (a, b) and the template can be expressed by this equation: Other uses include general purpose image processing equipment, particularly built-in processing equipment in factory automation (FA) applications requiring high-speed processing, as well as office automation (OA) equipment, and security equipment. N-IM-l S(a,b) = I,I,II(a+m-M,b+n-N)-T(m,n)1 n=O 111=0 N-2 where: • (a, b) is the lower right comer of the local area within the input image. • S(a, b) is the sum of differences with relation to the local area of M x N pixels having its lower right comer at (a, b). • I(a + m - M, b + n - N) is the pixel grayscale value of (m, n) within the local area of the input data. • T(m, n) is the template data for the corresponding point (m, n) within the template. Synchronized by vertical Rast~e~rs~~~~~~~~s~y~nC~br~o~m~' I Total screen area Synchronized by horizontal syncbronization signal The IP90COS calculates the sum of differences with respect to the input image, and outputs the result. The lower the sum of differences is, the less difference there is between the template and the image area of the input data, and so the closer the fit. The output value can be further augmented by supplementary functions, including addition of bias values, or division by means of a shift operation. This enables the IP90COS to function as a matched filter or average smoothing filter, and to create an output image composed of closeness-of-fit values. Figure 2: Definition of Image Area The IP90MDOS can process only the area defined by the vertical and horizontal synchronization signals, represented by the shaded rectangle in Figure 2. The host computer controls the size and pOSition of this area. In addition, areas outside this designated area can be considered background and processed as gradient value 0 (binary value [0]). In addition, the IP90COS can determine which sets of coordinates have the lowest sum of differences (corresponding to the positions with the best fit), and save the four lowest in its matching coordinates register. The chip can also rank these coordinates in order of closeness-of-fit. The output image is a matched filter (sum-ofdifferences) image, and, like the input image, is a raster image. The output also has the same pixel clock and horizontal and vertical synchronization signals as the input image. Figure 3 shows an example of an actual application. STRUCTURE AND OPERATION Pixel clock ~ Horizontal synchronization signal (1) Input/Output Images / =~~~;~~/-,,¢ V"",. ,,","0,,","00 "",01 The IP90MDOS module can handle binarycoded or S-bit grayscale raster images (noninterleaved). The IP90MDOS requires as a minimum a system that includes a pixel clock synchronized with the pixels of the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image. These signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. Frame memory 1 Source image Image data bus IP90MD08 Image data bus Frame memory 2 Figure 3: Sample Application N-3 Filtered image (2) Image Input Block (IP90C51) (3) IH Line Delay Figure 4 shows a block diagram of the IP90MD08 module. To perform two-dimensional grayscale template matching processing, the IP90MD08 requires seven successive horizontal lines of horizontal image data. The incoming image data enters one line at a time, so the module obtains seven lines by applying six successive line delays of one horizontal (lH) line each. Inverted image data enters through the input image bus, located at INOO*-IN07* in Figure 4. This input data is inverted again in the image input block. The input block also designates the area of the input image to be processed as described earlier, and, if binary processing is to be used, converts 8-bit grayscale data to binary format. INOO* -D7* ICLKI ICLK2 -+ HS* -+ VS* -+ SRST* -+ Vcc -+ GND -+ This is the block in which the IP90C08 performs the necessary functions for twodimensional grayscale template matching . .... i ... -+ (4) Core Block (IP90C08) ~ --,. IP90C51 image data bus controller (IMBC) .~ ~ 1H line ~~ delay ~~ x6 IP90C08 templa ~ • Overflow clipping ~ .. ~ OUTOO* -07* -r. OUT08* -15* • . ~ I+- IOEH* . ... ~ Ir ID ROM Host computer interface .... • . , ,~ .~ .Ir 'lr" SDOO-IS GST* BHE* SAOO-IO MIR* MEN* Figure 4: Block Diagram N-4 I+- IOEL* MWR* MRD* (5) Overflow Clipping Block (7) Host Computer Interface Block The results of sum-of-differences processing are output to the image bus with a maximum width of 16 bits (the IP90C08 can also be set for 8-bit operation). The lower 8-bits and upper 8-bits of the output have three possible states, enabling independent control of the connection. The output is in inverted logic format. The host interface block contains the interface through which the host computer controls the IP90MD08. The data bus (SDOO-15) is 16 bits wide, and the address bus (SAOO-10) is 11 bits wide. Write and read operations are controlled by the MWR* and MRD* signals, respectively. Byte access or cord access are enabled by a combination of the address AO setting and the BHE* signal. Although memory space and register space are defined in all SIDIP modules, the IP90MD08 allocates all functions to register space. The IP90MD08 is also designed for either 8-bit or 16-bit data bus width. If 8-bit output is used, output values in excess of 8 bits are considered overflow and are clipped to the maximum value of 255 (FFh). This function can be turned on or off by software. (6) Timing Control Block 1) ID Number Reading The timing control block is the point of entry for the pixel clocks (ICLK1, ICLK2), horizontal synchronization signal (HS*), and vertical synchronization signal (VS*). When GST* is taken to active level, the IP90MD08's module ID number (28h) is outputted using the lower 8 bits of the data bus. When the IP90MD08 uses a pixel clock frequency higher than 20 MHz, a two-phase clock input is created using both ICLK1 and ICLK2. At frequencies of 20 MHz or lower, only ICLK1 is used. 2) System Reset When the SRST* signal is set to active level, a hardware reset is initiated. This resets all registers in the module to ~Oh. N-5 PIN ASSIGNMENTS Table 1 lists the pin assignments for the IP90MD08. Signal pins are divided between the image system (Table lA) and control system (Table IB), having three and two external connectors, respectively. All signal pin assignments conform to SIDIP standards. Connector Pin No. ICLKI CNID 12 Image clock 1 I ICLK2 HS* CNID 14 Image clock 2 I CNID 8 Horizontal synchronization signal I VS* CNID 10 Vertical synchronization signal I Signal Function I/O INOO* CNIC 2 Input image data bus (Bit 0) I INOl* CNIC 17 Input image data bus (Bit 1) IN02* CNlC 3 Input image data bus (Bit 2) I I IN03* CNIC 18 Input image data bus (Bit 3) I IN04* CNIC 4 Input image data bus (Bit 4) I INOS* CNIC 19 Input image data bus (Bit 5) I IN06* CNIC 5 Input image data bus (Bit 6) I IN07* CNIC 20 Input image data bus (Bit 7) I OUTOO* CNIC 12 Output image data bus (Bit 0) 0 OUTOl* CNIC 27 Output image data bus (Bit 1) 0 OUT02* CNIC 13 Output image data bus (Bit 2) 0 OUT03* CNIC 28 Output image data bus (Bit 3) 0 OUT04* CNIC 14 Output image data bus (Bit 4) 0 OUTOS* CNIC 29 Output image data bus (Bit 5) 0 OUT06* CNlC 15 Output image data bus (Bit 6) 0 OUT07* CNIC 30 Output image data bus (Bit 7) 0 OUT08* CNID 2 Output image data bus (Bit 8) 0 OUT09* CNID 17 Output image data bus (Bit 9) 0 OUTlO* CNID CNID 3 18 Output image data bus (Bit 10) Output image data bus (Bit 11) 0 OUTll* OUTl2* CNID 4 Output image data bus (Bit 12) 0 OUTl3* CNID 19 Output image data bus (Bit 13) 0 0 0 OUTl4* CNID 5 Output image data bus (Bit 14) OUTlS* CNID 20 Output image data bus (Bit 15) 0 IOEL* CNIE 2 Image bus output enable (lower) I IOEH* CNIE 17 Image bus output enable (higher) I Note: An asterisk (*) following a signal name indicates inverse logic. Table lA: Image System Signal Pin Assignments N-6 Signal Connector Pin No. Function I/O SDOO CNIA 3 Control data bus (Bit 0) I/O SDOI CNIA 18 Control data bus (Bit 1) I/O SD02 CNIA 4 Control data bus (Bit 2) I/O SD03 CNIA 19 Control data bus (Bit 3) I/O SD04 CNIA 5 Control data bus (Bit 4) I/O SD05 CNIA 20 Control data bus (Bit 5) I/O SD06 CNIA 6 Control data bus (Bit 6) I/O SD07 CNIA 21 Control data bus (Bit 7) I/O SD08 CNIA 7 Control data bus (Bit 8) I/O SD09 CN1A 22 Control data bus (Bit 9) I/O SOlO CNIA 8 Control data bus (Bit 10) I/O SOlI CNIA 23 Control data bus (Bit 11) I/O I/O SD12 CN1A 9 Control data bus (Bit 12) SOl3 CNIA 24 Control data bus (Bit 13) I/O SD14 CN1A 10 Control data bus (Bit 14) I/O SD15 CNIA 25 Control data bus (Bit 15) I/O SAOO CNIB 17 Control address bus (Bit 0) I SAOI CNlB 3 Control address bus (Bit 1) I SA02 CNlB 18 Control address bus (Bit 2) I SA03 CNIB 4 Control address bus (Bit 3) I SA04 CNIB 19 Control address bus (Bit 4) I SA05 CNIB 5 Control address bus (Bit 5) I SA06 CNIB 20 Control address bus (Bit 6) I SA07 CNIB 6 Control address bus (Bit 7) I SA08 CN1B 21 Control address bus (Bit 8) I SA09 CNIB 7 Control address bus (Bit 9) I SAlO MEN* CNIB 22 Control address bus (Bit 10) I CNIA 14 Module enable I BHE* CNIB 2 Control bus upper byte enable I M/R* CNlB 25 Memory /register I MRD* CNIB 27 Read signal I MWR* CNIB 12 Write signal I CST* CNIA 29 ID read signal I SRST* CNIB 28 System reset I Note: An asterisk (*) following a signal name indicates inverse logic. Table 1B: Control System Signal Pin Assignments N-7 MECHANICAL DIMENSIONS Figure 5 shows the board size and signal pin connector locations. The board size and connector positions conform to SIDIP standards. 5.08 Components mounted on component side 2.2~ Components mounted on solder side Component side o a max 4.6 max 2.2 2.2 Figure 5: Board Size and Connector Positions Notes 1: Connectors: Japan Aviation Electronics Industry, Limited IL-WX-30PB-VFS4-B (Mating connector: Japan Aviation Electronics Industry, Limited IL-WX-30SB-VF-B) 2: Connector pin number assignments: 16-30 CJ e: #1 pin mark 1~15 N-S 3: Connectors to be mounted on the soldered surface. 4: To conform to specifications for module external shape (single-width). 5: Connector position measurements are to the center of the connector. SIDIP Image Processing Modules IP90MDIO Labeling Module Product Manual Ver. E 1.3 • Sumitomo Metal Industries, Ltd. SIDIP Labeling Module IP90MD10 FEATURES AND FUNCTIONS APPLICATIONS High-speed labeling module based on the IP90CI0 labeling processor LSI chip • General image-processing devices Built-in image-processing devices for Factory Automation (FA) equipment Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Metal Industries • High-speed 25-MHz pixel clock • Maximum processing area of 1024 x 1024 pixels • Binary processing capacity with on-board input signal • Same labeling processor functions as the IP90CI0 chip: • PRODUCT DESCRIPTION The IP90MDlO labeling processing module includes the IP90CI0 labeling accelerator LSI (large-scale integration) chip, one of Sumitomo Industries' image-processing LSI series. The module also includes peripheral circuitry on a proprietary circuit board designed as a labeling processor module. up to 4094 temporary labels The module's bus architecture is compatible with the SIDIP standard interface for digital image processing proposed by Sumitomo Metal Industries. The architecture also includes bus interfaces compatible with other boards in the Sumitomo Metal Industries image processing module series. up to 4094 primary labels up to 4095 linkage information entries • Processes one screen within the time span of 2 to 3 frames • 4-link and 8-link processing • Input image data width of 8-bits, with on-board binary conversion • Output image data width of up to 12 bits (can be divided into lower 8-bit and upper 4-bit signals) • Label tables can be loaded from the host computer • Module ID can be read out • Operates on a single 5V power source • All terminal signal levels are TTL level • Output compensation shift of 0-8 bits • Module size of 98.6x 127.0 mm (SIDIP double-wide size) Built-in image-processing devices for Office Automation (OA) equipment The IP90MDI0's labeling processor functions are identical to those of the IP90CI0 chip. Primary labeling, label linkage processing, and secondary labeling are automatically executed in sequence and synchronized with the input image frames. (For further information about labeling, processing algorithms, and other details, refer to the technical documentation for the IP90CI0 chip.) The IP90MDlO module requires as input the pixels of a binary or 8-bit grayscale raster input image, together with the pixel clock and the horizontal and vertical synchronization signals synchronized with those pixels. The input image is converted into a labeled image of up to 12 bits, and output with the same pixel clock and horizontal and vertical synchronization signals as the input image. (For details of input and output images, see "Input/Output Images.") 0-1 The core component of the IP90MDlO module is the IP90C10 LSI chip. The basic specifications for the module's labeling processor functions are the same as those of the chip. The maximum input image that can be processed is 1024 pixels horizontally by 1024 pixels vertically, and the maximum clock frequency is 25 MHz. The IP90MDlO module contains a comparator for binary conversion of grayscale input images, allowing the host computer to easily control the threshold value used for binary conversion. The module can handle a maximum output of 4094 labels with widths of up to 12 bits. This output can be divided into 8bit lower and 4-bit upper values. The IP90MD10 module also features a useraccessible memory for storing label tables, which allows label values to be assigned as needed. STRUCTURE AND OPERATION (1) Input/Output Images The IP90MD10 module can handle either binary-coded or 8-bit grayscale raster images (non-interleaved). The minimum system required for the IP90MDlO to perform label processing includes a pixel clock synchronized with the pixels that make up the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image (see Figure 1). These signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. Synchronized by vertical synchronization signal The IP90MDlO module has its own module ID, which can be read by the host computer for easier configuration of systems. This ID can be used to determine whether the IP90MD10 is present, or for automatic system configuration. The IP90MD10 module replaces previous lowspeed software processing systems and bulky hardware, providing a space-saving, highspeed hardware device for easy histogram and projection processing. The module is designed for use in general-purpose imageprocessing devices, and particularly for builtin image-processing devices in factory automation applications that require high processing speeds. It is also ideally suited for built-in systems in office automation equipment such as copiers and fax machines. Synchronized by horizontal synchronization signal Figure 1. Definition of Image Area for Processing The IP90MDlO module can process only the area defined by the vertical and horizontal synchronization signals, represented by the shaded area in Figure 1. The size and position of this area can be controlled from the host computer. In addition, areas outside this designated area can be considered background, and processed with a gradient value of 0 (or [0] in a binary image). The output image is a labeled raster image, as is the input image. The output image has same pixel clock, horizontal synchronization Signal, and vertical synchronization signal as the input image. However, an internal delay factor delays the output image by 8 pixels relative to the input image. 0-2 Inverted image data is input at the input image bus (located at INOO-IN07). The input block inverts this data again, defines the area of the image to be processed (as shown in Figure 1), and performs binary conversion of 8bit grayscale data. If binary data is input directly, the values used are OOh for [0] and FFh for [1]. Figure 2 shows an example of an actual application. Pixel clock ~Horizontal synch. signal *vertical synch. signal 12 (3) 1H Line Delay Frame memory 2 The IP90MD10 module requires two consecutive lines of horizontal image data for labeling processing. Because incoming image data enters only in ranks of one line at a time, the module internally applies a line delay of one horizontal line. Image Image '------' data '------' data Source image bus bus Labeled image Figure 2. Sample Application (2) Image Input Block (4) Labeling Chip Block Figure 3 shows a block diagram of the IP90MD10 module. Labeling takes place in this block. The IP90C10 chip performs the necessary functions for labeling, and also controls peripheral circuits. Vee GND ----- Frame memory H r o7' '2 IP90Cl0 labeling processor LSI chip lHline delay Image input processing INOO ,- ,-- 12. "E 0 <.> r-. 24 ; ~ ICLK2 - f+ HS 0 ~ 8 16 Timing control *- ~ Label tables VS * - ~ I IDROM I II t Note: An asterisk (*) following a signal name indicates inverse logic. c= Host computer intertace t t sl15 SAOO- M/R* MRD* 12 GST* MEN* BHE* Figure 3. Block Diagram 0-3 UTOO*- UT08*'"~ .§ ~~ l ' ~ ICLK1 - ~g 7* '5 c. '5 MWR* ~ IOEL* ~ IOEH* SRS T' INT At frequencies higher than 20 MHz, a twophase clock input is created using both pixel clocks ICLK1 and ICLK2. When the pixel clock frequency is 20 MHz or lower, only ICLK1 is used. (5) Label Table Block This block holds data linked with the temporary labels assigned in the primary labeling process. The block also contains the tables used to convert the temporary labels created in the label linkage process into final labels. These tables are used in the secondary labeling process, in which the temporary labeled image is converted to a final labeled image. Label tables are controlled by the IP90C10 chip. (9) Host Interface Block The host interface block contains the interface for the computer that controls the IP90MD10 module. The data bus (SDOO-15) is 16 bits wide, and the address bus (SAOO-12) is 13 bits wide. The MWR* and the MRD* signals control write and read operations, respectively. Byte access and word access are obtained by combining address AO and the *BHE signal. The M/R* signal controls memory/register access. (6) Frame Memory Block This block contains the temporary labeled image from the primary labeling process. The temporary labeled image is then read out for secondary labeling. This activity is controlled by the IP90ClO chip. The size of frame memory is 1024 horizontal pixels by 1024 vertical pixels by 12-bit data width, equivalent to one frame of data. (a) ID Number Reading The GST* signal outputs the ID number of the IP90MD10 module (04h) to the data bus. (b) Interrupt Signal (7) Image Output Control Block The interrupt signal becomes active when an error occurs in labeling processing, such as an overflow in the number of temporary labels or temporary label linkages. (For further details about these errors, see the technical documentation for the IP90C10 LSI chip.) The labeled image is output to the image bus with a bit width of 12 bits (consisting of lower 8-bit and upper 4-bit signals, each in threestate output with independently controlled connection status), and with inverted signal logic. (c) System Reset (8) Timing Control Block The SRST* signal resets all registers in the module to ~Oh. The timing control block is the point of entry for the pixel clocks (ICLK1 and ICLK2), horizontal synchronization signal (HS*), and vertical synchronization signal (VS*). 0-4 PIN ASSIGNMENTS Table 1 lists the pin assignments for the IP90MD10 module. Signal pins are divided between the image system (Table 1A) and control system (Table lB), having three and two external connectors, respectively. These pin assignments conform to SIDIP standards. Signal Connector Pin No. Function ICLK1 CNID 12 Image clock 1 I ICLK2 CNID 14 Image clock 2 I HS* CNID 8 Horizontal synchronization signal I VS* CN1D 10 Vertical synchronization signal I I/O INOO* CN1C 2 Input image data bus (Bit 0) I IN01* CN1C 17 Input image data bus (Bit 1) I IN02* CNlC 3 Input image data bus (Bit 2) I IN03* CNlC 18 Input image data bus (Bit 3) I IN04* CNlC 4 Input image data bus (Bit 4) I IN05* CN1C 19 Input image data bus (Bit 5) I IN06* CNlC 5 Input image data bus (Bit 6) I IN07* CN1C 20 Input image data bus (Bit 7) I OUTOO* CNlC 12 Output image data bus (Bit 0) 0 OUT01* CNlC 27 Output image data bus (Bit 1) 0 OUT02* CN1C 13 Output image data bus (Bit 2) 0 OUT03* CN1C 28 Output image data bus (Bit 3) 0 OUT04* CNlC 14 Output image data bus (Bit 4) 0 OUT05* CNlC 29 Output image data bus (Bit 5) 0 OUT06* CNlC 15 Output image data bus (Bit 6) 0 OUT07* CN1C 30 Output image data bus (Bit 7) 0 OUT08* CNID 2 Output image data bus (Bit 8) 0 OUT09* CNID 17 Output image data bus (Bit 9) 0 OUTlO* CN1D 3 Output image data bus (Bit 10) 0 OUTll* CN1D 18 Output image data bus (Bit 11) 0 10EL* CNlE 2 Image bus output enable (lower) I 10EH* CN1E 17 Image bus output enable (upper) I Table 1A. Image System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. 0-5 Signal SOOO SOOl S002 S003 S004 S005 S006 S007 S008 S009 SOlO SOl1 S012 SOl3 SD14 SOl5 SAOO SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SAlO SA 11 SA12 MEN* BHE* M/R* MRO* MWR* INT* GST* SRST* Connector CN1A CN1A CN1A CN1A CN1A CN1A CN1A CN1A CNIA CN1A CNIA CN1A CNIA CN1A CN1A CNIA CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1B CN1A CN1B CN1B CN1B CN1B CN1A CN1A CN1B Pin No. 3 18 4 19 5 20 6 21 7 22 8 23 9 24 10 25 17 3 18 4 19 5 20 6 21 7 22 8 23 14 2 25 27 12 27 29 28 Function Control data bus (Bit 0) Control data bus (Bit 1) Control data bus (Bit 2) Control data bus (Bit 3) Control data bus (Bit 4) Control data bus (Bit 5) Control data bus (Bit 6) Control data bus (Bit 7) Control data bus (Bit 8) Control data bus (Bit 9) Control data bus (Bit 10) Control data bus (Bit 11) Control data bus (Bit 12) Control data bus (Bit 13) Control data bus (Bit 14) Control data bus (Bit 15) Control address bus (Bit 0) Control address bus (Bit 1) Control address bus (Bit 2) Control address bus (Bit 3) Control address bus (Bit 4) Control address bus (Bit 5) Control address bus (Bit 6) Control address bus (Bit 7) Control address bus (Bit 8) Control address bus (Bit 9) Control address bus (Bit 10) Control address bus (Bit 11) Control address bus (Bit 12) Module enable Control bus upper byte enable Memory / register Read signal Write signal Interrupt request signal 10 read signal System reset Table lB. Control System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. 0-6 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I I I 1 1 I I 0 I I MECHANICAL DIMENSIONS Figure 4 shows the IP90MDIO's board size and signal pin connector locations. The size and locations conform to SIDIP standards. 1----------- 98.60----------1 r-90.80 - - - - - - - - - 1 . 1 - - - - - - - 61.80--------1 1 ~.- - - - 5 2 . 8 0 - - - - - I , - - - - 41.00 -.---1 2.4 0 (2 places) 127.0 Note 1 Note 3 Note 2 Components mounted on component side Components mounted on solder side Component side max 4.6 max 2.2 ., :!2 .,'" "E Note 3 Note 1 Note 2 \ 2.4 0 .8 .,"'" IE. 1-------~76.30------~ 1---------90.80-----------1 Figure 4. Board Size and Connector Positions Notes 1: The IP90MDlO module has no connectors CN2A, CN2C, or CN2D. 2: The labeling processor board uses these two connectors (CN2B, CN2E) as dummy connectors (no electrical function) to hold the board in position. 3: The IP90MDIO module has no holes at these positions. 0-7 Additional Information 3: Connectors to be mounted on the soldered surface. 1: Connectors: Japan Aviation Electronics Industry, Limited IL-WX-30PB-VF84-B. (Mating connector: Japan Aviation Electronics Industry, Limited IL-WX-30SB-VF-B.) 2: Connector pin number assignments: 4: To conform to specifications for module external shape (double-wide). 5: Connector position measurements are to the center of the connector. 16-30 component side: L=:J .: #1 pin mark 1-15 0-8 SIDIP Image Processing Modules IP90MD15 Sketch Module Image Data Reduction by Averaging/ Simple Enlargement Module Product Manual Ver. E 1.2 • Sumitomo Metal Industries, Ltd. SIDIP Image Data Reduction by Averagingl Simple Enlargement Sketch Module IP90MD15 FEATURES AND FUNCTIONS • APPLICATIONS Exceptionally easy-to-use module based on the IP90C15 LSI chip • Built-in image-processing devices for security monitoring systems Performs simple horizontal and vertical enlargement • Dynamic image-processing devices • General image-processing devices Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Metal Industries Built-in image-processing devices for Factory Automation (FA) equipment Built-in image-processing devices for Office Automation (OA) equipment Maximum pixel clock frequency of 25 MHz • PRODUCT DESCRIPTION Maximum processing area of 1024 x 1024 pixels • Provides compression ratios of 1/2,1/4, l/S, and 1/16 • Provides enlargement ratios of 2, 4, S, and 16 • Input and output image data bus widths of S bits • Variable processing area • Variable processing frame count (maximum of 64 frames, with continuous loop processing available) • Variable interval frame count setting allows frame processing at regular intervals • Provides tiling of average-value compressed images in frame memory • Module ID can be read out The IP90MD15 module contains the Sumitomo Metal Industries IP90C15 LSI (large scale integration) chip, one of Sumitomo Industries' image-processing LSI series. The IP90MD15 also includes additional peripheral circuitry in a compact, exceptionally easy-to-use processing module. The module's bus architecture is compatible with the SIDIP standard interface for digital image processing proposed by Sumitomo Metal Industries. The architecture also includes bus interfaces compatible with other boards in Sumitomo Industries' imageprocessing module series. The IP90MD15 module processes image data in real time, synchronized with the frames of the input image. It can also initialize internal frame memory. (For information about the algorithms the IP90MD15 uses to reduce image data by averaging, see the technical documentation for the IP90C15 chip.) Operates on a single 5V power source • All terminal signal levels are TTL level • Module size of 9S.6 x 127.0 mm (SIDIP double-wide size) P-l IP90MD15 (256) @ ,-A, (256) { I IP90C15 I Compression at ratio 1/4 Tiling array Image data reduction processing unit CD CD CD ® ® CD ® ® @ ® @ @ @ @ @ ® ~ 1024 Intemal frame memory Frames before processing The above illustrates a tiling array of 16 frames after image data reduction using a compression ratio of 1/4. • Tiling array: Frames are placed in the array in order from 1 to 16 and stored in frame memory. • Tiling frame size: Equivalent to the size of one frame after image processing (dimensions in parentheses). Figure 1. Schematic Diagram: Image Data Reduction by Averaging Processing and Tiling Array The IP90MD15 module requires only input of the pixels of an 8-bit grayscale input image, together with the pixel clock and the horizontal and vertical synchronization signals synchronized with those pixels. After processing, the image is output with either the same pixel clock as the input image (in I-phase clock mode) or with different phases (in 2-phase clock mode). The output image's horizontal and vertical synchronization signals are the same as the input image's. (For details about the input image, see the description of module operation.) between each frame selected for data reduction. Continuous data reduction processing is also available. The module's internal frame memory can store up to 64 processed frames at once. The IP90MD15 can also enlarge input images horizontally and vertically (see Figure 2). (AXB) @XQ) The core component of the IP90MD15 module is the IP90C15 LSI chip, which can process images with a maximum size of 1024 pixels hOrizontally by 1024 pixels vertically, and which has a maximum clock frequency of 25 MHz. This shows a 2x2-pixel image expanded by a factor of 2. Figure 2. Schematic Diagram: Simple Enlargement The IP90MD15 module places the results of image data reduction into a tiling array in internal frame memory. This is an efficient way to simultaneously display multiple compressed images on the output monitor (see Figure 1). The module offers a variable "interval frame count" setting, which establishes a fixed number of frames The IP90MD15 module has its own module ID, which can be read by the host computer for easier configuration of systems. This ID can be used to determine whether the IP90MD15 is present, or for automatic system configuration. P-2 The IP90MD15 module replaces previous lowspeed software processing systems and bulky hardware, providing a space-saving, highspeed hardware device for easy image data reduction or enlargement. The module is designed for use in general-purpose imageprocessing devices, particularly for the high processing speeds demanded by dynamic image-processing systems, as well as for builtin image-processing devices used in FA equipment, security monitoring equipment, and OA equipment. The IP90MD15 module can process only the area defined by the vertical and horizontal synchronization signals, represented by the shaded area in Figure 1. The size and position of this area can be controlled from the host computer. Areas outside this deSignated area can be considered background, and processed with a gradient value of o. The output image is a raster image, as is the input image. The output image has same pixel clock and horizontal and vertical synchronization signals as the input image. Figure 4 shows an example of an actual application. STRUCTURE AND OPERATION (1) Input/Output Images Pixel clock dHorizontal synch. signal wVertical synch. signal The IP90MD15 module processes 8-bit grayscale raster images (non-interleaved). The minimum system required by the IP90MD15 includes a pixel clock synchronized with the pixels that make up the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image (see Figure 3). These signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. Rasters Source image Image data bus Image data bus Average-value compressed! simple expanded image Figure 4. Sample Application Synchronized by vertical synchronization signal (2) Image Input Block Figure 5 shows a block diagram of the IP90MD15 module. Inverted image data enters at the input image bus (located at INOO-IN07). The input block inverts this data again, and defines the area of the image to be processed. Total screen area Synch by horizontal synchronization signal Figure 3. Definition of Image Area for Processing P-3 Vcc GNO INOO' -07' IP90C51 processing area definition IMBCil1 Frame memory 1024 x 1024 ICLK1 ICLK2 HS' OUTOO' -07' IP90C51 sketch control IMBC#2 Timing control VS' ~----I-- SRST' ~-.--r--.---'--~--~ SOOO07 SAOO07 GST' MfR' MEN' MWR' MRO' Note: An asterisk (') following a signal name indicates inverse logic. Figure 5. Block Diagram (3) Image Data Reduction by Averaging Processor Figure 8 shows.examples of tiling arrays, and Table 1 lists image sizes used in tiling. When a processing area of 1024 x 1024 pixels is compressed to 1/4 size, the size of the image in a tiling array is 256 x 256 pixels, and a total of 16 frames of average-value compressed images can be placed in the array. The point of origin can be any point from (0, 0) to (3, 3). The core of the IP90MD15 module is Sumitomo Industries' IP90C15 LSI chip. The IP90MD15 provides a variable compression ratio of 1/2, 1/4,1/8, or 1/16, as well as variable settings for processing frame count and interval frame COtmt. The minimum image size for tiling is 64 x 64 pixels. In some cases, image data reduction by averaging can produce images that are smaller than 64 x 64 pixels (such as 32 x 32 pixels), in which case the result is placed starting in the upper left comer of a 64 x 64 pixel area for tiling, and part of the tiling area is undefined (see Figure 6). Whenever a compressed image is smaller than the assigned tiling size, the module fills the remaining area with the gradient value O. (For more information, see Table 1, the explanation of tiling in item (4), the explanation of processing modes in item (5), and Figure 7.) (4) Tiling Compressed images can be placed in a tiling array in internal frame memory (1024 x 1024 pixels). The host computer controls the point of origin and the direction (vertical or horizontal) of tiling. Processed images can also be placed in the same tiling location. P-4 o 64 0 o If the resulting image is larger than the internal frame memory, the excess portions of the image cannot be stored or displayed (see Table 1 and Figure 10). Image after reduction Undefined area (7) Image Output Control Block Data previously placed in frame memory The processed image is output to the image bus with a width of 8 bits, in three-state output with independently controlled connection status, and with inverted signal logic. 64 Figure 6. Internal Frame Memory Array When the Result of Image Data Reduction is Smaller Than 64 x 64 Pixels (8) Timing Control Block (5) Processing Modes The timing control block is the point of entry for the pixel clocks (ICLK1 and ICLK2), horizontal synchronization signal (HS*), and vertical synchronization signal (VS*). Image data reduction can be applied to a frame count of 1 to 64 frames. Also, a number of frames can be skipped between processed frames, as specified by an interval frame count of 0 to 1023 frames. At frequencies higher than 20 MHz, a twophase clock input is created using both pixel clocks ICLK1 and ICLK2. When the pixel clock frequency is 20 MHz or lower, only ICLK1 is used. The IP90MD15 can operate either in "one-time mode," in which processing stops automatically after a designated number of frames, or in "loopback mode," in which processing continues as described above until the host computer sends a stop command. The processing time required (using an interval frame count of 0 frames) is equal to the frame count plus one (see Figure 9). (9) Host Interface Block The host interface block contains the interface for the computer that controls the IP90MD15 module. The data bus (SDOO-07) and the address bus (SAOO-07) are both 8 bits wide. The MWR* and the MRD* signals control write and read operations, respectively. The M/R* signal at low level controls memory / register access. (6) Simple Enlargement Processing The IP90MD15 performs simple enlargement processing by replicating pixel data along the horizontal or vertical axis, with the number of replications corresponding to the enlargement ratio (this is the zero-order hold method). An internal delay factor of one horizontal line is applied so that a line of horizontal pixel data can be replicated next to its original position. This process begins at the upper left comer of the processing area, and operates using an enlargement factor of 2, 4, 8, or 16. If the resulting image is smaller than the module's internal frame memory, the remaining area is filled in with gradient value O. (a) ID Number Reading The GST* signal outputs the IP90MD15's 8-bit ID number (10h) to the data bus. (b) System Reset The SRST* signal resets all registers in the module to OOh. P-5 Area processed 1024 x 1024 through 513 x 513 Compression ratio 512x512 through 257 x 257 256 x 256 through 129 x 129 128 x 128 through 65 x 65 64 x 64 or less Enlargement ratio Tiled image size 512x512 256 x 256 128 x 128 64x64 256 x 256 128 x 128 64x64 64 x 64* 128 x 128 64x64 64 x 64* 64x64 64x 64* 64x 64* 1/2 1/4 1/8 1/16 1/2 1/4 1/8 1/16 1/2 1/4 1/8 1/2 1/4 1/2 x2 through x16 * See description of tiling in section (4). Table 1. Image Data Reduction by Averaging/Simple Enlargement Ratios X (x. y) v{rEJ 1024 IZZZI '-~ Assigned gradient value 0 Xln < T or Yin < T • T: Tiling size (see table 1) • n: Compression ratio 1024 Figure 7. Example of Image Data Reduction by Averaging 1024 ~ n; S • 00>3 H N;::l"1j 0<0 0 :=>::s o~ .... -~~,;"" SRST* GST* MEN* MRD* SAOOMfR* MWR* Figure 3. Block Diagram applying a line delay of one horizontal line, in two iterations. (2) Image Input Block Figure 3 shows a block diagram of the IP90MD20. (Note: an asterisk [*] following a signal name indicates inverse logic.) (4) Core Block The rank value filter LSI (IP90C20) is used in its normal role, performing the necessary functions for rank value filter processing. Inverted image data is input at the input image bus (located at INOO-IN07). At the input block this data is inverted again, the previously described designation of the processing area takes place, and, if binary processing is used, 8-bit grayscale data is converted to binary data. Binary data is converted to 8-bit logic using the values OOh for [0] and FFh for [1]. Note that, because the bus carries values that are inverted for processing, data entering the module appears in the bus as FFh for [0] and OOh for [1]. (5) Image Output Control Block Following rank value filter processing, the image is output to the image bus with a width of 8 bits, and with signal logic still inverted. The output signal is in three states, enabling control over the connection. (6) Timing Control Block This block is the point of entry for the pixel clocks (ICLKl, ICLK2), horizontal synchronization signal (HS*), and vertical synchronization signal (VS*). (3) IH Line Delay Rank value filter processing in the IP90MD20 requires three successive lines of horizontal image data. Because incoming image data enters in ranks of one line at a time, the module meets the processing requirement by When the pixel clock frequency is higher than 20 MHz, both ICLKI and ICLK2 are used. When the frequency is 20 MHz or lower, only ICLKI is used. Q-3 I PIN (7) Host Interface Block ASSIGNMENTS Table 1 lists the pin assignments for the IP90MD20. Signal pins are divided between the image system and control system, having three and two external connectors, respectively. These signal pin assignments conform to SIDIP standards. The host interface provides control over the JP90MD20. Its data bus (SDOO-07) is 8 bits wide, and its address bus (SAOD-ll) is 12 bits wide. Write operations are controlled by the MWR* signal, and read operations by the MRD* signal. The registers on the IP90MD20 are write-only, and they are accessed by the MfR* signal. Table lA lists the signal pin assignments for the image system, and Table IB lists signal pin assignments for the control system. a) ID Number Reading MECHANICAL DIMENSIONS The GST* signal outputs the IP90MD20's ID number (08h) through the data bus. Figure 4 shows the board size and signal pin connector locations. The board size and connector positions conform to SIDIP standards. b) System Reset The SRST* signal causes a hardware reset, which returns all registers on the module to OOh. Signal Connector ICLKI CNlD Pin No. 12 Image clock 1 I ICLK2 CNlD 14 Image clock 2 I HS* CNlD 8 Horizontal synchronization signal I VS* CNlD 10 Vertical synchronization signal I INOO* CNIC 2 Input image data bus (Bit 0) I INOl* CNlC 17 Input image data bus (Bit 1) I IN02* CNlC 3 Input image data bus (Bit 2) I IN03* CNIC 18 Input image data bus (Bit 3) I IN04* CNIC 4 Input image data bus (Bit 4) I INOS* CNIC 19 Input image data bus (Bit S) I IN06* CNIC S Input image data bus (Bit 6) I I Function I/O IN07* CNIC 20 Input image data bus (Bit 7) OUTOO* CNlC 12 Output image data bus (Bit 0) 0 OUTOl* CNIC 27 Output image data bus (Bit 1) 0 OUT02* CNIC 13 Output image data bus (Bit 2) 0 OUT03* CNlC 28 Output image data bus (Bit 3) 0 OUT04* CNIC 14 Output image data bus (Bit 4) 0 OUTOS* CNIC 29 Output image data bus (Bit 5) 0 OUT06* CNIC 15 Output image data bus (Bit 6) 0 OUT07* CNIC 30 Output image data bus (Bit 7) 0 JOEL* CN1E 2 Image bus output enable (lower) I Table 1A. Image System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. Q-4 Signal Connector Pin No. Function I/O SDOO CN1A 3 Control data bus (Bit 0) I/O SD01 CN1A 18 Control data bus (Bit 1) I/O SD02 CNIA 4 Control data bus (Bit 2) I/O SD03 CN1A 19 Control data bus (Bit 3) I/O I/O SD04 CN1A 5 Control data bus (Bit 4) SD05 CN1A 20 Control data bus (Bit 5) I/O SD06 CN1A 6 Control data bus (Bit 6) I/O SD07 CN1A 21 Control data bus (Bit 7) I/O SAO a CN1B 17 Control address bus (Bit 0) I SA01 CNlB 3 Control address bus (Bit 1) I SA02 CNIB 18 Control address bus (Bit 2) I SA03 CN1B 4 Control address bus (Bit 3) I SA04 CN1B 19 Control address bus (Bit 4) I SA05 CN1B 5 Control address bus (Bit 5) I SA06 CN1B 20 Control address bus (Bit 6) I SA07 CN1B 6 Control address bus (Bit 7) I SA08 CN1B 21 Control address bus (Bit 8) I SA09 CN1B 7 Control address bus (Bit 9) I SAlO CNIB 22 Control address bus (Bit 10) I SAIl CN1B 8 Control address bus (Bit 11) I MEN* CNIA 14 Module enable I M/R* CN1B 25 Mell1ory/register I MRD* CN1B 27 Read signal I MWR* CN1B 12 Write signal I GST* CN1A 29 ID read signal I SRST* CN1B 28 Systell1 reset I Table lB. Control Systell1 Signal Pin Assignll1ents Note: An asterisk (*) follOWing a signal nallle indicates inverse logic. Q-5 5.0 2.2 '" Components I!l1e'Ull 'G"U on component side Components mounted on solder side Component side max 4.6 max 2.2 2.2 '" Note 1: Units: rom Figure 4. Board Size and Connector Positions Notes 1: Connectors: Japan Aviation Electronics Industry, Limited IL-WX-30PE-VFB4-B (Mating connector: Japan Aviation Electronics Industry, Limited IL-WX-30SB-VF-B) 2: Connector pin nwnber assignments: 16-30 L:J -: #1 pin mark 1-15 3: Connectors to be mounted on the soldered surface. 4: To conform to specifications for module external shape (single-wide). 5: Connector position measurements are to center of connector. SIDIP Image Processing Modules IP90MD25 Spatial & Logical Filter Module Product Manual Ver. E 1.1 • Sumitomo Metal Industries, Ltd. SIDIP Spatial & Logical Filter Module IP90MD25 FEATURES AND FUNCTIONS PRODUCT OVERVIEW • Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Metal Industries • High-speed filter built around an IP90C25 chip The core of the IP90MD25 spatial and logical processing module is the Sumitomo Metal Industries IP90C25 spatial and logical filter LSI (large scale integration) chip. This module is compatible with the SIDIP standard interface for digital image processing proposed by Sumitomo Metal Industries, and can perform spatial and logical filter processing of 3 x 3-pixel local areas at pixel clock speeds of up to 25 MHz. Broad internal computation range with no overflow • Binary processing capacity with on-board input signal • 3 x 3-pixel local area size • 8-bit input/ output image data width • 8-bit, encoded index value/addition constant • 0-8 bit output compensation shift The module has two basic operating modes: Maximum processing area of 2048 (horizontal) x 4095 (vertical) pixels • 25 MHz maximum operating frequency • Control software reference source list • Module ID can be read out • Operates on a single 5V power source • All terminal signal levels are TTL level • Module size 48.8 x 127.0 mm (SIDIP single-wide size) Built-in image-processing devices for factory automation (FA) equipment • Built-in image-processing devices for office automation (OA) equipment • Dynamic image-processing devices • Option board for general imageprocessing devices • IP90C25, IP90C51 evaluation A spatial filtering mode for processing 8-bit grayscale images using a programmable filter coefficient. (The filter's value is expressed in 8-bit, 2-complement format.) • A logical filtering mode for processing binary images using user-defined logical expressions. These expressions are designated by writing truth tables into a look-up table (LUT), which allows new filters to be created by rewriting the LUT. (For further details about filter processing, refer to the technical documentation for the IP90C25 chip.) The functions provided by the IP90MD25 module were previously only available by using bulky equipment. In contrast, the 48.8 x 127.0-mm (SIDIP single-size) module is designed for use as an add-on daughter board, and need only be connected to a CPU bus for control signals and to digital image input! output terminals to provide real-time spatial and logical filtering. APPLICATIONS • • The SIDIP module series features a base board with connections for VME, ISA, and other interfaces. These allow individual SIDIP add-on modules to be connected as daughter boards for easy configuration of image processing systems. R-1 STRUCTURE AND OPERATION The IP90MD25 module can process only the area defined by the. vertical and horizontal synchronization signals, represented by the shaded area in Figure 1. The size and position of this area can be controlled from the host computer. In addition, areas outside this area can be considered background and processed in gradients (0-255) designated by the host computer. The output image is a filtered raster image, as is the input image. At this point, the pixel clocks and the horizontal and vertical synchronization signals are the same as for the input image. However, the internal delay factor delays the output image by 15 to 39 rows relative to the input image, depending on the operating mode. (1) Input/Output wages The IP90MD25 module can handle either binary-coded or 8-bit grayscale raster images (non-interleaved). The minimum system required for the IP90MD25 to perform spatial and logical filtering includes a pixel clock synchronized with the pixels that make up the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image (see Figure 1). These synchronization signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. Figure 2 shows an example of an actual application. Synchronized by vertical synchronization ----'W- Pixel clock ~Horizontal synch. signal / hVertical synch. signal Source image Synchronized by horizontal synchronization signal Image data bus Image data bus memory 2 Filtered image Figure 2. Sample Application Figure 1. Definition of Image Area for Processing R-2 Vcc INOO* _--+~ -07* GNO ICLK1 ICLK2 --H~ HS* _-+~ VS* ec Image input processing e IP90C25 spatial & logical filter processing LSI (chip) Timing control -+-I~ u OUTOS* -15* e IOEL* ::; 0.. ::; Q) Cl co .5 SRST* SOOO-07 GST* MEN* MRO* SAOO-11 M/R* MWR* Figure 3. Block Diagram (2) Image Input Block (4) Chip Block Figure 3 shows a block diagram of the IP90MD25 module. (Note: an asterisk [*] following a signal name indicates inverse logic.) This is the block in which filter processing takes place. The spatial and logical filter LSI (IP90C25) performs the necessary functions for spatial and logical filter processing. Inverted image data is input at the input image bus (located at INOO-IN07). The input block inverts this data again, and also converts 8-bit grayscale data to binary data if binary processing is used. Binary data is converted to 8-bit logic using the values OOh for [0] and FFh for [1]. Note that because the bus carries values that are inverted for processing, data entering the module appears in the bus as FFh for [0] and OOh for [1]. (5) Image Output Control Block The filtered image is output to the image bus with a width of 8 bits, and with signal logic inverted. The output signal is in three states, enabling connection to tri-state buses in other modules. (6) Timing Control Block The timing control block is the point of entry for the two pixel clock signals (ICLK1, ICLK2), the horizontal synchronization signal (HS*), and the vertical synchronization signal (VS*). (3) 1H Line Delay Rank filter processing in the IP90MD25 requires three successive lines of horizontal image data. Because incoming image data enters in ranks of one line at a time, the module meets the processing requirement by applying a line delay of one horizontal line, in two iterations. When the pixel clock frequency is 20 MHz or lower, only ICLKl is used. When the frequency is higher than 20 MHz, a two-phase clock input is created using both ICLK1 and ICLK2. R-3 (7) Host Interface Block b) System Reset The host interface block contains the interface for the host computer that controls the operation of the IP90MD2S module. Its data bus (SDOO-07) is 8 bits wide, and its address bus (SAOO-Il) is 12 bits wide. The MWR* and MRD* signals control write and read operations, respectively. The MjR' signal controls memory j register access in accordance with SIDIP standards, although the IP90MD2S module contains no memory units. The SRST* signal causes a hardware reset, and must be executed every hardware startup. PIN ASSIGNMENTS Table 1 lists the pin assignments for the IP90MD2S. Signal pins are divided between the image system (Table lA) and control system (Table 1B), having three and two external connectors, respectively. These pin assignments conform to SIDIP standards. (8) Other MECHANICAL DIMENSIONS a) ID Number Reading Figure 4 shows the board size and signal pin connector locations. The size and locations conform to SIDIP standards. The GST' signal outputs the IP90MD2S's ID number (OCh) through the data bus. Signal Connector Pin No. ICLK1 CNlD 12 Image clock 1 I ICLK2 CN1D 14 Image clock 2 I HS* CNlD 8 Horizontal synchronization signal I Function I/O VS* CN1D 10 Vertical synchronization signal I INOO' CN1C 2 Input image data bus (Bit 0) I IN01* CN1C 17 Input data bus (Bit 1) I IN02' CN1C 3 Input image data bus (Bit 2) I im~e IN03* CNIC 18 Inp_ut image data bus (Bit 3) I IN04' CN1C 4 Input image data bus (Bit 4) I INOS* CN1C 19 Input image data bus (Bit S) I IN06' CN1C 5 Input image data bus (Bit 6) I IN07' CNlC 20 Input image data bus (Bit 7) I OUT08* CNlD 2 Output image data bus (Bit 0) 0 OUT09' CNlD 17 Output image data bus (Bit 1) 0 OUTlO' CNlD 3 Output image data bus (Bit 2) 0 OUTIl * CNlD 18 Output image data bus (Bit 3) 0 OUTl2* CNlD 4 Output image data bus (Bit 4) 0 OUTl3' CNlD 19 Output image data bus (Bit S) 0 OUTl4' CNlD 5 Output image data bus (Bit 6) 0 OUTlS' CNlD 20 Output image data bus (Bit 7) 0 IOEL' CN1E 2 Image bus output enable (lower) I Table 1A. Image System Signal Pin Assignments Note: An asterisk (.) following a signal name indicates inverse logic. R-4 Connector Pin No. Function 110 SDOO CNIA 3 Control data bus (Bit 0) I/O SDOI CNIA 18 Control data bus (Bit 1) I/O SD02 CNIA 4 Control data bus (Bit 2) I/O SD03 CNIA 19 Control data bus (Bit 3) I/O SD04 CNIA 5 Control data bus (Bit 4) I/O SD05 CNIA 20 Control data bus (Bit 5) I/O SD06 CNIA 6 Control data bus (Bit 6) I/O SD07 CNIA 21 Control data bus (Bit 7) I/O SAOO CNlB 17 Control address bus (Bit 0) I SAOI CNIB 3 Control address bus (Bit 1) I SA02 CNIB 18 Control address bus (Bit 2) I I Signal SA03 CNIB 4 Control address bus (Bit 3) SA04 CNlB 19 Control address bus (Bit 4) I SA05 CNIB 5 Control address bus (Bit 5) I SA06 CNIB 20 Control address bus (Bit 6) I SA07 CNlB 6 Control address bus (Bit 7) I SA08 CNlB 21 Control address bus (Bit 8) I SA09 CNlB 7 Control address bus (Bit 9) I SAlO CNIB 22 Control address bus (Bit 10) I SAIl CNlB 8 Control address bus (Bit 11) I MEN* CNIA 14 Module enable I M/R* CNIB 25 Memory / register I MRD* CNIB 27 Read signal I MWR* CNIB 12 Write signal I GST* CNIA 29 ID read signal I SRST* CNlB 28 System reset I Table IB. Control System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. R-5 5.0 2.2 \Ii on component side 11lIU'WlI,ea Components mounted on solder side Component side max 4.6 max 2.2 :g .... fIl ~ .8 2.2 \Ii Note 1: Units: rom Figure 4. Board Size and Connector Positions Notes 2: Connector pin n~ assignments: 1: Connectors: Japan Aviation Electronics Industry, Limited IL-WX-30PB-VF84-B (Mating connector: Japan Aviation Electronics Industry, Limited IL-WX-30SB-VF-B) 16-30 c=J e:#1pinmark 1-15 3: Connectors to be mounted on the soldered surface. 4: To conform to specifications for module external shape (single-wide). R-6 SIDIP Image Processing Modules IP90MD81/01/05 Histogram / Projection Module Prod uct Manual Ver. E 1.2 • Sumitomo Metal Industries, Ltd. SIDIP Histogram I Projection Module IP90MD81/01/05 The IP90MD81/0l/05 series is available in different models based on the size of the maximum processing area, as shown in the table below. Unless otherwise specified, this manual describes model IP90MD81-1K. Other models are available only in mass-produced versions. FEATURES AND FUNCTIONS • Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Metal Industries • Module size 48.8 x 127.0 mm (SIDIP single-wide size) Operates on single 5V power source All terminal signal levels are TTL level Compatible with 8- and 16-bit CPU busses Module ID can be read out • • • Maximum processing area Histogram processing Histogram Unit • Histogram processing of 8-bit grayscale image data • • • • Maximum histogram processing area of 1023 x 1023 pixels Vertical and horizontal processing area dimensions can be programmed independently One-shot clearing of histogram data Pixel clock frequency range of 5 to 25 MHz • • • IP90MD81-1K 1023 X 1023 1024 IP90MD81-512 1023 X 1023 512 IP90MDOl 1023 X 1023 X 1024 X 512 - IP90MD05-1K - 1024 X 1024 IP90MD05-512 - 512 X 512 APPLICATIONS Projection Unit • Projection processing of 8-bit grayscale image data • Projection processing Simultaneous projection processing of vertical and horizontal dimensions Vertical and horizontal processing area dimensions can be programmed independently Maximum projection processing area of 1024 x 1024 pixels • Character-recognition or patternrecognition devices • General purpose image-processing devices • Built-in image-processing devices for factory automation (FA) equipment • Built-in image-processing devices for office automation (OA) equipment PRODUCT OVERVIEW The IP90MD81 histogram/projection processing module uses a core containing two chips from the Sumitomo Metal Industries image-processing LSI (large scale integration) series: the IP90C01 histogramprocessing LSI, and the IP90C05A projectionprocessing LSI. The core also includes peripheral circuitry in a proprietary circuit board designed for histogram and projection processing. Pixel clock frequency range of 5 to 25 MHz PRODUCT LINEUP The IP90MD81 module can perform both histogram and projection processing. It is also available in versions for histogram processing only (IP90MDOl) and for projection processing only (IP90MD05). S-l The module's bus architecture is compatible with the SIDIP standard interface for digital image processing proposed by Sumitomo Metal Industries, and includes bus interfaces for other image-processing modules. Projection Processing The IP90MD81 board includes four IP90C05A chips, and performs projection processing in the same way as the IP90C05A chip. Projection processing can be either Y-axis processing (of the sums of the grayscale values of each row), or X-axis processing (of the sums of the grayscale values of each column). Histogram Processing The IP90MD81 performs histogram processing in the same way as the IP90COl chip. Projection processing requires input of the pixels of the 8-bit grayscale raster image to be processed, along with the pixel clock and the horizontal and vertical synchronization signals synchronized with those pixels. Histogram processing requires input of the pixels of the 8-bit grayscale raster image to be processed, together with the pixel clock and the horizontal and vertical synchronization signals synchronized with those pixels. All grayscale values are expressed in a 20-bit histogram. Grayscale histogram processing is done on the image bus in real time by the IMBC (image data bus controller IP90C51), which is located in the image input processing unit along with the IP90COl chip. The IP90MD81 module executes X-axis and Yaxis projection processing on the image bus simultaneously and in real time by the IMBC (image data bus controller IP90C51), located in the image input processing unit with the IP90C05A chips. The maximum area that can be processed is 1023 horizontal pixels by 1023 vertical lines. The pixel clock operates at a maximum frequency of 25MHz. Figure 1(a). Original Image 30.-----------------~--~~ 20+----rr~----~--~ 10+-~#a~~~~~~ O~aw~~Wll~~~ua~ Figure 1(b). Example of a Histogram of Distribution of Grayscale Values Figure 2. Example of Character Recognition by Projection Processing 5-2 The maximum area that can be processed is 1024 horizontal pixels by 1024 vertical lines. The pixel clock operates at a maximum frequency of 25 MHz. Synchronized by vertical synchronization signal The IP90MD81 module has its own module ID, which can be read by the host computer for easier configuration of systems. This ID can be used to determine whether the IP90MD81 is present, or for automatic system configuration. The IP90MD81 module replaces previous lowspeed software processing systems and bulky hardware, providing a space-saving, highspeed hardware device for easy histogram and projection processing. The module is designed for use in general-purpose imageprocessing devices, and particularly for builtin image processing devices in FA applications that require high processing speeds. It is also ideally suited for built-in systems in OA equipment such as copiers and fax machines. Synchronized by horizontal synchronization signal Figure 3. Definition of Image Area for Processing Pixel clock ~Horizontal synch. signal ~Vertical synch. signal STRUCTURE AND OPERATION (1) Input/Output Images The IP90MD81 module can handle either binary-coded or 8-bit grayscale raster images (non-interleaved). The minimum system required for the IP90MD8l to perform histogram and projection processing includes a pixel clock synchronized with the pixels that make up the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image (see Figure 3). These signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. 8 or 16 CPU CPU Image L...-_---' data '------' bus bus Figure 4. Sample Application Image bus selector INOO*-IN07* (A) (B) __ -- --,- .. -..... , ,-,, -~ I: , ,' The IP90MD81 module can process only the area defined by the vertical and horizontal synchronization signals, represented by the shaded area in Figure 3. The size and position of this area can be controlled from the host computer. In addition, areas outside this designated area can be considered background and processed in gradients (0-255) controlled from the host computer. INOS*-IN15* (el I' I .- .1._ (AI IMBC S IP90C51 ~ #1 IMBC IP90C51 #2 (A): INCO'·INO?' selection occurs in IMBC#l, and INOS'·IN15' selection occurs in IMBC#2. (B): INCO'·INO?, selection occurs in both IMBC#l and IMBC#2. (C): INOS'·IN15' selection occurs in both IMBC#l and IMBC#2. Figure 5. Image Bus Selection Figure 4 shows an example of an actual application. (2) Image Input Block Figure 6 shows a block diagram of the IP90MD81 module. Figure 5 shows the flow of image input from the bus selector in Figure 6. 5-3 Inverted image data is input at the input image bus (located at INOO-INI5). The input block inverts this data again, and also converts 8-bit grayscale data to binary data if binary processing is used. Binary data is converted to 8-bit logic using the values OOh for [0] and FFh for [1]. Note that because the bus carries values that are inverted for processing, data entering the module appears in the bus as FFh for [0] and OOh for [1]. (5) Timing Control Block The timing control block is the point of entry for the pixel clocks (ICLKI, ICLK2), the horizontal synchronization signal (HS*), and the vertical synchronization signal (VS*). The maximum pixel clock frequency handled by the IP90MD8I module is 25 MHz. At frequencies higher than 20 MHz, a two-phase clock input is created using both ICLKI and ICLK2. At frequencies of 20 MHz or lower, only ICLKI is used. (3) Histogram ProceSSing Block This block provides the necessary functions for histogram processing, using the IP90COI histogram-processing LSI chip. (6) Host Interface Block The host interface block contains the interface for the host computer that controls the operation of the IP90MD8I module. The data bus (SDOO-I5) and the address bus (SAOO-I5) are 16 bits wide. An 8-bit data bus interface can also be used by using only the first 8 bits of the data bus (SDOO-07). (4) Projection Processing Block This block provides the necessary functions for projection processing, using four IP90C05A histogram-processing LSI chips. The maximum processing area is 1024 x 1024 pixels. INOO' -INOr INOS' -IN15' ICLK1 ICLK2 HS' VS' Vcc GNO - .. - .. -'-- ,.. ,.. ,.. Image bus selector .-. (IP90C51) IMBC#1 ..... l IMBC Image i~put processing ~ I PROJ Projection processing ~ (IP90C05A) \(I P90C05A)\ (IP90C05A) #1 #3 #4 (IP90C51) IMBC#2 (lP90C05A) #2 j~ Timing Control HIST Histogram processing (lP90C01) ~ --.. --.. A • I • 10 ROM I * I Host interface ~ ~ ~ ~ A~ Ir ~ 1 ~ MEN' MRO' M/R' INT' S008 -15 GST' MWR' SRST BHE' SOOO -07 Figure 6. Block Diagram S-4 SAOO -15 PIN Write operations are controlled by the MEN* and MWR* signals, and read operations by the MEN* and MRD* signals. Register identification is controlled by the M/R* signal. ASSIGNMENTS Table 1 lists the pin assignments for the IP90MD81. Signal pins are divided between the image system (Table lA) and control system (Table IB), having three and two external connectors, respectively. These pin assignments conform to SIDIP standards. a) 10 Number Reading The GST* signal outputs the IP90MD81's ID number (ICh) through the data bus. MECHANICAL b) System Reset The SRST* signal causes a hardware reset, which resets all module registers to OOh. DIMENSIONS Figure 7 shows the board size and signal pin connector locations. The size and locations conform to SIDIP standards. Function 110 Signal Connector Pin No. ICLKI CNID 12 Image clock 1 I I ICLK2 CNID 14 Image clock 2 HS* CNID 8 Horizontal synchronization signal I 10 Vertical synchronization signal I VS* CNID INOO* CNIC 2 Input image data bus (Bit 0) I INOl* CNIC 17 Input image data bus (Bit 1) I IN02* CNIC 3 Input image data bus (Bit 2) I IN03* CNIC 18 Input image data bus (Bit 3) I IN04* CNIC 4 Input image data bus (Bit 4) I IN05* CNIC 19 Input image data bus (Bit 5) I IN06* CNIC 5 Input image data bus (Bit 6) I IN07* CNIC 20 Input image data bus (Bit 7) I IN08* CNIC 7 Input image data bus (Bit 8) I IN09* CNIC 22 Input image data bus (Bit 9) I INI0* CNIC 8 Input image data bus (Bit 10) I INll* CNlC 23 Input image data bus (Bit 11) I INI2* CNlC 9 Input image data bus (Bit 12) I INI3* CNIC 24 Input image data bus (Bit 13) I INI4* CNIC 10 Input image data bus (Bit 14) I INI5* CNIC 25 Input image data bus (Bit 15) I Table 1A. Image System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. S-5 Signal Connector Pin No. SDOO SDOI SD02 SD03 SD04 SD05 SD06 SD07 SD08 SD09 SOlO SDII SD12 SDl3 SDl4 SOlS SAOO SAOI SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SAlO SAll SA12 SA13 SA14 SA15 BHE* INT* MEN* M/R* MRD* MWR* GST* SRST* CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIA CNIB CNIB CNIB CNIB CNIB CNIB CNIB CNIB CNIB CNlB CNIB CNIB CNIB CNIB CNIB CNIB CNIB CNIA CNIA CNIB CNIB CNIB CNIA CNIB 3 18 4 19 5 20 6 21 7 22 8 23 9 24 10 25 17 3 18 4 19 5 20 6 21 7 22 8 23 9 24 10 2 27 14 25 27 12 29 28 Function I/O Control data bus (Bit 0) Control data bus (Bit 1) Control data bus (Bit 2) Control data bus (Bit 3) Control data bus (Bit 4) Control data bus (Bit 5) Control data bus (Bit 6) Control data bus (Bit 7) Control data bus (Bit 8) Control data bus (Bit 9) Control data bus (Bit 10) Control data bus (Bit 11) Control data bus (Bit 12) Control data bus (Bit 13) Control data bus (Bit 14) Control data bus (Bit 15) Control address bus (Bit 0) Control address bus (Bit 1) Control address bus (Bit 2) Control address bus (Bit 3) Control address bus (Bit 4) Control address bus (Bit 5) Control address bus (Bit 6) Control address bus (Bit 7) Control address bus (Bit 8) Control address bus (Bit 9) Control address bus (Bit 10) Control address bus (Bit 11) Control address bus (Bit 12) Control address bus (Bit 13) Control address bus (Bit 14) Control address bus (Bit 15) Control bus upper byte enable Interrupt request signal Module enable Memory/register Read signal Write signal ID read signal System reset I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I Table 1B. Control System Signal Pin Assignments Note: An asterisk (*) following a signal name indicates inverse logic. S-6 I I I I I I I I I I I I 0 I I I I I I 5.0 2.2 ¢ Components mounted on component side Components mounted on solder side DII Component side max 4.6 2.2 max 2.2 ¢ Note 1: Units: rom Figure 7. Board Size and Connector Positions Notes 1: 2: Connectors: Japan Aviation Electronics Industry, Limited IL-WX-30PB-VF84-B (Mating connector: Japan Aviation Electronics Industry, Limited IL-WX-30SB-VF-B) 3: Connectors to be mounted on the soldered surface. 4: To conform to specifications for module external shape (single-wide). Connector pin number assignments: 5: Connector position measurements are to the center of the connector. 16~30 ~ e:#lpinmark 1-15 S-7 SIDIP Image Processing Modules IP90MDI00 Frame Memory Module Product Manual Ver. E 1.1 • Sumitomo Metal Industries, Ltd. SIDIP Frame Memory Module IP90MD100 FEATURES AND FUNCTIONS APPLICATIONS • Compatible with the SIDIP (Standard Interface for Digital Image Processing) interface proposed by Sumitomo Metal Industries • Expansion frame memory for imageprocessing systems configured with Sumitomo Metal Industries base board/module components • Maximum pixel clock frequency of 25 MHz • Large-scale frame memory applications • Maximum input image area of 4095 x 4095 pixels • Built-in frame memory for general imageprocessing devices • Frame memory size of 1024 x 1024 x 8-bit x 2 frames, or 2048 (horizontal) x 512 (vertical) x 8-bit x 2 frames • Dual image bus systems for both input and output (four systems in all) • Frame memory space coordinates can be set at any location within the input/ output image space • Independent read/write window scanning in frame memory space • Supports read and write freeze functions with programmable freeze timing • Frame memory space can be accessed from host computer • 16-bit memory access to two memory frames • Compatible with 8-bit and 16-bit ISA busses • Module ID can be read out • Operates on a single 5-V power source • All terminal signal levels are TTL level • Module size of 48.8 x 127.0 mm (SIDIP single-width size) PRODUCT DESCRIPTION The IP90MD100 frame memory module is based on the SIDIP standard interface for digital image processing proposed by Sumitomo Metal Industries. The IP90MD100 provides memory frame capacity for two frames of 1024 (horizontal) x 1024 (vertical) x 8-bit images, or two frames of 2048 (horizontal) x 512 (vertical) x 8-bit images. The module supports window scanning for high-speed transfer and processing, using separate read and write windows whose coordinates can be defined independently within each frame memory space. Each frame memory space also supports definition of input/ output image space using programmable coordinates. The IP90MD100 module has two independent SIDIP image bus systems for input and two for output. This allows simultaneous transfer of two streams of image data to and from both frame memory spaces through the image bus systems. The IP90MD100 supports independent freeze functions for reading and writing. It provides access to frame memory from a host computer for sequential access read and write functions. T-l STRUCTURE AND OPERATION The output image is a labeled raster image, as is the input image, and has the same pixel clock and synchronization signals as the input image. However, the module uses an internal delay factor to delay the output image by a specified number of pixels horizontally and vertically relative to the input image. (1) Input/Output Images The IP90MD100 module can handle binarycoded or 8-bit grayscale raster images (noninterleaved). The IP90MDlOO requires as a minimum a system that includes a pixel clock synchronized with the pixels that make up the raster image, as well as the horizontal and vertical synchronization signals necessary to construct the raster image. These Signals are synchronized with the pixel clock, and must have the width of one cycle of the inverse logic pulse as changed by the rise of the pixel clock. Rasters Figure 2 shows an example of an actual application. Pixel clock ~Horizontal synchronization signal -I_--,~Vertical synchronization signal Synchronized by vertical synchronization signal Frame memory 8 1 Image data bus Source image 8 Frame memory Image data bus 2 IP90MD100 Filtered image Figure 2. Sample Application (2) Image Input Block Figure 3 shows a block diagram of the IP90MD100 module. Synchronized by horizontal synchronization signal Inverted image data enters through two input image bus systems: lower bytes enter at the eight-bit INO*-IN07* bus system, and upper bytes enter at the eight-bit IN08*-IN15* bus system. The lower bytes are allocated to frame memory FM#O, and the upper bytes to FM#l. Figure 1. Definition of Image Area for Processing The IP90MDlOO module can process only the area defined by the vertical and horizontal synchronization signals, represented by the shaded area in Figure 1. The host computer controls the size and position of this area. In addition, areas outside the deSignated processing area can be considered background and processed as any gradient value (0-255) designated by the host computer. This input data is logically inverted again in the image input block. T-2 INoe OUTOO* -07* -07 IOEL* OUT08* -15* INOE -1~ IOEH* IClK1 OIl IClK2 VS* HS* SOOO-l ! SAOO-1 ! GST* BHE*, MEN*, SRST* MRO*, MWR*, MfR' INT*, MACK' Figure 3. Block Diagram Frame Memory Function (3) Frame Memory Block Frame memory is constructed from field memory units, and can be used as two 1024 (horizontal) x 1024 (vertical) x 8-bit frames, or as two 2048 (horizontal) x 512 (vertical) x 8bit frames. Frame memory function is described in "Frame Memory Function," below. (1) Frame Memory Input/Output Space The IP90MD100 module handles image data in terms of the following three types of space: input/ output image space, frame memory space, and clipping window areas. These are described below. (4) Image Output Block (1-1) Input/Output Image Space Data can be outputted over two output image bus systems: lower bytes at the eight-bit OUTO*-OUT07* bus system, and upper bytes at the eight-bit OUT08*-OUT15* bus system. The lower bytes are allocated to frame memory FM#O, and the upper bytes to FM#l. The IP90MDlOO handles the vertical and horizontal synchronization signals VS* and HS* in terms of a rectangular image area called the clipping window area. This area has a maximum size of 4095 x 4095 pixels, and is mapped at a designated address within frame memory along the time axis, using any given coordinates. This area is used to input or output images. The module produces three-state output, with inverted signal logic and independently controlled connection status. T-3 Figure 4 shows a two-dimensional image space representing a raster scan based on the synchronization signal system, with two sample clipping window areas mapped in frame memory. HS*~ (1-2) Frame Memory Space The IP90MDlOO's frame memory has capacity for two 1024 x 1024 x 8-bit frames, or two 2048 (horizontal) x 512 (vertical) x 8-bit frames. As Figure 5 shows, each clipping window area is defined within frame memory space by mapping selected coordinates in the input/ output image space. Figure 6 shows a one-dimensional representation of frame memory address space along the memory address axis. Ir------------------------ - , image space _~o.'2!1i!'iC!,OL---------clipping window start point (OFx,OFy) address UUUUUh~ Sad area end point (OFx+Wx,OFy+Wy) Sad + FMx [Two-dimensional image space coordinates along time OFx: Horizontal start point of clipping window (horizontal off OFy: Vertical start point of clipping window (vertical offset) Wx: Clipping window width Wy: Clipping window height Sad + FMx X(Wy-1) ~(W~yC:-)~t"'.L"";n-..:l, fw0 FMx Figure 4. Schematic Diagram of TwoDimensional Input/Output Space (Along Time Axis) I----I--.i. FFFFFhex.~ origin address ( [One~dimensional (0,0 Sad: Wx: Wy: FMx: FMy: T frame memory size (FMy) Figure 6. Schematic Diagram of Frame Memory Address in One Dimension r'~ (1-3) Clipping Window Areas ! -- - - - _...... I trame memory size (FM'-----l (1023,1023) or f«---- 1024/2048 *note A clipping window is a local area of frame memory space that is defined as an input area or output area. Two areas can be designated within a single frame memory area, one as a window for output (reads from frame memory) and the other as a window for input (writes to frame memory). Figure 7 shows output and input clipping areas mapped in twodimensional image space. -------, (2047,511 ) final address FFFFF hex. l Two~dimensional coordinates and size ot frame memory address ~ Sx: Sy: Wx: Wy: FMx: FMy: Horizontal start point of clipping window Vertical start point of clipping window Clipping window width Clipping window height Frame memory width Frame memory height Note 1 In 1024 x 1024 pixel mode, frame memory configuration is horizontal FMx FMy = 1024. In 2048 x 512 addressing in frame memory address space] Starting address for clipping window Clipping window width Clipping window height Frame memory width Frame memory height = 1024, vertic pixel mode, fram memory configuration is horizontal FMx = 20· vertical FMy = 512. Figure 5. Schematic Diagram of Frame Memory Address in Two Dimensions T-4 HS*-y i image space origin (0,0) I --r------~------------------i OFry (OFrx,OFry; I These two (input and output) clipping window can be created within H same frame memory. T OFrx Wry OFwy 00( (OFwx,OFwy: OFwx i T 1111I Wwy o~::E 0 1 < 4095(Max, a.. - .... \ (OFwx+Wwx, OFwy+Wwy) .... 1 > [Two-dimensional image space coordinates along time OFrx: Horizontal start point of output clipping window (horizontal offset, OFry: Vertical start point of output clipping window (vertical offset) OFwx: Horizontal start point of input clipping window (horizontal offset) OFwy: Vertical start point of input clipping window (vertical offset) Wrx: Output clipping window width Wry: Output clipping window height Wwx Input clipping window width Wwy Input clipping window height Figure 7. Example of Mapping Input and Output Clipping Windows in Two-Dimensional Space Along the Time Axis T-5 ! Op;..o ::!"~I 01 E l_________ ~_~~!~_~~_~~~~_t!~~~~~_~_i~_~~_~_~_____________________________________ ~ tn , ~OJ'8 1 r--ww'X ~;:l OJ ::E (A) Output clipping window placed at an earlier position in image space than the Input clipping window (2) Input/Output Data Phase Relationship The image data written into frame memory is sent to the output image bus after a delay of 0 or 1 frames. If the input and output clipping windows overlap in frame memory address space, the delay is then the period before the input image data is sent back as output. As long as the clipping windows do not overlap, however, the input image data is not immediately sent back as output, so no delay factor is used. The delay factor between image data input and output differs according to the image space coordinates of the clipping window areas. Figure 8 shows three examples of phase relationships between windows, and describes the corresponding differences in delay in relation to their relative positions. HS' fg ~ -~~~------------ , f Wry w....::....~~.t (8) Input clipping window placed at an earlier position in image address space than the output clipping window HS' =u ~ -.~~~-------------, I, I (2-1) Output Clipping Window Located at an Earlier Position in Image Space (Figure 8, Case A) The contents of the output clipping window are sent before image data is written into the input clipping window. Thus, output is always delayed by one frame, even though the user has accessed the same address in frame memory. This means incoming data is not output until the next frame. For example, image data input in the nth frame is output as the (n+1)th frame. (C) Input and output clipping windows overlapping in image lield space. HS' 1!: =-u --J.-(~~------------I ,I II II II (2-2) Input Clipping Window Located at an Earlier Position in Image Space (Figure 8, Case B) I The image data is written into the input clipping window before data is read out of the output clipping window. This means the freshest incoming image data is always output within the same frame (delay of 0 frames) when the user has accessed the same address in frame memory. Figure 8. Three Relationships of Input and Output Clipping Windows Mapped in TwoDimensional Input/Output Image Space and Frame Memory Address Space Along the Time Axis T-6 (3-2) Read Freeze (2-3) Input and Output Clipping Windows Overlap (Figure 8, Case C) A read freeze transfers from the module to the host computer the authority to read the contents of frame memory to the host computer. To apply a read freeze, it is first necessary to apply a write freeze from the host computer. As long as the pixel data is written into frame memory and read out in 160 clock counts or less, the data read out will be one frame earlier than the latest input data. If more than 160 clock counts elapse, the data written out will be the latest input data. Therefore, if any pixels in the output clipping window occupy the same addresses as pixels in the input clipping window, and are 160 pixels or more behind the input image on the raster axis, the frame delay is 0 frames. If the difference is less than 160 pixels, the delay is 1 frame. When a read freeze is enabled from the host computer, reading from frame memory to the image bus is stopped with the frame synchronized with the next VS' signal that follows the enable signal. After this, frame memory output is connected to the host computer bus. To notify the host computer that the read freeze is complete (meaning that the host computer can now read from frame memory), the module sets the read freeze flag in the status register. Also, if a read freeze interrupt from the host computer is permitted, the module generates an interrupt request for the host computer. When the read freeze function is enabled, the image bus output is 'Hi-z.' (3) Freeze Functions Each module has independent freeze functions for both memory frames. These functions can freeze images during reading from frame memory to the image bus, or during writing from the image bus to frame memory. Freeze functions are controlled from the host computer. (3-1) Write Freeze When the host computer disables the read freeze function, the freeze is released beginning with the frame synchronized with the next VS' signal that follows the disable signal. The write freeze function can only be released after the read freeze function is released. The timing of a write freeze is determined by selecting and entering a VS' signal count setting (this setting must be in the range from 0 to 255 counts). When the host computer enables the write freeze function, the module counts the designated number of VS' signals, and freezes the image frame that is synchronized with the last VS' signal count. Applying a write freeze stops the writing of image data to frame memory from the input image bus, so frame memory contents no longer change. To notify the host computer that the write freeze is complete, the module sets the write freeze flag in the status register. Also, if a write freeze interrupt from the host computer is permitted, the module generates an interrupt request for the host computer. (4) Window Scan Functions By designating certain areas of frame memory space as clipping windows for image bus input and output, the IP90MDlOO module makes it possible for the image bus to read to or write from only the desired portions of frame memory space. Settings for clipping window areas are subject to the following restrictions: When the write freeze function is then disabled from the host computer, the write freeze is released beginning with the frame synchronized with the next VS' signal that follows the disable signal. T-7 • Minimum window area: 160 pixels (horizontal) x 4 lines (vertical) • Horizontal window size increment/ decrement units: 32 pixels • Vertical window size increment/ decrement units: 4 lines • Read/write scans of two separate frames can be made by separate window scans o ..9l ;:l o "0 ....
  • :: line 2 *CIl FMl (324 Kb) :I: .......... f--_ _ _ _-'l"'in"'e""n'--_ _ _ _--i FM2 (324 Kb) ........... r - - - - - - - - - - - 1 FM3 (324 Kb) ........... r - - - - - - - - - - - j FM4 (324 Kb) ........... ' - - - - - - - - - - - - ' HS * and VS * are generated by the line sensor camera synchronzation signal generator. Figure 4: ACU_FM Configuration 2.2) LUT (Look-Up Table) transfer, the camera clock can be programmed to select a 640 x 480 area from the data input frame memory by using the AOI (Area Of Interest) extraction circuit. This RAM is used to convert the AID converter's output to 8 bits and 256 gradations. (1) CAMERA INTERFACE BLOCK 2.3) Data Input Frame Memory (ACU_FM) 1.1) Input Section Figure 4 shows the ACU_FM structure. It selects only the range of effective pixels from the video signals output by the line sensor camera, and stores them in the first line of the ACU_FM as one-line data. It also stores the effective pixel range that begins with the next start pulse in the second line, up to line n set by the software, thus forming a frame (FM1). This section inputs video signals from the line sensor. Its input voltage level can be switched between 0 and 5 or 0 and 2.5 V by opening and closing the jumper post. 1.2) Camera Drive This outputs line sensor camera drive signals (camera clock and start pulse) that comply with RS-422 standards. This process is repeated four times to complete the frames FMl-4 that form the ACU_FM. (2) DATA INPUT BLOCK 2.1) ADC (AID Converter) Figure 4 shows that the horizontal area size of the ACU_PM is determined by the number of effective pixels, with the ACU_FM set as an area ranging in size from 256 x 5,184 pixels to 7,936 x 164 pixels. This circuit performs AID conversion on the input video signal, converting it into 8 bits and 256 gradations. X-5 Number of effective pixels (horizontal) r--------~ 256 • r ____ ••________~1~O=24~ , _______.~ r_ ••_ _ _ _ _ _ _ _ _ _ _ _ _ _~7~9~36~ ________________ ~l Figure 5: ACU]M Area Setting Examples and Maximum Values VGA output produces a 640 (horizontal) x 480 (vertical)-pixel area, but the entire 324-Kb area of the memory can be used to store interim data during processing. 2.4) Sync. Generator for Line Sensor Camera The software sets the start pulse width for the line sensor camera and the vertical area width for the number of effective pixels of the camera, and generates the synchronization signal needed for the camera interface. 3.2) Sync. Generator for VGA Output (3) VGA OUTPUT BLOCK The synchronization generator for VGA output generates VGA-standard synchronization signals. 3.1) VGA Output Frame Memory (VGA_FM) 3.3) RAMDAC Uses a 324-Kb frame memory. Three 256-byte palette RAMs (red, green, and blue) are used to produce quasi-natural colors and remapping changes. Number Transfer Route Transfer Method CD ACU_FM ) VGA_FM Concurrent transfer @ ACU_FM ) VGA_FM Transfer after freezing ACU_FM ® ACU_FM ) MVME162 ) VGA_FM Transfer after freezing ACU_FM @ VGA_FM) MVME162 VGA Frame Memory Access ® ® ACU_FM ) SmIP bus) VGA_FM Concurrent transfer ACU_FM ) SmIP bus) VGA_FM Transfer after freezing ACU_FM X-6 Camera Clock 25 MHz VGA Frame Memory 324 Kb x 4 Camera IN FM '-I--.R Frame Memory 640 x480 RAM DAC I---J~G L----_ _---lI---J~B Figure 6: ACU_FM to VGA_FM (Concurrent transfer) Camera Clock 25 MHz ACU_FM VGA_FM Frame Memory 324 Kb x4 Camera IN I--'-~R Frame Memory 640 x 480 RAM DAC I---J~ G I---J~B '-----' Figure 7: ACU_FM to VGA_FM (Transfer after freezing ACU_FM) 8 MHz ACU_FM VGA Frame Memory 324K x 4 Camera IN FM Frame Memory 640 x 480 RAM DAC MVME 162 Figure 8: ACU_FM to MVME162 to VGA_FM (Transfer after freezing ACU_FM) MVME 162 J I IP IIF LJ I'--__~I . . . Frame Memory 640 x 480 8 MHz Figure 9: VGA Frame Memory Access, VGA_FM to MVME162 X-7 G B 25 MHz Camera Clock R SIDIP VGA_FM Frame memory 324 Kb x 4 Frame memory 640 x 480 Camera clock RAM DAC R G B 25 MHz Figure 10: ACU_FM to SIDIP bus to VGA_FM (Concurrent transfer) SIDIP ACU VGA_FM Frame memory 324Kx4 Frame memory 640 x 480 Camera Clock R RAM DAC G B 25 MHz Figure 11: ACU_FM to SIDIP bus to VGA_FM (Transfer after freezing) ACU_FM write data ACU_FM read data Figure 12: ACU_FM input/output delay (concurrent transfer) (4) SIDIP EXTENDED I/F CIRCUIT The SIDIP extended interface circuit includes an output image data bus, input image data bus, image clock, and frame synchronization signal outputs (VS, HS). ACU_FM image data is output to the output image data bus, and image data sent through the input image data bus is picked up by the VGA_FM. This circuit is used to connect the image bus of the module baseboard (for example, the IP90BD550) to the IP90MS803. The image bus conforms to the SIDIP standard. X-8 3) OPERATIONS The ACU_FM's structure is determined by the number of pixels of the line sensor camera. It performs six different operations depending on the method of transfer used from ACU_FM to VGA_FM and the transfer route. The transfer rates vary depending on which operation is run (see the table on page 6). Transfer rate: 8 Mb/sec (16 bits). Note: Stop the line sensor camera synchronization generator in this mode. 4) Note: Stop the VGA synchronization generator in this mode. 5) ACU_FM to VGA_FM (Figure 6) The transfer rate depends on the camera clock used. 2) VGA_FM to MVME162 (Figure 9) Transfer rate: 8 Mb/sec (16 bits). (1) Input Transfer Modes 1) ACU_FM to MVME162 to VGA_FM (Figure 8) ACU_FM to SIDIP bus to VGA_FM (Figure 10) The transfer rate depends on the camera clock used. ACU_FM to VGA_FM (Figure 7) 6) Transfer rate: 25 Mb/sec (8 bits). ACU_FM to