1996_TI_Data_Transmission_Circuits_Vol_2_Communications_Controllers_Data_Book 1996 TI Data Transmission Circuits Vol 2 Communications Controllers Book

User Manual: 1996_TI_Data_Transmission_Circuits_Vol_2_Communications_Controllers_Data_Book

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~TEXAS

INSTRUMENTS

Data Transmission Circuits
Communications Controllers
.

1996
-=================~==

Mixed-Signal Products

General Information

III

~~~~~~~~

UARTs

UART Product Previews

~~~~~~~~~~

~IE=E=E-=13=9=4================~1II
IEEE-1394 Product Previews

~M=e=c=h=a=n=ic=a=I=D=at=a================~1I!I

Data Transmission Circuits
Data Book
Volume 2

Communications Controllers

•
TEXAS
INSTRUMENTS

Fl'lnlld on fIecycIecI ....,..

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems. necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or Infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri

INTRODUCTION
In the 1996 Data Transmission Circuits Data Book, Volume 2, the Mixed-Signal Products
Division of Texas Instruments (TI) presents technical information on various products for
electronic media and electronic devices.
The TI data transmission circuits represent technologies from classic bipolar through Advanced
Low-Power Schottky (ALS), IMPACTTM, LinBiCMOSTM, CMOS, and BiMOS processes. The ALS
and IMPACT oxide-isolated technologies provide the data transmission family with improved
speed-power characteristics.
This data book provides information on the following types of products:
•

UARTs

•

Plug-and-play compatible devices

•

Infrared serial data inputs and outputs

•

IEEE 1394-1995.

Among the new products offered by TI within the 1996 Data Transmission Circuits Data
Book, Volume 2 are:
•

TL 16PNP1 OOA - a standalone plug-and-play controller.

•

TL 16PNP550A - the industry's first UART with plug-and-play capability.

•

TL 16C750 - a UART with a 64-byte FIFO buffer that reduces the number of
interrupt requests.

•

TSB21 LV03 - a 1394 triple cable transceiver/arbiter that provides three fully
compliant cable ports at 100/200 Mbits/s

•

TSB11 LV01 - a 1-port 1394 cable transceiver/arbiter for 3-V supply operation at
100 Mbits/s

•

TSB14C01 - a 1-port 1394 backplane transceiver/arbiter that provides the
transceiver functions needed to implement a single port node at 50/1 00 Mbits/s in a
backplane-based 1394 network.

The data book is organized for quick location of a specific data sheet. The sequence is in base
part number order (Le., TL 16C450 is located next to the TL 16C451). The alphanumeric index
provides a quick method of locating the data sheet for a known part number and indicates new
products in this edition. A preview of new products that are near release to production are
included for the first time in this data book.
The selection guide is grouped by industry standard and includes key features and the standard
device footprint of the products in each category. The cross-reference guide lists other
manufacturers' devices with the suggested TI replacement. Package mechanical information is
in the last section of the data book.

IMPACT and LinBiCMOS are a trademarks of Texas Instruments Incorporated.

While this data book offers design and specification data only for data transmission products,
complete technical data for any TI semiconductor product is available from your nearest TI Field
Sales Office, local authorized TI distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. Box 809066
DALLAS, TEXAS 75380-9066
or telephone the TI Literature Response number: 1-800-477-8924.
We sincerely believe the new 1996 Data Transmission Circuits Data Book, Volume 2 will be a
valuable addition to your collection of technical literature.

1-1

G)
(1)

:::s

...
m

(1)

--.....:::s
o...

3
m
P+

_.o
:::s

1-2

ALPHANUMERIC JNDEX

TIR1000
Standalone IrDA Encoder and Decoder ............................................ 2-3
TL16C450
Asynchronous Communications Element ........................................... 2-9
TL16C451
Asynchronous Communications Element .......................................... 2-33
TL16C452
Asynchronous Communications Element .......................................... 2-33
TL16C550A
Asynchronous Communications Element .......................................... 2-57
TL16C550B
Asynchronous Communications Element .......................................... 2-87
TL16C550C
Asynchronous Communications Element with Autoflow Control ..................... 2-117
Dual Asynchronous Communications Element with FI FO ........................... 2-151
TL 16C552
TL 16C552A
Dual Asynchronous Communications Element with FI FO ........................... 2-183
TL16C552AI
Dual Asynchronous Communications Element with FIFO ........................... 2-217
TL16C554
Asynchronous Communications Element ......................................... 2-251
Asynchronous Communications Element with 64-Byte FIFOs and Autoflow Control .... 2-281
TL 16C750
PCMCIA Universal Asynchronous Receiver Transmitter ............................ 2-315
TL 16PC564A
TL 16PIR552
Dual UART with DualirDA and 1284 Parallel Port ................................... 3-3
TL16PNP100A Standalone Plug-and-Play (PnP) Controller ...................................... 2-347
TL 16PNP200t Standalone Plug-and-Play (PnP) COntroller ........................................ 3-5
TL 16PNP550A Asynchronous Communications Element with Plug-and-Play and Autoflow Control .... 2-365
TSB11C01
IEEE 1394-1995 Triple-Cable Transceiver/Arbiter ................................... 4-3
TSB11 LV01 t
i-Port P1394 Cable Transceiver/Arbiter For 3-Volt Supply Operation .................. 5-3
TSB12C01 A
1394 High-Speed Serial-Bus Link-Layer Controller ................................. 4-21
TSB12C01AMt P1394 High-Speed Serial-Bus Link-Layer Controller ................................. 5-7
TSB14C01t
P1394 Backplane Transceiver/Arbiter For 5-Volt Supply Operation ................... 5-21
TSB14C01Mt
IEEE 1394-1995 Backplane Transceiver/Arbiter For 5-Volt Supply Operation .......... 5-23
TSB21 LV03t
P1394 Triple-Cable Transceiver/Arbiter ......................................... ,. 5-25
TSB21 LV03Mt IEEE 1394-1995 Triple-Cable Transceiver/Arbiter .................................. 5-29
t This is a product preview data sheet.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-3

SELECTION GUIDE

UARTs
DEVICE

DEVICE TYPEt

DESCRIPTIONt

PACKAGES

PAGE

TIR1000

Standalone IrDA encoder and decoder

Tl16C450

UART

Single ACE without FIFO

FN,N

2-3

TL16C451

UART

Single ACE with parallel port and without FIFO

2-33

TL16C452

UART

Dual ACE wHh parallel port and without FIFO

2-33

TL16C550A

UART

Single ACE wHh FIFO

FN,N

2-57

TL16C550B

UART

Single ACE with 16-byte FIFOs

FN,N,PT

2-87

TL16C55OC

UART

Single ACE with 16-byte FIFOs and auto flow control

FN,N,PT

2-117

TL16C552

UART

Dual ACE with 16-byte FIFOs and parallel port

2-151

TL16C552A

UART

Dual ACE with 16-byte FIFOs and parallel port

2-183

Tl16C552A1

UART

Dual ACE with 16-byte FIFOs and parallel port characterized over
industrial temperature range

2-217

Tl16C554

UART

Quadruple ACE with 16-byte FIFOs

2-251

Tl16C750

UART

Single ACE with 64-byte FIFOs, autoflow control, and low-power modes

FN,PM

2-281
2-315

2-9

Tl16PC564A

UART, PCMCIA

Single ACE with 64-byte FIFOs and PCMCIA interface

TL16PIR552§

UART,IR

Dual ACE with 16-byte FIFOs and has selectable IR and 1284 modes

nla

TL16PNP100A

PnP

Standalone PriP controller that supports two logical devices

FN,PT

TL16PNP200§

PnP

Standalone PnP controller that supports five logical devices

nla

3-5

TL16PNP550A

UART, PnP

Single ACE with 64-byte FIFOs, autoflow control, and PnP controller

2-365

3-3
2-347

t UART= universal asynchronous receiversitransmitters, PCMCIA = Personal Computer Memory Card International Association, PnP = plug and
play, IR = ifrared.
:j: ACE = asynchronous communications element, FIFO = first inlfirst out, IrDA = Infrared Data Association

§ The data sheet for this device is product preview.

:'I
TEXAS
INSTRUMENTS
1-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

SELECTION GUIDE

IEEE 1394-1995
DEVICE

PACKAGE

PAGE

TSB11C01

Triple-cable transceiver/arbHer

DESCRIPTION

4--3

TSB11LV01t

Triple-cable transceiver/arbiter

5-3

TSB12C01A

High-speed serial-bus link-layer controller

4-21

TSB12C01AMt

High-speed serial-bus link-layer controller

5-7

TSB14C01t

P1394 Single-Port Backplane Transceiver/Arbiter For 5-Volt Supply Operation

5-21

TSB14C01Mt

P1394 Single-Port Backplane Transceiver/Arbiter For 5-Volt Supply Operation

TSB21 LV03t

Triple-cable transceiver/arbiter

TSB21 LV03Mt
Triple-cable transceiver/arbiter
The data sheet for this device is product preview.

5-23

5-25

5-29

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-5

1-6

I UARTs

2-1

2-2

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
-REVISED

PSPACKAGE
(TOP VIEW)

• Adds Infrared (IR) Port to Universal
Asynchronous Receiver Transmitter
(UART)
• Compatible with Infrared Data Association
(IrDA) & Hewlett Packard Serial Infrared
(HPSIR)
•
•
•
•
•

Provides 1200 bps to 115 kbps Data Rate
Uses 2.7-V to 5.5-V Supply
Provides Simple Interface With UART
Decodes Negative or Positive Pulses
Available in 8-Pln Small Outline Package
(SOP)

functional block diagram

Decoder

description
The TIR1000 serial infrared (SIR) encoder!
decoder is a CMOS device which encodes and
decodes bit data in conformance with the IrDA
specification.

Encoder

A transceiver device is needed to interface to the
photo-sensitive diode (PIN) and the light emitting
diode (LED). A UART is needed to interface to the
serial data lines.

Terminal Functions
TERMINAL
NAME
16XCLK

NO.
1

I/O

DESCRIPTION

Clock signal. 16XCLK should be set to 16 times the baud rate. The highest baud rate for IrDA is 115.2 kbps, for
which the clock frequency equals to 1.843 MHz (this terminal is tied to the BAUDOUT of a UART).

GND

IR_RXD

Ground
Infrared receiver data. IR_RXD is IRDA·SIR modulated input from an optoelectronics transceiver whose input
pulses should be 3116 of the baud rate period.

I~TXD

Infrared transmitter data. IR_TXD is IRDA·SIR modulated output to an optoelectronics transceiver.

RESET

Active high reset. RESET inHializes a IRDA·SIR decode/encode state machine (this terminal is tied to a UART
reset line).

U_RXD

Receiver data. U_RXD is decoded (demodulated) data from
tied to SIN of a UART).

U_TXD

Transmitter data. U_TXD is encoded (modulated) data and output data as IR_TXD (this terminal is tied to SOUT
from a UART).

VCC

I~RXD per the

IRDA specification (this terminal is

Power supply. The VCC requirement is 2.7 V to 5.5 V

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265

2·3

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
SLLS228A - DECEMBER 1995 - REVISED FEBRUARY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Supply voltage range, Vee (see Note 1) ............................................... -0.5 V to 6 V
Input voltage range at any input, VI ............................................ -0.5 V to Vee + 0.5 V
Output voltage range, Vo .................................................... -0.5 V to Vee + 0.5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Case temperature for 10 seconds: SOP package ............................................. 260°C

Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxi mum-rated conditions for ex1ended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.

recommended operating conditions over recommended operating free-air temperature range
low voltage (3 V nominal)
Supply voltage, VCC
High-level input voltage, VIH

MIN

NOM

MAX

2.7

3.3

0.2VCC

°c

0.7VCC

LOW-level input voltage, VIL
Operating free-air temperature, TA

UNIT

standard voltage (5 V nominal)
Supply voltage, VCC
High-level input voltage, VIH

MIN

NOM

MAX

UNIT

4.75

5.25

V
V

0.7VCC

LOW-level input voltage, VIL
Operating free-air temperature, TA

0.2VCC

°C

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

TYP

MAX

UNIT

VCC=5V

VCC-0.8

IOH=-1.8mA

VCC=3V

VCC-0.55

IOL=+4rnA

VCC=5V

0.5

IOL=+1.8mA

VCC=3V

0.5
±1

IJA

MHz

VOH

High-level output voltage

VOL

LOW-level output voltage

Input current

VI=OtoVCC,

All other pins floating

ICC

Supply current

VCC = 5.25 V,
All inputs at 0.2 V,
No load on outputs

TA=25°C,
16XCLK at 2 Mhz,

Ci(16XCLK)

Clock input capacitance

f(16XCLK)

Clock frequency

~TEXAS

POST OFFICE BOX 6553!l3 • DALLAS. TEXAS 75265

INSTRUMENTS
2-4

MIN

IOH=-4mA

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
SLLS228A- DECEMBER 1995 - REVISED FEBRUARY 1996

switching characteristics
PARAMETER

TEST CONDITIONS

MIN

TYpt

MAX

UNIT

I Output rise time

G(LOAD) = 15 pF (10% to 90%)

1.3

I Output fall time

G(LOAD)= 15 pF (90% to 10%)

1.8

t Typical values are at TA = 25°G.

APPLICATION
Optoelectronics

TIR1000

TL16C550C UART

U_TXD

SOUT

To LED 4 - - IR_TXD
From
PIN

--+

U_RXD

SIN

IR_RXD
16XCLK
RESET

BAUDOUT

RESET

Figure 1. Typical application of the TIR1 000

PRINCIPLES OF OPERATION
IrDA overview
The Infrared Data Association (IrDA) defines several protocols for sending and receiving serial infrared data,
including rates of 115.2 kbps, 0.576 Mbps, 1.152 Mbps, and 4 Mbps. The low rate of 115.2 kbps was specified
first and the others must maintain downward compatibility with it. At the 115.2 kbps rate, the protocol
implemented in the hardware is fairly simple. It primarily defines a serial infrared data "word" to be surrounded
by a start bit equal to 0 and a stop bit equal to 1. Individual bits are encoded or decoded the same whether they
are start, data, or stop bits. The TIR1 000 evaluates only single bits and only follows the 115.2 kbps protocol.
The 115.2 kbps rate is a maximum rate. When both ends of the transfer are set up to a lower but matching speed,
the protocol (with the TIR1 000) still works. The clock used to code or sample the data is 16 times the baud rate,
or 1.843 Mhz maximum. To code a 1, no pulse is sent or received for 1-bit time period, or 16 clock cycles. To
code a 0, one pulse is sent or received within a 1-bit time period, or 16 clock cycles. The pulse must be at least
1.61JS wide and 3 clock cycles long at 1.843 Mhz. At lower baud rates the pulse can be 1.6 ~s wide or as long
as 3 clock cycles. The transmitter output, IR_TXD, is intended to drive a LED circuit to generate an infrared
pulse. The LED circuits work on positive pulses. A PIN circuit is expected to create the receiver input, IR_RXD.
Most, but not all, PIN circuits have inversion and generate negative pulses from the detected infrared light. Their
output is normally high. The TIR1000 can decode either negative or positive pulses on IR_RXD.

~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-5

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
SLLS228A - DECEMBER 1995 - REVISED FEBRUARY 1996

PRINCIPLES OF OPERATION

IrDA encoder function
Serial data from a UART is encoded to transmit data to the optoelectronics. While the serial data input to this
block (U_TXD) is high, the output (IR_TXD) is always low, and the counter used to form a pulse on IR_TXD is
continuously cleared. After U_TXD resets to 0, IR_TXD rises on the falling edge of the seventh 16XCLK. On
the falling edge of the tenth 16XCLK pulse, IR_TXD falls, creating a 3-clock-wide pulse. While U_TXD stays
low, a pulse is transmitted during the seventh to tenth clocks of each 16-clock bit cycle.

U_TXD

-----+----II------!~

If-I
I

Figure 2. IrDA-SIR Encoding Scheme Detailed Timing Diagram

Figure 3. Encoding Scheme - Macro View

IrDA decoder function
After reset, U_RXD is high and the 4-bit counter is cleared. When a falling edge is detected on IR_RXD, U_RXD
falls on the next rising edge of 16XCLK with sufficient setup time. U_RXD stays low for 16 (16XCLK) cycles and
then returns to high as required by the IrDA specification. As long as no pulses (falling edges) are detected on
IR_TXD, U_RXD stays high.

1_ _ _ _ _ _ _---;._

I
I

-II

16XCLK

IR_RXD

123456

U_RXD

I 16 Cycles I 16 Cycles I 16 Cycles I

1 :

;1~~1--------------~
II
I

U_RXD

Figure 4. IrDA-SIR Decoding Scheme Detailed Timing Diagram

II
~

1 'I
I

I
I

II
~

Figure 5. Decoding Scheme - Macro View

~TEXAS

INSTRUMENTS
2-6

16 Cycles

16XCLK _ _ _ _ _ _

IR_RXDH

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
SLLS228A - DECEMBER 1995 - REVISED FEBRUARY 1996

PRINCIPLES OF OPERATION
It is possible for jitter or slight frequency differences to cause the next falling edge on IR_RXD to be missed for
one 16XCLK cycle. In that case, a 1-clock wide pulse appears on U_RXD between consecutive zeroes. It is
important for the UART to strobe U_RXD in the middle of the bit time to avoid latching this temporary value. The
TL 16C550C UART already strobes incoming serial data at the proper time. Otherwise, note that data is required
to be framed by a leading zero and a trailing one. The falling edge of that first zero on U_RXD synchronizes the
read strobe. The strobe is on the eighth 16XCLK pulse after the U_RXD falling edge and once every 16 cycles
thereafter until the stop bit occurs.

IR_RXD

L-Jri-i---------iliU..-----------

16XCLK
1

U_RXD

--l~----r-------------------~
I

Figure 6. Timing Causing 1-clock Wide Pulse Between Consecutive Ones

14----

16XCLK

IR_RXD

U_RXD

16 Cycles

-----.I 14--

16 Cycles

---.I

I
I
II
I
I
I
II
I
I

lJ
I

W
II

H
II

External"Strobe:

7Cycles

III I

. 1 " ' 1 6 Cycles
I

p. . .----+-

---.:

Figure 7. Recommended Strobing For Decoded Data

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-7

TIR1000
STAND-ALONE IrDA ENCODER AND DECODER
SLLS228A - DECEMBER 1995 - REVISED FEBRUARY 1996

PRINCIPLES OF OPERATION
The TIR1000 can also decode positive pulses on IR_RXD. The timing is different, but the variation is invisible
to the UART. Because the decoder works from the falling edge, it now recognizes a zero on the trailing edge
of the pulse rather than on the leading edge. As long as the pulse width is fairly constant, as defined by the
specification, the trailing edges should also be 16 clock cycles apart and data can readily be decoded. The zero
appears on U_RXD after the pulse rather than at the start of it.

16XCLK

I 11
U_RXD

-r---:H,..I______________. . . .I
Figure 8. Positive IR_RXD Pulse Decode - Detailed View

'+- Cycles
16
---..!.- 16 --.t.- 16 ---..!.- 16 ~
I Cycles
I
Cycles
I Cycles
I

16XCLK _ _ _ _

I
I

IR_RXD~

I
U_RXD - ,

I
I

Inn
I

II
I

Figure 9. Positive IR_RXD Pulse Decode - Macro View

~TEXAS

INSTRUMENTS
2·8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

I
I

I
r
I

I
I
I

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
NPACKAGE
(TOP VIEW)

• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 16 -1) and Generates an Internal16x
Clock

Vee

D1
D2

• Full Double Buffering Eliminates the Need
for Precise Synchronization
• Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream

DCD
DSR
CTS
MR

D7
RCLK
SIN

• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

OUT1
DTR
RTS
OUT2
INTRPT
NC

CSO
CS1
CS2
BAUDOUT
XTAL1
XTAL2
DOSTR
DOSTR

• Fully Programmable Serial Interface
Characteristics:
- 5-,6-,7-, or a-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation
and Detection
- 1-,1 1/2-, or 2-Stop Bit Generation
- Baud Generation (dc to 256 Kbitls)

AO
A1
A2
ADS
CSOUT
DDIS
DISTR
DISTR

Vss

• False Start Bit Detection
• Complete Status Reporting Capabilities

FNPACKAGE
(TOP VIEW)

• 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus

'¢:...4< -r...f¢ ::... :
1

CSO,CS1,CS2

th3~

~tcl3

11 1)90%
1

~tc13

1i~9O%

---+I--IJI
14- twe~
1
1
I+- tcl4t ~
j4- th4t~
DOSTR,
OOSTR

~~t~~_c-~
10%{\
I

14- tsU3-¥- thS-+l
00-07

-------«

9O%Vaiid Oata9O%))---

t Applicable only when ADS Is tied low.

Figure 2. Write Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·17

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PARAMETER MEASUREMENT, INFORMATION
14--~~Ir- tW5

I
10%

10%

. i4--AO-A2

tsu1-.1

:
=X=

-.!

-%-{C

~ltsU2

1l1li

I+- th1

Von. 1<'--v-a-lId-t10

I4-th2

CSO, CS1, CS2
10%

l+*CSOUT

td3t

:)90%

---+--+,1·
I 14-

i~90%

14- tw7-.!

~ th7t~

td7t-+j

14- ldat-.l

DISTR,
DISTR

~ td3t

I4---td9

_____....J~?:::~'-----I

ldis(R) ~

\.!

- - - - - - 1 - 1.....
DDIS

:10%'\

~ tdls(R)

I
:

~O%

I
I
i+ td10-.l !4-- ld11---.i
00-07 _ _ _ _ _ _ _ _--«90% Valid Data

t Applicable only when ADS is tied low.

Figure 3. Read Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
2-18

POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
RCLK

--fl~

--f1fL
I
~ ~ fct12

8CLKs

SAMPLE
CLOCK

SIN \

;=n:t:-B-;~

Start

Parity

Stop

SAMPLE
CLOCK

~~.

INTRPT
_____________________________________
(RORlLSI)

d1 3
t .
·
90%
10%

td14~
OISTR, OISTR
(RO RBRlLSR)

__________________________________~)( Ac3~~~
Figure 4. Receiver Timing Waveforms

SOUT

100/\ Start

ro:;~~

Parity

Stop

~
INTRPT """""\.
(THRE) 10%\-

td17

~ 14- ~

td15

90%

fW~~~T~~O%

500/~

~I~------"\.-

90%

I' 50%

td18

loiii

td16

I
-.I 14- td17

50%

~
I
I

____________________________

_+.----I

td19~ j4-

OISTR (RO IIR) ___________________________________________________

Figure 5. Transmitter Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·19

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
DOSTR (WR MeR)

~td20

td20

~~O_%_______________________9JO~

RTS,DTR
OUT1,OUT2

_____________J~~~10~%~-------------------------
td21
INTRPT
(MODEM)

-.I !+-

50%~50%

______________9Oj/
J

*:4---I~~
DISTR (RD MSR)

I
td22

/,....-50'l-~'\
--------------~.

I
I

\~_ _ __J9°7
Figure 6. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
2-20

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

td21

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

APPLICATION INFORMATION
::>"'"
D7-oo

RTS
DTR
INTRPT

RESET

DSR

AO
A1

B
u
s

..-L

CTS

TL16C450
(ACE)

ADS

XTAL1

DOSTR

.DISTR

-"-

DCD

EIA232-D
Drivers
and
Receivers

DOSTR

INTR

SIN

DISTR

MEMW or liON

SOUT

D7-DO

MEMRor I/OR

CS2

XTAL2

CS1

BAUDOUT

cso

RCLK

3.072
MHz

1
7

L...c::
Fig\lre 7. Basic TL16C450 Configuration
Receiver
Disable

~~-----'------~~--------------~DOSTR

Microcomputer
System

Data Bus

TL16C450
(ACE)

Data Bus

C+===~>I

8-BIt
Bus Transceiver

D7-DO

'--------.---------1 DDIS
Driver
Disable

Figure 8. Typical Interface for a High-Capacity Data Bus

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·21

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

APPLICATION INFORMATION
TL16C450

Alternate
Xtal Control

XTAL1f1~6------~.-__--~

A16-A23!========;--;==:::; A16-A23

XTAL2f1!.!.7------~i-~--~
12
CSO
Address
Decoder

CS1
14

BAUDOUT 15

RCLK 9

CS2
20

CPU

ADS~--~----------------------~

ADS
OUT1

ADO-AD15

K=~~:)

OUT2

AO-A2

Ri 39

DO-D7

DCD
DSR

PHI1 PHI2

CTS

PHI1 PHI2

37
36

5V
8
6
5

ADS RSTO
21
RO

TCU
WR

DISTR
18

SOUT

SIN
ADO-AD15
INTRPT

DISTR

5V
(VCC)

Figure 9_ Typical TL16C450 Connection to a CPU

2-22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NC 29

~TEXAS

DDIS 23

DOSTR

INSTRUMENTS

CSOUT
22

DOSTR

EIA-232-D
Connector

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 1. Register Selection
DLAst

Interrupt enable

Interrupt identification (read only)

Li ne control

Modem control

Line status

Modem status

Scratch

Divisor latch (LSB)

Divisor latch (MSB)

t The divisor latch access bit (DLAB) IS the most significant bit of the line control register. The DLAB signal
by writing to this bit location (see Table 3).

controlled

Table 2. ACE Reset Functions
REGISTER/SIGNAL

RESET
CONTROL

RESET STATE

Interrupt enable register

Master reset

All bits low (0-3 forced and 4-7 permanent)

Interrupt identification register

Master reset

Bit 0 is high, bits 1 and 2 are low, and bits 3 -7 are
permanently low
All bits low

Line control register
Modem control register

Master reset

All bits low

Line status register

Master reset

Bits 5 and 6 are high, all other bits are low

Modem status register

Master reset

Bits 0-3 are low, bits 4-7 are input signals

SOUT

Master reset

High

INTRPT (receiver error flag)

Read LSRlMR

Low

INTRPT (received data available)

Read RBRlMR

Low

INTRPT (transmitter holding register empty)

Read IIRlWrite
THRlMR

Low

INTRPT (modem status changes)

Read MSRlMR

Low

OUT2

Master reset

High

RTS

Master reset

High

DTR

Master reset

High

OUT1

Master reset

High

Scratch register

Master reset

No effect

Divisor latch (LSB and MSB) register

Master reset

No effect

Receiver buffer register

Master reset

No effect

Transmitter holding register

Master reset

No effect

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-23

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.

Table 3. Summary of Accessible Registers
REGISTER ADDRESS

Bit
No.

ODLAB=O

1 DlAB=O

ODlAB=l

1
DlAB
=0

Receiver
Buffer
Register
(Read
Only)

Transmitter
Holding
Register
(Write
Only)

Interrupt
Enable
Register
IER

Interrupt
Ident.
Register
(Read
Only)

line
Control
Register
lCR

Modem
Control
Register

line
Status
Register

Modem
Status
Register

Scratch
Register

Divisor
latch
(lSB)

Latch
(MSB)

RBR

THR

IER

IIR

lCR

MCR

lSR

MSR

SCR

Dll

DlM

Data Bit 0

Enable
Received
Data
Available
Interrupt
(ERBF)

"0" If
Interrupt
Pending

Word
Length
Select
Bit 0
(WLSO)

Data
Terminal
Ready
(DTR)

Data
Ready
(DR)

Delta
Clear
to Send
(DCTS)

Bit 0

Bit 8

Data Bit I

Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBE)

Interrupt
10
Bit (0)

Word
Length
Select
Bill
(WLSI)

Requesl
to Send
(RTS)

Overrun
Error
(OE)

Delta
Data
Set
Ready
(DDSR)

Bit I

Bil9

Data Bit 2

Enable
Receiver
LineSlatus
Inlerrupt
(ELSI)

Interrupt
10
Bit(l)

Number of
Slop Bils
(STB)

Outl

Trailing
Edge Ring
Indicalor
(TERI)

Bit 2

Bil2

Bit 10

Oul2

Delta
Data
Carrier
Detect
(DDCD)

Bit3

Bit 3

Bit II

Data Bit O·

DalaBil1

Data Bil2

Parity

Error
(PE)

Enable
Modem

Data Bit 3

Dala Bit 3

Status
Interrupt
(EDSSI)

Partty
Enable
(PEN)

Data Bit 4

Even
Parity
Select
(EPS)

Loop

Break
Interrupl
(BI)

Clear
to Send
(CTS)

Bit4

Bit 4

Bit 12

Dala BitS

Data BilS

Stick
Parity

Transmitter
Holding
Register
(THRE)

Data
Set
Ready
(DSR)

BitS

Bit 13

Data Bil6

Transmitter
Empty
(TEMT)

Ring
Indicalor
(RI)

Bit 6

Bil6

Bit 14

Data Bit 7

Data Bit7

Data
Carrier
Delect
(DCD)

Bit 7

Bil7

BillS

Framing

Set
Break

Divisor
Latch
Access
Bil
(DLAB)

Error
(FE)

*Blt 0 IS the least Sl9n1flcant bit. It IS the first bit senally transmitted or received.

~TEXAS

INSTRUMENTS
2-24

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each ofthe four types of interrupts (refer to Table 4) and the INTRPT output signal in response
to an interrupt generation. By clearing bits 0 - 3, the IER can also disable the interrupt system. The contents
of this register are summarized in Table 3 and are described in the following bulleted list.
•

Bit 0: This bit, when set, enables the received data available interrupt.

•

Bit 1: This bit, when set, enables the THRE interrupt.

•

Bit 2: This bit, when set, enables the receiver line status interrupt.

•

Bit 3: This bit, when set, enables the modem status interrupt.

•

Bits 4 - 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of interrupt in its three
least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and described
in Table 4.
•

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When bit 0 is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.

•

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.

•

Bits 3 - 7: These bits in the IIR are not used and are always clear.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-25

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B- MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

interrupt identification register (IIR) (continued)
Table 4. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT2

BIT 1

BITO

PRIORITY
LEVEL

INTERRUPT TYPE

None

INTERRUPT SOURCE

INTERRUPT RESET
METHOD

None

Receiver line status

Overrun error, parity error,
framing error or break
interrupt

Received data available

Receiver data available

Transmitter holding register
empty

Reading the interrupt
identification register (if
source of interrupt) or writing
into the transmitter holding
register

Clear to send, data set
ready, ring indicator, or data
carrier detect

Reading the modem status
register

Transmitter holding register
empty

Modem status

Reading the line status
register
Reading the receiver buffer
Buffer register

line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCA. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
•

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 5.

Table 5. Serial Character Word Length
Bit 1

BitO

Word Length

0
0
1

0
1

5 Bits

0
1

7 Bits

•

6 Bits
8 Bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver checks the first stop bit only,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 6.

~TEXAS

INSTRUMENTS
2-26

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 6. Number of Stop Bits Generated
Bit 2

Word Length Selected
by Bits 1 and 2

Any word length

5 bits

1 1/2

6 bits

7 bits

8 bits

Number of Stop
Bits Generated

•

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, if bit 3 is set, parity is checked. When bit 3 is
cleared, no parity is generated or checked.

•

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s is in the data and parity bits) is selected. When parity is enabled (bit 3 is set)
and bit 4 is clear, odd parity (an odd number of logic 1s) is selected.

•

Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.

•

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, Le, a condition where the serial
output terminal (SOUT) is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition
is disabled. The break condition has no affect on the transmitter logic, it only affects the serial output.

•

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the IER.

line status register (LSR)t
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and are described in the following bulleted list.
•

Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR and is cleared by reading the RBR.

•

Bit 1:1:: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator
is cleared every time the CPU reads the contents of the LSR.

•

Bit 3:1:: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
does not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.

•

Bit4:1:: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR.

t The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
:j: Bits 1 through 4 are the error conditions that produce a receiver line-status interrupt.

-!II

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·27

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION'
line status register (LSR)t (continued)
•

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU.

•

Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the transmitter shift
register are both empty. When either the THR or the transmitter shift register contains a data character, the
TEMT bit is cleared.

•
Bit 7: This bit is always clear.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
•

Bit 0: This bit (OTR) controls the data terminal ready (OTR) output. Setting bit 0 forces the OTR output to
its active state (low). When bit 0 is clear, OTR goes high.

•

Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit D's control over
the OTR output.

•

Bit 2: This bit (OUT1) controls the output 1 (OUT1) signal, a user designated output signal, in a manner
identical to bit D's control over the OTR output.

•

Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user designated output signal, in a manner
identical to bit D's control over the OTR output.

•

Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When bit 4 is set, the
following occurs:
1.
2.

3.
4.
5.

The SOUT is asserted high.
The SIN is disconnected.
The output of the transmitter shift register is looped back into the RSR input.
The four modem control inputs (CTS, OSR, OCO, and RI) are disconnected.
The four modem control outputs (OTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
The four modem control output terminals are forced to their inactive states (high).

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational but the modem control interrupt sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
•

Bits 5 through 7: These bits are clear.

t The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

-!11

TEXAS
INSTRUMENTS
2-28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75266

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change
information; when a control input from the modem changes state the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
•

Bit 0: This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.

•

Bit 1: This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status interrupt is
enabled, a modem status interrupt is generated.

•

Bit 2: This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.

•

Bit 3: This bit is the delta data carrier detect (DDCD) indicator. Bit 3 indicates that the DCD input to the chip
has changed state since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.

•

Bit 4: This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (RTS).

•

Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCR bit 0 (DTR).

•

Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCRs bit 2 (OUT1).

•

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCRs bit 3 (OUT2).

programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz
and divides it by a divisor in the range between 1 and (2 16 -1). The output frequency of the baud generator is
sixteen times (16x) the baud rate. The formula for the divisor is:
divisor #

=XTAL 1 frequency input +

(desired baud rate x 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in orderto ensure desired operation ofthe baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 7 and 8 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz,
respectively. For baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy
of the selected baud rate is dependent on the selected crystal frequency.
Refer to Figure 10 for examples of typical clock circuits.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-29

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 7. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE

DIVISOR USED
TO GENERATE
16xCLOCK

50
75
110
134.5

2304
1536
1047
857

150

768
384
192

300
600
1200
1800
2000
2400

PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL

0.026
0.058

96
64
58
48
32
24
16

3600
4800
7200
9600
19200
38400
56000

0.69

12
6
3
2

2.86

Table 8. Baud Rates Using a 3.072-MHz Crystal
DESIRED
BAUD RATE

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIVISOR USED
TO GENERATE
16xCLOCK

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

~TEXAS

2-30

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL

0.026
0.034

0.312

0.628
1.23

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

Driver
External
Clock

XTAL1

Optional
Oscillator Clock
to Baud
1 - - 1 - - - - - - - - - - t t - - - - . Generator
Logic
L -____________________________________

Optional
Clock
Output

XTA~

VCC

XTAL1
lC1

> Rp

-=-

Crystal

-,-

-=Oscillator Clock
to Baud
Generator
Logic

RX2

XTAL2
C2

TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL

Rp
1 MQ

RX2

3.1 MHz

1.5kQ

10-30 pF

40-60 pF

1.8MHz

1 MQ

1.5kQ

10-30 pF

40-60 pF

Figure 10. Typical Clock Circuits

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

2-31

TL16C450
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS037B - MARCH 1988 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register and a RBA. Timing is supplied by the 16x receiver
clock (RCLK). Receiver section control is a function of the ACE line control register.
The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift
register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the
RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared
when the data is read out of the RBA.

scratch register
The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that
it temporarily holds programmer data without affecting any other ACE operation.

transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud
out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register.
The ACE THR receives data from the internal data bus and, when the shift register is idle, moves it into the
transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output
(SOUT). If the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt
is generated. This interrupt is cleared when a character is loaded into the register.

~TEXAS

INSTRUMENTS
2-32

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B- MAY 1989 - REVISED MARCH 1996

• Integrates Most Communications Card
Functions From the IBM PC/ATTM or
Compatibles With Single- or Dual-Channel
Serial Ports
• TL 16C451 Consists of One TL 16C450 Plus
Centronix Printer Interface
• TL 16C452 Consists of Two TL 16C450s Plus
a Centronix-Type Printer Interface

• Fully Programmable Serial Interface
Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation
and Detection
- 1-, 1 1/2-, or 2 Stop-Bit Generation
- Programmable Baud Rate
(dc to 256 kbitls)
• Fully Double Buffered for Reliable
Asynchronous Operation

description
The TL 16C451 and TL 16C452 provide single- and dual-channel (respectively) serial interfaces along with a
single Centronix-type parallel-port interface. The serial interfaces provide a serial-to-parallel conversion for data
received from a peripheral device or modem and a parallel-to-serial conversion for data transmitted by a CPU.
The parallel interface provides a bidirectional parallel data port that fully conforms to the requirements for a
Centronix-type printer interface. A CPU can read the status of the asynchronous communications element
(ACE) interfaces at any point in the operation. The status includes the state of the modem signals (CTS, DSR,
RLSD, and RI) and any changes to these signals that have occurred since the last time they were read, the state
of the transmitter and receiver including errors detected on received data, and printer status. The TL 16C451
and TL 16C452 provide control for modem signals (RTS and DTR), interrupt enables, baud rate programming,
and parallel-port control signals.

IBM PC/AT is a trademark of International Business Machines Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily Include
testing of al/ parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-33

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B- MAY 1989- REVISED MARCH 1996

TL16C451 ... FN PACKAGE
(TOP VIEW)

9 8 765 4 3 2 1 68 67 66 65 64 63 62 61

NC
NC
NC
GND
DBO

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

~1~181~1~1~
~ ~ ~I~I~I~I~
8~ ~~
~o
--offi>w~~

~~~

NC - No internal connection

~TEXAS

2-34

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

NC
INT2
SLIN
INIT
AFD
STB
GND
PDO
PD1
PD2
PD3
PD4
PD5
PD6
PD7
INTO
BDO

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B- MAY 1989 - REVISED MARCH 1996

TL 16C452 ... FN PACKAGE

(TOP VIEW)

9 8 7 6 5 4 3 2

1 68 67 66 65 64 63 62 61

INT1
59 INT2

SOUT1

58
57
56

DB1

12
13
14
15
16
17
18

55
54
53
52
51
50
49
48
47
46
45
44

PD2
PD3
PD4

PD7

VM~~~~~~~~~~~~~~~

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-35

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

TL 16C451 functional block diagram
TL16C451
28
31
29
30
41
32
14-21

CTSO
DSRO
RLSDO
RIO
SINO
CSO
8/

DBO-DB7
AO-A2
lOW
lOR
RESET
CLK

24
25
26
45

ACE
1

RTSO
DTRO
SOUTO
INTO

33-35
36
37
39
3

~
Select
and
Control
Logic

BOO

/.,2,
63
65
66
67
68
1
38

ERROR
SLCT
BUSY
PE
ACK
LPTOE
CS2

53-46
57
Parallel
Port

56
...

PDO-PD7
INIT
AFD
STB

SUN

INT2

TL 16C452 functional block diagram
TL16C452
28
31
29
30
41
32
14-21

CTSO
DSRO
RLSDO
RIO
SINO
CSO
DBO-DB7

ERROR
SLCT
BUSY
~
ACK
LPTOE
CS2

24
25
26
45

RTSQ
DTRO
SOUTO
INTO

ACE
2

12
11
10
60

RTS1
DTR1
SOUT1
INT1

BOO

13
5
8
6
62
4

CTS1
DSR1
RLSD1
RI1
SIN1
CS1

AO::::Ag
lOW
lOR
RESET
CLK

ACE
1

3 /

33-35
36
37
39
4

...
Select
and
Control
Logic

8
10...

63
65
66
67
68
1
38

Parallel
Port

53-47
57
56
55

58
59

~TEXAS

INSTRUMENTS
2-36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PDO-PD7
INIT
AFD
STB
SLIN
INT2

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NAMEt

NO.

1/0

DESCRIPTION

35
34
33

A1
A2

Register select. AO, A 1, and A2 are used during read and write operations to select the register to read
from or write to. Refer to Table 1 for register addresses, also refer to the chip select signals (CSO, CS1,
CS2).

ACK

Printer acknowledge. ACK goes low to indicate that a successful data transfer has taken place. It
generates a printer port interrupt during its positive transition.

AFD

110

Printer autofeed. AFD is an open·drain line that provides the printer with a low signal when
continuous-form paper is to be autofed to the printer. An internal pullup is provided.

BDO

Bus buffer output. BDO is active (high) when the CPU is reading data. When active, this output can
disable an external transceiver.

BUSY

Printer busy. BUSY is an input line from the printer that goes high when the printer is not ready to accept
data.

ClK[VCC]

110

CSO
CS1 [ClK]
CS2

Chip selects. Each chip select enables read and write operations to its respective channel. CSO and
CS1 select serial channels 0 and 1, respectively, and CS2 selects the parallel port.

CTSO
CTS1 [GND]

28
13

Clear to send. CTSx is an active-low modem status signal. Its state can be checked by reading bit 4
(CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this Signal
has changed states since the last read from the modem status register. If the modem status interrupt
is enabled when CTSx changes state, an interrupt is generated.

DBO-DB7

14-21

110

Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information
between the Tl 16C451ITl16C452 and the CPU. DBO is the least significant bit (lSB).

DSRO
DSR1 [GND]

31
5

Data set ready. DSRx is an active-low modem status signal. Its state can be checked by reading
bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this
signal has changed states since the last read from the modem status register. If the modem status
interrupt is enabled when the DSRx changes state, an interrupt is generated.

DTRO
DTR1 [NC]

25
11

Data terminal ready. DTRx, when active (low), informs a modem or data set that the ACE is ready to
establish communication. DTRx is placed in the active state by setting the DTR bit of the modem control
register. DTRx is placed in the inactive state either as a result of a reset or during loop mode operation
or clearing bit 0 (DTR) of the modem control register.

ERROR

Printer error. ERROR is an input line from the printer. The printer reports an error by holding this line
low during the error condition.

INIT

I/O

Printer initialize. INIT is an open-drain line that provides the printer with a signal that allows the printer
initialization routine to be started. An internal pullup is provided.

INTO
INT1 [NC]

45
60

Interrupt. INTx is an active-high 3-state output that is enabled by bit 3 of the MCR. When active, INTx
informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: a receiver error, received data is available, the transmitter holding register is empty,
and an enabled modem status interrupt. The INTx output is reset (low) either when the interrupt is
serviced or as a result of a reset.

INT2

External clock. ClK connects the ACE to the main timing reference.

Printer port interrupt. INT2 is an active-high 3-state output generated by the positive transition of ACK.

It is enabled by bit 4 of the write control register.
lOR

Data read strobe. When lOR input is active (low) while the ACE is selected, the CPU is allowed to read
status information or data from a selected ACE register.

lOW

Data write strobe. When lOW input is active (low) while the ACE is selected, the CPU is allowed to write
control words or data into a selected ACE register.

Parallel data output enable. When low, lPTOE enables the write data register to the PDO- PD7 lines.
A high puts the PDO-PD7Iines in the high-impedance state allowing them to be used as inputs. lPTOE
is usually tied low for printer operation.

lPTOE

t Names shown In brackets are for the Tl16C451.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-37

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

Terminal Functions (continued)
TERMINAL

1/0

DESCRIPTION

53-46

I/O

Parallel data bits (0-7). These eight lines provide a byte-wide input or output port to the system. The
eight lines are held in a high-impedance state when LPTOE is high.

Printer paper empty. This is an input line from the printer that goes high when the printer runs out of
paper.

RESET

Reset. When active (low), RESET clears most ACE registers and sets the state of various output
signals. Refer to Table 2.

RIO
RI1[GND]

30
6

Ring indicator. Rlx is an active-low modem status signal. Its state can be checked by reading bit 6 (RI)
of the modem status register. Bit 2 (TERI) of the modem status register indicates that the Rlx input has
transitioned from a low to a high state since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.

RLSDO
RLSD1 [GND]

29
8

Receive line signal detect. RLSDx is an active-low modem status signal. Its state can be checked by
reading bit 7 of the modem status register. Bit 3 (DRLSD) of the modem status register indicates that
this signal has changed states since the last read from the modem status register. If the modem status
interrupt is enabled when RLSDx changes state, an interrupt is generated. This bit is low when a data
carrier is detected.

RTSO
RTS1 [NC]

24
12

Request to send. When active (low), RTSx informs the modem or data sel that the ACE is ready to
transmit data. RTSx is set to its active state by setting the RTS modem control register bit and is set
to its inactive (high) state either as a result of a reset or during loop mode operations or by clearing bit
1 (RTS) of the modem control register.

SINO
SIN1 [GND]

41
62

Serial input. SINx is a serial data input from a connected communications device.

SLCT

Printerselected. SLCT is an input line from the printer that goes high when the printer has been selected.

SUN

I/O

Printer select. SUN is an open-drain line that selects the printer when it is active (low). An internal pullup
is provided on this line.

SOUTO
SOUT1 [NC]

26
10

Serial output. SOUTx is a composite serial data output to a connected communication device. SOUTx
is set during a reset.

STB

I/O

Printer strobe. STB is an open-drain line that provides communication synchronization between the
TL 16C451ITL16C452 and the printer. When it is active (low), it provides the printer with a signal to latch
the data currently on the parallel port. An internal pullup is provided on this line.

VCC

23,40,
64

GND

2,7,9
22,27,42,
43,54,61

NAMEt
PDO-PD7

NO.

5-V supply voltage
Supply common

t Names shown in brackets are for the TL 16C451.

~TEXAS

INSTRUMENTS
2-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS0538 - MAY 1989 - REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1 ) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI .................................................. -0.5 V to 7 V
Output voltage range, Vo .......................................................... -0.5 V to 7 V
Continuous total power dissipation ...................................................... 1100 mW
Operating free-air temperature range, TA ............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, T e ...................................................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

UNIT

4.75

5.25

V
V

-0.5

VCC
0.8

°c

High-level Input voltage, VIH
low-level Input voltage, Vil
Operating free-air temperature, TA

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

TYpt

MAX

UNIT

IOH = -0.4 rnA on DBO-DB?
VOH

High-level output voltage

IOH = -2 rnA to 4 rnA on PDO-PD?
IOH = -0.2 rnA on INIT,

AFD, STB, and SUN

2.4

IOH = -0.2 rnA on all other outputs
IOl = 4 rnA on DBO-DB?
IOl = 12 rnA on PDO-PD?
VOL

low-level output voltage

IOl = 10 rnA on INIT,
AFD, STB, and SUN (see Note 2)

0.4

±10

flA

±20

flA

rnA

IOl = 2 rnA on all other outputs
Ilkg

Input leakage current

VCC = 5.25 V,
VI = 0 to 5.25 V,
ing

VSS =0,
All other terminals float-

loz

High-impedance output current

VCC = 5.25 V,
VSS=O,
Vo = 0 to 5.25 V,
Chip selected and in write mode, or chip deselected

ICC

Supply current

VCC = 5.25 V,
VSS = 0,
SIN, DSR, RlSD, CTS, and AT at 2 V,
XTAll at 4 MHz,
All other inputs at 0.8 V,
Baud rate = 50 kbitls
No load on outputs,

CXTAL1

Clock input capacitance

CXTAL2

Clock output capacitance

Input capacitance

Output capacitance

VCC = 0,
VSS=O,
TA = 25°C,
f= 1 MHz"
All others terminals grounded

All typical values are at VCC = 5 V, TA = 25°C.
NOTE 2: INIT, AFD, STB, and SUN are open-collector output terminals that each have an internal pull up to VCC. This generates a maximum of
2 rnA of internallOl per terminal. In addition to this internal current, each terminal sinks at least 10 rnA while maintaining the VOL
specification of 0.4 V maximum.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-39

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER

FIGURE

MIN

MAX

UNIT

tcR

Cycle time, read (tw7 + td8 + td9)

175

tcw

Cycle time, write (tw6 + td5 + td6)

175

tw1

Pulse duration, clock i

tw2

Pulse duration, clock J,

tW5

Pulse duration, write strobe (lOW) i

tw6

Pulse duration, read strobe (lOR) J,

twRST

Pulse duration, reset

1000

tsu1

Setup time, address (AD - A2) valid before lOW J,

2,3

tsu2

Setup time, chip select (CSx) valid before lOW J,

2,3

tsu3

Setup time, data (DO - 07) valid before lOW i

th1

Hold time, address (AD - A2) valid after lOW i

2,3

th2

Hold time, chip select (CSx) valid after lOW i

2,3

th3

Hold time, data (DO - 07) valid before lOW i

td3

Delay time, write cycle (lOW) i to lOW J,

td4

Delay time, read cycle (lOR) i to lOR J,

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER

FIGURE

TEST CONDITIONS

td5

Delay time, data (DO - 07) valid before read (lOR) i

CL = 100 pF

1e16

Delay time, floating data (DO - 07) valid after read (lOR) i

CL= 100pF

leIis(R)

Read to driver disable, lOR J, to BOO J,

CL = 100 pF

MIN

MAX

UNIT

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER

1e17

FIGURE

Delay time, RCLK i to sample clock i

TEST CONDITIONS

MIN

td8

Delay time, stop (sample clock) i to set interrupt (INTRPT) i

td9

Delay time, read RBRlLSR (lOR) i to reset interrupt (INTRPT) J,

MAX

100
1
CL= 100pF

1
140

UNIT

ns
RCLK
cycles
ns

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

td10

Delay time, initial write THR (lOW) i to transmit start (SOUT) J,

baudout
cycles

tdl1

Delay time, stop (SOUT) low to interrupt (INTRPT) i

baudout
cycles

td12

Delay time, write THR (lOW) J, to reset interrupt (INTRPT) low

td13

Delay time, initial write (lOW) ito THRE interrupt (INTRPT) i

td14

Delay time, read IIR (lOR) i to reset THRE interrupt (INTRPT)
low

~TEXAS

2-40

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CL = 100 pF
16
CL = 100 pF

140

baudout
cycles

140

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
Delay time, write MCR (lOW)

td16

set interrupt (INTRPT) high

td17

Delay time, read MSR (lOR)

MIN

MAX

UNIT

FIGURE

TEST CONDITIONS

CL= 100 pF

100

CL=100pF

170

CL=100pF

140

l' to output (RTS, DTS) ,j,l'
Delay time, modem input (CTS, DSR, RLSD) l' to

'<115

l' to reset interrupt (INTRPT) low

parallel port switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
FIGURE

TEST CONDITIONS

td18

Delay time, write parallel port control (SLlN, AFD, STB, INIT) ,j,l'
to output (lOW) high

CL= 100pF

td19

Delay time, write parallel port data (PO - P7) ,j,l' to
output (lOW) high

CL= 100pF

td20

Delay time, output enable to data, PDO - PD7 valid after LPTOE ,j,

CL= 100 pF

'<121

Delay time, ACK,j, l' to INT2 ,j,l'

CL= 100pF

100

PARAMETER

MIN

MAX

UNIT

PARAMETER MEASUREMENT INFORMATION

~tw1

I
ClK

vrr--f

r-\.2

(9 MHz Max) - - /

0.8 V

~tw2
~I

__JU-

ClK

BAUDOUT

(1/1)
(see Note A)
BAUDOUT

(112)
BAUDOUT

(113)
BAUDOUT
(1/N)
(N)3)

11-------11
_

~
I

2Clock _
Cycles
~I

L
1-

(N-2) Clock
Cycles

~-I

NOTE A: BAUDOUT is an internally generated signal used in the receiver and transmitter circuits to synchronize data.

Figure 1. Baud Generator Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

2-41

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
AO-A2

~90%

Valid

10%

10%X

1
1
1

I
CSO, CS1, CS2

X~~~
1 1
1
1

Valid

10%X

1
th2

1
1

I I I + - tws ----+i
j+1 i+------+L t
1

lOW

1 su2
I+ t su1 +1
1
1

th1 ~

1
1-1

tel3

I+I

10%(

tsu3 ~ th3--+1

90%(

)90%

Valid Data

Figure 2. Write Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
2-42

1
~
90%'--

\J,..10%

00-07

1
1
1
1

1-1

POST OFFICE BOX 655303 • DAUAS, TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
---v.-90%
AO-A2 ~ 10%

CSO, CS1, CS2

10%

--..,,:X = Vo'.
I
I

th2~

I+- th1 -+I

~ td4 ---.l~1

10~

tc!iS(R) -.:

~O%
I+-

------!..I,:

td5 --:.--.:
90%-)"
---------<\

90%' -

~ tc!is(R)
I :/ r - - - -

I \. 10% :

BOO

'-_ _

~ tWS--.!

I i+- tsu2 -+j
I+- tsu1 ~

00- 07

X
'O%1<~:____

Valid

..} 10%

I+- td6 ~
Valid Data

.r:90%

Figure 3. Read Cycle Timing Waveforms
RCLK
(internal signal only
same as BAUDOUT)

---~

-----~~I ~tc!7
Sample Clock
(internal signal only)
SIN

Sample
Clock

--------------~~
rn:a-;~~
7 \...J
Start

Parity

Stop

INTRPT
(RDRlLSI)

lOR
(RD RBRlLSR)

Figure 4. Receiver Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·43

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

10~ Start ry;:ta~~~

SOUT

tdl0
INTRPT
(THRE)

-+l

~ 11
10%

d12

--.I

I.-

IOW(WRTHR) \ . :

Parity

Stop

I+-

tdll
L

·1

10%'l....jtl0%

+-1

~50_%_ _ _ _ _ _ _ _ _ _ _ _90%~
...
50% 1

9O%1f
1

1I"

5O%W

td13

1!.- ...~ 12
':. /
-+I

10%

'L..../

td14

-+i
I

lOR (RD IIR)

Figure 5. Transmitter Timing Waveforms

90%

lOW (WR MCR)

190%

~ tellS

tellS

--f--1

---------~\9O%L
_ _ _ _ _ _ _ _ _ _ _ _9JO%~
RTS,DTR

---JX

CTS, DSR, RLSD _ _ _ _ _ _

10%

~I~-----------------------

tel16
INTRPT
(MODEM)

--j+-+I

90%1~---~~

_ _ _ _ _ _ _ _ _J

50% 1

tc!17

1 50%.

---I41..----.t.1

1
IOR(RD MSR)

"----XO%

--1

50%-.V
'--_ _----J'T

Figure 6. Modem Control Timing Waveforms

~TEXAS

2·44

j.-

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~td16

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

50%/

/50%

'-----J

td1 B "-"14e---~.1

\t~~~%---------------il~---------------i

SLIN,AFD,
STB,INIT _ _ _ _ _ _ _ _ _ _ _l:\-10%

PDQ - PD7

14
id19
",..50-%-------------------------------.\X'io,-,~""·...
"'----~~.

______________________________J~~1~0·~"'_ _ _ __

14 .: id20
L~OE ~~1~0%~________________________________________________

\110.1:.::0~%_ _ _9..J01:
id21

1NT2

td21

____~~yl~--------~

----------------------~~9~CO%

10%;

Figure 7. Parallel Port Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-45

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS0538 - MAY 1989 - REVISED MARCH 1996

APPLICATION INFORMATION

Data Bus

<../

)
ACE and
Printer
Port

Address Bus

Control Bus

Serial
Channel 0
Buffers

9-Pin
D
Conn

.........

25-Pin

Parallel
Port
RIC Net

~ Jumpers
Option ~

D
Conn

.........

Figure 8. Basic TL 16C451 Test Configuration

./
Data Bus

, Address Bus

/ ")
<..

Dual
ACE and
Printer
Port

Serial
Channel 0
Buffers

9-Pin
D
Conn

.........

./
)

Serial
Channel 1
Buffers

9-Pin
D
Conn

,
Control Bus

./
25-Pln

Parallel
Port
RIC Net

~ Jumpers
Option ~

D
Conn

.........

Figure 9. Basic TL16C452 Test Configuration '

~TEXAS

2-46

.........

)

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 1. Register Selection

DLABt

Receiver buffer (read), transmitter holding register (write)

Interrupt enable register

Interrupt identification register (read only)

Line control register

Modem control register

Line status register

Modem status register

Scratch register

Divisor latch (LSB)

Divisor latch (MSB)

The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB
signal is controlled by writing to this bit location (see Table 3).

Table 2. ACE Reset Functions
RESET
CONTROL

RESET STATE

Interrupt enable register

RESET

All bits cleared (0-3 forced and 4-7 permanent)

Interrupt identification register

RESET

Bit 0 is set, bits 1 and 2 are cleared, and bits 3-7
are permanently cleared

Line control register

RESET

All bits cleared

Modem control register

RESET

All bits cleared

Line status register

RESET

Bits 5 and 6 are set, all other bits are cleared

Modem status register

RESET

Bits 0-3 are cleared, bits 4-7 are input signals

RESET

High

SOUT
INTRPT (receiver error flag)

Read LSRlRESET

Low

INTRPT (received data available)

Read RBRIRESET

Low

Read IIRIWrite
THR/RESET

Low

INTRPT (transmitter holding register empty)
INTRPT (modem status changes)

Read MSRlRESET

Low

OUT2 (interrupt enable)

RESET

High

RTS

RESET

High

DTR

RESET

High

OUTI

RESET

High

Scratch register

RESET

No effect

Divisor latch (LSB and MSB) registers

RESET

No effect

Receiver buffer registers

RESET

No effect

Transmitter holding registers

RESET

No effect

-!!1 TEXAS

.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-47

TL16C451 ,. TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

Table 3. Summary of Accessible Registers
REGISTER ADDRESS

Bit
No.

ODLAB_O

ODLAB-O

Receiver
Buffer
Register
(Read
Only)

Transmitter
Holding
Register
(Write
Only)

RBR

Data BitOt

Data Bit 1

Data Bit 2

I DLAB_O

ODLAB=I

I DLAB=O

Interrupt
Enable
Register

Interrupt
Ident.
Register
(Read
Only)

Line
Control
Register

Modem
Control
Register

Line
Status
Register

Modem
Status
Register

Scratch
Register

Divisor
Latch
(LSB)

Latch
(MSB)

THR

IER

IIR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

Data Bit 0

Enable
Received
Data
Available
Interrupt
(ERBF)

"0" II
Interrupt
Pending

Word
Length
Select
Bit 0
(WLSO)

Data
Terminal
Ready
(DTR)

Data
Ready
(DR)

Deita
Clear
to Send
(DCTS)

BitO

Bit 0

Bit 8

Data Bit 1

Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBE)

Word
Length
Select
Bitt
(WLSI)

Request
to Send
(RTS)

Overrun
Error
(OE)

Deita
Data
Set
Ready
(DDSR)

Bit 1

Bit 9

Number 01
Stop Bits
(STB)

Out 1

Parity
Error
(PE)

Trailing
Edge Ring
Indicator
(TERI)

BH2

Bit 2

BitlO

Out 2
(Interrupt
Enable)

Framing
Error
(FE)

Delta
Receive
Line
Signal
Detect
(DRLSD)

Bit 3

Bit 11

Break
Interrupt
(BI)

Clear
to
Send
(CTS)

Bit4

Bit 4

BH 12

Data
Set
Ready
(DSR)

BitS

Bit 13

Ring
Indicator
(RI)

Bit 6

BitS

Bitt4

Receive
Line
Signal
Detect
(RLSD)

Bit 7

Bit IS

Data Bit 2

Enable
Receiver
Line Status
Interrupt
(ELSI)

Interrupt

10
Bit (0)

Interrupt

10
Bit(t)

Data Bit3

Data Bit 3

Enable
Modem
Status
Interrupt
(EDSSI)

Data Bit4

Data Bit 4

Even
Parity
Select
(EPS)

Loop

Data BitS

Data Bit 5

Stick
Parity

Data Bit6

Data Bit 6

Set
Break

Parity
Enable
(PEN)

Transmit~

ter
Holding
Register
(THRE)

Transmitter
Empty
(TEMT)

Data Bit 7

Data Bi! 7

Divisor
Latch
Access
Bit
(DLAB)

..
t Bit 0 IS the least slgmflcant
bit. It IS the first bit senally transmitted or received .

~TEXAS

2-48

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS0538 - MAY 19B9 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Interrupt control logic
The interrupt control logic is shown in Figure 10.
DR (LSR Bit O)--------r~
ERBFI (IER Bit 0 ) - - - - - - - - - 1
THRE (LSR bit 5 ) - - - - - - - - - 1
ETBEI (IER Bit 1)---------L~
OE (LSR bit 1)

Interrupt
Output

PE (LSR Bit 2) -;:==~
FE (LSR bit 3)
BI (LSR Bit 4)
ELSI (IER Bit 1) - - - - - - '
DCTS (MSR Bit 0)
DDSR (MSR Bit 1)

TERI (MSR Bit 2)
DRLSD (MSR Bit 3)
EDSSI (IER Bit 3) - - - - - - - '
INTERRUPT ENABLE (MCR Bit 3)

Figure 10. Interrupt Control Logic

interrupt enable register (IER)
The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPToutput signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table 3 and are described in the following bulleted list.
•

Bit 0: This bit, when set, enables the received data available interrupt.

•

Bit 1: This bit, when set, enables the THRE interrupt.

•

Bit 2: This bit, when set, enables the receiver line status interrupt.

•

Bit 3: This bit, when set, enables the modem status interrupt.

•

Bits 4 thru 7: These bits in the IER are not used and are always cleared.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-49

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most microprocessors.
The ACE provides four prioritized levels of interrupts:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and indicates the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 4.
•

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.

•

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.

•

Bits 3 - 7: These bits in the interrupt identification register are not used and are always clear.

Table 4. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 2

BIT 1

BITO

PRIORITY
LEVEL

INTERRUPT TYPE

None

INTERRUPT SOURCE

INTERRUPT RESET
METHOD

None

Receiver line status

Overrun error, parity error.
framing error or break
interrupt

Received data available

Receiver data available

Reading the receiver buffer
register

Transmitter holding register
empty

Reading the interrupt
Identification register (if
source of interrupt) or writing
into the transmitter holding
register

Clear to send. data set
ready, ring indicator. or data
carrier detect

Reading the modem status
register

Transmitter holding register
empty

Modem status

~TEXAS

INSTRUMENTS
2-50

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Reading the line status
register

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B- MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the cDntents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
•

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 5.
Table 5. Serial Character Word Length

•

Bit 1

Bit 0

Word Length

a
a

5 bits

6 bits

7 bits

8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The number of stop bits generated in relation
to word length and bit 2 is as shown in Table 6.
Table 6. Number of Stop Bits Generated
Number of Stop
Bits Generated

Bit 2

Word Length Selected
by Bits 1 and 2

Any word length

5 bits

1 1/2

6 bits

7 bits

8 bits

•

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit
3 is cleared, no parity is generated or checked.

•

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic is in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.

•

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, Le, a condition where SOUT
terminal is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The
break condition has no affect on the transmitter logic, it only affects the serial output.

•

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-51

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (LSR)t
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are summarized in Table 3 and are described in the following bulleted list.
•

•

Bit 1+: This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator
is cleared every time the CPU reads the contents of the LSR.

•

Bit 2+: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR.

•

Bit 3+: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.

•

Bit 4+: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the
total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents
of the LSR.

•

Bit 6: This bit is the transmitter empty (TEMT) indicator, bit 6 is set when the THR and the transmitter shift
register are both empty. When either the THR or the transmitter shift register contains a data character, the
TEMT bit is cleared.

•

Bit 7: This bit is always clear.

modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
•

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its active state (low). When bit 0 is cleared, DTR goes high.

•

Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit O's control over
the DTR output.

•

Bit 2: This bit (OUT 1) is a reserved location used only in the loopback mode.

•

Bit 3: This bit (OUT 2) controls the output enable for the interrupt signal. When set, the interrupt is enabled.
When bit 3 is cleared, the interrupt is disabled.

~TEXAS

INSTRUMENTS
2·52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B- MAY 1989- REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
•

Bit 4: This bit provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
1.
2.
3.
4.
5.
6.

The SOUT is asserted high.
The SIN is disconnected.
The output of the transmitter shift register is looped back into the receiver shift register input.
The four modem status inputs (CTS, DSR, RLSD, andRl) are disconnected.
The MCR bits (DTR, RTS, OUT1 , and OUT2) are connected to the modem status register bits (DSR,
CTS, RI, and RLSD), respectively.
The four modem control output terminals are forced to. their inactive states (high).

Bits 5 through 7: These bits are always cleared.

modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change
information; when a control input from the modem changes state the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
•

Bit O. This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is
enabled, a modem status interrupt is generated.

•

Bit 1. This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed
states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is
enabled, a modem status interrupt is generated.

•

Bit 2. This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status Interrupt is enabled, a
modem status interrupt is generated.

•

Bit 3. This bit is the delta receive line signal detect (DRLSD) indicator. Bit 3 indicates that the RLSD input
to the chip has changed states since the lastlime it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.

•

Bit 4. This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, bit
4 is equivalent to the MCR bit 1 (RTS).

•

Bit 5. This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, bit
5 is equivalent to the MCR bit 0 (DTR).

•

Bit 6. This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCR bit 2 (OUT 1).

•

Bit 7. This bit is the complement of the receive line signal detect (RLSD) input. When bit 4 (loop) of the MCR
is set, bit 7 is equivalent to the MCR bit 3 (OUT 2).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-53

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

parallel port registers
The parallel port registers interface either device to a Centronix-style printer interface; When chip select 2 (CS2)
is low, the parallel port is selected. Tables 7 and 8 show the registers associated with this parallel port. The read
or write function of the register is controlled by the state or the read (lOR) and write (lOW) terminal as shown.
The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the five most significant
bits. The status bits are printer busy (BUSY), acknowledge (ACK) which is a handshake function, paper empty
(PE), printer selected (SLCT), and error (ERROR). The read control register allows the state of the control lines
to be read. The write control register sets the state of the control lines, which are interrupt enable (IRQ ENB),
select in (SLlN), initialize the printer (INIT), autofeed the paper (AFD), and strobe (STB), which informs the
printer of the presence of a valid byte on the parallel bus. These signals are cleared when a reset occurs. The
write data register allows the microprocessor to write a byte to the parallel bus. The parallel port is completely
compatible with the parallel port implementation used in the IBM serial/parallel adaptor.

Table 7. Parallel Port Registers
REGISTER BITS

BIT7

BIT 6

BITS

BIT4

BIT 3

BIT2

BIT 1

BITO

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD~

Read status

BUSY

ACK

SLCT

ERROR

Read control

IRQ ENB

SUN

INIT

AFD

STB

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD~

IRQ ENB

SUN

INIT

AFD

STB

Read data

Write data
Write control

Table 8. Parallel Port Register Select
CONTROL TERMINALS

lOR

lOW

CS2

Read data

Read status

Read control

Invalid

Write data

Invalid

Write control

Invalid

-!11

TEXAS
INSTRUMENTS
2-54

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C451, TL16C452
ASYNCHRONOUS COMMUNICATIONS ELEMENTS
SLLS053B - MAY 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz
and divides it by a divisor in the range between 1 and (2 16-1). The output frequency of the baud generator is
sixteen times (16 x) the baud rate. The formula for the divisor is:
divisor # = ClK frequency input + (desired baud rate x 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure desired operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. For
baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy of the selected
baud rate is dependent on the selected crystal frequency.

receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register and a RBR. Timing is supplied by the 16x receiver
clock (RClK). Receiver section control is a function of the ACE line control register.
The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift
register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the
RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared
when the data is read out of the RBR.

transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud
out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register.
The ACE THR receives data off of the internal data bus and, when the shift register is idle, moves it into the
transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output
(SOUn. When the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an
interrupt is generated. This interrupt is cleared when a character is loaded into the register.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-55

2-56

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

• Capable of Running With All Existing
TL 16C450 Software

• Fully Programmable Serial Interface
Characteristics:
- 5-,6-,7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation
and Detection
- 1-,11/2-, or 2-Stop Bit Generation
- Baud Generation (dc to 256 Kbitls)

• After Reset, All Registers Are Identical to
the TL16C450 Register Set
• In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
• In the TL 16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data

• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection

• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 16 -1) and Generates an Internal16x
Clock
• Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled

• Internal Diagnostic Capabilities:
- Loopback Controls for Communications
Link Fault Isolation
- Break, Parity, Overrun, Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Faster Plug-In Replacement for National
Semiconductor NS16550A

description
The TL 16C550A is a functional upgrade of the TL 16C450 asynchronous communications element (ACE).
Functionally identical to the TL 16C450 on power up (character modet), the TL 16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL 16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL 16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any pOint in the ACE's operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL 16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (2 16 -1) and producing a 16x clock for driving the internal
transmitter logic. Provisions are included to use this 16x clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user's requirements to minimize the computing required to handle the communications link.

t The TL 16C550A can also be reset to the TL16C450 mode under software control.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-57

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D-AUGUST 1989- REVISED MARCH 1996

NPACKAGE

FNPACKAGE

(TOP VIEW)

Vcc

07
RCLK
SIN
SOUT
CSO
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2

Vss

9
10
11
12
13
14

m
.". C'l C\I ~ 0
0 o
0 1_ 100 10:
m 1Ioooooz>o:ooo

OCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
AO
A1
A2
ADS
TXROY
DDIS
R02
R01

D5
D6
D7
RCLK
SIN
NC
SOUT
CSO
CS1
BAUDOUT

7 6 5 4 3 2 1 44 434241 489

38
37
9
36
10
35
11
34
12
33
13
32
14
31
15
16
30
17
29
181920 21 222324 25 2627 28

OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
AO
A1
AS

NC-No internal connection

~TEXAS

2-58

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

block diagram
r--

Internal _
Data Bus

8-1
07-00 ~

Line
Control
Register

S
e
I
e
.... c
t

tJ.

Receiver
Buffer
Register

Line
Control
Register

Receiver
FIFO

I---

Receiver
Buffer
Register

SIN

Receiver
Timing and
Control

RCLK

AO ~
A1

Divisor
Latch (LS)

A2 ~
CSO

CS1
CS2

..oL

Divisor
Latch (MS)

~
~

Line
Status
Register

ADS.~
MR ~

RD1 ~
RD2

Select
and
Control
Logic

...!4-

DDIS ~
XIN ~
XOUT ~

~}
20

..oL

I Transmitter ~
I FIFO

-S
e
I
e
c
t

Power
Supply

BAUDOUT

Line
Control
Register

~
~
Modem
Control
Logic

Modem
Status
Register

RXRDY.~

VSS

Modem
Control
Register

TXRDY.~

VCC

Baud
JI Generator
II

Transmitter
Holding
Register

WR1 .~
WR2

Interrupt
Enable
Register

Interrupt
Control
Logic

Interrupt

1/0

:----

~
~
~
~
~
~
30

SOUT

RTS
CTS
DTR
DSR
DCD

Ai
OUT1
OUT2
INTRPT

~TEXAS

INSTRUMENTS
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2-59

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NAME

I/O

DESCRIPTION

28[31]
27[30]
26[29]

Al
A2

Register select. AO, A 1, and A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.

ADS

25 [28]

Address strobe. When ADS is active (low), the register select signals (AO, A 1, and A2) and chip select signals (CSO,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.

BAUDOUT

15[17]

Baud out. BAUDOUT is a 16 x clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.

CSO
CS1
CS2

12[14]
13[15]
14 [16]

Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.

CTS

36[40]

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.

DO-D7

1-8
[2-9]

1/0

Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
ACE and the CPU.

DCD

38[42]

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes
state, an interrupt is generated.

DDIS

23[26]

Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an ex1ernal transceiver.

DSR

37 [41]

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.

DTR

33[37]

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control registerto a high level.
DTR is placed in the inactive state either as a result of a master reset or.during loop mode operation or clearing
bit 0 (DTR) of the modem control register.

INTRPT

30[33]

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.

35[391

Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
toTable 2.

OUT1
OUT2

34[381
31 [35]

Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are setto their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.

RCLK

9[10]

Receiver clock. RCLK is the 16x baud rate clock for the receiver section of the ACE.

RD1
RD2

21 [24]
22 [25]

Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).

NO.t

Terminal numbers shown in brackets are for the FN package.

~TEXAS

INSTRUMENTS
2-60

PO:lT OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

Terminal Functions (continued)
TERMINAL

I/O

DESCRIPTION

39 [43]

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem status
register. Bit 2 (TERI) of the modem status register indicates that the Ai input has transitioned from a low to a high
state since the last read from the modem status register. If the modem status interrupt is enabled when this transition
occurs, an interrupt is generated.

RTS

32 [36]

Request to send. When active, RTS informs the modem or data set that the ACE is ready to transmit data. RTS
is set to its active state by setting the RTS modem control register bit, and is set to its inactive (high) state either
as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the modem control register.

RXRDY

29 [32]

Receiver ready output. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected with FCR3. When operating in the TL 16C450
mode, only DMA mode 0 is allowed. Mode 0 supports Single-transfer DMA in which a transfer is made between
CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
receiver FIFO has been emptied. In DMA mode 0 (FCRO = 0 or FCRO = 1, FCR3 = 0), if there is at least 1 character
in the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active but there
are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1 (FCRO = 1, FCR3
= 1), when the trigger level or the timeout has been reached, RXRDY goes active (low); when it has been active
but there are no more characters in the FIFO or holding register, it goes inactive (high).

SIN

10 [11]

Serial input. SIN is a serial data input from a connected communications device.

SOUT

11 [13]

Serial output. SOUT is a composite serial data output to a connected communication device. SOUT is set to the
marking (high) state as a result of master reset.

TXRDY

24[27]

Transmitter ready output. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected with FCR3. When operating in the TL 16C450 mode, only DMA
mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles.
Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the transmit FIFO has
been filled.

NAME

NO.t

VCC

40[44]

5-V supply voltage

VSS

20 [22J

Supply common

WRI
WR2

18 [20J
19 [21J

XIN
XOUT

16[18J
17[19J

110

Write inputs. When either WRI or WR2 are active (high or low respectively) while the ACE is selected, the CPU
is allowed to write control words or data into a selected ACE register. Only one of these inputs is required to transfer
data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied lowor WRI tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

t Termmal numbers shown In brackets are for the

FN package.

~TEXAS

INSTRUMENTS
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2-61

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS0570 - AUGUST 1989 - REVISEO MARCH 1996

absolute maximum ratings over free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI ................................................... -0.5 V to 7 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, T e: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ..................... 260°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA

MIN

NOM

MAX

UNIT

4.75

5.25

VCC

-0.5

0.8

°c

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH+

High-level output voltage

IOH=-1 mA

VOL+

Low-level output voltage

IOL= 1.6mA

Ilkg

Input leakage current

VCC = 5.25 V,
VI = 0 to 5.25 V,

IOZ

High-impedance output current

VCC = 5.25 V,
VSS=O
VO= Oto 5.25 V,
Chip selected in write mode or chip deselected

ICC

Supply current

TA = 25°C,
VCC - 5.25 V,
SIN, DSR, DCD, crs, and Ai at 2 V,
XTAL1 at 4 MHz,
All other inputs at 0.8 V,
Baud rate = 50 kbiVs
No load on outputs,

CXIN

Clock input capacitance

CXOUT

Clock output capacitance

Input capacitance

Output capacitance

TYpr

MAX

2.4

VCC=O,
VSS=O,
All other terminals grounded,
f= 1 MHz,
TA = 25°C

All typical values are at VCC = 5 V, TA = 25°C.
=1= These parameters apply for all outputs except XOUT.

~TEXAS

INSTRUMENTS
POST OFFICE eox 655303 • DALLAS, TEXAS 75265

UNIT
V

VSS=O,
All other terminals floating

2-62

MIN

0.4

±10

I!A

±20

I!A

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL

FIGURE

MIN

MAX

UNIT
ns

tcR

Cycle time, read (tw7 + td8 + td9)

175

tcw

Cycle time, write (tw6 + td5 + td6)

175

tw5

Pulse duration, ADS low

tADS

2,3

tw6

Pulse duration, write strobe

Pulse duration, read strobe

twR
tRD

tw7

tW8

Pulse duration, master reset

tMR

tsu1

Setup time, address valid belore ADS!

tAS

2,3

tsu2

Setup time, CS belore ADS!

tcs

2,3

tsu3

Setup time, data valid belore WR1 J, or WR2!

tDS

th1

Hold time, address low after ADS!

tAH

2,3

th2

Hold time, CS valid after ADS!

tCH

2,3

ns
ns

th3

Hold time, CS valid after WR 1! or WR2 J,

twcs

th4§

Hold time, address valid after WR 1! or WR2 J,

twA

th5

Hold time, data valid after WR1! or WR2 J,

tDH

th6

Hold time, CS valid after RD1! or RD2J,

tRCS

th7§

Hold time, address valid after RD1! or RD2J,

tRA

td 4 !:i

Delay time, CS valid belore WR 1 J, or WR2!

tcsw

td5 S
td6§

Delay time, address valid belore WR1 J, or WR2!

tAW

Delay time, write cycle, WR1! or WR2 J, to ADS J,

twc

td 7 !:i

Delay time, CS valid to RD1 J, or RD2!

tCSR

td8 S

Delay time, address valid to RD1 J, or RD2!

td9

Delay time, read cycle, RD1! or RD2J, to ADSJ,

tAR
tRC

§ Applicable only when ADS

tied low.

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

tw1

Pulse duration, clock high

tXH

I = 9 MHz maximum

tw2

Pulse duration, clock low

tXl

I = 9 MHz maximum

td10

Delay time, RD1 J, or RD2! to data valid

tRVD

Cl = 100 pF

td11

Delay time, RD1! or RD2J, to Iloating data

tHZ

Cl=100pF

tdis(R)

Disable time, RD1 J,! or RD2! J, to DDIS! J,

tRDD

CL = 100 pF

PARAMETER

NOTE 2: Charge and discharge time

MAX

UNIT
ns
ns

determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

100

tW3

Pulse duration, BAUDOUT low

tlW

1=9 MHz, ClK + 2,
Cl=100pF

tw4

Pulse duration, BAUDOUT high

tHW

1=9 MHz, ClK + 2,
Cl = 100 pF

td1

Delay time, XIN! to BAUDOUT!

tBLD

Cl = 100 pF

125

td2

Delay time, XIN-! J, to BAUDOUT J,

tBHD

CL -100 pF

125

~TEXAS

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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
PARAMETER

ALT. SYMBOL

FIGURE

td12

Delay time, RCLK tq sample clock

tSCD

td13

Delay time, stop to set RCV error interrupt or
read RBR to LSI interrupt or stop to
RXRDY-i,

tSINT

4,5,6,7,8

TEST CONDITIONS

MIN

MAX

100
1

UNIT

ns
RCLK
cycles

Delay time, read RBRlLSR to reset interrupt
4,5,6,7,8
150
ns
CL= 100 pF
td14
tRINT
, ,
"
NOTE 3: In FIFO mode RC = 425 ns (minimum) between reads of the receiver FIFO and the status registers (Interrupt Identification
register or
line status register),

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

td15

Delay time, INTRPT to transmit start

tlRS

baudout
cycles

td16

Delay time, start to interrupt

tSTI

baudout,
cycles

td17

Delay time, WR THR to reset interrupt

tHR

td18

Delay time, initial write to interrupt (THRE)

td19

Delay time, read IIR to reset interrupt (THRE)

td20

Delay time, write to TXRDY inactive

td21

Delay time, start to TXRDY active

CL= 100 pF
16

140

baudout
cycles

tSI

tlR

CL= 100 pF

140

tWXI

10,11

CL = 100 pF

195

tSXA

10,11

CL= 100 pF

baudout
cycles

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
ALT. SYMBOL

FIGURE

td22

Delay time. WR MCR to output

tMDO

CL= 100 pF

100

td23

Delay time, modem interrupt to set interrupt

tSIM

CL= 100 pF

170

1d24

Delay time, RD MSR to reset interrupt

tRIM

CL=100pF

140

PARAMETER

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TEST CONDITIONS

MIN

MAX

UNIT

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

2.4V

XINor RCLK
(9 MHz Max)

0.4 V

1..._ _ _ _ _ _ _ _ _

N _ _ _ _ _ _ _ _ _ _...
~:I

_____ JlS

XIN

BAUDOUT
(111)

BAUDOUT
(1/3)

BAUDOUT
(1/N)
(N)3)

1'-------'

~ 2 XIN Cycles ~

1<111"--- (N-2) XIN Cycles - - -•• 1
1

Figure 1_ Baud Generator Timing Waveforms

~TEXAS

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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
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PARAMETER MEASUREMENT INFORMATION

I..

tws

50%
I

tsu1 ----+j
~

AO-A2

th1
50% Validt

50%

eso, eS1, eS2 _ _

______

JI~

* * ¥..

- r~-o/c.J.
I

50%

50%
I
I

th3

___

I
I

S_00T";_ _-,-_ __

V.Hd'

V.1d

+--I

I
I+-tw6~
I
~td4t -+j
~th4t ~

I
I

I
I
i+-- td6t ~

14-- tdst --+I

WR1, WR2 _______s_o-J%* Active *:5=0=%===============
tsu3 I..
I

07-00
t

.thS
I

v Valid Data ~/)-.- - - - - - -

--------~\

Applicable only when ADS is tied low.

Figure 2. Write Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
' 4 - - - ' + - tws

50%

j4-- tsu1 --+I 1

AO-A2

-+'

Valid

I+-

th1

: xr-SO-%-V-al-id-t-s-O%"")(

1' - - - . . - - - -

.,
--.:

_ _.;...1""'\ 1

cso, CS1, CS2

50%

)I(

1
1

'+th2
1

I~----~---

th6 ~
1
1
i+- t w7-+i
1
i4- td7t ~
I+- th7t ~

------------""'\1

50%)1( Active

------------~I

---j++j
------j'-\L
1\50%

)I(I~------------50%

1'--------------I
I
I

/1,.-_ _ __
50%

ld104:..

07-00

~ tdis(R)

ldis(R)

OOIS

J.-- td9 ~I

~ ldst ---+I

R01, R02

~:_ _"'--__

SO% Valldt )(500/.

Valid

----~I~I

tsu2

--------~<

Valid

~ata

td11

Y,..-----

t Applicable only when ADS is tied low.
Figure 3. Read Cycle Timing Waveforms

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TL16C550A
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PARAMETER MEASUREMENT INFORMATION
RCLK

-fl

I...

~~~12
.I

rcJ'

8 Clocks

Sample Clock

TL 16C450 Mode:

SIN \

Start /

Data

~\ts

5-8

Parity

"---I

Stop

Sample Clock
f(

INTRPT
(data ready)

I
I /50%
td13

INTRPT
(RCV error)

50% \..
~

--------------------------------~I I

--+1

~14 -1414-~.1

14I

1\50% I

50%

--------------------------------~.

I~·~I-------I

RD1,RD2
:
(read RBR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...
5_0%.....~

(r~~~'L~~~

I I

~'i-~

__________________
50_%_0

td14 ~I

Figure 4. Receiver Timing Waveforms

~TEXAS

INSTRUMENTS
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_ _ _ _...,.._

1"-

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
SIN

___

~,-_-""'G

D_a.,ta.,..B_it_S_5_-8_--,

Sample Clock
{(

Trigger-Level
Interrupt
(FCR6, 7 0, 0)

--------~(jc,...)___--"I~II

I~-------"""L---

td13
LSI Interrupt _

---+!

I
~

_______
(S.,ee.,..N_o_te_A_)_--J)1

td14

Trigger Level)
(FIFO at or Above
(FIFO Below
Trigger Level)

I~ ~I

')'J

RD1
(RD LSR)

I
I

td14 --I4-~.1

I
I
'----1
I
I

---------'l'r------,

RD1
(RD RBR)
NOTE A: For a timeout interrupt. td13 = 8 RCLKs.

Figure 5. Receiver FIFO First Byte (Sets DR Bit) Waveforms

SIN

Sample Clock

Time Out or
Trigger Level
Interrupt

-------"10

td13
1 I
(see Note A) ~I ~

LSI Interrupt

-------,

1d14

I:'

(FIFO at or Above
Trigger Level)
(FIFO Below
Trigger Level)

--J4-+I
I

--------~\......./l.!~~~~~-\,..,__+I----1
I I
1d13

-.1<11\41---••1

td14

--1+--+1

RD1, RD2
(RDLSR)

_---.-.----Jx'------"'x~:_

RD1, RD2
(RDRBR)

______

~)(~-A-ct-iv-e~:>('-_ _ _ _ _ _ _ _ _J~~-A-c-tiv-e-~
Previous Byte
Read From FIFO

NOTE A: For a timeout interrupt. td13 = 8 RCLKs.

Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

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PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)

Active

(\1-'- - - -....\

~
~ Stop ' - - -

SIN
(first byte)

I
I
I
I
I
I

(see Note

B)~I"-I
I
"{

RXRDY

SeeNoteA

Sample Clock
td13

..J).I----

_ _ _ _-It-_ _ _t_d1_4_ _I...
))

NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, td13 = 8 RCLKs.

Figure 7. Receiver Ready (RXRDY) Waveforms, FCRO

=0 or FCRO =1 and FCR3 =0 (mode 0)
))

RD
(RD RBR)

SIN

I
I
I

~~~~~

the trigger l e v e l ) .

Sample Clock

RXRDY (_.,...)

SeeNoteA

:
I

td13

Active

~,..,i____

-1(1-('_ _ _
td_l_4_ -1-....J)

....; - - - -

NOTES: A. This is the reading of the last byte in the FIFO.
B. For a timeout interrupt, td13 = 8 RCLKs.

Figure 8. Receiver Ready (RXRDY) Waveforms, FGR

=1 or FCR3 =1 (mode 1)

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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
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PARAMETER MEASUREMENT INFORMATION

~
td15

I
~

~~~~rt

__________________- J

I
I

.=.:.jI I"- 1d17

F\.. . ------------------+l--

50%

td19
ROIIR

I
I

td18

I+- I
I

'\..

Stop

td16
50%
______

---i4-"~
I~

1d17 ~

Parity

INTRPT
(THRE)

WRTHR

Start /

~.....5_0'_Y• ....&._ _ _ _
oa....tS\\",B_I_t8_ _-,

SOUT

--+iI

~
I

-------------------------------------------------~
Figure 9. Transmitter Timing Waveforms

WR
(WRTHR)

B~e#1

(

I
SOUT

Data

X parltY~

1d21~

'X'-__

Figure 10. Transmitter Ready (TXRDY) Waveforms, FCRO = 0 or FCRO = 1 and FCR3

WR
(WRTHR)

= 0 (mode 0)

B~e#16 (
I

SOUT

_----Oa-ta-----1:x

Parity

~
td21~

FIFO Full

\.1\:

10....-_ _

Figure 11. Transmitter Ready (TXRDY) Waveforms, FCRO = 1 and FCR3 = 1 (mode 1)

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TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
WR
(WRMCR)

50%

td22 --i4-----+J.1

RTS, OTR, - - - - - - -......{50%
OUT1,OUT2
'"

\50%
td234

(~~~~~~ ________..J'r"5-0%-.--5-0%""".} ' - _ - - ' {50%
td24~
(RO

M~~~

___________

I+--*-

---+1_______
I

______~t~50-%-------

Figure 12. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
2-72

td23

50% "\.....

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

APPLICATION INFORMATION

P'"

SOUT
07-00

P7-DO
MEMRor 1I0R
MEMW or liON
INTR
C

RESET

U
B
u
s

RD1

RTS

WR1

DTR

INTRPT

DSR

DCD

SIN

EIA
232-0 Drivers
and Receivers

...

TL16C550A CTS
(ACE)
Ai

_L£
CS

H-C

ADS

XIN

WR2
RD2
CS2

XOUT

CS1

BAUDOUT

cso

RCLK

3.072MHz

T
-=-

Figure 13. Basic TL16C550A Configuration
- - - -..... WR

Receiver Disable

~----~~--------.-----------------~ WR1

TL16C550A
(ACE)
Microcomputer
~stem

Data Bus

I\-~~~--;-~I

S-Bit
Bus Transceiver

07-00

'------1-----------1 DDIS

Driver Disable

Figure 14. Typical Interface for a High-Capacity Data Bus

~TEXAS .

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

2-73

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEME~T
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

APPLICATION INFORMATION

n 16C550At

Alternate
XTAL Control
XIN ....1....:6_ _ __ . -.....-...,

A16-A23

1----------------,

.....- ,

XOUTr--~~_.-

12
I------Icso
Address
13
Decoder 1------1 CS1

BAUDOUT
RCLK

14 CS2
L-----t--I

CPU

DTR
RTS 1 - - - - - - 1

ADSI--.______________________~2=_i5 ADS

OUT1
OUT2 31

:>0-----------1 MR

Aoo-AD151\-----r-_-,-_-11
PHI1

.---..,...-fl

00-D2

iii

PHI2

DSR~---OC

CTS

PHil

ADS

PHI2

RSTO
RDI-----I

f--_ _2'-1.... RD1

WRI-----I

f--_ _1_8.... WR1

TCU

1-'3::.:6~:x:

SOUTr---I
10
SIN I----Oc:
30
INTRPT
24
TXRDY

Aoo-AD15
RD2

DDIS

19 WR2

RXRDY

-=40
5V
(VCC)

t Terminal numbers for the TL16C550A are for the N package.
Figure 15. Typical TL16C550A Connection to a CPU

~1ExAs

INSTRUMENTS
2·74

POST OFFICI' BOX 855303 • DALLAS, TEXAS 75265

EIA·232·D
Connector

TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D - AUGUST 1989 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 1. Register Selection
DLABt

Receiver buffer (read), transmitter holding register (write)

Interrupt identification register (read only)

FIFO control register (write)

Line control register

Modem control register

Line status register

Modem status register

Scratch register

1
1

Divisor latch (LSB)

Divisor latch (MSB)

..
t The divisor latch access bit (DLAB) IS the most significant
bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 3).

Table 2. ACE Reset Functions
REGISTER/SIGNAL

RESET
CONTROL

RESET STATE

Interrupt Enable Register

Master Reset

All bits cleared (0-3 forced and 4-7 permanent)

Interrupt Identification Register

Master Reset

Bit 0 is set, bits 1 -3 are cleared, and bits 4-7 are permanently
cleared

FIFO Control Register

Master Reset

All bits cleared

Line Control Register

Master Reset

All bits cleared

Modem Control Register

Master Reset

All bits cleared (5-7 permanent)
Bits 5 and 6 are set, all other bits are cleared

Line Status Register

Master Reset

Modem Status Register

Master Reset

Bits 0-3 are cleared, bits 4-7 are input signals

SOUT

Master Reset

High

INTRPT (receiver error flag)

Read LSRlMR

Low

INTRPT (received data available)

Read RBR/MR

Low

INTRPT (transmitter holding register empty)

Read IRlWrite
THRlMR

Low

INTRPT (modem status changes)

Read MSR/MR

Low

OUT2

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUTl

Master Reset

High

Scratch Register

Master Reset

No effect

Divisor Latch (LSB and MSB) Registers

Master Reset

No effect

Receiver Buffer Registers

Master Reset

No effect

Transmitter Holding Registers

Master Reset

No effect

RCVR FIFO

MRlFCR1-FCROI
OCQQa

FIT

OCO
OSR
CTS
MR
OUT1
OTR
RTS
OUT2
INTRPT
RXROY
AO
A1
A2
AOS
TXROY
OOIS
R02
R01

SIN
SOUT
CSO
CS1
CS2
BAUOOUT
XIN
XOUT
WR1
WR2

Vss

05
06
07
RCLK
SIN
NC
SOUT
CSO
CS1
CS2
BAUOOUT

6 5 4 3 2 1 44 4342 41 40
7
39
38
8
37
9
10
36
11
35
12
34
13
33
14
32
15
31
16
30
17
29
18 192021 2223 2425 26 2728

I-lit

0) 1>-[0)

Z
~ O)zQQ-QQ
a I~ C\I
-:::>
xo:s::s:>
OCOC§oc«
x
x

I-

PTPACKAGE
(TOP VIEW)

I-

0) 10)

a"OCQQaz

48 4746 45 44 4342 41 40 39 3837
NC
05
06
07
RCLK
NC
SIN
SOUT
CSO
CS1
CS2
=BA""-U=O"'O"'-U=T

10
2
3
4
5
6
7
8
9
10
11
12

36
~

34
33
32
31
30
29
28
27
26
25

13 14 15 16 17 18 192021 22 23 24

aZx:::>OCOCO)QQZCiQQ
Z I-I~ C\I 0) I~ C\I a 0) 1>-[0)
o:s::s:>OCOC

QOC«
~

NC-No internal connection

~TEXAS

2-88

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NC
MR
OUT1
OTR
RTS
OUT2
INTRPT
RXROY
AO
A1
A2
NC

MR
OUT1
OTR
RTS
OUT2
NC
INTRPT
RXROY
AO
A1
A2

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-JANUARY 1994 - REVISED MARCH 1996

functional block diagram
r--

S
e
I
Internal
~
e
Data Bus
..... c
t

8-1
07-00 ~

Data
Bus
Buffer

Receiver
Buffer
Register

Line
Control
Register

Receiver
FIFO

-+-

Receiver
Shift
Register

SIN

Receiver
Timing and
Control

---.-!--

RCLK

AO ~
AI ~

Divisor
Latch (LS)

A2 ~

CSO

CSI ~
14
CS2 ADS ~
MR ~
RDI ~
RD2 ~
WRI ~
WR2 ~
DDIS

TXRDY

RXRDY

Select
and
Control
Logic

I Transmitter ~
I FIFO

Transmitter
Holding
Register

~
~

BA UDOUT

Line
Control
Register

Line
Status
Register

XIN ~
XOUT

I Baud I
LGenerator J

Divisor
Latch (MS)

Modem
Control
Register

S
e
I
e
c
t

Line
Control
Register

I---

Modem
Control
Logic

Modem
Status
Register

~ SOUT

RTS

~
33

CTS

DTR

DSR

~
~

DCD

~ OUT1
~ OUT2
Interrupt
Enable
Register

Interrupt
Control
Logic

Interrupt

INTRPT

~TEXAS

INSTRUMENTS
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2-89

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NO.
N

NO.
FN

NO.
PT

1/0

DESCRIPTION

AO
A1
A2

28
27
26

31
30
29

28
27
26

Register select. AO-A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses, and refer to the address strobe (ADS) signal
description.

ADS

Address strobe. When ADS is active (low), the register select signals (AO, A 1, and A2) and chip select
signals (CSO, CS1, CS2) drive the internal select logic directly; when high, the register select and chip
select signals are held in the state they are in when the low-to-high transition of ADS occurs.

BAUDOUT

Baud out. BAUDOUT is a 16x clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT can also be used for the receiver section by tying this output to RCLK.

CSO
CSI
CS2

12
13
14

14
15
16

9
10
11

Chip select. When CSO = high, CSI = high, and CS2 = low, these three inputs select the ACE. When
any of these inputs are inactive, the ACE remains inactive. Refer to the ADS signal description.

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (ACTS) of the modem status regisfer indicates that this signal has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when CTS changes state, an interrupt is generated.

DO
01
02
03
04
05
06
07

1
2
3
4
5
6
7
8

2
3
4
5
6
7
8
9

43
44
45
46
47
2
3
4

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (ADCD) of the modem status register indicates that this signal has
changed states since the last read from the modern status register. If the modem status interrupt is
enabled when DCD changes state, an interrupt is generated.

DDIS

Driver disable. This output is active (high) when the CPU is not reading data. When active, this output
can disable an external transceiver.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (A DSR) of the modem status register indicates this signal has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes state, an interrupt is generated.

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active state by setting the DTR bit of the modem control
register to a high level. DTR is placed in the inactive state either as a result of a master reset, during
loop mode operation, or clearing the DTR bit.

INTRPT

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data is available or
timed out (FIFO mode only), the transmitter holding register is empty, or an enabled modern status
interrupt. The INTRPT output is reset (deactivated) either when the interrupt is serviced or as a result
of a master reset.

Master reset. When active (high). MR clears most ACE registers and sets the state of various output
signals. Refer to Table 2.

OUTI
OUT2

34
31

38
35

34
31

Outputs 1 and 2. User-designated outputs that are set to their active low states by setting their
respective modem control register bits (OUTI and OUT2) high. OUT1 and OUT2 are set to their inactive
(high) states as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the modem control register.

RCLK

NAME

Receiver clock. RCLK is the 16 x baud rate clock for the receiver section of the ACE.

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSl36A - JANUARY 1994 - REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NO.
N

NO.
FN

NO.
PT

DESCRIPTION

RD1
RD2

21
22

24
25

19
20

Read inputs. When either input is active (low or high respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is
required forthe transfer of data during a read operation; the other input should be tied in its inactive state
(Le., RD2 tied low or RD1 tied high).

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that the Ai input has
transitioned from a low to a high state since the last read from the modem status register. If the modem
status interrupt is enabled when this transition occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to its active state by setting the RTS modem control register bit and is set to its inactive
(high) state either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
of the MCR.

RXRDY

Receiver ready output. Receiver direct memory access (DMA) signalling is available with this terminal.
When operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO
control register bit 3 (FCR3). When operating in the TL 16C450 mode, only DMA mode 0 is allowed.
Mode 0 supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1
supports multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO
has been emptied. In DMA mode 0 (FCRO 0 or FCRO 1, FCR3 0), when there is at least one
character in the receiver FIFO or receiver holding register, RXRDY is active low. When RXRDY has
been active but there are no characters in the FIFO or holding register, RXRDY goes inactive (high).
In DMA mode 1 (FCRO 1, FCR3 1), when the trigger level orthe time out has been reached, RXRDY
goes active (low); when it has been active but there are no more characters in the FIFO or holding
register, it goes inactive (high).

NAME

SIN

SOUT

Composite serial data output. Output to a connected communication device. SOUT is set to the marking
(set) state as a result of master reset.

Serial data input. Input from a connected communications device

TXRDY

Transmitter ready output. Transmitter DMA Signalling is available with this terminal. When operating in
the FIFO mode, one of two types of DMA Signalling can be selected using FCR3. When operating in
the TL 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single·transfer DMA in which a
transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple
transfers are made continuously until the transmit FIFO has been filled.

Vce
VSS

WR1
WR2

18
19

20
21

16
17

XIN
XOUT

16
17

18
19

14
15

110

5-V supply voltage
Supply common
Write inputs. When either input is active (high or low respectively) and while the ACE is selected, the
CPU is allowed to write control words or data into a selected ACE register. Only one of these inputs is
required to transfer data during a write operation; the other input should be tied in its inactive state (Le.,
WR2 tied low or WR1 tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

~TEXAS

INSTRUMENTS
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2-91

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSI36A-JANUARY 1994 - REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI ................................................... -0.5 V to 7 V
Output voltage range, Va ........................................................... -0.5 V to 7 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Continuous total power dissipation at (or below) 70°C ...................................... 300 mW
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, T e: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N or PT package ............... 260°C

recommended operating conditions
Supply voltage, V CC
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA

MIN

NOM

MAX

UNIT

4.75

5.25

VCC

-0.5

0.8

°c

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH:!:

High-level output voltage

10H=-1 rnA

VOL:!:

Low-level output voltage

10L= 1.6mA

Input current

Vce = 5.25 V,
VI = 0 to 5.25 V,

10Z

High-impedance-state output current

VCC = 5.25 V,
VSS=O,
VO=Ot05.25V,
Chip selected in write mode or chip deselect

lec

Supply current

Ci(CLK)

Clock input capacitance

Co(CLK)

Clock output capacitance

Input capacitance

Output capacitance

MIN

TYpt

MAX

2.4

UNIT
V

VSS=O,
All other terminals floating

0.4

llA

±20

llA

rnA

Vce=5.2~_

TA=25°C,
SIN, DSR, DCD, eTS, and Rl at 2 V,
All other inputs at 0.8 V,
XTAL 1 at 4 MHz,
No load on outputs,
Baud rate = 50 kbitls

Vce =0,
VSS =0,
f= 1 MHz,
TA = 25°C,
All other terminals grounded

All tYPical values are at Vee = 5 V, TA = 25°C.
:!: These parameters apply for all outputs except XOUT.

~TEXAS

INSTRUMENTS
2-92

POST OFFICE BOX 055303 • DALLAS, TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

IeR

Cycle time, read (tw7 + td8 + td9)

tcw

Cycle time, write (tw6 + td5 + td6)

twl

Pulse duration, clock high

tXH

I = 9 MHz maximum

tw2

Pulse duration, clock low

tXL

I = 9 MHz maximum

tW5

Pulse duration, address strobe low

lADS

2,3

tw6

Pulse duration, write strobe

tWR

I1s

tw7

Pulse duration, read strobe

tRD

tW8

Pulse duration, master reset

tMR

tsu1

Setup time, address valid belore ADS1'

tAS

2,3

tsu2

Setup lime, chip select valid belore ADS1'

tcs

2,3

Isu3

Setup lime, dala valid belore WRl J. or WR21'

tDS

thl

Hold time, address low after ADS1'

tAH

2,3

th2

Hold time, chip select valid after ADS1'

ICH

2,3

th3

Hold lime, chip select valid after WR11' or WR2J.

twcs

th4

Hold time, address valid after WR11' or WR2J.

IWA

tDH

IRCS

tRA

tcsw

Delay time, address valid belore WRl J. or WR21'

lAW

td6t

Delay time, write cycle, WR11' or WR2J. 10 ADSJ.

twc

id7t

Delay time, chip select valid to RDl J. or RD21'

ICSR

td8 t

Delay lime, address valid 10 RDl J. or RD21'

tAR

th5

Hold lime, data valid after WR11' or WR2J.

th6

Hold time, chip select valid after RD11' or RD2J.

Ih7

Hold time, address valid afterRD11' or RD2J.

td4t

Delay lime, chip select valid belore WRl J. or WR21'

td5 t

td9

Delay time, read cycle, RD11' or RD2J. 10 ADSJ.

tRC

Idl0

Delay time, RDl J. or RD21' 10 data valid

tRVD

CL = 75pF

Idll

Delay lime, RD11' or RD2J. to floating dala

tHZ

CL= 75 pF

t Only applies when ADS IS low
system switching characteristics over recommended ranges of supply voltage and operating
.
free-air temperature (see Note 2)
TEST CONDITIONS

PARAMETER

Disable time, RD11' J. or RD2J. l' to DDIS1' J.

CL = 75 pF

Charge and discharge time is determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL =75 pF
ALT. SYMBOL

FIGURE

tW3

Pulse duration, BAUDOUT low

tLW

I - 9 MHz, ClK + 2

tw4

Pulse duration, BAUDOUT high

IHW

f = 9 MHz, ClK + 2

idl

Delay time, XIN1' to BAUDOUT1'

IBLD

Id2

Delay time, XIN1'J. to BAUDOUTJ.

tBHD

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

ns
ns

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-93

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
PARAMETER
td12

Delay time, RCLK to sample

td13

Delay time, stop to set interrupt or read
RBR to LSI interrupt or stop to RXRDY J,

td14

Delay time, read RBRlLSR to reset interrupt low

ALT. SYMBOL

FIGURE

tSCD

tSINT

4,5,6,7,8

tRINT

4,5,6,7,8

TEST CONDITIONS

MIN

MAX

RCLK
cycle

CL= 75 pF

UNIT

NOTE 3: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receiver FIFO and the status registers (Interrupt
identification register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

td15

Delay time, initial write (INTRPT low) to transmit
start (SOUT low)

tlRS

baudout
cycles

td16

Delay time, stop (SOUT low) to interrupt (INTRPT
high)

tSTI

baudout
cycles

id17

Delay time, WR THR high to reset interrupt
(INTRPT low)

tHR

id18

Delay time, initial WR THR low to THRE interrupt
(INTRPT high)

tSI

baudout
cycles

id19

Delay time, RD ItR low to reset THRE interrupt
(INTRPT low)

tlR

CL = 75 pF

id20

Delay time, WR THR high to TXRDY high
(inactive)

twXI

10,11

CL= 75 pF

id21

Delay time, start (SOUT low) to TXRDY low
(active)

tSXA

10,11

CL=75 pF

baudout
cycles

CL = 75 pF
16

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
MIN

MAX

UNIT

ALT. SYMBOL

FIGURE

tMDO

td23

Delay time, modem interrupt (CTS, DSR, DCD) low to set interrupt
(INTRPT) high

tSIM

td24

Delay time, RD MSR low to reset interrupt (INTRPT) low

tRIM

PARAMETER
td22

Delay time, WR MCR low to output (RTS, DTR, OUT1, OUT2) low or high

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

4-.--.-------------N--------------------~.1I
I
XIN

BAUDOUT
(1/1)
td1

BAUDOUT
(1/2)

II~.'"

f-t w3-+ 1
I
j.-tw4+
BAUDOUT
(1/3)

BAUDOUT
(1/N)
(N > 3)

~I~~__________

((

l4-- 2 XIN Cycles ---+-I
I

If-<==

Previous Byte
Read From FIFO
NOTE A: For a time out interrupt, td13

=8 RCLKs.

Figure 6. Receiver FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

~TEXAS

INSTRUMENTS
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2-99

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A- JANUARY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

(RD

(first

R:~

b~~

It'

---....r-\.
---.I Stop \

50%}. Active

See Note A

----------11-----I

.......

I
I

Sample Clock

td13
(see Note B)

--!4--.1
I

td14

I
~

50%~~____~I'~(------J)I~5-0.-~--

RXRDY

NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time out interrupt, td13 = 8 RCLKs.

Figure 7. Receiver Ready (RXRDY) Waveforms, FCRO = 0 or FCRO = 1 and FCR3
l\
((

RD
(RD RBR)
SIN
(first byte that reaches
the trigger level)

50% \ . Active

=r\

Sample Clock
td13
(see Note B)

RXRDY

I
I
I
I
I
I
I
I

~
50%\

td14

= 0 (Mode 0)

See Note A

--+--j
/50%

II
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time out interrupt, td13 = 8 RCLKs.

Figure 8. Receiver Ready (RXRDY) Waveforms, FCR

=1 or FCR3 =1 (Mode 1)

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

\!:rt /

SOUT

tci15

WRTHR

Panty

~-~~

INTRPT
(THRE)

tci17 c+i

Da~~Bns

I
I

tci16

!4- I

50%

I
I
I
I
I

I
I

.::..:.j/

50%

__JI
I
~ tci18

Stop

j4--- tci17

F\'-------------------+i_

50%

td19

---+l

RDIIR

l4--I

----------~--------------~~
Figure 9. Transmitter Timing Waveforms

WR
(WRTHR)

----~

Byte #1

t ~-------~I~(------50%
I

SOUT

... :x . ~~
td20 4

td21

_____________J){~50-%-------~"50%
Figure 10. Transmitter Ready (TXRDY) Waveforms, FCRO

WR
(WRTHR)

Byte #16

=0 or FCRO =1 and FCR3 =0 (Mode 0)

t,..5-0%--------~(~ll- - - - - - -

SOUT

=======~~D~a_ta-_-_~~~~~~""X Parity ~
~ ~

tci21~

50%){,-----F-IF-O-F-UI-I----~~~5_0_%_ _~
Figure 11. Transmitter Ready (TXRDY) Waveforms, FCRO

=1 and FCR3 =1 (Mode 1)

~TEXAS

INSTRUMENTS
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2-101

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-.JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
WR
(WRMCR)

50%

tcI22
RTS,OTR,
OUT1,OUT2

--i4----+'.1

----------{50%
"

\, 50%

tcI23~
(~N!~~ _ _ _ _ _ _ _ _-'lr~-O%---50-%""'}....---';(50%
(RO

M~~

__'1

tcI24~

50%' \

_ _ _ _ _--.. _ _

:
I

________y~50-%--------

Figure 12. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
2·102

td23

POOTOFFICE BOX 655303 • DALLAS, TEX~ 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSl36A - JANUARY 1994 - REVISED MARCH 1996

APPLICATION INFORMATION

:::r'
07-00

MEMRor IIOR
MEMW or lION
INTR
C

U
B
u
s

SOUT
07-00

RESET
AD

RD1
WR1

DTR

INTRPT

DSR

DCD

SIN
RTS

TL16C550B
(ACE)

..
EIA·
232·0 Drivers
and Receivers

CTS

<=>

...

_L£

ADS

XIN

WR2

CS2

XOUT

-A

H-C cso

BAUDOUT

CS1

.ono·I

RD2

....c

RCLK

-=-

Figure 13. Basic TL16C550B Configuration

Receiver Disable

Microcomputer
System

Data Bus

WR1
TL16C550B
(ACE)

Data Bus

8-BII
Bus Transceiver

07-00

DDIS
Driver Disable

Figure 14. 'TYpical Interface for a High-Capacity Data Bus

~1ExAs

INSTRUMENTS
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2-103

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A- JANUARY 1994 - REVISED MARCH 1996

APPLICATION INFORMATION
Alternate

TL16C550B

XIN 1--'-'16'---_ _C_ry_S.ta_1C_0--int
..ro_l----,

A16-A23

A16-A231---_ _ _ _ _ _ _--,

XOUT~--J~r-e----i.------,

12
1-----'----1 CSO
Address
13
Decoder 1 - - - - - - - 1 CS1
1--_ _ _1_4--1 CS2

CPU

BAUDOUT
RCLK

15
9

1...-_ _....1

DTR
RTS . - = - - - _ 1

ADSI----.-------------~__IADS
RSVABT HH-----4~--t>_____l

ADO-AD151\--,-_ _,---f1
PHI1

OUT1

OUT2

~r_--~-~_IMR

.----t1

DO-D7

PHI2
37
DSR 1-------oC

PHI1

ADS

PHI2

RSTO
RD~-----I

1---_...:2:..;.1--1 RD1

WRI------j

1--__1_8_1 WR1

TCU

11
SOUT 1------1

10
SIN I - - - - { X
INTRPT
ADO-AD15

TXRDY

30
24

RD2

DDIS

WR2

RXRDY

-=40
5V
(VCC)
Terminal numbers shown are for the N package.

Figure 15. Typical TL16C550B Connection to a CPU

~TEXAS

2-104

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

EIA-232-D
Connector

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A- JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 1. Register Selection

DLAst

Receiver buffer (read), transmitter holding (write)
Interrupt enable register

Interrupt identification register (read only)

FIFO control register (write)

Line control register

Modem control register

Line status register

Modem status register

Scratch register

Divisor latch (LSB)

Divisor latch (MSB)

. . latch access bit (DLAB) IS the most Significant
.. bit of the hne control register. The DLAB signal
t The diVisor
is controlled by writing to this bit location (see Table 3).

Table 2. ACE Reset Functions

REGISTERISIGNAL

RESET
CONTROL

RESET STATE

Interrupt Enable Register

Master Reset

All bits cleared (bits 0-3 forced and bits 4-7 permanent)

Interrupt Identification Register

Master Reset

Bit 0 is set, bits 1-3 are cleared, and bits 4-7 are permanently
cleared

FIFO Control Register

Master Reset

All bits cleared

Line Control Register

Master Reset

All bits cleared

Modem Control Register

Master Reset

All bits cleared (5-7 permanent)

Line Status Register

Master Reset

Bits 5 and 6 are set, all other bits are cleared

Modem Status Register

Master Reset

Bits 0-3 are cleared, bits 4-7 are input signals

SOUT

Master Reset

High

INTRPT (receiver error flag)

Read LSRlMR

Low

ReadRBRlMR

Low

INTRPT (received data available)
INTRPT (transmitter holding register empty)

Read IRlWrite THRlMR

Low

Read MSRlMR

Low

OUT2

Master Reset

High

RTS

Master Reset

High

DTR

Master Reset

High

OUT1

Master Reset

High

Scratch Register

Master Reset

No effect

Divisor Latch (LSB and MSB) Registers

Master Reset

No effect

Receiver Buffer Registers

Master Reset

No effect

Transmitter Holding Registers

Master Reset

No effect

INTRPT (modem status changes)

RCVRFIFO

MRlFCR1- FCROI
AFCRO

All bits low

XMITFIFO

MRlFCR2-FCROI
AFCRO

All bits low

~TEXAS

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2·105

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSI36A - JANUARY 1994 - REVISED MARCH 1996

Table 3. Summary of Accessible Registers

Bft
No.

ODLAB=O

Receiver

transmitter

Buller
Register
(Read
Only)

Holding
Register
(Write
Only)

RBR

THR

1 DLAB.O

REGIS'TER ADDRESS

Intenupt

FIFO

IER

IIR

FCR

Intenupt

Enable

Control

Enable

Received
0

Dola BIIOt

Data Bit 0

Dala

Available
Interrupt

interrupt
Pending

FIFO

Enable

(ERBI)

Uno
Control
Regteter

Modem
Control
Register

Un.
Btatue
Register

Modem
Status
Register

Scratch
Register

LCR

MCR

LSR

MSR

SCR

DLL

DLM

BRO

Bno

BRa

BRI

Bnl

BH9

BR2

BH2

BRIO

BR3

Bna

Bftll

BR4

Bn4

BR 12

BRS

IfdS

BH13

BHa

BR14

BH7

Bil7

BII15

Word
Lenglll
Selecl
Bno
(WLSO)

Dala

Tanninal
Ready
(DTR)

ODLAB=1
D_

Latch
(LSB)

1DLAB=1

Latch
(MBB)

DoRa

DoIa
Ready
(DR)

Clear
to Send

Overrun
Error
(OE)

Dala
Sel
Ready

(dCTS)

Enable

Transmitter
Holding
1

Dala Bn 1

Dala Bill

Interrupt
10

Receiver

BII(I)

Raset

FIFO

Enable
2.

Dala BI12

Oola 8112

Receiver

Interrupt

Transmitter

Line Slatus

FIFO

Interrupt

BII(2)

Reset

(ELSI)
Enable
Modem
3

DoIa.an 3

Oola BR 4

Dala Bn S

Oola Bn 3

OmaBH4

OmaBHS

S1atus

DMA

BII(2)
(see

Nolo 4)

Oala Bn a

Oala Bna

Dala Bit 7

Data Bit 7

Slop Bfta
(STB)

to Send
(ATS)

(dDSR)

OUTI

ParI1y
Error
(PE)

Enabled
(see

FIFO.
Enabled
(see
Nole 4)

Parily
Enable
(PEN)

Framing
OUT2

Error
(FE)

Receiver
Trigger
(LSB)

Even
·Parily
Selecl
(EPS)

Break

Loop

Stick
Parily

Break
Control

Indicator
(TERI)
Dalla
Oola

carrier
Ootect

(MSB)

La1ch

Aooess

BR
(OLAB)

Clear
to
Send
(CTS)

Transmitter
Holding
Register

Ready

(THRE)

(OSR)

Oola
Sol

Transmitter

Ring

Empty
(TEMT)

Indicator
(RI)

Error in

DMsor

Receiver
Trigger

Interrupt
(BI)

..
t Bit 0 IS the least Significant
bit. It IS the first bit senally transmitted or received .

RCVR
FIFO

(see
NOla 4)

NOTE 4: These bits are always 0 in the TL16C450 mode.

~TEXAS

2-106

Trailing
Edgo Ring

(l!.ocD)

Reserved

Nole 4)

Mode
Selecl

Reserved

FIFO.

Number
01

DoRa
Requesl

Interrupt

Interrupt
(EDSSI)

Word
Lenglll
Selecl
Bnl
(WLS1)

INSTRUMENTs
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Dola
camer
DoIeci
(OCO)

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-JANUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signalling.
Bit 0: FCRO, when set, enables the transmit and receive FIFOs. This bit must be set when other FCR bits are
written to or they are not programmed. Changing this bit clears the FIFOs.
•

Bit 1: FCR1, when set, clears all bytes in the receiver FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.

•

Bit 2: FCR2, when set, clears all bytes in the transmit FIFO and clears its counter. The shift register is not
cleared. The one that is written to this bit position is self clearing.

•

Bit 3: When FCRO is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to
mode 1.

•

Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

•

Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 5).

Table 4. Receiver FIFO Trigger Level
RECEIVER FIFO
TRIGGER LEVEL (BYTES)

BIT7

BIT 6

o·

FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCRO = 1, IERO = 1) receiver interrupt occur as
follows:
1.

The receive data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.

The II R receive data available indication also occurs when the FI FO trigger level is reached, and like the
interrupt, it is cleared when the FIFO drops below the trigger level.

The receiver line status interrupt (IIR
interrupt (IIR 0100).

The data ready bit (LSRO) is set when a character is transferred from the shift register to the receiver
FIFO. It is cleared when the FIFO is empty.

= 0110) has higher priority than the

received data available

~TEXAS

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TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT

SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO time-out interrupt occurs as follows:
1.

FIFO time-out interrupt occurs when the following conditions exist:
a.

At least one character is in the FIFO.

The most recent serial character received is longer than four continuous character times ago (when
two stop bits are programmed, the second one is included in this time delay).

The most recent microprocessor read of the FIFO is longer than four continuous character times
ago. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.

Character times are calculated by using the RCLK input for a clock signal (makes the delay proportional
to the baud rate).

When a time-out interrupt has occurred, it is cleared and the timer is reset when the microprocessor
reads one character from the receiver FIFO.

When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received
or after the microprocessor reads the receiver FIFO.

When the transmit FIFO and transmitter interrupts are enabled (FCRO = 1, IER1
as follows:

=1), transmit interrupts occur

The transmitter holding register interrupt (02) occurs when the transmit FIFO is empty. It is cleared as
soon as the THR is written to (1 to 16 characters may be written to the transmit FIFO while servicing this
interrupt) or the IIR is read.

The transmit FIFO empty indications are delayed one character time minus the last stop bit time when
the following occurs: THRE 1 and there have not been at least two bytes at the same time in the
transmit FIFO since the last THRE =1. The first transmitter interrupt after changing FCRO is immediate
when it is enabled.

Character time-out and receiver FI FO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt.

FIFO polled mode operation
When FCRO is set, clearing IERO, IER1, IER2, IER3, or all four puts the ACE in the FIFO polled mode of
operation. Since the receiver and transmitter are controlled separately, either one or both can be in the polled
mode of operation.
In this mode, the user program checks receiver and transmitter status via the LSR. As stated previously:
•

LSRO is set as long as there is one byte in the receiver FIFO.

•

LSR1 - LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = o.

•

LSR5 indicates when the transmit FIFO is empty.

•

LSR6 indicates that both the transmit FIFO and shift registers are empty.

•

LSR7 indicates whether there are any errors in the receiver FIFO.

There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmit FIFOs are still fully capable of holding characters.

~TEXAS

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TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 4) and the INTRPToutput signal in response
to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The
contents of this register are summarized in Table3 and are described in the following bulleted list.
•

Bit 0: This bit when set enables the received data available interrupt.

•

Bit 1: This bit when set enables the THRE interrupt.

•

Bit 2: This bit when set enables the receiver line status interrupt.

•

Bit 3: This bit when set enables the modem status interrupt.

•

Bits 4 - 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors. The ACE provides four prioritized levels of interrupts:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of that interrupt in its
three least significant bits (bits 0, 1, and 2). The contents ofthis register are summarized in Table 3 and described
in Table 4. Detail on each bit are as follows:
•

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.

•

Bits 1 and 2: These two bits identify the highest priority interrupt pending, as indicated in Table 4.

•

Bit 3. This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a time out interrupt is pending.

•

Bits 4 - 5: These two bits are not used and are always cleared.

•

Bits 6 and 7: These two bits are always cleared in the TL 16C450 mode. They are set when bit 0 of the FI FO
control register is set.

~TEXAS

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2-109

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt identification register (UR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 3 BIT 2 BIT 1 BIT 0
0

PRIORITY
LEVEL

INTERRUPT TYPE

None

INTERRUPT SOURCE

INTERRUPT RESET
METHOD

None

None
Reading the line status register

Receiver line status

Overrun error, parity error,
framing error or break interrupt

Received data available

Receiver data available in the
TL16C450 mode or trigger level
reached in the FIFO mode.

Reading the receiver buffer
register

Character time out
indication

No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time

Transmitter holding
register empty

Transmitter holding registerempty

Reading the interrupt
identHication register (H squrce
of interrupt} or writing into the
transmitter holding register

Modem status

Clear to send, data set ready,
ring indicator, or data carrier
detect

Reading the modem status
register

line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCA. In addition, the programmer is able to retrieve, inspect, and mOdify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and are described in the following bulleted list.
•

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded in Table 6.

Table 6. Serial Character Word Length

•

BIT 1

BIT 0

WORD LENGTH

5 bits

6 bits

7 bits

8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.

~lExAs

2-110

INSTRUMENTS
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TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSl36A-JANUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
BIT 2

WORD LENGTH SELECTED
BY BITS 1 AND 2

NUMBER OF STOP
BITS GENERATED

Any word length

5 bits

11/2

6 bits

7 bits

8 bits

•

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When
bit 3 is cleared, no parity is generated or checked.

•

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.

•

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled and has no
affect on the transmitter logic; it· only effects the serial output.

•

Bit 7: This bit is the divisor latch access bit (OLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver
buffer, the THR, or the lEA.

Bit 0: This bit is the data ready (DR) ihdicator for the receiver. Bit 0 is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. Bit 0 is cleared by reading all of the
data in the RBR or the FIFO.

•

Bit 1 This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character
in the RBR is read, it is overwritten by the next character transferred into the register. The OE indicator is
cleared every time the CPU reads the contents of the LSA. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. An OE is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred tO,the FIFO.

~TEXAS

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2-111

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (lSR) (continued)t
•

Bit 2:1:: This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.

•

Bit 3:1:: This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.

•

Bit 4:1:: This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input
was held cleared for longer than a full-word transmission time. A full-word transmission time is defined as
the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the
contents of the LSR.ln the FIFO mode, this error is associated with the particular character in the FIFO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.

•

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready
to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, an interrupt is
generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This
bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when the
transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.

•

Bit 6: This bit is the transmitter empty (TEMT) indicator. Bit 6 is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.

•

Bit 7: In the TL16C550B mode, this bit is always cleared. In the TL16C450 mode, this bit is alwayS cleared.
In the FIFO mode, LSR7 is set when there is at least one parity, framing, or break error in the FIFO. It is
cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to
its low state. When bit 0 is cleared, DTR goes high.

•

Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit O's control over
the DTR output.

•

Bit 2: This bit (OUT1) controls the output 1 (OUT1) Signal, a user-designated output Signal, in a manner
identical to bit O's control over the DTR output.

~TEXAS

2-112

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-JANUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
•

Bit 3: This bit (OUT2) controls the output 2 (OUT2) signal, a user-designated output signal, in a manner
identical to bit O's control over the DTR output.

•

Bit 4: This bit provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
-

The SOUT is set high.

The SIN is disconnected.

The output of the TSR is looped back into the receiver shift register input.

The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.

The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.

The four modem control outputs are forced to their inactive (high) states.

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt's sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
•

Bits 5 - 7: These bits are permanently cleared.

modem status register (MSR)
The MSR is an a-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
•

Bit 0: This bit is the change in clear-to-send (~CTS) indicator. Bit 0 indicates that the CTS input has
changed states since the last time it was read by the CPU . When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.

•

Bit 1: This bit is the change in data set ready (~DSR) indicator. Bit 1 indicates that the DSR input has
changed states since the last time it was read by the CPU. When this bit is set and the modem status
interrupt is enabled, a modem status interrupt is generated.

•

Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. Bit 2 indicates that the RI input to the
chip has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled,
a modem status interrupt is generated.

•

Bit 3: This bit is the change in data carrier detect (~DCD) indicator. Bit 3 indicates that the DCD input to
the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.

•

Bit 4: This bit is the complement of the clear-to-send (CTS) input. When bit 4 (loop) of the MCR is set,
bit 4 is equivalent to the MCR bit 1 (RTS).

•

Bit 5: This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set,
bit 5 is equivalent to the MCR bit 1 (DTR).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-113

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
•

Bit 6: This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6
is equivalent to the MCRs bit 2 (OUT1).

•

Bit 7: This bit is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
bit 7 is equivalent to the MCRs bit 3 (OUT2).

programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 8 MHz
and divides it by a divisor in the range between 1 and (2 16 _1). The output frequency of the baud generator is
16x the baud rate. The formula for the divisor is:
divisor #

= XIN frequency input + (desired baud rate x

16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization ofthe ACE in orderto ensure desired operation ofthe baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 8 and 9 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbiVs and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency. Refer to Figure 16 for examples of typical
clock circuits.

Table 8. Baud Rates Using a 1.8432-MHz Crystal
DESIRED
BAUD RATE

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

DIVISOR USED
TO GENERATE
16xCLOCK

PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
. 16
12
6
3
2

0.026
0.058

0.69

2.86

~TEXAS

2-114

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 9. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED

DESIRED
BAUD RATE

PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL

TO GENERATE

16xCLOCK

3840

2560

110

1745

0.026

134.5

1428

0.034

150

1280

300

640

600

320

1200

160

1800

107

2000

2400

3600

4800

7200

9600

19200

38400

0.312

0.628

1.23

Driver
XIN

External
Clock

Crystal
Rp

Optional
Driver
Optional
Clock
Output

OSCillator Clock

XOUT

I---t-----et-+-to Baud Generator

=
RX2

Oscillator Clock

.---e-.--Wv--t-----et-+- to Baud Generator

Logic

'-------------'T

Logic

XOUT
C2

TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL

RX2

3.1 MHz

1 MQ

1.5 kQ

10-30 pF

40-60pF

1.8 MHz

1 MQ

1.5 kQ

10-30 pF

40-60 pF

Figure 16. Typical Clock Circuits

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-115

TL16C550B
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS136A-JANUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBR. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16x receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into
the RBR FIFO. In the TL16C450 mode, when a character is placed in the receiver buffer register and the'
received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data
is read out of the RBR. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO
control register.

scratch register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratchpad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.

transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE's line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
The TSR serializes the data and outputs it at the SOUTo In the TL 16C450 mode, when the THR is empty and
the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This interrupt is
cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated based on
the control setup in the FiFO control register.

~TEXAS

2-116

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B- MARCH 1994 - REVISED MARCH 1996

• Programmable Auto-RTS and Auto-CTS
• In Auto-CTS Mode, CTS Controls
Transmitter
• In Auto-RTS Mode, RCV FIFO Contents and
Threshold Control RTS
• Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
• Capable of Running With All Existing
TL 16C450 Software
• After Reset, All Registers Are Identical to
the TL 16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
• In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 16 -1) and Generates an Internal16x
Clock
• Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream

• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
• Fully Programmable Serial Interface
Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation
and Detection
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (dc to 1 Mbitls)
• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
- Loopback Controls for Communications
Link Fault Isolation
- Break, Parity, Overrun, and Framing
Error Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)

description
The TL 16C550C is a functional upgrade of the TL 16C550B asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL 16C450. Functionally equivalent to the TL 16C450 on power up
(character or TL16C450 mode), the TL16C550C, like the TL16C550B, can be placed in an alternate mode
(FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status
per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow using RTS output and CTS input signals.
The TL 16C550C performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-tocserial conversion on data received from its CPU. The CPU can read the ACE status at any time.
The ACE includes complete modem control capability and a processor interrupt system that can be tailored to
minimize software management of the communications link.
The TL 16C550C ACE includes a programmable baud rate generator capable of dividing a reference clock by
divisors from 1 to 65535 and producing a 16x reference clock for the internal transmitter logic. Provisions are
included to use this 16x clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate (16-MHz
input clock) so that a bit time is 1 its and a typical character time is 10 its (start bit, 8 data bits, stop bit).
Two of the TL 16C450 terminal functions on the TL 16C550C have been changed to TXRDY and RXRDY, which
provide signaling to a DMA controller.

PRODUCTION DATA Information Is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing 01 all parameters.

-!II

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-117

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B - MARCH 1994 - REVISED MARCH 1996

NPACKAGE

FN PACKAGE

(TOP VIEW)

DO
D1

VCC

'ttOO()

AT
DCD
DSR
CTS
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
AO
A1
A2
ADS
TXRDY
DDIS
RD2
RD1

D7
RCLK
SIN
SOUT
CSO
CS1
CS2
BAUDOUT
XIN
XOUT
WR1
WR2

VSS

D5
D6
D7
RCLK
SIN
NC
SOUT
CSO
CS1
CS2
BAUDOUT

7
8
9
10
11
12
13
14
15
16
17

6 5 4 321 44 4342 41 40
39
38
37
36
35
34
33
32
31
30
29
181920 21 222324 25 2627 28

zX:;:)sttenzOO1S00
1--10: C\J en () I~ C\J en I>-I en
o
s>
ttttott«
~

PTPACKAGE

(TOP VIEW)
()

~
0

a~~.Ci 0~

OO-1

8 1ffi ll--en ()
0
0 »Itt 0 0 () Z

484746454443424140393837
NC

36
35
34
33
32
31
30
29
28
27
26
25

D7
RCLK
NC
SIN

CS1
CS2
BAUDOUT

10
11
12
13 141516 17 18 19 2021 22 23 24

I>-I

en
()
Z I-- I~ C\J en I~ C\J () en
zx:;:)ttttenOoz1Soo
Oss>tttt
X

ott«
~

NC-No internal connection

~TEXAS

2-118

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NC
MR
OUT1
DTR
RTS
OUT2
INTRPT
RXRDY
AO
A1
A2
NC

MR
OUT1
DTR
RTS
OUT2
NC
INTRPT
RXRDY
AO
A1
A2

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B- MARCH 1994 - REVISED MARCH 1996

detailed description
autoflow control
Auto-flow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS input must be active before
the transmitter FIFO can emit data (see Figure 1). With auto-RTS, RTS becomes active when the receiver needs
more data and notifies the sending serial device (see Figure 1). When RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has space forthe data; thus, overrun errors are eliminated
using ACE1 and ACE2 from a TLC16C550C with the autoflow control enabled. If not, overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
ACE1

ACE2
SIN

SOUT

07-00 ..................

07-00
SOUT

SIN

Figure 1. Autoflow Control (Auto-RTS and Auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8 (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the RCV FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 6), RTS is deasserted after the first data bit of the 16th character is
present on the SIN line. RTS is reasserted when the RCV FIFO has at least one available byte space.

auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, CTS level changes do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error may result.

enabling autoflow control and auto-CTS
Auto-flow control is enabled by setting modem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
1. Auto-flow incorporates both auto-RTS and auto-CTS. When only auto-CTS is desired, bit 1 in the modem
control register should be cleared (this assumes that a control signal is driving CTS).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-119

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLSI77B- MARCH 1994 - REVISED MARCH 1996

auto-CTS and auto-RTS functional timing
SOUT \

Start 1 Bits 0-71 Stop

~ Start

J - - - " " \ Start 1 Bits 0-71 Stop
B-i-ts-0-_-7'I-S-to-p----"""I','r

1""1

----------------------1

NOTES: A. When CTS is low. the transmitter keeps sending serial data out.
B. If CTS goes high before the middle of the last stop bit of the current byte. the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low. the transmitter begins sending data again.

Figure 2. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
SIN

-1,\ Start

r--B-yt-e-N---rI-s-to-p-hr\~:T"'B-~---e-N--+-l-TI-S-to-~--'';'I---',')c,..'J- - - - - - - \ Start

I....---'-~----I

RTS

L _ _ _ _ _ _ _ _ _ _ _ ..1

Byte 1 Stop

_ _ _ _----J/

(RDRBR)----------------------~

NOTES: A. N = RCV FIFO trigger level (1. 4. or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto·RTS section.

Figure 3. RTS Functional Timing Waveforms, RCV FIFO Trigger Level

= 1,4, or 8 Bytes

SIN

RD
(RD RBR)
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full aiter finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
C. When the receive FIFO is full. the first receive buffer register read reasserts RTS.

Figure 4. RTS Functional Timing Waveforms, RCV FIFO Trigger Level

~TEXAS

INSTRUMENTS
2·120

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

= 14 Bytes

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLSl77B- MARCH 1994 - REVISED MARCH 1996

functional block diagram

Internal ~
Data Bus

8-1

r-+

-S
e
I
e
c
t

-+1

Receiver
Buffer
Register

Data
Bus
Buffer

0(7-0)

line
Control
Register

Receiver
FIFO

Receiver
Shift
Register

~
Receiver
TIming and
Control

r--

r--+-

A1 ~

Divisor
Latch (LS)

A2 ~

CS1 ~
14
CS2 ADS ~

Line
Status
Register
Select
and
Control
Logic

RD1 ~
RD2 ~

Transmitter
Holding
Register

WR2 ~

RXRDY

.rr-.-

S
e
I
e
c
t

B AUDOUT

Autofl ow
Contr01
(AFE)

Transmitter
Timing and
Control

L.,8"

Transmitter
Shift
Register

36
33

Modem
Status
Register

Modem
Control
Logic

37
38
39

}-,

VCC~

VSS

20
--=---.-

Supply

-++-

SOUT

"-r

Modem
Control
Register

XIN ~
XOUT

I Transmitter ~
I FIFO

WR1 ~

TXRDY

--"

MR ~

I
I

Baud
Generator

Divisor
Latch (MS)

DOIS

RCLK

r+-

AO ~

CSO

SIN

Interrupt
Enable
Register

Interrupt
Identification
Register

Interrupt
Control
Logic

CTS

DTR
DSR
DCO

Ai
OUT1
OUT2

30 INTRPT

FIFO
Control
Register

NOTE A: Terminal numbers shown are for the N package.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-121

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLSl778 - MARCH 1994 - REVISED MARCH 1996

Terminal Functions
TERMINAL
I/O

DESCRIPTION

28
27
26

Register select. AO-A2 are used during read and write operations to select the ACE register to read
from or write to. Refer to Table 1 for register addresses and refer to ADS description.

Address strobe. When ADS is active (low), AO, A 1. and A2 and CSO, CS1, and CS2 drive the internal
select logic directly; when ADS is high, the register select and chip select signals are held at the logic
levels they were in when the low-to-high transition of ADS occurred.

Baud out. BAUDOUT is a 16x clock signal for the transmitter section of the ACE. The clock rate is
established by the reference oscillator frequency divided by a divisor specified by the baud generator
divisor latches. BAUDOUT may also be used for the receiver section by tying this output to RCLK.

CSO
CSl
CS2

12
13
14

14
15
16

9
10
11

Chip select. When CSO and CSl are high and CS2 is low, these three inputs select the ACE. When any
of these inputs are inactive, the ACE remains inactive (refer to ADS description).

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of
the modem status register. Bit 0 (A CTS) of the modem status register indicates that CTS has changed
states since the last read from the modem status register. If the modem status interrupt is enabled when
CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used
in the auto-CTS mode to control the transmitter.

DO
Dl
D2
D3
D4
D5
D6
D7

1
2
3
4
5
6
7
8

2
3
4
5
6
7
8
9

43
44
45
46
47
2
3
4

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD)
of the modem status register. Bit 3 (ADCD) of the modem status register indicates that DCD has
changed states since the last read from the modem status register. If the modem status interrupt is
enabled when DCD changes levels, an interrupt is generated.

DDIS

Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable
an external transceiver.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of
the modem status register. Bit 1 (ADSR) of the modem status register indicates DSR has changed
levels since the last read from the modem status register. If the modem status interrupt is enabled when
DSR changes levels, an interrupt is generated.

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to
establish communication. DTR is placed in the active level by setting the DTR bit of the modem control
register. DTR is placed in the inactive level either as a result of a master reset, during loop mode
operation, or clearing the DTR bit.

INTRPT

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced.
Four conditions that cause an interrupt to be issued are: a receiver error, received data that is available
or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status
interrupt. INTRPT is reset (deactivated) either when the interrupt is serviced or as a result of a master
reset.

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output
signals (refer to Table 2).

NO.
N

NO.
FN

NO.

AO
Al
A2

28
27
26

31
30
29

ADS

BAUDOUT

NAME

~TEXAS

INSTRUMENTS
2-122

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLSI77B - MARCH 1994 - REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NAME

oun
OUT2

NO.
N

NO.
FN

NO.
PT

110

DESCRIPTION

34
31

38
35

34
31

Outputs 1 and 2. These are user·designated output terminals that are set to the active (low) level by
setting respective modem control register (MCR) bits (OUTI and OUT2). OUTI and OUT2 are set to
inactive the (high) level as a result of master reset, during loop mode operations, or by clearing bit 2
(OUT1) or bit 3 (OUT2) of the MCR.

Receiver clock. RCLK is the 16 x baud rate clock for the receiver section of the ACE.

RDI
RD2

21
22

24
25

19
20

Read inputs. When either RDI or RD2 is active (low or high respectively) while the ACE is selected,
the CPU is allowed to read status information or data from a selected ACE register. Only one of these
inputs is required for the transfer of data during a read operation; the other input should be tied to its
inactive level (i.e., RD2 tied low or RDI tied high).

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the
modem status register. Bit 2 (TERI) of the modem status register indicates that Rf has transitioned from
a low to a high level since the last read from the modem status register. If the modem status interrupt
is enabled when this transition occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to the active level by setting the RTS modem control register bit and is set to the inactive
(high) level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS)
olthe MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver threshold control logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When
operating in the FIFO mode, one of two types of DMA signalling can be selected using the FIFO control
register bit 3 (FCR3). When operating in the TL 16C450 mode, only DMA mode 0 is allowed. Mode 0
supports single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports
multitransfer DMA in which multiple transfers are made continuously until the receiver FIFO has been
emptied. In DMA mode 0 (FCRO 0 or FCRO 1, FCR3 0), when there is at least one character in
the receiver FIFO or receiver holding register, RXRDY is active (low). When RXRDY has been active
butthere are no characters in the FIFO or holding register, RXRDY goes inactive (high). In DMA mode 1
(FCRO 1, FCR3 1), when the trigger level or the time-out has been reached, RXRDY goes active
(low); when it has been active but there are no more characters in the FIFO or holding register, it goes
inactive (high).

RCLK

SIN

Serial data input. SIN is serial data input from a connected communications device

SOUT

Serial data output. SOUT is composite serial data output to a connected communication device. SOUT
is set to the marking (high) level as a result of master reset.

TXRDY

Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FI~O
mode, one of two types of DMA signalling can be selected using FCR3. When operating in the
TL 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer
is made between CPU bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are
made continuously until the transmit FIFO has been filled.

VCC

5-V supply voltage

VSS

Supply common

WRI
WR2

18
19

20
21

16
17

XIN
XOUT

16
17

18
19

14
15

1/0

Write inputs. When either WRI or WR2 is active (low or high respectively) and while the ACE is
selected, the CPU is allowed to write control words or data into a selected ACE register. Only one of
these inputs is required to transfer data during a write operation; the other input should be tied to its
inactive level (i.e., WR2 tied low or WRI tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303. DALLAS. TEXAS 75265

2-123

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177B - MARCH 1994 - REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, V, ................................................... -0.5 V to 7 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, Te: FN package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: Nor PT package ............... 260°C
t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions
Supply voltage, V CC
High-level input voltage, V,H
Low-level input voltage, V,L
Operating free-air temperature, TA

MIN

NOM

MAX

UNIT

4.75

5.25

VCC

-0.5

0.8

°c

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

VOH§

High-level output voltage

IOH =-1 mA

VOL§

Low-level output voltage

IOL = 1.6 mA

Input current

VCC = 5.25 V,
V, = 0 to 5.25 V,

High-impedance-state output current

VCC = 5.25 V,
VSS=O,
VO=Ot05.25V,
Chip selected in write mode or chip deselect

"
IOZ

ICC

Supply current

Ci(CLK)

Clock input capacitance

Co{CLK)

Clock output capacitance

Input capacitance

Output capacitance

TYP*

MAX

VSS=O,
All other terminals floating

VCC = 5.25 V,
TA = 25°C,
SIN, DSR, DCD, CTS, and Ai at 2 V,
All other inputs at 0.8 V,
XTAL 1 at 4 MHz,
No load on outputs,
Baud rate = 50 kbitls

VCC=O,
VSS =0,
f= 1 MHz,
TA = 25°C,
All other terminals grounded

§ These parameters apply for all outputs except XOUT.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT

2.4

+All tYPical values are at V CC = 5 V and TA = 25°C.

2-124

MIN

0.4

±20

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177B- MARCH 1994 - REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

tcR

Cycle time. read (tw7 + 1d8 + Ids)

tcw

Cycle time. write (tw6 + td5 + td6)

tw1

Pulse duration. clock high

tXH

f=16MHzMax

tw2

Pulse duration. clock low

tXL

1= 16 MHz Max

tw5

Pulse duration, ADS low

tAOS

6, 7

tW6

Pulse duration, WR

twR

tw7

Pulse duration, RD

tRD

tw8

Pulse duration, MR

tMR

~tS

tsu1

Setup time, address valid belore ADS!

tAS

6, 7

tsu2

Setup time, CS valid belore ADS!

tcs

6,7

tsu3

Setup time, data valid belore WR1l or WR2!

tDS

tsu4

Setup time, CTS! belore midpoint 01 stop bit

th1

Hold time, address low after ADS!

tAH

6, 7

th2

Hold time, CS valid after ADS!

tcH

6,7

th3

Hold time, CS valid after WR1! or WR2l

twcs

th4

Hold time, address valid after WR1! or WR2l

twA

th5

Hold time, data valid after WR1! or WR2l

tDH

th6

Hold time, chip select valid after RD1! or RD2l

tRCS

ns
10

th7

Hold time, address valid after RD1! or RD2l

tRA

td4t

Delay time, CS valid belore WR1l or WR2!

tcsw

td5 t

Delay time, address valid belore WR1l or WR2!

tAW

td6 t

Delay time, write cycle, WR1! or WR2l to ADSl

twc

td7t

Delay time, CS valid to RD1l or RD2!

tCSR

td8t

Delay time, address valid to RD1l or RD2!

tAR

tdS

Delay time, read cycle, RD1! or RD2l to ADSl

tRC

td10

Delay time, RD1l or RD2! to data valid

tRVD

CL = 75 pF

td11

Delay time, RD1! or RD2l to Iloating data

tHZ

Cl= 75 pF

t Only applies when ADS

low

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
TEST CONDITIONS

PARAMETER

Disable time, RD1l! or RD2! 1 to DDIS!1
Charge and discharge times are determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

tW3

Pulse duration, BAUDOUT low

tlW

1_ 16 MHz, ClK + 2

tw4

Pulse duration, BAUDOUT high

tHW

1_ 16 MHz, elK + 2

td1

Delay time, XIN! to BAUDOUT!

tBLD

td2

Delay time, XIN!1 to BAUDOUT1

tBHD

PARAMETER

MAX

UNIT

ns
ns

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-125

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B- MARCH 1994- REVISED MARCH 1996

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 3)
ALT. SYMBOL

FIGURE

tSCD

td13

Delay time, stop to set INTRPT or read
RBR to LSI interrupt or stop to RXRDY t

tSINT

8,9,10,
11, 12

td14

Delay time, read RBR/LSR to resetlNTRPT

tRINT

8,9,10,
11, 12

PARAMETER
td12

Delay time, RCLK to sample

NOTE 3:

TEST CONDITIONS

MIN

MAX
10
1
70

CL= 75 pF

UNIT
ns
RCLK
cycle
ns

..
In the FIFO mode, the read cycle (RG) = 425 ns (min) between reads olthe receive FIFO and the status registers (Interrupt Identification
register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
ALT. SYMBOL

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

td15

Delay time, initial write to transmit start

tlRS

baudout
cycles

td16

Delay time, start to INTRPT

tSTI

baudout
cycles

id17

Delay time, WR (WR THR) to resetlNTRPT

tHR

CL = 75 pF

baudout
cycles
ns

td18

Delay time, initial write to INTRPT (THREt)

tSI

td19

Delay time, read IIRt to resetlNTRPT
(THREt)

tlR

CL= 75 pF

td20

Delay time, write to TXRDY inactive

tWXI

14,15

CL= 75 pF

td21

Delay time, start to TXRDY active

tSXA

14,15

CL= 75 pF

ns
baudout
cycles

t THRE = transmitter holdmg register empty; IIR = Interrupt Identification register.

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER

MIN

UNIT

ALT. SYMBOL

FIGURE

td22

Delay time, WR MCR to output

tMDO

td23

Delay time, modem interrupt to setlNTRPT

tSIM

td24

Delay time, RD MSR to resetlNTRPT

tRIM

MAX

td25

Delay time, CTS low to SOUTt

baudout
cycles

id26

Delay time, RCV threshold byte to RTSt

baudout
cycles

td27

Delay time, read of last byte in receive FIFO to RTSt

baudout
cycles

td28

Delay time, first data bit of 16th character to RTSt

baudout
cycles

td29

Delay time, RBRRD low to RTSt

baudout
cycles

~TEXAS

INSTRUMENTS
2-126

POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177B - MARCH 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

4-.--,------------N-------------------..:
I
XIN

BAUDOUT
(1/1)
td1

BAUDOUT
(112)

BAUDOUT
(1/3)

BAUDOUT
(1/N)
(N)3)

I4-tw 3
I-

td2

-.1
I

!------I
I
I

j4-tw4+j

~~-------------

~------~\~\--------~

,~----------~
~ 2 XIN Cycles ~

~----I

I I1I

1,..------------

SO%)( Active

SO%

------------'1

I~--------

tdis(R) ~
-----Ih\l

~ tdis(R)
1 /1,..--_ _ __

DDIS

I
I

\SO%

ld104

I
I

SO%

i..

07-00

I+- th7t --+i

J.-- td9 --+1

!4-- tdSt --+I

__________~I
RD1, RD2

~._ _...I...-_ _

';(50% Validt )(SO%

1
1

----.:

)I(

--"""T"'I-'

"I tsu2

----------(

..I

td11

Valid Data

Y. .-----

t Applicable only when ADS is low
Figure 7. Read Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·129

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B-MARCH 1994-REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
RCLK

--fl

-+~td12

·' h

8CLKs

Sample Clock

TL16C4S0 Mode:

SIN \

Start /

Data

~\ts

5-8

Parity

Stop

Sample Clock
((

INTRPT
(data ready)

/SO%

SO% \..

.!'---

------------------------------~I

----+1

-14I4--.J.1

td13
14td14
1
1
INTRPT
~
(RCV error) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J.
SO%
SO%
1
I '-.~If__----

1\
I

\V=\r

RD1,RD2
: y
•~
(read RBR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r S_o......

v:::::\k'!

RD1, RD2
(read LSR) _ _ _ _ _-'-_ _ _ _ _ _ _ _ _ _ _ _S_o'*_.~~-------

-.1 I+- td14
1 I

Figure 8. Receiver Timing Waveforms

~TEXAS

INSTRUMENTS
2-130

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS177B - MARCH 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

)

SIN \

Sample Clock

Trigger Level
(FCR6, 7INTRPT
= 0, 0)

Data~its 5-8

'
-------,L....
P
--------------"[1
---J L
\-J

50%

td13
(see Note A)
INTRPT
Line Status
Interrupt (LSI)

__~~~)'~jll~n~~~~~~~___
50%

~I"'-

-------------------~,

50%

1
1

(FIFO at or above
trigger level)
(FIFO below
trigger level)

I
I

\.l\

d14

50%

I .....~I-------td14~

RD1 --------------~'\ AmlveJt~-~I------(RD LSR)
"---../ 50%
I

\.L Active

RD1
(RD RBR)

50% ' - - - . /

NOTE A: For a time-out interrupt, td13 = 9 RCLKs.

Figure 9. Receive FIFO First Byte (Sets DR Bit) Waveforms

Sample Clock

P!.- '}
I

Time·Out or
Trigger Level
Interrupt

1d13
(see Note A)
Line Status
Interrupt (LSI)

--.!

:• •1

1d14

---r-----I:X

*'------T-=
: -

1 _ _ _ _ _ _ _ _ _ _ _ _- - - .

RD1, RD2
(RD RBR)

trigger level)

td14 -1'14e----Pl~

=======~q~~~~~~-},-5-!r-Y.-----1d13

RD1, RD2
(RD LSR)

(FIFO at or above

-50:-- trigger level)

~ (FIFO below

_ _ _ _ _ _ _.....,1" 1 50%

~ 50%

_ _ _.....

50%)1( Active

><=

Previous Byte
Read From FIFO
NOTE A: For a time-out interrupt, td13 = 9 RCLKs,

Figure 10. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-131

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B-MARCH 1994-REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)

50%

~
I
I
I
I
I
I

SIN~
(first byte)

--..J

Stop " - - -

Sample Clock

Active

SeeNoteA

--+1

~
--------5o-%~~~______~I'~(----------~)I~50-%----

id13
(see Note B)

td14

NOTE A: This is the reading of the last byte in the FIFO.

Figure 11. Receiver Ready (RXRDY) Waveforms, FCRO = 0 or FCRO = 1 and FCR3 = 0 (Mode 0)

II~--------~

RD
(RD RBR)

SIN
(first byte that reaches
the trigger level)

50% \

Active
II

SeeNoteA

Sample Clock
td13
(see Note B)

~
I

!
I

id14 ---;.-.:

50%~~________TNI~________~jI~5-~-Yo---NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, !d13 = 9 RCLKs.

Figure 12. Receiver Ready (RXRDY) Waveforms, FCRO

~TEXAS

INSTRUMENTS
2-132

POST OFFICE BOX 655303 • DAUAS, TEXAS 75265

=1 or FCR3 =1 (Mode 1)

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLSl77B- MARCH 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

)..s:rt
/ Oa~Bits
'---..L-_~'r-_-JX

SOUT

ParRy

.1
1

fel15

\t..~
_~~rt

Stop

fel16

~
I

INTRPT
(THRE)

50%

fel17

-.I

14--

I+--+j-

fel18

..:.:.I J4- td17

(WR:~ ~

r;;;:\. .-----------------it--

50%

td19

ROIIR

...

-----------------------------------------------~
Figure 13. Transmitter Timing Waveforms

By1e#l

t,..5-0%-------;N

(WRTHR)

1
1

SOUT

X...

_ _ _ _ _o_a_ta_ _--.,I~

Stop

fel20

~
1

--+i ~

td21

________..J1_--------------~
50%

Byte #16

' \ 50%

Figure 14. Transmitter Ready (TXRDY) Waveforms, FCRO

(WRTHR)

v-::::-\ __~tart

_pa_r_ity_1

=0 or FCRO =1 and FCR3 =0 (Mode 0)

t ,..-----~~~l------50%
,

----------,X

SOUT _ _ _ _ _o_a_ta_ _ _ _

fel20

Parity

~ ,,~rt

Stop

fel21

~
~

50% lr----F-IF-O-F-UI-I--"""",5_0%
_ __

Figure 15. Transmitter Ready (TXRDY) Waveforms, FCRO

=1 and FCR3 =1 (Mode 1)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-133

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLlS177B - MARCH 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
WR
(WRMCR)

1'----fct22 -;4---...1
1

fct22

RTS, DTR, - - - - - -......\L50%
OUT1, OUT2
'\

50%r

\50%
fct23

(!~:~~

-*-'I

_______--Jl~50-%---5O%--..}. . -.--J{50%
td24~

(RD

M~~

_ _ _ _ _ _ _ _.__J

50%'\

: - fct23
1

\ _______~y~5O%---------Figure 16. Modem Control Timing Waveforms

CTS

t50%
I

HIsu4

50%/ Ii

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

I4-tI- fct25
SOUT

50%{""-"(_

I rj~'I....iL(_ ____I1

____II \ /

t
I

Midpoint of Stop Bit

Figure 17. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit

SIN

~ I""_ _--...JI
__

fct26

fct27

_ _ _--11_ __

____________J~50%

,\50%

- - - - - - - - - - - _ - - - -_ _ _ 1

. 50%
. __________

Figure .18. Auto-RTS Timing for RCV Threshold of 1, 4, or 8 Waveforms

~1EXAS

2-134

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS177B - MARCH 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
Midpoint of Data Bit 0
SIN\,

/15th Character!

; h Character!

14-

td28

ld29

--I

~------~!-----

________________________________________J;Ysa%

~~S_O%______

------------------------------------------------~'\SO%

Figure 19. Auto-RTS Timing for RCV Threshold of 14 Waveforms

APPLICATION INFORMATION

SOUT
D7-oo

D7-DO
MEMRor UOR
MEMWorUON
INTR
C

RESET

U
B
u
s

RD1

RTS

WR1

DTR

INTRPT

DSR

DCD

SIN

TL16CS50C
(ACE)

...
EIA
232-D Drivers
and Receivers

CTS

<=>

...

_L£
CS

H-C

ADS

XIN

WR2

RD2
CS2

XOUT

CS1

BAUDOUT

cso

RCLK

l.c

T
-=-

3.072 MHz

I
-=-

Figure 20. Basic TL16C550C Configuration

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·135

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTO FLOW CONTROL
SLLS1 TIB - MARCH 1994 - REVISED MARCH 1996

APPLICATION INFORMATION
Receiver Disable

Microcomputer
System

Data Bus

8-Blt
Bus Transceiver

WR1
TL16C55OC
(ACE)

Data Bus

....

D7-DO

DDIS

Driver Disable

Figure 21. Typical Interface for a High Capacity Data Bus

~TEXAS

2-136

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C550C
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH AUTOFLOW CONTROL
SLLS1ns - MARCH 1994 - REVISED MARCH 1996

APPLICATION INFORMATION
Alternate

TL16C550C

XIN r-1;;..:.6_____C_ry_s.ta_1c_0-41n.....
tro_l---,

A16-A23

~------------~

12
t-------I CSO
Address
13
Decoder t-----'--I CS1

17
XOUT J------A.IVv-........- -.....---,
15
BAUDOUT
9
RCLK

L-____-t------1-41CS2

CPU

DTR
RTS~----I

ADSt-~----------------------~2~5 ADS
RSUABTI--4I~-~-~,

OUT1

35
>UI------------I MR

OUT2

AO-A2
ADO-AD151\----,-_----r_-f1
PHI1

,-----1'1

DO-D7

38
DCD I--'-"---~
~

~w
~

description
The TL16C552 is an enhanced dual channel version of the popular TL 16C550 asynchronous communications
element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters

IBM PC/AT is a trademark of International Business Machines Corporation.

~':':1!8:="1;"~,,,::,c=...":i
not II8CI888IIIy Include
oro"

standard warranty. Producllon praceulng _
IBIIfng
po..........

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75255

2-151

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 028 - DECEMBER 1990 - REVISED MARCH 1996

description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL 16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
between 1 and (2 16 _1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.

functiohal block diagram
CTSO
DSRO
DCDO
RIO
SINO
CSO
DB-DB7

r---

26
ACE
#1

30
41

45
9

32
14-21

12
11

DSR1 5

DCD1 8
ACE
#2

RI1 6

lOR
RESET
ClK

SIN1 62

CS1 3

RXRDYO
TXRDYO

RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1

...... -

35-33

Select
and
Control
logic

37
39
4

ERR
SlCT
BUSY
PE
ACK
PEMD
CS2
ENIRQ

......

53·-46
57

67
68

BOO

Parallel
Port

38
43

~TEXAS

INSTRUMENTS
2-152

INTO

"---

CTS1 13

lOW

DTRO
SOUTO

8
8

AO-A2

RTSO

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

58
59

PDO-PD7
INIT
AFD
STB
SLiN
INT2

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSI 02B - DECEMBER 1990 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NAME

NO.

110

DESCRIPTION

ACK

Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.

AFD

I/O

Line printer autofeed. AFD is an open·drain line that provides the printer with an active·low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to VDD of approximately 10 kn.

35,34,33

Address lines AO-A2. AO, A I, and A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.

BDO

Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the
parallel port is read. This output can control the system bus driver (74lS245).

BUSY

Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.

AO,Al,A2

Clock input. ClK is an external clock input to the baud rate divisor of each ACE ..

32,3,38

Chip selects. CSO, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CSO) and 2 (CSI ). CS2 enables the signals to the printer port.

CTSO, CTSI

28, 13

Clear to send inputs. The logical state of CTSO or CTSI is reflected in the CTS bit of the modem
status register (CTS is bit 4 olthe modem status register, written MSR4) of each ACE. A change
of state in either CTS terminal, since the previous reading of the associated modem status register,
causes the setting of delta clear to send (&CTS) bit (MSRO) of each modem status register.

DBO-DB7

14-21

I/O

Data bits DBO - DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,
and status information between the Tl16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. DO is the least significant bit (lSB) and is the
first serial data bit to be received or transmitted.

DCDO, DCDI

29,8

Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or &DCD) bit
of the modem status register indicates whether the DCD input has changed states since the
previous reading of the modem status register. DCD has no affect on the receiver.

DSRO, DSRI

31,5

Data set ready inputs. The logical state of DSRO and DSRI is reflected in MSR5 of its associated
modem status register. The MSRI (delta data set ready or &DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
register.

DTRO,DTRI

25,11

Data terminal ready lines. DTRO and DTRI can be asserted low by setting modem control register
bit 0 (MCRO) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCRO)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.

ENIRQ

Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
Input is tied high, the INT2 output is internally tied to the PRINT signal in the Ii~e printer status
register. INT2 is latched high on rising edge of ACK.

ERR

Line printer error.· ERR is an input line from the printer. The printer reports an error by holding this
line low during the error condition.

GND

7,27,54

INIT

I/O

Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer iniiializetion routine to be started. This terminal has an internal pullup
resistor to VDD of approximately 10 kn.

lOR

InpuVoutput read strobe. lOR is an active-low input that enables the selected channel to output
data to the data bus (DBO-DB7). The data output depends upon the register selected by the
address inputs AO, A I, A2, and chip select. Chip select 0 (CSO) selects ACE #1, chip select 1 (CS1)
selects ACE #2, and chip select 2 (CS2) selects the printer port.

lOW

InpuVoutput write strobe. lOW is an active-low input causing data from the data bus to be input to
either ACE orto the parallel port. The destination depends upon the register selected by the address
inputs AO, A I, A2, and chip selects CSO, CS1, and CS2.

ClK
CSO, CS1, CS2

Ground (0 V). All terminals must be tied to ground for proper operation.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-153

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSI 02B - DECEMBER 1990 - REVISED MARCH 1996

Terminal Functions (continued)
TERMINAL

110

DESCRIPTION

45,60

Serial channel interrupts. INTO and INT1 are 3-state serial channel interrupt outputs (enabled by bit
3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition
and is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modem status. The interrupt is cleared upon
appropriate service. When reset, the interrupt output is in the high-impedance state.

Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of ACK.
It is enabled by. bit 4 of the write control register. Upon a reset, the interrupt output is in the
high-impedance state. Its mode is also controlled by ENIRQ.

53-46

I/O

PEMO

Parallel data bits (0-7). These eight lines (POO-P07) provide a byte wide input or output port to the
system.
Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of
paper.
Printer enhancement mode. When low, PEMD enables the write data register to the PDO-PD7Iines.
A high on this signal allows direction control olthe PDO-PD7 port by the DIR bit in the control register.
PEMD is usually tied low for the printer operation.

RESET

Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are
suspended. The modem control register along with its associated outputs are cleared. The line status
register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain
in an idle state until programmed to resume serial data activities. This input has a hysteresis level of
typically 400 mV.

RTSO,RTS1

24,12

Request to send outputs.. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control
register. Both RTSx terminals are set by RESET. A low on the RTSx terminal indicates that its ACE has
data ready to transmit. In half-duplex operations, RTSx controls the direction of the line.

RXRDYO,
RXRDY1

9,61

Receiver ready. RXRDYO and RXRDY1 are receiver direct memory access (DMA) signaling
terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3)
when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450
mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple
transfers that are made continuously until the receiver FIFO has been emptied are supported by
mode 1.

NAME

INTO,INT1

INT2

POO-P07

NO.

Mode O. RXRDYx is active (low) when in the FIFO mode (FCRO=1, FCR3=0) or when in the TL16C450
mode (FCRO=O) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx
terminal goes inactive (high).
Mode 1. RXRDYx goes active (low) in the FIFO mode (FCRO=1) when FCR3=1 and the time-out or
trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is
empty.
RIO, RI1

30,6

SINO, SIN1

41,62

SLCT

SLiN

I/O

Line printer select. SLiN is an open-drain input that selects the printer when it is active (low). This
terminal has an internal pullup resistor to VDD of approximately 10 kn.

26,10

Serial data outputs. SOUTO and SOUT1 are the serial data outputs from the ACE transmitter circuitry.
A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the
transmitter is disabled, when RESET is true (low), when the transmitter register is empty, or when in
the loop mode.

SOUTO, SOUT1

Ring indicator inputs. RIO and RI1 are modem control inputs. Their condition is tested by reading
MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or
MSR2) that indicates whether either input has changed states from high to low since the previous
reading of the modem status register.
Serial data inputs. SINO and SIN1 are serial data inputs that move information from the communication
line or modem to the TL 16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is
low state. Data on the serial data inputs is disabled when operating in the loop mode.
Printer selected. SLCT is an input line from the printer that goes high when the printer has been
selected.

~TEXAS

2-154

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

Terminal Functions (continued)
TERMINAL

NO_

NAME

I/O

DESCRIPTION

STB

1/0

Printer strobe. STB is an open-drain line that provides communication between the TL16C552 and the
printer. When it is active (low), it provides the printer with a signal to latch the data currently on the
parallel port. This terminal has an internal pullup resistor to VOD of approximately 10 kG.

TRI

3-state control. TRI controls the 3-state control of all 1/0 and output terminals. When TRI is asserted,
all 1/0 and outputs become high impedance, allowing board level testers to drive the outputs without
overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down
with an internal resistor that is approximately 5 kG.

22,42

Transmitter ready. TXRDYO and TXRDYI are transmitter ready signals. Two types of DMA signaling
are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode
ois allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between
CPU bus cycles) is supported by mode o. Multiple transfers that are made continuously until the
transmitter FIFO has been filled are supported by mode 1.
Mode o. When in the FIFO mode (FCRO=I , FCR3=0) or in the TL 16C450 mode (FCRO=O) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDY are active (low). Once
TXROY is activated (low), it goes inactive after the first character is loaded into the holding register of
transmitter FIFO.

TXRDYO,
TXRDYI

Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCRO=I) when FCR3=1 and there are no
characters in the transmitter FIFO. When the transmitter FIFO iscompletelyfull, TXRDYx goes inactive
(high).
VDD

23,40,64

Power supply. VOO is the power supply requirement is 5 V ±5%.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo (see Note 1) ................................... _.. -0.5 V to Voo + 0.3 V
Input voltage range, VI ................................................... _.......... -0.5 V to 7 V
Output voltage range, Va ........... _....................................... -0.5 V to Voo + 0,3 V
Continuous total power dissipation ... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 500 mW
Operating free-air temperature range, TA ........................................... -10°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to ground (VSS).

recommended operating conditions
Supply voltage, VDO

MIN

NOM

MAX

UNIT

4.75

5.25

VOD
0.8

Clock high-level input voltage, VIH(CLK)

-0.5

Clock lOW-level input voltage, VIL(CLK)
High-level input voltage, VIH

LOW-level input voltage, VIL

-0.5

Clock frequency, fclock
Operating free-air temperature range, TA

V
V

MHz

°C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265,

2-155

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSI 02B - DECEMBER 1990 - REVISED MARCH 1996

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage
TEST CONDITIONS

MIN

= -0.4 rnA for OBO-OB7,
=-2 rnA for POO-P07,
= -0.4 rnA for INIT, AFO, STB, and SLiN (see Note 2),
= -0.4 rnA for all other outputs

2.4

PARAMETER

MAX

UNIT

High-level output voltage

IOH
IOH
IOH
IOH

Low-level output voltage

IOL = 4 rnA for OBO-OB7,
IOL = 12 rnA for POO-P07,
IOL = 10 rnA for INIT, AFO, STB, and SLiN (see Note 2),
IOL = 2 rnA for all other outputs

0.4

Input current

VOO = 5.25 V,

All other terminals are floating

±10

II(CLK)

Clock input current

VI = Oto 5.25 V

±10

!1A
!1A

loz

High-impedance output current

Vo = 0 with chip deselected, or
VOO = 5.25 V,
Vo = 5.25 V with chip and write mode selected

±20

!1A

100

Supply current

VOO = 5.25 V,
No loads on outputs,
SINO, SIN1, OSRO, OSR1, OCOO, OC01, CTSO, CTS1,
RIO and Rll at 2 V,
Other inputs at 0.8 V,
Baud rate = 56 kbitls
Baud rate generator fclock = 8 MHz,

rnA

VOH

VOL

NOTE 2: These four terminals contain an internal pullup resistor to VOO of approximately 10 k.Q.

clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
MIN

MAX

UNIT
ns

twl

Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1)

tw2

Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1)

tW3

Pulse duration, master (RESET) low (see Figure 16)

1000

read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN

MAX

UNIT

tw4

Pulse duration, lOR low

tsul

Setup time, chip select valid before lOR low (see Note 3)

15.

tsu2

Setup time, A2-AO valid before lOR low (see Note 3)

thl

Hold time, A2-AO valid after lOR high (see Note 3)

th2

Hold time, chip select valid after lOR high (see Note 3)

idl

Delay time, tsu2 + tw4 + td2 (see Note 4)

175

Delay time, lOR high to lOR or lOW low

id2
NOTES:

3. The Internal address strobe IS always active.
4. In the FIFO mode,idl = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).

~TEXAS

INSTRUMENTS
2-156

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN

MAX

UNIT

1w5

Pulse duration, lOW low

lsu4

Setup time, chip select valid before lOW low (see Note 3)

lsu5

Setup time, A2-AO valid before lOW low (see Note 3)

lsu6

Setup time, 00- 07 valid before lOW high

th3

Hold time, A2-AO valid after lOW high (see Note 3)

th4

Hold time, chip select valid after lOW high (see Note 3)

th5

Hold time, 00- 07 valid after lOW high

id3

Delay time, lsu5 + tW5 + td4

175

Delay time, lOW high to lOW or lOR low
id4
NOTE 3: The Internal address strobe IS always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER

TEST CONOmONS

ipd1

Propagation delay time from lOR high to BOO high or from lOR low to
BOO low

CL= 100pF,

See Note 5

ten

Enable time from lOR low to 00-07 valid

CL= 100pF,

See Note 5

tdis

Disable time from lOR high to 00-07 released

CL= 100pF,

See Note 5

MIN

MAX

UNIT

NOTE 5: VOL and VOH (and the external loading) determine the charge and discharge time.

transmitter switching characteristics over recommended ranges of operating free-air temperature
.
and supply voltage (see Figures 6, 7, and 8)
PARAMETER

TEST CONOmONS

MAX

UNIT

RCLK
cycles

MIN

td5

Delay time, interrupt THRE low to SOUT low at start

td6

Delay time, SOUT low at start to interrupt THRE high

See Note 6

RCLK
cycles

id7

Delay time, lOW (WR THR) high to interrupt THRE high

See Note 6

RCLK
cycles

ida

Delay time, SOUT low at start to TXRDY low

CL= 100pF

RCLK
cycles

tpd2

Propagation delay time from lOW (WR THR) low to Interrupt THRE low

CL= 100pF

140

~d3

Propagation delay time from lOR (RD IIR) high to interrupt THRE low

CL= 100pF

140

tpd4

Propagation delay time from lOW (WR THR) high to TXRDY high

CL= 100pF

195

NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time.

-!!1 TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

2-157

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B - DECEMBER 1990 - REVISED MARCH 1996

receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9,10,11,12 and 13)
TEST CONDmoNS

PARAMETER

MIN

See Note 7

leis

Delay time from stop to INT high

tOO5

Propagation delay time from RCLK high to sample CLK high

tod6

Propagation delay time from lOR (RD RBRIRD LSR) high to reset interrupt low

CL= loopF

MAX

UNIT

RCLK
cycle

100

150

Propagation delay time from lOR (RD RBR) low to RXRDY high
150
ns
tOO7
...
NOTE 7: The receiver data available Indication, the overrun error Indication, thetngger level Interrupts and the active RXRDY IndicatIOn IS delayed
three RCLK cycles in the FIFO mode (FCRO = 1). After the first byte has been received, status indicators (PE, FE, BI) Is delayed three
RCLK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RCLK
cycle delays for trigger change level interrupts.

modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 14)
MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

tpde

Propagation delay time from lOW (WR MCR) high to RTS (DTR) lowlhigh

CL=100pF

100

todS

Propagation delay time from modem Input (CTS, DSR) lowlhigh to interrupt high

CL=100pF

170

Iodl0

Propagation delay time from lOR (RD MSR) high to interrupt low

CL=100pF

140

tpdll

Propagation delay time from RI high to interrupt high

CL=100pF

170

parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 15)
MIN

MAX

tsu7

Setup time, data valid before STB low

th6

Hold time, data valid after STB high

tw6

Pulse duration, STB low

lei 10

Delay time, BUSY high to ACK low

Defined by printer

tdll

Delay time, BUSY low to ACK low

Defined by printer

tw6

Pulse duration, ACK low

Defined by printer

tw7

Pulse duration, BUSY high

Defined by printer

1e112

Delay time, BUSY high after STB high

Defined by printer

~TEXAS

INSTRUMENTS
POST OFFICE eox 655303 • DAllAS. TEXAS 75285

UNIT

lis
lis
500

lIS

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

I..

CLK(XTAL1)

tw1

~ --'----r-=\,.---

"-J----~1

tw2
fclock

2V
O.8V

=8 MHz MAX

Figure 1. Clock Input (ClK) Voltage Waveform

2.54 V

Device Under Test

6800
TL16C552

82pFt

tlncludes scope and jig capacitance

Figure 2. Output load Circuit
TL16C552

Data Bus

<____---1>
-1>

Serial
Channel 1
Buffers

g.Pin D Connector

Serial
Channel 2
Buffers

g.Pln D Connector

Address Bus _ _ _ _ _

Dual

Ace and
Printer
Port

Control Bus
Option
Jumpers

Parallel
Port

RIC

25·Pln D Connector

Network

Figure 3. Basic Test Configuration

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-159

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSl 02B - DECEMBER 1990 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
A2, A1, AD

X __________________ X

Valid

50%

1
1

5O~¥
1

I..

__JI~--------------

l~th1-+1
Valid

~1-------------+~1

tsu2

~-~--%------------

I+- th2 ----.j

tsu1

50%

Active
I
I

t pd 1 "

50% \ .

Valid

1,....-------

f~O%

I.....--I~>l-I- tdls

~~I_________________

50%

*. __________

~~~

~=.= 5O~*"~ X
1 :..
I"

tsu4 -----+.1
tsus

50"

¥'-_______

-------------+·1

.....

I + - - tws

y'"S-O-%-----'lII\

----'1"

td4

tsu6

I..

.1 4

00-07 ----------------------------~\. Valid Data

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

thS

50%\ . Active

·1

()~ ~~ctive
50'ro " \ . . : : :

~I~-----------------

Figure 5. Write Cycle Timing Waveforms

2-160

~-----

I+- th4 ---+1
I
td3

.1"

00"

Active

tpd1

Figure 4. Read Cycle Timing Waveforms

Data
00-07 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ( \ . Valid Data

A2,A1,AO

Activ

(I~II
OR

I..
I

- - - -_ _ _ _ _+-1---",I

La
-+~

50%

I....-----td2 ________

ten

----'1
I
I

l + - - tw4

BOO

(~!

I
150%

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
Serial Out
(SOUT)

Data Bits S-8

SO%

I"'--'--------'
tds--k--+I

Parity

-¥

Interrupt - - -.....{
(THRE)
I SO%.!"---Il SO%
tpd2 I"
~I
I
1
l"-ld7-'1
IOW::\L

(WRTHR)SO%~

SO%L

SO%}..._ _ _ _ _ _- J

~tpd2"'1

1
1

SO%

tpd3~1

SO%V

V""5-0.-V.--

lOR
(RD IIR)

Figure 6. Transmitter Timing Waveforms
lOW \
(WRTHR)

Byte #1

ISO%
1

SOUT

Data
tpd4

I..

TXRDY

Parity

~ SO% Start

Stop

td8 ----1+--+1
SO%\

S0 %

Figure 7. Transmitter Ready Mode 0 Timing Waveforms
((

lOW
(WRTHR)

SO%
1 Start of

'-----' 1

SOUT

Data

Parity

Stop

Start

~i"--~'

-+*-

tpd4
td8
TXRDY ______________-J)trS-O-%-----F-IF-O-F-U-II------~\r\----~~ SO%

Figure 8. Transmitter Ready Mode 1 Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-161

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B-DECEMBER 1990- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

l-------!rL
I+-

RCLK

s--------.:~:
CLK

______________

tpd5

~IL

T(:::::i:;;E~~
r:~_D_a_ta_B_it_s_5_-_8_ ~
Start

.....

data)

Sample

CLK-L_~_~~)I\~~_ _ _~_ _~_ _ _~~__~______~)r-

~ f r-~-----',I, ~ ~no

td9
Interrupt
(data ready or
500;.
RCVR ERR) __________________________________- - - J

tpd6

Active

~
~I

,1500;.

"-------J

Figure 9. Receiver Timing Waveforms

SIN
Sample
CLK
Trigger
Interrupt
(FCR6, 7=0, 0)

~fataBits5-8 ~

I I I It'~,--'----L-~II-....a...~_

----------------'"'f""----\L

II ~LIr
I
500;.

---------------+'1
Id9 -

lOR
(RD RBR)

Line Status
Interrupt (LSI)

~no,

tpd6 ~I

I I

:
I~_ _---..

500;.~

500;.1

tpd6-H
lOR
(RD LSR)

~-5-0-0;.--

Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms

~TEXAS

INSTRUMENTS
2-162

(FIFO at or above
trigger level)

~ (FIFO below

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

trigger level)

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

x:x:::'J

SIN _ _ _ _

I I I I I

Sample
ClK --'---'---.1..--''+-1--'-_--'_"-----'-_

td9~

1-4-

TimeOut or
(see Note A)
Trigger level
Interrupt ____________J]f50%

I,----L>(,

:\..

5_0_%. . 4-~~~~~~~':~-C\_1-1___________

\...;,~___
td9

lOR
(RD lSR)

--------+I-~\
I

t pd6

:'"

l~--~'------I

50%

Active

lOR \
(RD RBR)

(FIFO below
trigger level)

~tpd6

-.1
lSI - - - - ,
Interrupt

(FIFO at or above
trigger level)

50%)<. . ____

Active

150%

50%\,

Active

Previous Byte
Read From FIFO

Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
I(

))

lOR
(RD RBR)
SIN
(first byte)

50%\
1

Active

See Note A

1
1
1

Sample
ClK

1
1

1d9~
RXRDY

(see Note B)

!.-

50%\

1
1

f(
}j

tpd7 ---.,

{50%
~

Figure 12. Receiver Ready Mode 0 Waveforms
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCRO=1, then td9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.

~TEXAS

INSTRUMENTS
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2-163

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
I(

lOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)

0;.\

Active
1

See Note A

1
1
1
1

Sample
ClK

RXRDY

td9 ---.J
(see Note B)

1
1

0;.\

{SO

tpd7~

0;.

NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCRO=1 , then td9 = 3 RCLK cycles. For a trigger change level interrupt, td9 = 8 RCLK

Figure 13. Receiver Ready Mode 1 Waveforms

IOW~\...._ _So_o".J0 1

(WR MCR)

'+-+t-

RTS, DTR

CTS, DSR, DCD

lOR
(RD MSR)

~ tpd8

tpd8

--------~\I

II~-----SOo;.

-J

1..._ _ _ _ _ _ _ _ _ _

_ _ _s_oo_*,.J 1
tpd9

INTO, INTI,
lINT,2INT

..._ _
SO_"".J0

--1+---+1

1 SOo;.

I..

tpd9

Soo;.)rr--So-""~o~I.._ _s_o_o;.J}rr--~~I.._ _SO_""JO~
------~

tpdl0 ~

tpdll

\..J

SOo;.

I..

I
\

Figure 14. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
2·164

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0;. ,,....---

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B-DECEMBER 1990- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
DATA

~1...5_00_l"_ _

Valid

tsu7~1

~th6

----5-o0~l"~~5-0o/.-0--------------------------

tw6

50 % L 1 5 0 %
1

I.-- td10-----.j
14
i
l~td11

tw6

50%~ 50% ~1...50-o/.-0___________

BUSY

td12

l-tw7~

Figure 15. Parallel Port Timing Waveforms

RESET

50%

L-'
1

50%

twa

Figure 16. RESET Voltage Waveform

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-165

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data.
Mnemonic abbreviations are shown in the Table 1 for the registers.
Table 1. Internal Register Types With Mnemonics
CONTROL

MNEMONIC

STATUS

MNEMONIC

DATA

MNEMONIC

Line control register

LCR

Line status register

LSR

Receiver buffer register

RBR

FIFO control register

FCR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MCR

Divisor latch LSB

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register
(bit 7) to select the register to be written to or read from (see Table 2).
Table 2. Register Selectiont*
DLAB

MNEMONIC

RBR

Receiver buffer register (read only)

THR

Transmitter holding register (write only)

IER

Interrupt enable register

IIR

Interrupt identification register (read only)

X
X
X

FCR

LCR

Line control register

MCR

Modem control register

FIFO control register (write only)

LSR

Line status register

X
X

MSR

Modem status register

SCR

Scratch register

DLL

Divisor latch (LSB)

DLM

Divisor latch (MSB)

t X = Irrelevant, L = low level, H = high level

:j: The serial channel is accessed when either csa or CS1 is low.

Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis.
As an example, LCR7 refers to line control register bit 7.
The transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of
data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always
the first serial data bit received and transmitted. The ACE data registers are double buffered so that read and
write operations may be performed when the ACE is performing the parallel-to-serial or serial-to-parallel
conversion.

~TEXAS

INSTRUMENTS
2·166

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PRINCIPLES OF OPERATION

accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.

Table 3. Summary of Accessible Registers
ADDRESS

BIT 3

BIT 2

BIT 1

BIT 0

RBR
(read only)

Data
Bit 7
(MSB)

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0
(LSB)

THR
(write only)

Data
Bit 7

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

BIT 7

BITS

DLL

Bit 7

Bit 6

BitS

Bit4

Bit3

Bit2

Bit 1

Bit 0

DLM

BitlS

Bit 14

Bit 13

Bit 12

Bitll

Bitl0

Bit 9

BitS

IER

(EDSSI)
Enable

(ERLSI)
Enable

(ERBFI)
Enable

modem
status
interrupt

receiver

(ETBEI)
Enable
transmitter
holding

FCR
(write only)

IIR
(read only)

LCR

Receiver

received
data
available
interrupt

FIFO

empty
interrupt
Receiver
FIFO

reset

Interrupt ID
Bit (2)+

Interrupt ID
Bit(l)

Interrupt ID
Bit (0)

011
interrupt
pending

(EPS)
Even parity
select

(PEN)
Parity
enable

(STB)
Number 01
stop bits

(WLSB1)
Word length
select bit 1

(WLSBO)
Word length
select bit 0

Loop

Enable
external
interrupt
(INTO or
INTI)

OUTI
(an unused
internal
signal)

(RTS)
Request
to send

(DTR)
Data
terminal
ready

(61)
Break
interrupt

(FE)
Framing
error

(PE)
Parity
error

(OE)

Overrun
error

(DR)
Data
ready

DMA
mode
select

Tranmitter

Stick
parity

Receiver
Trigger
(LSB)

Reserved

Trigger
(MSB)
FIFOs
Enabled+

FIFOs
Enabled+

(DLAB)

Set
break

Divisor latch
access bit

line
status
interrupt

MCR

LSR

Error in
receiver
FIFO+

(TEMT)

(THRE)

Transmitter

empty

holding

Reserved

FIFO
Enable

MSR

detect

(RI)
Ring
indicator

(DSR)
Dataset
ready

(CTS)
Clear
to send

("'DCD)
Delta
data carrier
detect

(TERI)
Trailing
edge ring
indicator

("'DSR)
Delta
data set
ready

("'CTS)
Delta
clear
to send

Bit7

Bit6

BitS

Bit4

Bit 3

Bit2

Bit 1

Bit 0

(DCD)

Data carrier

SCR

t DLAB = 1
:j: These bits are always 0 when FIFOs are disabled.

~TEXAS

INSTRUMENTS
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2-167

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO control register (FCR)
This write-only register is at the same location as the IIR. It enables and clears the FIFOs, sets the trigger level
of the receiver FIFO, and selects the type of DMA signaling. The contents of FCR are described in Table 3 and
the following bulleted list.
•

Bit 0: FCRO enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be reset by
clearing FCRO. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL 16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCRO =1.

•

Bit 1: FCR1 =1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the shift
register.

•

Bit 2: FCR2=1 clears all bytes in the transmitter FIFO and resets the counter. This does not clear the shift
register.

•

Bit 3: FCR3=1 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCRO=1.

•

Bits 4 and 5: These two bits are reserved for future use.

•

Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt as shown in Table 4.
Table 4. Receiver FIFO Trigger Level
RECEIVER FIFO

BIT

TRIGGE.R LEVEL (BYTES)

a
a

FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1.

LSRO is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is cleared.

IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt IIR = 04.

Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.

IIR = 04 (receive data available indication) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.

~TEXAS

2-168

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1.

A FIFO timeout interrupt occurs when the following conditions exist:
a.

Minimum of one character in FIFO

Last received serial character was longer than four continuous previous character times ago (if two stop
bits are programmed, the second one is included in the time delay).

The last CPU read of the FIFO was more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.

By using the RCLK input for a clock signal, the character times can be calculated. (The delay is proportional
to the baud rate.)

The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received, when
there has been no time-out interrupt.

A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.

Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCRO = 1, IER = 1).
1.

When the transmitter FIFO is empty, the THR interrupt (IIR = 02) occurs. The interrupt is cleared as soon
as the THR is written toorthe IIR is read. One to sixteen characters can be written to the transmit FIFO when
servicing this interrupt.

The transmitter FIFO empty indications are delayed one character time minus the last stop bit time
whenever the following occurs:
THRE = 1 and there has not been a minimum of two bytes at the same time in transmitter FIFO, since the
last THRE = 1. The first transmitter interrupt after changing FCRO is immediate, however, assuming it is
enabled.
.

Receiver FIFO trigger level and character time-out interrupts have the same priority as the received data
available interrupt. The THRE interrupt has the same priority as the transmitter FIFO empty interrupt.

FIFO polled mode operation
Clearing IERO, IER1, IER2, IER3, or all, with FCRO = 1, puts the ACE into the FIFO polled mode. Receiver and
transmitter are controlled separately. Therefore, either or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
ACE status.

interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTO or
INT1) output. All interrupts are disabled by clearing IERO - IER3. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are described in Table 3 and in the following bulleted list.
•

Bit 0: IERO, when set, enables the received data available interrupt and the time-out interrupts in the FIFO
mode.

~TEXAS

INSTRUMENTS
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2-169

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
•

Bit 1: IER1, when set, enables the THRE interrupt.

•

Bit 2: IER2, when set, enables the receiver line status interrupt.

•

Bit 3: IER3, when set, enables the modem status interrupt.

•

Bits 4 - 7: IER4 - IER7 are always cleared.

interrupt identification register (IIR)
In order tominimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are shown in the following bulleted list:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the IIR. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.

Table 5. Interrupt Control Functions
FIFO
MODE
ONLY

INTERRUPT
IDENTIFICATION
REGISTER
BIT 0

INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL

BIT 3

BIT 2

BIT 1

First

INTERRUPT TYPE

INTERRUPT SOURCE

None

Receiver line status

OE, PE, FE, or BI

LSR read

Second

Received data available

Receiver data available or trigger level
reached

RBR read until FIFO
drops below the
trigger level

Second

Character time-out
indication

No characters have been removed
from or input to the receiver FIFO
during the last four character times and
there is at least one character in it
during this time.

RBR read

Third

THRE

IIR read if THRE is
the interrupt source
orTHR write

Fourth

Modem status

CTS, DSR, RI, or DCD

MSR read

•

Bit 0: IIRO indicates whether an interrupt is pending. When IIRO is cleared, an interrupt is pending.

•

Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

•

Bit 3: IIR3 is always cleared when in the TL 16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.

•

Bits 4 and 5: IIR4 and IIR5 are always cleared.

•

Bits 6 and 7: IIR6 and IIR7 are set when FCRO=1.

~TEXAS

INSTRUMENTS
2-170

INTERRUPT RESET
CONTROL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR)
The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described
in the following bulleted list and shown in Figure 17.
•

Bits 0 and 1: LCRO and LCR1 are the word length select bits. The number of bits in each serial character
is programmed as shown in Figure 17.

•

Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character
as shown in Figure 17. The receiver always checks for one stop bit.

•

Bit 3: LCR3 is the parity enable bit 3. When LCR3 is high, a parity bit between the last data word bit and
stop bit is generated and checked.

•

Bit 4: LCR4 is the even parity select bit 4. When enabled, setting this bit selects even parity.

•

Bit 5: LCR5 is the stick parity bit 5. When parity is enabled (LCR3=1), LCR5=1 causes the transmission
and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity to a known
state and allows the receiver to check the parity bit in a known state.

•

Bit 6: LCR6 is the break control bit 6. When LCR6 is set, the serial output (SOUT1 and SOUTO) is forced
to the spacing state (low). The break control bit acts only on the serial output and does not affect the
transmitter logic. When the following sequence is used, no invalid characters are transmitted because of
the break:
Step 1. Load a zero byte in response to the transmitter holding register empty (THRE) status indication.
Step 2. Set the break in response to the next THRE status indication.
Step 3. Wait for the transmitter to be idle when transmitter empty status signal is set high (TEMT=1). Then
clear the break when the normal transmission has to be restored.

•

Bit 7: LCR7 is the divisor latch access bit (DLAB) bit 7. Bit 7 must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register or the interrupt enable register.

~TEXAS

INSTRUMENTS

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2-171

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR) (continued)

Word Length
Select
Stop Bit
Select

Parity Enable

Even Parity
Select

o 0 = 5 Data Bits
o 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits

o =1 Stop Bits

1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected

o=Parity Disabled
1

=Parity Enabled

o =Odd Parity
1

=Even Parity

Stick Parity

o =Stick Parity Disabled

Break Control

o =Break Disabled

Divisor Latch
Access Bit

=Stick Parity Enabled

1 = Break Enabled

o = Access Receiver Buffer
1

=Access Divisor Latches

Figure 17. Line Control Register Contents

line printer port (LPT)
The line printer port contains the functionality of the port included in the TL 16C452, but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PEMD) terminal. This
enhancement is the addition of a direction control bit, and an interrupt status bit.
register 0 line printer data register (LPD)

The LPO port is either output only or bidirectional, depending on the state of the extended mode terminal and
data direction control bits.
•

Compatibility mode (PEMO is low). Reads to the LPD register return the last data that was written to the
port. Write operations immediately output data to the POO-P07 terminals.

•

Extended mode (PEMO is high). Read operations return either the data last written to the LPT data register
when the direction bit is cleared to write, or the data that is present on POO-PO? when the direction is set
to read. Writes to the LPD register latch data into the output register, but only drive the LPT port when the
direction bit is cleared to write.

~TEXAS

2-172

INSTRUMENTS
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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990- REVISED MARCH 1996

PRINCIPLES OF OPERATION
line printer port (LPT) (continued)
Table 6 summarizes the possible combinations of extended mode and the direction control bit. In either
case, the bits of the LPO register are defined as follows:

Table 6. Extended Mode and Direction Control Bit Combinations
PEMD

DIR

PDO-PD7 FUNCTION
PC/AT mode - output

PS/2™ mode - output

PS/2T" mode - input

register 1 read line printer status register
The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT
connector terminals. In Table 7 (in the default column), are the values of each bit after reset in the case of the
printer being disconnected from the port.

Table 7. LPS Register Bit Description

BIT

DESCRIPTION

DEFAULT

Reserved

ERR

SLCT

t
t
t
t
t

ACK

BSY

Outputs are dependent upon device Inputs.

•

Bits 0 and 1: These bits are reserved and are always set.

•

Bit 2: This bit is the printer interrupt (PRINT, active low) status bit. When cleared indicates that the printer
has acknowledged the previous transfer with an ACK handshake (bit 4 of the control register is set). The
bit is cleared on the active to inactive transition of the ACK signal. This bit is set after a read of the status
port.

•

Bit 3: This bit is the error (ERR, active low) status bit corresponds to ERR input.

•

Bit 4: This bit is the select (SLCT) status bit corresponds to SLCT input.

•

Bit 5: This bit is the paper empty (PE) status bit corresponds to PE input.

•

Bit 6: This bit is the acknowledge (ACK, active low) status bit corresponds to ACK input.

•

Bit 7: This bit is the busy (BSY, active low) status bit corresponds to BUSY input (active high).

register 2 line printer control (LPC) register
The LPC register is read/write port that controls the POO- P07 direction and drive the printer control lines. Write
operations set or clear these bits, while read operations return the state of the last write operation to this register.
The bits in this register are described in Table 8.

PS/2 is a trademark of International Business Machines Corporation.

~TEXAS

INSTRUMENTS
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2-173

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSI 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line printer port (LPT) (continued)
Table 8. LPC Register Bit Description
BIT

DESCRIPTION

STB

AFD

INIT

SUN

INT2 EN

DIR

Reserved (0)

•

Bit 0: This bit is the printer strobe (STB) control bit. When this bit is set, the STB signal is asserted on the
LPT interface. When STB is cleared, the signal is negated.

•

Bit 1: This bit is the auto feed (AFD) control bit. When this bit is set, the AFD signal is asserted on the LPT
interface. When AFD is cleared, the signal is negated.

•

Bit 2: This bit is the initialize printer (INIT) control bit. When this bit is set, the INIT signal is negated. When
INIT is cleared, the INIT signal is asserted on the LPT interface.

•

Bit 3: This bit is the select input (SUN) control bit. When this bit is set, the SLCT signal is asserted on the
LPT interface. when SUN is cleared, the signal is negated.

•

Bit 4: This bit is the interrupt request enable (INT2 EN) control bit. When set, this bit enables interrupts from
the LPT port whenever the ACK signal is released. When cleared, INT2 EN disables interrupts and places
INT2 signal in 3-state.

•

Bit 5: This bit is the direction (DIR) control bit (only used when PEMD is high). When this bit is set, the output
buffers in the LPD port are disabled allowing data driven from external sources to be read from the LPD port.
When DIR is cleared, the LPD port is in output mode.

line status register (LSR)
The LSR is a single register that provides status indications. The LSR is shown in Table 9 and is described in
the following bulleted list.

Table 9. Line Status Register Bits
1

Ready

Not ready

LSR1 overrun error (OE)

Error

No error

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

LSR BITS
LSRO data ready (DR)

LSR5THRE

Empty

Not empty

LSR6 transmitter empty (TEMT)

Empty

Not empty

Error in FIFO

No error in FIFO

LSR7 receiver FIFO error

LSR IS Intended only for factory test. It should be considered as read only by applications software .

~TEXAS

INSTRUMENTS
2-174

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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (LSR) (continued)
•

Bit 0: LSRO is the data ready (DR) bit. DR is set high when an incoming character has been received and
transferred into the receiver buffer register or the FIFO. LSRO is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.

•

Bit 1: SR1 is the overrun error (OE) bit. OE indicates that data in the receiver buffer register was not read
by the CPU before the next character was transferred into the receiver buffer register overwriting the
previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An OE
occurs in the FIFO mode after the FIFO is full and the next character is completely received. The OE is
detected by the CPU on the first LSR read after the overrun happens. The character in the shift register is
not transferred to the FIFO but it is overwritten.

•

Bit 2: LSR2 is the parity error (PE) bit. PE indicates that the received data character does not have the
correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared
when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with a
particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

•

Bit 3: LSR3 is the framing error (FE) bit. FE indicates that the received character did not have a valid stop
bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing
level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the
framing error is associated with a particular character in the FIFO. LSR3 reflects the error when the
character is at the top of the FIFO.

•

Bit 4: LSR4 is the break interrupt (BI) bit. BI is set when the received data input is held in the spacing
(cleared) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The
BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO, LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.

LSR1 - LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting
IER2=1 in the interrupt enable register.
•

Bit 5: LSR5 is the THRE bit. THRE indicates that the ACE is ready to accept a new character for
transmission. The THRE bit is set when a character is transferred from the transmitter holding register
(THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading of the transmitter holding
register by the CPU. LSR5 is not reset by a CPU read of the LSR. In the FIFO mode when the transmitter
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. When THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.

•

Bit 6: LSR6 is the transmitter empty (TEMT) bit. TEMT is set when the THR and the TSR are both empty.
LSR6 is cleared when a character is loaded into the THR and remains low until the character is transferred
out of SOUTo TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the transmitter
FIFO and shift register are empty, this bit is set.

•

Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in the TL 16C450 mode. In FIFO
mode, it is set when at least one of the following data errors is in the FIFO: PE, FE, or BI indication. It is
cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.

~TEXAS

INSTRUMENTS
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2-175

TL16C552
DUAL ASYCHRONOUSCOMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 028 - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
1.

It initializes the transmitter and receiver clock counters.

It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared. All of the discrete
lines, memory elements, and miscellaneous logic associated with these register bits are also cleared or
turned off. The LCR, divisor latches, RBR, and transmitter buffer register are not effected.

Following the removal of the reset condition (RESET high), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the affect of a reset on the ACE is given in Table 10.

Table 10. RESET Affects On Registers and Signals
REGISTER/SIGNAL

RESET CONTROL

RESET

All bits cleared (0-3 forced and 4-7

Interrupt enable register

Reset

Interrupt identification register

Reset

Bit 0 is set, bits 1, 2, 3, 6, and 7 cleared
Bits 4-5 are permanently cleared

permanent)

Line control register

Reset

All bits cleared

Modem control register

Reset

All bits cleared

FIFO control register

Reset

All bits cleared

Line status register

Reset

All bits cleared, except bits 5 and 6 are set

Modem status register

Reset

Bits 0-3 cleared, bits 4-7 input signal

SOUT

Reset

High

Interrupt (receiver errs)

Read LSRlReset

Interrupt (receiver data ready)

Read RBRIReset

Cleared

Read IIRlWrite THR/Reset

Cleared

Read MSRlReset

Cleared

Interrupt (THRE)
Interrupt (modem status changes)

Cleared

OUT2

Reset

High

RTS

Reset

High

DTR

Reset

High

OUT1

Reset

High

~TEXAS

INSTRUMENTS
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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 18. The MCR can be written
to and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high
input asserts a low (true) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:

Data Terminal
Ready

0= DTR Output High (inactive)
1 = DTR Output Low (active)

Request
to Send

0= RTS Output High (inactive)
1 = RTS Output Low (active)

Out 1

o = OUT1 Output High

Out 2

o = OUT2 Output High

Loop

o = Loop Disabled

1 = OUT1 Output Low

=OUT2 Output Low

1 = Loop Enabled

Bits are Cleared

Figure 18. Modem Control Register Contents
•

Bit 0: When MCRO is set, the DTR output is forced low. When MCRO is cleared, the DTR output is forced
high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.

•

Bit 1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.

•

Bit 2: When MCR2 is set, OUT1 is forced low.

•

Bit 3: When MCR3 is set, the OUT2 output is forced low.

•

Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output (SOUT) is set to the marking (high) state, and the SIN is disconnected. The output of the TSR
is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD, and
RI) are disconnected. The modem control outputs (DTR, RTS, OIUT1, and OUT2) are internally connected
to the four modem control inputs. The modem control outputterminals are forced to their inactive state (high)
on the TL16C552. In the diagnostic mode, data transmitted is immediately received. This allows the
processor to verify the transmit and receive data paths of the selected serial channel. Interrupt control is
fully operational. However, interrupts are generated by controlling the. lower four MCR bits internally.
Interrupts are not generated by activity on the external terminals represented by those four bits.

•

Bits 5 - 7: These three bits(MCR5 - MCR7) are permanently cleared.

~TEXAS

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2-177

TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B- DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
ACE in addition to the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set when a control input from the modem
changes state and cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 - MSR7 are status indications of these lines. A
status bit = 1 indicates the input is a low. A status bit = 0 indicates the input is high. When the modem status
interrupt in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSRO - MSR3
is set. The MSR is a priority 4 interrupt. The contents of the MSR are described in Table 11.

Table 11. Modem Status Register Bits
MSRBIT

MNEMONIC

MSRO

,lCTS

DESCRIPTION
Delta clear to send

MSR1

,lDSR

Delta data set ready

MSR2

TERI

Trailing edge of ring indicator

MSR3

,lDCD

MSR4

CTS

Clear to send

MSR5

DSR

Data set ready

MSR6

Ring indicator

MSR7

DCD

Delta data carrier detect

Data carrier detect

•

Bit 0: MSRO is the delta clear to send (,~CTS) bit. LlCTS displays that the CTS input to the serial channel
has changed state since it was last read by the CPU.

•

Bit 1: MSR1 is the delta data set ready (LlDSR) bit. LlDSR indicates that the DSR input to the serial channel
has changed state since the last time it was read by the CPU.

•

Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High·to-Iow
transitions on RI do not activate TERI.

•

Bit 3: MSR3 is the delta data carrier detect (LlDCD) bit. LlDCD indicates that the DCD input to the serial
channel has changed state since the last time it was read by the CPU.

•

Bit 4: MSR4 is the clear to send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUTo When the serial channel
is in the loop mode ((MCR4 = 1), MSR4 reflects the value of RTS in the MCR.

•

Bit 5: MSR5 is the data set ready (DSR) bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data to the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4=1), MSR5 reflects the value of DTR in the
MCR.

•

Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in the
loop mode (MCR4=1), MSR6 reflects the value of OUT1 in the MCR.

•

Bit 7: MSR7 is the data carrier detect (DCD) bit. DCD indicates the status of the data carrier detect (DCD)
input. When the channel is in the loop mode (MCR4=1), MSR7 reflects the value of OUT2 in the MCR.

~TEXAS

INSTRUMENTS
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TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSl 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Reading the MSR register clears the delta modem status indications but has no affect on the other status bits.
For LSR and MSR, the setting of status bits is inhibited during status register read operations. When a status
condition is generated during a read lOR operation, the status bit is not set until the trailing edge of the read.
If a status bit is set during a read operation, and the same status condition occurs, that status bit is cleared at
the trailing edge of the read instead of being set again. In the loop back mode, when modem status interrupts
are enabled, the CTS, DSR, RI and DCD input terminals are ignored. However, a modem status interrupt can
still be generated by writing to MCR3 - MCRO. Applications software should not write to the MSR.

parallel port registers
The TL 16C552 parallel port can interface to the device to a Centronics-style printer interface. When chip select
2 (CS2) is low, the parallel port is selected. Table 12 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (lOR) and write (lOW) terminal as
shown. The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the six most significant
bits. The status bits are printer busy BSY, acknowledge (ACK) which is a handshake function, paper empty (PE),
printerselected (SLCT), error (ERR) and printer interrupt (PRINT). The read control register allows the state
of the control lines to be read. The write control register sets the state of the control lines. They are direction
(DIR), interrupt enable (INT2 EN), select in (SUN), initialize the printer (INIT), autofeed the paper (AFD), and
strobe (STB) , which informs the printer of the presence of a valid byte on the parallel bus. The write data register
allows the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the
parallel port implementation used in the IBMTM serial parallel adaptor.

Table 12. Parallel Port Registers
REGISTER

BIT 6

BITS

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Read Data

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD~

Read Status

BSY

ACK

SLCT

ERR

Read Control

DIR

INT2 EN

SUN

INIT

AFD

STB

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD~

DIR

INT2 EN

SUN

INIT

AFD

STB

Write Data
Write Control

Table 13. Parallel Port Register Select
CONTROL TERMINALS
AO

lOR

lOW

CS2

Read data

Read status

Read control

Invalid

Write control

Invalid

Write data
. Invalid

~TEXAS

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2-179

Tl16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSl 02B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

programmable baud generator
The ACE serial channel contains a programmable baud rate generator that divides the clock (dc to a MHz) by
any divisor from 1 to (2 16-1). The output frequency of the baud rate generator is 16x the data rate (divisor #
clock + (baud rate x 16)) referred to in this document as RCLK. Two a-bit divisor latch registers store the divisor
in a 16-bit binary format. These divisor latch registers must be loaded during initialization. Upon loading either
of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The
baud rate generator can use any of three different popular frequencies to provide standard baud rates. These
frequencies are 1.8432 MHz, 3.072 MHz, and a MHz. With these frequencies, standard bit rates from 50- to
512-kbits/s are available. Tables 14, 15, and 16 illustrate the divisors needed to obtain standard rates using
.
these three frequencies.

Table 14. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

DIVISOR (N) USED TO
GENERATE 16 X CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

0.026
0.058

0.690

2.860

Table 15. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIVISOR (N) USED TO
GENERATE 16 X CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

3840
2560

1745

0.026
0.034

1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

~TEXAS

INSTRUMENTS
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0.312

0.628

1.230

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B - DECEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

programmable baud generator (continued)
Table 16. Baud Rates Using a 8.192-MHz Crystal
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000

DIVISOR (N) USED TO
GENERATE 16 X CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

1000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1

0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080

0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400

programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.

receiver
Serial asynchronous data is input into the SIN terminal. The ACE continually searches for a high-to-Iow
transition
from the idle state. When the transition is detected, a counter is cleared, and counts the 16x clock to 71/2, which
is the center of the start bit. The start bit is valid when the SIN is still low. Verifying the start bits prevents the
receiver from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character [LCRD, LCR1]. When parity is used LCR3 and the
polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indication in LSRD is set. The CPU reads the RBR,
which clears LSRD. If the character is not read prior to a new character transfer from the RSR to the RBR, the
OE status indication is set in LSR1. When there is a PE, the PE bit is set in LSR2. If a stop bit is not detected,
a FE indication is set in LSR3.
When the data into SIN is a symmetrical square wave, the center of the data cells occurs within ±3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16x clock cycle
prior to being detected.

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INSTRUMENTS
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2·181

TL16C552
DUAL ASVCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1 O2B - D!:CEMBER 1990 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
scratch pad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to temporarily hold data.

~TEXAS

INSTRUMENTS
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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

• IBM PC/ATTM Compatible
•
•
•
•

• Programmable Serial Interface
Characteristics for Each Channel:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity-Bit Generation
and Detection
- 1-,1 112-, or 2-Stop Bit Generation

Two TL 16C550 ACEs
Enhanced Bidirectional Printer Port
16-Byte FIFOs Reduce CPU Interrupts
Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation

• 3-State Outputs Provide TTL Drive for the
Data and Control Bus on Each Channel

• Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel

• Hardware and Software Compatible With
TL16C452

• Individual Modem Control Signals for Each
Channel
FNPACKAGE

1Ie
>-

(TOP VIEW)

I'"

a:
Cl Ie: " ~ - ~
>-00 IIa: ~
xozl~oo~looa:~~w~gOa:~~
a:Cl~a:ClOOI-~<~moo~wooa:
9

8 7

5 4 3 2

1 68 67 66 65 64 63 62 61

11
12
13
14
15

60
59

INTI
INT2

58
57
56

55
54

17
18
19

53
52
51

21
22
23
24
25

STS
GND
PDO
PDl
PD2
PD3
PD4
PD5
PD6
PD7
INTO

48
47
46

V~~~~~~M~~~~~~~~a

description
The TL 16C552A is an enhanced dual channel version of the popular TL 16C550B asynchronous
communications element (ACE). The device serves two serial input/output interfaces simultaneously in
microcomputer or microprocessor-based systems. Each channel performs serial-to-parallel conversion on data
characters received from peripheral devices or modems and parallel-to-serial conversion on data characters

IBM PC/AT is a trademark of International Business Machines COrporation.

~TEXAS

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2-183

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

description (continued)
transmitted by the CPU. The complete status of each channel of the dual ACE can be read at any time during
functional operation by the CPU. The information obtained includes the type and condition of the transfer
operations being performed and the error conditions.
In addition to its dual communications interface capabilities, the TL 16C552A provides the user with a
bidirectional parallel data port that fully supports the parallel Centronics-type printer interface. The parallel port
and the two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system
ports. A programmable baud rate generator is included that can divide the timing reference clock input by a
divisor between 1 and (2 16 -1).
The TL 16C552A is available in a 68-pin plastic leaded chip-carrier (FN) package.

functional block diagram
CTSO
DSRO
DCDO
RIO
SINO
CSO
DBO-DB7

r----

26
ACE
#1

30
41

14-21

lOR
RESET
ClK

DSR1 5

DCD1 8

10
ACE

SIN1 62

CS1 3

...... -

Select
and
Control
logic

37
39
4

SlCT
BUSY
PE
ACK
PEMD
CS2
ENIRQ

Parallel
Port

38
43

~TEXAS

2-184

53-46

DTRO
SOUTO
INTO
RXRDYO
TXRDYO

RTS1
DTR1
SOUT1
INT1
RXRDY1
TXRDY1

BDO

.......
ERR.

RTSO

RI1 6

lOW

9
22

CTS1 13

35-33

AO-A2

INSTRUMENTS
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58
59

PDO-PD7
INIT
AFD
STB
SLiN
INT2

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994- REVISED MARCH 1996

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

ACK

Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
ACK generates a printer port interrupt during its positive transition.

AFD

I/O

Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. AFD has an internal pullup resistor to
VDD of approximately 10 kQ.

35,34,33

Address. The address lines AO-A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.

BDO

Bus buffer. BDO is an active-high output that is asserted when either serial channel or the parallel
port is read. BDO controls the system bus driver (74lS245).

BUSY

Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.

AO, A1, A2

ClK

Clock. ClK is the external clock input to the baud rate divisor of each ACE.

32,3,38

Chip select. Each input acts as an enable for the write and read signals for serial channels 1 (CSO)
and 2 (CS1 ). CS2 enables the signals to the printer port.

CTSO, CTS1

28, 13

Clear to send. The logical state of each CTSx terminal is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTSx terminal, since the previous reading olthe associated modem status register,
causes the setting of ACTS (MSRO) of each modem status register.

DBO- DB7

14-21

1/0

Data bits DBO - DB7. The data bus provides eight 1/0 lines with 3-state outputs for the transfer of
data, control, and status information between the Tl16C552A and the CPU. These lines are
normally in the high-impedance state except during read operations. DBO is the least significant bit
(lSB) and is the first serial data bit to be received or transmitted.

DCDO, DCD1

29,8

Data carrier detect. DCDx is a modem input. Its condition can be tested by the CPU by reading
MSR7 (DCD) of the modem status registers. MSR3 (ADCD) of the modem status register indicates
whether the DCD input has changed since the previous reading of the modem status register. DCDx
has no affect on the receiver.

DSRO, DSR1

31,5

Data set ready. The logical state of the DSRx terminals is reflected in MSR5 of its associated
modem status register. ADSR (MSR1) indicates whether the associated DSRx terminal has
changed state since the previous reading of the modem status register.

DTRO, DTR1

25,11

Data terminal ready. Each DTRx output can be asserted low by setting MCRO, modem control
register bit of its associated ACE. DTRx is asserted high by clearing the DTR bit (MCRO) or
whenever a reset occurs. When active (low), DTRx indicates that its ACE is ready to receive data.

ENIRQ

Parallel port interrupt source mode selection. When ENIRQ is low, the AT mode of interrupts is
enabled. In AT mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
output is tied high, the PS-2 mode of interrupt is enabled and the INT2 output is internally tied to
the inverse of the PRINT bit in the printer status register. INT2 is latched high on the rising edge of
ACK. INT2 is held until the status register is read, which then resets the PRINT status bit and INT2.

ERR

Line printer error. ERR is an input line from the printer. The printer reports an error by holding ERR
low during the error condition.

GND

7,27,54

INIT

1/0

Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal
that allows the printer initialization routine to be started. INIT has an internal pullup resistor to VDD
of approximately 10 kQ.

45,60

External serial channel interrupt. Each serial channel interrupt 3-state output (enabled by bit 3 of
the MCR) goes active (high) when one of the following interrupts has an active (high) condition and
is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modern status. The interrupt is cleared on
appropriate service. Upon reset, the interrupt output is in the high-impedance state.

CSO, CS1, CS2

INTO,INT1

Ground (0 V). All terminals must be tied to GND for proper operation.

~TEXAS

INSTRUMENTS
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2-185

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994- REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NAME

NO.

110

DESCRIPTION

INT2

Printer port interrupt. INT2 is an active-high, 3-state output generated by the positive transition of
ACK. INT2 is enabled by bit 4 of the write control register. Upon reset, INT2 is in the high-impedance
state. Its mode is also controlled by ENIRQ.

lOR

InpuVoutput read strobe. lOR is an active-low input that enables the selected channel to output data
to the data bus (DBO-DB7). The data output depends on the register selected by the address inputs
AO, AI, A2, and chip select. Chip select (CSO) selects ACE #1, chip select 1 (CS1) selects ACE #2,
and chip select 2 (CS2) selects the printer port.

lOW

53-46

I/O

Line printer paper empty. PE is an input line from the printer that goes high when the printer runs out
of paper.

PEMD

Printer enhancement mode. When low, PEMD enables the write data register to the PDO- PD7 lines.
A high on this signal allows direction control of the PDO-PD7 port by the DlR bit in the control register.
PEMD is usually tied low for the printer operation.

RESET

Reset. When low, RESET forces the TL 16C552A into an idle mode in which all serial data activities
are suspended. The modem control register along with its associated outputs are cleared. The line
status register is cleared except for the THRE and TEMT bits, which are set. All functions of the device
remain in an idle state until programmed to resume serial data activities. RESET has a hysteresis level
of typically 400 mV.

24, 12

Request to send. The RTS outputs are set low by setting the MCRI of its UARTs modem control
register. Both RTS terminals are asserted high by RESET. A low on RTS indicates that its ACE has data
ready to transmit. In half duplex operations, RTS controls the direction of the line.

9,61

Receiver ready. Receiver direct memory access (DMA) signaling is also available through this output.
One of two types of DMA signaling can be selected using FCR3 when operating in the FIFO mode. Only
DMA mode is allowed when operating in the TL 16C450 mode. For signal transfer DMA (a transfer
is made between CPU bus cycles), mode is used. Multiple transfers that are made continuously until
the receiver FIFO has been emptied are supported by mode 1.

PDO-PD7
PE

RTSO,RTSI

RXRDYO,
RXRDYI

InpuVoutput write strobe. lOW is an active-low input causing data from the data bus to be input to either
ACE or to the parallel port. The destination depends on the register selected by the address inputs AO,
AI, A2, and chip selects CSO, CS1, and CS2.
Parallel data bits (0-7). PDO-PD7 provide a byte wide input or output port to the system.

Mode 0. RXRDY is active (low) when in the FIFO mode (FCRO = 1, FCR3 = 0) or when in the TL 16C450
mode (FCRO = 0) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the FIFO or holding register, RXRDY goes inactive (high).
Mode 1. RXRDY goes active (low) in the FIFO mode (FCRO = 1) when FCR3 = 1 and the time-out or
trigger levels have been reached. RXRDY goes inactive (high) when the FIFO or holding register is
empty.
RIO, Rll

30,6

Ring indicator. The RI signal is a modem control input. Its condition is tested by reading MSR6 (RI) of
each ACE. The modem status register output TERI (MSR2) indicates whether Rf has changed from
high to low since the previous reading of the modem status register.

SINO, SINI

41,62

Serial data. SINO and SINI move information from the communication line or modem to the
TL 16C552A receiver circuits. A mark (set) is high and a space (cleared) is low. Data on serial data
inputs is disabled when operating in the loop mode.

SLCT

Line printer select. SLCT is an input line from the line printer that goes high when the line printer is
selected.

SUN

I/O

Line printer select. SUN is an open-drain I/O that selects the printer when active (low). SUN has an
internal pullup resistor to VDD of approximately 10 kU

26, 10

Serial data outputs. These lines are the serial data outputs from the ACE transmitter circuitry. A mark
is a set bit (high) and a space is a cleared bit (low). Each SOUT is held in the mark condition when
the transmitter is disabled (RESET is asserted low) the transmitter register is empty, orwhen in the loop
mode.

I/O

Line printer strobe. STB is an open-drain line that provides communication between the TL 16C552A
and the printer. When STB is active (low), it provides the printer with a signal to latch the data currently
on the parallel port. STB has an internal pullup resistor to VDD of approximately 10 k£l.

SOUTO, SOUTI

STB

~TEXAS

INSTRUMENTS
2-186

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NO.

NAME

110

DESCRIPTION

TRI

3-state output control input. TRI controls the 3-state control of all I/O and output terminals. When TRI
is asserted, all I/O and outputs are in the high-impedance state allowing board level testers to drive the
outputs without overdriving internal buffers. This CMOS input is level sensitive and is pulled down with
an internal resistor that is approximately 5 k.Q.

TXRDYO
TXRDYI

22
42

Transmitter ready. Two types of DMA signaling are available. Either can be selected using FCR3 when
operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL 16C450 mode.
Single-transfer DMA (a transfer is made between CPU bus cycles) is supported by mode O. Multiple
transfers that are made continuously until the transmitter FIFO has been filled are supported by
mode 1.
ModeO. When inthe FIFO mode (FCRO= I, FCR3= 0) orintheTL 16C450 mode (FCRO=O) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDYx is active (low). Once
TXRDYx is activated (low), it goes inactive after the first character is loaded into the holding register
of the transmitter FIFO.
Mode 1. TXRDYx goes active (low) when in the FIFO mode (FCRO = 1) when FCR3 = 1 and there are
no characters in the transmitter FIFO. When the transmitter FIFO is completely full, TXRDYx goes
inactive (high).

23,40,64

VDD

Power supply. The VDD requirement is 5 V ±5%.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Voo (see Note 1) .. , .................... , ... ,.......... -0.5 V to Voo + 0.3 V
Input voltage range, VI .............. , ............................................... -0.5 V to 7 V
Output voltage range, Vo ................................................... -0.5 V to Voo + 0.3 V
Continuous total power dissipation at (or below) 70°C ...................................... 500 mW
Operating free-air temperature range, TA ........................................... -10°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to GND.

recommended operating conditions
Supply voltage, VDD
Clock high-level input voltage, VIHfCLK)
Clock low-level input voltage, VIL(CLK)
High-level input voltage, VIH
Low-level input voltage, VIL

MIN

NOM

MAX

UNIT

4.75

5.25

VDD

-0.5

0.8

VDD

-0.5

0.8

MHz

°C

Clock frequency, fclock
Operating free-air temperature, TA

-!!1

TEXAS
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2-187

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994 - REVISED MARCH 1996

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
TEST CONDITIONS

PARAMETER

VOH

High-level output voltage

VOL

low-level output vOltage

MIN

=-0.4 mA for DBO-DB7,
=-2 mA for PDO-PD7,
=-0.4 mA for INIT, AFD, STB, and SUN (see Note 2),
=-0.4 mA for ail other outputs
IOl =4 mA for DBO-DB7,
IOl =12 mA for PDO-PD7,
IOl =10 mA for INIT, AFD, STB, and SUN (see Note 2),
IOl =2 mA for ail other outputs
Ail other terminals are floating
VDD =5.25 V,
VI =0 to 5.25 V
Vo =0 with chip deselected, or
VDD =5.25 V,
Vo =5.25 V with chip and write mode selected
No loads on outputs,
VDD =5.25 V,
IOH
IOH
IOH
IOH

Input current

II(ClK)

Clock input current

IOZ

High-impedance output current

IDD

Supply current

UNIT

2.4

SINO, SIN1, DSRO, DSR1, DCDO, DCD1, CTSO, CTS1,
RIO and Ri1 at 2 V,
Other inputs at 0.8 V,
Baud rate 56 kbitls
Baud rate generator fClock 8 MHz,

MAX

0.4

±10

IlA

±10

I1A

±20

IlA

NOTE 2: These four terminals contain an internal puilup resistor to VDD of approximately 10 kO.

clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage
MIN

MAX

UNIT

tw1

PUlse duration, ClK l' (external clock) (see Figure 1)

tw2

Pulse duration, ClK.l- (external Clock) (see Figure 1)

tw3

PUlse duration, master reset (see Figure 18)

1000

read-cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN

MAX

UNIT

tw4

PUlse duration, lOR .).

tsu1

Setup time, CSx valid before lOR.). (see Note 3)

tsu2

Setup time, A2-AO valid before lOR.). (see Note 3)

th1

HOld time, A2-AO valid after lOR

th2

HOld time, chip CSx after lOR

td1

Delay time, tsu2 + tw4 + td2 (see Note 4)

td2

Delay time, lOR

NOTES:

t (see Note 3)
t (see Note 3)

l' to lOR.). or lOW .l-

175

3. The internal address strobe is always active.
4. In the FIFO mode, td1 = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification register
and line status register).

~TEXAS

INSTRUMENTS
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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN

MAX

UNIT

tW5

Pulse duration, lOW low

tsu4

Setup time, CSx valid before lOW .l- (see Note 3)

tsu5

Setup time, A2-AOvalid before lOW .l- (see Note 3)

tsu6

Setup time, DBO-DB7 valid before lOW

th3

Hold time, A2-AO valid after lOW

th4

Hold time, CSx valid after lOW

th5

Hold time, DBO-DB7 valid after lOW

td3

Delay time, tsu5 + tW5 + td4

td4

Delay time, lOW

(see Note 3)

t to lOW or lOR .l-

175

NOTE 3: The Internal address strobe IS always actIve.

read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, CL = 100 pF (see Note 5 and Figure 4)
MIN

PARAMETER
tpd1

Propagation delay time from lOR .l- to BDO

ten

Enable time from IOR.l- to DBO-DB7 valid

tdis

Disable time from lOR

t or from lOR t to BDO .l-

t to DBO-DB7 released

MAX

UNIT

NOTE 5: VOL and VOH (and the external loading) determine the charge and dIscharge tIme.

transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

See Figure 6

RCLK
cycles

See Note 6 and Figure 6

RCLK
cycles

See Note 6 and Figure 6

RCLK
cycles

td5

Delay time, interrupt THREt .l- to SOUT .l- at start

1d6

Delay time, SOUT .l- at start to interrupt THRE

td7

Delay time, lOW (WR THR)

td8

Delay time, SOUT .l- at start to TXRDY .l-

CL = 100 pF,
See Figures 7 and 8

tpd2

Propagation delay time from lOW (WR THR) .l- to interrupt THRE .l-

CL = 100 pF,
See Figure 6

140

tpd4

Propagation delay time from lOR (RD ItR)

CL = 100 pF,
See Figure 6

140

tpd5

Propagation delay time from lOW (WR THR)

CL = 100 pF,
See Figures 7 and 8

195

t to interrupt THRE t

t to interrupt THRE .lt to TXRDY t

t The acronym THRE IS for transmItter holdIng regIster empty.
NOTE 6: If the transmitter interrupt delay is active, this delay is lengthened by one character time minus the last stop bit time.

~TEXAS

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2-189

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SllSI76B- FEBRUARY 1994 - REVISED MARCH 1996

receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
PARAMETER

TEST CONDITIONS

td9

Delay time from stop to INT i

~d6

Propagation delay time from RClK i to sample ClK i

tpd7

Propagation delay time from lOR (RD RBR/RD lSR) 1, to reset interrupt 1,

tpd8

Propagation delay time from lOR (RD RBR) 1, to RXRDY

MIN

See Note 7

Cl:l00pF

MAX

UNIT

RClK
cycle

100

150

NOTE 7: The receiver data available indicator, the overrun error Indicator, the trigger level Interrupts, and the active RXRDY Indicator are delayed
three RClK cycles in the FIFO mode (FCRO: 1). After the first byte has been received, status indicators (PE, FE, BI) are delayed three
RClK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RClK
cycle delays for trigger change level interrupts.

modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 14)
PARAMETER

MIN

MAX

UNIT

100

170

Propagation delay time from lOR (RD MSR)

140

Propagation delay time from RI

170

to RTS (DTR) 1, i

tpd9

Propagation delay time from lOW (WR MCR)

tpdl0

Propagation delay time from modem input (CTS, DSR) 1,i to interrupt i

tpdl1
tpd12

i to interrupt 1,
i to interrupt i

parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figures 15,16, and 17)
MIN

MAX

UNIT

tsu7

Setup time, data valid before STB 1,

th6

Hold time, data valid after STB

tW6

Pulse duration, STB 1,

tdl0

Delay time, BUSY i to ACK 1,

Defined by printer

tdll

Delay time, BUSY 1, to ACK 1,

Defined by printer

tw7

Pulse duration, BUSY i

Defined by printer

tW8

Pulse duration, ACK 1,

td12

Delay time, BUSY i after STB

1c113

Delay time, INT2 1, after ACK 1, (see Note 8)

td14

Delay time, INT2 i after ACK

td15

Delay time,

td16

Delay time,

/lS

/ls

Defined by printer

i (see Note 8)
INT2 i after ACK i (see Note 8)
INT2 1, after lOR i (see Note 8)

NOTE 8: tdl3-tdl6 are all measured with a 15-pF load.

~TEXAS

INSTRUMENTS
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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

I-.L
I

CLK(XTAL1)

twl

r-\. 2V

0.8 V \ - J

'\!:,8 V

tw2~

fclock = 16 MHz MAX

Figure 1. Clock Input (ClK) Voltage Waveform

2.54 V
Device Under Test

680n

82pF
(see Note A)

NOTE A. Includes scope and jig capacitance.

Figure 2. Output load Circuit
TL16C552A

Data Bus

Address Bus

-------/

Control Bus

Dual
ACE and
Printer
Port

Option
Jumpers

Serial
Channell
Buffers

g-Pin D Connector

Serial
Channel 2
Buffers

g-Pin D Connector

Parallel
Port

RIC

25-Pin D Connector

Network

Figure 3. Basic Test Configuration

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2-191

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
A2,A1,AO --VSO%

Valid

----10

50%)(

I~-------------

~~~

____~I

i \,50%

CSO, CS1, CS2

Valid

1 1

1 I~

tsu1 ---+l~1

1<1

1"- th2 ~
td1--+I---------+

tsu2

----------------~i
lOR

50%t

Ir--------~T--~

50%

} ....
SO_o/c_O_A_ct_i_ve_S_O..J%1

~ tw4 ---'i"'~---- td2
1
1

tpd1

1
1

BOO _ _ _ _ _ _ _ _ _ _ _..,ir-_s_O...J%f
ten

DBO-DB7

tpd1

\ . 50%

-I
.I~·

tdis

~
/)--- - - - - - - - - -

---------------iC\.V _validData

Figure 4. Read Cycle Timing Waveforms

A2, A1, AO

~I__________________________
50%
Valid
1

i \ , 50%
1

_____________

) ( 50%

~~~

_____~I
CSO, CS1, CS2

--JI~

Valid

50%

1 I~
tsu4
.1
l..- t h4-1
1...
~-------~I~---td3--+I---------+
1
I
I
I~

tsus---+·I

'\,50% Active

50%

I",~___

1<1--- tW5 ---'1
tsu6

Valid Data

1<1

~TEXAS

INSTRUMENTS
POST OFFICE BOX655303 • DALLAS, TEXAS 75265

)

Figure 5. Write Cycle Timing Waveforms

2-192

...4

DBO-DB7 _ _ _ _ _ _ _ _ _ _ _ _ _ _---(

,....._ _ _ _ _ _ _ __

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
Serial Out
(SOUT)

50%

Data Bits 5-8
I '--_______
..J

td5~

Interrupt
(THRE)

Parity

---~l50% - ' 50%
I
!L.:..I1
tpd2

~50%

~I
I
I- td7-'1

50%L

14- tpd2 ~

50%~~-------------tp-d-4-~--Ir---

lOW
(WR THR) 50%"'--1' 50%

lOR
(RDIIR)

I~_-

50 %

Figure 6. Transmitter Timing Waveforms
lOW ~
(WR THR)

Byte #1

((

...J{

\ '...._ _

50%

-'x

SOUT _ _ _ _ _
Da_ta_"""""l_ _

tpd5 -I~~------.~
TXRDV ________________

Parity

Stop 50%t..._ _S_ta_rt____

td8

-I

-...J)tr~-0-%-------------5-0~%~'___________

Figure 7. Transmitter Ready Mode 0 Timing Waveforms
((

lOW
(WRTHR)

50%
1 Start of

"-----' I

SOUT

Data
tpd5

Parity

Stop

Start

-I~I~------.~I

TXRDY ________________

-+J ~

td8

-...J)tr5-0-%-----FI-F-O-F-UI-I----~\'\~--5O-o/c~.~'__ ___

Figure 8. Transmitter Ready Mode 1 Timing Waveforms

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2-193

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

RClK

-----.;~:
ClK
Tl16C450 Mode
(receiver

in~~ ~

Interrupt
(data ready or
RCVRERR)

tpd6

--------------~~

data)
Sample
ClK

J.--

Start

~
n n

Data Bits 5-8

-lL.....JL...Jl....ifr-J1

td9~

l+,

~\I---

I ~----'I'~
"no,"
) ~
50%

------------------' i+-50%

t pd7 -----,

Active / ' " - - -

Figure 9. Receiver Timing Waveforms

SIN
Sample
ClK
Trigger
Interrupt
(FCR6, 7=0, 0)

~Data Bits 5-8

JJLL

~I-~L-~~-~~--~~-.~--I~---

I
I ~'!-\-------""""II:~---

---------------t-l
If 50%
td9
"' I
-6i

50%
~

tpd7

lOR
(RORBR)

""I

50%~

:
}'-....5-0.-Yo--50-%""\

lSI
Interrupt - - - - - - - - - - - - - - - - - - - - - - - '
lOR
(RO lSR)

I~-----------

l-tpd7~

-----------------~ A~ive /~--------50%~

Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms

~TEXAS

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(FIFO at or above
trigger level)
(FIFO below
trigger level)

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

>CY::\J

SIN _ _ _.....

Time Out or
Trigger level
Interrupt

50'Y1\. . ____
~tpd7
----,

(FIFO at or above
trigger level)
(FIFO below
trigger level)

50%/

lSI
\
Interrupt _ _ _ _ _ ,

~
1\ 500/.

Top Byte of FIFO

...l-"----...I+-----"]----t-'--I-----td9 ~
tpd7 I"
~I
1

lOR
(RDlSR)

------~I-~
1

Active

----50
1I~---~I
%

1
(RD

R~~

Active

50'Y\.

50%

Active

Previous Byte
Read From FIFO

Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
((
)}

lOR
(RD RBR)

Active

50%\

SIN
(first byte)

Ys:\

(see Note A)

1
1

Sample
elK

RXRDY

td9
I"
(see Note B)

1
1

\50%

,rjJ

tpd8

Figure 12. Receiver Ready Mode 0 Waveforms
NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCRO 1, td9 3 RCLK cycles. For a time-out interrupt, td9

=8 RCLK cycles.

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2-195

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
lOR
(RD RBR)
SIN
(first byte that reaches
the trigger level)

--------------------~~~\------------~
50% \

____

-J~~

Active

(see Note A)
_____

Sample
ClK
td9
(see Note B)

I• • 1
1

- - - - - " ' \ \...
50_0/._0____-'1'/1-)_ _ _ _ _ _ _ _

~..J;(50%

tpd8

NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCRO-l, td9 = 3 RClK cycles. For a trigger change level interrupt, 1d9 = 8 RClK.

Figure 13. Receiver Ready Mode 1 Waveforms

IOW~
.
\.~___5_0..J0/1f

(WR MCR)

50%11

'----..Jf.

~tpd9

~tpd9
RTS,DTR - - - - - - - -.....\

500/1,..----------

50%

5_0.J%{

'}\",5_00_VO_ _ _ _ _ _ _ _ _ _ ___

CTS, DSR, DCD _____

tpdl0 ~
INTO,INT1,
l1NT,21NT

tpdl0

~50% 50%}r,..----~~\",____5_00..JVO~

_ _ _ _ _ _ _5_00
-JVO}l

tpdll ~

M~~
-

(RD

------..

tpd12 -11~.--~.1

'\..J

50%

~
Figure 14. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
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50%',..-----

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

DATA

tsu7

5_00_YO_ _

Valid

I-+- th6

--50-o/c~o~

Jt~5-0o/c-o---------------

~
~I

tw6

50%~50%

td10

tW8

l--+td11

BUSY

50_o/c~o~~I~~~ 50% ~,-5_0_%_ _ _ _ _ _ __

______

td12

~tw7-1

Figure 15. Parallel Port Timing Waveforms
ENIRQ

, , ' - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____

50% } ...._ _..,{ 50%
td13

--+1

- I 1-

INT2
line Printer
Status Register,
Bit 2 (PRINT)

td14

)l50%

-----5-00~~~

50%,f

----+I
1

~ td(intl

(see Note A)

"----'50%

NOTE A. A timing value is not provided for td(int) in the tables since the line printer status register, bit 2 (PRINT) is an internal signal.

Figure 16. Parallel Port AT Mode Timing (EN IRQ = Low) Waveforms

~TEXAS

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ENIRQ

\,-_-,/50%
td15 --..:

-----.J

INT2

________--11

-+1"'"" I

1....-_ _ _

50%

td16

\.50%

\ .......-----1-11II
1

~50%
Figure 17. Parallel Port PS/2 Mode Timing (EN IRQ = High) Waveforms

RESET

50%

t.......i
I~
1

50%

tw3

Figure 18. RESET Voltage Waveform

~TEXAS

INSTRUMENTS
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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLlS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data. Mnemonic
abbreviations for the internal registers are shown in Table 1.
Table 1. Internal Register Types With Mnemonics
CONTROL

MNEMONIC

STATUS

MNEMONIC

DATA

MNEMONIC

Line control register

LCR

Line status register

LSR

Receiver buffer register

RBR

FIFO control register

FCR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MCR

Divisor latch LSB

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register (bit 7)
to select the register to be written or read (see Table 2). Individual bits within the registers are referred to by the register
mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
The transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of data.
If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first serial
data bit received and transmitted. The ACE data registers are double buffered (TL 16C450 mode) or FIFO buffered
(FIFO mode) so that read and write operations can be performed when the ACE is performing the parallel-to-serial
or serial-to-parallel conversion.
Table 2. Register Selectlont
DLAB

MNEMONIC

RBR

Receiver buffer register (read only)

THR

Transmitter holding register (write only)

IER

Interrupt enable register

X
X
X

IIR

Interrupt identification register (read only)

FCR

FIFO control register (write only)

LCR

Line control register

X
X

MCR

Modem control register

LSR

Line status register

MSR

Modem status register

SeR

Scratch pad register

DLL

LSB divisor latch

DLM

MSB divisor latch

The senal channel IS accessed when either CSO or CS1 IS low.
X = irrelevant, L = low level, H = high level

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS1?6B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.

Table 3. Summary of Accessible Registers
ADDRESS

BIT 6

BIT5

BIT 4

BIT 3

BIT2

BITI

BIT 0

RBR
(read only)

Data
Bit?
(MSB)

Data
Bit 6

Data
Bit 5

Data
Bit 4

Data
BitS

Data
Bit 2

Data
Bitt

Data
Bit 0
(LSB)

THR
(write only)

Data
Bit?

Data
Bit 6

Data
Bit 5

Data
Bit4

Data
BitS

Data
Bit 2

Data
Bitt

Data
BitO

DLL

Bit?

Bit 6

Bit 5

Bit 4

BitS

Bit 2

Bit 1

Bit 0

DLM

Bit 15

Bit14

Bit IS

Bit12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
modem
status
interrupt

(ERLSI)
Enable
receiver
line
status
interrupt

(ETBEI)
Enable
transmitter
holding

(ERBFI)
Enable

DMA
mode
select

Transmitter
FIFO

Receiver

reset

FeR
(write only)

Receiver

Receiver
Trigger
(LSB)

Reserved

Trigger
(MSB)

Reserved

empty
interrupt
FIFO

received
data
available
interrupt
FIFO
Enable

IIR
(read only)

FIFOs
Enablecfl:

FIFOs
Enabledt

Interrupt 10
Bit3t

Interrupt ID
Bit 2

Interrupt 10
Bitt

o If
interrupt
pending

LCR

(DLAB)
Divisor latch

Set
break

Stick
parity

(EPS)
Even parity
select

(PEN)
Parity
enable

(STB)
Number of
stop bits

(WLSB1)
Word length
select bit 1

(WLSBO)
Word length
select bit 0

Loop

OUT2
Enable
external
interrupt
(INTO or INTI)

OUTI
(an unused
internal
signal)

(RTS)
Request
to send

(DTR)
Data
terminal
ready

Error in

(TEMT)
Transmitter
empty

(THRE)

receiver
FIFOt

Transmitter

(BI)
Break
interrupt

(FE)
Framing
error

(PE)
Parity

(OE)
Overrun

error

(DR)
Data
ready

access bit
4

MCR

LSR

holding
register
empty

MSR

(DCD)
Data carrier
detect

(RI)
Ring
indicator

(DSR)
Dataset
ready

(CTS)
Clear
to send

("'DCD)
Delta
data carrier
detect

(TERI)
Trailing
edge ring
indicator

("'DSR)
Delta
data set
ready

("'CTS)
Delta
clear
to send

SCR

Bit?

Bit6

Bit 5

Bit4

Bit3

Bit 2

Bit 1

Bit 0

tDLAB = 1

:I: These bits are always 0 when FIFOs are disabled.

~ThXAS

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

Bit 0: FCRO enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be cleared by
resetting FCRO. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL 16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCRO.

•

Bit 1: FCR1 = 1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the shift
register.

•

Bit 2: FCR2 = 1 clears all bytes in the transmitter FIFO and resets the counter. This does not clear the shift
register.

•

Bit 3: FCR3 = 1 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 if FCRO = 1.

•

Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

•

Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt as shown in Table 4.

Table.4. Trigger Level For the Receiver FIFO Interrupt
7

BIT

RECEIVER FIFO
TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1.

LSRO is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is cleared.

IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt
IIR=04.

Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. When the FIFO drops below its programmed trigger level, it is cleared.

IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.

~TEXAS

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO

SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1.

A FIFO timeout interrupt occurs when the following conditions exist:
a.

Minimum of one character in FIFO

Last received serial character is longer than four continuous previous character times ago (if two stop
bits are programmed, the second one is included in the time delay)

The last CPU read of the FIFO is more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.

By using the RCLK input for a clock Signal, the character times can be calculated. The delay is proportional
to the baud rate.

The time-out timer is reset after the CPU reads the receiver FI FO or after a new character is received when
there has been no time-out interrupt.

A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.

Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCRO 1, IER 1).

When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR 02) occurs. The
interrupt is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen
characters can be written to the transmitter FIFO when servicing this interrupt.

The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time when
the following occurs:
THRE = 1 and there is not a minimum of two bytes at the same time in transmitter FIFO since the last
THRE 1. The first transmitter interrupt after changing FCRO is immediate assuming it is enabled.

Receiver FIFO trigger level and character time-out interrupts have the same priority as the received
data available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter
FIFO empty interrupt.

FIFO polled mode operation

Clearing IERO, IER1, IER2, IER3, or all with FCRO 1 puts the ACE into the FIFO polled mode. receiver and
transmitter are controlled separately. Either one or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
ACE status.

interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTO or
INT1) output. All interrupts are disabled by clearing IERO - IER3 of the lEA. Interrupts are enabled by setting
the appropriate bits of the lEA. Disabling the interrupt system inhibits the IIR and the active (high) interrupt
output. All other system functions operate in their normal manner, including the setting of the LSR and MSR.
The contents of the IER shown in Table 3 are described in the following bulleted list.
•

Bit 0: When set, IERO enables the received data available interrupt and the time-out interrupts in the FIFO
mode.

~TEXAS

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
•

Bit 1: When set, IER1 enables the transmitter holding register empty interrupt.

•

Bit 2: When set, IER2 enables the receiver line status interrupt.

•

Bit 3: When set, IER3 enables the modem status interrupt.

•

Bits 4 - 7: IER4 - IER7 are always cleared.

interrupt identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are as follows:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER

INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL

INTERRUPT RESET
CONTROL

BIT 3

BIT 2

BIT 1

First

Second

Received data available . Receiver data available or trigger level
reached

RBR read until FIFO
drops below the
trigger level

Second

Character time-out
indicator

No characters have been removed
from or input to the receiver FIFO
during the last four character times and
there is at least one character in it
during this time.

RBR read

Third

THRE

IIR read if THRE is
the interrupt source
orTHRwrite

Fourth

Modem status

CTS, DSR, RI, or DCD

MSR read

BIT 0

INTERRUPT TYPE

INTERRUPT SOURCE

None

Receiver line status

OE, PE, FE, or BI

LSR read

•

Bit 0: IIRO indicates whether an interrupt is pending. When IIRO is cleared, an interrupt is pending.

•

Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

•

Bit 3: IIR is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.

•

Bits 4 and 5: IIR4 and IIR5 are always cleared.

•

Bits 6 and 7: IIR6 and IIR7 are set when FCRO

=1.

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR)
The format of the data character is controlled by the LCR. The LCR can be read. Its contents are described in
the following bulleted list and shown in Figure 19.
•

Bits 0 and 1: LCRO and LCR1 are the word length select bits. The number of bits in each serial character
is programmed as shown.

•

Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.

•

Bit 3: LCR3 is the parity enable bit. When LCR3 is high, a parity bit between the last data word bit and stop
bit is generated and checked.

•

Bit 4: LCR4 is the even parity select bit. When set, LCR4 enables even parity.

•

Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 = 1) and LCR5 = 1, this bit causes the
transmission and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity
to a known state and allows the receiver to check the parity bit in a known state.

•

Bit 6: LCR6 is the break control bit. When this bit is set, the serial output (SOUT1/S0UTO) is forced to the
spacing state (low). The break control bit acts only on the serial output and does not affect the transmitter
logic. When the following sequence IS used, no invalid characters are transmitted because of the break:
Step 1: Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.
Step 2: Set the break in response to the next THRE status indicator.
Step 3: Wait forthe transmitter to be idle when transmitter empty status signal is set high (TEMT =1); then
clear the break when the normal transmission has to be restored.

•

Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. Bit 7 must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register, or the interrupt enable register.

~1ExAs'

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TL16C552A
DUAL ASYNCHIjIONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Line Control Register

IL~RIL~RIL~RIL~RIL~RIL~RIL~RIL~RI

T.-

o 0 =5 Data Bits

Word Length
Select
Stop Bit
Select

Parity Enable

Even Parity
Select

o 1 =6 Data Bits

1 0
1 1

=7 Data Bits

=8 Data Bits

o =1 Stop Bits
1

=1.5 Stop Bits

If 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected

o= Parity Disabled
1

=Parity Enabled

o =Odd Parity
1

=Even Parity

Stick Parity

o= Stick Parity Disabled

Break Control

o=Break Disabled

Divisor Latch
Access Bit

1 = Stick parity Enabled

=Break Enabled

o= Access Receiver Buffer
1

=Access Divisor Latches

Figure 19. Line Control Register Contents

line printer port
The line printer port contains the functionality of the port included in the TL16C452 but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PEMD) terminal. This
enhancement is the addition of a direction control bit and an interrupt status bit.

register 0 line printer data register (LPT)
The LPT port is either output only or bidirectional depending on the state of the extended mode terminal and
data direction control bits.
Compatibility mode (PEMD =L)
Reads to the LPT data register return the last data that was written to the port. Write operations immediately
output data to PDO-PD7.
Extended mode (PEMD =H)
Read operations return either the data last written to the LPT data register if the direction bit is set to write
(low) or the data that is present on PDO- PD7 if the direction is set to read (high). Write operations to the LPT
data register latch data into the output register; however, they only drive the LPT port when the direction bit is
set to write (lOW).

~I
~ TEXAS

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2·205

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

line printer port (continued)
The Table 6 summarizes the configuration of the PD port based on the combinations of logic level on the
PEMO terminal and value of the direction control bit (OIR).

Table 6. Extended Mode and Direction Control Bit Combinations
PEMD

DIR

PDO-PD7 FUNCTION

PC/AT mode - output

H
H

0
1

PS/2 mode - output
PS/2 mode - input

register 1 read line printer status register (LPS)
The LPS register is a read-only register that contains interrupt and printer status of the LPT connector terminals.
In Table 7 (in the default column) are the values of each bit after reset in the case of the printer being
disconnected from the port.

Table 7. LPS Register Bit Description

BIT

DESCRIPTION

DEFAULT

Reserved

ERR

SLCT

t
t
t
t
t

ACK

BSY

Outputs are dependent upon device inputs.

•

Bits 0 and 1: These bits are reserved and are always set.

•

Bit 2: PRINT is the printer interrupt status bit. When cleared, this bit indicates that the printer has
acknowledged the previous transfer with an ACK handshake (if bit 4 of the control register is set). The bit
is cleared on the active to inactive transition of the ACK signal. This bit is set after a read of the status port.

•

Bit 3: ERR is the error status bit that corresponds to ERR terminal input.

•

Bit 4: SLCT is the select status bit that corresponds to SLCT terminal input.

•

Bit 5: PE is the paper empty status bit that corresponds to the PE terminal input.

•

Bit 6: ACK is the acknowledge status bit that corresponds to ACK terminal input.

•

Bit 7: BSY (active low) is the busy status bit that corresponds to BUSY terminal input (active high).

~1EXAs

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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

line printer port (continued)
register 2 line printer control register (LPC)
The LPC register is a read/write port that controls the PDO-PD7 direction and drive the printer control lines.
Write operations set or clear these bits, while read operations return the state of the last write operation to this
register. The bits in this register are defined in Table 8 and described in the following bulleted list.
Table 8. LPC Register Bit Description
BIT

DESCRIPTION

STB

AFD

INIT

SUN

INT2 EN

DIR

Reserved 0

•

Bit 0: STB is the printer strobe control bit. When STB is set, the STB terminal is asserted on the LPT
interface. When STB is cleared, the signal is negated.

•

Bit 1: AFD is the auto feed control bit. When AFD is set, the AFD terminal is asserted on the LPT interface.
When AFD is cleared, the signal is negated.

•

Bit 2: INIT is the initialize printer control bit. When INIT is set, the INIT terminal is negated. When INIT is
cleared, the INIT terminal is asserted.

•

Bit 3: SUN is the select input control bit. When SUN is set, the SUN signal is asserted on the LPT interface.
When SUN is cleared, the signal is negated.

•

Bit 4: INT2 EN is the interrupt request enable control bit. When INT2 EN is set, interrupts from the LPT port
are enabled. When INT2 EN is cleared, interrupts are disabled and the INT2 terminal is placed in the
high-impedance state.

•

Bit 5: DIR is the direction control bit (only used when PEMD is high). When DIR is set, the output buffers
in the PO port are disabled allowing data driven from external sources to be read from the PO port. When
DIR is cleared, the PO port is in the output mode.

•

Bits 6 and 7: These bits are reserved and always cleared.

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DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

line status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 9 is described in the
following bulleted list.

Table 9. Line Status Register Bits
1

Ready

Not ready

LSR1 overrun error (OE)

Error

No error

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

LSR BITS
LSRO data ready (DR)

LSR5 transmitter holding register empty (THRE)

Empty

Not empty

LSR6 transmitter empty (TEMT)

Empty

Not empty

Error in FIFO

No error in FIFO

LSR7 receiver FIFO error

•

Bit 0: LSRO is the data ready (DR) bit. Data ready is set when an incoming character is received and
transferred into the receiver buffer register or the FIFO. LSRO is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.

•

Bit 1: LSR1 is the overrun error (OE) bit. Overrun error indicates that data in the receiver buffer register
is not read by the CPU before the next character is transferred into the receiver buffer register overwriting
the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An
overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.
The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift
register is not transferred to the FIFO, but it is overwritten.

•

Bit 2: LSR2 is the parity error (PE) bit. Parity error indicates that the received data character does not have
the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is
cleared when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with
a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

•

Bit 3: LSR3 is the framing error (FE) bit. Framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.

•

Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the received data input is held in the
spacing (low) state for longer than a full-word transmission time (start bit + data bits + parity + stop bits).
The BI indicator is cleared when the CPU reads the contents ofthe LSR.ln the FIFO mode, this is associated
with a particular character in the FIFO. LSR4 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.

LSR1 - LSR4 are the error conditions that produce a receiver line status interrupt [priority 1 interrupt in the
interrupt identification register (IIR)] when any of the conditions are detected. This interrupt is enabled by setting
IER2 in the interrupt enable register.

~TEXAS

INSTRUMENTS
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TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B- FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (LSR) (continued)
•

Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register into the transmitter shift register. LSR5 is cleared by the loading of the
transmitter holding register by the CPU. LSR5 is not cleared by a CPU read of the LSR. In the FIFO mode
when the transmitter FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter
FIFO. When the THRE interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. When
THRE is the interrupt source indicated in IIR, INTRPT is cleared by a read of the IIR.

•

Bit 6: LSR6 is the transmitter empty (TEMT) bit. TEMT is set when the transmitter holding register (THR)
and the transmitter shift register (TSR) are both empty. LSR6 is cleared when a character is loaded into the
THR and remains low until the character is transferred out of SOUTo TEMT is not cleared by a CPU read
of the LSR. In the FIFO mode, when both the transmitter FIFO and shift register are empty, this bit is set.

•

Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in the TL 16C450 mode. In FIFO
mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing error, or
break interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors in the
FIFO.
NOTE
The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.

master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
1. It initializes the transmitter and receiver clock counters.
2.

It clears the LSR except for transmitter shift register empty (TEMT) and transmit holding register empty
(THRE), which are set. The MCR is also cleared. All of the discrete lines, memory elements, and
miscellaneous logic associated with these register bits are also cleared or turned off. The LCR, divisor
latches, receiver buffer register, and transmitter buffer register are not effected.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-209

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
master reset (continued)
Table 10. RESET Affects on Registers a,nd Signals
RESET CONTROL

RESET

Interrupt enable register

REGISTERISIGNAL

Reset

All bits low (0-3 forced and 4-7 permanent)

Interrupt identification register

Reset

Bit 0 is high, bits 1, 2, 3, 6, and 7 are low, and
bits 4-5 are permanently low.

Line control register

Reset

All bits low

Modem control register

Reset

All bits low (5-7 permanent)

FIFO control register

Reset

All bits low

Line status register

Reset

All bits are low, except bits 5 and 6 are high.

Modem status register

Reset

Bits 0-3 low, bits 4-7 input signal

SOUT

Reset

High

Interrupt (receiver errs)

Read LSR/Reset

Low

Interrupt (receiver data ready)

Read RBR/Reset

Low

Read IIRlWrite THRlReset

Low

Interrupt (THRE)
Interrupt (modem status changes)

Read MSRlReset

Low

Reset

High

OUT2
RTS

Reset

High

DTR

Reset

High

OUT1

Reset

High

modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written and
read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. The MCR bits are shown in the following bulleted list.
•

Bit 0: When MCRO is set, the DTR output is forced low. When MCRO is cleared, the DTR output is forced
high. The DTR output of the serial channel may be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.

•

Bit 2: MCR2 has no affect on operation.

•

Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.

•

Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
SOUT is asserted to the marking (high) state and SIN is disconnected. The output of the transmitter shift
register is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD,
and RI) are disconnected. The modem control outputs (DTR, RTS, OUT1, and OUT2) are internally
connected to the four modem control inputs. The modem control output terminals are forced to their inactive
(high) state on the TL 16C552A. In the diagnostic mode, data transmitted is immediately received. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, interrupts are generated by contrOlling the lower four MCR bits
internally. Interrupts are not generated by activity on the external terminals represented by those four bits.

~TEXAS

INSTRUMENTS
2-210

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
•

Bits 5 - 7: MCR5 - MCR7 are permanently cleared.
Modem Control Register

Data Terminal
Ready

0"; DTR Output High (inactive)
1 = DTR Output Low (active)

Request
to Send

0= RTS Output High (inactive)
1 RTS Output Low (active)

Out 1
(internal)

No Effect on External Operation

Out 2
(internal)

o = External Interrupt Disabled

Loop

1 = External Interrupt Enabled

o = Loop Disabled
1 = Loop Enabled

Bits Are Cleared

Figure 20. Modem Control Register Contents

modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
ACE in addition to the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set when a control input from the modem
changes state and is cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4- MSR7 are status indicators ofthese lines. A status
bit =1 indicates the input is low. A status bit =0 indicates that the input is high. When the modem status interrupt
in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSRO - MSR3 is set. The
MSR is a priority 4 interrupt. The contents of the MSR are described in Table 11 and the following bulleted list.

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-211

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Table 11. Modem Status Register Bits
MSRBIT

MNEMONIC

MSRO

aCTS

DESCRIPTION

MSR1

aDSR

Delta data set ready

MSR2

TERI

Trailing edge of ring indicator

MSR3

aDCD

MSR4

CTS

MSR5

DSR

Data set ready

MSR6

Ring indicator

MSR7

DCD

Delta clear to send

Delta data carrier detect
Clear to send

Data carrier detect

•

Bit 0: MSRO is the delta clear-to-send (dCTS) bit. dCTS displays that the CTS input to the serial channel
has changed states since it was last read by the CPU.

•

Bit 1: MSR1 is the delta data set ready (dDSR) bit. dDSR indicates thatthe DSR inputto the serial channel
has changed states since the last time it was read by the CPU.

•

Bit 3: MSR3, delta data carrier detect (dDCD) bit. d DCD indicates that the DCD input to the serial channel
has changed states since the last time it was read by the CPU.

•

Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUTo When the serial channel
is in the loop mode (MCR4 = 1), MSR4 reflects the value of RTS in the MCR.

•

Bit 5: MSR5, data set ready (DSR) bit. DSR is the complement of the DSR input from the modem to the
serial channel that indicates that the modem is ready to provide received data to the serial channel receiver
circuitry. When the channel is in the loOp mode (MCR4 = 1), MSR5 reflects the value of DTR in the MCR.

•

Bit 6: MSR6,ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in the loop
mode (MCR4= 1), MSR6 reflects the value of OUT1 in the MCR.
.

•

Bit 7: MSR7, data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier detect
(DCD) input. When the channel is in the loop mode (MCR4 = 1), MSR7 reflects the value of OUT2 in the
MCR.

Reading the MSR clears the delta modem status indicators but has no affect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read lOR operation, the status bit is not set until the trailing edge of the read. If a status bit
is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing edge
of the read instead of being set again. In the loop back mode, when modem status interrupts are enabled, the
CTS, DSR, RI and DCD input terminals are ignored; however, a modem status interrupt can still be generated
by writing to MCR3-MCRO. Applications software should not write to the MSR.

~ThxAs

INSTRUMENTS
2·212

POST OFFICE BOX 655303 • DALLAS, TEXAS:75265

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

parallel port registers
The TL 16C552A parallel port can connect the device to a Centronics-style printer interface. When chip select 2
(CS2) is low, the parallel port is selected. Table 13 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (lOR) and write (lOW) terminals as
shown. The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the six most significant
bits. The status bits are printer busy (BSY), acknowledge (ACK) (a handshake function), paper empty (PE),
printer selected (SLCT), error (ERR) and printer interrupt (PRINT). The read control register allows the state
of the control lines to be read. The write control register sets the state of the control lines. They are direction
(DIR), interrupt enable (INT2 EN), select in (SUN), initialize the printer (INIT), autofeed the paper (AFD), and
strobe (STB), which informs the printer of the presence of a valid byte on the parallel bus. The write data register
allows the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the
parallel port implementation used in the IBM serial parallel adaptor.

Table 12. Parallel Port Registers
REGISTER

BIT6

BITS

BIT4

BIT 3

BIT 2

BIT 1

BIT 0

Read data

PD7

PD6

PD5

PD4

PD3

PD2

POI

PD~

Read status

BSY

ACK

SLCT

ERR

Read control

PEMD·DIR

INT2 EN

SLiN

INIT

AFD

STB

PD7

PD6

PD5

PD4

PD3

PD2

POI

PD~

DIR

INT2 EN

SLiN

INIT

AFD

STB

Write data
Write control

Table 13. Parallel Port Register Select
CONTROL TERMINALS
CS2

lOR

lOW

Read data

Read status

Read control

Invalid
Write data

Invalid

Write control

Invalid

programmable baud generator
The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (de to
8 MHz) by any divisor from 1 to (2 1L 1). The outputfrequency ofthe baud generator is 16xthe data rate [divisor
# = clock + (baud rate x 16)] referred to in this document as RCLK. Two 8-bit divisor latch registers store the
divisor in a 16-bit binary format. These divisor latch registers must be,Joaded during initialization. Upon loading
either of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial
load. The BRG can use any of three different popular frequencies to provide standard baud rates. These
frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 to 512
kbps are available. Tables 14, 15, 16, and 17 illustrate the divisors needed to obtain standard rates using these
three frequencies.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·213

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 14. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

0.026
0.058

0.690

2.860

Table 15. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

~TEXAS

2-214

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

0.026
0.034

0.312

0.628

1.230

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 16. Baud Rates Using a 8-MHz Clock
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

10000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1

0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080

0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400

Table 17. Baud Rates Using a 16-MHz Clock
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000000

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

20000
13334
9090
7434
6666
3334
1666
834
554
500
416
278
208
138
104
52
26
18
8
4
2
1

0.00
0.00
0.01
0.01
0.01
-0.02
0.04
-0.08
0.28
0.00
0.16
~0.08

0.16
0.64
0.16
0.16
0.16
-0.79
-2.34
-2.34
-2.34
0.00

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-215

TL16C552A
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS176B - FEBRUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.

receiver
Serial asynchronous data is input into SIN. The ACE continually searches for a high-to-Iow transition
from the idle state. When the transition is detected, a counter is reset and counts the 16x clock to 71/2, which
is the center of the start bit. The start bit is valid if SIN is still low. Verifying the start bits prevents the receiver
from assembling a false data character due to a low going noise spike on the SIN input.
The LCR determines the number of data bits in a character (LCRO and LCR1). When parity is used, LCR3 and
the polarity of parity LCR4 is needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indicator in LSRO is set high. The CPU reads the
receiver buffer register, which clears LSRO. If the character is not read prior to a new character transfer from
the RSR to the RBR, the overrun error status indicator is set in LSR1. If there is a parity error, the parity error
is set in LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
If the data into SIN is a symmetrical square wave, the center of the data cells occurs within ±3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16x clock cycle
prior to being detected.

scratch pad register
The scratchpad register is an 8-bit read/write register that has no affect on either channel in the ACE. It is
intended to be used by the programmer to hold data temporarily.

~TEXAS

2-216

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
• Programmable Serial Interface
Characteristics for Each Channel:
- 5-,6-,7-, or 8-Bit Characters
Even, Odd, or No Parity Bit Generation
and Detection
1-,1-1/2-, or 2-Stop Bit Generation

• IBM PC/ApM Compatible
• Two TL 16C550 ACEs
• Enhanced Bidirectional Printer Port
• 16-Byte FIFOs Reduce CPU Interrupts
• Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation

• 3-State Outputs Provide TTL Drive for the
Data and Control Bus on Each Channel

• Transmit, Receive, Line Status, and Data
Set Interrupts on Each Channel
Independently Controlled

• Hardware and Software Compatible With
TL16C452

• Individual Modem Control Signals for Each
Channel
FN PACKAGE
(TOP VIEW)
0

I~0:
xozr~::(/)~I(/)
0:00
or

o:o1(

Valid

,"'---------

~~~

----~,

CSO, CS1, CS2

Valid

, I
,

lOll

tsu1

,04

-----+I.,

tsu2

50%

~ th2 ----.I

td1

,"I

50%

,
\50% Active

. : '

\~
Activ
5 0 % - Le

50%1
'

~tW4 - - - - - + j - - t d 2 ~
:
'
r,~
'.

tpcl1

BOO

:..

ill

tpcl1

" \.

50%

----------------------,~---'
ten
'"
.'
DBO-DB7

,,,

'(
----------------------------(.. Valid Data

or
Active

50%",-=

50%

~-------------

!dis

~
/)--- - - - - - - - - - - - - - - - - - -

Figure 4. Read Cycle Timing Waveforms

...I¥. .

A2, A1, AO J _ 5 0 _ %___________v_a_lid________________

,~~~

,,
CSO,CS1,CS2 ---..,....:\ . 50%
,

Valid

50%

, I..

tsu4

:..

,,,

5O%
_______________

tsu5

I.,.- th4

-+l'

--------~.,

td3--+-'

.:
).50% Active

,~!~

:
J.-50-%-----------'l,

~tw5 ----+1*"- - ! d 4
:
tsu6 -r1"t---". ...--.l..I- th5
,f•

. .)I

A_"'n_

50%

A::ve

DBO-DB7 ___________________________~I(~--'. Valid Data .)--- - - - - - - - - - - - - - - - -

Figure 5. Write Cycle Timing Waveforms

~TEXAS
2·226

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A-NOVEMBER 1994-REVISEDMARCH 1996

PARAMETER MEASUREMENT mFORMATION
Start'l
~Start/
Data Bits 5-S
50%
50%\1'---'-_
_ _ _ _ _.....
Stop (1-2) I ___"""""_________

Serial Out
(SOUT)

td5 ----!+------+i

In~:f~~ ---'""~ 50%
tpd2 14
~I
1
1

I+-+l---- td6

Parity
'}. 50%

50% Y,..------5-0%"""\L

I
I
I

~ tpd2 -+i

I+- td7 --+i

IOW:::{
(WR THR) 50%~ 50%

50%

tpd4 ~

lOR
(RDIIR)

1,.-_50%

Figure 6. Transmitter Timing Waveforms
lOW ~
(WR THR)

Byte #1

t
I

,.._ _ _ _ _---'1','1-;- - - - - - - - - - - - 50%

_~X

SOUT _ _ _ _D_a_ta_""'T"1

Parity

Stop 50",,(, ).",--_S_ta_rt_-,I

tpd5 -111~4-----.;~I

Ids ---i+---+I
I,----------------~I

TXRDY _ _ _ _ _ _ _ _--J!50%

50% \ ' -_ _ _ _ __

Figure 7. Transmitter Ready Mode 0 Timing Waveforms
lOW
(WRTHR)

SOUT

r----~I--------~~'~;-------

"--_..II
Data
tpd5

50%

Parity

Stop

Start /

~1~4----+i~1

150

TXRDY _ _ _ _ _ _ _ _- . J

FIFO Full

Start of
B
tlytyteefl#11t16

\f----Ir
" ~ I+- tdS

r>~

);

50% \ ' -_ __

Figure 8. Transmitter Ready Mode 1 Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-227

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

r---flJ.-

RClK

-------.;~i
ClK
Tl16C450 Mode
(receiver

--------------~~

in:~ ~

data)

sa~r:
Interrupt
(data ready or
RCVR ERR)

tpd6

Start

Data Bits 5-8

. .1. . ._~~I.-....IL..I_J~'--_~~l.-----I~

----Jll~/.,..J-

.....

Idg ~

I ,---------'lr~ "nO<.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

50%

I+--tpd7~1

50% \ .

Active ; " - - -

Figure 9. Receiver Timing Waveforms

SIN
Sample
elK
Trigger
Interrupt
(FCR6, 7=0, 0)

~oata Bits 5-8

~(J~

I I
I
I ~~\-------~l'""""---

-------------+1IfI+bg ~
...

lOR
(RORBR)

50%

I
I

tpd7

" - - (FIFO below
trigger level)

~
. I ' '1

50%~

--J)t,.5-0-%--50%~~~---------

lSI _ _ _ _ _ _ _ _ _ _ _ _ _
Interrupt
lOR
(RO lSR)

i+--

tpd7

---+J

~ Active /~---------50%"----./
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms

~TEXAS

2-228

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(FIFO at or above
trigger level)

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

'X:Y::::'J

SIN _ _ _ _

Sa~r; .....u.-~. . .u. . ~....11.-1

-+-,...a....-I.....u.-I_

...&-1

tcJ9 ----t14-4-~.I

---JPI
50%
"

Trigger
Level
(see
A)_ _
lime Out
or _ _ _ _
_Note
__
Interrupt

(FIFO at or above
trigger level)

5O%'i. . ____

(FIFO below
trigger level)

~tpd7

f._____ ..., ___\,-+'--II
1\ __________

lSI - - - - ,
Interrupt
\

50%· Top Byte of FIFO

50%

~_""--_---J+

tcJs ---J+-----+I

lOR
(RO lSR)

(RO

R~R~

I
I
I

Active

loll

tpd7

-------+I-~\

Active

·1

II~----I~----.

I
I
I

50%

50%,\

Active

Previous Byte
Read From FIFO
NOTE A: This is the reading of the last byte in the FIFO.

Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
(
}j

lOR
(RORBR)
SIN
(first byte)
Sample
elK

RXROY

Active

50%\

I
I
I
I
I
I

Ys:\

tdS
lol
(see Note B )

.1
1

See Note A

1
. tpd8

I
I
loll

,\50%
(

1
,,50%

NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCRO = 1, tdS =3 RClK cycles. For a time-out interrupt, IdS =8 RCLK cycles.

Figure 12. Receiver Ready Mode 0 Waveforms

~TEXAS

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1998

PARAMETER MEASUREMENT INFORMATION
((

lOR
(RDRBR)
SIN
(first byte that reaches
the trigger level)

50%\
____

Active

See Note A

-J~~_____

Sample

ClK

14 _I

leIe

(see Note B)

~~50%
______~~IT~______________~-J;(5O%

RXRDY

lpcta

NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCRO-1,1d9 = 3 RCLK cycles. For a trigger change level interrupt,ld9 = 8 RCLK.

Figure 13. Receiver Ready Mode 1 Waveforms

IOW~
(WR MCR)

\."--___5_0%.J~

~tpde

RTS, DTR

CTS, DSR, DCD

--------------~\ 50%

_______

\ 1~50_%_______________________

5O%-J~

tpd10 ~

INTO,INT1,
1INT,2INT

tpd10

5O%)rr---~~50%
tpd11

lOR
(RD MSR)

5O%)rr---~,,~

---1+-+1

tpd12

------------~\JI 50%

____5O~%~
14

"--./

Figure 14. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
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50%''"--------

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
DATA

~
tsu7 ---J.--..i
l

~"",5_00_YO_ _

Valid

I~ th6

Jtr5-0%-o---------------

--50-%~o\L

I-

-I

tw6

50%~50%

I-

td10

-I

I-

tw8

*-+td11

50%~50% ~""'5-00-~-------

BUSY

td12

I-

I+--tw7~

Figure 15. Parallel Port Timing Waveforms
ENIRQ

"""'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

50%\

150%

1 ' - - - - _ - '1
td13-+1
~
·1
--------~I

INT2
Line Printer
Status Register,
Bit 2 (PRINT)

50%\

'--I

td14

_______________________

150%

50%{

------.I
1

~ td(intl
1
(see Note A)

~50%

NOTE A: A timing value is not provided for td(int) in the tables since the line printer status register, bit 2 (PRINT) is an internal signal.

Figure 16. Parallel Port AT Mode Timing (ENIRQ = Low) Waveforms

~TEXAS

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DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ENIRQ

\ . . .--Jt 50%

td15 -.:

INT2

1--

----.I

I~_ _ _ _+I..... I

________---J150%

td16

\,50%

I
I

'-------iJj

"---JI~5-0.-~----Figure 17. Parallel Port PS/2 Mode Timing (ENIRQ = High) Waveforms

RESET

50%

~ 50%

·1

tw3

Figure 18. RESET Voltage Waveform

~TEXAS

INSTRUMENTS

2-232

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLSI89A- NOVEMBER 1994 - REVISED MARCH 1996

Table 1. Internal Register Mnemonic Abbreviations
CONTROL

MNEMONIC

STATUS

DATA

MNEMONIC

Line control register

LCR

Line status register

LSR

Receiver buffer register

RBR

FIFO control register

FCR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MCR

Divisor latch LSB

DLL

Divisor latch MSB

DLM

Interrupt enable register

IER

The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register (bit 7)
to select the register to be written or read (see Table 2). Individual bits within the registers are referred to by the register
mnemonic and the bit number in parenthesis. As an example, LCR7 refers to line control register bit 7.
The transmitter holding register and receiver buffer register are data registers that hold from five to eight bits of data.
If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always the first serial
data bit received and transmitted. The ACE data registers are double buffered (TL 16C450 mode) or FIFO buffered
(FIFO mode) so that read and write operations can be performed when the ACE is performing the parallel-to-serial
or serial-to-parallel conversion.

Table 2. Register Selectiont
DLAB

MNEMONIC

RBR

Receiver buffer register (read only)

THR

Transmitter holding register (write only)

IER

Interrupt enable register

IIR

Interrupt identification register (read only)

FCR

LCR

Line control register

MCR

Modem control register

LSR

Line status register

MSR

Modem status register

SCR

Scratch pad register

DLL

LSB divisor latch

DLM

MSB divisor latch

FIFO control register (write only)

t The senal channel IS accessed when either CSO or CSt

low.

X = irrelevant, L = low level, H = high level

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DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SllS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

Table 3. Summary of Accessible Registers
ADDRESS

BITS

BIT 5

BIT4

BIT3

BIT 2

BIT 1

BIT 0

RBR
(read only)

Data
Bit 7
(MSB)

Data
Bit 6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0
(lSB)

THR
(write only)

Data
Bit 7

Data
Bit6

Data
BitS

Data
Bit 4

Data
Bit 3

Data
Bit 2

Data
Bit 1

Data
Bit 0

Dll

Bit 7

Bit 6

BitS

Bit4

Bit 3

Bit 2

Bit 1

BitO

DlM

Bit 15

Bit14

Bit13

Bit12

Bit 11

Bitl0

Bit 9

Bit 8

IER

(EDSSI)
Enable
modem
status
interrupt

(ERlSI)
Enable
receiver
line
status
interrupt

(ETBEI)
Enable

(ERBFI)
Enable

DMA
mode
select

FCR
(write only)

Receiver
Trigger
(MSB)

Receiver
Trigger
(lSB)

Reserved

transmitter

received

holding
register
empty
interrupt

data
available
interrupt

Transmitter

Receiver

FIFO

FIFO
Enable

reset

IIR
(read only)

FIFOs
Enabled+

Interrupt ID
Bit 3+

Interrupt ID
Bit 2

InterruptlD
Bit 1

011
interrupt
pending

lCR

(DlAB)
Divisor latch
access bit

Set
break

Stick
parity

(EPS)
Even parity
select

(PEN)
Parity
enable

(STB)
Number of
stop bits

(WlSB1)
Word length
select bit 1

(WlSBO)
Word length
select bit 0

MCR

loop

OUT2
Enable
external
interrupt
(INTO or INTI)

OUTI
(an unused
internal
signal)

(RTS)
Request
to send

(DTR)
Data
terminal
ready

lSR

(THRE)
Transmitter
holding

(BI)
Break
interrupt

(FE)
Framing
error

(PE)
Parity

(OE)
Overrun

error

(DR)
Data
ready

(dDCD)
Delta

data carrier

(TERI)
Trailing
edge ring

detect

indicator

(dDSR)
Delta
data set
ready

(dCTS)
Delta
clear
to send

Bit 3

Bit 2

Bit 1

Bit 0

Error in

(TEMT)

Receiver

Transmitter

FIFO+

empty

MSR

SCR

(DCD)
Data carrier
detect

(RI)
Ring
indicator

(DSR)
Data set
ready

(CTS)
Clear
to send

Bit 7

Bit 6

BitS

Bit 4

tDLAB = 1

:I: These bits are always 0 when FIFOs are disabled.

~TEXAS

INSTRUMENTS
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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO control register (FCR)
This write only register is at the same location as the interrupt identification register. It enables and clears the
FIFOs, sets the trigger level of the receiver FIFO, and selects the type of DMA signaling.
•

Bit 0: FCRO enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be cleared by
clearing FCRO. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL 16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCRO.

•

Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the
shift register.

•

Bit 2: When set, FCR2 clears all bytes in the transmitter FIFO and resets the counter. This does not clear
the shift register.

•

Bit 3: When set, FCR3 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCRO
is set.

•

Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

•

Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4):
Table 4. Receiver FIFO Trigger Level
7

BIT

RECEIVER FIFO
TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1.

LSRO is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.

IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt
IIR=04.

Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by
the FIFO. When the FIFO drops below its programmed trigger level, it is cleared.

IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is
cleared when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.

~TEXAS

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1.

When the following conditions exist, a FIFO character time-out interrupt occurs:
a.

Minimum of one character in FIFO

Last received serial character is longer than four continuous previous character times ago (if two stop
bits are programmed, the second one is included in the time delay)

By using the RCLK input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.

The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received when
there has been no time-out interrupt.

A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.

Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCRO = 1, IER = 1).
1.

When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.

The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time when the
following occurs:
THRE =1 and there is not a minimum of two bytes at the same time in transmitter FIFO since the last
THRE = 1. The first transmitter interrupt after changing FCRO is immediate assuming it is enabled.

receiver FIFO trigger level and character time-out interrupts have the same priority as the received data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.

FIFO polled mode operation
Clearing IERO, IER1, IER2, IER3, or all with FCRO = 1 puts the ACE into the FIFO polled mode. The receiver
and transmitter are controlled separately. Either one or both can be in the polled mode.
In the FI FO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
ACE status.

interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTO or
INT1) output. All interrupts are disabled by clearing IERO - IER3. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the interrupt identification register and the
active (high) interrupt output. All other system functions operate in their normal manner, including the setting
of the LSRs and MSRs. The contents of the IER shown in Table 3 are described in the following bulleted list.
•

Bit 0: When IERO is set, IERO enables the received data available interrupt and the time-out interrupts in
the FIFO mode.

~TEXAS

INSTRUMENTS
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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
•

Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.

•

Bit 2: When IER2 is set, the receiver line status interrupt is enabled.

•

Bit 3: When IER3 is set, the modem status interrupt is enabled.

•

Bits 4 -7: IER4 through IER7 are cleared.

In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are as follows:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER

INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL

BIT3

BIT2

BIT 1

First

BITO

INTERRUPT TYPE

INTERRUPT SOURCE

INTERRUPT RESET
CONTROL

None

Receiver line status

DE, PE, FE, or BI

LSR read

Second

Received data available

Receiver data available or trigger level
reached

RBR read until FIFO
drops below the
trigger level

Second

Character time-out
indicator

No characters have been removed
from or input to the receiver FIFO
during the last four character times and
there is at least one character in it
during this time.

RBR read

Third

THRE

fiR read if THRE is
the interrupt source
orTHR write

Fourth

Modem status

CTS, DSR, RI, or DCD

MSR read

•

Bit 0: IIRO indicates whether an interrupt is pending. When IIRO is cleared, an interrupt is pending.

•

Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

•

Bit 3: IIR3 is always cleared when in the TL 16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.

•

Bits 4 and 5: IIR4 and IIR5 are always cleared.

•

Bits 6 and 7: IIR6 and IIR7 are set when FCRO

= 1.

~TEXAS

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DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

Bits 0 and 1: LCRO and LCR1 are the word length select bits. The number of bits in each serial character
is programmed as shown.

•

Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.

•

Bit 3: LCR3 is the parity enable bit. When LCR3 is set, a parity bit between the last data word bit and stop
bit is generated and checked.

•

Bit 4: LCR4 is the even parity select bit. When LCR4 is set, even parity is enabled.

•

Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 = 1), LCR5 = 1 causes the transmission
and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity to a known
state and allows the receiver to check the parity bit in a known state.

•

Bit 6: LCR6 is the break control bit. When LCR6 is set, the serial output (SOUT1/S0UTO) is forced to the
spacing state (low). The break control bit acts only on the serial output and does not affect the transmitter
logic. When the following sequence is used, no invalid characters are transmitted because of the break:
Step 1: Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.
Step 2: Set the break in response to the next THRE status indicator.
Step 3: Waitfor the transmitter to be idle when transmitter empty status signal is set high (TEMT = 1); then
clear the break when the normal transmission has to be restored.

•

Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. LCR7 must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register, or the interrupt enable register.

~TEXAS

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Line Control Register

IL~RIL~RIL~RIL~RIL~RIL~RIL~RIL~RI

Word Length
Select

o 0 =5 Data Bits
o 1 = 6 Data Bits

Stop Bit
Select

1 0 = 7 Data Bits
1 1 = 8 Data Bits
o = 1 Stop Bits
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected

Parity Enable

o = Parity Disabled

Even Parity
Select

1 = Parity Enabled

o = Odd Parity

1 = Even Parity

Stick Parity

o= Stick Parity Disabled
1 = Stick Parity Enabled

Break Control

o= Break Disabled

Divisor Latch
Access Bit

1 = Break Enabled

o= Access Receiver Buffer
1 = Access Divisor Latches

Figure 19. Line Control Register Contents

line printer port
The line printer port contains the functionality of the port included in the TL 16C452 but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PE) terminal. This enhancement
is the addition of a direction control bit and an interrupt status bit.

register 0 line printer data register
The line printer (LPT) port is either output only or bidirectional depending on the state of the extended mode
terminal and data direction control bits.
Compatibility mode (PEMO

= L)

Reads to the LPT data register return the last data that was written to the port. Write operations immediately
output data to POO-P07.
Extended mode (PEMO = H)
Read operations return either the data last written to the LPT data register when the direction bit is cleared or
return the data that is present on POO - PO? when the direction is set to read. Write operations to the LPT
data register latch data into the output register; however, they only drive the LPT port when the direction bit is
cleared.

-!!1

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

line printer port (continued)
Table 6 summarizes the configuration of the PD port based on the combinations of logic level on the PEMD
terminal and value of the direction control bit (DIR).
Table 6. Extended Mode and Direction Control Bit Combinations
PEMD

DIR

PDO-PD7 FUNCTION

X
0

PC/AT mode - output

PS/2 mode - input

H
H

PS/2 mode - output

The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT
connector terminals. Table 7 (in the default column) shows the values of each bit after reset in the case of the
printer being disconnected from the port.
Table 7. LPS Register Bit Description

BIT

DESCRIPTION

DEFAULT

Reserved

3
4

ERR

t
t
t
t
t

SLCT

ACK

BSY

Outputs are dependent upon device" Inputs.

•

Bits 0 and 1: LPSO and LPS1 are reserved and always set.

•

Bit 2: LPS2 is the printer interrupt (PRINT, active low) status bit. When cleared, LPS2 indicates that the
printer has acknowledged the previous transfer with an ACK handshake (if bit 4 of the control register is set).
The bit is cleared on the active-to-inactive transition of the ACK signal. This bit is set after a read of the status
port.

•

Bit 3: ERR is the error status bit and corresponds to ERR input.

•

Bit 4: SLCT is the select status bit and corresponds to SLCT input.

•

Bit 5: PE is the paper empty status bit and corresponds to PE input.

•

Bit 6: ACK is the acknowledge status bit corresponds to ACK input.

•

Bit 7: BSY is the busy status bit and corresponds to BUSY input (active high).

~TEXAS

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line printer port (continued)
register 2 line printer control register
The line printer control (LPG) register is a read/write port that controls the PDD-PD? direction and drive the
printer control lines. Write operations set or clear these bits, while read operations return the state of the last
write operation to this register. The bits in this register are defined in Table 8 and the following bulleted list.

Table 8. LPC Register Bit Description
BIT

DESCRIPTION

STB

AFD

INIT

SLiN

INT2 EN

DIR

Reserved 0

•

Bit 0: STB is the printer strobe control bit. When STB is set, the STB signal is asserted on the LPT interface.
When STB is cleared, the STB signal is negated.

•

Bit 1: AFD is the autofeedcontrol bit. When AFD is set, the AFD signal is asserted on the LPT interface.
When AFD is cleared, the signal is negated.

•

Bit 2: INIT is the initialize printer control bit.When INIT is set, the INIT signal is negated. When INIT is
cleared, the INIT signal is asserted on the LPT interface.

•

Bit 3: SUN is the select input control bit. When SUN is set, the SUN signal is asserted on the LPT interface.
When SUN is cleared, the signal is negated.

•

Bit 4: INT2 EN is the interrupt request enable control bit. When set, INT2 EN enables interrupts from the
LPT port. When cleared, INT2 EN disables interriJpts and places INT2 signal in the high-impedance state.

•

Bit 5: DIR is the direction control bit which is only used when PEMD is high. When DIR is set, the output
buffers in the LPD port are disabled allowing data driven from external sources to be read from the LPD port.
When DIR is cleared, the LPD port is in the output mode.

•

Bits 6 and?: These bits are reserved and are always cleared.

~TEXAS

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2·241

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 9 is described in the
following bulleted list.
•

Bit 0: DR is the data ready bit. When DR is set when an incoming character is received and transferred into
the receiver buffer register or the FIFO. LSRO is cleared by a CPU read of the data in the receiver buffer
register or the FIFO.

•

Bit 1: OE is the overrun error bit. An OE indicates that data in the receiver buffer register is not read by the
CPU before the next character is transferred into the receiver buffer register overwriting the previous
character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An overrun error
occurs in the FIFO mode after the FIFO is full and the next character is completely received. The overrun
error is detected by the CPU on the first LSR read after it happens. The character in the shift register is not
transferred to the FIFO, but it is overwritten.

•

Bit 2: PE is the parity error bit. A PE indicates that the received data character does not have the correct
parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared when
the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with a particular
character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

•

Bit 3: FE is the framing error bit. A FE indicates that the received character does not have a valid stop bit.
LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing level).
The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the framing
error is associated with a particular character in the FIFO. LSR3 reflects the error when the character is at
the top of the FIFO.

•

Bit 4: BI is the break interrupt bit. BI is set when the received data input is held in the spacing (low) state
for longer than a full word transmission time (start bit + data bits + parity + stop bits). The BI indicator is
cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated with a particular
character in the FIFO. LSR4 reflects BI when the break character is at the top of the FIFO. The error is
detected by the CPU when its associated character is at the top of the FIFO during the first LSR read. Only
one zero character is loaded into the FIFO when BI occurs.

LSR1 - LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any ofthe conditions are detected. This interrupt is enabled by setting IER2
in the interrupt enable register.
•

Bit 5: THRE is the transmitter holding register empty bit. THRE indicates that the ACE is ready to accept
a new character for transmission. The THRE bit is set when a character is transferred from the transmitter
holding register into the transmitter shift register. LSR5 is cleared by the loading of the transmitter holding
register by the CPU. LSR5 is not cleared by aCPU read of the LSR. Inthe FIFO mode when the transmitter
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the IIR. If THRE is the interrupt source
indicated in IIR, INTRPT is cleared by a read of the IIR.

•

Bit 6: TEMT is the transmitter empty bit. TEMT is set when the transmitter holding register (THR) and the
transmitter shift register are both empty. LSR6 is cleared when a character is loaded into the THR and
remains cleared until the character is transferred out of SOUTo TEMT is not cleared by a CPU read of the
LSR. In the FIFO mode, when both the transmitter FIFO and shift register are empty, TEMT is set.

•

~TEXAS

INSTRUMENTS
2·242

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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
line status register (LSR) (continued)
NOTE

The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.

Table 9. Line Status Register Bits
LSR BITS
LSRO data ready (DR)

Ready

Not ready

LSRI overrun error (OE)

Error

No error

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

LSR5 transmitter holding register empty (THRE)

Empty

Not empty

LSR6 transmitter empty (TEMT)

Empty

Not empty

Error in FIFO

No error in FIFO

LSR7 receiver FIFO error

master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A Iowan RESET causes the following:
•

It initializes the transmitter and receiver clock counters.

•

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-243

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
master reset (continued)
Table 10. RESET Affects on Registers and Signals
REGISTERISIGNAL

RESET

RESET CONTROL

Interrupt enable register

Reset

All bits cleared (0-3 forced and 4-7 permanent)

Interrupt identification register

Reset

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared, and
bits 4-5 are permanently cleared.

Line control register

Reset

All bits cleared

Modem control register

Reset

All bits cleared (5 - 7 permanent)

FIFO control register

Reset

All bits cleared

Line status register

Reset

All bits are cleared, except bits 5 and 6 are set.

Modem status register

Reset

Bits 0-3 cleared, bits 4-7 input signal

SOUT

Reset

High

Interrupt (RCVR errs)

Read LSR/Reset

Low

Interrupt (receiver data ready)

Read RBRlReset

Low

Read IIR1Write THR/Reset

Low

Read MSRlReset

Low

Interrupt (THRE)
Interrupt (modem status changes)
OUT2

Reset

High

RTS

Reset

High

DTR

Reset

High

OUT1

Reset

High

modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 20. MCR can be written and
read. The RTS and OTR outputs are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. The MCR bits are shown in the following bulleted list.
•

Bit 0: When MCRO is set, the OTR output is forced low. When MCRO is cleared, the OTR output is forced
high. The OTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.

•

Bit 2: MCR2 has no affect on operation.

•

Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.

•

Bit 4: MCR4 provides a localloopback feature for diagnostic testing of the channel. When MCR4 is set,
SOUT is set to the marking (high) state and the SIN is disconnected. The output of the transmitter shift
register is looped back into the receiver shift register input. The four modem control inputs (CTS, OSR, OCO,
and RI) are disconnected. The modem control outputs (OTR, RTS, OUT1, and OUT2) are internally
connected to the four modem control inputs. The modem control output terminals are forced to their inactive
(high) state on the TL16C552AI. In the diagnostic mode, data transmitted is immediately received. This
allows the processor to verify the transmit and receive data paths of the selected serial channel. Interrupt
control is fully operational; however, interrupts are generated by controlling the lower four MCR bits
internally. Interrupts are not generated by activity on the external terminals represented by those four bits.

~TEXAS

INSTRUMENTS
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TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
•

Bits 5 - 7: MCR5 - MCR7 are permanently cleared.
Modem Control Register

Data Terminal
Ready

L--_ _ _ _+_

o =DTR Output High (Inactive)
1

=DTR Output Low (active)

=RTS Output High (inactive)

Request
to Send

o
1

Out 1

No Effect on External Operation

=RTS Output Low (active)

(internal)

'----------1_

Out 2
(Internal)

LOOp

o =External Interrupt Disabled
1

=External Interrupt Enabled

o=Loop Disabled
1

=Loop Enabled

Bits Are Cleared

Figure 20. Modem Control Register Contents

modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs. This is done by accessing the data bus
interface of the ACE in addition to the current status of four bits of the MSR. These four bits indicate whether
the modem inputs have changed since the last reading of the MSR. The delta status bits are set when a control
input from the modem changes state and is cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 - MSR7 are status indicators of these lines. A set
status bit indicates that the input is low. A cleared status bit indicates that the input is high. When the modem
status interrupt in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSRO MSR3 is set. The MSR is a priority-4 interrupt. The contents of the MSR are described in Table 11.
•

Bit 0: MSRO is the delta clear-to-send (dCTS) bit. dCTS displays that the CTS input to the serial channel
has changed states since it was last read by the CPU.

•

Bit 1: MSR1 is the delta data set ready (d DSR) bit. d DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.

•

~TEXAS

INSTRUMENTS
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2-245

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
•

Bit 3: MSR3 is the delta data carrier detect (dDCD) bit. dDCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.

•

Bit 4: MSR4 is the clear-to-send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUTo When the serial channel '
is in the loop mode (MCR4 is set), MSR4 reflects the value of RTS in the MCR.

•

Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.

•

Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR register clears the delta modem status indicators but has no affect on the other status bits.
For LSR and MSR, the setting of status bits is inhibited during status register read operations. If a status
condition is generated during a read lOR operation, the status bit is not set until the trailing edge of the read.
When a status bit is set during a read operation and the same status condition occurs, that status bit is
cleared at the trailing edge of the read instead of being set again. In the loop back mode, when modem
status interrupts are enabled, the CTS, DSR, RI and DCD input lerminall3 are ignored; however, a modem
status interrupt can still be generated by writing to MCR3-MCRO. Applications software should not write 10
the MSR.

Table 11. Modem Status Register Bits
MSRBIT

MNEMONIC

MSRO

dCTS

DESCRIPTION

MSRI

dDSR

Delta data set ready

MSR2

TERI

Trailing edge of ring indicator

MSR3

dDCD

MSR4

CTS

Clear to send

MSR5

DSR

Data set ready

MSR6

Ring indicator

MSR7

DCD

Delta clear to send

Delta data carrier detect

Data carrier detect

~TEXAS

INSTRUMENTS
2-246

POST OFFICE BOX 655303 • OALLAS. TEXAS 752e5

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

parallel port registers
The TL16C552AI parallel port can connect the device to a Centronics-style printer interface. When chip select 2
(CS2) is low, the parallel port is selected. Table 13 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (lOR) and write (lOW) terminals as
shown. The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of tbe printer in the six most significant
bits. The status bits are printer busy BSY, acknowledge (ACK) (a handshake function), paper empty (PE), printer
selected (SLCT), error (ERR) and printer interrupt (PRINT). The read control register allows the state of the
control lines to be read. The write control register sets the state of the control lines. They are direction (OIR),
interrupt enable (INT2 EN), select in (SUN), initialize the printer (INIT), autofeed the paper (AFO), and strobe
(STB), which informs the printer of the presence of a valid byte on the parallel bus. The write data register allows
the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the parallel
port implementation used in the IBM serial parallel adaptor.
Table 12. Parallel Port Registers
REGISTER

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

Read data

PD7

PD6

PD5

PD4

PD3

PD2

PDl

PD~

Read status

BSY

ACK

SLCT

ERR

Read control

PEMD. DIR

INT2 EN

SLiN

INIT

AFD

STB

PD7

PD6

PD5

PD4

PD3

PD2

PDl

PD~

DIR

INT2 EN

SLiN

INIT

AFD

STB

Write data
Write control

Table 13. Parallel Port Register Select
CONTROL PINS

lOW

CS2

Read data

Read status

lOR

Read control

Invalid
Write data

Invalid

Write control

Invalid

programmable baud rate generator
The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to (2 1L 1). The outputfrequency ofthe baud generator is 16x the data rate [divisor
# clock + (baud rate x 16)] referred to in this document as RCLK. Two 8-bit divisor latch registers store the
divisor in a 16-bit binary format. These divisor latch registers must be. loaded during initialization. Upon loading
either of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial
load. The BRG can use any of three different popular frequencies to provide standard baud rates. These
frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 to
512 kbps are available. Tables 14, 15, 16, and 17 illustrate the divisors needed to obtain standard rates using
these three frequencies.

~TEXAS

INSTRUMENTS
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2-247

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLlS189A- NOVEMBER 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 14. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE

DIVISOR (N) USED TO

DESIRED

GENERATE 16xCLOCK
2304
1536
1047
857
768
384
192
96

50
75
110

134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

0.026
0.058

0.690

58
48
32
24
16
12
6
3
2

2.860

Table 15. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

3840
2560
1745
1428
1280
640
320
160
107
96

53
40
27
20
10
5

~TEXAS

2·248

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.026
0.034

0.312

0.628

1.230

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A - NOVEMBER 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 16. Baud Rates Using a 8-MHz Clock
BAUD RATE

DIVISOR (N) USED TO

DESIRED

GENERATE 16xCLOCK

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600'
19200
38400
56000
128000
256000
512000

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

10000
6667
4545
3717
3333
1667
833
417

0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080

250
208
139
104
69
52
26
13
9
4
2
1

0.180
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400

Table 17. Baud Rates USing a 16-MHz Clock
DESIRED

DIVISOR (N) USED TO
GENERATE 16x CLOCK

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
1000000

20000
13334
9090
7434
6666
3334
1666
834
554
500
416
278
208
138
104
52
26
18
8
4
2
1

BAUD RATE

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

0.00
0.00
0.01
0.01
0.01
-0.02
0.04
-0.08
0.28
0.00
0.16
-0.08
0.16
0.64
0.16
0.16
0.16
-0.79
-2.34
-2.34
-2.34
0.00

~TEXAS

INSTRUMENTS
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2-249

TL16C552AI
DUAL ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS189A- NOVEMBER 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

receiver
Serial asynchronous data is input into SIN. The ACE continually searches for a high-to-Iow transition
from the idle state. When the transition is detected, a counter is reset and counts the 16x clock to 7 1/2, which
is the center of the start bit. The start bit is valid if SIN is still low. Verifying the start bits prevents the receiver
from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character (LCRO and LCR1). When parity is used, LCR3 and
the polarity of parity LCR4 is needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indicator in LSRO is set. The CPU reads the receiver
buffer register, which clears LSRO. If the character is not read prior to a new character transfer from the RSR
to the RBR, the overrun error status indicator is set in LSR1. If there is a parity error, the parity error is set in
LSR2. If a stop bit is not detected, a framing error indicator is set in LSR3.
If the data into SIN is a symmetrical square wave, the center of the data cells occurs within ±3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16x clock cycle
prior to being detected.

scratch pad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.

~TEXAS

INSTRUMENTS
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TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSI658 - JANUARY 1994 - REVISED MARCH 1996

• Integrated Asynchronous Communications
Element
• Consists of Four Improved TL16C550 ACEs
Plus Steering Logie
• In FIFO Mode, Each ACE Transmitter and
Receiver Is Buffered With 16-Byte FIFO to
Reduce the Number of Interrupts to CPU
• In TL 16C450 Mode, Hold and Shift
Registers Eliminate Need for Precise
Synchronization Between the CPU and
Serial Data
• Up to 16-MHz Clock Rate for up to 1-Mbaud
Operation
• Programmable Baud Rate Generators Allow
Division of Any Input Reference Clock by 1
to (216 _1) and Generates Internal 16 x
Clock
• Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
• Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts

• Fully Programmable Serial Interface
Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit
- 1-,1112-, or 2-Stop Bit Generation
- Baud Generation (DC to 256 Kilobits Per
Second)
• False Start Bit Detection
• Complete Status Reporting Capabilities
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
- Loopback Controls for Communications
Link Fault Isolation
- Break, Parity, Overrun, Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• 3-State Outputs Provide TTL Drive
Capabilities for Bidirectional Data Bus and
Control Bus

description
The TL 16C554 is an enhanced quadruple version of the TL 16C550B asynchronous communications element
(ACE). Each channel performs serial-to-parallel conversion on data characters received from peripheral
devices or modems and parallel-to-serial conversion on data characters transmitted by the CPU. The complete
status of each channel of the quadruple ACE can be read at any time during functional operation by the CPU.
The information obtained includes the type and condition of the operation performed and any error conditions
encountered.
The TL 16C554 quadruple ACE can be placed in an alternate FI FO mode, which activates the internal FI FOs
to allow 16 bytes (plus 3 bits of error data per byte in the receiver FIFO) to be stored in both receive and transmit
modes. To minimize system overhead and maximize system efficiency, all logic is on the chip. Two terminal
functions have been provided to allow signaling of direct memory access (OMA) transfers. Each ACE includes
a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and

(2 16 _1).
The TL 16C554 is available in the 68-pin plastic-leaded chip-carrier (PLCC) FN package.

~TEXAS

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2-251

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

FNPACKAGE
(TOP VIEW)

1(3
C
IZ oc
18
o$~Z~~~
MN~O~
xQo
c~~~ccc~cccc~~~bc
9 8 7
10
11

OSRA
CTSA
OTRA
VCC

RTSA
INTA
CSA
TXA
lOW
TXB
CSB
INTB
RTSB
GNO
DTRB
CTSB
OSRB

6 5 4 3 2

1 68 67 66 65

63 62 61

12
13

59
58
57

17
18
19

20
21

50
49

23
24

47
46

52
51

~~~~~~~M~~~~~~~~~

OSRO
CTSO
OTRO
GNO
RTSO
INTD
CSO
TXO
lOR
TXC
CSC
INTC
RTSC
Vcc

OTRC
CTSC
OSRC

NC - No internal connection

functional block diagramt
D7-oo

Data
Bus

I
I

,.-+-

A2-AO
CSx
IOR,IOW
RESET
INTx
TXRDY, RXRDY

XTAL1
XTAL2

Control
logic

Interrupt
Logic I

Clock
Circuit

TL16C550B
Circuitry

r--

Transmit
Control
Logic

TXx

j--------1

t For TL16C550 circuitry, refer to the TL16C550B data sheet.

~lExAs

2·252

RXx

TL16C550B
Circuitry

Receive
Control
Logic

INSTRUMENTS

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Modem
Control
logic

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B-JANUARY 1994- REVISED MARCH 1996

Terminal Functions
TERMINAL

110

DESCRIPTION

34
33
32

Register select terminals. AO, A 1, and A2 are three inputs used during read and write operations to select
the ACE register to read or write.

CSA,CSB,
CSC,CSD

16,20,
50,54

Chip select. Each chip select (CSx) enables read and write operations to its respective channel.

CTSA,CTSB,
CTSC,CTSD

11,25,
45,59

Clear to send. CTSx is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the
modem status register. CTS has no affect on the transmit or receive operation.

07-00

66-68
1-5

I/O

Data bus. Eight data lines wnh 3-state outputs provide a bidirectional path for data, control and status
information between the TL 16C554 and the CPU. DO is the least significant bit (LSB).

DCDA,DCDB,
DCDC, DCDD

9,27,
43,61

Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The condition
of this signal is checked by reading bit 7 of the modem status register.

DSRA,DSRB,
DSRC,DSRD

10,26,
44,60

DTRA,DTRB,
DTRC,DTRD

12,24,
46,58

Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready to
establish communications. It is placed in the active state by setting the DTR bit olthe modem control register.
DTRx is placed in the inactive state (high) either as a result of the master reset during loop mode operation
or clearing bit 0 (DTR) of the modem control register.

Interrupt normal. INTN operates in conjunction with bit 3 olthe modem status register and affects operation
of the interrupts (INTA, INTB, INTC, and INTO) for the four universal asynchronous receiver/transceivers
(UARTs) per the following table.

NAME

AO
Al

INTN

NO.

Data set ready. DSRx is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. DSR has no affect on the transmit or receive operation.

INTN

OPERATION OF INTERRUPTS

Brought low or
allowed to float

Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR bit
3 is cleared, the 3-state interrupt output of that UART is in the high-impedance state.
When the MCR bit 3 is set, the interrupt output of the UART is enabled.

Brought high

Interrupts are always enabled, overriding the OUT2 enables.

GND

6,23,
40,57

INTA,INTB,
INTC,INTD

15,21,
49,55

lOR

Read strobe. A low level on lOR transfers the contents of the TL 16C554 data bus to the external CPU bus.

lOW

Write strobe. lOW allows the CPU to write into the selected by the address register.

RESET

Master reset. When active, RESET clears most ACE registers and sets the state of various signals. The
transmitter output and the receiver input is disabled during reset time.

RIA,RIB,
RIC, RID

8,28,
42,62

Ring detect indicator. A low on Rlx indicates the modem has received a ring signal from the telephone line.
The condition of this signal can be checked by reading bit 6 of the modem status register.

RTSA, RTSB,
RTSC,RTSD

14,22,
48,56

Request to send. When active, RTSx informs the modem or data set that the ACE is ready to receive data.
Writing a 1 in the modem control register sets this bitto a low state. After reset, this terminal is set high. These
terminals have no affect on the transmit or receive operation.

RXA,RXB
RXC,RXD

7,29,
41,63

Serial input. RXx is a serial data input from a connected communications device. During loopback mode,
the RXx input is disabled from external connection and connected to the TXx output internally.

Receive ready. RXRDY goes low when the receive FIFO is full. It can be used as a single transfer or
multitransfer.

17,19,
51,53

Transmit outputs. TXx is a composite serial data output that is connected to a communications device. TXA,
TXB, TXC, and TXD are set to the marking (high) state as a result of reset.

RXRDY
TXA,TXB
TXC, TXD

Signal and power ground
External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and inform the
CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt to be issued are:
a receiver error, receiver data available or time out (FIFO mode only), transmitter holding register empty,
and an enabled modem status interrupt. The interrupt is disabled when it is serviced or as the result of a
master reset.

~TEXAS

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2-253

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

Terminal Functions (continued)
TERMINAL

NO.

NAME

TXRDY

I/O

DESCRIPTION

Transmit ready. TXRDY goes low when the transmit FIFO is full. It can be used as a single transfer or
multltransfer function.
Power supply

13,30,
47,64

VCC
XTAL1

Crystal input 1 or external clock input. A crystal can be connected to XTAL1 and XTAL2 to utilize the internal
oscillator circuit. An external clock can be connected to drive the internal clock circuits.

XTAL2

Crystal output 2 or buffered clock output (S99 XTAL 1).

absolute maximum ratings over free-air temperature range (unless otherwise noted)t
Supply voltage range, Vcc (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI ................................................... -0.5 V to 7 V
Output voltage range, Va .................................................... -0.5 V to Vee + 3 V
Continuous total power dissipation at (or below) 70°C ...................................... 500 mW
Operating free-air temperature range, TA ............................................ -O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are wHh respect to GND.

recommended operating conditions
Supply voltage, Vee

MIN

NOM

MAX

UNIT

4.75

5.25

V
V
V

Clock high-level input voltage at XTAL1, VIH(CLK)
Clock lOW-level Input voHage at XTAL 1, VIL(CLKI

-0.5

Vee
0.8

High-level input VOltage, VIH

2
-0.5

VCC
0.8

LOW-level input voHage, VIL
Clock frequency, fclock
Operating free-air temperature, TA

~TEXAS

2-254

INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

V
V

MHz

°e

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS1658 - JANUARY 1994 - REVISED MARCH 1996

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

VOH:!:

High-level output voltage

IOH=-1 rnA

VOL:!:

Low-level output voltage

IOL=I.6mA

Ilkg

Input leakage current

Vee = 5.25 V,
VI = 0 to 5.25 V,

IOZ

High-impedance output
current

GND=O,
Vee 5.25 V,
Vo = 0 to 5.25 V,
Chip selected in write mode or chip deselected

Supply current

VCC = 5.25 V,
TA = 25°C,
RX, DSR, DCD, CTS, and Ai at 2 V,
All other inputs at O.B V,
XTAL1 at 4 MHz,
No load on outputs,
Baud rate = 50 kilobits per second

ICC

CiIXTAL1)

Clock input capacitance

Co(XTAL2)

Clock output capacitance

Input capaqitance

Output capacitance

TYpt

MAX

UNIT

2.4

GND=O,
All other terminals floating

0.4

±10

I1A

±20

I1A

rnA

VCC=O,
All other terminals grounded,

VSS=O,
f= 1 MHz,

TA=25°C

t All typical values are at VCC = 5 V, TA = 25°C.
:!: These parameters apply for all outputs except XTAL2.

clock timing requirements over recommended ranges of operating free-air temperature and supply
voltage (see Figure 1)
MIN

MAX

UNIT

twl

Pulse duration, clock high (external clock)

tw2

Pulse duration, clock low (external clock)

tw3

Pulse duration, RESET

1000

read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN

MAX

UNIT

tw4

Pulse duration, lOR low

tsul

Setup time, CSx valid before lOR low (see Note 2)

tsu2

Setup time, A2-AO valid before lOR low (see Note 2)

thl

Hold time, A2-AO valid aiter lOR high (see Note 2)

th2

Hold time, CSx valid aiter lOR high (see Note 2)

Idl

Delay time, tsu2 + tw4 + 1d2 (see Note 3)

140

1d2

Delay time, lOR high to lOR or lOW low

NOTES: 2. The Internal address strobe IS always active.
3. In the FIFO mode, tdl = 425 ns (min) between reads of the receilier FIFO and the status registers (interrupt identification register
and line status register).

~TEXAS .
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2-255

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSI65B-JANUARY 1994- REVISED MARCH 1996

write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN

MAX

UNIT

tW5

Pulse duration, lOW,!.

tsu3

Setup time, CSx valid before lOW,!. (see Note 2)

tsu4

Setup time, A2-AO valid before lOW,!. (see Note 2)

tsu5

Setup time, D7 -DO valid before IOW1'

th3

Hold time, A2-AO valid after IOW1' (see Note 2)

th4

Hold time, CSx valid after IOW1' (see Note 2)

th5

Hold time, D7 -DO valid after IOW1'

td3

Delay time, tsu4 + tW5 + td4

td4

Delay time, IOW1' to lOW or lOR,!.

120

NOTE 2: The mternal address strobe IS always active.

read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage, CL = 100 pF (see Note 4 and Figure 4)
. PARAMETER
ten

Enable time, lOR,!. to D7-DO valid

tdis

Disable time, IOR1' to D7 - DO released

MIN

MAX

UNIT

NOTE 4: VOL and VOH (and the external loading) determine the charge and discharge time.

transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RCLK
cycles

1d5

Delay time, INTx'!' to TXx'!' at start

td6

Delay time, TXx,!. at start to INTx1'

See Note 5

RCLK
cycles

td7

Delay time, lOW high or low (WR THR) to INTx1'

See Note 5

RCLK
cycles

tda

Delay time, TXx,!. at start to TXRDY,!.

CL= 100 pF

RCLK
cycles

tpd1

Propagation delay time, lOW (WR THR)'!' to INTx,!.

CL= 100pF

tpd2

Propagation delay time, lOR (RD IIR)1' to INTx'!'

CL= 100pF

tpd3

Propagation delay time, lOW (WR THR)1' to TXRDY1'

CL= l00pF

NOTE 5:

~TEXAS

INSTRUMENTS
2-256

. .

If the transmitter Interrupt delay IS active, thiS delay IS lengthened by one character time minus the last stop bit time .

, POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSI65B-JANUARY 1994- REVISED MARCH 1996

receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9 through 13)
TEST CONDITIONS

PARAMETER
td9

Delay time, stop bit to INTxI or stop bit to RXRDY! or read RBR to set
interrupt

tpd4

Propagation delay time, Read RBRlLSR to INTx!/LSR interrupt!

lpd5

Propagation delay time, lOR RCLK! to RXRDYI

NOTES:

MIN

See NoteS

MAX

UNIT

RCLK
cycle

CL = 100 pF, See Note 7

See Note 7

S. The receiver data available Indicator, the overrun error Indicator, the tngger level Interrupts, and the active RXRDY indicator are
delayed three RCLK (intemal receiver timing clock) cycles in the FIFO mode (FCRO = 1). After the first byte has been received, status
indicators (PE, FE, BI) are delayed three RCLK cycles. These indicators are updated immediately for any further bytes received after
lOR goes active for a read from the RBR register. There are eight RCLK cycle delays for trigger change level interrupts.
7. RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.

modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 14)
MIN

PARAMETER

MAX

UNIT

tpdS

Propagation delay time, lOW (WR MCR)I to RTSx, DTRxI

tpd7

Propagation delay time, modem input CTSx, DSRx, and DCDx ! I to INTxI

tpd8

Propagation delay time, lOR (RD MSR)I to interrupt!

tpd9

Propagation delay time, Rixi to INTxI

~TEXAS

INSTRUMENTS
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DALLAS, TEXAS 75265

2-257

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

Clock
(XTAL1)

fClock

=16 MHz MAX

(a) CLOCK INPUT VOLTAGE WAVEFORM

RESET~

'/,

L
I

1~4---------------tW3----------------~~
(b) RESET VOLTAGE WAVEFORM

Figure 1. Clock Input and RESET Voltage Waveforms
2.54 V

Device Under Test

•

680g

82 pF
(see Note A)

NOTE A: This includes scope and jig capacitance.

Figure 2. Output Load Circuit

Data Bus

g-Pin 0 Connector

"\;----------11

Address Bus
Control Bus "\;-________-11

g-Pin 0 Connector

TL16C554
Quadruple
ACE

1-------1

Serial
Channel 3
Buffers

g-Pin 0 Connector

1-------1

Serial
Channel 4
Buffers

g-Pin 0 Connector

Figure 3. Basic Test Configuration

~TEXAS

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INSTRUMENTS
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TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
A2, A1, AO =::::>:<_SO_OI<_O_ _ _ _ _ _ _
va_li_d_ _ _ _ _ _ _ _

~th1 ~

I
_----,I~
CSx

...I~'-S-OO-yO--------

: }.SO%

: 1~
... - - t s u 1
I'" I

Valid

---~.I
I

td1

---t-----------.;.I

141"'--- tsu2 -----....:
SO%\

th2

SO%

t~s-OO-Yo-------l.,I) Ii

Active

I
I
!.-tw4 ~ ....- - - - td2

I
I
I
I...

07-00

:
I
len -l:<_SO_"I<_O_ _ _ _ _ _
Va_li_d_ _ _ _ _ _ _ _

-'~'-S-Oo-yO--------

~~~

I
____~I~

i ).SO%
Valid
: ~ tsu3 ---+l~

ISO%

:.--- th4 ---.:

1....--------+1----~3-~~--------~.1
I'"

tsu4

I~:

~SO%

Active

{~S-OO-Yo------'Jj

SO%

~ve

I+-- tws - -..... 1 - - - - - td4 ----+1.1
+11
...

Ill,

SO%\' Active

tsus ---I.1"'4--...~I"'----1....
1-

07-00 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~I(
..

th5

Valid Data

/)-0- - - - - - - - - -

Figure 5. Write Cycle Timing Waveforms

~TEXAS

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2-259

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

SO%~ll
Oala (5-8)
v-vSlop
;'\"",Slart!
.....L'--________
I\..J

TXx

---.: IdS :.-

Parily

INTx ---s-oo/c""'.V 50%
Ipd1

50%" Slart/
(1-2)1''--_...._ _ _ _ _ _ _ _ __

So%I,.--------..~

}SO%

~ Id7 -.I

~ Ipd1

~R~~:' ~SO%

IdS

---.j

~r----------------~i---Ipd2+1

lOR
(RO IIR)

------------------------------------------~~,.S-O.-~---

Figure 6. Transmitter Timing Waveforms
lOW
(WRTHR)

~ B~e#1;(r5-0%--------~)(rJ- - - - - - - - - - - - - - - - - - - - - - - - 1

TXx

-,X

______o_a_la_"'I":_ _
Ipd3

Parily

.11

~50%

Slop
Id8

I..
I

Slart

Jl',.5-0.-~-------------~\''-S_0_%
________
_

TXROY _________
____
FIFO Emply
,

Figure 7. Transmitter Ready Mode 0 Timing Waveforms

,----~.~--------~\(~)---------

lOW
(WATHR)

50%
1

TXx _____o_a_la_ _

~~""-p-a-ri-ly-J)I

Slop

Slart

Ipd3

Slart

-+I....--~.I
~ ~ Id8
SO%)rr------FI-FO-FU-I-I----~)~

Figure 8. Transmitter Ready Mode 1 Timing Waveforms

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
TL16C450 Mode:

~
A.::::::!../ ::nop " - - - - /J

1'\

S I N " Start
Data Bits (S-8)
(receiver input data)
~\)- _ _ _ _ _ _

...Inll.-_....._~)\~~

Sample Clock ~

,____
n
~IIS\-

_ _ _ _- L_ _~_ _ _ _ _ _-+~I

A -_ _

~9~t ~

--J!

INTx _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
(data ready or
RCVR ERR)

50%

SO%
1

i+--tpd4~
1

Active

SO% \

I.-_ _J.

Figure 9. Receiver Timing Waveforms

RXx

~Data Bits (S-8)

Sample
Clock
1

r-I,-I_______.._--L

INTx (trigger
I)
1 . 1 SO%
(FCR6,interrupt)
7 0, 0) _ _ _ _ _ _ _ _ _ _ _ _ _--+-11

~9 --.I
lOR
(RDRBR)

I+1

50%

tpd4 ~

1
I+-

(FIFO at or
above trigger
level)
(FIFO below
trigger level)

SO%~

I
1

Inter~~; _ _ _ _ _ _ _ _ _ _.....;..!___S0-J%l,....---""'\~
I+- tpd4 --+1
lOR
(RDLSR)

SO%~
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms

~TEXAS

INSTRUMENTS
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2·261

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994:'" REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

--------~

RXx

S~~:~:_L__

- L__

~IL--AI___+---L--~I--------.J

I+-

td9 (see Note A)
rl
50%

Ipl

INTx
(time-out or
trigger level) _ _ _ _~-----J
Interrupt
INTx - - - - - ,
Interrupt
"

-+i

50%

Top Byte of FIFO

td9 -1~"--+l.1
----------~I----~

lOR
(RO LSR)

lOR
(RO RBR)

\
50%

)50%

tpd4 ---i'II1"f---~.1

150%
.

(FIFO at or above
trigger level)
I
(FIFO below
" ' - - - - - - - - trigger level)
I+- tpd4

I~----~I----------

Active

II"'5-0.-~-------------------5-0"""\%~.

Active
\.~ _ _.J.
Previous BYTE
Read From FIFO

Active

r--

NOTE A: This is the reading of the last byte in the FIFO.

Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
(I

lOR
(RORBR)

50%\

Active

RXx~
Sample
Clock ________.lL..____....IL.____

--l+--+I

id9
(see Note B)

50%~~

___

~~lr~I--------~-'~50%
tpd5~

NOTES: B. This is the reading of the last byte in the FIFO.
C. If FCRO = 1, then id9 = 3 RCLK cycles. For a time-out interrupt, td9 = 8 RCLK cycles.

Figure 12. Receiver Ready Mode 0 Timing Waveforms

~TEXAS

INSTRUMENTS
2-262

(see Note A)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSl65B - JANUARY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
~(rl----------------~

lOR
(RORBR)

50%\

Active

(see Note A)

SIN~
Stop

(first byte that reaches
the trigger level)

Sample
Clock ________-!'~________
1

--*--+I

td9
(see Note B)

---------i-....I{

50%"''------I,(,'!r-I

50%

tpd5~

NOTES: A. This is the reading of the last byte in the FIFO.
B. If FCRO 1, tdS 3 RCLK cycles. For a trigger change level interrupt, lds

=8 RCLK.

Figure 13. Receiver Ready Mode 1 Timing Waveforms

\.'--_---JI

IOW~

(WR MCR)

\1.....--....11

50%

I.---+j- tpd6

CTSx,

50%

~~~~ _ _ _ _.J;{50%
14
INTx

--------~\IO%
RTSx,OTRx

50%

tpd7

1r----.,)... .

50%

lOR - - - - - - - " " " ' \ .
(RO MSR)

-.I

\..J'

1'"------

}'I..________..,-_________________

--i'I14t------.!~1

---JF

1r-

50_%_ _..J

tpd8

tpd6

SO-%---..\...._ _

I
14--

tpd9 --11~4--+l~1

50%

"-/

Rlx

III

1,...-_ _-

500/01

Figure 14. Modem Control Timing Waveforms

~TEXAS

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2-263

TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLSl65B-JANUARY 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
Three types of information are stored in the intemal registers used in the ACE: control, status, and data.
Mnemonic abbreviations for the registers are shown in Table 1. Table 2 defines the address location of each
register and whether it is read only, write only, or read writable.
Table 1. Internal Register Mnemonic Abbreviations
CONTROL

MNEMONIC

STATUS

MNEMONIC

DATA

MNEMONIC

Line control register

LeR

Line status register

lSR

Receiver buffer register

RBR

FIFO control register

FeR

Modem status register

MSR

Transmitter holding register

THR

Modem control register

MeR

Divisor latch lSB

Dll

Divisor latch MSB

DlM

Interrupt enable register

IER

Table 2. Register Selectiont
DLAB*

A2§

Al§

AO§

0
X
X
X
X
X
X
1

0
1
1
0
0
1
1
0
0

1
0
1
0
1
0
1
0
1

1
X

0
0
1
1
1
1
0
0

READ MODE
Receiver buffer register

WRITE MODE
Transmitter holding register
Interrupt enable register

Interrupt identification register

FIFO control register
Line control register

Modem control register
Line status register
Modem status register
Scratch pad register

Scratchpad register
lSB divisor latch
MSB divisor latch

=Irrelevant, 0 =low level, 1 =high level

t The serial channel is accessed when either eSA or eSD is low.
:): DLAB is the divisor latch access b~ and bit 7 in the leA.
§ A2.-AO are device terminals.
Individual bits within the registers are referred to by the register mnemonic and the bit number in parentheses.
For example, LCR7 refers to line control register bit 7. The transmitter buffer register and receiver buffer register
are data registers that hold from five to eight bits of data. If less than eight data bits are transmitted, data is right
justified to the LSB. Bit 0 of a data word is always the first serial data bit received and transmitted. The ACE data
registers are double buffered (TL16450 mode) or FIFO buffered (FIFO mode) so that read and write operations
can be performed when the ACE is performing the parallel-to-serial or serial-to-parallel conversion.

="TEXAS

INSTRUMENTS
2-264

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TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 1. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS

BIT7

BIT 6

BIT5

BIT4

BIT 3

BIT2

BIT 1

BIT 0

RBR
(read only)

Data Bit 7
(MSB)

Data Bit 6

Data BitS

Data
Bit4

Data Bit 3

DataBit2

Data Bit 1

Data Bit 0
(LSB)

THR
(write only)

Data Bit 7

Data Bit 6

Data BitS

Data
Blt4

Data Bit 3

Data Bit 2

Data Bit 1

Data Bit 0

ADDRESS

DLL

Bit 7

Bit 6

BitS

Bit4

Bit 3

Bit 2

Bit 1

Bit 0

DLM

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bit 10

Bit 9

BitS

IER

(EDSSI)
Enable
modem
status
interrupt

(ERLSI)
Enable
receiver
line status
interrupt

(ETBEI)
Enable
transmitter
holding
register
empty
interrupt

(ERBI)
Enable
received
data
available
interrupt

FCR
(write only)

Receiver
Trigger
(MSB)

Receiver
Trigger
(LSB)

Reserved

DMA
mode
select

Transmit
FIFO reset

Receiver
FIFO reset

FIFO Enable

IIR
(read only)

FIFOs
Enabled:j:

Interrupt
IDBit(3):j:

Interrupt ID
Bit (2)

Interrupt ID
Bit (1)

o II interrupt

LCR

(DLAB)
Divisor
latch
access bit

Set break

Stick parity

(EPS)
Even
parity
select

(PEN)
Parity
enable

(STB)
Number 01
stop bits

(WLSB1)
Word length
select bit 1

(WLSBO)
Word length
select bit 0

MCR

Loop

OUT2
Enable
external
interrupt
(INT)

Reserved

(RTS)
Request to
send

(DTR) Data
terminal
ready

LSR

Error in
receiver
FIFO:j:

(TEMT)
Transmitter
registers
empty

(THRE)
Transmitter
holding
register
empty

(BI)
Break
interrupt

(FE)
Framing
error

(PE)
Parity error

(OE)
Overrun
error

(DR)
Data ready

MSR

(DCD)
Data
carrier
detect

(RI)
Ring
indicator

(DSR)
Data set
ready

(CTS)
Clear to
send

(L1DCD)
Delta
data
carrier
detect

(TERI)
Trailing
edge ring
indicator

(L1DSR)
Delta data
set ready

(L1CTS)
Delta
clear to send

SCR

Bit7

Bit6

BitS

Bit 4

Bit3

Bit 2

Bit 1

BitO

pending

tDLAB 1
:j: These bits are always 0 when FIFOs are disabled.

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TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of
the receiver FIFO, and selects the type of DMA signalling.
•

Bit 0: FCRO enables the transmit and receiver FIFOs. All bytes in both FIFOs can be cleared by clearing
FCRO. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL 16C450
mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCRO.

•

Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the
shift register.

•

Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the
shift register.

•

Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCRO is set.

•

Bits 4 and 5: FCR4 and FCR5 are reserved for future use.

•

Bits 6 and 7: FCR6 and FCR7 sets the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT

RECEIVER FIFO
TRIGGER LEVEL (BYTES)

FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled.
1.

LSRO is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.

IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt
IIR=04.

Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.

IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.

The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.

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PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1.

When the following conditions exist, a FIFO character time-out interrupt occurs:
a.

Minimum of one character in FIFO

Last received serial character is longer than four continuous previous character times ago. (If two stop
bits are programmed, the second one is included in the time delay.)

By using the XTAL 1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.

The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.

A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.

Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCRO = 1, IER = 1).
1.

The transmitter FIFO empty indicators are delayed one character time minus the last stop bit time whenever
the following occurs:
THRE = 1, and there has not been a minimum of two bytes at the same time in transmit FIFO since the last
THRE = 1. The first transmitter interrupt after changing FCRO is immediate, however, assuming it is
enabled.

Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.

FIFO polled mode operation
Clearing IERO, IER1, IER2, IER3, or all to zero with FCRO = 1 puts the ACE into the FIFO polled mode. receiver
and transmitter are controlled separately. Either or both can be in the polled mode.
In the FI FO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.

interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IERO -IER3 of the lEA. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list.

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PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
•

Bit 0: When IERO is set, IERO enables the received data available interrupt and the time-out interrupts in
the FIFO mode.

•

Bit 1: When IER1 is set, the transmitter holding register empty interrupt is enabled.

•

Bit 2: When IER2 is set, the receiver line status interrupt is enabled.

•

Bit 3: When IER3 is set, the modem status interrupt is enabled.

•

Bits 4 -7: IER4 - IER7. These four bits of the IER are cleared.

interrupt identification register (UR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are as follows:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

Information indicating that a prioritized interrupt is pending and the type of interrupt that is stored in the IIR. The
IIR indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.

Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER

INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL

BIT 3

BIT2

BIT 1

First

BITO

INTERRUPT TYPE

INTERRUPT SOURCE

None

Receiver line status

OE, PE, FE, or BI

LSR read

Second

Received data available

Receiver data available or
trigger level reached

RBR read until FIFO
drops below the trigger
level

Second

Character time-out
indicator

No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.

RBR read

Third

THRE

IIR read if THRE is the
interrupt source or THR
write

Fourth

Modem status

CTS, DSR, RI, or DCD

~TEXAS

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PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
•

Bit 0: IIRO indicates whether an interrupt is pending. When IIRO is cleared, an interrupt is pending.

•

Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.

•

Bit 3: IIR3 is always cleared when in the TL 16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.

•

Bits 4 and 5: IIR4 and IIR5 are always cleared.

•

Bits 6 and 7: IIR6 and IIR7 are set when FCRO = 1.

line control register (LCR)
The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described
in the following bulleted list and shown in Figure 15.
•

Bits 0 and 1: LCRO and LCR1 are word length select bits. These bits program the number of bits in each
serial character and is shown in Figure 15.

•

Bit 2: LCR2 is the stop bit select bit. This bit specifies the number of stop bits in each transmitted character.
The receiver always checks for one stop bit.

•

Bit 3: LCR3 is the parity enable bit. When LCR3 is set, a parity bit between the last data word bit and stop
bit is generated and checked.

•

Bit 4: LCR4 is the even parity select bit. When this bit is set and parity is enabled (LCR3 is set), even parity
is selected. When this bit is cleared and parity is enabled, odd parity is selected.

•

Bit 5: LCR5 is the stick parity bit. When parity is enabled (LCR3 is set) and this bit is set, the transmission
and reception of a parity bit is placed in the opposite state from the value of LCR4. This forces parity to a
known state and allows the receiver to check the parity bit in a known state.

•

Bit 6: LCR6 is a break control bit. When this bit is set" the serial outputs TXx are forced to the spacing state
(low). The break control bit acts only on the serial output and does not affect the transmitter logic. If the
following sequence is used, no invalid characters are transmitted because of the break.
Step 1.

•

Load a zero byte in response to the transmitter holding register empty (THRE) status indicator.

Step 2.

Set the break in response to the next THRE status indicator.

Step 3.

Wait for the transmitter to be idle when transmitter empty status signal is set (TEMT = 1); then
clear the break when the normal transmission has to be restored.

Bit 7: LCR7 is the divisor latch access bit (DLAB) bit. This bit must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register, or the interrupt enable register.

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PRINCIPLES OF OPERATION

line control register (LCR) (continued)
LINE CONTROL REGISTER
I

L~R I L~RI L~R L~RI L~R IL~RI L~R I L~R

-""

Word Length
Select

Stop Bit
Select
~

Parity Enable
Even Parity
Select

---+--

Stick Parity

0 =5 Data Bits
1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data bits

o
o

0=1 Stop Bit
1 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected

o =Parity Disabled
1

=Parity Enabled

o = Odd Parity
1

=Even Parity

o = Stick Parity Disabled
1

=Stick Parity Enabled

Break Control

0 = Break Disabled
1 Break Enabled

Divisor Latch
Access Bit

0 = Access Receiver Buffer
1 = Access Divisor Latches

Figure 15. Line Control Register Contents

line status register (LSR)
The LSR is a single register that provides status indicators. The LSR shown in Table 6 is described in the
following bulleted list.
•

•

Bit 1: LSR1 is the overrun error (OE) bit. An overrun error indicates that data in the receiver buffer register
is not read by the CPU before the next character is transferred into the receiver buffer register overwriting
the previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An
overrun error occurs in the FIFO mode after the FIFO is full and the next character is completely received.
The overrun error is detected by the CPU on the first LSR read after it happens. The character in the shift
register is not transferred to the FIFO, but it is overwritten.

•

Bit 2: LSR2 is the parity error (PE) bit. A parity error indicates that the received data character does not
have the correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error
and is cleared when the CPU reads the contents ofthe LSR. In the FIFO mode, the parity error is associated
with a particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.

•

Bit 3: LSR3 is the framing error (FE) bit. A framing error indicates that the received character does not have
a valid stop bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero
bit (spacing level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO
mode, the framing error is associated with a particular character in the FIFO. LSR3 reflects the error when
the character is at the top of the FIFO.

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PRINCIPLES OF OPERATION
line status register (LSR) (continued)
•

Bit 4: LSR4 is the break interrupt (BI) bit. Break interrupt is set when the receiv~d data input is held in the
spacing (low) state for longer than a full word transmission time (start bit + data bits + parity + stop bits).
The BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.

LSR1 - LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register when any of the conditions are detected. This interrupt is enabled by setting IER2
in the interrupt enable register.
•

Bit 5: LSR5 is the transmitter holding register empty (THRE) bit. THRE indicates that the ACE is ready to
accept a new character for transmission. The THRE bit is set when a character is transferred from the
transmitter holding register (THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading
ofthe THR by the CPU. LSR5 is not cleared by a CPU read ofthe LSR. In the FIFO mode, when the transmit
FIFO is empty this bit is set. It is cleared when one byte is written to the transmit FIFO. When the THRE
interrupt is enabled by IER1, THRE causes a priority 3 interrupt in the fiR. If THRE is the interrupt source
indicated in fiR, INTRPT is cleared by a read of the fiR.

•

Bit 6: LSR6 is the transmitter register empty (TEMT) bit. TEMT is set when the THR and the TSR are both
empty. LSR6 is cleared when a character is loaded into THR and remains low until the character is
transferred out of TXx. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the
transmitter FIFO and shift register are empty, this bit is set.

•

Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is cleared in the TL16C450 mode (see FCR bit 0).
In the FIFO mode, it is set when at least one of the following data errors is in the FIFO: parity error, framing
error, or break interrupt indicator. It is cleared when the CPU reads the LSR if there are no subsequent errors
in the FIFO.
NOTE

The LSR may be written. However, this function is intended only for factory test. It should be considered as read
only by applications software.

Table 6. Line Status Register Bits
LSRBITS

Ready

Not ready

LSR1 overrun error (OE)

Error

No error

LSR2 parity error (PE)

Error

No error

LSR3 framing error (FE)

Error

No error

LSR4 break interrupt (BI)

Break

No break

LSR5 transmitter holding register empty (THRE)

Empty

Not empty

LSR6 transmitter register empty (TEMT)

Empty

Not empty

Error in FIFO

No error in FIFO

LSRO data ready (DR)

LSR7 receiver FIFO error

-!11
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PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 16. MCR can be written and
read. The RTS and DTR outputs are directly controlled by their control bits in this register. A high input asserts
a low signal (active) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
•

•

Bit1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel may be input into an inverting line <;Iriver to obtain the proper
polarity input at the modem or data set.

•

Bit 2: MCR2 has no affect on operation

•

Bit 3: When MCR3 is set, the external serial channel interrupt is enabled.

•

Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output TXx is set to the marking (high) state and SIN is disconnected. The output of the TSR is looped
back into the RSR input. The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected. The
modem control outputs (DTR and RTS) are internally connected to the four modem control inputs. The
modem control output terminals are forced to their inactive (high) state on the TL 16C554. In the diagnostic
mode, data transmitted is immediately received. This allows the processor to verify the transmit and receive
data paths of the selected serial channel. Interrupt control is fully operational; however, interrupts are
generated by contrOlling the lower four MCR bits internally. Interrupts are not generated by activity on the
external terminals represented by those four bits.

•

Bit 5 - Bit 7: MCR5, MCR6, and MCR7 are permanently cleared.
MODEM CONTROL REGISTER

Data Terminal
Ready

o" DTR Output Inactive (high)

Request
to Send

o" RTS Output Inactive (high)

Out1 (Internal)

No affect on external operation

Out2 (internal)

o" External lnterrupt Disabled

Loop

0" Loop Disabled
1 " Loop Enabled

1 " DTR Ol,ltput Active (low)
1 " RTS Output Active (low)

1 " External Interrupt Enabled

Bits Are Set to Logic 0

Figure 16. !IIIodem Control Register Contents

~lExAs

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PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines for the modem or peripheral devices. The MSR
allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the ACE
in addition to the current status of four bits of the MSR that indicate whether the modem inputs have changed
since the last reading of the MSR. The delta status bits are set when a control input from the modem changes
states and are cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, and DCD. MSR4 - MSR7 are status indicators of these lines. A status
bit = 1 indicates the input is low. When the status bit is cleared, the input is high. When the modem status interrupt
in the IER is enabled (IIR3 is set), an interrupt is generated whenever MSRO- MSR3 is set. The MSR is a priority
4 interrupt. The contents of the MSR are described in Table 7.
•

Bit 0: MSRO is the delta clear-to-send (L\CTS) bit. DCTS indicates that the CTS input to the serial channel
has changed state since it was last read by the CPU.

•

Bit 1: MSR1 is the delta dataset ready (L\DSR) bit. L\DSR indicates that the DSR input to the serial channel
has changed states since the last time it was read by the CPU.

•

Bit 2: MSR2 is the trailing edge of .ring indicator (TERI) bit. TERI indicates that the Rlx input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-Iow
transitions on RI do not activate TERI.

•

Bit 3: MSR3 is the delta data carrier detect (L\DCD) bit. L\DCD indicates that the DCD input to the serial
channel has changed states since the last time it was read by the CPU.

•

Bit 5: MSR5 is the data set ready DSR bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data from the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4 is set), MSR5 reflects the value of DTR in
the MCR.

•

Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the Rlx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.

•

Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set). MSR7 reflects the value of OUT2
in the MCR.

Reading the MSR clears the delta modem status indicators but has no affect on the other status bits. For LSR
and MSR. the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read lOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode when modem status interrupts are enabled,
CTS, DSR, RI and DCD inputs are ignored; however, a modem status interrupt can still be generated by writing
to MCR3-MCRO. Applications software should not write to the MSR.

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PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Table 7. Modem Status Register Bits
MSRBIT

MNEMONIC

MSRO

ACTS

DESCRIPTION

MSRl

ADSR

DeRa data set ready

MSR2

TERI

Trailing edge of ring indicator

MSR3

ADCD

MSR4

CTS

Clear to send

MSR5

DSR

Data set ready

MSR6

Ring indicator

MSR7

DCD

Delta clear to send

DeRa data carrier detect

Data carrier detect

programming
The serial channel of the ACE is programmed by the control registers LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.

programmable baud rate generator
The ACE serial channel contains a programmable baud rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to (2 16-1). Two 8-bit divisor latch registers store the divisor in a 16-bit binary
format. These divisor latch registers must be loaded during initialization. Upon loading either of the divisor
latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The BRG can
use any of three different popular frequencies to provide standard baud rates. These frequencies are 1.8432
MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are available.
Tables 8, 9, 10, and 11 illustrate the divisors needed to obtain standard rates using these three frequencies. The
output frequency of the baud rate generator is 16x the data rate [divisor # clock + (baud rate x 16)] referred
to in this document as RCLK.

~TEXAS

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PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 8. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE

DIVISOR (N) USED TO

DESIRED

GENERATE 16xCLOCK

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000

2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

0.026
0.058

0.690
-

2.860

Table 9. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400

3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5

0.026
0.034
0.312
-

0.628
1.230
-

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PRINCIPLES OF OPERATION
programmable baud rate generator (continued)
Table 10. Baud Rates Using a 8-MHz Clock

BAUD RATE

DIVISOR (N) USED TO

DESIRED

GENERATE 16xCLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

10000

6667

0.005
0.010
0.Q13

110

4545

134.5

3717

150

333
1667

300
600

883

0.020
0.040

1200

417

0.080

1800

277

0.080

2000

250

2400
3600

208
139

0.160
0.080

4800

104

0.160

7200

0.644

9600

0.180

19200
38400

26
13

0.160
0.160

56000

0.790

128000

2.344

256000
512000

2.344

2.400

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PRINCIPLES OF OPERATION

programmable baud rate generator (continued)
Table 11. Baud Rates Using a 16-MHz Clock
BAUD RATE
DESIRED

DIVISOR (N) USED TO
GENERATE 16x CLOCK

PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL

20000

13334

0.00

110

9090

0.01

134.5

7434

0.01

150

6666

0.01

300

3334

-0.02

600

1666

0.04

1200

834

-0.08

1800

554

0.28

2000

500

0.00

2400

416

0.16

3600

278

-0.08

4800

208

0.16

7200

138

0.64

9600

104

0.16

19200

0.16

38400

0.16

56000

-0.79

128000

-2.34

256000

-2.34

512000

-2.34

1000000

0.00

receiver
Serial asynchronous data is input into the RXx terminal. The ACE continually searches for a high-to-Iow
transition from the idle state. When the transition is detected, a counter is reset and counts the 16x clock to
71/2, which is the center of the start bit. The start bit is valid when the RXx is still low. Verifying the start bits
prevents the receiver from assembling a false data character due to a low going noise spike on the RXx input.
The LCR determines the number of data bits in a character (LCRO, LCR1). When parity is enabled, LCR3 and
the polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received including parity and stop bits, the data received indicator in LSRO is set. The CPU reads the RBR, which
clears LSRO. If the character is not read prior to a new character transfer from the RSR to the RBR, the overrun
error status indicator is set in LSR1. If there is a parity error, the parity error is set in LSR2. If a stop bit is not
detected, a framing error indicator is set in LSR3.
In the FIFO mode operation, the data character and the associated error bits are stored in the receiver FIFO.
If the data into RXx is a symmetrical square wave, the center ofthe data cells occurs within ±3.125% of the actual
center, providing an error margin of 46.875%. The start bit can begin as much as one 16x clock cycle prior to
being detected.

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PRINCIPLES OF OPERATION

reset
After power up, the ACE RESET input should be held high for one microsecond to reset the ACE circuits to an
idle mode until initialization. A high on RESET causes the following:
1.

It initializes the transmitter and receiver internal clock counters

It clears the LSR, except for transmitter register empty (TEMT) and transmit holding register empty (THRE),
which are set. The MCR is also cleared. All of the discrete lines, memory elements, and miscellaneous logic
associated with these register bits are alsD cleared or turned off. The LCR, divisor latches, RBR, and
transmitter buffer register are not affected.

RXRDY operation
In mode 0, RXRDY is asserted (low) when the receive FIFO is not empty; it is released (high) when the FIFO
is empty. In this way, the receiver FIFO is read when RXRDY is asserted (low).
In mode 1, RXRDY is asserted (low) when the receive FIFO has filled to the trigger level or a character time-out
has occurred (four character times with no transmission of characters); it is released (high) when the FIFO is
empty. In this mode, multiple received characters are read by the DMA device, reducing the number of times
it is interrupted.
RXRDY and TXRDY outputs from each of the four internal ACEs of the TL 16C554 are ANDed together
internally. This combined signal is brought out externally to RXRDY and TXRDY.
Following the removal of the reset condition (RESET low), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bits in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the effect of a reset on the ACE is given in Table 12.

Table 12. RESET Affects on Registers and Signals
REGISTER/SIGNAL

RESET CONTROL

RESET STATE

Interrupt enable register

Reset

All bits cleared (0-3 forced and 4-7 permanent)

Interrupt identification register

Reset

Bit 0 is set, bits 1, 2, 3, 6, and 7 are cleared,
Bits 4-5 are permanently cleared
All bits cleared

Line control r~gister

Reset

Modem control register

Reset

All bits cleared (5-7 permanent)

FIFO control register

Reset

All bits cleared

Line status register

Reset

All bits cleared, except bits 5 and 6 are set

Modem status register

Reset

Bits 0-3 cleared, bits 4-7 input signals

TXx

Reset

High

Interrupt (RCVR ERRS)

Read LSRlReset

Low

Interrupt (receiver data ready)

Read RBRIReset

Low

Read IIR1Write THRIReset

Low

Read MSRlReset

Low

RTS

Reset

High

DTR

Reset

High

Interrupt (THRE)
Interrupt (modem status changes)

~TEXAS

INSTRUMENTS
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TL16C554
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS165B - JANUARY 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
seratehpad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to hold data temporarily.

TXRDY operation
In mode 0, TXRDY is asserted (low) when the transmit FIFO is empty; it is released (high) when the FIFO
contains at least one byte. In this way, the FIFO is written with 16 bytes when TXRDY is asserted (low).
In mode 1, TXRDY is asserted (low) when the transmit FIFO is not full; in this mode, the transmit FIFO is written
with another byte when TXRDY is asserted (low).

Vec

Driver

lCl
T
-=-

Crystal

1---+----___.-XTAL2

Oscillator Clock
to Baud
Generator Logic

C::J
-

Optional
Driver
Optional
Clock
Output

XTAL1

External
Clock

U~
RX2

lC2
T

-=-

XTAL2

Oscillator Clock
to Baud
Generator Logic

TYPICAL CRYSTAL OSCILLATOR NETWORK
CRYSTAL

RX2

3.1 MHz

1 MQ

1.5 kQ

10-30 pF

40-60 pF

1.8 MHz

1 MQ

1.5 kQ

10-30 pF

40-60 pF

Figure 17. Typical Clock Circuits

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-279

2-280

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

• Pin-to-Pin Compatible With the Existing
TL 16C550B/C
• Programmable 16- or 64-Byte FIFOs to
Reduce CPU Interrupts
• Programmable Auto-RTS and Auto-CTS
• In Auto-CTS Mode, CTS Controls
Transmitter
• In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
• Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
• Capable of Running With All Existing
TL 16C450 Software
• After Reset, All Registers Are Identical to
the TL 16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
• In the TL 16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 16 -1) and Generates an Internal 16 x
Clock
• Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream

• 5-V and 3-V Operation
• Register Selectable Sleep Mode and
Low-Power Mode
• Independent Receiver Clock Input
• Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
• Fully Programmable Serial Interface
Characteristics:
- 5-,6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity Bit Generation
and Detection
- 1-,1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1 Mbits Per
Second)
• False Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output CMOS Drive Capabilities for
Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
- Loopback Controls for Communications
Link Fault Isolation
- Break, Parity, Overrun, Framing Error
Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Available in 44-Pin PLCC and 64-Pin SQFP

description
The TL 16C750 is a functional upgrade of the TL 16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL 16C450. Functionally equivalent to the TL 16C450 on power up
(characterorTL 16C450 mode), the TL 16C750, like the TL 16C550C, can be placed in an alternate mode (FIFO
mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.
The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte
forthe receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode.
In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload
and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS
input signals (see Figure 1).
The TL 16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The
ACE includes complete modem control capability and a processor interrupt system that can be tailored to
minimize software management of the communications link.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does nol necessarily include
testing of all parameters.

~TEXAS

INSTRUMENTS
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2-281

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

description (continued)
The TL 16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by
divisors from 1 to (2 16 -1) and producing a 16x reference clock for the internal transmitter logic. Provisions are
also included to use this 16x clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate
(16-MHz input clock) so a bit time is 1 ~s and a typical character time is 10 ~s (start bit,8 data bits, stop bit).
Two of the TL 16C450 terminal functions have been changed to TXROY and RXROY, which provide signaling
to a direct memory access (OMA) controller.
FN PACKAGE
(TOP VIEW)

o I'Tlen
.... '" N ~ 0 0 010 en Joooooz>o:ooo
05
06
07
RCLK
SIN
NC
SOUT
CSO
CS1
CS2
BAUOOUT

6 5 4 3 214443424140
7
39
8
38
37
9
10
36
11
35
12
34
13
33
32
14
31
15
16
30
17
29
18192021 222324 25 26 2728

oun
OTR
RTS
OUT2
NC
INTRPT
RXROY
AO
A1
A2

PM PACKAGE
(TOP VIEW)
J-

::J

o
o

IN
... «>LOO
aJzoozoenzzeno:zoooz

J~
~
o::J
....J
«oenenoenooo~oo

::J

64 63 62 61
10

60 59 58 57 56 55 54 53 52 51 50 49

~
Q
46
45
44

12
13
14
15
16
17 1819 20 21 22 23 24 25 26 27 28 29 3031 32

NC - No internal connection

~TEXAS

INSTRUMENTS
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03
02

40
10

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64·BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

functional block diagram
r--

S
e
I
e
Internal ~
..... c
Data Bus
t
9-2

Data
Bus
Buffer

D(7-0)

Receiver
Buffer
Register

Line
Control
Register

Receiver
FIFO

Receiver
Shift
Register

~
Receiver
Timing and
Control

f---+-

A 1~

Divisor
Latch (LS)

A2~

Divisor
Latch (MS)

CSO~

Baud
Generator

I
~

CS2~

Line
Status
Register

ADS.~

Select
and
Control
Logic

WR 2~

~
~

XOUT.~

vss

}p-,

-S
e
I
e
c
t

--=---+--

Supply

Transmitter
Shift
Register

Modem
Control
Logic

40
37
41
42

38
Interrupt
Enable
Register

Interrupt
Identification
Register
FIFO
Control
. Register

Interrupt
Control
Logic

SOUT

rr-

44
-=--.22

L.-

I----

Autoflo w
Control
Enable
(AFE)

Transmitter
Timing and
Control

Modem
Status
Register

RXRDY.~

VCC

Modem
Control
Register

TXRDY.~
XIN

I Transmitter ~
I FIFO
Transmitter
Holding
Register

WR 1~
DDIS

17 BA UDOUT

cs 1~

RCLK

r+-

A O~

AD1~
RD 2~

SIN

CTS
DTR
DSR
DCD

Ai
OUT1

OUT2
33 INTRPT

NOTE A: Terminal numbers shown are for the FN package.

~TEXAS

INSTRUMENTS
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2-283

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64·BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191B-JANUARY 1995 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NO.
PM

I/O

DESCRIPTION

AO
A1
A2

31
30
29

20
18
17

Register select. AO-A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses and ADS signal description.

ADS

Address strobe. When ADS is active (low), the register select signals (AO, A 1, and A2) and chip select signals
(CSO, CS1, CS2) drive the internal select logic direCtly; when ADS is high, the register select and chip select
signals are held at the logic levels they were in when the low-to-high transition of ADS occurred.

BAUDOUT

Baud out. BAUDOUT is a 16 x clock signal forthe transmitter section of the ACE. The clock rate is established
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT can also be used for the receiver section by tying this output to RCLK.

CSO
CS1
CS2

14
15
16

59
61
62

Chip select. When CSO and CS1 are high and CS2 is low, the ACE is selected. When any of these inputs
are inactive, the ACE remains inactive. Refer to the ADS signal description.

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the
modem status register. Bit 0 (L\.CTS) of the modem status register indicates that CTS has changed states
since the last read from the modem status register. When the modem status interrupt is enabled, CTS
changes states, and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.

2
3
4
5
6
7

I/O

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU. As inputs, they use fail safe CMOS compatible input buffers.

NAME

DO
D1
D2
D3
D4
D5
D6
D7

NO.

42
43
45
46
48
50
51
52

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of
the modern status register. Bit 3 (L\.DCD) of the modem status register indicates that DCD has changed states
since the last read from the modern status register. When the modem status interrupt is enabled and DCD
changes state, an interrupt is generated.

DDIS

Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an
external transceiver.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit5 (DSR) of the
modem status register. Bit 1 (L\.DSR) of the modem status register indicates DSR has changed states since
the last read from the modem status register. When the modem status interrupt is enabled and the DSR
changes states, an interrupt is generated.

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to one.
DTR is placed in the inactive condition either as a result of a master reset, during loop mode operation, or
clearing the DTR bit.

INTRPT

Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed
out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT
is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.

Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(refer to Table 2).

OUT1
OUT2

38
35

30
25

Outputs 1 and 2. These are user-designated output terminals that are set to their active (low) level by setting
their respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and bUT2 are set to their
inactive (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.

RCLK

Receiver clock. RCLK is the 16x baud rate clock for the receiver section of the ACE.

~TEXAS

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191B-JANUARY 1995 - REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NO.
FN

NO.
PM

DESCRIPTION

RD1
RD2

24
25

9
10

Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is required
for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied
low or RD1 tied high).

Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem
status register. Bit 2 (TERI) of the modem status register indicates that Ai has transitioned from a low to a high
level since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS
is set to its active level by setting the RTS MCR bit and is set to its inactive (high) level either as a result of a
master reset, during loop mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS
is set to its inactive level by the receiver threshold control logic.

RXRDY

Receiver ready. Receiver direct memory access (DMA) Signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected through the FIFO control register bit
3 (FCR3). When operating in the TL 16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transfer DMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA
in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0
(FCRO 0 or FCRO 1, FCR3 0), when there is at least one character in the receiver FIFO or receiver holding
register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or
holding register, RXRDY goes inactive (high). In DMA mode 1 (FCRO 1, FCR3 1), when the trigger level
or the timeout has been reached, RXRDY goes active (low); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (high).

NAME

SIN

SOUT

Composite serial data output to a connected communication device. SOUT is set to the marking (high) level
as a result of master reset.

Serial data. SIN is the input from a connected communications device.

TXRDY

Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected through FCR3. When operating in the TL 16C450 mode,
only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU
bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
transmit FIFO has been filled.

VCC

VSS

WR1
WR2

20
21

4
6

XIN
XOUT

18
19

1
2

110

5-V supply voltage
Supply common
Write inputs. When either input is active (low or high respectively) and while the ACE is selected, the CPU is
allowed to write control words or data into a selected ACE register. Only one of these inputs is required to
transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or
WR1 tied high).
External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).

detailed description
autoflow control

Auto-flow control is composed of auto-CTS and auto-RTS. With auto-CTS, CTS must be active before the
transmit FIFO can emit data (see Figure 1). With auto-RTS, RTS becomes active when the receiver is empty
or the threshold has not been reached. When RTS is connected to CTS, data transmission does not occur
unless the receive FIFO has empty space. Thus, overrun errors are eliminated when ACE1 and ACE2 are
TLC16C750s with enabled autoflow control. If not, overrun errors occur if the transmit data rate exceeds the
receive FIFO read latency.

~TEXAS

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191 B-JANUARY 1995- REVISED MARCH 1996

autoflow control (continued)
ACE1

SOUT

SIN

07-00 -J-<.--tH

07-00
SOUT

SIN

Figure 1. Autoflow Control (auto-RTS and auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1,4, 8, or 14 in 16-byte mode or 1, 16, 32, or 56 in 64-byte mode, RTS is deasserted. The sending ACE may
send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register. The
reassertion signals the sending ACE to continue transmitting data.

auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and does not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error can result.

enabling auto-RTS and auto-CTS
The auto-RTS and auto-CTS modes of operation are activated by setting bit 5 of the modem control register
(MCR) to 1 (see Figure 2).
SOUT \

Start 1 Bits 0-71 Stop

~ Start

I. .

--~\ Start

B-i-ts-0-_-7TI-St-o-p------'l''''r,

--------------------~/

1 Bits 0-71 Stop

NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but
it does not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.

Figure 2. CTS Functional Timing

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191B-JANUARY 1995- REVISED MARCH 1996

enabling auto-RTS and auto-CTS (continued)
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or56 bytes
for 64-byte mode (see Figure 3).
','1-,- - - - - - - \ Start

RTS

Byte

Stop

-------'

(RDRBR)---------------------~

NOTES: A. N = receiver FIFO trigger level
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in auto·RTS.

Figure 3. RTS Functional Timing, Receiver FIFO Trigger Level

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 6 V
Input voltage range, VI: Standard ............................................ -0.5 V to Vee + 0.5 V
Fail safe ...................................... . . . . . . . . . . .. -0.5 V to 6.5 V
Output voltage range, VO: Standard .......................................... -0.5 V to Vee + 0.5 V
Fail safe ................................................ -0.5 V to 6.5 V
Input clamp current, 11K (VI < 0 or VI > Vee) (see Note 1) ................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) (see Note 2) ............................... ±20 mA
e
Operating free-air temperature range, TA .............................................. oDe to 70 D
Storage temperature range, Tstg .................................................. -65 D to 150 D

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

recommended operating conditions
low voltage (3.3 V nominal)

MIN

NOM

MAX

Supply voltage, Vee

3.3

3.6

Input voltage, VI

Vee

High-level input voltage, VIH (see Note 3)

0.7 Vee

low-level input voltage, Vil (see Note 3)

0.3 Vee

Output voltage, Vo (see Note 4)

UNIT

Vee

V
V

High-level output current, IOH (all outputs)

1.8

low-level output current, IOl (all outputs)

3.2

pF
°e

Input capacitance, ci
Operating free-air temperature, TA

Junction temperature range, TJ (see Note 5)

115

°e

MHz

Oscillator/clock speed

NOTES: 3. Meets TIL levels, VIHmin = 2 V and Vilmax = 0.8 V on nonhysteresis inputs
4. Applies for external output buffers
5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150o e. The customer is
responsible for verifying junction temperature.

standard voltage (5 V nominal)
Supply voltage, Vee
Input voltage, VI

MIN

NOM

MAX

UNIT

4.75

5.25

Vee

High-level input voltage, VIH

0.7 Vee

lOW-level input voltage, Vil

0.2 Vee

Output voltage, Vo (see Note 4)

Vee

V
V

High-level output current, IOH (all outputs)

lOW-level output current, IOl (all outputs)

Input capacitance, ci

pF
°e

Operating free-air temperature, TA

Junction temperature range, TJ (see Note 5)

115

°e

MHz

Oscillator/clock speed
NOTES:

4. Applies for external output buffers
5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150o e. The customer is
responsible for verifying junction temperature.

~TEXAS

INSTRUMENTS
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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low voltage (3.3 V nominal)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage t

10H =-1.8mA

VOL

Low-level output voltage t

IOL=3.2 mA

10Z

High-impedance 3-state output current (see Note 6)

VI = Vee or GND

IlL

Low-level input current (see Note 7)

VI =GND

IIH

High-level input current (see Note 8)

VI=Vee

MIN

MAX

UNIT

Vee- 0.55
0.5

±10

-1

t For all outputs except XOUT
NOTES:

6. The 3-state or open-drain output must be in the high-impedance state.
7. Specifications only apply with pullup termination turned off.
8. Specifications only apply with pulldown termination turned off.

standard voltage (5 V nominal)
TEST CONDITIONS

PARAMETER

VOH

High-level output voltage t

10H =-4 mA

VOL

LOW-level output voltaget

IOL=4 mA

10Z

High-impedance 3-state output current (see Note 6)

VI = Vee or GND

IlL

Low-level input current (see Note 7)

IIH

High-level input current (see Note 8)

MIN

MAX

UNIT
V

Vee- O.B
0.5

±10

VI=GND

-1

VI = Vee

t For all outputs except XOUT
NOTES:

6. The 3-state or open-drain output must be in the high-impedance state.
7. Specifications only apply with pull up termination turned off.
8. Specifications only apply with pulldown termination turned off.

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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

tcR

Cycle time, read (tw7 + td8 + td9)

tcw

Cycle time, write (tw6 + td5 + td6)

twl

Pulse duration, clock (XIN) high

tXH

tw2

Pulse duration, clock (XIN) low

tw5

Pulse duration, ADS low

tW6

Pulse duration, write strobe

tw7
tw8
tsul

Setup time, address valid before ADSt

tAS

tsu2

Setup time, CS valid before ADSt

tcs

tsu3

Setup time, data valid before WRI J, or WR2t

tDS

tsu4t

Setup time, CTSt before midpoint of stop bit

thl

Hold time, address low after ADSt

f = 16 MHz maximum

tXL

f = 16 MHz maximum

tADS

5,6

twR

Pulse duration, read strobe

tRD

Pulse duration, MR

tMR

lis

5,6

th2

Hold time, CS valid after ADSt

th3

Hold time, CS valid after WRI tor WR2J,

th4t

Hold time, address valid after WRI tor WR2J,

th5
th6
th7t

tAH

5,6

ns
10

ns
ns

tCH

5,6

twcs

tWA

Hold time, data valid after WRI t or WR2J,

tDH

Hold time, CS valid after RDI tor RD2J,

tRCS

Hold time, address valid after RDI tor RD2J,

tRA

ld4t

Delay time, CS valid before WRI J, or WR2t

tcsw

td5

Delay time, address valid before WRI J, or WR2t

tAW

td6t

Delay time, write cycle, WR1 tor WR2J, to ADSJ,

twc

td7t

Delay time, CS valid to RDI J, or RD2t

tCSR

tds t

Delay time, address valid to RDI J, or RD2t

tAR

td9

Delay time, read cycle, RDI t or RD2J, to ADSJ,

tRC

tdl0

Delay time, RD1 J, or RD2t to data valid

tRVD

CL =75 pF

tdl1

Delay time, RDI tor RD2J, to floating data

tHZ

CL = 75 pF

t Only applies when ADS is low

system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 9)
PARAMETER
tdis(R)

TEST CONDITIONS

Disable time, RDI J, tor RD2t J, to DDISt J,

CL = 75 pF

NOTE 9: Charge and discharge times are determined by VOL, VOH, and external loading.

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL =75 pF
PARAMETER

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

tw3

Pulse duration, BAUDOUT low

tLW

f = 16 MHz, CLK+ 2

tw4

Pulse duration, BAUDOUT high

tHW

f= 16 MHz, CLK+2

tdl

Delay time, XINt to BAUDOUTt

tBLD

td2

Delay time, XINt J, to BAUDOUT J,

tBHD

'!/} TEXAS
2-290

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MAX

UNIT
ns
ns

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191B-JANUARY 1995 - REVISED MARCH 1996

commercial maximum switching characteristics,
PARAMETER
tpLH

FROM
(INPUT)

TO
(OUTPUT)

XIN

Vee =4.75 V, TJ =115°C

INTRINSIC
DELAY
(ns)

DELTA
DELAY
(ns/pF)

CL=15pF

CL=50pF

CL = 85 pF

-0.92

0.571

7.65

27.66

47.66

56.23

-0.79

0.312

3.89

14.83

25.76

30.45

tpHL

DELAY (ns)
CL=100pF

Output rise time, XO

10.86

40.42

69.98

82.65

Output fall time, XO

5.47

20.90

36.34

42.95

commercial maximum switching characteristics,
PARAMETER
tpLH

FROM
(INPUT)

TO
(OUTPUT)

XIN

Vee = 3 V, TJ = 115°C

INTRINSIC
DELAY
(ns)

DELTA
DELAY
(nslpF)

CL=15pF

CL=50 pF

CL=85pF

CL = 100 pF

-4.69

1.017

10.57

46.16

81.75

97.00

-3.05

0.442

3.58

19.04

34.51

41.13

tpHL

DELAY (ns)

Output rise time, XO

14.39

64.87

115.35

136.98

Output fall time, XO

5.06

26.53

48.01

57.21

receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 10)
PARAMETER

ALT. SYMBOL

FIGURE

td12

Delay time, RCLK to sample clock

tSCD

td13

Delay time, stop to set receiver error interrupt or read RBR to lSI interrupt or stop to
RXRDY-l-

tSINT

7,8,9,
10,11

RCLK
cycle

td14

Delay time, read RBR/LSR low to reset
interrupt low

tRINT

7,8,9,
10,11

..
read cycle (RC) = 425 ns (minimum)

NOTE 10: In the FIFO mode, the
identification register or line status register).

TEST CONDITIONS

MIN

MAX

120

Cl = 75 pF

UNIT

between reads of the receive FIFO and the status registers (Interrupt

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
PARAMETERt

ALT. SYMBOL

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

td15

Delay time, INTRPT to transmit start

IIRS

baudout
cycles

td16

Delay time, start to interrupt

ISTI

baudout
cycles

td17

Delay time, WR THR to reset interrupt

tHR

td18

Delay time, initial write to interrupt (THRE)

td19

Delay time, read IIR to reset interrupt (THRE)

td20

Delay time, write to TXRDY inactive

td21

Delay time, start to TXRDY active

CL= 75 pF
16

baudout
cycles
ns

tSI

tlR

CL= 75 pF

tWXI

13,14

Cl = 75 pF

tSXA

13, 14

..
t THRE = transmitter holding register empty, IIR = Interrupt Identification
register.

CL = 75 pF

ns
baudout
cycles

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-291

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL 75 pF

ALT. SYMBOL

FIGURE

tMDO

td23

Delay time. modem interrupt to set interrupt

tSIM

td24

Delay time, RD MSR to reset interrupt

tRIM

PARAMETER
td22

Delay time. WR MCR to output

MIN

MAX

UNIT

td25

Delay time, CTS low to SOUT J,

baudout
cycles

td26

Delay time, receiver threshold byte to RTSt

baudout
cycles

td27

Delay time, read of last byte in receive FIFO to RTSJ,

baud out
cycles

PARAMETER MEASUREMENT INFORMATION

I••_ _-,--_ _ _ _ _ _ N _ _ _ _ _ _ _ _ _ _ _...:

tWl~M

tw2

XIN

BAUDOUT
(1/1)

BAUDOUT
(1/2)

tdl

.: I.

I
~tw3 ---+1

1------l14~,

~tW4-.j

BAUDOUT
(1/3)

BAUDOUT
(lIN)
(N)3)

~I~~__________

,.....-,

----'I'/T---J- - - - ' 1 - - - -

I+- 2 XIN Cycles -+I
1
1"11.1---- (N-2) XIN Cycles ------..1:

Figure 4. Baud Generator Timing Waveforms

~TEXAS

INSTRUMENTS
2-292

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191B- JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

104
1
1

1 IwS
1
50%

50%

ADS

1
1

~lsu1~
~

AO-A2
_ _...I

'------.r
~ Isu2 ---'1
1
1
---'1

I
CSO, CS1, CS2

----'~-O"A~"

th2

)I( "',,<0'

V..

i+-

S_O"AT"";"_ _...,.....-_ _

Ih3~

I+-tW6~

14-- Id4 --+1
~ IdS --+I

¥. .

WRf, WR2 _ _ _ _ _ _S_O°.J'

tsu3

AoUw

104

1"- th4t ~

1+---ld6 ~

*=s=oo=yo==============
.1
104

Ih5

07-00 - - - - - - - - - - ( ( Valid Oala ) " ' " - - - - - - -

Applicable only when ADS is low

Figure 5. Write Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·293

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191B-JANUARY 1995- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

50%

~tsu1~

AO-A2

Valid

)i(

50% Validt 50%)(

I
1

1 ........-...,.---

4---~.1 tsu2

-.:

~ th2

eso, eS1, eS2

th6

1
1

~ td7 t

-*1

--l4---+I

~ td9--+1

---------~I

)I(

50%

I~-------

t1
-----1--0.1\l
tdis(R)

:.---+
1r----tdis(R)

' \50%

50%

td10~

I..

---------((

td11

Y,...----1

07-00

1
1

Ir--------

50%)1( Active

Valid Data

t Applicable only when ADS is low
Figure 6. Read Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
2-294

_ __

1..- th7t

1'--1dst ~

OOIS

-JI~~_~

I4-tW7~

---------~I
R01, R02

1
r-~-~---

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
RCLK

-fl,-------,n

----.-11n~

~--""'(/r-I

td12

hL-_________

~14-------8 Clocks - - - - - - - - - . . 1
Sample Clock

TL16C450 Mode:

SIN " \ Start /

Sample Clock

Data

~~~s

5-8

Parity

\..J

Stop

-----L--~--~)(r)--~L-.--~------~----~I---------I

INTRPT

/50%

50% \..

•

---------------------------------~I I
td13

---+1

14I

td14

INTRPT
~
(receiver error) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
50--'%

-f4-14--.t~
I

} ....50_'*~011--____

V::::v-

RD1, RD2
:
O% ~
(read RBR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _r5_

RD1,RD2
(read LSR) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
50_'*_0~i_I------td14

---+1

I+-

Figure 7. Receiver TIming Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-295

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

~(I

Data~its

SIN \

5-8

)

Sample Clock

( _ _ _ _ _.....,.....
L

Trigger L e v e l ) '
INTRPT _ _ _ _ _ _ _ _ _ _ _ _ _ _ 1
50%
(FCR6, 7 = 0, 0)
_

td13
(see Note A)
Line Status
INTRPT
(LSI)

RD1
(RD LSR)
RD1

50%

l.-

-II

td14

50%

-------------------~.

50%

(FIFO at or above
trigger level)
(FIFO below
trigger level)

l\ I
I ~.~I~-------

td14~

-------------~'\ A~iveJtr---TI------

I
I

" ' - - . / 50%

----------------------\::/A~ive

50%

(RD RBR)
NOTE A: For a time·out interrupt, td13 = 9 RCLKs.

Figure 8. Receive FIFO First Byte (Sets DR Bit) Waveforms

SIN

-----~

Sample Clock
1

Time-Out or
Trigger Level
INTRPT

~
50%
..

td13
(see Note A)
Line Status
INTRPT (LSI)

()

(FIFO at or above

__ _ _ _ _ _ _""'1 1

' - 50%

td14

trigger level)
(FIFO below
trigger level)

-+loII~-~.1

- - - - - - - - ' \ 50% - ' Top Byte of FIFO \ . 5~%
---------~r--------I~·+:----------td13

lol

RD1, RD2
(RD LSR)

----r-'..........JX

RD1, RD2
(RD RBR)

_ _ _.....

td14

-----1++1

*,---~o%-,-:_ _

Ir-----------~Ir----

~r-A-ct-iv-e"" 50%

50%)1(

A~ive ~

Previous Byte
Read From FIFO
NOTE A: For a time-out interrupt, td13

=9 RCLKs.

Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms

~TEXAS

INSTRUMENTS
2-296

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B- JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

I~('----50-"""".).

RD
(RDRBR)

I
I
I
I

SIN~
(first byte)

-.J

Stop ' - - - -

RXRDY

See Note A

I
I
I
I

Sample Clock
td13
(see Note B)

Amlve

I
1_ _

td14 --;.--..:

50% \ ' -_ _ _ _-II.'II.. _ _ _ _ _J

50- % - -

NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, td13 = 9 RCLKs.

Figure 10. Receiver Read,Y (RXRDY) Waveforms, FCRO = 0 or FCRO = 1 and FCR3 = 0 (Mode 0)

RD
(RDRBR)
SIN
(first byte that reaches
the trigger level)
Sample Clock

50% \ . Active

td13 ~I
(see Note B)
I
I
RXRDY

50%\

I See Note A
I
I
I
I
I
I
I
td14~
/50%

NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, td13 = 9 RCLKs.

Figure 11. Receiver Ready (RXRDY) Waveforms, FCRO

=1 and FCR3 =1 (Mode 1)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-297

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTO FLOW CONTROL
SLLS191B -JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
-----..

Slart

) . 50%

SOUT

,..---1,'(

Dal~; Bils

Parity

'\.- _~~~rt /
~

Slop

Id15 ~-~.I

td17

---.I

14-

WRTHR

1,-----,

50%
____________________________50%
-J

__JI

INTRPT
(THRE)

Id16

~ld181
1

~ !+- Id17

5~50%

MI..------------------r:-Id19 -----.:
1

RDIIR

-------------------------------------~
Figure 12. Transmitter Timing Waveforms

WR
(WRTHR)

Byte #1

t,..5-00-Yo------~!I-('- - - - - - 1

X....

SOUT

______
Da_la
_ _ _.,.I--'
1

td20

_p_ar_ily_

v-:::-\ __Slart
1 Slop ~
1

-----'1

Id21

._-------""'\

Figure 13. Transmitter Ready (TXRDV) Waveforms, FCRO

WR
(WRTHR)

Byte #16

' \ 50%

_ _ _ _ _ _ _ _-J150%

=0 or FCRO =1 and FCR3 = 0 (Mode 0)

,..--------1!I-('- - - - - - - - - 50%

_______________--..1
SOUT

_ _ _ _ _D_a_ta_ _ _ _ _

Id20

~ ~;~rt

Parily

-*1 1..-

SlOp

Id21

~
~

-I'"""'":

I ....--_ _ _ _ _ _..,. :

50%

FIFO Full

....5_00_Yo_ __

Figure 14. Transmitter Ready (TXRDV) Waveforms, FCRO = 1 and FCR3 = 1 (Mode 1)

~TEXAS

INSTRUMENTS
2-298

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64·BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191 B - JANUARY 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
WR
(WR MCR)

SO%

td22

---i4--~.1

RTS, DTR, - - - - - - - " " ' \ L S o %
OUT1,OUT2
'\

\ . SO%
td23

--J.-.j

}'--_..J{

(~~~~~~ ________--Il'"s-oo-vo---so-o;,""'o

td24~
RD2
_________
(RD MSR)

50%

~ td23

50%\

\~_ _ _ _ _ _~y~50-%------Figure 15. Modem Control Timing Waveforms

CTS

~O%

50%1

I ~-----------------------------------------~
~td25

SOUT

1_----J!

50%\..........

\ /

r)~'--'-I_ ___..J/

SU 4

i
I
I

Midpoint of Stop Bit

Figure 16. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms

SIN~

Midpoint of Stop Bit

/
/(
'--.J..._ _ _ _- - I
~ td26

IIIUOI~I>_I>IIIII~IIII

EXTEND
VTEST
SSAB
GND
ARBCLKI
GND
ARBCLKO
ARBPGMO
ARBPGM1

75
74

'; Vee) (see Note 1) ................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee) (see Note 2) ............................... ±20 mA
Operating free-air operating temperature range, TA ...................................... O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This applies for external input and bidirectional buffers. VI > Vee does not apply to fail safe terminals.
2. This applies for external output and bidirectional buffers. Vo > Vee does not apply to fail safe terminals.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-327

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLSI72B- MAY 1994 - REVISED MARCH 1996

recommended operating conditions
low voltage (3.3 V nominal)
MIN

NOM

MAX

Supply voltage, VCC

3.3

3.6

Input voltage, VI

High-level input voltage (CMOS), VIH (see Note 3)

VCC

low-level input voltage (CMOS), Vil (see Note 3)
High-level output current, IOH
low-level output current, IOl

V
V
V

0.7VCC

Output voltage, Vo (see Note 4)

UNIT

0
All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5)

0.3VCC

VCC
1.8

All outputs except RST

3.2

RST

6.4

Input transition time, tt

Operating free-air temperature range, TA

°C

115

°C

Junction temperature range, TJ (see Note 6)
NOTES:

3.
4.
5.
6.

Meets TTL levels, VIHmln 2 V and Vilmax 0.8 V on non hysteresIs Inputs.
Applies for external output buffers.
RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply.
These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.

standard voltage (5 V nominal)
I

Supply voltage, VCC
Input voltage, VI

MIN

NOM

MAX

UNIT

4.75

5.25

High-level input voltage (CMOS), VIH

VCC

lOW-level input voltage (CMOS), Vil
Output voltage,

0.2VCC

Vo (see Note 4)

High-level output current, IOH
lOW-level output current, IOl

V
V

O.7VCC
0

VCC
4

All outputs except RST, STSCHG, OUT1, OUT2 (see Note 5)
All outputs except RST

RST

V
V
mA
mA

Input transition time, tt

Operating free-air temperature range, TA

°C

Junction temperature range, TJ (see Note 6)

115

°C

NOTES:

4. Applies for external output buffers.
5. RST, STSCHG, OUT1, and OUT2 are open-drain outputs, so IOH does not apply.
6. These junction temperatures reflect simulation conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.

~TEXAS

INSTRUMENTS

2-328

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994- REVISED MARCH 1996

electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted)
.
low voltage (3.3 V nominal)
TEST CONDITIONS

PARAMETER

= rated
10l = rated

VOH

High·level output voltage

VOL

low-level output voltage

VIT+

Positive-going input threshold voltage (see Note 7)

VIT-

Negative-going input threshold voltage (see Note 7)

Vhvs

Hysteresis (VIT + - VIT _) (see Note 7)

loz

3-state-output high-impedance current (see Note 8)

III

low-level input current (see Note 9)

IIH

High-level input current (see Note 10)

NOTES:

7.
8.
9.
10.

MAX

MIN

0.5
0.7 Vee

V
V
V

0.3 Vee
0.1 Vee

UNIT

Vee- 0.55

10H

0.3 Vee

=Vee or GND .
VI = GND
VI =Vee
VI

±10

-1

Applies for external mput and bidirectional buffers with hysteresIs.
The 3-state or open-drain output must be in the high-impedance state.
Specifications only apply with pullup terminator turned off.
Specifications only apply with pulldown terminator turned off.

standard voltage (5 V nominal)
TEST CONDITIONS

PARAMETER

= rated
10l = rated

MIN

VOH

High-l~lVel

VOL

low-level output voltage

VIT+

Positive-going input threshold voltage (see Note 7)

VIT-

Negative-going input threshold voltage (see Note 7)

0.2 Vee

Vhvs

Hysteresis (VIT + - VIT _) (see Note 7)

0.1 Vee

10Z

3-state-output high-impedance current (see Note 8)

III

low-level input current (see Note 9)

IIH

High-level input current (see Note 10)

NOTES:

7.
8.
9.
10.

output voltage

MAX

UNIT

Vee- 0.8

10H

0.5
0.7 Vee

V
V
V

0.3 Vee

=Vee or GND

±10

VI= GND

-1

=Vee

Applies for external Input and bidirectional buffers with hysteresIs.
The 3-state or open-drain output must be in the high-impedance state.
Specifications only apply with pullup terminator turned off.
Specifications only apply with pulldown terminator turned off.

XIN timing requirements over recommended operating free-air temperature range (see Figure 1)
TEST CONDITIONS

Input frequency

tc1

Cycle time, XIN

tw1

Pulse duration, XIN clock high

tw2

Pulse duration, XIN clock low

MIN

MAX

Vee=3.3V

Vee=5V

Vee=3.3V

Vee=5V

16.7

Vee=3.3V

Vee=5V

Vee =3.3V

Vee=5V

UNIT

MHz

ns
ns

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-329

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B - MAY 1994 - REVISED MARCH 1996

clock switching characteristics over recommended operating free-air temperature range (see
Figure 1)
PARAMETER

td1

Delay time, XI Nt to UARTCLKt

td2

Delay time, XIN-l- to UARTCLK-l-

td3

Delay time, XI Nt to UARTCLK,],

td4

Delay time, XI Nt to UARTCLKt

td5

Delay time, XIN,], to UARTCLKt

TEST CONDITIONS

MIN

MAX

VCC= 3.3V

VCC = 5 V
VCC = 3.3 V

VCC=5V

10
19.8

VCC= 3.3V

VCC=5V
VCC=3.3V

20.6

VCC=5V

13.5
21

VCC = 3.3 V

13.8

VCC = 5 V

UNIT

host CPU 110 read cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 11)
MIN

th1

Hold time, HA(9-0) valid after IORDt

th2

Hold time, REGt valid after IORDt

tw4

Pulse duration, lORD low

MAX

tsu1

Setup time, HA(9-0) valid before lORD,],

tsu2

Setup time, CEx']' before lORD,],

th3

Hold time, CExt after IORDt

165

ns
ns

th4

Hold time, HD(7-0) valid after IORDt

tsu3

Setup time, REG,], before lORD,],

td6

Delay time, HD(7 -0) valid after lORD,],

ns
100

NOTE 11. The maximum load on INPACK IS one LSTIL With 50-pF total load. All timing

UNIT

measured In nanoseconds.

host CPU I/O read cycle switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 2 and Note 11)
PARAMETER

MIN

MAX

UNIT

td7

Delay time, INPACK,], after lORD,],

td8

Delay time, INPACKt after IORDt

NOTE 11. The maximum load on INPACK is one LSTTL with 50-pF total load. All timing is measured In nanoseconds.

~TEXAS

INSTRUMENTS
2-330

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SllS172B- MAY 1994- REVISED MARCH 1996

host CPU 1/0 write cycle timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 3)
MIN

MAX

UNIT

tsu4

Setup time, HD(7-0) valid before IOWRJ.

th5

Hold time, HA(9-0) valid after IOWRI

tw6

Pulse duration, IOWR low

165

tsu5

Setup time, HA(9-0) valid before IOWRJ.

th6

Hold time, REGI after IOWRI

tsu6

Setup time, CExJ. before IOWRJ.

th7

Hold time, CExl after IOWRI

tsu7

Setup time, REGJ. before IOWRJ.

th8

Hold time, HD(7-0) valid after IOWRI

transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td9

Delay time, SOUTJ. after IOWRI

Baud
cycles

tdlD

Delay time, IREOJ. after SOUTJ.

Baud
cycles

tdl1

Delay time, IREOJ. after IOWRI

Baud
cycles

td12

Delay time, IREOI after IOWRI

Cl = 100pF

140

td13

Delay time, IREOI after IORDI

Cl=100pF

140

receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 5)
PARAMETER

td14

Delay time, sample ClKI after RClKI

tdlS

Delay time, IREOJ. after SINJ.

1d16

Delay time,IREOI after IORDI

TEST CONDITIONS

MIN

MAX

100
1
Cl= 100 pF

150

UNIT

ns
RClK
cycles
ns

modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage, CL = 100 pF (see Figure 6)
PARAMETER

MIN

MAX

UNIT

Id17

Delay time, RTS, DTR, OUTl , OUT2 J. or I after IOWRI

td18

Delay time, IREOJ. after CTS, DSR, DC OJ.

td19

Delay time, IREOI after IORDI

td20

Delay time, IREOJ. after RII

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-331

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITIER
SLLS172B- MAY 1994 - REVISED MARCH 1996

host CPU attribute memory write cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figures 7 and 8)
MIN

MAX

UNIT

tc2

Write cycle time, HA(9-0)

250

tW8

Pulse duration, WE low

150

tsu8

Setup time, tExt before WEt

180

tsu9

Setup time, HA(9-0) before WEt (see Note 12)

180

tsul0

Setup time, HA(9-0) before WEt and CExt(see Note 12)

tsull

Setup time, OEt before WEt

th9

Hold time, HD(7 -0) IN after WEt

trecl

Recovery time, HA(9-0) after WEt

tsu12

Setup time, HD(7 -0) IN before WEt

thl0

Hold time, OEt after WEt

tsu13

Setup time, CExt before WEt

thll

Hold time, CExt after WEt

NOTE 12. The REG signal timing IS Identical to address signal timing.

host CPU attribute memory write cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 7)
PARAMETER

MIN

MAX

UNIT

leiisl

Disable time, HD(7 -0) OUT after WEt

100

tdis2

Disable time, HD(7 -0) OUT after OEt

100

tenl

Enable time, HD(7 -0) OUT after WEt

ten2

Enable time, HD(7 -0) OUT after OEt

host CPU attribute memory read cycle timing requirements over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
MIN

MAX

UNIT

tc3

Read cycle time

td22

Delay time, HD(7 -0) after HA(9-0)

300

td23

Delay time, HD(7 -0) after CExt

300

td24

Delay time, HD(7 -0) after OEt

150

th12

Hold time, HD(7 -0) after HA(9-0)

tsu14

Setup time, CExt before OEt

th13

Hold time, HA(9-0) after OEt

tsu15

Setup time, HA(9-0) before OEt

th14

Hold time, CExt after OEt

300

host CPU attribute memory read cycle switching characteristics over recommended ranges of
operating free-air temperature and supply voltage (see Figure 9)
MAX

UNIT

tdis3

Disable time, HD(7 -0) after CExt

100

tdis4

Disable time, HD(7 -0) after OEt

100

ten3

Enable time, HD(7 -0) after CExt

ten4

Enable time, HD(7 -0) after OEt

PARAMETER

~TEXAS

INSTRUMENTS
2-332

POST OFFICE BOX 655303. DALLAS. TEXAS 75265

MIN

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994- REVISED MARCH 1996

subsystem Intel mode timing requirements (32 MHz) (see Figure 10)
INTEL
SYMBOL

JEDEC
SYMBOL

tLHLL

twll

Pulse duration, ALE high

tAVLL

tsu16

Setup time, SA8, SAD(7 -0) valid to ALE low

tpLLL

td25

Delay time, CS low to ALE low

tLLAX

th15

Hold time, SA8, SAD(7-0) valid after ALE,!,

tLLWL

td26

Delay time, ALE low to WR low

tLLRL

td27

Delay time, ALE low to RD low

tWHLH

td28

Delay time, WR high to ALE high

tAFRL

td29

Delay time, SA8, SAD(7 -0) in high-impedance state to RD low

tRLRH

tw12

Pulse duration, RD low

120

twLWH

tw13

Pulse duration, WR low

120

lRHAX

td30

Delay time, RD high to SA8, SAD(7 -0) active

twHDX

th16

Hold time, SA8, SAD(7 -O} valid after WR high

twHPH

1et31

Delay time, WR high to CS high

tRHPH

td32

Delay time, RD high to CS high

tpHPL

tw14

Pulse duration, CS high

MIN

MAX

UNIT

subsystem Zilog mode timing requirements (20 MHz) (see Figure 11)
ZILOG
SYMBOL
tdA(AS)

JEDEC
SYMBOL

MIN

tsu17

Setup time, SA8 and SAD(7 ~O) valid before AS high

20
35

tdAS(A)

td33

Delay time, AS high to SA8 and SAD(7 -O} invalid

tdAS(DR)

td34

Delay time, AS high to data in on SAD(7 -O}

twAS

tw 15

Pulse duration, AS low

tdA(DS)

td35

Delay time, SA8 and SAD(7 -0) invalid to DS low

twDS(read)

tw16

MAX

UNIT
ns
ns

150

Pulse duration, DS low (read)

125

twDS(write)

tw17

Pulse duration, DS low (write)

tdDS(DR)

td36

Delay time, DS low to data in valid

thDS(DR)

th17

Hold time, DS high to data in invalid

IetDS(i\t

th18

tdDS(AS) ,
tdDO(DS)
tdRW(AS)

ns
80

Hold time, DS high to data out invalid

td37

Delay time, DS high to AS low

td38

Delay time, SAD(7 -0) (write data from IlP) valid to DS low

td39

Delay time, RIW active to AS high

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-333

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLSI72B- MAY 1994- REVISED MARCH 1996

subsystem Intel non multiplexed timing requirements (see Figure 12)
MIN

tsu18

Setup time, SA(8-0), CS valid to RD, WRJ-

tw 18

MAX

UNIT

Pulse duration, RD low

120

tw19

Pulse duration, WR low

120

tsu19

Setup time, SAD(7 -0) valid to WRt

ten4

Enable time, RDJ- to SAD(7 -0) driving

td40

Delay time, RDJ- to SAD(7 -0) valid

th19

Hold time, SA(8-0), CS valid after RD, WRt

th20

Hold time, SAD(7 -0) valid after WRt

tdis3

Disable time, RDt to SAD(7 -0) high impedance

ns
105

ns
ns
ns

MIN

MAX

subsystem Zilog nonmultiplexed timing requirements (see Figure 13)
UNIT

tsu20

Setup time, SA(8-0), CS, RIW valid to DSJ- (write)

tsu21

Setup time, SA(8-0), CS, RIW valid to DSJ- (read)

tw20

Pulse duration, DS low (write)

tw21

Pulse duration, DS low (read)

125

Isu22

Setup time, SAD(7 -0) valid 10 DSt

ns
ns

ten5

Enable time, DSt to SAD(7-0) driving

Id41

Delay lime, DSt to SAD(7 -0) valid

th21

Hold time, SA(8-0), CS, RIW valid after DSt

th22

Hold time, SAD(7 -0), CS, RIW valid after DSt

tdis4

Hold time, DSt 10 SAD(7 -0) high impedance

105

~TEXAS

INSTRUMENTS
2-334

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLSl72B- MAY 1994- REVISED MARCH 1996

ARBCLK switching characteristics over recommended operating free-air temperature range (see
Figure 14)
TEST CONDITIONS
tc4

Cycle time, internal arbitration clock ( ARBCLKI + ARBPGM)

tc5

Cycle time, arbitration clock

td42

Delay time, ARBCLKI1' to ARBCLK01' (+ 1)

td43

Delay time, ARBCLKlt to ARBCLKOt (+ 1)

td44

Delay time, ARBCLKI1' to ARBCLK01' (+2)

td45

Delay time, ARBCLKI1' to ARBCLKOt (+2)

td46

Delay time, ARBCLKI1' to ARBCLK01' (+4)

td47

Delay time, ARBCLKI1' to ARBCLKot (+4)

td48

Delay time, ARBCLKI1' to ARBCLK01' (+8)

td49

Delay time, ARBCLKI1' to ARBCLKOt (+8)

MIN

MAX

VCC = 3.3 V

Note 13

VCC = 5 V

Note 13

VCC =3.3V

VCC = 5 V

UNIT
ns

ns
13

VCC=3.3V

7.3

VCC= 5 V

15.5

VCC = 3.3 V

VCC = 5 V

15.3

VCC=3.3V

8.8

VCC=5 V

17.5

VCC=3.3V

VCC = 5 V
VCC=3.3V

19.5

VCC =5 V

11.5

VCC=3.3V

21.5

VCC = 5 V

13.5

VCC=3.3V

22.7

VCC = 5 V

13.5

ns
ns

VCC = 3.3V

15.7

VCC = 5 V

NOTE 13. 1c4 max = N/6, where N = shortest (In ns) of the two attribute memory accesses, host CPU or subsystem.

reset timing requirements over recommended ranges of operating free-air temperature and supply
voltage (unless otherwise noted) (see Figure 15)
TEST CONDITIONS

MIN

tw22

Pulse duration, RESET active

8·tc5

tw23

Pulse duration, RESET inactive

8·tc 5

Delay time, ARBCLKI1' to RST low

td51

Delay time. ARBCLKI1' to RST high impedance

UNIT
ns
ns

10A

VCC = 3.3 V

td50

MAX

7.5

VCC = 5 V

13.9

VCC = 3.3 V

9.7

VCC=5V

subsystem interrupt request timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 16)
MAX

UNIT

2tc5

3tc5

ARBCLKI
cycles

tc5

21c5

ARBCLKI
cycles

MIN
td52

Delay time, WEt to IROt (see Note 14)

td53

Delay time, SCR bit 6t to IROt (see Note 15)

NOTES: 14. Synchronized to rising edge of ARBCLKI
'15. Synchronized to falling edge of ARBCLKI

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-335

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994 - REVISED MARCH 1996

host CPU status change timing requirements over recommended ranges of operating free-air
temperature and supply voltage (see Figure 17)

tdS4

Delay time, subsystem write! to STSCHGJ- (see Note 14)

tdSS

Delay time, OEJ- to STSCHG high impedance (see Nole 15)

MIN

MAX

UNIT

2tcS

31cS

ARBCLKI
cycles

1c5

2lcs

ARBCLKI
cycles

..
Synchronized to rising edge of ARBCLKI

NOTES: 14.
15. Synchronized to falling edge of ARBCLKI

PARAMETER MEASUREMENT INFORMATION
~-------------------N-------------------..I

I
I

XIN

UARTCLK
(1/0.5 -1/1.S)

I
td3 ~

UARTCLKt

(1/2 -In)

i4- -+I !4-1-

=--fl
u'

1 XIN Cycle
td3

f-t-'________1---:-_____

.1" i I

(1/8 -1/31)

(N-l)XIN Cycles --7-----------.... 1

td5
I
~----------T_~~l-------;

1.5 XIN Cycles -+-i-----------I~--------- (N-l.S)XIN Cycles

td3
UARTCLK+

~LJ

1/)

I
I

UARTCLKt
(1/2.5 -117.5)

td4

~ ~

td4~ ~[.

)

i "'I~---- 4 XIN Cycles ---------~"'t-~ (N-4)XIN Cycles ~

Id3
UARTCLK*

(1/8.5 -1/31.5)

-+I i+-

td5 --'

i4-

t,!-I)----',~

~~========--4-.5-X-IN-C-YC-le-S----------~---_-_-_~,.~..__

(N-4.5)
XIN Cycles

tThe low portion of the UARTCLK cycle = 1 XIN cycle for PGMCLK integer values of 2 to 7 and 1.5 XIN cycles for PGMCLK noninlegervalues
2.5 to 7.5.
:\: The low portion of the UARTCLK cycle = 4 XIN cycles for PGMCLK integer values of 8 10 31 and 4.5 XIN cycles for PGMCLK noninteger values
8.5 to 31.5.

Figure 1. XIN Clock Timing Waveforms

~TEXAS

2-336

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITIER
SLLS1728 - MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

HA(9-0)

~90% ________________________________ V 50%
._~10~o/.~o

J~
1

REG

~~'?'7""J""'?'"'7""?"""'~

1~%

~10%

~.,..,...,..,...,..,....""
CE1,CE2

tsu3

th2

---.1

th1

f?/////////d

~10%i
I
I

I+-

~""""'""77"7"'7'77'7"

1rO~
-----.j

tsu2

~ th3

~1~~------tW4--------~.1

i
i+- tsu1

}

50%lr---------------

50%

---*1...-- td7 ~
1

10%

114~------- td6 ------~.!

I
I

10%(

*-- td8~

~1~r____l.~I-- th4
1

HO(7-0)

----------------------<:r--v-ali-d--.l--------

NOTE A: Ali timings are measured at the card. Skews and delays from the system driverlreceiverto the card must be accounted for by the system
design.

Figure 2. Host CPU 110 Read Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·337

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

HA(9-0)

~_SO_%_._______________________________________SO_%J.)(~_________

~,O%
~
I

~I
CE1, CE2

HD(7-0)

thS

'O%~

~~~

I
tSU7-t>:

~10%

----------(

10%~

J---------

NOTE A: All timings are measured at the card. Skews and delays from the system driver/receiverto the card must be accounted for by the system
design.

Figure 3. Host CPU 1/0 Write Timing Waveforms

SOUT

Start

Data

sl{s (5-8)

XiY

Start
Stop \50%

r-/

141"--I~M-td10

r-'~----------------------~~
I

I
I
I
I

~td12
IOWR
(write transmitter
holding register)

lORD
(read interrupt
identification
register)

td13~

50%

\'~!------------------~

\~---J/ 50%

Figure 4. Transmitter Timing Waveforms

~TEXAS

INSTRUMENTS
2-338

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
!<
.
I I.
I '-

RClK

8 Clocks - - - - - - - -... '

Jl'-------..In~---i\(r_i_,"""",h~___

t+-

td14-1

SampleClK
(internal)

___________________~((\~--~Il~-----

))

Tl16C450 Mode:
SIN

~,_S_ta....rt/~___...l,I,-_ _

...J
1

Sample ClK

IREQ
(data read or
receive ERR)

lORD
(read RBR or
read lSR)

I
)(~)--L---~--L-~I--~------------
I
----+i 14- td15

---------------~\~\------------------~~
50% ,'__ _ _ _ _
50-.J% 1
.

---------------~\(~)--------------------~\

td16--+oII"I--~·1

, I r_ __
'__ _...J
,
,

50%

Figure 5. Receiver Timing Waveforms

(write

I~~R~

150%

'--_-...i

1 50%

'--_-...i

~
td17
--------____
~I
RTS,J>TR
OUT1,OUT2

50o/~'_

,..

.'I r -_
td17 _ _ _ _ ___

_____________________J)l50%

\,,50%

td18---lo111..-~.1

- - - -_ _ _ _ _~I
50% ,

I
td19 -loI..l---~
.. I
lORD
(read MSR)

~'-5-0o/c-._ _

__________________5_0o/c-l.

l+-td20~

1~50-%--+:---------

' - -__-...i

/50%

Figure 6. Modem Control Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·339

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS1?2B- MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
-------------------te2-----------------------.~1
1

1• •

HA(9-0)

~
90%
90% ~ 90%
-0...:1.::.0.~*'_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.:.:10~%~~1i;...:.1.::.0.;.~.--'4---------- tsuB - - - - - - - - - - - - - - . .

14--------1-1----- tsu9 - - - - - - - - - - - - - - - . , i~
1

: :'>f-.L.Ji
I+- tsu10 1 "i

7\.... :

I~.----- twB ------------.r~

90%

1 110%
--+11 i4-i-1

10%

' 1 1

~I 1'- th10
I
su 1'} ---~..,
'I ~'th9
1

HD(7-0) IN

_I
114[----rtreel

11 1

....
t ...f - - - - - t

See Note B

1
11 1

1
1
---------~I~~'O%
tsu11

90% .r---------'-~~
Data Input Established

-------t--+---{

HD(7-0) OUT
NOTES: A, The hatched portion may be either high or low,
B, When the data I/O terminal is in the output state, no signals shall be applied to HO(? -0) by the system,

Figure 7. Host CPU Attribute Memory Write Timing Waveforms (WE ContrOl)

~TEXAS

INSTRUMENTS
2-340

th11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

CE1, CE2

See Note C
90%
HO(7-0) - - - - - - - - - - {
Data Input Established
10% -,..._ _ _ _ _ _ _ _ _

90%
~10%

NOTES: A. The hatched portion may be either high (H) or low (L).
B. OE must be high (H).
C. When the data I/O terminal is in the output state, no signals shall be applied to HD(7 -0) by the system.

Figure 8. Host CPU Attribute Memory Write Timing Waveforms (CE Control)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·341

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS1728 - MAY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

1414--------- te3 -----,----~.I

114-4---

icl22

---~~I

HA(9-0)

1
1

14~-- td23

<~£{N,...
1

V~9"'0""%-----

--.I I+-

th13

----+.:

n :

--+I 141

th14

tsu14

tsu15

i4ften3~

~10%!

r-- td2~ 4

ten4

90Jt~~--+-------1

-11111'--~~:

________-<,

iclis4

iii

-+-1

tdis3

90%

(90%

90%:

)-1

\10%

10%

10%2

NOTE A: The shaded portion may be either high or low.

Figure 9. Host CPU Attribute Memory Read Timing Waveforms

~TEXAS

INSTRUMENTS
2-342

th12

1
1

T$~~"""4"7"'l~f..-r;~r7~"7"'l

---------~"90%

HD (7-0)

90%

~~1~0'~~_ _ _ _ _ _ _~._ _ _ _ _~1~0·~~~~~1~0~%~_ _ __

CE<,CE2

~ j- 90%

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLSl72B- MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

J.-tW11~

ALE

\SO%
tsu16 -!+----.I~

SA~~

j '" ~_.*=:h=0:=:'=============llp==Da=t=~d=2=8=::
==========s=oo=Yo:4:=
td29
I+--td30. th16-----.j

'0%

I ~ ~
I
I I
lOl
.14

td26. td27
WR RD

tw14
cs

,..-_______

~'\!O%
SO%/IY
'------------' I

td2S r-"l
I,.
I

tw 12. tw13------+i~

td31. td32 -I414---.~1I
SO%)tr----

.1
I

J \ SO%

NOTE A: This figure is from the microprocessor perspective, not from the UART perspective.

Figure 10. Subsystem Intel Mode Timing Waveforms

~ ~~:~;~:__________________________J)(~_____
14~---1.*I- td39

90%V
10%f _____
\~

i4-----td34 - - - - - . t

SA8.
SAD(7-0)

90%
~p

Data Out

10%

tsu17

I I

~I ~

~th18~

90%

10%

l.-td38~

~ ______
td33

~~I

90% 1

~th17

td37

:.----.I
~I______~____~________~~

AS ~
10%
10% ~I ~td3S II
:
tw1S ~ ~
~14---+1 td36 ~
90% -0
~%
10%'\
~ 10%
I

I
lOl

90%

I
I

~90%

~O%

~tw174
tw 16

NOTE A: This figure is from the microprocessor perspective, not from the UART perspective.

Figure 11. Subsystem Zilog Mode Timing Waveforms

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-343

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B-MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

SA(8-0)eS

~I------------------------------------------------~

tsu18

1
1
1
1
1
I"
14

1
.1
~

tsu19

------------------1---------(
ten4

SAD (7-0) OUT

WR or RD

SAD (7-0) IN

.14 th19~

tw18, tw19

.1
1
1

td40

---------------------<

~ *- tdis3
Data Valid

Figure 12. Subsystem Intel Nonmultiplexed Timing Waveforms

SA(8-0~

i
14
1
14

tsu20
tsu21

1
SAD (7-0) OUT

--.!

{'
tw22

I..

tens

tw20

14
1
1
1
1

SAD (7-0) IN

td41

(

·1
.1

tsu22

--4i

.1
1
1

~
Data Valid

Figure 13. Subsystem Zilog Nonmultiplexed Timing Waveforms

~TEXAS

INSTRUMENTS
2-344

14
1

th21

1
14

·1

1
1
·1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~
>-=-

I+-

tdis4

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITIER
SLLS172B - MAY 1994 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ARBCLKI

I ~

tcl43

td4~~~
:
I

ARBCLKO (1/1)

td44
ARBCLKO (112)

II
Ii+i+-

-.j

iI
~I 1
.I

I+---

tcI%~~
ARBCLKO (1/4)

-+I I
tc4

.-lJ

I
I
I I..

td45

1""1---

I~
1
tcl47

tc4 ~

:I
I

L.------"""'i~

--.I 14- td49
tc4

tcl48~ ~
ARBCLKO (1/8)

-:1-------------+1.1

--.JI

_------,II

Figure 14. Arbitration Clock Timing Waveforms

ARBCLKI

~~-----------tw22-------TI~~~.. ---------~23-------~~

RESET

II1

•
L.-_
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~--~

--'1 :..... td50

--Jr---

td51 --.:

RST - - - - - - - - - - - - - - - - - - - - - \ ' -_ _ _ _ _ _ _ _ _ _ _

Figure 15. Reset Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·345

TL16PC564A
PCMCIA UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER
SLLS172B- MAY 1994- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

--------------

i~--~\(~I
'-----...II

SCRBlt6

--J'I~\"------

_ _ _ _ _ _ _ _ _ _+I_ _ _ _-I,\~()_ _ _ _

~ i4- td53

--.: 1.- t

--'I-j_d_5_2_ _ _ _ _ _ _ _~1

IRQ _ _ _ _ _ _ _ _ _ _

Figure 16. IRQ Timing Waveforms

----------

Subsystem Write - - - " " ' \
i,...------'l(j'~j
(Intel WR)
(Zilog OS)
"-------' I

I
I

I'-----J

~- td54

r--------

STSCHG - - - - - - - - - - - - - - \ ' -_
_ _-1,(/~)_ _--J.
.

Figure 17. STSCHG Timing Waveforms

~TEXAS

INSTRUMENTS
2-346

POST OFFIC~ BOX 655303 • DALLAS, T~XAS 75265

td55

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

• PnP Card Autoconfiguration Sequence
Compliant
• Supports Two Logical Devices
• Decodes 10-Bit 1/0 Address Location With
Programmable 1-, 2-, 4-, 8-, 16-Byte Block
Size
• Maps Interrupts to Six Interrupt Outputs
IRQ3-IRQ7 and IRQ9
• Provides Simple 3-Terminallnterface to
SGS-Thomson EEPROM 2K14K ST93C56/66
or Equivalent
• 3-State Output EEPROM Interface Allows
the EEPROM to be Accessed by Another
Controller
• Provides Direct Connection to ISA/AT Bus
• Data and Interrupt Signals Require No
Buffer
• Available in 44-Pin Plastic Leaded Chip
Carrier (PLCC) and 48-Pin TQFP Package

654

3 2

1 44 43 4241 40
0
39

8
9
10

38
37
36

11
12

04
05

13
14
15

33
32
31

GNO

06
07

16
30
17
29
1819 20 21 22 23 24 25 26 27 28

CSO

02
03
GNO

GNO
IRQ3

ClK
INTRa
EEPROM

description
The TL 16PNP1 OOA responds to the plug-andplay (PnP) autoconfiguration process. The
process puts all PnP cards in a configuration
mode, isolates one PnP card at a time, assigns a
card-select number (CSN), and reads the card
resource-data structure from the ST93C56/66
EEPROM. After the resource requirements and
capabilities are determined for all cards, the
process uses the CSN to configure the card by
writing to the configuration registers. The
TL 16PNP1 OOA implements configuration registers only for 1/0 applications with two logical
devices, and DMA application support is not
provided. Finally, the process activates the
TL 16PNP1 OOA card and removes it from
configuration mode. After the configuration
process, the logic function can then start
responding to industry standard architecture
(ISA) bus cycles. The controller disables the
EEPROM interface after the configuration is
complete to allow another on-board controller to
access the EEPROM.

PTPACKAGE
(TOP VIEW)

tii

tiJla: 15: [3 () () a ~

LFSR
Key

Enable

NOTE A: Terminal numbers shown are for the FN package.

2-348

Select

Address
Register

-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265

t--

""
,/

I--

TL16PNP100A
STANDALONE PLUG·AND·PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

Terminal Functions
TERMINAL
FN
NO.

PT
NO.

110

DESCRIPTION

1
44-34

42
41-33,
31,30

12·bit ISA address terminals. AO and AI - All are all used during the PnP autoconfiguration
sequence.

AEN

ISA address enable. During DMA operation, AEN is active and causes the controller to ignore
the ISA transaction.

NAME
AO
A11-Al

CLK

22-MHz external clock input. CLK synchronizes PnP logic and generates a 0.68-MHz SCLK.

CSO

Chip select for logical device number O. The address decoder only decodes a 1O-bit address for
one 1/0 location with programmable block size.

CSI

Chip select for logical device number 1 . The address decoder only decodes a 1O-bit address for
one 1/0 location with programmable block size.

7-10
12-15

1-4
6,8-10

1/0

Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and
status information between the TL 16PNP100A and the CPU. Output drive sinks 24 mA at 0.4 V
and sou rces 12 mA at 2.4 V.

1/0

EEPROM interface access enable. A 3-state bidirectional signal. When EEPROM is pulled low,
the EEPROM interface is being accessed. A release state indicates the EEPROM interface is
idle. A 100 J.LA pUIiUp transistor is connected internally to this terminal.

11, 16,
33

5, 11,
29

INTRO

INTRI

Interrupt request from logical device number 1. INTRI is an active-high signal.

lOR

ISA read input

DO-D3
D4-D7
EEPROM

GND

lOW

Ground (0 V). All terminals must be tied to GND for proper operation.
Interrupt request from logical device number O. INTRO is an active-high signal.

ISA write input

17-21
22

12-16
17

Interrupt request. INTRn request is mapped to one of the IROs based on the value of the content
of the interrupt request level (Ox70) register. Output drive sinks 24 mA at 0.4 V and sources
12 mA at 2.4 V. These terminals are 3-state outputs.

RESET

Reset. When active (high), RESET clears most logical device registers and puts the
TL 16PNP100A in the wait-for-key state. The CSN is reset to OxO. All configuration registers are
set to their power-up values.

SCLK

1/0

Serial clock (3-state output path). SCLK controls the serial bus timing for address data. A 100 JlA
pulldown transistor is connected internally to this terminal.

SCS

1/0

EEPROM chip select (3-state output). SCS controls the activity of the EEPROM. A 100
pulldown transistor is connected internally to this terminal.

SIO

1/0

Serial input/output. A 3-state bidirectional EEPROM 1/0 data path. A 100 J.LA pulldown transistor
is connected internally to this terminal.

VCC

2,25

21,43

IR03-IR07
IR09

J.LA

5-V supply voltage

~TEXAS

INSTRUMENTS
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2-349

TL 16PNP1 OOA
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

detailed description
block size
This device generates read instructions for the EEPROM. Read transactions consist of read opcode, address
and data cycles. Data cycles are comprised of 2-byte DATA. After power up resets, this device reads the
programmable block size value from address zero in the EEPROM. Data [15:13] carries the block size
information for logical device O. Data [11 :9] carries the block size information for the logical device 1 (see
Table 1).

Table 1. Block Size
DATA [15:13]1[11:91

BLOCK SIZE
(Bytes)

ADDRESS BITS DECODED

000

[A9:AOI

001

[A9:A1]

010

[A9:A2]

100

[A9:A3]

111

16 (default)

[A9:A4]

EEPROM signal description
This device interfaces to SGS-Thomson's compatible EEPROM 2-Kbit ST93C56 or 4-Kbit ST93C66. After
completion of the configuration sequence, it allows an optional on-board controller to access the EEPROM.
During and after reset, TL 16PNP1 OOA gains access to the EEPROM by asserting EEPROM low, informing the
optional on-board controller that it is accessing the EEPROM. After the configuration is complete, the device
leaves the configuration mode, is activated, and is in the wait-for-key state. The EEPROM signal is then
released and pulled high, SIO is released and pulled down, and SCS and SCLK are placed in the
high-impedance state and pulled down.
NOTE
When the device enters the configuration mode again and leaves the wait-for-key state, it gains
direct access to the EEPROM after the EEPROM signal is released. The wake command generates
a read transaction from address Ox1, which is the beginning of the resource data of the card.
When the EEPROM signal is released, the interface of the EEPROM is idle. The TL 16PNP1 OOA
drives the EEPROM signal low when the device enters the configuration mode again.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee ......................................................... -0.5 V to 7 V
Input voltage range at any input, VI ................................................... -0.5 V to 7 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds: FN package .............................................. 260°C

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL 16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

recommended operating conditions
Supply voltage, VCC

MIN

NOM

MAX

UNIT

4.75

5.25

VCC

-0.5

0.8

°c

High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

TEST CONDITIONS

MIN

IOH = -4 mA (see Note 1)

VCC-0.8

IOH = -12 mA (see Note 2)

VCC~0.8

TYpt

MAX

UNIT

VOH

High-level output voltage

VOL

Low-level output voltage

Input current

VCC=5.25V,
VI = 0 to 5.25 V,

VSS=O,
All other pins floating

±1

IJA

102

High-impedance-state output current

VCC=5.25 V,
VSS=O,
Vo = 0 to 5.25 V,
Pullup transistors and pulldown transistors are off

±10

ICC

Supply current

VCC = 5.25 V,
All inputs at 0.8 V,
No load on outputs

0.7

Ci(CLK}

Clock input capacitance

fCLK

Clock frequency

IOL = 4 mA (see Note 1)

0.5

IOL = 24 mA (see Note 2)

0.5

TA = 25°C,
CLKat4 MHz,
15
10

MHz

t All typical values are at VCC = 5 V and TA = 25°C.
NOTES:

1. These parameters apply for all outputs except 07-00, IRQ3-IRQ7 and IRQ9.
2. These parameters only apply for 07-00 and IRQ3-IRQ7 and IRQ9 outputs.

clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOL

PARAMETER

tw(SCLKH)

Pulse duration, SCLK high to low (see Note 3)

tCHCL

tw(SCLKL)

Pulse duration, SCLK low to high (see Note 3)

tCLCH

fCLK

SCLK clock frequency (see Note 4)

NOTES:

TEST CONDITIONS

MIN

MAX

250
See Figure 8

250
0.3

UNIT

ns
0.68

MHz

3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles according
to the ST93C56 specification.
4. The SCLK signal is attained by internally dividing the frequency of the XIN signal by 32.

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2-351

TL16PNP100A
STANDALONE PLUG·AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

switching characteristics
PARAMETER

ALTERNATE
SYMBOL

TEST CONDITIONS

tSHCH

See Figure 8

'<11

Delay time, CS high to SCLK high

td2

Delay time, SIO input valid to SCLK high

tOVCH

tpd1

Propagation delay time, SCLK high to SIO level transition

tCHOX

tpd2

Propagation delay time, SCLK high to output valid

tCHQV

tpd3

Propagation delay time, SCLK low to CS transition

tCLSL

td3

Delay time, CS low to O/Q output Hi-Z

tSLQZ

See Figure 8 and
Figure 9

MIN

MAX

UNIT

100

ns
500

See Figure 9

2
100

ns
clock
period
ns

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tw1

Pulse duration, write strobe, lOW low

tWR

See Figure 5

clock
periods

tw2

Pulse duration, read strobe, lOR low

tRO

See Figure 6

clock
periods

tw3

Pulse duration, master reset

tMR

tsu1

Setup time, data 07-00 valid before 10W'l'

tos

See Figure 5

th1

Hold time, chip select CSx valid after address
Ao-A 11 becomes invalid

tCH

From the first rising edge of XIN
after address becomes invalid,
See Figure 5 and Figure 6

th2

Hold time, data valid 07-00 after 10WI

tOH

See Figure 5
From the first rising edge of XIN
after address valid,
See Figure 5 and Figure 6

ns
ns

td4

Delay time, CSx valid after address Ao-A 11 valid

tCSRW

th3

Hold time, address Ao-A 11 valid after 10WI

tAW

See Figure 5

td5

Delay time, lOR valid to data 00-07 valid

tCSVO

CL = 45 pF after 2 clock periods,
See Figure 6

td6

Delay time, 10RI to floating data 00-07

tHZ

CL =45 pF,
See Figure 6

td7

Delay time, INTROI, INTR11, INTRot, or INTR1Jto IRQI or IRQJ-

See Figure 7

~TEXAS

INSTRUMENTS
2-352

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP1 OOA
STANDALONE PLUG·AND·PLAV (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
10WR
r

lOR
D7-oo

A3-AO

logical
Device #0

RESETDRV
r

10WR
lOR
r

ISABus

D7-DO

A3-AO

Logical
Device #1

RESETDRV
A

I~
A11-AO
D7-DO

II:
I-

I§

2!:

23
12

2!:

1,34-44
7-10,12-15

RESETDRV

lOW

lOR

SClK

SCS

C
r

Tl 16PNP1 OOA
~

IRQ3-7, IRQ9
AEN

S
EEPROM

28..._SIO

17-22
6

EEPROM
r

To Optional
On-Board
Controller

ClK
NOTE A: A 2-kQ resistor should be inserted between D and Q. See the SGS-Thomson EEPROM 2K14K ST93C56166 application
report.

Figure 1. Basic TL16PNP1 OOA Configuration

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2-353

TL16PNP100A
STANDALONE PLUG-AND-PLAV (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
on-board EEPROM programming
This section describes a simple approach to programming the resource EEPROM in an expansion board that
uses the TL 16PNP1 OOA. This approach involves utilizing a readily available standard EEPROM programmer
and a ribbon cable in addition to minor additions to the expansion board.
A connector is needed on the expansion board to provide access to the EEPROM signals as shown in the
diagram below. Two jumpers are also needed to isolate the EEPROM during programming. Power to the board
must be removed before programming. To isolate the Vee ofthe EEPROM from the board Vee, Jumper 2 should
be disconnected. This disables the PnP controller and prevents it fro(Tl driving the EEPROM inputs. Jumper 1
should also be taken off during programming to isolate the D input and Q output. The PnP controller uses a single
pin for the EEPROM data input and output.
The ribbon cable plugs into the on-board connector on one end, and the other end has a DIP connector that
plugs into the EEPROM programmer.
Programming the EEPROM is achieved by connecting the unpowered board to the programmer using the
ribbon cable, removing the jumper wires, and then using the software supplied with the programmer. After
programming is complete, the jumper wires are reattached and the board is now ready for testing.

hardware required for programming an expansion board EEPROM
The hardware required for programming an expansion board EEPROM is listed in the following bulleted list and
shown in Figure 2.
•

EEPROM programmer

•

Ribbon cable with connectors

•

Oncboard connector and two jumper wires
EEPROM

TL16PNP100A
SCLK

SCS

SIO

D
'A:v- -:-'

Jumper 1

III

Jumper 2

Vce

VCC

DU f---ORG f-Vss

Connector

Figure 2. Programming an Expansion Board EEPROM

~TEXAS

2-354

INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265

J-

TL16PNP1 OOA
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION

32-byte I/O block size
The TL 16PNP1 OOA supports I/O block sizes ranging from 1 to 16 bytes. The following is one method to enable
this device to support 32-byte I/O block size.
•

Use only one logical device, and consequently one es, either eso or eS1.

•

In the first 2 bytes of the EEPROM select an I/O block size of 16 bytes for the selected logical device.

•

In the EEPROM I/O descriptor resources, set the number of ports to 32 and the base address increment
to 32.

•

Use a NOR gate and an inverter to qualify address line A4 with the signal EEPROM as shown in
Figure 3:

A4(frOmISABUS)~
to A4 of TL16PNP100A

EEPROM (from TL16PNP100A)

Figure 3. 32-Byte 110 Support
This operation forces A4 to 0 after completing the confirguration process (EEPROM signal is pulled up internally
and goes high after the configuration process is complete.) When the address on the ISA bus is in the next 16
I/O addresses, only A4 changes from 0 to 1. Since A4 is being forced to 0, the TL16PNP1 OOA thinks that the
address is still in the 16-byte range and it asserts es.
Example:
Using logical device 0:
•

Connect eso directly to the es input of the device.

•

Insert the NOR gate as described above.

•

In the EEPROM, set the I/O block size to OxOOEO (Blk_size = 16 bytes)

•

The I/O descriptor in the EEPROM resources should be as follows:
I/O Port Descriptor 1
db

047h; Small item, type I/O port descriptor

OOOh; Information, [0] = 0, 10 bit decode

020h

; Minimum base address [7:0]

002h

; Minimum base address [15:8]

OeOh

; Maximum base address [7:0]

003h

; Maximum base address [15:8]

020h

; Base address increment = 32

020h

; Number of ports required

= 32

~TEXAS

INSTRUMENTS
POST OFACE BOX 655303 • DALlAS, TEXAS 75265

2-355

TL16PNP1 DDA
STANDALONE PLUG-AND-PLAV (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
During configuration, assuming the system assigned the device address range Ox220 to Ox23F, EEPROM is
low and A4 from the ISA bus passes to A4 on the TL 16PNP1 OOA. When configuration is complete EEPROM
goes high, and A4 atthe input ofTL16PNP1 OOA is resetto O. Since the block size is 16, the TL16PNP1 OOA looks
at address bits A9 to A4. When the address on the A9 to AO is in the range of 0x220 to Ox22F, A9 to A4 is:
A9

000
and

eso is asserted low.

When the address is in the range of Ox230 to Ox23F, A9 to A4 is:
A9

000

However, since A4 atthe input of PNP1 OOA is forced to 0, A9 to A4 is the same as in the range of Ox220 to 0x22F
and TL 16PNP100A asserts eso low.

obtaining WIN95 logo
To obtain the WIN95 logo, the card should be able to decode 16-bit I/O address. Since the TL15PNP1 OOA uses
1O-bit address decoding, an OR gate is needed on-board to decode the upper 6 address bits (SA 15-SA10). The
customer can use this gate by changing the I/O port descriptors in the EEPROM to reflect the 16-BIT ISA
address. However, the customer must make sure that the upper 6 BITS in the I/O port descriptors have the same
minimum and maximum base in the address registers.
For example, a logical device requires a base address between 0200h and 0300h with an 8-byte as a base
alignment and one I/O port requested. (Notice that the requested base address is such that the upper six bits
in the minimum and maximum base address ranges are the same as in this example all are considered to be
zeros). To meet the requested resources, the following steps must be done:
1.

Modify the gate logic on the board as shown in Figure 4.
SA15--......
SA14--......
SA13--......
SA12--.......
SA11--......
SA10--......
SAEN--......

OR GATE
LOGIC

1---..... AEN PIN (ToTL16PNP100A)

Figure 4. Gate Logic Modification
All the signals on the left side of the OR gate are ISA signals. Output AEN should be zero for valid I/O addresses.

~TEXAS

2-356

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
2.

Program the I/O ports descriptors in the EEPROM as follows:
47h

1/0 port descriptors with 7 bytes

01h

Information, bit [0] is set. The logical device is decoding full 16-bit ISA addresses

OOh

Address bits [7:0] for minimum configuration base 1/0 address

02h

Address bits [15:8] for minimum configuration base 1/0 address

OOh

Address bits [7:0] for maximum configuration base 1/0 address

03h

Address bits [15:8] for maximum configuration base 1/0 address

08h

Base alignment, which has a block size of 8 bytes

01 hOne 1/0 port is needed
Using the above setup, the PnP BIOS maps the logical device to an address so that the upper six bits are always
zeros. The logic 0 output from the OR gate occurs when SA 15-SA10 and SAEN are low. This forces the logical
device to check SA09-SAO for a possible valid address.

PARAMETER MEASUREMENT INFORMATION

ClK
AO-A11

-i~l-lj---....r..I,JLrUL
50%X:
~ 50%
Valid Address

--ri ),"50-%---

~ tcl4

CSO/CS1

I+- th1

-----5-0%-..~

Valid

14-~-- tw1

---------..'

50%\ .

Active

j4-- tsu1

~..

th3

th2

I(,,.-----------50%

D7-DO--------~k~_ _~_a_lid_D_a_ta_ _J)~'-----Figure 5. Write-Cycle Timing

~ThxAs

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2·357

TL16PNP1 OOA
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION

ClK

~~'r-'j----;'jJLfl--f1-

Vo..

AO-A11 _ _S_O%..J

Add~

~ 1c14

CSO/CS1

I+- th1

----'

-----S-~"""~t

Valid

)lSO%

_ _ _ _"""" I~
I
tw2 -------~1,...-_ _ _ _ __

\\J.i__

SO%

A_ct_iV_B_ _..

----l

!+- tdS

SO%

td6

D7-DO--------(k~_ _v_al_ld_D_ata_ _~)~!----Figure 6. Read-Cycle Timing

INTRMNTR1

IRQx

-----~-!,

14- td7

Figure 7. External Interrupt (EXINTR) Timing

~TEXAS

2·358

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
PnP card configuration sequence
The PnP logic is quiescent on power up and must be enabled by software.
1. The initiation key places the PnP logic into configuration mode through a series of predefined writes to
the ADDRESS port (see PnP Autoconfiguration Ports section).
2.

A serial identifier is accessed in bit-sequence and used to isolate the ISA cards. Seventy-two
READ_DATA port reads are required to isolate each card.

Once isolated, a card is assigned a CSN that is later used to select the card. This assignment is
accomplished by programming the CSN.

The PnP software then reads the resource-data structure on each card. When all resource capabilities
and demands are known, a process of resource arbitration is invoked to determine resource allocation
for each card.

All PnP cards are then activated and removed from the configuration mode. This activation is
accomplished by programming the ACTIVE register.

PnP autoconfiguration ports
Three 8-bit ports (see Table 2) are used by the software to access the configuration space on each ISA PnP
card. These registers are used by the PnP software to issue commands, check status, access the resource data
information, and configure the PnP hardware.
The ports have been chosen so as to avoid conflicts in the installed base of ISA functions, while at the same
time minimizing the number of ports needed in the ISA 1/0 space.
Table 2. Autoconfiguration Ports
PORT NAME

LOCATION

TYPE

Ox0279 (printer status port)

Write only

WRITE_DATA

OxOA79 (printer status port + OX0800)

Write only

READ DATA

Relocatable in range Ox0203 to OxOSFF

Read only

ADDRESS

The PnP registers are accessed by first writing the address of the desired register to the ADDRESS port,
followed by a read of data from the READ_DATA port or a write of data to the WRITE_DATA port. Once
addressed, the desired register may be accessed through the WRITE_DATA or READ_DATA ports.
The ADDRESS port is also the destination of the initiatiori key writes (see PnP ISA specification).
The address of the READ_DATA port is set by programming the SET RD_DATA PORT register. When a card
cannot be isolated for a given READ_DATA port address, the READ_DATA port address is in conflict. The
READ_DATA port address must then be relocated and the isolation process begun again. The entire range
between Ox0203 and Ox3FF is available; however, in practice it is expected that only a few address locations
are necessary before the software determines that PnP cards are not present.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265

2-359

TL16PNP1 OOA
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
PnP registers
PnP card standard registers are divided into three parts: card control, logical device control, and logical device
configuration. There.is exactly one of each card control register on each ISA card. Card control registers are
used for global functions that control the entire card. Logical device control registers and logical device
configuration registers are repeated for each logical device. Since the TL 16PNP1 OOA has two logical devices
and they are intended only for I/O applications, not all the configuration registers are implemented.

PnP card control registers
The PnP card device control registers are listed in the following Table 3.

Table 3. PnP Card Control Registers
ADDRESS PORT
VALUE
OXOO

READIWRITI!:
CAPABILITY

POWER UP

Write only

00000000

Writing to this register modifies the address port used for reading from the PnP ISA card. Writing to this register is only
allowed when the card is in the isolation state.
Bit<7:0>
Become I/O port address bits <9:2>.
0><01

Read only

SERIAL ISOLATION

00000000

Reading from this register causes a card in the isolation state to compare one bit of the board ID.
0><02

Write only

CONFIGURATION CONTROL

000

This 3-bit register consists of three independent commands, which are activated by writing a 1 to their corresponding
register bits. These bits are automatically reset to 0 by the hardware alter the commands execute.
Writing a 1 to bit 1 causes the card to reset its CSN and RD-DATA port to zero.
Bi1<2>
Writing a 1 to bit 2 causes the card to enter the wait-for-key state, but the card CSN is
Bil
preserved and the logical device is unaffected.
Writing a Ito bit 0 resets the configuration registers of the logical device to their default state, and the
Bit
CSN is preserved.
0><03

Write only

WAKE[CSN]

0000 00 00

Writing to this register, when the write data [7:0] matches the card CSN, causes the card to go from the sleep state either
to the isolation state when the write data for this command is zero, or to the configuration state when the write data is not
zero. The pointer to the. SERIAL IDENTIFIER is reset. This register is write only.
0><04

Read only

RESOURCE DATA

00000000

Reading from this register reads the next byte of resource information from the EEPROM. The STATUS register must be
polled until its bit is reset before this register may be read.
Ox05

Bit
Ox06

Read only

STATUS

A one-bit register that, when set, indicates it is okay to read the next data byte from the
RESOURCE DATA register.
Readiwrite

CARD-SELECT NUMBER

00000000

Writing to this register sets a card CSN, which is uniquely assigned after the serial identification process. This allows each
card to be individually selected during a Wake[CSN] command.
Ox07

Read/write

LOGICAL DEVICE NUMBER
This register specifies which logical device is being configured.

~TEXAS

INSTRUMENTS
2-360

POST OFACE BOX 655303 • DALLAS, TEXAS 75265

00 000000

TL16PNP100A
STANDALONE PLUG·AND·PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
PnP logical device control registers
The registers in Table 4 are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus.
Table 4. PnP Logical Device Control Registers
ADDRESS PORT
VALUE
Ox30

READIWRITE
CAPABILITY

POWER UP

Readlwrite

00000000

This register controls whether the logical device is active on the bus.
This is reserved and must be set to zero.
Bit<7:1>
If set, activates the logical device.
Bit
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, 110 range check
must be disabled.
Ox31

110 RANGE CHECK

Readlwrite

00000000

This register is used to perform a conflict check on the 110 port range programmed for use by the logical device.
Bit<7:2>
This is reserved and must be set to zero.
If set, I/O range check is enabled. 110 range check is only valid when the logical device is inactive.
Bit
If set, the logical device responds to 110 reads to its assigned 110 range with a Ox55 when
Bit
110 range check is in operation. If clear, the logical device responds with a OxAA.

PnP logical device configuration registers
The registers in Table 5 are repeated for each logical device and are used to program the ISA bus resource use
of the device.
Table 5. PnP Logical Device Configuration Registers
ADDRESS PORT
VALUE
0><60

110 PORT BASE ADDRESS [15:8)

READIWRITE
CAPABILITY

POWER UP

Read/write

This register indicates the selected 110 lower limit address bits [15:8) for 110 descriptor O. When the device is activated,
if there is an address match to register Ox61 and an address match to this register, a chip select is generated to the logical
device.
Bits 15-10 are not supported, since the logical device uses 10-bit address decoding.
Bit<7:2>
Address bits 9 and 8 are indicated here.
Bit
0x61

110 PORT BASE ADDRESS [7:0)

Read/write

00000000

This register indicates the selected 110 lower limit address b~s [7:0) for 110 descriptor O. When the device is activated, if
there is an address match to register Ox60 and an address match to this register, a chip select is generated to the logical
device.
Address bits 7-0 are indicated here.
Bit<7:0>
Ox70

INTERRUPT REQUEST LEVEL SELECT

Readlwrite

0000

This register indicates the selected interrupt level.
Select the interrupt level. This device uses 6 interrupts from IRQ3 to IRQ7 and IRQ9.
Bit<3:0>
Ox71

INTERRUPT REQUEST TYPE

Readlwrite

0000

This register indicates which type of interrupt is used for the selected interrupt level.
Bit<7:2>
This is reserved.
Level, where 1 high, 0 low
Bit
Type, where 1 level, 0 edge
Bit

=
=

Ox74

=
=

DMA CHANNEL SELECT 0

Read only

00000100

Read only

00000100

This register has a value of 4 to indicate that DMA is not supported.
Ox75

DMA CHANNEL SELECT 1
This register has a value of 4 to indicate that DMA is not supported.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-361

TL16PNP1 DDA
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
EEPROM
The TL16PNP100A has been designed to interface with the ST93C56/66 EEPROM eSGS-Thomson) Dr an
equivalent. The EEPROM provides the block size for each device and the PnP resource data.

memory organization
The EEPROM should be organized as 128/255 words times 16 bits, so its ORG terminal should be connected
to Vee or left unconnected. The EEPROM memory organization is shown in Table 6.
Table 6. EEPROM Memory Organization
EEPROM
LOCATION

...- - - - - - - BIT LOCATION ---------+~

15 14 13

X 000

PnP Resource Data

12~255~

___________________

EEPROM READ (see Figure 8 and Figure 9)
This device only supports read transactions. The READ op code instruction (10) must be sent to the EEPROM.
The op code is then followed by an 8-bit-long address forthe 16-bit word. The READ op code with accompanying
address directs the EEPROM to output serial data on the EEPROM data terminals D and Q, which is connected
to the TL 16PNP1 OOA bidirectional serial data bus (SIO). Specifically, when a READ op code and address are
received, the instruction and address are decoded and the addressed EEPROM data is transferred into an
output shift register in the EEPROM. Each read transaction consists of a start bit, 2-bit op code (10), 8-bit
address, and 16-bit data. The TL 16PNP1 OOA does not accommodate the EEPROM autoaddress next-word
feature.

READ op code transfer (see Figure 8)
Initially, the EEPROM chip select signal, S, which connects to the TL 16PNP100AEEPROM chip select (CS),
is raised. The EEPROM data, D and Q, then sample the TL 16PNP1 OOA SIO line on the following rising edges
of the TL 16PNP100A serial clock, SCLK, until a 1 is sampled and decoded by the EEPROM as a start bit. The
TL 16PNP1 OOA SCLK signal connects to the EEPROM clock C. The READ op code (10) is then sampled on
the next two rising edges of SCLK. TL 16PNP1 OOA sources the op code at the falling edges of SCLK.

~TEXAS

2-362

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP100A
STANDALONE PLUG·AND·PLAY (PnP) CONTROLLER
SLLS200B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
READ op code transfer (continued)
tw(SClKH)
C

(SClK)

(CS) _ _ _ _ _..J
td2

D/Q _____
(SIO)

~~t---.t

I
II

tpd1

Start

Op Code Input

=1 \

I
I
14

Op Code Input

r--

=0 I[

~
Op Code Input
~
NOTE A: The corresponding TL16PNPl OOA terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together through 2-kO resistor.
~ Start

Figure 8. READ Op Code Transfer

READ address and data transfer (see Figure 9)
After receiving the READ op code, the EEPROM samples the READ address on the next eight rising edges of
SCLK. The device sources the address at the falling edge of SCLK. The EEPROM then sends out a dummy
o bit on the D/Q line, which is followed by the 16-bit data word with the MSB first. Output data changes are
triggered by the riSing edges of SCLK. The data is also read by the TL16PNP1 OOA on the rising edges of SCLK.

S
(CS)

(:.: ::x
I

td2

tpd1

x:::::x
Address Input

'\
I

-.J IfI
I

1''''':'1---

tpd2

I)
1

x::::::x

Data Output

ld3--ti 4-

»)-11- ~

NOTE A: The corresponding terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs are tied together
through 2-kO resistor.

Figure 9. READ Address and Data Transfer

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-363

2·364

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B-MARCH 1995 - REVISED MARCH 1996

• PnP Card Autoconfiguration Sequence
Compliant
• External Terminal-to-Bypass PnP
Autoconfiguration Sequence
• In UART Bypass Mode, the Stand-Alone
PnP Controller is Configured With One
Logical Device
• Provides 10-lnterrupts IRQ3-IRQ7,
IRQ9-IRQ12,IRQ15
• Simple 3-Pin Interface to SGS-ThomsonTM
EEPROM 2K14K ST93C56/66
• High Output Current Drive. No External
Buffer Needed for Data and Interrupt
Signals
• Programmable Auto-RTS and Auto-CTS
• In Auto-CTS Mode, CTS Controls
Transmitter
• In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
• The Serial and Modem Control Outputs
Drive a 1-Meter RJ11 Cable Directly if
Equipment Is on the Same Power Drop
• Capable of Running With All Existing
TL 16C450 Software
• After Reset, All Registers Are Identical to
the TL16C450 Register Set
• Clock Prescalar Allows 22-MHz Oscillator
Clock to be Divided by 12, 6, 3, or 1
• In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 16 -1) and Generates an Internal16x
Clock

• On-Chip 1/0 Port Address Decoding
• In PnP Bypass Mode, 6 External Terminals
Configure the VO Base Address and
Interrupt Mapping
• Adds or Deletes Standard Asynchronous
Communication Bits (Start, Stop, and
Parity) to or From the Serial Data Stream
• Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
• Programmable Serial Interface
Characteristics:
- 5-, 6-, 7-, or 8-Bit Characters
- Even-, Odd-, or No-Parity-Bit Generation
and Detection
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1 Mbit Per
Second)
• False Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Outputs Provide TTL Drive for
Bidirectional Data Bus and Interrupt Lines
• Line Break Generation and Detection
• Internal Diagnostic Capabilities:
- Loopback Controls for Communications
Link Fault Isolation
- Break, Parity, Overrun, and Framing
Error Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Transmitter and Receiver Run at the Same
Speed
• Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation for the Internal ACE
• Available in 68-Pin PLCC

description
The TL 16PNP550A is a functional upgrade of the TL 16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL 16C450. Functionally equivalent to the TL 16C450 on power up
(character or TL 16C450 mode), the TL 16PNP550A, like the TL 16C550C, can be placed in an alternate mode
(FIFO mode). This relieves the CPU of excessive software overhead by buffering received and transmitted
characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status

SGS·Thomson is a trademark of SGS·Thomson Incorporated.

~~~~~t~~~o~':1! si~~f~~~~~si~~~~~~r~! ~: Ie~~~~~~~~m~~f~

standard warranty. Production processing does not necessarily include
testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·365

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED M).RCH 1996

description (continued)
per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature that can
significantly reduce software overload and increase system efficiency by automatically controlling serial data
flow using RTS output and CTS input signals.
The TL 16PNP550A responds to the plug-and-play (PnP) autoconfiguration process. The autoconfiguration
process puts all PnP cards in a configuration mode, isolates one PnP card at a time, assigns a card select
number (CSN), and reads the card resource data structure fromthe EEPROM. After the resource requirements
and capabilities are determined for all cards, the autoconfiguration process uses the CSN to configure the card
by writing to the configuration registers. The TL 16PNP550A only implements configuration registers for I/O
applications with one logical device and no direct memory access (DMA) support. Finally, the process activates
the TL 16PNP550A card and removes itfrom configuration mode. Afterthe configuration process, the ACE starts
responding to industry standard architecture (ISA) bus cycles. This device can also be configured to bypass
the PnP autoconfiguration sequence. In this mode the TL 16PNP500A can be configured to select the COM port
address and IRQ level. In the UART bypass mode, the UART is disabled and this device is configured to be a
stand-alone PnP controller that supports one logical device and no DMA support.
The TL 16PNP550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE operation. Reported status information includes the type of transfer operation in progress, the status
of the operation, and any error conditions encountered.
The TL 16PNP550A includes a clock prescalar that divides the 22-MHz input clock by 12, 6, 3, or 1. The prescalar
output clock is fed to the programmable baud rate generator, which is capable of dividing this clock by divisors
from 1 to (2 16 -1).

~TEXAS

INSTRUMENTS
2-366

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (Pn~tt9~B~!~C!ge~5~~Y!S~D~~R1~~9~

00
01
02
03
GNO
04
05
06
07
IRQ1S
IRQ3
IRQ4
Vee
IRQS
IRQ6
IRQ7
IRQ9

9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
0
11
59
12
58
13
57
14
56
15
55
16
54
17
53
18
52
19
51
20
50
21
49
22
48
23
47
24
46
25
45
26
44
V~~~~~~M~~~~~~~Qa

CTS
OCO
EEPROM
SIO
Vee
SCLK
CS
PNPSO
PNPS1
SOUT
OTR
GNO
EXINTR
AEN
RESETORV
A11

O-NrOO-~~~~~u~oomo
---Uz«
« « u~« < ~
<

000

Q;Q;Q;

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-367

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY IPnP\ AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MXRCH 1~96

functional block diagram

ClK From Prescalar

/ 32-34

AO_A2
3
TolSABus

{

lOW
_
lOR

SIN

151

SOUT

149

RTS

160

10-13,15-18
00-07

ACE

CTS

150

OTR

159

CS_IN

To External {
logical Device

INTRPT

162

OSR

EXINTR
}
UARTBYPASS

CS 30

I 32-38 40-44

8 I 10-13,15-18

00-07
8

RESETORV

lOW
lOR
I

IRQ 3-7, 9-12, 15

PnP
Controller

AEN

SClK
SIO

EEPROM
PNPS1
PNPSO

19-21 23-29
66

67,
1-4
68 4
2

UI
UI

If
~
D-

Z
D-

iI
Z

XIN

iI
Z

!:l
Oivldeby
12,6,3,1

~. Oscillator J
22 MHz

(prescalar)

~TEXAS

2-368

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

}

~ ~~PROM

XOUT

To External
logical Oevice

UARTBYPASS~

AO-A11

TolSA
Bus

OCO

161

To RS-232
Transceivers

ClK
(to the ACE)

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTO FLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

ACE functional block diagram
r-Internal ~
DetaBus
.....

S
e
I
e

Receiver ~
FIFO

'"'r18-15,13-10
0(7-0)

Data
Bus
Buffer

Receiver
Shift
Register

Receiver
Buffer
Register

Select
and
Control
Logic

I Transmitter ~
I FIFO

Transmitter
Holding
Register

Supply

i...++-

--+-

S'
e
I
e
c
t

L.8

Transmitter
Shift
Register

SOUT

Autoflow
Contr01
(AFE)

Transmitter
Timing and
Control

Modem
Status
Register

Interrupt
Enable
Register

Interrupt
Control
logic

Interrupt
Identification
Register

FIFO
Control
Register

Modem
Control
Register

ClK ---+(from
Prescalar)

Baud
Generator

...

Line
Status
Register

-4-

Vcc --+vss --+-

Divisor
Latch (MS)

-;;;i
~

f----

Divisor
Latch (LS)

MR
(from

Receiver
Timing and
Control

-+-

AO ~
A1 ~

CS
(from

SIN

f-+-

Line
Control
Register

Modem
Control
logic

60
CTS
50
DTR
62
DSR
.... 59
DCD
61
'

INTRPT

I
..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-369

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
~~!~B~h~~~~~~~rv~~!M{~~~~9~ND AUTOFLOW CONTROL
Terminal Functions
TERMINAL
NO.
FN

110

DESCRIPTION

AO-A6
A7-All

32-38
40-44

12·bit ISA address terminals. All 12 bits are used during PnP autoconfiguration sequence. After
autoconfiguration, bits AO-A2 select the ACE registers and bits A3-A9 are used in the address decoding
to generate chip select for the device.

ACONFIGO,
ACONFIGI

67,68

Address configure. In PnP bypass mode, both ACONFIGO and ACONFIGI configure the COM port base
address.

NAME

AEN

Address enable. AEN disables the ACE and PnP controller during DMA.

Chip select. CS is a 3-state output. It controls the activity of the EEPROM. A 100
connected to this terminal.

Chip select. CS is the 1/0 chip select for the logical device.

CTS

Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the
modem status register (MSR). Bit 0 (~CTS) of the modem status register indicates that this signal has
changed states since the last read from the MSR. When the modem status interrupt is enabled when CTS
changes states and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.

10-13
15-18

1/0

Data bus. DO - D7 are eight data lines with 3-state outputs that provide a bidirectional path for data, control,
and status information between the ACE and the CPU. The output drive sinks 24 mA at 0.4 V and sources
12 mA at 2.4 V.

DCD

Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of
the MSR. Bit 3 (~DCD) of the MSR indicates that this signal has changed levels since the last read from the
MSR. When the modem status interrupt is enabled when DCD changes states, an interrupt is generated.

DSR

Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
MSR. Bit 1 (~DSR) of the MSR indicates this signal has changed states since the last read from the MSR.
If the modem status interrupt is enabled when the DSR changes states, an interrupt is generated.

DTR

Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in its active level by setting the DTR bit of the MCR. DTR is placed in its
inactive level either as a result of a master reset, during loop mode operation, or clearing the DTR bit.

EEPROM

1/0

EEPROM access. EEPROM is a 3-state bidirectional signal. When it is pulled low, either the TL 16PNP550A
or controller is accessing the EEPROM. A 100 IlA pullup circuit is connected to this terminal.

EXINTR

External interrupt. During UARTBYPASS mode, the external logical device interrupt (EXINTR) is mapped
to the configured IRQs.

DO-D3
D4-D7

GND
ICONFIGOICONFIG3

14,31,
48,65

IJ.A pulldown circuit is

Ground (0 V). These four GND terminals must be tied to ground for proper operation.

1-4

lOR

Read input. When lOR is active while the ACE is selected, the CPU is allowed to read from the ACE.

lOW

Write input. When lOW is active while the ACE is selected, the CPU is allowed to wrtte to the ACE.

IRQ3-IRQ4
IRQ5-IRQ7
IRQ9-IRQI2
IRQ15

20-21
23-25
26-29
19

3-state interrupt requests. When active (high), IRQx informs the CPU that the ACE has an interrupt to be
serviced. Four conditions that cause an interrupt to be issued are: a receiver error, received data is available
or timed out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt.
IRQx is generated when one or all of the above conditions occur and the value of bits 0-3 in the interrupt
request level (Ox70) is equal to x (of IFlQx). The output drive sinks 24 mA at 0.4 V and sources 12 mA at
2.4 V.

PNPBYPASS

Bypass PnP configuration sequence. When PNPBYPASS is tied to GND, the PnP autoconfiguration
sequence is bypassed.

52-53

PNPS1PNPSO
RESETDRV

IRQ configure. In PnP bypass mode, ICONFIGO, ICONFIG2, and ICONFIG3 configure the required IRQ.

PnP internal states. See the PNPSI and PNPSO truth table in the PnP states section of this document.
Reset. When active (high), RESETDRV clears most ACE registers and puts the ACE in wait for key state.
The CSN is reset to OxOO. All configuration registers are set to their power-up values.

~TEXAS

INSTRUMENTS
2-370

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTO FLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

Terminal Functions (Continued)
TERMINAL
NO.
FN

1/0

DESCRIPTION

Ring indicator. RI is modem status signal. Its condition can be checked by reading bit 6 (RI) of the MSR. Bit
2 (TERI) of the MSR indicates that Ai has transitioned from a low to a high level since the last read from the
MSR. If the modem status interrupt is enabled when this transition occurs, an interrupt is generated.

RTS

Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data.
RTS is set to its active level low by setting the RTS modem control register bit and is set to its inactive (high)
level either as a result of a master reset or during loop mode operations or by clearing bit 1 (RTS) of the MCR.
In auto-RTS mode, RTS is set to its inactive level by the receiver threshold control logic.

SCLK

3-state EEPROM clock. SCLK is a 3-state EEPROM clock output that controls address and data transfer.
A 100 !IA pulldown circuit is connected to this terminal.
Serial data. SIN is input from a connected communications device.

NAME

SIN

SIO

1/0

3-State bidirectional EEPROM serial data bus. During outpU1 mode, 510 provides only read opcode and
address which are sourced at the falling edge of SCLK. During inpU1 mode it provides the data which is
captured at the rising edge of SCLK. A 100 !IA pulldown circuit is connected to this terminal.

SOUT

Composite serial data output to a connected communication device. SOUT is set to the marking (high) level
as a result of master reset.

UARTBYPASS

UART bypass. When it is active, UARTBYPASS disables the UART and the TL 16PNP550A acts as a PnP
stand-alone controller.

VCC

5,22,
39,56

XIN,XOUT

63,64

5-V supply voltage.
1/0

External clock. XIN and XOUT connect the TL 16PNP550A to the main timing reference, a 22-MHz clock or
crystal.

detailed description
autoflow control
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the input must be active before the
transmitter FIFO can emit data (see Figure 1). Auto-RTS becomes active when the receiver needs more data
and notifies the sending serial device (see Figure 1). When RTS is connected to CTS, data transmission does
not occur unless the receiver FIFO has space for the data; thus, overrun errors are eliminated if ACE1 and ACE2
are TL 16PNP550As with enabled autoflow control. If autoflow control is not enabled; overrun errors occur when
the transmit data rate exceeds the receiver FIFO read latency.
ACE2

ACE1
SIN

SOUT

D7-DO-+.....~

07-00
SOUT

SIN

Figure 1. Autoflow Control Example (Auto-RTS and Auto-CTS)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-371

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
~L'!~B~h~~:~~~;rv~!M~~!~l9~ND AUTOFLOW CONTROL
auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
and is linked to the programmed receiver FIFO trigger level. When the receiver FIFO level reaches a trigger level
of 1, 4, or 8, (see Figure 3), RTS is deasserted. With trigger levels of 1, 4, and 8, the sending ACE may send
an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register.
When the trigger level is 14 (see Figure 4), RTS is deasserted after the first data bit of the sixteenth character
is present on the SIN line. RTS is reasserted when the receiver FIFO has at least one available byte space.
auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, it sends the next
byte. To stop the transmitter from sending the following byte, CTS must be released before the middle of the
last stop bit that is currently being sent (see Figure 2). The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, changes of CTS level do not trigger host interrupts because the device
automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in the
transmit FIFO and a receiver overrun error may result.
enabling autoflow control and auto-CTS
Autoflow control is enabled by setting moc;lem control register bits 5 (autoflow enable or AFE) and 1 (RTS) to
1. Autoflow incorporates both auto-RTS and auto-CTS. If only auto-CTS is desired, bit 1 in the MCR should be
cleared (this assumes a control signal is driving CTS).
SOUT , S t a r t

1Bits 0-71 Stop rj~Start 1Bits 0-71 Stop

r/l-J- - - - . . \ Start

1Bits 0-71 Stop

__~____~__________--JI
NOTE A: When crs is low, the transmiiter keeps sending serial data out. If CTS goes high before the middle of the last stop bit of the current
byte, the transmiiterfinishes sending the current byte but it does not send the next byte. When CTS goes from high to low, the transmitter
begins sending data again.

Figure 2. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.

SIN ~~
RTS

Start

Ir--Byt-e-N""'"TI-St-o-p-nr\~:T~:-~I:o~-l
L _ _ _ _ _ _ _ _ _ _ _ -'

Start

Byte

1Stop

r~
.~,
I ~~4-------)

_ _ _ _ _-----J/

(RDRBR)----------~

L _N+11
_ _ -'

NOTES: A. N = receiver FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.

Figure 3. RTS Functional Timing Waveforms, Receiver FIFO Trigger Level

~TEXAS

INSTRUMENTS
2-372

POST OFFICE BOX 655303 • DAUAS. TEXAS 75265

=1, 4, or 8 Bytes

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

enabling autoflow control and auto-CTS (continued)

SIN

RD
(RD RBR)
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receiver FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
e. When the receiver FIFO is full, the first receiver buffer register read reasserts RTS.

Figure 4. RTS Functional Timing Waveforms, Receiver FIFO Trigger Level = 14 Bytes
flow control and interrupt
When flow control is enabled, bit 0 (~CTS) of the modem status register does not cause a modem status
interrupt. The ACE accommodates a 1-Mbaud serial rate (16-MHz input clock) so that a bit time is 1 itS, and
a typical character time is 10 its (start bit, 8 data bits, and a stop bit).
The TL 16PNP550A ACE includes a programmable, on-board, baud rate generator that divides a reference
clock input by 1 to (2 16 -1) for producing a 16 x clock to drive the internal transmitter logic. Provisions are
included to use this 16 x clock to drive the receiver logic. The ACE includes complete modem control capability
and a processor interrupt system that may be software tailored to minimize the system overhead for handling
the communications link.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 7 V
Input voltage range at any input, VI ................................................... -0.5 V to 7 V
Output voltage range, Vo ........................................................... -0.5 V to 7 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 10 seconds, T e: FN package .......................................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions
Supply voltage, Vee
High-level input voltage, VIH
Low-level input voltage, VIL
Operating free-air temperature, TA

MIN

NOM

MAX

UNIT

4.75

5.25

Vee

-0.5

0.8

°e

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-373

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER

MIN

TEST CONDITIONS

VOH*

High-level output voltage

IOH=-12 rnA

VOL*

Low-level output voltage

10L= 24 rnA

VOH

High-level output voltage

10H = -4 rnA (see Note 2),
VCC =0.8V

VOL

Low-level output voltage

10Z

TYPt

MAX

UNIT
V

VCC-O.B
0.5

10L = 4 rnA (see Note 2)

0.5

Input current

VCC=5.25 V,
VI = 0 to 5.25 V,

±1

High-impedance-state output current

VCC=5.25 V,
VSS=O,
Va = 0 to 5.25 V,
Pullup and pulldown circuits are off

±10

ICC

Supply current

VCC = 5.25 V,
TA = 25'C,
SIN, DSR, DCD, CTS, and Ai at 2 V,
All other inputs at O.B V,
Clock at 4 MHz (no crystal used),
No load on outputs,
Baud rate = 50 kbiVs

rnA

Ci(CLK)

Clock input capacitance

Co(CLK)

Clock output capacitance

VSS=O,
All other terminals floating

VCC = 0,
VSS=O,
f = 1 MHz,
TA = 25'C,
All other terminals grounded

Input capacitance

Output capacitance

f(XIN-XOUT)

Oscillator speed (XIN and XOUT)

VCC-0.8

MHz

t All typical values are at VCC = 5 V and TA = 25'C.
* These parameters apply only for IRQx and 07 -DO.
NOTE 2: These parameters apply for all outputs except XOUT, IRQx, and 07 -DO.

clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOLS

PARAMETER

TEST
CONDITIONS

MIN

MAX

UNIT

td1

Delay time, chip select (CS) high to clock (SCLK) high

tSHCH

td2

Input valid to clock (SCLK) high

tDVCH

100

tpd1

Propagation delay time, clock (SCLK) high to input transition
(SIO)

tCHDX

100

tpd2

Propagation delay time, clock (SCLK) high to output valid
(SIO)

tCHQV

tpd3

Propagation delay time, .clock (SCLK) low to chip select
transition (CS)

tCLSL

td3

Delay time, chip select (CS) low to output Hi-Z (SIO)

tSLQZ

tw(SCLKH)

Pulse duration, clock (SCLK) high to clock (SCLK) low
(see Note 3)

tCHCL

250

tw(SCLKL)

Pulse duration, clock (SCLK) low to clock (SCLK) high
(see Note 3)

tCLCH

250

fclock

Clock frequency (SCLK) (see Note 4)

FCLK

0.5

NOTES:

See Figure 18
and Figure 19

2
100

0.68

ns
clock
periods
ns

MHz

3. The ST93C56 chip select, S, must be brought low for a minimum of 250 ns (tSLSH) between consecutive Instruction cycles according
to the ST93C56 specification.
4. The SCLK signal is attained by internally frequency dividing the XIN signal by 32.

~TEXAS

INSTRUMENTS
2-374

500

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B- MARCH 1995- REVISED MARCH 1996

system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOL

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

tcR

Cycle time, read (tw7 + td8 + td9)

lew

Cycle time, write (tw6 + td5 + td6)

tw1t

Pulse duration, XIN high

tXH

Figure 5

f = 16 MHz maximum

tW2t

Pulse duration, XIN low

tXl

Figure 5

f = 16 MHz maximum

tW6

Pulse duration, write strobe (lOW)

tWR

Figure 6

tw7

Pulse duration, read strobe (lOR)

tRD

Figure 7

tW8

Pulse duration, master reset

tMR

!IS

tsu3

Setup time, data valid before IOWt

tDS

Figure 6

th1

Hold time, chip select (CS) valid after address (AO
- A2) becomes invalid

tCH

Figure 6,
Figure 7

th2

Hold time, data valid after lowi

tDH

Figure 6

5
From the first rising
edge of XIN after
address valid

td4

Delay time, chip select (CS) valid after address
valid (AO - A2)

td5

Delay time, address valid (AO - A2) before IOWt

tAW

Figure 6

td6

Delay time, address valid (AO - A2) before IORt

tAR

Figure 7

td7

Delay time, chip select (CS) valid to data valid
(07-00)

tCSVD

Figure 7

CL = 75 pF

td8

Delay time, IORt to floating data (07 - DO)

tHZ

Figure 7

Cl= 75 pF

td9

Delay time, EXINTRt or EXINTRt to IRQxi or
IRQxt

t This only applies when PNPBYPASS

tCSRW

tplH

Figure 8

low.

oscillator cell maximum switching characteristics,
PARAMETER

Figure 6,
Figure 7

From the first rising
edge of XIN after
address invalid

FROM
(INPUT)

TO
(OUTPUT)

XIN

XOUT

Vee = 4.75 V, TJ = 115°C

INTRINSIC
DELAY
(ns)

DELTA
DELAY
(ns/pF)

-0.25

0.300

-0.24

0.206

tpHl

DELAY (ns)
CL=15pF

CL =50 pF

CL=85pF

CL = 100 pF

4.26

14.76

25.26

29.77

2.85

10.06

17.27

20.36

Output rise time, XOUT

5.83

21.15

36.47

43.04

Output fall time, XOUT

3.76

13.50

23.24

27.41

baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL 75 pF (see Figure 5)

PARAMETER

ALTERNATE
SYMBOL

TEST CONDITIONS

MIN
50

tW3t

Pulse duration, PNPS1 low

tlW

f = 16 MHz, ClK + 2

tw4t

Pulse duration, PNPS1 high

tHW

f = 16 MHz, ClK + 2

td1t

Delay time, XINt to PNPS1t

Delay time, XINt t to PNPS1 t
lti2 t
t This only applies when PNPBYPASS IS low.

MAX

UNIT

tBLD

tBHD

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-375

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
~~!~B~h!!~H-e~~;rv~~!M~~~~~9~ND AUTO FLOW CONTROL
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 5)
PARAMETER

ALTERNATE
SYMBOL

FIGURE

td10

Delay time, stop (SIN) to set INTRPT or read
RBR to LSI interrupt (IRQx)

tSINT

Figure 9,
Figure 10,
Figure 11

td11

Delay time, read RBRlLSR (lOR) to reset
INTRPT (IRQx)

tRINT

Figure 9,
Figure 10,
Figure 11

NOTE 5:

TEST CONDITIONS

MIN

MAX

UNIT

RCLK
cycle

CL=75 pF

In the FIFO mode, the read cycle (RC) = 425 ns (min) between reads of the receiver FIFO and the status registers (interrupt identification
register or line status register).

transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Figure 12)
ALTERNATE
SYMBOL

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

td12

Delay time, initial write (IRQx) to transmit start (SOUT)

tlRS

baudout
cycles

td13

Delay time, start (SOUT) to INTRPT (IRQx)

tSTI

baudout
cycles

td14

Delay time, lOW (WR THR) to reset INTRPT (IRQx)

tHR

td15

Delay time, initial write (lOW) to INTRPT (THREt) (IRQx)

tSI

id16

Delay time, read IIRt (lOR) to reset INTRPT (THREt)
(lRQx)

tlR

CL=75 pF
16
CL = 75 pF

baudout
cycles

t THRE = transmitter holding register empty; IIR = interrupt identification register.

modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, CL = 75 pF
PARAMETER

ALTERNATE
SYMBOL

FIGURE

MIN

MAX

UNIT

td17

Delay time, WR MCR (lOW) to output (RTS, DTS)

1M DO

Figure 13

td18

Delay time, modem interrupt (CTS, DSR, DCD/RI) to set INTRPT
(IRQx)

tSIM

Figure 13

td19

Delay time, RD MSR (lOR) to reset INTRPT (IRQx)

tRIM

Figure 13

td20

Delay time, CTS low to SOUT.j,

Figure 14

baudout
cycles

td21

Delay time, receiver threshold byte (SIN) to RTSt

Figure 15

baudout
cycles

td22

Delay time, read of last byte in receiver FIFO (lOR) to RTS.j,

Figure 15

baudout
cycles

td23

Delay time, first data bit of 16th character (SIN) to RTSt

Figure 16

baudout
cycles

td24

Delay time, RD RBR (lOR) .j, to RTS.j,

Figure 16

baudout
cycles

-!!1
TEXAS
INSTRUMENTS
2-376

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B- MARCH 1995- REVISED MARCH 1996

PARAMETER MEASUREMENT INFORMATION
.-------------------N---------------------+~I

'------'Ir-----ILI

XIN

PNPSl
(1/1)

I~_---I

PNPS1
(1/3)

r---------~)'~j----------~

----,

PNPSl
(lIN)
(N > 3)

I~----------~

~-----

~ 2 XIN Cycles ~

J<..rI It - - - - - - - (N-2) XIN Cycles -----i~~1

NOTE A: When PNPBYPASS - 0, the PNPS1 terminal is acting as the BAUDOUT. The above timing assumes
that the prescalar value is one.

Figure 5. Baud Generator Timing Waveforms

XIN

AO-A2

IJl-fUl--

"'~'j
50%

>:< :

1 ~
------~I~~I

----I>i 1<1-- thl

Ir----,50%

Valid

I.~

tw6

50%\

Active

--------~I
lOW

5_0_%_ _ _ __

td4

: 50%\ .
td5

x~;

Valid Address

1.------------

, { 50%

j4---- tsu3

~
07-00 -----------------il\
NOTE A: The above timing assumes that AEN

Valid Data

th2

~
/'>--- - - - - -

=O.

Figure 6. Write Cycle Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-377

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
~~!~B~h~~:e~~;~~t!M{~~~~9~ND AUTOFLOW CONTROL
PARAMETER MEASUREMENT INFORMATION

XIN

AO-A2

~~r,...()----\(JJLfl-fl--'~
50%):<1...-'-:_ _ _V_a_lid_A_d_dr_es_s_ _

I
~ Id4
- - -...., -----... I
CS

50%\

50%

-----.I ~ Ih1
I

Valid

Id6 -11~"--t.oI
TERMINAL

ACONFIG <1 :0>
TERMINAL

PnP controlier and logical device (ACE)

Stand-alone PnP Controlier

ACE TL 16C550C only

Active

Manufacturer test mode:!:

t X = Irrelevant, 0 = low level, 1 = high level
:I: During manufacturer test mode, the oscillator clock is disabled. This mode is used by the manufacturer for test only.
Connecting the PNPBYPASS terminal to Vee enables the PnP autoconfiguration sequence. When PnP is
enabled, the ACONFIG<1 :0> and ICONFIG<3:0> are irrelevant and should be tied to GND or Vee.
In the stand-alone PnP controller mode, the controller responds to the autoconfiguration sequence and supports
one logical device, one 1/0 address, one interrupt, and no DMA. The address decoder only decodes eight
contiguous locations. During this mode, the UART is disabled and CS and EXINTR terminals become active.
The UART input terminals should be tied to either Vee or GND to avoid floating input terminals.
When PnP is disabled or bypassed, the PNPBYPASS terminal is tied to GND and the configuration in Table 2
applies.

Table 2_ PnP Disabled or Bypassed Configuration
ACONFIG<1 :0>

COM

110 BASE ADDRESS

COM1

3F8-3FF

COM2

2F8-2FF

COM3

3E8-3EF

COM4

2E8-2EF

The decimal value X of ICONFIG<3:0> content enables the corresponding IRQx. For example,
ICONFIG<3:0> = 0011 enables IRQ3 (Table 3).

Table 3_ ICONFIG to IRQx
IRQx

ICONFIG

IRQx

ICON FIG

0000

N/A

1000

N/A

0001

N/A

1001

IR09

0010

N/A

1010

IR010

0011

IR03

1011

IR011

0100

IR04

1100

IR012

0101

IR05

1101

N/A

0110

IR06

1110

N/A

0111

IR07

1111

IR015

~TEXAS

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2-383

PRINCIPLES OF OPERATION

PnP card configuration sequence
The PnP logic is quiescent on power up and must be enabled by software. The following sequence configures
the PnP card:
1.

The initiation key places the PnP logic into configuration mode through a series of predefined writes to
the ADDRESS port (see autoconfiguration ports section).

A serial identifier is accessed bit serially and isolates the Industry Standard Architecture (ISA) cards.
Seventy-two READ_DATA port reads are required to isolate each card.

Once isolated, a card is assigned a handle [card select number (CSN)] that later selects the card. This
assignment is accomplished by programming the CSN.

The PnP software then reads the resource data structure on each card. When all resource capabilities
and demands are known, a process of resource arbitration is invoked to determine resource allocation
for each card.

All PnP cards are then activated and removed from the configuration mode. This activation is
accomplished by programming the ACTIVE register.

PnP autoconfiguration ports
Three 8-bit ports (see Table 4) are used by the software to access the configuration space on each PnP ISA
card. These registers are used by the PnP software to issue commands, check status, access the resource data
information, and configure the PnP hardware.
The ports have been chosen so as to avoid conflicts in the installed base of ISA functions, while at the same
time minimizing the number of ports needed in the ISA I/O space.

Table 4. Autoconfiguration Ports
PORT NAME
ADDRESS

LOCATION

TYPE

Ox0279 (printer status port)

Write only

WRITE_DATA

OxOA79 (printer status port + Ox0800)

Write only

READ_DATA

Relocatable in range Ox0203 to Ox03FF

Read only

The PnP registers are accessed by first writing the address of the desired register to the ADDRESS port,
followed by a read of data from the READ_DATA port, or a write of data to the WRITE_DATA port. Once
addressed, the desired register may be accessed using the WRITE_DATA or READ_DATA ports.
The ADDRESS port is also the destination of the initiation key writes.
The address of the READ_DATA port is set by programming the SET RD_DATA PORT register. If a card cannot
be isolated for a given READ_DATA port address, the READ_DATA port address is in conflict. The READ_DATA
port address must then be relocated and the isolation process begun again. The entire range between Ox0203
and Ox3FF is available; however, in practice it is expected that only a few address locations are necessary
before the software determines that no PnP cards are present

~TEXAS

INSTRUMENTS
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TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B- MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
PnP registers
PnP card standard registers are divided into three parts: card control, logical device control, and logical device
configuration. There is exactly one of each card control register on each ISA card. Card control registers are
used for global functions that control the entire card (see Table 5). Logical device control registers and logical
device configuration registers are repeated for each logical device. Since the TL 16PNP550A has one logical
device (ACE) and it is intended only for I/O applications, not all the configuration registers are implemented.
Table 5. PnP Card Control Registers
ADDRESS PORT
VALUE
OxOO

READIWRITE
CAPABILITY

POWER UP

Write only

0000 00 00

Writing to this location modifies the address port used for reading from the PnP ISA card. Writing to this register is
only allowed when the card is in the isolation state.
Bit<7:0>
Become I/O port address bits [9:2].
Ox01

SERIAL ISOLATION

Read only

00000000

A read to this register causes a card in the isolation state to compare one bit of the board ID.
Ox02

CONFIGURATION CONTROL

Write only

000

This 3-bit register consists of three independent commands, which are activated by setting their corresponding
register bits. These bits are automatically cleared by the hardware after the commands execute.
Bik2>
Setting this bit causes the card to clear its CSN and RD DATA port.
Bikh
Setting this bit causes the card to enter the wait for key state, but the card CSN is
preserved and the logical device (ACE) is unaffected.
BikO>
Setting this bit resets the logical device (ACE) configuration registers to their default
state and the CSN is preserved.
Ox03

WAKE[CSN]

Write only

00000000

A write to this register, if the write data [7:0] matches the card CSN, causes the card to go from the sleep state to
either the isolation state, if the write data for this command is zero, or the configuration state if the write data is not
zero. The pointer to the SERIAL IDENTIFIER is reset. This register is write only.
Ox04

RESOURCE DATA

Read only

00000000

A read from this address reads the next byte of resource information from the EPROM. The STATUS register must
be polled until its bikO> is set, before this register may be read.
Ox05

STATUS
BikO>

OX06

Read only

A 1-bit register that when set, indicates it is okay to read the next data byte from the RESOURCE
DATA register.

CARD SELECT NUMBER

Read/write

00000000

A write to this address sets a card CSN, which is uniquely assigned to this card after the serial identification process,
so each card may be individually selected during a WAKE [CSN] command.
Ox07

LOGICAL DEVICE NUMBER

Read

0000 00 00

This register has a read-only value of OxOO, since the card has only 1 logical device.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-385

PRINCIPLES OF OPERATION
PnP logical device control registers
The following registers are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus (see Table 6).
Table 6. PnP Logical Device Control Registers
ADDRESS PORT
VALUE
Ox30

READIWRITE
CAPABILITY

POWER UP

Read/write

00 00 0000

This register controls whether the logical device is active on the bus.
Reserved and must be cleared.
BiI<7:1>
Bit
When set. activates the logical device.
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, I/O range
check must be disabled.
Ox31

I/O RANGE CHECK

Read/write

00 00 00 00

This register performs a conflict check on the I/O port range programmed for use by the logical device.
Reserved and must be cleared.
Bit<7:2>
Bil
When set. I/O range check is enabled. I/O range check is only valid. when the logical device is
inactive.
When set, the logical device (an ACE in this case) responds to I/O reads of the logical device
Bit
(ACE) assigned I/O range with a Ox55 when I/O range check is in operation. When clear, the
logical device responds with a OxAA. This register is read/write.

PnP logical device configuration registers
These registers program the device ISA bus resource use (see Table 7).
Table 7. PnP Logical Device Configuration Registers
ADDRESS PORT
VALUE
Ox60

READIWRITE
CAPABILITY
Read/write

POWER UP
00

This register indicates the selected I/O upper limit address bits [15:8] for I/O descriptor O. When the device is
activated, if there is an address match to register Ox61 and an address match to this register, a chip select is
generated.
Bit<7:2>
Bits 15-10 are not supported, since the logical device uses la-bit address decoding.
Bit
Indicates address bits 9 and 8.
Ox61

I/O PORT BASE ADDRESS [7:0]

Read/write

00 00 00 00

This register indicates the selected I/O lower limit address bits [7:0] for I/O descriptor O. When the device is activated,
if there is an address match to register Ox60 and an address match to this register, a chip select is generated.
Bit<2:0>
Are not supported since the logical device has eight registers.
BiI<7:3>
Indicates address bits 7-3.
Ox70

INTERRUPT REQUEST LEVEL SELECT

Read/write

0000

This register indicates the selected interrupt level.
BiI<3:0>
Selectthe interrupt level. This device uses 10 interrupts from IRQ2 to IRQ7 and IRQ9 to IRQI2.
Ox71

INTERRUPT REQUEST TYPE

Read

00 00 00 11

This register indicates which type of interrupt is used for the selected interrupt level.
Are reserved.
Bit<7:2>
Bil
Is set to indicate active high.
BiI
Is set to indicate level sensitive.
Ox74

DMA CHANNEL SELECT a

Read only

00 00 0100

This register has a value of 4 to indicate that DMA is not supported.
Ox75

DMA CHANNEL SELECT 1

Read only

This register has a value of 4 to indicate that DMA is not supported.

~TEXAS

INSTRUMENTS
2-386

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

00000100

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B- MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

PnP terminal states
Terminals PNPS1 and PNPSO reflect the states of PnP logic when PNPBYPASS is set (see Table 8).

Table 8. PNPx Terminal States
PNPS1

PNPSO

0
0
1
1

0
1
0
1

PnPSTATE
WAIT FOR KEY
SLEEP
ISOLATION
CONFIGURATION

If the device leaves the wait-for-key state, it means the device is in configuration mode.
Please note, when PNPBYPASS
PNPSO.

= 0, BAUDOUT is monitored using PNPS1

and RXRDY is monitored using

EEPROM
The TL16PNP550A has been designed to interface with the ST93C56/66 EEPROM (SGS-Thomson) or
equivalent. The EEPROM provides the clock prescalar divisor and PnP resource data.

Table 9. EEPROM Memory Organization
EEPROM
LOCATION

X 000

...
15

BIT LOCATION
9
8
7

•
0

I I I I I I I I I I I I I I I
PnP Resource Data

X 128/255L..-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----'

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-387

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTO FLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
clock prescalar
The TL 16PNP550A includes a clock prescalar block. The block takes the 22-MHz input clock and divides it by
a divisor read from the EEPROM at address zero. After reset, the device reads the EEPROM content at address
zero. The 2 most significant data bits of the word (2 bytes) define the divisor value as show in Table 10.
Table 10_ Default Deviser Value
EEPROM LOCATION
000 (BITS 15 AND 14)

DIVISOR VALUE

1 (default)

The device monitors the EEPROM to check whether the divisor value has been updated or not. Read the
EEPROM interface section for more details in this mode. Note the EEPROM address location zero is reserved
for the divisor value.

EEPROM signal description (see Figure 17)
2

\,,--_3--J/

\1..--_----J/
5

During and after reset, the TL 16PNP550A gains access to EEPROM interface by asserting EEPROM (low).
The device reads the prescalar divisor value from address zero. After it receives the WAKE command, the
device starts receiving PnP resource data from address location 00x01 H.

After the device is configured and leaves the configuration mode (the device is activated and it is in the wait
for key state), the TL 16PNP550A releases the EEPROM interface by releasing signals EEPROM, SCLK,
SIO, and CS.

The on-board controller is accessing the EEPROM.

The TL 16PNP550A assumes the prescalar divisor value has been updated.

The TL 16PNP550A accesses the EEPROM by asserting EEPROM signal. It reads location 00 and updates
the prescalar divisor.

The TL 16PNP550A releases the EEPROM signal and SCLK, CS and 810 signals.

If the device enters the configuration mode again (leaves the wait for key state), it gains access directly to the
EEPROM after the EEPROM signal is released.
If the EEPROM is driven by an on-board controller and the TL 16PNP550A enters the configuration mode, it is
highly recommended that the controller release the EEPROM signal to allow the TL 16PNP550Ato gain control
of EEPROM. It is possible to deactivate and reconfigure the TL 16PNP550A when it enters the configuration
mode. PNPSO and PNPS1 terminals inform the controller when the TL 16PNP550A enters the configuration
mode.

~TEXAS

INSTRUMENTS
2-388

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SllS190B- MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
ISA Bus

A
SIO

Tl16PNP550A

_.. S

SCll<..

EEPROM

-.-

EEPROM

EEPROM
Interface
Control
(optional)

I I
CPU

NOTE A: It is recommended that a 2-kQ resistor be connected between D and Q terminals.

Figure 17. TL16PNP550A and EEPROM Interface

EEPROM READ
The TL 16PNP550A only supports read transactions. The READ op code instruction (10) must be sent into the
EEPROM. The op code is then followed by an address for the 16-bit word, which is 8-bits long. The READ op
code with accompanying address directs the EEPROM to output serial data on the EEPROM data terminal D/Q
which is connected to the TL 16PNP550A bidirectional serial data bus (SIO). Specifically, when a READ op code
and address are received, the instruction and address are decoded and the addressed EEPROM data is
transferred into an output shift register in the EEPROM. Each read transaction consists of a start bit, 2-bit op
code (10), 8-bit address, and 16-bit data. The TL 16PNP550A does not accommodate the EEPROM
auto-address next word feature.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-389

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLSI90B-MARCH 1995-REVISED M);RCH 1996

PRINCIPLES OF OPERATION
READ op code transfer (see Figure 18)
Initially, the EEPROM chip select signal, S, which is connected to the TL 16PNP550A EEPROM chip select (CS),
is raised. The EEPROM data, D/Q then samples the TL 16PNP550A (SIO) line on the following rising edges of
the TL 16PNP550A clock (SCLK), until a 1 is sampled and decoded by the EEPROM as a start bit. The
TL 16PNP550A (SCLK) signal is connected to the EEPROM clock, C. The READ op code (10) is then sampled
on the next two rising edges of SCLK. TL 16PNP550A sources the op code at the falling edges of SCLK.
tw(SCLKH)

C
(SCLK)

'--_...I

td1~

(C~ __________J;(r-+i----------------------~i----------(~~

td2

_____J

r--+-I--------~

+.1

Start

Op Code Input = 1 \

I
:
14--

Start

tpd1

Op Code Input = 0

Op Code Input

r--

NOTE A: The corresponding TL 16PNP550A terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together with a 2-kn resistor.

Figure 18. READ Op Code Transfer Waveforms

READ address and data transfer (see Figure 19)
After receiving the READ op code, the EEPROM samples the READ address on the next eight rising edges of
(SCLK). The device sources the address at the falling edge of SCLK. The EEPROM then sends out a dummy
o bit on the D/Q line, which is followed by the 16-bit data word with the MSB first. Output data changes are
triggered by the rising edges of SCLK. The data is also read by the TL 16PNP550A on the rising edges of SCLK.

(SCL~-~...Ir~r"""\'-~'-~
s
(CS)

I
II

I4--------i- td2
I

(~~ =~
14

tpd1

>e::=x
Address Input

}
~I

I
I

--+i

tpd3

14--

i)
14

14~

~t.----

tpd2

-.I

>e===:x

Data Output

1d3--.j1

~
~

NOTE A: The corresponding terminal names are provided in parentheses. D/Q indicates that D and Qterminals in the EEPROMs are tied together
with a 2-kQ resistor.

Figure 19. READ Address and Data Transfer Waveforms

~TEXAS

INSTRUMENTS
2-390

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTO FLOW CONTROL
SLLS190B-MARCH 1995- REVISED MARCH 1996

PRINCIPLES OF OPERATION
Table 11. ACE Register Selection
DLABt

Receiver buffer (read), transmitter holding register (write)

Interrupt enable

Interrupt identification (read only)

FIFO control (write)

Line control
Modem control

Line status

Modem status

Scratch

Divisor latch (LSB)

Divisor latch (MSB)

..
t The divisor
latch access bit (DLAB) is the most significant bit of the line control register. The DLAB signal
is controlled by writing to this bit location (see Table 13).

Table 12. ACE Reset Functions
REGISTER/SIGNAL

RESET
CONTROL

RESET STATE

Interrupt Enable Register

Master Reset

All bits cleared (0-3 forced and 4-7 permanent)

Interrupt Identification Register

Master Reset

Bit 0 is set, bits 1-3, 6, 7 are cleared, and bits 4-5 are
permanently cleared

FI FO Control Register

Master Reset

All bits cleared

Line Control Register

Master Reset

All bits cleared

Modem Control Register

Master Reset

All bits cleared (6-7 permanent)

Line Status Register

Master Reset

Bits 5 and 6 are set, all other bits are cleared

Modem Status Register

Master Reset

Bits 0-3 are cleared, bits 4-7 are input signals

SOUT

Master Reset

High

INTRPT (receiver error flag)

Read LSRlMR

Low

INTRPT (received data available)

Read RBRlMR

Low

Read IRlWrite THRlMR

Low

INTRPT (transmitter holding register empty)
INTRPT (modem status changes)

Read MSRlMR

Low

RTS

Master Reset

High

DTR

Master Reset

High

Scratch Register

Master Reset

No effect

Divisor Latch (LSB and MSB) Registers

Master Reset

No effect

Receiver Buffer Registers

Master Reset

No effect

Transmitter Holding Register

Master Reset

No effect

Receiver FIFO

MR/FCR1-FCROI
!J.FCRO

All bits cleared

XMITFIFO

MR/FCR2- FCROI
!J.FCRO

All bits cleared

~TEXAS

INSTRUMENTS
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2-391

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED

M~RCH 1996

PRINCIPLES OF OPERATION

accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers. These
registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in
Table 13.
Table 13. Summary of Accessible Registers
REGISTER ADDRESS

Bit
No.

oDlAB =0

ODLAB=O

Receiver

Transmitter

1 DlAB=O

Interrupt
Ident.

FIFO

Control

Buffer

Holding

Interrupt

Enable
Register

RBR

THR

IER

IIR

FCR

Enable
0

Data BIIOt

Data Bit 0

Received
Data
Available

Interrupt

o If
Interrupt

Pending

FIFO
Enable

(ERBI)

Enable
Transmitter
Holding
1

Data Bit 1

Data Bit 2

Data Bit2

Enable
Receiver
Une Status
Interrupt
(ELSI)

Data Bit 3

Enable
Modem
Status
Interrupt
(EDSSI)

Interrupt
ID
Bit 1

Receiver
FIFO
Reset

ODLAB=1

1 DlAB=1

Line
Control

Modem

Line

Control

Status
Register

Modem
Status
Register

Scratch
Register

Divisor
Latch
(lSB)

LCR

MCR

lSR

MSR

SCR

Dll

DlM

Data
Ready
(DR)

to Send

Bit 0

Bit 8

Bit 1

BitS

Bit 2

Bit 10

Bit 3

Bit3

Bit 11

Word
Length
Select
Bit 0
(WLSO)

Word
Length
Select
Bit 1
(WLS1)

Data

Terminal
Ready
(DTR)

Request
to Send
(RTS)

Transmitter
FIFO
Reset

Interrupt
ID
Bit 3*

Reserved

Parity
Enable
(PEN)

01
Stop Bits
(STB)

Delta

Clear
(~CTS)

Delta
Data
Set
Ready
(~DSR)

Number

Interrupt
ID
8it2

Overrun
Error
(OE)

Latch
(MSB)

Trailing
Edge of
Ring
Indicator
(TERI)

OUT1

Parity
Error
(PE)

OUT2
UART
Interrupt
Enable§

Framing
Error
(FE)

Loop

Break
Interrupt
(BI)

Clear
to
Send
(CTS)

Bit4

Bit 4

Bit12

Delta
Data
Carrier
Detect
(~DCD)

Data Bit 4

DataBit4

Reserved

Even
Parity
Select
(EPS)

Data Bit 5

Reserved

Stick
Parity

Flow
Control
Enable
(AUTO)

Transmitter
Holding
Register
(THRE)

Data
Set
Ready
(DSR)

Bit 5

Bit5

Bit 13

Data Bit 6

DataBit6

FIFOs
Enabled*

Receiver
Trigger
(LSB)

Break
Control

Transmitter
Empty
(TEMT)

Ring
Indicator
(RI)

Bit 6

Bit 14

Data Bit 7

FIFOs
Enabled;

Receiver
Trigger
(MSB)

Divisor
Latch
Access
Bit
(DLAB)

Error in
Receiver
FIFO
(see
Note6t

Data
Carrier
Detect
(DCD)

Bit 7

Bit 15

t Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
:j: These bits are always 0 in the TL 16C45D mode.
§ By setting this bit high in PNPBYPASS mode, the selected interrupt (IRQx) is enabled, otherwise, IRQx output is in the high-impedance state.

~TEXAS

INSTRUMENTS
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TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

Bit 0: FCRO, when set, enables the transmit and receive FIFOs. This bit must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.

•

Bit 1: FCR1, when set, clears all bytes in the receiver FIFO and resets its counter. The shift register is not
cleared. The logic 1 that is written to this bit position is self clearing.

•

Bit 2: FCR2, when set, clears all bytes in the transmit FIFO and resets its counter. The shift register is not
cleared. The logic 1 that is written to this bit position is self clearing.

•

Bits 3, 4, and 5: FCR3, FCR4, and FCR5 are reserved for future use.

•

Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 14).
Table 14. Receiver FIFO Trigger Level
RECEIVER FIFO
TRIGGER LEVEL (BYTES)

BIT 7

BIT 6

0
1

FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCRO = 1, IERO = 1,IER2';' 1), receiver interrupt
occur as follows:
1. When the receiver FIFO reaches its programmed trigger level, the received data available interrupt is
issued to the microprocessor and IIR (3-0) are set to the value 6 (to indicate received data available).
The received data available interrupt is cleared and IIR (3-0) are set (no interrupt) when the FIFO drops
below its programmed trigger level.
2. The data ready bit (LSRO) is set as soon as a character is transferred from the shift register to the
receiver FIFO. It is cleared when the FIFO is empty.
3. The receiver line status interrupt (IIR
(IIR =0100h) interrupt.

= 0110h) has higher priority than the received data available

~lEXAS

INSTRUMENTS
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2-393

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY IPnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED M).RCH 1996

PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
When the receiver FIFO and receiver interrupts are enabled, receiver FIFO time-out interrupt occurs as follows:
1.

FIFO time-out interrupt occurs when the following conditions exist:
a.

At least one character is in the FIFO.

The most recent serial character received is longer than the four previous continuous character
times (if two stop bits are programmed, the second one is included in this time delay).

The most recent microprocessor read ofthe FIFO is longer than four previous continuous character
times. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.

Character times are calculated by using the internal receiver clock (RCLK) input for a clock signal (makes
the delay proportional to the baud rate). The RCLK frequency equals the clock frequency generated by the
prescalar block divided by the user-defined internal UART baud rate generator divisor.

When a time-out interrupt has occurred, it is cleared and the timer is reset when the microprocessor reads
one character from the receiver FIFO.

When a time-out interrupt has not occurred, the time-out timer is reset after a new character is received or
after the microprocessor reads the receiver FIFO.

When the transmit FIFO and transmitter interrupts are enabled (FCRO = 1, IER1 = 1), transmit interrupts occur
as follows:
1.

The transmitter holding register empty interrupt [IIR (3-0) = 2] occurs when the transmit FIFO is empty. It
is cleared [IIR (3-0) 1] as soon as the THR is written to (1 to 16 characters may be written to the transmit
FIFO while servicing this interrupt) or the IIR is read.

The transmitter FIFO empty indicator [LSR5 (THRE) = 1] is delayed one character time minus the last stop
bit time when there have not been at least two bytes in the transmitter FIFO at the same time since the last
time that THRE = 1. The first transmitter interrupt after changing FCRO is immediate when it is enabled.

Character time-out and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current transmitter holding register empty
interrupt.

FIFO polled mode operation
With FCRO = 1 (transmitter and receiver FIFOs enabled), clearing IERO, IER1, IER2, IER3, or all four puts the
ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately, either
one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR.
•

LSRO is set as long as there is one byte in the receiver FIFO.

•

LSR1 - LSR4 specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = O.

•

LSR5 indicates when the transmit FIFO is empty.

•

LSR6 indicates that both the transmit FIFO and shift registers are empty.

•

LSR7 indicates whether there are any errors in the receiver FIFO.

There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmit FIFOs are still fully capable of holding characters.

~TEXAS

INSTRUMENTS
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TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTO FLOW CONTROL
SLLSl90B- MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 15) and the internallNTRPT output signal
in response to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through
3. The contents of this register are summarized in Table 13 and are described in the following bulleted list.
•

Bit 0: This bit, when set, enables the received data available interrupt.

•

Bit 1: This bit, when set, enables the transmitter holding register empty interrupt.

•

Bit 2: This bit, when set, enables the receiver line status interrupt.

•

Bit 3: This bit, when set, enables the modem status interrupt.

•

Bits 4 - 7: These bits in the IER are not used and are always cleared.

interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
•

Priority 1 - Receiver line status (highest priority)

•

Priority 2 - Receiver data ready or receiver character time out

•

Priority 3 - Transmitter holding register empty

•

Priority 4-Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and the type of that interrupt in its
three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 13 and
described in Table 15. Details on each bit are as follows:
•

Bit 0: This bit can be used either in a hardwire prioritized, or polled interrupt system. When this bit is cleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.

•

Bits 1 and 2: These two bits identify the highest priority interrupt pending, as indicated in Table 15.

•

Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a time-out interrupt is.pending.

•

Bits 4 and 5: These two bits are not used and are always cleared.

•

Bits 6 and 7: These two bits are always cleared in the TL 16C450 mode. They are set when bit 0 of the FIFO
control register is set.

~TEXAS

INSTRUMENTS
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2-395

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED M),RCH 1696

PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 15. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
BIT 3

BIT 2

BIT 1

BITO

PRIORITY
LEVEL

INTERRUPT TYPE

None

INTERRUPT SOURCE

INTERRUPT RESET
METHOD

None

Receiver line status

Overrun error, parity error,
framing error or break interrupt

Received data available

Receiver data available in the
TL 16C450 mode or trigger level
reached in the FIFO mode

Reading the receiver buffer
register

Reading the line status register

Character time-out
indication

No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time

Transmitter holding
register empty

Transmitter holding register
empty

Reading the interrupt
identification register (if source
of interrupt) or writing into the
transmitter holding register

Modem status

Clear to send, data set ready,
ring indicator, or data carrier
detect

Reading the modem status
register

line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LeR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LeR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 13 and described in the following bulleted list.
•

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 16.

Table 16. Serial Character Word Length

•

BIT 1

BIT 0

WORD LENGTH
5 bits

6 bits

7 bits

8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Iable 17.

~TEXAS

INSTRUMENTS
2-396

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B-MARCH 1995- REVISED MARCH 1996

PRINCIPLES OF OPERATION

line control register (LCR) (continued)
Table 17. Number of Stop Bits Generated
BIT 2

WORD LENGTH SELECTED
BY BITS 1 AND 2

Any word length

5Ms

11/2

6 bits

7bits

8 bits

NUMBER OF STOP
BITS GENERATED

•

Bit 4: Bit 4 is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity (an
even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is cleared,
odd parity (an odd number of logic 1s) is selected.

•

Bit 5: This bit is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked
as cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.
When bit 5 is cleared, stick parity is disabled.

•

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where the serial
output (SOUT) is forced to the spacing (low) state. When bit 6 is cleared, the break condition is disabled
and has no affect on the transmitter logic; it only affects the serial output.

•

line status register (LSR)t
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are described in the following bulleted list and summarized in Table 13.
•

Bit 0: Bit 0 is the data ready (DR) indicator for the receiver. This bit is set whenever a complete incoming
character has been received and transferred into the RBR or the FIFO. Bit 0 is cleared by reading all of the
data in the RBR or the FIFO.

•

Bit 1:1:: Bit 1 is the overrun error (OE) indicator. When this bit is set, it indicates that before the character
in the RBR is read, it is overwritten by the next character transferred into the register. The OE indicator is
cleared every time the CPU reads the contents of the LSR. If the FIFO mode data continues to fill the FIFO
beyond the trigger level, an overrun error occurs only after the FIFO is full and the next character has been
completely received in the shift register. An OE is indicated to the CPU as soon as it happens. The character
in the shift register is overwritten, but it is not transferred to the FIFO.

•

Bit 2:1:: Bit 2 is the parity error (PE) indicator. When this bit is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the
CPU reads the contents of the LSR. In the FIFO mode, this error is associated with the particular character
in the FIFO to which it applies. This error is revealed to the CPU when its associated character is at the top
of the FIFO.

t The line status register is intended for read operations only; writing to this register is not recommended outside a factory testing environment.
:I: Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-397

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY fPnP\ AND AUTO FLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MXRCH 1696

PRINCIPLES OF OPERATION
line status register (LSR) (continued)t
•

Bit 3:1:: Bit 3 is the framing error (FE) indicator. When this bit is set, it indicates that the received character
did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.
In the FIFO mode, this error is associated with the particular character in the FIFO to which it applies. This
error is revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to
resynchronize after a framing error. To accomplish this, it is assumed that the framing error is due to the
next start bit. The ACE samples this start bit twice and then accepts the input data.

•

Bit 4:1:: Bit 4 is the break interrupt (BI) indicator. When this bit is set, it indicates that the received data input
was held in the low state for longer than a full-word transmission time. A full-word transmission time is
defined as the total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads
the contents ofthe LSR. In the FIFO mode, this error is associated with the particular character in the FI FO to
which it applies. This error is revealed to the CPU when its associated character is at the top of the FIFO.
When a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled
after SIN goes to the marking state and receives the next valid start bit.

•

Bit 5: Bit 5 is the transmitter holding register empty (THRE) indicator. This bit is set when the THR is empty,
indicating that the ACE is ready to accept a new character. Ifthe THRE interrupt is enabled when the THRE
bit is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the TSR.
This bit is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, this bit is set when
the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.

•

Bit 6: Bit 6 is the transmitter empty (TEMT) indicator. This bit is set when the THR and the TSR are both
empty. When either the THR or the TSR contains a data character, the TEMT bit is cleared. In the FIFO
mode, this bit is set when the transmitter FIFO and shift register are both empty.

•

Bit 7: In the TL 16C550C mode, this bit is always cleared. In the TL 16C450 mode, this bit is always cleared.
In the FIFO mode, LSR7 is set when there is at least one parity error, framing error, or break error in the
FIFO. It is cleared when the microprocessor reads the LSR and there are no subsequent errors in the FIFO.

modem control register (MCR)
The MCR is an a-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 13 and are described in the following
bulleted list.

•

Bit 0: Bit 0 (OTR) controls the data terminal ready (OTR) output. Setting this bit forces the OTR output to
its low state. When bit 0 is cleared, OTR goes high.

•

Bit 1: Bit 1 (RTS) controls the request-to-send (RTS) output in a manner identical to bit O's control over the
OTR output.

•

Bit 2: Bit 2 (OUT1) controls the internal signal OUT1.

•

Bit 3: Bit 3 (OUT2) when set in PNPBYPASS mode, the selected interrupt line IRQx is enabled; otherwise,
IRQx is 3-state.

The line status register is intended for read operations only; writing to this register is not recommended outside a factory testing environment.

~TEXAS

INSTRUMENTS
2-398

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
•

Bit 4: Bit 4 provides a local loop back feature for diagnostic testing of the ACE. When this bit is set, the
following occurs:
-

The transmitter serial output (SOUT) is asserted high.

The receiver serial input (SIN) is disconnected.

The output of the TSR is looped back into the receiver shift register input.

The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.

The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.

The four modem control outputs are forced to their inactive (high) states.
NOTE
OUT1 is a user-designated output signal for TL16C550. It is an internal signal and not used in the
TL 16PNP550A.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify the
transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational. The
modem control interrupts are also operational, but the modem control interrupt sources are now the lower four
bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the lEA.
The ACE flow can be configured by programming bits 1 and 5 of the MCA. Table 18 shows that autoflow control
can be enabled by setting MCR bit 5, autoflow enable (AFE) and also setting MCR bit 1, RTS. autoflow
incorporates both auto-RTS and auto-CTS. If only auto-CTS is desired, set bit 5 and clear bit 1. If neither
auto-RTS nor auto-CTS is desired, clear bit 5.

Table 18. ACE Flow Configuration
MCRBIT5
(AFE)

MCR BIT 1
(RTS)

ACE FLOW CONFIGURATION

Auto-RTS and auto-CTS enabled (autoflow control enabled)

Auto-CTS only enabled

Auto-RTS and auto-CTS disabled

modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information; when a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 13 and are
described in the following bulleted list.
•

Bit 0: Bit 0 is the change in the clear-to-send (LlCTS) indicator. This bit indicates that the CTS input has
changed state since the last time it was read by the CPU. When this bit is set (autoflow control is not enabled
and the modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control
is enabled, no interrupt is generated.

•

Bit 1: Bit 1 is the change in the data set ready (LlDSR) indicator. This bit indicates that the DSR input has
changed state since the last time it was read by the CPU. When this bit is set and the modem status interrupt
is enabled, a modem status interrupt is generated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265

2-399

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG-AND-PLAY (PnP\ AND AUTOFLOW CONTROL
SLLS190B-MARCH 1995- REVISED MXRCH 1696

PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
•

Bit 2: Bit 2 is the trailing edge of ring indicator (TERI) detector. This bit indicates that the RI input to the chip
has changed from a low to a high state. When this bit is set and the modem status interrupt is enabled, a
modem status interrupt is generated.

•

Bit 3: Bit 3 is the change in data carrier detect (aDCD) indicator. This bit indicates that the DCD input to
the chip has changed state since the last time it was read by the CPU. When this bit is set and the modem
status interrupt is enabled, a modem status interrupt is generated.

•

Bit 4: Bit 4 is the complement of the clear-to-send (CTS) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (RTS).

•

Bit 5: Bit 5 is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, this
bit is equivalent to the MCR bit 1 (DTR).

•

Bit 6; Bit 6 is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, this bit
is equivalent to the MCR bit 2 (OUT1).

•

Bit 7: Bit 7 is the complement of the data carrier detect (DCD) input. When bit 4 (loop) of the MCR is set,
this bit is equivalent to the MCR bit 3 (OUT2).

programmable baud generator
The ACE contains a programmable baud generator that receives a clock input generated by the prescalar block
in the range between 1.833 and 22 MHz and divides it by a divisor in the range between 1 and (2 16-1). The
output frequency of the baud generator is sixteen times (16x) the baud rate. The formula for the divisor is:
divisor #

=clock frequency generated by the prescalar block + (desired baud rate x 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE in order to ensure correct operation of the baud generator. When either
of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Table 19 illustrates the use of the baud generator with a crystal frequency of 22 MHz and a prescalar divisor
of 12. Refer to Figure 20 for an example of a typical clock circuit.

~TEXAS

2-400

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

programmable baud generator (continued)
Table 19. Baud Rates Using a 22-MHz Crystal
and a Prescalar Divisor of 12
DESIRED
BAUD RATE
50

PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL

DIVISOR USED
TO GENERATE
16xCLOCK
2304

1536

110

1047

0.026

134.5

857

0.058

150

768

300

384

600

192

1200

1800

2000

2400

3600

4800

7200

9600

19200

38400

56000

0.69

2.86

Driver
XIN

External
Clock

Crystal

Rp
Optional
Clock
Output

Optional
Driver
I---XO_U_T+_ _ _7~.....~ Oscillator Clock

to Prescalar Logic

RX2

.---4~HM-+----___'--

'--------------' r

XOUT

Oscillator Clock
to Prescalar Logic

TYPICAL CRYSTAL OSCILLATOR NETWORK

Figure 20. Typical Clock Circuits

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2·401

TL 16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
~~!~B~~~~·~~~;~~YM{~!~~~ND AUTOFLOW CONTROL
PRINCIPLES OF OPERATION
receiver buffer register (RBR)
The ACE receiver section consists of a receiver shift register (RSR) and a RBA. The RBR is actually a 16-byte
FIFO. Timing is supplied by the 16x receiver clock (RCLK). Receiver section control is a function of the ACE
line control register.
The ACE RSR receives serial data from the serial input (SIN) terminal. The RSR then deserializes the data and
moves it into the RBR FIFO. In the TL 16C450 mode, when a character is placed in the RBR and the received
data available interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out
of the RBA. In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control
register.

scratch register
The scratch register is an 8-bit register that is intended for the programmer's use as a scratch pad in the sense
that it temporarily holds the programmer's data without affecting any other ACE operation.

transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
16-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the TSR is idle, moves the data into the TSR.
The TSR serializes the data and outputs it at the serial output (SOUT). In the TL 16C450 mode, if the THR is
empty and the transmitter holding register empty (THRE) interrupt is enabled, an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.

~TEXAS

INSTRUMENTS
2-402

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TL16PNP550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH PLUG·AND·PLAY (PnP) AND AUTOFLOW CONTROL
SLLS190B - MARCH 1995 - REVISED MARCH 1996

APPLICATION INFORMATION
TL16PNP550A
~

0""

07-00

lOW

lOR

AEN
RESETORV

B
U
S

lOW

SIO

lOR
AEN
RESETORV

l.C

SCLK
A11-AO

ST93C56

ORG

A11-AO

I
VCC

IRQ

IRQ3-7
IRQ9-12
IRQ15

OTR
RTS

22MHZ

CS
OCO
XIN

l ?<

I ±
-

EIA
232-0 Drivers
and Receivers

OSR
CTS

<==>

XOUT

SOUT

-=-

--'"

SIN

ii9' i i r
III
III

~
>
III
I:\.

I:\.

it
Z
0
0

it
Z
0

!:!

III
III

~
>
III

....IE:

;!;

III
I:\.

I:\.

:::I

NOTES: A. No data or IRQ buffer is needed.
B. Check ST93C56 application note: When 0 and Q terminals are shorted it is recommended that a 2-kO resistor be inserted
between terminals 0 and Q.

Figure 21. Basic TL 16PNP550A Configuration

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-403

2-404

3-1

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3-2

TL16PIR552
DUAL UART WITH DUAL IrDA
AND 1284 PARALLEL PORT
SLLS222 - OCTOBER 1995

• Software Compatible with TL16C550C
UART
• IEEE 1284 Bidirectional Parallel Data port
- Compatible with Standard Centronics
Parallel Interface
- Support for Parallel Protocols ECP and
EPP
- Data Path 16-Byte FIFO Buffer
- Direct Memory Access (DMA) Transfer
- Decompression of Run Length Encoded
Data in ECP Reverse Mode
- Direct Connection to Printer, No External
Transceiver is Needed
• Serial Ports Have IrDA Inputs and Outputs
- 1200 bitls to 115.2 kbitls Data Rate
• 16-Byte FIFOs Reduce CPU Interrupts
• 12 mA Drive Current for All 1284 Control
Pins and Parallel Port Data Pins

• Capable of Running With All Existing
TL 16C452 Software
• After Reset, All Registers Are Identical to
the TL16C450 Register Set
• Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
• Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 -1) and Generates an Internal16x
Clock
• Independent Receiver Clock Input
• Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
• Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
• Available in 80-Pin PQFP

• Programmable Auto-RTS and Auto-CTS

description
Functionally equivalentto the TL 16C450 on power up (character orTL16C450 mode), the TL 16PIR552 can also
be placed in FIFO mode. This relieves the CPU of excessive software overhead by buffering received and
transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits
of error status per byte for the receiver FIFO. In the FIFO mode, there is a selectable autoflow control feature
that can significantly reduce software overload and increase system efficiency by automatically controlling serial
data flow using RTS output and CTS input signals.
The TL16PIR552 is similar to the TL16C552A dual-channel UART. The device serves two serial 110 ports
simultaneously in a microcomputer or microprocessor-based system. Each channel performs serial-to-parallel
conversion on data characters received from peripheral devices or modems and parallel-to-serial conversion
on data characters transmitted by the CPU. The complete status of each channel of the dual-channel UART
can be read at any time during functional operation by the CPU. The information obtained includes the type and
condition of the transfer operation being performed and the error condition.
The serial ports also have a dedicated Infrared Data Association (IrDA) serial data input (IRSINO/1) and the
serial data outputs multiplex between RS-232 type serial output or IrDA serial data output. This is selected
through an internal register bit and uses the same SOUTO and SOUT1 output pins. The same UART circuit is
used for the data path for the IrDA or the RS232 case.
In addition to the dual communication capabilities, the TL16PIR552 provides the user with an IEEE 1284
host-side-compatible bidirectional parallel data port. The parallel port operates in compatible mode, nibble
mode, byte mode, extended capability port (ECP) mode (with RLE data decompression), or enhanced parallel
port (EPP) mode. The default mode of operation is compatible with the Centronics-type printer port interface.
The parallel port and the two serial ports provide IBM PC/ATTM-compatible computers with asingle device to
serve a 3-system port. The TL16PIR552 has one IBM PCIXTTM compatible parallel port which includes a
PS/2™-type bidirectional parallel port (SSP), that is supported by EPP and ECP protocols.

IBM PC/AT, IBM PCIXT, and PS/2 are a trademarks of International Business Machines Corporation.
PRODUCT PREVIEW information concems products In the fonnatlve or
ph", 01 developmenL Cha_ data and othar
s are delign goals. Texas Instrumenta reserves the right to
90 or dlaconlln.. "'" produell without nollce.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-3

5>
w

D..

I-

o:::)
c

oa:

D..

TL16PIR552
DUAL UART WITH DUAL IrDA
AND 1284 PARALLEL PORT
SLLS222 - OCTOBER 1995

description {continued}
The TL16PIR552 includes a programmable baud rate generator capable ·of dividing a reference clock by
divisors from 1 to (2 16 _1) and producing a 16x reference clock for the internal transmitter logic. Provisions are
also included to use this 16x clOCk for the receiver logic. The UART accommodates a 1-Mbaud serial rate
(16-MHz input clock) so that a bit time is 1 ~ and a typical character time consisting of a start bit, 8 data bits,
and a stop bit is 10~.

"o::D
C

"::Dm

-m

3-4

:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285

TL16PNP200
STAND ALONE PLUG-AND-PLAV (PnP) CONTROLLER
SLLS229 - NOVEMBER 1995

• PnP Card Autoconfiguration Sequence
Compliant
• Satisfies All Requirements for Qualifying
for the Windows 95™ Logo
• Supports up to Five Logical Devices
• 24-Bit Memory Address Decoding, and
16-Bit I/O Address Decoding With
Programmable (1, 2, 4, a, 16,32,64)
1/0 Block Size
• Configurable OEN Signals That Can Be
Used to Enable Logical Device
Transceivers
• Device-Interrupt Mapping to any of the 11
Interrupt Request (IRQ) Signals on the ISA
Bus

• DMA SliPport For Two Logical Devices with
Configurable DMA Channel Connection
• Simple 3-Terminallnterface to Serial
EEPROM 2K14K ST93C56166 or Equivalent
for Resource Data Storage
• Default Configuration Loading and
Activation Upon Power-up for Non-PnP
Systems
• Direct Connection to ISA/AT Bus Without
Need for Buffers
• 5-V Power Supply Operation
• Available in aO-pin PQFP

description
The TL 16PNP200 is an ISA plug-and-play (PnP) controller that provides autoconfiguration capability to ISA
cards according to the ISA PnP 1.0a specification. This device interfaces to a serial EEPROM where card
resource requirements and power-up defaults are stored. On power up, the controller loads the default
configuration from the EEPROM making it ready for operation (non-PnP systems) or to be configured by the
PnP configuration process (PnP-capable systems). During the configuration mode, the PnP autoconfiguration
process reads the card resource requirements, configures the card by writing to the TL 16PNP200 configuration
registers, activates the device, and removes it from the configuration mode. Thereafter, the TL16PNP200 routes
all ISA transactions between the card and the ISA bus.
The TL 16PNP200 operates in one of two modes. In mode 0, the device supports two logical devices with
memory, 1/0, interrupt, and DMA resources for each device. In mode 1, the device supports five logical devices
with 1/0 and interrupt resources for all logical devices and direct memory access (DMA) resources for two of
the five logical devices; there is no memory support in mode 1. The TL 16PNP200 provides interface signals
to allow on-board logic access to the serial EEPROM.

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Windows 95 is a trademark of Microsoft Corporation.
PRODUCT PREVIEW Infonnatlon concern. products In the farmatlve or
desl!in pIIaoo 01 dovelOpment. Ch......'11Iic doIa and OIlier
_catl... a" daalgn goals. Tmlinolrumonlll......... the right ..
change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-5

3-6

4-1

-mm
m

.....
I

W
CD

.,s::..

4-2

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLSI67A-MARCH 1994- REVISED MARCH 1996

•

Supports Provisions of IEEE 1394-1995 for
High-Performance Serial Bus

•

Fully Interoperable With FireWire™
Implementation of IEEE 1394-1995

•

Provides Three Fully Compliant Cable
Ports at 100 Mbits Per Second (Mbits/s)

•

Cable Ports Monitor Line Conditions for
Active Connection to Remote Node

•

Inactive Ports Disabled to Save Power

•

Logic Performs System Initialization and
Arbitration Functions

•

Encode and Decode Functions Included for
Data Strobe Bit Level Encoding

•

Incoming Data Resynchronized to Local
Clock

•

Interface to Link Layer Controller Supports
Optional Electrical Isolation

•

Data Interface to Link Layer Controller
Provided Through Two Parallel Lines at
50 Mbits/s

•

25-MHz Crystal Oscillator and PLL Provide
Transmit, Receive Data, and Link Layer
Controller Clocks at 50 MHz

•

Selectable Oscillator Input for External
100-MHz Reference Signal

•

Node Power Class Information Signaling
for System Power Management

•

Cable Power Presence Monitoring

•

Cable Bias and Driver Termination Voltage
Supply

•

Single 5-V Supply Operation

•

Separate Multiple Package Terminals
Provided for Analog and Digital Supplies
and Grounds

•

High-Performance 56-Pin SSOP (DL)
Package

DLPACKAGE
(TOP VIEW)

CPS
AVcc 2
AVcc
XI
XO
AVcc 6
AVcc
PDOUT
VCOIN
TESTM2
RESET
ISO
AGND
AGND
AGND
AGND
AGND
DGND
LPS
DGND
LREQ
TESTMl
DVcc
SYSCLK
CTLO
CTL1
DO
D1

43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

TPA1
TPA1
TPBl
TPBl
TPA2
TPA2
TPB2
TPB2
TPA3
TPA3
TPB3
TPB3
AGND
AGND
AGND
AGND
AGND
RO
R1
PC2
TPBIAS
PCl
PCO
DVcc
CLK100
ENCLK100
DGND
C/LKON

description
The TS811 C01 provides the analog transceiver functions needed to implement a 3-port node in a cable-based
IEEE 1394-1995 network. Each cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions needed for determining connection status, for initialization and
arbitration, and for packet reception and transmission. The TS811C01 is designed to interface with a link layer
controller, such as the TS812C01A.

FireWire is a trademark of Apple Computer, Incorporated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-3

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

description (continued)
The TSB11 C01 requires either an external 24.576-MHz crystal or an external 98.304-MHz reference oscillator
input. When using the crystal oscillator option, an internal phase-locked loop (PLL) generates the required
98.304-MHz reference signal. Selecting the external oscillator option turns off both the crystal oscillator and the
PLL. The 98.304-MHz reference signal is internally divided to provide the 49.152-MHz ± 100 ppm clock signals
that control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock signal
is also supplied to the associated link layer controller for synchronization of the two chips and is used for
resynchronization of the received data.
Data bits to be transmitted are received from the link layer controller on two parallel paths and are latched
internally in the TSB11 C01 in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and transmitted at 98.304 Mbits/s as the outbound data strobe information stream. During
transmit, the encoded data information is transmitted differentially on the TPB cable pair(s) and the encoded
strobe information is transmitted differentially on the TPA cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two parallel streams,
resynchronized to the local system clock and sent to the associated link layer controller. The received data is
also transmitted (repeated) out of the other active cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is
used as an indication of cable connection status.
The TSB11 C01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when seen
through a cable by a remote receiver, senses the presence of an active connection. The value of this bias voltage
has been chosen to allow interoperability between transceivers operating from either 5-V nominal supplies or
3-V nominal supplies. This bias voltage source should be stabilized by using an external filter capacitor of
approximately 1 j.1F.
The line drivers in the TSB11 C01 operate in the high-impedance current mode and are designed to work with
external 112-Q line matching resistor networks. One network is provided at each end of each twisted-pair cable.
Each network is composed of a pair of series-connected 56-Q resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal.
The midpoint of the pair of resistors that is directly connected to the twisted-pair B-package terminals is coupled
to ground through a parallel RC network with recommended values of 5 kQ and 250 pF. The values of the
external resistors are designed to meet the IEEE 1394-1995 specifications when connected in parallel with the
internal receiver circuits.
The driver output current, along with other internal operating currents, is set by an external resistor. This resistor
is connected between R1 and RO and has a value of 6.36 kQ ±0.5%.

Two terminals set up various test conditions used in manufacturing. Terminals TESTM1 and TESTM2 should
be connected to Vee for normal operation.
Four terminals are used as inputs to set four configuration status bits in the self identification packet. These
terminals are hardwired high or low as a function of the equipment design. PC[0:2] are three terminals that
indicate either the need for power from the cable or the ability to supply power to the cable. The fourth terminal,
C/LKON, indicates if a node is a contender for configuration manager. C/LKON can also output a 6.114-MHz
±100 ppm Signal, indicating reception of a link-on packet. See Table 4-27 of the IEEE 1394-1995 standard for
additional details.

~TEXAS

4-4

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

description (continued)
The TSB11C01 supports an optional isolation barrier between itself and its link layer controller. When ISO is
tied high, the link interface outputs behave normally; when tied low, an internal differentiating logic is enabled
and the outputs become short pulses that can be coupled through a capaCitor or transformer.
The TSB11 C01 is characterized for operation from O°C to 70°C.

functional block diagram
1

CPS

LPS

Received
Data
Decoderl
Retimer

ISO ~

SYSCLK

-24

LREQ

-21

CTLO

CTL1

Bias Voltage
and
Current
Generator

TPBIAS

I I
1

56
55

TPA1
TPA1

Link
Interface
1/0

Cable Pori 1
54
DO

....
t-<

.- -

r- .........
~

Arbitration
and
Control
State
Machine
Logic

PCO
PC1
PC2
TESTM1
TESTM2

~
~
Cable Pori 2

29
34

35
37

TPB1

~
~

TPA2
TPA2
TPB2
TPB2

TPA3

TPB3

Cable Pori 3
I---

22
10

T
11

TPB1

~
~

I---

C/LKON

Transmit
Data
Encoder

TPB3

Crystal
Oscillator PLL
System and
Transmit Clock
Generator

~
~
32

XO
PDOUT
VCOIN
CLK100
ENCLK100

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-5

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLSI67A- MARCH 1994 - REVISED MARCH 1996

Terminal Functions
TERMINAL
NAME
AGND

13-17,40-44

AVCC

2,3,6,7

Analog circuit ground
Analog circuit supply voltage

CLK100

C/LKON

I/O

CPS

CTL[0:1J

25.26

I/O

D[0:1J

27,28

I/O

DGND

18,20,30

DVCC

23.33

ENCLK100

DESCRIPTION

I/O

NO.

Optional external clock input
Configuration manager contender status input or link-on output
Cable power status
Link interface bidirectional control signals
Link interface bidirectional data signals
Digital circuit ground
Digital circuit supply voltage

Disable crystal oscillator and PLL, enable CLK1 00 input

ISO

Physical (phy) link interface isolation status

LPS

Link power status

LREQ

Link request from controller

PDOUT

Output from PLL phase detector. input to external filter

PC[O:2]

34,35.37

Power class bits 0 through 2 inputs

R[O:1J
RESET
TESTM1, TESTM2

External bias current-setting resistor

38,39
11

Reset

22,10

Test mode control, normally tied high

49.152-MHz clock to link controller

TPA 1, TPA2, TPA3

56,52,48

I/O

Port n cable pair A, positive signal

TPA 1, TPA2, TPA3

55,51,47

I/O

Port n cable pair A, negative signal

TPB1, TPB2, TPB3

54,50,46

I/O

Port n cable pair B, positive signal

TPB1, TPB2, TPB3

53,49,45

I/O

Port n cable pair B, negative signal

Cable termination voltage source

SYSCLK

TPBIASt
VCOIN

XI,XO

4,5

I/O

Input to VCO, output from external filter
External crystal for oscillator

t The output voltage at TPBIAS (terminal 36) IS approximately 50 mV below the target deSign value. ThiS can cause
the measured TPBIAS output voltage to fall outside the specified limits when under the worst case conditions
of minimum supply voltage and maximum load current. To adjust the output voltage at TPBIAS to the specified
limit, connect an external resistor of approximately 785 n between TPBIAS (terminal 36) and AVCC (terminals
2,3,6, or 7). The nominal TPBIAS output voltage will be adjusted to the target design value on a future revision
of this device.

~TEXAS

INSTRUMENTS
4-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee .......................................................... -0.5 V to 6 V
Input voltage range, VI ....................................................... 0.5 V to Vee + 0.5 V
Output voltage range at any output, Vo ........................................ 0.5 V to Vee + 0.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature, TA .................................................... O°C to 70°C
Storage temperature range ....................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 300°C

DISSIPATION RATING TABLE
PACKAGE

TA~25°C

POWER RATING

DERATING FACTOR;
ABOVE TA 25°C

2500mW

TA=70°C
POWER RATING
1600mW

This is the inverse of the traditional junction-to-case thermal resistance (RaJA) and uses a board
mounted device rated at 5O°CIW.

recommended operating conditions
Supply voltage, VCC
High-level input voltage, VIH

CMOS inputs

LOW-level input voltage, VIL

CMOS inputs

Differential input voltage, VID

Cable inputs

Common-mode input voltage, VIC

Cable inputs

High-level output current, 10H
Low-level output current, 10L
Output current, 10

MIN

NOM

MAX

UNIT

4.75

5.25

V
V

0.7VCC
0.2VCC

142

260

1.12

2.54

SYSCLK

-16

CTLO, CTL1, DO, D1

-12

SYSCLK

CTLO, CTL1, DO, D1

TPBIAS

-5

2.5

rnA
rnA
rnA

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-7

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A-MARCH 1994- REVISED MARCH 1996

electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)
driver
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

RL=55U

180

260

-0.55

0.55

VOD

Differential output voltage

IIC

Common-mode input current

Driver enabled

VOFF

Off-state voltage

Driver disabled

receiver
PARAMETER

IIC
zlD

zlC

Common-mode input current

TEST CONDITIONS

MIN

MAX

Driver disabled

-20

Differential input impedance

0.6

Cable bias detect threshold, TPBx inputs

llA
kU

Common-mode input impedance

UNIT

pF
kU

1.12

device
PARAMETER

TEST CONDITIONSt

Power status threshold

0.4-MU resistor

VOH

High-level output voltage

IOH = MAX,

VCC=MIN

VOL

Low-level output voltage

IOL= MIN,

VCC=MAX

Positive arbitration comparator threshold
Negative arbitration comparator threshold
TPBIAS output voltage

MIN

MAX

4.7

7.5

3.7
0.5

168

-168

-89

1.71

Positive input threshold voltage, LREQ, CTL, D inputs

VCC/2+0.2

VCC/2+1.1

VIT-

Negative input threshold voltage, LREQ, CTL, D inputs

VCC/2 -1.1

VCC/2+0.2

ICC

Supply current

.. .
.. shown as MIN or MAX, use the appropriate value specified
.. under recommended operating conditions
t For conditions

~TEXAS

INSTRUMENTS
4-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V
V

VIT+

VCC = 5.25 V

UNIT

140

V
V
V
mA

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994 - REVISED MARCH 1996

switching characteristics
PARAMETER

TEST CONDITIONS

MIN

Transmit jitter

MAX

UNIT

±0.8

Transmit rise time

Transmit fall time

Isu

Setup time, D, CTL, LREQ low or high before SYSCLKf

Hold time, D, CTL, LREQ low or high aiter SYSCLKf

Delay time, SYSCLK to D, CTL

TYP

MAX

CL=10pF,

RL=55Q

thermal characteristics
PARAMETER

TEST CONDITIONS

RaJA

Junction-to-free-air thermal resistance

ROJC

Junction-to-case thermal resistance

MIN

Board mounted, No air flow

UNIT

°CIW

PARAMETER MEASUREMENT INFORMATION
D,CTL,LREQ

_---'¥'-50_%---'~'--_
1 I..
.1
---+1 i.th1.

tsu1

..J,r--

5 0- % - -......- -

SYSCLK _ _ _ _

Figure 1. D, CTL Output Delay Relative to SYSCLK Waveforms

D,CTL

50%

Id~

SYSCLK~
Figure 2. D, CTL, LREQ Input Setup and Hold Time Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-9

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

APPLICATION INFORMATION
TSBllCOl
CPS
O.4MO

TPBIAS

1 !IF TYP

>-----f--"----*---.--.----l~
56 o (each)

r------,

TPA

One
Cable

TPB

I
I
I
IL _ _ _ _ _ _ .JI

56 0 (each)

5k!l

250pF

To Other Ports

Figure 3. Twisted-Pair Cable Interface Connections

internal register configuration
The accessible internal registers of this device are listed in Table 1 and the description of the fields are listed
in Table 2.

Table 1. Accessible Internal Registers
ADDRESS

0001

RHB

I CPS

IBR

0010

SPD

Reserved

0011

AStat1

BStall

Chl

ConI

Reserved

0100

ASlat2

BSlat2

Ch2

Con2

Reserved

0101

AStat3

BStal3

Ch3

Con3

Reserved

0110

Reserved

0111

Reserved

~lExAs

INSTRUMENTS
4·10

PhysicallD

0000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

APPLICATION INFORMATION

internal register configuration (continued)
Table 2. Internal Register Field Descriptions
FIELD

SIZE
(Bits)

AStat(n)

DESCRIPTION

TYPE

These bits give the line state of TPA of port n.
11 =Z
01 = 1
10=0
00= invalid

BStat(n)

These bits give the line state of TPB of port n, the encoding is the same as AStat(n).

ChIn)

When ChIn) = 1, then port n is a child; otherwise, it is a parent.

Con(n)

When Con(n) = 1, then port n is connected; otherwise it is disconnected.

CPS

This bit is the cable power status for the CPS terminal.

IBR

Rd/Wr

This bit initiates bus reset at next opportunity.

RdlWr

These bits are the gap count may be changed by the serial bus manager to optimize performance. See the
IEEE 1394-1995 standard for details.

These bits are the number of ports on this TSBllCOl and are always set to 0011.

PhysicallD

These bits contain the address of the local node determined during self identification.

This bit indicates that the local node is the root.

RHB

Rd/Wr

SPD

This is the root hold-off bit that instructs the local node to try to become the root during the next bus reset.
These bits indicate the top signalling speed of this TSBll COl and is always cleared.

external components and connections
Cable power status (CPS): This terminal is normally connected to the cable power through a O.4-MQ resistor.
This circuit feeds an internal comparator, which detects the presence of cable power. This information is
available to the link layer controller.
Oscillator crystal (XI and XO): These terminals are usually connected to an external 24.576-MHz
parallel-resonant fundamental mode crystal. The optimum values for the external shunt capacitors are
dependent on the specifications of the external crystal used and on circuit board layout.
PLLIVCO filter (PDOUT and VCOIN): These terminals are for an external lag-lead filter required for stable
operation of the frequency multiplier running off the crystal oscillator.
Test mode control inputs (TESTM1 and TESTM2): These terminals are used in manufacturing to enable
production line testing of the TSB11C01. For normal use, these should be tied to Vee.
Logic reset input (RESET): When forced low, this terminal causes a bus reset condition on the active cable ports
and resets the internal logic to the reset/start state. An internal pullup resistor is provided that is connected to
Vee, so only an external delay capacitor is required. This input is a standard logic buffer and may also be driven
by a logic buffer.
Link power status input (LPS): A 1O-kQ resistor connected to Vee supplying the link layer controller to monitor
the link power status. When the link is not powered on, SYSCLK is disabled and the TSB11 C01 performs only
the basic repeater functions required for network initialization and operation.
Link request input (LREQ): An input from the link layer controller that is used by the linkto signal the TSB11C01
of a request to perform some service
System clock output (SYSCLK): This terminal provides a 49.152-MHz clock signal to which the data, control,
and link request information is synchronized.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-11

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

APPLICATION INFORMATION
external components and connections (continued)
Controll/Os (CTL[0:1]): These terminals are bidirectional signals communicated between the TSB11C01 and
. the link layer controller that control passage of information between the two devices
Data I/Os (DO and D1): These terminals are bidirectional information signals communicated between the
TSB11 C01 and the link layer controller
Power class bits 0 through 2 inputs (PC[0:2]): These terminals are used as inputs to set the bit values of the
three power class bits in the self-ID packet. They may be programmed by tying the terminals high to Vcc or low
to GND.
Enable external clock input (ENCLK1 00): This terminal is a logic input that allows a choice between using the
internal crystal oscillator and PLL frequency multiplier or an external 98.304-MHz signal source. When tied high,
the internal crystal oscillator and the PLL are disabled and the external clock input can be used.
External clock input (CLK1 00): When this terminal is asserted high (enabled), an external 98.304-MHz oscillator
can drive the TSB11 C01. Input voltages as low as 0.2 V peak-to-peak may be used, and the input should be
ac coupled through a capacitor of 300 pF or greater. When the crystal oscillator and PLL are being used, it is
recommended that this terminal be tied to GND.
Twisted-pair cable bias-voltage output (TPBIAS): This terminal provides the 1.86-V nominal bias voltage
needed for proper operation of the twisted-pair cable drivers and for signalling to the remote nodes that there
is a valid cable connection.
Configuration manager contender input or link-on output (C/LKON): C/LKON is a bidirectional terminal that is
used as an input to specify in the self-ID packet that the node is a configuration manager contender. As an
output, it signals the reception of a link-on message by supplying a 6.114-MHz signal. The bit-value
programming is done by tying the terminal through a 10-kn resistor high (VCC> or low (GND). The use of the
series resistor allows the link-on output to override the input value when necessary.
Current setting resistor (R[O: 1]): An internal reference voltage is applied across the resistor connected between
these two terminals to set the internal operating currents and the cable driver output currents. A low
temperature-coefficient (TC) resistor should be used to meet the IEEE 1394-1995 output voltage limits.
Supply filters (AVCC and DVcc>: A combination of high-frequency decoupling capaCitors is suggested for these
terminals, such as paralleled 0.1 J..LF and 0.001 J..LF. These supply lines are separated on the device to provide
noise isolation. They should be tied together at a low-impedance point on the circuit board. Individual filter
networks are desirable.

~TEXAS
4-12

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB11C01
IEEE 1394·1995 TRIPLE·CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

APPLICATION INFORMATION

external components and connections (continued)
400kn
Cable Power --'v'v"v----t CPS

TSB11C01

TPA1

VCC --.__-----4~--I AVCC

TPA1

AVCC

TPB1

4
, - - - - - - - - - - - - - - - - 1 XI

TPB1

1---......._ _ _ _ _ _ _ _--=5-1 XO
12pF

-:::c-

-:::c- 12pF

-=-

TPA2

AVCC

VCC ------4..--------4..-----1 AVCC
...--'VVI.-----1

,--~I----.__-....-----'-I

96Q
0.01 !!Fr

TPB2
TPB2

PDOUT
VCOIN

TPA3

TESTM2

TPA3

,--_ _ _1_1--1 RESET

-=0.1

!!F~ VCC

TPB3

ISO

TPB3
AGND

AGND

PC2
Link Controller Interface

TPBIAS

TESTM1
23
VCC - - -__- - - - - - - 1 DVCC
24
SYSCLK
25
CTLO
26
Link Controller
CTL1
Interface
27
DO

PC1

VCC

55
54

53
52
51
TPCables

50
49

48
47
46
45

44
43
42
41
40

6.36 kQ ± 0.5%
39
RO 1----..J\f'0r---,
38
R11-----------'

18
10kn

PCO

37
36

Power Class
Programming

1--'-'--------....- - TPBIAS
35 }
34

Power Class
Programming

33
DVCC 1 - - - - - - - - -....- - - VCC
32
0.1 !!F
CLK100
31
ENCLK100 1--'-=------=------,
30
DGND 1--'-=------,
29
C/LKON
LKON

-:::c-

~~VV\r-

Contender Programming

10kQ

Figure 4. External Component Hookup Circuit

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-13

TSB11C01
IEEE 1394-1995
TRIPLE-CABLE
TRANSCEIVER/ARBITER
.
.
SLLSI67A-MARCH 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

external components and connections (continued)
The TSB11 C01 is designed to operate with a link layer controller such as the Texas Instruments TSB12C01 A. These
devices use an interface described in annex I of the IEEE 1394-1995 standard. Details of how the TSB12C01A
devices operate are described in the TSB12C01 A data manual (literature number SLLS219). The following describes
the operation of the physical (phy) link interface.
The TSe11 C01 supports 100 Mbits/s data transfers and has two bidirectional data lines 0[0: 1] crossing the interface.
In addition, there are two bidirectional control lines CTL[0:1], the 50-MHz SYSCLK line from the TSB11C01 to the
link, and the link request line (LREQ) from the link to the TSB11 C01. The TSB11 C01 has control of all the bidirectional
terminals. The link is allowed to drive these terminals only after it has been given permission by the TSB11 C01. The
dedicated LREQ request terminal is used by the link for any activity it wishes to initiate.
There are four operations that may occur in the phy link interface: request, status, transmit, and receive. With the
exception of the request operation, all actions are initiated by the TSB11 C01.
When the TSB11 C01 has control of the bus the CTL[0:1] lines are encoded as shown in Table 3.
Table 3. TSB11 C01 Control of Bus Functions
CTL [0:1]
00

DESCRIPTION OF ACTIVITY

NAME

No activity is occurring (this is the default mode).

Idle

Status

Status information is being sent from the TSBllCOl to the link

Receive

An incoming packet is being sentfrom the TSBllCOl to the link

Transmit

The link has been given control of the bus to send an outgoing packet.

When the link has control of the bus (TSB11C01 permission) the CTL[0:1] lines are encoded as shown in Table 4.
Table 4. Link Control of Bus Functions
CTL [0:1]

NAME

DESCRIPTION OF ACTIVITY

Idle

The link has released the bus (transmission has been completed).

Hold

The link is holding the bus prior to sending a packet.

Transmit

An outgoing packet is being sent from the link to the TSBllC01.

Reserved

None

When the link wishes to request the bus or access a register that is located in the TSB11 C01, a serial stream of
information is sent across the LREQ line. The length of the stream varies depending on whether the transfer is a bus
request, a read command, or a write command (see Table 5). Regardless of the type of transfer, a start bit of 1 is
required at the beginning of the stream and a stop bit of 0 is required at the end of the stream. Bit 0 is the most
significant and is transmitted first.
Table 5. Link Request Functions
NO. of BITS

REQUEST TYPE
Bus Request

Read Register Request

Write Register Request

~TEXAS
4-14

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SllS167A- MARCH 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
external components and connections (continued)
For a bus request, the length of the LREQ data stream is 7 bits, as shown in Table 6.

Table 6. Bus Request Functions
BIT(S)

NAME

Start Bit

DESCRIPTION
This bit indicates the beginning of the transfer (always a 1).

1-3

Request Type

This bit indicates the type of bus request (see Table 7 for the encoding of this field).

4-5

Request Speed

These bits should always be 00 for the TSB11 C01 100-Mbitsfs speed.

Stop Bit

This bit indicates the end of the transfer (always a 0).

For a read register request, the length of the LREQ data stream is 9 bits, as shown in Table 7.

Table 7. Read Register Request Functions
BIT(S)

NAME

DESCRIPTION

Start Bit

This bit indicates the beginning of the transfer (always a 1).
These bits are always a 100 indicating that this is a read register request.

1-3

Request Type

4-7

Address

These bits contain the address of the TSB11 C01 register to be read.

Stop Bit

This bit indicates the end of the transfer (always a 0).

For a write register request, the length of the LREQ data stream is 17 bits, as shown in Table 8 and LREQ timing is
shown in Figure 5.

Table 8. Write Register Request Functions
BIT(S)
0

NAME

DESCRIPTION

Start Bit

This bit indicates the beginning of the transfer (always a 1).
These bits are always a 101 indicating that this is a write register request.

1-3

Request Type

4-7

Address

These bits conatin the address of the TSB11 C01 register to be written to.

8-15

Data

These bits contain the data that is to be written to the specified register address.

Stop Bit

This bit indicates the end of the transfer (always a 0).

...... ~
Figure 5. LREQ Timing (Each Cell Represents One Clock-Sample Time)

"!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-15

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION
external components and connections (continued)
The 3-bit request-type field has the following possible values as shown in Table 9.
Table 9. Request Functions
LREQ[1:3]

NAME

DESCRIPTION

000

TakeBus

Immediate request. Upon detection of an idle, take control of the bus immediately (no arbitration).

001

IsoReq

Isochronous request. Arbitrate after an isochronous gap.

010

PriReq

Priority request. Arbitrate after a fair gap, ignore fair protocol.

all

FairReq

Fair request. Arbitrate after a fair gap; use fair protocol.

100
101

RdReg

Return the specified register contents through a status transfer.

WrReg

Write to the specified register.

Reserved

110,111

bus request
For fair or priority access, the link requests control of the bus at least one clock after the phy link interface
becomes idle. When the link senses that the CTL terminals are in a receive state (CTL[0:1] =10), it knows that
the request has been lost. This is true any time during or after the link sends the bus request transfer. The
TSB 11 C01 ignores any fair or priority requests when it asserts the receive state while the link is requesting the
bus. The link then reissues the request one clock after the next interface idle.
The cycle master uses a normal priority request to send a cycle start message. After receiving a cycle start, the
link can issue an isochronous bus request. When arbitration is won, the link proceeds with the isochronous
transfer of data. The isochronous request is cleared in the TSB11 C01 once the link sends another type of
request or when the isochronous transfer has been completed.
The TakeBus request is issued when the link needs to send an acknowledgment after reception of a packet
addressed to it. This request must be issued during packet reception. This is done to minimize the delays that
the TSB 11 C01 has to wait between the end of a packet and the transmittal of an acknowledgment. As soon as
the packet ends, the TSB11 C01 immediately grants access of the bus to the link. The link sends an
acknowledgment to the sender unless the header cycle redundancy check (CRC) of the packet is bad. In this
case, the link releases the bus immediately; it is not be allowed to send another type of packet on this grant.
To ensure this, the link is forced to wait 160 ns after the end of the packet is received. The TSB11C01 then gains
control of the bus and the acknowledgment indicating the CRC error is sent. The bus is released and allowed
to proceed with another request.
It is conceivable that two separate nodes might believe that an incoming packet is intended for them. The nodes
then issue a TakeBus request before checking the CRC of the packet. Since both nodes seize control of the
bus at the same time, a temporary localized collision of the bus occurs somewhere between the competing
nodes .. This collision would be interpreted by the other nodes on the network as being a ZZ line state, not a bus
reset. As soon as the two nodes check the CRC, the mistaken node drops its request and the false line state
is removed. The only side effect is the loss of the intended acknowledgment packet (this is handled by the higher
layer protocol).

~TEXAS

INSTRUMENTS
4-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

read/write requests
When the link requests to read the specified register contents, the TSB11 C01 sends the contents of the register
to the link through a status transfer. If an incoming packet is received while the TSB 11 C01 is transferring status
information to the link, the TSB11C01 continues to attempt to transfer the contents of the register until it is
successful.
For write requests, the TSB 11 C01 loads the data field into the appropriately addressed register as soon as the
transfer has been completed. The link is allowed to request read or write operations at any time.
A status transfer is initiated by the TSB11 C01 when it has some status information to transfer to the link. The
transfer is initiated by asserting CTL[0:1] = 01 and 0[0:1] = 00 (100 Mbits/s only). The 0[0:1] = 00 represents
the speed at which the status transfer is to occur; status information at 100 Mbits/s is always transmitted two
bits at a time.
The status transfer can be interrupted by an incoming packet from another node. When this occurs, the
TSB11 C01 attempts to resend the status information after the packet has been acted upon. The TSB11 C01
continues to attempt to complete the transfer until the information has been successfully transmitted.
NOTE
There must be at least one idle cycle between consecutive status transfers. The definition of the bits in the status
transfer is shown in Table 10.

status request
Length of stream: 4 or 16 bits

Table 10. Status Request Functions
BIT(s)

NAME

DESCRIPTION

Arbitration Reset
Gap

This bit indicates that the TSBll COl has detected that the bus has been idle for an arbitration reset gap time (this
time is defined in the IEEE 1394-1995 standard). This bit is used by the link in its busylretry state machine.

Subaction Gap

This bit indicates that the TSBllCOl has detected that the bus has been idle for a subaction gap time (this time
is defined in the IEEE 1394-1995 standard). This bit is used by the link to detectthe completion of an isochronous
cycle.

Bus Reset

This bit indicates that the TSBll COl has entered the bus reset state

State Time Out

The TSBllCOl has stayed in a particular state for too long.

4-7

Address

These bits hold the address of the TSBll COl register whose contents are transferred to the link.

8-15

Data

The data that is to be sent to the link

Normally, the TSB11 C01 sends just the first 4 bits of status data to the link. These bits are used by the link state
machines; however, when the link has initiated a read register request the TSB11C01 sends the full status
packet to the link (see Figure 6). The TSB11 C01 also sends a full status packetto the link if it has some important
information to pass on to the link. Currently, the only condition where this occurs is after the self identification
process when the TSB11 C01 needs to inform the link of its new node address (physical 10 register).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-17

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION
status request (continued)

... '2RkX

TSB11C01
CTL[0:1]

•••

TSB11C01
0[0:1]

•••

.r.::v-:V!V-v ... ~'AD.I
~

S(2,3)

Figure 6. Status Transfer Timing
There may be times where the TSB11 C01 wants to start a second status transfer. The TSB11 C01 waits at least
one clock cycle with the CTL lines idle before it begins a second transfer.

transmit
When the link wants to transmit information, it first requests access to the bus through the LREQ line. When
the TSB11 C01 receives this request, it arbitrates to gain control of the bus. When the TSB11 C01 wins ownership
of the bus, it grants the bus to the link by asserting the transmit state on the CTL terminals for at least one
SYSCLK cycle. The link takes control of the bus by asserting either hold or transmit on the CTL lines. Hold is
used by the link to keep control of the bus if it needs more time to prepare the data for transmission. The
TSB 11 C01 keeps control of the bus for the link by asserting a data-on state on the bus. It is not necessary for
the link to use hold when it is ready to transmit as soon as bus ownership is granted.
When the link is prepared to send data, it asserts transmit on the CTL lines as well as sending the first bits of
the packet onthe D[O:1] lines. The transmit state is held on the CTL terminals until the last bits of data have been
sent. The link then asserts idle on the CTL lines for one clock cycle, after which it releases control of the interface.
There are times when the link needs to send another packet without releasing the bus. For example, the link
may want to send consecutive isochronous packets or it may want to attach a response to an acknowledgment.
To do this, the link asserts hold instead of idle when the first packet of data has been completely transmitted.
Hold, in this case, informs the TSB11 C01 that the link needs to send another packet without releasing control
of the bus. The TSB11 C01 waits a set amount of time before asserting transmit, and the link can then proceed
with the transmission of the second packet. After all data has been transmitted and the link has asserted idle
on the CTL lines, the TSB11C01 asserts its own idle state on the CTL lines. When sending multiple packets in
this fashion, all data must be transmitted at the same speed. This is because the transmission speed is set
during arbitration, and since the arbitration step is skipped, there is no way of informing the network of a change
in speed.

~TEXAS

INSTRUMENTS
4-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB11C01
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS167A- MARCH 1994- REVISED MARCH 1996

PRINCIPLES OF OPERATION

transmit timing
Transmit timing is shown in Figure 7.
TSB11C01 •••
CTL[0:1]
TSB11C01 •••
0[0:1]

Link
CTL[0:1]

•••

Link
0[0:1]

•••

~ ••• ~ ••• ~•••
~

~ ••• ~ ••• ~•••
~~~

~ ••• ~ ••• ~•••
~

"C...J'\.:../\

~ ••• ~ ••• ~•••

~~~
SINGLE PACKET

TSB11C01 •••
CTL[0:1]
TSB11C01 •••
0[0:1]

~••• ~••• ~ •••
~

~••• ~••• ~ •••

~~~

Link
CTL[0:1]

•••

~••• ~••• ~ •••

Link
0[0:1]

•••

~••• ~••• ~ •••

~~~
CONTINUED PACKET

zz. =high-impedance state

DO - Dn = packet data

Figure 7. Transmit Timing

receive operation
When data is received by the TSB11 C01 from the serial bus, it transfers the data to the link for further processing.
The TSB11C01 asserts receive (10) on the CTL lines and 11 on the D lines. The TSB11C01 indicates the start
of the packet by placing the speed code on the data bus. The TSB11 C01 then proceeds with the transmission
of the packet to the link on the D lines while keeping the receive status on the CTL lines. Once the packet has
been completely transferred, the TSB11C01 asserts idle on the CTL lines to complete the receive operation.
The speed code is a phy link protocol and not included in the CRC.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-19

TSB11C01
IEEE 1394·1995 TRIPLE·CABLE TRANSCEIVER/ARBITER
SLLS167A - MARCH 1994 - REVISED MARCH 1996

PRINCIPLES OF OPERATION

receive timing
The receive timing is shown in Figure 8.

•••

TSB11C01
CTL[0:1]

•••

"C../\.J\

TSB11C01
D[0:1]

•••

"\:../\.J\

SPO = speed code

~
~

00 - On

=packet data

Figure 8. Receive Timing
The speed code for the receiver is shown in Table 11.
Table 11. Receiver Speed Code
DATA RATE
100 Mbits/s

~TEXAS

INSTRUMENTS
4-20

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

•••

"C/\:.J\.:../\

TSB12C01A
Data Manual

1394 High-Speed Serial-Bus
Link-Layer Controller

-!II
TEXAS
INSTRUMENTS
4-21

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to
discontinue any semiconductor product or service without notice, and advises its
customers to obtain the latest version of relevant information to verify, before placing
orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the
specifications applicable at the time of sale in accordance with TI's standard warranty.
Testing and other quality control techniques are utilized to the extent TI deems necessary
to support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the
customer. Use of TI products in such applications requires the written approval of an
appropriate TI officer. Questions concerning potential risk applications should be directed
to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design
and operating safeguards should be provided by the customer to minimize inherent or
procedural hazards.
TI assumes no liability for applications assistance, customer product deSign, software
performance, or infringement of patents or services described herein. Nor does TI
warrant or represent that any license, either express or implied, is granted under any
patent right, copyright, mask work right, or other intellectual property right of TI covering
or relating to any combination, machine, or process in which such semiconductor
products or services might be or are used.

4-22

Contents
Section

Title

Page

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.1 Description..........................................................
1.2 Features............................................................
1.2.1 Link..........................................................
1.2.2 Physical-Link Interface .........................................
1.2.3 Host Bus Interface .............................................
1.2.4 General ......................................................

4-29
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4-29
4-29
4-29

Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1 Functional Block Diagram .............................................
2.1.1 Physical Interface ..............................................
2.1.2 Transmitter....................................................
2.1.3 Receiver......................................................
2.1.4 Transmit and Receive FIFOs ....................................
2.1.5 Cycle Timer ................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.1.6 Cycle Monitor .................................................
2.1.7 Cyclic Redundancy Check (CRC) ................................
2.1.8 Internal Registers ..............................................
2.1.9 Host Interface .................................................
2.2 Terminal Assignments and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.1 Terminal Assignments ............................ . . . . . . . . . . . . ..
2.2.2 Terminal Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2.3 TSB12C01A Terminal Functions ......... , .... " .................

4-31
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4-31
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4-32
4-32
4-32
4-33
4-33
4-33
4-33
4-34
4-34
4-35
4-35

Internal Registers .......................................................
3.1 General ............................................................
3.2 Internal Register Definitions ...........................................
3.2.1 Version/Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.2 Node-Address/Transmitter Acknowledge Register. . . . . . . . . . . . . . . . ..
3.2.3 Control Register ...............................................
3.2.4 Interrupt and Interrupt-Mask Registers. . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.2.5 Cycle-Timer Register ...........................................
3.2.6 Isochronous Receive-Port Number Register . . . . . . . . . . . . . . . . . . . . . ..
3.2.7 Diagnostic Control and Status Register ...........................
3.2.8 Phy-Chip Access Register ......................................
3.2.9 Phy-Interface State Register ....................................
3.2.10 Other State Register ...........................................
3.2.11 Asynchronous Transmit-FI Fa (AT F) Status Register. . . . . . . . . . . . . . ..
3.2.12 ITF Status Register ............................................
3.2.13 GRF Status Register ...........................................

4-39
4-39
4-39
4-41
4-41
4-41
4-43
4-45
4-45
4-46
4-47
4-47
4-48
4-48
4-49
4-49
4-23

Contents (continued)
Section
3.3

Title

Page

FIFO Access ........................................................
3.3.1 General ......................................................
3.3.2 ATF Access ...................................................
3.3.3 ITF Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3.4 General-Receive-FIFO (GRF) ...................................
3.3.5 RAM Test Mode ...............................................

4-50
4-50
4-50
4-51
4-51
4-51

TSB12C01 A Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . ..
4.1 Asynchronous Transmit (Host Bus to TSB12C01 A) .......................
4.1.1 Quadlet Transmit ..............................................
4.1.2 Block Transmit ................................................
4.1.3 Quadlet Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.1.4 Block Receive .................................................
4.2 Isochronous Transmit (Host Bus to TSB12C01A) ........................
4.3 Isochronous Receive (TSB12C01A to Host Bus) .........................
4.4 Snoop..............................................................
4.5 CycleMark..........................................................
4.6 Phy Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4.7 Receive Self-ID ......................................................

4-53
4-53
4-53
4-54
4-54
4-55
4-57
4-57
4-58
4-59
4-59
4-60

Electrical Characteristics ...........•....................................
5.1 Absolute Maximum Ratings Over Free-Air Temperature Range ............
5.2 Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature ...................................
5.4 Host-Interface Timing Requirements Over Operating Free-Air
Temperature Range ................ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.5 Host-Interface Switching Characteristics Over Operating Free-Air
Temperature Range, CL = 45 pF .......................................
5.6 Phy-Interface Timing Requirements Over Operating Free-Air
Temperature Range ..................................................
5.7 Phy-Interface Switching Characteristics Over Operating Free-Air
Temperature Range, CL = 45 pF .......................................
5.8 Miscellaneous Timing Requirements Over Operating Free-Air
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5.9 Miscellaneous Signal Switching Characteristics Over Operating Free-Air
Temperature Range ..................................................

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4-63
4-63
4-63
4-63

Parameter Measurement Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-65

TSB12C01 A to Phy Interface Specification ................................
7.1 Introduction .........................................................
7.2 Assumptions ........................................................
7.3 Block Diagram .......................................................
7.4 Operational Overview ................................................
7.4.1 . Phy Interface Has Control of the Bus .............................

4-24

4-69
4-69
4-69
4-69
4-69
4-70

Contents (continued)
Section
7.5

Title

Request............................................................
7.5.1 LREQ Transfer ................................................
7.5.2 Bus Request ..................................................
7.5.3 ReadlWrite Requests ...........................................
7.6 Status ..............................................................
7.6.1 Status Request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7.6.2 Transmit ......................................................
7.6.3 Receive ......................................................
7.7 TSB12C01A to Phy Bus Timing ........... , ............................
8

Page
4-70
4-70
4-71
4-72
4-72
4-72
4-73
4-74
4-74

Mechanical Data .. ....................................................... 4-77

4-25

List of Illustrations
Figure

Title

Page

2-1
2-2

TSB12C01ABIock Diagram ........................................... 4-31
TSB12C01A Terminal Functions ....................................... 4-35

3-1
3-2
3-3

Internal Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-40
Interrupt Logic Diagram Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4-43
TSB12C01A Controller-FIFO-Access Address Map. . .. . . . . ... ... . . . .. . . . . 4-50

4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10

Quadlet-Transmit Format .............................................
Block-Transmit Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Quadlet-Receive Format ............................................ ..
Block-Receive Format ................................................
Isochronous-Transmit Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Isochronous-Receive Format ..........................................
Snoop Format .......................................................
CycleMark Format ...................................................
Phy Configuration Format .......................................... . ..
Receive Self-ID Format ......................... '" ...................

4-53
4-54
4-55
4-56
4-57
4-57
4-58
4-59
4-59
4-60

6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10

BCLK Waveform .....................................................
Host Interface Write Cycle Waveforms ..................................
Host Interface Read Cycle Waveforms ..................................
SCLK Waveform .....................................................
TSB12C01A-to-Phy-Layer Transfer Waveforms. . . . . . . . . . . . . . . . . . . . . . . . ..
Phy-Layer-to-TSB12C01A Transfer Waveforms. . . . . . . . . . . . . . . . . . . . . . . . ..
TSB 12C01 A-Link-Request-to-Phy-Layer Waveforms .....................
Interrupt Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CYCLEIN Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
CYCLEIN and CYCLEOUT Waveforms .................................

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4-66
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4-67
4-67
4-68
4-68

7-1
7-2
7-3
7-4
7-5

Functional Block Diagram of the TSB12C01A to Phy Layer. . . . . . . . . . . . . . ..
LREQ Timing ........................................................
Status-Transfer Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Receiver Timing .....................................................

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4-74
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4-75

4-26

List of Tables
Table

Title

Page

2-1
2-2
2-3

Host Bus Interface Terminal Functions ................................ .
Phy Interface Terminal Functions .................................... .
Miscellaneous Signals Terminal Functions ............................ .

4-35
4-36
4-36

3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13

Version/Revision Register Field Descriptions .......................... .
Node-Address/Transmitter Acknowledge Register Field Descriptions ..... .
Control-Register Field Descriptions ................................... .
Interrupt- and Mask-Register Field Descriptions ........................ .
Cycle-Timer Register Field Descriptions .............................. .
Isochronous Receive-Port Number Register Field Descriptions .......... .
Diagnostic Control and Status-Register Field Descriptions ............... .
Phy-Chip Access Register .......................................... .
Phy-Interface State Register ........................................ .
Other State Register ............................................... .
ATF Status Register ................................................ .
ITF Status Register ................................................ .
GRF Status Register ............................................... .

4-41
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4-41
4-44
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4-45
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4-49
4-49

4-1
4-2
4-3
4-4
4-5
4-6
4-7
4-8
4-9
4-10

Quadlet-Transmit Format ........................................... .
Block-Transmit Format Functions .................................... .
Quadlet-Receive Format Functions .................................... .
Block-Receive Format Functions ..................................... .
Isochronous-Transmit Functions ..................................... .
Isochronous-Receive Functions ...................................... .
Snoop Functions ................................................... .
CycleMark Functions ............................................... .
Phy Configuration Functions ........................................ .
Receive Self-ID Functions .......................................... .

4-53
4-54
4-55
4-56
4-57
4-58
4-58
4-59
4-59
4-60

7-1
7-2
7-3
7-4
7-5
7-6
7-7

Phy Interface Control of Bus Functions ............................... .
TSB12C01A Control of Bus Functions ................................ .
Request Functions ................................................. .
Bus-Request Functions (Length of Stream: 7 Bits) ..................... .
Read-Register Request Functions (Length of Stream: 9 Bits) ............ .
Write-Register Request (Length of Stream: 17 Bits) .................... .
TSB12C01A Request Functions ..................................... .

4-70
4-70
4-70
4-70
4-71
4-71
4-71

4-27

List of Tables
Table

Title

7-8
TSB12C01A Request-Speed Functions .......... " . .. . .. . . . .. . . . .. . . . .
7-9
Status-Request Functions (Length of Stream: 16 Bits) ...................
7-10 Speed Code for Receive.. . . .. . . .. ... . . . . . . . . . . .. . .. . .. . . . . . . . . .. . . ..

4-28

Page

4-71
4-73
4-74

1 Overview
1.1

Description

The TSB12C01A is an IEEE-1394 standard (from now on referred to only as 1394) high-speed serial-bus
link-layer controller that allows for easy integration into an 1/0 subsystem. The TSB12C01A transmits and
receives correctly formatted 1394 packets and generates and inspects the 32-bit cyclic redundancy check
(CRC). The TSB12C01 A is capable of being a cycle master and supports reception of isochronous data on
two channels. It interfaces directly to the TSB11 C01 , TSB11 LV01 , and TSB21 LV03 physical-layer chips and
can support bus speeds of 100,200, and 400 Mb/s. The TSB 12C01 A has a generic 32-bit host bus interface,
which makes connection to most 32-bit host buses very simple. The TSB12C01 A has software-adjustable
FIFOs for optimal FIFO size and performance characterization and allows for variable-size
asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO (ITF), and general-receive FIFO (GRF).
This document is not intended to serve as a tutorial on 1394; users should refer to the IEEE draft standard
1394 serial bus for detailed information regarding the 1394 high-speed serial bus.

1.2

Features

The following are features of the TSB12C01 A.

1.2.1

Link

•
•
•
•
•
•
•
1.2.2

Complies With IEEE-1394 Standard Version 7.1v1
Transmits and Receives Correctly Formatted 1394 Packets
Supports Isochronous Data Transfer
Performs Function of Cycle Master
Generates and Checks 32-Bit CRC
Detects Lost Cycle-Start Messages
Contains Asynchronous, Isochronous, and General-Receive FIFOs

Physical-Link Interface

•
•
•
1.2.3

Interfaces Directly to the TSB11C01, TSB11 LV01, and TSB21 LV03 Phy Chips
Supports Speeds of 100, 200, and 400 Mb/s
Implements the Physical-Link Interface Described in Annex J of the IEEE-1394 Standard

Host Bus Interface
•
•
•

1.2.4

Provides Chip Control With Directly Addressable Registers
Is Interrupt Driven to Minimize Host Polling
Has a Generic 32-Bit Host Bus Interface

General
•
•
•

Requires a Single 5-V ±5% Power Supply
Manufactured with low-Power CMOS Technology
Packaged in a 100-Pin thin quad flat package (TQFP) (PZ Package)

4-29

4-30

2 Architecture
2.1

Functional Block Diagram

The functional block architecture of the TSB12C01A is shown in Figure 2-1.

r-------------------,
.. P
Transmitter

r---'
..

o
s
t

I
n
t

I
I
lj

I
I

ATF 1-+----1

I
I
I
I
I --- I
I
I
I
I
I
ITF
I
1----1_...
1-+---'

r
f

I
I --I
I
~ I GRF

a
c
e

'--

I
I
I
I
I

I
I
I
I
I
II
I
I
I
I
I
I

rrll~~'---1r-1

L-f-~

Cycle Timer

Cycle Monitor

I
I

c
a
I

I I
CRC

Receiver

n
t

e
r
f

a
c
e

L--------l----------~

Configuration Registers

Figure 2-1. TSB12C01A Block Diagram

2.1.1

Physical Interface

The physical (phy) interface provides phy-Ievel services to the transmitter and receiver. This includes
gaining access to the serial bus, sending packets, receiving packets, and sending and receiving
acknowledge packets.
The phy interface module also interfaces to the phy chip and conforms to the phy-link interface specification
described in Annex J of the IEEE-1394 standard (refer to section 7 of this document for more information).

2.1.2

Transmitter

The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus
packets to be transmitted through the phy interface. When data is present at the ATF interface to the
transmitter, the TSB12C01A phy interface arbitrates for the serial bus and sends a packet. When data is
present at the ITF interface to the transmitter, the TSB12C01A arbitrates for the serial bus during the next
isochronous cycle. The transmitter autonomously sends the cycle-start packets when the chip is a cycle
master.

4-31

2.1.3

Receiver

The receiver takes incoming data from the phy interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header
CRC is good, the header is confirmed in the GRF. For block and isochronous packets, the remainder of the
packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last
quadlet of the packet is confirmed in the GRF. The status quadlet contains the error code for the packet. The
error code is the acknowledge code that is sent for that packet. For broadcast packets that do not need
acknowledge packets, the error code is the acknowledge code that would have been sent. This
acknowledge code tells the transaction layer whether or not the data CRC is good or bad. When the header
CRC is bad, the header is flushed and the rest of the packet is ignored.
.
When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages are not placed in the GRF like other quadlet packets. At the end of an
isochronous cycle and if the cycle mark enable (CyMrkEn) bit of the control register is set, the receiver
inserts a cycle-mark packet in the GRF to indicate the end of the isochronous cycle.

2.1.4

Transmit and Receive FIFOs

The TSB12C01A contains two transmit FIFOs (asynchronous and isochronous) and one receive FIFO
(general receive). Each of these FIFOs are one quadlet wide and their length is software adjustable. These
software-adjustable FIFOs allow customization of the size of each FI FO for individual applications. The sum
of all FI FOs cannot be larger than 509 quadlets. To understand how to set the size of the FI FOs, see sections
3.2.11 through 3.2.13. The transmit FIFOs are write only from the host bus interface, and the receive FIFO
is read only from the host bus interface.
An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the
implementer can set the ITF and GRF to a large size (200 quadlets each) and set the ATF to a smaller
size (100 quadlets). Notice that the sum of all FIFOs is less than or equal to 509 quadlets.

2.1.5

Cycle Timer

The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE-1394 standard. In the TSB12C01A, the cycle-timer register is implemented in the cycle
timer and is located in IEEE-1212 initial register space at location 200h and can also be accessed through
the local bus at address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which increments
once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count of 8, OOO-Hz
(or 125 ~s)cycles, and the highest 7 bits count seconds.
The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle
offset, cycle count, and seconds count. The cycle timer has two possible sources. First, if the cycle source
(CySrc) bit in the configuration register is set, then the CYCLEIN input causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is cycle master. When the cycle-count field increments,
CYCLEOUT is generated. The timer can also be disabled using the cycle-timer-enable bit in the control
register. See section 3.2.5, Cycle-Timer Register for more information.
The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 ~s.

4-32

CYCLEOUT indicates to the cyclemaster node that it is time to send a cycle-start packet. And, on
noncyclemaster nodes, CYCLEOUT indicates that it is time to expect a cycle-start packet. The cycle-start
bit is set when the cycle-start packet is sent from the cyclemaster node or received by a noncyclemaster
node.

2.1.6

Cycle Monitor

Tflecycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cycle-master bit is set in the control register.

2.1.7

Cyclic Redundancy Check (CRC)

The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The
CRC module generates the header and data CRC for transmitting packets and checks the header and data
CRC for received packets. See the IEEE-1394 standard for details on the generation of the CRCt.

2.1.8

Internal Registers

The internal registers control the operation of the TSB12C01A. The register definitions are specified in
section 3.

2.1.9

Host Bus Interface

The host bus interface allows the TSB12C01A to be easily connected to most host processors. This host
bus interface consists of a 32-bit data bus and an a-bit address bus. The TSB12COtA utilizes cycle-start
and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be
asynchronous to one another. The TSB12C01A is interrupt driven to reduce polling.

This is the same CRC used by the IEEE802 LANs and the X3T9.5 FOOL

4-33

2.2

Terminal Assignments and Functions

2.2.1

Terminal Assignments
To Phy Layer

i
~~~~~Rffi~~~~~~~~gmm~~m~~~~
POWERON
RAMEz
GND
GND
GND
GND
DATAO

76
77
78
79
80

50
49
48
47
46

DATA2
DATA3

PZ PACKAGE

DATA4
87
DATA5
88
DATA6 ====::11 89
DATA790
GND
91
DATA8
92
DATA9
93
DATA10
94
DATA11
95
~

DATA12
DATA13
DATA14
DATA15

(TOP VIEW)

39
38
37
36
35
34
33
32
31

97
98
99
1000

29
28
27
26

O~~M~~~~mmO~~M~~

~N~v~w~~m~~~~~~~~~~NNNNNN

To Host
NOTES: A. lie reserved terminals to GND.
B. Bit 0 is the most significant bit (MSB).

4-34

CYST
CYDNE
GRFEMP
GND
GND
GND
CYCLEOUT
VCC
CYCLEIN
GND
GND
RESET
GND
INT
WR
CA
CS
VCC
BCLK
GND
ADDR7
ADDR6
ADDR5
ADDR4
VCC

2.2.2

Terminal Functions
DATA[0:31]

....

TSB12C01A

ADDR[0:7]
CS

Host Bus

CA
WR
INT
CYCLEIN
CYCLEOUT
BCLK
RESET
RAMEz
NTCLK
NTOUT
NTBIHIZ

...

....
...

....

.......

CTLO

CTL1

....,

...

..
..
..
r

0[0:7]

LREQ
ISO
SCLK

10 L
"/

" 22

VCC
GND
POWERON

...

.....

CYST

GRFEMP

Phy Interface

CYONE

Figure 2-2. TSB12C01A Terminal Functions

2.2.3

TSB12C01A Terminal Functions
Table 2-1. Host Bus Interface Terminal Functions
TERMINAL

I/O

DESCRIPTION

22-25
27-30

Address 0 through address 7. Host bus address bus bits 0 through 7 that address
the quad let-aligned FIFOs and configuration registers. The two least significant
address lines, 6 and 7, must be grounded.

Cycle acknowledge (active low). CA is a TSB12C01A control signal to the host bus.
When asserted (low), access to the configuration registers or FIFO is complete.

Cycle start (active low). CS is a host bus control signal to enable access to the
configuration registers or FIFO.

2-5
7-10
12-15
17-20
82-85
87-90
92-95
97-100

I/O

Data 0 through 31. DATA is a host bus data bus bits 0 through 31.

INT'

Interrupt (active low). When INT is asserted (low), the TSB12C01 A notifies the host
bus that an interrupt has occurred.

Read/write enable. When WR is deasserted (high) in conjunction with CS, a read
from the TSB12C01A is requested. When WR is asserted (low) in conjunction with
CS, a write to the TSB12C01A is requested.

NAME

ADDR[0:7]

DATA [0:31]

NO.

4-35

Table 2-2. Phy Interface Terminal Functions
TERMINAL

1/0

DESCRIPTION

62,63

1/0

Control 1 and control 0 of the phy-link control bus. CTL 1 and CTLO indicate the four
operations that can occur in this interface (see section 7 or annex J of the IEEE-1394
standard for more information about the four operations).

52-55
57-60

1/0

Oata 0 through data 7 of the phy-link data bus. Oata is expected on 0[0:1] for
100 Mb/s packets, 0[0:3] for 200 Mb/s, and 0[0:7] for 400 Mb/s.

ISO

Isolation barrier (active low). This ISO is asserted (low) when an isolation barrier is
present.

LREQ

Link request. LREQ is a TSB12C01 A output that makes bus requests and accesses
the phy layer.

POWERON

Power on indicator to phy interface. When active, POWERON has a clock output with
1/32 of the BCLK frequency and indicates to the phy interface that the TSB12C01A
is powered.

NAME

NO.

CTL1, CTLO

0[0:7]

Table 2-3. Miscellaneous Signals Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

BClK

Bus clock. BCLK is the host bus clock used in the host-interface module of the
TSB12C01A. It is asynchronous to SCLK.

CYCLEIN

Cycle in. CYCLEIN is an optional externaI8,000-Hz clock used as the cycle clock,
and it should only be used when attached to the cycle-master node. It is enabled
by the cycle source bit and should be tied high when not used.

CYCLEOUT

Cycle out. CYCLEOUT is the TSB12C01A version of the cycle clock. It is based
on the timer controls and received cycle-start messages.

CYONE

Status of CyOne bit. When the RevAEn bit of the control register is set, CYONE
indicates the value of the CyOne bit of the interrupt register. When RevAEn is
cleared, CYONE is a 3-state output.

CYST

Status of CySt bit. When the RevAEn bit of the control register is set, CYST
indicates the value of the CySt bit of the interrupt register. When RevAEn is
cleared, CYST is a 3-state output.

GNO

1, 11, 21,
31,38,40,
41,45-47,
51,61,66,
68,70,
78-81,91

Ground reference

GRFEMP

Status of Empty bit. When the RevAEn bit of the control register is set, GRFEMP
indicates the value of the Empty bit of the GRF status register. When RevAEn is
cleared, GRFEMP is a 3-state output.

RAMEz

RAM 3-state enable. When RAMEz is deasserted (low), FIFOs are enabled. When
RAMEz is asserted, the FIFOs are 3-state outputs. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

NTBIHIZ

NANO-tree bidirectional 3-state output. When NTBIHIZ is deasserted (low), the
bidirectionall/Os operate in a normal state. When NTBIHZ is asserted (high), the
bidirectional I/Os are in the 3-state output mode. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

4-36

Table 2-3. Miscellaneous Signals Terminal Functions (Continued)
NTCLK

NAND clock input. The NAND-tree clock is used for VIH and VIL manufacturing
tests. (This input should be grounded under normal operating conditions.)

NTOUT

NAND-tree output. This output should remain open under normal operating
conditions.

RESET

Reset (active low). RESET is the asynchronous reset to the TSB12C01A.

SCLK

System clock. SCLK is a 49.152-MHz clock from the phy, that generates the
24.576-MHz clock.

VCC

6,16,26,
33,43,56,
64,74,86,
96

5-V ±5% power supplies

4-37

4-38

3 Internal Registers
3.1

General

The host-bus processor directs the operation of the TSB12C01A through a set of registers internal to the
TSB12C01A itself. These registers are read or written by asserting CS with the proper address on
ADDR[O:7] and asserting or deasserting WR depending on whether a read or write is needed. Figure 3-1
lists the register addresses; subsequent sections describe the function of the various registers.

3.2

Internal Register Definitions

The TSB 12C01 A internal registers control the operation of the TSB 12C01 A. The bit definitions of the internal
registers are shown in Figure 3-1 and are described in sections 3.2.1 through 3.2.13.

4-39

Figure 3-1. Internal Register Map

OOh

Version

04h

Node
Address

08h

Control

OCh

Interrupt

10h

Interrupt
Mask

14h

Cycle
Timer

18h

Isoch Port
Number

1Ch

Reserved

20h

Diagnostics

24h

PhyChip
Access

28h

Phy
Interface
State

2Ch

Other
State

30h

Size

ATF Status

34h

Size

ITF Status

38h

Reserved

3Ch

GRF Status

40h

Reserved

NOTE A: All gray areas (bits) are reserved bits.

4-40

3.2.1

Version/Revision Register

The version/revision register allows software to be written that supports multiple versions of the high-speed
serial-bus link-layer controllers. This register is at address OOh and is read only. The initial value is
3031_3041h.

Table 3-1. Version/Revision Register Field Descriptions
BITS

ACRONYM

0-15
16-31

3.2.2

DESCRIPTION

FUNCTION NAME

Version

Version of the TSB12C01A

Revision

Revision of the
TSB12C01A

Node-AddresslTransmitter Acknowledge Register

The node-address/transmitter acknowledge register controls which packets are accepted/rejected, and it
presents the last acknowledge received for packets sent from the ATF. This register is at offset 04h. The
bus number and node number fields are read/write. The AT acknowledge (ATAck) received is normally read
only. Setting the regRW bit in the diagnostic register makes these fields read/write. The initial value is
FFFF_OOOOh.

Table 3-2. Node-Address/Transmitter Acknowledge Register Field Descriptions
DESCRIPTION

BITS

ACRONYM

0-9

BusNumber

Bus number

BusNumber is the 10-bit IEEE 1212 bus number that the
TSB12C01A uses with the node. number in the SOURCE
address for outgoing packets and to accept or reject incoming
packets. The TSB12C01A always accepts packets with a bus
number equal to 3FFh.

10-15

NodeNumber

Node number

NodeNumber is the 6-bit node number that the TSB12C01A
uses with the bus number in the source address for outgoing
packets and to accept or reject incoming packets. The
TSB12C01A always accepts packets with the node address
equal to 3Fh. See BlkBusOep bits for exceptions.

16-23

Reserved

24-27

ATAck

Address transmitter
acknowledge
received

ATAck is the last acknowledge received by the transmitting
node in response to a packet sent from the asynchronous
transmit-FIFO.

28-31

Reserved

3.2.3

FUNCTION NAME

Control Register

The control register dictates the basic operation of the TSB 12C01 A. This register is at address 08h and is
read/write. The initial value is OOOO_OOOOh.

Table 3-3. Control-Register Field Descriptions
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

IdVal

10 Valid

When IdVal is set, the TSB 12C01 A accepts packets addressed
to the IEEE 1212 address set (Node Number) in the
node-address register. When IdVal is cleared, the TSB12C01 A
accepts only broadcast packets.

RxSld

Received self-IO
packets

When RxSld is set, the self·identification packets generated by
phy chips during bus initialization are received and placed into
the GRF as a single packet. Each self· identification packet is
composed of two quadlets, where the second quad let is the
logical inverse of the first. If ACK (4 bits) equals 1h, then the
data is good. If ACK equals Oh, then the data is wrong.

4-41

Table3-3. Control-Register Field Descriptions (Continued)
BITS

ACRONYM

FUNCTION NAME

2-4

BsyCtrl

Busy control .

These bits control which busy status the chip returns to incoming
packets. The field is defined as below:
000 = follow normal busy/retry protocol, only send busy when
necessary.
001 = sendbusyA when it is necessary to send a busy acknowledge.
010 = send busyB when it is necessary to send a busy
acknowledge.
011 = reserved
100 = send a busy acknowledge to all incoming packets following the
normal busy/retry protocol.
101 = send a busy acknowledge to all incoming packets by sending
a busyA acknowledge.
110 = send a busy acknowledge to all incoming packets by sending
a busyB acknowledge.
111 = reserved
When retry_X is received and the receiving node needs to send a busy
acknowledge signal, it sends an ack_busy_X Signal.

TxEn

Transmitter enable

When TxEn is cleared, the transmitter does not arbitrate or send
packets.

RxEn

Receiver enable

When is RXEn cleared, the receiver does not receive any packets.

PSBz

Physical DMA
busy

When:
1) PSOn is set,
2) PSRO is cleared or the incoming packet is a read,
3) destination offset is in lower 4 Gbytes, and
4) PSBz is set,
the TSB12C01A sends a busy acknowledge to the incoming packet.

PSOn

Physical DMA on

When PSOn is set, the TSB 12C01 A uses PSRO and PSBz to determine
acceptance of incoming request packets addressed to the lower
4 Gbytes of initial memory space.

PSRO

Physical DMA read
only

When PSOn is set, the TSB12C01A uses PSRO to determine
acceptance of incoming write request packets addressed to the lower
4 Gbytes of initial memory space.

RstTx

Reset transmitter

When RstTx is set, the entire transmitter resets synchronously. This bit
clears itself.

RstRx

Reset receiver

When RstRx is set, the entire receiver resets synchronously. This bit
clears itself.

12-15

BlkBusDep

Block i:)usdependent
address

This field is used by the receiver to filter out broadcast packets to the
bus-dependent area of CSR space. Setting the LSB of this field disables
the reception of broadcast packets to the lowest 128 bytes of
bus-dependent CSR space. Setting the MSB of this field disables the
reception of broadcast packets to the highest 128 bytes of
bus-dependent CSR space.

16-17

ATRC

AT retry code

This field contains the last retry code received. This code is logically
ORed with the retry code field (00) in the transmit packet, and the packet
is resent. This alleviates the need to change the retry code in the transmit
packet. The retry encoding follows the IEEE-1394 standard 7.1v1. The
retry code is as follows:
retry_o (new)
01
retry_X
00
retry_A
11
retry_B
10

4-42

DESCRIPTION

Table 3-3. Control-Register Field Descriptions (Continued)
BITS

ACRONYM

18-19 Reserved

FUNCTION NAME

DESCRIPTION

Reserved

CyMas

Cycle master

When CyMas is set and the TSB 12C01 A is attached to the root phy, the
cyclemaster function is enabled. When the CYCle_count field of the cycle
timer register increments, the transmitter sends a cycle-start packet.

CySrc

Cycle source

When CySrc is set, the cycle_count field increments and the
cycle_offset field resets for each positive transition of CYCLEIN. When
CySrc is cleared, the CYCle_count field increments when the cycle_offset
field rolls over.

CyTEn

Cycle~timer enable

When CyTEn is set, the cycle_offset field increments.

CyMrkEn

Cycle mark enable

When CyMrkEn is set, cycle marks are inserted into GRF at the end of
each isochronous cycle (TSB12C01A compatible). When CyMrkEn is
cleared, no cycle marks are generated.

IRP1En

IR port 1 enable

When IRP1 En is set, the receiver accepts isochronous packets when
the channel number matches the value in the IR Port1 field.

IRP2En

IR port 2 enable

When IRP2En is set, the receiver accepts isochronous packets when
the channel number matches the value in the IR Port2 field.

26-30

Reserved

RevAEn

3.2.4

Interrupt and Interrupt-Mask Registers

The interrupt and interrupt-mask registers work in tandem to inform the host bus interface when the state
of the TSB12C01A changes. The interrupt register is at address OCh. The interrupt mask register is at
address 1Oh. The interrupt mask register is read/write. Its initial value is OOOO_OOOOh. When regRW is zero,
the interrupt register (except for the Int bit) is write to. clear. When regRW is set, the interrupt register
(including the Int bit) is read/write. Its initial value is 1000_0000h.
The interrupt bits all work the same. For example, when a phy interrupt occurs, the Phlnt bit is set. When
the PhlntMask bit is set, the Int bit is set. When the IntMask is set, the INT signal is asserted. The logic for
the interrupt bits is shown in Figure 3-2. Table 3-4 defines the interrupt and interrupt-mask register field
descriptions.
Phlnt Source
DATA (01)
WR

CS
SCLK

PhlntBit

Set

,...
,...

Clear

Phlnt Bit

Clk

0 t--------~-

- - - - Interrupt Bit (INT)

PhlntMask Bit - - - ,

Other
Interrupts

Interrupt Bit
IntMask Bit

--L/
'

----D-------

Figure 3-2. Interrupt Logic Diagram Example
4-43

Table 3-4. Interrupt- and Mask-Register Field Descriptions
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Int

Interrupt

Int contains the value of all interrupt and interrupt mask bits ORed
together.

Phlnt

Phy chip interrupt

When Phlnt is set, the phy chip has signaled an interrupt through the
Phy interface.

PhyRRx

Phy register
information received

When PhyRRx is set, a register value has been transferred to the phy
chip access register (offset 24h) from the Phy interface.

PhRst

Phy reset started

When PhRst is set, a phy-Iayer reconfiguration has started (1394 bus
reset).

Reserved

TxRdy

Transmitter ready

When TxRdy is set, the transmitter is idle and ready.

RxDta

Receiver has data

When RxDta is set, the receiver has confirmed data to the GRF
interface.

CmdRst

Command reset
received

When CmdRst is set, the receiver has been sent a quadlet write
request addressed to the RESET_START CSR register.

Reserved

ITStk

Transmitter is stuck
(IT)

When ITStk is set, the transmitter has detected invalid data at the
isochronous transmit-FIFO interface.

ATStk

Transmitter is stuck
(AT)

When ATStk is set, the transmitter has detected invalid data at the
asynchronous transmit-FIFO interface. If the first quadlet of a packet
is not written to the ATF_First or ATF_First&Update, the transmitter
enters a state denoted by an ATStuck interrupt. An underflow of the
ATF also causes an ATStuck interrupt. If this state is entered, no
asynchronous packets can be sent until the ATF is cleared via the CLR
ATF control bit. Isochronous packets can be sent while in this state.

Reserved

SntRj

Busy acknowledge
sent by receiver

When SntRj is set, the receiver is forced to send a busy acknowledge
to a packet addressed to this node because the GRF overflowed.

HdrEr

Header error

When HdrEr is set, the receiver detected a header CRC error on an
incoming packet that may have been addressed to this node.

TCErr

Transaction code
error

When TCErr is set, the transmitter detected an invalid transaction code
in the data at the transmit FIFO interface.

8-10

17-19

Reserved

CySec

Cycle second
incremented

When CySec is set, the cycle-second field in the cycle-timer register
incremented. This occurs approximately every second when the cycle
timer is enabled.

CySt

Cycle started

When CySt is set, the transmitter has sent or the receiver has received
a cycle-start packet.

CyDne

Cycle done

When CyDne is set, an arbitration gap has been detected on the bus
after the transmission or reception of a cycle-start packet. This
indicates that the isochronous cycle is over.

CyPnd

Cycle pending

When CyPnd is set, the cycle-timer offset is set to 0 (rolled over or
reset) and remains set until the isochronous cycle ends.

CyLst

Cycle lost

When CyLst is set, the cycle timer has rolled over twice without the
reception of a cycle-start packet. This occurs only when this node is not
the cycle master.

Table 3-4. Interrupt- and Mask-Register Field Descriptions (Continued)
BITS
25
26-30
31

3.2.5

ACRONYM
CArbFI

DESCRIPTION

FUNCTION NAME

When CArbFI is set, the arbitration to send the cycle-start packet failed.

Cycle arbitration
failed

Reserved

IArbFI

Isochronous
arbitration failed

When IArbFI is set, the arbitration to send an isoch ronous packetfailed.

Cycle-Timer Register

The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer.
The register is at address 14h and is read/write. This field is controlled by the cycle master, cycle source,
and cycle timer enable bits of the control register. Its initial value is OOOO_OOOOh.

Table 3-5. Cycle-Timer Register Field Descriptions

3.2.6

BITS

ACRONYM

DESCRIPTION

FUNCTION NAME

0-6

seconds_count

Seconds count

1-Hz cycle-timer counter

7-19

cycle~count

Cycle count

8,000-Hz cycle-timer counter

20-31

cycle_offset

Cycle offset

24.576-MHz cycle-timer counter

Isochronous Receive-Port Number Register

The isochronous receive-port number register controls which isochronous channels are received by this
node. This register is at address 18h. The register is read/write, and its initial value is OOOO_OOOOh.

Table 3-6. Isochronous Receive-Port Number Register Field Descriptions
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

0-7

I RPort1

Isochronous receive
port 1 channel number

IRPort1 contains the channel number of the isochronous packets the
receiver accepts. The receiver accepts when IRP1 En is set (bits 0
and 1 are reserved).

8-15

I RPort2

Isochronous receive
port 2 channel number

I RPort2 contains the channel number of the isochronous packets the
receiver accepts. The receiver accepts when IRP2En is set (bits 8
and 9 are reserved).

16-31

Reserved

4-45

3.2.7

Diagnostic Control and Status Register

The diagnostic control and status register allows for the monitoring and control of the diagnostic features
of the TSB12C01 A. The register is at address 20h. The regRW and enable snoop bits are read/write. When
regRW is cleared, all other bits are read only. When regRW is set, all bits are readlwrite. Its initial value is
OOOO_OOOOh. For a RAM test read/write, enable RAM test mode and set Adccir to clear the RAM internal
address counter. Do the host bus read/write to location 80h; this accesses RAM starting at location OOh.
With each read/write the RAM internal address counter increments by one.
Table 3-7. Diagnostic Control and Status-Register Field Descriptions
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

ENSp

Enable Snoop

When ENSp is set, the receiver accepts all packets on the bus
regardless of address or format. The receiver uses the snoop data
format defined in Section 4.4, Quadlet Receive.

BsyFI

Busy flag

When BsyFI is set, the receiver sends an ack_busyB the next time the
receiver must busy a packet. When cleared, the receiver sends an
ack_busyA the next time the receiver must busy a packet.

ArbGp

Arbitration reset
gap

When ArbGp is set, the serial bus has been idle for an arbitration reset
gap.

FrGp

Fair gap

When FrGp is set, the serial bus has been idle for a fair-gap time
(Sub-Action Gap).

regRlW

When regRlW is set, most registers are fully read/write.

Adr_clr

Address clear

When Adccir is set, the intemal RAM address counter and the
Control_biCerr flag are cleared.

ControLbit1

Control bit for RAM
test write

During RAM test mode, ControLbit1 is written into the control bit of
RAM (bit 33) for RAM write transaction.

ControLbiCerr

Control bit error
flag

When ControLbiCerr is set, the control bit of the RAM does not
match Control_bit1 during RAM test mode.

RAMTest

RAM test mode

When RAMTest and regRW are set, RAM test mode is enabled.

9-31

Reserved

4-46

3.2.8

Phy-Chip Access Register

The phy-chip access register allows access to the registers in the attached phy chip. The most significant
16 bits send read and write requests to the phy-chip registers. The least significant 16 bits are for the phy
chip to respond to a read request sent by the TSB12C01A. The phy-chip access register also allows the
phy interface to send important information back to the TSB12C01A. When the phy interface sends new
information to the TSB12C01 A, the phy register-information-receive (PhyRRx) interrupt is set. The register
is at address 24h and is read/write. Its initial value is OOOO_OOOOh.
Table 3-8. Phy-Chip Access Register
BITS

ACRONYM

DESCRIPTION

FUNCTION NAME

RdPhy

Read phy-chip
register

When RdPhy is set, the TSB12C01 A sends a read register request with
address equal to phyRgAd to the Phy interface. This bit is cleared when
the request is sent.

WrPhy

Write phy-chip
register

When WrPhy is set, the TSB12C01A sends a write register request
with address equal to phyRgAd to the Phy interface. This bit is cleared
when the request is sent.

2-3

Reserved

4-7

PhyRgAd

Phy-chip-register
address

PhyRgAd is the address of the phy-chip register that is to be accessed.

8-15

PhyRgData

Phy-chip-register
data

PhyRgData is the data to be written to the phy-chip register indicated
in PhyRgAd.

16-19 Reserved

Reserved

20-23

PhyRxAd

Phy-chip-registerreceived address

PhyRxAd is the address of the register from which PhyRxData came.

24-31

PhyRxData

Phy-chip-registerreceived data

PhyRxData contains the data from register addressed by PhyRxAd.

3.2.9

Phy-Interface State Register

The Phy-interface state register contains the state values of the internal state machines of the Phy interface
module and is used for debugging purposes. The register is at 28h and is read only. Its initial value is
OOOO_OOOOh.
Table 3-9. Phy-Interface State Register
BITS

ACRONYM

0-15

Reserved

DESCRIPTION

FUNCTION NAME
Reserved

Reserved

16-19 Req_State

State of the request
module

Req_State is the state value of the request module.

20-23 TLState

State of the transmit
interface module

TLState is the state value of the transmit interface module.

24-26

RDI_State

State of the receiver
data interface module

RDI_State is the state value of the receiver data interface module.

27-28

RSLState

State of the receiver
status interface
module

RSI_State is the state value of the receiver status interface module.

29-31

RA_State

State of the receive
acknowledge module

RA..State is the state value of the receive ack module.

4--47

3.2.10 Other State Register
The other state register contains state values of all other modules except phy interface module. It is used
for debugging purposes. The register is at address 2Ch and is read only. Its initial value is OOOO_OOOOh.
Table 3-10. Other State Register
BITS

FUNCTION NAME

ACRONYM

DESCRIPTION

0-3

Reserved

4-6

CM_State

Cycle monitor

CM_State is the state value of the cycle monitor module.

7-9

RAC_State

RAM access control

RAC_State is the state value of the RAM access control
module

10-11

ITF_Link_State

Link transmit FIFO logic

ITF_Link_State is the state value of the link transmit FIFO
logic module for the ITF

ITF_HosCState

Host transmit FIFO logic

ITF_HosCState is the state value of the host transmit FIFO
logic module for the ITF.

13-14

ATF_Link_State

Link transmit FIFO logic

ATF_Link_State is the state value of the link transmit FIFO
logic module for the ATF.

ATF_HosCState

Host transmit FIFO logic

ATF_HosCState is the state value of the host transmit FIFO
logic module for the ATF.

16-18

GRF_HosCState

Host receive FIFO logic

GRF_HosCState is the state value of the host receive FIFO
logic module for the GRF.

19-21

RB_State

Receive busy

RB_State is the state value of the receive busy module.

20-22

Rcv_State

Receive

Rcv_State is the state value of the receive module.

23-31

Tx State

Transmit

Tx State is the state value of the transmit module.

3.2.11

Asynchronous Transmit-FIFO (ATF) Status Register

The ATF status register allows access to the registers that control or monitor the ATF. The register is at
address 30h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is OOOO_OOOOh.
Table 3-11. ATF Status Register
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Full

ATFfull flag

When Full is set, the FIFO is full. Writes are ignored.

AIF

ATF almost-full flag

When AIF is set, the FIFO can accept one more write.

2-3
4
5-13
14
15
16-18
19

Reserved

4AV

ATF-4-available flag

When 4AV is set, the FIFO has space available for at least four
quadlets.

Reserved

AlE

ATF-almost-empty flag

When AlE is set, the FIFO has only one quadlet in it.

Empty

ATF-empty flag

When Empty is set, the FIFO is empty.

Reserved

Clr

ATF-clear control bit

When Clr is set by softwarelfirmware, the FIFO is cleared of all
entries.

20-22

Reserved

23-31

Size

ATF-size control bits

Size is equal to the ATF size number in quadlets.

4-48

3.2.12

ITF Status Register

The ITF status register allows access to the registers that control or monitor the ITF. The register is at
address 34h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is DDDD_DDDDh.

Table 3-12. ITF Status Register
BITS

ACRONYM

FUNCTION NAME

DESCRIPTION

Full

ITF full flag

When Full is set, the FIFO is full and all writes are ignored.

AIF

ITF almost-full flag

When AIF is set, the FIFO can accept only one more write.

2-3
4

Reserved

4AV

ITF-4-available flag

When 4AV is set, the FIFO has space for at least four more quadlets.

Reserved

AlE

ITF-almost-empty flag

When AlE is set, the FIFO has only one quadlet in it.

Empty

ITF-empty flag

When Empty is set, the FIFO is empty.

5-13

16-18
19
20-22
23-31

3.2.13

Reserved

Clr

ITF-clear control bit

When Clr is set by software/firmware, the FIFO is cleared of all
entries.

Reserved

Size

ITF-size control bits

The size is equal to the ITF size number in quadlets.

GRF Status Register

The GRF status register allows access to the registers that control or monitor the GRF. The register is at
address 3Ch. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is DDDD_DDDDh.

Table 3-13. GRF Status Register
BITS

ACRONYM

DESCRIPTION

FUNCTION NAME

Full

GRFfull flag

When Full is set, the FIFO is full.

AIF

GRF-almost-full flag

When AIF is set, the FIFO can accept only one more write.

2-11
12

Reserved

4Th

GRF four there

When 4Th is set, the FIFO has at least four quadlets in it.

Reserved

AlE

GRF-almost-empty
flag

When AlE is set, the FIFO has one quadlet in it.

Empty

GRF-empty flag

When Empty is set, the FIFO is empty and reads are ignored.

GRF control bit

This is the control bit for the GRF. When cd is set, the first quadlet
of a packet is being read from the GRF_Data address.

Reserved

Clr

GRF-clear control bit

When Clr is set by software/firmware, the FIFO is cleared of all
entries.

17-18
19
20-22

Reserved

23-31

Size

GRF-size control bits

The size is equal to the GRF size number in quadlets.

4-49

3.3

FIFO Access

Access to all the transmit FIFOs is fundamentally the same; only the address to where the write is made
changes.

3.3.1

General

The TSB12C01A controller FIFO-access address map shown in Figure 3-3 illustrates how the FIFOs are
mapped. The suffix _First denotes a write to the FIFO location where the first quadlet of a packet should
be written when the writer wants the packet to be held in the FIFO until a quadlet is written to an update
location.
The suffix _Continue denotes a write to the FI FO location where the second through n-1 quadlets of a packet
could be written.
The suffix _First&Update denotes a write to the FIFO location where the first quadlet of a packet should be
written when the writer wants the packet to be transmitted as soon as possible.
The suffix _Continue&Update denotes a write to the FIFO location where the second throughn quadlets
of a packet could be written when the writer wants the packet to be transmitted as soon as possible. The
last quadlet of a multiple quadlet packet should be written to the FIFO location with the notation
_Continue&Update.

1 2 3 4

is 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

SOh

ATF_First

84h

ATF_Continue

SSh

ATF_First & Update

SCh

ATF_Continue & Update

90h
94h

ITF_Continue

ITF_First

9Sh

ITF_First & Update

9Ch

ITF_Continue & Update

AOh

Reserved

A4h

Reserved

ASh

Reserved

ACh

Reserved

BOh

Reserved

B4h

Reserved

BSh

Reserved

BCh

Reserved

COh

GRF Data

C4h

Reserved

CSh

Reserved

CCh

Reserved

Figure 3-3. TSB12C01 A Controller-FIFO-Access Address Map

4-50

3.3.2

ATF Access

Access to the ATF is as follows:
1.
2.
3.
4.

Write to ATF location BOh: the data is not confirmed for transmission (first quadlet of the packet).
Write to ATF location B4h: the data is not confirmed for transmission (second n-1 quadlets of the
packet).
Write to ATF location BBh: the data is confirmed for transmission (first quadlet of the packet). The
read logic sees all data written to the FIFO since the last confirm (update).
Write to ATF 10cationBCh: the data is confirmed for transmission (second n quad lets of the
packet).
If the first quad let of a packet is not written to the ATF_First or ATF_First&Update, the transmitter
enters a state denoted by an ATStuck interrupt. An underflow of the ATF also causes an ATStuck
interrupt. When this state is entered, no asynchronous packets can be sent until the ATF is
cleared via the CLR ATF control bit. Isochronous packets can be sent while in this state.

ATF access example:
The first quadlet of n quadlets is written to ATF location BOh. Quadlets (2 to n-1) are written to ATF
location B4h. The last quadlet (nth) is written to ATF location BCh. If the ATFEmpty bit is true, it is
set to false and the TSB12C01 A requests the phy layer to arbitrate for the bus. To ensure that an
ATF underflow condition does not occur, loading of the ATF in this manner is suggested.

3.3.3

ITF Access

Access to the ITF is as follows:
. 1.
2.
3.
4.

Write to ITF location 90h: the data is not confirmed for transmission (first quadlet of the packet).
Write to ITF location 94h: the data is not confirmed for transmission (second n-1 quadlets of the
packet).
Write to ITF location 9Bh: the data is confirmed for transmission (first quadlet of the packet). The
read logic sees all data written to the FIFO since the last confirm (update).
Write to ITF location 9Ch: the data is confirmed for transmission (second n quadlet of the packet).
If the first quadlet of a packet is not written to the ITF_First or ITF_First&Update, the transmitter
enters a state denoted by an ITStuck interrupt. An underflow of the ITF also causes an ITStuck
interrupt. When this state is entered, no isochronous packets can be sent until the ITF is cleared
by the CLR ITF control bit. Asynchronous packets can be sent while in this state.

ITF a:ccess example:
The first quadlet of n quad lets is written to ITF location 90h. Quadlets (2 to n-1) are written to ITF
location 94h. The last quadlet (nth) is written to ITF location 9Ch. If the ITFEmpty is true, it is set to
false and the TSB12C01 A requests the phy layer to arbitrate for the bus. To ensure that an ITF
underflow condition does not occur, loading of the ITF in this manner is suggested.

3.3.4

General-Receive-FIFO (GRF)

Access to the GRF is done with a read from the GRF, which requires a read from address COho

4-51

3.3.5

RAM Test Mode

The purpose of RAM test mode is to test the RAM with writes and reads. During RAM test mode, RAM, which
makes up the ATF, ITF, and GRF, is accessed directly from the host bus. Different data is written to and read
back from the RAM and compared with what was expected to be read back. ATF status, ITF status, and GRF
status are not changed during RAM test mode, but the stored data in RAM is changed by any write
transaction. To enable RAM test mode, set regRW bit and RAMTest bit of the diagnostics register. Before
beginning any read or write to the RAM, the Adr_clr bit of the diagnostics register should be set to clear the
internal RAM address counter. This action also clears the Adr_clr bit.
During RAM test mode, the host bus address should be BOh. The first host bus transaction (either read or
write) accesses location 0 of the RAM. The second host bus transaction accesses location 1 of the RAM.
The nth host bus transaction accesses location n-1 of the RAM. After each transaction, the internal RAM
address counter is incremented by one.
The RAM has 512 locations with each location containing 33 bits. The most significant bit is the control bit.
When it is set, that indicates the quadlet is the start of the packet. In order to set the control bit, Control-bit1
of the diagnostics register has to be set. In order to clear the control bit, Contro,-bit1 of the diagnostics
register has to be cleared. When a write occurs, the 32 bits of data from the host bus is written to the low
order 32 bits of the RAM and the value in Control-bit1 is written to the control bit. When a read occurs, the
low order 32 bits of RAM are sent to the host data bus and the control bit is compared to Contro'-bit1. If the
control bit and Contro,-bit1 do not match, Contro'-biCerr of the diagnostics register is set. This does not
stop operation and another read or write can immediately be transmitted. To clear Contro'-biCerr, set
Adr_clr of the diagnostics register, or transact another write.

4-52

4 TSB12C01 A Data Formats
The data formats for transmission and reception of data are shown in the following sections. The transmit
format describes the expected organization of data presented to the TSB 12C01 A at the host-bus interface.
The receive formats describe the data format that the TSB12C01A presents to the host-bus interface.

4.1

Asynchronous Transmit (Host Bus to TSB12C01 A)

Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface. The
general-receive FIFO (GRF) is shared by asynchronous data and isochronous data. There are two basic
formats for data to be transmitted and received. The first is for quadlet packets, and the second is for block
packets. For transmits, the FIFO address indicates the beginning, middle, and end of a packet. For receives,
the data length, which is found in the header of the packet, determines the number of bytes in a block packet.

4.1.1

Quadlet Transmit

The quadlet-transmit format is shown in Figure 4-1. The first quadlet contains packet control information.
The second and third quadlets contain the 64-bit, quadlet-aligned address. The fourth quadlet is data used
only for write requests and read responses. For read requests and write responses, the quadlet data field
is omitted.

priority
destinationlD
destinationOffsetLow
quadlet data (for write request and read response)

Figure 4-1. Quadlet-Transmit Format
Table 4-1. Quadlet-Transmit Format
DESCRIPTION

FIELD NAME
spd

This field indicates the speed at which this packet is to be sent. 00 =100 Mb/s, 01
and 10 =400 Mb/s, and 11 is undefined for this implementation.

=200 Mb/s,

tLabel

This field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This is used to pair up a response packet with its corresponding request
packet.

The retry code for this packet is: 00 =new, 01

=retry_X, 10 =retryA, and 11 =retryB.

tCode

tCode is the transaction code for this packet. (see Table 6-10 of IEEE-1394 standard)

priority

The priority level for this packet. For cable implementation, the value of the bits must be zero.
For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.

destination I0

This is the concatenation of the 1O-bit bus number and the 6-bit node number that forms the
destination node address of this packet.

destination OffsetHigh,
destination OffsetLow

The concatenation of these two fields addresses a quadlet in the destination nodes address
space. This address must be quadlet aligned (modulo 4).

quadlet data

For write requests and read responses, this field holds the data to be transferred; For write
responses and read requests, this field is not used and should not be written into the FIFO.

4.1.2

Block Transmit

The block-transmit format is shown in Figure 4-2. The first quadlet contains packet-control information. The
second and third quadlets contain the 64-bit address. The first 16 bits of the fourth quadlet contains the
4-53

dataLength field. This is the number of bytes of data in the packet. The remaining 16 bits represent the
extended_tCode field. (See Table 6-11 of the IEEE-1394 standard for more information on
extended_tCodes.) The block data, if any, follows the extended_tCode. Block write responses are identical
to the quadlet write response and use the format described insection 4.1.3, Quadlet Receive.

destinationlD

destinationOffsetHigh
destinationOffsetLow

data Length

extended_tCode
block data

Figure 4-2. Block-Transmit Format
Table 4-2. Block-Transmit Format Functions
FIELD NAME

DESCRIPTION

=200 Mb/s,

spd

This field indicates the speed at which this packet is to be sent. 00 100 Mb/s, 01
and 10 400 Mb/s, and 11 is undefined for this implementation.

tLabel

This field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This is used to pair up a response packet with its corresponding request
packet.

=new, 01 =retry_X, 10 =retryA, and 11 =retryB.

The retry code for this packet is 00

tCode

tCode is the transaction code for this packet (see Table 6-10 of IEEE-1394 standard).

priority

The priority level forthis packet. For cable implementation, the value of the bits must be zero.
For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.

destinationlD

This is the concatenation of the 1O-bit bus number and the 6-bit node number that forms the
node address to which this packet is being sent.

destination OffsetHigh,
destination OffsetLow

The concatenation of these two fields addresses a quadlet in the destination node's address
space. This address must be quadlet aligned (modulo 4). The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets and
the remaining bits are reserved.

dataLength

The number of bytes of data to be transmitted in the packet.

extended_tCode

The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the
IEEE-1394 standard.

block data

The data to be sent. If data Length is 0, no data should be written into the FI FO for this field.
Regardless of the destination or source alignment of the data, the first byte of the block must
appear in byte 0 of the first quad let.

4.1.3

Quadlet Receive

The quad let-receive format is shown in Figure 4-3. The first 16 bits of the first quadlet contain the destination
node and bus id, and the remaining 16 bits contain packet-control information. The first 16 bits ofthe second
quadlet contain the node and bus 10 ofthe source, and the remaining 16 bits ofthe €lecond and third quadlets
contain the 48-bit, quad let-aligned destination offset address. The fourth quad let contains data that was
used by write requests and read responses. For read requests and write responses, the quadlet data field
is omitted. The last quadlet contains packet-reception status, added by the TSB12C01A.
4-54

destinationlD
sourcelD

tLabel

tCode

priority

destinationOffsetHigh
destinationOffsetLow

quadlet data (for write request and read response)
ackSent

Figure 4-3. Quadlet-Receive Format
Table 4-3. Quadlet-Receive Format Functions
FIELD NAME

DESCRIPTION

destinatiolllO

This is the concatenation of the 1O-bit bus number and the 6-bit node number that forms the
node address to which this packet is being sent.

tLabel

This field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This is used to pair up a response packet with its corresponding request
packet.

The retry code for this packet is 00 = new, 01 = retry_X, 10= retryA, and 11 = retryB.

tCode

tCode is the transaction code for this packet. (See Table 6-10 of the I EEE-1394 standard).

priority

The priority level for this packet. For cable implementation, the value of the bits must be zero.
For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.

sourcelO

This is the node 10 of the sender of this packet.

destination OffsetHigh,
destination OffsetLow

The concatenation of these two fields addresses a quadlet in the destination nodes address
space. This address must be quadlet aligned (modulo 4). (The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets, and
the remaining bits are reserved.)

quadlet data

For write requests and read responses, this field holds the transferred data. For write
responses and read requests, this field is not present.

spd

This field indicates the speed at which this packet was sent. 00 = 100 Mb/s, 01 = 200 Mb/s,
10 = 400 Mb/s, and 11 is undefined for this implementation.

ackSent

This field holds the acknowledge sent by the receiver fOr this packet. (See Table 6-13 in the
draft standard.)

4.1.4

Block Receive

The block-receive format is shown in Figure 4-4. The first 16 bits of the first quadlet contain the node and
bus ID of the destination node, and the last 16 bits contain packet-control information. The first 16 bits of
the second quadlet contain the node and bus ID of the source node, and the last 16 bits of the second
quadlet and all of the third quadlet contain the 48-bit, quadlet-aligned destination offset address. All
remaining quadlets, except for the last one, contain data that is used only for write requests and read
responses. For block read requests and block write responses, the data field is omitted. The last quadlet
contains packet-reception status.
4-55

tLabel

destinationlD

tCode

priority

destinationOffsetHigh

sourcelD

destinationOffsetLow
extended_tCode

dataLength

block data (if any)

ackSent

Figure 4-4. Block-Receive Format
Table 4-4. Block-Receive Format Functions
FIELD NAME

DESCRIPTION

destinationlD

This is the concatenation of the 1O-bit bus number and the 6-bit node number that forms the
node address to which this packet is being sent.

tLabel

This field is the transaction label, which is a unique tag for each outstanding transaction
between two nodes. This is used to pair up a response packet with its corresponding request
packet.

The retry code for this packet is 00 = new, 01 = retry_X, 10= retryA, and 11 = retryB.

tCode

tCode is the transaction code for this packet. (See Table 6-10 of the IEEE-1394 standard).

priority

The priority level for this packet. For cable implementation, the value of the bits must be zero.
For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE-1394 standard.

sourcelD

This is the node ID of the sender of this packet.

destination OffsetHigh,
destination OffsetLow

The concatenation of these two fields addresses a quadlet in the destination nodes address
space. This address must be quadlet aligned (modulo 4). The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets and
the remaining bits are reserved.

dataLength

For write request, read responses, and locks, this field indicates the number of bytes being
transferred. For read requests, this field indicates the number of bytes of data to be read. A
write-response packet does not use this field. Note that the number of bytes does not include
the head, only the bytes of block data.

extended_tCode

The block extended_tCode to be performed on the data in this packet. See Table 6-11 of the
IEEE-1394 standard.

block data

This field contains any data being transferred for this packet. Regardless of the destination
address or memory alignment, the first byte of the data appears in byte 0 of the first quadlet
of this field. The last quadlet of this field is padded with zeros out to four bytes, if necessary.

spd

This field indicates the speed at which this packet was sent. 00 = 100 Mb/s, 01 = 200 Mb/s,
10 = 400 Mb/s, and 11 is undefined for this implementation.

ackSent

This field holds the acknowledge sent by the receiver for this packet.

4-56

4.2

Isochronous Transmit (Host Bus to TSB12C01A)

The format of the isochronous-transmit packet is shown in Figure 4-5. The data for each channel must be
presented to the isochronous-transmit FIFO interface in this format in the order that packets are to be sent.
The transmitter sends any packets available at the isochronous-transmit interface immediately following
reception or transmission of the cycle-start message.

TAG

dataLength

chanNum

isochronous data

Figure 4-5. Isochronous-Transmit Format
Table 4-5. Isochronous-Transmit Functions
FIELD NAME

DESCRIPTION

dataLength

This field indicates the number of bytes in this packet

TAG

This field indicates the format of data carried by isochronous packet (00 = formatted, 01 -11
are reserved).

chanNum

This field carries the channel number with which this data is associated

spd

This field contains the speed at which to send this packet

This field carries the transaction layer-specific synchronization bits

isochronous data

This field contains the data to be sent with this packet. The first byte of data must appear in byte

oof the first qOadlet of this field. If the last quadlet does not contain four bytes of data, the unused
bytes should be padded with zeros.

4.3

Isochronous Receive (TSB12C01A to Host Bus)

The format of the iscohronous-receive data is shown in Figure 4-6. The data length, which is found in the
header of the packet, determines the number of bytes in an isochronous packet.

1 2 314 5 6 718 9 10 11112 13 14 15 1617 18 19 2021 2223 24252627 282930 31

dataLength
h

TAG

chanNum

tCode

sy
h

Isochronous data
errCode

Figure 4-6. Isochronous-Receive Format

4-57

Table 4-6. Isochronous-Receive Functions
FIELD NAME

DESCRIPTION

dataLength

This field indicates the number of bytes in this packet

TAG

This field indicates the format of data carried by isochronous packet (00 = formatted, 01 - 11 are
reserved).

chanNum

This field contains the channel number with which this data is associated

tCode

This field carries the transaction code for this packet. (tCode = Ah)

This field carries the transaction layer-specific synchronization bits

isochronous data

This field has the data to be sent with this packet. The first byte of data must appear in byte 0 of
the first quadlet of this field. The last quadlet should be padded with zeros.

spd

This field indicates the speed at which this packet was sent

errCode

This field indicates whether this packet was received correctly. The possibilities are Complete,
DataErr, or CRCErr and have the same encoding as the corresponding acknowledge codes.

4.4

Snoop

The format of the snoop data is shown in Figure 4-7. The receiver module can be directed to receive any
and all packets that pass by on the serial bus. In this mode, the receiver presents the data received to the
receive-FIFO interface.

123

snoopecCdata

ackSnpd

Figure 4-7. Snoop Format
Table 4-7. Snoop Functions
FIELD NAME

DESCRIPTION

snooped_data

This field contains the entire packet received or as much as could be received.

spd

This field carries the speed at Which this packet was sent

snpStat

This field indicates whether the entire packet snooped was received correctly. A value equal to the
complete acknowledge code indicates complete reception. A busyA or busyB acknowledge code
indicates incomplete r~ception.

ackSnpd

This field indicates the acknowledge seen on the bus after the packet is received.

4-58

4.5

CycleMark

The format of the Cycle Mark data is shown in Figure 4-8. The receiver module inserts a single quad let to
mark the end of an isochronous cycle. The quadlet is inserted into the receive-FIFO.

Figure 4-8. CycleMark Format
Table 4-8. CycleMark Functions

4.6

FIELD NAME

DESCRIPTION

CyDne

This field indicates the end of an isochronous cycle.

Phy Configuration

The format of the phy configuration packet is shown in Figure 4-9. The phy configuration packet transmit
contains two quadlets, which are loaded into the ATF. The first quadlet is written to address 80h. The second
quadlet is written to address 8Ch. The OOEOh in the first quadlet tells the TSB12C01A that this is the phy
configuration packet. The Eh is then replaced with Oh before the packet is transmitted to the phy interface .
..

0
0

1 2 31 4 5 6 7 8 9 1011112131415 16 1718 1912021 2223124 25 26 27128 29 30 31

rooUD

RITI

gap_ent

000000001

logical inverse of first 16 bits of first quadlet 1

1 1

1 1 1 1 1 1

0 000

1 1 1 1 1

Figure 4-9. Phy Configuration Format
Table 4-9. Phy Configuration Functions
FIELD NAME

DESCRIPTION

This field is the phy configuration packet identifier.

rooUD

This field is the physicaUD of the node to have its force_root bit set (only meaningful when
R is set).

When R is set, the force-root bit of the node identified in rooUD is set and the force_root bit
of all other nodes are cleared. When R is cleared, rooUD is ignored.

When T is set, the PHY_CONFIGURATION .gap_countfield of all the nodes is setto the value
in the gap_cnt field.

gap_cnt

This field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This
value goes into effect immediately upon receipt and remains valid after the next bus reset.
After the second reset, gap_cnt is set to 63h unless a new Phy configuration packet is
received.

t A phy configuration packet with R = 0, and T

= 0 is reserved and is ignored when received.

4-59

4.7

Receive Self-ID

The format of the receive self-IO packet is shown in Figure 4-10. When RxSld (bit 1 of the control register)
is set, the receive self-IO packet is stored in GRF.

Figure 4-10. Receive Self-IO Format
Table 4-10. Receive Self-IO Functions

4-60

FIELD NAME

DESCRIPTION

ACK

When this field is set, the data in the self-ID packet is correct. When
ACK is cleared, the data in the self-ID packet is incorrect.

5 Electrical Characteristics
5.1

Absolute Maximum Ratings Over Free-Air Temperature Range (Unless
Otherwise Noted)t
Supply voltage range, Vee (see Note 1) ............................ -0.5 V to 6 V
Input voltage range, at any input, VI ........................ -0.5 V to Vee + 0.5 V
Output voltage range, Vo ................................. -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI > Vee> (see Note 2) .................. ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee> (see Note 3) .............. ±20 mA
Operating free-air temperature range, TA ............................ ODC to 70 DC
Storage temperature range, Tstg ................................. -65 DC to 150DC
Case temperature for 10 seconds, T e ..................................... 260 DC

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This applies to all inputs.
3. This applies to all outputs.

5.2

Recommended Operating Conditions

Supply voltage, VCC

UNIT

MIN

NOM

MAX

4.75

5.25

Input voltage, VI

VCC

High-level input VOltage, VIH

VCC

Low-level input voltage, VIL

0.8

Clock frequency

I BCLK
I SCLK

49.152

MHz

Operating free-air temperature, TA

°c

Virtual junction temperature range, TJ

115

°C

4-61

5.3

Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature (Unless Otherwise Noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH =-4 mA

VOL

Low-level output voltage

IOL=4 mA

MIN

TYPt

MAX

UNIT

VCC-0.8
0.5

Phy interface

0.7VCC
V

VIT+

Positive-going input threshold voltage

All other inputs
(see Note 4)

VIT-

Negative-going input threshold voltage

All other inputs
(see Note 4)

IlL

Low-level input current

VI = GND

-1

IlA

IIH

High-level input current

VI =VCC

IlA

IOZ

High-irnpedance-state output current

VI = VCC or GND
(see Note 5)

±10

IlA

ICC

Supply current

No load on outputs,
SCLK = 49.152 MHz
BCLK = 25 MHz

Phy interface

Input capacitance

Input
terminals
Bidirectional
terminals

2
0.2 VCC

0.8

150

rnA

5
VCC=5 V,
TA = 25°C

Output capacitance

pF
13
pF

All typical values are at VCC = 5 V and TA = 25°C.
NOTES: 4. This applies for all inputs except SCLK, BCLK, and RESET.
5. All outputs are in the high-impedance state.

5.4

Host-Interface Timing Requirements Over Operating Free-Air
Temperature Range
PARAMETER

MIN

MAX

UNIT

lei

Cycle time, BCLK (see Figure 6-1)

tw1(H)

Pulse duration, BCLK high (see Figure 6-1)

tw1(L)

Pulse duration, BCLK low (see Figure 6-1)

tsu1

Setup time, DATA[0:31] before BCLKt (see Figure 6-2)

th1

Hold time, DATA[0:31] after BCLKt (see Figure 6-2)

tsu2

Setup time, ADDR[0:7] before BCLKt (see Figures 6-2 and 6-3)

th2

Hold time, ADDR[0:7] after BCLKt (see Figures 6-2 and 6-3)

tsu3

Setup time, CS before BCLKt (see Figures 6-2 and 6-3)

th3

Hold time, CS after BCLKt (see Figures 6-2 and 6-3)

tsu4

Setup time, WR before BCLKt (see Figures 6-2 and 6-3)

th4

Hold time, WR after BCLKt (see Figures 6-2 and 6-3)

4-62

5.5

Host-Interface Switching Characteristics Over Operating Free-Air
Temperature Range, CL = 45 pF (unless otherwise noted)
PARAMETER

MIN

MAX

td1

Delay time, BCLKt to CA (see Figure 6-2)

td2

Delay time, BCLKt to CA (see Figure 6-2)

ns
ns
ns

td3

Delay time, BCLKt to DATA[0:31] valid (see Figure 6-3)

td4

Delay time, BCLKt to DATA[0:31] invalid (see Figure 6-3)

5.6

UNIT

Phy-Interface Timing Requirements Over Operating Free-Air
Temperature Range
PARAMETER

MIN

MAX

UNIT

20.24

20.45

tc2

Cycle time, SCLK (see Figure 6-4)

tw2(H)

Pulse duration, SCLK high (see Figure 6-4)

tw2(L)

Pulse duration, SCLK low (see Figure 6-4)

tsu5

Setup time, DATA[0:7] before SCLKt (see Figure 6-6)

th5

Hold time, DATA[0:7] after SCLKt (see Figure 6-6)

tsu6

Setup time, CTL[O:1] before SCLKt (see Figure 6-6)

th6

Hold time, CTL[O:1] after SCLKt (see Figure 6-6)

5.7

Phy-Interface Switching Characteristics Over Operating Free-Air
Temperature Range, CL =45 pF (unless otherwise noted)
PARAMETER

MIN

MAX

UNIT

td5

Delay time, SCLKt to 0[0:7] valid (see Figure 6-5)

td6

Delay time, SCLKt to 0[0:7] (see Figure 6-5)

td7

Delay time, SCLKt to 0[0:7] invalid (see Figure 6-5)

td8

Delay time, SCLKt to CTL[O:1] valid (see Figure 6-5)

td9

Delay time, SCLKt to CTL[O:1] (see Figure 6-5)

td10

Delay time, SCLKt to CTL[O:1] invalid (see Figure 6-5)

td11

Delay time, SCLKt to LREQ (see Figure 6-7)

5.8

Miscellaneous Timing Requirements Over Operating Free-Air
Temperature Range (see Figure 6-9)
PARAMETER

MIN

MAX

124.99

125.01

UNIT

tc3

Cycle time, CYCLEIN

tw3(H)

Pulse duration, CYCLEIN high

/-ts

tw3(L)

Pulse duration, CYCLEIN low

/-ts

5.9

/-ts

Miscellaneous Signal Switching Characteristics Over Operating Free-Air
Temperature Range
PARAMETER

MIN

MAX

UNIT

td12

Delay time, SCLKt to INT low (see Figure 6-8)

td13

Delay time, SCLKt to INT high (see Figure 6-8)

td14

Delay time, SCLKt to CYCLEOUT high (see Figure 6-10)

td15

Delay time, SCLKt to CYCLEOUT low (see Figure 6-10)

4-63

4-64

6 Parameter Measurement Information
BCLK
tw1 (H)

~IOII

t w1(L)

~tc1---+i

Figure 6-1. BCLK Waveform

BCLK

I~
1

DATA[0:31]

·1

ADDR[0:7]

50%

tsu2

·1

\k.,

th3

.1 th1
1

)

1 th2

1
1

1 50%1

tsu4

td1
CA
(see Note A)

~hX
tsu3

1
tsu1

1
1
~

1
1

50%

\k.,

I th4

.1
1

td2

50%1

NOTE A: When back-to-back write cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge
of CS before CA is asserted (low). DATA[O:31], ADDR[O:7], and WR need to remain valid until CA is asserted
(low).

Figure 6-2. Host-Interface Write-Cycle Waveforms

4-65

BCLK

{(
DATA[0:31] -------i------.....I.,~---.,....-~
)}
1
1

tsu2

.1 th3
tsu3 --::4'--~I----I~
~
1

cs ---50-o/c~O~~____~__
J
50%1

~~
((

tsu4
((

CA
(see Note A)

--------------------------~)(~j----------

NOTE A: When back-to-back read cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge
of CS and before CA is asserted (low). ADDR[O:7] and WR need to remain valid until CA is asserted (low).

Figure 6-3. Host-Interface Read-Cycle Waveforms

SCLK

tw2(H) --loot--~:"_---"'IIIi
..I_
-

t w2(L)

j4--tc2~

Figure 6-4. SCLK Waveform

Figure 6-5. TSB12C01A-to-Phy-Layer Transfer Waveforms
4-66

SCLK
tsu5

14
1

tsu6

14
1

th6

CTL[0:1]

th5

(

0[0:7]

Figure 6-6. Phy-Layer-to-TSB12C01A Transfer Waveforms

SCLK

50%
td11

LREQ

.1
1
1

)(

Figure 6-7. TSB12C01A-Link-Request-to-Phy-Layer Waveforms

SCLK

L
i

td12 ---iOII141---.t~
1

INT

------~I

50%\\..._ _ _ _ _ _ _ _~

td13

50%7

))r------J.

Figure 6-8. Interrupt Waveform

4-67

CYCLEIN

tw3(H) ----hIII1---~_ _ _.~...-

t w3(L)

j4--tC3~

Figure 6-9. CYCLEIN Waveform

SCLK
1

CYCLEIN

-.J

1 i+:

td14 --+1

(j~
~------------~I--------td15 --.I
1..--.

t l~(~)----------~I
50%~~_ __

CYCLEOUT _ _ _ _ _ _ _ _ _ _ _ _
50..J%

Figure 6-10. CYCLEIN and CYCLEOUT Waveforms

4-68

7 TSB12C01A to 1394 Phy Interface Specification
7.1

Introduction

This chapter provides an overview of a TSB 12C01 A to the phy interface. The information that follows helps
guide you through the process of connecting the TSB12C01A to a 1394 physical-layer device. The part
numbers referenced, the TSB11 C01 and the TSB12C01 A, represent the Texas Instruments implementation
of the phy (TSB11 C01) and link (TSB12C01 A) layers of the IEEE-1394 standard.
The specific details of how the TSB11C01 device operates is not discussed in this document. Only those
parts that relate to the TSB12C01A phy-link interface are mentioned.

7.2

Assumptions

The TSB12C01A is capable of supporting 100 Mb/s, 200 Mb/s and 400 Mb/s phy-Iayer devices. For that
reason, this document describes an interface to a 400-Mb/s (actually 393.216-Mb/s) device. To support
lower-speed phy layers, adjust the width of the data bus by two terminals per 100 Mb/s. For example, for
100-, 200- and 400-Mb/s devices, the data bus is 2, 4, and 8 bits wide respectively. The width of the CTL
bus and the clock rate between the devices, however, does not change regardless of the transmission speed
that is used.
Finally, the 1394 phy layer has control of all bidirectional terminals that run between the phy layer and
TSB12C01A. The TSB12C01A can drive these terminals only after it has been given permission by the phy
layer. A dedicated request terminal (LREQ) is used by the TSB12C01A for any activity that you wish to
initiate.

7.3

Block Diagram

The functional block diagram of the TSB12C01A to phy layer is shown in Figure 7-1.

1394
Link
Layer

...,

0[0:7]
CTL[0:1]
LREQ

TSB12C01A

...

1394
Phy-Layer
Device

SCLK

NOTE A: See Table 2-2 for signal definition.

Figure 7-1. Functional Block Diagram of the TSB12C01A to Phy Layer

7.4

Operational Overview

The four operations that can occur in the phy-link interface are request, status, transmit, and receive. With
the exception of the request operation, all actions are initiated by the phy layer.
The CTL[O: 1] bus is encoded as shown in the following sections.
4-69

7.4.1

Phy Interface Has Control of the Bus
Table 7-1. Phy Interface Control of Bus Functions

CTL[O:1]

DESCRIPTION OF ACTIVITY

NAME

No activity is occurring (this is the default mode).

Idle

Status

Status information is being $ent from the phy layer to the TSB12C01A.

Receive

An incoming packet is being sent from the phy layer to the TSB12C01A.

Transmit

The TSB 12C01 A has been given control of the bus to send an outgoing packet.

The TSB12C01 A has control of the bus after receiving permission from the phy layer.

Table 7-2. TSB12C01A Control of Bus Functions
CTL[O:1]

DESCRIPTION OF ACTIVITY

NAME

Idle

The TSB12C01A releases the bus (transmission has been completed).

Hold

The TSB12C01A is holding the bus while data is being prepared for transmission, or the
TSB 12C01 A wants to send another packet without arbitration.

Transmit

An outgoing packet is being sent from the TSB 12C01 A to phy layer.

Reserved

None

7.5

Request

A serial stream of information is sent across the LREQ terminal whenever the TSB 12C01 A needs to request
the bus or access a register that is located in the phy layer. The size of the stream varies depending on
whether the transfer is a bus request, a read command, or a write command. Regardless of the type of
transfer, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end
of the stream.

Table 7-3. Request Functions
#of BITS

7.5.1

NAME

Bus Request

Read Register Request

Write Register Request

LREQ Transfer

The definition of the bits in the three different types of transfers are shown in Table 7-4.

7.5.1.1

TSB12C01ABus Request
Table 7-4. Bus-Request Functions (Length of Stream: 7 Bits)

BIT(S)

NAME

DESCRIPTION

Start Bit

Start bit indicates the beginning of the transfer (always set).

1-3

Request Type

Request type indicates the type of bus request (see Table 7-7 for the encoding of this
field).

4-5

Request Speed

Request speed indicates the speed at which the phy interface sends the packet for this
particular request (see Table 7-8 for the encoding of this field).

Stop Bit

Stop bit indicates the end of the transfer (always cleared).

4-70

7.5.1.2

TSB12C01 A Read-Register Request
Table 7-5. Read-Register Request Functions (Length of Stream: 9 Bits)

BIT(S)

DESCRIPTION

NAME
Start Bit

Start bit indicates the beginning of the transfer (always set).

1-3

Request Type

Request type indicates the type of request function (see Table 7-7 for the encoding of
this field).

4-7

Address

The address of the phy register to be read.

Stop Bit

Stop bit indicates the end of the transfer (always cleared).

7.5.1.3

TSB 12C01 A Write-Register Request
Table 7-6. Write-Register Request (Length of Stream: 17 Bits)

BIT(S)

DESCRIPTION

NAME

0
1-3

Start Bit

Start bit indicates the beginning of the transfer (always set).

Request Type

Request type indicates that this is a write-register request (see Table 7-7 for the
encoding of this field).

4-7

Address

The address of the phy register to be written to.

8-15
16

Data

The data that is to be written to the specified register address.

Stop Bit

Stop bit indicates the end of the transfer (always cleared).

7.5.1 .4

Request-Type Field for TSB 12C01 A Request
Table 7-7_ TSB12C01A Request Functions

LREQ[1:3]

DESCRIPTION

NAME

000

TakeBus

Immediate request. Upon detection of an idle, take control of the bus immediately (no
arbitration) for asynchronous packet ACK response.

001

IsoReq

Isochronous request. IsoReq arbitrates for control of the bus after isochronous gap.

010
011

PriReq

Priority request. PriReq arbitrates for control of the bus after a fair gap, ignore fair protocol.

FairReq

Fair request. FairReq arbitrates for control of the bus after a fair gap; use fair protocol.

100

RdReg

Read request. RdReg returns the specified register contents through a status transfer.

WrReg

Write request. WrReg writes to the specified register.

Reserved

101
110,111

7.5.1.5

Request-Speed Field for TSB12C01A Request
Table 7-8. TSB12C01A Request-Speed Functions
LREQ[4:S]

7.5.2

DATA RATE

00
01
10

100 Mb/s
200 Mb/s

Reserved

400 Mb/s

Bus Request

For fair or priority access, the TSB12C01A requests control of the bus at least one clock after the
TSB12C01A phy interface becomes idle CTL[0:1] = 00, which indicates the physical layer is in an idle state.
If the TSB12C01 A senses that CTL[0:1] = 10, then it knows that its request has been lost. This is true any
time during or after the TSB12C01 A sends the bus request transfer. Additionally, the phy interface ignores
any fair or priority requests when it asserts the receive state while the TSB12C01A is requesting the bus.
The link then reissues the request one clock after the next interface idle.

4-71

The cycle master uses a normal priority request to send a cycle-start message. After receiving a cycle start,
the TSB12C01A can issue an isochronous bus request. When arbitration is won, the TSB12C01 A proceeds
with the isochronous transfer of data. The isochronous request is cleared in the phy interface once the
TSB12C01 A sends another type of request or when the isochronous transfer has been completed.
The TakeBus request is issued when the TSB12C01A needs to send an acknowledgment after reception
of a packet addressed to it. This request must be issued during packet reception. This is done to minimize
the delay times that a phy interface would have to wait between the end of a packet reception and the
transmittal of an acknowledgment. As soon as the packet ends, the phy interface immediately grants access
of the bus to the TSB12C01 A. The TSB12C01 A sends an acknowledgment to the sender unless the header
CRC of the packet turns out to be bad. In this case, the TSB12C01 A releases the bus immediately; it is not
allowed to send another type of packet on this grant. To ensure this, the TSB 12C01 A is forced to wait 160
ns after the end of the packet is received. The phy interface then gains control of the bus and the
acknowledge with the CRC error sent. The bus is then released and allowed to proceed with another
request.
Although highly improbable, it is conceivable that two separate nodes believe that an incoming packet is
intended for them. The nodes then issue a TakeBus request before checking the CRC of the packet. Since
both phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs
somewhere between the competing nodes. This collision would be interpreted by the other nodes on the
network as being a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken
node drops its request and the false line state is removed. The only side effect is the loss of the intended
acknowledgment packet (this is handled by the higher layer protocol).

7.5.3

ReadIWrite Requests

When the TSB12C01 A requests to read the specified register contents, the phy interface sends the contents
of the register to the TSB12C01A through a status transfer. When an incoming packet is received while the
phy interface is transferring status information to the TSB12C01A, the phy interface continues to attempt
to transfer the contents of the register until it is successful.
For write requests, the phy interface loads the data field into the appropriately addressed register as soon
as the transfer has been completed. The TSB 12C01 A is allowed to request read or write operations at any
time.
See section 7.6, Status, for a more detailed description of the status transfer.

7.6

Status

A status transfer is initiated by the phy interface when it has some status information to transfer to the
TSB 12C01 A. The transfer is initiated by asserting the following: CTL[O: 1] = 01 and 0[0:7] = the appropriate
states; see Table 7-9 for status-request functions.
The status transfer can be interrupted by an incoming packet from another node. When this occurs, the phy
interface attempts to resend the status information after the packet has been acted upon. The phy interface
continues to attempt to complete the transfer until the information has been successfully transmitted.

NOTE
There must be at least one idle cycle between consecutive status transfers.

7.6.1

Status Request

The definition of the bits in the status transfer is shown in Table 7-9.

4-72

Table 7-9. Status-Request Functions (Length of Stream: 16 Bits)
BIT(s)

NAME

DESCRIPTION

Arbitration Reset
Gap

The arbitration-reset gap bit indicates that the phy interface has detected that the bus
has been idle for an arbitration reset gap time (this time is defined in the IEEE-1394
standard). This bit is used by the TSB12C01 A in its busylretry state machine.

Fair Gap

The fair-gap bit indicates that the phy interface has detected that the bus has been
idle for a fair-gap time (this time is defined in the IEEE-1394 standard). This bit is
used by the TSB12C01A to detect the completion of an isochronous cycle.

Bus Reset

The bus reset bit indicates that the phy interface has entered the bus reset state.

phy Interrupt

The phy interrupt bit indicates that the phy interface is requesting an interrupt to the
host.

4-7

Address

The address bits hold the address of the phy register whose contents are transferred
to the TSB12C01A.

8-15

Data

The data bits hold the data that is to be sent to the TSB12C01A.

Normally, the phy interface sends just the first four bits of data to the TS812C01A. These bits are used by
the TS812C01A state machine. However, if the TS812C01A initiates a read request (through a request
transfer), then the phy interface sends the entire status packet to the TS812C01 A. Additionally, the phy
interface sends the contents of the register to the TS812C01 A when it has some important information to
pass on. Currently, the only condition where this occurs is after the self-identification process when the phy
interface needs to inform the TS812C01A of its new node address (physicallD register).
There may be times when the phy interface wants to start a second status transfer. The phy interface first
has to wait at least one clock cycle with the CTL lines idle before it can begin a second transfer.

7.6.2

Transmit

When the TS812C01A wants to transmit information, it first requests access to the bus through an LREQ
signal. Once the phy interface receives this request, it arbitrates to gain control of the bus. When the phy
interface wins ownership of the serial bus, it grants the bus to the TS812C01 A by asserting the transmit state
on the CTL terminals for at least one SCLK cycle. The TS812C01A takes control of the bus by asserting
either hold or transmit on the CTL lines. Hold is used by the TS812C01 A to keep control of the bus when
it needs some time to prepare the data for transmission. The phy interface keeps control of the bus for the
TS812C01A by asserting a data-on state on the bus. It is not necessary for the TS812C01A to use hold
when it is ready to transmit as soon as bus ownership is granted.
When the TS812C01A is prepared to send data, it asserts transmit on the CTL lines as well as sends the
first bits of the packet on the D[0:1] lines (assuming 100 Mb/s). The transmit state is held on the CTL
terminals until the last bits of data have been sent. The TS812C01A then asserts idle on th.e CTL lines for
one clock cycle after which it releases control of the interface.
However, there are times when the TS812C01A needs to send another packet without releasing the bus.
For example, the TS812C01 A may want to send consecutive isochronous packets or it may want to attach
a response to an acknowledgment. To do this, the TS812C01A asserts hold instead of idle when the first
packet of data has been completely transmitted. Hold, in this case, informs the phy interface that the
TS812C01 A needs to send another packet without releasing control of the bus. The phy interface then waits
a set amount of time before asserting transmit. The TS812C01A can then proceed with the transmittal of
the second packet. After all data has been transmitted and the TS812C01A has asserted idle on the CTL
terminals, the phy interface asserts its own idle state on the CTL lines. When sending multiple packets in
this fashion, it is required that all data be transmitted at the same speed. This is required because the
transmission speed is set during arbitration, and since the arbitration step is skipped, there is no way of
informing the network of a change in speed.
4-73

7.6.3

Receive

When data is received by the phy interface from the serial bus, it transfers the data to the TSB12C01 A for
further processing. The phy interface asserts receive on the CTL lines and logic 1 on each D terminal. The
phy interface indicates the start of the packet by placing the speed code on the data bus (see the following
note). The phy interface then proceeds with the transmittal of the packet to the TSB12C01A on the D lines
while still keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the phy interface asserts idle on the CTL terminals that completes the receive operation.

NOTE
The speed code sent is a phy-TSB12C01A protocol and not included in the packets
CRC calculation.
SPD = Speed code
DO => Dn = Packet data

Table 7-10. Speed Code for Receive
OATARATE

0[0:7]

OOxxxxxxt

100 Mb/s

0100xxxxt

200 Mb/s
400 Mb/s

01010000
111111111

Data-on indication

t Note

the x means transmitted as 0 and
ignored by phy layer.

7.7

TSB12C01A to Phy Bus Timing

......
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description
The TSB11 LV01 provides the analog transceiver functions needed to implement a single port node in a
cable-based P1394 network. The cable port incorporates two differential line transceivers. The transceivers
include circuitry to monitor the line conditions as needed for determining connection status,· initialization and
arbitration, and packet reception and transmission. The TSB11 LV01 is designed to interface with a link layer
controller such as the TSB12C01A.
The TSB11 LV01 requires an external 24.576-MHz crystal, which drives an internal phase-locked loop (PLL)
generating the required 98.304-MHz reference signal. The 98.304-MHz reference signal is internally divided
to provide the 49.152-MHz ±100-ppm system clock signals that control transmission of the outboundencoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link layer
controller for synchronization of the two chips and is used for resynchronization of the received data. The power
down function, enabled by taking the PWRDN terminal high, stops operation of the PLL.
Data bits to be transmitted are received from the link layer controller on two parallel paths and are latched
internally in the TSB11 LV01 in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and then transmitted at 98.304-Mbits/s as the outbound data-strobe information stream.
During transmit, the encoded data information is transmitted differentially on the TPBx cable pair, and the
encoded strobe information is transmitted differentially on the TPAx cable pair.

t P1394 Draft 8.Ov.l
=1=

dated June 16, 1995
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.

FireWire is a trademark of Apple Computer, Incorporated.
PRODUCT PREVIEW Infonnatlon concerns products In the fonnatlve or
design phase of development. Characteristic data and olher

specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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TSB11 LV01
1-PORT P1394 CABLE TRANSCEIVER/ARBITER
FOR 3-VOLT SUPPLY OPERATION
SLLS232- JANUARY 1996

During packet reception the TPAx and TPBx cable port transmitters are disabled and the cable port receivers
are enabled. The encoded data information is received on the TPAx cable pair, and the encoded strobe
information is received on the TPBx cable pair. The received data-strobe information is decoded to recover the
receive clock signal and the serial data bits. The serial data bits are split into two parallel streams,
resynchronized to the local system clock, and sent to the associated link layer controller.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. In addition, the TPB channel monitors the incoming cable common-mode voltage for the
presence of the remotely supplied twisted-pair bias voltage. The presence or absence of this bias voltage is an
indication of cable connection status. The cable connection status signal is internally debounced in the
TSB11 LV01. The debounced cable connection status signal initiates a bus reset. On a cable
disconnect-to-connect the debounce delay is 335 ms. On a connect-to-disconnect there is minimal debounce.
The TSB11 LV01 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, senses the presence of an active connection. The value of this bias
voltage has been chosen to allow interoperation between transceiver chips operating from either 5-V nominal
supplies or 3-V nominal supplies. This bias-voltage source should be stabilized by using an external filter
capacitor of at least 1.0 11F.
The transmitter circuitry is disabled under the following conditions: power down, cable not active, reset, or
transmitter disabled. The receiver circuitry is disabled under the following conditions: power-down, cable not
active, or receiver disabled. The twisted-pair bias-voltage circuitry is disabled during either a power down or
reset condition. The power-down condition occurs when the PWRDN terminal is high. The cable-not-active
condition occurs when the cable connection status indicates no cable is connected and is not debounced. The
reset condition occurs when the RESET terminal is low. The transmitter disabled and receiver disabled
conditions are determined from the internal logic.

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The line drivers in the TSB11 LV01 operate in the high-impedance current mode and are designed to work with
external 112-0 line-matching resistor networks. One network is provided at each end of each tWisted-pair cable.
Each network is composed of a pair of series-connected 56-0 resistors. The pair of resistors that are connected
to the twisted-pair TPAx terminals are also connected to the TPBIAS terminal. The pair of resistors that are
connected to the twisted-pair TPBx terminals are also coupled to ground through a parallel
resistance-capacitance (RC) network with recommended value of 5 kO and 250 pF. The values of the external
resistors are designed to meet the IEEE P1394 draft standard specifications when connected in parallel with
the internal receiver circuits.

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5-6

TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

• Link
- Complies With High-Speed IEEE
1394-1995 Serial Bus Standard
- Transmits and Receives Correctly
Formatted 1394 Packets
- Supports Isochronous Data Transfer
- Performs Function of Cycle Master
- Generates and Checks 32-Bit CRC
- Detects Lost-Cycle Start Messages
- Contains Asynchronous, Isochronous,
and General-Receive FIFOs
• Physical-Link Interface
- Interfaces Directly to the TSB21 LV03M or
TSB14C01M Phy Chip
- Supports Speeds of 100, 200, or 400 Mb/s

- Implements the Phy-Link Interface
Described in Annex I of the IEEE
1394-1995 Serial Bus Standard
• Host Bus Interface
- Provides Chip Control Via Directly
Addressable Register
- Is Interrupt Driven to Minimize Host
POlling
- Has a Generic 32-Blt Host Bus Interface
• General
- Requires a Single 5-V ±5% Power Supply
- Low-Power CMOS Technology
- Packaged in a 100-Pin Ceramic Quad Flat
Pack (WN) Military Package for
Operation From -55°C to 125°C

description
The TSB12C01AM is an IEEE 1394-1995 standard (from now on refered to as 1394) high-speed serial-bus
link-layer controller that allows for easy integration into an 1/0 subsystem. The TSB12C01AM transmits and
receives correctly formatted 1394 packets and generates and checks the 32-bit CRC. It is capable of being a
cycle master and supports reception of isochronous data on two channels. It interfaces directly to the
TSB21 LV03M or the TSB14C01 M physical layer chips. It also supports bus speeds of 100,200, and 400 Mbps.
The TSB12C01 AM has a generic 32-bit host bus interface, which makes connection to most 32-bit host buses
very simple. The TSB12C01AM has software-adjustable FIFOs for optimal FIFO size and performance
characterization and allows for variable-size asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO
(ITF), and general-receive FIFO (GRF).
This document is not intended to serve as a tutorial on IEEE 1394-1995; users should refer to the 1394 serial
bus for detailed information regarding the 1394 high-speed serial bus.

- 55°C to 125°C

TSB12C01AMWNB

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

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PACKAGE
CERAMIC QUAD FLAT PACK
(WN)

AVAILABLE OPTIONS

5-7

TSB12C01AM
IEEE 1394·1995 HIGH·SPEED SERIAL·BUS LlNK·LAYER CONTROLLER
SG LS088 - MARCH 1996

architecture
functional block diagram
The functional block architecture of the TSB12C01 AM is shown in Figure 1.

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Transmitter

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Configuration Registers

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Figure 1. TSB12C01 AM Functional Block Diagram

Physical Interface
The physical (phy) interface provides phy-Ievel services to the transmitter and receiver. This includes gaining
access to the serial bus, sending packets, receiving packets, and sending and receiving acknowledge packets.
The phy interface module also interfaces to the phy chip and conforms to the phy-link interface specification
described in Annex J of the I EEE-1394 standard (refer to section 7 of the TSB 12C01 A Data Manual for more
information) .
Transmitter
The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus packets
to be transmitted through the phy interface. When data is present at the ATF interface to the transmitter, the
TSB12C01 AM phy interface arbitrates for the serial bus and sends a packet. When data is present at the ITF
interface to the transmitter, the TSB12C01AM arbitrates for the serial bus during the next isochronous cycle.
The transmitter autonomously sends the cycle-start packets when the chip is a cycle master.
Receiver
The receiver takes incoming data from the phy interface and determines if the incoming data is addressed to
this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header CRC
is good, the header is confirmed in the GRF. For block and isochronous packets, the remainder of the packet
is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last quadlet of the
packet is confirmed in the GRF. The status quadlet contains the error code for the packet. The error code is the

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acknowledge code that is sent for that packet. For broadcast packets that do not need acknowledge packets,
the error code is the acknowledge code that would have been sent. This acknowledge code tells the transaction
layer whether or not the data CRC is good or bad. When the header CRC is bad, the header is flushed and the
rest of the packet is ignored.
When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle timer.
The cycle-start messages are not placed in the GRF like other quadlet packets. At the end of an isochronous
cycle and if the cycle mark enable (CyMrkEn) bit of the control register is set, the receiver inserts a cycle-mark
packet in the GRF to indicate the end of the isochronous cycle.
Transmit and Receive FIFOs
The TS812C01AM contains two transmit FIFOs (asynchronous and isochronous) and one receive FIFO
(general receive). Each of these FIFOs are one quadlet wide and their length is software adjustable. These
software-adjustable FIFOs allow customization of the size of each FIFO for individual applications. The sum
of all FIFOs cannot be larger than 509 quadlets. To understand how to set the size of the FIFOs, see sections
3.2.11 through 3.2.13. The transmit FI FOs are write only from the host bus interface, and the receive FIFO is
read only from the host bus interface.
An example of how to use software-adjustable FIFOs follows:

::>

In applications where isochronous packets are large and asynchronous packets are small, the
implementer can set the ITF and GRF to a large size (200 quadlets each) and setthe ATFto a smaller
size (100 quadlets). Notice that the sum of all FIFOs is less than or equallo 509 quadlets.

;:>

~~
The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit cycle-timer
register. Each node with isochronous data-transfer capability has a cycle-timer register as defined in the
IEEE-1394 standard. In the TS812C01AM, the cycle-timer register is implemented in the cycle timer and is
located in IEEE-1212 initial register space at location 200h and can also be accessed through the local bus at
address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which increments once every
24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count of 8, OOO-Hz (or 125
I-l-s)cycles, and the highest 7 bits count seconds.
The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle offset,
cycle count, and seconds count. The cycle timer has two possible sources. First, if the cycle source (CySrc) bit
in the configuration register is set, then the CYCLEIN input causes the cycle count field to increment for each
positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros. CYCLEIN should only
be the source when the node is cycle master. When the cycle-count field increments, CYCLEOUT is generated.
The timer can also be disabled using the cycle-timer-enable bit in the control register. See section 3.2.5,
Cycle-Timer Register for more information.
The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the reception
of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 Ils.
CYCLEOUT indicates to the cyclemaster node that it is time to send a cycle-start packet. And, on
noncyclemaster nodes, CYCLEOUT indicates that it is time to expect a cycle-start packet. The cycle-start bit
is set when the cycle-start packet is sent from the cyclemaster node or received by a noncyclemaster node.

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TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

Cycle Monitor
The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity. When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cycle-master bit is set in the control register.
Cyclic Redundancy Check (CRC)
The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The
CRC module generates the header and data CRC for transmitting packets and checkS the header and data CRC
for received packets. See the IEEE-1394 standard for details on the generation of the CRC (This is the same
CRC used by the IEEE802 LANs and the X3T9.5 FDDI).
Internal Registers
The internal registers control the operation of the TSB12C01AM. The register definitions are specified in
section 3.
Host Bus Interface
The host bus interface allows the TSB 12C01 AM to be easily connected to most host processors. This host bus
interface consists of a 32-bit data bus and an 8-bit address bus. The TSB12C01AM utilizes cycle-start and
cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be asynchronous to
one another. The TSB12C01AM is interrupt driven to reduce polling.

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TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLSOBB - MARCH 1996

TERMINAL ASSIGNMENTS

+--To Host

GNO
OATA16
OATA17
OATA18
OATA19
VCC
OATA20
OATA21
OATA22
OATA23
GNO
OATA24
OATA25
OATA26
OATA27

Reserved
VCC
NTCLK
NTOUT
NTBIHIZ
GNO
ISO
GNO
LREQ
GNO
SCLK

TSB12C01AM
WN PACKAGE

~¥Eo

(TOP VIEW)

CTL1
GNO

Vce

To Phy Layer
-..

OATA28
OATA29
OATA30
OATA31
GNO
AOORO
AOOR1
AOOR2
AOOR3

01
02
03
VCC
04
05
06
07
GNO

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NOTES: A. Tie reserved pins to GNO.
B. Bit 0 is the most significant bit (MSB).

-!!1

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terminal functions
TSB12C01AM

_.,,{

DATA[O:31]
ADDR[O:7]

D[O:7]
CTLO

CTL1

LREQ

ISO

INT

SCLK

CYCLEIN

CYCLEOUT
BCLK

RESET
NTCLK

CYST

NTOUT

CYDNE
GRFEMP

NTBIHIZ

Figure 2. TSB12C01AM Terminal Functions

."
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Table 1. Host Bus Interface Terminal Functions
TERMINAL

I/O

DESCRIPTION

22-25
27-30

Address 0 through address 7. Host bus address bus bits 0 through 7 that address the quadlet-aligned FIFOs
and configuration registers. The two least significant address lines, 6 and 7, must be grounded.

Cycle acknowledge (active low). CA is a TSB12C01AM control signal to the host bus. When asserted (low),
access to the configuration registers or FIFO is complete.

Cycle start (active low). CS is a host bus control signal to enable access to the configuration registers or FIFO.

2-5
7-10
12-15
17-20
82-85
87-90
92-95
97-100

I/O

Data 0 through 31. DATA is a host bus data bus bits 0 through 31.

INT

Interrupt (active low). When INT is asserted (low), the TSB12C01AM notifies the host bus that an interrupt
has occurred.

Read/write enable. When WR is deasserted (high) in conjunction with CS, a read from the TSB12C01AM is
requested. When WR is asserted (low) in conjunction with CS, a write to the TSB12COI AM is requested.

."
JJ

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GRFEMP

VCC

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5-V ±5% power supplies

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TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

absolute maximum ratings over free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.5 V to 6 V
Input voltage range, at any input, VI .......................................... -0.5 V to Vee + 0.5 V
Output voltage range, Vo ................................................... -0.5 V to Vee + 0.5 V
Input clamp current, 11K (VI < 0 or VI> Vee> (see Note 2) ................................... ±20 mA
Output clamp current, 10K (Vo < 0 or Vo > Vee> (see Note 3) ............................... ±20 mA
Storage temperature range ....................................................... -65°C to 150°C
Case temperature for 10 seconds .......................................................... 260°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. Applies to all inputs
3. Applies to all outputs

recommended operating conditions
Supply voltage, VCC

C
C

-t

MIN

NOM

MAX

UNIT

4.75

5.25

Input voltage, VI

VCC

High-level input voltage, VIH

VCC

Low-level input voltage, VIL

0.8

Clock frequency

I BCLK

ISCLK

49.152
-55

Operating free-air temperature, TA

-
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host-interface timing requirements over operating free-air temperature range

o-I

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All typIcal values are at VCC = 5 V and TA = 25°C .
NOTES: 4. This applies for all inputs except SCLK, BCLK, and RESET.
5. All outputs are in the high-impedance state.

0.2 VCC

:::D

0.7VCC

V'T+

Phy interface

UNIT

VCC-O.S

PARAMETER

w
MIN

MAX

UNIT

tc1

Cycle time, BCLK (see Figure 3)

tw1(H)

Pulse duration, BCLK high (see Figure 3)

tw1(L)

Pulse duration, BCLK low (see Figure 3)

tsu1

Setup time, DATA[0:31] before BCLKi (see Figure 4)

th1

Hold time, DATA[0:31] after BCLKi (see Figure 4)

tsu2

Setup time, ADDR[O:7] before BCLKi (see Figures 4 and 5)

th2

Hold time, ADDR[O:7] after BCLKi (see Figures 4 and 5)

tsu3

Setup time, CS before BCLKi (see Figures 4 and 5)

:::D

-
W
a:
a..

I
I
I
I
I..
I
I
I
I..

50% '\.

thl

50%1

leIl
CA
(see Note A)

tsu2

•1

I..

I
I"

tsul

I th4

I-

~
.1

:::l
C

td2

a:
a..

50%1

NOTE A: When back-to-back write cycles are done, a maximum of 9 BCLK cycles may be required
after the falling edge of CS before CA is asserted (low). DATA[O:31j, ADDR[O:7j, and WR
need to remain valid until CA is asserted (low).

Figure 4. Host-Interface Write-Cycle Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALu\S, TEXAS 75265

5-17

TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

BCLK

((

OATA[0:31] -------;-------'l.,..----r--~
JJ
1
1

ADOR[0:7]

tsu2

~~~I~~----------~.,..----~~------~---~'--.....,.-----......,.,....----+-----r_
:
tsu3-ti..t--l~_~_
.1

th3

50%1

CS ---5-0·;......' \...._-;-_-..1
1

I..

tsu4
((

"tJ
:JJ

CA
(see Note A)

o
C

-------------~)(.,..)------

NOTE A: When back-to-back read cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge
of CS and before CA is asserted (low). AODR[0:7] and WR need to remain valid until CA is asserted (low).

Figure 5. Host-Interface Read-Cycle Waveforms

-I
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m
:E

Figure 6. SCLK Waveform

SCLK
tdS

I..

0[0:7]

tdS
CTL[0:1]

.1
I

.1
1

~~:" ~
~

td9

I..

.1 td10
1

f---

Figure 7. TSB12C01AM-to-Phy-Layer Transfer Waveforms

~TEXAS

INSTRUMENTS
5-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

SCLK

0[0:7]

tsu6

th5

th6

-----f

I..

...

CTL[O:1] - - - - - { -

Figure 8. Phy-Layer-to-TSB12C01 AM Transfer Waveforms

td11

---"'~I-----+'.:
1

LREQ---""""'\Xr-----

==
w

Figure 9. TSB12C01AM-Link-Request-to-Phy-Layer Waveforms

5>
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a:
c.

~
I

I-

td13

~______~)\~______5_0.~Yo;r---

::J

o
a:
c.

Figure 10. Interrupt Waveform

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-19

TSB12C01AM
IEEE 1394-1995 HIGH-SPEED SERIAL-BUS LINK-LAYER CONTROLLER
SGLS088 - MARCH 1996

CYCLEIN

--rl-----.~-*~- tw3(L)
I
I
j4-- te3 --+i
Figure 11. CYCLEIN Waveform

SCLK

I
CYCLEIN

-.-I

'j~

I
td14-----'1

Figure 12. CYCLEIN and CYCLEOUT Waveforms

o
C

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m
~

~TEXAS

INSTRUMENTS
5·20

1.-

------1

ir-l'r-'j
CYCLEOUT _ _ _ _ _ _ _ _ _ _ _ _ _5_0°.J'Iot

"'tJ

--------

~-----------ri
td1S--.I

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

50%\..._ _ __

TSB14C01
P1394 BACKPLANE TRANSCEIVER/ARBITER
FOR 5-VOLT SUPPLY OPERATION
• Supports Provisions of IEEE P1394 Draft
Standardt for High-Performance Serial
Bus*
• Fully Interoperable With FireWire™
Implementation of P1394
• Provides A Backplane Environment That
Supports 100 Megabits per Second
(Mbits/s)

• Separate Transmitter and Receiver for
Greater Flexibility
• Data Interface to Link Layer Controller
Provided Through Two Parallel Signal
Lines at 50 Mbits/s

• Logic Performs System Initialization and
Arbitration Functions
• Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding

• Single 5-V Supply Operation
• High-Performance 64-Pin TQFP (PM)
Package

• 100-MHz Oscillator Provides Transmit,
Receive-Data, and Link Layer Controller
Clocks at 50 MHz

• Incoming Data Resynchronized to Local
Clock

description
The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplanebased P1394 network. The TSB14C01 provides two terminals for transmitting, two terminals for receiving, and
two terminals to externally control the drivers for data and strobe. The TSB14C01 is not designed to drive the
backplane directly, this function must be provided externally. The TSB14C01 is designed to interface with a link
layer controller such as the TSB12C01 A.
The TSB14C01 requires an external 98.304-MHz reference oscillator input. The 98.304-MHz reference signal
is internally divided to provide the 49.152-MHz ±1 ~O-ppm system clock signals used to control transmission of
the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the
associated link layer controller for synchronization of the two chips and is used for resynchronization of the
received data.
Data bits to be transmitted are received from the link layer controller on two parallel paths and are latched
internally in the TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and then transmitted at 98.304-Mbits/s as the outbound data-strobe information stream.
During transmission, the encoded data information is transmitted on TDATA, and the encoded strobe
information is transmitted on TSTRB.
During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the
associated link layer controller.
The TSB14C01 is a 5-V only device and provides CMOS-level outputs.

t P1394 Draft 8.0v.1 dated June 16, 1995
:j: This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.

FireWire is a trademark of Apple Computer, Incorporated.
PRODUCT PREVIEW infotmltion concerns products in the formative or
desl"n phase or development. Character1sllc data and other

:c:nge~r~:::tI~:,~=~~==~~rvestherightto

~TEXAS

INSTRUMENTS
POI$T OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-21

3:
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a:
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I-

::l
C

oa:

c..

5-22

TSB14C01M
IEEE 1394·1995 BACKPLANE TRANSCEIVER/ARBITER
FOR 5·VOLT SUPPLY OPERATION
• Supports Provisions of IEEE 1394-1995
Standardt for High-Performance Serial
Bus*
• Fully Interoperable With FireWire™
Implementation of IEEE 1394-1995
• Provides A Backplane Environment That
Supports 100 Megabits per Second
(Mbits/s)

• Separate Transmitter and Receiver for
Greater Flexibility

• Logic Performs System Initialization and
Arbitration Functions

• Single 5-V Supply Operation
• High-Performance 64-Pin TQFP (PM)
Package

• Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
• Incoming Data Resynchronized to Local
Clock

• Data Interface to Link Layer Controller
Provided Through Two Parallel Signal
Lines at 50 Mbits/s
• 100-MHz Oscillator Provides Transmit,
Receive-Data, and Link Layer Controller
Clocks at 50 MHz

• 68-Pin Ceramic Quad Flat Package (HV) For
Military Operation (-55°C to 125°C)

description
The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplanebased IEEE1394-1995 (from now on refered to as 1394) network. The TSB14C01 provides two terminals for
transmitting, two terminals for receiving, and two terminals to externally control the drivers for data and strobe.
The TSB14C01 is not designed to drive the backplane directly, this function must be provided externally. The
TSB14C01 is deSigned to interface with a link layer controller such as the TSB12C01A.
The TSB14C01 requires an external 98.304-MHz reference oscillator input. The 98.304-MHz reference signal
is internally divided to provide the 49.152-MHz ±1 OO-ppm system clock signals used to control transmission of
the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the
associated link layer controller for synchronization of the two chips and is used for resynchronization of the
received data.
Data bits to be transmitted are received from the link layer controller on two parallel paths and are latched
internally in the TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined
serially, encoded, and then transmitted at 98.304-Mbits/s as the outbound data-strobe information stream.
During transmission, the encoded data information is transmitted on TDATA, and the encoded strobe
information is transmitted on TSTRB.
During packet reception the encoded information is received on RDATA and strobe information on RSTRB. The
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the
associated link layer controller.
The TSB14C01 is a S-V only device and provides CMOS-level outputs.

tThis serial bus implements technology covered by one or more patents of Apple Computer. Incorporated and INMOS, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCT PREVIEW Information con..rns praclucIIln the _
or
de8lgn ph_ 01 cIovelopment. Cheroctortotio daIa .nd _
_ _...... _n goals. Tuas Instru..........rvaothe right ..
ctIange ordlsconUnualhoIa produc:tIwIUIout notIca.

'~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DAllAS, TEXAS 75265

5-23

3:
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:>
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a..
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::J
C

a:
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5-24

TSB21 LV03
P1394 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS230 - MARCH 1996

• Supports Provisions of IEEE P1394 Draft
Standardt for High-Performance Serial
Bus:!:

• Data Interface to Link Layer Controller
Provided Through Two/Four Parallel Lines
at SO Mbits/s

• Fully Interoperable with FireWire™
Implementation of P1394 Draft Standard

• 2S-MHz Crystal Oscillator and PLL Provide
Transmit, Receive Data at SO/100 MHz, and
Link Layer Controller Clock at SO MHz

• Provides Three Fully-Compliant Cable
Ports at 100/200 Megabits per Second
(Mbits/s)

• Interoperable with Link Controllers Using
S-V Supplies

• Cable Ports Monitor Line Conditions for
Active Connection to Remote Node

• Node Power Class Information Signaling
for System Power Management

• Device Power-Down Feature to Conserve
Energy in Battery Powered Applications

• Cable Power Presence Monitoring

• Inactive Ports Disabled to Save Power
• Logic Performs System Initialization and
Arbitration Functions
• Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
• Incoming Data Resynchronized to Local
Clock
• Single 3.3-V Supply Operation

• Cable Bias and Driver Termination Voltage
Supply
• Separate Multiple Package Terminals
Provided for Analog and Digital Supplies
and Grounds
• Interoperable with Transceivers Using S-V
Supplies

:r:w

• High-Performance 54-Pin TQFP (PM)
Package

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• Interface to Link Layer Controller Supports
Optional Electrical Isolation

a::

description
The TSB21 LV03 provides the analog transceiver functions needed 10 implement a 3-port node in a cable-based
P1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry
to monitor the line conditions as needed for determining connection status, initialization and arbitration, and
packet reception and transmission. The TSB21 LV03 is designed to interface with a link layer controller such as
the TSB12C01A.
The TSB21 LV03 requires an external 24.576-MHz crystal. The crystal oscillator drives an internal phase-locked
loop (PLL), which generates the required 196.608-MHz reference signal. The 196.608-MHz reference signal
is internally divided to provide the 49.152-!98.304-MHz clock signals that control transmission of the outbound
encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the associated link layer
controller for synchronization of the two chips, and is used for resynchronization of the received data. The
power-down function, enabled by taking the PO terminal high, stops operation of the PLL.
The TSB21 LV03 supports an optional isolation barrier between itself and its link layer controller. When the ISO
terminal is tied high, the link interface outputs behave normally. When this terminal is tied low, internal
differentiating logic is enabled and the outputs become short pulses that can be coupled through a capacitor
or transformer. See the P1394!Oraft 8.0v1 Annex J for further details.

t P1394 Draft S.Ov.1

dated June 16, 1995
:j: This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic: data and other
specHlcations are design goals. Texas Instruments reserves the right to
change or discontinue th88t products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-25

I-

::l
C

a::

TSB21 LV03
P1394 TRIPLE-CABLE TRANSCEIVER/ARBITER
SLLS230 - MARCH 1996

description (continued)
Data bits to be transmitted are received from the link layer controller on two/four parallel paths, and are latched
internally in the TSB21 LV03 in synchronization with the 49.152-MHz system clock. These bit pairs are combined
serially, encoded, and then transmitted at 98.304/196.608 megabits per second (Mbits/s) as the outbound
data-strobe information stream. During transmission, the encoded data information is transmitted differentially
on the TPBx cable pair(s), and the encoded strobe information is transmitted differentially on the TPAx cable
pair(s).
During packet reception the TPAx and TPBx receiving cable port transmitters are disabled, and the cable port
receivers are enabled. The encoded data information is received on the TPAx cable pair, and the encoded
strobe information is received on the TPBx cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial data bits are split into two/four parallel
streams, resynchronized to the local system clock, and sent to the associated link layer controller. The received
data is also transmitted (repeated) out of the other active cable ports.
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage value. The value of
this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In
addition, the TPB channel monitors the incoming cable common-mode voltage for the presence of the remotely
supplied twisted-pair bias voltage. The presence or absence of this common-mode voltage is an indication of
cable connection status. The cable connection status signal is internally de bounced in the TSB21 LV03 on a
cable disconnect-to-connect. The debounced cable connection status signal initiates a bus reset. On a cable
disconnect-to-connect the debounce delay is 335 ms. There is no delay on a cable connect-to-disconnect.

"0
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The TSB21 LV03 provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, senses the presence of an active connection. The value of this bias
voltage has been chosen to allow interoperability between transceiver chips operating from either 5-V nominal
supplies or 3-V nominal supplies. This bias-voltage source should be stabilized by using an external filter
capacitor of approximately 1.0 IlF.

"0
l:J

The transmitter circuitry is disabled under the following conditions: power-down, cable not active, reset, or
transmitter disabled. The receiver circuitry is disabled under the following conditions: power-down, cable not
active, receiver disabled. The twisted-pair bias-voltage circuitry is disabled either with a power-down or a reset
condition. The power-down condition occurs when the PO terminal is high. The cable-not-active condition
occurs when the cable connection status indicates no cable is connected and is not debounced. The reset
condition occurs when the RESET terminal is low. The transmitter disabled and receiver disabled conditions
are determined from the internal logic.

<
-

The line drivers in the TSB21 LV03 operate in a high-impedance current mode and are designed to work with
external 112-0 line-matching resistor networks. One network is provided at each end of each twisted-pair cable.
Each network is composed of a pair of series-connected 56-0 resistors. The pair of resistors that are connected
to .the twisted-pair TPAx terminals are also connected to the TPBIAS terminal. The pair of resistors that are
connected to the twisted-pair TPBx terminals are also coupled to ground through a parallel
resistance-capacitance (RC) network with recommended values of 5 kO and 250 pF. The values of the external
resistors are designed to meet the draft standard specifications when connected in parallel with the internal
receiver circuits.
The driver output current, along with other internal operating currents, is set by an external resistor. This resistor
is connected between the RO and R1 terminals and has a value of 6.3 kO, ±O.5%.

~TEXAS

5-26

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TSB21 LV03
P1394 TRIPLE·CABLE TRANSCEIVER/ARBITER
SLLS230 - MARCH 1996

description (continued)
Four package terminals are used as inputs to set four configuration status bits in the self-identification packet.
These terminals are hardwired high or low as a function of the equipment design. PCO - PC2 are the three
terminals that indicate either the need for power from the cable or the ability to supply power to the cable. The
fourth terminal (CMC/LKON) indicates whether a node is a contender for configuration manager. See Table
4-29 of the IEEE P1394 draft standard for additional details.
A power-down terminal (PO) is provided to allow most of the TSB21 LV03 circuits to be powered down to
conserve energy in battery-driven applications. A cable status terminal (CNA) provides a high output when all
twisted-pair cable ports are disconnected. This output is not debounced. The CNA output can determine when
to power the TSB21 LV03 down. In the power-down mode all circuitry is disabled except the CNA detection
circuitry. It should be noted that while the device is powered down it does not act in a repeater mode.
If the TSB21 LV03 is being used in a single port application and the power supply of the TSB21 LV03 is removed
while the twisted-pair cables are connected, the TSB21 LV03 transmitter and receiver circuitry presents a
high-impedance signal to the cable and does not load the reference voltage on the other end of the cable.

3:
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IX:

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IX:

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~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-27

5-28

TSB21 LV03M
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
• Supports Provisions of IEEE 1394-1995
Standard for High-Performance Serial Bust

• Provides Three Fully Compliant Cable
Ports at 100/200 Mbits Per Second (Mbitsls)

• Data Interface to Link-Layer Controller
Provided Through 214 Parallel Lines at
50 Mbitsls
• 25-MHz Crystal Oscillator and PLL Provide
Transmit, Receive Data at 50/100 MHz, and
Link-Layer Controller Clocks at 50 MHz

• Cable Ports Monitor Line Conditions for
Active Connection to Remote Node

• Interoperable With Link Controllers and
Transceivers Using 5-V Supplies

• Device Power Down Feature to Conserve
Power in Battery-Driven Applications

• Node Power Class Information Signaling
for System Power Management

• Inactive Ports Disabled to Save Power
• Logic Performs System Initialization and
Arbitration Functions

• Cable Power Presence Monitoring
• Cable Bias and Driver Termination Voltage
Supply

• Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding

• Separate Multiple Package Terminals
Provided for Analog and Digital Supplies
and Grounds

• Fully Interoperable With FireWire™
Implementation of IEEE 1394-1995

• Incoming Data Resynchronized to Local
Clock
• Single 3.3-V Supply Operation
• Interface to Link Layer Controller Supports
Optional Electrical Isolation

• Interoperable with Transceivers Using 5-V
Supplies
• 68-Pin Ceramic Quad Flatpack (HV) and
Characterized For Operation Over the Full
Military Temperature Range of -55°C to
125°C

3:
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description
The TSB21 LV03M provides the analog transceiver functions needed to implement a three-port node in a
cable-based IEEE 1394-1995 (from now on referred to as 1394) network. Each cable port incorporates two
differential line transceivers. The transceivers include circuitry to monitor the line conditions needed for
determining connection status, for initialization and arbitration, and for packet reception and transmission. The
TSB21 LV03M is designed to interface with a link-layer controller, such as the TSB12C01 AM.
The TSB21 LV03M requires an external 24.576-MHz crystal. The crystal oscillator drives an internal
phase-locked loop (PLL), which generates the required 196.60S-MHz reference signal. The 196.60S-MHz
reference signal is internally divided to provide the 49.152/9S.304-MHz signals used to control transmission of
the outbound encoded strobe and data information. The 49.152-MHz clock signal is also supplied to the
associated link-layer controller for synchronization of the two chips and is used for resynchronization of the
received data.
The TSB21 LV03M supports an optional isolation barrier between itself and its link-layer controller. When ISO
is tied high, the link interface outputs behave normally. When ISO is tied low, internal differentiating logic is
enabled and the outputs become short pulses that can be coupled through a capacitor or transformer. See the
IEEE 1394-1995 Standard Annex J for more information.

t Implements technology covered by one or more patents of Apple Computer, Incorporated and INMOS, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCT PREVIEW information concerns products in the formative or

re:::es:: ri:~~

=~ficaff~~:eare°:.es1:~=~~!xa;~~~::~~c

change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265

5-29

I-

U
::J
C

oa:
a..

TSB21 LV03M
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS089 - MARCH 1996

description (continued)
Data bits to be transmitted are received from the link-layer controller on two/four parallel paths and are latched
internally in the TSB21 LV03M in synchronization with the 49.152-MHz system clock. These bit pairs are
combined serially, encoded, and transmitted at 98.304/196.608 Mb/s as the outbound data-strobe information
stream. During transmit, the encoded data information is transmitted differentially on the TPB cable pair(s) and
the encoded strobe information is transmitted differentially on the TPA cable pair(s).
During packet reception, the TPA and TPB transmitters of the receiving cable port are disabled and the receivers
for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded
strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover
the receive clock signal and the serial data bits. The serial data bits are split into two/four parallel streams,
resynchronized to the local system clock and sent to the associated link-layer controller. The received data is
also transmitted (repeated) out of the other active cable ports.

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-

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during
initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the
arbitration status. The TPA channel monitors the incoming cable common-mode voltage value, which is used
during arbitration to set the speed of the next packet transmission. The TPB channel monitors the incoming
cable common-mode voltage. The presence or absence of this bias voltage is used as an indication of
cable-connection status.
The TSB21 LV03M provides a 1.86-V nominal bias voltage for driver load termination. This bias voltage, when
seen through a cable by a remote receiver, is used to sense the presence of an active connection. The value
of this bias voltage has been chosen to allow interoperability between transceiver chips operating from either
5-V nominal supplies or 3-V nominal supplies. This bias voltage source should be stabilized by using an external
filter capacitor of approximately 1 1lF.
The line drivers in the TSB21 LV03M operate in the high-impedance current mode and are designed to work with
external 112-Q line matching resistor networks. One network is provided at each end of each twisted-pair cable.
Each network is composed of a pair of series-connected 56-Q resistors. The midpoint of the pair of resistors
that is directly connected to the twisted-pair A-package terminals is connected to the TPBIAS voltage terminal.
The midpoint of the pair of resistors that is directly connected to the twisted-pair B-packageterminals is coupled
to ground through a parallel RC network with recommended values of 5 kQ and 250 pF. The values of the
external resistors are designed to meet the IEEE 1394-1995 standard specifications when connected in parallel
with the internal receiver circuits.
The driver output current, along with other internal operating currents, is set by an external resistor. This resistor
is connected between RO and R1 and has a value of 6.3 kQ ±0.5%.
Two terminals are used to set up various test conditions used in manufacturing. Terminals TESTM1 and
TESTM2 should be connected to Vee for normal operation.
Four terminals are used as inputs to set four configuration status bits in the self-identification packet. These
terminals are hardwired high or low as a function of the equipment design. PC[0:2] are three terminals used to
indicate either the need for power from the cable or the ability to supply power to the cable. The fourth pin,
CMC/LKON, is used to indicate if a node is a contender for configuration manager. See Table 4-29 of the IEEE
1394-1995 standard for additional details.
A power down terminal (PD) is provided to allow most of the TSB21 LV03M circuits to be powered down to
conserve energy in battery-driven applications. A cable-status terminal (CNA) provides a high output when all
twisted-pair cable ports are disconnected. This output can be used to determine when to power the device down.
In the power-down mode, all circuitry is disabled except the CNA-detection circuitry. Note that when the device
is powered down, it will not act in a repeater mode.

~TEXAS

INSTRUMENTS
5-30

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TSB21 LV03M
IEEE 1394-1995 TRIPLE-CABLE TRANSCEIVER/ARBITER
SGLS089 - MARCH 1996

If the TSB21 LV03 is being used in a single port application and the power supply of the TSB21 LV03 is removed
while the twisted-pair cables are connected, the TSB21 LV03 transmitter and receiver circuitry presents a
high-impedance signal to the cable and does not load the reference voltage on the other end of the cable.
The TSB21 LV03M is characterized for operation from -55°C to 125°C.

3:
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-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-31

5-32

Mechanical Data

6-1

-C

...mm

6-2

DL (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

48 PIN SHOWN

·l rl11

A MAX

0.380
(9,65)

0.630
(16,00)

0.730
(18,54)

A MIN

0.370
(9,40)

0.620
(15,75)

0.720
(18,29)

DIM

0.025 (0,635)

1-$-1

0.012 (0,305)
0.005 (0 13)
0.008 (0,203)··
'

@1
.

-------x-

0.299 (7,59)
0.291 (7,39)

o
T'T"r'1"I'"I'T' ' ' ' ' A"!'T"T 'T!" ~M'"T~"T~'n~T 'T"T'~T'1"~'!" m~+-i
"T'"'!~ _--I.l

0.420 (10,67)

~~~~

! - r' r m l

0.020 (0,51)

Sort",

",~I~~ @-+-------"hL

1=1 0.004(0,10)

4040048/802195
NOTES: A. A" linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-3

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN
Seating Plane

1~ =10.004(0,10)

~----

-----~

__o\-- 0.180 (4,57) MAX

i4------.r- 0.120 (3,05)

01~
3

0.090 (2,29)
0.020 (0,51) MIN

~I
0.032 (0,81)
0.026 (0,66)

02/E2

El
~

0.013 (0,33)
1-$-1 0.007 (0,18)

DIE

NO. OF
PINS
MIN

02/E2

t-+-1==~:::Jg~

01/El
MAX

MIN

®J

02lE2
MAX

MIN

MAX

0.141 (3,58)

0.169 (4,29)

0.385 (9.78)

0.395 (10.03)

0.350 (8,89)

0.485 (12,32)

0.495 (12,57)

0.450 (11,43)

0.456 (11,58)

0.191 (4,85)

0.219 (5,56)

0.685 (17,40)

0.695 (17,65)

0.650 (16,51)

0.656 (16,66)

0.291 (7,39)

0.319 (8,10)

0.356 (9,04)

0.785 (19,94)

0.795 (20,19)

0.750 (19,05)

0.756 (19,20)

0.341 (8,66)

0.369 (9,37)

0.985 (25,02)

0.995 (25,27)

0.950 (24,13)

0.958 (24,33)

0.441 (11,20)

0.469 (11,91)

1.185 (30,10)

1.195 (30,35)

1.150 (29,21)

1.158 (29,41)

0.541 (13,74)

0.569 (14,45)
40400051 B 03195

NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS·018

~TEXAS

INSTRUMENTS
6·4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N (R-PDIP-T**)

PLASTIC DUAL-IN-L1NE PACKAGE

24 PIN SHOWN
A

0.560 (14,22)
0.520 (13,21)

~~~~
12

0.200 (5,08) MAX

0.020 (0,51) MIN

0.610(15,49)

0.590(14,99) \

WUWUWfUW~
JL
JL I.-.H
Seating Plane

0.100 (2,54)

0.125 (3,18) MIN

®1

1-$-1

0.021 (0,53)
0.010 (0 25)
0.015 (0,38)··
'
-

0.010 (0,25) NOM

A MAX

1.270
(32.26)

1.450
(36.83)

1.650
(41.91)

2.090
(53.09)

2.450
(62.23)

2.650
(67.31)

A MIN

1.230
(31.24)

1.410
(35.81)

1.610
(40.89)

2.040
(51,82)

2.390
(60.71)

2.590
(65,79)

DIM

4040053/804195
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-Oll
D. Falls within JEDEC MS-015 (32 pin only)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-5

PM (S-PQFP-G64)

PLASTIC QUAD FLATPACK

11:~~~ I~I

0,08

l-rm
~

',OOTYP
10,20 SQ
9,80

l
rmr
===::j

1 + - - - - - - - 12,20 SQ ------~
11,80

Seating Plane

4040152/803/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136

~TEXAS

INSTRUMENTS
6-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PS (R-PDSO-G8)

PLASTIC SMALL-OUTLINE PACKAGE

1-$-1 0,25 ®I
0,35 '---"'--'--'-'-'---"'''-'
~5 0,51

TIl
5,60
5,00

8,20
7,40

~-r-r--' ~

'--r-r

4040063/802195
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-7

PT (S-PQFP-G48)

PLASTIC QUAD FLATPACK

1r-:

0,271-$-1
0,08 @I
0,17 '--"-'--'--_=-.J

9,20

sa ____~

8,80

[

ftrs

0,05 MIN

rbr--UU-U-UU-U-UU-U"""1'tZh'\

1,60 MAX

L
,ooti"" ~'".
~c.lo'lO

0,45

40400521 B 03195

NOTES: A.
B.
C.
D.

All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Falls within JEDEC MO-136
This may also be a thermally enhanced plastic package with leads conected to the die pads.

~TEXAS

INSTRUMENTS
6-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PZ (S-PQFP-G100)

10:

PLASTIC QUAD FLATPACK

1151 ~:~ 1~I 0,08 @I

nnr,nnlnnnn"nrlnnnnl,nn

15,80 sa ____
16,20

~
f
[= .dJ"'-UU-U-U-UU-U-U-UU-U-U-UU-U-U-uu-u-u-uu-0
1,60 MAX

~-=-10,08 1
40401491 A 03/95

NOTES: A. A1llinesr dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136

~1EXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285

6-9

6-10

NOTES

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600-366-6731 Hamilton Hallmark
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600-524-4735
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(407) 296-7100
(818) 768-7400
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(512) 834-2022Minco Tachnology Labs
CATALOG
Allied Electronics
600-433-5700
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6OD-777-2776
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800-367-3573
For Dlsllfbutors DUfIIIde North America, contact your /ocal Sales OffIce.
Impol'lllll MOllet: Texas Instru...... en) rtSlI!Y8' the lightto make chlllgas to or to _nua any
procIuc:t or seMceldentilied In th~ publication without noUce. TI advises its customers to obtain the latest
version of the relevent innation to verify, befora placing orders, thet the information being reled .....n Is
current.
Please be edv8edIhetTi warrants Its semiconductor ~ and relatod _ a to the s~s
eppIIcabIa altha time of sale in accordance with TI~ standard warranty. TI easumes no llablily for
epptications assistance, software performance, or thiuljJarty procIuc:t information, or tor i1tIingement of
I ~nm. ~r~ described in this pWlHcation. Tlassurnas no responsibiilytor customers' appicetlona or
1_"""IIn~

A022398
1996 Texas Instruments Incorporated
Printed in the USA

"1ExAs
INSTRUMENTS

•
TEXAS
INSTRUMENTS
Printed in U.S.A.

3-96

SLLD003

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1996_TI_Data_Transmission_Circuits_Vol_2_Communications_Controllers_Data_Book 1996 TI Data Transmission Circuits Vol 2 Communications Controllers Book

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