1996_TI_High Performance_FIFO_Memories_Designers_Handbook 1996 TI High Performance FIFO Memories Designers Handbook
User Manual: 1996_TI_High-Performance_FIFO_Memories_Designers_Handbook
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TEXAS
INSTRUMENTS
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High.Performance
FIFO Memories
1996
1996
Advanced System Logic Products
General Information
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Product OveNiew
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Power Considerations
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Device Models
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Mechanical and Thermal Information
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Quality and Reliability Assurance
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High-Performance FIFO Memories
Designer's Handbook
:'IlExAs
INSTRUMENTS
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Printad on Recycled " -
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
representthat any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri
INTRODUCTION
The Texas Instruments (TI) High-Performance FIFO Memories Designer's Handbook has
been created to provide users and potential users of TI's FIFOs with a comprehensive
collection of information and data used as a reference guide during the design-in process.
In a much broader sense, the designer's handbook also is a means to further the overall
understanding and awareness of TI's FIFOs and their many applications.
The contents of the handbook complement the information contained in the 1996
High-Performance FIFO Memories Data Book, literature number SCAD003C. In addition
to an expanded series of FIFO application notes, the handbook also contains information
that is useful to the deSigner, such as sample power-dissipation calculations, mechanical
packaging data, thermal-resistance data, and quality/reliability assurance information.
Section 6, Device Models, includes lists of available VHDL [VHSIC (very high-speed
integrated circuits) hardware-description language] models and logic-modeling behavior
models.
This deSigner's handbook is organized into seven major sections: General Information
(section 1), Product Overview (section 2), Specific Application Reports (section 3), Power
Considerations (section 4), Mechanical and Thermal Information (section 5), Device
Models (section 6), and Quality and Reliability Assurance (section 7).
Section 1 contains a glossary of symbols, terms, and definitions that are used throughout
the handbook. These symbols, terms, and definitions are presented in accordance with
those currently agreed upon by the JEDEC Council ofthe Electronic Industries Association.
Section 2 provides an overview of TI's FIFO products. The summary charts in this section
allow quick reference of key FIFO parameters, such as architecture, organization, speed
sort, maximum clock frequency, and available packaging options. The features associated
with TI's advanced application-specific FIFOs are summarized in this section. Section 2
also includes a flow chart that can be used as an aid in selecting a FIFO architecture based
on a known bus width.
Section 3 provides a comprehensive set of FIFO application reports. The application
reports are organized into subsections based on the subject matter of each report. The
subsections are FIFO Performance and Reliability, FIFO Features, and FIFO Applications.
Section 4 provides typical power characteristics in the form of active supply current versus
frequency for each of TI's advanced FIFOs. Plots of idle supply current versus frequency
also are given for a select number of FIFOs. In addition to this data, sample
power-clissipation calculations are performed for a representative set of FIFOs. The
application report in this section is used as a guideline for these calculations. Calculations
and equations are provided for CMOS FIFOs and Advanced BiCMOS Technology (ABT)
FIFOs.
Section 5 contains mechanical drawings for each FIFO packaging option. The official
JEDEC descriptor is used to identify each package type. These drawings typically include
the following dimensions: lead pitch (tip to tip), body width and length, shoulder-to-shoulder
insertion width, lead width, thickness, and angles, and package maximum height, and
stand-off clearances from seating plane to bottom of the package. Included with the
mechanical data is thermal data for each FIFO packaging option. Thermal resistance
values for varying conditions and power-dissipation derating curyes for varying air flows are
v
'\
presented for each package type. Several application reports and papers also are included
in this section to provide further detail regarding overall thermal considerations and
thermal-resistance measurements, including the design and development of the thermally
enhanced thin quad flat package (TQFP).
Section 6 contains a list ofthe behavioral models currently available from TI. All speed sorts
of the devices under consideration are included in the models. VHDL models of FIFO
devices included in this section may be obtained by calling the Advanced System LogiC
hotline at 903-868-5202.
Section 7 addresses the issue of quality and reliability assurance for TI's FIFO products.
Concepts such as the qualification of products and processes, quality and reliability
assurance in integrated-circuit design, and quality and reliability monitoring are discussed.
For further information on TI's FIFO products or applications, please contact the Advanced
System Logic hotline at 903-868-5202. For information on TI's military FIFO devices,
contact military Advanced System Logic marketing at 915-561-7289.
vi
Contents
Section 1 - General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. 1-1
Glossary .•...••••••.•••••••.••••••.••••..•.••••••••••••.•.••••••••••••.•••••.•••••••• 1-3
Section 2 - Product Overview. • . . . • . . . . . . . . . . • . . . . . . . . • . . . . • . . . . . . . . .. 2-1
FIFO Product Offerings ••••••••••••••••••••••..•••••.•••.••••••••••••.•••••.•••••.•••• 2-3
Advanced Clocked FIFOs ......................................................... 2-5
Advanced Strobed FIFOs ......................................................... 2-5
Advanced Application-Specific Clocked FIFOs ....................................... 2-6
Advanced Application-Specific FIFO Features ........................................ 2-6
Synchronous Mature FIFOs ....................................................... 2-6
Asynchronous Mature FIFOs ...................................................... 2-7
FIFO Functionality ................................................................ 2-8
.
FIFO Selection Flow Chart •••.••••••••••••••••••.•••••••••••••••.•••••••••••.•••••••• 2-11
Sect/on 3 - Specific Application Reports . .•...•.......•.............. " 3-1
FIFO Performance and Reliability ••••••••••••••••••.•••••••••••••••••.••••••••.••••••.• 3-3
Metastability Performance of Clocked FIFOs ......................................... 3-5
FIFO Memories: Solution to Reduce FIFO Metastability •............................. 3-17
Simultaneous-Switching Noise Analysis for Texas Instruments FIFO Products ........... 3-23
FIFO Solutions for Increasing Clock Rates and Data Widths .......................... 3-41
FIFO Features •••••••••••••.••••••••.•.•••••••••••••••••••••••••.•.••••••••••••••.••. 3-51
FIFO Patented Synchronous Retrans~it: Programmable DSP-Interface Application
for FIR Filtering .............................................................. 3-53
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control ....... 3-65
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications .. 3-75
Parity-Generate and Parity-Check Features
for High-Bandwidth-Computing FIFO Applications ....................•............ 3-67
FIFO Applications ••••••••••••••••••••••.•••••••••••••••••••••.•••••••••••••••••••••• 3-95
Multiple-Queue First-In, First-Out Memory SN74ACT53861 ...•....................... 3-97
Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors ......... 3-121
FIFOsWith a Word Width of One Bit ............................................. 3-141
Internetworking the SN74ABT3614 ..........•................................... 3-161
High-Speed, High-Drive SN74ABT7819 FIFO ..................................... 3-181
SPARC MBus-to-Futurebus+ Bridge Using the Texas Instruments Futurebus+ Chipset .. 3-193
1K x 9 x 2 Asynchronous FIFOs SN74ACT2235 and SN74ACT2236 ............... 3-207
64-Byte FIFOs SN74ALS2232A and SN74ALS2233A .............................. 3-217
Section 4 - Power Considerations • •••.•...•••••.•..•....••.•••....•... 4-1
Introduction •••••••••••••.••••••••.•••••••.•••••.•••••••••••••••••••••••••••••••••••. 4-3
Key Power-Dissipation Equations for ACT FIFOs ...............•.........•........... 4-5
Key Power-Dissipation Equations for ABT FIFOs ...................•................. 4-6
Application Report .................................................................... 4-9
Power-Dissipation Calculations for TI FIFO Products ................................. 4-11
Single-Bit FIFOs •••••••••.•••••••••••••.••••••••••••.•••••••••••••••••••••••••••••..• 4-31
Sample Power-Dissipation Calculations for SN74ACT2229 ........................... 4-33
Power Characteristics ........................................................... 4-34
SN74ACT2226 and SN74ACT2228 Single FIFO Supply Current
Versus Clock Frequency .................•.................................. 4-34
SN74ACT2227 and SN74ACT2229 Single FIFO Supply Current
Versus Clock Frequency .................................................... 4-34
vii
Section 4 - Power Considerations (Continued)
3~Blt
Clocked FIFOs •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4~
Sample Power-Dissipation Calculations for SN74ABT3613 ...............•....•...••. 4-37
Power Characteristics •.•.....••.•.•........•.....•.•........•................... 4-3.8
SN74ABT3611 Supply Current Versus Clock Frequency .....•.......•.•...•.•..•.. 4-38
SN74ABT3612 Supply Current Versus Clock Frequency ...........•....•...••..•.. 4-38
SN74ABT3613 Supply Current Versus Clock Frequency .•.•........•.............. 4-39
SN74ABT3614 Supply Current Versus Clock Frequency .......•...•............... 4-39
SN74ABT3614 Idle Current With ClKA Switching, Other Inputs at 0 or Vec - 0.2 V
and Outputs Disconnected .................................................. 4-40
SN74ABT3614 Idle Current With ClKB Switching, Ottier Inputs at 0 or Vee - 0.2 V
and Outputs Disconnected .................................................. 4-40
Sample Power-Dissipation Calculations for SN74ACT3641 •..•.................•....• 4-41
Power Characteristics ........................................................... 4-42
SN74ACT3632 Supply Current Versus Clock Frequency ........................... 4-42
SN74ACT3638 Supply Current Versus Clock Frequency ......•...... , ............. 4-42
SN74ACT3631 and SN74ACT3641 Supply Current Versus Clock Frequency ..•.•..•. 4-43
SN74ACT3641 Idle Current With ClKA Switching ................................. 4-43
SN74ACT3641 Idle Current With ClKB Switching' ................................. 4-44
SN74ACT3641 Active Current With ClKA and ClKB Switching,
Simultaneous ReadIWrlte and ClKB as Data Output ...•••..•.....•.......•..... 4-44
18-Blt Clocked/Strobed FIFOs •••••••••••••••••••••••••••••••••••••••••••••••••••••••• 4-45
Sample Power-Dissipation Calculations for SN74ABT7819 ....•......•....•...•...... 4-47
Power Characteristics ...................•..•................•.........•....•.... 4-48
SN74ABT7819 Supply Current Versus Clock Frequency ....•.....................• 4-48
SN74ABT7820 Supply Current Versus Clock Frequency ••..•...........•....•....• 4-48
Sample Power-Dissipation Calculations for SN74ACT7803 ...••......•.............•• 4-49
Power Characteristics •..•.•....•..........•....................................• 4-50
SN74ACT7804 Supply Current Versus Clock Frequency .............•.....•....... 4-50
SN74ACT7806 Supply Current Versus Clock Frequency •...•...........•..•......• 4-50
SN74ACT7814 Supply Current Versus Clock Frequency ......•.•.•...•............ 4-51
SN74ACT7803 Supply Current Versus Clock Frequency ......................•..•. 4-51
SN74ACT7803 Idle Current With RDClK or WRTClK Switching .•.•.•.••........... 4-52
SN74ACT7805 Supply Current Versus Clock Frequency ..........•................ 4-52
SN74ACT7813 Supply Current Versus Clock Frequency ........•........••...••... 4-53
9-Bit Clocked/Strobed FIFOs •••••••••••••••••••••••••••••••••.••••••••••••••••••••••• 4~5
Sample Power-Dissipation Calculations for SN74ACT7807 ........................... 4-57
Power Characteristics .•.........•.................................•............. 4-58
SN74ACT7807 Supply Current Versus Frequency .....•..................•....•. .4-58
SN74ACT78071dle Current With WRTClK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected .....•...•......•.... 4-58
SN74ACT7807 Idle Current With RDClK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected .....•..•..........•. 4-59
SN74ACT7808 Supply Current Versus Frequency ................................ 4-59
Section 5 - Mechanical and Thermal Information ••••••••••••••••••••••• 5-1
Comparison Summary of Advanced Packaging Derating Curves (In Stili Air) •••••••••••••• 5-3
Introduction .•.........••..•....•...............•...........................•.... 5-5
Application Reports/Papers ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 5-7
FIFO Surface-Mount Package Information ...•...••.•.•..•....•.......•.•...•....•..• 5-9
FIFO Memories: Fine-Pitch Surface-Mount Manufacturability .•.•......•.•....••.....•. 5-19
Package Thermal Considerations ................................................. 5-29
K-Factor Test-Board Design Impact on Thermal-Impedance Measurements ....•......•. 5-41
More Power in less Space: A Thermal Enhancement Solution for Thin Packages ........ 5-55
FIFO Surface-Mount Packages for PCMCIA Applications .........•.......•........... 5-69
viii
Section 5 - Mechanical and Thermal Information (Continued)
Package Outlines and Thermal Data •..•••..•••.••...•••..••..•••..•••••••..•.•••••..• 5-81
Introduction .................................................................... 5-83
Plastic Dual-In-Line Package (PDIP)
N/R-PDIP-T16 (16-Pin DIP) .................................................... 5-84
N/R-PDIP-T20 (20-Pin DIP) .................................................... 5-86
N/R-PDIP-T28 (28-Pin DIP-600 mil) ............................................. 5-88
N/R-PDIP-T40 (40-Pin DIP) .................................................... 5-90
NP/R-PDIP-T28 (28-Pin DIP-300 mil) ........................................... 5-92
NT/R-PDIP-T24 (24-Pin DIP) ................................................... 5-94
Plastic J-Leaded Chip Carrier (PQCC)
FN/S-PQCC-J20 (20-Pin PLCC) ................................................ 5-96
FN/S-PQCC-J28 (28-Pin PLCC) ................................................ 5-9S
FN/S-PQCC-J44 (44-Pin PLCC) .............................................. 5-100
FN/S-PQCC-J6S (6S-Pin PLCC) .............................................. 5-102
RJ/R-PQCC-J32 (32-Pin PLCC) .............................................. 5-104
Plastic Wide-Body Small-Outline Package (PDSO)
DW/R-PDSO-G16 (16-Pin SOIC) ............................................. 5-106
DW/R-PDSO-G20 (20-Pin SOIC) ............................................. 5-108
DW/R-PDSO-G24 (24-Pin SOIC) .............................................. 5-110
DW/R-PDSO-G28 (28-Pin SOIC) .............................................. 5-112
Plastic Small-Outline Package (PDSO)
DV/R-PDSO-G28 (28-Pin SOIC) .......................................•....... 5-114
Plastic Shrink Small-Outline Package (PDSO)
DLIR-PDSO-G56 (56-Pin SSOP) .............................................. 5-116
Plastic Quad Flatpack (PQFP)
PAGlS-PQFP-G64 (64-Pin TQFP) ............................................. 5-118
PCBlS-PQFP-G120 (120-Pin TQFP) .......................................... 5-120
PHlR-PQFP-GSO (SO-Pin TQFP) ....•........................................ 5-122
PM/S-PQFP-G64 (64-Pin TQFP) ............................................. 5-124
PN/S-PQFP-GSO (SO-Pin TQFP) .............................................. 5-126
PQ/S-PQFP-G132 (132-Pin TQFP) .................................... : ....... 5-12S
PZlS-PQFP-G100 (100-Pin TQFP) ............................................ 5-130
Section 6 - Device Models . ••••••••..•••...••...••......••..•••.•.•••• 6-1
VHDL Models ••.•••••••••••••.•••••••.•••••••••••••••••••••••.••......•••.••••.•.•.•• 6-3
Logic-Modeling Behavioral Models ••••••••••••••••••••••••••••.••...•.•.•••••••••..••• 6-5
Section 7 - Quality and Reliability Assurance •....•.••...•.••..•......• 7-1
Qualification of Products and Processes •••••••••••••••••••••••••••••••••••••••••••••.• 7-3
Introduction •••••••••••••••••••••••••..••••••••••••.••••.••••.••••.•.•••• , ••••.•••••• 7-5
Quality and Reliability Assurance In Integrated-Circuit Design ••••••••..••••••••••••.•••• 7-7
General Quality and Reliability Rules ............................................... 7-9
Process-Specific Design Rules ..................................................... 7-9
Methodology-Oriented Design Rules ............................................... 7-9
Change Control ............•..................................................... 7-'iJ
ix
Section 7 - Quality and Reliability Assurance (Continued) .............. 7-1
Quality and Reliability Monitoring ••••••••••.•••••••••••••••.•••••••.••••••••••••••••• 7-11
Environmental Laboratory •............•.....••....... ·...•........................ 7-13
Methods of Measuring Component Reliability ...•................................... 7-13
Failure-Rate Calculations for FIFO Products ........................................ 7-13
Qualification Data for FIFO Products ............................................... 7-13
Life-Test and ESD-Characterization Data ................................ , .... : ...... 7-14
x
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1-2
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
INTRODUCTION
These symbols, terms, and definitions are in accordance with those currently agreed upon by the JEDEC
Council ofthe Electronic Industries Association (EIA) for use in the USA and by the International Electrotechnical
Commission (IEC) for international use.
operating conditions and characteristics (in sequence by letter symbols)
Cj
Input capacitance
The internal capacitance at an input of the device
Co
Output capacitance
The internal capacitance at an output of the device
Cpd
Power dissipation capacitance
Used to determine the no-load dynamic power dissipation per logic function (see individual circuit pages):
Po = Cpd Vee2 f + Icc Vee·
f max
Maximum clock frequency
The highest rate at which the clock input of a bistable circuit can be driven through its required sequence
while maintaining stable transitions of logic level at the output with input conditions established that
should cause changes of output logic level in accordance with the specification
Icc
Supply current
The current into· the Vee supply terminal of an integrated circuit
~ICC
Supply current change
The increase in supply current for each input that is at one of the specified TTL voltage levels rather than
o or Vee
'CEX
Output high-leakage current
The maximum leakage current into the collector of the pulldown-output transistor when the output is high
and the output forcing condition Vo = 5.5 V
'I (hold)
Input-hold current
Input current that holds the input at the previous state when the driving device goes to a high-impedance
state
High-level input current
The current into· an input when a high-level voltage is applied to that input
Low-level Input current
The current into· an input when a low-level voltage is applied to that input
loff
Input/output power-off leakage current
The maximum leakage current int%ut of the input/output transistors when forcing the input/output to
4.5 V and Vee = 0
IOH
High-level output current
The current into· an output with input conditions applied that, according to the product speCification,
establishes a high level at the output
IOL
Low-level output current
The current into· an output with input conditions applied that, according to the product speCification,
establishes a low level at the output
'Current out of a terminal is given as a negative value.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-3
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
IOZ
RElJA
Off-state .(hlgh-Impedance-state) output current (of a 3-state output)
The current flowing into* an output having 3-state capability with input conditions established that,
according to the product specification, establishes the high-impedance state at the output
,
Junctlon-ta-ambient thermal resistance
The thermal resistance from the semiconductor junction(s) to the ambient
RElJC
Junctlon-to-case thermal resistance
The thermal resistance from the semiconductor junction(s) to a stated location on the case
ta
Access time
The time interval between the application of a specified input pulse and the availability of valid signals
at an output
tc
Clock cycle time
Clock cycle time is 1/fmax .
tcils
Disable time (of a 3-state or open-collector output)
The propagation time between the specified reference points on the input and output voltage waveforms
with the output changing from either of the defined active levels (high or low) to a high-impedance (off)
state
NOTE: For 3-state outputs, tdis = tpHZ or tpLZ. Open-collector outputs change only if they are low at the
time of disabling, so ~is =tpLH.
ten
Enable time (of a 3-state or open-collector output)
The propagation time between the specified reference pOints on the input and output voltage waveforms
with the output changing from a high-impedance (off) state to either of the defined active levels (high or
low)
NOTE: In the case of memories, this is the access time from an enable input (e.g., OE). For 3-state
outputs, ten = tpZH or tpZL. Open-collector outputs change only if they are responding to data
that would cause the output to go low, so ten = tpHL.
th
Hold time
The time interval during which a signal is retained at a specified input terminal after an active transition
occurs at another specified input terminal
NOTES: 1. The hold time is the actual time interval between two signal events and is determined by the
system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is to be expected.
2. The hold time may have a negative value, in which case, the minimum limit defines the
longest interval (between the release of the signal and the active tranSition) for which correct
operation of the digital circuit is to be expected.
tpd
Propagation delay time
The time between the specified reference pOints on the input and output voltage waveforms with the
output changing from one defined level (high or low) to the other defined level (tpd = tpHL or tpLH)
tpHL
Propagation delay time, hlgh-ta-Iow level output
The time between the specified reference pOints on the input and output voltage waveforms with the
output changing from the defined high level to the defined low level
tpHZ
Disable time (of a 3-state output) from high level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined high level to the high-impedance (off) state
·Current out of a terminal is given as a negative value.
~TEXAS
1-4
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
tpLH
Propagation delay time, low-to-hlgh level output
The time between the specified reference points on the input and output voltage waveforms with the
output changing from the defined low level to the defined high level
tpLZ
Disable time (of a a-state output) from low level
The time interval between the specified reference points on the input and the output voltage waveforms
with the 3-state output changing from the defined low level to the high-impedance (off) state
tpzH
Enable time (of a a-state output) to high level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined high level
tpzL
Enable time (of a a-state output) to low level
The time interval between the specified reference points on the input and output voltage waveforms with
the 3-state output changing from the high-impedance (off) state to the defined low level
tsu
Setup time
The time interval between the application of a signal at a specified input terminal and a subsequent active
transition at another specified input terminal
NOTES: 1. The setup time is the actual time interval between two signal events and is determined by
the system in which the digital circuit operates. A minimum value is specified that is the shortest
interval for which correct operation of the digital circuit is to be expected.
2. The setup time may have a negative value, in which case, the minimum limit defines the
longest interval (between the active transition and the application of the other signal) for which
correct operation of the digital circuit is to be expected.
tw
Pulse duration (width)
The time interval between specified reference points on the leading and trailing edges of the pulse
waveform
VIH
High-level Input voltage
An input voltage within the more positive (less negative) of the two ranges of values used to represent
the binary variables
NOTE: A minimum is specified that is the least-positive value of high-level input voltage for which
operation of the logic element within specification limits is to be expected.
VIL
Low-level input voltage
An input voltage within the less positive (more negative) of the two ranges of values used to represent
the binary variables
NOTE: A maximum is specified that is the most-positive value of low-level input voltage for which
operation of the logic element within specification limits is to be expected.
VOH
High-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a high level at the output
VOL
Low-level output voltage
The voltage at an output terminal with input conditions applied that, according to product specification,
establishes a low level at the butput
VIT+
Positive-going Input threshold level
The voltage level at a transition-operated input that causes operation of the logic element, according to
specification, as the input voltage rises from a level below the negative-going threshold voltage, VIT-
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-5
GLOSSARY
SYMBOLS, TERMS, AND DEFINITIONS
VIT_
Negative-going Input threshold level
The voltage level at a transition-operated input that causes operation of the logic element, according to
specification, as the input voltage falls from a level above the positive-going threshold voltage, VIT+
VOHV
High-level output voltage change during simultaneous switching
The minimum (valley) voltage induced on a quiescent high-level output during switching of other outputs
VOlP
Low-level output voltage change during simultaneous switching
The maximum (peak) voltage induced on a quiescent low-level output during switching of other outputs
definitions
asynchronous FIFO
Data writes are initiated by a low-level pulse on the write-enable input when the full flag Is not asserted. Likewise,
data reads are initiated by a low-level pulse on the read-enable input when the empty flag is not asserted. The
empty and full flags are not synchronized to a particular clock and reflect the instantaneous comparison of the
read and write pointers.
clocked FIFO
Data is written by a low-to-high transition of a write clock when write-enable inputs are asserted and the
input-ready flag is not asserted. Likewise,· data is read by a low-to-high transit!on of a read clock when
read-enable inputs are asserted and the output-ready flag is asserted. The input-ready flag is multistaged
synchronized to the write clock and the ouput-ready flag is multistaged synchronized to the read clock,
improving metastability.
strobed FIFO
Data is written on a low-to-high transition on the load-<:Iock input when the full flag is not asserted. Likewise, data
is read on a low-to-high transition on the unload-<:Iock input when the empty-flag is not asserted. The empty and
full flags are not synchronized to a particular clock and reflect the instantaneous comparison of the read and
write painters.
synchronous FIFO
The term synchronous refers to a port-control method and does not imply that data writes and reads must be
synchronous to one another. Data is written by a low-to-high transition of a write clock when write-enable inputs
are asserted and the full flag is not asserted. Likewise, data is r~ad by a low-to-high transition of a read clock
when read-enable inputs are asserted and the empty flag is not asserted. The empty flag is single-staged
synchronized to the read clock and the full flag is single-staged synchronized to the write clock.
~TEXAS
1-6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-1
...""D
·0
Co
c
2
o
<'
(I)
_.
;
~
2-2
FIFO Product Offerings
Page
Advanced Clocked FIFOs .•.........................................................
Advanced Strobed FIFOs ...........................................................
Advanced Application-Specific Clocked FIFOs .........................................
Advanced Application-Specific FIFO Features .........................................
Synchronous Mature FIFOs .........................................................
Asynchronous Mature FIFOs ...................................•....................
FIFO Functionality .................................................................
2-5
2-5
2-6
2-6
2-6
2-7
2-8
2-3
2-4
PRODUCT OVERVIEW
FIFO PRODUCT OFFERINGS
Advanced Clocked FIFOs
DEVICE
ORGANIZATION
SPEED SORT
to (ns)
MAXIMUM
FREQUENCY ACCESS
TIME (ns)
(MHz)
IOH/lOL
(mA)
PACKAGE
PITCH
(mm)
AREA
(mm2)
SN74ACT7884
SN74ACT7882
SN74ACT7881
4K x 18
2K x 18
1K x 18
-15, -20,-30
67,50,33
11,13,18
8/16
8o-pin TQFP (PN)
68-pin PLCC (FN)
0.5
1.27
196
310
SN74ACT7811
1K x 18
-15, -18, -20,
-25
40, 35, 29, 17
15,18,
20,25
8/16
8o-pin TQFP (PN)
68-pin PLCC (FN)
0.5
1.27
196
310
SN74ACT7803
SN74ACT7805
SN74ACT7813
512 x 18
256 x 18
64 x 18
-15,-20,-25,
-40
67,50,40,30
12,13,
15,20
8116
56-pin SSOP (OL)
0.635
191
SN74ACT7807
2K x 9
-15, -20, -25,
-40
67,50,40,25
12,13,
18,25
8/16
64-pin TQFP (PM/PAG)
44-pin PLCC (FN)
0.5
1.27
144
310
SN74ABT7819
512 x 18 x 2
-12, -15, -20,
-30
80,67,50,33
9,10,12,
14
12124
8o-pin TQFP (PN)
80-pin PQFP (PH)
0.5
0.8
196
432
512 x 18
256 x 18
64 x 18
-20, -25,-40
25,40,50
13,15,20
8/16
56-pin SSOP (OL)
0.635
191
PITCH
(mm)
AREA
(mm2)
SN74ALVC7803
SN74ALVC7805
SN74ALVC7813
Advanced Strobed FIFOs
MAXIMUM
FREQUENCY ACCESS IOH/lOL
TIME (ns)
(mA)
(MHz)
ORGANIZATION
SPEED SORT
SN74ACT7802
1K x 18
-25, -40, -60
40,25,17
30,35,45
8116
80-pin TQFP (PN)
68-pin PLCC (FN)
0.5
1.27
196
635
SN74ACT2235
SN74ACT2236
1K x 9 x 2
-20, -30, -40,
-60
50,33,25,17
25,25,
35,45
8/16
64-pin TQFP (PM/PAG)
44-pin PLCC (FN)
0.5
1.27
144
310
SN74ACT7804
SN74ACT7806
SN74ACT7814
512 x 18
256 x 18
64 x 18
-20, -25, -40
50,40,25
15,18,20
8/16
56-pin SSOP (OL)
0.635
191
SN74ACT7808
2K x 9
-20, -25, -30,
-40
50,40,33,25
15,18,
20,22
8116
64-pin TOFP (PM/PAG)
44-pin PLCC (FN)
0.5
1.27
196
635
SN74ABT7820
512 x 18 x 2
-15,-20,-25,
-40
67,50,40,33
12,14,
15, 17
12124
80-pin TQFP (PN)
8o-pin PQFP (PH)
0.5
0.8
196
432
512 x 18
256 x 18
64 x 18
-20, -25,-40
25,40,50
13,15,20
8/16
56-pin SSOP (OL)
0.635
191
DEVICE
SN74ALVC7804
SN74ALVC7806
SN74ALVC7814
to (ns)
PACKAGE
~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
2-5
PRODUCT OVERVIEW
FIFO PRODUCT OFFERINGS
Advanced Appllcatlon-8peclflc Clocked FIFOs
DEVICE
ORGANIZATION
SPEED SORT
(ns)
to
MAXIMUM
FREQUENCY
(MHz)
ACCESS
TIME (ns)
IOH/IOL
(mA)
PACKAGE
PITCH
(mm)
AREA
(mrn2)
165
SN74ACT2226
SN74ACT2228
64 x 1
256 x 1
22
20
8/16
24-pin SOIC (OW)
1.27
SN74ACT2227
SN74ACT2229
64 x 1
256 x 1
60
9
8/16
28-pin SOIC (OW)
1.27
192
0.4
0.635
256
781
SN74ACT3638
512 x 32 x 2
-15.-20. -30
67.50.33
11.13.15
4/8
12O-pin TQFP (PCB)
132-p1n PQFP (PQ)
SN74ACT3622
SN74ACT3632
SN74ACT3642
256x36x2
512 x 36 x 2
1K x 36 x 2
-15.-20.-30
67.50.33
11.13.15
4/8
12D-pin TQFP (PCB)
132-pin PQFP (PQ)
0.4
0.635
256
781
SN74ACT3631
SN74ACT3641
SN74ACT3651
512 x 36
1K x 36
2K x 36
-15.-20.-30
67.50.33
11.13.15
4/8
120-pin TQFP (PCB)
132-p1n PQFP (PQ)
0.4
0.635
256
781
SN74ABT3611
SN74ABT3613
64 x 36
64 x 36
-15. -20. -30
67.50.33
10.12.15
4/8
12D-pin TQFP (PCB)
132-pin PQFP (PQ)
0.4
0.635
256
781
SN74ABT3612
SN74ABT3614
64x36x2
64x36x2
-15.-20.-30
67.50.33
10.12.15
418
120-pin TQFP (PCB)
132-pin PQFP (PQ)
0.4
0.635
256
781
:
Advllnced Application-Specific FIFO Features
TELECOMMUNICATIONS FIFOs
SN74ACT2226
SN74ACT2228
SN74ACT2227
SN74ACT2229
Ouallndependent FIFO with separate output enables. separate 1/0. separate
resets. characterized to industrial temperature specification: -40·C to 85·C
DIGITAL-SIGNAL-PROCESSING FIFOs
SN74ACT3638
SN74ACT3631
SN74ACT3641
SN74ACT3651
Microprocessor interface-controllogic. synchronous retransmit capability.
mailbox-bypass registers for each FIFO
SN74ACT3622
SN74ACT3632
SN74ACT3642
Microprocessor interface-controllogic. mailbox-bypass registers for each FI FO
HIGH-BANDWIDTH COMPUTING FIFOs
SN74ABT3611
SN74ABT3612
Microprocessor interface-controllogic. parity generation and parity check.
mailbox-bypass registers for each FIFO
INTERNETWORKING FIFOs
SN74ABT3613
SN74ABT3614
Microprocessor interface-controllogic. parity generation and parity check. bus
matching and byte swapping. mallbox-bypass registers for each FIFO
Synchronous Mature FIFOs
DEVICE
SN74ACT72211L
SN74ACT72221L
SN74ACT72231 L
SN74ACT72241 L
ORGANIZATION
,
512 x
1K x
2K x
4K x
9
9
9
9
SPEED SORT
(n8)
MAXIMUM
FREQUENCY
(MHz)
ACCESS
TIME (n8)
-15. -20. -25.
-50
67. 50. 40. 20
10.12.
15.25
to
~1ExAs
2-6
INSTRUMENTS'
POST OFFICE eox 665303 • DALlAS. TEXAS 75266
PACKAGE
32-pin PLCC (RJ)
PRODUCT OVERVIEW
FIFO PRODUCT OFFERINGS
Asynchronous Mature FIFOs
DEVICE
SN74ACT7200L
SN74ACT7201 LA
SN74ACT7202LA
SN74ACT7203L
SN74ACT7204L
ORGANIZATION
SPEED SORT
tc (ns)
MAXIMUM
FREQUENCY ACCESS
TIME (ns)
(MHz)
256 x 9
-15,-25,-50
67,40,20
10,12,20
512x9,1Kx9
-15,-25,-35,
-50
67,50,40,20
10,12,
15,25
-15, -25, -50
67,40,20
10,12,20
2K x 9
4K x 9
PACKAGE
28-pin DIP (NP)
28-pin SOIC (DV)
32-pin PLCC (RJ)
SN74ACT7205L
8K x 9
-15,-25,-50
67,40,20
10,12,20 28-pin DIP (NP)
SN74ACT7206
16K x 9
-15,-25,-50
67,40,20
10,12,20 32-pin PLCC (RJ)
SN74ALS2238
32x9x2
40
40-pin DIP (N)
44-pin PLCC (FN)
SN74ALS2233A
64 x 9
40
28-pin DIP (N)
44-pin PLCC (FN)
SN74ALS2232A
64 x 8
40
24-pin DIP (NT)
28-pin PLCC (FN)
SN74ALS235
64 x 5
25
20-pin DIP (N)
20-pin SOIC (DW)
SN74ALS233
16 x 5
30
20-pin DIP (N)
20-pin SOIC (DW)
SN74ALS232B
16 x 4
30
16-pin DIP (N)
16-pin SOIC (DW)
20-pin PLCC (FN)
SN74ALS229B
16 x 5
30
20-pin PLCC (FN)
20-pin DIP (N)
20-pin SOIC (DW)
SN74S225
16 x 5
10
20-pin DIP (N)
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-7
FIFO Functionality
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64
1
20
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SW4ACT2227
64
1
9
til
SN74ACT2226
256
1
20
r/
SN74ACT2229
256
1
9
r/
r/
SN74ALS232
16
4
23
r/
r/
SN74ALS234
64
4
17
r/
r/
r/
SN74ALS236
64
4
17
r/
r/
r/
SN74ALS229
16
5
30
r/
r/
SN74ALS233
16
5
30
r/
r/
SN74S225
16
5
75
r/
r/
r/
SN74ALS235
64
5
17
r/
r/
r/
SN74Al.S2232
64
8
26
r/
r/
SN74ALS2238
32
9
33
r/
r/
SN74ALS2233
64
9
26
r/
r/
SN74ACT7200.
256
9
15
r/
SN74ACT72211
512
9
10
r/
SN74ACT7201
512
9
15
r/
SN74ACT72221
1K
9
10
r/
SN74ACT2235
1K
9
25
r/
r/
r/
r/
i
SN74ACT2236
lK
9
25
r/
r/
r/
r/
i
SN74ACT7202
1K
9
15
SN74ACT7807
2K
9
12
SN74ACT72231
2K
9
10
SN74ACT7806
2K
9
15
SN74ACT7203
2K
9
SN74ACT72241
4K
9
SN74ACT7204
4K
9
15
r/
r/
r/
SN74ACT7205
8K
9
15
r/
r/
r/
SN74ACT7206
16K
9
15
SN74ACT7813
64
18
12
r/
r/
!
i
r/
r/
I
r/
r/
r/
r/
r/
r/
r/
r/
r/
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r/
r/
r/
r/
r/
15
r/
r/
10
r/
r/
I
r/
I
r/
i
r/
r/
r/
r/
r/
r/
r/
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r/
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- -
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FIFO Functionality (Continued)
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64
18
13
t/
t/
SN74ACT7814
64
18
15
t/
t/
SN74ALVC7814
64
18
18
t/
t/
SN74ACT7805
258
18
12
t/
t/
t/
SN74ALVC7805
258
18
13
t/
t/
t/
SN74ACT7806
258
18
15
t/
t/
SN74ALVC7806
258
18
18
t/
t/
SN74ACT7803
512
18
12
t/
t/
t/
SN74ALVC7803
512
18
13
t/
t/
t/
SN74ACT7804
512
18
15
t/
t/
SN74ALVC7804
512
18
18
t/
t/
SN74ABT7819
512
18
9
t/
t/
SN74ABT7820
512
18
12
t/
t/
SN74ACT7881
lK
18
11
t/
t/
t/
t/
SN74ACT7811
lK
18
15
t/
,;
t/
t/
SN74ACT7802
lK
18
30
t/
t/
SN74ACT7882
2K
18
11
t/
t/
t/
t/
SN74ACT7884
4K
18
11
t/
t/
t/
t/
SN74AC753881
4K
18
11
t/
,;
t/
SN74ACT3638
512
32
11
,;
,;
SN74ABT3611
64
36
10
t/
SN74ABT3613
64
36
10
t/
SN74ABT3612
64
36
10
t/
t/
SN74ABT3614
64
36
10
t/
SN74ACT3622
256
36
11
t/
t/
SN74ACT3631
512
36
11
t/
t/
SN74ACT3632
512
36
11
t/
t/
SN74ACT3641
lK
36
11
t/
t/
SN74ACT3642
lK
36
11
t/
t/
SN74ACT3651
2K
36
11
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t/
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2-10
FIFO Selection Flow Chart
2-11
2-12
PRODUCT OVERVIEW
FIFO SELECTION FLOW CHART
This chart can be used to select the appropriate strobed or clocked FI FO for the application based on the desired FI FO
width.
Which FIFO?
Require More Than One
9-Blt FIFO (Cascading)?
Y
N
Faster Than 33 MHz?
N
Y
N
Faster Than 33 MHz?
N
Y
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-13
2-14
3-1
tn
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(1)
(')
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_.
---
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3-2
FIFO Performance and Reliability
Page
Metastability Performance of Clocked FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-5
FIFO Memories: Solution to Reduce FIFO Metastability ................................ 3-17
Simultaneous-Switching Noise Analysis for Texas Instruments FIFO Products ............ 3-23
FIFO Solutions for Increasing Clock Rates and Data Widths ............................ 3-41
3-3
Metastability Performance
of Clocked FIFOs
First-In, First-Out Technology
Chris Wellheuser
Advanced System Logic - Semiconductor Group
~TEXAS
INSTRUMENTS
SCZAOO4A
IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to its products or to discontinue any
. semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications',).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant orrepresent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-6
Contents
Title
Page
Introduction .............................................................................. 3-9
Metastability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-9
TI Clocked FIFOs ........................................................................ 3-11
Test Setup for Measuring FIFO Flag Metastability ................. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-12
Test Results .............................................................................. 3-14
MTBF Comparisons ...................................................................... 3-15
Conclusion .............................................................................. 3-16
References ............................................................................... 3-16
3-7
3-8
Introduction
This report is intended to help the user understand more clearly the issues relating to the metastable performance of Texas
Instruments (TI) clocked FIFOs in asynchronous-system applications. It discusses basic metastable-operation theory,
shows the equations used to calculate metastable failure rates for one and two stages of synchronization, and describes
the approach TI has used for synchronizing the status flags on its series of clocked FIFOs. Additionally, a test setup for
measuring the failure rate of a device to determine its metastability parameters is shown and results are given for both
an advanced BiCMOS (ABT) FIFO and an advanced CMOS (ACT) FIFO. Using these parameters, calculations of
MTBF under varying conditions are performed.
Metastability
Metastability in digital systems occurs when two asynchronous signals combine in such a way that their resulting output
goes to an indeterminate state. A common example is the case of data violating the setup and hold specifications of a
latch or a flip-flop. In a synchronous system, the data always has a fixed relationship with respect to the clock. When
that relationship obeys the setup and hold requirements for the device, the output goes to a valid state within its specified
propagation delay time. However, in an asynchronous system, the relationship between data and clock is not fixed;
therefore, occasional violations of setup and hold times can occur. When this happens, the output may go to an
intermediate level between its two valid states and remain there for an indefinite amount of time before resolving itself
or it may simply be delayed before making a normal transition 1. In either case, a metastable event has occurred.
Metastable events can occur in a system without causing a problem, so it is necessary to define what constitutes a failure
before attempting to calculate a failure rate. For a simple CMOS latch, as shown in Figure I, valid data must be present
on the input for a specified period of time before the clock signal arrives (setup time) and must remain valid for a
specified period of time after the clock transition (hold time) to assure that the output functions predictably. This leaves
a small window of time with respect to the clock (to) during which the data is not allowed to change. If a data edge occurs
within this aperture, the output may go to an intermediate level and remain there for an indefinite amount of time before
resolving itself either high or low, as illustrated in Figure 2. This metastable event can cause a failure only if the output
has not resolved itself by the time that it must be valid for use (for example, as an input to another stage); therefore, the
amount of resolve time allowed a device plays a large role in calculating its failure rate.
Data - - - - - - - 1
Input
....
.x)---~I------
Clock - - - - - - - - '
Figure 1. A Simple CMOS Latch
* 1,...---------j4-- tsu -+I
Clock
~·tw-~
I
j4-
1
Data
Input
Output
1
-----'. 1
I
th--l
I
I1414---- tr
I
~I
I
_______~I____~I____~/~--------~i(r------
Figure 2. Output at Intermediate Level Due to Data Edge Within to Aperture
Output
The probability of a metastable state persisting longer than a time, tr. decreases exponentially as 11: increases2. This
relationship canbe characterized by equation 1:
.
f
-
(r) -
e( - tr/t)
(1)
where the function f(r) is the probability of nonresolution as a function of resolve time allowed, tr. and the circuit time
constant t (which has also been shown to be inversely proportional to the gain-bandwidth product of the circuit)3,4.
For a single-stage synchronizer with a given clock frequency and an asynchronous data edge that has a uniform
probability density within the clock period, the rate of generation of metastable events can be calculated by taking the
ratio of the setup and hold time window previously described to the time between clock edges and multiplying by the
data edge frequency. This generation rate of metastable events coupled with the probability of nonresolution of an event
as a function of the time allowed for resolution gives the failure rate for that set of conditions. The inverse of the failure
rate is the mean time between failure (MTBF) of the device and is calculated with the formula shown in equation 2:
failure rate
(2)
Where:
11:
t
- resolve time allowed in excess of the normal propagation delay time of the device
- metastability time constant for a fJip-flop
to - a constant related to the width of the time window or aperture wherein a data edge
triggers a metastable event
fc - clock frequency
fd
asynchronous data edge frequency
The parameters to and t are constants that are related to the electrical characteristics of the device in question. The
simplest way to determine their values is to measure the failure rate of the device under specified conditions and solve
for them directly. If the failure rate of a device is measured at different resolve times and plotted, the result is an
exponentially decaying curve. When plotted on a semilogarithmic scale, this becomes a straight line the slope of which
is equal to t; therefore, two data points on the line are sufficient to calculate the value of t using equation 3:
tr2 - trl
t
= In(Nl/N2)
(3)
Where:
11:1 - resolve time 1
11:2 - resolve time 2
Nl - number of failures relative to 11:1
N2 - number of failures relative to 11:2
Mter determining the value for t, to may be solved for directly.
The formula for calculating the MTBF of a two-stage synchronizer, equation 4, is merely an extension of equation 2:
(4)
Where:
11:1 - resolve time allowed for the fIrst stage of the synchronizer
11:2 - resolve time allowed in excess of the normal propagation delay
fco fd, t, and to are as previously defmed, with t and to assumed to be the same for both stages.
3--10
The first tenn calculates the MTBF of the fust stage of the synchronizer, which in effect becomes the generation rate
of metastable events for the next stage. The second tenn then calculates the probability that the metastable event will
be resolved based on the value ofta, the resolve time allowed external to the synchronizer. The product of the two tenns
gives the overall MTBF for the two-stage synchronizer.
TI Clocked FIFOs
The TI clocked FIFOs are designed to reduce the occurrence of metastable errors due to asynchronous operation. This
is achieved through the use of two- and three-stage synchronizing circuits that generate the status-flag outputs input
ready (IR) and output ready (OR). In a typical application, words may be written to and then read from the FIFO at
varying rates independent of one another, resulting in asynchronous flag-signal generation (internally) at the boundary
conditions of full and empty; for example, the operation when the FIFO is at the full boundary condition with writes
taking place faster than and asynchronous to reads. The IR flag is low, signifying that the FIFO is full and can accept
no more words. When a read occurs, the FIFO is no longer completely full. This causes an internal flag signal to go high,
allowing another write to take place. Since the exit from the full state happens asynchronously to the write clock
(WRTCLK) of the FIFO, this flag is not useful as a system write-enable signal. The solution is to synchronize this
internal flag to the write clock through two D-type flip-flop stages and output this synchronized signal as the IR flag
(see Figure 3). The OR status flag is generated in a similar manner at the empty boundary condition and is synchronized
to the read clock through a three-stage synchronizing circuit.
Internal
Asynchronous
Flag Signal
IR
CLK
Internal Logic Delay
CLK
WRTCLK----~--------------------------------------~
Figure 3. IR-Flag Synchronizer
The remainder of this report pertains to the metastability perfonnance of the two-stage IR synchronizer, which is the
limiting case of the two in tenns of MTBF characteristics. The internal flag signal that goes high on a read and low on
a write is synchronized to the write clock through two D-type flip-flop stages. Since this results in the IR flag status of
the FIFO being delayed for two clock cycles, a predictive circuit is used to clock the status into the synchronizer at (full
minus two) words so that the action of the IR flag going low coincides with the actual full status of the FIFO. However,
once the FIFO is full and IR is low, a read that causes the internal flag to go high is not reflected in the status of the IR
flag until two write clocks occur.
With the FIFO full and the IR flag low, a read causes the internal flag signal to go high. This signal is clocked into the
ftrSt stage of the two-stage synchronizer on the next write clock. Because these two signals are asynchronous to one
another, the potential for the output of the first stage of the synchronizer to go to a metastable state exists. If this condition
persists until the next write clock rising edge, a metastable condition could be generated in the second stage and reflected
on the IR flag output. This metastable condition manifests itself as a delay in propagation time and is considered a failure
only if it exceeds the maximum delay allowed in a design.
The effectiveness of the two-stage synchronizer becomes apparent when attempting to generate failures at a rate high
enough to count in a reasonable period of time. A metastable event generated in the ftrSt stage must persist until the next
write clock, i.e., when that data is transferred to the second stage. The resolve time for the first stage is governed by the
frequency or period of the write clock. At slower frequencies, the failure rate of the first stage is very low, resulting in
a low metastable generation rate to the second stage. The second stage of the synchronizer further reduces the probability
of a metastable failure based on the resolve time allowed at the output. The overall failure rate of the device may be
affected by increasing the initial asynchronous data generation rate (adding jitter to the data centered about the setup
and hold window), by decreasing the resolve time of the first stage (increasing the write clock frequency), and by
reducing the external resolve time at the output.
3-11
Test Setup for Measuring FIFO Flag Metastability
The failure rate of a device is measured on a test fixture as shown in Figure 4. The input waveforms used on this setup
are also shown in Figure 4. Rising data is jittered asyilchronously about the setup and hold aperture of the device under
test (DUT) in a ±400-ps window with respect to the device clock (CLK). The output of the OUT is then clocked into
two separate flip-flops, FFI and FF2, by two different clock signals, CLKI and CLK2. The resolve time, tp is set by
the relationship between CLKI and CLK and is measured as the delta between the normal output transition time and
the rising edge ofCLKl minus the setup time required for FFl. CLK2 occurs long enough afterCLKl to allow sufficient
time for the OUT to have resolved itself to a valid state. The outputs ofFFI and FF2 are compared by the exclusive OR
gate, the output state of which is latched intoFF3 by CLK3. When a metastable failure occurs, the output ofthe exclusive
OR gate goes high caused by FFl and FF2 having opposite data due to the OUT not having resolved itself by time tr.
On the next cycle, low data is clocked into the OUT and FFl and FF2 in order to reset the status latch, FF3. Failures
are counted for different resolve times, and t is then calculated using equation 3.
Using the test setup in Figure 4, failure rates are measured for both an SN74ABT7819, 512x 18 x 2 clocked FIFO, and
an SN74ACT7807, 2K x 9 clOCked FIFO. The device is initially written full to set IR low at the boundary condition.
A read clock is generated to send the internal flag high, and ajitter signal is superimposed on it to sweep asynchronously
with respect to the write clock in an 800-ps-wide envelope and centered such that the IR flag goes high alternately on
the second and third write clocks. The nominal write-clock frequency of the test setup is 40 MHz, but to increase the
failure rate to an observable level, a pulse is injected into the write-clock stream just after the read clock occurs such
that the first and second write clocks (the ones that clock the status through the synchronizer) are only 5.24 ns apart. This
increases the effective write clock frequency to 191 MHz, reducing the resolve time allowed in the first stage and
increasing the failure rate.
This test setup and these actions together create the.necessary conditions to generate a metastable occurrence on the IR
output that is seen after the second write clock and manifests itself as a delay in propagation time. In this instance, the
write clock is the syilchronizing clock and·the read clock generates the asyilchronous internal data signal. CLKI is
adjusted to vary the external resolve time, ta, and the resulting failure rates are recorded (see Table 1).
3-12
RClK
DUT
(FIFO)
ClK
D
Q
ClK
ClK
FF1
FF2
ClK1
ClK2
ClK3
...-----Jltter
RDClK
(data)
WRTClK
(clock)
Metastable Event
IR (out)
//II 7 X' __\..10--.__
i
I
ClK1
ClK2
load FF1
Reset FF1
___________.~_~~~~~
_____~r_l.-
_______
_ ____'r_l.-
load FF2
Reset FF2
---'nL.-~
__________________ __
load FF3
ClK3
~n~~
Reset FF3
~~
Figure 4. Metastable Event Counter and Input Waveforms
3-13
Test Results
Table 1. SN74ABT7819 Failure Ratest
RESOLVE TIME,
tr2 (ns)
NUMBER OF
FAILURESIHOUR
NUMBER OF
FAILURES/SECOND
MTBF
(seconds)
0.27
890
0.2472
4.04
0.39
609
0.1692
S.91
0.53
396
0.1101
9.08
t VCC = 4.S V. TA = 2SoC
After measuring the metastable performance of the SN74ABTI819, some assumptions must be made to calculate the
parameters't and to. Because the individual flip-flops comprising the two-stage synchronizer cannot be measured
separately, it is first assumed that the values fon and to are the same for both. This is a safe assumption, as these constants
are driven by the process technology and because the schematics are identical. The other assumption made involves
determining the resolve time allowed in the first stage of the synchronizer. The clock period is set at 5.24 ns, but the delay
through the flip-flop and the setup time to the next stage must be subtracted from the clock period to arrive at the true
resolve time (tel)' These values could not be measured directly and were, therefore, estimated from SPICE analysis to
be 1.3 ns.
Using equation 4 and the measured failure rates to calculate't results in a value of 0.33 ns for the conditions given. The
following values from the test setup must be used to solve for to:
Where:
tel
ta
-
3.94 ns (5.24-ns clock period - 1.3-ns setup and delay time)
= 0.27 ns (set externally at IR output by CLK1)
fc
fd
MTBFl -
40MHz
125 MHz (4-MHz input adjusted by 25/0.8 jitter ratio)
4.04 s
Substituting these values into equation 4 and solving for to yields a value of 16.9 ps.
Table 2 summarizes the results for the SN74ABTI819 and SN74ACTI807 clocked FIFOs. An internal setup and delay
time of 1.8 ns was assumed for the SN7 4ACTI807.
Table 2. Values of 't and to for SN74ABT7819 and SN74ACT7807
TA
2SoC
vcc
SN74ABT7819
~
(ns)
to (ps)
SN74ACT7807
~
(ns)
to (ps)
4.SV
0.33
16.9
O.SO
1.13
SV
0.30
7
0.40
2.0S
S.SV
0.23
28.8
0.30
9.40
These numbers indicate the performance of only a few devices and are not intended to represent a fully characterized
parameter. However, they should be valid for the purpose of relative performance comparisons, and the values do fall
within the expected range given the circuit configuration and process technology in which the devices are fabricated.
3-14
MTBF Comparisons
With the constants t and to now known, calculations of the MTBF of the device under different operating conditions
may be performed. First, however, consider an example of the metastability performance of a single-stage synchronizer
using equation 1 and the circuit constants t and to from Table 2. Assume an application running with a 33-MHz write
clock, an S-MHz read clock, a 9-ns maximum propagation delay time for the IR path, and a 5-ns setup time for IR to
the next device. Therefore:
tr = 16 ns (30-ns clock period - 9-ns propagation delay - 5-ns tsu)
fc = 33 MHz
fd - SMHz
Using equation 2 to calculate the MTBF gives 2.55 y 1017 seconds or a little bit more than S billion years.
The reliability of a one-stage synchronizer degrades as operating frequency increases. With a 50-MHz write clock, a
12-MHz read clock, a 9-ns maximum delay, and a 5-ns setup time:
tr - 6 ns (20-ns clock period - 9-ns propagation delay - 5-ns tsu)
fc - 50MHz
fd - 12MHz
Substituting these values into equation 2 yields an MTBF of about 2 hours. This performance is unacceptable, even with
a device fabricated in the O.S-mm BiCMOS process, which is more resistant to metastability than other processes.
The benefits of two-stage synchronization become evident with the next example. Using the conditions stated in the last
example:
tr1
IS.7 ns (20-ns clock period - 1.3-ns setup and delay time)
6 ns (20-ns clock period - 9-ns propagation delay - 5-ns tsu)
fc - 50MHz
fd - 12MHz
tr2
Using equation 4 to calculate the MTBF gives 3.16 y 1028 seconds or 1.00 y 1021 years.
Table 3 gives a performance summary of both one- and two-stage synchronizing solutions under different conditions.
Table 3. MTBF Comparlsonst
CONDITIONS
fe=33 MHz. fd=8MHz
fe=40 MHz. fd-10MHz
ACT 1 STAGE
8400 years
ABT1 STAGE
8.1 x 109 years
92 days
1400 years
ACT 2 STAGE
2.62 x 1028 years
3.S6 x 1019 years
2 hours
4.90 x 1010 years
fe= SO MHz. fd=12MHz
fe= 67 MHz. fd = 16 MHz
fe= 80 MHz. fd=20 MHz
417 years
ABT 2 STAGE
4.77 x 1047 years
2.18 x 1034 years
1.00 x 1021 years
1.28 x 109 years
2900 years
t Assumptions for the MTSF comparisons:
- The values for to and t are those given previously for both the AST and ACT devices with VCC- 4.S V. TA _ 2SoC.
- Flag propagation delay time (IR or OR) is assumed to be 9 ns.
-Setup times to the next device are S ns (up to SD-MHz operation). 4 ns (up to 67-MHz operation). and 3 ns (up
to 80-MHz operation).
3-1S
Conclusion
Metastability failures must be accounted for in the design of asynchronous digital circuits. These failures become
increasingly prevalent at higher operating frequencies. When higher frequencies are used, extreme care must be taken
to ensure that system reliability is not adversely affected due to inadequate synchronization methods.
ClockedFlFOs from 11 provide a solution to this problem by synchronizing the boundary flags with at least two flip-flop
stages to improve the metastable MTBF over one-stage synchronization. This architecture allows designers to utilize
the high-throughput performance of the memory without endangering the reliability of their end products.
References
1.
J. Horstmann, H. Eichel, and R. Coates, "Metastability Behavior of CMOS ASIC Flip-Flops in Theory and Test,"
p. 146, IEEE Journal of Solid State Circuits, February 1989.
2.
H. Veendrick, "The Behavior of Flip-Flops Used as Synchronizers and Prediction of Their Failure Rate," p. 169,
IEEE Journal of Solid State Circuits, April 1980.
3.
S. T. Flannagan, "Synchronization Reliability in CMOS Technology," p. 880, IEEE Journal of Solid State Circuits,
August 1985.
4.
T. Kacprzak and A. Albicki, "Analysis of Metastable Operation in RS CMOS Flip-Flops," p. 59, IEEE Journal of
Solid State Circuits, February 1987.
5.
L. Kleeman and A. Cantoni, "Metastable Behavior in Digital Systems," p. 4, IEEE Design and Test of Computers,
December 1987.
3-16
FIFO Memories:
Solution to Reduce FIFO Metastability
First-In, First-Out Technology
Tom Jackson
Advanced System Logic - Semiconductor Group
~TEXAS
.INSTRUMENTS
SCAA011A
3-17
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is uriderstood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance; customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-18
As system operating frequencies continue to increase in excess of 33 MHz, designers must begin to address the issues
of overall system reliability due to increased chance of a metastable event occurring. A metastable event is defined as
the time period when the output of a logic device is neither at a logic high nor at a logic low but rather in an indeterminate
level. The chancel of a metastable occurrence is exponentially increased if single-stage synchronization is employed, as
in the case of the '722xx synchronous-style devices versus the two-stage synchronization that is implemented by
Texas InstrumentS (11) (see Figure 1). The following information assists designers in understanding and improving
upon the metastable characteristics of '722xx synchronous-style devices and their reliability.
-
1.00E+67
1.00E+52
1.00E+47
,- ••
1.00E+42
1.00E+37
II)
1.00E+32
...
1~OOE+27
:Ii
1.00E+22
I
CD
....
.'"
0
1.00E+17
1.00E+12
0
1.00E+07
1.00E+02
o
.I'
o
10
20
30
40
60
Two-Stage Synchronization
On.Stage Synchronization
I
u
1.00E-43
1.00E-48
•
080
70
Frequency - MHz
Figure 1. MTBF for Metastability as a Function of Frequency
Metastability may occur when using a FIFO to synchronize two digital signals operating at different frequencies. This
type of application is a familiar one to many design engineers. Triggering a metastable event is common in single-stage
(single flip-flop) synchronized FIFOs that are used to synchronize different clock signals (see Figure 2). With this
method, the asynchronous input might change states too close to the clock transition, violating the flip-flop's setup and
hold times. This causes an increase in resolve time (tc) which then results in an overall increase in propagation
delay (tpd)' Once a metastable event is triggered, the probability of the output recovering to a high or low level increases
exponentially with the increased resolve time. The expected time until the output of a single flip-flop with asynchronous
data has a metastable event is described by the mean time between failure (MTBF) equation (see equation 1). The first
term of the equation is the probability that the asynchronous data will trigger a metastable event. The second term is the
data rate. The third and fmal term is the probability of the metastable event recovering given the resolve time. A linear
increase in resolve time exponentially increases the MTBF of a metastable event.
3-19
Clock
Asynchronoua
Flag
Clock
D
/
tau
I
I
I
t
:::;!~
f/)
Asynchronous
Flag
Synchronized
Flag
Synchronized
Flag
Q
~
tpd
\
r
{
~tr--t/
Figure 2. Single-Stage Synchronizer
MTBFl = _1_ x .1 x exp(!t)
tofe fd
't
(1)
Where:
to tr -
flip-flop constant representing the time window during which changing data invokes a failure
resolve time allowed in excess of the normal propagation delay
't - flip-flop constant related to the settling time of a metastable event
fc
clock frequency
fd - asynchronous data frequency (for OR-flag analysis, it is the frequency at which data is written to
empty memory; for IR-flag analysis, it is the frequency at which data is read from full memory).
11 has increased the metastable MTBF by several orders of magnitude over single-stage synchronization with its
advanced FIFO family by employing two-stage synchronization (see Figure 3). The output of the first flip-flop is clocked
into the second flip-flop on the next clock cycle. For the output of the second stage to become metastable, the first stage
must have a metastable event that lasts long enough to encroach upon the setup time of the second stage. The addition
of the second flip-flop to the single-stage synchronizer allows the flip-flops more time to resolve any metastable output.
This is statistically equivalent to increasing its resolve time by the clock period minus its propagation delay. MTBF for
a two-stage synchronizer is given in equation 2. All terms, except for the third one, are the same as in equation 1. The
third term represents the additional propagation delay through the added flip-flop.
[t -~]
1
1
(tr)
MTBF
.
2 = -x-xexp
- - xexptofe fd
't
't
tpd
MTBF2 Where:
3-20
propagation delay through the first flip-flop
MTBFI
(2)
Q
Clock
Aaynchronous
Flag
Clock
Asynchronous
Flag
First Stage
;:@~
----~£
I
Synchronized
Flag
Synchronized
Flag
D
D
I
---I
Q
''--___r
''--___I
{
/
~------~
I
-. tpd If- tr --It
f7///////////$d
!
High or Low (does not mattar)
Figure 3. Two-Stage Synchronizer
The functional block diagram in Figure 4 illustrates the connections necessary to add the second-stage synchronization
to the '72211 synchronous FIFO. A quick and inexpensive schematic to resolve metastability of a synchronous FIFO
is shown in Figure 5. In this case, the FIFO is the '72211U and, by implementing a single TI SN74F74 D-type
positive-edge-triggered flip-flop and a TI SN74F08 two-input positive AND gate, the metastability characteristics of
this circuit can be dramatically improved. The TI SN74F74 acts as the second stage for this circuit, increasing the resolve
time as described in the previous paragraphs. The TI SN74F08 is implemented to act as the control-empty and
control-full flags to the receiving device. These control lines of the first-stage and second-stage synchronized flags are
then ANDed together to create the control flags (control empty and control full). The control lines are essentially read
enables that ensure the synchronization of the device. As is shown in the logic diagram and truth table, synchronization
is complete only when the empty flags (EF) of both the second stage (truth table input A) and the device (truth table input
B) are high. The empty flag is used for read control and the full flag (FF) is used for write control. If either flag from
the synchronizer or the device is held low or becomes metastable, a read is not permitted (truth table output Y) until the
write flag is synchronized.
As can be seen in today's digital systems, synchronous and asynchronous operations can and will produce random errors
due to metastability in single-stage FIFO designs like those of the '722xx synchronous FIFO family. The described
method of implementing a second stage for flag synchronization is extremely useful for clock speeds that are either
approaching or exceeding 33 MHz. Metastability can be virtually eliminated in the '722xx synchronous FIFO family
by the simple addition of a second flip-flop. The second-stage synchronizer greatly reduces metastability, thereby
increasing the MTBF and allowing designers to use faster microprocessors and higher data-transfer rates for greater
overall system performance and reliability.
To reduce metastability and improve system reliability, TI offers a complete line of high-performance FIFO memory
devices. TI's FIFOs have dual-stage synchronization designed onto each chip. This eliminates the need for any external
discrete solution and reduces critical board space by fully utilizing TI's family of fine-pitch surface-mount packaging.
3-21
72211
WCLK
Second Stage
EF I FF Control Logic
RCLK I - - - - - - - E >
Control Empty
EF
Q
Control Full
FF
~----------~~~D
Figure 4. Connecting the Second-Stage Synchronizer to the '72211 Synchronous FIFO
TISN74F74
D-Type
Positive-Edge-Triggered
Flip-Flop
72211
TISN74F08
2-lnput
Positive
AND Gate
Control Empty EF
, To
Receiving
Device
11
.
......'"
Control FuliFF
F = D - Control Empty
Two Stage E
_
EF
INPUTS
F = 'D - Control Full
Two Stage F
_
FF
OUTPUT
Y
A
B
H
H
X
H
L
X
L
L
L
Figure 5. Resolving Metastability of a Synchronous FIFO
3-22
Simultaneous-Switching
Noise Analysis for Texas Instruments
FIFO Products
Navid Madani
Advanced System Logic - Semiconductor Group
~1ExAs
INSTRUMENTS
SCAAOOSA
3-23
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthetime of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applicatlons'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product deSign, software performance, or
Infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-24
Contents
Title
Page
Abstract. • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 3-27
Introduction ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• 3-27
TI Solution for Simultaneous-Switching Noise • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • ••
Reducing Package Inductance ....................•......................................
Multiple GND and Vee Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Output Edge Control (OECTM) Method ....................................................
Dirty and Clean Grounds in 36-Bit FIFO Families ...........................................
3-29
3-29
3-29
3-31
3-32
Simultaneous-Switching Tests Performed to Ensure Reliability of FIFO Products •••••••••••••••••••
SPICE Simulation ....................................................................
GroundIPower-Noise Measurements (VOLP and VORY) ......................................
Special Test Performed on 36-Bit FIFOs (VIH and VIL Testing) ..............................•.
3-32
3-32
3-32
3-33
Summary ................................................................................ 3-33
References ............................................................................... 3-33
Acknowledgements ....................................................................... 3-33
Appendix A .............................................................................. 3-34
Appendix B .............................................................................. 3-39
3-25
List of mustratioDS
FigUre
1
Title
Page
Power/Ground Noise Coupling Through a dc-on Driver to External Circuitry ................... 3-27
2
Simultaneous Switching ................•............................•................ 3-28
3
Example of Ground-Bounce Waveform ...•............................................. 3-28
4
SN74ACTI814 FIFO With Multiple GND Pins . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . • . . . .. 3-30
5
CMOS-Transistor-Gate Layout ....................................................... 3-31
6
TI's Patented OEC Circuitry . . . . • . . . . . . . . • • • . . . . • . . . . . . • . . . • . . . • . . . . . . . . . . . . . . . . . . . . .. 3-32
A-I SN74ACT3638 VOLP, Vee - 5.5 V ................................................... 3-34
A-2 SN74ACT3638VOHV,Vee-5.5V .........•.......................................•. 3-34
A-3 SN74ABT3611 VOHV. Vee - 5 V •............•........•............................. 3-35
A-4 SN74ABT3611 VOHV. Vee-5.5V ..••........•..........•...................•....... 3-35
A-5 SN74ABT3611 VOLP, Vee-5V ..........•.......•.................................. 3-36
A-6 SN74ABT3611 VOLP. Vee - 5 V ..................................................... 3-36
A-7 SN74ABT3613VOHV. Vee-5V .................................................... 3-37
A-8 SN74ABT3613 VOHV , Vee - 5.5 V ............•...•.................................. 3-37
A-9 SN74ABT36I3 VOLP. Vee - 5 V ..............•................•.......••......•..... 3-38
A-I0 SN74ABT3613 VOLP. Vee - 5.5 V .................•...................•............. 3-38
B-1 Surface-Mount Package Options . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . • . • . . . . . . . . . • . . . . . • . . . .. 3-39
B-2 Surface-Mount Package Area by Package Type ....•...................................... 3-40
List of Thbles
Table
3-26
Title
Page
1
Inductance Value per Pin for Most Package Types Used for FIFO Products ..................... 3-29
2
Number of Data Output Pins per Ground Pin for Different FIFO Products ...................... 3-30
3
SPICE Simulations for the SN74ACT3632 Device When 18 or 36 Outputs Switch Simultaneously .. 3-32
4
Sample VOLP and VOHV Test Results for 36-Bit FIFO Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-33
5
Thst Required for the 36-Bit SN74ACT3632 ............•........•....................... 3-33
Abstract
Analysis of circuit-noise immunity during simultaneous switching of multiple outputs is crucial in the high-speed
advanced logic families including ACT and ABT FIFO products. Consequently, reduction of simultaneous-switching
noise is of the utmost concern to the FIFO design team at Texas Instruments (T!). TI offers reliable FIFO products that
meet the fast-speed requirement of today's technology. In this application report, a thorough explanation of
noise-reduction techniques for TI's FIFO devices is provided. This report assists component and system design
engineers in their evaluations of simultaneous-switching noise for TI's ACT and ABT FIFO products.
Introduction
One concern in advanced integrated circuit (lC) design is the challenge of minimizing simultaneous-switching noise
while increasing switching speed of the device. This application report presents the achievements TI has made in
providing very high-speed FIFO products with minimum simultaneous-switching noise.
This report provides an introduction to advanced CMOS simultaneous-switching noise and the approaches taken by the
FIFO design group to effectively reduce the noise. lest procedures for measuring noise during simultaneous switching
of multiple outputs are also presented. Test results provide the data necessary to ensure proper operation of the FIFO
during simultaneous switching of multiple outputs.
In high-speed, high-density CMOS VLSI devices, many output drivers may switch simultaneously. During the
transition, the excessive current drawn from the power supply can produce a significant amount of power/ground noise
called simultaneous-switching noise (SS noise). The noise may be generated in the package VOOIVss planes and also
in the internal (on-chip) VoolVSS buses. Figure 1 shows the power/ground noise coupling through a dc-on driver to
external circuitry.
Vee
VI
(VSS)
Vss
J~
+-
}y~
Offj
..,.;v
v2
J
}
j
J
v3
(Vee)
'\Jw---+
00
vee
}y~
jt
vss
Figure 1. Power/Ground Noise Coupling Through a dc-on Driver to External Circultry1
A simultaneous-switching scenario where several drivers switch at the same time is shown in Figure 2. The electrical
path from the ground/power IC pads to the package terminals is inductive as shown in Figure 2. The IC pads are
connected through bonding wires to the package pads that are connected through a multilayer package to the package
terminals, which, in tum, are connected to ground/power planes on the printed circuit board (PCB). All of these different
elements in the packaging of the IC behave as inductances with negligible resistive components. 2
Switching Drivers
PCPVCC
Driver I
Quiescent
Driver
-=Ole
GND
Vgl
PCP
GND
Ole
GND
Vgl
PCP
GND
CL
Die
GND
I
Vgl
PCP
GND
Figure 2. Simultaneous Swltchlng2
The physics of the device package plays a fundamental role in the voltage-noise spike. The major effect on a high-speed
device is the induced voltage on the GND and Vee terminals caused by the transient currents from switching capacitive
loads. 3 If only one output is switched, the ground noise is calculated by equation 1 where Lg is the inductance of the
ground terminal due to the bond wire, lead, and via, and dildt is the time rate of change in transient current driving the
capacitive load. Equation 2 illustrates transient current where dVoidt is the change of output voltage in time.
VONO--Lg x dildt
(1)
i(t) = CL x dVoidt
(2)
The induced ground bounce appears on the quiescent output as shown in Figure 3.
o-to·1 Trsnsltlon of Switching Drivers
o
Vn (ground noise)
J.- _______________ _
1·to·0 Trsnsltlon of Switching Drivers
Figure 3. Example of Ground·Bounce Waveform 2
When the number of simultaneously switchingputputs increases, ground noise increases. For large ICs, the relationship
between ground-bounce amplitude and the number of switching drivers is no longer linear. 1,2, 4
Unless these power/ground noise fluctuations are controlled, simultaneous-switching noise can degrade or even limit
system performance. Uncontrolled noise spikes can lead to loss of stored data, severe speed degradation, output glitches,
and reduction in system-noise immunity.3 From a functional perspective, ground bounce reduces noise margins of the
gate and may cause false switching of quiet gates. Noise margins for the low state are usually smaller than noise margins
for the high state; therefore, noise of the ground bus in the IC concerns designers the most. 2, 5
Several techniques have been proposed for reducing simultaneous-switching noise. At the package level, one approach
is to reduce the inductance by improved packaging techniques, such as decreasing the various inductive contributions
3-28
to ground bounce. 2 Surface-mount packages, such as PQFPs, are a better package option than through-hole packages,
such as DIP or PGA, because the former have shortened pins or a lower-profile package. Another approach is to decrease
the inductance of the ground pins by placing as many ground! power pins in the package as possible. I , 2 At the design
level, some designers have proposed output edge control (OEe™) as a solution to reduce noise. 4
At the circuit level, simultaneous-switching noise can be reduced by skewing the output drivers and! or by damping out
power and ground noise with additional damping resistors at the source end of both p- andn-channel transistors of output
drivers,3 and/or by adding bypass capacitors that reduce the current noise associated with output buffers driving off-chip
loads. 4 This application report concentrates only on TI's approaches to reduce the simultaneous-switching noise in
high-performance advanced FIFO products.
TI Solution for Simultaneous-Switching Noise
TI's solutions to minimize noise caused by simultaneous switching of outputs include reducing package inductance by
using multiple ground pins, controlling the output edge, and separating the ground pins. Measurements used by TI in
evaluating the chip's performance are included in the following discussion.
Reducing Package Inductance
To reduce voltage spikes, the value of lead inductance (Lg) in equation 1 should be lowered. Lead inductance is
dependent upon lead lengths as well as the location of GNDIVcc pins in the package. Decreasing the overall size
of the FIFO package lowers the package inductance. The inductance value per pin for most of the package types used
for FIFO products is shown in Table 1. TI's current technology has provided high-performance 9-, 18-, and 36-bit FIFO
products with less inductance per pin, giving TI a performance edge in the FIFO market. More information on TI
package types is provided in Appendix B.
Table 1. Inductance Value per Pin for Most Package Types Used for FIFO Products
PITCH
Standard-Pitch Option
Fine-Pitch Option
PACKAGE TYPE
FIFO TYPE
INDUCTANCE
PER PIN (nH)
24-pin DIP
4-,5-,8-, and 9-bit FIFO
3-15
28-pin DIP
9-bit (lOT) FIFO
2-15
44-pin PLCC
9-bitFIFO
6-8
28-pinSOIC
1-bit FIFO
3-8
12o-pin TQFP
36-bitFIFO
4-5
ao-pinTQFP
18-bltFIFO
64-pinTQFP
9-bitFIFO
5
3-4
Multiple GND and Vee Pins
By adding more GND and Vee pins on a chip, TI offers advanced FIFO products with lower noise compared to other
products with only one GND and one Vee corner pin. The previous section discussed simultaneous-switching noise
being directly proportional to the inductance of the ground! power leads. Multiple ground! power pins improve the noise
immunity of the chip by reducing the total ground! power lead inductance because the total inductance is a parallel
combination of the lead inductances of the ground!power pins. For example, SN74ACTI814 FIFO memory in
Figure 4 has four GND pins distributed among the outputs. The total ground-lead inductance of this chip is
approximately one-fourth of that of a similar chip with only one GND pin. Assuming Ll, L2. L3, and L4 are the lead
iilductances of the four ground pins on the chip, and assuming these inductances are equal, the combination of the parallel
inductances is 114 of the inductance when only one GND pin is on the chip (see equation 3).
(3)
OEC is a trademark of Texas Instruments Incorporated.
3-29
Multiple ground! power pins are used on all TI FIFO products. Table 2 shows the nlllilber of data output pins per ground
pin for different FIFO products.
DLPACKAGE
(TOP VIEW)
RESET
017
016
015
014
013
012
011
010
VCC
09
08
GNO
07
06
05
04
03
02
01
00
HF
PEN
AF/AE
LOCK
NC
NC
FULL
1 V56
2
55
3
54
4
53
52
5
51
6
7
50
8
49
9
48
10
47
11
48
12
45
44
13
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE
Q17
Q16
Q15
GNO
Q14
VCC
Q13
Q12
Qll
Ql0
Q9
GNO
as
Q7
as
as
VCC
Q4
Q3
Q2
GNO
Ql
QO
UNCK
NC
NC
EMPTY
Figure 4. SN74ACT7814 FIFO With Multiple GND Pins
Table 2. Number of Data Output Pins per Ground Pin for Different FIFO Products
FIFO
9 Bits
18 Bits
FIFO PRODUCT
SN74ACT2335
102492
SN74ACT2236
102492
SN74ACT7807
20489
SN74ACT7803
51218
SN74ACT7811
SN74ABT7819
32 Bits
36 Bits
SN74ACT3638
102418
512182
512322
SN74ABT3614
64362
SN74ACT3632
512362
SN74ACT3641
3-30
SIZE
102436
PACKAGE TYPE
GND
PINS
DATA OUTPUTS
PERGNDPIN
4.5
44-pin PLCC (FN)
4
64-pin TQFP. (PM)
12
1.5
44-pin PLCC (FN)
4
4.5
44-pin PLCC (FN)
6
1.5
64-pin TQFP (PM)
12
0.75
4
4.5
68-pin PLCC (FN)
(OL)
10
1.8
8O-pin TQFP (PN)
14
1.3
8O-pin QFP (PH)
14
2.6
SO-pin TQFP (PN)
14
2.6
120-pinTQFP (PCB)
14
4.6
132-pin PQFP (PQ)
15
4.3
120-pln TQFP (PCB)
10
7.2
132-pin PQFP (PQ)
18
4.0
120-pin TQFP (PCB)
14
5.1
132-pin PQFP (PQ)
14
5.1
120-pin TQFP (PQ)
15
2.4
132-pin PQFP (PCB)
15
2.4
Output Edge Control (OECTM) Method
OECTM is another method for controlling simultaneous-switching noise. This is a circuit method that reduces the dildt
portion of equation 1. The output transistor is split into many small subtransistors with sequential turnon of each
subtransistor. By splitting the total current into a series of smaller currents distributed over time, the effective diJdt is
reduced. The delay in turnon of the successive subtransistors reduces the maximum peak diJdt for the entire output
transistor.
Drains
\
0
0
0
0
~
Drains
/
Polyslllcon Gate
\
I~
0
0
0
0
I~
0
0
0
0
~
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
/
(a) TYPICAL ARRANGEMENT
~
0
0
0
0
0
C
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Polyslllcon Gate
~
0
0
0
0
0
0
0
0
0
0
~
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
----
0
0
0
0
0
(b) SERPENTINE ARRANGEMENT
Figure 5. CMOS-Transistor·Gate Layout
At the output, the structure of the polysilicon gate is modified to grade the tumon by removing portions of the polysilicon
gate to form a serpentine arrangement and by driving the gate from one end (see Figure 5). The resistance of the
polysilicon and the capacitance of each gate segment form a distributed RC network that slows the turnon of each
succeeding segment. Figure 6 shows the equivalent-circuit schematic for the distributed output transistor. 4
3-31
Out
In
Figure 6. Tl's Patented OEC Circuitry
The OEC circuitry implemented in output structures reduces simultaneous-switching noise by reducing the edge rate.
The distributed output transistor with pull-down transistors evenly added gives a fast-turnoff feature to the circuit and
minimizes the through current as well. The undesirable slow turnoff is resolved by evenly adding pull-down transistors
to the distributed output transistor. Thmoff transistors minimize through current by rapidly turning off all the segments
of the output-transistor circuit; therefore, the OEC method not only provides an effective means for controlling dildt
noise in high-speed CMOS FIFO products, but adds a fast-turnoff feature to the output circuit.
Dirty and Clean Grounds In 36-81t FIFO Families
To reduce effects of simultaneous-switching noise on 36-bit FIFOs, TI divides the ground pins into dirty and clean
ground terminals. A dirty ground is used only for device outputs and a clean ground is used for inputs and other internal
circuit connections. A dirty ground is isolated from a clean ground on the chip, but users can connect them to the same
external ground. Isolating the. two grounds benefits the FIFO chips because output-switching noise does not affect the
rest of the chip, thereby reducing the possibility of false clocks and intermittent data errors. \
Simultaneous-Switching Tests Performed to Ensure Reliability of FIFO Products
SPICE Simulation
Simultaneous-switching SPICE simulations were performed for the SN74ACT3632 device during the design process
for 36-bit FIFO products. Simulation results for SN74ACT3632 indicate that Vee droop and ground bounce when 18
bits are switching simultaneously are only 4.39 and 0.67 V, respectively. When 36 bits are switching simultaneously,
Vee droop and ground bounce only change to 4 and 0.9 V, respectively. The results of this SPICE simulation illustrate
the reliability of TI's high-performance FIFO products against ground noise6 (see Table 3).
Table 3. SPICE Simulations for the SN74ACT3632 Device When 18 or 36 Outputs Switch
Simultaneously
SN74ACT3632 SWITCHING
SIMULTANEOUSLY
18 bits
36 bits
Vcc DROOP (V)
4.39
4.0
GROUND BOUNCE.(V)
0.67
0.9
Ground/Power-Noise Measurements (VOlP and VOHV)
Noise measurements evaluate the performance of FIFO products while simultaneously switching the outputs. A typical
simultaneous-switching test is performed to determine the magnitude of the disturbance on the output that is not being
switched, as well as stored data integrity for devices with multiple outputs. The voltage induced on a quiescent output
during simultaneous switching is referred to as VOLPandVOHV. ForVOLP (VOHV) measurements ,theoutputundertest
is held low (high) while the rest of the outputs are switching from high to low (low to high). VOLP, the maximum (peak)
. voltage induced on a quiescent low-level output during switching of other outputs, is measured with respect to a ground
reference near the output under test. VOHV is the minimum (valley) voltage induced on a quiescent high-level output
during switching of other outputs. Table 4 summarizes the VOLP and VOHV results for 36-bit FIFO products. Data was
taken on an automatic test machine (lIP 82000) at room temperature (25°C).
3-32
Table 4. Sample VOLP and VOHV Test Results for 36·Blt FIFO Products
DEVICE
SN74ABT3614
VOLPM
0.75
SN74ACT3632
1.0
VOHV(V)
VCc(V)
0.2
5.5
1.4
5.0
The results ofVOLP and VOHVmeasurements perfonned on n's 36-bitFIFO products indicate the reliability and noise
immunity of n's high-perfonnance FIFO products. Sample wavefonns for SN74ACT3638, SN74ACT361I, and
SN74ACT3613 are presented in Appendix A.
Special Test Performed on 36-Bit FIFOs (VIH and VIL Testing)
VIH and VIL values for 36-bit FIFO families are tested while outputs are simultaneously switching. For example, the
SN74ACT3632 continues to function properly with VIH and VIL values shown in Table 5. These results show that
separating the output ground from the ground used for the rest of the chip results in excellent input-noise margins for
the 36- and 32-bit-wide FlFOs.
Table 5. Test Required for the 36-Blt SN74ACT3632
Vee
4.5 V
5.5 V
VIH
1.8V
1.9V
VIL
1.3 V
1.3 V
Summary
Fast switching speeds in today's technology require solutions to problems such as simultaneous-switching noise. The
fast switching of drivers can cause uncontrolled noise spikes on the chip's ground bus, which lead to false clocks or
incorrect data and control signals on the device. As more outputs of an IC switch simultaneously, noise effects increase
and limit the usefulness of the device.
Better packaging options, multiple ground/ power pins, output edge control, arid separating the ground pins as clean and
dirty ground pins reduce the simultaneous-switching noise. Finally, results obtained from simultaneous-switching tests
are provided to illustrate the noise immunity of n's high-perfonnance FIFO devices.
References
1.
R. Senthinathan, J. L. Prince and S. Nimmagadda. "Noise Immunity Characteristics of CMOS Receivers and
Effects of SkewinglDamping CMOS Output Driver Switching Wavefonn on the Simultaneous Switching
Noise," 23 pp. 29-36, Microelectronics Journal, 1992.
2.
Lilianan Diaz-Olavarrieta, "Ground Bounce in ASIC's: Model and Thst Results," IEEE International
Symposium on Electromagnetic Compatibility, 1991, Cherry Hill, NJ.
3.
Texas Instruments Advanced CMOS Logic Designer's Handbook, 1988.
4.
Craig Spurlin and Dale Stein, "EPIC Advance CMOS Logic Output Edge Control," Texas Instruments
TechnicalJournal, March-April 1989,.
5.
H. Hashemi, U. Ghoshal, K. Ziai, and P. Sandborn, "Analytical and Simultaneous Study of Switching Noise
in CMOS Circuits," Proceedings of the Technical Conference, September 1990, pp. 762-773.
6.
Design Review Reports for 74ACT3632 FIFO.
Acknowledgements
The VOLP and VOHV graphs in Appendix A are provided with the assistance of Al Sawyer.
Packaging infonnation in Appendix B is provided by n packaging engineers and organized by Tom Jackson.
3-33
Appendix A
Appendix A shows VOLP and VOHV measurements during simultaneous switching. Measurements are made with
respect to ground at 25°C with an HP8200 automatic test machine. Viis the quiescent voltage on the output being tested
prior to switching other outputs. V2 is the peak voltage on the output being tested while switching other outputs. Vn is
the difference in V I and V2.
70
60
>
E
I
50
&
40
i
.&
..
'S
0
I
.p
30
20
10
0
-10
0
5
10
15
20
25
30
35
40
45
50
t-Tlme-na
VI-25mV, V2-14.7mV, Vn-12.2mV
Figure A-1. SN74ACT3638 VOLP. Vee
=5.5 V
7
>
6
i
'S
.&
.
5
I
~
0
4
3
2
I
.p
01
-1
0
5
10
15
20
25
30
35
40
45
t-Tlme-na
VI - 3.63 V, V2 - 5.31 V, Vn -1.69V
Figure A-2. SN74ACT3638 VOHV. Vee
=5.5 V
50
7
>
I
i
I
8
5
4
~
3
J
2
I
~
0
-1
0
5
10
15
20
25
30
35
40
45
50
t-Tlme-na
VI - 3.25 V, V2 - 2.93 V, VD - -312.5 mV
Figure A-3. SN74ABT3611 VOHY. Vee = 5 V
7
8
>
I
5
j
4
~
3
!
2
'S
""
I
~
--
0
-1
0
5
10
15
-
AI""'\..
J
20
25
30
35
40
t-Tlme-na
VI - 3.71mV, V2 - 3.21 mY, VD - -500 mV
Figure A-4. SN74ABT3611 VOHY. Vee
=5.5 V
45
50
7
>I
I
I.p
6
5
4
\
3
2
I
uJ~
o
~
I
-1
o
5
10
15
20
25
30
35
40
45
50
45
50
t-Tline-ns
VI - 218.75 mY, V2 - 843.75 mY, Vo - 625 mV
Figure A-5. SN74ABT3611 VOLP, Vee =5 V
7
>
I
6
t
5
I.p
3
~
4
h
2
I
...1\
o
-1
W'
o
5
10
15
20
25
30
35
40
t-Tlme-ns
VI - 218.75 mY, V2 - 843.75 mY, Vo - 625 mV
Figure A-6. SN74ABT3611 VOLP, Vee
3-36
=5 V
7
,..
>I
III
~
::I
.&
::I
6
5
~
"",....,
4
3
j
2
0
I
.p
0
-1
0
5
10
15
20
25
30
35
40
45
50
45
50
t-Tlme-ns
Vl- 3.18 V, V2 -2.71 V, VD=-468.75mV
Figure A-7. SN74ABT3613 VOHV. Vee = 5 V
,..
>
I
GI
~
::I
.&
::I
0
7
6
5
4
3
2
I
.p
0
-1
0
5
10
15
20
25
30
35
40
t-Tlme-ns
Vl-3.18V, V2 = 2.71 V. VD--468.75mV
Figure A-S. SN74ABT3613 VOHV. Vee
=5.5 V
3-37
7
6
>
I
5
i
4
3
I.p
2
I
-1
"
.f'\.
o
MAo
~
o
5
10
15
20
25
30
35
40
45
50
t-Tlme-ne
Vl-250mV, V2-1.12V, VD-87SmV
Figure A-9. SN74ABT3613 VOLP, Vee
=5 V
7
>I
i
I.p
6
5
4
\
3
2
I
.I \
o
-1
.-.
~
o
5
10
15
20
25
30
35
40
t-Tlme-ne
Vl-218.7SmV, V2-1.l8 V, VD-968.7SmV
Figure A-10. SN74ABT3613 VOU), Vee = 5.5 V
45
50
Appendix B
FIFO Package Types
1 Bit
9 Bit
18 Bit
36 Bit
27,94
It-- 17,6 ---+I
44-Pln
PLCC(FN)
17,6
=
=
Area 192,0 mm 2
Height 2,65 mm
Lead Pitch 1,27 mm
=
rr~~~
25,2
Area 635,04 mm 2
Height 4,37 mm
Lead Pitch 1,27 mm
=
132·Pln
PQFP(PQ)
2794
PLCC (FN)
=
=
Area =309,78 mm 2
Height =4,37 mm
Lead Pitch 1,27 mm
~
=
=
Area 780,64 mm 2
Height 4,32 mm
Lead Pitch =0,635 mm
n
=
wuu:i
l. JWIWIIIJWIIII16
1j
I
12()"Pln
TQFP (PCB)
U°'----'
=
Area 165,0 mm 2
Height 2,65 mm
Lead Pitch 1,27 mm
=
=
=
=
Area 224,5 mm 2
Height 3,05 mm
Lead Pitch 1,27 mm
=
Area 415,36 mm 2
Height 2,95 mm
Lead Pitch 0,8 mm
=
=
=
=
=
Area 258 mm 2
Height 1,58 mm
Lead Pitch 0,4 mm
=
14--14,95~
IT
II
~18,42~
32.Pln
",-co (RJ)
T
56-Pin
SSOP (OL)
10,35
JJmmmmmummrnm'
=
Q
=
Area 186,62 mm 2
Height 3,30 mm
Lead Pitch 1,27 mm
=
=
Area 190,647 mm 2
Height =2,6 mm
Lead Pitch 0,635 mm
=
1--12~
n
64-Pln
.l.!~QFP (PM)
=
=
Area 144 mm 2
Height 1,5 mm
Lead Pitch 0,5 mm
=
=
=
Area 196 mm 2
Height 1,5 mm
Lead Pitch 0,5 mm
=
Figure B-1. Surface-Mount Package Options
3-39
SOO
*7S1
700
"635
600
500
415
N
E
E
400
310
I
~
300
cr:
200
100
0
24-Pln
SOIC
28-Pln
SOIC
'---v---'
1 Bit
64-Pln
TQFP
32·Pln
PLCC
28-Pln
SOIC
V
9 Bit
44-Pln
PLCC
/
8O-Pln
TQFP
\
58-Pln
SSOP
SD-Pln
PQFP
68-Pln
PLCC
V
1SBIt
"Competitors' Best Solution
Figure 8-:2. Surface-Mount Package Area by Package Type
3-40
120-Pln
TQFP
132·Pln
SOIC
'---v---'
36 Bit
FIFO Solutions
for Increasing Clock Rates
and Data Widths
First-In, First-Out Technology
Kam Kittrell
Advanced System Logic - Semiconductor Group
~1ExAs
INSTRUMENTS
SZZA001A
3-41
IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is curr~nt.
TI warrants performance of Its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage C'Critical Applications'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products In such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of petents or services described herein. Nor does TI warrant or represent that any license, '
either express or implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-42
Contents
Title
Page
Introduction ............................................................................. 3-45
Clocked FIFOs ........................................................................... 3-45
Flag Synchronization ...................................................................... 3-45
.
Compact Packaging ....................................................................... 3-47
New Clocked FIFOs ....................................................................... 3-48
Conclusion .............................................................................. 3-49
List of mustrations
Figure
I
2
3
4
5
Title
Page
Triggering a Metastable Event With a One-Stage Synchronizer ............................... 3-46
Two-Stage Synchronizer ............................................................. 3-46
Storage Oscilloscope Plots Taken Over a I5-Hour Duration ................................. 3-47
Surface-Mount Package Area Comparison ............................................... 3-48
Bidirectional Configuration for the SN74ACT7803 ................. : ...................... 3-49
3--43
3-44
Introduction
Steady increases in microprocessor operating frequencies and bus widths over recent years have challenged system
designers to find FIFO memories that meet their needs. To assist the designer, new FIFOs from Texas Instruments (TI)
are available with features that complement these microprocessor trends.
Higher data-transfer rates have dictated the need for FIFOs to evolve into clocked architecture wherein data is moved
in and out of the device with synchronous controls. Each synchronous control of the clocked FIFO uses enable signals
that synchronize the data exchange to afree-running (continuous) clock.
Since the continuous clocks on each port of a clocked FIFO can operate asynchronously to each other, internal status
signals indicating when the FIFO is empty or full can change with respect to either clock. To use a status signal for port
control, it is synchronized to the port's clock on a clocked FIFO. Synchronization of these signals with flip-flops
introduces metastability failures that increase with clock frequency. TI uses two-stage flag synchronization to greatly
improve reliability.
Higher clock frequencies augment raw speed, but greater bandwidth is also achieved by increasing the data width. Wider
datapaths can have the associated cost of large board area due to increased package sizes. New compact packages for
TI's FIFOs reduce this cost.
Clocked FIFOs
Clocked FIFOs have become popular for relieving bottlenecks in high-speed data traffic. Data transfers for many
systems are synchronized to a central clock with read and write enables. These free-running clocks can be input directly
to a clocked FIFO with the same enables controlling its data transfer on the low-to-high transition of the clock.
Reducing the number of clocks keeps the interface simple and easy to manage. Extra logic is needed to produce a gated
pulse when using a FIFO that accepts a clock only for a data transfer request. The generated clock signal is a derivative
of the master clock with a margin of timing uncertainty. At high clock frequencies, this timing uncertainty is not tolerable
and costly adjustments are needed.
Additional logic also is conserved by implementing flag synchronization on the clocked FIFO. Tracking is done to
generate flags that indicate when the memory is empty or full. In many applications, the input and output to the FIFO
are asynchronous and the flag signals must be synchronized for use as control. A read is not completed on the FIFO if
no data is ready, so the EMPTY signal is synchronized to the read clock. This synchronous output-ready (OR) flag is
useful for controlling read operations. Likewise, the FULL signal is synchronized to the write clock, producing the
input-ready (IR) flag.
Flag Synchronization
As previously explained, one of the advantages of the clocked FIFO is the on-board synchronization of the EMPTY and
FULL status flags when the input and output are asynchronous. In one method of synchronization, a single flip-flop
captures the asynchronous flag's value (see Figure 1). With this method, the rising transition of data can violate the
flip-flop's setup time and produce a metastable event (metastability is a malfunction of a flip-flop wherein the latch
hangs between high and low states for an indefinite period of time).
3-45
Clock
Q
Asynchronous
Flag
Clock
D
I
llf
~ ~tsu
Flag
I
I
I
OR
Synchronized
Flag
{
(
tpd~
r
\
~tr4
Figure 1. Triggering a Metastable Event With a One-Stage Synchronizer
Once a metastable event is triggered, the probability of the output recovering to a high or low level. increases
exponentially with increased resolve time (tr). The expected time until the output of a single flip-flop with asynchronous
data has a metastable event that lasts tr or longer is characterized by the following mean time between failures (MTBF)
equation:
exp(¥)
MTBF, =of t
f
ed
Where:
to - flip-flop constant representing the time window during which changing data invokes a failure
tr - resolve time allowed in excess of the normal propagation delay
t - flip-flop constant related to the settling time of a metastable event
fc - clock frequency
fd - asynchronous data frequency. For OR-flag analysis, it is the frequency at which data is
written to empty memory. For IR-flag analysis, it is the frequency at which data is read from
full memory.
The MTBF decreases as clock and data frequency increase and as the time allowed for a metastable event to settle (tr)
decreases.
Metastability failures are a formidable issue for short-clock cycle times. Increasing the clock frequency linearly
increases the number of metastable events triggered, but the shortened available resolve time exponentially increases
the failure rate. It is impossible to eliminate the possibility of a metastable event under these conditions, but solutions
exist to reliably increase the expected time between failures.
Clock
Aaynchronous
Flag
Q
D
Q
D
Figure 2. Two-Stage Synchronizer
3-46
Synchronized
Flag
11 increases the metastable MTBF by several orders of magnitude for m and OR flags by employing two-stage
synchronization (see Figure 2). For the output of the second stage to be metastable, the first stage must have a metastable
event that lingers until it encroaches upon the setup time of the second stage. Adding another stage to a single flip-flop
synchronizer is statistically equivalent to increasing its resolve time by the clock period minus its propagation delay.
The mean time between failures for a two-stage synchronizer is given by:
exp[
t,
+t-tpj
t
C
Where:
tp - propagation delay of the fJrst flip-flop
fo= 50 MHz, fd = 5 MHZ, VCC
=5 V
(8) ONE-STAGE SYNCHRONIZATION
fo = 55.7 MHz, fd
=6.7 MHz, VCC =5 V
(b) TWO-STAGE SYNCHRONIZATION
Figure 3. Storage OSCilloscope Plots Taken Over a 15-Hour Duration
Figure 3 compares the two synchronization methods previously discussed. Both plots were taken at room temperature
and nominal Vee while each data transition violated setup time. Figure 3(a) shows the performance of an EMPTY flag
synchronizer using only one flip-flop, while Figure 3(b) is the m flag of an SN74ACI'7S07 with the write clock
operating at maximum frequency.
Compact Packaging
Microprocessor bus widths have continuously doubled every few years to maximize their performance. Bus widths of
32 and 64 bits are commonplace today, whereas they were almost unheard of a few years ago. The downside to the
increased bit count is that each subordinate device in the system must match this width with corresponding increases
in board size.
New shrink packages forTI's clocked FIFOs provide a solution to this problem. Multiple-byte datapaths can be buffered
while covering only a fraction of the area of conventional packages. These new FIFO packages are presently available
in 56-, 64-, and SO-pin configurations. Dubbed shrink quad flat package (SQFP), the 64-pin package is used for
9-bit-wide FIFOs, and the SO-pin package is used for IS-bit-wide FIFOs. Both SQFP packages have a lead pitch of
0.5 mm. The 56-pin shrink small-outline package has a O.025-inch lead pitch and also houses IS-bit-wide FIFOs. A
variety ofTI's FIFOs are offered in these new packages (see Table 1).
3-47
Table 1. FIFOs Available In Space-Efficient Packages
DEVICE
CLOCKED
ORGANIZATION
CLOCK CYCLE
TIME (n8)
PACKAGES
SN74ACT2235
No
1Kx9x2
20,3040,50
64 TQFP
44 PLCC
SN74ACT7802
No
1Kx18
25,40,60
60TQFP
68 PLCC
SN74ACT7811
Yes
1Kx18
15,18,20,25
80TQFP
68PLCC
SN74ACT7803
SN74ACT7805
SN74ACT7813
Yes
512 x 18
256 x 18
64x 18
15,20,25,40
56SS0P
SN74ACT7804
SN74ACT7806
SN74ACT7814
No
512x 18
256 x 18
64x 18
20,25,40
56SS0P
SN74ACT7807
Yes
2Kx9
15, 20, 25, 40
64 TQFP
44 PLCC
SN74ACT7808
No
2Kx9
20,25,30,40
64 TQFP
44 PLCC
Figure 4 compares the space savings of the new compact packages compared to competitive surface-mount solutions.
A 4-byte path constructed with four clocked FIFOs in 32-pin PLCC packages occupies 1.16 in2, while two 56-pin SSOP
packages occupy only 0.59 in2.
1
0.9
0.8
-
IN
0.7
0.6
C
:::.
I
CC
0.5
0.4
0.3
0.2
0.1
0
64 TQFP 56 SSOP 80 SQFP. 32 PLCC 44 PLCC 68 PLCC
Figure 4. Surface-Mount Package Area Comparison
New Clocked FIFOs
Four new CMOS clocked FIFOs from 11 offer a variety of memory depths. All four can match applications that require
maximum clock frequencies of 67 MHz and access times of 12 ns. Suited for buffering long packets, the 2K x 9
SN74ACT7807 is the deepest of the four and is available in the 44-pin PLCC or 64-pin TQFP. The SN74ACT7803,
SN74ACT7805, and SN74ACT7813 are organized as 512 x 18,256 x 18, and 64 x 18, respectively, and have the same
pin arrangement in the 56-pin SSOP. Every 11 clocked FIFO is easily expanded in word width, and the
SN7 4ACT7803/05/13 can also be arranged to form a bidirectional FIFO. With the two FIFOs connected as in Figure 5,
no extra logic is needed for bidirectional operation.
.
3-48
'ACT7803
ClKA
WRTCLK RDCLK
ClKB
WiRA
WRTENl
OEl
W/RB
A
CS
WRTEN2
RDEN
012
cst
.J
18
DO-D17 QO-Q17
BO-B17
'ACT7803
-
L
AO-A17
18
RDCLK WRTCLK
r--
OEl
WRTENl
r--
RDEN
WFi'i'EN2
OE2
QO-Q17 DO-D17
Figure 5. Bidirectional Configuration for the SN74ACT7803
Silicon is currently available for a bidirectional clocked FIFO fabricated in TI's Advanced BiCMOS (ABT) process.
The SN74ABT7819 is organized as 512 x 18 x 2 with two internal independent FIFOs. Each port has a continuous
free-running clock, a chip select (CS), a read/write select (WW), and two separate read and write enables for control.
It supports clock frequencies in excess of 80 MHz and a maximum access time below 10 ns. This device is packaged
in the 80-pin QFP and 80-pin SQFP.
Conclusion
Several semiconductor manufacturers, including TI, have responded to customer needs by providing clocked FIFOs
whose synchronous interfaces conform to the requirements of many high-performance systems. Capitalizing on the
available continuous system clocks, this architecture limits the amount of necessary glue logic and the number of timing
constraints.
Flag synchronization is important for clocked FIFOs buffering between asynchronous systems. Flip-flop synchronizers
used for this task have a metastable failure rate that grows exponentially with clock frequency. TI employs two stages
of synchronization that improve the flags' reliability significantly.
Finally, providing a FIFO buffer for wide buses has historically consumed large amounts of board area. Designers
seeking relief from this problem can fmd it in the packaging options offered for TI's FIFOs. Used to house 9- and I8-bit
devices, these packages require only about 50% of the space required for conventional surface-mount packages.
3-49
3-50
FIFO Features
Page
FIFO Patented Synchronous Retransmit: Programmable DSP-Interface Application
for FIR Filtering .............................................................
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control ........
Advanced Bus-Matching/Byte-Swapping Features for Internetworking FIFO Applications ...
Parity-Generate and Parity-Check Features
for High-Bandwidth-Computing FIFO Applications ...............................
3-53
3-65
3-75
3-87
3-51
FIFO Patented Synchronous
Retransmit: Programmable
DSP-Interface Application
for FIR Filtering
Steve Strom and Kam Kittrell
Advanced System Logic - Semiconductor Group
~lExAs
INSTRUMENTS
SCAAOO9A
3-53
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthetime of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage (''Critical Appllcations',.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license.
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright@ 1996, Texas Instruments Incorporated
3--'54
Contents
ntle
Page
Introduction .........................•...•.............•................................. 3-57
Description of Synchronous Retransmit ......•............................................... 3-57
Example of Retransmit for FIR Filtering .....•............................................... 3-59
Modified Code for TMS320C3x FIR Filtering .•.....••....•.•...••.............•.......•...... 3-61
Conclusion ............................................................................... 3-63
Figure
List of mustrations
ntle
Page
I
SN74ACf3638 Functional Block Diagram ...............................•.............. 3-58
2
FIFOI Retransmit Timing Diagram Showing Minimum Retransmit Length ......••..•••...•.. " 3-59
3
Using a FIFO for Coefficient Storage in Multiply/Accumulate Operations ...................... 3-59
4
5
6
Bidirectional FIFO Interface ...•.........•............•...••.......................... 3-60
Interconnection Example . . . . . . . . . . . . . . . • • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . .. 3-60
Retransmit Timing for Interconnection Example .......................................... 3-61
7
IOF Register Bit Summary .•..•......................•.........................•..... 3-61
8
FIFO Retransmit Control for FIR Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . .. 3-62
9
Control Timing for FIFO Retransmitfor the FIR Filter ..........•.......................... 3-63
3-55
3-56
Introduction
TIris application report presents one example of the many uses of the synchronous-retransmit feature of Texas
Instruments (TI) digital signal processing (DSP) application-specific FIFOs. This report describes TI's patented
synchronous-retransmit feature and shows how this feature can be used in conjunction with a DSP for fmite-Iength
impulse-response (FIR) filtering. The TMS32OC31 floating-point DSP and the SN74ACT3638 bidirectional clocked
FIFO are the examples for this discussion.
Description of Synchronous Retransmit
An SN74ACT3638 functional block diagram with the synchronous-retransmit logic block highlighted is shown in
Figure 1. The synchronous-retransmit feature of the SN7 4ACT3638 allows data stored within the FIFO to be reread
starting at a selected position. FIFO 1, one of two 512 x 32 dual-port SRAM FIFOs on board the SN74ACT3638 device,
buffers data from port A to port B. FIF01 is placed in the retransmit mode to select a beginning word and to prevent
ongoing FIFO write operations from destroying data to be retransmitted. Data vectors with a minimum length of three
words can be retransmitted repeatedly starting at the selected word. The FIFO can be taken out of the retransmit mode
at any time, allowing normal operation to resume.
Figure 2 shows the FIF01 retransmit timing and minimum retransmit length. FIFOl is placed in the retransmit mode
by a low-to-high transition on CLKB when the retransmit mode (RTM) input is high and the port-B output-ready (ORB)
flag is high. This rising clock edge marks the data present in the FIFO 1 output register as the first retransmit word. FIFO 1
remains in the retransmit mode until a low-to-high transition of CLKB occurs while RTM is low.
When two or more reads have been performed past the initial retransmit word, a retransmit is initiated by a low-to-high
transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the first retransmit
word to the FIF01 output register and subsequent reads begin immediately. While FIFOl is in the retransmit mode,
retransmit loops can be performed repeatedly with each pulse of the RFM terminal.
When FIF01 is in the retransmit mode, it operates with two read pointers. The current-read pointer operates normally,
incrementing each time anew word is shifted to the FIFO 1 output register. TIris pointer is used as a reference by the ORB
and port-B almost-empty (AEB) flags. The shadow-read pointer stores the SRAM location at the time FIFOl is placed
in the retransmit mode and does not change until FIF01 is taken out of the retransmit mode. TIris pointer is used as a
reference by the port-A input-ready (IRA) and almost-full (AFA) flags. While the FIFO is in the retransmit mode, data
writes to the FIFO may continue. AFA is setlow by the write that stores (512 - Y1) words after the frrst retransmit word,
where 512 is the FIFO depth and Y1 is the almost-full-flag offset value. The IRA flag is set low following 512 writes
after the first retransmit word.
When FIF01 is in retransmit mode and RFM is high, a rising CLKB edge loads the current pointer with the
shadow-read-pointervalue. The ORB flag immediately reflects the new level offill. If the retransmit changes the status
of FIFO 1 such that it is no longer within the almost-empty range, up to two CLKB rising edges after the retransmit cycle
are required before the AEB flag is asserted. The rising CLKB edge that takes FIFO lout of the retransmit mode shifts
the read pointer used by the IRA and AFA flags from the shadow-read pointer to the current-read pointer.
3-57
MBF1
I
CLKA
CSA WiRA ENA
MBA
R::~r
-
-
Port·A
Control 1 - Logic 1 - - l-
l
...
Jr~
-
r---
~
I
512x32
SRAM
I'S I+-
FIF01,
Mal11
Reaat
Logic
C2.
.5
""'--
1.32
~
RTM
f-+--4
I
Write
Pointer
II
RFM
Reed
Pointer
T
IRA
AFA
I
.
1f-'
I
ORA
AEA
I
I
I
..
.,.
Logic -..
Reed
Pointer
T~
II
.,.
I
I
Write
Pointer
IRB
AFB
II
..
512x32
SRAM
~~
l32
-.
I
I'S
C2.
--.5
I
ROYB
BO-B 31
._-
...1
[FIF02
,
ORB
AEB
I
.
ProgrammableFlag
Offset
",
ROYA
I
~
FSO
FS1
AO-A31
T
Logic -.. I
R::~~r
I
FIF02,
Mall2
Reaat -+-'RST2
Logic
f-4-<
....
I-- Port·B -4-CLKB
'--- I-- Control
.... r--
I
Figure 1. SN74ACT3638 Functional Block Diagram
3-58
Logic
....::=i~:B
..... ·MDD
eLKB
I
I
\
\
~ Ih(EN)
I??j I 'W
tau(EN)
ENB
tau(RM)
I
I
I
I
I
I
I
I
I
I
I
~ "'(AM)
IW I~
RTM
I
I
I
I
I
I
RFM
ORB
II
High
I4-ta-tl
wo
BO-B31
Initiate Retransmit Mode
WIth WO .. First Word
*
I
\
tau(EN)
~
I
I
I
I
I
I
I
I
I
~ta....,
I4-ta"""
*
W2
Retransmit From
Selected Position
"'(AM)
'&~ I~
#» -!Ut§\)
I
\
I
I
I
tau(AM)
'--ta"""
W1
I
\
~ Ih(EN)
*
wo
End Retransmit
Mode
tsu(EN)
Setup time, CSA, WIRA, ENA, end MBA before CLKAt; ese, WIRB,
ENB, MBB, ATM, end RPM slter CLKBt
tsU(EN)
Hold time, CSA, WiRA, ENA, end MBA slter CLKAt; ese, WIRB,
ENB, MBB, ATM, end RFM after CLKBt
fa
Access time, CLKAttoAO-A31 end CLKBtto 80- 831
*
W1
Figure 2. FIF01 Retransmit nmlng Diagram Showing Minimum Retransmit Length
Example of Retransmit for FIR Filtering
In addition to the typical interface functions, such as rate matching and clock partitioning, FIFOs with retransmit
capabilities can provide arepeated sequence of data to a processing element such as a DSP. This sequence ofinfonnation
may take the form of coefficients for use in a DSP multiply/accumulate operations as shown in Figure 3.
Retransmit
Loop
Initializing
Informetion
forDSP
Data
Block 1
Coefffcients
for
FFTofFIR
Data WrIte! Reed Order
---+
Figure 3. Using a FIFO for Coefficient Storage In Multiply/Accumulate Operations
3-69
\
Many DSP applications require filtering. The FIR fIlter is a type of digital filter that is implemented very efficiently by
the TMS32OC31. The FIR filter in the time domain takes the general form of:
N-I
y(n)
=
I
h(i) x x(n - I)
i=O
Where:
y(n) is the output sample at time n,
h(i) is the ith coefficient or impulse response, and
x(n - i) is the (n - i)th input sample.
The capability for parallel multiply/add operations and circular addressing permits easy implementation of the FIR filter
with the TMS32OC31 DSP. The former allows a multiplication and addition operation to execute in one machine cycle;
the latter generates a finite buffer of length N for the data x(n).
When used for coefficient storage, the FIFO serves as a zero-wait-state SRAM. Applications in which coefficients or
other data are stored in external SRAM or EPROMs can be greatly simplified, thereby reducing cost, space
requirements, and overall device count. In other instances where DSP internal RAM is used to store the coefficients,
a penalty is often paid in the form of overhead time for transferring the coefficients from the buffering FIFO to RAM.
This overhead penalty and inefficient use of RAM can be eliminated by the use of the patented synchronous-retransmit
feature of the 11 FIFO.
'I\vo TMS32OC31 external input/output (110) flags (XFO and XFI) can be configured as input or output terminals under
software control. In the example of FIR filtering, I/O flags can be implemented to control the retransmit function of the
FIFO, providing a programmable DSP interface; Figure 4 shows a block-diagram representation of the bidirectional
interface to the programmable DSP.
rG
....._H_o_st__
32
4/~
32
4/~
SN74ACT3638
I"-~
Point
.
DSP
Figure 4. Bidirectional FIFO Interface
Figure 5 shows an interconnection example for the SN74ACT3638-30 FIFO and TMS32OC31-40 DSP. The DSP XFO
and XFI terminals are configured for general-purpose output and are directly connected to the RTM and RPM terminals
of the FIFO, respectively. The retransmit timing associated with this interface is shown in Figure 6. The I/O flag register
(lOp), which is one of28 registers in the TMS32OC3 I CPU register file, controls the external pins XFO and XFI. Figure
7 shows a summary of 10F register bit assignments. Additional information on the 10F register may be obtained by
consulting the TMS32OC3x User's Guide (literature number SPRU031C).
SN74ACT3638-30
TMS320C31-40
ClKS
0
css
Decode
ENS
W/RS
~
A23,A20
W/R
XFO
RFM
XF1
33
Figure 5. Interconnection Example
3-60
~
STRS
RTM
SO-S31
H3
DO-D31
~ Fetch/Load
+
Decode
H3
OUTFxBlt
Oar 1
14--
13ns~
I
XFxPln ________________________________________________--J~ Oor1
Figure 6. Retransmit Timing for Interconnection Example
31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
Ixx Ixxlxxl xxlxxlxxl xxlxxl
xx
xx
xx
I xxi
xx
xx
xx
I xxi
151413121110 9 8
7
6
5
4
3
2
0
Ixxlxxlxxlxxlxxlxxlxxlxxl INXF1 I OUTXF11 T/OXF1 Ixxl INXFO IOUTXFOI T/OXFO Ixxl
R
R
R/W
R/W
R/W
R/W
NOTES: A. xx =reserved bit, read as ,0
B. R =read, W =write
BIT
o
NAME
RESET VALUE
Reserved
o
Read as 0
i/OXFO
o
o
o
o
o
If ItOXFO '" 0, XFO is configured as a general-purpose input terminal.
If I/OXFO '" 1, XFO is configured as a general-purpose output terminal.
2
OUTXFO
3
INXFO
4
Reserved
5
i/OXF1
6
OUTXF1
7
INXF1
o
o
Reserved
0-0
31-8
FUNCTION
Data output on XFO
Data Input on XFO. A write has no effect.
Read as 0
If ItOXF1 '" 0, XF1 is configured as a general-purpose input terminal.
If I/OXF1 '" 1, XF1 is configured as a general-purpose output terminal.
Data output on XF1
Data input on XF1. A write has no effect.
Read as 0
Figure 7. IOF Register Bit Summary
Modified Code for TMS320C3x FIR Filtering
The FIFO retransmit control for FIR filtering can be structured as in the following modified code fragment from the
TMS32OC3x User's Guide (see Figure 8). The values loaded into the IOF register are chosen to set and reset the RTM
and RFM terminals of the FIFO as appropriate, providing retransmit control. Figure 9 shows the control timing
associated with the FIFO retransmit for the FIR filter.
*
TITLE FIR FILTER
(I! denotes changes from code example in
*
the TMS320C3x User's Guide)
*
SUBROUTINE FIR
*
EQUATION: yen) = h(O) * x(n) + hell * x(n-1) +
*
... + h(N-l) * X(n-(N-l»
TYPICAL CALLING SEQUENCE
*
LOAD
ARO
*
LOAD
AR1
*
LOAD
RC
*
LOAD
BK
*
LOAD
IOF
* II
*
CALL
FIR
*
ARGUMENT ASSIGNMENTS:
*
ARGUMENT I " FUNCTION
*
*
--------+------------------------------------------------
* II
ARO
ADDRESS OF FIFO where h vector is stored starting with
h(N-1)
*
ADDRESS OF x(n-(N-1»
*
AR1
LENGTH OF FILTER - 2 (N-2)
*
RC
LENGTH OF FILTER (N)
*
BK
* I I IOF
XFO, XF1 configured as outputs. XFO is high, XF1 is low.
*
Initial register content is 026h. FIFO in retransmit mode.
* ! I REGISTERS USED AS INPUT: AR1, RC, BK, IOF
* I I REGISTERS MODIFIED: RO, R2, ARO, AR1, RC, IOF
*
REGISTER CONTAINING RESULT: RO
.global FIR
*
Initialize RO
FIR
MPYF3
*ARO,*AR1++(l)%,RO
I I ARO not incremented
h(N-1) * x(n-(N-1» -> RO
*
LDF
O.O,R2
Initialize R2
FILTER
(1
<=
i
<
N)
*
RPTS
RC
Setup the repeat cycle
I I ARO not incremented
*
*ARO,*AR1++(1)%,RO
MPYF3
h(N-1-i)*x(n-(N-1-i»->RO
RO,R2,R2
ADDF3
Multiply and add operation
II
*
*
ADDF
RO,R2,RO
Add last product
LDI
066h,IOF
Retransmit FIFO data starting
with h(N-1) by asserting RFM
(XF1) high
LDI
026h,IOF
I!
*
*
*
II
*
*
*
3-62
RETURN SEQUENCE
RETS
end
.end
End RFM (XF1) high pulse to
begin normal data reads
Return
Figure 8. FIFO Retransmit Control for FIR Filtering
CLKA
(H3)
RTM
(XFO)
RFM
(XF1)' _ _ _+-.....JI\-....J
80-831
h(N-1)
h(O)
Set FIFO In
Retransmit Mode
\ (LDI O2Oh.IOF)
h (N_-_1_)1-__--'-_""""I__
Retransmit
CoefIIclent V8CICr
(LDI 066h.IOF)
End RFM Pulse
(LDI 028h.IOF)
/
h(N-1)
h(O)
Retransmit
CoefIIclent Vector
(LDI 088h.lOF)
h(N-1)
End RFM Pulse
(LDI028h.IOF)
End Retransmit
Mode on FIFO
(LDI 022h.IOF)
v~-----_--J
Generate yin)
Cell FIR M Times
10 Generate y Vector
~----------~v~--------------J
Generate y Vector of Length M + 1
Figure 9. Control Timing for FIFO Retransmit for the FIR Filter
Conclusion
Unlike conventional retransmit, 11's patented synchronous-retransmit feature allows the user to select or mark the FIFO
data to be retransmitted. Synchronous retransmit is easily controlled by two FIFO terminals: R1M and RPM. As
previously discussed in this application report, synchronous retransmit provides a very efficient method for transferring
a series of FIR filter coefficients to a DSP without storing the coefficients in a standard SRAM or EPROM. By
interfacing the DSP external 110 terminals to the FIFO retransmit tenninals, the DSP can effectively request the FIR
filter coefficients on demand.
The following FIFOs belong to the DSP application-specific family featuring synchronous retransmit.
Table 1. DSP Applicatlon·Speclflc Family
SPEED SORTS
tc (n8)
MAXIMUM
FREQUENCY
(MHz)
MAXIMUM
ACCESS
512x32x2
-15,-20,-30
67
11
SN74ACT3631
512 x 36
-15,-20,-30
67
11
SN74ACT3641
1Kx36
-15,-20,-30
67
11
SN74ACT3651
2Kx36
-15,-20,-30
67
11
DEVICE
ORGANIZATION
SN74ACT3638
(n8)
3-63
3-64
FIFO Mailbox-Bypass Registers:
Using Bypass R~gisters to Initialize
DMA Control
Kam Kittrell and Steve Strom
Advanced System LogIc - Semiconductor Group
:illExAs
INSTRUMENTS
SCAA007A
3-65
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the Information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may Involve potential risks of death, personal injury,
or severe property or environmental damage C'Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any licanse,
either express or Implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, TE!xas Instruments Incorporated
Contents
Title
Page
Introduction ............................................................................. 3-69
Mailbox-Bypass Register Operation ......................................................... 3-69
DMA Controller Description ............................................................... 3-71
Initializing DMA Controllers With Mailbox-Bypass Registers .................................... 3-72
Conclusion .............................................................................. 3-74
List of IDustrations
Figure
Title
Page
SN74ACT3641 FIFO Functional Block Diagram .......................................... 3-69
2
Timing Diagram for Maill Register and MBFl Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-70
3
TMS32OC31 Memory Map in Microprocessor Mode Showing Mailbox-Bypass Register
and FIFO SRAM Addresses .......................................................... 3-71
4
TMS320C31 DSP Block Diagram ..................................................... 3-72
5
Using DMA Controlto Transfer Large Data Blocks ........................................ 3-72
6
Using Mailbox-Bypass Registers to Initialize DMA Control ................................. 3-73
3-68
Introduction
This application report describes the operation of FIFO mailbox-bypass registers and shows their application in an
example that implements the direct memory access (DMA) control of a digital signal processor (DSP). All Texas
Instruments (TI) 32- and 36-bit FIFOs contain mailbox-bypass registers that transmit priority data from one FIFO port
to the other, either from port A to port B or port B to port A, without storing the data in the FIFO SRAM buffer. The
SN74ACT3641, a unidirectional, clocked-DSp, application-specific FIFO (lK x 36), is used as the example for our
discussion. In the following scenario, this device connects to a DMA controller that may be viewed as an integral part
of any generic processing element. This discussion focuses on the DMA controller that is resident on board the
TMS320C3! DSP.
Mailbox-Bypass Register Operation
The operation of the FIFO mailbox-bypass register is straightforward. Each FIFO that features the mailbox option has
two 32- or 36-bit bypass registers (Maill and Mai12) to pass command and control information between both ports
without queuing the information in the FIFO SRAM buffer. The functional block diagram of the SN74ACT3641 is
shown in Figure 1. The associated timing of the Mail! register in the FIFO functional block diagram is shown in
Figure 2.
+
CLKA, -
CSA,- Port-A
W/RA, - Control
ENA, MBA,-
I
Mall1
Reglstar
Logic
-
~
-
-@]
.........
-
I
'S
Go
512 x 36,
1024 x 36,
or
2048x36
SRAM
~
.s
-
LogiC
I
T~
r.- !
! .......-::J
T
:=
RTM
.cEo
3~
0
I
I
Write
Pointer
AO-A35
I
IR
I
AF
I
II
Read
Pointer
T
~
0 -
~iS
II:
-44
RFM
T
BO-B35
Status-Flag
Logic
OR
AE
+
Flag-offset
Reglatar
FSo/SD
FS1/SEN
'"""-
10
'----
0( ....
I
Mal12
Register
I
I
Port-B
Control
Logic
~
~
f+-
CLKB
CSB
W/RB
ENB
MBB
T
Figure 1. SN74ACT3641 FIFO Functional Block Diagram
3-69
ClKA
I
\
,
________~~~(~EN~l~
r-__
\\-__--J/
\\-_ _.....J/
t_h(_EN_l___________________________________
H : W'
W/RA
??ZlIT!ZZT4
MBA
?2lZZZl/ZZZZ?
I
I
I I
I
: I
W'
ENA
AO-A35
ClKB
I
W/RB
o/ZIflf:
II
ENB
ten
BO-B35
II.
I
I
MBB
II
i"--t
!
1..1.1
I"
~,
:
tsu(ENl~
tpd(M-DV)
1
,I
mdJ
i__.
~......,
k~w
1h(ENl
fu\'\
tpd(C-MRl
I
I
I
-tI
~ tdls
------~~::.~:::::.:::).~ W1(remalns valid In Mall1 register after readl
j..-.
FIFO Output Register
Figure 2. Timing Diagram for Mall1 Register and MBF1 Status Flag
Operation of the SN74ACT3641 mailbox~bypass registers is summarized below and shown in Figure 2. The
mailbox-select inputs (MBA and MBB) are used to choose between a mail register and the FIFO SRAM for a port data
transfer operation. A low-to-high transition on CLKA writes the data on AO-A35 to the Maill register when a port-A
write is selected by CSA, WiRA, and ENA while MBA is high. Likewise, a low-to-high transition on CLKB writes the
data on BO-B35 to the Mail2 register when a port-B write is selected by CSB, W/RB, and ENB while MBB is high.
Writing data to a mail register sets its corresponding status flag (MBFl or MBF2) low. Attempted writes to a mail register
are ignored while the mail flag is low.
When the port-B data outputs (BO-B35) are active and the mailbox-select input (MBB) is low, data on the bus comes
from the FIFO output register. When the port-B data outputs are active and the port-B mailbox-select input is high, data
on the bus comes from the mailbox register (Maill). The MaiU register data is always present on the port-A data outputs
(AO-A35) when they are active. The Maill register flag (MBFl) is set high by a low-to-high transition on CLKB when
MBB is high and a port-B read is selected by CSB, W/RB, and ENB. The Mai12 register flag (MBF2) is set high by a
low-to-high transition on CLKA when MBA is high and a port-A read is selected by CSA, wiRA, and ENA. Data in
a mail register remains intact after it is read and changes only when new data is written to the register.
The mailbox-bypass registers can be easily mapped to a location within aDSPthat is separate from the location assigned
to the FIFO SRAM within the same memory map. This is made possible by virtue of the mailbox-register control
terminals and timing similarities between the mailbox-register read/write operation and the FIFO SRAM read/write
operation. An example of assigning the mailbox register and FIFO to the memory map of the TMS32OC31 is shown in
Figure 3.
3-70
Oh
03Fh
040h
Interrupt Vectors
and Reserved
External STRB
Active
(NSMwords)
7FFFFFh
SOOOOOh
S07FFFh
808000h
S097FFh
S09800h
S09BFFh
809COOh
S09FFFh
32KWords
Reserved
Peripheral eBus
Memory-Mapped Registers
IntemalRAM
Block 0
Internal RAM
Block 1
SOAOOOh
9OO000h
AOOOOOh
I
FIFO Read I
FIFO Write
External
STRB
Active
FFFFFFh
Figure 3. TMS320C31 Memory Map in Microprocessor Mode Showing Mailbox-Bypass Register
and FIFO SRAM Addresses
DMA Controller Description
The TMS32OC3 I DSP contains an on-board direct-memory-access (DMA) controller that minimizes the requirement
for the CPU to perform input/output operations. The TMS320C31 DSP block diagram is shown in Figure 4. Because
of the DMA controller, the TMS320C31 can operate with slow external memories, peripherals, or analog-to-digital
converters, for example, without slowing the computational throughput of the CPU.
Address and data buses are specifically dedicated to the DMA. As a result, there exists minimal conflict between the
CPU and DMA controller. Using its address generators, source and destination registers, and transfer counter, the DMA
controller can react to interrupts much like the CPU. Performing data transfers based upon interrupts received enables
the DMA to execute input/output transfers that are typically the task of the CPU. While the DMA is receiving and
transmitting data, the CPU is permitted to continue processing data.
A DMA transfer consists of two operations: reading from a memory location and writing to a memory location. These
read and write operations can be as a block or a single word. The DMA controller can read from and write to any location
in the TMS32OC31 memory map, including all memory-mapped peripherals.
3-71
Program
cache
(64 x 32)
ROY,
HOlOA,
STRB,
RJW,
031-00,
A23-AO
RESET
INT3-0
4(
-
+-
ClKIN
VOO
VSS
-
SHZ
-
X2!
l!
~
8
RAM
Block 1
(1K x 32)
OateBuaes
1
1:
-
lACK XF1-0
MCBl!
MP
X1
RAM
Block 0
(1K x 32)
'I'
..j
CPU
OMA
Integer!
Integer!
Floating-Point Floating-Point
Multiplier
AlU
Address
Generators
Generator 0
.........
Serial
PortO
II)
.'
:::I
III
i!III
Control
Registers
8 Extended-Precision
Registers
Address
D=l
.c
i .........
Timer
.........
Timer
0
Address
Generator 1
8 Auxllllary Registers
1
12 Control Reglstera
"'''---
~
Figure 4. TMS320C31 DSP ,Block Diagram
Initializing DMA Controllers With Mailbox-Bypass Registers
FIFO memories, such as the SN74ACT3641, typically channel data between a generic local or backplane bus and a
TMS32OC3l DSP. The FIFO collects incoming information from the bus and develops packets or vectors of data for
transfer to the DSP via the DMA controller (see Figure 5). The packet size of the stored data is easily defined by using
the FIFO programmable almost-empty or almost-full flags and, if necessary, its empty and full flags. Data transfers via
the DMA controller are performed block by block from the FIFO to the DSP or to off-chip memory such as RAM. The
DMA-controlled transfer is preferred for moving large blocks of data. Instead of using the DSP's CPU for each
single-word transfer, investing in a small amount of setup overhead allows the DMA to initialize the transfer of several
words. In this case, the DMA controller becomes the bus master and performs the block transfer while the CPU is not
using the external bus. The CPU is free to accomplish its primary task of performing mathematical operations.
Host
Processor
36
FIFO
SRAM
r------,
I
I
I
I
36
I
OMA
I
1-.....-t-......~l-7y...-+I~ Control
I
I
I
IL _ _ _
DSP
_ _ _ .JI
SN74ACT3641
Unidirectional FIFO
Figure 5. Using DMA Control to Transfer Large Data Blocks
3-72
Generally, the DMA controller requires the following information for data-block transfers: location of the data,
destination of the data, and size of the data block to be transferred. The DMA controller is initialized by using the FIFO
mailbox-bypass registers. This concept is shown in Figure 6. AJ; previously, mailbox-bypass registers are useful in
separating a control word from the data in a FIFO queue. In the example shown in Figure 6, the bypass registers of the
SN74ACT3641 FIFO provide the DMA controller with the block-length initialization before performing the block
transfer. At the same time, the mailbox-register status flags alert the DMA controller that the FIFO data is ready for
transfer. In other instances, the mailbox register can also store a destination address in the DSP memory for incoming
data.
In the earlier discussion, data flow through the mailbox register has been assumed to be in the bus-to-DSP direction.
However, because of the bidirectional nature of the mailbox feature, the Mai12 register (see Figure 5) can also be used
for transferring data in the DSP-to-bus direction. Many bus architectures support burst writes or have virtual addresses
that can use the mailbox-bypass register for initialization.
FIFO
Memory
FIFO Write {
LocaUon
Block 1
Date
•••
Bypass
Register
•••
Date Write Order
Block 1
Length
-+
Block 2
Length
(a) BU8-To-FIFO DATA FLOW
FIFO Read {
Location
FIFO
Memory
•••
Bypass
Register
•••
Initialize DMA With
Block Length
1tl1
Date Read Order
-+
DMA Transfer
(b) FIFo-To-BUS DATA FLOW
Figure 6. Using Mailbox-Bypass Registers to Initialize DMA Control
3-73
Conclusion
Mailbox-bypass registers are very useful in performing block-data transfers from a bus to a processing element or vice
versa. Integrating the 32- or 36-bit mailbox registers on board the FIFO chip significantly reduces the device count per
system. Likewise, implementing on-board mailbox registers with access timing similar to the FIFO SRAM also reduces
the requirement for control logic.
TI's DSP application-specific FIFOs, in addition to the other application-specific FIFOs with mailbox-bypass registers,
are summarized in Table 1.
Table 1. FIFOs Featuring Mailbox-Bypass Registers
3-74
DEVICE
ORGANIZATION
SPEED SORTS
MAXFREQ
MAX ACCESS
APPLICATION
SN74ACT3622
256x36x2
-15,-20,-30
67
11
DSP
SN74ACT3621
512x36
-15, -20,-30
67
11
DSP
SN74ACT3632
512x36x2
-15,-20,-30
67
11
DSP
SN74ACT3638
512x32x2
-15,-20,-30
67
11
DSP
SN74ACT3641
1Kx36
-15, -20, -30
67
11
DSP
SN74ACT3642
1Kx36x2
-15,-20,-30
67
11
DSP
SN74ACT3651
2Kx36
-15, -20, -30
67
11
DSP
SN74ABT3611
64x36
-15,-20,-30
67
10
High Bandwidth
SN74ABT3612
64x36x2
-15, -20, -30
67
10
High Bandwidth
SN74ABT3613
64x36
-15, -20, -30
67
10
Intemetworking
SN74ABT3614
64x38x2
-15, -20, -30
67
10
Intemetworking
Advanced Bus-Matching/
Byte-Swapping Features for
Internetworking FIFO Applications
Tom Jackson
Advanced System Logic - Semiconductor Group
:II
TEXAS
INSTRUMENTS
SCAA014A
3-75
IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to Its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtaln the latest version
of relevant information to verify, before placing orders, that the information being relied on Is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications',).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards. "
TI assumes no liability for applications assistance, customer product design, software performance, or
Infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or Implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-76
Contents
Title
Page
Introduction ............................................................................. 3-79
Conventional Bus-Matching Data Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-80
Tl's Bus-Matching Data Reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-81
Conventional Bus-Matching Data Writes ..................................................... 3-84
TI's Bus-Matching Data Writes ............................................................. 3-85
TI's Byte-Swapping Feature .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-86
Conclusion .............................................................................. 3-86
List of illustrations
Figure
Title
Page
Big-Endian and Little-Endian Fonnats ...... ~ ........................................... 3-79
2
Data-Read Cycle for 36-Bit to 9-Bit Bus Matching ........................................ 3-80
3
Bus Sizer ......................................................................... 3-81
4
Port-B Data-Read Cycle for 36-Bit to 9-Bit Bus Matching .................................. 3-82
5
Little-Endian Data-Output Structure .................................................... 3-83
6
Big-Endian Data Output ............................................................. 3-83
7
Big-Endian Data-Output Structure ..................................................... 3-83
8
Data-Write Cycle for 9-Bit to 36-Bit Bus Matching ........................................ 3-84
9
Port-B Data-Write Cycle for 9-Bit to 36-Bit Bus Matching .................................. 3-85
10
Big-Endian Fonnat of Byte Write ...................................................... 3-85
11
Byte Swapping ..................................................................... 3-86
3-77
3-78
Introduction
Bus matching and byte swapping are features that Texas Instruments (TI) has added to their intemetworking family of
application-specific, flrst-in flrst-out memories (FIFOs). The first two FIFOs available are the SN74ABT3614 and
SN74ABT3613. The bus-matching feature allows the user to dynamically select the desired bandwidth, either
long-word format (36 bits), word format (18 bits), or byte format (9 bits) for mixed-bus systems. Byte swapping allows
the user to reconfigure protocols for different microprocessor-based systems, such as big-endian format (i.e.,
RISe-based microprocessors such as the Me68000, IBM370) where the most signiflcant bit (MSB) is 0 or little-endian
format (i.e., elSe-based microprocessors such as iPAX, x86, DEe VAX) where the least significant bit (LSB) is 0 (see
Figure 1). The bus-matching and byte-swapping features can be used independently or in conjunction with one another,
which allows the user a wide range of possible solutions.
Motorola Microprocessor
(big endlan)
Intel r " Microprocessor
(little end Ian)
•
XOOO8
X0004
~------:-------
I-t-----------31
o
•
:~~:t1--------------:--------------o
31
(MSB)
(LSB)
Figure 1. Big-Endian and Little-Endian Formats
Intel is a trademark of Intel Corp.
3-79
Conventional Bus-Matching Data Reads
With the evolution of 32-bit microprocessors and digital signal processors (DSPs), designers must add large complex
discrete circuits to provide data continuity between mixed data-bus systems. A typical solution requires four 9-bitFIFOs
and considerable board space (s~ Figure 2).
ROCLK
Status
Flags
ROCLK
FIFO 1
9
00-08
Q1
ROEN1,OE1
Q1
09-017
FIFO 2
9
Q2
J
I
\
~
3B~e1_;)
I
i~-f
ROEN2,OE2
018-026
FIFO 3
9
Q3
Q3,Z
027-0~5
FIFO 4
Status
Flags
9
Q4,Z
Q4
9
I
L.-t
I
I
I
I
I
I
I
I
I
I
I
I
i
Q2,Z
1
0
1
0
10to-15 ns
~
KB~2_1>B--
~I
I
QO-Qa
Figure 2. Data-Read Cycle for 36-Blt to 9-Blt Bus Matching
To provide bus matching from a 36-bit bus to a 9-bit bus, access time and flag synchronization are critical issues due
to the combination of separate components. Figure 2 shows the required circuitry and associated timing diagram for a
conventional bus-matching operation. The fIrSt byte of the long word is written into FIFOl on 00-08. On the rising
edge of the read clock with read enable-l (RDEN1) and output enable-l (OEl) held high, the first byte of FIFO 1 (byte
1_1) is read out. During that first read cycle, the remaining three FIFOs must be disabled. Before reading the second
byte from FIF02 (byte 2_1), the read enables and output enables of FIFO 1 are asserted low, putting the FIFO outputs
into 3-state, which prevents any bus-arbitration problems. FIF01 must be disabled before FIF02 is enabled.
In addition to the associated propagation delays of enabling and disabling the FIFOs, the typical access time of a single
FIFO can range from 10 to 20 ns. To ensure proper device synchronization, the FIFO access time must be increased to
allow for the propagation delays of the control signals. The increased propagation time for data reads can cause a
bottleneck for data that is waiting to be written into the other FIFOs. This delay dramatically impacts system
performanCe and data throughput. If the timing parameters are violated, the result is bus contention and lost data. To
complete the long-word read, the cycle is repeated three more times. For subsequent long-word data reads, the process
begins with the second byte of FIFO 1 (byte 1_2). This data ping-ponging is prolonged and requires excessive access
times and data setUp and hold times to perform a single long-word read cycle. These factors contribute to reducing the
effective maximum operating frequency of the system.
3-80
Tl's Bus-Matching Data Reads
11 has designed the intemetworking FIFOs to provide the user a single-chip solution for dynamic bus matching, in
addition to fast data access times (ta - 10 ns). The bus-matching feature offers a flow-through architecture that maintains
port-to-port transparency and eliminates the need for any bus-arbitration control logic. Bus matching is performed with
the FIFO on the port B bus and can be configured in long-word format (36 bits), word format (18 bits), or byte format
(9 bits) for data reads from FIFOI or written to FIF02, in the case of the SN74ABT3614 bidirectional FIFO. Port-B
bus size can be changed dynamically and synchronous to CLKB to communicate with peripherals of various bus widths.
The bus-matching feature is implemented using the big-endian (BE) format and the port-B bus size-select (SIZO, SIZ1)
terminals (see Table 1).
Table 1. Bus Size-Select Terminals
TERMINAL NUMBER
PACKAGE
BE
SIZ1
12O-pin TOFP (PCB)
47
50
SIZO
51
132-pin POFP (PO)
132
129
128
The sizing function is performed on the output of port B after a long word has been written into the FIFO on port A (see
Figure 3). If an output register is not used (e.g., 9- or 18-bit data reads), no line terminations such as pullup resistors are
required due to the bipolar output structures of 11's advanced BiCMOS technology.
36
Sizer
Port B
Figure 3. Bus Sizer
By varying the_ assertion levels of the three control terminals, five different bus-format configurations can be selected
(see Table 2).
Table 2. Bus Configurations
BE
SIZO
SIZ1
X
L
L
L
H
H
L
H
H
L
L
L
H
L
H
BUS CONFIGURATION
Long-word size
Word size - big endlan
Word size -little endian
Byte size - big Bndlan
Byte size -1!We endlan
3-81
-----------
The byte-order arrangement of data that is read from or written to the FIFO can be changed synchronous to the clock.
The bytes are rearranged within the long word, but the bit order within the bytes remains constant. The byte-swapping
feature is implemented by asSerting port-B byte-swap select (SWO, SWl) terminals (see Table 3).
Table 3. Byte-Swap Select Terminals
TERMINAL
NUMBER
PACKAGE
SW1
SWO
12o-pln TOFP (PCB)
48
49
132-pin POFP (PO)
131
130
The example as shown in Figure 4 takes the conventional 36-bit to 9-bit bus-matching example as shown in Figure 2
one step further by incorporating the byte-swapping feature. A timing diagram of a little-endian, byte-size, byte-swap
data read from port B using the SN74ABT3613 unidirectional FIFO is shown in Figure 4. With a 36-bit-long word
written into memory from port A, data read can be performed. On the rising edge of CLKB with the port-B chip select
(CSB) asserted low, the size and swap functions can be selected. The littIe-endian format is chosen by asserting BE high.
Byte size is selected by asserting SIZI high and SIZO low. On the second clock cycle, the byte swap is performed by
asserting SWI low and SWO high for one clock cycle.
ClKB
ENB
~~~
~~~~~~I I
I
I
I:
taU(SWl
~
lh(sZ)~
~.
I
I
I
l.-.:- lh(8W)
~
~
$
No Operation
I
~
ij
I
.
I
I
tau(EN) --*-t!
I I
I
I
I
~i;....:hI~,-h.~~~~A
!I
~ !
I
I
lh(SZ,~
I
---l4--tI
BE_
I
I
,.,..
!I
~
I
I
!I
I
~
~
I
I
Not
tau(PO)
~
tan
BO-B8
t
---t-+I
~
j4- ta ~
*
Previous Data
SIZO = Hand SIZ1 • H selects the mail1 register for output on BO-B35.
Figure 4. Port-B Data-Read Cycle for 36-Blt to 9-Blt Bus Matching
I
IcIIS~
Read 4
j--
During the second clock cycle, the first byte appears on the output bus BO-B8. After four successive read cycles are
completed, the entire long word is parsed out onto the bus in four 9-bit data packets (see Figure 5). In byte-size or
word-size data reads, the unused bytes hold the last FIFO output values. After the four bytes are read, the configuration
can be dynamically changed.
Example: Little Endlan, Byte Size, Byte Swap
BE = H, SIZ1 =H, SIZO= L,SW1 =L,SWO= H
Firat Read
A
••
•
B
c
Fourth Read
D
Figure 5. Little-Endian Data-Output Structure
If the example shown in Figure 4 is configured for big-endian format, the data is output on bus B27-B35 (see Figure 6
and Figure 7). No line termination is required for the unused data outputs. This is a dramatic improvement, not only in
design ease, but in performance over the conventional data ping-ponging technique shown in Figure 2.
B27-B35 ------«PrevloU8 Dats
X
Read 1
X
Read 2
X
Read 3
Figure 6. Blg-Endlan Data Output
Example: Big Endlan, Byte SIze, Byte Swap
BE = L, SIZ1 = H, SIZO = L, SW1 = L, SWO = H
I
I
I
I
A
Firat Read
B
c
•••
D
Fourth Read
Figure 7. Blg-Endlan Data-Output Structure
X
Read 4
r-
Conventional Bus-Matching Data Writes
Conventional bus-matching data writes experience the same timing restrictions as data reads. The example in Figure 8
shows the circuitry required for 9-bit to 36-bit data writes. Just as in the example in Figure 2. four 9-bit FIFOs are
required in addition to an extra control-logic block to synchronize all the write enables.
WRTCLK
Status
Flags
QO-Qa
Q9-Q17
9
FIFO 1 1-+-----...,
9
Q1
FIFO 2
I-+----i-...,
9
W3
Q18-Q26
FIFO 3 1-1-----1---l
Q3
9
W1
W2
W3
W4
W4
WEN Control Logic
Q27-Q35
Status
Flags
FIFO 4
1------+----'
9
Q4
9
Figure 8. Data-Write Cycle for 9-Bit to 36-Blt Bus Matching
The write-control logic controls each data write in a round-robin style. The control logic consists of a bank of flip-flops
that generate the appropriate write-enable signal. After four successful data writes. a long word can be read from the
FIFO bank. However. the FIFO bank must have its full- and empty-status flags monitored to ensure data integrity. The
empty status is monitored from FIF04. the last FIFO in the chain. Upon an empty signal. additional data reads are
immediately disabled. The full status is monitored from FIFO!. the tIrst FIFO in the chain. When a full status is
indicated. further data writes are disabled. To ensure maximum performance. the status flags require fast propagation
delays for proper data synchronization. Otherwise. data overwrites can occur. corrupting the FIFO data. or additional
wait states must be introduced into the system. Due to the synchronization issues. additional bus control or interrupts
become extremely difficult by using the half-full. almost-full or almost-empty flags. This also limits FIFO operations.
The data setup and hold times also must be increased to ensure there are no bus contentions during a write operation.
TI's Bus-Matching Data Writes
The timing diagram for perfonning a little-endian, byte-size, byte-swap data write to port B of FIF02 using the
SN74ABT3614 is shown in Figure 9. By implementing TI's SN74ABT3614 bidirectional FIFO in a design, bus
matching can be performed in either direction without the need for additional glue logic or loss of system performance.
elKB
FFB
(HIgh)
I
I
I
I
I
I
I
I
thlEN) -+I 14-
IsUIEN)=ri
1. :
lj"---
~~I--------------------------------------------------------~: I
W/RB
ENB
SW1, SVo/O
mmllmm
II
SIZ1,SIZO
Write 1
t SIZO =Hand SIZ1
Write 2
Write 3
Write 4
=H wrHes data to the mail2 register.
Figure 9. Port-B Data-Write Cycle for 9-Bit to 3~Bit Bus Matching
On the rising edgeofCLKB with the portB selected (CSB), the size and swap functions can be selected. The little-endian
format is chosen by asserting BE high. Byte swap is selected by asserting SIZO high and SIZllow. These assertion levels
are maintained for the entire write cycle. On the second clock cycle, the byte swap is performed by asserting SWllow
and SWO high for one clock cycle. The data is then written into BO-B8, since the little-endian format has been selected.
If Figure 9 is configured for big-endian format, the data is written into B27-B35 (see Figure 10). No line tennination
in the form of pullup resistors is required for the unused data inputs.
B27-B35
WrIte 1
Write 2
WrIte 3
WrIte 4
Figure 10. Blg-Endian Format of Byte Write
3-85
TI's Byte-Swapping Feature
TI has designed the intemetworking FIFOs to provide designers maximum flexibility and ease of use. In addition to the
bus-matching feature, a byte-swapping option has been added. The byte-swapping feature allows communication
between systems with mixed bus protocols such as those using by RISe and else microprocessors. The previous
examples of TI's bus matching (Figure 2 through Figure 10) have included the byte-swapping function to demonstrate
the true power and flexibility these features provide when implemented together.
Byte swappin:g is performed on port B of the FIFO (see Figure 11) after the bus-matching function has been executed.
Either feature can be implemented separately depending on the system requirements.
PortA
A
B
c
o
PortB
9
9....
,
9,
9
FIFO
SN74ABT3614
9,
9
,
o
c
9
,
B
9
,
A
i
i
Byte Data
Byte Swap
Figure 11. Byte Swapping
As with the bus-matching function, there are several variations of byte swapping, depending upon the assertion levels
of the port-B byte-swap select terminals (see Table 4).
Table 4. Byte--Swapping Option
SWO
SW1
L
L
H
H
L
H
L
H
BUS CONFIGURATION
No swap
Byte swap
Word swap
Byte-word swap
Bus matching and byte swapping are performed in the following sequence for all data reads; the 36-bit word is first read,
the swap is performed, followed by the bus-size function. The converse is true for data writes.
Conclusion
The ability to dynamically select the desired bus configuration and format is a very useful feature for today's designs.
Many systems, such as networlc switches and routers, implement high-speed backplanes that are typically 32 to 36 bits
to ensure maximum bandwidth for data; however, there are many 8-bit and 16-bit controllers and buses in existence.
TI's bus-matching feature ensures a flow-through, high-speed architecture that permits multiple logical permutations;
There is no longer the need for rerouting bytes on buses and manually controlling bus arbitration through a large and
costly discrete solution. The SN74ABT3613 FIFO provides a unidirectional datapath with bus matching and byte
swapping on port B. The SN74ABT3614 provides a full bidirectional datapath and supports bus matching and byte
swapping in either direction. Both of these FIFOs feature TI advanced-clocked architecture ina space-saving single-chip
solution that offers a maximum clock speed of 67 MHz with 10-ns access time.
Parity-Generate and
Parity-Check Features
for High-Bandwidth-Computing
FIFO Applications
Tom Jackson
Advanced System Logic - Semiconductor Group
~1ExAs
INSTRUMENTS
SCAA015A
3-87
IMPORTANT NOTICE
Texas Instruments' (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant Information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or Implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
Contents
Title
Page
Introduction ............................................................................. 3-91
Parity-Generate Feature ..................... : ............................................. 3-91
Using Parity Error to Force an Exception ..................................................... 3-93
Conclusion .............................................................................. 3-94
3-89
3-90
Introduction
Parity-generate and parity-check features are available in both the intemetworking family of first-in, first-out memories
(FIFOs), SN74ABT3614 and SN74ABT3613, and the high-bandwidth-computing family, SN74ABT3612 and
SN7 4ABT3611. Parity generate and parity check are needed in high-bandwidth and high-speed computing applications
where demanding data integrity levels are required. All of TI's 36-bit FIFOs have bidirectional mailbox registers that
allow quick access to data by bypassing the FIFO static random-access memory (SRAM) core. The same input/output
(I/O) is shared between the mailbox registers and the FIFO data registers that allow parity generate and parity check on
both the FIFO memory data and the mailbox-register data. The parity-generate and parity-check features are designed
for fault-tolerant systems, such as those in computing and telecom that require error-detection techniques, in addition
to many of today's microprocessors that have provisions for parity detection.
Parity-Generate Feature
The parity-generate feature enables the user to generate odd or even parity in the most significant bit (MSB) of each byte
on either port A or port B of the FIFO. Odd and even parity are defmed as follows:
Odd parity: The parity bit is set to one for an even number of ones, including the parity bit.
Even parity: The parity bit is set to zero for an odd number of ones, including the parity bit.
Parity is generated for data reads from either port A or port B of a bidirectional FIFO by asserting parity generate A
(PGA) and parity generate B (pGB), respectively ~CSAIB low, PGAIB high, ENA/B high). In Figure I, a write to a
FIFO or mailbox register stores the levels applied to all 36 inputs, regardless of the state of the parity-generate inputPGB.
When data is written to a port, the lower eight bits of each byte are copied to the parity-generate tree. These bits are then
used to generate a parity bit according to the level of the ODDIEVEN select pin (see Table 1). When PGB is asserted,
the results of the parity generator are written to the MSB of the output register. If PGB is low, the original contents of
the MSB of the byte under consideration are transferred to the corresponding location in the output register.
Memory
Odd/Even
PGB
P
8
Data
Input
Output
Register
BO-B8
Parity
Generator
Memory Out
Figure 1. Parity-Generate Circuit
3-91
Table 1. Parity-Generate Input Pins
PACKAGE
PEFA
PIN NUMBER
PEFB
ODD/EVEN
120-pin TOFP (PCBl
39
53
44
132-pin POFP (POl
9
125
3
Each mailbox register has an associated parity-generate and check (gen/check) circuit (see Figure 2) that enables parity
to be generated and checked on either port of the FIFO. The circuit that generates parity for the Maill mailbox register
is shared by the port-B bus (BO-B35) and generates and checks parity for the FIFO data bus, as well as to check parity
for the Mail2 mailbox register. The circuit that generates parity for the Mail2 mailbox register is shared by the port A
bus (AO-A35) to check parity for FIFO data and mailbox register. The shared parity trees of a port generate parity bits
for the data in a mailbox register when the port write/read select input is low, port-mail select input is high, and
port-parity-generate select is high. Generating parity for mail register data does not change the contents of the register.
cLKA-----I
CSA - - - - - I Port-A
r---r=:::::,=========
I
wiifA
ENA - - - - - I Control
Lagle
MBA - - - - - I
Parity ,J-I....- - - - ,
,..-_-, ~++=++:""'__...r-"jM~a;nIli"1-1+'1
~Gen/Chec..:J+,
RSf -
~:E~ -
C
1===;~IL!R~eg~l~ster~..J-+9;:::==~_I::;;==~~.......__ PGB
Devlce
r-~ ---------~-=r~~~
Control
~ ~
I
I
i
i _
64 x 36
a:
rr..
SRAM
IS
... ~e
I"" III
c!
I "-..
II
I
Q)
a.,c
36t++-~11+f j
AO-A35--....-
:M:B:F:1
PEFB
I
Write
II
""-- -
I
Read
I Pointer Pointer I
"t"t
I.- Hf~t,
I
I
..
I
! r:I
36
I
II
...........-BO-B35
I
FF---+--~t+~~I~---~iSte~N;.~F~la~g.,-----~I~-~++~---AEFE
AF---4---rI1--~'~~-IIL-~LO~)g~llc~~r------r-'-ttl1l1----
L~~-----4---------J
I
FSO
I
FS1----~~.-------I
~
I
ProgrammableFlag
Offset Register
J
PGA-----tt====~~~~~b,~r_~~~_,I-~--~
~
.,~I
Mall2
:
~ Parity _~
PEFA _ _ _ _~~~~.-_-_-_-_·_...
1IcGe=nJ::C:.:hec:::Jkl
I
MBF2--------.-------~
Register
........
..---CLKB
..---CSB
Port-B ......
Control "'---W/RB
Lagle "'---ENB
"'---MBB
......
--~
Figure 2. SN74ABT3611 Mailbox Registers and Associated Parity Gen/Check Circuits
Functional Block Diagram
The parity-generate and parity-check features allow the user to select odd or even parity and to passively check the results
of all incoming data to either port A or port B of the FIFO without disrupting normal operations. Both port A (AO-A35)
inputs and port B (BO-B35) inputs have four 9-bit parity trees to check the parity of incoming or outgoing data (see
Figure 3). Parity is checked on the ninth MSB of each byte.
3-92
Odd/Even - - - - ,
BE----,
Odd/Even
SIZ1
SIZO
A35
9
B35
ER
ER
ER
ER
ER
ER
ER
ER
9
9
9
9
9
9
9
AO
BO
Figure 3. Parity Trees
A parity failure on one or more bytes of the input bus is indicated by a low level on the port parity-error flag (PEFA,
PEFB) (see Table 2). The parity-error flags can be ignored if this feature is not desired.
Table 2. Parity-Error Input Pins
PACKAGE
PIN NUMBER
PGA
PGB
ODD/EVEN
120-piri TOFP (PCB)
38
54
44
132-pin POFP (PO)
10
124
3
The user can choose odd or even parity by asserting the ODDIEVEN input or allow the FIFO to default to even parity.
In this manner, the user can select the parity format that best fits the application requirements. Since foUr 9-bit parity
trees are used, it is possible to implement the parity-check function on the bus-configuration port in conjunction with
the bus-matching feature of the intemetworking FIFOs. In this manner, any bus width that has been selected, 9-bit
through 36-bit, can have parity checked. The parity-checking circuit is designed to ignore all error flags that may be
generated on unused bytes.
As in parity generate, the four parity trees used to check the port-A inputs are shared by the Mail2 mailbox register.
Port-B inputs on bidirectional FIFOs are shared by the Maill mailbox register (see Figure 2); therefore, parity errors
are detected before the data is entered into the FIFO SRAM core.
Using Parity Error to Force an Exception
Although the parity-check feature is passive, it permits the designer to disregard data before it is written into the FIFO
SRAM core. This type of functionality is easily implemented by the circuit shown in Figure 4. Since parity is checked
on the inputs before being written to the FIFO, it is possible to capture the erred data and force an exception. Figure 4
shows a data error that has been detected by a low onPEFA. The associated propagation delay, [tpd(D-PE)] of a valid error
flag is IOns for the -15 speed sort. This allows adequate time for a fast programmable logic device (tpd PLD) to disallow
a data write prior to the data becoming valid. If no parity error is detected, the data write is performed. If FIFOs with
slower speed sorts (-20, -30) are used, the associated propagation delay is increased. This method eliminates the need
for external counters to track the erroneous data through the FIFO to the output. By forcing an exception, the parity is
captured and the clock cycle passes without writing the datil: to the FIFO memory core.
3-93
CLK
WRTCLK
T
WEN
PLD
PEFA
~ ~:
WRTCLK
I
I
\
--./
tau
j----
II
W E N _ " " T ' " :_ __
tpd(pLD)
PEFA
~I
I
"'''''''''''''''''''~'''''''''''''''''''''''''''''''''''''''''''~'''''''''7''7\ : ~----':----.
DATA
~
.
tpd(D-PE)
~.I
~~,.,.,..,..,..,..,.~""""""..,..,..,..,..,.,.,..,..,..,..,.~
i
14-
I
:
tpd(D-CLK) ~
Figure 4. Parity-Error Exception Circuit
Conclusion
As systems become more integrated and bus speeds increase, there is a growing need to ensure data integrity.
When parity generate or parity check is required by dynamic random-access memory (DRAM) refresh cycles, bus noise,
or other card-to-card performance issues, U's parity-generate and parity-check features provide a high-speed,
space-saving alternative.
3-94
FIFO Applications
Page
Multiple-Queue First-In, First-Out Memory SN74ACT53861 ............................. 3-97
Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors ............ 3-121
FIFOs With a Word Width of One Bit ................................................ 3-141
Internetworking the SN74ABT3614 ................................................. 3-161
High-SpeEld, High-Drive SN74ABT7819 FIFO ..................•..................... 3-181
SPARC MBus-to-Futurebus+ Bridge Using the Texas Instruments Futurebus+ Chipset .... 3-193
1K x 9 x 2 Asynchronous FIFOs SN74ACT2235 and SN74ACT2236 .................. 3-207
64-Byte FIFOs SN74ALS2232A and SN74ALS2233A ......•.......................... 3-217
3-95
3-96
Multiple-Queue
First-In, First-Out Memory
SN74ACT53861
Peter Forstner
Semiconductor Group
SCAA026A
~ThxAs
INSTRUMENTS
3-97
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of Its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products In such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringenient of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3--98
\
Contents
TItle
Page
Introduction ............................................................................ 3-101
Main Areas of Application . ................................................................ 3-102
The Multi-Q FIFO ....................................................................... 3-103
Construction of the Multi-Q FIFO ......................................................... 3-103
Configuration Registers ............................................................... 3-105
Allocation of Queues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-105
Cells Instead of Words of Data .......................................................... 3-106
Flags ......................................... ; .................................... 3-108
Programming ....................................................................... 3-109
Extension of Word Width ................................................................ 3-111
Progranuning Examples ................................................................. 3-115
Applications ............................................................................ 3-117
Summary ............................................................................... 3-120
3-99
List of IDustrations
Figure
1
TItle
Page
FIFO Data Flow ......................•...............•..•......................... 3-101
2
A1M Te1eco=unications Exchange System Block Diagram . .. • . . . . . . . . . . . . . . . . . • . . . . . . . .. 3-102
3
A1M-Header Structure ....................................••....................... 3-103
4
Multi-Q FIFO Functional Block Diagram ......•.......•..•....•.............•.......... 3-104
5
Data Stream With Odd Cell Size ..............................•....................... 3-106
6
Writing Cells Into the FIFO ..........................•.. '.' . . . . . • . . . . . . . . . . . • . . . . . • . . . 3-107
7
Faulty Writing of Cells Into the FIFO: ISOC Comes Too Soon ... .. . . . . . .. . . . . . .. . . . .. .. .. .. 3-107
8
Faulty Writing of Cells Into the FIFO: ISOC Comes Too Late or Not at All .................... 3-107
9
Reading Cells Out of the FIFO ....................................................... 3-108
10
Hysteresis of the PFI Flags With Configuration Registers PFl_W and PFl..R, .................. 3-109
11
Connection of a Microcontroller to the Auxiliary Bus ..................................... 3..:.109
12
Extension of Word Width With 18-Bit or 36-Bit Input and/or Output Data .............•....... 3-112
13
Extension of Word With 9-Bit Input Data ............................................... 3-113
14
Data Flow of an A1M Data Stream in Two Multi-Q FIFOs ........... ,...................... 3-114
15
A1M-ExchangeReceivingUnit ...................................................... 3-117
16
A1M-Exchange Transmitting Unit .................................................... 3-117
17
Connection of a Multi-Q FIFO to a Receiving Unit
Using an 8-Bit or 16-Bit UTOPIA Interface With One Queue ............................... 3-118
18
Priority-Controlled Connection of a Multi-Q FIFO to a Receiving Unit
Using an 8-Bit or 16-Bit UTOPIA Interface ............................................. 3-118
19
Connection of a Multi-Q FIFO to a Transmitting Unit
Using an 8-Bit or 16~Bit UTOPIA Interface With One Queue .............. " ...... , •....... 3-119
20
Priority-Controlled Connection of a Multi-Q FIFO to a Transmitting Unit
Using an 8-Bit or 16-Bit UTOPIA Interface ............................................. 3-119
21
Switching Matrix With Bottleneck Between Two Switching Elements ........................ 3-120
List of Tables
Table
1
2
3
4
5
6
7
8
3-100
,TItle
Selecting the Queue When Reading the FIFO.. . . . .. . .. .. .. . . .. .. .. . . .. . .. . .. .. . . .. . . . ...
Configuration Registers . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Port-Control Register PORT ..................•....•..................••........•....
Multi-Q FIFO Flags ...................•............................................
Configuration-Registers Access Order .................................................
Example of Configuration Registers Programmib.g: 18-Bit W:rite, 18-Bit Read .................
Example of Configuration Registers Programming: 9-Bit Write, 18-Bit Read ..................
Example of Configuration Registers Programming: 18-Bit Write, 9-Bit Read ..................
Page
3-104
3-105
3-106
3-108
3-11 0
3-115
3-115
3-116
Introduction
This application report presents a detailed description of the versatile functions of the SN74ACT53861 multiple-queue
(Multi-QTM) first-in, first-out (FIFO) memory. Examples of circuits show how the device can be controlled and cascaded.
Typical application examples show how the device can be used in asynchronous transfer mode (ATM)
telecommunications exchange systems.
Memories are indispensable circuit components of digital-system subassemblies. There are a large number of memories
in various configurations for many application requirements. Each memory is suited for specific and specialized
applications.
One of these specialized memories is the FIFO memory, which provides intermediate storage of data being transferred
between two electronic systems. The designation FIFO indicates how the data flows. A FIFO has separate data
input and data output; however, the first word of data written into the memory is the first to leave when it is read
(see Figure 1). Within the FIFO, words of data wait in a data queue. If a FIFO is configured between two systems that
are working asynchronously, the FIFO must be able to manage the synchronization of the data flow to both systems to
prevent metastable situations.
I
Input Data
I
II
FIFO
"'V
I
Stored Data
I
t
I
Stored Data
I
't
I
I
Stored Data
•
••
Stored Data
I
I
t
I
Stored Data
I
't
I
Stored Data
L
Output Data
I
U
J
Figure 1. FIFO Data Flow
FIFOs differ from one another iIJ. their word widths, memory capacity, and in the way they are controlled. Texas
Instruments (TI) offers FIFOs with word widths from 1 to 36 bits and memory capacities from 64 to 4096 words. Because
FIFOs have alternative methods of control, TI offers strobed FIFOs and clocked FIFOs. A detailed description of the
various methods of controlling FIFOs can be found in other TI application reports. The various word widths and memory
capacities available are described in the 1996 High-Performance FIFO Memories Data Book, literature number
SCADOO3C.
In addition to standard FIFOs, versions for special purposes have been designed for specific applications. The TI
Multi-Q FIFO is an application-specific FIFO designed for ATM telecommunications exchange systems.
Multi-Q is a trademark of Texas Instruments Incorporated.
3-101
Main Areas of Application
The SN74ACT53861 Multi-Q FIFO is designed specifically for ATM telecommunications exchange systems.
As shown in Figure 2, ATM telecommunications exchange systems can have three functional parts:
• Receiving unit (one per channel)
• Switching matrix
• Transmitting unit (one per channel)
The ATM used for data transmission supplies the receiving unit with digital information, which is usually apportioned
in cells having a length of 53 bytes. Each cell consists of a 5-byte cell header and a 48-byte payload. The cell header
!
includes:
• Ultimate destination: virtual channel identifier (VCI)
• Immediate next destination, i.e., the next ATM exchange installation through which the ultimate destination
is reached: virtual path identifier (VPI)
• The type of information contained in the cell: payload type (PI')
• The importance, or priority, of the cell: cell-loss-priority (CLP) bit
• Error-correction controller: header error control (HEC)
In certain applications, extending the cell header by one to two bytes provides the ATM exchange installation with
internal information (tagged cells) (see Figure 3).
Interfaces
•
Interfaces
Switching Mstrlx
•
•
•
•
•
Controller
Figure 2. ATM Telecommunications Exchange System Block Diagram
3-102
Bit:
8
7
6
4
5
2
3
User Definable
VPI
VCI
VPI
2
3
VCI
PT
VCI
HEC
I
CLP
4
5
Figure 3. ATM-Header Structure
If delays occur because transmission channels in the ATM exchange are not available, the Multi-Q FIFO allocates cell
priorities, known as quality of service (QOS), by interpreting the PT infonnation and the CLP bit in the cell header. Data
that is critical as to the time taken for transmission, such as audio or video signals, is swept more rapidly through the
ATM exchange than, for example,less critical computer data. If the CLP bit is set to 0, the cell contains important data
that must reach its destination; whereas cells with the CLP bit set to 1 can be deleted. In a digital ATM exchange system,
a priority control for cell transmission must be implemented.
The cells being received arrive asynchronously to the clock signal of the exchange system; therefore, synchronization
of the input data stream to the system clock is necessary.
The Multi-Q FIFO solves synchronization problems and controls transmission priority with minimal complexity. The
architecture of this FIFO, unlike conventional FIFOs, is not based on words of data but on cells. This device can control
up to three priorities. The writing of the input data can be perfonned completely asynchronously with respect to the
reading of the output data.
The Multi-Q FIFO
The most remarkable feature of the Multi-Q FIFO is that memory can be allocated to three independent queues. These
queues allow the implementation of three QOS priorities. .
Construction of the Multi-Q FIFO
Figure 4 shows the functional block diagram of the Multi-Q FIFO, which is clocked; i.e., it has inputs for free-running
write ~d read clocks. Write accesses occur at the rising edges of the write clock when one of the three write-enable-x,
(WRTENx) (x - 1,2, or 3) lines is set. Read accesses are implemented at the rising edges of the read clock by setting
the read-enable (RDEN) line. Reading or writing stops when a low level is applied to WRTENx or RDEN. For writing
operations, the three control lines, WRTENx per queue, are individually brought out. The control lines for write accesses
are operated by a multiplexer. The desired queue is chosen with MUXO and MUXI selecting access to the chosen queue
using RDEN (see Table 1).
Before use, this device must be reset by four rising edges of the write clock (WRTCLK) and four rising edges of the read
clock (RDCLK) while the reset input (RST) is high.
3-103
Table 1. Selecting the Queue When Reading the FIFO
MUX1
MUXO
0
0
SELECTED QUEUE
Queue 1
0
1
Queue 1
1
0
Queue 2
1
1
Queue 3
POE
DS
RiW
-BREQ
P0-P7
DWRDY
...
WRTCLK
WRTEN1
WRTEN2
WRTEN3
-ABRT
Auxiliary-Bus
Control
8
+
8
I
I
.....
.....
.....
......
FF2
PF3
FF3
---------------
...
Queue2
...
b
r-"I
:;
Q,
-
.5
1
2
4096 x 18
Dual-Port
SRAM
In 16
256 x 18
Divisions
15
16
,....
CR3
iH &01
~
..
4-
&~I
r-+-
~
~
iii!
Read-Address Generstlon
~
'a:;!
it;
&0
~
Figure 4. Multl·Q FIFO Functional Block Diagram
3-104
CR1
.... I
Write-Address jleneratlon
....., T-
MUXO
MUX1
RDEN
CR2
r-+-
~
RDCLK
OSOC
.
Queue3
I
+f-+__ f-+-
Flags
Queue1
DO-D17
RST
T
PF1
FF1
I
Configuration
Registers
ISOC ..... - r - -ALER ""'""-
PF2
Reset
Logic
-
~
OE
QO-Q17
Configuration Registers
Eleven configuration registers allow matching the FIFO to requirements of a particular application (see Table 2). These
configuration registers can be written to and read from using a microcontroller through the auxiliary-bus control
interface.
Table 2. Configuration Registers
REGISTER
SYMBOL
REGISTER NAME
NO. OF DEFAULT PROGRAMMABLE
BITS
VALUE
RANGE
FUNCTION
Port control
5
0
Bit-slice control
Chooses the data input and output bus size and
format. Controls output byte destufling.
QU
Queue 1 length
5
a
0-16
Defines the number of256 x 18 memory blocks
for Queue 1
QL2
Queue 2 length
4
6
0-15
Defines the number of 256 x 18 memory blocks
for Queue 2
QL3
Queue 3 length
4
2
0-15
Defines the number of 256 x 18 memory blocks
for Queue 3
Cell size
6
27
10-32
Defines the cell size in 18-bit words
PF1_W
Programmable flag 1,
write threshold
9
71
0-409
Defines the number of cells in Queue 1 to set
PFllow
PF1_R
Progremmable flag 1,
read threshold
9
70
1-408
Defines the number of cell~ in Queue 1 to set
PFl high
PF2_W
Programmable flag 2,
write threshold
9
51
0-383
Defines the number of cells in Queue 2 to set
PF210w
PF2_R
Programmable flag 2,
read threshold
9
50
1-382
Defines the number of cells in Queue 2 to set
PF2 high
PF3_W
Programmable flag 3,
write threshold
a
13
1-383
Defines the number of cells in Queue 3 to set
PF310w
8
12
0-382
Defines the n':lmber of cells in Queue 3 to set
PF3 high
PORT
CLSZ
PF3_R
Programmable flag 3,
read threshold
Allocation of Queues
The Multi-Q FIFO memory consists of 4096 IS-bit words that have a maximum of three independent queues. These
queues can be called up to control up to three QOS priorities of ATM cells. Using configuration registers QL1, QL2,
and QL3, the sizes of the individual queues can be allocated in steps of 256 IS-bit words. The initial value of QL1 = S
if Queue 1 has a size ofS x 256 - 2048 IS-bit words. The development engineer has access only to configuration registers
QLI and QL2 and can only determine the size of the fIrst two queues; after that, the Multi-Q FIFO automatically reserves
the part of the memory that is still available for the third queue. Programming queue lengths of zero allocates the memory
to one or two queues.
The word width of the memory is IS bits; however, the development engineer can choose between 9-bit and I8-bit access
when reading and writing. In these cases, the bus widths for reading and writing operations can be different. For example,
it is possible to write with 9-bit access but implement the reading cycle with a word width of 18 bits. If the 9-bit access
is chosen, the FIFO can write the fll'St 9-bit word to the lower signifIcant half of the IS-bit memory and the second 9-bit
word to the higher signifIcant half (little endian). Alternatively, this order can be reversed (big endian). The
programming for write accesses is performed in the configuration register PORT using bits INSIZ, OUTSIZ, and INBE
(see Table 3). With read accesses, the 9-bit data word is output on bits Q8-QO in little-endian data format and on the
bits Q17-Q9 in big-endian format. In this case, the hardware wiring determines the data format; whereas with the input
data, the software programming determines the data format.
3-105
Table 3. Port-Control Register PORT
OUTSTF
OUTSIZ
Blta
INST
BIt2
INBE
Bit 1
INSIZ
X
X
X
0
18-blt input bus
X
X
0
0
1
9-bit input bus with an even number of bytes
per cell in little-endian data format
X
X
0
1
1
9-blt input bus with an even number of bytes
per cell in big-endian data format
X
X
1
0
1
9-bit input bus with an odd number of bytes per
cell In little-endian data format
X
X
1
1
1
X
0
X
X
X
18-bit output bus
Bit 4
X
FUNCTION
Bit 0
9-bit input bus with an odd number of bytes per
cell in big-endian data format
0
1
X
X
X
9-bit output bus with an even number of bytes
percell
1
1
X
X
X
9-blt output bus with an odd number of bytes
percell
Cells Instead of Words of Data
The Multi-Q FIFO flags (e.g., empty, full, etc.) indicate the presence or the absence of complete cells. The cell size can
be set with the configuration register CLSZ in the range of 10 to 3218-bit words to allow a cell size of 20 to 64 bytes.
The Multi-Q FIFO can also be programmed to odd cell sizes (e.g., S3 bytes) with 9-bit writing access by byte stuffing
and with 9-bit reading access by removing the stuffmg bytes (see Figure S). This property can be chosen in the
configuration register PORT with the help of bits INST and OUTSTF (see Table 3).
8-Blt Input Data Stream
53-Blt Cell
53-Bit Cell
~
8-Blt Output Data Stream
18-Blt Data Stream In FIFO
Multl·Q FIFO
53-Bit Cell
53-Blt Cell
~
Stuffing Bytes
Figure 5. Data Stream With Odd Cell Size
When writing into acell, the Multi-Q FIFO must be informed of the beginning of a cell with the input start-of-cell (ISOC)
signal, as shown in Figure 6. At the rising clock-pulse edge when the first data word of a cell is written into the FIFO,
both ISOC and the valid data word must be set high. If a cell has been written completely into the FIFO, ISOC must again
be set with the beginning of the next cell. The FIFO compares the beginning of a cell, which has been indicated, with
the expected cell beginning in accordance with the previously implemented programming of the cell size and indicates
any fault at the alarm (ALER) output (see Figure 7 and Figure 8). If a fault of this kind occurs and ALER is low, the fault
must be reset with the abort (ABRT) input signal before further cells can be written into the FIFO.
When reading from cells, the output start-of-cell (OSOC) signal indicates the beginning of a cell. OSOC can be used
to control subsequent parts of the circuit (see Figure 9).
3-106
"
II
~'
Figure 6. Writing Cells Into the FIFO
Do-D18
(f
ALER
ABRT
II
If
II
I
I
I
I
II
\.
I
I
I
I
\..LI
Figure 7. Faulty Writing of Cells Into the FIFO: ISOC Comes Too Soon
Do-D18
I
II
{
,f
I
I
I
(f
ALER
ABRT
II
I
,tI
\..lJ
Figure 8. Faulty Writing of Cells Into the FIFO: ISOC Comes Too Late or Not at All
3-107
Figure 9. Reading Cells Out of the FIFO
Flags
Table 4 defmes the functions of flags that indicate the extent to which the memory is filled in the Multi-Q FIFO. A fonn
of hysteresis is implemented with the programmable flags PFl, PF2, and PF3. The number of requir~ cells in Queue 1
to set PFI low is determined using the configuration register. At subsequent readout, PFI is reset to high as soon as the
number of the cells still remaining in the memory reaches the value PF1_R in the configuration register. The extent to
which the FIFO is filled can be set with configuration register PFl_W. From that point, ATM cells whose CLP bit is set
to 1 are erased and no longer written into the FIFO. Only when the FIFO is again filled below the value in configuration
register PFCR does an external cell-priority logic accept the writing in of cells whose CLP bit has a value of 1.
The purpose of adjustable hysteresis is explained using as an example a standard FIFO having only one simply
programmable almost-full (AF) flag without hysteresis. H the FIFO is filled to the predetermined value, the FIFO
displays this at the AF flag output This process is repeated when the FIFO again exceeds the predetermined value and
ignores CLP - 1 cells. As a result of the reading out of a cell, the AF flag is reset and the external cell-priority logic
immediately allows the storage of CLP - 1 cells. At this point, the external cell-priority logic switches between
acceptance and rejection of CLP - 1 cells.
The implementation of hysteresis in the Multi-Q FIFO allows the user to suppress continuous switching between
acceptance and rejection of CLP - 1 cells (see Figure 10).
Hysteresis can be suppressed by an appropriate choice of threshold values for PFl_W and PFl_R.
Table 4. Multi·Q FIFO Flags
FLAG
SYNCHRONIZED TO
DWRDY
WRTCLK
Data write ready. DWRDY must be high before data can be written into the FIFO.
FF1
WRTCLK
Full flag, Queue 1. When FF1 is low, there is no more room for an additional cell in
Queue 1.
PF1
WRTCLK
FF2
WRTCLK
PF2
WRTCLK
Programmable flag, Queue 1. Indicates the extent to which Queue 1 is occupied, as
previously defined with configuration registers PF1 Wand PF1 R
Full nag, Queue 2. When FF2 is low, there Is no more room for an additional cell in
Queue 2.
Programmable flag, Queue 2. Indicates the extent to which Queue 2 is occupied, as
previously defined with configuration registers PF2 Wand PF2 R
FF3
WRTCLK
3-'108
FUNCTION
PF3
WRTCLK
CR1
RDCLK
Full flag, Queue 3. When FF3 is low, there is no more room for an additional.cell in
Queue 3.
Programmable nag, Queue 3. Indicates the extent to which Queue 3 is occupied, as
previously defined with configuration registers PF3_W and PF3_R
Cell ready, Queue 1. If there is at least a complete cell In Queue 1, CR1 is high.
CR2
RDCLK
Cell ready, Queue 2. If there is at least a complete cell in Queue 2, CR2 is high.
CR3
RDCLK
Cell ready, Queue 3. If there Is at least a complete cell in Queue 3, CR3 is high.
Cell 74
Cell 70
Cell 65
Cell 60
t.
oaf
Cell 55
iii
fIl'~
11
.....
=
PF1 W From this point, CLP 1 cells
are no longer accepted.
Cell 50
13a
Cell 45
PF1_R From this point, CLP
are again accepted.
Cell 40
=1 cells
Cell 35
::I»
:tt
c8
!!o
Cell 25
cZ
Cell 20
Cell 30
Cell 15
Cell 10
Cell 5
Celli
Figure 10. Hysteresis of the PF1 Flags With Configuration Registers PF1_W and PF1_R
Programming
The Multi-Q FIFO can be set up to meet the requirements of a particular application after resetting and before writing
in the first word of data with the. configuration registers. These registers are written to and read from using a
microcontroller via the auxiliary-bus control interface (see Figure 11).
MC66302
Multl-Q FIFO
A23-A0
AS
24
I
Address Decode
r-;1
I
I
I
DTACK
I....-
DS
D7-00
RiW
8
I
1
BREQ
DWRDY
DS
P7-P0
RiW
.....
POE
Figure 11. Connection of a Mlcrocontroller to the Auxiliary Bus
3-109
Table 5. Configuration-Registers Access Order
ACCESS
ORDER
REGISTER
SYMBOL
1
PORT
2
REGISTER NAME
PROGRAM BUS
BIT WIDTH
5
MSB
P4 "
LSB
Port control
QL1"
Queue 1 length
5
P4
PO
3
QL2
Queue 2 length
4
P3
PO
4
CLSZ
P5
PO
5
Cell size
Programmable flag 1, write threshold
P7
PO
PO
6
PFCW
PF1 R
Programmable flag 1, read threshold
6
9
9
P7
PO
7
PF2_W
Programmable flag 2, write threshold
9
P7
PO
8
PF2 R
Programmable flag 2, read threshold
P7
PO
9
10
PF3 W
PF3_1'1
Programmable flag 3, write threshold
Programmable flag 3, read threshold
9
8
8
P7
P7
PO
PO
The writing into the configuration registers is perfonned sequentially (see Table 5). Access to register QL3 is
unnecessary because the content of this register always consists of the memory size of the Multi-Q FIFO of 4096 words
of data minus the values of registers QLl and QL2.
To open access to the configuration registers, the bus request (BREQ) signal must be low. As a result, the data write ready
(DWRDY) output replies with a low level after two rising edges of the write clock (WRTCLK). DWRDY indicates an
active data access. When DWRDY is high, access to the FIFO is through the D inputs. When DWRDY is low, access
is through the P tenninals to the configuration registers (see Figure 4). At every falling edge of the data strobe (DS)
signal, the FIFO writes an 8-bit data word from the P tenninals in sequence to the configuration registers. If all ten
configuration registers from Table 5 are filled with values, the FIFO ignores all further write accesses. Only after a
renewed reset of the device are write accesses to the configuration registers again possible.
The following rules apply for the values that are permitted to be written into the configuration registers.
Rules for the length of the queues QLl, QL2, QL3 are:
• The minimum value is O.
• For QLl, the maximum value is 16.
• For QL2 or QL3, the maximum value is 15.
• The sum of QLl and QL2 must not exceed a value of 16; it can be less than 16.
• Only QLl and QL2 can be programmed by the user. The value of QL3 is determined by the Multi-Q FIFO
in that it is infonned of the length of the memory that is still available.
Rules for the cell-size (CLSZ) register are:
• The minimum value is 10.
• The maximum value is 32.
Rules for programmable flag values PFI_W, PF2_W, and PF3_Ware:
• The minimum value is 1.
• The value may not be larger than the number of whole cells for which there is room in the queue.
• The PFCW, PF2_W, and PF3_W registers are nine bits. The higher-valued eight bits are programmable by
the development engineer. The least significant bit (LSB) is always 1. Accordingly, all PFx_W values are odd
numbers.
Rules for programmable flag values PFCR, PF2_R, and PF3_R are:
• The minimum value is 1.
• The value must be smaller than the value of the corresponding PFx_W register.
• The PFl_R, PF2_R. and PF3_R registers each consist of nine bits. The higher-valued eight bits are
programmable by the development engineer. The LSB is always O. Accordingly, all PFx_R values are even
numbers.
3-110
Extension of Word Width
An extension of word width is possible with a 36-bit access. As shown in Figure 12 (36-bit access), all input control lines
must be switched in parallel while the flag outputs are connected together with AND or OR gates. In theory, both FIFOs
must have the same internal state and, accordingly, signal-identical flags; however, when there is unfavorable
ovedapping, the flag of one device can change one clock cycle later than the other device. This does not cause differences
in the contents of memory or loss of data. The flag synchronization can decide on a clock-pulse edge sooner or later,
resulting in differences in the display. In this case, the connection with AND or OR gates ensures reliable results.
If an IS-bit access is desired with an extension of word width, this can be achieved as shown in Figure 12. The only
difference, in this case, is that both FIFOs are programmed for 9-bit access and only nine data lines per FIFO (DS-DO
and Q8--QO) are used.
3-111
Multl-QFIFO
RST
RST
WRTCLK
WRTCLK
WRTEN1
WRTEN1
ROEN
ROEN
WRTEN2
WRTEN2
MUXO
MUXO
WRTEN3
WRTEN3
MUX1
FF1
-
PF2
-
m
-
PF1
PF3
FF3
ISOC
ALER
ABRT
-
PF1
&
~
~
ROCLK
MUX1
T
CR1
CR1
FF1
CR2
r====ID-
CR2
CR3
==ill-
CR3
ISOC
OSOC
ALER
OE
rffi-
PF2
=
<1
FF2
.=.
&
PF3
~
----0=
FF3
OSOC
OE
ABRT
035-00
017-00
36
ROCLK
Q17-QO
18
18
36
Q35-QO
Multl-Q FIFO
RST
'--- WRTCLK
ROCLK
' - - - WRTEN1
ROEN
WRTEN2
MUXO
WRTEN3
MUX1
'---
PF1
CR1
FF1
CR2
PF2
CR3
-
FF2
PF3
FF3
ISOC
OSOC
ALER
OE
ABRT
017-00
18
Q17-QO
18
Figure 12. Extension of Word Width With 18-Blt or 38-Bit Input and/or Output Data
3-112
FIF02
RST
WRTCLK
WRTCLK
I--
WRTEN
RST
ISOC
-
~
J
ISOC
ALER
Q
ABRT
C
~
K
R
"7"
QI-
0
-
FIF01
Q
RST
C
R
WRTCLK
--r&
WRTEN
ISOC
-
In--
ALER
ABRT
08-00
o Flip-Flop
I"-
08-D0
J.K"~"opr
WRTEN
ALER
ABRT
08-D0
9
9
Figure 13. Extension of Word With 9-Blt Input Data
If a 9-bit access to two Multi-Q FIFOs having extended word width is desired, these devices must be provided with
external logic to control them in accordance with the ping-pong principle. InFigure 13, WRTEN and ISOC control lines
demonstrate the ping-pong principle; i.e., the first 9-bit word is read into FIFO 1 and the second 9-bit word is read into
FIF02. In this case, ISOC must also be generated for the second 9-bit data word, because this data word represents the
beginning of a cell of FIF02. The order in which the 9-bit words are read into the two FIFOs is shown in Figure 14.
3-113
Ef
!(~
Wl
Wl
W64
ECIl
W53
W53
ef
W53
liS;
W52
W52
~o
W52
~l
W52
W51
S!
::len
W2
W2
Wl
j~
I··
ell
W3
j~
W51
~
::
Wl
"
~l'
"'~:.l
W3 W2 W4
liS:
W51
~.~~4
h~
~~ ::
::len
W2
W64
W51
;:I;
~j~
!(~
W3·
Wl
Wl
ef
W55
::len
!(~
W3
W2
Wl
Wl
" "
-I1lli
Wl
W3 W2 W4
Wl
W3 W2 W4
Wl
W3 W2 W4
W5 W7 W6 W8
W5 Wl W6 W8
W5 W7 W6 W8
W5 Wl W6 W8
W9 Wll Wl0 W12
W9 Wll Wl0 W12
W9 Wll Wl0 W12
W9 Wll Wl0 W12
W49 W61 W50 W52
W49W51 W50 W52
W49 W51 W50 W52
W3 W2 W4
W53l1lll1tflW2 W4
. W53llllih9JIIW64 ill~iiillil
Wl
W3 W6 W8
Wl
Wl
W9 Wll Wl0 W12
W51Wl Wl0 W12
W51W7 W6 W8
W5 W7
FIFO 1
FIFO 2
FIFO 1
FIFO 2
FIFO 1
FIFO 2
FIFO 1
FIFO 2
Cell
Size:
13
18-Blt
Words
Cell
Size:
13
18-Blt
Words
Cell
Size:
Cell
Size:
13
18-Blt
Words
Cell
Size:
Cell
Size:
Cell
Size:
Cell
Size:
14
18-Blt
Words
W3 W2 W4
W53 W56 W64
W5 Wl W6 W8
Wl
W3
14
14
14
14
18-Blt
Words
18-Blt
Words
18-Blt
Words
18-Blt
Words
~
=9-Blt Data Word, Third Word of ATM Data Stream
•
=Stuffing Byte
NOTE A: Two Multi-Q FIFOs are connected as a 36-bit-wide FIFO with 9-bit data access.
Figure 14. Data Flow of an ATM Data Stream In Two Multi·Q FIFOs
3-114
Programming Examples
Before use, the Multi-Q FIFO must be reset and programmed to perform the desired function using the configuration
registers (see Table 2). Table 6, Table 7, and Table 8 show examples of register programming.
Table 6. Example of Configuration Registers Programming: 18-Bit Write, 18-Blt Read
Function:
REGISTER
53 bytes ~ 27 18-bit words
18bH
18bH
75 ATM cells ~ 2048 18·bit words
56 ATM cells ~ 1536 18·bit words
18 ATM cells ~ 512 18-bit words
65 ATM cells
55 ATM cells
50ATMcelis
40ATMcelis
15ATMcelis
10ATMcelis
Cell size:
Write access:
Read access:
Size of Queue 1:
Size of Queue 2:
Size of Queue 3:
PF'_W:
PF1_R:
PF2_W:
PF2_R:
PF3_W:
PF3_R:
P7
P6
P5
P4
PORT
0
0
0
0
QL1
0
0
0
QL2
0
0
0
P3
P2
P1
0
0
0
0
1
0
0
0
0
1
1
PO
HEX
DESCRIPTION
00
PO = 0 ~ 18-bit input bus
P3 = 0 ~ 18-bit output bus
0
08
8 x 256
0
06
6 x 256
53 cells ~ 27 18-bit words
0
= 2048 18-bit words
= 1536 18-bit words
CLSZ
0
0
0
1
1
0
1
1
18
PF1_W
0
1
0
0
0
0
0
1
41
65ATM cells
PF1 R
0
0
1
1
0
1
1
1
37
55ATMcelis
PF2 W
0
0
1
1
0
0
1
0
32
50ATMcelis
PF2 R
0
0
1
0
1
0
0
0
28
40ATMcelis
PF3 W
0
0
0
0
1
1
1
1
OF
15ATMcelis
PF3 R
0
0
0
0
1
0
1
0
A
10ATMcelis
Table 7. Example of Configuration Registers Programming: 9-Bit Write, 18-Blt Read
Function:
REGISTER
53 bytes ~ 27 18-bit words
9 bit, little endian
18bit
66 ATM celis ~ 1792 18-bit words
56 ATM celis ~ 1536 18-bit words
28 ATM celis ~ 768 18-bit words
60ATMcelis
50ATMcelis
50ATMcelis
40ATMcelis
24ATMcelis
16ATMcelis
Cell size:
Write access:
Read access:
Size of Queue 1:
Size of Queue 2:
Size of Queue 3:
PF1 W:
PFCR:
PF2_W:
PF2 R:
PF3::::W:
PF3 R:
P7
P6
P5
P4
P3
P2
P1
PO
HEX
DESCRIPTION
1
00
PO = 1 ~ 9-bit input bus
P1 = 0 ~ little endian
P2 = 1 ~ odd-numbered celi size
P3 = 0 ~ 18-bit output bus
1
1
07
7 x 256
1
0
06
6 x 256
53 cells ~ 27 18-bit words
PORT
0
0
0
0
0
1
0
QL1
0
0
0
0
0
1
QL2
0
0
0
0
0
1
=1792 1a-bit words
=1536 1a-bit words
CLSZ
0
0
0
1
1
0
1
1
18
PFCW
0
0
1
1
1
1
0
0
3C
60ATM celis
PF1 R
0
0
1
1
0
0
1
0
32
50ATM celis
PF2_W
0
0
1
1
0
0
1
0
32
50ATMcelis
PF2_R
0
0
1
0
1
0
0
0
28
40ATMcelis
PF3 W
0
0
0
1
1
0
0
0
18
24ATMcelis
PF3 R
0
0
0
1
0
0
0
0
10
16ATM cells
3-115
Table 8. Example of Configuration Registers Programming: 18-Blt Write, 9-Blt Read
Function:
Register
Cell size:
Write access:
Read access:
Size of Queue 1:
Size of Queue 2:
Size of Queue 3:
PF1_W:
PFCR:
PF2_W:
PF2_R:
PF3_W:
PF3_R:
54 bytes -7 27 18-bit words
18 bit
9 bit
56 ATM cells -7 153618-bit words
56 ATM cells -7 153618-bit words
37 ATM cells -7102418-bit words
50 ATM cells
40 ATM cells
50 ATM cells
40ATMcelis
30ATMcelis
20ATMcelis
P7
P3
P6
P5
P4
P2
PI
PO
,
HEX
Description
0
1
0
0
0
00
PO =0 -7 18-bit Input bus
P3 =1 -7 9-bit output bus
P4 = 0 -7 even-numbered cell size
0
0
0
1
1
0
07
6 x 256
0
0
0
1
1
0
06
6 x 256 = 1536 18-bit words
PORT
0
0
0
QU
0
0
Ql2
0
0
=1536 18-bit words
CLSZ
0
0
0
1
1
0
1
1
1B
54 cells -7 27 18-bit words
PF1 W
0
0
1
1
0
a
1
0
32
50ATMcelis
PF1 R
0
0
1
0
1
0
0
0
28
40 ATM cells
PF2_W
0
0
1
1
0
0
1
0
32
50 ATM cells
PF2_R
0
0
1
0
1
0
0
0
28
40 ATM cells
PF3_W
0
0
Q
1
1
1
1
0
1E
30 ATM cells
PF3_R
0
0
0
1
0
1
0
0
14
20 ATM cells
3-116
Applications
The Multi-Q FIFO provides several alternatives for arranging the priority control of various QOS classes. A common
implementation is the priority control in the receiving unit (see Figure 15) and transmitting unit
(see Figure 16) of an ATM exchange. If the content of the transmitted ATM cells in the receiving unit is larger than the
capacity of the switching matrix, a priority control must be installed and cells of less importance put in a waiting queue
or eliminated completely. The same phenomenon can arise with the transmitting unit when the capacity of the outgoing
line cannot accept the cells received from the switching matrix. In both cases, use of a Multi-Q FIFO is recommended.
Flaga
J
ATM
Data Stream
-+-
PHY
Priority Control
8
t
Control
Linea
Multl-QFIFO
9
9,18,36
To
Switching
Matrix
-
PHY = Physlcallntarfaca
Figure 15. ATM-Exchange Receiving Unit
Flaga
I
From
Switching
Matrix
Control
Lines
-
Multl·Q FIFO
Priority Control
9,18, 38
t
9,18, 38
PHY
8
r--+
ATM
Data Stream
~
PHY
=Physlcallntarfaca
Figure 16. ATM-Exchange Transmitting Unit
3-117
The universal test and operations physical interface to ATM (UTOPIA) in 8-bit and 16-bit bus widths has become the
preferred interface between the physical interface (pHY) and the subsequent or preceding stages. Figure 17 shows the
connection of the Multi-Q FIFO on the receiving side to a PHY with a UTOPIA interface when one queue is used. When
priority control of the ATM cells is implemented, an arrangement as shown in Figure 18 can be used. Similarly, the
connection on the transmitting side to a PHY with a UTOPIA interface can be implemented as shown in Figure 19 and
Figure 20.
UTOPIA
Multl-Q FIFO
07-00,015-00
8, 16
08,016-017
~
1,2
Q.
CJI
ATM
OataStream
.s:c:
Start of Cell
ISOC
RxEmpty
'a:1
WRTEN1
FF
WRTCLK
PHY =Physlcallntarfaca
Figure 17.
.
Conne~lon
of a Multl-Q FIFO to a Receiving Unit Using an 8-Bit or
16-Bit UTOPIA Interface With One Queue
UTOPIA
8,16
08,016-017
1,2
ISOC
>-
iECJI
c:
j
WRTEN1
RxEmpty
WRTEN2
Priority Logic
WRTEN3
PF1
RxEnable
PF2
PF3
WRTCLK
PHY =Physical interfaca
' - - - - - - - - I Oscillator
Figure 18. Priority-Controlled Connection of a Multl-Q FIFO to a Receiving Unit Using an
8-Blt or 16-Bit UTOPIA Interface
3-118
UTOPIA
Multl·Q FIFO
Q7-QO, Q15-Q01--..........----~------~----......
8,16
Q8, Q16-Q171--..........
---"""'1--------Pr----......
OSOC~----1,-2--------r_~s~m~rt~o~f~Ce~I~I--;_------~~
TxFull
RDEN1
~r------------+------------~--------~
ATM
Dam Stream
CR1
MUXO
MUX1
RDCLK
Oscillator 1-----------'
PHY = Physical Interface
Figure 19. Connection of a Multl·Q FIFO to a Transmitting Unit Using an 8-Blt or
16-Blt UTOPIA Interface With One Queue
Multl·QFIFO
Q7~,Q16-QOI------~~---~~-----~--~~
OSOCr-------------------~~~~~~--~--~~
RDEN
MUXO
MUX1
CR1
CR2
CR3
RDCLK
~.-~----~~----------~--~~~----~~
Oscillator 1-----------'
PHY =Physical Interface
Figure 20. Priority-Controlled Connection of a Multl-Q FIFO to a Transmitting Unit Using an
8-Blt or 16-Bit UTOPIA Interface
3-119
To Output 000-+
To Output 001 - +
11
000
12
001
13
010
14
011
15
100
16
101
17
110
18
111
Figure 21. Switching Matrix With Bottleneck Between Two Switching Elements
There are different versions of the switching matrix. A simple example is shown in Figure 21. In this case, a bottleneck
arises between the next-to-last and the last switching elements. This problem can be solved by increasing the
transmission bandwidth of this part of the transmission path to double that of an input channel or by installing a priority
control for the ATM cells to be transmitted. A Multi-Q FIFO is a suitable device for implementing this priority control.
In view of the many ways in which an ATM exchange system can be implemented, there are certainly a large number
of potential applications for the Multi-Q FIFO. When the priority control of up to three QOS classes is required, the
Multi-Q FIFO is the logical choice.
Summary
The Multi-Q FIFO is designed to fulfill the particular requirements of ATM telecommunications exchange systems by:
• Buffering ATM cells until they are passed on to the switching matrix
• Matching asynchronous rates of data flow between a transmission line and the switching matrix
• Managing up to three different priorities (QOS classes) of ATM cells
• Matching the bus width (for example, from a 9-bit input bus to a 36-bit output bus, or vice versa)
Programming the device by using ten configuration registers allows it to be used in a variety of applications. The 11
SN74ACT53861 Multi-Q FIFO is an outstanding component that fulfills the requirements of telecommunications
applications.
3-120
Interfacing TI Clocked FIFOs With
TI Floating-Paint Digital Signal
Processors
First-In, First-Out Technology
~1ExAs
INSTRUMENTS
SCAA005A
3-121
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas InstrumentS Incorporated
3-122
Contents
TItle
Page
Introduction ............................................................................ 3-125
DSP Applications Using FIFOs ............................................................ 3-125
Communication Between a TI Bidirectional Clocked FIFO and a TI Floating-Point DSP ............ 3-127
DMA Considerations ................................................................... 3-130
Example Control of the SN74ACT3632 Using the DMA ....................................... 3-131
Programming the FIFO Almost-Full-Flag and Almost-Empty-Flag Offsets ........................ 3-135
Calculating FIFO Flag-Offset Values ....................................................... 3-135
Hardware Interface ...................................................................... 3-136
Read and Write Cycles .................................................................. 3-137
Interrupt Generation .................................................................... 3-138
Conclusion ............................................................................. 3-139
List ormustrations
Figure
ntle
Page
Clocked FIFOs Used for High-Speed Data Acquisition .................................... 3-126
2
Clocked FIFOs Used in Pipelined Image-Processing Systems ............................... 3-127
3
Bidirectional Clocked FIFO Used for Bus-Speed Matching ................................. 3-127
4
TMS320C31 DSP ................................................................. 3-128
5
SN74ACT3632512 x 36x 2 Bidirectional FIFO ......................................... 3-129
6
TMS320C31 Memory Map in Microprocessor Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-130
7
Routine for Almost-Empty Flag CPU Interrupt to Schedule FIFO Reads ...................... 3-132
8
Scheduling FIFO Writes ..................................... .' ...................... 3-133
9
Routine for DMA Interrupt to CPU When Transfer Counter Reaches Zero ..................... 3-134
10
Almost-Full-Flag and A1most-Empty-Flag Offset Selection ................................ 3-136
11
TMS32OC31-40InterfacetoanSN74ACT3632-30FIFO .................................. 3-136
12
TMS32OC31-40 Read-Read-Write Timing Diagram With an SN74ACT3632 512 x 36 x 2 FIFO ... 3-137
13
TMS320C31 Interrupt Generation by FIF02 Almost-Empty Flag . . . • . . . . . . . . . . . . . . . . . . . . . . .. 3-138
14
TMS32OC31 Interrupt Generation by FIFO 1 Almost-Full Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-138
3-123
3-124
Introduction
Digital signal processors (DSPs) are used in a variety of applications to analyze real-time data or speed computationally
intensive tasks. A DSP is a microprocessor tuned to the task of number crunching by an instruction set that conveniently
ties together special hardware components needed for fast floating-point and fixed-point math and by powerful
input/output (110) functions that keep data flowing quickly. Design of the 110 for a digital-signal-processing system
is one of the major factors that dictates the machine's performance. First-in, flfSt-out (FIFO) memories often are used
as data rate buffers to optimize the throughput of digital-signal-processing systems and increase overall performance.
A FIFO is a dual-port memory with built-in write and read addressing to pass out data in the same order it is written.
Data reads and writes can be done asynchronous to one another. Flag circuitry indicates when the queue is empty or full,
preventing simultaneous read/write access to the same memory location. Advanced FIFO memories from Texas
Instruments (11) produced in CMOS or BiCMOS technology also have user-programmable almost-empty and
almost-full flags to measure the number of words in memory. FIFOs provide a seamless bridge between two buses
operating at different clock speeds and acting as temporary data bins to exchange information between two systems
without handshaking delay.
11's TMS32OC3x and TMS320C4x processors are popular DSPs that include a 4O-/32-bit floating-Iflxed-point math
unit, one or two 32-bit external buses, and an on-board direct-memory-access (DMA) controller. Unidirectional and
bidirectional clocked FIFO devices from 11 frequently are used to support systems built around these processors.
Attractive features offered by 11 clocked FIFOs are synchronous (clocked) interface on each port, asynchronous I/O
capability, programmable flags, maximum write/read frequencies up to 80 MHz, maximum read access times as low
as 9 ns, and fine-pitch surface-mount packaging.
DSP Applications Using FIFOs
DSP systems doing real-time data analysis or control functions use analog-to-digital (AID) converters to translate
continuous-time, real-valued signals into discrete-time, integer-valued sequences. The rate used to sample the analog
signal is chosen based on the frequency bandwidth of the signal. This sample rate is independent of the
microprocessor-bus rate, and asynchronous buffering is required to pass the information to the DSP. Serial ports on the
TMS32OC3x1C4x processors provide an asynchronous interface with AID converters and are adequate when the
incoming data traffic has a relatively low bit rate. For higher bit rates, unidirectional clocked FIFOs provide a parallel
buffer between the converters and the DSP bus.
Figure 1 shows several digitized signals, each using a FIFO for rate buffering to the processor bus. An example of this
application is multiplexing several analog telephone lines for compression or symbol detection. An input signal packet
is gathered in the FIFO and burst into memory by the DMA unit on the TMS32OC3x/C4x. This method also is useful
when the analog data is sampled at a high rate for short duration, as in some medical-imaging equipment. Each FIFO
holds its AID samples in queue until the processor retrieves the information that must be completed before the next
sampling period. The block labeled FIFO Enable can have a single-memory-space address and control the FIFOs in
round-robin fashion as the DMA fills the random-access memory (RAM) with digitized signals.
3-125
FIFO
Enable
-J
EOC
--+
Data
AID
r---
1WEN
OEIRDEN f--
I-- H3
D
Clocked
FIFO
Q
~
-
c
Address,
STRB,
W
f
c(
~
'iii
i
'V --+
AID
112;<18
II.
(/)
12-18
~
RCLK
WCLK
Clocked
FIFO
I
&
I
j:::
-
DO-D31
Q
••
•
•••
c
c(
--+
AID
112;<18
Clocked
FIFO
Q
D A
RAM
Figure 1. Clocked FIFOs Used for High-Speed Data Acquisition
DSP algorithms are drawn as functional boxes with interconnecting lines representing data streams. This concept can
translate directly to a hardware organization as shown in the pipelined image-processing system (see Figure 2), wherein
the unidirectional TI clocked FIFOs provide the data connection between the TI floating-point DSPs. The FIFO that
connects the bus to the first processing element (PE) performs the task of rate matching, as the bus generally operates
at a slower rate than the DSP bus. FIFOs that connect adjacent PEs are used as packet builders; that is, a packet of data
is stored and then detected with the use of the almost-full/almost-empty or half-full flags and read by the next processor.
Transferring a known packet size simplifies DMA control. The FIFO interconnect between PEs eliminates the need for
processor interlock protocols and reduces clock-distribution requirements by allowing each PE to utilize its own
independent clock.
3-126
VME,
SBus,
etc.
'--C-I-oC-ked--'
r------------------,
I
I
I
PE1
FIFO
- -.... Addr
o --+ Q I-i--+---+_
.....----' I
I
I
I
I
I
I
Addr
Clocked
FIFO
TI OSP
Data
0
--+
PE2
Q
I
I
~------------------~
..
o
Clocked
FIFO
Q
Output
Figure 2. Clocked FIFOs Used In Plpellned Image-Processing Systems
Software applications often are written for a general-purpose workstation platfonn, incorporating signal-processing
functions that are not efficiently perfonned by the workstation. A solution to this problem is to use a special-purpose
DSP system as a coprocessor for the application and communicate with the host computer via a local or backplane bus
(see Figure 3). The bidirectional clocked FIFO is most useful when data traffic is heavy both to and from the host
computer, such as when the host provides the input data and receives the processed results. Bidirectional FIFOs also can
be used as instruction queues between a host processor and the DSP. The FIFO in the datapath provides clock partitioning
so each bus can operate at its maximum rate; it also eliminates transfer delay required for a bus request to be granted
to either the host or the DSP.
VME,
SBus,
etc.
... ["'.,.... Clock
-0ff-set-----"'l"'O~1 No. of Words In FIF02 S Offset
-t\
INT1t
__________________
t-- tpd
----~~=~~~S1~
-tI t-- tpd
~~:2~2~?~-------
t Low level on INT1 Indicates an available FIF02 packet space.
Figure 13. TMS320C31 Interrupt Generation by FIF02 Almost-Empty Flag
H3
H1
I4-tI
tpd(C-AF)
I4-tt tpd(C-AF)
_ _-"t""Z",,,..~-r:N:":'0';'.-of~E~m""pty~":::s""pa"ces~':"ln-:F:::IF::O::":1:->~Off==set"""!"'--"11:\::~i No. of Empty Spaces In FIF01 S Offset
t--
INTot
-t\
tpd
--~\~~~~~~
__________________
t--
-tI
tpd
~e:2~2~?~-------
t Low level on INTO indicates an available FIF01 packet space.
Figure 14. TMS320C31 Interrupt Generation by FIF01 Almost-Full Flag
3-138
Conclusion
FIFO memories are used in DSP systems for matching two datapaths with asynchronous clock or data rates. The
SN74ACT3632 512 x 36 x 2 clocked FIFO provides a single-chip bidirectional buffering solution that interfaces nicely
with TI floating-point DSPs. Programmable FIFO flags enable a variety of DMA control techniques to be used in
handling data flow, and the FIFO control signals are easily derived from TMS32OC3x outputs. Available in a variety
of speed options, the SN74ACT3632 can interface a DSP to buses operating up to 67 MHz.
3-139
3-140
FIFOs With
a Word Width of One Bit
First-In, First-Out Technology
Peter Forstner
Mixed Signal Logic Products
~TEXAS
INSlRUMENTS
SCAAOO6A
3-141
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to Its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable althe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Appllcations'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product deSign, software performance, or
infringement of patents or services descrlbed herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or procElss in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-142
Contents
Title
Page
Introduction ............................................................................ 3-145
FIFO Basics ............................................................................ 3-145
Telecommunications . ..................................................................... 3-147
Digital-Transmission Methods ............................................................ 3-148
A PDH Application Example ............................................................. 3-149
Frame Structure of the First Hierarchy Level .............................................. 3-149
Frame Structures of the Second to Fifth Hierarchy Levels .................................... 3-150
Clock Adjustment With FlFOs .......................................................... 3-154
Modems With Data Compression . .......................................................... 3-156
Signal-Processor Interfaces . ............................................................... 3-158
Teletext Decoders ........................................................................ 3-159
Summary ............................................................................... 3-160
3-143
List of Illustrations
Figure
I
Title
Page
First-In, First-Out Data Flow ......................................................... 3-145
2
Connections of a Strobed FIFO . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-146
3
Connections of a Clocked FIFO ...................................................... 3-146
4
Time-Division Multiplex of Several Channels ........................................... 3-147
5
Logarithmic 13-Segment Characteristics for the Coding of Telephone Signals .................. 3-148
6
Frame Str\Jcture of the 2048-kbitls Multiplex Signal (First Hierarchy Level) ..•................ 3-150
7
Frame Structure of the 8448-kbit/s Multiplex Signal (Second Hierarchy Level) ................. 3-151
8
Frame Structure of the 34368-kbit/s Multiplex Signal (Third Hierarchy Level) ................. 3-151
9
Frame Structure of the 139264-kbit/s Multiplex Signal (Fourth Hierarchy Level) ............... 3-151
10
Frame Structure of the 564992-kbit/s Multiplex Signal (Fifth Hierarchy Level) . . . . . . . . . . . . . . . .. 3-152
11
Clock Adjustment at the Transmitting End
With Positive Pulse-Stuffing Techniques Block Diagram ................................... 3-154
12
Bit Stream at the FIFO of the Transmitter-Clock Adjustment ............................... 3-154
13
Clock Adjustment at the Receiving End
With Positive Pulse-Stuffing Techniques Block Diagram ................................... 3-155
14
Bit Stream at the FIFO of the Receiver-Clock Adjustment .................................. 3-155
15
Clock Signals at the Receiver ........................................................ 3-156
16
Data Transmission by Modem With Data Compression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-157
17
Serial-Port Data-Transmission Protocol of a TMS320CXX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-158
18
Serial-Port Data-Transmission Protocol With Inverted Signals .............................. 3-158
19
Connection of 1\vo Signal Processors via a Serial Port
With the Help of the FIFO SN74ACT2229 .............................................. 3-159
20
Video Signal ..................................................................... 3-159
21
Teletext Decoder With 1 x 512 FIFO Block Diagram ....•................................ 3-160
22
Extending MemOry Depth of a SN74ACT2229 FIFO to 512 x 1 Bit ....... , ...... , ........... 3-160
List of Tables
Table
Title
Page
1
Plesiochronous Digital Hierarchies .. • . . .. . . .. .. .. .. .. . .. .. . . . . .. .. . . . . . .. .. . .. . . . . . . .. 3-149
2
3
Synchronous Digital Hierarchy and SONET ............................................ 3-149
4
Spread of the Transmission Capacity of a 34368-kbit/s Signal Consisting of Four Multiplexed
8448-kbitls Signals With a Net Nominal Transmission Speed of 4 x 8448 kbit/s - 33792 kbit/s .... 3-153
5
Spread of the Transmission Capacity of a 139264 kbit/s Signal Consisting of Four Multiplexed
34368-kbit/s Signals With a Net Nominal Transmission Speed of
4 x 34368 kbit/s - 137472 kbit/s ..................................................... 3-153
6
Spread of the Transmission Capacity of a 564992-kbit/s Signal Consisting of Four Multiplexed
.
139264-kbit/s Signals With a Net Nominal Transmission Speed of
4 x 139264 kbit/s - 557056 kbit/s .................................................... 3-153
7
One-BitFIFOs From TI .............•............................................... 3-156
3-144
Spread of the Transmission Capacity of a 8448-kbit/s Signal ConSisting of Four Multiplexed
2048-kbit/s Signals With a Net Nominal Transmission Speed of 4 x 2048 kbit/s - 8192 kbit/s ..... 3-153
Introduction
In every digital system, data is continually being exchanged between various subsystems. Intennediate storage is always
necessary if data arrives at the receiving subsystem at a high rate or in batches but can then only be processed slowly
or irregularly. Such intermediate stores are familiar to us in our daily lives, for example, as queues of customers at the
checkout of a supennarket or cars waiting at traffic lights. The checkout of goods. at the supennarket point of sale
proceeds slowly and regularly, while customers arrive there unpredictably; if many customers all want to pay at the same
time, a queue builds up that the cashier processes on the principle of first come, first served. Queues of cars at traffic
lights result from the sporadic arrival of traffic, which the lights allow to proceed only in regular batches.
An intennediate store or memory that operates on the above principle is known as a fIrst-in, first-out (FIFO) memory.
The fIrst data written into a FIFO is also the first to leave it at readout. Texas Instruments (TI) offers a variety ofFIFOs.
These are available with word widths from 1 bit to 36 bits, storage densities from 64 to 2048 words of data, and clock
speeds of up to 80 MHz. This application report is concerned exclusively with FIFOs having a word width of one bit
and it suggests various possible applications for them.
Whenever a buffer memory is needed for serial-data transmission, there is a requirement for I-bit-wide FIFOs. Digital
telecommunications, local-area networks (LANs), serial transmission of data with the help of data compression, and
communication between signal processors are all examples of serial data-transfer applications that require I-bit-wide
FIFOs. In some applications, the FIFOs are already integrated into the application-specifIc integrated circuit (ASIC) or
the chip set with LANs. However, very often discrete FIFO components are required.
FIFO Basics
Every memory component for which the fIrst word of data written to the memory is also the flfSt to leave it when the
memory is read out can be classified as a FIFO (see Figure 1). In practice, a further characteristic often required from
a FIFO is asynchronism between the writing and reading processes. This kind of FIFO is known as an asynchronous
FIFO.
•
••
Figure 1. First-In, First-Out Data Flow
3-145
A FIFO has an input to which data words are written and a separate output from which data words are read. Since writing
can take place completely asynchronously to reading, it is permissible for the writing and reading pulses to have
completely different clock speeds, chosen at will. Control signals such as full, empty, half full, and almost full allow
the controlling circuitry to monitor the internal state of the FIFO before every writing or reading process.
According to the control signals to write and read, asynchronous FIFOs can be classified into two groups; strobed FIFOs
(see Figure 2) and clocked FIFOs (see Figure 3).
WRTCLK
RDCLK
Strobed
FIFO
Input Data
Output Data
Figure 2. Connections of a Strobed FIFO
Free-Running
WRTCLK
Free-Running
RDCLK
WRTEN
IR
Clocked
FIFO
Input Data
RDEN
OR
Output Data
Figure 3. Connections of a Clocked FIFO
The strobed FIFO enters a word of data into its internal memory at every rising (or every falling) edge of the write clock
(WRTCLK). FULL shows whether there is room in the memory for a data word. Reading adata word takes place at every
rising (or falling) edge of the read clock (RDCLK). If there is no data word awaiting readout, this is indicated by the
status signal EMPTY. The disadvantage of this kind of FIFO is that the status signals cannot be fully synchronized with
the corresponding clock signals.
Clocked FIFOs require a free-running write clock (WRTCLK) and read clock (RDCLK). The writing and reading
processes are controlled by the control signals write enable (WRTEN) and read enable (RDEN). The status signals input
ready (IR) and output ready (OR) indicate the internal state of the FIFO. As a result of the two free-running clock signals,
all status signals can be synchronized within the FIFO. The IR signal changes its level exclusively in synchronism with
the writing pulse, while OR switches synchronously with the reading pulse.
The I-bit FIFOs in this application report (SN74ACT2226, SN7 4ACT2227, SN74ACT2228, and SN74ACT2229) are,
without exception, clocked FIFOs with complete built-in synchronization of all available status signals, including:
Output ready (OR) synchronized with read clock (RDCLK)
Input ready (IR), half full (HF), and almost fulValmost empty (APIAE) synchronized
with write clock (WRTCLK)
3-146
Telecommunications
The rapidly increasing need for telecommunication installations cannot, in the long run, be met by providing a separate
line for every telephone connection; the simultaneous use of one line for several channels is a requirement. Digital
transmission via pulse-code modulation (PCM) techniques enables the cost-effective use of single lines for multichannel
transmission. Using these techniques, digitized telephone signals are switched successively onto a connecting line with
the help of a multiplexer and separated from one another at the end of the line with a demultiplexer (see Figure 4).
81
83
1841
1
84
1 1 1 1 1
f4 ta
t2 t1
81
1 1
1 1
1.1
1 1
1 1
1 1 1 1 1
f4 ta
t2 t1
83
1841
1
84
1 1 1 1 1
f4
t3 t2 t1
Figure 4. Time-Division Multiplex of Several Channels
With the 3.4-kHz upper bandwidth limit of a telephone channel and the internationally standardized sampling frequency
for digitizing the signal (fo = 8 kHz), there remains enough space in the frequency band to insert the edge of the necessary
bandwidth-limiting low-pass filter.
Although extensive tests of syllable intelligibility have shown that 7-bit quantization with 128 quantization intervals
is adequate even with successive analog-to-digital-to-analog conversion, an 8-bit quantization with 256 intervals has
been made the standard. For the compression of the instantaneous value of the signal, the logarithmic 13-segment
characteristic shown in Figure 5 is used.
For the transmission of a channel, a bit rate of 8 kHz x 8 bit = 64 kbit/s is necessary and, correspondingly, a line for
32 multiplexed channels must attain a transmission rate of64 kbit/s x 32 = 2048 kbitls (CCITIrecommenc4ttions G.732
and G.704).
3-147
Input Level [dB]
-20 -15 -10
If
-5 -4-3 -2 -1
0
2
•
+3
01111111
01110000
01100000
01010000
01000000
00110000
00100000
1
718
6/8
5/8
00000000
0
418
3/8
218
11100000
11010000
11000000
10110000
10100000
10010000
10000000
-218
-3/8
-418
-5/8
-618
-7/8
-1
1
-1
•
Coder Input
0
Figure 5. Logarithmic 13-Segment Characteristics for the Coding of Telephone Signals
Digital-Transmission Methods
At present, four different digital-transmission methods are used for telecommunications:
European plesiochronous digital hierarchy (pOH, see Table 1)
American plesiochronous digital hierarchy (POH, see Table 1)
Japilnese plesiochronous digital hierarchy (pOH, see Table 1)
Synchronous digital hierarchy (SOH, see Table 2)
Signals coming from various clock generators should have the same bit speeds but, in practice, the bit speed may deviate
by a certain tolerance from the nominal value. These signals are referred to as plesiochronous signals.
The lack of worldwide standardization of the three POH transmission methods makes world networking much more
difficult, and the use of equipment from various manufacturers is limited to the networks of individual national
telecommunications organizations. The fact that the standard for synchronous digital hierarchy (SOH, see Table 2) has
worldwide validity does, however, offer the promise of assistance. SOH evolved from the North American synchronous
optical network (SONET) specifications but is based, (as described in the CCITTrecommendations 0.707, 0708, and
0709) on a bit rate of 155520 kbit/s (see Table 2); that is, exactly three times the SONET basic bit rate of 51840 kbitls.
The SOH basic signal is designated as synchronous transport module level one (STM-I); higher hierarchy levels are
whole integer multiples of the level-one bit rate.
3-148
Table 1. Pleslochronous DIgItal HIerarchIes
HIERARCHIES
BASED ON
2 Mbltls
HIERARCHY
LEVEL
HIERARCHIES
BASED ON
1.5 Mbltls
EUROPE,
SOUTH
AMERICA
USA
JAPAN
1
2048 kbills
1544 kbit/s
1544 kbit/s
2
8448 kbills
6312 kbit/s
6312 kbit/s
3
34368 kbit/s
44736 kbit/s
4
139264 kbit/s
32064 kbills
97728 kbit/s
Table 2. Synchronous DIgItal HIerarchy and SONET
SONET
SOH
BIT RATE
LEVEL
SIGNAL
IDENTIFICATION
1
STM-1
51840 kbit/s
155520kbit/s
466560 kbit/s
LEVEL
SIGNAL
IDENTIFICATION
ST5-1
OC-1
ST5-3
0C-3
ST5-9
00-9
ST5-12
00-12
933120 kbit/s
ST5-18
00-18
1244160 kbit/s
ST5-24
00-24
1866240 kbit/s
ST5-36
0C-36
STS-48
OC-48
622080 kbit/s
2488320 kbills
4
16
STM-4
STM-16
A PDH ApplicatIon Example
The plesiochronous digital hierarchy and the application of FIFOs for the synchronization of the PDH signals are
demonstrated using as an example European transmissions based on a bit speed of 2048 kbit/s.
Frame Structure of the First Hierarchy Level
The bit speed of the first hierarchy level (2048 kbit/s, see Table 1) allows the transmission of 32 telephone channels,
each of 64 kbitls, over a normal telephone line. In this case, only 30 telephone conversations are transmitted, since two
channels are required for the following additional information (see Figure 6):
Frame recognition word for the synchronization of the receiver
Cyclic-redundancy-check (CRC4) bits for the recognition of bit faults during the transmission
Service bits for initiating alarms
Registration bits for national and international telecommunication traffic
Telephone exchange technical identification (signalization)
Each of the eight bits of the 32 channels is multiplexed bit by bit; that is, bit 0 of the 32 channels is first sent serially
over the line followed by 32 times bit 1, etc. These 8 x 32 bits - 256 bits are consolidated in a frame (see Figure 6).
Channels 0 and 16 contain the necessary control information, while the remaining channels can be used for the
transmission of 30 telephone connections. The transmission of a 256-bit frame of this kind at 2048 kbit/s requires a time
period of 125 /LS.
Sixteen frames together make up a 16 x 256 - 4096-bit multiple frame with a transmission time period of 2 ms. The
256 control bits in channels 0 and 16 can be seen in Figure 6.
3-149
--- ---- ---
---
FRAME BITS
FRAME
NO.
1
2
3
4
5
6
7
0
Cl
0
0
1
1
0
1
---- -
FRAME BITS
8
FRAME
NO.
1
2
3
4
5
6
7
1
0
0
0
0
0
X
Y
X
°1
02
dl
a17
b17
°17
d17
dz
a18
b18
°18
d18
1
0
1
0
N
Sn
Sn
Sn
Sn
1
al
bl
2
C2
0
0
1
1
0
1
1
2
a2
bz
8
X
3
0
1
0
N
Sn
Sn
Sn
Sn
3
as
bs
03
d3
a19
b19
°19
d19
4
C3
0
0
1
1
0
1
1
4
84
b4
°4
d4
a20
bzo
020
d20
b5
°5
d5
a21
b21
021
d21
be
OS
d6
a22
bz2
022
dzz
°7
08
d]
a23
b23
023
d23
d8
a24
bz4
024
d24
5
0
1
0
N
Sn
Sn
5
C4
0
0
1
Sn
1
Sn
6
0
1
1
6
as
as
7
0
1
0
N
Sn
Sn
Sn
Sn
7
a7
b]
8
Cl
0
0
1
1
0
1
1
8
a8
b8
9
0
1
0
N
Sn
Sn
Sn
Sn
9
ag
bg
Cg
d9
a25
bz5
025
d25
10
C2
0
0
1
1
0
1
1
10
al0
bl0
010
dl0
a26
bz6
026
d26
11
0
1
0
N
Sn
Sn
Sn
Sn
11
all
bll
°11
dll
a27
bz7
027
d27
12
C3
0
0
1
1
0
1
1
12
a12
b12
012
d12
a28
bz8
028
d28
13
0
1
0
N
Sn
Sn
Sn
Sn
13
a13
b13
013
d13
a29
bz9
029
dz9
14
C4
0
0
1
1
0
1
1
14
a14
b14
c14
d14
aso
b30
030
d30
15
0
1
0
N
Sn
Sn
Sn
Sn
15
a15
b15
c15
d15
asl
b31
c31
d31
0011011
C4··· C1
D,N
SI,Sn
Frame Recognition Word
CRC4 Control Bits
Bits for Alarm Initiation
Registration Bits
OOOOXYXX
an ••• d n
Multiple Frame Recognition Word
Signalization for Channel n
Figure 6. Frame Structure of the 2048-kblt/s Multiplex Signal (First Hierarchy Level)
Frame Structures of the Second to Fifth Hierarchy Levels
For further sections, four 2048-kbit/s signals are transmitted with successive bit-by-bit time-division multiplexing
combined with the pulse-stuffing procedure at bit speeds of 8448 kbit/s, 34368 kbit/s, 139264 kbit/s, and 564992 kbit/s.
If several plesiochronous signals are multiplexed, they must be synchronized before the multiplexing process.
Plesiochronous signals have nominally the same bit speeds; but, in practice, the following kinds of asynchronism can
arise:
The bit rates deviate from one another within the specified tolerance (drift).
As a result of long transmission distances and significant differences of temperature, etc.,
the bit speeds fluctuate for short periods (jitter).
For the synchronization of many plesiochronous 2048 kbit/s signals, positive pulse-stuffing techniques are used when
multiplexing these signals into an 8-mbit/s signal. The principle of this technique is based on the fact that, in the
multiplexed signal, a bandwidth is made available that is wider than the nominal bit rate requires. If at particular points
in the transmission information bits or empty bits (so-called stuffing bits) are sent out, the bit speed can be reduced and
thus adjusted to suit the input signal. This technique also compensates for driftand jitter of the input signal.
3-150
4
x
~I
212 Bit = 848 Bit
I
Block II
Block I
I
Block III
NI
RKW:
S:
NI:
St:
B:
Block IV
NI
Frame-Recognition Word
SeNlceBlts
Useful Information Bits
Stuffing Information Bits
Stuffing or Useful Bits
Bit Position
per Block
Figure 7. Frame Structure of the 8448-kblt/s Multiplex Signal (Second Hierarchy Level)
'4~------------1
4 X 348
Block II
Block I
BI~= 1536 Bit
I
- - - - - - - - - - - - -..
~
Block III
Block IV
1
5
NI
RKW:
S:
NI:
St:
B:
NI
Frame-Recognition Word
SeNlceBlts
Useful Information Bits
Stuffing Information Bits
Stuffing or Useful Bits
Bit Position
per Block
Figure 8. Frame Structure of the 34368-kbit/s Multiplex Signal (Third Hierarchy Level)
1'4'<11-------------1
Block I
Block II
4 X 488 BI~= 2928 Bit - -.........- - - - - - - - - -.......
~
Block III
I
RKW:
S:
NI:
St:
B:
Block IV
Block V
Frame-Recognition Word
Service Bits
Useful Information Bits
Stuffing Information Bits
Stuffing or Useful Bits
Block VI
1
Bit Position
per Block
Figure 9. Frame Structure of the 139264-kblt/s Multiplex Signal (Fourth Hierarchy Level)
3-151
...
~------------
I
Block I
Block II
Block III
71384BIt=2688~1t
I
Block IV
I
- - - - - - - - - - - -......
~
Block V
Block VI
Block VII
I
RKW: Fram.Recognltlon Word
s:
HI:
St:
B:
Service Blta
Useful Information Blta
Stumng Infonnatlon Blta
Stumng or Useful Blta
Bit Position
per Block
Figure 10. Frame Structure of the 564992·kblt/s Multiplex Signal (Fifth Hierarchy Level)
When multiplexing with positive pulse-stuffing techniques, a frame that is constructed with a 8448-kbitls signal is
partitioned into four blocks (see Figure 7). This frame structure envisages four stuffmg bits in block N in bit positions 5
to 8. These stuffing bits can either contain useful information or they can be empty bits. The stuffing information in bit
positions 1 to 4 in blocks II, ill, and N indicates whether empty bits or useful bits are present in block N. This 4-bit
stuffmg information is transmitted three times (blocks II, ill, and N) to assure a correct decision about the information
content of the stuffing bits in the case of bit faults within the stuffing information. If there is a conflict between the
individual bits of the three transmissions of stuffing bits, a majority decision can be used to avoid a false conclusion that
would result in a bit slip and, consequently, a loss of synchronization of the 2-mbit/s systems. If, for example, one of
the bit combinations 0-0-0, 0-0-1,0-1-0, or 1-0-0 is received as stuffing information in blocks II, ill, and N for the ftrSt
stuffmg bit, a useful bit follows at bit position 5 in block N; the reception of 1-1-1, 1-1-0, 1-0-1, or 0-1-1 indicates an
empty bit. A 2-bit fault in the stuffmg information results in the loss or gain of a bit (bit slip) and, consequently, in loss
of the frame synchronism of the multiplexed signals.
Techniques similar to multiplexing with positive pulse stuffing with the 8448-kbit/s signal are also performed with the
34368-kbit/s, 139264-kbit/s, and 564992-kbit/s signals (see Figures 8, 9, and 10).
As a result of these stuffing techniques, a 8448-kbit/s frame has a transmission speed in the range of 8169-kbitls to
8209-kbit/s useful bits. With the nominal transmission speed for four multiplexed 2048-kbit/s signals of 8192-kbit/s,
fluctuations in the transmission speed in the range of about ±0.2% can be compensated for (see Tables 3, 4,5, and 6).
3-152
Table 3. Spread of the Transmission Capacity of an 8448-kblt/s Signal Consisting of
Four Multiplexed 2048-kblt/s Signals With a Net Nominal Transmission Speed of
4 x 2048 kblt/s 8192 kblt/s
=
USEFUL BITS
FRAME
oSTUFFING
BITS
Frame Capacity
Transmission Speed
2 STUFFING
BITS
4 STUFFING
BITS
848 bits
820 bits
822 bits
824 bHs
8448 kbit/s
8169 kbit/s
8189 kbH/s
8209 kbit/s
8192 kbit/s
8192kbit/s
8192 kbit/s
-0.28%
-0.04%
+0.21%
Nominal Value
Deviation from Nominal Value
Table 4. Spread of the Transmission Capacity of a 34368-kblt/s Signal Consisting of
Four Multiplexed 8448-kblt/s Signals With a Net Nominal Transmission Speed of
4 x 8448 kblt/s 33792 kblt/s
=
USEFUL BITS
FRAME
oSTUFFING
BITS
Frame Capacity
Transmission Speed
2 STUFFING
BITS
4 STUFFING
BITS
1536 bits
1508 bits
1510 bits
1512 bits
34368 kbH/s
33742 kbit/s
33786 kbH/s
33831 kbH/s
33792 kbit/s
33792 kbH/s
33792 kbH/s
-0.15%
-0.02%
+0.12%
Nominal Value
Deviation from Nominal Value
Table 5. Spread of the Transmission Capacity of a 139264·kblt/s Signal Consisting of
Four Multiplexed 34368-kblt/s Signals With a Net Nominal Transmission Speed of
,
4 x 34368 kbit/s = 137472 kblt/s
USEFUL BITS
FRAME
oSTUFFING
BITS
Frame Capacity
Transmission Speed
2 STUFFING
BITS
4 STUFFING
Bits
2928 bits
2888 bits
2890 bits
2892 bits
139264 kbit/s
137361 kbit/s
137457 kbit/s
137552 kbit/s
137472 kbH/s
137472 kbH/s
137472 kbit/s
-0.08%
-0.01%
+0.06%
Nominal Value
Deviation from Nominal Value
Table 6. Spread of the Transmission Capacity of a 564992·kblt/s Signal Consisting of
Four Multiplexed 139264-kblt/s Signals With a Net Nominal Transmission Speed of
4 x 139264 kblt/s 557056 kbit/s
=
USEFUL BITS
FRAME
Frame Capacity
Transmission Speed
Nominal Value
Deviation from Nominal Value
o STUFFING
BITS
2 STUFFING
BITS
4 STUFFING
BITS
2688 bits
2648 bits
2650 bits
2652 bits
584992 kblt/s
556584 kblt/s
557005 kbit/s
557425 kbit/s
557056 kbit/s
557056 kbit/s
557056 kbit/s
-0.08%
-0.01%
+0.07%
3-153
Clock Adjustment With FIFOs
Clock Adjustment at the Transmitting End
A block diagram showing the principle of clock adjustment at the transmitting end with positive pulse-stuffmg
teclmiques is shown in Figure 11. In this case, each channel is provided with an elastic memory in the form of a FIFO.
RDCLK
RDEN
WRCLK
FIFO
Input
Slgnal---4._------...., 1D
2048kblt/a
Control
Logic
HF
HF
I----+l~
3 Mora Telephone Channela
M
With 2048 kblta/a Each, -:--+-1 U
X
Frame Recognition Word,.
Service Blta, •
Stuffing Information Blta, •
Stuffing or Useful Blta - - + I
Output
Signal
8448kblt/a
Figure 11. Clock Adjustment at the Transmitting End With Positive Pulse-Stuffing Techniques
Block Diagram
The input data is written into this FIFO with the help of a circuit for clock recovery. The FIFO takes on the buffering
of the input data while the frame and stuffmg information is being transmitted. If information bits are to be transmitted.
the control logic of the transmission path extracts the data from the FIFO. With positive pulse-stuffmg teclmiques, the
net bit speed of the transmission path is slightly higher than the bit speed of the incoming signal. As a result, the
transmission-path controller reads the data from the FIFO more quickly than it can deliver it to the input channel.
Whenever the FIFO contains less than a certain minimum filled level (e.g., half full), the transmission path sends at the
next possible moment a stuffmg bit instead of a data bit. As a result, the input channel has enough time to raise the filled
level of the FIFO above the specified minimum levei by writing in further data (see Figure 12).
NI: Uaefullnformatlon blta
St: Stuffing Information blta
\~~
I Frame I
NI
rJ.¢I'
~to
NI
NI
NI
Time
Figure 12. Bit Stream at the FIFO of the Transmitter-Clock Adjustment
If the minimum level of the FIFO when sending block II (see Figure 7) is not reached, the stuffmg information in block II
can no longer be changed. Accordingly, a wait must be made until the next frame when the necessary
stuffmg-information bits and the associated stnffmg bits can be transmitted. The maximum number of data words that
can be stored in the FIFO should be chosen such that the FIFO will not become empty during this time period. In addition,
the FIFO must be in a position to buffer the arriving data during the transmission of the frame bits.
3-154
Clock Adjustment at the Receiving End
There is also an elastic memory (FIFO) at the receiving end of each channel. Figure 15 shows that the information is
written into the FIFO with the multiplex clock pulse divided by n. As a result of the now well-known frame structure,
writing must be inhibited while the additional information is being received. The writing process also must be
interrupted when stuffing bits are received (see Figure 13). Consequently, received data is written into the FIFO block
by block (see Figure 14).
--.J
Clock
Recovary
...
Control
Logic
.
WRCLK
WREN
1D
l' •••
r+
RDCLK
PLL
FIFO
Output
Signal
8448kblt/s
1Q
f---+
Input
Signal
2048kblt/s
~
••
•
Three More Telephone Channels
~
Figure 13. Clock Adjustment at the Receiving End
With Positive Pulse-Stuffing Techniques Block Diagram
NI: Useful Information bits
St: Stuffing Information bits
J
:t:
III
, Frame'
NI
NI
NI
Figure 14. Bit Stream at the FIFO of the Receiver-Clock Adjustment
The write clock of the FIFO has as a nominal clock frequency (the multiplex clock divided by n); however, during the
reception of the frame and the stuffmg bits, several clock periods are omitted. Over a long period of time, the bit speed
is identical with that of the original signal at the transmitter end (see Figure 15). As a read pulse for the FIFO, a regular
clock without gaps is needed so that a continual bit stream conforming to the original signal is supplied. A PLL circuit
reconstitutes this continuous clock signal from the clock signal containing gaps, although there is a small amount of jitter.
3-155
Input Clock
Dlvldedbyn
Clock
With
Gap.
Regular Clock
Without Gap.
Figure 15. Clock Signals at the Receiver
Types of FIFOs Suitable for Clock Adjustment
The width of a FIFO data word for clock adjustment at the transmitting or receiving end is merely one bit and,
consequently, the FIFOs listed in Table 7 can be considered as candidates for this application.
Table 7. One-Bit FIFOs From TI
SN74ACT2229
FIFO TYPE
SN74ACT2226
SN74ACT2227
SN74ACT2228
Word Width
1 bit
1 bit
1 bit
1 bit
Memory Capacity
64 words
64 words
256 words
256 words
FIFOs per Package
2
2
2
2
Clocked FIFO
..J
..J
fmax
22 MHz
60 MHz
..J
22 MHz
60 MHz
Totem-Pole Q Output
..J
3-State Q Output
..J
..J
..J
..J
Half-Full Flag
..J
..J
..J
..J
Almost-Full Flag
..J
..J
..J
..J
Modems With Data Compression
Modems are now widely used for transmitting data over telephone lines. The telephone network was, however,
originally developed for speech communications and for the transmission of analog audio signals. The result is that only
alternating-current signals having an upper bandwidth limit of 3.4 kHz can be transmitted. Binary-digital information
must be modulated, or converted, into another kind of signal. With acoustic couplers, frequency modulation is used such
that a 0 is audible as a high note and a 1 as a lowernote. This frequency-modulated signal is analog, with 2100 Hz used
for 0 and 1700 Hz for 1. These frequencies lie within the frequency band that can be transmitted over a telephone line.
The maximum transmission rate is only 600 baud.
Since significantly higher frequencies cannot be transmitted by a telephone network, a trick must be used to attain higher
transmission speeds. If the number of possible states (e.g., frequencies) is created from two to four, two bits can be
transmitted simultaneously without exceeding the upper bandwidth limit of 3.4 kHz. A further sophistication of this
multistage modulation process to 16 or even 32 states (4 or 5 bits can be simultaneously transmitted) resulted in modems
having atransmission capacity of up to 9600 bitls but at the same time a transmission system that was more susceptible
to interference.
A further increase of transmission speed by means of yet more sophisticated modulation methods would have been
difficult; therefore, data compression has been used to improve performance. This involves examining the bit stream
for redundant information, then compressing it. The receiver recognizes the parts of the signal that have been
compressed and expands them in order to reconstitute the original signal. In a typical case, redundancy of the transmitted
bit stream allows a 50% reduction of the original data, whereby the possibility for compression can typically range from
0% to 75%.
3-156
If, for example, a computer sends data via synchronous serial interface to a modem having a data rate of 4800 baud, the
modem uses data compression to reduce the information to a transmission speed of 2400 baud and subsequently sends
it without problems over a telephone line (see Figure 16). Variations in the compressibility of the signal are, in this case,
buffered by a FIFO. If the transmitted data is not compressible, the data received from the interface line is temporarily
stored by a FIFO in the modem. When the potential for data compression increases to over 50%, the modem again
accepts data stored in the FIFO. Only if the compressibility of the transmitted data deviates significantly and for a long
time from the average value (50%) must the arriving data stream be halted or the data stream that is leaving be
interrupted.
The same speed variations arise with data expansion at the receiver as with compression at the transmitter. A FIFO also
is used here to buffer the data and to ensure a constant flow of data to the receiver.
FIFO
FIFO
Interface Cable
4800 Baud
Figure 16. Data Transmission by Modem With Data Compression
Since in this application a serial stream needs to be buffered by the FIFO, the FIFOs having a word width of one bit shown
in Table 7 are suitable. The two FIFOs needed for duplex operation (for transmitter and receiver) have already been
integrated with these FIFO types into a single package.
3-157
Signal.Processor Interfaces
The signal processors from TI's TMS320CXX family have one or more serial ports to allow them to communicate with
other signal processors or for data exchange with peripheral equipment such as the analog interface circuit (AIC). For
data transmission, the signal processors make use of the following signals:
Transmit clock - clock transmit (CLKX)
Transmitter control- frame sync transmit (FSX)
Transmit data - data transmit (DX)
Receiver clock - clock receive (CLKR)
Receiver control- frame sync receive (FSR)
Receive data - data receive (DR)
The protocol for the transmission of data is shown in Figure 17. The fact that data is to be transmitted is signaled by FSX,
which occurs on the falling edge of the clock pulse CLKX. To make the waveform of the signal processor in Figure 17
compatible with that required by the FIFO, both the clock signal CLKX and the control signal FSX must be programmed
to give an inverted output. The TMS320C30 offers the possibility of programming both the polarity of the clock signal
and the control signal. The resulting signals shown in Figure 18 are directly compatible with the FIFO.
CLKX
FSX------~,~
____________________________________JI
DX ________~--------------__
Figure 17. Serial·Port Data·Transmission Protocol of a TMS320CXX
..I'
FSX ______
,
DX ______~~--------------__
Figure 18. Serial-Port Data-Transmission Protocol With Inverted Signals
, With data transmission via a serial port, both the transmitter and the receiver must normally be ready to operate
simultaneously since the TMS320CXX has only a single word of internal buffer memory apart from the transmit and
receive buffers. If a'SN74ACT2229 FIFO is switched into the communication channel, both transmitter and receiver
do not need to transfer data simultaneously. Each participant can complete the data transfer when time allows. The time
that is saved is available for processing other jobs.
Figure 19 shows the connection of two TMS32OC30 devices. The connection of an analog interface circuit (AlC) to a
TMS320C30 is made similarly. Since two independentFIFOs are integrated into a single SN74ACT2229, full-duplex
operation is possible with only one package.
3-158
TMS320C30
TMS320C30
SN74ACT2229
IR
WRTCLK
WRTEN
XFO
CLKX
FSX
DX
RESET
256 x 1
FIFO
D
RESET
OR
RDCLK
RDEN
XF1
CLKR
FSR
DR
r---
-
r--256 x 1
FIFO
Q
-
r+
OR
RDCLK
RDEN
XF1
CLKR
FSR
DR
g
IS
WRTCLK
WRTEN
D
RESET
r
XFO
CLKX
FSX
DX
RESET
RESET
RESET
Figure 19. Connection of Two Signal Processors via a Serial Port
With the Help of the FIFO SN74ACT2229
Teletext Decoders
With teletext, pages of text are transmitted as digital infonnation in addition to the nonnal television signal. To be
compatible with existing TV receivers, this digital infonnation is transmitted in the picture-frequency blanking interval.
The invisible picture lines, sent during beam flyback but after those for picture synchronization, contain the digital
teletex data instead of picture infonnation (see Figure 20). With D2-MAC, 360 bits with a bit rate of 20.25 Mbit/s are
transmitted per TV line; therefore, the teletext infonnation occupies 17.8 JlS of the 64 JlS for which the TV line lasts.
In this example, a D2-MAC decoder extracts the digital teletext infonnation from the television sigual and conducts it
to a 512 x 1 FIFO (see Figure 21). The D2-MAC decoder writes the data block by block at a rate of 20.25 Mbit/s into
the FIFO. The teletext module is now able to read out and process the 360-bit digital infonnation within 64 JlS at a
significantly slower rate of up to 5.625 Mbit/s. In this example, the FIFO undertakes the adjustment and synchronization
of the two different rates.
,..-_-===============::::::::::::==_
+.
Picture
=-_=======::=:::::;::::::::::::__
~~
I
I
I
~~
I
Horizontal
Synchronous Pulses
~I~I I
I
Vertical
Synchronous Pulses
I I
I
Horizontal
Synchronous Pulses
Figure 20. Video Signal
3-159
Teletext
Teletext
Data
Data
22.25MH
D2-MAC
Decoder
C
B8-BO _ _ _.JX,-_D_..JX,-_C_..JX,-_B_..JX,-_A
__
so S1
S2 S3 S4 -
Select byte-sIze JltUe endlan
Write byte 0 at poslUon 1; wrItes to FIFO dIsabled
Write byte C at poslUon 2; wrItes to FIFO dIsabled
WrIte byte B st posItIon 3; wrItes to FIFO dIsabled
WrIte byte A at posItIon 4; load fuJI 3&-blt long word to memory
Figure 8. Input Registers and Timing for Write Operation During Byte-Size,
Little-Endian Configuration
3-171
Effect on Status Flags
Bus sizing affects the operation of the almost-empty (AEB) and almost-full (AFB) flags associated with port B and, to
some degree, the empty (EFB) and full (FFB) flags. The almost-empty and almost-full flags can be programmed to one
of the preset values of 4,8,12, or 16 during device reset. These depths are based on full 36-bit words. When used with
bus sizing, the internal flag still reacts to the programmed depth to a multiple of the byte or word size selected. For
example, if a depth of eight long words is programmed and byte sizing is selected, the AEB flag indicates when there
are 32 bytes remaining to be read from FIFO 1 before it goes empty. This results from the internal flag reacting to eight
long words remaining in the memory. Due to the byte size being selected, it takes 32 read-clock'pulses to unload them.
Similarly, if a depth of four long words is programmed and a bus size of 18-bit words is selected, the AFB flag reacts
when there are eight more valid CLKB pulses before FIF02 is written full. This is based on the need for two write-clock
pulses to load each long word into memory and the internal flag reacting when there are four available locations
remaining in the memory.
The empty and full flags for port B still indicate when the,associated boundary condition is met during sizing operations
because the internal flags for FlFOl and FIF02 are based on 36-bit words only. The write to FIF02 memory during
bus-size mode occurs on the last byte or word of the full 36-bit word being loaded. This means FFB does not indicate
a full condition until all four 9-bit bytes (or both 18-bit words) of the last full long word are clocked into FIF02. If, for
instance, only three of the bytes are loaded during byte sizing, the internal write to memory has not occurred yet, and
the status flag does not indicate full until the last byte is clocked in and the internal write to FIF02 memory takes place.
Likewise, due to an internal long-word read access being performed at the beginning of a bus-sized byte or word transfer,
the internal empty-flag status updates immediately, since FIF01 has effectively been read empty. However, in the
instance of byte sizing, there are still three bytes remaining in the pipeline to be shifted out before the user considers
the EFB flag to be valid. To provide a proper empty-flag indication, the same signal that disables the internal memory
accesses during remaining byte (or word) transfer is combined with the synchronized empty-flag~ut signal and
prevents it from switching until the final byte (or word) is clocked to the outputs. This results in the EFB flag correctly
indicating when the empty-boundary condition occurs, regardless of the bus size chosen.
Dynamically Changing the Bus Size
Many applications select a bus size at system initialization, which remains fixed due to the architectural design of the
system. However, applications that require dynamic bus sizing to be performed can use the SN74ABT3614 to provide
an effective interface. To avoid data loss when making the transition, the following explanation is provided. Mailbox
operations, which are selected with bus-size control terminals, also are discussed.
Bus-size selections must be made one cycle before they are to take effect. The values present on SIZO and SIZ1 are stored
in registers XFF1 and XFF2 on the rising edge of CLKB as shown in Fignre 9. This latency allows the control logic t<;>
be set up for the next transfer, resulting in short setup and hold times for these inputs and allows comparisons to the
previous state of the inputs to determine if an actual change in bus size is being requested. This is important when using
the size inputs to enter mailbox mode, then returning to the previous size for FIFO operations.
In Figure 9, exclusive NOR (XNOR1 and XNOR2) gates are used to compare the current state of the size inputs to the,ir
previous states. If either input is changed from its previous state, the signal COUNT_RES is driven low. This signal is
a synchronous reset to the counters that keep track of the byte or word count. When a size change is requested, the rising
clock edge that loads the new size value into the registers also resets the counters, ensuring proper byte tracking of the
new size beginning with the next clock pulse. If a size change is requested before the last byte/word is transferred from/to
the FIFO, the remaining data is lost or the entire word is not written (see Figure 10).
3-172
SWO~~------------------------------~~
SW1~~------------------------------~~
XFFO
FF RES
.....
~
Clock
Reset
D
XFF1
FF_RES
Clock
SIZO
XNOR1
Reset
XFF2
FF RES
Clock
SIZ1
XNOR2
Reset
.>o--+t-l D
XNOR3
Clock
Q
Reset
Figure 9. Size-Control Block
In the special case of mailbox operations, which use the size inputs to select mailbox mode on port B, it is essential not
to interpret this as a change in bus size. When SIZI and SIZO inputs are driven high (mailbox mode), COUNT_RES is
disabled (along with the counters) and the size registers are not updated (see XNOR2 in Figure 9). This allows mail
operations to take place without disturbing any data transfers to/from the FIFO.
3-173
RCLK
0_,_1_____X'--________O_,O_ _ _ _ _ _ __
SIZO, SIZ1 _ _ _ _ _
W2A
X W2B X W2C X W3 X W4 X W5
X~__
(a) TIMING FOR CHANGE FROM BYTE SIZE TO LONG WORD, LOST LAST BYTE OF WORD 2
0,1
SIZO,SIZ1
Data
!!V<
0,0
X
W1D X W2A X W2B X W2C X W2D X W3 X W4 X W5
(b) TIMING FOR CHANGE FROM BYTE SIZE TO LONG WORD, NO DATA LOSS
WCLK
1_,_0___.IX'--________O,_O_ _ _ _ _ _ _ _ __
SIZO, SIZ1 _ _ _ _
Input
3<
W2A X W2B X W3A X W4 X W5 X
LO~:: --W-1-A~+-W-1B-""'Xr. . ===W=2A=+=W=2=B==:Xr-W-4~Xr-W5~X
we
X....__C
we X. . ____
(e) TIMING FOR CHANGE FROM WORD SIZE TO LONG WORD, WORD W3A IS NOT WRITTEN
1,0
SIZO,SIZl
Input
Data
Loaded
X
0,0
3<
W2A X W2B X W3A X W3B X W4 X W5 X
W1A+W1B X W2A+W2B >E3A +W3BX W4 X W5 X
C
(d) TIMING FOR CHANGE FROM WORD SIZE TO LONG WORD, NO DATA LOSS
Figure 10, Dynamically Changing Byte-/Word-Slze Transfers to Long-Word Data Transfers
3-174
Byte Swapping
Four different modes of byte-order arrangement (byte swap, word swap, byte-word swap, and no swap) can be
performed with any port-B size selection. When byte swap is performed, the order of the bytes are rearranged within
the long word but the bit order remains the same. The port-B swap-select (SWI and SWO) inputs are used to achieve
these byte-order arrangements. Table 2 lists the levels on the SWI and SWO input terminals and the respective size
implemented. Figure II shows the different schemes of byte swap.
Table 2. Control of Byte-Swap Operation on Port BUsing SW1 and SWO
Port A
PortB
PortA
SW1
SWO
L
L
BUS CONFIGURATION
No swap
L
H
Byte swap
H
L
Word swap
H
H
Byte-word Swap
PortB
PortA
Port B
PortA
Port B
~
cifB
~
~
(a) No Swap
(b) Byte Swap
(e) Word SWap
(d) Byte-Word Swap
Figure 11. Byte-Swap for Long-Word-Size Data Transfers
The byte swap is performed with any port-B size selection. Byte-order arrangement is implemented by the levels on the
port-B swap select inputs on a CLKB rising edge that reads a new long word from FIFOI or writes a new long word
to FIF02. When long-word-size (36-bit) transfers are selected on port B, the byte-order arrangement can be changed
on each clock cycle. On the other hand, when byte (9-bit) or word-size (I8-bit) transfers are selected on port B, the byte
order chosen on the first byte or word of a new long-word read from FIFO I or written to FIF02 is maintained until the
entire long word is transferred, regardless of the swap-select input states during subsequent reads or writes. This implies
that for byte- or word-sized data transfers, the byte-order arrangement can be changed only on the first byte or word data
transfer of a new long-word read. Simultaneously performing a byte swap and bus size on port B results in the sequence
of events shown in Figure 12.
3-175
FIF01 Reads
FIF01 Writes
No
Yea
36-Blt Long Word
Storad In FIF02 SRAM
In ~pped Order
Figure 12. FIF01 Data-Read and FIF02 Data-Write Sequence
During Simultaneous Bus-Sizing and Byte-Swapping Operations
3-176
Parity Generation and Checking
Parity Checking
The odd or even parity-checking function can be selected on both port A and port B using the ODDIEVEN input. Four
parity trees examine the parity of incoming or outgoing data bytes on each port as shown in Figure 13. Port-A bytes are
arranged as AO-A8, A9-Al7, A18-A26, and A27-A35, with the most significant bit used as the parity bit. A parity
error on each of these four bytes is indicated internally by a low signal on the individual-error (ER) flag. These four ER
outputs are combined to output a single parity-error (PEFA) flag that indicates an error on one or more bytes on
portA.
Similarly, port-B bytes are arranged as BO-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit used
as the parity bit. Again, a single parity-error (PEFB) flag indicates an error on one or more bytes on port B. During the
port-B sizing operation, the internal flag output for invalid data bytes is disabled; the parity-error flag indicates an error
only on the bytes that are valid for the particular size selected. Parity checking on both ports is a passive operation; the
port parity-error flags can be ignored if this feature is not desired.
ODD/EVEN - - - - ,
BE---,
ODD/EVEN
SIZ1
SIZO
B35
A35
9
9
ER
ER·
ER
ER
ER
ER
ER
ER
9
9
9
9
9
9
BO
AO
Figure 13. Parity-Checking Block Diagram
Parity Generation
Parity generation for port reads from the FIFO or mailbox can be selected using the parity-generate select-input terminal
for that port (pGA or PGB). ODDIEVEN selects the type of parity generated. Port-A bytes are arranged as AD-A8,
A9-A17, A18-A26, and A27-A35, with the most significant bit used as the parity bit. Port-B bytes are arranged as
BO-B8, B9-B17, B18-B26, and B27-B35, with the most significant bit used as the parity bit. A write to the FIFO or
mailbox stores all 36 bits regardless of the state of the parity generate select (PGA) input. When data is read from the
FIFO, the lower eight bits of each byte are used to generate the parity bit as shown in Figure 14. If parity generation is
selected (PGA - 1), the levels originally written to the most significant bits of each byte are substituted by the generated
parity bit as the word is read to the outputs. Otherwise, the levels originally written to most significant bit of each byte
are output.
3-177
ODD/EVEN
MemorY
PGB
P
Output
Register
8
Date
Input
BO-B8
Parity
Generator
Memory Out
Figure 14. Parity-Generation Block Diagram
Parity generation on mailbox reads for a port is performed by the four parity trees used to check the parity on the inputs
to the port. When odd- or even-parity generation is selected on a port-A or port-B read from the mailbox, the port
parity-error (pEFA or PEFB) flag is held high regardless of the state of the inputs AO-A35 or BO-B35. The generated
parity does not change the contents of the mailbox register.
Internetworking
Intemetworking is the process of connecting a variety of local-area-network (LAN) and wide-area-network (WAN)
computer systems and related devices to build the communications infrastructure required to satisfy the needs of an
organization. Bridges and routers are two key devices that provide intemetworking capability (see Figure 15).
Layer 7 - Application
Layer 6 - Presentation
Layer 5 - Session
Layer 4 - Transport
Layer 3 - Network
Layer 2 - Data Link
Layer 1 - Physical
t
EtherNet
(a) OSI REFERENCE MODEL
t
Token Bus
t
Token Bus
(b) BRIDGE
t
X.25
(c) ROUTER
Figure 15. Bridge and Router Devices
Bridge and router designs are critical in meeting the increasing bandwidth requirements and volume of data transfer in
existing network elements. The use of FlFOs in these designs provides a viable means for improving the system
performance. The FlFOs provide a link between the communications processors and buses operating at different speeds
and data widths. The handshaking signals for control can provide operating speeds that match the bus-communication
speeds.
3-178
A bridge operates at the data-link layer (layer 2) in the OS1 model to connect two similar LANs. A bridge reads the
destination address contained on each incoming packet and uses the address to transmit the packets or to ignore them.
This process is known as address filtering. An example of a bridge design using multiple FIFOs is shown in Figure 16.
-.-
-
~
Serlal-ta-Parallel
Conversion
Data
---4
Control Block
Address Generation
Data Multiplexing
Read/Wrlta
Control
FIFO
Flags
Data
Data
Control
FIFO
Parallel Data
to FIFOs
Data
Flags
f-+- To Host Bus
r+r+- .. I
r+-
~
I Microprocessor
I
Figure 16. Implementation of a Bridge Using FIFOs
A router, on the other hand, operates at the network layer (layer 3) in the OS1 model and can be used to connect two
different networks; therefore, a router has the added complexity to perform frame conversion in addition to address
filtering.
For example, in the situation where devices on a WAN communicate with the devices on a token-ring LAN, the
interconnecting device is required to convert HDLC frames to token-ring frames and vice versa as shown in Figure 17.
~r----------------~~----------------,
I
Layer 2
T1
36
36
36-Blt
Router Bus
Layer 2
1-4..,16"+0-1 Token-Ring HI-?''+-I
Controller
L ___________________________ _
Figure 17. WAN to Token-Ring Router Using SN74ABT3614 FIFO
3-179
The layer-2 device provides the functions of flag generation and detection, zero-bit insertion and deletion,
cyclic-redundancy-check (eRC) generation and detection, and abort generation and detection. The layer-2 device
interfaces with the T1 transceiver on the line side. The SN74ABT36l4 FIFO provides a bidirectional buffer between
the layer-2 device and the high-speed router bus. In l¥idition, if the layer-2 device has a 36-bit interface on the bus side,
the bus-matching function on the SN74ABT36I4 device is used to interface to a high-speed 36-bit bus. Similarly, the
layer-2 device provides the necessary token-ring LAN protocols and links the token-ring LAN controller to the router
bus. The SN74ABT36I4 is used to match the data width and rates between the token-ring controller and the 36-bitrouter
bus. A FIFO solution implemented in the hardware offers a speed advantage over the latency for a software setup
performing the same functions.
Conclusion
The SN74ABT3614 is a clocked, bidirectional 64 x 36-bit member of TI intemetworking family ofFIFOs. This FIFO
integrates the glue logic necessary to simplify design of communications networks. In addition to providing the
traditional FIFO function of removing input/output bottlenecks, this FIFO provides full functionality for bus-sizing,
byte-swapping, and parity-generation checking logic, and mailbox operations. These functions are necessary for
effective communication between microprocessors, communicatious processors, and buses. The SN7 4ABT3614 FIFO
can operate at frequencies up to 66 MHz and can provide data access times as fast as lins. The FIFO also is available
in speed sorts to provide 33-MHz and 50-MHz operation.
3-180
High-Speed, High-Drive
SN74ABT7819 FIFO
Teruo Ishii and Navid Madani
Advanced System Logic - Semiconductor Group
~TEXAS
INSTRUMENTS
SCAA016A
3-181
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable althe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications'').
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-182
Contents
TItle
Page
Introduction ............................................................................ 3-185
Structure ..... .......................................................................... 3-186
High-Speed Performance ................................................................. 3-186
High-Drive Capability .................................................................... 3-186
Incident-Wave Switching Capability ........................................................ 3-187
VME Backplane Drive . .•................................................................. 3-190
Summary .................................... ............................................ 3-191
Reference .............................................................................. 3-191
Figure
List of lliustrations
Title
Page
1
SN74ABT7819 Block Diagram ...................................................... 3-185
2
Output Wavefonn at 80-MHz Clock (CL - 50 pF) ........................................ 3-186
3
Output Characteristics of the SN74ABT7819 (Vee - 5 V, TA - 25°C) ........................ 3-187
4
5
6
7
Shelf Voltage When Switching a Transmission Line ...................................... 3-188
Backplane Driven From End . . . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-190
Backplane Driven From Center. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3-190
Number of Slots Versus Shelf Voltage (Center Drive) ..................................... 3-191
~183
3-184
Introduction
First-in, fIrst-out (FIFO) memories are used as high-speed data-stream buffers for maximizing throughput between
buses having different data-transfer speeds, for example, between multiprocessors or a microprocessor and peripheral
circuits. Recently, the processing speed of microprocessors has become so fast that the gap between the speed of the
microprocessor and peripheral circuits has widened. As a result, the demand for faster FIFOs that can maximize the use
of the microprocessor capabilities has increased. Usually, when a memory integrated circuit drives a heavy-load bus line,
external bus buffers are required. FIFO memories, however, help to minimize the design complexity and cycle time by
providing the capability to buffer data while at the same time directly driving the bus line.
The Texas Instruments SN74ABT7819 is a high-speed, high-drive, advanced BiCMOS FIFO with operating
frequencies up to 80 MHz and a drive capability ofl()H/IoL - -12124 rnA (see Figure 1).
PENA
RENA
WENA
CSA
Port-A
Control
logIc
WiRA
t
I Read
I Polntar
ClKA
RSTA
I
t
j,
18
: Raglstar:
512 x 18
Dual·Port SRAM HRaglstar
FIFOB-A
18
+
18
-+---+-I PoInter
WrIte
I
Flag
logIc
FIFOB-A
ORA
AO-A17
-
IRB
AF/AEB
HFB
8
~ BO-B17
8
IRA
AF/AEA
HFA
I Write
"I
Flag
logIc
FIFOA-B
ORB
I PoInter
t
18
I Raglster
r.-
512x 18
Dual·Port SRAM
~ HRaglstar
FIFOA-B
I
..."
t
Read I
Polntar
I
RsrB
ClKB
Port·B
Control
logIc
CSB
WiRB
WENB
RENB
PENB
Figure 1. SN74ABT7819 Block Diagram
3-185
Structure
The SN74ABT7819is a512x 18 dual-port bidirectional clocked FIFO (see Figure 1). It comprises two SRAMs (FIFOA,
FIFOB), specific circuits for controlling these two SRAMs, and II 0 registers. Read/write operations are carried out on
the SRAMs at the low-to-high transition of their respective free-running clocks, CLKB and CLKA. Read/write
operations are synchronized by independent clocks from the system. Likewise, EMPTY and FULL flags are
synchronized with independent clocks from the system. Neither an external clock-enable circuit nor an external circuit
for synchronizing output flags to the clocks are required. Output data is buffered by output registers and can be enabled
at alL times. These features facilitate design by eliminating the need for detailed timing considerations, especially in
applications requiring high-speed operation.
High-Speed Performance
The SN7 4ABT7819-12 is a high-speed FIFO memory with an access time of9 ns (at CL - 50 pF). Operation is specified
for free-running clock (CLKA, CLKB) inputs of up to 80 MHz. These high-speed characteristics allow microprocessor
time management to be reduced and allow an efficient system to be configured. Figure 2 shows the waveform of output
data read by an 80-MHz clock.
7
6
5
>I
;
~
'S
S-
4
11
3
I
2
J
J
I
II
a
I
~
,/'
11
/
r-
0
-1
~
lr
,..,J
~
lr
L
,.,1
-2
-3
O.
10
20
30
40
50
60
70
60
90
100
t-Tlme-nl
Figure 2. Output Waveform at SO-MHz Clock (CL = 50 pF)
High-Drive Capability
The advanced BiCMOS SN74ABT7819 comprises a bipolar-output circuit that achieves a high-drive capability.
Figure 3 shows the output characteristics for the SN7 4ABT7819. Output impedance is equivalent to about 30 0 at high
output and 50 0 at low output. Output impedance values for the SN74ABT7819 are equivalent to the output impedance
for FAST and BCT bus-interface logic; therefore, a designer can effectively implement the SN74ABT7819 as an
interface to a bus line.
3-186
1.1
5.5
5
>
> 4.5
I
I
!
0.9
CD
G)
al
I
4
~ 3.5
'$
3
:::I
,..- V
.s-
0
./
1.... 2.52
.J:.
al
:E 1.5
~
I
J:
.p
0.5 /
~
~
'$
.s-:::I
V"
0.8
0.7
0.6
0
]
~
....~
V ""'"
!oJ
.p
0.5
0.4
0.3
0.2
0.1
o
-100 -90 -80 -70 -80 -50 -40 -30 -20 -10
0
/
o
o
IOH - High-Level Output Current - mA
........
10
20
~~
30
40
-
50
........
~ ~-
60
70
80
90 100
IOL - Low-Level Output Current - mA
Figure 3. Output Characteristics of the SN74ABT7819 (Vee
=5 V, TA =25°C)
Incident-Wave Switching Capability
When specific data (rectangular wave) is carried over the transmission line, data is influenced by the impedance of the
transmission line, introducing distortion in the data waveforms. This distortion can cause a mismatch in required
data-transfer speed; therefore, the characteristic impedance of the transmission line must be considered in the system
design. The following describes the relationship between the output characteristics of the SN74ABT7819 and the
transmission line.
The impedance of the transmission line and the drive capability of the device can introduce distortion in the waveforms
at the low-to-high and high-ta-Iow transition referred to as shelf voltage. The shelf voltage lowers as the impedance of
the transmission line and the drive capability of the device decrease. The shelf voltage is expressed by the following
equations and is shown in Figure 4.
Zo
V OHS = ZONH X Zo X V OH
(a low-to-high transition)
(1)
ZONL
xZ
XVOH
ONL
(a high-to-Iow transition)
(2)
VOLS=Z
o
Where:
V OHS VOLS V OH ZoNH
ZONL =
Zo
=
Shelf voltage at the low-to-high transition (V)
Shelf voltage at the high-to-Iow transition (V)
High output voltage of device (V)
High output on resistance of device (0)
Low output on resistance of device (0)
Impedance of transmission line (0)
3-187
v
SN74ABT7819
------,
VOH
I
l ! l'
VOH
~~--11
"'""" .. 0
Pol"
","L. 50
VOHS
VOLS
-
------1
------
Time
Figure 4. Shelf Voltage When Switching a Transmission Line
When a low-impedance line is driven by a device with high output resistance, the sbelfvoltage occurs in the threshold
region, causing delay in establishing the transmitted logic. In order to drive a low-impedance transmission line without
any performance degradation, a high-drive capability is required.
On the bus lines of backplanes or memories, the impedance of the transmission line drops as load capacitance is
distributed over the transmission line. Generally, the characteristic impedance and the propagation delay time of the
transmission line are shown by the following equations:
(3)
(4)
Where:
Zo
=
LO Co -
tpd -
Impedance of transmission line (0)
Impedance per unit length (H)
Capacitance per unit length (F)
Propagation delay time of transmission line (s/m)
When the load capacitance is applied on the transmission line, the characteristic impedance and the propagation delay
time of the transmission line are changed as follows:
(5)
(6)
Where:
Z'
-
tpd'
=
Cl
-
Impedance after application of capacitance (0)
Propagation delay time after application of capacitance (s/m)
Applied capacitance (F)
Example
The effect of loading a Zo - 100 0 and tpd - 7 ns transmission line with 8-pf loads equally spaced at 3-cm intervals is
calculated in equations 7 and 8. The high- and low-output impedance necessary to drive the loaded transmission line
with no settling time delay is calculated in equations 9 and 10.
3-188
From equations 3 and 4:
1.0 - Zo x tpd Co -
100 x 7 x 10--9 - 700 nHlm - 21 nHl3cm
tpdZo -7 x 10--9/100 -70 pF/m -
2.1 pF/3cm
Substituting for Co in equations 5 and 6:
Zo'
=
Zo
~
1+
= -;:.=~100~:::;:=;:~ = 45.6
V ic;
tpd'
r.!
(7)
8x10-12
1 + 2.1 X 10-12
= tpd V~
1 + Co = 7 x
-9
10
8 X 10-12
1 + 2.1 X 10-12
= 15.4 ns / m
(8)
The values calculated by equations 7 and 8 are Zo' - 45.6 a and tpd' - 15.4 nslm, respectively. The propagation delay
time of the transmission line is about doubled, and the impedance of the transmission line is about halved. The output
impedance required of a device to drive this transmission line without a settling time delay is calculated by the following
equations:
(high-output impedance)
Z'
2SZ0NH~ZOXVOH
(9)
45.6
x 35
2 <
- ZONH + 45.6
.
ZONH S 34.2 r.!
(low-output impedance)
0.8 ~ Zo'
ZONL
+ ZONL X VOH
(10)
ZONL S 13.5 r.!
The transmission line must be driven by a device having an output impedance of 34 a or less at high output and 13 a
at low output; therefore, this transmission line can be driven with the SN74ABT7819.
3-189
VME Backplane Drive
Since the drive perfonnance of almost all memory integrated circuits is low, it has been difficult to drive memory lines
or backplane buses directly; therefore, external bus buffers have been required to interface a memory to a bus driver.
Now the SN74ABT7819 allows direct driving of medium-scale bus lines.
Figure 5 shows the wavefonn of a 12-s10t VME backplane driven by an SN74ABT7819 FIFO from the line end.
Although wavefonn distortion caused by multiple reflection due to the 3-cm stub length and DIN connector occurs, there
is no influence of reflection in the threshold region; therefore, when the SN74ABT7819 drives the VME backplane from
the end, direct driving is possible. However, when the 12-slot VME bus is driven from the center, the backplane line
is regarded as a branch pattern and the impedance becomes one-half the impedance at that point, resulting in generation
of a step in the threshold region (see Figure 6). For this reason, a bus buffer having a higher drive capability is required.
7
7
6
6
5
5
4
4
rvf
!.oj"'"
3
>
I
2
:I!!
~
>I
:I!!
812
81
~~
-
-1
-2
o
20
30
VCC=5V
40 50 60 70
t-Tlme-ns
80
rt
sa
I
812
" .... I£.
o ::r--
1\1
-1
-2
90 100
VCC=5V
o ro
~
~
~
~
80
t-Tlme-ns
VCC=5V
~
80
80 100
VCC=5V
3300
mo
3~0
4700
4700
4700
Pulse
Generator
Figure 5.. Backplane Driven From End
3-190
2
-3
10
Il ~
3
~
J
0
-3
"-
Pulse
Generator
Figure 6. Backplane Driven From Center
Figure 7 shows the stepped levels when the VME bus is driven from the center slot by the SN74ABT7819. The influence
of multiple reflections increases and the level of the shelf approaches the threshold region as the number of slots
increases (the transmission line of the backplane is optimized corresponding to the number of slots). Based on these
results, a design of five or fewer slots is preferable for driving with sufficient margin,to preclude unwanted delay and
possible data errors.
2.5...-----------------...,
1.5
6
8
10
12
Number of Slots
Figure 7. Number of Slots Versus Shelf Voltage (Center Drive)
Summary
The SN74ABT7819 is a high-speed, high-drive capability FIFO memory that meets the high-speed data-transfer rate
requirements and drives the bus lines directly. This application report presents the essential points that a designer should
consider in using a SN74ABT7819 for high-speed data transfer. The importance of drive capability and the influence
of distortion is explained. Comprehending the relationship between drive capability and transmission line characteristics
is essential to obtain the best performance of the SN74ABT7819.
Reference
Bus-Interface Circuits Application and Data Book, Texas Instruments Incorporated, 1990
3-191
3-192
SPARe MBus-to-Futurebus+ Bridge
Using the Texas Instruments
Futurebus+ Chipset
Robert Gugel
Mixed Signal Product Group
~TEXAS
INSTRUMENTS
SCAA019A
3-193
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with TI's standard warranty. Testing and other quality control
techniques are utiiized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessariiy performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-194
Contents
Title
Page
Introduction ••••••••••••••••••.•••••••••••••..••••.••••••••••••.•••••••••••••••••••••••• 3-197
Transaction Support •••••••••••••••.•••••••••.••••••••••••••••••.•••••••••••••••••••••••• 3-197
Bridge Architecture ••••••••••••••••••••••••••.••••••••••••••••••.•••••••••••••••••••••••• 3-199
Command •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.•• 3-200
Address ................................................................................ 3-200
Direct-Memory Model .................................................................. 3-200
Page-Memory Model ................................................................... 3-200
Datapatb ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••. 3-201
Considerations ......................................................................... 3-201
Byte-Lane Mapping .................................................................... 3-201
Control Logic ........................................................................... 3-203
Summary ............................................................................... 3-206
List of IUustrations
Figure
2
3
4
5
6
7
8
Title
Page
SPARCFB+ ......................................................................
MBus-to-HIP Bridge ...............................................................
MBus/FB+ Memory Map ...........................................................
Byte-Lane Mapping for a 64-Bit-Only System ...........................................
Byte-Lane Mapping for a 64-1 32-Bit System ............................................
Byte-Lane Mapping Showing Path Taken by Address Quadlet on HD ........................
MBus-Word Read to HIP Single-Read Transaction .......................................
MBus-Word Write to HIP Single-Write Transaction ......................................
3-197
3-199
3-201
3-202
3-202
3-203
3-204
3-205
3-195
3-196
Introduction
This application report describes the logic necessary to connect the SPARC MBus to the Texas Instruments (TI)
Futurebus+ (FB+) chipset host interface (HIP). This logic is a translator of MBus transactions to HIP transactions and
vice versa. The MBus-to-HIP bridge described is MBus level-I compliant. Level-I transactions are the
noncache-coherent subset of MBus level-2 transactionS. Even though level-2 transactions are occurring on the MBus,
they cannot cross the L1 bridge.
Figure 1 shows a block diagram of a FB+ module featuring a SPARC processor that can access FB+. The MBus-to-HIP
bridge block is highlighted. Since knowledge of FB+, the HIP, and MBus is necessary to understand this defmition,
references to the applicable specifications also are included in Figure I.
Memory
SPARC
L2MBu8
SPARC MBu8 Interface
Specification, Rev 1.2
TI Futurebu8+ Interface
Family Data Manual, Rev 1.2
Unceched FUtUrebU8+
NOTE: Reference IEEE P896.1 and P896.2
Figure 1. SPARe FB+
Transaction Support
A transaction originating on the MBus must be transported to the HIP and then to the FB+. This requires the L1 bridge
to be a slave to MBus transactions and a master to HIP transactions. Likewise, a transaction originating from FB+ is
transported to HIP and then to the MBus. In this case, the LI bridge is a slave to HIP transactions and a master of the
MBus transactions. Each of the three buses has a set of transactions that must be mapped to each other when crossing
bridges.
3-197
Table 1 shows the translation of MBus transactions to HIP transaction that is perfonned by the L1 bridge when it is a
slave to the MBus and a master of the HIP..
Table 1. MBus-to-HIF Transaction Mapping
MBUS TRANSACTION TYPE
Byte read fwrite
Half-word (2 bytes) readfwrite
RESULTING HIF TRANSACTION TYPE
DW32 single l-byte readfwrite partial
\ DW32 single 2-byte readfwrite partial
Word (4 bytes) readfwrite
DW32 single readfwrite
Double word (8 bytes) readfwrite
DW64 B-byte burst readfwrite
16-byte burst read fwrite
DW64 16-byte burst readfwrite
32-byte burst readfwrite
DW64 32-byte burst readfwrite
64-byte burst readfwrite
DW64 64-byte burst readfwrite
12B-byte burst readfwrite
Two DW64 64-byte burst readsfwrites
chained together with HIF MORE signal
Table 2 shows the translation of HIP transactions to MBus transactions that is perfonned by the L1 bridge when it is a
slave to the HIP and a master of the MBus. The data-width 32 (DW32) HIP bursts always cause 4-byte-wide transactions
on MBus, and data-width 64 (DW64) HIP bursts always cause 8-byte-wide MBus transactions. This means that dynamic
bus sizing from HIP to MBus is not supported by the architecture suggested.
Table 2. HIF-to-MBus Transaction Mapping
HIF TRANSACTION TYPE
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RESULTING MBUS TRANSACTION TYPE
DW32 single l-byte readfwrite partial
Byte readfwrite
DW32 single 2-byte readfwrite partial
Half-word (2 bytes) readfwrite
DW32 single 3-byte readfwrite partial
Half-word (2 bytes) readfwrite and a byte readfwrite
DW32 single readfwrite
Word (4 bytes) readfwrite
DW32 8-byte burst readfwrite
Two individual word (4 byte) readsfwrites
DW32 l6-byte burst readfwrite
Four individual word (4 byte) readsfwrites
DW32 32-byte burst read fwrite
Eight individual word (4 byte) readsfwrites
DW32 64-byte burst readfwrite
Sixteen individual word (4 byte) readsfwrites
DW64 8-byte burst read fwrite
Double-word (8 bytes) readfwrite
DW64 16-byte burst readfwrite
16-byte burst readfwrite
DW64 32-byte burst readfwrite
32-byte burst readfwrite
DW64 64-byte burst readfwrite
64-byte burst readfwrite
Bridge Architecture
Figure 2 shows suggested implementation of the MBus to HIP bridge.
-- -----------------------------------
COMMAN D
I MBus-Attrlbute I
63-36
T
~-
->
ADDRESS
FB+
Page
Register
L
MATTR
TvDe
Size
Lock
Encoder
J
TRW,DL,DW
---a4,
TBST, TSIZE, K
L
HIF-Attrlbute
Encoder
HATTR-J
-- ----------------------------------4
~
-r+-,-
36
,
Selected
t--
~
32
,
>
35-0
MBus
Page
Register
4
r--
-
HA (31-0)
-- ----------- ~------------------- -,---
DATA PATH
MAD (63-56)
MAD (63 -0)-
HA (31-24)
FIFO
64x36x2
MAD (31-24)
r--..
HD (31-24)
MAD (47-40)
HA (15-8)
MAD (15-8)
HD (15-8)
SN74ABT3614
-
- I>
r--..
<
-
MAD (55-48)
HA(23-16)
FIFO
64x36x2
MAD (23-16)
HD (23-16)
MAD (39-32)
r--..
HA(7-0)
MAD (7-0)
HD (7-0)
HD (31-0)
SN74ABT3614
-
-I-'
"CONTROL
HCLK
------------ -F- r----------------------r
V
MATTRY, MRTY, MERR
MBC
-
-
I-+- HATTR
I--
HFC
4
BR,MBG,MBB
I
I
MORE, HIP, HAS, HDS,
DSACK (1 -0), ---Y,
BSTRD
BSTAT(1-0)
MS (1-0)
BSTRDY
L---~
HBR, HBG,
GACK
Figure 2. MBus-to-HIF Bridge
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A typical bus-bridge implementation consists of command, address, datapath, and control logic. The operations of these
sections in this design are as follows:
Command
The host interface defines a set of discrete signals that indicate the attributes (i.e., type, size, etc.) of the transaction taking
place. The MBus does the same thing; however, these signals are multiplexed onto signals in the field MAD (63:0) that
are not used to carry the address during the address phase of transactions. These command attributes also are logically
encoded differently by the two buses.
When a slave to MBus, the command section of the L1 bridge must latch the transaction-specific information from
MAD (63:36) during the address phase and encode it into host-interface attributes that correspond to the resulting
transaction to be mastered on the host interface.
When a slave to the host interface, the command logic encodes the HIP's attribute signals into MBus attributes that
correspond to the resulting transaction to be mastered on the MBus. These encoded MBus attributes must be multiplexed
onto MAD (63:36) along with theMBus address during the MBus-address phase.
Address
The host interface has a 32-bit physical address space with a 36-bit extension. The MBus defmes a 36-bit
physical-address space. The address portion of the L1 bridge logic must dO three things:
Recognize the address region that it must respond to as an MBus slave and as an HIP slave
Transport the physical address from one protocol to the other
Relate one bus-memory region to the other
Direct-Memory Model
The simplest memory model would be a logically direct connection between the MBus 36-bit address and the HIP 36-bit
address. This would mean that all MBus addresses not within FB+ MEM_BASE and MEM_BOUND or UNIT_BASE
and UNIT_BOUND would be mapped into the lower 64 Gbytes of the 64-bit FB+ address region. It would also mean
. that all MBus memory would be accessible from FB+ (between MEM_BASE and MEM_BOUND) and no MBus
memory would be private.
Page-Memory Model
A slightly more complex memory model is defined here that allows for private memory on the MBus.
When a slave to the MBus, a 4-bit FB+ page register is used to map one of 16 4-Gbyte MBus memory regions into the
FB+ 32-bit address space. Within the 4-Gbyte FB+ page, the MEM_BASE and MEM_BOUND registers contained in
the TI FB+ chipset point to local public memory on the MBus. Other addresses within the page but outside of
MEM_BASE and MEM_BOUND are remote addresses and are transported to FB+ via the HIP.
When a slave to the host interface, the MBus-page register is used to map the incoming 32-bit FB+ address to one of
16 4-Gbyte MBus memory regions. Within the 4-Gbyte MBus page, the ME~BASE and MEM_BOUND registers
contained in the TI FB+ chipset point to memory on the MBus, which can be accessed from FB+.
If the FB+ and MBus page are kept the same, the addresses outside the page are private (he., not accessible by the other
bus).
Figure 3 shows the memory mapping between MBus and HIP for the page-memory model.
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16 x 232
Page 15
-
15 x 232
FB+ Page Register
Private MBuI Memory
FB+
Page
Register
~
Page 2
2
'" '" _----+------1 MEM_BOUND
- ---
l,-'"
4 x 232
x 232
Page 1
i'~--,
,,
,,
232
Page 0
0
,.
"
' ..."-_ _ _ _ _...... 0
MBuI
FB+
Figure 3. MBus/FB+ Memory Map
Datapath
Considerations
There are several considerations when designing the datapath interface between the MBus and the host interface.
•
•
•
•
•
Since MBus runs at 40 MHz nominally and the HIP at 20-2S MHz, a FIFO is needed to synchronize the two
different time domains.
MBus has a big-endian datapath and requires that words and half words be word and byte aligned. The HIP
has no endian preference with the exception of big-endian access to FB+ CSR space.
MBus always multiplexes address and data on 64 signals; the HIP has demultiplexed address and data when
the data width is 32 bits, and multiplexed address and data when the data width is 64 bits.
MBus does 1-,2-,4-, and 8-byte nonburst (word) and 16-, 32-, 64-..and 128-byte burst transactions while the
HIP does 1-,2-,3-, and 4-byte nonburst (single) and 8-, 16-,32-, and 64-byte burst transactions. MBus bursts
are always of data width 64. HIP bursts can be of data width 32 and 64.
MBus has no parity protection on its address/data lines. The HIP address/data lines do have parity; however,
the TI chipset can generate parity internally and pass it on to FB+ when sourcing data to FB+.
Taking the above considerations into account requires the use of two bidirectional FIPOs capable of being clocked at
40 MHz. These FIPOs need to be 32 bits wide and 64 words deep. They need empty/full flags, clock enables, and
port-direction control. A byte-swap function within a 16-bit word also is required. The TI SN74ABT3614 is an ideal
candidate.
Byte-Lane Mapping
FB+ systems require address invariant byte-lane mapping. This means that data byte 0 (the byte pointed to by byte
address 0) always appears onFB+ AD (7:0). MBus systems require that data transfers ofless than a double word (8 bytes)
be aligned. Figure 4 shows byte-lane mapping between MBus, the FIFOs, the HIP, and FB+ for a 64-bit implementation
only.
3-201
HA
HA (31)
Byte 3
MAD (63)
AD (63)
Byte 0
Byte 7
Byte 6
Byte 1
FIFO
Byte 2
Byte 5
Byte 3
FB+
Chipset
Byte 4
Byte 4
Byte 3
Byte 2
Byte 5
FIFO
Byte 1
Byte 6
Byte 7
Byte 0
MAD (0)
AD (0)
Byte 0
MAD
FB+
HD (0)
HIF
Figure 4. Byte-Lane Mapping for a 64-Blt-Only System
Since 32-bit data transfers can take place on FB+ and the HIF, quadlet (4-byte word) steering is required to correctly
align 32-bit data quadlets from the HIF to those of the MBus. Quadlet steering of this type require a cross-point switch
with two 32-bit ports on each end. This could be implemented with four pairs of 16-bit Widebus™ transceivers; however,
this is expensive in terms of board space and datapath performance. A FIFO with the ability to swap bytes within 16-bit
words performs the quadlet-steering function with the byte lanes wired as shown in Figure 5.
HA
FIFO
AD (63)
MAD (63)
Byte 0
Byte 7
Byte 1
Byte 6
Byte 2
Byte 5
HA(O)
Byte 3
FB+
Chipset
Byte 4
HD
Byte 4
Byte 3
HD (31)
Byte 5
Byte 2
Byte 6
Byte 1
Byte 7
Byte 0
MAD
FB+
AD (0)
MAD (0)
HIF
Figure 5. Byte-Lane Mapping for a 64-/32-Blt System
Wldebus is a trademark of Texas Instruments Incorporated.
3-202
An example of this quadlet steering in action is the following scenario: the TI FB+ chipset is a slave to a single-beat
DW64 write transaction on FB+ (8 bytes). The chipset's 64-bit HIP enable bit is not set; therefore, it perfonns
4-byte-wide, 8-byte burst writes onto the HIP. This HIP burst write contains two 4-byte data phases. The first data is
an even-address quadlet and needs to be steered to MAD (63:32). The second data is an odd-address quadlet and needs
to be steered to MAD (31 :0). Figure 6 shows the datapath for the odd-address quadlet.
HA
FIFO
~--'HA(31)
r----, AD (53)
MAD (53) r----,
Byte 0
Byte 7
Byte 1
Byte 5
Byte 2
Byte 5
Byte 3
FB+
Chipset
Byte 4
Byte 4
Byte 3
Byte 5
Byte 2
Byte 5
Byte 1
Byte 7
Byte 0
'-_..I AD (0)
MAD (0)
MAD
FB+
HIF
Figure 6. Byte-Lane Mapping Showing Path Taken by Address Quadlet on HD
Control Logic
The MBus controller (MBC) and host interface controller (HIPC) are synchronous state machines that operate in the
two clock domains. They handle the protocols of their respective buses. They also handle arbitration protocols when
bus mastership is required. These controllers drive the latch enables, 3-state controls, and FIFO control signals of the
command, address, and datapath sections of the Ll bridge. They are responsible for coordinating data flow between the
two buses that operate at different data rates by using the master hold-off and slave-wait capabilities of their respective
buses. They also are responsible for manipulating arbitration protocols in response to locked-transaction requests.
Details of the implementation of these bus controllers is outside the scope of this application report. An example of an
MBus-initiated word-read transaction resulting in an HIP single read is shown in Figure 7.
The L1 bridge is a slave to MBus and a master on the host interface. It responds to an MBus address as a selected slave
and then arbitrates for HIP mastership.
Likewise, an example of an MBus-initiated word-write transaction resulting in an HIP single write is shown in Figure 8.
In this case, the MBus write is acknowledged before the HIP write is complete. If another write occurs to the L1 bridge
before the HIP transaction is complete, an ~Bus relinquish and retry operation must be perfonned to back off the MBus
master until the HIP transaction is finished.
3-203
I
I
IOn8
l250n8
I
I
MCLK
MAS
MAD
(83-0)
----~~~------------------------------------~~~---------
\.J
MRDY
Miffi
MEiiR
Selected
HBR
HBG
HBGACK
_ _ _ _J~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
-----------\~~----~I
________
\~
J/~----------------------
\~--------------------~I
HCLK
HA (31-0)
HD(31-0)
HAS
MS(1-0)
HDS
HIP
TR_W
TSIZ(1-0)
DW84
TBST
DSACK1
DSACKO
i'STRi5V
Figure 7. MBus-Word Read to HIF Single-Read Transaction
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I
1250 ns
I
MCLK
\J
\J
MAD
(83-0)
~
~
MRDY
\J
MAS
\.J
MRTY
MERR
Selected
HBR·
HBG
HBGACK
1\
I
\
I
\
I
\
HCLK
HA (31-0)
(
(
HD(31-0)
HAS
MS(1-0)
\
TSIZ(1-0)
(
DW84
I
TBST
I
BSTRDY
I
I
\
TR_W
DSACKO
X
01
\
HIP
)
dO
I
\
X
HDS
DSACK1
)
Addr
I
00
\
\
\
)
\
\
I
I
I
FigureS. MBus-Word Write to HIF Single-Write Transaction
3-205
Summary
Methods of connecting the SPARe MBus to the TIFB+ chipset's host interface are explored. Levell MBus transactions
are mapped to HIF transaction by the bridge logic. The HIF transactions are then mapped to FB+ I/O transaction by
the chipset. Direct- and paged-memory mapping are described. Techniques used to implement a 64-bit-only datapath
and a datapath that has a dynamically configurable 32-bit MBus/32-bit HIF or 64-bit MBus/64-bit HIF also are
described. Finally, the state-machine controller's task is summarized and example transactions directed by the
controllers are shown.
3-206
1K x 9 x 2 Asynchronous FIFOs
SN74ACT2235 and SN74ACT2236
First-In, First-Out Technology
. Kam Kittrell
Advanced System Logic - Semiconductor Group
SCAA010A
~TEXAS
INSTRUMENTS
3-207
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the Information being relied on is current.
TI warrants performance of Its semiconductor products and related software to the specifications
applicable at the time of sale In accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage C'Crltlcal Applications'1.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procadural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or othl\!r
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or l;Iervices might be or are used.
Copyright © 1995, Texas Instruments Incorporated
3-208
Contents
Title
Page
Introduction ............................................................................ 3-211
FIFO Control ........................................................................... 3-212
High-Frequency Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-212
Programmable Flags ................. ,................................................... 3-213
Output Drive ........................................................................... 3-214
Conclusion ............................................................................. 3-215
List ofmustrations
Figure
1
Title
SN74ACT2235 Block Diagram
Page
3-211
2
Controlling the SN74ACT2235 Using a Clock, Write Enable, and Read Enable per System ....... 3-212
3
Read Operation When Cycle Time Is Less Than Access Time ............................... 3-213
4
AF/AEAFlag-ProgrammingLogicforFIFOA ........................................... 3-213
5
Programming AF/AEB Flag ofFIFOB From PortA ...................................... 3-214
6
SN74ACT2235 YOLP Measurement. .................................................. 3-215
3-209
3-210
Introduction
Texas Instruments (11) designed the SN74ACf2235 to meet a variety of synchronous or asynchronous bidirectional
applications. Two lK x 9 first-in, first-out (FIFO) memories are arranged in parallel to buffer data in opposite directions.
Data ports also may exchange real-time data. Three-state control (GAB, GBA) and real-time/stored data select (SAB,
SBA) match the popular '652 transceiver logic. Produced in 11's EPICTM CMOS process, the inputs accept TTI.-voltage
levels. An option to the SN74ACT2235 is the SN74ACT2236, which has '646 transceiver control (DIR, G). The
functional block diagram for the SN7 4ACT2235 is shown in Figure 1.
0(.7
;-
I
UNCKA
-
-
'
RSTA
SBA,- -
LDCKA, -
GBA
AO-AS
-
-
~
~
=c
Read
Pointer
FULLA
EMPTYA
AF/AEA
HFA
Flag
Logic
I
I
I
Location 1
I
1024x9RAM
Write
Pointer
Location 1024
G1
EN2
I
2V
I ~
'-.-
~
2:1 MUX
I
G1 I--EN2 I--2V
I
~
-
SAB
GAB
BO-BS
2:1 MUX
Write
Pointer
h
-
UNCKB
Read
POinter
~~
-
LDCKB
Location 1024
1024x9RAM
Location 1
HFB
FULLB
EMPTYB
AF/AEB
I
I
I
Flag
Logic
I
I
-
(')Figure 1. SN74ACT2235 Block Diagram
EPIC is a trademark of Texas Instruments Incorporated.
3-211
FIFO. Control
The SN74ACT2235 consists of two FIFO memories, FIFOA and FIFOB. Both FIFOs can be accessed from either port
A or port B. Four control signal lines (GAB, GBA, SAB, and SBA) control the eight possible data flow paths through
the device (these datapaths are illustrated in the device data sheet). Each FIFO has a load clock (LDCK) that writes data
into memory and an unload clock (UNCK) that reads the data in the same order it was written. Both clocks are
positive-edge-triggered and may operate asynchronously to one another. The first word loaded into an empty FIFO
propagates directly to the outputs and the EMPTY flag switches high. EMPTY represents the valid state of data on the
outputs (data is valid when EMPTY is high and invalid when EMPTY is low). EMPTY may be used to enable an UNCK
pulse when it is synchronized with the bus that reads the data. FULL can qualify a LDCK pulse in the same way.
Figure 2 is an example of an SN74ACf2235 interfacing two asynchronous systems. Each system provides a read enable,
write enable, and free-running clock. Synchronization of a flag to the system clock is needed to use it as device-clock
control. Although the flag's high-to-low transition is synchronous to the clock it enables, the low-to-high transition is
asynchronous. The output of the latch qualifying this transition has the possibility of going metastable when bistable
(setup and hold) conditions are not met. An output is metastable ifit lingers between the specified VOH and VOL levels.
Two-stage synchronization of the flags reduces the probability of a metastable-induced failure.
r------------.---r-- CLK2
Sye
SYL--r--~----------~
CLKl
SN74ACT2235
)-------+------i>LDCKA LDCKBLDCKA
LDCKB11-_-_-_t1~+
______...r"1:::;:::;__=~
,_
UNCKB
UNCKA ....
·--,~~;;;::==t----<~;::1GBA
H
SAB
OAF
18-Blt
Data
....'
GAB
t-;-::-~t===F;=~4
SBAI-
FULLA
DBF
FULLB
AO-A8
B~8
~--~~~~ EM~~~~~--~
NOTE: Two devices are used for 18-bit width expansion.
Figure 2. Controlling the SN74ACT2235 USing a Clock, Write Enable, and Read Enable per System
High-Frequency Applications
A unique feature of the SN74ACT2235 is that the UNCK cycle time may be less than the device access time. The
SN74ACT2235-20 has a maximum LDCK and UNCK frequency of 50 MHz (20-ns cycle time) and a 25-ns maximum
access time (lpd UNCKA or UNCKB to B bus or A bus). In a series of FIFO reads, the next access may be initiated before
the present one is complete. The largest concern associated with this technique is the length of time data is assured as
valid. Minimum access time from the rising edge of UNCK also may be viewed as minimum data hold time. Timing
for this relationship is shown in Figure 3. Valid data time from the SN74ACT2235 over the commercial temperature
range and ± 10% Vee is given by equation 1:
tv 3-212
to + lpdmin -lpdmax
(1)
Data from an SN7 4ACT2235 operating at a 50-MHz clock frequency is valid for at least 7 ns. This allows a 4-ns setup
and I-ns hold time with a 2-ns tolerance to the next device in the datapath.
BO-BS
W1
,tpdmln-1
14
tpdmax
For SN74ACT2235-20: tpd min = 12 ns, Ipd max" 25 ns, tv" 7 ns
Figure 3. Read Operation When Cycle Time Is Less Than Access Time
Programmable Flags
Data is often transmitted in packets, where each packet is a specific number of bytes and must be delivered in an
unbroken stream. A FIFO transmitting packeted data needs a flag that shows the number of bytes stored. This keeps from
breaking the transmission of a packet due to an empty or full condition. The SN74ACT2235 has a programmable
almost-full/almost-empty (AF/AB) flag for this application. The AFIABA offset value (X) and the AFIABB offset value
(Y) are programmed separately. AFIABA is high when FIFOA contains X or fewer words or (1024 - X) or more words.
It is low when FIFOA contains between (X + 1) and (1023 -X) words. AF/ABB functions in the same manner with its
programmed value Y. The programmed or default value of 256 is chosen during a reset of each FIFO.
Flag-programming logic is illustrated in Fi~ ~g the AFIAB flag value for each FIFO is done with the
define-flag (OAF, DBF) inputs and resets (RSTA, RSTB). Define-flag inputs are negative-edge-triggered clocks that
store input data to a register. IfDAF or DBF is low when the rising edge of RSTA or RSTB occurs, the registered value
is used for the FIFO AF/AB flag. The flag uses the default value of 256 ifDAF orDBF is high during the rising edge
of RSTA or RSTB.
x>---t>
RSTA---...,
C
MUX
AO-AS
9
D
9 AF/AE Offset
Default Value
of 256
Value (X)
Figure 4. AF/AEA Flag-Programming Logic for FIFOA
3-213
Programming both flag offset values from either port is possible using real-time select. Figure 5 is a timing example of
programming APIAEB from port A. To program the APIAEB offset value (Y) from port A, the binary value for Y is
on AO-A8, SAB is low, and GAB is high. With this COnitguration, the port-A aata appears on the inputs ofFlFOB and
a falling edge of DBF stores the Y value.
GBA
------------------------------------------------------ 0
SAB
GAB
AO-A8
"'----
/
_ __ J
~~_________B_I_na_~_~_a_IU_e_Y________~·~
BO-B8 _______~_____B_I_na_~_~_a_IU_e_Y_____J~
Figure 5. Programming AF I AEB Flag of FIFOB From Port A
Output Drive
Charging and discharging the load of a bus with acceptable speed requires high device-output drive. The I/O ports of
the SN74ACT2235 provide 16-mA IOL and 8-mA IoH for this task.
Most memory devices have low drive capability and require buffers to interface a bus. They do not use larger transistors
that support high current because the rate of change of current with respect to time (di/dt) increases. When several
transistors switch simultaneously, the rate of change of current through ground and Vee lines multiplies. Voltage
transients on the power lines are given by equation 2:
V--L(dildt)
(2)
Where:
L - inductance of the bond wire and package lead
The SN7 4ACT2235 provides a two-fold solution to allow high-output current capability with low noise. One solution
is to reduce inductance of ground and Vee lines. The SN74ACT2235 has four GND and two Vee pins in parallel. The
resulting ground inductance is about 1/4 that of a single connection and divides Vee inductance in half.
3-214
Reducing di/dt per output transistor is another way to minimize voltage transients. TI's patented output-edge-control
(OECTM) design divides a large transistor into smaller segments that turn on in series and turn off simultaneously. OECTM
lowers di/dt, maintains a quick voltage transition through threshold, and avoids the high power consumed when
gradually turned off .1
The result of a VOlP test on the SN74ACT2235 is shown in Figure 6. VOlP is a measurement of ground-voltage noise
when all outputs of a bus are switched from high to low. Eight of nine outputs of a bus are switched, and the peak-voltage
rise of the steady-state low output is measured. Maximum ground-voltage rise is only 700 mV. The output fall time is
less than 3 ns with a 50-pF load.
5
r-
-
BO-B7
I .......
VCC=5V
TA=25OC
CL=5OpF
RL=5000
\
4
\
3
~
I
2
\
!!J
~
1
0.7
B8
o
-1
Ij' ,\
~
\J( ;'
o
5
10
15 20
25
1'\
-
;"
30
35 40
45
50
SwItching Time - n8
NOTE: Eight bus outputs switching, one remains low
Figure 6. SN74ACT2235 VOlP Measurement
Conclusion
The SN74ACT2235 and SN74ACT2236 provide several advantages for high-speed asynchronous bus interface. Simple
control logic offers great design flexibility. Programmable flags may be used for data flow optimization. High-output
drive for bus leading is balanced with noise reduction through package and circuit design.
1 Advanced CMOS Logic Designer's Handbook, pages
3-1 through 3-12.
OEC is a trademark of Texas Instruments Incorporated.
3-215
3-216
64-Byte FIFOs
SN~ALS2232AandSN~ALS2233A
First-In, First-Out Technology
Kam Kittrell
Advanced System Logic - Semiconductor Group
~1ExAs
INS1RUMENTS
SCAA023A
3-217
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to Its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale In accordance with TI's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device Is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applicatlons'?
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such epplications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
Infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either exprass or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
3-218
Contents
Title
Page
Introduction ............................................................................ 3-221
Clocks .................................................................................. 3-221
Flags .................................................................................. 3-222
Noise Control ........................................................................... 3-222
Applications ............................................................................
Using the FULL and EMPTY Flags ........................................................
Width Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus Conversion .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-224
3-224
3-224
3-225
List of mustrations
Figure
1
2
3
4
5
6
7
Title
Page
FIFO Read Control With READ/OE Logic .............................................
'ALS2232A and 'ALS2233A UNCK Control ............................................
Noise From a GND Pad to a 0-V Plane .................................................
'ALS2232A and 'ALS2233A Clock Input Circuit ........................................
Clock Generation With Two-Stage Synchronization of FULL and EMPTY ....................
Width Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bus-Folding Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3-221
3-222
3-223
3-223
3-224
3-224
3-225
3-219
3-220
Introduction
First-in, first-out (FIFO) memories are irreplaceable bus logic when interfacing two asynchronous systems. The Texas
Instruments SN74ALS2232A 64 x 18 and SN74ALS2233A 64 x 9 FIFOs are ideal solutions for many high-speed
buffering needs. These bipolar devices, produced in IMPACT-X technology, come in a 28-pin PLCC and a 24-pin DIP
for the 'ALS2232A and 28-pin PLCC and DIP for the 'ALS2233A.
Data is stored in a dual-port SRAM that supports transfer rates up to 40 MHz and maximum access times of 27 ns. Reads
are accomplished independent of writes with separate internal addressing.
Clocks
The read enables of many FIFOs also control the active/high~impedance state of the data outputs. FIFOs using this logic
must have a read-enable pulse long enough to include an access and hold time before it disables the outputs, which makes
high-frequency clock design difficult (see Figures 1 and 2).
READ/OE
Data Out
I
I '------' I
~ta~
FIFO Data Qual
_______+i__
tau~
ta
tsu
th
a
I
J~~-----.~~th
access time maximum
setup time minimum
hold time minimum
Figure 1. FIFO Read Control With READ/OE Logic
3-221
UNCK
OE
Data Out
(QO-Q7,Qa)
FIFO Data Qual
twl
12 ns
tw2
13n8
_______...Ix\,,______
x
W_O_rd_X
_ _ _ _ _..J
_ _----..J1
WordX+ 1
\_----
Figure 2. 'ALS2232A and 'ALS2233A UNCK Control
Texas Instruments has allowed clock generation to be simple for its FIFOs. Load-clock (LOCK) and unload-clock
(UNCK) inputs are edge triggered, which makes the device more suited for use as a buffer in a data-transmission path.
Fewer constraints are placed on a design with edge-triggered clocks since duty cycles are permitted to vary greatly (see
Figure 2). A separate output-enable (OE) input is provided for applications requiring 3-state buses.
The LOCK and UNCK independently control all data transfers into and out of memory and can be synchronous or
asynchronous. The first word loaded into an empty FIFO propagates directly to the data outputs. Any UNCK pulses that
occur during an empty condition are ignored, while any LOCK pulses that occur during a full condition are ignored.
Flags
The'ALS2232A has two flags to indicate boundary conditions of the memory: EMPTY and FULL. In addition to these,
the 'ALS2233A has the aImost-full/aImost-empty (AF/AE) and half-full (HF) flags. AF/AE is high when memory
contains less than nine words or more than 55 words. To distinguish between an almost-full and an almost-empty state,
HF is high when memory contains more than 31 words. The extra flags are provided for applications wherein full and
empty conditions should be avoided.
Noise Control
Ground bounce is a result of current surges produced by output switching. Bond wire, lead, and board inductance cause
.intemal ground levels to fluctuate from the current surge (rise above, then dip below 0 V). Extreme ground noise that
causes input levels to cross the transition threshold may be detected as clock pulses by high-speed devices. Worst-case
conditions for ground bounce are high Vee and outputs switching simultaneously from high to low.
The'ALS2232A and 'ALS2233A have package-centered Vee and GND pins to combat ground bounce. The shortened
bond wire and lead distance reduce package inductance from conventional comer-pin configurations.
Figure 3 shows a large voltage transient that might be measured on the ground pad of any device referenced to a 0-V
plane. An input at a steady high or steady low level is likely to cross the transition threshold as a result.
3-222
1.5
>
0.5
I
S
c
"0
ID
0
'Q
C
e"
-4.5
CJ
"
-
1\
\
V
\
-1
-1.5
Time -10 na/Dlv
Figure 3. Noise From a GND Pad to a O-V Plane
Figure 4 is the equivalent circuit of the clock inputs for the 'ALS2232A and 'ALS2233A. This modified RS flip-flop
is more likely to pass a very quick high pulse (0 to 5 ns) caused by noise when it is in the steady low state than it is to
pass a very quick low pulse when in the steady high state. The clock input one-shot structure is immune to a very quick
(0 to 5 ns) low pulse when in the steady high state. For improved noise protection. LDCK and UNCK signals may be
generated as inactive high with a low pulse generated for clocking.
UNCKor
LDCK
CLKPulse
Figure 4. 'ALS2232A and 'ALS2233A Clock Input Circuit
3-223
AppliCations
Using the FULL and EMPTY Flags
The FULL and EMPTY flags are provided to indicate that the FIFO is at one of its boundaries. An example of how to
qualify these flags as enables for the device clocks is shown in Figure 5. Without the flip-flop qualification, a flag can
cause the asynchronous generation of a clock. The two-stage synchronization alternative shown reduces the chances of
a metastable output from one-stage synchronization.
SYS1 Clock - - - - - - . . - - - - ,
,--------<.-----SYS2 Clock
SN74ALS2232A
or
SN74ALS2233A
Write Enable - - - - - ,
~---Resd
Enable
LOCK UNCK
o
o
0
~
00-07,08
QO-Q7,Q8
Figure 5. Clock Generation With lWo-Stage Synchronization of FULL and EMPTY
Width Expansion
Several'ALS2232A devices can be used in width expansion to handle datapaths with several bytes. The ' ALS2232A
can likewise be expanded and also pass parity for each byte. No special control logic is needed to implement this
application (see Figure 6).
SN74ALS2232A
or
SN74ALS2233A
LOCK
2 Bytes
Data
In
-
1 Byte
,
FULL
UNCK
EMPTY
-
1 Byte
,
SN74ALS2232A
or
SN74ALS2233A
LOCK
.-0=
FULL
UNCK
EMPTY
1 Byte
1 Byte
Figure 6. Width Expansion
3-224
D-
2 Bytes
Bus Conversion
Systems frequently require that data be converted from l-byte buses to multiple-byte buses operating asynchronously.
Figure 7 shows an IS-bit bus folded into a 9-bit bus using the I ALS2233A. The control logic can be implemented with
a TIBPAL20R4.
SYSCLK
,~--------------
EMPTYA _ _ _..£.../.,-""2",2,,,2.,,7
'......_----
EMPTYB _ _ _..//",,,,%,,,%,,,,%
.../',,,,1
UNCKA
''---_/
,'----.,,/
' .... __J/
UNCKB
' ......_...J/
OEA _ _ _ _ _ _ _......,-'~...._ _---J~'-_ _ _ _ _ _ _ __ _
OEB ____________________--'~'--___J~...._ _ _ _ __
SN74ALS2232A
SYS CLK
or
-+-----------------4.......
SN74ALS2233A
.--------------+-------r-------------i>UNCK
.------~f-----------___I
LDCK~----.--
OE
.-------1 EMPTY
SN74ALS2232A
or
SN74ALS2233A
L---------------------------------------+-~--t>UNCK
LDCK~--+_~
.---------------+--1---1 OE
L-+_--1 EMPTY
1 Byte -
...~~-I
Figure 7. Bus-Folding Logic
3-225
Table 1. Terminal Functions
FUNCTION
Control inputs
TERMINAL NAME
DEFINITION
LOCK
Load clock; rising-edge clock. Writes data into the FIFO; updates the flags.
UNCK
Unload clock; rislng-edge clock. Reads data out of FIFO; updates the flags.
OE
Output enable. Controls the actlvelhlgh-Impedance state of the data outputs.
A high level on OE selects the active state; low selects high impedance.
RESET
Reset. Low level resets the read and write pointers to the first location and sets
the flag status to empty. The FIFO must be reset after power up.
EMPTY
Empty flag. tpLH transitions are controlled by LOCK. tpHL transitions are
controlled by UNCK or RESET. FIFO read pointers are unaffected by UNCK
when EMPTY is low.
FULL
Full flag. tpHL transitions are controlled by LOCK. tpLH trensltions are
controlled by UNCK or RESEi. FIFO memory and write pointers are
unaffected by LOCK when FULL is low.
.
AF/AE
Aimost-fuil/almost-empty flag: high level when FIFO is eight locations from a
full or empty condition (FIFO contains less than nine words or more than
55 words)
HF
Half-full flag. tPLH transitions are controlled by LOCK. tpHL transitions are
controlled by UNCK or RESET. HF Is at a high level when the FIFO contains
more than 31 words.
Status-flag outputs
Data
3-,-226
00-07 (SN74ALS2232A)
00-08 (SN74ALS2233A)
Data Inputs: data latched by LOCK Into marnory
QO-Q7 (SN74ALS2232A)
QO-OO (SN74ALS2233A)
Data outputs: data read from FIFO
4-1
"i
...
oo
::s
en
_.
Q.
CD
...o
;_.
::s
en
4-2
Introduction
Page
Key Power-Dissipation Equations for ACT FIFOs . . . . . . . . . . . . . . . . . . • . . • . . • . . . . . . . . . . . . .. 4-5
Key Power-Dissipation Equations for ABT FIFOs ....................................... 4-6
Introduction
This section of the FIFO Designer's Handbook shows typical power characteristics in the form of active supply current
versus frequency plots for each of Texas Instruments (TI's) advanced FIFOs. In some cases, plots of idle supply current
(IeeI) versus frequency are also included. In addition to the current versus frequency data, sample calculations of power
dissipation are included in this section for a representative set of FIFOs. The application report entitled Power
Dissipation Calculations for TI FIFO Products serves as a guideline for the example calculations. Equations for
dynamic, quiescent, and total power dissipation for both ACT and ABT FIFOs are given, along with the idle lee versus
frequency plots required for the sample calculations in this section. These and other key equations that are used in the
calculation of power dissipation are repeated below and numbered for convenience.
Key Power-Dissipation Equations for ACT FIFOs
Quiescent
Pq - vee x [leeI + (NTIL x Alec x DCYIH)]
(1)
Where:
- fclock x pF(clock) - supply current when FIFO is idle
- clock switching frequency
fclock
clock switching power factor (slope of lee versus fclock curve)
pF(clock)
= number of inputs driven by TIL levels
NTIL
- increase in supply current for each input at a TIL high level (see data sheet)
Alec
- percent of TIL signals at a high level of 3.4 Y
DCVIH
leeI
Dynamic Power
Pd - Vee x [leef + (NTIL x Alee x DCvrn)] + l:(CL x Vee2 x fo)
(2)
Where:
Vee
leef
NTIL
Alee
DCVIH
CL
fo
= supply voltage
-, supply current when FIFO is transferring data
- number of inputs driven by TIL levels
- increase in supply current for each input at a TIL high level (see data sheet)
= percent of TIL signals at a high level of 3.4 Y
- load capacitance
- output switching frequency - [112 (since maximum data rate is 112 clock frequency)
x (fraction of outputs switching at a given time) x (frequency of the slowest
of the port clocks)]
Tota/Power
Pt - Pd(DCd) + Pq(1-DCd)
Where:
Pd
Pq
DCd
dynamic power dissipation
quiescent power dissipation
- duty cycle
=
(3)
Key Power-Dissipation Equations for ABT FIFOs
Quiescent Power
Pq - Vcc x [DCENX (NHx ICCHINT+ NLx IcCrfNT) + (l-DCEN) x Iccz + Iccd
(4)
Where:
vCC
IcCI
fclock
pF(clock)
DCEN
IcCH
ICCL
ICCZ
NL
NH
NT
-
supply voltage
fclock x pF(clock) - supply current when FIFO is idle
clock switching frequency
clock switching power factor (slope of ICC versus fclock curve)
percent duty cycle enabled
power supply current when outputs are in the high state (see data sheet)
power supply current when outputs are in the low state (see data sheet)
= power supply current when outputs are in the high-impedance state (see data sheet)
number of outputs in low state
- number of outputs in high state
- total number of outputs
Dynamic Power
Pq - VCC XIcCf+ I: [VCC xCLx(VOH- Vou xfo]
(5)
Where:
vCC
ICCf
fo
VOH
VOL
CL
supply voltage
supply current when FIFO is transferring data, active current
output switching frequency - [112 (since maximum data rate is 112 clock frequency)
x (fraction of outputs switching at a given time) x
(frequency of the slowest of the port clocks)]
- output voltage in high state
output voltage in low state
= load capacitance
=
=
=
Total Power
Pt = Pd(DCd) + Pq(1-DC~
(6)
Where:
Pd
Pq
DCd
- dynamic power dissipation
quiescent power dissipation
duty cycle
In all of the following power calculation examples, the FIFO inputs are being driven by a 1TL device. In the case where
the inputs are driven by a CMOS device, the MCC term in the power-dissipation equation equals zero and can be ignored.
In each calculation, the number of inputs (or outputs) equal to the width of the FIFO are assumed to be switching in order
to provide a worst-case solution for the conditions being as~umed.
Figure 1 contains the results of the sample power-dissipation calculations. The plotis divided up into results for the ACf
FIFOs and results for the ABT FIFOs. Within each of these technologies, the conditions for each sample calculation have
been chosen to provide (as much as possible) an apples-to-apples comparison (see individual calculations in this
section). As previously noted, the number of bits switching at a given time is assumed to be equal to the width of the
FIFO under consideration. In addition to the results of the calculations, the maximum power-dissipation capability of
the packages associated with these devices at 70°C with no air flow is also plotted. In every case, the dissipation
capability of the package significantly exceeds the power being dissipated by the device, even under the rather severe
conditions stated above. The specific packages and their associated dissipation capabilities are listed in Figure 1.
2000
..
c
0
!
ACT
~I
ABT
-
1500
r-
ICL
E
•
:::I
I/)
c
~
r1000
iICL
j
c
-
-
0
•
500
I
ICL
0_
...L
JI Ju
ACT3641
(36 Bits)
ACT7803
(18 Bits)
D
-
ACT7807
(9 Bits)
.1
i.
ACT2229
(1 Bit)
PACKAGE A
...L
-
ABT3613
(36 Bits)
I...L
Device Dlsslpatlonl
Consumption
PackageA
Dissipation Capability
PackageS
Dissipation Capability
'--
ABT7819
(18 Bits)
PACKAGE B
NOMENCLATURE
DISSIPATION
CAPABILITY
(mW)t
NOMENCLATURE
DISSIPATION
CAPABILITY
(mW)t
ACT3641
120-pin TOFP (PCB)
1606
132-pin POFP (PO)
1610
ACT7803
56-pln SSOP (OL)
851
ACT7807
64-pin TOFP (PAG)
1121
44-pin PLCC (FN)
1244
ACT2229
24-pin SOIC (OW)
909
28-pin SOIC (OW)
978
ABT3613
12o-pin TOFP (PCB)
1606
132-pin POFP (PO)
1610
ABT7819
8O-pin TOFP (PN)
911
8o-pin POFP (PH)
954
DEVICE
t The conditions of 70·C and no air flow are assumed.
Figure 1. Comparison of Device and Package Power-Dissipation/Consumption capabilities
4-7
4-8
Application Report
4-10
Power-Dissipation Calculations
for TI FIFO Products
Navid Madani
Advanced System Logic - Semiconductor Group
~TEXAS
INSTRUMENTS
SCAA013A
4-11
· IMPORTANT NOTICE
Texas Instruments (TIl reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises Its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthetime of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications',.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or Implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright + Pq (1- DCd)
- 1047.1625 mW x 1/3 + 202.436 mW x 213 - 484.0115 mW
Therefore, total power is approximately:
IT -
484mW
The SN74ACT3632 is available in 120-pin TQFP and 132-pin PQFP packages (refer to Appendix B for the maximum
power curve calculated for reliability purposes). At maximum ambient temperature (70°C) and no air flow for 132-pin
PQFP and 120-pin TQFP packages, the maximum power that the packages can dissipate to free air is 1610 mW and
1606 mW, respectively. The SN74ACT3632, in this example, meets the reliability requirement since 484 mW is much
less than 1610 mWor 1606 mW.
4-19
Quiescent or Nonswltchlng Power Dissipation In ABT FIFO Devices (BICMOS FIFO products)
Unlike CMOS devices that have a single value for lec, BiCMOS devices have varying static current levels depending
on the state of the output (ICCL, IeCR, ICcz). Quiescent power includes the power consumed while outputs are active,
the power consumed when outputs are disabled, and the power consumed by the switching clocks. The design of the
BiCMOS inputs is such that when a 1TL high level is applied at the input, it does not increase the current; therefore,
the alec term (NTIL x alec x DCd> is excluded from the following equation (from Texas Instruments ABTAdvanced
BieMOS Technology Data Book, 1993, literature # SCBDOO2A) in calculating power for ABT FIFO products.
Pq - VCC x [DCEN x (NR x ICCRINT + NL x IeCLINT) + (1 - DCEN)IeCZ + lecd
Where:
VCC x [DCEN x (NR x IecwNT + NL x IeCIJNT)] - power consumed while outputs are active
VCC x (1 - DCEN)IeCZ - power consumed when outputs are disabled
VccXICCI - power consumed by switching clocks
VCC
- supply voltage
IeCI
- fclock x pF - supply current when FIFO is idle (the clocks are running
but no data is written to or read from the FIFO) (not in the data sheet)
fclock - clock switching frequency
pF
- clock switching power factor, the slope oflec versus fclock curve (see data sheet)
% duty cycle enabled
DCEN
power-supply current when outputs are in high state (see data sheet)
IeCR
power-supply current when outputs are in low state (see data sheet)
ICCL
power-supply current when outputs are in high-impedance state (see data sheet)
lecz
number of outputs in low state
NL
number of outputs in high state
NR
total number of outputs
NT
Dynamic or SWitching Power Dissipation In ABT FIFO Devices (BICMOS FIFO products)
For most applications, dynamic power accounts for most of the total power consumption of a BiCMOS device. Dynamic
power consumption includes the device switching power consumed without the load, as well as the power consumed
due to the capacitive load.
Pd - VCC x IeCf+ r[VCC x CL x (VOR- VOL) x fol
Where:
VCC x ICCf - device switching power without the load
r[Vcc x CL x (VOR - VOL) x fo 1- power consumed due to the output switching frequency
and the load capacitance
VCC
- supply voltage
IeCf
- supply current when FIFO is transferring data, active current
(see active ICC versus frequency plot in data sheet)
fo
- output switching frequency
VOR
output voltage in high state
VOL
output voltage in low state
CL
load capacitance '
4-20
Example 2
This example shows how to calculate the power dissipation for an SN7 4ABT3614 bidirectional FIFO used in a system
under the following conditions:
Data input l~ (AO-A35) and the control signals (CLKA, CLKB, CSA, CSB, WiRA, W/RB. ENA,
ENB, MBA, BE, RST, SIZO, SIZl, ODDIEVEN, SWO, SWl, PGA, PGB) are driven by a CMOS device.
Only 213 of the inputs (or outputs) are switching at a given time.
The output of the FIFO is fed to a memory device.
The port-B clock rate is 33.3 MHz and the port-A clock rate is 40 MHz.
The SN74ABT3614 is only used 60% of the time by the system.
The load capacitance of each output is about 50 pF, and the supply voltage is set to 5 V.
During the FIFO active period, the bus is enabled 75% of the time.
When the bus is enabled, the output is in the high state 80% of the time.
The SN74ABT3614 is used equally in both directions.
Figures 5 through 7 and included information are needed to calculate power dissipation:
400
,
,!.
, -'
'
fdata = 1/2 fclock
-TA=25°C
CL=OpF
350
VCC=5.5V /
V
300
VCC=5Z
0(
E
I
8
I
I
~
250
/
200
/ :/
V
/ ./ . /
:Y V~
~ ~ /VCC=4.5V
150
100
,~
50
o
o
10
~ '?
V
20
30
40
50
60
70
60
fclock - Clock Frequency - MHz
Figure 5. SN74ABT3614 Active Icc With eLKA and eLKB Switching,
Simultaneous Read/Write and eLKB as Data Output
4-21
40
c
I
_ ~ Vee=4.5V
36
. . . Vee=5V
-'- ...... Vee=5.5V
30
TA = 250
~r-
E
I
8
25
i
20
~
15
.....-'
10
---' ~
~
~
-----
------
~
~~~
~~~
r~
I
----
~
~
L
Slope = 0.25
5r-----~------_+------_r------4_------+_------~----~
o~----~------~------~------~------~------~----~
o
10
20
30
40
50
60
70
f - Frequency - MHz
Figure 6. SN74ABT3614 Idle ICC With ClKA Switching,
Other Inputs at 0 or VCC - 0.2 V and Outputs Disconnected
40r-----~-------.-------.------.-------.-------.------,
1
I
=
35
~ vec 4.5 V --+_------~----~f-----__+----::::;;oo.....,."-------__i
. . . Vee=5V
30
...... Vee = 5.5 V
TA =250
--+-------,-+_----___l6......,e:~__+--__=_....~----__i
25r-------+------_+----~~"-----~~~----+_~~~~----~
8
i
I
~
15.
10r-----~------_+---'----_r------4_------+_------~----~
5r-----~------_+------_r------4_------+_------+_----___l
O~----~------~------~------~------~------~----~
o
10
20
30
40
50
f - Frequency - MHz
Figure 7. SN74ABT3614 Idle ICC With elKB Switching,
Other Inputs at 0 or VCC - 0.2 V and Outputs Disconnected
4-22
60
70
The following parametric values are needed to calculate power dissipation:
Vcc
VOH VOL
DCd
1 - DCd fclockA fclockB pF(A) pF(B) DCEN ICC!
ICCf
ICCH =
ICCL Iccz NL/NT NWNT CL
fo
-
supply voltage - 5 V
VCC - 1.3 V
0.3V
% time FIFO is switching - 0.6
% time FIFO is not switching - 0.4
clock switching frequency of port A - 40 MHz
clock switching frequency of port B - 33.3 MHz
clock-A switching power factor, the slope of Icc versus fclock curve (see data sheet) = 0.25
clock-B switching power factor, the slope of Icc versus fclock curve (see data sheet) - 0.28
% duty cycle enabled - 0.75
[fclockA x pF(Al + [fclockB x pF(B) - (40 x 0.25) + (33.3 x 0.28) - 19.32 mA
idle supply current when FIFO is transferring data - 136.26 mA
active supply current when outputs are in high state (see data sheet) = 30 mA
power supply current when outputs are in low state (see data sheet) = 130 mA
power supply current when outputs are in high-impedance state (see data sheet) - 30 mA
ratio of number of outputs in low state to total number of outputs - 0.2
ratio of number of outputs in high state to total number of outputs - 0.8
load capacitance - 50 pF
112 (since maximum data rate is 112 clock frequency) x 2/3
(since 2/3 of the outputs are switching at a given time) x 33.3 MHz
(slowest of the the two clock frequencies, fclockA or fclockB) - 11.1 MHz
Solution
PT - PT (from A to B) + PT (from B to A)
- Pq (from A to B) + Pq (from B to A) + Pd (from A to B) + Pd (from B to A)
- Pq +Pd
Where Pq and Pd include power from A to B and from B to A directions.
Quiescent Power
Pq - Vee x [DCENx (NHx IcewNT+NLx IceIlNT) + (I-DCEN)Icez+ Icc!l
- 5 V x [0.75 x (0.8 x 30 mA + 0.2 x 130 mA) + (1 - 0.75) 30 mA + 19.32 mAl
- 5 V x [37.5 mA + 7.5 mA + 19.32 mAl- 321.6 mW
Dynamic Power
Pd - Vec x Ieef+ 'L[Vcc xCLx (VOH- VOL) xfol
- 5 V x 136.25 mA + 'L[5 x 50 pF x (5 V - 1.3 - 0.3 V) x (11.1 MHz)l
- 681.25 mW + (36 x 9.44 mW) - 681.25 mW + 339.66 mW = 1020.91 mW
Total Power
PT - Pd (DCd) +Pq (l-DCd)
- 1020.91 mW x 0.6 + 321.6 x 0.4 -741.19 mW
Therefore, total power is approximately:
PT - 741.19 mW
The SN74ABT3614 is available in 120-pin TQFP and 132-pin PQFP packages (refer to Appendix B for the maximum
power curve calculated for reliability purposes). At maximum ambient temperature (70°C) and no air flow for the
132-pin PQFP and 120-pin TQFP packages, the maximum power that the package can dissipate to free air is 1610 mW
and 1606 mW, respectively. The SN74ABT3614, in this example, meets the reliability requirement since 741.19 mW
is much less than 1610 mW or 1606 mW.
4-23
Summary
Power-dissipation calculations are essential to meet the design requirements related to the chip temperature and the
system power. In this application report, a simple method of calculating power is provided to assist the design engineer
with power-dissipation calculations for 11 CMOS and BiCMOS FIFO products. Total power includes quiescent power
and dynamic power. For most applications using CMOS and BiCMOS FIFOs, dynamic power accounts for most of the
power requirement. Examples of power-dissipation calculations are provided to show the practical use of this
application report. In each example, the reliability of the chip was tested against the absolute maximum power
dissipation in free air. For example, the total calculated power consumption for the SN74ACT3632 and SN74ABT3614
examples resulted in 484 mW and 741 mW, respectively. These values are much less than the maximum power
dissipation of the 120-pin TQFP (1606 mW) or 132-pinPQFP (1610 mW) packages in still air. Icc versus frequency
curves are provided in Appendix A. These graphs assist the design engineer in the search for the FIFO device with the
minimum power consumption. After total power is calculated for a system, the design engineer can ensure that this value
does not exceed the maximum power capability of the package type. The table of maximum power versus ambient
temperature for different package options are included in Appendix B.
Acknowledgements
The author would like to express her appreciation to Kam Kittrell for his editorial comments and AI Sawyer for his
assistance in providing the Icc versus frequency curves in Appendix A.
4-24
Appendix A
Graphs of ICC Versus Frequency
The following information is provided to assist the designer with the power-consumption calculations. Graphs of Icc
versus frequency are shown for the SN74ACT7803, SN74ACT7811, SN74ACT3641, SN74ACT7807, and
SN74ABT7819. While the FIFOs were idle, data was taken on five units on an automatic test machine (lIP 82(00). Five
readings were taken for each frequency and the average was used to plot the graphs. The tests were done by setting VIL
and VIH as shown below:
VIL - OV
VIH - Vee- 0.2V
For each of the FIFOs, two graphs are provided for idle Icc. One graph shows the Icc versus frequency when WRTCLK
is running, whereas the other graph shows the Icc versus frequency when RDCLK. is running. The slope of the 5-V
supply voltage curve is calculated for both graphs and the largest of the two slopes is used as the power factor for power
calculations.
The slopes of the lceI versus frequency graphs in the tests performed were 0.09 (SN74ACT7807),
0.12 (SN74ACT7803, SN74ACT7811), 0.2 (SN74ACT3641), and 0.28 (SN74ABT3614); therefore, if the slope of the
lceI versus frequency plot is not readily available, it is appropriate to estimate the slope as 0.2.
6
....... VCC=4.6V
..... Vce=6V
-IP- Vee 6.5 V
TA=2S0
6
1
I
=
4
0
E
.!!
3!
3
I
B
2
o~----~------~----~------~----~------~----~----~
o
5
10
15
20
25
30
35
40
f - Frequency - MHz
Figure A-1. SN74ACT7811 Idle Icc With RDCLK or WRTCLK Switching
4-25
9
..... VCC=4.6V
..... VCC=5V
...... VCC=5.5V
TA =25·
8
7
1
8
8
5
i
4
B
3
I
I
2
f - Frequency - MHz
Figure A-2. SN74ACT7803 Idle Icc With RDCLK or WRTCLK Switching
18
..... VCC=4.5V
..... VCC=5V
...... VCC=5.5V
TA = 25·
18
14
1
12
8
10
I
i
8
B
8
I
4
2
O~~
o
____L -______L -______L -______L -______L -______L -____
ro
m
~
~
~
f - Frequency - MHz
Figure A-3. SN74ACT3641 Idle Icc With CLKA Switching
4-26
~
~
~
14.----,----,----,----,----,----,-----.
...... Vee=4.5V
~ Vee = 15 V
~ Vee=5.5V
TA = 25°
12
1
10
--+----+----+----+-----bJfl""""'----:I.
I
8
i
I
~
8~---~---~---~--~~~~~F-~~-~--~
8~---~---~--~~~~~~~--~---~--~
4~---~--_2~~~~r----~---~---~--~
2~--~~~~--~------r_----_+-------r------+_--~~
10
20
30
40
eo
50
70
f - Frequency - MHz
Figure A-4. SN74ACT3641 Idle Icc With ClKB Switching
2eo.----,----,----,----,----,----,---~
...... Vcc =4.5 V
~
Vee=5V
Vee = 5.5 V --+----+----~--_i----:::;JfI""""_+--:::;o,,-;;_i
TA=25°
200
~
1I
B
1eor------r----~r_----;_----~~--~~~~-r----__i
I
100r----+----+--~~~~~~+----+----+---__i
I
=
Slope 2.94
g
50r----~~~JfI""""T----+----+----+--~-+---__i
o~----~------~------~----~------~------~----~
o
10
20
30
40
50
eo
70
f - Frequency - MHz
Figure A-5. SN74ACT3641 Active Icc With ClKA and ClKB Switching,
Simultaneous ReadlWrite and ClKB as Data Output
4-27
6
...... VCC=4.5V
~ VCC=5V
-lAP- Vee = 5.5 V
TA = 26°
6
~
4
I
8
J!
3!
3
I
~
2
O~----~------~------~------~------~------L-----~
o
10
20
30
40
50
60
70
f - Frequency - MHz
Figure A-B. SN74ACT7807IdleJce With WRTCLK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected
7
...... VCC=4.5V
~ Vee=5V
-lAP- Vee = 6.5 V
TA = 25°
6
~
5
8
4
I
.!!
3!
I
3
~
2
O~----~~----~------~------~------~------~----~
o
ro
~
30
40
50
f - Frequency - MHz
Figure A-7. SN74ACT7807 Idle lee With RDCLK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnectea
4-28
60
N
200
I
180 -
_
./
Vee=4.5V
V".....-I
~ Vee=5V
180
1
I
~
- -A-
Vee = 5.5 V
i
l5
80
~
~~
/"~ ~" f-~~
....d ~
~
80
I
40
20
o
....04
./.~ ~
120
100
2
./".J~
140 f- TA=25°
o
10
20
30
40
Slope = 2.40
50
70
80
f - Frequency - MHz
Figure A-8. SN74ACT7807 Active Icc With Simultaneous ReadIWrlte
200
I
I
I
I
Vee = 4.15 V
180 I- _
........... r
~ Vee=5V
180
1
140
t- -A- Vee = 5.5 V
t- TA = 260
./V
k-"""'"
./
I
~
Ic
120
100
I
80
B
80
..-I~ ~
~
...-! ~ ..... ~
f' ......
~
40
....
~
r---
,. I"""'"
~~
........ ......... r'"' ,...
~
~
.........
........
V
V ........~ ~
~
t-::: ~
..... Ir---""
~
~
~
,-
20
o
10
15
20
25
30
315
40
45
50
55
80
65
70
75
80
65
90
95
100
f - Frequency - MHz
Figure A-9. SN74ABT7819 Active Icc Versus Frequency
4-29
Appendix B
Maximum Power Dissipation for Different Package Types
For reliability purposes, maximum power is calculated for each package option using the following equation:
Chip temperature - Power x 9lA + TA
Where:
Chip temperature - lS00C (absolute maximum chip temperature)
9lA
- thermal characteristics of a package (known)
TA
- ambient temperature (known)
Table 1 lists maximum power dissipation by package type for ambient temperature from 25°C to 90°C.
Table B-1. Maximum Power Dissipation (mW) for Packaged FIFOs
AMBIENT
TEMPERATURE
(OC)
25
30
35
40
45
50
65
60
1,911
1,811
65
70
75
60
65
90
PQl32PQFP
2,515 2,414 2,314 2,213 2,113 2,012
PCBl20TQFP
2,510 2,410 2,309 2,209 2,108 2,008 1,908 1,601' 1,707 1,505 1,505 1,406 1,305 1,205
1,424 1,367 1,310 1,253 1,196 1,139 1,082 1,025 968
797
854
654
740
683
PN80TQFP
PM64TQFP
1,351
PH80 PQFP
1,490 1,430 1,371
D156SS0P
1,330 1,277 1,223 1,170 1,117 1,064 1,011
1,528 1,467 1,406 1,345 1,284 1,222 1,161
DW28S0IC
DW24S0lC
4-30
1,297 1,243 1,189 1,135 1,081
1,311
1,251
1,027
973
1,710 1,509 1,509 1,408 1,308 1,207
919
1,192 1,132 1,073 1,013
904
1,100 1,039
1,420 1,364 1,307 1,250 1,193 1,136 1,060 1,023 966
957
811
811
757
703
894
894
834
775
649
715
798
798
745
691
917
852
917
656
795
638
733
852
795
739
682
Single-Bit FIFOs
Page
Sample Power-Dissipation Calculations for SN74ACT2229 .............................
Power Characteristics ....................... ,.....................................
SN74ACT2226 and SN74ACT2228 Single FIFO Supply Current Versus Clock Frequency ..
SN74ACT2227 and SN74ACT2229 Single FIFO Supply Current Versus Clock Frequency ..
4-33
4-34
4-34
4-34
. 4-31
Sample Power-Dissipation Calculations for SN74ACT2229
This example shows power-dissipation calculations for the SN74ACT2229 FIFO used in a system under the conditions
below. On board the SN74ACT2229 are two separate and independent FIFOs. The calculation below is for only one
FIFO: FIFOI is assumed active and FIF02 is assumed idle.
Assumed Conditions
•
•
•
•
•
•
Data input line (10) is driven by a TTL device.
Control signals (1 WRTCLK, IRDCLK, IRESET, 1WRTEN, lOE, IRDEN) are driven by a CMOS device.
The input (or output) is switching at a given time.
The RDCLK clock rate is 33.3 MHz and the WRTCLK clock rate is 40 MHz.
The SN74ACT2229 is used about 113 of the time by the system.
The load capacitance on each output is about 30 pF, and the supply voltage is 5 V.
The following parametric values are needed to calculate power dissipation:
Vcc
DCd
fWRTCLK
fRDCLK
pF
ICCI
NTTL
ICCp
AlCC
DCVIH
CL
fo
-
5 V (assumed condition)
113 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.2 mAlMHz (worst-case approximation)
(fWRTCLK + fRDCLK) x pF - 14.7 mA
(calculated, see equation 2 in the introduction to Section 4)
1 (assumed condition)
20 mA @ 33.3 MHz (from active ICC versus frequency plot)
1 mA (see data sheet)
1 (assumed condition)
30 pF (assumed condition)
(0.5) x (1) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 4 in the introduction to Section 4)
Solution
Quiescent Power
PT -
Vcc x [lccI + (NTTL x Alec x DCvm)]
5Vx [14.7 mA + (1 x 1 mAx 1)]
78.3mW
(1)
Dynamic Power
Pq -
Vcc x [ICCf+ (NTTLxaICC x DCvm)] + l;(CLXVCC2 xfo )
5Vx [20 mA + (1 x 1 mAx 1)] +[30pFx(5V)2x 16.7 MHz]
117.5mW
(2)
Total Power
PT -
(Pd x DCd) + [Pq x (I-DCd)]
(117.5mWx1l3)+(78.3mWx2/3)
91.4mW
(3)
Therefore, the total power is approximately 91 mW.
4-33
Power Characteristics
The SN74ACI'2229 is available in the 24-pin SOIC and 28-pin SOIC packages. The maximum power-dissipation
capabilities of these packages forvarying ambient temperatures and airflows can be found in Section 5 of this handbook.
At an ambient temperature of 70°C with no air flow, the maximum power that each of these packages can dissipate to
free air is 909 mW and 978 mW, respectively. The total power dissipation of the SN7 4ACT2229 with one input (or
output) switching falls well within the thermal budget of either of these packages.
18
fl = 1/2 fclock
TA=75°C
CL=OpF
16
1I
14
'E
12
~
:::I
U
10
fa.
8
:::I
UJ
I
~
8
4
2
0
5
0
10
15
20
25
'clock - Clock Frequency - MHz
Figure 1. SN74ACT2226 and SN74ACT2228 Single FIFO Supply Current Versus Clock Frequency
40
35
1
30
~
26
I
:::I
u
~
20
a.
a.
:::I
UJ
15
I
e:
J~
10
fl = 1/2 fclock
--+----+--+ TA = 75°C
5
CL=OpF
0
0
10
20
30
40
50
60
fclock - Clock Frequency - MHz
Figure 2. SN74ACT2227 and SN74ACT2229 Single FIFO Supply Current Versus Clock Frequency
4-34
36-Bit Clocked FIFOs
Page
Sample Power-Dissipation Calculations for SN74ABT3613 •............................
Power Characteristics .............................................................
SN74ABT3611 Supply Current Versus Clock Frequency ......•..................•.....
SN74ABT3612 Supply Current Versus Clock Frequency ...............................
SN74ABT3613 Supply Current Versus Clock Frequency ...............................
SN74ABT3614 Supply Current Versus Clock Frequency ....•........•.................
SN74ABT3614 Idle Current With ClKA Switching. Other Inputs at'O or Vee - 0.2 V
and Outputs Disconnected ............•.•............•...........................
SN74ABT3614 Idle Current With ClKB Switching. Other Inputs at 0 or Vee - 0.2 V
and Outputs Disconnected . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . ..
Sample Power-Dissipation Calculations for SN74ACT3641 ..........................•..
Power Characteristics .....•.............••............•...........................
SN74ACT3632 Supply Current Versus Clock Frequency ............•....•.............
SN74ACT3638 Supply Current Versus Clock Frequency .........................•.....
SN74ACT3631 and SN74ACT3641 Supply Current Versus Clock Frequency .............
SN74ACT3641 Idle Current With ClKA Switching .....................................
SN74ACT3641 Idle Current With CLKB SWitching .....................................
SN74ACT3641 Active Current With ClKA and ClKB Switching.
Simultaneous ReacllWrite and ClKB as Data Output ....•......•........•...........
4-37
4-38
4-38
4-38
4-39
4-39
4-40
4-40
4-41
4-42
4-42
4-42
4-43
4-43
4-44
4-44
4-35
4-36
Sample Power-Dissipation Calculations for SN74ABT3613
This example shows the power-dissipation calculations for the SN74ABT3613 unidirectional FIFO used in a system
under the following conditions.
Assumed Conditions
•
•
•
•
•
•
•
Data input (AO-~S) ~2.con.,.!!:>l signals (CLKA, CLKB, CSA, CSB, ENA, ENB, FSO, FS1, MBA, RST,
ODDIEVEN, W/RA, WIRB, BE, SIZO, SIZ1, SWO, SW1, PGA, PGB) are driven by a CMOS device.
36 inputs (or 36 outputs) are switching at a given time.
The port-B clock rate is 33.3 MHz and the port-A clock rate is 40 MHz.
The SN74ABT3613 is used about 60% of the time by the system.
The load capacitance on each output is about SO pF and the supply voltage is 5 V.
During the FIFO active period, the bus is enabled 75% of the time.
When the bus is enabled, the output is in the high state 80% of the time.
The following parametric values are needed to calculate power dissipation:
-
VCC
VOH
VOL
DCd
fCLKA
fCLKB
pF
DCEN
Iccr
-
ICCF
IcCH
IcCL
Iccz
NUNT
NHINT
CL
fo
-
-
-
5 V (assumed condition)
VCC-1.3 V
0.3V
0.6 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.265 mAlMHz (assumption based on data for the SN74ABT3614)
0.75 (assumed condition)
(fCLKA + fCLKB) x pF - 19.4 rnA
(calculated, see equation 7 in the introduction to Section 4)
136 rnA@ 33.3 MHz (from active Icc versus frequency plot)
30 rnA (see data sheet)
130 rnA (see data sheet)
30 rnA (see data sheet)
0.2 (assumed condition)
0.8 (assumed condition)
50 pF (assumed condition)
(0.5) x (1) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 9 in the introduction to Section 4)
Solution
Quiescent Power
Pq
-
-
VCC x [DCEN x (NH x IcCHINT+ NLx IcCLINT) + (l-DCEN) x Iccz + Iccd
5 V x [0.75 rnA x (0.8 x 30 rnA + 0.2 x 130 rnA) + (0.25) x 30 rnA + 19.4 rnA]
322mW
(I)
Dynamic Power
Pq
-
-
VCCxIcCf+l:[VCCxCLx(VOHxVOL)xfo1
5 Vx 136 rnA + (36 x 5 V xSOpFx (5 V -1.3 V -0.3 V) x 16.7 MHz)
1191 mW
(2)
Total Power
For - (Pd x DCd) + [Pq x (l-DCd)]
-
(1191 mW) (0.6) + (322 mW) (0.4)
843.4mW
(3)
Therefore, the total power is approximately 843 mW.
4-37'
Power Characteristics
The SN74ABT3613 is available in the 120-pin TQFP and 132-pin PQFP packages. The maximum power-dissipation
capabilities of these packages for varying ambient temperatures and airflows can be found in Section 5 of this handbook.
At an ambient temperature of 70°C with no air flow, the maximum power that each of these packages can dissipate to
free air is 1606 mW and 1610 mW, respectively. The total power dissipation of the SN74ABT3613, under the rather
severe conditions of 36 inputs (or 36 outputs) switching simultaneously, falls well within the thermal budget of either
of these packages.
400
'd~ = 1~2 'clo Ik
I
I
VCC = 5.5 V /
350 ,TA=25°C
CL=OpF
11
300
i,.
250
(.)
>15.
a.
~
1
s:
J~
150
50
o
o
./
/
". /
1/~ /
~ ~ V VCC =4.5V
VCC=~Z
200
100
~
/
/
,~
10
k% ~
V
20
30
40
50
60
70
80
'clock - Clock Frequency - MHz
Figure 1. SN74ABT3611 Supply Current Versus Clock Frequency
400
1
'data = 112 'clock
350 r- TA = 25°C
CL=OpF
"'
E
1
250
fa.
200
(.)
:::0
1
s:
J~
150
100
50
o
o
~
/
V
/
/
/ )': V
~ ~ """""VCC = 4.5 V
VCC=5Z
~
en
/
/
300
,.~
_I,
VCC=5.5V /
,~
10
~~
V
20
30
40
50
60
70
80
'clock - Clock Frequency - MHz
Figure 2. SN74ABT3612 Supply Current Versus Clock Frequency
4-38
400
c(
E
I
C
300
~~
250
~
Do
200
0
II
,
_I.
VCC=5.5V
150
_0
100
50
o
o
~
l/ ~V . .
~ ~ VVCC = 4.5 V
~
I
L
L L
I'"
V
L .L L
VCC=~
II)
s:
0
I
'data = 1/2 'clock
350 f-TA=25°C
CL=OpF
,~
10
~~
V
20
30
40
50
60
70
60
'clock - Clock Frequency - MHz
Figure 3. SN74ABT3613 Supply Current Versus Clock Frequency
1I
~
G
b
8:
~
~
150 t--II--t-7F7""-P"-+--t--t--;
J~
100t--I1-~~~--r-+--t--t-~
50t-~~-t--+--r-+--t--t-~
O~~--~--~--~~~~--~~
o
10
20
30
40
50
60
70
60
'clock - Clock Frequency - MHz
Figure 4. SN74ABT3614 Supply Current Versus Clock Frequency
4-39
~
I
J
J
I
B
o~~~~--~--~--~--~--~
o
10
20
30
40
50
80
70
f - Frequency - MHz
Figure 5. SN74ABT3614 Idle Current With CLKA Switching,
Other Inputs at 0 or Vce - 0.2 V and Outputs Disconnected
~
I
J
J
I
B
5r-~r--;--~---+---+---r--~
O~~~~--~--~--~--~--~
OW"
~
40
80
80
~
f - Frequency - MHz
Figure 8. SN74ABT3614 Idle Current With CLKB Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected
4-40
Sample Power-Dissipation Calculations for SN74ACT3641
This example shows power-dissipation calculations for the SN74ACT3641 unidirectional FIFO used in a system under
the folIowing conditions.
Assumed Conditions
•
•
•
•
•
•
Data input (AO-A35) are driven~ TIL device.
_
_
Control signals (CLKA, CLKB, CSA, CSB, ENA, ENB, FSO, FSI, MBA, MBB, RPM, RTM, RST, WIRA,
WIRB) are driven by a CMOS device.
36 inputs (or 36 outputs) are switching at a given time.
The port-B clock rate is 33.3 MHz and the port-A clock rate is 40 MHz.
The SN74ACT3641 is used about 113 of the time by the system.
The load capacitance on each output is about 30 pF, and the supply voltage is 5 V.
The following parametric values are needed to calculate power dissipation:
VCC DCd =
fCLKA fCLKB pF(A) pF(B) DCEN ICCI NTIL
ICCf
Icc
CL
fo
=
-
5 V (assumed condition)
1/3 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.20 rnAlMHz (from idle Icc versus frequency plot, CLKA switching)
0.16 rnAlMHz (from idle ICC versus frequency plot, CLKB switching)
0.75 (assumed condition)
[fCLKA x pF(A)} + [fCLKB x pF(B)] - 13.3 rnA
(calculated, see equation 2 in the introduction to Section 4)
36 (assumed condition)
100 rnA@ 33.3 MHz (from active Icc versus frequency plot)
1 rnA (assumed condition)
30 pF (assumed condition)
(0.5) x (I) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 4 in the introduction to Section 4)
SolutIon
Quiescent Power
Pq
-
Vccx[IcCI+(Nrn...xAIccxDCVIH)]
5 V x [13.3 rnA + 36 x 1 rnA xl)]
246.5mW
(1)
Dynamic Power
Pd
-
Vcc x [IcCf+ (NTTL x AIcc x DCVIH)] + l:[CL x (VCc2 x fo)
5 Vx [100 rnA + (36 x 1 rnA xl)] + [36 x 30 pFx (5 V)2 x 16.7 MHz)
1130.9mW
-
(Pd x DCd) + [Pq x (I-DCd)]
(1130.9 mW x 113) + (246.5 mW x 213)
541.3mW
(2)
Total Power
PT
=
-
(3)
Therefore, the total power is approximately 541 mW.
4-41
Power Characteristics
The SN74ACT3641 is available in the 120-pin TQFP and 132-pin PQFP packages. The maximum power-dissipation
capabilities of these packages for varying ambient temperatures and air flows can be found in Section 5 of this handbook.
At an ambient temperature of 70°C with no air flow, the maximum power that each of these packages can dissipate to
free air is 1606 mW and 1610 mW, respectively. The total power dissipation of the SN74ACT3641, under the rather
severe conditions of 36 inputs (or 36 outputs) switching simultaneously, falls well within the thermal budget of either
of these packages.
300 , . - - - , - - - , - - - , - - - , - - , - - , - - - - - ,
1
~
fdata = 1/2 'clock
TA=75°C
CL 0 pF +---t---+--__+--t---:~
=
250
I
G
I
150~-+_-+_-+-_.~~~~__+-_t
I
~
100
50
O~-~-~-~-~-~-~-~
o
10
20
30
40
50
60
70
fclock - Clock Frequency - MHz
Figure 1. SN74ACT3632 Supply Current Versus Clock Frequency
250
1
fdata = 1/2 fclock
TA = 25°C
CL=OpF
200
I
i
:::I
U
150
b
a.
a.
ci
I
100
e:
u
_u
50
O~--~--~--~--~--~--~--~
o
10
20
30
40
50
60
70
fclock - Clock Frequency - MHz
Figure 2. SN74ACT3638 Supply Current Versus Clock Frequency
4-42
250 r----r----r----r----r----r----,..---,
'data =1/2 'clock
1
TA=25°C
CL=OpF
200
I
J 1501--t--t--t--hI'....,.h~+----f
1(/)
J
100 1--t--t-~~'2I't--+--+----f
I
501--~WI--t--t--t--+----f
O~--~-~--~-~-~--~~
w
o
~
~
~
50
50
N
'clock - Clock Frequency - MHz
Figure 3. SN74ACT3631 and SN74ACT3641 Supply Current Versus Clock Frequency
18
TA
18
!. 25°
~
12
./
8
/. ~
8
L.
4
o
/
/ /
~~ /
VCC=5V,
10
2
~
VCC=5.5V
14
./
o
"
10
~ V Vee = 4.5 V
V
~
20
~
1\
,
~
Slope = 0.20
40
50
50
70
,- Frequency - MHz
Figure 4. SN74ACT3641 Idle Current With CLKA Switching
4-43
14
12
1
10
I
8
i
6
I
:::I
()
iI
~
4
2
10
20
30
40
50
60
70
f - Frequency - MHz
Figure 5. SN74ACT3641 Idle Current With CLKB Switching
10
20
30
40
50
60
70
f - Frequency - MHz
Figure 6. SN74ACT3641 Active Current With CLKA and ClKB Switching,
Simultaneous ReadlWrlte and CLKB as Data Output
1S-Bit Clocked/Strobed FIFOs
Page
Sample Power-Dissipation Calculations for SN74ABT7819 .............................
Power Characteristics .............................................................
SN74ABT7819 Supply Current Versus Clock Frequency ....•....•.....................
SN74ABT7820 Supply Current Versus Clock Frequency ...............................
Sample Power-Dissipation Calculations for SN74ACT7803 .........••..................
Power Characteristics .....•........................•....•...........•.............
SN74ACT7804 Supply Current Versus Clock Frequency ....................•..........
SN74ACT7806 Supply Current Versus Clock Frequency ...............................
SN74ACT7814 Supply Current Versus Clock Frequency ...............................
SN74ACT7803 Supply Current Versus Clock Frequency ...............................
SN74ACT7803 Idle Current With RDCLK or WRTCLK Switching ...•...•....••..........
SN74ACT7805 Supply Current Versus Clock Frequency ................•.•............
SN74ACT7813 Supply Current Versus Clock Frequency .................•.............
4-47
4-48
4-48
4-48
4-49
4-50
4-50
4-50
4-51
4-51
4-52
4-52
4-53
4-45
4-46
Sample Power-Dissipation Calculations for SN74ABT7819
This example shows power-dissipation calculations for the SN7 4AB17S19 unidirectional FIFO used in a system under
the following conditions.
Assumed Conditions
•
•
•
•
•
•
•
Data input lines (AO-AI7) and control signals (CLKA, CLKB, CSA, CSB, RENA, RENB, WENA, WENB,
RSTA, RSTB, PENA, PENB, WiRA, W/RB) are driven by a CMOS device.
IS inputs (or IS outputs) are switching at a given time.
The port-B clock rate is 33.3 MHz and the port-A clock rate is 40 MHz.
The SN74AB 17S19 is used about 60% of the time by the system.
The load capacitance on each output is about 50 pF, and the supply voltage is 5 V.
During the FIFO active period, the bus is enabled 75% of the time.
When the bus is enabled, the output is in the high state SO% of the time.
The following parametric values are needed to calculate power dissipation:
VCC
VOH
VOL
Ded
fCLKA
fCLKB
pF
DCEN
ICCI
-
ICCf
IcCH
IcCL
ICCZ
NLINT
NHINT
CL
fo
-
=
5 V (assumed condition)
VCC-1.3 V
0.3V
0.6 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.2 mAlMHz (worst-case assumption)
0.75 (assumed condition)
(fCLKA + fCLKB) x pF - 14.7 rnA
(calculated, see equation 7 in the introduction to Section 4)
75 rnA @ 33.3 MHz (from active Icc versus frequency plot)
15 rnA (see data sheet)
95 rnA (see data sheet)
15 rnA (see data sheet)
0.2 (assumed condition)
O.S (assumed condition)
50 pF (assumed condition)
(0.5) x (1) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 9 in the introduction to Section 4)
Solution
Quiescent Power
Pq -
VCC x [DCEN x (NH x ICCHINT + NL x Iccr/NT) + (1- DCEN) x Iccz + IccIl
5 V x [0.75 x (O.S x 15 rnA + 0.2 x 95 rnA) + (0.25) x 15 rnA + 14.7 rnA]
20S.5mW
(1)
Dynamic Power
Pd
=
VCC x ICCf+ l;[Vcc xCLx (VOH- VOL) x fo]
5Vx [100 rnA + (36 x 1 rnA x 1)] + [36x30pFx(5 V)2x 16.7 MHz]
630.5mW
(2)
Total Power
PT -
(PdxDCd)+[Pqx(I-DCd)]
(630.5 mW) (0.6) + (20S.5 mW) (0.4)
461.7mW
(3)
Therefore, the total power is approximately 462 mW.
4-47
Power Characteristics
The SN74ABTI819 is available in the 80-pin TQFP and 80!pin PQFP packages. The maximum power-dissipation
capabilities of these packages forvarying ambient temperatures and airflows can be found in Section 5 of this handbook.
At an ambient temperature of 70°C with no air flow, the maximum power that each of these packages can dissipate to
free air is 911 mWand 954 mW, respectively. The total power dissipation of the SN74ABTI819, under the rather severe
conditions of 18 inputs (or 18 outputs) switching simultaneously, falls well within the thermal budget of either of these
packages.
160
I II
TA=76°C
CL=OpF
Vcc
=6.6 V. /V
/
V ,/V
140
1
120
i
d
100
8:
60
I
I
~
60
40
"/.
~ ~ ,/
i-"
V
,/
V ,/V , / ~
b
~
,/
VCC=6V -
/
10'
~ V
,/
VCC
=4.6 V
~ ~V
20
10 16 20 26 30 36 40 46 60 55 60 66 70
'clock - Clock Frequency - MHz
Figure 1. SN74ABT7819 Supply Current Versus Clock Frequency
160
140
1
120
::I
100
i
TA=76°C
CL=OpF
VCC=5V
b
Go
Go
~
60
I
~
60
40
~ ,/ , /
'" , /
~~
t -'_
L
V ~ ,/
"
,/
.~ V ,/i-" , / , /
~
V
V
,/ V
,,-
U
I
VCC=6.6V /
,/
~VCC=4.5V
20
10 15 20 25 30 36 40 46 60 55 60 66 70
'clock - Clock Frequency - MHz
Figure 2. SN74ABT7820 Supply Current Versus Clock Frequency
Sample Power-Dissipation Calculations for SN74ACT7803
This example shows power-dissipation calculations for the SN74AC17803 unidirectional FIFO used in a system under
the following conditions.
Assumed Conditions
• Data input lines (00-D17) are driven by a TIL device.
• Control signals (WRTCLK, RDCLK, RESET, WRTEN1, =WR=TE=N:=2, OE1, OE2, RDEN, PEN) are driven by
a CMOS device.
• 18 inputs (or 18 outputs) are switching at a given time.
• The RDCLK clock rate is 33.3 MHz and the WRTCLK clock rate is 40 MHz.
• The SN74ACT7803 is used about 113 of the time by the system.
• The load capacitance on each output is about 30 pF, and the supply voltage is 5 V.
The following parametric values are needed to calculate power dissipation:
VCC
DCd
fWRTCLK fRDCLK pF
DCEN
ICCI
NTIL
Iccf
AlCC
IcCL
DCvm
CL
fo
-
5 V (assumed condition)
113 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.12 mNMHz (from idle Icc versus frequency plot)
0.75 (assumed condition)
(fwRTcLK + fRDCLK) XpF - 8.8 rnA
(calculated, see equation 2 in the introduction to Section 4)
18 (assumed condition)
75 rnA @ 33.3 MHz (from active ICC versus frequency plot)
1 rnA (see data sheet)
95 rnA (see data sheet)
1 rnA (see data sheet)
30 pF (assumed condition)
(0.5) x (1) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 4 in the introduction to Section 4)
Solution
Qulescsnt Power
Pq -
VCCX[IcCI+NTILXAIccXDCVIH)]
5 Vx [0.75 x (8.8 rnA + (18 xl rnA x 1)]
134mW
(1)
Dynamic Power
Pd -
Vcc x [IcCf+ (NTIL x AIcc x DCVIH)] + :E(CLx Vc,..z xfo)
5 V x [75 rnA + (18 x 1 rnA x 1)] + [18 x 30pFx (5 V)2 x 16.7 MHz]
690.5mW
(2)
Tota/Power
PT -
(Pd xDCd) + [Pqx(I-DCd)]
(690.5 mW x 113) + (134 mW x 2/3)
319.5mW
(3)
Therefore, the total power is approximately 320 mW.
4-49
Power Characteristics
The SN74ACT7803 is available in the 56-pin SSOP package. The maximum power-dissipation capabilities of these
packages for varying ambient temperatures and air flows can be found in Section 5 of this handbook. At an ambient
temperature of 70°C with no air flow, the maximum power that the 56-pin SSOP package can dissipate to free air is
851 mW. The total power dissipation of the SN74ACT7803, under the rather severe conditions of 18 inputs (or 18
outputs) switching simultaneously, falls well within the thermal budget of either of this package.
200
180
1I
~
V
/ Y
120
80
I
./
VCC=5V,
100
s:
8
I
140
a.
a.
::I
II)
.-
VCC=5.5V
160
G
~
I
TA =75°C
CL=OpF
b
./
VCC=4.5V
~
,~W
20
0
// /
~~
40
/'
/ /
/
80
I'
o
20
10
30
40
50
60
70
'clock - Clock Frequency - MHz
Figure 1. SN74ACT7804 Supply Current Versus Clock Frequency
200
180
1I
~
I
TA=75°C
CL=OpF
VCC=5.5V
160
VCC=5V"
140
120
::I
0
~
a.
,jl
I
s:
8
/
/ Y
/ /
L
/
100
80
b
60
~~
40
l/
./
VCC=4.5V
~
p
20
0
V/ ~
I'
",
o
10
20
30
40
50
60
70
'clock - Clock Frequency - MHz
Figure 2. SN74ACT7806 Supply Current Versus Clock Frequency
4-50
200
180
I
TA = 75°C
CL=OpF
VCC=5.5V
180
VCC=5V"
""E
140
~
120
I
G
100
::s
80
I
60
~
D.
/
V/ /
8
l/
/ Y ./
/ '/
VCC=4.5V
~~
40
, P'
20
0
V
V
~~
II)
S
~
o
10
20
30
40
50
80
70
'clock - Clock Frequency - MHz
Figure 3. SN74ACT7814 Supply Current Versus Clock Frequency
200
180
I
TA = 75°C
CL=OpF
""E
~::s
I
()
itil
I
S
8
/
/ Y
VCC=5V~
140
120
V/ /
80
l/
./
L "£
/
100
VCC=4.5V
~ Y'"
~~
80
40
,p
20
0
V
Vcc = 5.5 V /
180
o
10
20
30
40
50
60
70
'clock - Clock Frequency - MHz
Figure 4. SN74ACT7803 Supply Current Versus Clock Frequency
4-51
1
I
J
I
I
B
10
20
30
40
50
80
70
f - Frequency - MHz
Figure 5. SN74ACT78031dle Current WlthRDCLK or WRTCLK Switching
200
180
I
TA = 75·0
OL=OpF
Vcc = 5.5 V ~
~
180
1
I
I
3
i~
I
~
V ,/
/ rY . /
/ / /
/,/ /" Vcc = 4.5 V
VOO=5V~
140
120
100
80
h Y'
80
~~
~W
40
,
20
o
o
10
20
30
40
50
60
70
fclock - Clock Frequency - MHz
Figure 8. SN74ACT7806 Supply Current Versus Clock Frequency
200
180
I
TA=75OC
CL=OpF
VCC=5.5V
I
180
~
I
i
B
iIi:
I
~
VCC=5V~
140
100
h
80
~~
~~
40
20
o
V
l/
/ IY /
/ / /
/ / / VCC=4.5V
120
80
V
~
~
r"
o
10
20
30
40
50
50
70
fclock - Clock Frequency - MHz
Figure 7. SN74ACT7813 Supply Current Versus Clock Frequency
4-53
4-54
9-8;t Clocked/Strobed FIFOs
Page
Sample Power-Dissipation Calculations for SN74ACT7807 ..........................•..
Power Characteristics .............................................................
SN74ACT7807 Supply Current Versus Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SN74ACT7807 Idle Current With WRTCLK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected ..........................
SN74ACT78071dle Current With RDCLK Switching,
Other Inputs at 0 or Vee - 0.2 V and Outputs Disconnected ..........................
SN74ACT7808 Supply Current Versus Frequency ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
4-57
4-58
4-58
4-58
4-59
4-59
4-56
Sample Power-DIssipation CalculatIons for SN74ACT7807
This example shows power-dissipation calculations for the SN74ACT7807 unidirectional FIFO used in a system under
the following conditions.
Assumed Conditions
•
•
•
•
•
•
Data input lines (DO-D8) are driven by a TIL device.
Control signals (WRTCLK, RDCLK, RESET, WRTEN1, WRTEN2, DE, RDEN1, RDEN2, PEN) are driven
by a CMOS device.
Nine inputs (or nine outputs) are switching at a given time.
The RDCLK clock rate is 33.3 MHz and the WRTCLK clock rate is 40 MHz.
The SN74ACT7807 is used about 113 of the time by the system.
The load capacitance on each output is about 30 pF, and the supply voltage is 5 V.
The following parametric values are needed to calculate power dissipation:
vCC
DCd
fWRTCLK
fRDCLK
pF(WRTCLK)
pF(RDCLK)
DCEN
IcC!
-
NTIL
Icer
-
~Icc
IccL
DCVIH
CL
fo
=
-
5 V (assumed condition)
113 (assumed condition)
40 MHz (assumed condition)
33.3 MHz (assumed condition)
0.07 rnA/MHz (from idle Icc versus frequency plot)
0.09 mAlMHz (from idle Icc versus frequency plot)
0.75 (assumed condition)
(fWRTCLK x pF(WRTCLK» + (fRocLK x pF(RDCLK» - 5.8 rnA
(calculated, see equation 2 in the introduction to Section 4)
9 (assumed condition)
65 rnA @ 33.3 MHz (from active Icc versus frequency plot)
1 rnA (assumed, from data sheet)
95 rnA (see data sheet)
1 rnA (assumed condition)
30 pF (assumed condition)
(0.5) x (1) x (33.3 MHz) - 16.7 MHz
(calculated, see equation 4 in the introduction to Section 4)
Solution
Quiescent Power
Pq
-
Vcc x [Icc! + NTIL x ~Icc x DCVIH))
5 V x [5.8 rnA + (9 x 1 rnA xl)]
74mW
(1)
Dynamic Power
Pd
-
VCC X [Icer+ (NTILx ~Icc x DCVIH)] +l:(CL x VCc2 x fo)
5 V x [65 rnA + (9 x 1 rnA xl)] + [9 x 30 pF x (5 V)2 x 16.7 MHz]
482.7mW
(2)
Tota/Power
PT -
(Pd x DCd) + [Pq x (l-Ded)]
(482.7mWx1l3)+(74mWx2l3)
21O.2mW
.
(3)
Therefore, the total power is approximately 210 mW.
4-57
Power Characteristics
The SN74ACT7807 is available in the 64-pin TQFP and 44-pin PLCC packages. The maximum power-dissipation
capabilities of these packages for varying ambient temperatures and airflows can be found in Section 5 of this handbook.
At an ambient temperature of70°C with no air flow, the maximum power that each of these packages can dissipate to
free air is 1121 mWand 1244 mW, respectively. The total power dissipation of the SN74ACT7807, under the rather
severe conditions of nine inputs (or nine outputs) switching simultaneously, falls well within the thermal budget of either
of these packages.
o~~--~--~--~~--~--~~
o
10
20
30
40
50
60
70
80
'clock - Clock Frequency - MHz
Figure 1. SN74ACT7807 Supply Current Versus Frequency
O~--~--~--~--~---L--~--~
o
10
20
30
40
50
60
70
, - FrequencY - MHz
Figure 2. SN74ACT78071dle Current With WRTCLK Switching.
Other Inputs at 0 or Vee - O.2V and Outputs Disconnected
4-58
~
I
J
i
I
~
2r-~--~~~---+---+---+--~
o~~--~--~--~--~--~--~
~
~
~
~
~
~
o
ro
, - Frequency - MHz
Figure 3. SN74ACT7807 Idle Current With RDCLK SWitching,
Other Inputs at 0 or VCC - 0.2 V and Outputs Disconnected
1~
1~
TA=75OC
CL=OpF
I
, .'.
/
VCC=5V""\
~
120
I
100
I
3>0
~
~
~
1
/
/
,1~
V
~
I
S
8
~
~
o
~
1/
VCC =5.5 V
V
VV
~/
/ ' VCC=4.5V
~ """
o ro
~
~
~
~
~
~
~
'clock - Clock Frequency - MHz
Figure 4. SN74ACT7808 Supply Current Versus Frequency
4-59
4-60
5-1
3:
CD
n
:::sO)
_.
:1
n
0)
-
0)
:1
Co
-t
:::s-
...CD3
0)
0'
...3
...o_.
:1
0)
:1
5-2
Comparison Summary of Advanced Packaging
Derating Curves (in Still Air)
Introduction
This section of the FIFO Designer's Handbook contains mechanical and thermal information and data relating to the
packages used for Texas Instruments (TI) FIFOs. A series of application reports and papers that address such issues as
package thermal resistance, package moisture sensitivity, fme-pitch packaging manufacturability, and measurement
procedures of thermal resistance are included in this section. One of these papers, More Power in Less Space: A
Thermal-Enhancement Solution for Thin Packages, was published in TI Technical Journal, Volume 11, Number 4
(July-August 1994). The paper discusses the design and development of the thermally enhanced thin quad flat package
(TQFP TEP) that is capable of dissipating 2.4 watts of power in a 256-mm2 board area. The thermally enhanced,
fme-pitch package is the result of the efforts of a cross-functional team at TI that included resources from package
design, chip design, package assembly, reliability, and device testing.
Following the application reports is the mechanical and thermal data for each FIFO package. The mechanical data
consists of outline drawings of each package annotated with critical dimensions. Accompanying each package drawing
is the associated thermal data. This data consists of measured thermal resistances and derating curves of maximum power
dissipation versus ambient temperature for varying air flows.
Figure I is a summary plot of the still-air derating curves for the advanced FIFO packaging options. The 120-pin TQFP
TEP and the 132-pin PQFP packages are nearly equivalently capable of dissipating more power for a given ambient
temperature than any of the other packages considered.
3000
--- 24-Pln SOIC (OW)
-6- 28-Pln SOIC (OW)
....... 44-Pln PLCC (FN)
-0- 56-Pln SSOP (OL)
64-Pln TQFP (PAG)
....... 64-Pln TQFP (PM)
___ 68-Pln PLCC (FN)
+
2500
-b- SO-Pin PQFP (PH)
-0- SO-Pin TQFP (PN)
-+-
10o-Pln TQFP (PZ)
___ 12o-Pln TQFP (PCB)
-D- 132-Pln PQFP (PQ)
2000
1500
1000
500
25
30
35
40
45
50
55
60
65
70
75
80
85
90
TA - Ambient Temperature _·C
Figure 1. Comparison Summary of Advanced Packaging Derating Curves (In stili air)
5-5
Application Reports/Papers
Page
FIFO Surface-Mount Package Information .•........................................... 5-9
FIFO Memories: Fine-Pitch Surface-Mount Manufacturability ........................... 5-19
Package Thermal Considerations ................................................... 5-29
K-Factor Test-Board Design Impact on Thermal-Impedance Measurements .............. 5-41
More Power in Less Space: A Thermal-Enhancement Solution for Thin Packages ......... 5-55
FIFO Surface-Mount Packages for PCMCIA Applications. . . . . . . . . . . . . • . . . . . . . . . . . . . . . .. 5-69
5-7
FIFO Surface-Mount
Package Information
First-In, First-Out Technology
Tom Jackson and Mary Helmick
Advanced System Logic - Sem/conductor Group
:lllExAs
INSIRUMENTS
SSPA001A
5-9
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by govemment
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications'~.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
5-10
Contents
Title
Page
Introduction ............................................................................. 5-13
Thermal Resistance ....................................................................... 5-13
Package Moisture Sensitivity ............................................................... 5-14
Shipping Metbods/Quantities/Dry Pack ..................................................... 5-15
Package Dimensions and Area Comparison ................................................... 5-15
Test Sockets .............................................................................. 5-17
5-11
5-12
Introduction
Texas Instruments provides seven types of plastic surface-mount packages for CMOS FIFO memory devices. These
packages and the data bus width that each package can provide are listed in Table 1.
Table 1. Plastic Surface-Mount FIFO Packages
PACKAGE
44-pinPLCC
NO. OF DATA BITS
64-pinTQFP
9
9
56-pinSSOP
• 18
68-pinPLCC
18
8().pin TQFP
18
8~inQFP
12O-pin TQFP
SSOP.
PLCC TQFP •
QFP ..
18
32 or 36
shrink small-outhne package
plastic leaded chip carrier
thin quad flat package
quad flat package
This application report discusses several topics concerning the FIFO packages listed in Table 1:
• The thermal resistance. RaJA, and the chip junction temperature of the device
• The need for dry packing to maintain safe moisture levels inside the package
• The three methods used by Texas Instruments for shipping FIFOs to customers
• The package dimensions. including two-dimensional drawings that show areas, heights, and lead pitches
• The area comparison of surface-mount packages used for commercial FIFO memories
• The test sockets available for surface-mount FIFO packages
Thermal Resistance
Thermal resistance is dermed as the ability of a package to dissipate heat generated by an electronic device and is
characterized by RaJA. RaJA is the thermal resistance from the integrated circuit chip junction to the free air (ambient).
Units for this parameter are in degrees Celsius per watt. Table 2 lists RaJA for SSOP, PLCC, TQFP, and QFP packages
under five different air-flow environments: 0, 100,200,250, and 500 linear feet/minute. The chip junction temperature
(TJ) can be determined using equation 1.
(1)
Where:
Tl
- chip junction temperature (0C)
RaJA - thermal resistance, junction to free-air (oC/watt)
l>T - total power dissipation of the device (watts)
TA
- free-air (ambient) temperature in the particular environment in which the device is operating (0C)
5-13
Table 2. Thermal Resistance, RaJA, for FIFO Packages
ReJA(OCIW)
PACKAGE
LEAD
FRAME
OLFPM
100LFPM
200LFPM
260LFPM
500LFPM
56-plnSSOP
Copper
94.2
62.2
N/A
70
57.8
44-pin PLCC
Copper
65
NlA
NlA
N/A
NlA
68-pinPLCC
Copper
47.2
43.4
NlA
32.7
27.8
64-pinTQFP
Copper
92.5
87.8
N/A
72.9
57.8
8O-plnTQFP
Copper
87.8
79.1
N/A
67.3
54.2
12Q-pln TQFPt
Copper
49.6
44.3
N/A
38.3
28.6
8Q-pinQFP
Alloy 42
80
67
61
NlA
N/A
t Heat slug molded inside the package
N/A
=not available
The RaJA generally increases with decreasing package size; however, this is not true with the 120-pin SQFP package.
A heat slug molded inside the package absorbs a large amount of heat dissipated by the device. As a result, this package
provides a relatively low RaJA'
Package Moisture Sensitivity
When a plastic surface-mount package is exposed to temperatures typical of furnace reflow, infrared (IR) soldering, or
wave soldering (215°C or higher), the moisture absorbed by the package turns to steam and expands rapidly. The stress
caused by this expanding moisture results ininternal and external cracking of the package that leads to reliability failures.
Possible damage includes the delamination of the plastic from the chip surface and lead frame, damaged bonds, cratering
beneath the bonds, and external package cracks.
To prevent potential damage, packages that are susceptible to the effects of moisture expansion undergo a process called
dry pack. This dry pack process helps to reduce moisture levels inside the package. The process consists of a 24-hour
bake at 125°C followed by sealing of the packages in moisture-barrier bags with desiccant to prevent reabsorption of
moisture during the shipping and storage processes. These moisture-barrier bags allow a shelf storage of 12 months from
the date of seal. Once the moisture-barrier bag is opened, the devices in it must be handled by one of the following four
methods, listed in order of preference:
The devices may be mounted within 48 hours in an atmospheric environment of less than 60% relative
humidity and less than 30°C.
The devices may be stored outside the moisture-barrier bag in a dry-atmospheric environment of less than
20% relative humidity until future use.
The devices may be resealed in the moisture-barrier bag adding new fresh desiccant to the bag. When the bag
is opened again, the devices should be used within the 48-hour time limit or resealed again with fresh
desiccant.
The devices may be resealed in the moisture-barrier bag using the original desiccant. This method does not
allow the floor life of the devices to be extended. The cumulative {:xposure time before reflow must not exceed
a total of 48 hours.
All plastic surface-mount FIFO devices are tested for moisture sensitivity in accordance with Texas Instruments
JESD A112 procedure.
5-14
Shipping Methods/Quantities/Dry Pack
Three methods are used by Texas Instruments for shipping FIFOs to customers. These methods are tubes, tape/reel, and
trays. The quantities for each of the shipping methods are listed in Table 3. The shipping quantity is dermed as the
maximum number of packages that can be packed in a single shipping unit (e.g., the maximum number of 56-pin SSOP
packages that can be packed in a tube is 20). Whether or not the packages require dry pack before shipping is noted in
the dry-pack column.
Table 3. Shipping Methods and Quantities
PACKAGE
SHIPPING METHOD
TUBEt
TAPE/REELt
TRAYSt
DRY PACK
56-pinSSOP
20
500
N/A
No
44-pln PLCC
27
N/A
68-pin PLCC
No
Yes
64-pinTQFP
18119*
NlA
500
250
80-plnTQFP
NlA
N/A
160
N/A
NlA
119
Yes
120-pin TQFP
N/A
NlA
90
Yes
8O-pinTQFP
N/A
N/A
50
Yes
Yes
t Texas Instruments reserves the right to change any of the shipping quantities at any
time without notice.
* Eighteen packages can be packed In a single tube when pin is used as a tap or
nineteen packages can be packed in a tube when plug is used as a tap.
NlA =not applicable
Package Dimensions and Area Comparison
Figure I contains two-dimensional drawings of the seven available surface-mount FIFO packages. For detailed
mechanical drawings of these packages, please refer to the mechanical drawing section of the 1994 High-Performance
FIFO Memories Data Book, literature #SCADOO3B.
5-15
14-- 16.0 ---.j
J+::: 14.0 -~
I
1
ISO-Pin
14.0
TQfP
I
0 (PN)
JE..
Area: 144.00 mm2
Area: 196.00 mm2
Height: 1.50 mm
Height: 1.50 mm (PM)
Height: 1.0 mm (PAQ)
Lead Pitch: 0.5 mm
12Cl-pln
TQFP
11(0
;c
Lead Pitch: 0.5 mm
0
(PCB)
Area: 256.00 mm2
Height: 1.6 mm
Lead Pitch: 0.4 mm
"'14- - 26.2 - -....
~
I+--
I
--.j
17.6
44-pln
1
PLCC
(FN)
Area: 309.60 mm2
1
1
68-pln
PLCC
(FN)
.:
Area: 636.04 mm2
Height: 4.37 mm
Height: 4.37 mm
Lead Pitch: 1.27 mm
Lead Pitch: 1.27 mm
I+-- 23.6 - -..
I
Area: 189.50 mm2
Height: 2.59 mm
Lead Pitch: 0.635 mm
1
Area: 415.40 mm2
"ii8lghti2.96 mni
Lead Pitch: 0.8 mm
Figure 1. Package Dimensions
,.
"
5-16
'-
"
Figure 2 shows the area comparison of surface-mount packages for FIFOs from Texas Instruments and other FIFO
vendors.
144 mm2
84-Pln TQFP
{
32-PlnPLcc • • • 11Jmm
l
44-Pln PLCC • • • • • J.8mm2
. .PlnSSOP
18-BIt-Wlde {
Data
_1
1 .5
8O-Pln TQFP • • • 1J
m~
mm~
8O-Pln QFP • • • • • • 41 4 mm2
88-Pln PLCC • • • • • • • • •
32-or
38-Blt-Wlde {
Data
120-PlnTQFP • • • • • • • • •
132-Pln QFp ..
o
100 200 300 400 500Il00 700 800
IIiIo 1000
A.... (mm2)
Figure 2. Surface-Mount Package Area Comparison
Test SOckets
For prototype development of a system, it is often an advantage to have sockets for surface·mo'\lllt products. Test sockets
a....ailable for use with Texas Instruments FIFO packages are listed in Table 4. Only one manufacturer is listed for each
socket type, although other vendors may offer comparable sockets.
Table 4. Test Sockets for FIFO Packages
PACKAGE
56-pinSSOP
44-pln PLOO
66-pln PLeO
64-pinTQFP
8O-pInTQFP
12D-pln TQFP
8O-pInQFP
MANUFACTURER
Yamalchl
NEY
NEY
Yamalchl
Yamalchl
Yamalchi
Yamalchi
NUMBER
1051-0562-1387
6068
1051-0644-807
1051..()8()4-808
1051-1204-1596
DESCAIPTIOH
Solder through hole
Solder through hole
Solder through hole
Solder through hole
Solder through hole
Solder through hole
1051-0604-394
Solder through hole
6044
5-17
5-18
FIFO Memories:
Fine-Pitch Surface-Mount
Manufacturability
First-In, First-Out Technology
Tom Jackson
Advanced System Logic - Semiconductor Group
~lExAs
INSTRUMENTS
SCZAOO3A
5-19
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to Its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products In such applications Is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC·sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
Infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, Is granted under any patent right, copyright, mask work right, or other
Intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
5-20
Contents
TItle
Page
Introduction .............................................................................. 5-23
Improved Function Density ................................................................ 5-23
Manufacturing ......................................................... . . . . . . . . . . . . . . . . .. 5-23
Palladium-Plated Lead Frames ............................................................. 5-25
Testabllity ............................................................................... 5-26
DesignlPreproduction Considerations ....................................................... 5-26
Conclusion .............................................................................. 5-27
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
List of Tables
Table
1
2
3
4
5
ntle
Page
Fine-Pitch Packages ................................................................. 5-23
Defect Causes and Effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-24
Results of Soldered Joint Strength ..................................................... 5-25
Lead-Frame Platings by Package Type .................................................. 5-26
Available Fine-Pitch Test Sockets and Mechanical Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-27
5-21
5-22
Introduction
Recent advances in semiconductor processing and packaging have produced highly integrated, fine-pitch devices to
satisfy the demand for smaller systems. With the trend towards higher chip complexity occupying less board space,
device manufacturers must increase bit density while decreasing package size. To accommodate these requirements,
manufacturers have two choices: increase bit density, keeping the number of pins constant while reducing pitch and area,
or reduce the package lead pitch, keeping area constant while increasing pin count. Manufacturers of hand-held and
laptop computers and data communications and telecommunications equipment require the use of [me-pitch packages
to build and maintain a competitive advantage.
Improved Function Density
Texas Instruments (TI) provides five types of fine-pitch plastic surface-mount packages for its FIFO product line (see
Table 1). Each of these surface-mount packages has lead-to-Iead spacing less than or equal to 0.635 mm (0.025 in.). All
of these packages offer designers critical board-space savings that is required for advanced systems. Compared to the
commonly used 68-pin plastic leaded chip carrier (PLCC) for 18-bitFIFOs, TI's Widebus™ package, in either the 56-pin
shrink small-outline package (SSOP) or the 80-pin thin quad flat package (TQFP) , reduces board space by 70%. A 67%
saving of board space is available with TI's 36-bit FIFO family in the 120-pin TQFP compared to the 132-pin plastic
quad flat package (PQFP).
Table 1. Fine-Pitch Packages
THIN SHRINK
SMALL-OUTLINE
PACKAGE (SSOP)
THIN QUAD FLAT PACKAGE (TQFP)
Pin count
Lead pitch (mm)
Footprint (mm)
Board area (mm2)
Package suffix
64
80
0.5
12x 12
0.5
14x 14
120
0.4
16x 16
144
PM
196
256
PN
PCB
132
0.635
28x28
784
PO
56
0.635
10.35 x 18.42
190,6
DL
Manufacturing
Manufacturers are currently employing high-volume board-assembly techniques using standard lead pitches of 0.5 mm
(20 mils) and greater. However, as lead pitch continues to decrease, questions must be asked of both the'manufacturer
and the supplier:
Are [me-pitch packaging capabilities available?
Does production equipment have sufficient accuracy to produce high-volume, high-quality parts?
Do the manufacturing personnel have experience in high-volume, high-quality production using fine-pitch
packaging?
Have the testability issues of [me-pitch packaging been considered?
Standard processing techniques such as those used with surface-mount rigid-lead packages become difficult with
fine-pitch packaging. Manufacturing issues may arise from compromises in screen-printing techniques, solder
board/lead coplanarity, placement-accuracy requirements of components, and solder deposition methods (e.g., mass
reflowing). All of these factors can result in shorts or opens due to poor placement, too much solder, or not enough solder.
These issues influence the overall yield and reliability of the product.
Widebus is a trademark of Texas Instruments Incorporated.
5-23
Equipment for the placement of fine-pitch packaging must feature a highly accurate positioning system. Placement
accuracy for fme-pitch packages must increase as lead pitch decreases. Misaligned packages and boards greatly reduce
production yields as well as throughput. Systems that feature state-of-the-art machine vision, align and inspect leads,
and calculate registration with an extremely high degree of accuracy and repeatability, ensure high production yields.
There must also be careful control over the Z-axis pressure when placing these fme-pitch packages to' protect the lead
coplanarity. Currently, there are systems available with accurate placement as fme as O.I-mm pitch.
One of the most critical issues facing the manufacturer is the reliability of the footprint design. Constraints include the
length and width of the footprint and the amount of solder paste used to produce a good joint. If too much solder is used,
the footprint can bridge, causing a short (see Table 2). The minute dimensions associated with fme-pitch packages
require that the footprint be drawn to the highest level of accuracy in order to ensure consistent reliability. Board
assemblers must be able to match the footprint with the same level of accuracy and repeatability.
Table 2. Defect Causes and Effects
DEFECT
CONTROL
Solder bridging
Control the solder-paste quantity
Open circuits
Control solder-paste thickness and maintain lead coplanarity
Shorts and opens
Control equipment accuracy in the placement of parts
As previously discussed, the key to ensuring high yield is an accurate footprint pattern. Many manufacturers request
footprint pattems and dimensions to assist in their board assembly. There are several factors to consider when designing
a footprint pattern to ensure reliability:
• Device design - JEDEC or EIAJ Standard
• PWB - foil thickness, number of layers, supplier's capabilities
• Solder paste - type, solder mesh
• Printer - manufacturer, standoff control, squeegee pressure
• Print mask - type (stencil/mesh), tension, bias
• Reflow process - preheat, temperature, dwell, etc.
The key dimensions for designing an accurate footprint layout is shown in Figure 1.
A =
B1
B2 =
L
Distance Package Edge to End of Pad
= Pad Extension Beyond Heel of Foot
Pad Extension Beyond Toe of Foot
= Lead Foot Length
P = Lead Pitch
S = Distance From Center of Pin to Center of Pin
Figure 1. Footprint Diagram
5-24
Palladium-Plated Lead Frames
Another area for manufacturers to investigate is metallization, or bonding of the leads to the circuit board with solder.
There are several widely used localized reflow techniques including hand soldering, hot bar, focused infrared (IR), and
laser. With each technique, heat is applied to the leads until the solder melts. When the heat source is removed, the solder
cools forming the joint. Each manufacturer must make the choice between precision point-to-point systems (one chip
at a time) and the speed of gang bonding (multiple chip bonding). Another area ofmeta1lization to consider is preplating
of the leads by the device manufacturer. TI has begun to implement palladium (Pd) lead plating on many fme-pitch
packages. These efforts began with joint testing of palladium-plated leads with several large computer and telecom
customers in 1987. Since then, TIhas begun high-volume manufacturing with over five billion palladium-plated devices
in the field.
Palladium preplating is essentially a nickel- (Ni) plated lead frame that has a minimum of3 micro inches (0.076 micron)
of Pd. The Pd fmish protects the Ni from oxidation and eliminates the need for silver spotting. Silver (Ag) spots are used
to attach the fine wires from the die to the lead frames. However, the silver can migrate over time to form extraneous
electrical contacts that greatly impact reliability. Many problems associated with fine-pitch manufacturing can be
eliminated with palladium preplating:
•
•
•
•
•
•
•
•
Reduces excess solder
Excellent Pd wetting characteristics
Reduced handling
Improved package integrity
Reduced mechanical damage
Tarnish resistant
Compatible with existing assembly processes
Excellent adhesion to mold compounds
Table 3 shows the results of a solder-joint strength test comparing Pd solder joints to traditional solder joints. The results
demonstrate an equal performance between the two techniques. Palladium preplating also exhibits adhesion to most
mold compounds, which reduces moisture ingress and plastic-to-Iead-frame delimitation.
Table 3. Results of Soldered Joint Strength
SAMPLE
HOURS OF HEAT AGING
OHR
aHR
3 microinches Pd
5.171bf
5.951bf
5.85lbf 4.711bf
16HR
24HR
Solder dip
5.071bf
4.511bf
5.551bf
5.50 Ibf
In many cases, the cause for shorts and opens can be attributed to lead coplanarity, or the extent to which all leads lie
in a single plane. This holds especially true for fine-pitch packaging due to the smaller geometries and delicate leads.
Traditional solder-dipped leads tend to have more pin-to-pin alignment problems than the Pd-plated leads. The
Pd-preplated leads have a more conformal and uniform coating than those that are solder dipped since the plating is
performed prior to the packaging process (see Figure 4). An increase in coplanarity improves overall circuit reliability.
The excellent wetting characteristics of Pd improve the wicking effects of solder and form a better solder joint/fillet.
The thin Pd coating and minimal handling reduce the chance of coplanarity problems (i.e., shorts and opens) and also
produce uniform solder joints with a minimum amount of solder. Table 4 lists TI's fme-pitch packages that implement
Pdplating.
5-25
COPLANARITY
vs
%OFVALUE
40
35
I
30
25
o
PdUnlts
20
•
Dipped Units
15
10
5
o
0.2
0.4
0.6
0.8
n
,..,
1.2
..
1.4
1.8
Coplanarlty (mm)
Figure 2. Coplanarlty Results
Table 4. Lead-Frame Platings, by Package Type
PACKAGE
SUFFIX
LEAD FRAME
132-pin POFP
PO
Palladium
12o-pin TOFP
PCB
Palladium
8D-pinTOFP
PN
Solder
64-plnTOFP
PM
Solder
56-pinSSOP
DL
Palladium
Testability
Another issue introduced by the onset offme-pitch surface-mount packages involves testing circuit boards. With denser
printed-circuit boards heavily populated with fme-pitch surface-mount packages, the issues involved with functional
testing should be addressed. One of the most cost-effective solutions is the implementation of boundary-scan
methodology defmed by the joint test action group (JTAG) and adopted by the mEE 1149.1 committee. JTAG devices
incorporate on-chip test points called boundary-scan cells and utilize a serial-scan protocol tQrough the device. Devices
with JTAG can be designed into the datapath and provide the controllability and observability needed to troubleshoot
manufacturing defects.
Design/Preproduction Considerations
For designers who wish to implement fme-pitch packaging, TI provides an easy alternative for the development of
prototypes and breadboarding. TI has worked with several test-socket manufacturers who provide accurate and
easy-to-use through-hole test sockets for all of their surface-mount packaging. In addition to test sockets, TI also offers
mechanical packages. These are packages that include lead frames without the silicon and meet all mechanical
specifications. Mechanical packages provide an inexpensive means for manufacturing capability studies, machine
setup, personnel training, and process-development work (see Table 5).
5-26
Table 5. Available Fine-Pitch Test Sockets and Mechanical Packages
SOCKET
TYPE
MANUFACTURER
PART NUMBER
DESCRIPTION
64-pinTQFP
Yamaichi
1051-0644-807
Through hole
56-pinSSOP
Yamaichi
IC51-0562-1514
Through hole
8o-pinTQFP
Yamaichi
IC51-0804-808
Through hole
12o-pin TQFP
Yamaichi
IC51-1204-1596
Through hole
132-pin PQFP
Yamaichi.
I051-828-KS12338
Through hole
PACKAGE
TI PART NUMBER
64-pinTQFP
SN700870PM
56-pinSSOP
SN250011 DLR
8o-pinTQFP
SN700871PN
12o-pin TQFP
SN700782PCB
Conclusion
Designs that incorporate fine-pitch packages have the advantage of critical board-space reduction. As designers
continue to implement higher levels of integration, board space remains at a premium. With the implementation of
concurrent engineering practices from design to test to manufacturing, many packaging difficulties can be overcome.
Fine-pitch packaging is the designers' easiest option to reduce critical board space without the loss of higher chip
integration.
References
Abbott, D.C., Brook, R.M., McLelland, N., Wiley, J.S., "Palladium as a Lead Finish for Surface Mount Integrated
Circuit Packages," IEEE Transaction on Components, Hybrid Manufacturing Tech., Vol. 14, No.3, Sept. 1991.
Romm, D., McLellan, N., "Evaluation of Water Soluble and No-Clean Solder Pastes with Palladium Plated and Solder
Plated SMT Devices."
5-27
5-28
Package Thermal Considerations
Darla WeI/heuser
Advanced System Logic - Semiconductor Group
~1ExAs
INSTRUMENTS
SCZA002A
5-29
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to Its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to th'e specifications
applicableatthe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products In such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
5-30
Contents
TItle
Page
Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-33
Introduction ............................................................................. 5-33
Reliability ............................................................................... 5-34
Power Consumption ...................................................................... 5-34
Power Calculations ....................................................................... 5-36
CMOS ................................................................................ 5-37
BiCMOSlBipolar .....•.....•........................................................... 5-37
Thermal-Resistance Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5...:J7
Summary ................................................................................ 5-40
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-40
Figure
List of IDustrations
TItle
Page
1
Advanced Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-33
2
3
Icc Versus Frequency (One Switching, Unused Outputs Low) ...............................
Icc Versus Frequency (All Outputs Switching) ..•................................•.......
Icc Versus Frequency (All Switching, 50% Duty Cycle Enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Icc Versus Duty Cycle Enabled (25 MHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . ..
4
5
6
7
8
5-35
5-35
5-35
5-36
48-Pin SSOP 9JA Versus Trace Length ...........................................•..... 5-38
48-Pin SSOP 9JA Versus Air Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-38
48/56-Pin SSOP K-Factor Board Modeling ..........................•................... 5-39
5-31
5-32
Abstract
To meet current and future system requirements of increasing speed and decreasing size, integrated circuit
manufacturers are pushing the edge on existing packaging technology. A component's perfonnartce is detennined by
process technology and the thennallimitations of its package. As a leader in package technology, Texas Instruments (TI)
has introduced a number offme-pitch packages and is acutely aware of the thermal considerations that must be examined
by systems designers. This paper is intended to create awareness and understanding of thennal issues and to .explore
factors that influence thermal perfonnance.
Introduction
Thennal awareness became an industry concern when surface-mount (SMT) packages began replacing through-hole
(DIP) packages in PCB designs. Circuits operating at the same power enclosed in a sma1lerpackage meant higher power.
To add to the issue, systems required increased throughput, which resulted in higher frequencies, increasing the power
density even further. Not only are these same concerns haunting designers today, they are progressively getting more
severe.
Figure 1 shows part of the reason for increased attention to thennal issues. As a baseline for comparison, the 24-pin
small-outline integrated circuit (SOIC) is shown along with several fme-pitch packages supplied by n, including the
24-pin SSOP (shrink small outline), 48-pin SSOP, and the lOO-pin TQFP (thin quad flat pack). The 24-pin SSOP (8,
9, and 10 bits) allows for the same circuit functionality of the 24-pin SOIC to be packaged in less thanha1fthe area, while
the 48-pin SSOP (16, 18, and 20 bits) occupies just slightly more area but has twice the functionality of the 24-pin SOIC.
This same phenomena is expanded even further with the lOO-pin TQFP (32 and 36 bits), which is the functional
equivalent of four 24-pin or two 48-pin devices, with additional board savings over that of the SSOP packages. As the
trend in packaging technology continues toward smaller packages, attention must be focused on the thermal issues that
are created.
D
24-PlnSOIC
Area = 165 mm2
D
48-PlnSSOP
Area = 171 mm2
24-PlnSOIC
)
,
,
l
Height = 2.65 mm
Volume = 437 mm3
Lead Pitch = 1.27 mm
0
24-PlnSSOP
Area=70mm2
~
Helght=2mm
Volume = 140 mm3
Lead Pitch = 0.65 mm
10o-Pln TQFP
48-PlnSSOP
Height = 2.74 mm
Volume = 469 mm3
Lead Pitch = 0.635 mm
24-PlnSSOP
1CJO.Pln TQFP and
100-Pln Cavity TQFP
Area = 262 mm2
Height = 1.6 mm
Volume = 419 mm3
Lead Pitch = 0.5 mm
Figure 1. Advanced Packages
5-33
Reliability
The overriding effect of increased power densities in integrated circuits is a decrease in overall system reliability. A
direct relationship exists between junction temperature and reliability.
Table 1 provides an example of a device with an initial junction temperature of 150°C and the calculated failure-rate
decrease as the in-use junction temperature is lowered. The data in Table 1 indicates that lower junction temperature
results in increased system reliability.
Table 1
TEMPERATURE
·C
% FRt
150
96
140
80
130
46
120
11
110
1
100
0.02
t Failure rate at 100,000 hours
A better understanding of the factors that contribute to junction temperature (Tl) provides a system designer with more
flexibility when attempting to solve thermal issues. Device junction temperature is determined by equation 1:
(1)
Where:
TJ
TA
- junction (die) temperature (0C)
- ambient temperature (0C)
alA - thermal resistance of the package from the junction to the ambient (OC/W)
P-r - total power of the device (W)
Junction temperature can be altered by lower chip power consumption, longer trace length, heat sinks, forced air flow,
package mold compound, lead-frame size and material, surface area, and die size. Some of these are mechanically
inherent to a particular package while others are controlled by the designer and are application specific. Understanding
which variables can be influenced by practicing good thermal-design techniques requires a more detailed investigation
of power considerations as well as thermal-resistance measurements.
Power Consumption
One way to lower the junction temperature (TJ) of a device, thus improving reliability, is to lower the power
consumption. A vaiiety of options are available to help achieve this, such as low-power process technologies, reduced
output swing, and reduced power-supply voltage. A closer look at the power performance and advantages of several
popular logic families can assist the designer when choosing what best fits his/her needs.
The choices available from TI for high-speed bus interfaces range from standard bipolar (F) to advanced CMOS
(ACL/ACT) to state-of-the-art BiCMOS (BCT) and advanced BiCMOS (ABT). Figures 2 through 4 show comparisons
of current (ICC) consumption of'244 functions for these technologies across frequency. As expected, the bipolar device
consumes more current than the CMOS device at lower frequencies, but as frequency increases, this relationship no
longer holds true. In fact, there is a region in the frequency range where the CMOS device consumes more current than
the bipolar device. The point where they are equal is referred to as the crossover frequency.
80
70
~
-- - -- - -- - -
~
- - ECr
!It""
50
40
I
- -- --
F
60
ABT
30
20 ~
10
o
-1....--'
o
10
-
....--'r
20
40
30
50
~
60
t-- il'CT
70
80
100
90
Frequency - MHz
Figure 2.
Icc Versus Frequency (One Switching, Unused Outputs Low)
180
CT
V
160
/
140
c(
E
100
I
80
8
60
40
~CT
V
120
k:==e'! tr
~
k-:1 7
-
.,6
V
20
o~
o 10
20
~
_r-
~
:.----
ABT
40
30
----'
~~ F
50
60
70
80
90
100
Frequency - MHz
Figure 3.
Icc Versus Frequency (All Outputs Switching)
100
F
80
~
60
I
~
40
!-----""
~
..-;if.--l ~ CT
~
20 ~--
o
~
/
---?
V~
o
10
20
V"
V
V -- --- f..-""
v--' ~
30
40
V
r--
50
60
70
~
~
-
---
- -BCT~
ABT
80
90
100
Frequency - MHz
Figure 4.
Icc Versus Frequency (All SWitching, 50% Duty Cycle Enabled)
5-35
Typical applications for bus-interface devices require them to be disabled or in the standby mode during certain periods
of time, for instance, while other devices access the bus. This can result in a large decrease in current consumption for
ABT, BCT, and ACT devices, which have low-standby current. These values are given in the data sheets as ICC for ACT
and Iccz for ABT (250 IJA) and BCT (~ 10 mA). Current-consumption data versus percent duty cycle enabled is shown
in Figure 5. The frequency of the data is held constant at 25 MHz and all outputs are switching.
80
-
70
F
80
50 ~
t-- .......CT
40
30
20
10
.~
.......V
V
o --""
o 10
:,..::--
.
..- f.-- f-"
20
30
40
,--
. .. .
i-- I--
.....- f--
60
60
70
.
. .. .
--
ACT
...
P
--ra;
80
90
100
Duty Cycle Enabled - %
Figure 5. IcC Versus Duty Cycle Enabled (25 MHz)
The power-consumption data provided is limited to a small range of variations. However, using this data, along with
standard formulas, power consumption can be calculated for specific applications.
Power Calculations
When calculating the total power consumption of a circuit, both the static and the dynamic currents must be taken into
account. Both bipolar and BiCMOS devices have varying static-current levels, depending on the state of the output
(IcCLo IcCH, or ICCz), while a CMOS device has a single value for Icc. These values can be found in the individual data
sheets. ACT and ABT inputs, when driven at TTL levels, also consume additional current because they may not be
driven all the way to VCC or GND; therefore, the input transistors are not completely turned off. This value is known
as Mcc and is provided in the data sheet.
Dynamic power consumption results from charging and discharging of both internal parasitic capacitances and external
load capacitance. The parameter for ACT and AC devices that accounts for the parasitic capacitances is known as Cpd'
It is obtained using equation 2 and is found in the data sheet.
(l)
Where:
fi
- input frequency (Hz)
Vcc - supply voltage (V)
CL - load capacitance (F)
Icc - measured value of current into the device
Although a Cpd value is not provided for ABT, BCT, or F devices, the Icc versus' frequency curves display essentially
the same information. The slope of the curve provides a value in the form of mA/(MHz x bit), which when multiplied
by the nUmber of outputs switching and the desired frequency, provides the dynamic power dissipated by the device
without the load current.
Equations 3 through 7 can be used to calculate total power for CMOS, bipolar, and BiCMOS devices:
P,. - PS(static) + PD(dynamic)
5-36
(3)
CMOS
AC (CMOS-level inputs)
Ps -Vee x lee
PD - [(Cpd + cr) x vee2 x ftl Nsw
(4)
ACf (TIL-level inputs)
Ps - Vee lice + (N'ITLxAlee x DCd>]
PD - [(Cpd + Cr) x Vee2 x fdNsw
(5)
BICMOs/Blpolar
Ps - Vee [DCen(NH x leeHINT + NL x leaJNT)
+ (I-DCen)Iccz] + (N'ITL x Alee x DCd>
(6)
Note: alee - 0 for bipolar devices
Po - [DCen x Nsw x Vee x fl x (VOH- VOr) x CLI
+ [DCen x Nsw x Vee f2 x (mAlMHz x bit)] x 10-3
(7)
Where:
Vee
lee
IeCL
IeCH
lecz
alee
DCen
DCd
NH
NL
Nsw
NT
fl
f2
VOH
VOL
CL
.=
mA/(MHz x bit) -
Supply voltage (V)
Power-supply current (A) (from the data sheet)
Power-supply current (A) when outputs are in low state (from the data sheet)
Power-supply current (A) when outputs are in high state (from the data sheet)
Power-supply current (A) when outputs are in high-impedance state
(from the data sheet)
Power-supply current (A) when inputs are at a TIL level (from the data sheet)
% duty cycle enabled (50% - 0.5)
% duty cycle of the data (50% - 0.5)
Number of outputs in high state
Number of outputs in low state
Total number of outputs switching
Total number of outputs
Operating frequency (Hz)
Operating frequency (MHz)
Output voltage (V) in high state
Output voltage (V) in low state
Extemalload capacitance (F)
Slope of the lee versus frequency curve
Thermal-Resistance Values
Design trends requiring board size reduction have made way for circuit manufacturers to produce fme-pitch packages
that appear to threaten the reliability of systems due to further thermal constraints. As a leader in packaging technology,
TI has done considerable research into the validity of traditional thermal measurements and data provided by circuit
manufacturers.
Unlike data-sheet parameters, where the industry has adopted a standard load for measurement (50 pf, 500 0), the
measurement of alA has no standard to which all manufacturers comply. The problem facing the designer wishing to
make comparisons of thermal data from several manufacturers is that this could be an apples-to-oranges type
comparison. As a result, a software package has been developed at TI to allow designers to obtain thennal data based
on their specific application.
The validity and usefulness of the traditional approach to presenting alA values became a pressing issue when TI and
another manufacturer measured an identical package and obtained results that varied by 40%. Extensive research led
5-37
to the conclusion that the methodology used to measure ElJA did not cause the discrepancy but the physical aspects such
as trace length, trace width, number of devices per board, and proximity of the other devices did.
To demonstrate the extreme impact of trace length alone, Figure 6 shows the EllA values forTI's 48-pin SSOP at 0 LFMP
and 250 LFMP with varying trace lengths. The 48-pin SSOP is shown in Figure 1 for a side-by-side comparison with
the standard 24-pin SOle, the 24-pin SSOP, and the I OO-pin TQFP. The data in Figure 6 clearly shows the need for more
complete thermal data, not simply a single data point.
,,
130
110
90
A_
-....
OLFPM
..........
-A _
~
--- --- --........... -- - 250 rPM
70
50
~
o
0.2
0.4
0.8
0.8
1.0
1.2
1.4
1.8
1.8
2.0
Trace Length -In
Figure 6. 48-Pln SSOP ElJA Versus Trace Length
There are other methods to lower the EljA of a device. Using heat sinks or blowing air across a device certainly improves
the ability to remove heat from its surface. Figure 7 provides EllA data for the 48-pin SSOP with trace lengths of200 mils
and 1 inch while varying the amount of air flow. Although many applications tend to limit the amount of air flow,
excellent benefits are possible with increased air flow.
120
. ...
100
80
80
---
.. .
. .. .
...
r--, ~
r--.
r--
200 Mils
• i'-"
~
1000 Mils
..
-r---,r-- .:.:..:;
40
20
o
50
100 150 200 250
300 350 400 450 500
Air Flow - LFPM
Figure 7. 48-Pln SSOP ElJA Versus Air Flow
5-38
Several variables that have a direct effect on @JA values were compared and results are shown in Figure 8. Surprisingly,
the major contributing factor is trace length, not air flow. Once again, this validates the need for improvement not
necessarily in the test methodology used to calculate @JA values, but certainly in the way those values are provided.
D
VARIAIU.s
BAmlE
~
QQ!::!IBIBUIIQN
Trace Length
75 mils - 2000 mils
41.4
AirFlow
o LFM -
500 LFM
28.8
Board Extension
~
After Trace
o mils -400 mils
6.5
~
Board Extension
After Package End
o mils - 755 mils
2.6
~
Trace Thickness
1oz-2oz
2.2
Trace Width
3 mlls-15 mils
2.1
Power
0.5W-1.5W
0.1
Total Interactions Betwaen Factors
16.3
a-HI
EI
--
Figure 8. 48-/56-Pln SSOP K-Factor Board Modeling
TI provides @JA values for a variety of packages (including the SOle, SSOP, and QSOP) in a user-friendly software
. package. The program allows designers to specify their conditions, such as trace length, air flow, proximity of other
devices, and trace width in order to obtain realistic thermal solutions.
5-39
Summary
How a system can avoid being a reliability nightmare in today's world where:
•
•
•
Eight-bit devices are being replaced by 16 and 32 bits in a single package, increasing the power.
Higher operating frequencies add to the increase in power.
Fine-pitch packages are reducing the amount of available surface area to remove heat from a device.
Semiconductor manufacturers must take the first step and provide realistic and useful thermal information that will
provide designers key variables to focus on for thermal management.
References
Thermal Software
Contact the factory at (903) 868-7682.
Power Dissipation
Advanced CMOS Logic Designer's Handbook, Texas Instruments Incorporated, 1988, literature number SCAAOOIB
SSOP Designer's Handbook, Texas Instruments Incorporated, 1991, literature number SCYAOOI
6-40
K-Factor Test-Board Design Impact
on Thermal-Impedance
Measurements
LarryW. Nye
Advanced System Logic - Semiconductor Group
:lllExAs
INSTRUMENTS
SCAA022A
5-41
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI prodl,.lcts in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize Inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
5-42
Contents
ntle
Page
Abstract. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-45
Introduction ............................................................................. 5-45
Modeling Approach . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. S-46
Design of the Experiment .................................................................. 5-47
Orthogonal·Polynomial Expansion .....•..•...............................•...•............. 5-49
Verificadon: Equation Versus Actual Measurements ........................................... 5-52
Conclusion .............................................................................. 5-53
Acknowledgements .................................•........................... ,.......... 5-S3
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5-53
5-44
Abstract
The rapid advancement in semiconductor-device technology is placing unprecedented demands on device-packaging
technology. In an effort to meet system requirements for increased speed in smaller footprints, integrated circuit
manufacturers are pushing existing packaging technology to new limits. Product performance is a function of both
device and packaging technologies. In many instances, the thermallirnitations of the packaging system can severely
restrict the performance of the device, thus limiting systems applications. System designers and integrated circuit
manufacturers are becoming increasingly more concerned about accurate thermal characterization.
There are several indices typically reported to reflect the thermal performance of a package. Thermal impedances, ElJA
(junction to ambient) and ElJC (junction to case) are the most frequently used throughout the industry. Although there
are several specifications on the administration of these tests and measurements, there is no universally accepted
industry-wide standard. This lack of standardization promotes an apples-to-oranges comparison of published data, as
well as inaccurate estimation of application performance.
This paper focuses on the impact of the wind-tunnel k-factor test-board design parameters on reported ElJA results. By
employing statistical experimental design techniques and finite element analysis (PEA), equations are derived that can
be used to quickly normalize reported ElJA values under various test-board conditions. These mathematical equations
are shown to correlate well with empirical wind-tunnel results. A computer program, THETACAVM, has been
developed by Texas Instruments (TI) to assist system designers in understanding and comparing the thermal capabilities
of packages sourced from various integrated-circuit manufacturers.
Introduction
The use of statistical design of experiment (DOE) techniques combined with PEA provides the engineering community
with valuable tools for forecasting the behavior of a system or process. A natural marriage, the DOE and PEA
combination allows the engineer to study a range of boundary conditions for numerous design factors and to analyze
the impact and associated response for each factor and interaction within the system. With the use of orthogonal
polynomial expansion techniques, experimental results can be effectively transformed into mathematical equations
based on the strength of the various factors and associated interactions. These equations are useful for performing
what-if analyses on a system or process.
The thermal impedance (k-factor) of a package is defined as the increase injunction temperature above the ambient due
to the power dissipated by the device and is measured in degrees Celsius per watt. There are two indices commonly used
to describe the thermal characteristics of an integrated-circuit package: ElJA and ElJC' ElJC is the thermal impedance from
the integrated-circuit die junction to the package external case and is typically measured in a circulating bath of an inert
liquid simulating an infinite heat sink. ElJA is the most widely used and least understood measurement utilized in package
selection for application design criteria. There are actually two 9lA measurements commonly reported:
Socket mounted and measured in 1 cubic foot of still air
Board mounted and measured in a wind tunnel at various air flows
In case #1, the type of socket and socket manufacturer should be noted when comparing reported values, as they can
significantly impact the reported ElJA values.
The focus of this report and the development of the THETACAL software tools are targeted to address the problems
associated with board-mounted ElJA values reported under wind-tunnel conditions (case #2). As indicated earlier, there
are several specifications on the administration of wind-tunnel tests and measurements, but there is no universally
accepted standard. Wmd-tunnel dimensions and k-factOl;' board construction techniques vary widely from manufacturer
to manufacturer and can dramatically impact the reported ElJA values. Figure 1 shows the differences noted on an
identical package measured on two different integrated-circuit manufacturer's k-factor boards in the same wind tunnel.
THETACAL is a trademark of Texas Instruments Incorporated.
5-45
In Figure I, there is roughly a 45°C/W difference (still air) between manufacturers induced by the k-factor board alone.
Considering this fact, it is possible for a wide range of reported k-factorvalues to exist for any given package, depending
on the test-board design employed by the manufacturer. Systems designers unaware of these differences can be
artificially restricted in packaging selections based only on reported thermal-impedance values.
120
11 "
... ~
100
90
80
-- --
___ TI Short-Trace Board (actual)
COmpetItor's Long-Trace Board (actual)
-+I---
~
70
6 o~~
50
----
t---
--~ ~
-----
40
30
o
50
100
150
200
250
300
350
400
450
500
AlrFlow-lfm
Figure 1. Competitor Versus TI K-Factor Board (52-pin· MQFP)
In an effort to provide system designers with an accurate tool for estimating the impact ofk-factor test-board designs
on reported thermal impedance values (aJA), TI has developed the THETACAL software package. By employing
statistical experimental design techniques combined with finite element analysis tools, equations can be derived to
perform what-lfanalyses varying single or multiple input parameters simultaneously to accurately estimate their impact
on ~e desired response (aJA)' This tool allows designers to compare the thermal performance of a given package
sourced from various manufacturers on an apples-to-apples basis. In addition, the software can be utilized to better
understand the influence of the various board-related parameters and their impact on aJA.
Modeling Approach
The following four-phase methodology was utilized to develop the THETACAL software package:
1. Design of the experiment using orthogonal arrays
2.
Modeling the package using PEA (ABAQUSTM) tools
3. Expansion of the matrix results into an orthogonal-polynomial equations
4.
Mathematical simulation of the thermal response (aJA) for performing what-if analyses
OnCe the orthogonal-polynomial equations are completed and verified, they are incorporated into the THETACAL
software environment. Each package type and pin count are evaluated separately to ensure accuracy in the equations.
ABAQUS is a trademark of Texas Instruments Incorporated.
5-46
Design of the Experiment
Typical k-factor boards are constructed using an FR4 or polyimide-composite substrate. Copper traces of varying
dimensions are fabricated upon this substrate for package mounting and to complete the electrical connections required
for k-factor testing. The parameters in Table 1 are most typically varied in k-factor board construction (see Figure 2)
and are the focus of this study and the THETACAL software development.
Table 1. Evaluation Parameters
TRACE
LENGTH
(mils)
AIRFLOW
(11m)
POWER
(watts)
50
750
0
500
0.5
1.5
Low
High
TRACE
WIDTH
(mils)
BOARDZ
EXTENSION
(mils)
BOARDY
EXTENSION
(mils)
TRACE
THICKNESS
(mils)
3
0
550
0
550
2.8
15
1.4
Board Extension
After Trace (or V)
T
Trace
Length
-r~~~~~~~~~
OUT
o
Board Extension
After Package (or Z)
Trace Width
NOTE: Y and Z are used for PLCC and QFP packages.
Figure 2. Test Board
An L16 orthogonal arrayl was selected as the design vehicle used to evaluate the impact of all identified main factors
and their expected interactions within the k-factor test-board system. Since the focus of this study is to derive
mathematical equations to be utilized for estimation purposes, it is extremely important to properly define the layout
of the experiment to capture all sources of variability; i.e., the accuracy of the equation is best when the unresolved
variability is minimized. Once the experiment has been properly defined, appropriate models are prepared per the matrix
and processed through the fmite element analysis thermal solver (ABAQUS). A typical data set, as returned by the FEA
software, is shown in the far right column of Table 2. Statistical analysis is done and orthogonal-polynomial equations
can be derived from the completed data set.
5--47
Table 2. Matrix Definition and Results
RUN
1
2
3
4
5
6
7
8
9
10
11
12'
TRACE
LENGTH
(mils)
AIRFLOW
(lfm)
POWER
(watts)
50
50
0
0
0.5
50
50
50
0
0
500
50
50
50
750
750
750
500
500
500
0
0
13
750
750
14
15
750
750
16
750
0
0
500
500
0.5
1.5
1.5
0.5
0.5
1.5
1.5
0.5
0.5
1.5
1.5
0.5
500
0.5
1.5
500
1.5
TRACE
WIDTH
(mils)
BOARDZ
EXTENSION
(mils)
BOARDY
EXTENSION
(mils)
TRACE
THICKNESS
(mils)
MODEL
3
15
0
550
0
550
3
15
0
550
550
0
151.3
100.6
119.2
121.2
3
15
3
15
3
15
550
0
550
0
0
0
550
550
0
0
550
1.4
2.8
2.8
1.4
2.8
1.4
1.4
2.8
2.8
1.4
3
15
550
0
550
3
15
550
0
0
550
3
550
550
2.8
2.8
15
0
0
1.4
550
0
1.4
2.8
1.4
("~A
W)
66.5
68.6
61.6
75.5
77.7
71.6
84.0
67.5
56.1
50.0
53.5
52.5
By using statistical tools such as the effects table (see Table 3) and analysis of variance (ANOYA) table (see Table 4),
one can analyze the impact of each individual factor and associated interactions within the system. In Table 4, the
air-flow parameter accounts for 47.3% of the total variability measured within the ranges probed, followed closely by
the trace length parameter with a 31.4% contribution. In addition, the trace length by air-flow interaction accounts for
8.6% of the variability measured in the system. In total, the airflow, trace length, and the interaction between these two
factors accounts for 87.3% of the total variability of the system. The sum of the contribution of the remaining factors
is a mere 12.7%. When analyzing the effects table (see Table 3), one can see that employing a longer trace length (see
high-level average) on a k-factor board achieves basically the same impact as using a high velocity of moving air across
the package. Longer trace lengths on a k-factor board essentially act as built-in heat spreaders on the board and are one
of the primary reasons for the dramatic differences noted between manufacturers in reported aJA values on identical
packages. In light of the fact, it is essential that designers understand the measurement conditions employed when
determining the fitness for use of a package for a given application.
Table 3. Effects Table
SUM OF
SQUARES
LOW-LEVEL
AVERAGE °ClW
HIGH-LEVEL
AVERAGE °ClW
EFFECToClW
Airflow
5959.84
3956.41
1079.12
402.00
99.14
95.56
60.54
64.11
-38.60
Trace length
88.05
84.85
71.63
74.83
84.20
83.74
83.54
75.48
75.94
76.14
76.31
76.76
FACTOR
Trace length by air flow
BoardZ ext.
Trace length by board Y ext.
Trace width
Board Yext.
Trace thickness
Trace length by board Z ext.
Trace length by trace thickness
Trace width by trace thickness
Trace length by power
Air flow by power
5-48
304.50
243.36
219.04
198.81
151.29
83.36
82.91
,40.32
81.43
15.60
8.41
7.84
80.83
80.56
80.54
78.25
78.85
79.11
79.14
-31.45
-16.42
-10.02
-8.72
-7.80
-7.40
-7.05
-6.15
-3.18
-1.98
-1.45
-1.40
Table 4. Analysis of Variance (ANOVA) (50-mil thru 7So-mll trace lengths)
FACTOR
DOF
SUM OF
SQUARES
MEAN
SQUARES
F·TEST
%
CONTRIBUTION
STATISTICAL
SIGNIFICANCE
Airflow
1
5959.84
5959.84
2995
47.3
99%
Trace length
1
3956.41
3956.41
1988
31.4
99%
Trace length by airflow
1
1079.12
1079:12
542
8.6
99%
Board Z ext.
1
402.00
402.00
202
3.2
99%
Trace length by board Y ext.
1
304.50
304.50
153
2.4
99%
Trace width
1
243.36
243.36
122
1.9
99%
BoardYext.
1
219.04
219.04
110
1.7
99%
Trace thickness
1
198.81
198.81
100
1.6
99%
Trace length by board Z ext.
Trace length by trace thickness
1
1
151.29
151.29
76
95%
40.32
40.32
20
1.2
0.3
Trace width by trace thickness
1
15.60
15.60
8
0.1
Trace length by power
1
8.41
8.41
4
0.1
Air flow by power
1
7.84
7.84
4
Power
1
3.42
Trace length by trace width
1
95%
Error pool:
Residual
0.56
0.005
Total residual
2
3.98
Total
15
12590.54
1.99
0.2
100
Orthogonal-Polynomial Expansion
The results of an orthogonal array can be easily expanded into a powerful orthogonal-polynomial equation. Employing
statistical principles, it is possible to construct an accurate mathematical model to quickly estimate the thennal response
of a package by analyzing the impact of critical design parameters and key interactions. There has long been a need for
an effective thennal calculator that can accurately and reliably estimate the thennal condition of a package under various
design parameters, i.e., to analyze the impact of various material, dimensional, and air-flow conditions.
Orthogonal-polynomial equations provide such a tool. Utilizing this approach, the solving power of the PEA software
can be effectively transfonned into a mathematical equation or a system of equations for the desired response for
performing what-if analyses within the ranges probed. The general equation fonnat for a two-level orthogonal array with
interactions follows. Higher-order equations for nonlinear responses, not described in this work, can also be employed
using this technique2.
General Equation Format
a
JA =
8M:
+bl(a)(a-a)
[linear tenns for factor a]
+ bl(b)(b - b)
+ bll(a _ x _ b)ea - a)(b - b) .. ·
[linear tenns for factor b]
[interaction tenns for factor a - x -b]
5-49
Where:
aJA
- Predicted matrix response
8M: - Average matrix response
b I(i) - Coefficient of the linear response for i
lvl(i) -
Number of factor levels at indicated setting for factor i
h(i) - Il setting between factor levels
b II (i) - Coefficient of interaction response for i
= Factor input variable for what-if analysis
a
a
- Average of factor settings
Factor CoeffIcIents
Linear coefficient:
b 1(a)
_ -AI + Ai
-::-;,f--_-:--'"
r * ""'(a)h(a)
-
Where:
Ai
- Sum of factor response at level indicated
r
- Number of runs per factor level
AS
- (1 for a 2-level factor) (2 for a ;3-level factor)
heal = Factor Il setting
Interaction coefficient:
b
11 (A-x-B)
_ [(AI
-
+ B I) - (AI + B 2)]
- [(A 2 + B I) - (A 2
r*AsAhA * ASBhB
+ B 2)]
Once the equation is derived, the initial test conditions can be plugged into the equation to check for accuracy against
the original modeled parameters as shown in Table 5. If the experiment has been properly designed to capture all
significant sources of variability, the equation results should closely match the modeled results. If the error term is
minimal (see Table 4), as in this case, the equation matches the modeled results exactly. As the error increases, the
accuracy of the equation decreases. At this point, the power of the FEA is transformed into a simple mathematical model
for this response within the ranges probed for all parameters. It is now possible to vary individual or multiple input
parameters (within the ranges studied) for performing what-if analyses. As with any simulation, equation results should
be tested against empirical results to ensure proper accuracy. If the desired accuracy is not achieved, the input models
should be reevaluated and adjusted as required.
HO
Table 5. Equation Versus Model
RUN
1
2
3
4
5
6
7
TRACE
LENGTH
(mils)
AIR
FLOW
(lfm)
POWER
(watts)
50
50
50
50
50
50
0
0
0
0
0.5
0.5
1.5
1.5
500
500
500
0.5
0.5
1.5
1.5
0.5
8
9
10
11
50
50
50
750
' 750
12
13
750
750
14
15
750
750
750
16
500
0
0
0
0
500
500
500
500
TRACE
WIDTH
(mils)
BOARDZ
EXTENSION
(mils)
BOARDY
EXTENSION
(mils)
TRACE
THICKNESS
(mils)
MODEL
8JA
("C/W)
0
0
550
1.4
2.8
2.8
1.4
2.8
151.3
100.6
119.2
121.2
66.5
1.4
1.4
2.8
2.8
1.4
1.4
68.6
61.6
75.5
77.7
71.6
84.0
2.8
67.5
84.0
67.5
1.4
2.8
2.8
56.1
50.0
53.5
56.1
50.0
53.5
1.4
52.5
52.5
3
15
550
0
550
3
15
3
15
550
0
3
15
550
0
550
0
0
550
550
0
0.5
1.5
3
15
3
0
550
0
0
550
550
1.5
0.5
15
3
550
550
0
0
0.5
1.5
1.5
15
3
15
0
550
550
550
0
0
EQUATION
8JA{"C/W)
151.3
100.6
119.2
121.2
66.5
68.6
61.6
75.5
77.7
71.6
120
11
.I
v~~
100
~
~
90
80
------
7n.
...... TI Short-Trace Boerd (actual)
___ TI Short-Trace Boerd (equation)
___ Competitor's Long-Trace Board (actual)
~ Competitor's Long-Trace Boerd (equatIon)
~
~~
_jt-r--
60
50
40
30
o
50
100
-- ----.....:: ........... r--
I--.........
""'":l~
r--
150
~
200
250
300
350
400
450
..........
-:ll'
500
AlrFlow-lfm
Figure 3. 52-Pin MQFP (actual versus equation)
5-51
Verification: Equation Versus Actual Measurements
The air-flow and trace-length parameters were the most dominant influences noted with respect to 8JA' Wind-tunnel
measurements taken on k-factor boards with both short- and long-trace conditions were compared against the
orthogonal-polynomial equation. Figure 3 shows that the equation accurately estimates the 8JA under radically different
k-factor board conditions.
Individual FEA-model runs in the orthogonal array used to derive the equation can take several hours of computer
processing time. depending on the type of workstation used. In an effort to minimize the modeling time required for each
package. 2-1evel orthogonal arrays were used to minimize the number of runs required to approximate the system. Due
to the extremely broad range of trace lengths that can be employed in k-factor test board design (50 mils to 2000 mils).
and considering the dramatic influence of the trace-length parameter on 8JA. two separate matrices are evaluated for
each package. The impact on the 8JA induced by the trace-length parameter is quite dramatic on most packages between
50 mils and 750 mils. From 750 mils to 2000 mils. the impactis less dramatic. In an effort to achieve acceptable equation
resolution using linear approximations. two matrices were evaluated for each package. The first matrix focused on the
shorter trace lengths and the second matrix focused on the longer traces. In the mETACAL software. this is transparent
to the user upon input; however. minor discontinuities may be noted where the equations converge.
The equation(s) can now be utilized to perform what-if analyses on the various input parameters. Figure 4 indicates the
impact that the trace length has on 8JA at various wind-speed conditions.
The knee of the curve at approximately 0.75 inches (750 mils) is the point where the equations from the two matrices
converge. The mETACAL software can be used to evaluate any of the parameters considered in the study in a similar
fashion. The equations used in the mETACAL software package provide the end users with the power of FEA
capabilities (for the 8JA response) instantaneously and requires no workstation or special skills to use.
140
..... StliIAlr
____ 250lfm
. . . 500lfm -
120
~~
100
~
-- ---.~
~
60
... -
60
40
20
o
0.2
0.4
~
.....
.....
---
-
---
0.6
0.8
1.2
.....
.....
.....
"Y
"Y
"Y
-
-
-
1.4
Trace Length -Inches
Figure 4. 52·Pin MQFP (trace length effect)
- 1.6
1.8
2
Conclusion
Thennal management of semiconductor packages is becoming increasingly more critical with the move to smaller
package geometries and higher power requirements. In order to meet increasingly challenging design goals, systems
designers and end users of integrated-circuit packages must be able to make infonned decisions on the fitness for use
of a package based on thennal considerations. K-factor test-board construction can dramatically impact reported ElJA
results and promote restrictions in package selection and system-perfonnance specifications. The THETACAL software
package provides users with an effective tool to nonnalize reported ElJA values and assist in making infonned decisions
on package selection'to reach design goals.
Acknowledgements
The author wishes to thank the following persons for their contributions to this work: Paul Noel for his exten~jve efforts
in developing the THETACAL software enviromnent, Dr. Jerald Parker, Professor Jim Cutbirth, and the team of
engineering students at Oklahoma Christian University of Science and Arts for their efforts in perfonning the thennal
simulations, and Jim Fielding of Texas Instruments for his extensive modeling efforts. In addition, the author would like
to thank Darvin Edwards, Steve Groothius, and Lon McKinstry of Texas Instruments for their support in the areas of
finite element analysis and k-factor measurement.
References
1.
Genichi Taguchi, "Introduction to Quality Engineering," page 183, UNlPUB/Kraus International Publications,
1986.
2.
Genichi Taguchi, "Systems of Experimental Design," VolUme 2, pages 599-622, UNlPUB/Kraus International
Publications, 1988.
5-53
5-54
More Power in Less Space:
A Thermal Enhancement Solution
for Thin Packages
Mary Helmick, Larry Nye, and Edgar Zuniga
Advanced System Logic - Semiconductor Group
Reprinted from Texas Instruments Technical Journal;
Vol. 11, No.4, July-August 1994
~lExAs
INSTRUMENTS
SCAU001A
5-55
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable atthe time of sale in accordance with Tl's standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
of TI products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications asSistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which
such semiconductor products or services might be or are used.
Copyright © 1996, Texas Instruments Incorporated
5-56
ENGINEERING TECHNOLOGY
More Power in Less Space: A Thermal
Enhancement Solution for Thin Packages
Integrated circuit packaging technology can no
longer be treated as a secondary consideration to circuit
design. The packaging system is an integral part of the
device function, composed of sophisticated materials and
complex assembly processes that balances many diverse factors, dramatically impacting the device performance. Often,
package design must now be done concurrent with circuit
design, understanding the limitations of each on the other.
Recent advances in wafer fabrication technology have
forced IC package designers to provide packaging solutions for higher power in smaller spaces. Traditionally,
shrinking the size of plastic packages restricts the device
performance due to thermal constraints.
Using the equivalent 8- and 16-bit functions as the
board space benchmark, a package was needed to accom-
Abstract:
T
RENDS toward higher device
functionality in smaller
space have driven the
development of space-efficient
packages. Integrated circuit (lC)
devices have evolved from lowpin-count, coarse-pitch, throughhole packages to high-pin count,
fine-pitch, surface-mount packages.
This evolution has placed new thermal management demands on IC
packaging technology.
As plastic packages shrink in
area and thickness, thermal
impedances increase, limiting the
power and frequency at which
devices can operate. To take
advantage of the increasing capability of IC devices, solutions must
be found for smaller packages that
can dissipate high power. A traditional option for thermal management is to add external heat sinks
to conventional plastic packages,
modate 32- and 36-bit logic devices. The resulting package size presented thermal management problems that
had to be addressed with some revolutionary approaches.
Additional design goals were the equivalent package reliability to existing packages and the ability to produce the
package at an acceptable cost for the target market.
A cross-functional team was structured to include
resources from package design, chip design, package
assembly, reliability and device testing. Design for Manufacturability concepts were used to meet six sigma process capability on all aspects of the packaging system. The
resulting design was a thermally enhanced thin quad flat
package (TQFP TEP) that can dissipate 2.4 watts of power
in a 256-mm2 board area, assuming 25°C ambient temperature and 150°C maximum junction temperature.
but emerging applications (e.g.,
laptop and notebook PCs) have
placed additional clearance constraints, preventing this approach.
Customer requirements for this
package design were: meet existing package reliability levels,
2.4 W power dissipation, footprint
smaller than the equivalent function in multiple packages and
manufacturable at acceptable cost.
A design team was structured to
include chip designers, assembly
process engineers, package design
engineers and key component
suppliers to facilitate the development process.
Design Criteria
A new package was required for a
family of 32- and 36-bit bus interface logic components. Several
constraints were placed on the
design of the package: the package
must have 100- and 120-pin configurations; the board area must
be no larger than that required for
the equivalent function in 8- or 16bit versions; the package must dissipate 2.4 watts without an external heat sink; and the manufacturing cost must be competitive in
the marketplace.
Design Approach
Considering the design constraints, two form factors were
analyzed; a dual in-line design
and a quad design. Device architecture preferred the in-line
design, but considering available
die bonding and leadframe manufacturing capabilities, an in-line
design that met the board space
constraint would require a lead
pitch of 0.3 mm. Research
throughout the marketplace indicated that by 1993, O.4-mm pitch
Mary Helmick, Larry Nye and Edgar Zuniga
JULV-AUGUST
1994
5-57
ENGINEERING TECHNOLOGY
was acceptable, but O.3-mm pitch
was not compatible with current
board mount capabilities. The 0.4mm outer lead pitch quad design
was chosen.
Two approaches to thermal
enhancement were considered
(Figure 1) a cavity-type lidded
plastic package and an exposed
heat slug plastic package. Two
heat slug options were evaluated;
a heat slug attached to a conventional die pad and direct die
attach to a heat slug. All designs
were evaluated in chip-up and
chip-down configurations.
Thermal models and analytical
data showed that both design
approaches can dissipate the
required power. For each design,
the chip-down configuration maximizes the heat transfer from the
package, especially with forced
convection. In this configuration,
the customer has the option to use
an external heat sink if the application demands (Table D.
The cavity design had addi-
Table I. Modeled Power Dissipation of Various Package Configurations.
..........·,.~,_-~~~:1.1.•~
·muIm~J~""~·..
CbipOQWll
t-ieatSI\4Sty1e
ChIp.U,p .
Cavity Package - Chip Down
Heat Slug Package (Die Pad Attached) - Chip Up
Heat Slug Package (Direct Attach) - Chip Up
Heat Slug Package (Die Pad Attached) - Chip Down
Heat Slug Package (Direct Attach) - Chip Down
Figure 1. Package Configurations Considered.
TITECHNICAL JOURNAL
5-58
ENGINEERING TECHNOLOGY
tional process complexity and possible reliability problems due to
moisture ingress, thermal mismatch and bond wire movement.
The heat slug design used conventional processes and equipment.
The heat slug design in the chipdown configuration was chosen
based on its ability to meet the
design criteria, compatibility with
existing processes, potential for
improved reliability performance
and more cost-effective manufacturing flow. The package was
designed to meet the emerging
JEDEC standard for 1.4-mm thick
thin quad flat packages (MO-136)
(Figure 2).
Material Selection
Thermal constraints drove the use
of a copper leadframe and a copper heat slug (Figure 3). Based on
positive past results with finepitch packages, a palladium preplated leadframe was selected.
The heat slug was directly
attached to the leadframe due to
the 1.4-mm thickness of the package. This design, as opposed to a
slug attached to the die pad or a
drop in heat spreader, gives a
more direct heat path to the outside of the package and simplifies
the assembly process. The heat
slug is attached to the lead frame
using a two-sided adhesive film.
A polyimide film was chosen due
to its stability at elevated processing temperatures and its low
moisture absorption. The adhesive
film also provides electrical isolation between the heat slug and the
lead fingers.
The heat slug required a surface
treatment to inhibit corrosion
since it was exposed to air. A proprietary surface treatment was
selected based on its superior
1-._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1
adhesion performance with molding compounds. Shear tests were
Figure 3. Leadframe with Attached Heat Slug.
JUL V-AUGUST
Package Cross Section
Figure 2. Package Outline Drawing -100 TQFP TEP.
o
o
Bottom View
Top View
1994
5-59
ENGINEERING TECHNOLOGY
run to compare the adhesion of
"Button" of
various mold compounds to cop¥Mold Compound
per treated with this proprietary
process and standard leadframe
materials by shearing "buttons" of
mold compound off of material
samples (Figure 4). The "buttons"
of compound are molded to the
heat slugs or conventional dieattach pads and subjected to the
t:;CCCCCCCCCCCYv,~Treated Heat Slug
normal post-mold cure process
or Die Attach Pad
before being sheared from the
slugs. The shear force required to
remove the "button" from the Figure 4. "Button" Shear Test Setup.
sample provides a relative adhesion value for different compounds and leadframe or heat
slug materials (Table ID.
Finite element analysis was Table II. Average Shear Force Normalized for Button Area (psi).
used to determine the von Mises
stress levels in the silicon chip, at
the mold compound/chip surface
31
interface and at the die attach/
" .
heat slug interface using different
B
size and shape heat slugs (Figure
5). Heat slugs with troughs were
considered in an attempt to deflect
the point of maximum stress away
from the ball bond area. For exam- . extra processing step was not
The leadframe design employs
pIe, in Cases 1 and 3 (Figure 5), required to obtain the desired a preplated palladium finish. The
while the stress at the ball bond package reliability.
slug is attached to the leadframe
was reduced from 7 K psi to 5.9 K
using a two-sided adhesive film
psi with the addition of a trough, Design Features
applied at high temperature. The
stresses at the die attach/heat slug The heat slug was designed to film is cut in a "window-frame"
interface increased from 62 K psi maximize the exposed surface configuration, providing support
to 70 K psi. The die attach/heat area for heat flux and to accom- for all lead fingers. The package
slug interface is the weakest "link" modate the largest possible chip. assembly operation starts with an
in the package, therefore the The heat slug was designed with a assembled lead frame, which is
trough design was not chosen. flange on the top surface. This processed using the same equipHeat slug thickness and shape flange provides both a locking ment and flows as conventional
was optimized by balancing ther- mechanism with the mold com- plastic packages.
mal and stress responses to meet pound and a longer surface interThe ~hip-down configuration of
the design guidelines.
face between the compound and this package maximizes the therMold compound candidates the slug. If moisture penetrates mal performance. The leadframe
were evaluated for wire sweep along the slug-mold compound design allows the package to be
and autoclave performance and interface, this moisture would processed conventionally (chipgold wire was chosen to minimize have a longer path to reach the die up) through the molding operawire sweep in this package. Sili- surface. The slug shape also tion (Figure 7). The package oriencone die coating was evaluated for allows for easy orientation in tation is changed before lead form,
enhanced die corrosion resistance, automated assembly processes but this change is transparent to
but test results showed that this (FigUre 6).
the manufacturing process.
~.
TI
5-60
TECHNICAL JOURNAL
ENGINEERING TECHNOLOGY
Figure 7. Assembly Process Flow.
JULy-AUGUST 1994
5-61
ENGINEERING TECHNOLOGY
Thermal Performance
on the system conditions. (See Fig-
Both model and analytical data
shows that the heat slug package
can meet the design constraint of
dissipating 2.4 W in either the
chip-up or chip-down configurations. The chip-down style was
chosen due to its thermal efficiency when airflow is present in
the system. When considering if
the required heat could be dissipated using a thin package, different thicknesses of heat slugs were
modeled. The results showed that
a heat slug as thin as 0.015" could
be used without sacrificing the
desired performance (Table lID.
Actual power diSSipation of all
packages is dependent on the thermal impedance of the package, the
system ambient temperature, the
maximum allowable junction temperature and the available airflow.
The TQFP TEP package dissipates
between 1 and 5 watts, depending
ure 8 and Figure 9.)
The slug provides a spreading
effect for the heat generated by the
chip. Since the chip is attached
directly to the heat slug, the die
attach material is the only therrri.al
resistance interface between the
chip and the slug. This interface is
relatively short, typically 0.001"
and the heat is easily drawn away
from the chip. Conventional plastic packages. receive some heat
spreading effects from the die
attach pad, but the heat still has to
pass through a layer of plastic
molding compound before reaching the ambient air. Compared to
the conventional plastic package
of the same outline, the heat slug
package thermal impedance is
30% lower (Figure 10).
~sseDlblyProcess
DevelopDlent
Design for manufacturability concepts were used to meet six sigma
process capability in every assem-
Table III. Maximum Power Dissipation of 1.4mm Heat Slug Package (Watts)
- Thermal Model Data. (Assumes 25°C Ambient Temperature and 150°C
Maximum Junction Temperature.)
1.4mm Heat Slug
Power Analysis (100/120 Pin)
50
5
49.8
4.5
45
I'"
.....
25°CAMB
A 35°CAMB
o 45°CAMB
.55°CAMB
6. 65°CAMB
Figure 8. Power Dissipation at Scheduled Ambient Temperatures.
TI TECHNICAL JOURNAL
5-62
ENGINEERING TECHNOLOGY
1.4mm Heat Slug
Power Analysis (100/120 Pin)
50
5.5
49.8
5
45
~
~
4.5
4
40
3.5
35
3
.~
(!>
2.5
30
2.5
2.1
1.7 n--_ _ _ _
==~~~~~~-fr9-2":~
25
2
__
~~1J
1.3 . .
0.9 fr
"iii
~
~
D..
1.5
24.2
---ht"'c.r
20
0.5
oLFM
100 LFM
500 LFM
250 LFM
Airflow (LFM)
• Sja
<>
150°C Max Tj
.. 130°C Max Tj
o
•
90°C MaxTj
6. 70°C Max Tj
110°C Max Tj
Figure 9. Power Dissipation at Selected Maximum Junction Temperatures.
Actual K-Factor
8or-----------------------------------------,
72.7
70
=- 60
~
E 50
40
30
2o~----~--------------~------------~~--~
o
250
Airflow (LFM)
• Conventional 1.4mm
o
1.4mm Heat Slug
Figure 10. Thermal Impedance of Conventional vs. Heat Slug Packages.
JULy-AUGUST
bly process operation. Stress reduction and good thermal dissipation
required a low stress die attach
material with minimum voiding,
thick bond line (>0.001") and excellent adhesion characteristics. Several die attach materials, dispensing needles and parameters were
evaluated to find the best combination. The evaluation efforts combined with the improved adhesion
characteristics of the heat slug surface treatment yielded a substantial
improvement in die shear strength
compared with conventional Pd
plated lead frames, as Table IV
shows.
Optimum epoxy application
parameters and customized dispenser needles designs allowed us
to meet 100% epoxy coverage, less
than 10% epoxy voiding and a
minimum bond line thickness of
0.001" (Figure 11).
1994
5-63
ENGINEERING TECHNOLOGY
Table IV. Average Die Shear Force in Kg.
DIe Pad
Die . . .
Coating
Fcirce
standard .......
Pd Plated Die Pad
13.0
2.7
41.2
8.6
Heal Slug wIIh Surfaoe
treatment
DIe . . .
precise dam bar removal tooling
was required due to the O.4-mm
outer lead pitch. A "cam form"
process was used to form leads,
preventing damage to the preplated 5-mil-thick leads. Optical
lead inspection was employed to
confirm outgoing coplanarity and
lead true position.
Package Reliability
One of the design constraints for
developing a thin thermallyenhanced package was that its reliability meet the current reliability
level of conventional plastic packages. The heat slug package was
tested using the same qualification
requirements for all plastic packages. All electrical tests were preconditioned using 168 hours exposure at 85°C/60%RH followed by
two reflow operations. Table VI
Figure 11. Epoxy Dispensing Pattern.
The heat slug leadframe subassembly required substantial
wire bond process development.
Heater block design was critical
due to the presence of adhesive
film in the bonding areas. The fine
pitch leadframe fingers and the
chip bonding pads required a new
capillary design and utilization of
advanced wire looping techniques
(Figure 12).
Mold compounds were evaluated for wire sweep, voiding and
moldability (Table V). The highadhesion properties of the mold
compound candidates required a
unique mold die design, to assist
in mold release. Both bond process and mold process optimization were used to minimize wire
deflection during the encapsulation process (Figure 13).
Devices are symbolized using a
proprietary laser process. Ultra
Figure 12. Wire Looping -120 TQFP.
---------------------------------------------TI TECHNICAL JOURNAL
5-64
ENGINEERING TECHNOLOGY
Table V. Mold Compound Evaluations 100 Pin TQFP Packages.)
.... -CompoI.m4I
Cempound
A
'~
1.57
~.(m!n)
~~)
7.02
:. 81U'.~J'
1.88
Wire Sweep. ("Wire Sweep % Deflection for Various Mold Compounds on
,'I1"\d
..
~
c.mpDIIiId
1.4
1.9
D
..
~ r .. 5.11r .
;
.... , .....
un
I.
8
1.16
COmpOunct
~
COIIIpDUIId
F
1.4
1.11
1.9
•
S.
1m
.,
'~!16
1.07
•
""
6.9'4
.-'.'
1.'.
ping and storage using a "dry"
packaging scheme. This package
provides an excellent opportunity
to eliminate the need for desiccated
packaging and special handling in
a customer's factory.
Conclusions
Figure 13. Molded Wires.
describes the results of this reliability qualification testing.
The moisture sensitivity tests
were performed per the proposed
IPC-SM-786A Levell and Level 2
conditions, 168 hours of 85 °C/85
%RH and 168 hours of 85 °C/60
%RH, respectively. The heat slug
package passed both Levelland
Level 2 moisture sensitivity tests,
showing no degradation in delamination nor internal cracking after
stressing. This is superior performance to a conventional plastic
JULy-AUGUST
TQFP package. The photos in Figure 14 show a typical crack in a
TQFP package after Levell testing
and the heat slug package after
identical stress conditions (Figure
14).
Level 1 conditions equate to an
unlimited exposure time at factory
floor conditions of 30°C/ 60%RH
and no special "dry" packaging.
The Level 2 conditions equate to an
exposure time of one year at
30°C/60%RH, providing the
devices are protected during ship-
A thermally-enhanced plastic IC
package has been developed by a
cross-functional team from engineering and manufacturing to
meet the constraints of space and
power required by the customer.
The package was developed with a
primary goal of efficiency of manufacturing and compatibility with
current plastic package assembly
equipment and processes.
The TQFP TEP uses a leadframe subassembly, with a heat
slug attached by two-sided adhesive film. This leadframe is processed through conventional
assembly processes and equipment, with a change of orientation
after the mold process. The proprietary surface treatment of the copper heat slug provides a tenfold
improvement in mold compound
adhesion and a threefold improvement in die attach adhesion compared to conventional leadframe
surface finishes. The slug also provides stability to the thin package,
preventing warpage. This package
represents a substantial step forward in the quest for plastic IC
1994
5-65
ENGINEERING TECHNOLOGY
packages that can meet the everincreasing power and board space
requirements of the electronics
industry.
Acknowledgments
Typical Crack in TQFP Package
Resulting from "Popcorn Effect"
The authors would like to express
their sincere appreciation to the
following people, without whose
contributions the development. of
this package would not have been
possible: Bobby O'Donley, Mario
Magana, John Tellkamp, Pedro
Cabezas, Mike Pomeroy, John
Wiley, RIch Brook, Ray Purdom,
TQFP TEP Package
with No Cracks
Figure 14. Cross Sections of TQFP Packages After 168 Hours 85°C/85%RH.
Table VI. 120 Pin TQFP TEP Environmental Test Data.
,
(.,"
.
."
"'-'
... ~~
...
'
..
'
J~., .
. ,.
.,~
·· . Ws··
.
'
.....
,.
/~'
':
.,""
.... " .
':' '.".
....
" ,.."".:,;..
,'.
.
.
,,'
..
,.'<
.;
.
,0
. .:
"':':"''':~:''
,
..
,'
'
.
MO
ONO
ONO
TI TECHNICAL JOURNAL
5-66
ENGINEERING TECHNOLOGY
Terrill Sallee, Jim Fielding, Tomas
Luna, Brenda Gogue, Steve
Groothius, Dick Shaw, Jim Sisco,
Jay Alexander, Archie Sutton,
Herb Wyman and others who may
have been omitted.
Edgar R. Zuniga
Edgar Zuniga has been involved with
the development of new packages
since 1989, first as part of the group
that developed the 48- and 56-pin
SSOP packages. For the last two years
he has served as the team leader in the
development of the 100- and 120-pin
TQFP TEP packages. Before this,
Edgar spent two years as engineering
section head manager for the assembly
operations in the Flexible Assembly
Module in Sherman (FAM) and one
year as assembly process engineer.
He joined TI in 1975 at the TI plant
in EI Salvador as a process engineer in
the assembly operation. He transferred to Sherman in 1986.
Edgar received a B. S. in electrical
engineering in 1977 from the Catholic
University, San Salvador, EI Salvador,
and an M. S. in engineering science
from the University of Texas at Dallas
in 1993.
JULy-AUGUST
LarryNye
Larry Nye is currently a member of
the package development team within
the Advanced System Logic Organization. Since 1983, Larry has been heavily involved in die attach and bonding
process development activities including programs such as palladium
bonding process development, copper
wire bonding, low temperature bonding, hermetic chip, bonds over active
circuits (BOAC), rapid cure process
(RCP), and others.
Besides his development responsibilities, Larry serves as the ASL representative on the Worldwide Mount
Commodity Team, the Worldwide
Gold Wire Commodity Team and the
Worldwide Bond Process Standardization Team. Additional responsibilities include thermal and stress modeling activities along with material characterization and qualification. He
joined TI in 1983.
Larry has presented papers twice
at the international electronic packaging conference on thermal analysis of
semiconductor packages. He has written other papers on palladium bonding and thermal modeling of semiconductor packages. In addition, Larry
has served as a co-author on papers
dealing with thermal modeling, experimental design, semiconductor package design, and bonds over active circuits (BOAC). He currently has two
patents pending in the U.S. patent
office.
Mary Helmick
Mary Helmick is part of the package
development group for the Advanced
System Logic Department in Sherman.
Mary joined TI in 1990 as part of the
48- and 56-pin SSOP package development team in the ASL Test/Finish
area (formerly FAM). Since 1991 she
has been part of ASL packaging engineering, working on the 100/120 pin
Heat Slug Package Development
Team.
She received her bachelor of science in mechanical engineering from
Purdue University in 1986 and her
master's degree in computer integrated design and manufacturing
from George Washington University
0
in 1989.
1994
5-67
5-68
FIFO Surface-Mount Packages
for PCMCIA Applications
Tom Jackson
Advanced System Logic - Semiconductor Group
~TEXAS
INSTRUMENTS
SDMA001A
5-69
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest version
of relevant information to verify, before placing orders, that the information being relied on is current.
TI warrants performance of Its semiconductor products and related software to the specifications
applicableatthetime of sale in accordance with Tl's Standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of
all parameters of each device is not necessarily performed, except.those mandated by government
requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury,
or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR
SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use
ofTl products in such applications requires the written approval of an appropriate TI officer. Questions
concerning potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
Infringement of patents or services described herein. Nor does TI warrant or represent that any license,
either express or implied, Is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process In which
such semiconductor products or services might be or are used.
Copyright @ 1996, Texas Instruments Incorporated
5-70
Contents
Title
Page
Introduction ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.•• 5-73
PCMCIA •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••.••••••••••• 5-73
Packaging •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••••••• 5-74
Power ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••••••••••.••••• 5-78
Thermal Resistance ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••. 5-79
Conclusion •••••••••••••••••••••••••••••••••••'........................................... 5-80
List of Dlustrations
Figure
1
2
3
4
5
6
7
8
9
10
Title
PCMCIACardDimensions ...........................................................
Portable Computers Supporting PCMCIA Cards ....................................... : ..
FIFO Package Dimensions ...........................................................
Area Versus Package Option ..........................................................
TQFP Package Height ...............................................................
Type II PCMCIA Package Height Versus Dual Package Solutions ............................
Typical Package Height Versus Height Variance ..........................................
Active ICC Versus Frequency .........................................................
Multiple 9-Bit Solution Versus Single 36-Bit FIFO ........................................
RaJA for FIFO Packages in Still Air ...................................................
Page
5-73
5-74
5-75
5-76
5-76
5 -77
5 -77
5 -78
5-79
5 -80
5-71
5-72
Introduction
As today's applications become more complex and integrated, there is a continuing need to reduce board space without
sacrificing functionality. This need has never been greater than for Personal Computer Memory Card International
Association (PCMCIA) cards. The appeal for PC card adapters in large area network (LAN) is due to the small form
factor and performance. PCMCIA card designers face the challenge of reducing current half-size boards (typically
4.5 in x 8 in) such as those used in present deslaop systems, to the size of a credit card.
With the emergence of notebook computers, personal data assistants (PDAs), and wireless communications, designers
are turning to PCMCIA cards to meet the growing demand for more flexibility. This trend has driven the chip-set
manufacturers to reduce the number of add-on features normally designed into desktop computers to fit the·board
confines of portable systems. PCMCIA cards provide an alternative: standard add-on features in a miniature-portable
format. Until the introduction and standardization ofPCMCIA cards, portable systems were left virtually unconnected
to other systems and peripherals. Many of the PCMCIA designs provide the needed interconnectedness between systems
by performing inputloutput (1/0) data functions. Typical 110 adapters found today are EtherNet, faxes, SCSI, and
modems, to name a few.
As bus widths and data speeds increase, so does the chance of data bottlenecks and latency. Specialty memories such
as FIFOs are required for either rate matching or clock partitioning from data buses and processors. Until now, many
designers either had to compromise performance or increase device count due to the lack ofPCMCIA-compliant FIFO
packaging. Texas Instruments (TI) has met the challenge of reduced board area and increased integration with their
advanced FIFO memories. TI offers 9-, 18-, and 36-bit high-performance FIFO memories in the PCMCIA-compatible
thin quad flat package (TQFP).
PCMCIA
PCMCIA was founded in 1989 to·define and set PC-card standards. In today's market, there are three widely accepted
standards: Type I, ratified in June 1990; Type II, ratified in September 1991; and Type m, which is pending. PCMCIA
cards all share a common length and width, differing only in their height (see Figure 1).
IOII~I----- 85.6mm ----~~I
T
54.0mm
PCMCIA
I!:::::=:====::!..L...J
_1_
H&19ht:J.
~--------------------"'L::!
-
T
Figure 1. PCMCIA Card Dimensions
Due to the increased popularity ofPCs (Le., laptops, notebooks, andPDAs), a demand for the same functionality as found
in larger PC counterparts has arisen. To keep pace with the growing market demand, portable-computer manufacturers
have begun to support PCMCIA card ports on nearly all new designs (see Figure 2).
5-73
80,000
70,000
6'
co
~
.!S.
CD
60,000
E
40,000
i
30,000
::I
II
50,000
PCMCIA
Supported
PCMCIA
Unsupported
20,000
10,000
0
1992
1993
1994
1995
1996
1997
t Gartner Group
Figure 2. Portable Computers Supporting PCMCIA Cardst
In the past, PCMCIA cards were seen as a way to easily upgrade system memory without adding storage overhead to
, the already compact chip sets. Today, PCs are replacing hardwired-desktop networked systems as the main computing
unit. The need to provide for system interconnection and data communications has targeted new PCMCIA designs for
LAN, fax, and modem-adapter cards. These applications typically are found in Type II PCMClA cards. Other designs
such as subminiature disk drives and wireless radio frequency communication adapters typically found in Type ill
PCMClA cards (see Table 1).
Table 1. PCMCIA Card Applications
TYPE
HEIGHT
IPC
3.3mm
Memory devices: Flash, DRAM, OTP, and high·speed add-ons
APPLICATION
II PC
Smm
110 devices: Fax, modems, and LAN adapters
III PC
10.Smm
Wireless devices: RF-communications devices and submini disk drives
Type I cards are focused mainly for plug-in memory. Type II and Type ill cards are gaining ground in many new
applications. Type II cards are used mainly for II 0 applications such as those listed in Table 1. The growing acceptance
of PCMClA cards for II 0 interface has caused manufacturers ofDSPs, CODECs, bus-interface devices, and ASlCs to
begin producing PCMCIA-compliant devices. For example, TI's Rio Grande chip set for PCl features ports to support
two PCMClA cards.
There is a demand for these features in a portable package the size of a PCMCIA card and an even greater demand for
devices in PCMClA-compatible packages. These devices must provide the needed features, consume less power, and
require less critical board space.
Packaging
The primary obstacle facing many designers is obtaining packages small enough to incorporate into their PCMCIA
designs. To shrink a current adapter-card design and have it fit into the small form factor of a PCMCIA card requires
all components, not just the printed circuit board, to be reduced in size. To ensure functionality is not lost, many designers
implement multilayered boards to help increase integration. Some boards have ten layers and measure only 0.03 in thick.
Multilayered boards are only part of the solution; both active and passive components must be dual-side mounted for
maximum chip count and overall integration. To ensure the entire board fits into a PCMClA form requires specialized
packaging from the device manufacturers. Since FIFOs playa key role in the functionality of many of these designs,
TI has utilized board-space-saving TQFP packaging across 9-, 18-, and 36-bit FIFO product lines (see Figure 3).
5-74
12o-Pln TQFP (PCB) 36 Bit
10o-Pln TQFP (PZ) 18 Bit
'~
0,40
t
14,0
Area of
Package
224mm2
Area of
Package
224mm2
0
0
~16'O
Package
Height
Typical
14,0
~16'O
1,5
+
J GBUUUIIIUUUUHIUUUUUU'uUdt.
f
Package
Height
Typical
1,5
t
.rGAAIlPIlPWIIIIIIlIlUUUWWh.
f
SO-Pin TQFP (PN) 18 Bit
0,50
Area of
Package
168 mm2
1,5
Package
Height
Typical
J~
Package
Height
Typical
n
Area of
Package
120mm2
10,0
~,.'~
~
f
64-Pln TQFP (PAG) 9 Bit
64-Pln TQFP (PM) 9 Bit
Area of
Package
120mm2
t
1,5
t
f
Package
Height
Typical
n
10,0
~,.'~
~
1,1
t
f
NOTE: Dimensions are in millimeters.
Figure 3. FIFO Package Dimensions
5-75
TQFP packaging not only reduces critical board area and height; it also offers increased performance and reliability due
to TI's advanced CMOS and BiCMOS processing. There are a number of players in the FIFO market today that employ
either plastic-leaded chip camer (FLCC) or leadless chip camer (LCC) packages as the smallest option for any
organization. Due to the larger size of these older packages, many designers that otherwise would have chosen a FIFO
for a design have been forced to design without FIFOs in their PCMCIA designs, incurring higher integration cost and
increased board space. By comparing total package area by FIFO organization, it is obvious that TI offers the smallest
package option for each of the popular FIFO organizations (see Figure 4).
1,000
898.2
..
~,
!
800
r
600
r
784.56
638.67
400
,
,
o n,
9Blt
•
18Blt
38Blf
mm
407.75
200 144
o
'KK
256
256
198
~t
....
~
%
"
'"
,
,
84 TQFP
32 PLCC
52 PLCC
88 PGA
120 TQFP
32 LCC
80 TQFP
88 PLCC
100 TQFP
132 PQFP
Figure 4. Area Versus Package Option
The board-space savings are even more dramatic when considering cascaded multiple 9-bit FIFOs in 32-pin PLCC
packages to construct an 18- or 36-bit FIFO solution. Tl's 9-, 18-, and 36-bit FIFOs offered in the TQFP packages not
only eliminate the need to cascade devices, but reduce board space. An example of this board-space savings is the
conventionall8-bit package, the 68-pin PLCC. Tl's 18-bit FIFOs in the 80-pin TQFP reduce board space by 80%. The
68-pin PLCC has a nominal package height of 4.38 mm versus 1.5 mm for all of Tl's TQFP packages. This is better
shown by Figure 5 , which illustrates two TQFP packages with a nominal height of 3 mm. An additional 0.5 mm for
PC board thickness makes the total height 3.5 mm. This is not only 20% thinner than PLCC, but also meets PCMCIA
TYPeIlspecDication.
6-mm Type II PCMCIA
Figure 5. TQFP Package Height
Figure 6 shows a comparison of FIFO surface-mount packages versus the PCMCIA TYPe II specification. Packages
below the reference line meet the TYPe II specDications. Those packages above the reference line exceed the maximum
height requirements. All values are calculated based on double-side mounting (two packages) and do not include the
PC board thickness (nominally 0.5 mm). Only the TQFP and 9-bit 32 LCC packages pass the TYPe II PCMCIA
specifications.
5-76
0
-
D
8
•
18Blt
-
•
36 Bit
6
Type II
----------- ----- -- --
r-------
9Blt
PCMCIA
. Maximum
Height
Specification
-
4
2
I
0
I
I
I
I
64 TQFP (PAG)
32 LCC
80 TQFP
68 PLCC
100 TQFP
132 PQFP
64TQFP (PM)
32 PLCC
52 PLCC
68 PGA
120 TQFP
Figure 6. Type II PCMCIA Package Height Versus Dual Package Solutlonst
t Board thickness is not included.
Although the LCC package may physically fit the requirements for PCMCIA cards, it does not permit optimum system
design, since so much of the board area is occupied by one device. TI FIFOs available in TQFP packages allow a designer
to choose the architecture and features that best meet the design criteria and dramatically reduce critical board space.
Another critical point to consider in PCMCIA design is package dimensioning and tolerances. As previously stated, the
nominal values specified for a package may appear to meet PCMCIA card specification. However, due to different
techniques involved in the mold processes of different packages, designers must carefully review all specifications given
in the mechanical drawings for each package. In the case of the 32-pin LCC, the height tolerance varies greatly from
a minimum of 1.27 mm to a maximum of 2.2 mm, a variance of 57% (see Figure 7).
6
5
E
E
4
+++
+
I
:c
f
iii
.5
E
3
I
2
T~~~~~~
0
z
o
I
I
I
I
I
I
I
I
I
I
I
I
68 PLCC
132 PQFP
32 PLCC 64 TQFP (18 Bit) 80 TQFP
120 TQFP
100 TQFP 64 TQFP (PAG)
52 PLCC
68 PGA
32 LCC
64 TQFP (PM)
Figure 7. Typical Package Height Versus Height Variance
5-77
Figure 7 shows thatTI's TQFP packages hold the tightest mechanical tolerances for all dimensions, ensuring the package
clearance desired never varies by more than 0.05 mm from the nominal value. Tight control on package height is critical
because clearance of a full circuit board is very tight to begin with, without factoring in variations in circuit board, solder
thickness, and the PCMCIA card. TI's control of the TQFP package dimensions allows mechanical conformity without
package inspection and sorting..
Power
The PCMCIA card specifications have forced all aspects of devices to be reduced in size. Equal to the need for smaller
packaging is the need for reduced device power consumption. Since PCMCIA cards are closed systems, cooling fans
are size restricted. Designers must carefully review device power consumption because PCMCIA cards are used
primarily with portable systems that are battery powered. Reducing power consumption is especially critical to
increased system battery life.
FIFO power consumption depends on several factors. Most of the power consumed by a FIFO is used in charging the
CMOS circuit while performing reads and writes, sometimes referred to as duty cycle. The speed at which a FIFO
operates affects the amount of power consumed. As speed increases, so does the frequency of reads and writes. To assist
designers in calculating power, TI provides an ICC versus frequency plot for each FIFO in the Sept. 1994
High-Performance FIFO Memories data book (literature number SCAD003B). Because the duty cycle and clock
frequency at which a FIFO is operated depend on the design, TI has implemented a unique circuit feature on its advanced
FIFOs, i.e., dynamic-sense amplifiers. Dynamic-sense amplifiers draw power only during a read or write operation;
otherwise, they are idle, drawing less than 400 ~. Conventional FlFOs implement static-sense amplifiers that draw
power even when the device is idle (approximately 50 rnA). TI's dynamic-sense amplifiers are designed to optimize
maximum performance without any degradation of propagation delay times. Figure 8 is a comparison of TI's 9-, 18-,
and 36-bit clocked FlFOs with several conventional synchronous 9-bit FIFOs. The synchronous 9-bit FlFOs all draw
more than 50 ~ when idle. As system speed increases, so does the amount of power consumed. As speeds approach
60 MHz, the 9-bit synchronous FIFO draws more power than TI's clocked 36-bit FlFOs.
~Or-----------------------------------------------~
____ Synchronous 1/2/4K x 9
......... ACT7807 2K x 9
""*- ACT7803512x18
...... ABT7819512x18x2
ACT3632512x36x2
",200
E
-+-
I
i..
a
150
~
a.
a.
~
100
I
~
50
O~------~------~------~------~------~------J
o
10
20
30
40
f - Frequency - MHz
Figure 8. Active ICC Versus Frequency
5-78
50
60
Using the following equation, an accurate power calculation can be made for any FIFO device.
PT - Vee x [lee + (N x Alee x dc)] + :E(Cpd x Vee2 x fi) + :E(CL x Vee2 x fo)
Where:
lee - power-down supply current maximum
N
- number of inputs driven by a TIL device
Alee - increase in supply current
de
Cpd
CL
fi
fo
duty cycle of inputs at a TIL high level of 3.4 V
power dissipation capacitance
output capacitance load
data input frequency
data output frequency
-
The power consumption of a single 9-bit device is an important consideration, since many designs require 18- or 36-bit
FIFO solutions. Since power consumption is primarily a factor of the number of outputs switching, reducing power
consumption with wider-word-width FIFOs is critical [for example, the total power consumption of a lK x 36 FIFO
when constructed by cascading four lK x 9 FIFOs (see Figure 9)]. TI's single-chip solution, the SN74ACT3641, not
only saves 65% board space, but reduces power consumption by 78% when operating at 60 MHz.
1,000
Synchronous ACT3641
___ 1/214Kx9
31:
........ ACT7807 2Kx9
800
E
I
c
0
i
800
J
400
c
I
lII.
200
0
0
10
20
30
40
50
60
f - Frequency - MHz
Figure 9. Multiple 9·Blt Solution Versus Single 36-Blt FIFO
Thermal Resistance
As with any small package, thermal considerations must be taken into account Any heat generated by a device must
be dissipated to ensure proper operation. The heat dissipation of a package is measured in terms of theI1Il!ll resistance
(RS). RSJA is defmed as the thermal resistance from the die junction to ambient air. Figure 10 shows a listing of all TI's
surface-mount packages and their associated RaJA values. The listed values are measured in still air, which is a better
representation of the true operating conditions of a FIFO in a PCMCIA card. The 120-pin TQFP is an example of TI's
new thermally enhanced packaging (TEP) technology. The 120-pin TQFP has a heat spreader mounted to the top of the
package and the die is mounted underneath in a dead-bug fashion. The 120-pin TQFP has the same RaJA characteristics
as the larger 132-pin PQFP and is 67% smaller. The heat dissipation similarities between the two packages are due to
the addition of a heat spreader built into the 120-pin TQFP.
5-79
3000
- - - 24-Pln SOIC (OW)
--.Ar- 28-Pln SOIC (OW)
....... 44-Pln PLCC (FN)
58-Pin SSOP (OL)
64-Pln TQFP (PAG)
-+- 64-Pln TQFP (PM)
-III- 68-Pln PLCC (FN)
-b- SO-Pin PQFP (PH)
-0- SO-Pin TQFP (PN)
--t- 100-Pln TQFP (PZ)
- . - 120-Pln TQFP (PCB)
-a- 132-Pin PQFP (PQ)
-<>-+-
2500
~I
c
0
i
j
2000
c
I
E
::I
E
'R
1\1
:Ii
1500
I
~
1000
500
25
35
30
40
45
50
55
60
65
70
75
80
85
90
TA - Ambient Temperature - ·C
Figure 10. RSJA for FIFO Packages in Still Air
The RSJA characteristics in Figure 10 are measured in still air (no laminar flow), which best represents the conditions
of a closed PCMCIA card. The RaJA values are calculated using the following equation:
Ra1A
=
T1
-
TA
power
Effective heat dissipation is needed as power increases to reduce junction temperature of the die. The increased
temperature can cause drift and even device failure, which dramatically decreases mean time between failure (MTBF).
TI has improved device reliability by combining decreased power and effective packaging.
Conclusion
As the demand forPCMCIA card continues, so does the demand for lower power and more space-saving packages. TI
has met both demands ·with TQFP packages for their advanced CMOS and BiCMOS FIFOs. The TQFP package
dramatically reduces board space over conventional packaging and eliminates the need to cascade multiple FIFOs to
create 18- and 36-bit FIFO solutions. The implementation of dynamic-sense amplifiers on all advanced FIFOs reduces
power consumption and; therefore, improves system reliability and provides longer battery life for portable systems.
5-80
Package Outlines
and Thermal Data
Page
Introduction ......................................................................
Plastic Dual-In-Line Package (PDIP)
N/R-PDIP-T16 (16-pin DIP) .................................................
N/R-PDIP-T20 (2o-pin DIP) .................................................
N/R-PDIP-T28 (28-pin DIP-600 mil) ..........................................
N/R-PDIP-T40 (40-pin DIP) .................................................
NP/R-PDIP-T28 (28-pin DIP-300 mil) .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
NT/R-PDIP-T24 (24-pin DIP) ................................................
Plastic J-Leaded Chip Carrier (PQCC)
FN/S-PQCC-J20 (2o-pin PLCC)
FN/S-PQCC-J28 (28-pin PLCC)
FN/8-PQCC-J44 (44-pin PLCC)
FN/S-PQCC-J68 (68-pin PLCC)
RJ/R-PQCC-J32 (32-pin PLCC)
5-83
5-84
5-86
5-88
5-90
5-92
5-94
............................................. 5-96
............................................. 5-98
............................................ 5-100
............................................ 5-102
............................................ 5-104
Plastic Wide-Body Small-Outline Package (PDSO)
DW/R-PDSO-G16 (16-pin SOIC) ............................................
DW/R-PDSO-G20 (20-pin SOIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DW/R-PDSO-G24 (24-pin SOIC) ...................................'. . . . . . . ..
DW/R-PDSO-G28 (28-pin SOIC) ............................................
5-106
5-108
5-110
5-112
Plastic Small-Outline Package (PDSO)
DV/R-PDSO-G28 (28-pin SOIC) ............................................ 5-114
Plastic Shrink Small-Outline Package (PDSO)
DUR-PDSO-G56 (56-pin SSOP) ........................................... 5-116
Plastic Quad Flatpack (PQFP)
PAG/S-PQFP-G64 (64-pin TQFP) . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PCB/S-PQFP-G120 (120-pin TQFP) ........................................
PH/R-PQFP-G80 (80-pin PQFP) ............................................
PM/S-PQFP-G64 (64-pin TQFP) ............................................
PN/S-PQFP-G80 (80-pin TQFP) ............................................
PQ/S-PQFP-G132 (132-pin PQFP) .........................................
PZ/S-PQFP-G100 (100-pin TQFP) ..........................................
5-118
5-120
5-122
5-124
5-126
5-128
5-130
5-81
5-82
MECHANICAL AND THERMAL DATA
Introduction
The remainder of this section contains mechanical and thermal data for each package offered for TI's FIFOs.
The mechanical data consists of drawings of each package annotated with critical dimensions. These drawings
typically include the following dimensions: lead pitch (tip to tip); body width and length; shoulder-to-shoulder insertion
width; lead width, thickness, and angles; and package maximum height and stand-off clearances from seating plane
to bottom of the package. For packages designed in English units, inch dimensions are shown first followed by
millimeter dimensions in parentheses. A period is used as the English units decimal point and a comma as the metric
units decimal point. The official JEDEC descriptor is used to identify each package type.
The thermal data consists of the thermal resistances from junction to ambient (ElJA) measured in either a
one-cubic-foot box or in a wind tunnel under varying air velocities. Values of thermal resistance from junction case
(ElJC) also are included for some package types. Derating curves of maximum power dissipation versus ambient
temperature for varying air flows are provided for each package.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
MECHANICAL AND THERMAL DATA
N/R·PDIP·1**
PLASTIC DUAL·IN·LINE PACKAGE
16 PIN SHOWN
C'~
T
0.260 (6,60)
0.240 (6,10)
~~~~~~~~
'8
0.070 (1,778) MAX
0.035 (0,89) MAX
JL -./ I."
0.014 (0,356)
0.010 (0,254)
0.100 (2,54)TVP
(see Note C)
J
0.125 (3,18) MIN
II
-
~6)'
0.010 (0,254)
\.- 0°-15°
4040049/8-10/94
NOTES: A. All linear dimensions 'are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Each lead centerline is located within 0.010 (0.254) of its true longitudinal position.
~1ExAs
5-84
INSTRUMENTS
'
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
i6-Pln DIP (N) Package Power Dissipation Derating In Stili Air
2000
1800
~I
c:
i
~..
I
E
;,
E
"5C
III
1600
1400
1200
1000
800
800
:&
400
200
0
25
30
35
45
40
60
80
55
65
70
75
80
65
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
("C/W)
9 JUNCTION TO CASE
0
0
100
250
500
1 ft 3 box
67
Wind tunnel
-
NlA
NlA
NlA
NlA
NlA
NlA
26
NlA
Wind tunnel
Wind tunnel
Wind tunnel
N/A
t Mounted on pnnted-clrcUit board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 665303 • DAu.AS. TEXAS 75265
("C/W)
90
MECHANICAL AND THERMAL DATA
N/R·PDlp·T**
PLASTIC DUAL·IN·L1NE PACKAGE
16PINSHOWN
CA~
T
0.260 (6,60)
0.240 (6,10)
~~~~~~~~
8
0.070 (1,778) MAX
~ 0.310(7,87)
0.035 (0,89) MAX
JL - .\ I.-
Ir--ll ,....
0.100 (2,54)TVP
(see Note C)
0.125 (3,18) MIN
0.014 (0,356)
0.010 (0,254)
j ll
_ \.~6)
V.."
0°_15°
0.010 (0,254)
4040049/8-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Each lead centerline is located wHhin 0.010 (0.254) of its true longitudinal position.
~TEXAS .
5-86
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
2o-Pln DIP (N) Package Power Dissipation Derating at Varying Air Flows
3000
Oft/min
100ft/min
250ft/min
500ft/min
2800
2600
2400
2200
~
E
2000
I
c
0
1600
'OJ
.!!!
1600
iQ.
..
c
I
1400
E
::I
E
1200
:IE
1000
';
800
600
400
200
0
25
30
35
45
40
60
60
55
65
70
75
60
85
90
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
0
0
100
250
500
N/A
ENVIRONMENT
1 1t3 box
9
JUNCl'lON TO AMBIENT
("C/W)
9
JUNCTION TO CASE
("C/W)
N/A
Wind tunnel
67
90
75
58
48
N/A
N/A
33
Wind tunnel
Wind tunnel
Wind tunnel
NlA
NlA
NlA
N/A
t Mounted on printed-CircUit board
~TEXAS
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-87
MECHANICAL AND THERMAL DATA
N/R·PDlp·T**
PLASTIC DUAL·IN·LINE PACKAGE
24 PIN SHOWN·
r
A ------1-3tJ11
24
0.560 (14,22)
0.520 (13,21)
~'i"i"""'i'T"'i""'i"'i'''i'''''i''i"''i''''''i''i''''~~
12
0.060 (1,52) TYP
0.020 (0,51) MIN -
0.200 (5,08) MAX
UUU~ UUUU~ U~ U~I~~.~~~~~--~-~
JL-.I I.--
Semlng Plane
0.100 (2,54) TYP
0.125 (3,17) MIN
0.021 (0,533)
0.015 (0,381)
JL
0°-15°
0.014 (0,355)
0.008 (0,203)
404OO53IB-10/94
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
:lllExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75266
MECHANICAL AND THERMAL DATA
28-Pln DIP (N) Package Power Dissipation Derating In Stili Air
3000
2800
2800
2400
2200
~I
c
0
:;::
t.
2000
1800
1600
is
;
1400
E
:.
E
1200
~
I
1000
800
600
400
200
0
25
30
45
40
35
50
60
55
65
70
75
60
65
Ambient Temperature _·C
Thermal Resistance (e) Measurementst
AIRFLOW
(ft/mln)
0
0
100
250
500
NlA
ENVIRONMENT
e JUNCTION TO AMBIENT
e JUNCTION TO CASE
1 ft 3 box
53
NlA
Wind tunnel
NlA
Wind tunnel
-
Wind tunnel
-
NlA
Wind tunnel
-
NlA
NlA
N/A
20
(·C/W)
t Mounted on pnnted-cIICUIt board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
(·C/W)
NlA
90
MECHANICAL AND THERMAL DATA
N/R·PDlp·T**
PLASTIC DUAL·IN-LINE PACKAGE
24 PIN SHOWN
A ------1-3+1.1
0.560 (14,22)
0.520 (13,21)
~'i'T""i'T""~~i"""i"i""'TT~~
12
0.060 (1,52) TYP
0.020 (0,51) MIN -
0.200 (5,08) MAX
~IDJ_~;--r-.
UUUUUUUUUUUU7 ' ~~
Jl'
Seating Plane
JL -.J I.--
0.100(2,54)TYP
0.125 (3,17) MIN
0.021 (0,533)
0.015 (0,361)
0°-15°
0.014 (0,355)
0.008 (0,203)
4040053/8-10194
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
~TEXAS
5-90
INSTRUMENTS
POST OFFICE BOX 665303 • DAUAS. TEXAS 752e5
MECHANICAL AND THERMAL DATA
4o-Pln DIP (N) Package Power Dissipation Derating In Stili Air
3000
2800
2600
2400
2200
~
E
2000
I
c
0
i
~
1800
1600
J
1400
=
1200
E
E
I
1000
800
600
400
200
0
25
30
40
35
45
50
60
55
65
70
75
80
65
90
Ambient Temperature _·C
Thermal Resistance (e) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
e JUNCTION TO AMBIENT
rC/W)
e JUNCTION TO CASE
(·C/W)
1 ft 3 box
43
Wind tunnel
0
0
100
250
500
Wind tunnel
-
Wind tunnel
-
Wind tunnel
-
NJA
NJA
NJA
NJA
NJA
NJA
N/A
N/A
12.5
t Mounted on pnnted-clllluit board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-91
MECHANICAL AND THERMAL DATA
NP/R·PDlp·T28
PLASTIC DUAL·IN·LINE PACKAGE
1.375 (34,93)
1.345 (34,16)
0.295 (7,49)
0.270 (6,68)
~~~~~~~~
14
0.030 (0,76)
0.015 (0,38)
0.180 (4,57)
0.145 (3,68)
Seating Plane
I
Jl
0.110 (2,79)
~ 0.090 (2,29)
0·_15·
0.015 (0,38)
0.008 (0,20)
404007518-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimemsions do not include mold flash or protrusion.
~1ExAs
5-92
I
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
28-Pln DIP (NP) Package Power Dissipation Derating at Varying Air Flows
5000r-------------------------------------~-------------------,
Oftlmln
4500
~I
_. -
4000
3500 __
c
o
J
J
E
:::I
E
I
200 ft/mln
400 ftlmln
I
- . __
r-
3000
2500
2000~
~
-- --
.--.--.
_
--.--.--- --.- -- ----.-_
_
• __ •
--
1500
- - . __
.
~
-......;;
-
1000
500
__~~___l~~I~~L___~~__~I~I__~I___~I__~I~I__~
O~~-L
~
~
~
~
40
~
~
~
~
ro
~
~
~
~
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
rC/W)
9 JUNCTION TO CASE
(·C/W)
0
1 1t3 box
-
0
Wind tunnel
63.5
200
Wind tunnel
43
400
Wind tunnel
36.5
NlA
NlA
NlA
NlA
NlA
-
N/A
NlA
t Mounted on pnnted-clrcult board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
5-93
MECHANICAL AND THERMAL DATA
NT/R-PDIP-T**
PLASTIC DUAL-IN-LiNE PACKAGE
24 PIN SHOWN
A-~~I
13
T
0.280 (7,11)
0.250 (6,35)
~~~~~~~~~~~~
12
0.200 (5,06) MAX
0.020 (0,51) MIN
Seating Piline
H
0.100 (2,54) 1
JL
.
0.125 (3,18) MAX
~:~~! ~~::: r-I."""I0-.0-10-('-O,25)=--;;:@:-11
Jl
0°_15°
~
0.010 (0,254) NOM
4040050/B-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
~1ExAs
5-94
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
2S-Pln DIP (NT) Package Power Dissipation Derating at Varying Air Flows
3000
Oft/mln
2800
2600
-
2200
c
0
'ia.
~
I
:.
E
::I
E
2000
1800
1600
1400
500ft/mln
..............
....
"".." .."..
.."..
as
..............
................
............ ....................
............................
............................
~
................
~
.............. .....................
1200
'5C
~
100 ft/mln
250ft/mln
..............................
2400
~I
--
1000
""....
..............
..............
..............
800
600
400
200
OL---~--~--~--~--~--~--~--~--~--~--~--~~
25
30
35
40
45
50
55
60
65
70
75
80
85
90
Ambient Temperature - ·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
0
0
100
250
500
N/A
9 JUNCTION TO AMBIENT
("C/W)
9 JUNCTION TO CASE
("C/W)
Windlunnel
67
81
72
55
46
NlA
NlA
NlA
NlA
NlA
N/A
N/A
25
ENVIRONMENT
1 ft 3 box
Wind tunnel
Windlunnel
Windlunnel
t Mounted on pnnted-clrcult board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-95
MECHANICAL AND THERMAL DATA
,
PLASTIC J·LEADED CHIP CARRIER
FN/8-PQc6.J**
20 PIN SHOWN
D-----~
01
0.020 (0,51) MIN
0.008 (0,20) NOM
~
4
E
D2/E2
----t
-.1
I
E1
lJ
0.032 (0,81)
0.028 (0,66)
D2/E2
~~
14
9
13
0.013 (0,33)
I'EfH 0.007 (0,18) ® I
DIE
NO. OF
PINS··
MIN
D2/E2
D1/E1
MAX
MIN
MAX
MIN
MAX
4040005/8-10194
NOTES: A. All linear dimensioris are in inches (millimeters);
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
~1ExAs
5-96
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
20-Pln PLCC (FN) Package Power Dissipation Derating at Varying Air Flows
3000
oft/mln
2800
_. -
100ft/mln
250 ft/mln
2600
----
500 ft/mln
2400
2200
~I
2000
i
I
1600
c
1400
~
1200
I
""" ...
...
""" ......
.. ~...
1600
I
E
......
.........
""" ... ... """ ...
"'""" """
--- --- .........~..
~...
--- --- ------ ~... ~ """ ......
------ ------ ~ ..
--- --- --- --- ---.
......
~
........
~
1000
...
800
800
400
200
0
25
Ambient Temperatura _·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
0
9 JUNCTION TO AMBIENT
9 JUNCTION TO CASE
(·C/W)
(·C/W)
1 ft3 box
99
0
Wind tunnel
98.6
86.1
100
Wind tunnel
250
Wind tunnel
70.7
500
Wind tunnel
58.1
NlA
NlA
NlA
NlA
NlA
N/A
23
NlA
NlA
t Mounted on printed-cIICult board
:lflExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5-97
MECHANICAL AND THERMAL DATA
PLASTIC J·LEADED CHIP CARRIER
FN/S·PQCC·J**
20 PIN SHOWN
D-----~
0.008 (0,20) NOM
4
E
0.020 (0,51) MIN
J
I
E1
U
D2/E2
0.032 (0,81)
(0,66)
-*-
~.026
9
D2/E2
t:~~
14
13
0.013 (0,33)
1+1 0•007 (0,18) @I
NO. OF
PINS"
DIE
D1/E1
D2/E2
404000518-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls wHhin JEDEC MS-018
~1ExAs
5-98
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
28-Pln PLCC (FN) Package Power Dissipation Derating at Varying Air Flows
3000
oft/mln
2800
100 ft/mln
2600
500ft/mln
250ft/mln
....
2400
2200
~I
2000
0
1800
i
1600
c
iCI.
...
~...
..............
Q
I
..
'" ................. .............
~
....... .......
..............
1400
IL
:::I
E
E
;c
1200
::Ii!
1000
. ..
...........
...~
~
....... .......
.. .............
...~
~
..............
.. ..
............. ..
...~
~
...........
................. ~
..............
....
...
....... ..............
800
600
400
200
0
25
30
35
40
45
50
55
60
65
70
75
80
85
90
Ambient Temperature - ·C
Thermal Resistance (9) Measurementst
t
AIR FLOW
(ft/mln)
ENVIRONMENT
0
9
JUNCTION TO AMBIENT
e JUNCTION TO CASE
(·C/W)
(·C/W)
1 ft 3 box
95.1
NlA
0
Wind tunnel
87.7
N/A
100
Wind tunnel
69.6
N/A
250
Wind tunnel
61
N/A
500
Wind tunnel
50
N/A
NlA
N/A
N/A
26.7
Mounted on pnnted-clrClult board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-99
MECHANICAL AND THERMAL DATA
FN/8-PQCC-J**
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
O-----~
01
0.008 (0,20) NOM
3
J
I
E
1J
°2 /E2
----t
-.1
0.032 (0,81)
0.026 (0,66)
02 /E2
~
14
13
9
0.013 (0,33)
1-.1 0•007 (0,18) @I
NO. OF
PINS"
OlE
01 /E1
02 /E2
4040005/8-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without noti~.
C. Falls within JEDEC MS-018
~1ExAs
5-100
INSTRUMENTS
POST OFRCE BOX 865303 • DALlAS. TEXAS 75285
MECHANICAL AND THERMAL DATA
44-Pln PLCC (FN) Package Power Dissipation Derating at Varying Air Flows
5000
-------
4500
4000
~I
---- ----------
o
3000
__
2500
----__
............
2000 --.
,.
E
E
I
..
......................
Q
~
250ft/min
500ft/min
350Q _____ _
I:
t
:;
I
Oft/min
100 ft/mln
-
----- __
_
_
1500
- -- - -------. ------
1000
-----
.......... - _ _ _ _ _
- __
_
- - • -..;:
-
500
0~~1-~1-_~1-1~~1-~1-_~1--1~~1-_~1-~1~1-~
~
~
~
~
~
50
~
50
M
ro
n
50
~
00
Ambient Temperatura - ·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
("C/W)
9 JUNCTION TO CASE
("C/W)
0
1 ft 3 box
68.1
N/A
0
Wind tunnel
64.3
N/A
100
Wind tunnel
54.9
N/A
250
Wind tunnel
44.2
N/A
500
Wind tunnel
35.8
N/A
N/A
22
NlA
N/A
t Mounted on pnnteck:lrcuit board
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS. TEXAS 75265
5-101
MECHANICAL AND THERMAL DATA
FN/8-PQCC-J**
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
D-----~
o.ooa (0,20) NOM
~
4
E
I
El
U
0.032 (0,81)
0.026 (0,66)
14
13
9
1-$-10.007 (0,18) ® 1
NO. OF
..
DIE
PINS
4040005/B-10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
~1ExAs
5-102
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
68-Pln PLCC (FN) Package Power Dissipation Derating at Varying Air Flows
5000
Oft/min
4500
200ft/min
400ft/min
400ft/min
4000
~I
c
3500
0
11a.
'iI
is
J
E
::0
E
'5C
::Ii
'"
3000
-- -- -- ---
2500
2000
1500
1000
500
0
25
30
35
40
45
50
60
55
65
70
75
80
85
90
Ambient Temperatura - °C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9
JUNCTION TO AMBIENT
(OC/W)
9
JUNCTION TO CASE
(OC/W)
0
1 1t3 box
51.3
N/A
0
Wind tunnel
51.3
NlA
100
Wind tunnel
43.4
N/A
250
Wind tunnel
32.7
NlA
500
Wind tunnel
27.8
NlA
NlA
N/A
N/A
14.5
t Mounted on pnnted-clrcult board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 76266
5-103
MECHANICAL AND THERMAL DATA
RJ IR·PQCC·J32
PLASTIC J·LEADED CHIP CARRIER
1 4 - - - - - 0.495 (12,57) _ _ _~
0.485 (12,32)
1 4 - - - - 0.453 (11,51) _ _-.!
0.449 (11,40)
0.045 (1,14) x 45°
5
29
0.595 (15,11)
0.565 (14,86)
"--_""--1_' 0.400 (10,16)
0.553 (14,05)
0.549 (13,94)
TYP
L.,---J'"T"""
-.l
0.530 (13,46)
0.490 (12,45)
21
14
20
0.050 (1,27) TYP
0.032 (0,81)
0.026 (0,66)
t
0.021 (0,53)
0.013 (0,33)
0.012 (0,30)
0.008 (0,20)
Seating Plane--
I
J+-
0.300 (7,62)
TYP
1 4 - - - - 0.430 (10,92)
I
---+I
_ _--+I
0.390 (9,91)
4040077/A-10/93
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion.
Formed leads shall be planar with respect to one another within 0.004 (0,10) at the seating plane.
~TEXAS
INSTRUMENTS
5-104
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL AND THERMAL DATA
32·Pin PQCC (RJ) Package Power Dissipation Derating at Varying Air Flows
5000
oft/mln
4500
_. -
200 ft/mln
400 ft/mln
4000
~I
c
- ---.-...-.-.... -....-...
--- -.-.... -....-...
--.....:.-....
- ...::::-..-... .-...
3500
0
:;
..
"0;
is
...
J
E
:::I
E
..
><
3000
2500
2000
1500
::I
1000
500
0
25
30
35
40
45
50
60
55
65
70
75
60
85
90
Ambient Temperature - 'C
Thermal Resistance (9) Measurementst
AIR FLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
('C/W)
9 JUNCTION TO CASE
("C/W)
0
1 ft3box
-
N/A
0
Wind tunnel
50.5
NJA
200
Wind tunnel
40.7
NJA
400
Wind tunnel
36.8
N/A
N/A
N/A
N/A
-
t Mounted on printed-circu~ board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-105
MECHANICAL AND THERMAL DATA
DWIR-PDSO-G**
PLASTIC WIDE-BODY SMALL-OUTLINE PACKAGE
20 PIN SHOWN
-x------t
20
10
1-$-1 ---=-..:...'
0.010 (0 25) @ 1
-'--"""'-'.
L .." ' - ' - .
0.050 (1,27)
0.016 (0,40)
404000018-10194
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
~1EXAS
5-106
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
16-Pln sOle (OW) Package Power DIssipation Derating at Varying Air Flows
2000
oft/mln
1800
_. -
1600
......
--- --- --.-----. --.
-- ----- ---
~
E
I
1400
c
0
I
~
E
:::I
E
'lC
ftI
:IE
...
................
1200
J
--. ...
......
- ....
...
100 ft/mln
250 ft/mln
500ft/mln
... ~ ...
---~
................
...................
--- -----.:.------.
1000
800
600
--.
.... .....
......
..:::;--
-
400
200
0
25
30
35
45
40
50
60
55
65
70
75
80
85
90
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
0
0
100
250
500
NlA
t
9 JUNCTION TO AMBIENT
(·C/W)
9 JUNCTION TO CASE
(·C/W)
N/A
N/A
Wind tunnel
130
123
102
91
78
N/A
N/A
42
ENVIRONMENT
1 ft 3 box
Wind tunnel
Wind tunnel
Wind tunnel
NlA
N/A
NlA
Mounted on printed-circuit board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
5-107
MECHANICAL AND THERMAL DATA
PLASTIC WIDE·BODY SMALL·OUTLINE PACKAGE
DW IR·PDSO·G**
20 PIN SHOWN
r
20
,,------t
0.419 (10,65)
0.400 (10,15)
0.299 (7,69)
0.293 (7,45)
0
L~-----I
10
r
0.104(2,65)
IL
0.093 (2,35)
! t--!fiUHUUUUUill-p- L..L-Ji
:::~:::
l JL·. . . . ,'
1=1 ........
0.014 (0,35)
1
~:::~:::::
' ., I
Jl
fl
IOIIIT~:::=
1-$-1
0.010 (0 25) @ 1
~.---=--'-,.....;.......
_"-'.
L...
0.050 (1,27)
0.016 (0,40)
4040000lB-l0/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
~1EXAS
5-108
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
2o-Pln sOle (OW) Package Power Dissipation Derating at Varying Air Flows
2000
.... ................
1800
-""""..................
-""""................
........
... """"-..
... .................
....... .......
""""-- """".............. ........
----..
1600
~I
c
Oft/min
100ft/min
.. ..
--....... .......
1400
0
250ft/min
500ft/min
iDo
1200
..
1000
.............. ... ...
""""..............
....... .............. """"- -""""--
800
--
.......
70
75
j
C
I
E
::I
E
iC
III
-
....
-- .
- -~
""""-"
-""""-
.......
600
::E
400
200
0
25
30
35
45
40
50
55
60
65
80
85
90
Ambient Temperature - °C
Therm!ll Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9
JUNCTION TO AMBIENT
("C/W)
9
JUNCTION TO CASE
(OC/W)
0
1 1t3 box
110
N/A
0
Wind tunnel
110
N/A
100
Wind tunnel
85
N/A
250
Wind tunnel
74
N/A
500
Wind tunnel
66
N/A
NJA
NJA
N/A
39
t Mounted on pnnted-clrcuit board
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
5-109
MECHANICAL AND THERMAL DATA
DWIR-PDSO-G**
PLASTIC WIDE-BODY SMALL-OUTLINE PACKAGE
20 PIN SHOWN
I-$-I 0.010 (0 25)
®1
....:...._::.L.l.
.L....:!;....L.----.;...:...'
0.050 (1,27)
0.016 (0,40)
404000018-10/94
NOTES: A. All linear dimensions are In inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold .flash or protrusion not to exceed 0.006 (0,15).
5-110
-!llExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
24·Pln sOle (OW) Package Power Dissipation Derating at Varying Air Flows
3000
Oft/min
2800
2600
-_. -
100ft/min
250 ft/mln
----
500 ft/mln
2400
2200
~I
2000
0
1800
f
1600
J
1400
c
i
c
E
::I
E
.;c
1\1
::i
1200
1000
800
600
400
200
0
25
30
35
45
40
50
55
60
65
75
70
80
85
90
Ambient Temperature - ·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9
JUNCTION TO AMBIENT
("C/W)
9
JUNCTION TO CASE
(·C/W)
0
1 ft 3 box
92
NlA
0
Wind tunnel
88
N/A
100
Wind tunnel
69
250
Wind tunnel
57
NlA
NlA
500
Wind tunnel
48
N/A
N/A
N/A
N/A
25
t Mounted on printed-circuit board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-111
MECHANICAL AND THERMAL DATA
DW/R-PDS()'G**
PLASTIC WIDE-BODY SMALL-OUTLINE PACKAGE
20 PIN SHOWN
0.419 (10,85)
0.400 (10,15)
r·
20
0.299 (7,59)
0.293 (7,45)
0
L~-----t
10
r-
0.104(2,85)
~::~:::~
1_1'"
0.093 (2,35)
Jl
1t-1ijijihililiUil_AM. L.L-A
. ,,- l JL
0.004 (0,10)
0.020 (0,51)
0.014 (0,36)
1+1 0.010 (0 25)
fL
1~10.004(O'10)IITO.01~(O'30)
0°-8"
@) 1
_.J:..L.~;.;..:.;;:.;';';':"'_::o.LI.
L..
1
., I
0.009 (0,23)
0.050 (1,27)
0.016 (0,40)
404000018-10194
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drswing is subject to change without notice.
C. Body dimensions do not include mold flash or protruSion not to exceed 0.006 (0,15).
~1ExAs
5-112
INSTRUMENTS
POST OFACE BOX 856303 • DALlAS. TEXAS 76266
MECHANICAL AND THERMAL DATA
28-Pln sOle (OW) Package Power Dissipation Derating In Still Air
2000
1800
~
E
1600
I
1400
ia.
1200
c
'iii
.!!
Q
J
E
:::I
E
ill
III
:::E
1000
800
600
400
200
0
25
30
35
40
45
50
55
60
65
70
75
80
85
90
Ambient Temperature - °C
Thermal Resistance (a) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
a JUNCTION TO AMBIENT
COC/W)
a JUNCTION TO CASE
(OC/W)
0
1 ft 3 box
81.8
N/A
0
Wind tunnel
100
Wind tunnel
250
Wind tunnel
500
Wind tunnel
-
NlA
NlA
N/A
N/A
N/A
N/A
N/A
15.4
t Mounted on printed-circuit board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-113
MECHANICAL AND THERMAL DATA
DVIR·PDS()"G28
PLASTIC SMALL·OUTLINE PACKAGE
1
~ 0.050 (1,27)
I
~O~
__________________~
1
0.350 (8,89)
0.340(8,64)
~
0.478(12,14)
0.462 (11,73)
~~~~~~~~~~
0.010 (0,25)
0.006 (0,15)
1 4 - - - - - - 0.728 (18,49) _____~
0.718 (18,24)
0.120 (3,05)
0.110 (2,79)
IT~---r---r-Sea--=tlng'--Pla
....---~'----h..
\8
t
__
ne
1.010.004(0,10) 1
. . .
0.014 (0,36)
0.005 (0,13)
4040076/8-10194
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
~1ExAs
5-114
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL AND THERMAL DATA
28-Pln sOle (DV) Package Power Dissipation Derating at Varying Air Flows
3000
Oftlmln
2800
-
-
200 ftlmln
-
--
400 ftlmln
2600
2400
...
2200
~
E
........
I
c
0
'ia.ii
:~Q
I
1800
-=
1000
::E
...
.................
...
................ ........
1400
1200
...
................ ........
1600
E
::I
E
" " "
"'" "
........................
2000
...
................ ~ ...
........................
800
600
400
200
0
25
30
35
45
40
60.
55
60
65
70
75
80
85
90
Ambient Temperature - °C
Thermal Resistance (e) Measurementst
AIRFLOW
(ft/mln)
0
0
200
400
NlA
ENVIRONMENT
e JUNCTION TO AMBIENT
e JUNCTION TO CASE
1 ft 3 boX
-
N/A
Wind tunnel
63
Wind tunnel
56
N/A
NlA
Wind tunnel
51
NlA
NlA
N/A
-
(OC/W)
(OC/W)
t Mounted on printed-circu~ board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-115
MECHANICAL AND THERMAL DATA
DL/R·PDSO·G**
PLASTIC SHRINK SMALL·OUTLINE PACKAGE
48 PIN SHOWN
~
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)L
0.395 (10,03)
0
~~~~~""""~~~~~~
0.110 (2,79)
'T_'~ ~,..--::..:,=.:~:-=.:..:....--r-~o==f--+ ~se _'02_0_N~_t:_1-1=) "
___
0.016 (0,406)
0.008 (0,203)
NOTES: A.
B.
C.
D.
40400481B-l0/94
All linear dimensions are In inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not Include mold flash or protrusion. not to exceed 0.006 (0,15).
Foot length is measured from lead top to point 0.01 0 (0.254) above seating plane.
~1EXAS
5-116
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
56-Pin SSOP (DL) Package Power Dissipation Derating at Varying Air Flows
3000
oft/mln
2800
-
2600
--
100 ft/mln
--
250 ft/mln
----
500 ft/mln
2400
2200
it
E
...................
2000
...............
I
c
0
1800
"ii
1800
~
1400
E
::I
E
1200
~
Q.
is
b
....
-.............
-... -... -...
Do.
.... .............
.. -.............
-...-...
.
---...-...
........
.
"5C
III
:::IE
1000
.............
.. .
............... ..
.. -...............
.............
.. ............... ....
-...-...
-.............
-... -... -...-... ..
..
-...-...
~
---
~
-...-...
800
800
400
200
0
25
30
35
45
40
50
55
60
65
70
75
80
85
90
Ambient Tempereture - °C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
@ JUNCTION TO AMBIENT
(OC/W)
@ JUNCTION TO CASE
(OC/W)
0
1 ft 3 box
94
NJA
0
Wind tunnel
94
N/A
100
Wind tunnel
82
N/A
250
Wind tunnel
70
NJA
500
Wind tunnel
58
NJA
N/A
N/A
N/A
22
t Mounted on printed-circuit board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75266
5-117
MECHANICAL AND THERMAL DATA
PAG/S·PQFp·G64
PLASTIC QUAD FLATPACK
11.
0,271.1 o,08@1
0,17
33
32
49
o
64
0,137
0,117
17
'$TVP
lii~. J
10,10 sa
9,90
1 4 - - - - - 12,10 sa ----~
0,05 MIN
11,90
t~
-
Seating Plane
1--------rI-~-tI-"-o,=08..,1
-
1,20 MAX
4040282/8-10194
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change withQut notice.
~TEXAS
5-118
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS. TexAS 75265
MECHANICAL AND THERMAL DATA
64-Pln TQFP (PAG) Package Power Dissipation Derating at Varying Air Flows
3000
Oft/min
2800
100ft/min
2800
500ft/min
250ft/min
2400
2200
~
E
2000
I
I:
0
1.
I
J
E
1800
1800
1400
l:I
1200
I
1000
I
800
800
400
200
0
25
30
35
45
40
50
60
55
66
70
75
80
66
90
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
e JUNCTION TO CASE
AIRFLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
("C/W)
0
1 ft3 box
75.7
0
Wind tunnel
71.3
N/A
100
Wind tunnel
61.9
NlA
N/A
(·C/W)
NlA
250
Wind tunnel
52.6
500
Wind tunnel
44.6
N/A
N/A
N/A
N/A
15.1
t Mounted on pnnted-clrcult board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
----------
-.--_._-
-
--_.__._------_._...._..
5-119
MECHANICAL AND THERMAL DATA
PCB/8-PQFp·G120
PLASTIC QUAD Fl,ATPACK
61
90
91
60
0,25
0,17
120
o
I-$-I
o,07@1
31
mmHmf I
14'10SQ~
""TYP
13,90
16,10 SQ _ _ _ _ _ _~
15,90
Seating Plane
1.0.10,07
I
4040202/B-1O/94
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion. Allowable protrusion is O,25mm maximum per side.
Thennally enhanced molded plastic package (HSP).
~1ExAs
5-120
INSTRUMENTS
POST OFFICE BOX 865303 • DALLAS, TEXAS 75265
MECHANICAL AND THERMAL DATA
12o-Pln TQFP (PCB)t Package Power Dissipation Derating at Varying Air Flows
5000
Oft/min
4500
100 ft/mln
4000
500ft/min
250ft/min
~I
c
--- --- --- ---
3500
0
t
c
I
Do
E
3000
2500
2000
:::I
--- --- --- ---
E
iC
:I
1500
--------- ----
1000
500
0
25
30
35
45
40
50
60
55
65
70
75
80
85
90
Ambient Temperature _·C
Thermal Resistance (e) Measurements*
AIRFLOW
Cft/mln)
ENVIRONMENT
e JUNCTION TO AMBIENT
e JUNCTION TO CASE
("C/W)
("C/W)
a
a
1 ft 3 box
52.4
N/A
Wind tunnel
49.8
NlA
N/A
100
Wind tunnel
44.2
250
Wind tunnel
34.3
N/A
500
Wind tunnel
24.7
NlA
NlA
N/A
N/A
3.3
t Thermally enhanced package (TEP)
:j: Mounted on printed-circuit board
~TEXAS '
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-121
MECHANICAL AND THERMAL DATA
PH/R·PQFP·G80
1r- ~:: 1;1
PLASTIC QUAD FLATPACK
0,18
@I
------------------~
65
~l
12,00TYP
14,20 18,00
13,60 17,20
nJ
60
14------ 18,40TYP - - - - - - - - . !
20,20 _ _ _ _ _ _--.!
19,60
24,00
23,20 --------~
.l~
r
0,10 MIN
2,70TYP
Seating Plane
404oo11/B -10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
~1ExAs
5-122
INSTRUMENTS
POST OFACE eox 665303 • DALLAS. TEXAS 76265
MECHANICAL AND THERMAL DATA
SO-Pln PQFP (PH) Package Power Dissipation Derating In Stili Air
2000
1800
~I
c
1800
1400
0
I
:IQ
J
I
E
1200
1000
800
::I
600
400
200
0
25
30
35
45
40
50
80
55
65
70
75
80
65
90
Ambient Temperature _·C
Thermal Resistance (9) Measurementst
AIRFLOW
Cft/mln)
0
0
100
250
500
NlA
ENVIRONMENT
9 JUNCTION TO AMBIENT
,"C/W)
9 JUNCTION TO CASE
C·C/W)
NlA
N/A
1 1t3 box
83.9
Wind tunnel
-
Wind tunnel
NlA
Wind tunnel
-
N/A
N/A
15.1
Wind tunnel
N/A
NlA
t Mounted on printed-ciICuit board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-123
MECHANICAL AND THERMAL DATA '
PLASTIC QUAD FLATPACK
PMlS·PQFP·G64
1r-°.
271 • 1 0.08®1
0.17
33
49
32
64
17
~
__________
12'~SQ
__________~
11.80
Seating Plane
4040152/B-10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
~1ExAs
5-124
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
64-Pln TQFP (PM)t Package Power Dissipation Derating at Varying Air Flows
3000
------
2800
2600
Oft/min
100ft/min
250ft/min
500ft/min
2400
2200
~I
2000
I
1800
c
1600
c
J
~
1200
!
... ""'-..
...... ""'-.. ...
~ ... ~
""'-
1400
E
""'-.. ...
__ __
... ""'-..
...... ""'-..
... ~ ...
----
--
1000
...... ""'-.. ...
~
... ""'-..
...... ""'-..
"'""",---
............................
~
---- ---- ---- ---...
-~
...
......
~
...
800
......
600
400
200
o~--~--~--~--~----~--~--~--~--~--~~--~--~--~
25
30
40
70
75
65
90
35
45
50
55
60
65
80
Ambient Temperature - °C
. Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9 JUNCTION TO AMBIENT
(OC/W)
9 JUNCTION TO CASE
(DC/W)
1 ft3 box
0
0
Wind tunnel
95.5
92.5
NJA
N/A
N/A
100
Wind tunnel
87.8
250
Wind tunnel
72.9
NJA
500
Wind tunnel
57.8
N/A
N/A
NJA
N/A
10.4
t Mounted on pnnted-clI'Cult board
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5-125
MECHANICAL AND THERMAL DATA
PN/8-PQFP-G80
PLASTIC QUAD FLATPACK
61
40
80
21
Seating Plane
404013518-10194
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC Mo-136
~ThxAs
5-126
INSTRUMENTS
POST OFFICE BOX 855303 • DALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
SO-Pin TQFP (PN) Package Power Dissipation Derating at Varying Air Flows
3000
oft/mln
2800
100ft/mln
2600
500ft/mln
250ft/mln
2400
2200
~I
2000
0
1800
c:
i
1800
Q
J
1400
E
:::a
E
1200
-=
1000
::E
600
800
400
200
0
25
30
35
45
40
50
60
55
65
70
75
80
85
90
Ambient Temperature - ·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9
JUNCTION TO AMBIENT
("C/W)
9
JUNCTION TO CASE
("C/W)
100
Wind tunnel
79.1
250
Wind tunnel
67.3
500
Wind tunnel
54.2
N/A
N1A
N1A
N1A
N1A
N1A
N/A
N/A
10.6
0
1 ft3 box
89.2
0
Wind tunnel
87.8
t Mounted on prnrted-clrcult board
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
5-127
MECHANICAL AND THERMAL DATA
PQl8-PQFp·G***
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
f
0.012 (0,30)
0.008 (0,20)
"03"TYP
0.025 (0,635)
t
39
1 + - - - - - "01" SQ
M------ "0" SQ
0.150 (3,18)
0.130 (3,30)
63
•
----~
---------lM
1 + - - - - - - "02" SQ - - - - - - + 1
f
Seating Plane
r---rlo.---rl0""'.0::-:0~4""(0""',10~)1
0.180 (4,57) MAX
40400451B-10194
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
~1ExAs
5-128
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
MECHANICAL AND THERMAL DATA
132·Pln PQFP (PQ) Package Power Dissipation Derating at Varying Air Flows
5000
--- --- ------- --- ------ --- --- --- ----- - -- ----- --- --. --.---- --- --- .
--- -- --.--. --Oft/min
4500
100 ft/mln
250ft/min
500 ft/mln
4000
~
E
I
3500
i
3000
..
2500
c
is
-=
~
E
:::I
E
I
2000
1500
1000
500
0
25
30
35
40
45
50
60
55
65
70
75
80
65
90
Ambient Temperature - ·C
Thermal Resistance (G» Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
G> JUNCTION TO AMBIENT
G> JUNCTION TO CASE
(·C/W)
(·C/W)
0
1 ft 3 box
49.6
0
Wind tunnel
49.7
100
Wind tunnel
42.6
NJA
N/A
NJA
250
Wind tunnel
34.1
N/A
500
Wind tunnel
27.2
NJA
9.S
N/A
N/A
t Mounted on pnnted-clrcUit board
N/A
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-129
MECHANICAL AND THERMAL DATA
PLASTIC QUAD FLATPACK
PZ/8-PQFP·G100
76
60
100
26
16,20 SQ _ _~_--.!
16,80
1,46
1,36
Seating Plane
1,60 MAX
4040149/B-10/94
NOTES: A. All linear dimensions are In millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
~1ExAs
5-130
INSTRUMENTS
POST OFFICE BOX 665303 • DAU.AS. TEXAS 76266
MECHANICAL AND THERMAL DATA
10o-Pln TQFP (PZ) Package Power Dissipation Derating at Varying Air Flows
3000
Oft/min
2800
100 ft/mln
2800
500ft/min
250ft/min
2400
2200
~
E
2000
I
c
0
ia.
·21
is
I
1800
1600
1400
D.
E
::I
E
"5C
1\1
:::I!
1200
1000
800
600
400
200
0
25
30
40
35
45
50
55
60
65
75
70
80
85
90
Ambient Temperature - ·C
Thermal Resistance (9) Measurementst
AIRFLOW
(ft/mln)
ENVIRONMENT
9
JUNCTION TO AMBIENT
(·C/W)
9
JUNCTION TO CASE
(·C/W)
0
1 tt 3 boX
79
N/A
0
Wind tunnel
72.7
N/A
100
Wind tunnel
65.2
N/A
250
Wind tunnel
54.5
NlA
500
Wind tunnel
43.6
N/A
N/A
N/A
N/A
11.6
t Mounted on pnnted-clrcult board
-!111EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-131
5-132
6-1
c
~
_.
(')
CD
i:
o
Co
CD
-
en
6-2
VHDL Models
VHDL models for the FIFOs listed below are available through your local Texas Instruments sales
office:
SN74ACT2226 (Dual 64 x 1, Dual 256 x 1 Clocked FIFO)
SN74ACT3632-15/20/30 (512 x 36 x 2 Clocked FIFO)
SN74AcT3651-15/20/30 (2048 x 36 Clocked FIFO)
SN74ACT7881-15/20/30 (1024 x 18 Clocked FIFO)
SN74ACT7804-20/25/40 (512 x 18 Strobed FIFO)
SN74ACT7813-15/20/25/40 (64 x 18 Clocked FIFO)
SN74ACT7814-20/25/40 (64 x 18 Strobed FIFO)
Logic-Modeling Behavioral Models
6-6
LOGIC-MODELING BEHAVIORAL MODELS
The Logic Modeling Group continually updates model libraries. If you do not see a TI FIFO model that you need,
contact a local Logic Modeling Group representative or call 1-800-34MODEL (1-800-346-6335) for current
availability. For international inquiries, call 503-690-6900.
Behavioral models of the following TI FIFOs are available from the Logic Modeling Group, 19500 N.W. Gibbs
Drive, P.O. Box 310, Beaverton, OR 97075, 503-690-6900, fax: 503-690-6906, Technical Product Support:
1-800-445-1888.
DEVICE
ARCHITECTURE
ORGANIZATION
SN74ACT2226
Clocked
64 x 1
SN74ACT2228
Clocked
256 x 1
SN74ACT2227
Clocked
64 x 1
SN74ACT2229
Clocked
256 x 1
SPEED SORTS
SN74ABT3611
Clocked
64 x 36
-15, -20, -30
SN74ABT3612
Clocked
64x36x2
-15, -20, -30
SN74ABT3613
Clocked
64 x 36
-15, -20, -30
SN74ABT3614
Clocked
64x36x2
-15, -20, -30
SN74ACT3632
Clocked
512 x 36 x 2
-15, -20, -30
SN74ACT3641
Clocked
1K x 36
-15, -20, -30
SN74ACT7813
Clocked
64 x 18
-15, -20, -25, -40
SN74ACT7803
Clocked
512 x 18
-15, -20, -25, -40
SN74ABT7819
Clocked
512 x 18 x 2
-12, -15, -20, -30
SN74ACT7811
Clocked
1K x 18
-15, -18, -20, -25
SN74ACT7807
Clocked
2K x 9
-15, -20, -25, -40
SN74ACT7814
Strobed
64 x 18
-20, -25, -40
SN74ACT7806
Strobed
256 x 18
-20, -25, -40
SN74ACT7804
Strobed
512 x 18
-20, -25, -40
SN74ABT7820
Strobed
512 x 18 x 2
-15, -20, -25, -40
SN74ACT2235
Strobed
1K x 9 x 2
-20, -30, -40, -60
SN74ACT2236
Strobed
1K x 9 x 2
-20, -30, -40, -60
SN74ACT7808
Strobed
2K x 9
-20, -25, -30, -40
SN74ACT7201
Asynchronous
512 x 9
-15,-25,-35,-50
SN74ACT7202
Asynchronous
1K x 9
-15, -25, -35, -50
SN74ALS2233
Asynchronous
64 x 9
SN74ALS2238
Asynchronous
32x9x2
SN74ALS2232
Asynchronous
64 x 8
SN74ALS236
Asynchronous
64 x 4
SN74ALS232
Asynchronous
64 x 4
~1ExAs
'
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
6-7
Quality and Reliability Assurance
7-1
D
r::::
D)
7-2
Qualification of Products and Processes
7-3
7-4
Introduction
A significant change has recently occurred in the way our customers qualify products. At one point, virtually all
customers were spending millions of dollars annually, duplicating supplier qualification tests. However, as years of
improving qUality and reliability have raised the level of customer confidence and satisfaction, much of this in-house
customer testing was eliminated and customers began to rely on Texas Instruments (TI) test results.
This approach also became applicable to major process changes. If a major process change is made to a product, TI
qualifies the new process through extensive testing and transmits the data to customers for approval.
Both of these qualification approaches form the basis of the quality and reliability assurance practices for TI's FIFO
products.
7-6
7-<3
Quality and Reliability Assurance
in Integrated-Circuit Design
Page
General Quality and Reliability Rules .................................................. 7-9
Process-Specific Design Rules ...............................................•...... 7-9
Methodology-Oriented Design Rules. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-9
Change Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7-9
7-7
7-8
Quality and Reliability Assurance in Integrated-Circuit Design
Quality and reliability of the products are important elements in achieving customer satisfaction. These elements must
be designed in during the design phase of the products and built in during fabrication. To ensure that this occurs, all
integrated-circuit designs at Texas Instruments (TI) follow a three-tier design-rule structure as follows:
•
•
•
General company-wide quality and reliability rules
Process-specific design rules
Methodology-oriented design rules
General Quality and Reliability Rules
The process-independent company-wide quality and reliability rules are defined and, as necessary, adapted to new
requirements by a committee that is organized worldwide. These rules include directives for:
•
•
•
•
•
ESD protection
Latch-up protection
Electromigration constraints on current density
Maximum junction temperature
Hot-electron injection
Strict application of these rules results in high process yields and high quality and reliability. These rules are company
standards at TI' the result of many years of experience in semiconductor production.
Process-Specific Design Rules
These rules are created by a design council that is composed of members from different areas including process
development, product development, wafer fabrication, test development, and quality and reliability engineering. The
design council meets on a regular basis to generate and periodically update the design notebook, which contains all the
process-specific design rules. The design council acts as a forum for worldwide sharing of experience, knowledge, and
problems related to a specific process. The design notebook is maintained on a central computer, which can be accessed
by any authorized user at any worldwide TI facility; therefore, the latest version is instantly available for worldwide
access. Major chapters of the notebook are:
•
•
•
•
•
•
•
•
•
•
General guidelines for circuit design
Process parameters
Simulation models for processes
Simulation instructions and guidelines
Design methodology
Design documentation
Process-layout rules
Reliability rules
Electrical models for circuit packages
Requirements for photomask generation in wafer fabrication
Methodology·Orlented Design Rules
The guidelines for design methodology are basically the same for all types of semiconductors at TI and are rigidly
adhered to. This gives the designer a high confidence level that the target specifications are maintained, the functions
of a device are correctly implemented, and a high standard of reliability is achieved. Designing integrated circuits is now
a classic application for computer-aided design. Each designer has a network at their disposal for circuit entry, circuit
simulation, mask layout, and circuit verification.
Change Control
Continuous improvement at TI is recognized as a key method of offering greater value to our.1ong-te~ customers. A
major responsibility is to ensure that improvements in the materials and processes do not adversely affect our customers.
One of TI's missions is to assure our customers of a source of qualified supply and to provide a stable market to our
suppliers.
Through joint development efforts with strategic suppliers, TI has provided our customers with a steady stream of
improvements to the materials that are used in volume production. In addition, to remain competitive, new equipment
7-9
-- - - - - - -
-------
and process methods are constantly being evaluated. It is TI's goal to keep our customers infonned of all changes
identified as requiring notification.
The change-control system is contained in TI's quality system and covers all operations worldwide. The list of changes
requiring notification (see Table 1) is based upon a dynamic composite of documented customer requirements and
experience. The required qualification testing and process-capability studies also are dermed in the quality system. The
change notification contains a description of the change, reason for change, anticipated impact on customers, if any,
supporting reliability and applicable electrical-characterization data, and effective timing.
Table 1. Examples of Major Changes That can Require User Notification
PROCESS
7-10
MAJOR DESIGN CHANGE
WaferFab
Wafer-fab site
Prooessflow
Gate-oxide materials
Dielectric material
Metallization material
Passivation material
Die-coating material
Wafer diameter
Diffusion dopant
Gate-oxide thickness
Polysillcon-dopant type
Metallization thickness
Passivation thickness
Die-coating thickness
Assembly
Assembly site
Plating material
Wire-bond material
Sealing material
Marking method
Leadframe-base material
Pleting method
Mold-compound material
Die-attech material
Marking appearance
Test
Elimination of test steps
Electrical Specification
Relaxation of AC specification
Relaxation of DC specification
Mechanical Specification
Case outline
Loosening tolerance(s)
Packing! Shipping! Labeling! Environment
Carrier (real, tray) dimensions
Maximum storage temperature
Drypack requirements
Quality and Reliability Monitoring
Page
Environmental Laboratory.; ...............•........................................
Methods of Measuring Component Reliability .........................................
Failure-Rate Calculations for FIFO Products . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Qualification Data for FIFO Products. . . . • . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Life-Test and ESD-Characterization Data. . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
7-13
7-13
7-13
7-13
7-14
7-11
7-12
Quality and Reliability Monitoring
Environmental Laboratory
The environmental-test laboratories provide environmental-test services, both climatic and mechanical, for device
qualification, engineering evaluation, and acceptance purposes to operating entities within Texas Instruments (TI). TI
acquires and maintains suitable calibrated equipment with which the test and inspections required by external customers
and internal specifications can be performed. A properly trained and certified staff is maintained to perform the required
tests and inspections in a timely, cost-effective manner. The TI laboratories worldwide are maintained in a
certified/ approved status for those customers and agencies requiring this condition. TI conforms to national and
international standards and is certified as an approved self-qualification lab for several major customers.
Lab personnel interface closely with equipment manufacturers and standards bodies for maintenance of test capabilities.
Environmental-test methods and specifications are developed and controlled for TI worldwide. For continuous
improvement in maintaining world-class status, the environmental lab uses self-measurement indices by tracking cycle
time and customer satisfaction, both internal and external.
Methods of Measuring Component Reliability
Product-reliability tests are performed at high-stress conditions so that performance levels can be established during a
relatively short test duration. Specific stress conditions are chosen because they represent accelerated versions ofvarious
device-application environments and allow meaningful extrapolations to lower stress levels. These reliability-test
conditions are held constant so that product improvements or deficiencies can be readily discerned by comparing current
test data with the historical database on identical tests. However, extreme care is exercised to avoid any overstress
condition that could cause a device failure not related to the final device application.
The reliability stresses used most widely at TI are:
•
•
•
•
•
Life stress
Biased temperature and humidity
Biased highly accelerated stress test (HAST)
Nonbiased autoclave
Temperature cycling (air-to-air)
Failure-Rate Calculations for FIFO Products
The failure-rate performance for FIFO products has been calculated to be 15 FITs (failures per 106 device hours). This
calculation is based upon the following assumptions:
•
•
•
•
•
Applied supply voltage: 5 V
Junction temperature; 125°e or 1500 e
Activation energy; 0.7 eV
Derating temperature; 55°e
ehi2 upper confidence level: 60%
Qualification Data for FIFO Products
Qualification data has been gathered for each of the key design sets in TI's FIFO product line. This data represents the
results from life test and ESD characterization (see Table 1).
7-13
Table 1. Life-Test and ESD-Characterlzatlon Data
LIFE TEST
DESIGN SERIES
QUALIFICATION
VEHICLE
PACKAGE
TYPE
SN74ABT3612
SN74ABT3614
PCB
SN74ABT3613
SN74ABT3614
PCB/PO
125°C,
68HRS
DYNAMIC
126"C,
1000HRS
DYNAMIC
01116
SN74ABT3614
SN74ABT3614
PCB
SN74ABT7819
SN74ABT7819
PH/PN
SN74ABT7820
SN74ABT7819
PH/PN
SN74ACT2235
SN74ACT2235
FN
SN74ACT2236
SN74AqT2235
FN
SN74ACT7808
SN74ACT7808
PAG
01116
SN74ACT2226
SN74ACT2229
OW
01116
SN74ACT2227
SN74ACT2229
OW
SN74ACT2228
SN74ACT2229
OW
SN74ACT2229
SN74ACT2229
OW
SN74ACT3632
SN74ACT3632
PCB/PO
SN74ACT3641
SN74ACT3632
PCB/PO
SN74ACT7803
SN74ACT7803
OL
SN74ACT7804
SN74ACT7803
OL
SN74ACT7805
SN74ACT7803
OL
SN74ACT7806
SN74ACT7803
OL
SN74ACT7807
SN74ACT7807
FN
01116
SN74ACT7811
SN74ACT7801
FN/PN
01116
SN74ACT7813
SN74ACT7803
OL
SN74ACT7814
SN74ACT7803
OL
01116
01116
01116
01116
01116 '
HUMAN·BODY MODEL
(V)
7-14
ESDLEVEL
160°C,
300HRS
STATIC
MACHINE MODEL
(V)
Levell
0-1999
0-199
Level II
2000-3999
200-399
Level III
4000 or greater
400 or greater
HUMAN·
BODY
MODEL
MACHINE
MODEL
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
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A022396
@
1996 Texes Instruments Incorporated
Printed In the USA
•
TEXAS
INSTRUMENTS
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INSlRUMENTS
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0496-CP
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