1996_TI_Power_Supply_Circuits_Data_Book 1996 TI Power Supply Circuits Data Book
User Manual: 1996_TI_Power_Supply_Circuits_Data_Book
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"TEXAS
INSTRUMENTS
Power Supply Circuits
Voltage References, Voltage Regulators,
PWM Controllers, Supervisors, Switches,
Optoisolators, and Special Functions
1996
1996
Mixed-Signal Products
============~============
General Information
III
~~~~~~~~
Voltage References
•
Voltage Regulators
...
~~~~~~~~~~~
PWM Controllers, DC-to-DC Converters.
Supply Voltage Supervisors
..
Power Distribution Switches
..
Optoisolators
..
Applications
Mechanical Data
Power Supply Circuits
Data Book
Voltage References, Voltage Regulators,
PWM Controllers, Supervisors, Switches,
Optoisolators, and Special Functions
•
TEXAS
INSTRUMENTS
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications',.
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk ofthe customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or .are used.
Copyright © 1995, Texas Instruments Incorporated
Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri
INTRODUCTION
The Texas Instruments 1996 Power Supply Circuits Data Book has been created to showcase our growing
line of analog components for power-supply designs. Featured in this data book are most of the components
previously found in the 1992 Linear Circuits Data Book, Volume 3, the many new and exciting power supply
products introduced since then, and other components useful for power-supply designs.
This new data book is more than a collection of data sheets; it is a tool for locating the best power supply
components for a successful design effort. It has been completely restructured to help you quickly find the
devices best suited to your application.
A complete alphanumeric index at the beginning of the book makes finding specifications for known part
numbers simple. You no longer have to search through chapter indexes when you don't know a device
function.
The new device index includes a description to highlight TI's newest devices. These products include new
families of PMOS high-side switches and personal computer memory card international association
(PCMCIA) power distribution switches, extremely low dropout (LDO) voltage regulators, advanced
pulse-width-molulation (PWM) controllers, and integrated power supply building blocks. Product-preview
data sheets are included for devices not completely released when this book was printed. Contact your local
TI sales office for complete data sheets and product availability.
Redesigned product selection guides give a condensed view of parametric information, organized to help
you choose the devices that most closely fit your needs. Key specifications and/or features are presented
for easy comparison.
An extensive glossary is provided for reference, defining and clarifying terms used by Texas Instruments and
the semiconductor industry that might be new or unfamiliar.
The data sheets have been organized into several chapters by product function.
•
Voltage references
•
Voltage regulators
•
PWM controllers and dc-to-dc converters
•
Supply voltage supervisors
•
PMOS and PCMCIA power distribution switches
•
Optoisolators
• Building blocks and special functions
Each chapter has its own table of contents that includes descriptions of the devices, which makes finding a
specific device much easier to find.
For convenience, a chapter for optoisolators is included in the 1996 Power Supply Circuits Data Book.
This eliminates the need to flip back and forth between two data books for your total power-supply solution.
In section 9 of this data book there is a collection of application notes. Texas Instruments is committed to
providing designers with detailed application notes for our newest power-supply components. This section
represents the beginning of this effort. These applications are fully tested and, in some cases, evaluation
boards may be available (contact your local TI sales office). More applications notes will be available from
the factory soon.
The last section of this data book contains complete mechanical specifications for all packages used with
Texas Instruments power supply circuits. This includes the latest innovations in surface-mount power
packages. Designers of space-critical systems may want to investigate new products offered in SOT-23 (DBV
suffix), power TSSOP (PWP suffix), and the PowerFlex™ (KTD, KTG, and KTP suffixes) packages.
PowerFlex is a trademark of Texas Instruments Incorporated.
v
While this data book offers design and specification data only for power-supply products, complete technical
data for any TI semiconductor product is available from your nearest TI Field Sales Office, local authorized
TI distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. Box 809066
DALLAS, TEXAS 75380-9066
or telephone the TI Literature Response number: 1-800-477-8924.
We sincerely believe the new 1996 Power Supply Circuits Data Book will be.a valuable addition to your
collection of technical literature.
vi
1-1
Contents
Page
Alphanumeric Index ...................................................... 1-3
New Device Index ......................................................... 1-5
Selection Guide ........................................................... 1-7
Glossary ............................ '...................................... 1-17
....oj
...3
a
_.
oj
1-2
ALPHANUMERIC INDEX
4N25
4N26
4N27
4N28
4N35
4N36
4N37
6N135 ...................
6N136 ...................
HCPL4502 .....•..........
LM185-1.2
LM185-2.5
LM23~2.5
LM285-1.2
LM285-2.5
LM336-2.5
LM385-1.2
LM385-2.5 ...............
LM385B-l.2 ..........•.•.
LM385B-2.5 .......••....•
LT1004-1.2 .....•.........
LT1004-2.5 ..............•
LT1009 .................•
LT1054 ..................
MCT2 •..................
MCT2E ..•...............
MOC3009 ................
MOC301 0
M0C3011
MOC3012
MOC3020
MOC3021
MOC3022
MOC3023
SG2524
SG3524 •.................
TIL191 •............•....
TIL191A .............•...
TI1191B ................•
TIL192 ..................
TIL192A ..............•..
TIL192B ..............•.•
TIL193 ....•....•.......•
TI1193A ...........••.•..
TI1193B ...........•.....
TIl300 ..••............••
TIl300A ................•
TIL3009 ..••..............
TIL3010
TIl3011
TIL3012
TlL3020
TIL3021
TIL3022
7-3
7-3
7-3
7-3
7-7
7-7
7-7
7-13
7-13
7-13
2-3
2-11
2-21
2-3
2-11
2-21
2-3
2-11
2-3
2-11
2-27
2-27
2-39
8-3
7-23
7-23
7-29
7-29
7-29
7-29
7-35
7-35
7-35
7-35
4-3
4-3
7-41
7-41
7-41
7-41
7-41
7-41
7-41
7-41
7-41
7-47
7-47
7-51
7-51
7-51
7-51
7-57
7-57
7-57
TIl3023 .••.....•••.......
TL-5CSI285 ..............
TL 1431 ..................
TLl451A ••......•........
TL 1454 ..•...............
TL2217-285 •.........•...
TL2218-285 ..............
TL317 ...................
TL430 ...•...•...•.......
TL431 ................••.
TL431A ........•.•••.....
TL494 ...........•.......
TL496 ......•............
TL497A ..................
TL499A ..................
TL5001 ................••
TL594 ........•........•.
TL598 ...............•...
TL750L05
TL750L08
TL750L10
TL750112
TL750M05
TL750M08
TL750M10
TL750M12
TL751L05
TL751LOB
TL751Ll0
TL751112
TL751M05
TL751M08
TL751M10
TL751M12
TL75LP05
TL75LPOB
TL75LP10
TL75LP12
TL75LP48
TL7702A
TL7702B
TL7705A
TL7705B
TL7709A
TL7712A
TL7715A
TL7757 .•...•...........•
TL7759 ...••......•......
TL777o-12 ...•...........
TL777o-15 .............••
TL777o-5 .............•..
TL780-05
TL780-12
TL780·15
7-57
8-27
3-93
4-81
4-101
8-33
8-39
3-3
3-11
3-17
3-17
4-19
4-31
4-37
4-47
4-121
4-55
4-67
3-49
3-49
3-49
3-49
3-59
3-59
3-59
3-59
3-49
3-49
3-49
3-49
3-59
3-59
3-59
3-59
3-35
3-35
3-35
3-35
3-35
5-3
5-15
5-3
5-15
5-3
5-3
5-3
5-25
5-37
5-43
5-43
5-43
3-71
3-71
3-71
TL783 •.....•....•.......
TLC7705
TLE2425 •...........•....
TLE2426 ..........•......
TLV2217~ •....•...•.....
TLV431A ......•...•..••..
TPS1100
TPS1101
TPS1110
TPS1120
TPS2010
TPS2011
TPS2012
TPS2013
TPS2201
TPS2202
TPS2202A ................
TPS2205
TPS2811
TPS2812
TPS2814
TPS2815
TPS5904
TPS5904A ...........•...•
TPS6734
TPS7101 ••...••.........•
TPS7133 .•........•......
TPS7133QPWP ...........•
TPS7148
TPS7150
TPS7201
TPS7233
TPS7248
TPS7250
TPS7301
TPS7333
TPS7348
TPS7350
TPS9103
uA723 ...................
uA7805
uA7806
uA7808
uA781 0
uA7812
uA7815
uA7818
uA7824
uA7885
uA78L02
uA78L05
uA78L06
uA78L08
uA78L09
3-79
5-53
8-47
8-61
3-123
3-109
8-3
6-13
6-23
&-35
&-47
&-47
6-47
&-47
6-65
&-87
&-107
&-127
8-79
8-79
8-79
8-79
7-63
7-83
4-139
3-129
3-129
3-159
3-129
3-129
3-185
3-185
3-185
3-185
3-213
3-213
3-213
3-213
8-81
3-247
3-259
3-259
3-259
3-259
3-259
3-259
3-259
3-259
3-259
3-275
3-275
3-275
3-275
3-275
Devices in bold type are new to this data book.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1-3
ALPHANUMERIC INDEX
uA78L10 ... ..... .........
uA78L12 • • • • • • • • • ' 0 ' • • • • •
uA78L15 .. , ...............
uA78M05 ...... , ..........
uA78M06 ........ .... .....
uA78M08
uA78M09
uA78M10 .................
uA78M12 .................
uA78M15
•••••
•
0
••••••••••
•••••
•
0
••••••••••
••••••••••••
00'
o.
3-275
3-275
3-275
3-289
3-289
3-289
3-289
3-289
3-289
3-289
uA78M20 ................. 3-289
uA78M24 . ................ 3-289
uA79M05 ................. 3-303
uA79M06
3-303
uA79M08
3-303
uA79M12
3-303
uA79M15 ................. 3-303
uA79M20 . ................ 3-303
uA79M24 . ................ 3-303
•
••
00
••••••••••••
••••••••
0
••••••••
..............
0
•••
~TEXAS
INSTRUMENTS
1-4
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
.
UC2842 . .................
UC2843 ..................
UC2844 . .................
UC2845 . .................
UC3842 . .................
UC3843
UC3844 . .................
UC3845 . .................
•
•••••
o
•••••••••••
4-157
4-157
4-157
4-157
4-157
4-157
4-157
4-157
NEW DEVICE INDEX
TIL300t
TIL300At
TL1454
TL2218-285
TL5001
TL75LP05
TL75LP08
TL75LP10
TL75LP12
TL75LP48
TLC7705
TLV2217-33
TLV431A
TPS1100
TPS1101
TPS1110
TPS1120
TPS2010
TPS2011
TPS2012
TPS2013
TPS2201
TPS2202
TPS2202A
Precision Linear Optocoupler ................................................. .
Precision Linear Optocoupler .........................•........................
Dual Channel Pulse-Width-Modulation (PWM) Control Circuit .................... .
Excalibur Current-Mode SCSI Terminator ...................................... .
Pulse-Width-Modulation Control Circuits ....................................... .
Low-Dropout Voltage Regulators ............................................. .
Low-Dropout Voltage Regulators ............................................. .
Low-Dropout Voltage Regulators ............................................. .
Low-Dropout Voltage Regulators ............................................. .
Low-Dropout Voltage Regulators ............................................. .
Micropower Supply Voltage Supervisors ....................................... .
Low-Dropout 3.3-V Fixed Voltage Regulators ................................... .
Low-Voltage Adjustable Precision Shunt Regulators ............................. .
Single P-Channel Enhancement-Mode MOSFETS .............................. .
Single P-Channel Enhancement-Mode MOSFETS .............................. .
Single P-Channel Logic-Level MOSFETS ...................................... .
Dual P-Channel Enhancement-Mode MOSFETS ............................... .
Power-Distribution Switches ................................................. .
Power-Distribution Switches ................................................. .
Power-Distribution Switches ................................................. .
Power-Distribution Switches ................................................. .
Dual-Slot PC Card Power-Interface Switches For Parallel PCMCIA Controllers ..... .
Dual-Slot PC Card Power-Interface Switches For Serial PCMCIA Controllers ....... .
Dual-Slot PC Card Power-Interface Switch With Reset For Serial PCMCIA
Controller .................................................................. .
TPS2205t
Dual-Slot PC Card Power-Interface Switch With Suspend Mode For Parallel
PCMCIA Controller .......................................................... .
TPS2811t
Dual High-Speed MOSFET Drivers ........................................... .
TPS2812t
Dual High-Speed MOSFET Drivers ........................................... .
Dual High-Speed MOSFET Drivers ........................................... .
TPS2814t
TPS2815t
Dual High-Speed MOSFET Drivers ........................................... .
TPS5904
Opto-Isolated Feedback Amplifiers ............................................ .
TPS5904A
Opto-Isolated Feedback Amplifiers ............................................ .
TPS6734
Fixed 12-V 120-mA Boost-Converter Supply ................................... .
TPS7101
Low-Dropout Voltage Regulators ............................................. .
TPS7133
Low-Dropout Voltage Regulators ............................................. .
TPS7133QPWP Micropower Low-Dropout Voltage Regulators .................................. .
TPS7148
Low-Dropout Voltage Regulators ............................................. .
TPS7150
Low-Dropout Voltage Regulators ............................................. .
TPS7201
Micropower Low-Dropout Voltage Regulators .................................. .
TPS7233
Micropower Low-Dropout Voltage Regulators .................................. .
TPS7248
Micropower Low-Dropout Voltage Regulators .................................. .
TPS7250
Micropower Low-Dropout Voltage Regulators .................................. .
TPS7301
Low-Dropout Voltage Regulators With Integrated Delayed Reset Function ......... .
TPS7333
Low-Dropout Voltage Regulators With Integrated Delayed Reset Function ......... .
TPS7348
Low-Dropout Voltage Regulators With Integrated Delayed Reset Function ......... .
TPS7350
Low-Dropout Voltage Regulators With Integrated Delayed Reset Function ......... .
TPS9103
Power Supply For GaAs Powers Amplifiers .................................... .
t This is a product preview data sheet.
7-47
7-47
4-101
8-39
4-121
3-35
3-35
3-35
3-35
3-35
5-53
3-123
3-109
6-3
6-13
6-23
6-35
6-47
6-47
6-47
6-47
6-65
6-87
6-107
6-129
8-79
8-79
8-79
8-79
7-63
7-63
4-139
3-129
3-129
3-159
3-129
3-129
3-185
3-185
3-185
3-185
3-213
3-213
3-213
3-213
8-81
~TEXAS
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
1-5
1-6
-
fixed output voltage series pass regulators
DEVICE
Vo
(V) NOM
10
(mA)
MAX
TOL
(%)
Iq
(mA)TYP
VDO
(V)
TYP-MAX
Vlmax
(V)
LDO
SHUT
DOWN
svst
TA
-40°C to 125°C
Very low dropout PMOS
X
-40°C to 125°C
Lowest dropout PMOS with SVS
DESCRIPTION
POSITIVE OUTPUT VOLTAGE
TPS7233
TPS7333
TLV2217-33
250
3.3
500
TPS7133
TPS7248
TPS7348
TL75LP48
250
4.85
TPS7148
!!A78L05A
~
~~
;~t::
::d~d
~~
~
lTH"
TL75LP05
~~
E(I)
TPS7150
(J)
TL750M05
~
TL780-05
~A7805
!!A78L06
!!A78M06
!!A7806
t
Supply-voltage supervisor
0.4-0.5
12
X
2
285 !!A
0.047 - 0.060
10
X
X
-40°C to 125°C
2
155 !!A
0.09-0.1
10
X
X
-40°C to 125°C Very low dropout PMOS
O°Cto 125°C
Low dropout pnp
Lowest droput PMOS
10
X
X
-40°C to 125°C
Lowest dropout PMOS with SVS
X
X
-40°C to 125°C
Low dropout pnp
500
2
285 !!A
0.03-0.037
10
X
X
-40°C to 125°C
Lowest dropout PMOS
5
380
2.5-3
20
10
3.8
2-3
20
4
10
0.2-0.6
26
X
4
10
0.2-0.6
26
X
10
18
0.32-0.6
26
X
300
100
6
19
23
1500
!!A78L06A
I
1
0.12-0.2
750
TL751M05
X
0.028 - 0.037
500
!!A78M05
X
X
4
250
5
X
340 !!A
LM2930-5
TPS7350
10
10
2
150
TPS7250
0.14-0.18
0.044-0.06
2
TL750L05
TL751L05
155 !!A
340 !!A
300
100
!!A78L05
2
2
X
-40°C to 125°C General purpose, low current
-40°C to 125°C General purpose, low current
-40°C to 150°C
X
Low dropout pnp, low current
-40°C to 150°C
Low dropout pnp, low current, shutdown
-40°C to 150°C
3-terminallow-dropout pnp
-40°C to 125°C
Very low dropout PMOS
-40°C to 125°C
Lowest dropout PMOS with SVS
2
155 !!A
0.76-0.85
10
X
X
2
340 !!A
0.27-0.035
10
X
X
2
4
0.12-0.2
23
X
X
-40°C to 125°C
Low dropout pnp
2
285 !!A
0.27-0.033
10
X
X
-40°C to 125°C
Lowest dropout PMOS
5
4.5
2-3
25
1
60
0.5-0.6
26
X
X
X
O°C to 125°C
-40°C to 125°C
X
1
60
0.5-0.6
26
1
5
2-3
25
-40°C to 125°C
10
4.2
2-3
25
5
3.9
2.5-3
20
O°Cto 125°C
O°C to 125°C
General purpose, medium current
Low dropout pnp, high current
Low dropout pnp, high current, shutdown
High current, upgrade for ~A7805
-40°C to 125°C General purpose, high current
General purpose, low current
10
3.9
2.5-3
20
O°Cto 125°C General purpose, low current
500
5
4.5
2-3
25
O°C to 125°C
General purpose, medium current
1500
10
4.3
2-3
25
O°C to 125°C
General purpose, high current
r-
Z
~
::D
C5
~
~cn
C)m
mr-
~~
C)::::!
cO
r-Z
~C)
~
05
cnm
::DC
I
'-(1)
fixed output voltage series pass regulators (continued)
DEVICE
Vo
(V) NOM
10
(rnA)
MAX
TOL
(%)
Iq
(mA)TYP
VDO
(V)
TYP-MAX
Vlmax
(V)
LDO
SHUT
DOWN
svst
TA
DESCRIPTION
100
j.tA78L08
TL750L08
150
TL751L08
LM2930-8
TL75LP08
8
j.tA78M08
TL750M08
j.tA7808
!i1-
j.tA7885
~~~
j.tA78L08A
~~d
j.tA78L09
~~!:
t=~rr:I
9
j.tA78L10A
~rr:I
~~
TL750L10
~~
TL75LP10
~
10
j.tA78M10
TL750M10
TL751M10
j.tA810
t
General purpose, low current
23
O°C to 125°C
General purpose, low current
4
10
0.2-0.7
26
X
-40°C to 150°C
Low dropout pnp, low current
4
10
0.2-0.7
26
X
X
-40°C to 150°C
Low dropout pnp, low current, shutdown
-40°C to 150°C
3-terminallow-dropout pnp
X
-40°C to 125°C
Low dropout pnp
0.32-0.6
26
X
4
0.12-0.2
23
X
500
5
4.6
2.5-3
25
1
60
0.5-0.7
26
X
X
1500
100
150
TL751L10
O°C to 125°C
2.5-3
18
100
j.tA78L10
23
4
2
500
j.tA78M09
4
10
10
750
8.5
5
2.5-3
300
TL751M08
C3
~
O°C to 125°C
X
General purpose, medium current
Low dropout pnp, high current
Low dropout pnp, high current, shutdown
1
60
0.5-0.7
26
4.3
2.5-3
25
O°C to 125°C
General purpose, high current
10
4.3
2-3
25
O°Cto 125°C
General purpose, high current
5
4.1
2.5-3
24
O°Cto 125°C
General purpose, low current
10
4.1
2.5-3
24
O°Cto 125°C
General purpose, low current
-40°C to 125°C
5
4.6
2.5-3
26
O°C to 125°C
General purpose, medium current
5
4.2
2.5-3
25
O°C to 125°C
General purpose, low current
10
4.2
2.5-3
25
O°C to 125°C
General purpose, low current
4
10
0.2-0.8
26
X
4
10
0.2-0.8
26
X
X
2
4
0.12 -0.2
23
500
5
4.6
2.5-3
28
1
60
0.5-0.8
26
X
1
60
0.5-0.8
26
X
10
4.3
2.5-3
28
1500
-40°C to 125°C
10
300
750
):!on
:0 ....
<0
POSITIVE OUTPUT VOLTAGE (CONTINUED)
j.tA78L08A
-m
z,mm
-40°C to 150°C
Low dropout pnp, low current
X
-40°C to 150°C
Low dropout pnp, low current, shutdown
X
-40°C to 125°C
Low dropout pnp
O°Clo 125°C
-40°C to 125°C
X
-40°C to 125°C
O°C to 125°C
Supply-voltage supervisor
,
General purpose, medium current
Low dropout pnp, high current
Low dropout pnp, high current, shutdown
General purpose, high current
Oz
~C)
~S
me
:om
m
C)
c:
,iI:I!
d
:0
(I)
fixed output voltage series pass regulators (continued)
DEVICE
Vo
(V) NOM
10
(mA)
MAX
TOL
(%)
Iq
(mA)TYP
VDO
(V)
TYP-MAX
Vlmax
(V)
LDO
SHUT
DOWN
svst
TA
DESCRIPTION
POSITIVE OUTPUT VOLTAGE (CONTINUED)
f.lA78L12A
TL750L12
f.lA78M12
12
TL750M12
TL780-12
27
-40°C to 125°C
General purpose, low current
2.5-3
27
-40°C to 125°C
General purpose, low current
4
10
0.2-0.9
26
X
-40°C to 150°C
Low dropout pnp, low current
4
10
0.2-0.9
26
X
X
-40°C to 150°C
Low dropout pnp, low current, shutdown
300
2
4
0.12-0.2
23
X
X
-40°C to 125°C
Low dropout pnp
500
5
4.8
2.5-3
30
1
60
0.9-0.9
26
X
-40°C to 125°C
X
-40°C to 125°C
1500
f.lA7812
!il-
.~~~
f.lA78L15A
100
f.lA78L15
~~d
f.lA78M15
~t::~
fl~
15
500
TL780-15
~tT1t1l
1500
f.lA7815
i~
'"
~
2.5-3
4.3
750
TL751M12
~
4.3
150
TL751L12
TL75LP12
5
10
100
f.lA78L12
f.lA7818
18
f.lA78M20
20
f.lA78M24
24
IlA7824
t
Supply-voltage supervisor
500
1500
O°C to 125°C
General purpose, medium current
Low dropout pnp, high current
Low dropout pnp, high current, shutdown
1
60
0.9-0.9
26
1
5.5
2.5-3
30
O°Cto 125°C
10
4.3
2.5-3
30
-40°C to 125°C
5
4.6
2.5-3
30
O°C to 125°C
General purpose, low current
10
4.6
2.5-3
30
O°C to 125°C
General purpose, low current
5
4.8
2.5-3
30
O°C to 125°C
General purpose, medium current
1
5.5
2.5-3
30
O°C to 125°C
High current, upgrade for f.lA7815
10
4.4
2.5-3
30
O°C to 125°C
General purpose, high current
10
4.5
3-3
33
O°Cto 125°C
General purpose, high current
5
4.9
3-3
35
O°C to 125°C
General purpose, medium current
5
5
3-3
38
O°C to 125°C
General purpose, medium current
10
4.6
3-3
38
O°Cto 125°C
General purpose, high current
High current, upgrade for f.lA7812
General purpose, high current
r-
Z
~
:D
~
~
l>cn
C)m
mr-
m
:D
me')
C)::::!
c:O
r-Z
~C)
oS
:b
:DC
cnm
ro
1""'(1)
fixed output voltage series pass regulators (continued)
DEVICE
Vo
(V) NOM
10
(mA)
MAX
TOl
(%)
Iq
(mA)TYP
VDO
(V)
TYP-MAX
Vlmax
(V)
lDO
SHUT
DOWN
svst
TA
DESCRIPTION
NEGATIVE OUTPUT VOLTAGE
MC79l05A
MC79l05
-5
j.iA79M05
5
5
2-3
-20
O°C to 125°C
Negative low current
10
10
2-3
-20
O°C to 125°C
Negative low current
500
5
1
2-3
-25
O°C to 125°C
Negative general purpose, medium current
Negative general purpose, medium current
100
j.iA79M06
-6
500
5
1
2-3
-25
O°C to 125°C
j.iA79M08
-8
500
5
1
2.5-3
-25
O°C to 125°C
Negative general purpose, medium current
5
5
2.5-3
-27
O°C to 125°C
Negative low current
Negative low current
MC79l12A
MC79l12
-:12
j.iA79M12
100
500
MC79L15A
100
10
10
2.5-3
-27
O°C to 125°C
5
1.5
2.5-3
-30
O°C to 125°C
Negative general purpose, medium current
5
5
2.5-3
-30
O°Cto 125°C
Negative low current
10
10
2.5-3
-30
O°Cto 125°C
Negative low current
@
MC79L15
~~Z4r
500
5
1.5
2.5-3
-30
O°Cto 125°C
Negative general purpose,medium current
j.iA79M20
-20
500
5
1.5
3-3
-35
O°Cto 125°C
Negative .general purpose, medium curreni
j.iA79M24
-24
500
5
1.5
3-3
-38
O°C to 125°C
Negative general purpose, medium current
~
81 .
r;;I-
I~~
i~
~
-15
j.iA79M15
t
Supply-voltage supervisor
-m
z.mm
3>0
:::D ....
ci:::O~
!:iC')
~:=
me
:::D m
~
c::
!;
d
:::D
(I)
adjustable series pass regulators
DEVICE
Vo
10
(V)
(rnA)
MAX
MIN-MAX
Tl317
TOl
(%)
Iq
(mA)TYP
VDO
(V)
TYP-MAX
Vlmax
(V)
lDO
SHUT
DOWN
1.2-32
100
4
1.5
2.5-3
35
TPS7201
1.2-9.75
250
3
1551lA
0.16-0.27
10
X
X
TPS7301
1.2-9.75
250
3
3401lA
0.052-0.085
10
TPS7101
1.2-9.75
500
3
2851lA
0.052-0.085
10
X
X
X
X
TL783
1.2-125
700
6
15
10-15
125
svst
DESCRIPTION
TA
O°C to 125°C General purpose low current adjustable
X
-40°C to 125°C
Very low dropout PMOS adjustable
-40°C to 125°C
lowest dropout PMOS with SVS
-40°C to 125°C
..
O°C to 125°C
lowest dropout PMOS adjustable
High voltage high current adjustable
t Supply-voltage supervisor
adjustable shunt regulators
...
!
~
DEVICE
Vref
(V)
o_~
~~
:;jd
!f~
tr1 '"
~~
f:
IZ
(rnA)
MIN-MAX
Vo
(V)
MIN-MAX
TOl
Vlmax
(%)
(V)
TEMP CO
(pprnf'C) TYP
DESCRIPTION
TlV431
1.24
0.1-15
Vref- 6
1
6
46
Low voltage adjustable shunt reference
TL1431
2.5
1-100
Vref- 36
0.40
36
30
Precision adjustable shunt reference
Adjustable shunt reference
Tl431
2.5
1-100
Vref- 36
2
36
30
Tl431 A
2.5
1 -100
Vref- 36
1
36
30
TL430
2.75
2-100
Vr"f- 3O
9
30
120
Precision adjustable shunt reference
Adjustable shunt reference
~
r-
Z
!:
::D
<
o
~
:1>cn
C)m
mr-
::D m
mO
C)::::!
cO
r-Z
~C)
~
:!:
-
oS
::DC
cnm
!
0
e:')
.....
DESCRIPTION
me
(Ok)
UtA)
(mA)
0.30
10
20
Micropower precision reference
:l:JZ
"TIc
m_
me:')
1
10
20
Micropower reference
LM385-1.2
2
10
20
Micropower reference (LM185/285 temperature grades also available)
LT1004-2.5
0.80
20
20
Micropower precision reference
mm
01
400
10
Precision voltage reference (LM236 temperature grade also available)
om
LM336B-2.5
LM385B-2.5
LT1009
2.5
1.5
20
20
Micropower precision reference
2
400
20
Voltage reference
LM385-2.5
3
20
20
Micropower reference (LM185/285 temperature grades also available)
LM336-2.5
4
400
10
Voltage reference (LM236 temperature grade also available)
~
m~~d
~t::
.'
.~
~l"l1
~~
~~
j
."....
..
Z
en
0_
I~~
:l:Jc
.
supply voltage supervisors
(V)
TOl
(%)
TL7702A
pgmt
2
3
TLn02B
pgmt
2
TLC7705
4.55
1.5
TL7705A
4.55
TLn05B
4.55
TLn57
4.55
TLn59
4.55
TL7n0-5
4.55
DEVICE
~
~2'"
: rn"&·
;~gd
':~
om
~~
Vt
PROGRAMMABLE
TIME DELAY
COMPLEMENTARY
OUTPUTS
3.60
X
X
Single SVS with programmable undervoltage threshold and
reset time delay
3
1
X
X
Single SVS with programmable undervoltage threshold and
reset time delay
251lA
1
X
X
Single micropower SVS (5 V) wRh programmable time delay
and push-pull outputs
2
3
3.60
2
3
1
X
X
X
X
Single SVS for 5 V systems with programmable time delay
3
401lA
1
3
401lA
1
X
4-tenninal SVS lor 5 V systems
1
5
1
X
X
Dual SVS, 5 V and programmable with programmable time
delay
X
X
X
Single SVS for 9 V systems with programmable time delay
X
Single SVS for 12 V systems with programmable time delay
X
X
Dual SVS, 12 V and programmable with programmable time
delay
X
X
Single SVS for 15 V systems with programmable time delay
X
Dual SVS, 15 V and programmable with programmable time
delay
ICC
(mA) MAX
VI min
(V)
TLn09A
7.60
2
3
3:60
TLn12A
10.80
2
3
3.60
TLn70-12
10.90
1
5
1
TLn15A
13.50
2
3
3.60
TLn70-15
13.64
1
5
1
OVS*
DESCRIPTION
Single SVS lor 5 V systems with programmable time delay
3-terminal SVS for 5 V systems
X
X
X
X
t Programmable using external resistor divider.
:t: Overvoltage sense (programmable)
(J)
~
en
e
"'tI
"'tI
!<
o<
~
)10
en
c:l m
mrenm
CO
"'tI~
m0
:::a
0_
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enm
r
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switching power supply controllers
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MODE
<-
S.
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>
CJ
90
II.
~
....I
0
aW
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~E
Z
0
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....I
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~
Z
w
a:
W
I&.
w
a:
:;
7-40
200
300
5
5
8-40
100
1000
5
4
7-40
200
300
5
1
~~~
Current-Mode
PWM
Fixed
On-lime
V-Mode
*
(J
....;:)
>
~<-
!:i
Voltage-Mode PWM
I
Z
I':..J!;
w
(J
rD
0
So
OJ
CJ
0(
zw
;:)
z
II.
I&.
W
a:
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~~
zw
~
-a:
!cia:
a:;:)
w(J
rn
0
!:i:t:
Y
....I
0
;:)
....a:
w
....I
Z
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0
w
:;
i=
Q
0(
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~
;:)
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Q
W
Q
Z
w
Q
w
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CJ
Y
Y
-
Y
Y
2
y
-
y
y
y
2
Y
-
Y
2
y
y
2
-
Y
1
-
2.5
3.513.1
Y
100
Y
3.6-40
20
400
1
5
1.1/1
Y
100
Y
-
Y
-
Y
-
2.3INA
N
1.210.003
N
1
11/NA
N
97
Y
2
11/NA
N
97
Y
N
-
1.1-35
500
40
*
10
1.26
5
4.5-12
500
50
1.2
5
Y
1
Y
1.25
40
1
-
2000
1200
-
90
±40
1.1-20
2
Y
3.6-20
5
II.
12.4/9
Y
5
(J
m
Z
a:
a:
;:)
-
100
500
0
0
Y
Y
500
~w
a:
0(
Y
1.7/1.3
±200
CJ
0
:l3
CJ)
90
4
±200
w
~
w
Q
O.81NA
N
11/6
N
Z
Y
Y
Y
Y
Y
Y
Y
Y
Y
y
y
-
-
-
a:
II.
z
;:)
Y
y
y
Oc
:eo
mm
;:)
~
0
c
II.
N
2.5
30t
CJ
0(
.
J
zW
0(
Q
::iii
?/8
500
30t
a:
rn
::i
Y
20
Y
::iii
II.
II.
z5
e)Z
"tJe)
GI
w
....I
W
CJ
::C-l
w
Y
3.6-50
5
W
....I
0(
ii:
Y
90
4
W
0
:;
:;
W
....I
0
90
Y
1.23
Q
m
~
rn
iii
151NA
7.15
;:)
II.
W
....I
:t:
~
Z
1
170
~
rn
iii
5
150
;:)
0
0(
Y
0(
::iii
300
225
....I
....I
~
(J
61NA
w
Q
±250
5-12
....;:)
!:i0
....
;:)
rn
a:
,!!!
I&.
::i
rn
II.
a: :;
w
~
-
II.
7-40
9.5-40
II.
II.
~
y
t Low-level voltage varies with UVLO value.
Fixed 9-V output.
[!?
;:)
~
>
S-4r
~~
W
W
a:
a:
;:)
>
(J
~
w
CJ
0
~
m~d
~
~
a:
(J
!3(1).
6Q
N
:t:
00
.TYPE
[!?
....a:
z
~z
:em
=i~
OUTPUTS
~
)-
rn
~
w
~
w
~
;:)
Q
TL494.494M
SG2524
-
TL594
TL598.598M
TL1451A
TL1454
TL5001
1
1
Y
1!A723
1
1
Y
TPS6734
1
1
Y
UC284X
1
1
Y
1
TL496C
1
-
1
1
TL497A
UC384X
TL499A
C
"tJ
"tJ
!<
o
o
~
:l3
o
rr-
m
:l3
CJ)
SELECTION GUIDE
OPTOISOLATORS
optoisolators
DEVICE
VISO
(PEAK)
(kV)
LEDVFt
(MAX)
(V)
VCE(SAT)
(MAX)
(V)
RISE TIME
(TYP)
(IJ.S)
FALL TIME
(TYP)
(I1S )
BASE
CONNECTION
CTR(MIN)
(%)
PACKAGE
4N25
2.5
1.5
0.5
2:1=
2:1=
Yes
20
6 Pin DIP
4N26
1.5
1.5
0.5
2:1=
2:1=
Yes
20
6 Pin DIP
4N27
1.5
1.5
0.5
2:1=
2:1=
Yes
10
6Pin DIP
4N2B
0.5
1.5
0.5
2:1=
2:1=
Yes
10
6 Pin DIP
4N35
3.5
1.5
0.3
10
10
Yes
100
6 Pin DIP
4N36
2.5
1.5
0.3
10
10
Yes
100
6 Pin DIP
4N37
1.5 .
1.5
0.3
10
10
Yes
100
6Pin DIP
6N135
3
1.7
0.4
1
0.7
Yes
7
BPin DIP
6N136
3
1.7
0.4
0.6
0.6
Yes
19
BPin DIP
HCPL4502
3
1.7
0.4
0.6
0.6
No
19
BPin DIP
MCT2
1.5
1.5
0.4
5:1=
5:1=
Yes
20
6 Pin DIP
MCT2E
3.5
1.5
0.4
5:1=
5:1=
Yes
20
6 Pin DIP
TIL191
3.5
1.4
0.4
6
6
No
20
4 Pin DIP
TIL191A
3.5
1.4
0.4
6
6
No
50
4 Pin DIP
TIL191B
3.5
1.4
0.4
6
6
No
100
4 Pin DIP
TIL192
3.5
1.4
0.4
6
6
No
20
BPin DIP
TIL192A
3.5
1.4
0.4
6
6
No
50
B Pin DIP
TIL192B
3.5
1.4
0.4
6
6
No
100
BPin DIP
,
TlL193
3.5
1.4
0.4
6
6
No
20
TIL193A
3.5
1.4
0.4
6
6
No
50
16Pin DIP
TlL193B
3.5
1.4
0.4
6
6
No
100
16 Pin DIP
16 Pin DIP
tAt 10 mA
:1= Phototransistor operation
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
1-15
SELECllON GUIDE
OPTOISOLATORS
optoisolators with triac output
1FT
dv/dt
(MAX)
(rnA)
(TYP)
(VI/ls)
VTM
(MAX)
(V)
1.5
30
12
3
250
1.5
15
12
3
250
6 Pin DIP
1.5
10
12
3
250
6 Pin DIP
VISO
(PEAK)
(kV)
LEDVF
(MAX)
MOC30P9
7 ..5
MOQ3010
7.5
MOC3011
7.5
DEVICE
VDRM
(V)
PACKAGE
6 Pin DIP
MOC3012
7.5
1.5
5
12
3
250
6 Pin DIP
MOC3020
7.5
1.5
30
100
3
400
6 Pin DIP
MOC3021
7.5
1.5
15
100
3
400
6Pin DIP
MOC3022
7.5
1.5
10
100
3
400
6 Pin DIP
MOC3023
7.5
1.5
5
100
3
400
6 Pin DIP
TIL3009
3.5
1.5
30
12
3
250
6 Pin DIP
TlL3010
3.5
1.5
15
12
3
250
6 Pin DIP
TIL3011
.3.5
1.5
10
12
3
250
6 Pin DIP
TIL3012
3.5
1.5
5
12
3
250
6 Pin DIP
TIL3020
3.5
1.5
30
100
3
400
6 Pin DIP
TIL3021
3.5
1.5
15
100
3
400
6 Pin DIP
TIL3022
3.5
1.5
10
100
3
400
6 Pin DIP
TIL3023
3.5
1.5
5
100
3
400
6 Pin DIP
~TEXAS
INSTRUMENTS
1-16
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
SERIES REGULATORS
Bias Current
The operating current of the device; the difference between input and output current. This current is usually the
current that flows in the ground or reference terminal of the regulator and may be load dependent. Also referred
to as quiescent current.
Current-Limit Sense Voltage
A voltage proportional to the load current that controls the current-limit circuitry.
Dropout Voltage
The input-to-output differential voltage at which the circuit ceases to regulate against further reductions in input
voltage.
Feedback Sense Voltage
A voltage proportional to the output voltage that controls the regulator.
Input Regulation (Line Regulation)
The change in output voltage due to a change in input voltage, often expressed as a percentage of the output
voltage.
Low Dropout Regulator (LDO)
A voltage regulator that can operate with an input-to-output differential voltage that is lower than the typical
series regulator (approximately 2 V). Operation at lower differential voltages allows for the use of lower voltage
inputs and better efficiency.
Output Noise Voltage
The RMS output voltage with constant output current and constant input voltage, often expressed as a
percentage of the output voltage. Output noise voltage is always specified over a given range of frequencies.
Output Impedance
The ratio of the change in output voltage to the change in output current during normal operation. A lower value
indicates better regulation of the output voltage. Output impedance is a function of frequency; at f=O, this
becomes output resistance.
Output Regulation (Load Regulation)
The change in output voltage due to a change in load current, often expressed as a percentage of the output
voltage.
Output Voltage Change With Temperature
The change in the output voltage due to a change in temperature, often expressed in parts per million per °c.
Output Voltage Long-Time Drift
The change in output voltage over a given long period of time, such as 100 hours or one year.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-17
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Peak Output Current
The maximum output current that can be obtained from the regulator due to the limits of the circuitry within the
regulator.
Reference Voltage
The voltage (usually fixed) that is compared with the feedback voltage to control the regulator. The output
tolerance of the regulator is determined primarily by the tolerance of this voltage.
Ripple Rejection
The ratio of the peak-to-peak input ripple voltage to the peak-to-peak output ripple voltage, usually expressed
in dB. This is the reciprocal of ripple sensitivity. Ripple rejection is a function of frequency and typically decreases
as frequency increases.
Ripple Sensitivity
The ratio of the peak-to-peak output ripple voltage to the peak-to-peak input ripple voltage usually expressed
in dB. This is the reCiprocal of ripple rejection.
Series Regulator
A circuit that regulates the output voltage by controlling the impedance of an active device, operating in a linear
mode, in series with the output.
Short-Circuit Output Current
The output current of the regulator with the output shorted to ground.
Standby Current
The input current drawn by a regulator, with a shutdown or enable terminal, when the output voltage is disabled
and with no reference voltage load.
Temperature Coefficient of Output Voltage (ocVIO)
The average value of the ratio of the change in output voltage to the change in temperature over the total
temperature range, often expressed as parts per million per cC.
~TEXAS
1-18
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
SHUNT REGULATORS
Anode
The terminal of the regulator from which load current flows when the regulator is biased for regulation.
Cathode
The terminal of the regulator that sinks external load current when the regulator is biased for regulation.
Dynamic Impedance (ZKM
The ratio of a change in voltage across the regulator to the corresponding change in current through the
regulator when biased for regulation. This is a function of frequency; at f=O, this becomes dynamic resistance.
Noise Voltage (Vn)
The RMS output voltage with constant output current and constant input voltage, often expressed as a
percentage of the output voltage. Output noise voltage is always specified over a given range of frequencies.
Reference Input Voltage (Vref) (of an adjustable shunt regulator)
The voltage at the reference input terminal with respect to the anode terminal.
Regulator Current (Iz)
The allowable range of dc current through the regulator when it is biased for regulation.
Regulator Voltage (Vz)
The dc voltage from cathode to anode of the regulator.
Shunt Regulator
A device that has a voltage-current characteristic similar to that of a voltage-regulator diode. The device controls
the output voltage by sinking excess current, flowing through a series resistance, away from the load. It is
normally biased to operate in a region of low differential resistance (corresponding to the breakdown region of
a regulator diode) that varies so as to control the voltage across the device to a constant value.
Temperature Coefficient of Reference Voltage (oNred
The ratio of the average change in reference voltage to the change in temperature over the total temperature
range. This value can be stated in parts per million per °C (ppm/°C) or as a percentage of the reference voltage.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-19
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
SWITCHING REGULATORS
Bode Plot
A design aid used to visualize a transfer function consisting ota logarithmic horizontal scale for frequency and
a linear vertical scale for gain in dB or phase in degrees.
Charge Pump
A converter topology that uses the transfer of charge through one or more capacitors to generate an output
voltage that is higher tha,n the input voltage.
CSA
Canadian Standards Association, an independent organization that establishes and tests safety standards for
electronic systems and components in Canada.
Compensation Network
The components connected around the error amplifier of a switching regulator which tailor the frequency
response of the control loop. The compensation network reduces phase shift around the control loop so as to
achieve sufficient phase margin for stability.
Conditionally Stable
Description of a control loop that has a phase shift of 360° at some frequency less than the unity-gain 'frequency,
but has a phase shift of less than 360° at unity gain. This loop oscillates when the gain is reduced to unity at
the frequency where the phase shift is 360°. A reduction in gain is possible at startup, under abnormal load
conditions, or as the components age.
Continuous Mode
A conduction mode in which current in the inductor or transformer of the converter flows during the entire cycle.
Converter (dc-dc)
A network of reactive components and switching elements that transforms power from one dc voltage level to
another. The circuit mayor may not provide isolation from the input to the output.
Crossover Frequency
The frequency at which the loop response of the regulator drops to unity gain (0 dB). Also known as the
unity-gain bandwidth of the converter or unity-gain frequency. This frequency determines the response time for
transient recovery.
Cross Regulation
The change in output voltage of one output of a multiple output power supply caused by a load change on
another output; usually expressed in percent.
Crow Bar Circuit
A protection circuit the prevents excessive output voltage from reaching the load by shorting the output to
ground. Typically, a crow bar circuit employs an semiconductor-controller rectifier (SCR) to short the output to
ground and a series fuse to break the circuit before the regulator is damaged.
~TEXAS
1-20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Current-Mode PWM Control
A PWM control technique consisting of two feedback loops; an inner loop that senses the inductor current and
an outer loop that senses the output voltage and is used as a reference for the inner loop control. Current-mode
control improves the stability of the control loop of many converter topologies, and provides various other
benefits such as pulse-by-pulse current limiting.
Dead Time
A fixed, load-independent off-time between output pulses of a switching regulator, sometimes referred to as
blanking time. Dead time control is employed to limit the maximum duty cycle of a converter to prevent damage
caused by such occurrences as crossover conduction.
Discontinuous Mode
A conduction mode in which current in the inductor or transformer of the converter drops to zero and remains
at zero for a finite period of time during each cycle.
Duty Cycle
The ratio of on-time of the switching element to the operating period of this element.
Dynamic Response (Transient Response)
Output voltage change that occurs in response to a step change in load current or line voltage.
Efficiency
Ratio of the total output power divided by the total input power of a power supply, usually expressed as a
percentage and measured at full-rated load current and at nominal input voltage.
ESL
Equivalent Series Inductance, the parasitic inductance in series with the ideal capacitance within a real
capacitor.
ESR
Equivalent Series Resistance, the paraSitic resistance in series with the ideal capacitance within a real capacitor,
originating from the lead resistance, terminal losses, etc.
Faraday Shield
An electrostatic shield within transformers that reduces both coupling capacitance between windings and output
common-mode noise. This shield is placed between the primary and secondary windings.
(Input Voltage) Feedforward Compensation
A technique to increase the loop response to supply voltage changes by contrOlling the ramp level as a function
of the input voltage.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-21
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Gain Margin
The amount that loop gain is reduced below zero dB at the frequency where there is exactly 360° of phase shift
around the control loop. This is the amount of gain that would need to be added to the loop in order for it to
oscillate.
Holdup Time
The period of time that a power supply output voltage remains within its specified operating conditions after loss
of input power.
Input Transient (Line Transient)
A voltage spike or step change in the input of a power supply.
Inverter
A type of switching converter that accepts dc input power and changes it to ac power.
Line Transient
See input transient.
Load Regulation
The dc change in output voltage caused by a change in output load, often express as a percentage of the
nominal output voltage.
Loop Response
The frequency response of the regulator, often expressed as a Bode plot. The total loop response is the
small-signal, open-loop transfer function around the control loop and is determined by the total gain and the
phase shift of the output filter, output sensing network, error amplifier (with its compensation network), and the
power modulator stage.
Off-Line Power Supply
A power supply that operates directly from the ac mains. The input voltage is rectified and filtered to a high dc
voltage before any isolation transformer.
Output Regulation
See load regulation.
Overcurrent Protection
A protection circuit that prevents damage to the regulator by sensing an overcurrent condition and limiting
excessive current flow or shutting down the regulator.
Overvoltage
A condition in which the output voltage magnitude is greater than the maximum specified limit. For both positive
and negative regulators, the voltage is farther away from zero.
~TEXAS
1-22
(
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Output Impedance
The ratio of the change in output voltage to the change in output current during normal operation. A lower value
indicates better regulation of the output voltage. Output impedance is a function of frequency; at f=O, this
becomes output resistance.
Parallel Operation
A multiple output switching configuration in which two or more output stages supply power to the same load
simultaneously. This configuration is used when one supply cannot meet the power demands of the load or for
redundancy in case of failure of one supply.
Phase Margin
The difference between the phase shift around the control loop at the unity gain frequency and 360°. When the
phase shift is less than 360°, the phase margin is positive. Generally, at least 45° of phase margin is needed
to ensure stability over manufacturing variations and to reduce overshoot.
Pole
A point where the open-loop transfer function of the control loop asymptotically approaches infinity as a result
of a term in the denominator approaching zero. A frequency breakpoint of the loop response that causes 20 dB
per decade reduction in gain and a shift of 90° in phase margin.
Post Regulator
A circuit-on the output of the power supply that improves the output regulation and/or reduces ripple or noise.
Power Factor Correction (PFC)
A design technique the changes the input current waveform of a power supply from a pulsed waveform (the
result of charging the input capacitor) to a sinusoidal waveform that reduces EMI injected into the source. Power
factor is proportional to the percentage of time during the cycle that current flows in the input. A power factor
of 1 indicates a sine wave input, while a value less than 1 indicates the presence of harmonic current in the input
circuit.
Power Good Signal
A signal generated within a power supply to indicate th,at the output of the supply is operating within its specified
tolerances.
Power Modulator Stage
The section of the regulator that processes the power from one dc level to another dc level. This includes the
comparator that converts the error signal to pulse width information, the power switch, and the
transformerlinductor.
Power Modulator Gain
The small-signal gain of the power modulator stage. Because the modulator is a switched circuit, state-space
averaging techniques are required to derive its gain, but the gain can be approximated as the maximum change
in output voltage divided by the maximum change in ramp voltage, usually expressed in dB.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1-23
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Pulse-Width-Modulation (PWM) Control
A switching regulator technique in which regulation is accomplished by changing the duty cycle of the power
switch.
Push-Pull Operation
A dual output switching configuration in which two power switches conduct alternately.
Ramp
The output voltage of the oscillator stage of a voltage-mode controller that is compared to the error signal in the
comparator to generate the duty cycle control signal. The peak-to-peak level of the ramp determines the gain
of the modulator stage.
Remote Sensing
A design technique to reduce output-voltage error induced by the impedance of the output-load cables by
including the load cables within the feedback loop. This is done by connecting sepa:rate voltage sensing cables
at the load that do not carry any load current.
Resonant Mode
A control technique that regulates the output by controlling the operating frequency while turning off the power
switch when the current through it (ZCS) or the voltage across it (ZVS) is zero.
Right-Half-Plane Zero
A frequency breakpoint of the loop response that causes the gain to rise 20 dB per decade but causes the phase
to fall 90°. This phenomenon is present in continuous-mode boost and flyback converters and is extremely
difficult to compensate for.
Single-Ended Operation
A single output switching configuration.
Soft Start
A protection circuit that prevents current surges during power up and protects against false signals that might
be generated by the control circuit when power is applied.
SMPS
Switch-mode power supply. Any of a class of power converters that control the output voltage by switching the
input voltage.
Synchronous Rectification
A design technique to increase converter efficiency by reducing the conduction losses in the commutation
rectifier of a converter. This is typically done by replacing the diode with a transistor that is turned on when the
rectifier would be expected to conduct.
~1EXAS
1-24
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Temperature Coefficient
The average change in a parameter, such as output voltage, per degree of temperature change, usually
expressed as a percentage over the specified temperature range or ppm/°C.
Transient Recovery Time
The time required for the output of a power supply to settle back into its specified tolerance range after a step
change in load current or line voltage. This is also called settling time.
Transient Response
The response of the converter to step changes in load or line variations.
TUV
Technischer Uberwachungs-Verin, a German organization approved for testing products' to VOE standards.
UL
Underwriters Laboratories, the U.S. independent organization that conducts safety testing of products to
established standards.
Unconditionally Stable
Description of a control loop that generally does not oscillate under any line/load conditions or when the loop
gain is reduced. An unconditionally stable loop has less than 360° of phase shift for all frequencies less than
or equal to unity-gain frequency.
Undervoltage
A condition in which the output voltage magnitude is less than the minimum specified limit. For both positive and
negative regulators, the voltage is closer to zero.
Undervoltage Lockout (UVLO)
A protection circuit that prevents switching outputs from turning on until a certain supply voltage threshold is
reached so as to prevent excessive dissipation on the switches and possible damage to the circuit.
Variable Frequency Control
A switching regulation technique in which a fixed output on-time or off-time is maintained. Regulation is
accomplished by changing the output frequency to vary the duty cycle.
voe
Verband Deutscher Elektrotechniker, the German organization that sets standards for product safety and noise
emissions and also tests and certifies products to those standards.
Voltage-Mode Control
A PWM control technique consisting of a single feedback loop that controls the output voltage by comparing it
to a fixed reference voltage.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
1-25
GLOSSARY
VOLTAGE REGULATOR TERMS AND DEFINITIONS
Zero
A point where the open-loop transfer function of the control loop approaches zero as a result of a term in the
numerator approaching zero. A frequency breakpoint of the .loop response where the gain rises 20 dB per
decade and a 90° rise in the phase margin.
~TEXAS
1-26
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-1
Contents
LM185-1.2
LM285-1.2
LM385-1.2
LM385B-1.2
LM185-2.5
LM285-2.5
LM385-2.5
LM385B-2.5
LM236-2.5
LM336-2.5
LT1004-1.2
LT1004-2.5
LT1009
2-2
Page
Micropower Voltage Reference ............................ 2-3
Micropower Voltage Reference ............................ 2-3
Micropower Voltage Reference ............................ 2-3
Micropower Voltage Reference ............................ 2-3
Micropower Voltage Reference ........................... 2-11
Micropower Voltage Reference ... ; ....................... 2-11
Micropower Voltage Reference ........................... 2-11
Micropower Voltage Reference ........................... 2-11
2.5-V Integrated Reference Circuit ....................... 2-21
2.5-V Integrated Reference Circuit ....................... 2-21
Micropower Integrated Voltage Reference ............... 2-27
Micropower Integrated Voltage Reference ............... 2-27
2.5-Vlntegrated Reference Circuit ....................... 2-39
LM185-1.2, LM285-1.2, LM385-1.2, LM385B-1.2, LM385V-1.2
MICROPOWER VOLTAGE REFERENCES
- APRIL 1989 - REVISED AUGUST 1995
• Operating Current Range
- LM185 ••• 10 ~A to 20 mA
- LM285 ••• 10 ~A to 20 mA
- LM385 ... 15 ~A to 20 mA
- LM385B .•• 15 ~ to 20 mA
• 1% and 2% Initial Voltage Tolerance
• Reference Impedance
- LM185 ••. 0.6 Q Max at 25°C
- LM385 ••• 1 Q Max at 25°C
- All Devices •.. 1.5 Q Max Over Full
Temperature Range
• Very Low Power Consumption
• Applications:
- Portable Meter References
- Portable Test Instruments
- Battery-Operated Systems
- Current-Loop Instrumentation
- Panel Meters
• Designed to be Interchangeable With
National LM185-1.2, LM285-1.2, and
LM385-1.2
u
DPACKAGE
(TOP VIEW)
NC
8 CATHODE
NC27NC
NC3
eNC
ANODE 4
5 NC
LPPACKAGE
(TOP VIEW)
ANODE
CATHODE
NC
NC-No internal connection
symbol
ANODE
*1--
--11
..
CATHODE
description
These micropowertwo-terminal band-gap voltage references operate over a 1O-~ to 20-mA current range and
feature exceptionally low dynamic impedance and good temperature stability. On-Chip trimming provides tight
voltage tolerance. The LM 185-1.2 series band-gap reference has low noise and long-term stability.
The LM185-1.2 series design makes the devices exceptionally tolerant of capacitive loading and thus easier
to use in most reference applications. The wide dynamic operating temperature range accommodates varying
current supplies with excellent regulation.
The extremely low-power drain of the LM185-1.2 series makes them useful for micropower circuitry. These
voltage references can be used to make portable meters, regulators, or general-purpose analog circuitry with
battery life approaching shelf life. The wide operating current range allows them to replace older references with
tighter-tolerance parts.
The LM185-1.2 is characterized for operation over the full military temperature range of -55°C to 125°C. The
LM285-1.2 is characterized for operation from -40°C to 85°C. The LM385-1.2 and LM3858-1.2 are
characterized for operation from O°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICEst
TA
Vz
TOLERANCE
PLASTIC
(LP)
2%
LM3850-1.2
LM385Lp·1.2
1%
LM385BO·1.2
LM385BLP-1.2
-40°C to 85°C
1%
LM2850-1.2
LM285LP-1.2
-55°C to 125°C
1%
LM1850-1.2
LM185LP-1.2
O°C to 70°C
t
SMALL OUTLINE
(D)
CHIP FORM
(V)
LM385Y-1.2
For ordering purposes, the deCimal pOint In the part number must be replaced With a hyphen (I.e., show
the -1.2 suffix as "-1-2").
The 0 package is available taped and reeled. Add the suffix R to the device type (e.g., LM3850R-1-2).
The chip form is tested at TA = 25°C.
PROOUC11ON DATA information Is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processlng does not necessarily include
testing of aU parameters.
'~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-3
LM18S-1.2, LM28S-1.2, LM38S-1.2, LM38SB-1.2, LM38SY-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS075B - APRIL 1989 _ REVISED AUGUST 1995
schematic
rr---------~~~~--~----~._------~
__--------e_------~~------CATHODE
7.5kO
200kO
50kO
300kU
20pF
e _ - - - - I Q9
100kO
5000
60kU
L---~~------------~----~~------~----------~------~~--~--ANODE
NOTE A: Component values shown are nominal.
absolute maximum ratings over operating free-air temperature ranget
Reverse current, IR ...................................................................... 30 rnA
Forward current, IF ........................................................................ 10 mA
Operating free-air temperature range, TA: LM185-1.2 ................................ -55°e to 125°e
LM285-1.2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40oe to 85°e
LM385-1.2, LM3858-1.2 ........................ ooe to 70 0 e
Storage temperature range, Tstg .................................................. -65°e to 1500 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260 0 e
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabil~.
recommended operating conditions
MIN
MAX
0.01
20
LM185-1.2
-55
125
LM285-1.2
-40
85
0
70
Reference current, IZ
Operating free-air temperature range, TA
LM385-1.2, LM3858-1.2
~TEXAS
2-4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UNIT
rnA
°C
LM18S-1.2, LM28S-1.2, LM385-1.2, LM38SS-1.2, LM38SY-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS075B - APRIL 1989 - REVISED AUGUST 1995
LM385Y-1.2 chip information
This chip, when properly assembled, displays characteristics similar to the LM385-1.2 (see electrical tables).
Thermal compression or ultrasonic bonding can be used on the doped aluminum bonding pads: The chip can
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
ANODE
(1)
_-t~~]rl--_ CATHODE
(2)
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
=
TJmax 150°C
TOLERANCES ARE ± 10%.
ALL DIMENSIONS ARE IN MILS.
TERMINAL NUMBERS APPLY
TO LP PACKAGE ONLY
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-5
If)
CJ)
PARAMETER
TEST
CONDITIONS
TAt
Vz
Reference voltage
IZ= I min to 20 mA'l:
25°C
avz
Average temperature coefficient of reference
voltage§
.
IZ= I min to 20 rnA:!:
.25°C
Iz=lmint01 rnA:!:
tNz
Change in reference voltage with current
IZ=1 mAt020mA
...
~-~
~~
~~d
!t:~
.
~
/!NZ/l1t
Long-term change in reference voltage
Izmin
Minimum reference current
Zz
Reference impedance
IZ = 100 JlA,
f=25Hz
Vn
Broadband noise voltage
IZ = 100 JlA,
f=10Hztol0kHz
IZ= 100JlA
LM385-1.2
UNIT
MIN
TYP
MAX
MIN
TVP
MAX
MIN
TYP
MAX
1.223
1.235
1.247
1.21
1.235
1.26
1.223
1.235
1.247
±20
±20
±20
1
Full range
1.5
1.5
1.5
25°C
12
20
20
25°C
25°C
±20
8
10
8
0.2
0.6
0.4
Full range
25°C
30
30
±20
1.5
60
8
1
0.4
1.5
60
Full range is -55°C t6 125°C for the LM185-1.2, -40°C to 85°C for the LM285-1.2, and O°C to}O°C for the LM385-1.2 and LM385B-l.2.
:!: I min = 10 JlA for the LM185-1.2 and LM285-1.2. Imin = 15 JlA forthe LM385-1.2 and LM385B-l.2.
§ The average temperature coefficient of reference voltage is defined as the total change in reference voitage divided by the specified temperature range .
>
-0
:D
~
<0
15
1
I
:D
m
S
CJ)
m
<::1
mV
>
c:
G)
I
c:
If)
-I
ppmlkhr
1.5
60
F
V
30
±20
15
I
ppml"C
1
Full range
UI
[Jl
LM385B-1.2
1
Full range
t
0
LM185-1.2
LM285-1.2
25°C
~
< s::r-s::
(')
..
electrical characteristics at specified free-air temperature
%
JlA
n
JlV
;D
~
:::UO)
OC('
-0 . .
O~
~m,r-
:OS::
N
<0)
r,"
oC('
~~
C)rms::
:oW
m'O)
'TIC('
m::-'"
:::UN,
mZr(')S::
mW
m
cnm
..
•
~
r-
s::
W
~rn
j~
..
0)
c.n
~~
~
-f.
~
-
-
LM185-1.2, LM285-1.2, LM385-1.2, LM385B-1.2, LM385Y-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS0758 - APRIL 1989 - REVISED AUGUST 1995
electrical characteristics, TA = 25°C
TEST CONDITIONS
PARAMETER
Vz
Reference voltage
IZ= 15 j.lAto 20 mA
CJ.VZ
Average temperature coefficient of reference voltage t
IZ = 15 J.lA to 20 mA
I'NZ
Change in reference voltage with current
TYP
MAX
1.21
1.235
1.26
Long-term change in reference voltage
Minimum reference current
zz
Reference impedance
IZ= 100j.lA
Broadband noise voltage
IZ= 100j.lA,
f= 10 Hz to 10 kHz
IZ", 100J.lA
V
1
mV
IZ = 1 mA to 20 mA
IZmin
UNIT
ppm/oC
±20
IZ = 15 J.lA to 1 mA
t!.VZlt!.t
Vn
LM385Y-1.2
MIN
20
±20
ppm/khr
8
15
0.4
1
60
J.lA
Q
j.lV
. .
..
.. of reference voltage IS defined as the total change In reference voltage divided
t The average temperature coefficient
by the specified temperature
range.
~TEXAS
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-7
LM185-1.2, LM285-1.2, LM385-1.2, LM385B-1.2, LM385Y-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS075B ':'APRIL 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REVERSE CURRENT
100
REFERENCE VOLTAGE CHANGE
vs
vs
REVERSE VOLTAGE
REVERSE CURRENT
16
I
I
~I
TA = -55°C to 125°C
T~ ~ ~~~~ to ~i5!6
11
cc
~
i
I
J
V
10
G
S
~
VV
a:
I
5-
0.1
o
/
0.2
0.4
/
V
V
f.--f-
1--"'' '
0.6
0.8
1.2
-4
0.01
1.4
0.1
VR - Reverse Vohage - V
Figure.1
I
100
Figure 2
FORWARD VOLTAGE
1.2
10
IR - Reverse Current - mA
REFERENCE VOLTAGE
vs
vs
FORWARD CURRENT
FREE-AIR TEMPERATURE
1.245
III~
TA=25°
,
V
>
I
~
I
GI
CD
0.8
~
1--"'1-'
~
'E
~
~ 1.235
e3
I-
~
I
IL
1.24
>
V
oil
a:
0.4
~
"'"
1.23
I
N
>
- r---.
V r--
>
1.225
o
0.01
0.1
10
100
1.220
-55 -35 -15
IF - Forward Current - mA
5
25
45
65
85
105 125
TA - Free-Air Temperature - °C
Figure 3
Figure 4
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
2-8
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
LM18S-1.2, LM28S-1.2, LM38S-1.2, LM38SB-1.2, LM38SY-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS075B -APRIL 1989 - REVISED AUGUST 1995
TYPICAL CtlARACTERISTICSt
NOISE VOLTAGE
REFERENCE IMPEDANCE
vs
vs
REFERENCE CURRENT
FREQUENCY
100
700
I 11111111
IZ = 100l1A
600 -TA=25°C
f=25Hz
TA -55°C to 125°C
=
c:
.,...
I
I:
til
10
'1:1
1\
.5.,
500
.,
400
:>I:
1\
8.
~
I
Cl
I
"I'
'"-
~
...
I:
~
.,
l!!
.,
.S!
r--...
300
In
'0
a:
Z
"'",
I
~
I
200
\
-:f
100
1',
o
0.1
0.01
0.1
10
10
100
"
100
1k
10 k
100 k
f - Frequency - Hz
IZ - Reference Current - mA
Figure 6
Figure 5
OUTPUT NOISE VOLTAGE
vs
TRANSIENT RESPONSE
CUTOFF FREQUENCY
70
~O~ ~~
1
Iz =
TA = 25°C
60
>::t
.,
I
50 -
Cl
~
~
.,
.!!!
40 -
Z
30
0
'5
~
0
A
I 111111I
RC Low Pass
>
I IIIII
I
/ ' """
100I1A
.,
1----+--->"/'---....1 36 lin '--_'_\r-+-_ _--1
In
Cl
~
~
~ O. 5
'5
a.
'S
C
I
-::-
0
'1:1
/
20
I
Output
1. 5
I:
til
r-_~Vr--V-'~-V-O-r---,
0
<
'5
a.
.5
10
o
l/ ....
0
10
f - Cutoff Frequency - kHz
100
Figure 7
t
v
Input
"
0.1
A
5
A
0
100
t - Time-115
500
600
FigureS
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-9
LM18S-1.2, LM28S-1.2, LM38S-1.2,LM38SB-1.2, LM38SY-1.2
MICROPOWER VOLTAGE REFERENCES
SLVS075B - APRIL 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
+
Mercury Cell _
1.345V -
R 2.00kO±1%
100kn±1%
w
SOOO
LM385-1.2
+
TypeK
Meter
t Adjust for 11.15 mV at 25°C across 953 0
f Adjust for 12.17 mV at 25°C across 412 0
Figure 9. Thermocouple Cold-Junction Compensator
V+ 2.3 V sV+ s 30 V
9V
499kO
'""---r-.......
R
1.2V
2.74kO
_.._------4__ 1.2 V
LM385-1.2
Figure 11. Reference From a 9-V Battery
Figure 10. Operation Over a
. Wide Supply Range
~1ExAs
2-10
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TExAs 75265
LM185-2.5, LM285-2.5, LM385-2.5, LM385B-2.5, LM385Y-2.5
MICROPOWER VOLTAGE REFERENCES
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
• Operating Current Range .•. 20 ~A
to 20 mA
• 1.5% and 3% Initial Voltage Tolerance
• Reference Impedance
- LM185 .•. 0.6 n Max at 25°C
- LM385 ... 1 n Max at 25°C
- All Devices ••• 1.5 n Max Over Full
- Temperature Range
• Very Low Power Consumption
• Applications:
- Portable Meter References
- Portable Test Instruments
- Battery-Operated Systems
- Current-Loop Instrumentation
- Panel Meters
• Designed to be Interchangeable With
National LM185-2.5, LM285-2.5, and
LM385-2.5
o PACKAGE
u
(TOP VIEW)
NC
8 CATHODE
NC27NC
NC3
eNC
ANODE 4
S NC
LPPACKAGE
(TOP VIEW)
ANODE
CATHODE
NC
NC-No internal connection
symbol
ANODE
description
--".~I--
CATHODE
These micropowertwo-terminal band-gap voltage references operate over a 20-~ to 20-mA current range and
feature exceptionally low dynamic impedance and good temperature stability. On-Chip trimming provides tight
voltage tolerance. The LM185-2.5 series band-gap reference has low noise and long-term stability.
The LM185-2.5 series design makes these devices exceptionally tolerant of capacitive loading and thus easier
to use in most reference applications. The wide dynamic operating temperature range accommodates varying
current supplies with excellent regulation.
The extremely low power drain of the LM185-2.5 series makes them useful for micropoiNer circuitry. These
voltage references can make portable meters, regulators, or general-purpose analog circuitry with battery life
approaching shelf life. The wide operating current range allows them to replace older references with tighter
tolerance parts.
The LM385-2.5 and LM385B-2.5 are characterized for operation from O°C to 70°C. The LM285-2.5 is
characterized for operation from -40°C to 85°C. The LM185-2.5 is characterized for operation over the full
military temperature range of -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICEST
TA
Vz
TOLERANCE
PLASTIC
(LP)
CHIP FORM
(Y)
LM38SD-2.S
LM38SLP-2.S
1.S%
LM38SBD-2.S
LM38SBLP-2.S
_40°C to 8SoC
1.S%
LM28SD-2.S
LM28SLP-2.S
-SsoC to 12SoC
1.S%
LM18SD-2.S
LM18SLP-2.S
O°Cto 70°C
3%
SMALL OUTLINE
(D)
LM38SY-2.S
t
For ordenng purposes, the decimal point In the part number must be replaced With a hyphen (I.e., show
the -2.S suffix as "-2-S").
The D package is available taped and reeled. Add the suffix R to the device type (e.g., LM38SDR-2-S).
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-11
LM185-2.5~ LM285-2.5, LM385-2.5, LM385S-2.5, LM385Y-2.5
MICROPOWER VOLTAGE REFERENCES
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
schematic
r---------~~----~~----_.--------_.~~----~--------~----_.-----
CATHODE
600 k.Q
7.S k.Q
soon
soon
100kn
L-__
~
____________
~~
soon
60 k.Q
____
~
________
~
__
~
____
~
________
~
____
~_____
ANODE
NOTE A: All component values shown are nominal.
absolute maxim!Jm ratings over operating free-air temperature ranget
Reverse current, IR .......................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Forward current, IF ........................................................................ 10 mA
Operating free-air temperature range, TA: LM185-2.5 ................................ -55°C to 125°C
LM285-2.5 .................................. -40°C to 85°C
LM385-2.5, LM385B-2.5 ........................ O°C to 70°C
Storage temperature range, Tstg ................................. :................ -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds .............................. 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent darY)age to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute·maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
MIN
MAX
0.02
20
LMI85-2.5
-55
125
LM285-2.5
-40
85
0
70
Reference current, IZ
Operating free-air temperature range, TA
LM385-2.5, LM385B-2.5
~TEXAS
INSTRUMENTS
2-12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
mA
°C
LM185-2.5, LM285-2.5, LM385-2.5, LM385B-2.5, LM385Y-2.5
MICROPOWER VOLTAGE REFERENCES
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
LM385Y-2.5 chip information
This chip, when properly assembled, displays characteristics similar to the LM385-2.5 (see electrical tables).
Thermal compression or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
ANODE
(1)
-::
-::
_-t~~]rl-- CATHODE
(2)
CHIP THICKNESS:
15 MILS TYPICAL
-::
-::
-::
BONDING PADS:
4 x 4 MILS MINIMUM
-::
-::
TOLERANCES ARE ±10%.
TJmax = 150°C
ALL DIMENSIONS ARE IN MILS.
TERMINAL NUMBERS APPLY
TO LP PACKAGE ONLY
-::
-::
-::
-::
-::
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-13
2:
PARAMETER
Vz
Reference voltage
avz
Average temperature coefficient of
reference voltage:j:
TEST CONDITIONS
IZ = 20 jlA to 20 rnA
IZ= 20 jlA to 20 mA
IZ=20jlAtol rnA
AVZ
Change in reference voltage with current
IZ= 1 jlA to 20 mA
~
AVzjAt
Long-term change in reference voltage
IZ(min)
Minimum reference current
~~d
!t:~
.~
!~
'"
i
IZ = 100 jlA
TAt
25°C
Reference impedance
IZ= 100 jlA
Vn
Broadband noise voltage
IZ = 100 jlA,
f=10Hztol0kHz
LM185-2.5
LM285-2.5
LM385-2.5
LM385B-2.5
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
2.462
2.5
2.538
2.425
2.5
2.575
2.462
2.5
2.538
V
25°C
±20
±20
±20
ppm/"C
1
2
2
Full range
1.5
2
2
25°e
_10
20
20
Full range
30
30
30
25°C
25°e
25°e
±20
±20
20
8
20
8
20
0.2
0.6
0.4
1
0.4
1
Full range
25°e
±20
8
1.5
120
1.5
z~
c:
Obi
'"0I ~m
»
120
t Full range is ooe to 700 e forthe LM385-2.5 and LM385B-2.5, -40°C to 85°e for the LM285-2.5, and -55°e to 125°C for the LM185-2.5.
:j: The average temperature coefficient of reference voltage is defined as the total. change in ~ference voltage divided by the specified1emperature range.
120
-<
i
JJ
m
:S
en
m
0
>
c:
Ii)
ppmlkhr
c:
jlA
i
Q
1.5
IlV
.....
(')
I
mV
3!!:r""
-iii:
2
JJ
Full range
Zz
'il-
~~~
~
electrIcal characteristics at specified free-air temperature
~
~
""g~
:e~
mr""
::rJiii:
N
a~
iJ>,sn
G) ....
m3!!:
::rJW
me»
'TIKI
m.
::rJ~
m,sn
zr""
(')3!!:
mw
(l)e»
U1
-f.
N
bI
LM185-2.5, LM285-2.5, LM385-2.5, LM385B-2.5, LM385Y-2.5
MICROPOWER VOLTAGE REFERENCES
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
electrical characteristics at TA = 25°C
PARAMETER
TEST CONomONS
LM385Y-2.5
MIN
2.462
TYP
MAX
2.5
2.575
Vz
Reference voltage
IZ =20!lA to 20 mA
avz
t:Nzjllt
Average temperature coefficient of reference voltage t
IZ =20!lA to 20 mA
±20
Long-term change in reference voltage
IZ=loo!lA
±20
Zz
Reference impedance
IZ= 1oo!lA
0.4
Broadband noise voltage
IZ = loo!lA.
f=10Hzto10kHz
120
Vn
UNIT
V
ppml"C
ppmlkhr
1
g
I1V
. . of reference voltage IS defined as the total change In reference voltage diVided
.. by the specified
.. temperature
t The average temperature coefficient
range.
:'I
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
2-15
LM18S-2.S, LM28S-2.S, LM38S-2.S, LM38SB-2;S, LM385Y-2.S
MICROPOWER VOLTAGE REFERENCES
SLVS023D -,JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REVERSE CURRENT
va
REVERSE VOLTAGE
100
I
REFERENCE VOLTAGE CHANGE
va
REVERSE CURRENT
16
I
T~ ~ ~~~~ to ~2~~61
TA =-55°Cto 125°C
10
0.1
I
o
~
/
0.5
.--- -
:e
I
12
f
t
8
i
4
j
V
$!
a::
I
N
",I-'
o
~
1.5
2
VR - Reverse Voltage - V
2.5
-4
3
0.01
0.1
10
IR - Reverse Current - mA
Figur~ 1
Figure 2
FORWARD VOLTAGE
va
FORWARD CURRENT
1.6
>
I
2.525
IZ = 20 IJA to 20 mA
1.4
2.52
1.2
> 2.515
I
&
:
0.8
If
0.6
...
>
2.51
$!
1!
I
REFERENCE VOLTAGE
va
FREE-AIR TEMPERATURE
T~I~~~~C
&
!
$!
!
100
fl 2.505
1/
c
I!
.;a::
l.,..o-I-'
~l--
I
~
0.4
0.2
0.1
10
IF - Forward Current - mA
100
V
2.495
2.49
2.485
o
0.01
2.5
L
i"""'
V
~
J'.
"- ~
/
2.48
-55 -35 -15 5
25 45 65 85
TA - Free·Alr Temperature - °C
Figure 3
105 125
Figure 4
t Data at high and low temperatures are applicable only within the, rated operating free-air temperature ranges of the various devices.
~TEXAS
2-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
......
LM18S-2.S, LM28S-2.S, LM38S-2.S, LM38SB-2.S, LM38SY-2.S
MICROPOWER VOLTAGE REFERENCES
SLVS023D -JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REFERENCE IMPEDANCE
REFERENCE IMPEDANCE
1000
vs
vs
REFERENCE CURRENT
FREQUENCY
10 k
f~~5IJ~1I11
I
I I
IZ = 100 J.IA
TA=25°C
TA = MIN to MArt
c:
I
8
c
.
.5
.
c:
os
8c
..
.5
..
os
\
"CI
Q.
u
1k
I
100
"CI
Q.
10
u
c
c
e
~
e
~
~r--
II:
I
./
10
I
..........
N
N
N
10
0.1
V
I-
./
0.1
0.01
100
1000
FILTERED RMS OUTPUT NOISE VOLTAGE
I
11\
VB
FREQUENCY
FREQUENCY
~ 100
I
..
11\
:ll!
~
.
~
3l
I
c
z
"$
/
\
400
>
::!i
40
V
II:
l
\
200
)~
0
III
!
20
i!
~ I--'"
o
o
100
1k
10k
100k
,...
60
t
600
10
"0:"""·
·0
'0
z
80
I I II
TA=25°C
IIII
III
800
:ll!
~
i ~O~~
120
TA = 25°C
c
..
vs
1~=ll~~I~~
'-
1000
Figure 6
NOISE VOLTAGE
l!>:
100
f - Frequency - kHz
Figure 5
1200
10
0.1
Iz - Reference Current - mA
1400
V
V
V
II:
N
0.1
0.01
100
V-
0.1
10
100
f - Frequency - kHz
f - Frequency - Hz
Figure 8
Figure 7
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
:j: For conditions shown as MIN or MAX, use the appropriate value specified under'recommended operating conditions.
"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-17
LM185-2.5, LM285-2.5, LM385-2.5, LM385B-2.5, LM385Y-2.5
MICROPOWER VOLTAGE REFERENCES.
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
TRANSIENT RESPONSE
A
v
>
J
41----+------+------;------;
I
~
I
3
/'\.
21-----H"L-- 24 kn
1
VI
.5
~V"
--+-----1
~ VO_-+_ _~
I
i
i
Output
0
<>"
5r---+-------+-l.--~y~----;
Inrt
O~----~------~--Jv~----~
o
100
500
600
t - Time-!1S
Figure 9
t Data at high and low temperatures are applicable only within the rated operating Iree-air temperature ranges 01 the various devices,
~TEXAS
2-18
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 752115
LM18S-2.S, LM28S-2.S, LM38S-2.S, LM38SB-2.S, LM38SY-2.S
MICRO POWER VOLTAGE REFERENCES
SLVS023D - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
+
3.3 kn
2 Mercury _
Cells 2.6 V -
200 k.Q ±1 %
R 2.00 k.Q ±1 %
cw
soon
LM385·2.5
+
l\'peK
Meter
tAdjust for 12.17 mV at 25°C across 412 n
Figure 10. Thermocouple Cold-Junction Compensator
V+
3.7VSV+S30V
9V
221 k.Q
2.74kn
LM38S·2.S
2.SV
Figure 12. Reference From a 9-V Battery
Figure 11. Operation Over a
Wide Supply Range
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-19
2-20
LM236-2.S, LM336-2.S, LM336Y-2.S
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS063A- NOVEMBER 1988 - REVISED AUGUST 1995
• Low Temperature Coefficient
• Wide Operating Current ••• 400
to 10 mA
DPACKAGE
(TOP VIEW)
u
I1A
NC
NC 2
NC3
ANODE 4
• 0.27-0 Dynamic Impedance
• ±1"1o Tolerance Available
• Specified Temperature Stability
• Easily Trimmed for Minimum Temperature
Drift
8 CATHODE
7 NC
sNC
5 ADJ
NC-No internal connection
• Fast Turn-On
• Three-Lead Transistor Package
LPPACKAGE
(TOP VIEW)
GJ
description
u
The LM236-2.5 and LM336-2.5 integrated circuits
are precision 2.5-V shunt regulator diodes. These
monolithic references operate as low temperature
coefficient 2.5-V zeners with a 0.2-0 dynamic
impedance. A third terminal provided on the circuit
allows the reference voltage and temperature
coefficient to be easily trimmed.
o
o
ANODE
CATHODE
ADJ
symbol
ANODE--IT-:l+L - - CATHODE
ADJ
The series are useful as precision 2.5-V
low-voltage references (Vz) for digital voltmeters,
power supplies, or operational amplifier circuitry. The 2.5-V voltage reference makes it convenient to obtain a
stable reference from 5-V logic supplies. Since the series operate as shunt regulators, they can be used as either
positive or negative voltage references.
The LM236-2.5 is characterized for operation from -25°C to 85°C. The LM336-2.5 is characterized for operation
from O°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP FORM
TA
SMALL OUTLINE
(D)
O°Cto 70°C
-25°C to 85°C
PLASTIC
(LP)
M
LM336D-2.5
LM336LP-2.5
LM33SY-2.5
LM23SD-2.5
LM236LP-2.5
-
The D package IS available taped and reeled. Add the SuffiX R to the deVICe type (I.e.,
LM336DR-2.5).
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
2-21
LM236-2.5, LM336-2.5, LM336Y-2.5
2.5-V INTEGRATED REFERENCE CIRCUITS
SLVS063A- NOVEMBER 1988 - REVISED AUGUST 1995
schematic diagram
r-------------------~~--~----~-.---CATHODE
~ ~
6.61<0
ADJ
All component values are nominal
LM336Y-2.5 chip information
This chip, when properly assembled, displays characteristics similar to the LM336-2.5 (see electrical tables).
Thermal compression or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
ANODE
(1)
___~~r___ CATHODE
=r
(2)
ADJ
(3)
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
T Jmax
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
I..
55
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'I'
~TEXAS·
2-22
INSTRUMENTS
POST OFF'CE BOX 655303 • DALLAS, TEXAS 75265
LM236-2.5, LM336-2.5, LM336Y-2.5
2.5-V INTEGRATED REFERENCE CIRCUITS
SLVS063A- NOVEMBER 1988 - REVISED AUGUST 1995
absolute maximum, ratings over operating free-air temperature range {unless otherwise noted)t
Reverse current, IR ...................................................................... 20 mA
Forward current, IF ....................................................................... 10 mA
Operating free-air temperature range, TA: LM236-2.5 ................................. -25°C to 85°C
.
LM336-2.5 .............. ,'..................... O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or LP package ............... 260°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
electrical characteristics at specified free-air temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
I LM236, LM336
I LM236A. LM336B
vz
Reference voltage
IZ=l rnA
AVZ(AT)
Change in reference
voltage with
temperature§
Vz adjusted to 2.490 V,
IZ=l rnA
AVZ(AI)
Change in reference
voltage with current
IZ = 400 jJA to 1{) rnA
AVZ(At)
Long-term change
in reference voltage
IZ= 1 rnA
Zz
Reference
impedance
IZ= 1 rnA,
f=lkHz
LM236-2.5
TA*
LM336-2.5
MIN
TYP
2.44
2.49
2.54
2.39
2.49
2.59
2.465
2.49
2.515
2.44
2.49
2.54
Full range
3.5
9
1.8
6
25°C
2.6
6
2.6
10
3
10
3
12
25°C
Full range
MAX
MIN
TYP
MAX
UNIT
V
mV
mV
ppmlkhr
25°C
20
20
25°C
0.2
0.6
0.2
1
Full range
0.4
1
0.4
1.4
n
:I: Full range is -25°C to 85°C for the LM236-2.5 and O°C to 70°C for the LM336-2.5.
§ Temperature stability (change in reference voltage with temperature) for these devices is ensured by design. Design limits are specified over the
indicated temperature and supply voltage ranges. These limits are not used to calculate outgoing quality levels.
electrical characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
Vz
Reference voltage
IZ= 1 rnA
AVZ(AI)
Change in reference voltage with current
IZ = 400 jJA to 10 rnA
AVZ(At)
Long-term change in reference voltage
IZ=l rnA
Zz
Reference impedance
IZ=l rnA,
LM336Y-2.5
MIN
TYP
MAX
2.39
2.49
2.59
2.6
10
20
f= 1 kHz
0.2
UNIT
V
mV
ppmlkhr
1
n
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-23
LM236-2.5, LM336-2.5, LM336Y-2.5
2.5-V INTEGRATED REFERENCE CIRCUITS
SLVS063A- NOVEMBER 1988 - REVISED AUGUST 1995
TYPICAl- CHARACTERISTICS
CHANGE IN REFERENCE VOLTAGE
2.5
vs
REFERENCE CURRENT·
FREQUENCY
I
TA=25°C
>
E
..
I
01
2
All
~
8c
1.5
I!!
.;a:
.5
8,
.
c
.c
U
I
N
0.5
>
--- Vo
LM236-2.5
LM336-2.5
=2.5 V
NC
Figure 3. 2.5-V Reference
Figure 5. Wide Input Range
Reference
t
Any silicon signal diode
:I: Adjust to 2.49 V
FiEJure 4. 2.5-V Reference With
Mimmum Temperature Coefficient
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-25
2-26
LT1 004C-1.2, LT1004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.2, LT1004Y-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
• Initial Accuracy
±4 mV for LT1004-1.2
±20 mV for LT1004-2.5
DPACKAGE
(TOP VIEW)
• Micropower Operation
N c u a CATHODE
NC27NC
NC 3
6 CATHODE
ANODE 4
S NC
• Operates up to 20 mA
• Very Low Reference Impedance
• Applications:
Portable Meter Reference
Portable Test Instruments
Battery-Operated Systems
Current-Loop Instrumentation
Terminals 6 and a are intemally connected.
LPPACKAGE
GJ
(TOP VIEW)
ANODE
n
description
The LT1 004 micropower voltage reference is a
two-terminal band-gap reference diode designed
to provide high accuracy and excellent
temperature characteristics at very low operating
currents. Optimizing the key parameters in the
design, processing, and testing of the device
results in specifications previously attainable only
with selected units.
o
o
CATHODE
NC
NC-No internal connection
symbol
ANODE
_-I~.l+-L_
(A)
CATHODE
(K)
The LT1004 is a terminal-for-terminal replacement for the LM185 series of references with improved
specifications. The LT1004 is an excellent device for use in systems in which accuracy was previously attained
at the expense of power consumption and trimming.
The LT1 004e is characterized for operation from ooe to 70°C. The LT1 004M is characterized for operation over
the full military temperature range of -55°C to 125°C.
. AVAILABLE OPTIONSt
PACKAGED DEVICES*
TA
O°C to 70°C
-SsoC to 12SoC
Vz
TYP
SMALL-OUTLINE
(D)
CHIP FORM
(Y)
PLASTIC
(LP)
1.2 v
LT1004CO-1.2
LT1004CLP-1.2
LT1004Y-1.2
2.SV
LT1 004CO-2.S
LT1004CLP-2.S
LT1004Y-2.S
1.2V
LT1004MO-1.2
LT1004MLP-1.2
2.SV
LT1004MO-2.S
LT1004MLP-2.S
-
t For ordering purposes, the decimal point in the part number must be replaced with a hyphen
(i.e., show the -1.2 suffix as -1-2 and the -2.S suffix as -2-S).
R suffix to the device type (i.e.,
LT1004COR).
:t: The packages are available taped and reeled. Add the
~TEXAS
Copyrlghl © 1995, Texas Ins1rumen1s Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
2-27
LT1004C-1.2, LT1004C-2.5; LT1004M-1.2
LT1004M-2.5, LT1 004Y-1.2, LT1004Y-2;5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST1995
schematic
LT10D4-1.2
,---,---~--~------~~--~~----.-----CATHODE
7.5 kn
200 kn
20pF
Q1
50 kn
600kn
500 kn
300 kn
Q5
Q13
60kn
ANODE
LT1004-2.5
CATHODE
7.5 kn
200 kn
500 kn
Q1
20pF
50 kn
600kn
._---1
Q8
Q13
500 kn
60 kn
L-~~
__~__~____~~____~____~__~__
NOTE A: All component values shown are nominal.
~TEXAS
2-28
INSTRUMENTS
POST OFFICE BOX 655303 •
T~ ~ ~~~!~ to ~2~,I~
E
..
..'"
..
:!l!'"
..
.2!
..l!!
I
VV
II:
I
$-
0.1
1
V
U
o
/
0.2
V
/'
0.4
V
~
8
~
u
c:
4
~I-"
II:
I
N
>
<1
0.6
0.8
1.2
0
-4
1.4
0.01
0.1
VR - Reverse Voltage - V
Figure 1
1.2
..
LT1004x-1.2
LT1004x-1.2
REFERENCE VOLTAGE
vs
vs
FORWARD CURRENT
FREE-AIR TEMPERATURE
1.245
T~~~~'~
IZ =1OOIlA
V
I
0.8
'E
0.6
~
>
..
..
..l!!
1.24
I
:!l!'"
~j;'
~
0
Ll..
I
Ll..
100
Figure 2
FORWARD VOLTAGE
>
:!l!'"
10
IR - Reverse Current - mA
~ 1.235
u
1-1-'
c:
'&i
II:
0.4
I
N
>
V
- t'-f'..
V +--
1.23
J"..
>
0.2
1.225
o
0.01
0.1
10
100
-55 -35 -15
IF - Forward Current - mA
5
25
45
65
85
105
125
TA - Free-Air Temperature - °C
Figure 3
Figure 4
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-31
LT1 004C-1.2, LT1004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.,2, LT1004Y-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
LT1004x-1;2
LT1004x-1.2
. REFERENCE IMPEDANCE
NOISE VOLTAGE
vs
vs
REFERENCE CURRENT
FREQUENCY
100
f~d51~!111I
700
TA = -55°C to 125°C
I
3
C
i.5
IZ =100~A
TA =25°C
600
~.
c;
I 11111111
I 1'111
l!:>
10
500
I'\~
c
~
I
400
&
:!l!
~
J
.
300
z
200
1-1-
i'~
CD
'0
"r-.
I
N
N
I
~
c
>
100
I'
I'
o
0.1
0.01
0.1
10
100
10
1k
100
IZ - Reference Current - rnA
10 k
100 k
f - Frequency - Hz
FigureS
Figure 6
TL1 004x-1.2
FILTERED OUTPUT NOISE VOLTAGE
70
LT1004x-2.5
TRANSIENT RESPONSE
..1\
I I IIIIIII
60
I-
&
:!l!
50
t-
.
40 I---
>:I.
vs
CUTOFF FREQUENCY
1111
IZ =100~A
TA =25°C
I
CD
'0
z
:i
~
30
l
20
t-
~
-
:!l!
2
VI--
::;-
j
~
:i
1I
~
o
.
V
0
1
Output
L
V
o.5
0
i
<:
-fir-
V1,V
36kQ
O
<:
.5
5
V
o
0.1
1.5
'tI
C
1/ ....
Ii:
10
/'
11111111
100~
~
I III
RC Low Pass
0
10
100
Cutoff Frequency - kHz
v
Input
o
100
500
600
t-Tirne-~
Figure 7
FigureS
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
2-32
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
}
LT1 004C-1.2, LT1004C-2.S, LT1 004M-1.2
LT1004M-2.S, LT1004Y-1.2, LT1004Y-2.S
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
LT1004x-2.5
REVERSE CURRENT
100
I
LT1004x-2.5
. FORWARD VOLTAGE
vs
vs
REVERSE VOLTAGE
FORWARD CURRENT
I
TA = -55°C to 125°C
cc
::1.
I
C
>
~
I
10
~
::I
(J
II
i
a::
I
!C
0.1
!
o
/
~
V
0.8 I-H+H-HfI--t-H+ttItl-+t+t+l+lfbo"''H-t+ttHI
:
:!l
"E
0.6 I-H+H-HfI--t-H+ttftbo.,oq.."t+t+I+Ilt--H-t+ttHI
j
I
IL
>
0.4
0.2 1--+-t-t+t-tttt--t--+l-t+tHt---+++t+H1H-+-i-t+ttttI
0.5
1.5
2
VR - Reverse Voltage - V
2.5
3
IF - Forward Current - mA
Figure 9
Figure 10
LT1 004x-2.5
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
2.52
IZ =1OOl1A
2.515
>
2.51
I
II
m
2.505
~
.
2.5
I!!
2.495
I
2.49
S
II
c
ila::
N
>
./
.............
/
i'-..
/'"
"" "
/
2.485
2.48
2.475
-55 -35 -15 5
25 45 65 85 105 125
TA - Free-Air Temperature - °C
Figure 11
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALl.AS, TEXAS 75265
2-33
LT1004C~1.2, LT1004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.2, LT1004V-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
1000
LT1004x-2.5
LT1004x-2.5
REFERENCE IMPEDANCE
'vs
REFERENCE CURRENT
NOISE VOLTAGE
vs
FREQUENCY
f~~I~~1I1I
1400
I IIII
TA =~55°Cto125°C
c:
1200
100
~:>c
I
g
t
.5
1000
r--.
800
I
\
10
r-
I 11111111
IZ =1oo~
TA =25°C
II
r" ....
01
1l!
I
~
600
.~
!
z
400
I
I
\
.;;
I'
N
N
200
0.1
0.01
, 0.1
10
o
100
10
100
IZ - Reference Current - mA
1k
10 k
100 k
f - Frequency - Hz
Figure 12
Figure 13
TL1004x-2.5
FILTERED OUTPUT NOISE VOLTAGE
vs
CUTOFF FREQUENCY
LT1004x-2.5
TRANSIENT RESPONSE
A
120
>::I.
IZ =100~
TA =25°C
4
100
I
II
01
1l!
~
RC LowPa¥
80
::
z
'S
60 t - -
~,
0
'1:1
40
~
II
I!!
~
it
V
100~
'0
20
>
3
i
2
I
V
l/'
i
o
'1:1
VltVO
1
0
C
>
01
./
>
i
.5
,.,- I-""
A
5
Input
o
0
0.1
.11..-
24kn
~
I/~
Output
10
100
Cutoff Frequency - kHz
-L
o
100
v
.A
v
500
t- TIme- j1S
Figure 14
Figure 15
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
2-34
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1 004C-1.2, LT1 004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.2, LT1004Y-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
100pF
24V
600J.lSRC
>-~~ Output
12kll
.16.9 kllt
LT1004-1.2
-5V
T
~L Input
~Y-J~1...Y __
O. 05 IlF
1.05 kllt
10kll
2N3904
-'\NIr-e---IH
56 kll
-5V
t
1% meial-film resistors
Figure 16. VI(PP) Generator for EPROMs (No Trim Required)
Network Detail
,..-----,
YSI44201
RTNetwork
Green
YSI44201
15V
I
I
I.-+w.r.....
2.7 kll
5%
I
I _-'VV'v----e
IL _ _302
_ kll
_ _ .JI
27650
0.1%
10kll
0.1%
Red
LT1DD4-1.2
10kll
0.1%
168.30
0.1%
10 kll
0.1%
Figure 17. ooe to 1000 e Linear Output Thermometer
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-35
LT1 004C-1.2, LT1 004C-2.5, LT1 004M-1.2
LT1004M-2.5, LT1004Y·1.2, LT1004Y-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS()~D,.c JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
, - - - - - - - - . - VI=6.5Vto15V
3
>=-6_...._ _ _...- Vo
=5 V
2
150 pF
LT1 004-1 ,2
3.01 MO
1%
1 MO
1%
Figure 18. Micropower 5-V Reference
VI;,,5V
100 I!A
1
9V
510kQ
220
._---'W\,---.- Output
LT1004-1.2
1.235 V
50llF
LT1004'1.2
Figure 19. Low-Noise Reference
100kQ
Figure 20. Micropower Reference
From 9-V Battery
f
R1
16840
3V, Lithium
.---+
LT1004-1.2
1870
18000
Thermocouple
Type
J
K
T
+
S
R1
232kO
298kQ
301 kO
2.1 MO
t Quiescent current" 151!A
:j: Yellow Springs Ins!. Co., Part #44007
NOTE A: This application compensates within ±1°C from O°C to 60°C.
Figure 21. Micropower Cold-Junction qompensation for Thermocouples
~TEXAS
INSTRUMENTS
2-36
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1004C-1.2, LT1004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.2, LT1004Y-2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
LT1084
5V
~
OUTI------ 5 V
01Ul
+
ADJ
Tl0~F
3010
1%
2.5 V
LT1004-2.5
LT1004-2.5
1000
1%
Figure 22. 2.S·V Reference
Figure 23. High-Stability S-V Regulator
15V
21Ult
2501Ul
. . . . _ - - - Output
LT1004-1.2
Rl
Input
(see Note A)
10 (see Note A)
t
2501Ul
-5 V
May be increased for small output currents
2001Ul
2V
1.235 V
NOTE A: R1 = 10+10~ ,10= -R-1-
' - - - - . . . . - - VCC- S -5 V
Figure 24. Ground-Referenced
Current Source
Figure 25. Amplifier With Constant Gain
Over Temperature
V+
1.5 V (see Note A)
I
31Ul
I
R~_...,
LM334 .....
:
1.235 V
6.81Ul
RsSIUl
LT1004-1.2
L.:
LT1004-1.2
1.3V
I0= -R-
NOTE A: Output regulates down to 1.285 V for 10 = O.
Figure 27. Terminal Current Source
With Low Temperature Coefficient
Figure 26. 1.2-V Reference From 1.S-V
Battery
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 •
DALLAS, TEXAS 75265
2-37
LT1 004C-1.2, LT1004C-2.5, LT1004M-1.2
LT1004M-2.5, LT1004Y-1.2, LT1004Y·2.5
MICROPOWER INTEGRATED VOLTAGE REFERENCES
SLVS022D - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
Battery Output
-=-
1 MO
12V
I
LO
=Battery Low
133 k.Q
1%
LT10D4-1.2
tRl sets trip point, 60.4 k.Q per celi for 1.8 V per celi
Figure 28. Lead-Acid Low-Battery Voltage Detector
LT1084
!" r:
?
ADJ
--
1200
I
~~
-=-
Vo
'VO
VI
+
11
LT1004-1.2
.~
i'"
R1 s;
VI:;C-1 V
0.015
~
R1
2k.Q
VccFigure 29. Variable Voltage Supply
~TEXAS
2-38
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
-=-
LT1009,LT1009Y
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
•
•
•
•
•
•
Excellent Temperature Stability
Initial Tolerance .•• 0.2% Max
Dynamic Impedance .•• 0.6 n Max
Wide Operating Current Range
Directly Interchangeable With LM136
Needs No Adjustment for Minimum
Temperature Coefficient
• Surface-Mount 3-Lead Package
DPACKAGE
(TOP VIEW)
u
u
NC
NC
NC
ANODE
The LT1 009C is characterized for operation from
O°C to 70°C. The LT10091 is characterized for
operation from -40°C to 85°C. The LT1009M is
characterized for operation over the full military
temperature range of -55°C to 125°C.
CATHODE
NC
CATHODE
ADJ
6
5
CATHODE
8 ADJ
NC 2
7 NC
6 ANODE
NC 3
NC45NC
LPPACKAGE
(TOP VIEW)
ANODE
Even though the LT1 009 needs no adjustments, a
third terminal (ADJ) allows the reference voltage
to be adjusted ±5% to eliminate system errors. In
many applications, the LT1009 can be used as a
terminal-for-terminal
replacement
for
the
LM136-2.5, which eliminates the external trim
network.
The uses of the LT1009 include a 5-V system
reference, an 8-bit ADC and DAC reference, and
a power supply monitor. The LT1 009 can also be
used in applications such as digital voltmeters and
current-loop measurement and control systems.
8
7
JGPACKAGE
(TOP VIEW)
description
The LT1009 reference circuit is a preclslontrimmed 2.5-V shunt regulator featuring low
dynamic impedance and a wide operating current
range. A maximum initial tolerance of ±5 mV is
available in the FK, JG, or LP package and
±10 mV in the D or PK package. The reference
tolerance is achieved by on-chip trimming, which
minimizes the initial voltage tolerance and the
temperature coefficient CXvz.
2
3
4
CATHODE
ADJ
FKPACKAGE
(TOP VIEW)
w
Cl
0
J:
o~oao
zoz«z
NC
NC
NC
NC
NC
3 2 1 2019
18
17
16
6
15
7
14
8
9 10 11 1213
4
5
NC
NC
NC
ANODE
NC
00000
logic symbol
ZZZZZ
ANODE _ _--I~
__r - - - CATHODE
NC-No intemal connection
PKPACKAGE
(TOP VIEW)
ADJ
CATHODE ANODE ADJ
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
Copyright © 1995. Texas Instruments Incorporated
On products compllantt. MIL~. CIaaa B.all para_a..
::e~~~:n::'=iy9~c~~=:::'~=:'
2-39
LT1009, LT1009Y
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
schematic
CATHODE
Q11
24kO
24kO
6.6kO
Q8
Q7
5000
30kO
ADJ
6.6kO
Q3
7200
~---.--------*-------------------------~~----------~----- ANODE
All component values shown are nominal.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
O°Clo 70°C
LT1009CD
-40°C to 85°C
LT1009ID
-55°C to 125°C
-
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
CYLINDRICAL
(LP)
PLASTIC
LEAD-MOUNT
(PK)
-
-
LT1009CLP
LT1009CPK
-
LT10091LP
LT1009MFK
LT1009MJG
-
-
CHIP
FORM
M
LT1009Y
The D and LP packages are available taped and reeled. Add R suffix to device type (e.g., LT1 009CDR). PK device is only available taped and reeled.
No R suffix is required.
~TEXAS
INSTRUMENTS
2-40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LT1009,LT1009Y
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
LT1009Y chip information
This chip, when properly assembled, displays characteristics similar to the LT1009C (see electrical tables).
Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
ANODE
(4)
_ ......~*r__
l]
CATHODE
(8)
ADJ
(5)
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
I~
55
~
111111111111111111111111111111111111111111111111111111II
absolute maximum ratings over operating free-air temperature ranget
Reverse current, IR ...................................................................... 20 mA
Forward current, IF ....................................................................... 10 mA
Continuous total power dissipation ............................. See Dissipation Rating Tables 1 and 2
Operating free-air temperature range, TA: LT1009C ..................................... O°C to 70°C
LT10091 .................................... -40°C to 85°C
LT1009M ................................. -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 60 seconds, T c: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, LP, and PK packages ......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package .................... 300°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilHy.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-41
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE
k
(J)
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=85°C
POWER RATING
D
725mW
5.8mW/oC
464mW
377mW
<
(J)
TA = 125°C
POWER RATING
~
m
'"
I
-
s:
FK
1375mW
11.0 mW/oC
880mW
715mW
275mW
JG
1050mW
8.4 mW/oC
672mW
546mW
210mW
LP
775mW
6.2mWrC
496mW
403mW
PK
500mW
4.0mWrC
320mW
:><
co
co
"""I
-
-
JJ
m
:S
(J)
m
0
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
PACKAGE
TC,,25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 70°C
POWER RATING
PK
3125 mW
25mW/oC
2000mW
'il-~
52
mC/) !!!IIi.
~~d
~t:~
PARAMETER
TEST CONDITIONS
FK, JG, LP package
Vz
Reference voltage
D, PK package
IZ= 1 rnA
~~r!
tr'J"'J
~~
FK, JG, LP package
D, PK package
VF
FOlWard voltage
IZ= 1 rnA,
Adjustment range
lO
,l.VZ(temp)
Change in reference
voltage with temperature
CJ.VZ
Average temperature
coefficient of
reference voltage:!:
LT1009C
TAt
25°C
Full range
VADJ = GND to Vz
IZ= 1 rnA,
VADJ = 0.6 V to VZ-0.6 V
FK, JG, LP package
D, PK package
25°C
LT1009M
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
2.495
2.5
2.505
2.495
2.5
2.505
2.495
2.5
2.505
2.49
2.5
2.51
2.49
2.5
2.51
2.491
2.509
2.48
2.52
2.485
2.515
2.475
2.525
0.4
1
0.4
1
125
125
45
45
Full range
O°C to 70°C
LT10091
MIN
15
2.46
2.535
0.4
1
4
15
15
IZ =400 IlA to 10 rnA
,l.VV,l.t
Long-term change in
reference voltage
IZ= 1 rnA
Zz
Reference impedance
IZ= 1 rnA
~~
m
C
:xJ
m
-n
m
:xJ
m
z
0
25°C
10
2.6
12
25°C
20
25°C
0.3
Full range
15'
=i
V
V
mV
ppml°C
25
2.6
6
1
2.6
10
20
1.4
0.3
:xi
0
c:
mV
20
Full range
UNIT
25
-55°C to 125°C
Change in reference
voltage with current
G) ......
:xJO
(J)
15
5
-40°C to 85°C
,l.VZ
ZCD
.....
-
mej
m
25°C
IF=2 rnA
<0
_0
0
~
~
co
co
'"
electrical characteristics at specified free-air temperature
2l
1"
»
c
Gl
c
~
~ej
C{1 ......
35
6
10
ppmlkhr
20
1
1.4
• On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
t Full range is O°C to 70°C for the LT1009C, -40°C to 85°C for the LT10091, and -55°C to 125°C for the LT1009M.
:!: The average temperature coefficient of reference voltage is defined as the total chaQge in reference voltage divided by the specified temperature range.
0.3
mV
0.6'
l'
g
LT1009,LT1009Y
2.S-V INTE'GRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
electrical characteristics at TA
=25°C
TEST CONDITIONS
PARAMETER
LT1009Y
TYP
MAX
2.5
2.51
V
1
V
Vz
Reference voltage
IZ= 1 mA
2.49
VF
Forward voltage
IF=2mA
0.4
IZ= 1 mA, VADJ = GND to Vz
125
Adjustment range
IZ=1 mA, VADJ = 0.6 V to Vz -0.6 V
E
/
I
GI
aI
>
~
2.51
~
I!!
'IIa:
./
2.49
I
/
!
I
GI
4
-...... ~
,/'"
3c
3
!
.;a:
r--...
.5
2
GI
aI
C
III
.........
N
>
c3
I
N
2.48
~
2.47
-50
-25
0
25
50
75
100
o
o
125
/
TA - Free-Air Temperature - °C
/
4
/
/v
12
8
16
20
IZ - Reference Current - mA
Figure 1
Figure 2
REVERSE CURRENT
FORWARD VOLTAGE
vs
vs
REVERSE VOLTAGE
FORWARD CURRENT
10-1
1.2
TJ=25°C
cc
10-2
>
I
I
C
~
::s
0
I
&
!
~
1!
10-3
I
TJ = 125°C
5- 10-4
10-5
0.6
I
V
,/
~
If
V
r--
-::::
t-
1.4
-
0.8
0.6
E
:.
I
~~
>
~
_ TJ=-55°C
2.2
- -~
./
)
0.2
I I
I-- TJ=25°C
1.8
0.4
~
/
/
/'
o
2.6
0.001
0.01
0.1
IF - Forward Current- mA
VR - Reverse Voltage - V
Figura 3
Figure 4
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS 2-44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
LT1009,LT1009Y
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
NOISE VOLTAGE
REFERENCE IMPEDANCE
vs
vs
FREQUENCY
FREQUENCY
250
100
~ Iz =1 rnA
1= TJ=
a
200
I
I"
l!:>
7
I
150
~
/
-
I
~
&
/
N
N
,
c
/
I
0.1
0.01
I 11111111
Iz=1rnA
~ TJ=25°C
55°Cto125°C
~
~
..
GI
"0
100
z
I
c
>
0.1
50
10
100
10
100
f - Frequency - kHz
Figure 5
10 k
1k
f - Frequency - Hz
100 k
Figure 6
TRANSIENT RESPONSE
A
!\
2.5
>
2
l
1.5
I
=
~
1S
t
0
\I
"tI
Input
::
C
til
\.
Output
'$
11.
.5
( utput
f&
0.5
0
..V
I
8
I
Tnput
4
0
o
20
t-Time-IJ.S
Figure 7
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2-45
LTt009,LT1009Y
2.SN INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
;
APPLICATION INFORMATION
5Vto35V
Output
LT1009
A---~
10knt
Trim'
trhis does npt affect temperature coefficient. It provides :1;5% trim range.
Figure 8. 2.S-V Refere~ce
3.6Vto40V
LT1009 A - - - - - . <
Figure 9. AdJListable Reference With Wide Supply Range
2kn
Figure 10. Power Regulator With Low Temperature Coefficient
~TEXAS
2-46
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LT1009, LT1009Y
2.S-V INTEGRATED REFERENCE CIRCUITS
SLVS013E - MAY 1987 - REVISED AUGUST 1995
APPLICATION INFORMATION
5V
5.1 kO
5V
J1.. ____
5v·1I/\IUl
r--.....-H
101Ul
1%
LT1009
-5V
Output
51Ul
-5V
Figure 11. Switchable ± 1.2S-V Bipolar Reference
10kO
> - - - - i t - - - - 2.5 V
Figure 12. Low-Noise 2.S-V Buffered Reference
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2-47
2--48
3-1
Contents
.. ~..
o
;:;:
.Q)
c.a
CD
l:J
CD
c.a
··c·
....
Dr
··.0
tn·
3-2
Page
TL317
3-Terminal Adjustable Regulator ...................... 3-3
TL430
Adjustable Shunt Regulator: .... c ••••••••••••••••••••• 3-11
TL431
Adjustable Precision Shunt Regulators .............. 3-17
TL431 A
Adjustable Precision Shunt Regulators .............. 3-17
TL75LPxx
Low-Dropout Voltage Reg"lators ..................... 3-35
TL750Lxx
Low-Dropout Voltage Regulators ..................... 3-49
TL751 Lxx
Low-Dropout Voltage Regulators ..................... 3-49
TL750Mxx
Low-Dropout Voltage Regulators ..................... 3-59
TL751 Mxx
Low-Dropout Voltage Regulators .......... : .......... 3-59
TL780xx
Positive Voltage Regulators ........................... 3-71
High-Voltage Adjustable Regulators ................. 3-79
TL783
TL1431
Precision Programmable References ................ 3-93
TLV431
Low-Voltage Adjustable Precision Shunt Regulators 3-109
TLV2217-xx
Low-Dropout 3.3-V Fixed Voltage Regulators ..... 3-123
TPS71 xx
Low-Dropout Voltage Regulators. . . . . . . . . . . . . . . . . . .. 3-129
TPS7133QPWP Micropower Low-Dropout Voltage Regulators ..... 3-159
TPS72xx
Micropower Low-Dropout Voltage Regulators ..... 3-185
TPS73xx
Low-Dropout Voltage Regulators With Integrated
Delayed Reset Function ............................. 3-213
Precision Voltage Regulators ....................... 3-247
J..lA723
·Positive-Voltage Regulators .............. ,.......... 3-259
J..lA78xX
Positive-Voltage Regulators ......................... 3-275
J..lA78Lxx
J..lA78Mxx
Positive-Voltage Regulators ......................... 3-289
Negative-Voltage Regulators ........................ 3-303
J..lA79Mxx
TL317, TL317V
3-TERMINAL ADJUSTABLE REGULATORS
SLVSOO4B
• Output Voltage Range Adjustable From
1.2 V to 32 V When Used With an External
Resistor Divider
• Output Current Capability of 100 rnA
• Input Regulation Typically 0.01 % Per
Input-Voltage Change
• Output Regulation Typically 0.5%
• Ripple Rejection Typically 80 dB
DPACKAGE
(TOP VIEW)
INPUTDa NC
OUTPUT 2
7 OUTPUT
OUTPUT 3
6 OUTPUT
ADJUSTMENT 4
5 NC
NOTE: OUTPUT terminals are all internally connected.
description
LPPACKAGE
(TOP VIEW)
The TL317C is an adjustable 3-terminal positivevoltage regulator capable of supplying 100 mA
over an output-voltage range of 1.2 V to 32 V. It is
exceptionally easy to use and requires only two
external resistors to set the output voltage.
INPUT
OUTPUT
ADJUSTMENT
In addition to higher performance than fixed
regulators, this regulator offers full overload
protection available only in integrated circuits.
NC-No internal connection
Included on the chip are current-limiting and
thermal-overload protection. All overload protection circuitry remains fully functional even when ADJUSTMENT
is disconnected. Normally, no capacitors are needed unless the device is situated far from the input filter
capacitors, in which case an input bypass is needed. An optional output capacitor can be added to improve
transient response. ADJUSTMENT can be bypassed to achieve very high ripple rejection, which is difficult to
achieve with standard 3-terminal regulators.
In addition to replacing fixed regulators, the TL317C regulator is useful in a wide variety of other applications.
Since the regulator is floating and sees only the input-to-output differential voltage, supplies of several hundred
volts can be regulated as long as the maximum input-to-output differential is not exceeded. Its primary
application is that of a programmable output regulator, but by connecting a fixed resistor between
ADJUSTMENT and OUTPUT, this device can be used as a precision current regulator. Supplies with electronic
shutdown can be achieved by clamping ADJUSTMENT to ground, programming the output to 1.2 V where most
loads draw little current.
The TL317C is characterized for operation from O°C to 125°C. The TL317Q is characterized for operation from
-40°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
PLASTIC
(LP)
CHIP FORM
(Y)
QOC to 125°C
TL317CD
TL317CLP
TL317Y
-40°C to 125°C
TL317QD
TL317QLP
-
The D and LP packages .are available taped and reeled. Add R suffix to device type
(e.g., TL317DR).
PRODUCTION DATA Info_Ion " current II 01 publication _ .
. Produell ccnform to speclllcattons per tho terms 01 Texss InlllrUmsnts
standard warranty. Production p......lng does not _ I V Include
tostIng 01011 psramelerl.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
Copyright © 1995. Texas Instruments Incorporated
TL317C, TL317Y
3-TERMINAL ADJUSTABLE REGULATORS
SLVS004B - APRIL 1979 - REVISED AUGUST 1995
TL317Y chip information
This chip, when properly assembled, displays characteristics similar to the TL317C. Thermal compression or
ultrasonic bonding may be used on the· doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
OUTPUT
(6)
INPUT
(1)
ADJUSTMENT
(4)
CHIP THICKNESS:
15 MILS TYPICAL
BONDINC) PADS:
4 x 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN
MILS.
TERMINALS 2,3,6, AND 7 ARE
CONNECTED TOGETHER
1111111111111111111111111111111 i 111111111111111111111111111111
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL317C, TL317Y
3-TERMINAL ADJUSTABLE REGULATORS
SLVS004B - APRIL 1979 - REVISED AUGUST 1995
schematic
r---~----~------~--------'-----~---'----------------------------
310Q
310Q
251 Q
190Q
__ INPUT
5.6kQ
1.4Q
30
2.12kQ
pF
195Q
5.3 kQ
5.7 kQ
70 Q
5.1 kQ
30
pF
670Q
10.8kQ
-'---'--OUTPUT
ADJUSTMENT
L-~--~~--~~~~--__---'--~~~~~--'-~~--~------------__
L---'V\/'v---------
40Q
NOTE A. All component values shown are nominal.
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Input-to-output differential voltage, VI- Vo ................................................... 35 V
Continuous total power dissipation ............................. See Dissipation Rating Tables 1 and 2
Operating free-air, case, TA, or virtual-junction temperature range, TJ: C Version ........... O°C to 150°C
Q Version ........ -40°C to 150°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ................................ 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE
PACKAGE
TA:O; 25°C
POWER RATING
D
725mW
DERATING FACTOR
ABOVE TA 25°C
5.8mW/oC
6.2mW/oC
=
TA =125°C
POWER RATING
145mW
LPt
155mW
775mW
t The LP package dissipation rating is based on thermal resistance measured in still air with the
device mounted in an Augat socket. The bottom of the package is 10 mm (0.375 in.) above the
socket.
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
PACKAGE
D
LP
=
TC:O; 25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE TC
TC 125°C
POWER RATING
1600 mW
1600 mW
29.6 mW/oC
28.6 mW/oC
96°C
94°C
742 mW
713 mW
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-5
TL317C, TL317V
3·TERMINAL,AOJUSTABLE REGULATORS
SLVSOO4B - APRIL 1979,- REVISED AUGUST 1995
recommended operating conditions,
MIN
MAX
Input-to-outputvoltage differential, VI- Vo
Output current, 10
Operating virtual-junction temperature, TJ
UNIT
35
V
2.5
100
mA
0
125
°c
electrical characteristics over recommended operating virtual-junction temperature range (unless
otherwise noted)
PARAMETER
Input voltage regulation (see Ngte 1)
TEST CONDITIONST
VI-VO='5 Vto35 V
VO=10V,
Ripple regulation
Output voltage regulation
. Output voltage change with temperature
TL317C, TL317Q
MIN
TYP
MAX
TJ = 25°e
0.01
0.02
10 = 2.5 mA to 100 mA
0.02
0.05
f= 120Hz
VO=10V,
10-!iF capacitor between ADJUSTMENT and ground
UNIT
"IoV
65
66
dB
80
VI = 5 V to 35 V,
10 = 2.5 mA to 100 mA,
TJ = 25°e
VOS,5V
25
mV
VO"25V
5
mVN
VI = 5 V to 35 V,
10 = 2.5 mA to 100 rnA
VOS,5V
50
mV
VO"25V
10
mVN
10
TJ = ooe to 125°e
Output voltage long-term drift (see Note 2)
After 1000 hours atTJ =.125°e and VI- Vo = 35V
Output noise voltage
f=10Hztol0kHz,
Minimum output current to maintain regulation
VI- VO=35V
Peak output current
VI-VOS,35V
3
30
TJ = 25°e
1.5
100
ADJUSTMENT current
ehangein ADJUSTMENT current
VI- VO=2.5 Vto35 V,
10 = 2.5 mA to 100 mA
Reference voltage (output to ADJUSTMENT)
VI- VO=5Vt035V,
P S, rated dissipation
10 = 2.5 mA to 100 mA,
mVN
10
1.2
mVN
IlVN
2.5
200
mA
mA
50
100
0.2
5
1.25
1.3
v.A
v.A
V
..
..
t Unless otherwise noted, these specifications
apply for the follOWing test conditions: VI- Vo = 5 V and 10 = 40 rnA. Pulse-testing techmques must
bEl used that maintain the junction temperature as close to'the ambient temperature as possible. All characteristics are measured with a O.l-IlF
capacitor across the input and a l-IlF capacitor across the output.
NOTES: 1. Input voltage regulation is expressed here as ttie percentage change in output voltage per l-V change at the input
2. Since long-term drift cannot bEl measured on the individual devices prior to shipment, this specification is not intended to be a
guarantee or warranty. It is an engineering estimate of the average drift to bEl expected from lot to lot.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TL317C,TL317Y
3-TERMINAL ADJUSTABLE REGULATORS
SLVS004B - APRIL 1979 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, TJ = 25°C (unless otherwise
noted)
PARAMETER
TEST CONDITIONST
Input voltage regulation (see Note 1)
TYP
0.01
VI-VO = 5 Vt035 V
f=120Hz
VO=10V,
Ripple regulation
VO=10V,
1O-~F capacitor between ADJUSTMENT and ground
Output voltage regulation
10 = 2.5 mA to 100 mA
MAX
UNIT
%V
65
80
dB
I VOS5V
25
mV
IVO~5V
5
mVN
Output noise voltage
f=10Hzt010kHz,
30
~VN
Minimum output current to maintain regulation
VI- VO=35V
1.5
mA
Peak output current
VI- VOS35V
200
mA
50
~
10 = 2.5 mA to 100 mA
0.2
~A
10 = 2.5 mA to 100 mA,
1.25
V
ADJUSTMENT current
t
TL317Y
MIN
Change in ADJUSTMENT current
VI- Vo = 2.5 V to 35 V,
Reference voltage (output to ADJUSTMENT)
VI-VO=5 Vt035 V,
P S rated dissipation
..
..
Unless otherwise noted, these specifications apply for the follOWing test conditions: VI- Vo = 5 V and 10 = 40 mAo Pulse-testing techniques must
be used that maintain the junction temperature as close to the ambient temperature as possible. All characteristics are measured with a 0.1-~F
capacitor across the input and a 1-~F capacitor across the output.
NOTE 1: Input voltage regulation is expressed here as the percentage change in output voltage per 1-V change at the input
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-7
TL317C, TL317Y
3·TERMINAL ADJUSTABLE, REGULATORS
SLVSOO4B -APRIL 1979 - REVISED AUGUST 1995
APPLICATION INFORMATION
35V-+----1
VI
Vo
(see Note D)
R1
Vo
(see Note B)
1200
C1 =0.1I!F
C1
0.11!F
C2 = 11!F
(see Note A)
R3
(see Note C)
8200
R2
3kO
1N4002
Figure 2. ()'V to 3()'V Regulator Circuit
Figure 1. Adjustable Voltage Regulator
TL317C
VI
INPUT OUTPUT 1--_'_-111-----411-- Vo
ADJUSTMENT
R1
4700
D1t
VI
1--.....-A./\J\r-_-
(see Note C)
IUmit
= 1.25
R1
1N4002
R2,
10k(!
Figure 4. Precision Current-Limiter Circuit
t
01 discharges C2 if output is shorted to ground.
Figure 3. Regulator Circuit
With Improved Ripple Rejection
NOTES: A. Use of an input bypass capacitor is recommended if regulator is far from the filter capacitors
B. Output VOltage is calculated from the equation: V 0 = V ref (1
+
=~)
where: Vref equals the difference between OUTPUT and ADJUSTMENT voltages (~ 1.25 V).
C. Use of an output capacitor improves transient response but is optional.
D. Output voltage is calculated from the equation: V 0
= V ref
(1 + R2;, R3) - 10 V
where: Vref equals the difference between OUTPUT and ADJUSTMENT voltages (~ 1.25 V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
TL317C,TL317Y
3-TERMINAL ADJUSTABLE REGULATORS
SLVS0048 - APRIL 1979 - REVISED AUGUST 1995
APPLICATION INFORMATION
R2
1.5 k!l
R1
Vo= 15V
4700
1N4002
C1
0.111F
R2
5.1 kO
R4
2k!l
Figure 5. Tracking Preregulator Circuit
Figure 6. Siow-Turn-On 15-V
Regulator Circuit
240
2400
1.1 kO
I
Figure 7. 50-mA Constant-Current
Battery Charger Circuit
VBE
R
VBE
=--
'CHG
V_------~~---L----~
Figure 8. Current-Limited 6-V Charger
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL317C, TL317Y
3·TERMINAL ADJUSTABLE REGULATORS
SLVSOO4B - APRIL 1979 - REVISED AUGUST 199.5
APPLICATION INFORMATION
T1P73
soon
22n
120n
1N4002
5kn
t Minimum load current is 30 mAo
:j: Optional capacitor improves ripple rejection
Figure 9. High-Current Adjustable Regulator
~TEXAS
3-10
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL430C, TL4301, TL430Y
ADJUSTABLE SHUNT REGULATORS
• Temperature Compensated
• Programmable Output Voltage
LPPACKAGE
(TOP VIEW)
• Low Output Resistance
• Low Output Noise
• Sink Capability to 100 mA
CATHODE
ANODE
description
REF
The TL430 is a 3-terminal adjustable shunt
regulator featuring excellent temperature stability,
wide operating current range, and low output
noise. The output voltage may be set by two
external resistors to any desired value between
3 V and 30 V. The TL430 can replace zener diodes
in many applications providing improved performance
The TL430C is characterized for operation from
O°C to 70°C. The TL4301 is characterized for
operation from -40°C to 85°C.
symbol
REF
ANODE
____
~~r-- CATHODE
AVAILABLE OPTIONS
PACKAGED DEVICEst
TA
PLASTIC
(LP)
O°C 10 70°C
TL430CLP
-4QOC 10 85°C
TL430ILP
CHIP FORM
(Y)
TL430Y
~TEXAS
-
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-11
TL430C, TL4301, TL430Y
ADJUSTABLE SHUNT'REGULATORS
SLVS050A- JUNE 1976 - REVISED AUGUST 1995
TL430Y chip information
This chip, when properly assembled, displays characteristics similar to the TL430C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
ANODE
(1)
....,...-II~*r__ CATHODE
(2)
f
REF
(3)
CHIP THICKNESS: .
15 MILS TYPICAL
44
BONDING PADS:
4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES
ARE ±10'Yo.
ALL DIMENSIONS
ARE IN MILS.
I..
.1
52
11111111111111111111111111111111111111111111111111111
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Regulator voltage (see Note 1) ............................................................. 30 V
Continuous regulator current ............................................................. 150 mA
Continuous total power dissipation at (or below) TA =25°C (see Note 2) ...................... 775 mW
Operating free-air temperature range, TA: TL430C ...................................... O°C to 70°C
TL4301 ..................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periOds may affect device reliability.
NOTES: 1. All voltage values are with respect to the anode terminal.
2. For operation above 25°C free-air temperature, derate at 6.2 mW/oC.
recommended operating conditions
Regulatorvoltage, Vz
Regulator current, IZ
ITL430C
Operating free-air temperature range, TA
ITL4301
~TEXAS
INSTRUMENTS
3-12
POST OFFICE BOX 655303 • DALLAS, TExAs 75265
. MIN
MAX
Vref
2
30
V
100
mA
0
70
-40
85
UNIT
°C
TL430C, TL4301, TL430Y
ADJUSTABLE SHUNT REGULATORS
SLVS050A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, TA
noted)
PARAMETER
TEST
FIGURE
TEST CONDITIONS
VI(re!)
Reference input voltage
1
VZ=Vl(re!),
IZ=10mA
aVI(ref)
Temperature coefficient of
reference input voltage
1
VZ=VI(ref)'
TA = full ranget
IZ=10mA,
II(ref)
Reference input current
2
IZ= 10mA,
Rl=10kn,
IZK
Regulator current near lower
knee of regulation range
IZK
Regulator current at maximum
limit of regulation range
rz
Differential regulator resistance
(see Note 4)
1
Vz = VI(ref),
t.IZ = (52 - 2) mA
Vn
Noise voltage
2
f=O.l Hz to 10Hz
TL4301
TL430C
TYP
MAX
MIN
TYP
2.5
2.75
3
2.6
2.75
2.9
V
120
200
ppm/"C
3
10
j.LA
0.5
2
mA
120
3
10
MAX
UNIT
MIN
R2=~
-
1
Vz = VI (ref)
1
VZ=VI(ref)
Vz = 5 V to 30 V,
2
=25°C (unless otherwise
0.5
See Note 3
2
50
50
100
100
1.5
3
mA
1.5
50
50
VZ= 12V
200
200
VZ=30V
650
650
VZ=3V
n
3
I1V
t Full temperature range IS ooe to 70°C for the TL430e and -40°C to 85°C for the TL4301.
NOTES: 3. The average power dissipation, Vz • IZ. duty cycle, must not exceed the maximum continuous rating in any 1O-ms interval.
4. The regulator resistance for Vz > VI (ref), rz, is given by:
rz ' = rz
(1
+
~
)
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
TEST
FIGURE
PARAMETER
VI(re!)
Reference input voltage
TEST CONDITIONS
1
II(ref)
Reference input current
2
IZK
Regulator current near lower knee of regulation
range
1
VZ=VI(re!),
Iz=10mA,
R2 =00
Regulator current.at maximum limit of regulation
range
2
rz
Differential regulator resistance (see Note 4)
1
VZ= VI (ref)
Vz = 5 V to 30 V,
Noise voltage
3
V
3
10
j.LA
0.5
2
mA
50
VZ=VI(ref), .......
t.IZ = (52 - 2) mA
2
.f = 0.1 Hz to 10 Hz
mA
100
1.5
VZ=3V
Vn
MAX
2.75
Rl =10kn,
See Note 3
UNIT
TYP
2.5
VZ=VI(ref)
1
IZK
IZ=10mA
TL430Y
MIN
3
n
50
VZ= 12V
200
VZ=30V
650
~V
NOTES: 3. The average power diSSipation, Vz • IZ • duty cycle, must not exceed the maximum conllnuous rating In any 10-ms Interval.
4. The regulator resistance for Vz > VI(ref), rz, is given by:
rz ' = rz
(1
+
:~
)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-13
TL430C, TL4301, TL430Y . .
ADJUSTABLE SHUNT REGULATORS
SLVSOSOA- JUNE 1976 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Input
R1
Input ---'1N'v~f--- Vi
1-
~IZ
11(rpf)
-'+
....
R2
TL430
Vz
Vir
":t> TL430
Vz = VI(ref) (1 +
=VI(ref)
Figure 1. Test Circuit for Vz
~)
+11(ref) x R1
Figure 2. Test Circuit for Vz > VI(ref)
TYPICAL CHARACTERISTICS
SMALL-SIGNAL REGULATOR IMPEDANCE
CATHODE CURRENT
va
va
FREQUENCY
CATHODE VOLTAGE
160
3
c:
I
8
I:
os
VZ=JI~ref)
2.8 !-- TA=25 C
I.§
j
2.6
c
2.4
r!
2.2
C
~;:,
;:,
III
ii
I:
f
N
N
120
IZM
I
I
/
2
1.8
V
1.6
1.4
u
80
i.c
60
~
.!
/
105
10
100
IZ
40
20
o
IZK
o
f - Frequency - Hz
Figure 3
2
3
V - Cathode Voltage - V
Figure 4
~TEXAS
3-14
V
/
e
1/1
I
VZ=VI~~
140 !--TA=25 C
INSTRUMENTS .
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TL430C, TL4301, TL430Y
ADJUSTABLE SHUNT REGULATORS
SLVS050A- JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
V+
R
V+
Vo
I
I
~
T
I
I
R2
Figure 5. Shunt Regulator
Figure 6. Series Regulator
V+
Figure 7. Current Limiter
V+ ---'VV\,-e--.....- - . - - Vo
Vo
R1
R2
v0
=
(1 +
=~)
Min Vo = V1(ref)
+
VI(ref)
SV
Figure 8. Output Control of a 3-Terminal
Fixed Regulator
Figure 9. Higher-Current Applications
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-15
TL430C, TL4301, TL430Y
ADJUSTABLE SHUNT REGULATORS
SLVSOSOA- JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
V+
U>-.......- - - 1 . _ _ - _ e - - - ; ! t - - Vo
R1
VCC--e----.......--~
R1B
R1A
R2
R2B
R2A
Low limit = V1(ref)
+
=~:)
High limit =
+
=~)
Figure 11. Vee Monitor
Figure 10. Crowbar
~·TEXAS
3-16
(1
V1(ref) (1
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
• Equivalent Full-Range Temperature
Coefficient ••• 30 ppml"C
OS
D OR PW PACKAGE
(TOP VIEW)
• 0.2-0 Typical Output Impedance
• Sink-Current Capability ..• 1 mA to 100 mA
• Low Output Noise
• Adjustable Output Voltage ..• VI(ref) to 36 V
• Available in a Wide Range of High-Density
Packaging Options:
- Small Outline (D)
- TO-226AA (LP)
- SOT-89 (PK)
description
The TL431 and TL431 A are 3-terminal adjustable
shunt regulators with specified thermal stability
over applicable automotive, commercial, and
military temperature ranges. The output voltage
can be set to any value between VI(ref)
(approximately 2.5 V) and 36 V with two external
resistors (see Figure 16). These devices have a
typical output impedance of 0.2 O. Active output
circuitry provides a very sharp turn-on characteristic, making these devices excellent replacements
for zener diodes in many applications, such as
on-board regulation, adjustable power supplies,
and switching power supplies.
CATHODE
ANODE
ANODE
NC
2
3
4
7
6
5
08
REF
ANODE
ANODE
NC
JG OR P PACKAGE
(TOP VIEW)
CATHODE
NC
NC
NC
2
3
4
7
6
5
REF
NC
ANODE
NC
PKPACKAGE
(TOP VIEW)
REF ANODE CATHODE
LPPACKAGE
(TOP VIEW)
The TL431 is offered in a wide variety of highdensity packaging options that includes an
SOT-89-type package (suffix PK).
CATHODE
The TL431 C and TL431 AC are characterized for
operation from O°C to 70°C, and the TL431 I and
TL431AI are characterized for operation from
-40°C to 85°C. The TL431 M is characterized for
operation over the full military temperature range
of -55°C to 125°C.
ANODE
REF
FKPACKAGE
(TOP VIEW)
w
Cl
0
::r:
LL
u!;cuwu
zuza:z
NC
NC
NC
NC
NC
1 2019
18
17
16
15
7
14
8
9 10 11 12 13
4
5
6
3 2
NC
NC
NC
ANODE
NC
uuuuu
ZZZZZ
NC- No internal connection
~~:1!::=:"~""J,.rent...:=!.'!:=-=
standard warranty. Production processing doe& not necessarily include
testing of all paramotera.
.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1995. Texas Instruments Incorporated
On products compliant to MIL-sTD-883. Class a, all parameters are
tested unless ofharwl8e noted. On all other praducts, production
processing does no! nec....rlly Include testing of all parameters.
3--17
TL431C, TL431AC, TL431I, TL431 AI, TL431M, TL431V
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSO05E - JULY 1978:" REVISED AUGUST 1995
AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D)
TA
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
TO-226AA
(LP)
PLASTIC
DIP
(P)
SOT-89
(PK)
DOC to 70°C
TL43tCD
TL431ACD
TL431CLP
TL431ACLP
TL431CP
TL431ACP
TL431CPK
-40°C to 85°C
TL4311D
TL431 AID
TL4311LP
TL431AILP
TL431IP
TL431AIP
TL431IPK
TL431MFK
-55°C to 125°C
CHIP
FORM
SHRINK
SMALL OUTLINE
(PW)
(Y)
TL431CPW
TL431Y
..
TL431MJG
The D and LP packages are available taped and reeled. Add R suffix to device type (e.g., TL431 CDR). The PK package IS only available taped
and reeled (no R suffix required). Chip forms are tested at TA = 25°C.
application schematic
S-V Precision Regulator
V+ -
.....-.,(
) r - - -....-
VO=SV
27.4 k.Q
Rb
(see Note A)
0.1%
27.4 k.Q
0.1%
NOTE A: Rb should provide cathode current;:, 1-mA to
the TL431.
symbol
functional block diagram
CATHODE
REF
ANODE
~~r
_ ..... __
CATHODE
ANODE
~TEXAS
INSTRUMENTS
3-18
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
equivalent schematic
CATHODE------__----------~~----~~~._--~--------_.~
20pF
REF
10kn
800n
ANODE--~~------~----~~----~~~--------------_.~
NOTE A: All component values are nominal.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-19
( TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSOO5E - JULY 1978 - REVISED AUGUST 1995
TL431 Y chip information
This chip, when properly assembled, displays characteristics similar to the TL431C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CATHODE
(1)
ANODE
(2)
66
TL431Y
(3) REF
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
Pins 2,3,6, and 7 are connected
together
Pins 4 and 5 are not connected
~
~
~
11111111111111111111111111111111111111111111111
~TEXAS
INSTRUMENTS
3-20
POST OFFICE BOX 655303 • OAu.AS, TEXAS 75265
TL431C, TL431AC, TL431I, TL431 AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Cathode voltage, VKA (see Note 1) .......................................................... 37 V
Continuous cathode current range, IKA ......................................... -100 mA to 150 mA
Reference input current range ................................................... -50 j.LA to 10 mA
Continuous total power dissipation ............................. See Dissipation Rating Tables 1 and 2
Operating free-air temperature range, TA: C-suffix ..................................... O°C to 70°C
I-suffix .................................... -40°C to 85°C
M-suffix ................................. -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 60 seconds: FK package .............................................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, P, or PW package ............ 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG, LP, or PK package .......... 300°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to the anode terminal unless otherwise noted.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE
PACKAGE
TA=25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
TA = 125°C
POWER RATING
D
725mW
5.8mW/oC
464mW
377mW
FK
1375 mW
11.0 mW/oC
880mW
715mW
275mW
JG
1050mW
8.4mW/oC
672mW
546mW
210mW
LP
775mW
6.2mW/oC
496mW
403mW
P
1000mW
8.0mW/oC
640mW
520mW
PK
500mW
4.0mW/oC
320mW
260mW
PW
525mW
4.2mW/oC
336mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
PACKAGE
TC = 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC=70°C
POWER RATING
TC=85°C
POWER RATING
PK
3125mW
25mW/oC
2000mW
1625mW
recommended operating conditions
Cathode voltage, VKA
Cathode current, IKA
UNIT
MIN
MAX
VI(ref)
36
V
1
100
rnA
.~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-21
~
TEST
CIRCUIT
PARAMETER
TL431 I
TL431C
TEST CONDITIONS
»-'1
<
U>
OS:
c..
w
'"m c: .....
U>
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise noted)
0
0
TL431M
MIN
TYP
MAX
MIN
TYP
MAX
MIN
.TYP
MAX
2440
2495
2550
2440
2495
2550
2400
2495
2600
4
17
5
30
UNIT
I
<-
VI (ref)
Reference input voltage
1
VKA = VI(ref),
VI(dev)
Deviation of reference
input voHage over full
temperature range:j:
1
VKA = VI(re!), IKA = 10 mA,
TA = Full ranget
IKA=10mA
2
II(ref)
Reference input current
2
IKA=10mA,
R1=10kQ,
R2=~
2
IKA=10mA, R1=10kQ,
TA = Full ranget
R2=~,
II(dev)
Deviation of reference
input current over full
temperature range:j:
Imin
Minimum cathode current
for regulation
1
VKA = VI(ref)
J.!Z
_
!il-~
loft
Oft-stllte cathode current
3
VKA=36V,
~~~~
~~
IZKAI
Dynamic inipedance §
1
IkA = 1 mA to 100 mA,
VKA = VI(refl, I,;; 1 kHz
~l"l1
mV
sU>
laVKA = 10 V - VI(re!)
I(dev)
(VI
V
(ref) at 25:C )
--oc
(ppm)
~»
::DO
m~
0-'1
-2.7
-1.4
-2.7
-1.4
-3
-1
-2
-1
-2
-1
-2.3
2
4
2
4
2
8*
0.4
1.2
0.8
2.5
1
0.4
1
0.4
1
0.4
1.5
mA
-'I»
0.1
1
0.1
1
0.1
3
IlA
m-'l
0.2
0 ..5
0.2
0.5
0.2
0.9*
IKA=10mA
laVKA=36V-10V
:1>-'1
tar
r 0l:Io
mw
.....
-1.4
V
IlA
IlA
m
0
»
c
G>
C
U>
-I
cD
~
0~
0 .....
Z~-
0-'1
::J:S:
C: W
::D~-
VI(ref)=O
n
* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
t Full temperature range is O°C to 70°C for the TL431 C, -40°C to 85°C lorthe TL431I, and -55°C to 125°C for the TI,.431 M.
:j: The deviation parameters Vrefl(dev) and lrefl(dev) are defined as the differences between the maximum and minimum values obtained over the rated temperature range. The average
full-range temperature coefficient of the reference input voltage, aVI(re!), is defined as:
laVI(ref)I
I
~$').
Z .....
~~
i{/)
I
mV
!<
....
'"co
m
aVI(re!)
aVKA
f.1(1)
c
JJ
Ratio of change in reference input voltage to the
change in cathode voltage
~
22
mV
=
106
x
aTA
where a TA is the rated operating free-air temperature range of the device.
.... V" ...
Min VI(ref)
QT
.-
-
-
(24~~~V)
I VI(dev)
..L i...
~aTA~
x 106
= 23 ppm;oC
70°C
Because minimum VI(re!) occurs at the lower temperature, the coefficient is positive.
§ The dynamic impedance is defined as: I zKA I =
aV·
I KA
aKA
When the device is operating with two extemal resistors (see Figure 2), the total dynamic impedance of the circuit is given by: Iz'l =
r .....
~Ls:
O-t
::Dr
0f)
.....
-<
avl(ref) can be positive or negative depending on whether minimum VI(re!) or maximum VI(re!), respectively, occurs at the lower temperature.
Example: Max VI(re!) =2496 mV at 30°C, Min VI(ref) = 2492 mV at O°C, VI(re!) = 2495 mV at 25°C, aTA = 70°C lor TL43J C
laVI(ref)I =
C)s:
C: W
~~ =
IzKAI (1
+ ~)
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise noted)
TEST
CIRCUIT
PARAMETER
~-~
:liz
~cn
!!oi"o
§lid
i~~
~lTIGi
~~
TL431AC
TEST CONDITIONS
VI(refl
Reference input" voltage
1
VKA = VI(refl,
VI(dev)
Deviation of reference input voltage over full
temperature range:J:
1
VKA = VI(ref)' IKA = 10 rnA,
TA = Full ranget
AVllrel)
AVKA
Ratio of change in reference input voltege to the
change in cathode voltage
2
IKA=10mA
Illref)
Reference input current
2
IKA= 10 rnA,
II(dev)
Deviation of reference input current over full
temperature range:J:
2
R1 = 10 kn,
IKA= 10 rnA,
TA = Full range t
Imin
Minimum cathode current for regulation
1
VKA=VI(ref)
loff
Off-stete cathode current
3
VKA= 36 V,
1
VKA= VI(ref)'
IKA=1 mAt0100mA,
Is 1 kHz
IZkal
Dynamic impedance §
IKA=10mA
I AVKA = 10 V -
UNIT
TYP
MAX
MIN
TYP
MAX
2470
2495
2520
2470
2495
2520
mV
4
15
5
25
mV
-1.4
-2.7
-1.4
-2.7
mV
-1
-2
-1
-2
2
4
2
4
V
IlA
0.8
1.2
0.8
2.5
IlA
Vllrefl
IAVKA=36V-10V
R2=~
R1 = 10 k.O,
TL431AI
MIN
R2=~,
VI(ref) =0
0.4
0.6
0.4
0.7
rnA
0.1
0.5
0.1
0.5
IlA
0.2
0.5
0.2
0.5
Q
t Full temperature range is ooe to 70°C for the TL431 Ae and -40°C to 85°C for the TL431AI.
:J: The deviation parameters Vrefl(dev) and lrefl(dev) are defined as the differences between the maximum and minimum values obteined over the rated temperature range. The average
full-range temperature coefficient of the reference input v9ltege, aVI(ref), is defined as:
I(dev)
(VI(ref)
V at 25°C )
laVI(ref)I
106
x
(ppm)
OC =
ATA
Mu·''''":br
Min VI(ref)
-
-
-
c:-
en?
I VI(dev)
....I- .1.
~t;
m
......
where ATA is the rated operating free-air temperature range of the device.
m
avl(ref) can be positive or negative depending on whether minimum VI(ref) or maximum VI(ref), respectively, occurs at the lower temperature.
Example: MaxVI(ref) = 2496 mV at 30°C, Min VI(ref) = 2492 mV at ooe, VI(ref) = 2495 mV at 25°C, ATA = 70°C forTL431Ae
(2~~~V)
r~
m(')
~ ATA---+I
-a:"
%l r
m.l=o
Ul
x 106
!;:
=
!:(
enw
::::t: ......
~
-t-t
'-
c
!N
AI:;:
When the device is operating with two external resistors (see Figure 2), the totel dynamic impedance of the circuH is given by: Iz'l
= ~~
= IzKAI (1 +
~~)
JJ
~
1Ilc
~
c:~
z--
%IS;:
mw
C) ......
c:i:
r-
~?
§ 0.1=0
%I~
i en<
Gl
~
- ......
en(')W
~m 5:"
zs;:
= 23 ppmre
laVI(ref)1 =
70°C
Because minimum VI(ref) oocurs at the lower temperature, the coefficient is positive.
§ The dynamic impedance is defined as: I zKA I
~E
C ......
c..(')
~~
-
-t
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST1995
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
.
TEST
CIRCUIT
PARAMETER
VI(re!)
Relerence input voltage'
aVI(re!)
aVKA
Ratio 01 change in relerence input
voltage to the change in cathode
voltage
1
2
TL431Y
TEST CONDITIONS
VKA = VI(re!),
MIN
IKA=10mA
2495
aVKA = 10 V - VI (rei)
-1.4
II(ref)
Relerenceinput current
2
IKA=10mA,
Minimum cathode current lor regulation
1
VKA = VI (rei)
loff
Off-state cathode current
3
VKA=36V,
VI(ref)=0
VKA = VI(re!),
IS; 1 kHz
IKA = 1 mA to 100 mA,
t
1
The dynamic impedance is defined as:
R1=10kQ,
R2==
UNIT
mV
mV
V
-1
aVKA=36V-10V
Dynamic impedancet
MAX
IKA=10mA
Imin
IZKAI
TYP
2
I1A
0.4
mA
0.1
I1A
0.2
(1
mKA
I zka I = ~
KA
When the device is operating with two extemal resistors (see Figure 2), the total dynamic impedance 01 the circuit is given by:
Iz'l = aV =
al
Iz
KA
I (1
+B!)
R2
PARAMETER MEASUREMENT INFORMATION
Input -'I/IIv--....- - VKA
Input
~IKA
R1
R2
VI~ref)
1.
Figure 1. Test Circuit for VKA
=VI(ref)
+
R1)
R2
+
II(rel) x R1
Figure 2. Test Circuit for VKA > VI(ref)
Input -'I/IIv--....- - VKA
~ loff
Figure 3. Test Circuit for loff
~TEXAS
INSTRUMENTS
3-24
.
(
V KA = Vref 1
POST OfFICE BOX 655303 • DALLAS, TEXAS 75265
TL431C, TL431AC, TL431I, TL431 AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSOO5E - JULY 1978 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VI(ref)
Reference input voltage
vs Free-air temperature
4
II(ref)
Reference input current
vs Free-air temperature
5
IKA
Cathode current
vs Cathode voltage
loff
Off-state cathode current
vs Free-air temperature
aVI(ref)
Change in reference voltage to change in cathode voltage
vs Free-air temperature
Vn
Equivalent input noise voltage
vs Frequency over a 10-second time-period
AV
Small-signal voltage amplification
vs Frequency
12
IZKAI
Reference impedance
vs Frequency
13
6, 7
8
9
10,11
Pulse response
14
Stability boundary conditions
15
Table of Application Circuits
FIGURE
Precision shunt regulator
16
Single-supply comparator with temperature-compensated threshold
17
Precision high-current series regulator
18
Output control of a 3-terminal fixed regulator
19
High-current shunt regulator
20
Crowbar circuit
21
Precision 5-V, 1.5-A regulator
22
Efficient 5-V, precision regulator
23
PWM down converter with reference
24
Voltage monitor
25
Delay timer
26
Precision current limiter
27
Precision constant-current sink
28
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-25
TL431C,TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSOO5E - JULY 1978 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REFERENCE INPUT VOLTAGE.
REFERENCE INPUT CURRENT
_
va
2600
~
I
fit
!!
5
VKA = VI(ref)
2580 r- IKA=10mA
2540
I
..
2480
./
I
Iu
2460
'S
a.
"-
3
...
fl
-...
c
i
2
"""- ~
-75 -50-25
0
25
50
75 100
TA - Free-Air Temperature - °c
Figure 4
C
E
I
I
~
U
II
'8
.c
li
I
~
CATHODE CURRENT
va
va
CATHODE VOLTAGE
CATHODE VOLTAGE
800
vKA=
VI(ref)
TA=25°c
c
800
1
VKA=
VI(ref)
TA = 25°C
:::I.
75
I
C
~~
50
j
0
-100
-2
li
r
-25
-50
Imin ....
---.........
400
u
25
-75
/
/
.
I
~
/
-1
J
200
o
2
3
0
-200
-1
I
VKA - cathode Voltage - V
Figure 6
/'
2
o
VKA - Cathode Voltage - V
Figure 7
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
:I: Data is for devices having the indicated value of VI(rei) at IKA = 10 rnA, TA = 25°C.
~TEXAS
3-26
125
FigureS
I
rr-
-
o
125
CATHODE CURRENT
125
r-
J
T'
100
r-- r-
I
2400
-75 -50 -25
0
25
50
75
100
TA - Free-Air Temperature - °c
150
~
II:
~I
I
4
.5
VI(ref) = 2440 mV* _
2420
R1 =10kO
R2=oo
IKA=10mA
~
--
"...
1'2440
~
:::I.
VI(re1 = 2495 mV* _
2500
II:
.1,
~-
.V
~
2520
'S
a.
.5
J
J.
1
c
VI(ref) = 2550 mV*
2560
va
FREE-AIR TEMPERATUREt
FREE-AIR TEMPERATUREt
INSTRUMENTS
POST OFF~CE B9X 655303 • DALLAS•.·TEXAS 75265
3
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
RATIO OF DELTA REFERENCE VOLTAGE TO
DELTA CATHODE VOLTAGE
OFF-STATE CATHODE CURRENT
VB
VB.
FREE-AIR TEMPERATURE
2.5
0(
:::I.
I
FREE-AIR TEMPERATURE
-0.85
V~=36IV
VI(ref) = 0
-0.95
2
C
~
-80
1.5
/ -1-1.25
/
~
~
GI
~
I
~
-1.05
0.5
l/
o
-1.15
I
" '"
~
-1.35
-75 -50 -25
0
25
50
75 100
TA - Free-Air Temperature - °C
I
VKA =3 Vto36 V
"~
I
~
.c
5
~E
J
::>
(J
I
" '"
""-
'"
-1.45
-75 -50 -25
0
25
50
75 100
TA - Free-Air Tempereture - °C
125
FigureS
125
Figure 9
EQUIVALENT INPUT NOISE VOLTAGE
VB
FREQUENCY
~:;;
260
IO=10mA
TA=25°C
240
C
I
220
3.
:i
200
=
180
a.
.5
160
~
'6
Z
'$
I
::>
.[
I
~
l\
\
140
\
'\
"-
120
100
10
100
1k
10k
100k
t - Frequency - Hz
Figure 10
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
3-27
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSOO5E - JULY 1978 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
EQUIVALENT INPUT NOISE VOLTAGE
OVER A 1o-SECOND PERIOD
6
>::l.
5
4
I
&
:
3
~
2
·ftz
!i
II
.,•• I~
Ml
LII'.,
'I
0
".5
-1
C
II
I'
-2
I
:::I
-3
IT
w
I
-5
-6
J
I
f=0.1 to10Hz
IKA=10mA
TA=25°C
-4
c
>
"
I
1 J ,~1
iliUl
, II',,
o
1
2
3
4
5
6
t-Tlme-s
7
8
9
10
19.1 V
VCC
.-_-;f-_2OOO.., ~F
VCC
To Oscilloscope
>---*--*--I~~
TLE2027
8200
161<0
160
0.1
1601<0
~F
AV=2VN
331<0
VEE
-=
TEST CIRCUIT FOR EQUIVALENT INPUT NOISE VOLTAGE
Figure 11
~TEXAS
INSTRUMENTS
3-28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VEE
TL431C, TL431AC, TL431I, TL431 AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVrSEDAUGUST 1995
TYPICAL CHARACTERISTICS
SMALL-SIGNAL VOLTAGE AMPLIFICATION
vs
FREQUENCY
60
IKA=10
rnA
TA=2SoC
m
'0
I
C
0
SO
,~
~
u
:e
a.
.-----~t---~t__
IS 1<0
Output
2320
40
E
<
~t--
TEST CIRCUIT FOR VOLTAGE AMPLIFICATION
r'-- ......
o
1k
10 k
100 k
1M
10M
f - Frequency - Hz
Figure 12
REFERENCE IMPEDANCE
vs
FREQUENCY
100
t'"
~ IKA=10
I- rnA
I- TA = 2SOC
Cl
I
8c
01
'0
11<0
.----ef--A,II/Ir--e-__e_--- Output
10
~
.5
8c
I!!
~
a::
I
'----e>---.-__e_---
~
..!!
I
-=-
1/
0.1
1k
10 k
GND
TEST CIRCUIT FOR REFERENCE IMPEDANCE
100 k
1M
10M
f - Frequency - Hz
Figure 13
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-29
TL431C, TL431AC, TL431I, TL431AI, TL431M, TL431V
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
PULSE RESPONSE
6
TA=25°C
I
Input
2200
5
>
I
J
io
Ii
i
4
~
3
Pulse
Generator
t= 100 kHz
Output
'1:1
500
1/
2
GNO
TEST CIRCUIT FOR PULSE RESPONSE
o
o
2
3
4
t-Time-ItS
6
5
7
Figure 14
1500
STABILITY BOUNDARY CONDITIONS
100
90
""E
I
80
AVKA=VI~ref)
IKA=10
mA
TA = 25°C
BVKA=5V
CVKA= 10V
OVKA=1j. Vt
Bt
70
C
~
:::I
CJ
i.c
'Iii
Stable
60
50
At
40
CJ
I
;:!
30
20
10
o
0.001
TEST CIRCUIT FOR CURVE A
ct
Stable
J
/\
II I
of
II
II / / \
/1 .// ~ \\
0.01
0.1
CL - Load capacitance - ItF
R1=10kQ
•
+IIKA
R2
10
TEST CIRCL!IT FOR CURVES B, C, AND 0
Figure 15
fThe areas under the curves represent conditions that may cause the device to oscillate. For curves B. C. and D. R2 and V+ were adjusted to
establish the initial VKA and IKA conditions with CL = O. VBATT and CL were then adjusted to determine the ranges of stability.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL431 C, TL431 AC, TL431I, TL431 AI, TL431 M, TL431 V
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
APPLICATION INFORMATION
R
(see Note A)
VBATT~~~--------.
Vo
VBATT
R1
0.1%
VI(ref)-------,--hla.
TL431
TL431
R2
Input
--'\A/\r--II-&
0.1%
RETURN
Vth =2.5 V
----+--------.
Vo
Vo
Von=2V
Voff= VBATT
-~._~.--
GND
_ (1 + R2
R1) V'(ref)
-
NOTE A: R should provide cathode current;;, 1-rnA
to the TL431 at minimum VBATT.
Figure 17. Single-Supply Comparator With
Temperature-Compensated Threshold
Figure 16. Shunt Regulator
VBATT-~-----------'
NOTE A: R should provide cathode current;;, 1-mA to the TL431 at
minimum VBATT.
Figure 18. Precision High-Current Series Regulator
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
. 3-31
TL431C, TL431AC, TL431I, TL431AI, TL431M,TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
APPLICATION INFORMATION
VBATT
TL431
Vo =
(1
+
Min Vo = VI(ref)
--'\NI,--e..-----e----.- Vo
R2
~) VI(ref)
+
Figure 20. High-Current Shunt Regulator
5 V
Figure 19. Output Control of a Three-Terminal
Fixed Regulator
VBATT
~--e-----~~------~- Vo
R1
TL431
C
(see Note A)
R2
NOTE A: Refer to the stability boundary conditions in Figure 15 to determine
allowable values for C.
.
Figure 21. Crowbar Circuit
~TEXAS
3-32
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL431C, TL431AC, TL431I, TL431 AI, TL431M, TL431Y
ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS005E - JULY 1978 - REVISED AUGUST 1995
APPLICATION INFORMATION
VSATT
_~~IN~~~:t~O~UT1r
__
LM317
8.2 kn
Vo ~ 5 V. 1.5 A
VBATT --i"--..,(
) , - - - - VO~5V
Rb
Adjust
2430
0.1%
(see Note A) L----411
27.4 kn
0.1%
TL431
27.4 kn
0.1%
2430
0.1%
NOTE A. Rb should provide cathode current
I
8.
,
10
8
'S
t
0
6
./
I
~
/
TL7 LP08
'Sa.
TL7 LP48
f
I
120
80
=
60
I
TL75LP05
4
8
10
6
VI - Input Voltage - V
12
o
14
~
T
o
2
CC
E
250
I
C
~
200
'S
a.
.s
150
OUTPUT CURRENT
250
100
225
>
/
TL75LP05
I
Jf
8.
/
TL75LP10
~
~
'S
0
iL75LP12
TL75LP48
/
~
Q
175
/
150
/
125
100
50
o
o
/
200
E
TL75LP08
f-----,
.1,
TJ = 25°C
;;- ,. -
lJ
I
=
vs
INPUT VOLTAGE
I
u=
----
75
2
50
,4
1012
6
8
VI - Input Voltage - V
14
o
/
50
Figure 7
100
150
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
200
10 - Output Current - mA
FigureS
~TEXAS
3-46'
14
DROPOUT VOLTAGE
vs
,
300
12
Figure 6
INPUT CURRENT
10= 100 mA
TJ=25°C
LP12
75LP~8
4
8
10
6
VI- Input Voltage - V
Figure 5
350
TL75 P10
,.
20
.)
l'
k
40
2
J
TL75 P08
100
.s
2
o
o
140
I
C
~
u=
TL7 LP05
/
4
CC
-
1/'
V
160
E
/
~
~
~5LP10
10= ~OmA
TJ = 25°C
180
250
300'
TL75LPxxQ SERIES
TL75LPxxY SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS073A- SEPTEMBER 1992 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TL75LP05
SHORT-CIRCUIT PROTECTION CONDITIONS
OUTPUT VOLTAGE
QUIESCENT CURRENT
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
12
TJ = 25°C
VI=14V '
CC
5~~\~~~-+~~\~~
10
E
/
I
C
8
~::s
6
.::s1
a
4
I
9
- -
~
2
I
t
I
0
C
>
o
o
20
40
f--
60
--'
80
/
~
I
V
4r-+-H--*~~~~+-H-~
\
TJ = 25°C
3~~~+\~~~~~
I
~
100
120
10 - Output Current - mA
140
160
2
/
TJ = 40°C
o
"--'----'-\..I-J--J'' --'----'----'-....L......I\
0.75 0.85 0.95 1.05 1.15 1.25 1.35 1.45 1.55
10 - Output Current - A
Figure 9
Figure 10
LOAD TRANSIENT RESPONSE
,
>
200
I
•
100
~
0
LINE TRANSIENT RESPONSE
VI(NOM) = Vo + 1 V
ESR=2
IL=20mA
CL= 10llF
TA=25°C
E
1\
"J
1-100
::s
v
VI(NOM) = Vo + 1 V
-200 r-- ESR=2
CL= 1O IlF
~
cc 150 r-- TA=25°C
E
l"I
C 100
~
0
I
~
::s
50
...
0
0
'5
.5
\
TJ = 1250C;'\.--+--\\-+---+--+--~/t--I
:::
. roo-
.::
-
I
E
-50
o
50
100
150
200
250
300
350
o
t- Time-lIS
Figure 11
50 100 150 200 250 300 350 400
t- Time-lIS
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-47
TL750L, TL751 L SERIES
TL751L05M,TL751L12M,TL750LxxY
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 1987 - REVISED AUGUST 1995
• Very Low Dropout Voltage, Less Than 0.6 V
at 150 mA
• Very Low Quiescent Current
• TTL- and CMOS-Compatible Enable on
TL751L Series, TL751 L05M, and
TL751L12M
•
•
•
•
•
Reverse Transient Protection to -50 V
Internal Thermal Overload Protection
Overvoltage Protection
Internal Overcurrent Limiting Circuitry
Less Than 500-jlA Disable (TL751 L Series,
TL75L05M, and TL75L12M)
• 60-V Load-Dump Protection
description
The TL750L and TL751L series and the TL751L05M and TL751L12M are low-dropout positive voltage
regulators specifically designed for battery-powered systems. These devices incorporate overvoltage and
current-limiting protection circuitry along with internal reverse-battery protection circuitry to protect both itself
and the regulated system. Both the series and the TL751 L05M and TL751 L12M are fully protected against 60-V
load-dump and reverse-battery conditions. Extremely low quiescent current during full-load conditions makes
these devices ideal for standby power systems.
The TL750L series of fixed-output voltage regulators offer 5-V, a-v, 10-V, and 12-V options. They are available
in TO-226AA (formerly TO-92) (LP) packages, TO-220AB (KG) packages, a-pin small-outline plastic packages
(D), and a-pin plastic dual-in-line packages (P).
The TL751 L series of fixed-output voltage regulators offer 5-V, a-v, 10-V, and 12-V options with the addition of
an enable input. The enable input, when taken high, places the regulator output in a high-impedance state. This
gives the designer complete control over power up, power down, or emergency shut down. This series is offered
in the a-pin small-outline plastic package and the a-pin plastic dual-in-line package.
The TL751 L05M and TL751 L12M fixed-output voltage regulators also offer 5-V and 12-V options with an enable
input. The enable input, when taken high, places the regulator output in a high-impedance state. This gives the
designer complete control over power up, power down, or emergency shut down. The TL751 LxM is offered in
the FK and JG package.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
O°Clo
125°C
-40°C 10
125°C
-55°C 10
"125°C
Votyp
AT 25°C
TO-226AA
(LP)
CERAMIC
FLATPACK
(P)
-
TL750L05CKC
TL750L05CLP
TL750L05CP
TL751 L05CP
TL750L05Y
-
TL750L08CKC
TL750L08CLP
TL750L08CP
TL751 L08CP
TL750L08Y
TL750L10CKC
TL750L 1OCLP
TL750L10CP
TL751L10CP
TL750Ll0Y
-
TL750L12CKC
TL750L12CLP
TL750L12CP
TL751L12CP
TL750L12Y
-
TL750L050KC
TL750L05QLP
TL750L05QP
TL751 L050P
-
TL750L080LP
TL750L080P
TL751 L08QP
-
TL750L 1OOKC
TL750Ll0QLP
TL750Ll0QP
TL751Ll00P
-
TL750L l20KC
TL750L l20LP
TL750L120P
TL751L120P
-
CHIP
CARRIER
(FK)
5V
TL750L05CO
TL751 L05CO
-
8V
TL750L08CO
TL751 L08CO
-
10V
TL750L10CO
TL751Ll0CO
-
-
l2V
TL750L12CO
TL751L12CO
-
5V
TL750L0500
TL751 L05QO
-
8V
TL750L0800
TL751 L0800
10V
TL750Ll000
TL751Ll000
-
-
12V
TL750L1200
TL751L1200
-
-
-
TL751 L05MFK
TL751 L05MJG
TL751L12MFK
TL751L12MJG
5V
l2V
-
PRODUCTION DATA infonnation ia current .. of pub_on - .
Products confonn to spacffications per the terms of Texas Instnunents
standard warranty. Production p!UC888ing does not n......rily inciude
l88Iing of aii parameters.
CHIP
FORM
(V)
To-220AB
(KC)
SMALL
OUTLINE
(D)
CERAMIC
DIP
(JG)
-
TL750L080KC
-
~TEXAS
INSTRUMENTS
POST OFFiCE BOX 655303 • DALLAS, TEXAS 75265
-
-
-
Copyright © 1995, Texas Instruments Incorporated
On products compliant to MILooSTD-883, Class B, an parameters 81'8
=~~=.:..no:t-lyrnJ:!t:='::':=
3-49
TL750L, TL751 L SERIES
TL751L05M,TL751L12M, TL750LxxY
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 187 - REVISED AUGUST 1995
TL750L •.• KC
HEAT-SINK-MOUNTED PACKAGE
(TOP VIEW)
Tl750L ... D
SMA Lt.-OUTLINE PACKAGE
(TOP VIEW)
TL750L .•. LP
SILECT'M PAC~GE
(TOP VIEW)
INPUT
OUTPUT[J8 INPUT
COMMON ·.2
7 COMMON
COMMON 3
. 6 COMMON
NC
4
5
COMMON
NC
OUTPUT
The common terminal is In electrical
contact with the mounting base.
To-226AA
To-220AB
TL751L ••. D
!;lMALL-OUTLINE PACKAGE
(TOP VIEW)
TL750L .•• P
DUAL-IN-LiNE PACKAGE
(TOP VIEW)
OUTPUT[]8
NC 2
7
NC 3
6
NC 4
5
OUTPUT[]8
COMMON 2
7
COMMON 3
6
NC 4
5
INPUT
NC
COMMON
NC
lU5H.... P
DUAL-IN,LlNE PACKAGE
(TOPyIEW)
INPUT
COMMON
COMMON
ENABLE
TL751 L05M, TL751L12M ..• FK PACKAGE
(TOP VIEW)
OUTPUTD8 INPUT
NC27NC
.
NC 3
6 COMMON
NC 4
. 5 ENABLE
TL751 L05M, TL751 L 12M ••• JG PACKAGE
(TOP VIEW)
I-
::::>
I=:
l-
::::>
c.>::::>0
c.> ~c.>
z
z_z
NC
NC
NC
NC
NC
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 1011 1213
OUTPUTO·
8
NC2
7
NC 3
6
NC 4
5
NC
NC
NC
COMMON
NC
Nc:.No internal connection
ACTUAL DEVICE
COMPONENT COUNT
Transistors
20
JFET
2
Diode!!
5
Resistors
16
SILECT is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS·
3-50
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
INP.UT
NC
COMMON
ENABLE
TL750L, TL751 L SERIES
TL751 L05M, TL751L12M, TL750LxxV
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 1987 - REVISED AUGUST 1995
TL750LxxY chip information
These chips, when properly assembled, display characteristics similar to the TL750LxxC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
OUTPUT (1)
COMMON (2)
TL750LxxY
COMMON (3)
(8)
INPUT
(7)
COMMON
(6)
COMMON
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax= 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
TERMINAL NUMBERS ARE FOR THE
TL750 D AND P PACKAGES
TERMINALS 2, 3, 6, AND 7 ARE CONNECTED TOGETHER
TERMINALS 4 AND 5 ARE NOT CONNECTED
14
45
~I
1'1'1'1'1'1'1'1'1'1'1 11 '1'1'1'1'1'1'1'1'1'1'1'
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-51
TL750L, TL751 L SERIES
TL751L05M, TL751L12M, TL750LxxY
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 187 - REVISED AUGUST 1995
absolute maximum ratings over operating junction temperature range (unless otherwise noted)
TL750L
TL751L
TL751L_M
UNIT
Continuous input voltage
26'
26
V
Transient input voltage, TA = 25°C (see Note 1)
60
60
V
Continuous reverse input voltage
-15
-15
V
Transient reverse input voltage: t ~ 100 ms
,-50
-50
V
Continuous total power dissipation
See Dissipation Rating Table'
Operating virtual junction temperature range, TJ
-40 to 150
"
-65 to 150
Storage temperature range, Tsta
Lead temperature 1,6 mm (1116 inch) for 10 seconds
-40 to 150
°C
-65 to 150
°C
260
°C
260
NOTE 1: The transient Input voltage rating applies for the waveform descnbed In Figure 1.
DISSIPATION RATING TABLE
PACKAGE
TA~25°C
POWER RATING
D
FK
JG
KC
LP
P
825mW
1375mW
1050mW
2000mW
775mW
1000mW
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
6.6mWPC
11.0mWPC
528mW
880mW
672/mW
1316mW
496mW
640mW
429mW
715inW
546mW
1088mW
403mW
520mW
8.4mW/oC
15.2mWPC
6.2mWrC
8.0mW/oC
recommended operating conditions over recommended operating junction temperature range
(unless otherwise noted)
MIN
MAX
8
26
TL75_L08
9
26
TL75_L10
11
26
TL75 L12 and TL751L12M
13
26
TL75_L05 and TL751 L05M
Input voltage, VI
High-level ENABLE input voltage, VIH
LOW-level ENABLE input voltage, VILt
I TA = 25°C
JTA = Full range
Output current range, 10
Operating virtual junction temperature, TJ
t
..
TL751 Land TL751 L_M
2
15
TL751 Land TL751 L.:.M
-0.3
0:8
TL751 Land TL751 L.:.M
-0.15
0.8
TL75_L and TL751 L_M
0
150
TL75_L_C
0
125
TL75 L.:.Q
-40
125
TL751L.:.M
-55
125
..
UNITS
V
V
V
mA
°C
The algebraiC convention, In which the least positive (most negatIVe) value IS deSignated minimum, IS used In thiS data sheet for ENABLE voltage
levels and temperature only.
~TEXAS
INSTRUMENTS
3--52
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL750L, TL751 L SERIES
TL751 L05M, TL751L12M,TL750LxxV
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 1987 - REVISED AUGUST 1995
electrical characteristics, VI
=14 V, 10 =10 rnA, TJ =25°C (unless otherwise noted)
TEST CONDITIONS;
PARAMETER
Output voltage
Input regulation voltage
ITJ=25°C
10=Oto 150mA I TJ = TJmin to 125°C
VI =6Vt026V
TYP
4.80
5
4.75
10
6
30
10=5mAto150mA
f=120Hz
60'
65
20
10=10mA
0.2
0.6
f=10Hztol00kHz
500
10
VI = 6 V to 26 V,
10= 10mA,
1
TJ = TJmin to 125°C
V
mV
dB
50
10=150mA
10=150mA
Input bias current
5.2
5.25
5
VI=8Vto18V,
UNIT
MAX
VI=6Vt026V
Ripple rejection
Output noise voltage
MIN
VI=9Vto16V
Output regulation voltage
Dropout voltage
TL750L05,TL751L05
TL751 L05M
mV
V
I'V
12
2
mA
0.5
ENABLE>2V
'On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
=1= Pulse-testing techniques are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.l-I'F capacitor across the input and a 10-I'F capacitor, with equivalent
series resistance of less than 1 {1 across the output.
electrical characteristics, VI
=14 V, 10 =10 rnA, TJ =25°C (unless otherwise noted)
TEST CONDITIONS;
PARAMETER
Output voltage
Input regulation voltage
VI =9Vt026V
MAX
8
8.32
7.6
8.4
20
VI =9Vt026V
25
50
VI=ll Vt021 V,
10= 5 mA to 150 mA
1= 120 Hz
60'
65
40
10= 10mA
0.2
0.6
f=10Hzt0100kHz
500
10
VI = 9 V to 26 V,
10=10mA,
T J = TJmin to 125°C
ENABLE>2V
1
UNIT
V
mV
dB
80
10=150mA
10= 150mA
Input bias current
TYP
10
Ripple rejection
Output noise voltage
MIN
7.68
VI=10Vto17V
Output regulation voltage
Dropout voltage
ITJ=25°C
10=Oto150mA ITJ = T
' to 1250C
Jmln
TL750L08,TL751LOB
mV
V
I'V
12
2
mA
0.5
'On products compliant to MIL-STD-883, Class B, thiS parameter IS not production tested.
=1= Pulse-testing techniques are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.l-I'F capacitor across the input and a 10-I'F capacitor, with equivalent
series resistance 01 less than 1 {1 across the output.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3--53
TL750L, TL751 L SERIES
TL751 L05M, TL7S1L12M, TL750LxxY
LOW-DROPOUT VOLTAGE REGULATORS
SLVSOI78 - SEPTEMBER 187 - REVISED AUGUST 1995
electrical characteristics, VI = 14 V, 10 =10 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Input regulation voltage
TEST CONDITIONS'"
.
..
ITJ=25°C
10=Oto 150 inA I TJ = TJmin to 125°C
VI =11 Vto 26 V
TYP
9.6
10
9.5
10
25
60
50
100
10=5mAto150mA
f= 120 Hz
60
0.6
1 = 10 Hz to 100 kHz
700
10
VI=11Vt026V,
10=10mA,
1
TJ = TJmin to 125°C
ENABLE>2V
UNIT
V
mV
dB
0.2
10=10mA
10=I50mA
10= 150 mA
t
10.4
10.5
30
65
VI=12Vto22V,
Input bias current
MAX
VI = 11 V to 26 V
Ripple rejection
Output noise voltage
MIN
VI,;,12VtoI9V
Output regulation voltage
Dropout voltage
TL750L10,TL751L10
mV
V
I1V
12
2
mA
0.5
Pulse-testing techniques are used to maintain the junction temperature as closes.to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O. l-I1F capacitor across the input and a 10-I1F capacitor, with equivalent
series resistance 01 less than 1 n across the output.
electrical characteristics, VI ; 14 V, 10 = 10 mA, TJ = 25°C (unless otherwise noted)
TEST CONDITIONS'"
PARAMETER
Output voltage
Input regulation voltage
VI=13Vt026V
MAX
11.52
12
12.48
11.4
12.6
15
20
Output regulation voltage
10=5mAto150mA
SO·
f=120Hz
10=10m~
120
mV
dB
0.6
1 = 10 Hz to 100 kHz
700
10
VI=13Vt026V,
10=10mA,
TJ = TJinin to 125°C
ENABLE>2V
1
V
mV
0.2
10= 150mA
UNIT
30
40
55
50.
10=150mA
Input bias current
TYP
VI = 13 V to 26 V
VI=13Vt023V,
Output noise voltage
I TJ = TJmin to 125°C
MIN
VI=14VtoI9V
Ripple rejection
Dropout voltage
ITJ=25°C
10=Oto lSOmA
TL750L12,TL751L12
TL751L12M
V
I1V
12
2
mA
0.5
• On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
t Pulse-testing techniques are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.I-I1F capacitor across the input and a 10-I1F capacitor, with equivalent
series resistance 01 less than 1 n across the output.
~TEXAS
INSTRUMENTS
3--54
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL750L, TL751 L SERIES
TL751 L05M, TL751L12M, TL750LxxV
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 1987 - REVISED AUGUST 1995
electrical characteristicsVI
=14 V, 10 =10 mA, TJ =25°C (unless otherwise noted)
PARAMETER
Output voltage
TEST CONDITIONS'
VI =6Vto26V
TL750LOSY
MIN
TYP
5
10=Oto150mA
VI=9VtoI6V
Input regulation voltage
VI=8VtoI8V,
Output regulation voltage
Output noise voltage
65
dB
10=5mAto150mA
20
mV
1= 10 Hz to 100kHz
500
10=150mA
Input bias current
mV
6
1=120Hz
UNIT
V
5
VI =6Vt026V
Ripple rejection
MAX
VI = 6 V to 26 V,
I1V
10
rnA
1
10= 10 rnA
t Pulse-testing techniques are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.I-I1F capacitor across the input and a 10-I1F capacitor, with equivalent
series resistance 01 less than 1 Q across the output.
electrical characteristics, VI
PARAMETER
Output voltage
Input regulation voltage
=14 V, 10 =10 mA, TJ =25°C (unless otherwise noted)
TEST CONDITIONS'
VI =9Vt026V
TYP
8
10
VI = 10Vto 17V
25
VI =9Vt026V
MAX
UNIT
V
mV
65
dB
10=5mAto150mA
40
mV
1= 10 Hz to 100kHz
500
Ripple rejection
VI = 11 Vt021 V,
Output regulation voltage
Output noise voltage
Input bias current
10=Oto150mA
TL750LOBY
MiN
1= 120 Hz
10
10=150mA
VI = 9 V to 26 V,
10=10mA
1
I1V
rnA
:t: Pulse-testing techniques are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.I-I1F capacitor across the input and a 10-I1F capacitor, with equivalent
series resistance 01 less than 1 Q across the output.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-55
TL750L, TL751 L SERIES
TL751L05M, TL75.1L12M, TL750LxxY·
LOW-DROPOUTVOLTAGE REGULATORS
SLVS017B - SEPTEMBER 187 - REVISED AUGUST 1995
electrical characteristics, VI
=14 V, 10 = 10 mA, TJ =25°C (unless otherwise noted)
PARAMETER
Output voltage
TEST CONDITIONS'
C
Input regulation voltage
VI=llVto26V
TL750L10Y
MIN
10=Otol50mA
TYP
MAX
V
10
VI=12Vto19V
10
VI=11Vt026V
30
1=120Hz
UNIT
mV
Ripple rejection
VI = 12Vt022V,
65
dB
Output regulation voltaQe
10 = 5 mA to 150 mA
50
mV
Output noise voltage
1=10HztolOOkHz
700
I1V
10= 150 rnA
Input bias current
VI=ll Vl026 V,
10
mA
1
10= 10mA
..
t Pulse-testing technIques are used to maIntain the Junction temperature as closes to the ambIent temperature as possIble. Thermal effects must
be taken into account separately. All characteristics are measured with a O.l-I1F capacitor across the input and a 1O-itF capacitor, with equivalent
series resistance Cli less than 1 n across the output.
electrical characteristics, VI
PARAMETER
Output voltage
Input regulation voltage
TEST CONDITIONS'
VI=13Vt026V
10=Oto150mA
TL750L12Y
MIN
TYP
12
VI=14Vto19V
15
VI=13Vt026V
20
1= 120 Hz
MAX
UNIT
V
mV
Ripple rejection
VI=13Vt023V,
55
dB
Output regulation voltage
10 = 5 rnA to 150 rnA
50
mV
Output noise voltage
1= 10 Hz to 100kHz
700
I1V
Input bias current
t
=14 V, 10 =10 mA, TJ =25°C (unless otherwise noted)
10
10= 150 mA
VI= 13Vt026V,
10= 10 mA
1
rnA
Pulse-testing techniqu~ are used to maintain the junction temperature as closes to the ambient temperature as possible. Thermal effects must
be taken into account separately. All characteristics are measured with a O.l-I1F capacitor across the input and a 10-I1F capacitor, with equivalent
series resistance 01 less than 1 n across the output.
~TEXAS
INSTRUMENTS
3-56
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL750L, TL751 L SERIES
TL751 L05M, TL751L12M, TL750LxxY
LOW-DROPOUT VOLTAGE REGULATORS
SLVS017B - SEPTEMBER 1987 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TL750L05
INPUT CURRENT
TRANSIENT INPUT VOLTAGE
60
>
50
I
:Il!
~
40
;
D..
.5
30
C
II
..
vs
INPUT VOLTAGE
~ t'-...
I
U
............
200
'"
300
400
25
/
20
D..
.5
~
15
10
5
500
I
o
o
600
/
I
7
I
=
-
I
'.5
r--
10
100
7
30
C
~
:::I
I"-tr =1ms
o
35
E
20
o
I
CC
C
~
I
'>
I
VI = 14 V + 46e(-t/O·230)
fort;" 5 ms
\ I\.
............
OJ
40
TA~250C
~
II
CI
vs
TIME
l'
2
3
4
5
6
VI - Input Voltage - V
t-Time-ms
Figure 2
Figure 1
TL750L12
INPUT CURRENT
vs
INPUT VOLTAGE
60
./
50
V
CC
E
I
C
~
:::I
u
I
40
I
30
/
;
D..
.5
I
=
20
I
10
o
n
o
V
2
4
6
8
10
12
14
VI - Input Voltage - V
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 '. DALLAS, TEXAS 75265
3-57
3-58
TL750M, TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021 D - JANUARY 1988 -
• Very Low Dropout Voltage, Less Than O.S V
at750mA
• Low Quiescent Current
• TTL- and CMOS-Compatible Enable on
TL751 M Series
•
•
•
•
1995
SO-V Load-Dump Protection
Overvoltage Protection
Internal Thermal Overload Protection
Internal Overcurrent Limiting Circuitry
description
The TL750M and TL751 M series are low-dropout positive voltage regulators specifically designed for
battery-powered systems. The TL750M and TL751 M incorporate on-board overvoltage and current-limit
protection circuitry to protect both themselves and the regulated system. Both series are fully protected against
60-V load-dump and reverse battery conditions. Extremely low quiescent current, even during full-load
conditions, makes the TL750M and TL751M series ideal for standby power systems.
The TL 750M series of fixed-output voltage regulators offer 5-V, 8-V, 10-V, and 12-V options available in 3-lead
KC (TO-220AB) and KTE plastic packages.
The TL751 M series of fixed-output voltage regulators also offer 5-V, 8-V, 10-V, and 12-V options with the addition
of an enable input. The enable input gives the designer complete control over power up, allowing sequential
power up or emergency shutdown. When taken high, the enable input places the regulator output in a highimpedance state. It is completely TTL- and CMOS-compatible. The TL751 M series is offered in 5-lead KC and
KTG plastic packages.
The TL750MxxC and TL751MxxC are characterized for operation from O°C to 125°C virtual junction
temperature, and the TL750MxxQ and TL751 MxxQ series are characterized for operation from -40°C to 125°C
virtual junction temperature.
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
O°Cto 125°C
-40°C to 125°C
VOTYP
(V)
HEAT-SINK MOUNTED
(loPIN)
(KC)
HEAT-SINK MOUNTED
(S-PIN)
(KC)
PLASTIC
FLANGE-MOUNT
(KTE)
PLASTIC
FLANGE-MOUNT
(KTG)
CHIP
FORM
(V)
5
TL750M05CKC
TL751 M05CKC
TL750M05CKTG
TL751 M05CKTG
S
TL750MOSCKC
TL751 MOSCKC
TL750MOSCKTG
TL751 MOSCKTG
TL750MOSY
10
TL750M10CKC
TL751M10CKC
TL750M1 OCKTG'
TL751M10CKTG
TL750M10Y
TL750M05Y
12
TL750M12CKC
TL751M12CKC
TL750M12CKTG
TL751M12CKTG
TL750M12Y
5
TL750M050KC
TL751 M050KC
TL750M050KTG
TL751 M050KTG
-
S
TL750MOSOKC
TL751 MOSOKC
TL750MOSOKTG
TL751 MOSOKTG
10
TL750M1OQKC
TL751 M1 OOKC
TL750M100KTG
TL751M100KTG
12
TL750M120KC
TL751M120KC
TL750M120KTG
TL751M120KTG
PRODUCTlON DATA I_Ion is currant as 01 publication dale.
Products confonn to specifications per the terms of Texas Instruments
standant warnmty. ProduCllon processing does not necesaarily Include
_ng 01 all parameters.
~TEXAS
-
-
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-59
TL750M,TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021 D - JANUARY 1988 - REVISED AUGUST 1995
TL750M ••• 3-LEAD KC PACKAGE
(TOP VIEW)
TL750M ••• 3-LEAD KTE PACKAGE
(TOP VIEW)
". .
[0:
OUTPUT
COMMON
INPUT
OUTPUT
COMMON
INPUT
·NOTE A: The common tenninal is in electrical contact with the mounting base.
TO-200AB
TL751 M ••• 5-LEAD KC PACKAGE
(TOP VIEW)
TL750M .•• 5-LEAD KTG PACKAGE
(TOP VIEW)
§I I
[[l
.'
.
.
.'
NC
OUTPUT
COMMON
INPUT
ENABLE
NOTE A: The common tenninal is in electrical contact with the mounting base.
E
NC - No internal connection
TI,.751 Mxx functional block diagram
ACTUAL DEVICE
COMPONENT COUNT
Transistors
ENABLE---I-I
28V
OUT
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
46
Diodes
14
Resistors
44
CapacHors
4
JFET
1
Tunnels
(emitterR)
2
TL750M, TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021D - JANUARY 1988 - REVISED AUGUST 1995
Tl750MxxY chip information
This chip, when properly assembled, displays characteristics similarto the TL750MxxC. Thermal compression
or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=
-=-=
-=
-=
-=-=
OUTPUT
COMMON
-=-=
-=
-=
-=-=
-=
CHIP THICKNESS: 11 MILS TYPICAL
-=-=
-=
-=
-=
-=
-=
BONDING PADS: 7 X 7 MILS MINIMUM
TJrnax = 150'C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
-=-=
-=
-=-=
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-61
TL750M, TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021D -JANUARY 1988 - REVISED AUGUST 1995
absolute maximum ratings over virtual junction temperature range (unless otherwise noted}t
Continuous input voltage ................................................................... 26 V
Transient input voltage (see Figure 5) ....................................................... 60 V
Continuous reverse input voltage ................................................. ,. . . . . . . .. -15 V
Transient reverse input voltage: t 100 ms .................................................. -50 V
Continuous total power dissipation at (or below) 25°C free-air temperature (see Note 1) ............. 2 W
Continuous total power dissipation at (or below) 40°C case temperature (see Note 1) .............. 20 W
Operating free-air, TA, case, T C, or virtual junction, T j, temperature range .............. -40°C to 150°C
Storage temperature range, Tstg ........................................... '" . . . . .. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
=
t
Stresses beyond those listed under "absolute maximum ratings" may cause pennanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: For operation above TA = 25°C and TC = 40°C, refer to Figures 1 and 2. To avoid exceeding the design maximum virtual junction
temperature, these ratings should not be exceeded. Due to variation in individual device electrical characteristics and thennal
resistance, the built-in thennal overload protection may be activated at power levels slightly above or below the rated dissipation.
CASE TEMPERATURE
DISSIPATION DERATING CURVE
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
2000
~I
c
~
t
.;;
is.
'c"
0
'"
~
1S00
1600
1400
1000
.~'"
to
800
;::
I
C
i.;;
600
400
=16 mW/"C
RaJA ~ f2•5°C/W J
:i
Derating Factor
200
.!Il
..'"
Q
"-
~
'",.
15
0
'"
c
'""
i0
u
50
75
100
125
TA - Free-Air Temperature - °c
10
E
E
'" ~
'"
'j(
to
:i
1"'-
0
25
20
Q.
,
1200
S
e
"'"
'"'""'-"-
25
."\..
150
5
Derating Factor
Above 40°C
o
=f1.S mW/"lc
RaJC~ ~.5°C/W
25
50
Figure 1
75
100
125
TC - Case Temperature - °c
150
Figure 2
recommended operating conditions over recommended virtual junction temperature range
MIN
MAX
6
26
TL75xM08
9
26
TL75xM10
11
26
26
TL75xM05
Input voltage range, VI
TL75xM12
13
High-level ENABLE input voltage, VIH
TL751Mxx
2
15
Low-level ENABLE input voltage, VIL
TL751Mxx
0
0.8
TL75xMxi
50
I
8.
:Ill
~
'5
Q.
.5
C
~
'\
40
I
14
I
TJ = 25. Q C
VI = 14 V + 46e(-tlO.230)
fort;:;'5ms
~
20
"
-
>
"'- ..........
tr=1 ms
:Ill
~ r--
I
TL75Xj10
8
1,;
r---
~
6
0
I
-?
/
4
200
300
400
5.00
600
o
o
TL75xM08
I
J
TL75xM05
J
2
t-TIme-ms
FigureS
4
10
6
8
VI - Input Voltage - V
Figure 6
~TEXAS
INSTRUMENTS
3-68
/
L
(
2
100
1/1
1/1
10
~
10
o
TL75~M12
-'
I
III
DI
;;
o
I
10'" 10mA
12 f- TJ '" 25°~
"
30 I-
~c
~
_t
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
POST OFFICE BOX 655303 • DALLAS; TEXAS 75265
12
14
TL750M, TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021D - JANUARY 1988 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
INPUT CURRENT
200
180
140
C
120
~
U
100
OJ0-
80
.5
I
--
INPUT VOLTAGE
350
!
I
TJ = 25°C
IV
""E
~
:::I
40
OJ0-
co
0
'"
~I- ~I- ~I- iI."
I!!
!::i!::i!::ii=!lIl-
I
20
0
2
~
200
4
6
8
10
12
:g- I-~
:;:
., 1
J
150
2
0
4
6
10
8
VI - Input Vohage - V
~
&
0-
f
Q
vs
OUTPUT CURRENT
OUTPUT CURRENT
12
I
TJ = 25°C
Tj = 25°C
V,=14V
200
""E
/
175
U
C
III
/'
4
I
9
2
o
50
/
6
§
"S
0
75
50
8
~
:::I
/
~
/
I
C
/
150
100
10
/
125
14
12
QUIESCENT CURRENT
vs
E
~
:1
~- ri=!
Figure 8
225
GI
aI
I-~
0
14
DROPOUT VOLTAGE
I
~I
50
Figure 7
>
C!-
100
VI - Input Voltage - V
250
~I
~- r-~
I
I
--
I
0
250
U
.5
V.
ff
C
I
I
I
I.
I
J
60
I
10= l00mA
300 I- TJ = 25°C
I
II
I
:::I
vs
INPUT VOLTAGE
f- 10 = 10 mA
160
'""E
INPUT CURRENT
vs
100
150
200
10 - Output Current - mA
250
o
300
o
~~
20
Figure 9
~
~tr
L
~(
40
60
80
100 150
10 - Output Current - mA
250
350
Figure 10
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
3-69
TL750M, TL751 M SERIES
LOW-DROPOUT VOLTAGE REGULATORS
SLVS021 D - JANUARY 1988 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
>e
LOAD TRANSIENT RESPONSE
e
I
8.
I
t
100
~
'\J,
a
~ ~
VI(NOM) = vo + 1 V
~ -200 -eSR=2
CL=10JlF
150 I--- TJ = 25°C
100
(,)
'"
50
~
0
1\
I
I
I
e
- >e
0
C
~
I
I
I
I
VI(NOM) = vo + 1 V
ESR=2
IL=20mA
CL=10JlF
TJ = 25°C
.l! >
1\ ,
~
0
'SCI.
'S -100
'e"
LINE TRANSIENT RESPONSE
>
200
~
.~
r-- -
r--
'S
0
I
9
o
50
100
150
200
250
300
350
o
20
t-Time-J.lS
60
SO
100
t-llme-J.lS
Figure 11
Figure 12
~TEXAS
3-7.0
40
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
150
250
350
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B -APRIL 1981 - REVISED AUGUST 1995
KCPACKAGE
(TOP VIEW)
• ±10/0 Output Tolerance at 25°C
• ±20/0 Output Tolerance Over Full Operating
Range
OUTPUT
COMMON
INPUT
• Thermal Shutdown
• Internal Short-Circuit Current Limiting
The common terminal is in electrical
contact with the mounting base.
• Pinout Identical to j.tA7800 Series
• Improved Version of ~A7800 Series
TO-200AB
description
Each fixed-voltage precIsion regulator in this
series is capable of supplying 1.5 A of load
current. A unique temperature-compensation
technique coupled with an internally trimmed
band-gap reference has resulted in improved
accuracy when compared to other 3-terminal
regulators. Advanced layout techniques provide
excellent line, load, and thermal regulation. The
internal current limiting and thermal shutdown
features make the devices essentially immune to
overload.
AVAILABLE OPTIONS
PACKAGED DEVICES
CHIP
FORM
(V)
TJ
VoTYP
(V)
5
TL78005CKC
TL78005V
O°Cto 125°C
12
TL78012CKC
TL78012Y
15
TL78015CKC
TL78015Y
HEAT-SINK MOUNTED
(3-PIN)
(KC)
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-71
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B -APRIL 1981 - REVISED AUGUST 1995
schematic
r-~-----------------'----~----------------~~--~--------~INPUT
L.....--.-____-*-__
_*_- OUTPUT
~-.--~~~----._----~~~------~--~~--------._-----------COMMON
~TEXAS
INSTRUMENTS
3-72
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B - APRIL 1981 - REVISED AUGUST 1995
TL780-05Y, TL780-12Y, and TL780-15Y chip information
These chips, when properly assembled, display characteristics similar to the TL780-xxC Series. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=-=
-=
-=-=
-=
-=-=
-=-=
-=-=
-=-=
-=
-=-=
-=-=
-=
COMMON
-=
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
-=-=
-=-=
TJmax
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
-=-=
/
~
n
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1',1'1'1'1'1'1'1'1'1'1'1'1'1'1'
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-73
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVSOs5B-APRIL 1981- REVISED AUGUST 1995
absolute maximum ratings over operating temperature range {unless otherwise noted)t
'Input voltage, VI .......................................................................... 35 V
Continuous total dissipation at TA = 25°C (see Note 1) .......................................... 2 W
Continuous total power dissipation at (or below) TC 25°C (see Note 1) ......................... 15 W
Operating free-air, TA, case, T C' or virtual junction, TJ, temperature range ................. O°C to 150°C
Storage temperature range, Tstg ...........•......•............................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ,............................... 260°C
=
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at Ihese or any other cond~ions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: For operation above TA = 25°C or TC = 25°C, refer to Figures 1 and 2. To avoid exceeding the design maximum virtual junction
temperature, these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal
resistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation,
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
~ 2000
I
6
i
iis
1800
f'\..
1600
1400
CASE TEMPERATURE
DISSIPATION DERATING CURVE
~
t
16
I
'"f'\..
~
\
~ 12
c
I
r'\.
\
10
,II.
'"""
"'"
'"
Derating factor = 16 mW/"C
RaJA = 62.5°CJW I
50
\
14
75
100
125
TA - Free-Air Temperature - °C
150
~
i
8
§
I
8
\
6
\
4
_",_.,,,"wrc.-",,,, ~
2
~c o
\
,RaJC = 1°CIW
25
Figure 1
I
J
I
50
75
100
125
TC - Case Temperature - °C
150
Figute2
recommended operating conditions
MIN
MAX
7
25
TL780-12C
14.5
30
TL780-15C
17.5
30
1.5
A
0
125
°C
TL780-05C
Input voltage, VI
Output current, 10
Operating virtual junction temperature, TJ
~TEXAS
INSTRUMENTS
3-74
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
V
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B-APRIL 1981- REVISEDAUGUST1995
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
Ripple rejection
MIN
TYP
MAX
25°C
4.95
5
5.05
O°C to 125°C
4.9
V, =7Vt025V
25°C
V,=BVtoI2V
V, = 8 V to 18 V,
Output voltage regulation
TJt
P";15W,
V, = 7Vt020V
Input voltage regulation
TL7SIl-OSC
TEST CONDITIONS
'0=5mAtolA,
Output voltage
1 = 120 Hz
O°C to 125°C
10= 5mAto 1.5A
70
25°C
10 = 250 mA to 750 mA
5.1
0.5
5
0.5
5
85
25
1.5
15
Output resistance
1= 1 kHz
0°Cl0 125°C
0.0035
O°C to 125°C
0.25
Output noise voltage
'0=5mA
1= 10 Hz to 100 kHz
Dropout voltage
10=1 A
Input bias current change
V, =7Vt025V
25°C
75
25°C
2
25°C
5
O°C to 125°C
'0=5mAtolA
UNIT
V
mV
dB
4
Temperature coefficient 01 output voltage
Input bias current
t
=10 V, 10 =500 mA (unless
mV
Q
mV/oC
IlV
V
B
0.7
1.3
0.003
0.5
mA
mA
Short-circuit output current
25°C
750
mA
Peak output current
25°C
2.2
A
Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured with a 0.33-IlF capacitor across the input and a 0.22-IlF capacitor across the output.
electrical characteristics at specified virtual junction temperature, VI = 19 V, 10 = 500 mA (unless
otherwise noted)
PARAMETER
Output voltage
Input voltage regulation
Ripple rejection
Output voltage regulation
TL7SD-12C
TEST CONDITIONS
10 = 5 mA to 1 A,
TJt
MIN
TYP
MAX
25°C
II.BB
12
12.12
O°C to 125°C
11.76
P";15W,
V, = 14.5 V to 27 V
V, = 14.5 V to 30 V
25°C
V,=16Vt022V
V, = 15 V to 25 V,
1= 120Hz
O°Cto 125°C
'0=5mAto1.5A
25°C
10 = 250 mA to 750 mA
1.2
12
1.2
12
80
V
mV
dB
6.5
60
2.5
36
mV
Output resistance
1 = 1 kHz
O°C to 125°C
0.0035
Temperature coefficient 01 output voltage
O°C to 125°C
0.6
mV/oC
Output noise voltage
'0=5mA
1=10Hztol00kHz
25°C
lBO
Dropout voltage
10=1 A
?5°C
2
IlV
V
25°C
5.5
8
0.4
1.3
0.03
0.5
Input bias current
Input bias current change
t
65
12.24
UNIT
V,=14.5Vt030V
'0=5mAtol A
O°Cto 125°C
Q
mA
mA
Short-circuit output current
25°C
350
mA
Peak output current
25°C
2.2
A
Pulse-testing techniques maintain the Junction temperature as cJose to the ambient temperature as pOSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-IlF capacitor across the input and a O.22-IlF capacitor across the output.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-75
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B-APRIL 1981-REVISEDAUGUST1995
electrical characteristics at specified virtual junction temperature, VI
otherwise noted) ,
PARAMETER
TL780-1SC
TEST CONDITIONS
Output voltage
TJt
MIN
TYP
MAX
25°C
14.85
15
15.15
O°C to 125°C
14.7
PS;15W,
10=5 mA to 1 A,
VI=17.5Vt03OV
VI=17.5Vt03OV
Input voltage regulation
25°C
VI = 20 V to 26 V
VI = 18.5 V to 28.5 V,
Ripple rejection
1= 120 Hz
ObC to 125°C
60
10=5 mA to 1.5 A
Output voltage regulation
10 = 250 mA to 750 mA
Output resistance
l=lkHz
Temperature coefficient of output voltage
10=5mA
Output noise voltage
Dropout voltage
25°C
15
1.5
15
75
V
mV
dB
7
75
2.5
45
mV
'n
0.0035
0.62
mV/oC
f=10Hztol00kHz
25°C
225
10=lA,
25°C
2
IlV
V
25°C
5.5
8
0.4
1.3
0.02
0.5
VI=17.5Vt03OV
Input bias current change
15.3
1.5.
UNIT
O°C to 125°C
Input bias current
t
=23 V, 10 =500 mA (unless
O°Cto 125°C
10=5mAtol A
mA
mA
Short-circuit output current
25°C
230
mA
Peak output current '
25°C
2.2
A
Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured with a 0.33-IlF capacitor across the input and a 0.22-IlF capacitor across the output.
electrical characteristics, VI
=10 V, 10 =500 mA, TJ =25°C (unless otherwise noted)
PARAMETER
Output voltage
Input voltage regulation
Output voltage regulation
TEST CONDITIONSt
10=5mAtol A,
PS;15W,
TL780-DSY
MIN
TYP
5
VI =7Vt025V
0.5
VI=8Vto12V
0.5
10 = 5mA to 1.5 A
4
10 = 250 mA to 750 mA
1.5
Output noise voltage
f=10Hztol00kHz
75
Dropout voltage
10= 1 A
Input bias current
Short-circuit output current
Peak output current
2
MAX
UNIT
V
mV
mV
IlV
V
5
mA
750
mA
2.2
A
t Pulse-testing techmques maintain the juncllOn temperature as close to the ambient temperature as possible, Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-IlF capacitor across the input and a 0.22-IlF capacitor across the output.
'~TEXAS,
INSTRUMENTS
3-76
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B-APRIL 1981-REVISEDAUGUST1995
electrical characteristics, VI
= 19 V, 10 = 500 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
Output voltage
TL780-12Y
MIN
PS15W,
10=5mAtolA,
TVP
12
VI = 14.5 V to 30 V
1.2
VI=16Vt022V
1.2
10 =5mA to 1.5A
6.5
10 = 250 mA to 750 mA
2.5
Output noise voltage
f=10Hztol00kHz
160
Dropout voltage
10=1 A
Input voltage regulation
Output voltage regulation
MAX
V
mV
mV
J.lV
V
2
Input bias current
Short·circuit output current
Peak output current
UNIT
5.5
rnA
350
mA
2.2
A
t Pulse-testing techniques the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into account
separately. All characteristics are measured with a 0.33-J.lF capacitor across the input and a 0.22-J.lF capacitor across the output.
electrical characteristics, VI
= 23 V, 10 = 500 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
Output voltage
PS15W,
10=5 mA to 1 A,
Input voltage regulation
TL780-15Y
MIN
15
VI=17.5Vt03OV
1.5
VI = 20 V to 26 V
1.5
10= 5 mA to 1.5A
Output voltage regulation
TVP
7
2.5
10 = 250 mA to 750 mA
Output resistance
f= 1 kHz
Output noise voltage
f=10Hztol00kHz
Dropout voltage
10=1 A
0.0035
225
2
MAX
UNIT
V
mV
mV
g
J.lV
V
Input bias current
5.5
mA
Short-circuit output current
230
mA
Peak output current
2.2
A
t Pulse-testing techniques the Junction temperature as close to the ambient temperature as pOSSible. Thermal effects must be taken Into account
separately. All characteristics are measured with a 0.33-J.lF capacitor across the input and a 0.22-J.lF capacitor across the output.
PARAMETER MEASUREMENT INFORMATION
INPUT--....- 1
TL780
0 1 - -....- - OUTPUT
(see Note C)
C1 =0.33 J.lF
(see Note A)
T
T
C2 = 0.22 J.lF
(see Note B)
NOTES: A. Cl is required when the regulator is far from the power supply filter.
B. C2 is not required for stability; however, transient response is improved.
C. Permanent damage can occur when output is pulled below ground.
Figure 3. Test Circuit
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-77
TL780 SERIES
POSITIVE VOLTAGE REGULATORS
SLVS055B-APRIL 1981-REVISEDAUGUST1995
,APPLICATION INFORMATION
....---1
INPUT -
+ _---'I=n-1
R1
'----~----4t__
OUTPUT
-+
10
10 =. (VoJR1) + 10 Bias Current
Figure 4. Positive Regulator In Negative
Configuration (VI Must Float)
Figure 5. Current Regulator
operation with a load common to a voltage of opposite polarity
In many cases, a regulator powers a load that is not connected to ground but instead is connected to a voltage
source of opposite polarity (e.g., operational amplifiers, level-shifting circuits, etc.). In these cases, a clamp
diode should be connected to the regulator output as shown in Figure 6. This protects the regulator from output
polarity reversals during startup and short-circuit operation.
-VO
Figure 6. Output Polarity Reversal Protection Circuit
reverse-bias protection
Occasionally, the input voltage to the regulator can collapse faster than the output voltage. This, for example,
could occur when the input supply is crowbarred during an output overvoltage condition. If the output voltage
is greater than approximately 7 V, the emitter-base junction of the series pass element (internal or external)
could break down and be damaged. To prevent this, a diode shunt can be employed, as shown in Figure 7.
Figure 7. Reverse-Bias Protection Circuit
"'TEXAS
3-78
INSTRUMENTS
POST OFFICE BOX 655303- DALLAS, TEXAS 75265
TL783C, TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
• Output Adjustable From 1.25 V to 125 V
When Used With an External Resistor
Divider
KCPACKAGE
{TOP VIEW)
• 70Q-mA Output Current
• Full Short-Circuit, Safe-Operating-Area, and
Thermal Shutdown Protection
@I
()
~ INPUT
.....a.._--,
OUTPUT
ADJUSTMENT
The output terminal is in electrical
contact with the mounting base.
• 0.001 %/v Typical Input Voltage Regulation
• 0.15% Typical Output Voltage Regulation
TO-220AB
• 76-dB Typical Ripple Rejection
• Standard TO-220AB Package
description
The TL783C is an adjustable 3-terminal high-voltage regulator with an output range of 1.25 V to
125 V and a DMOS output transistor capable of
sourcing more than 700 mA. It is designed for use
in high-voltage applications where standard
bipolar regulators cannot be used. Excellent performance specifications, superior to those of most bipolar
regulators, are achieved through circuit design and advanced layout techniques.
As a state-of-the-art regulator, the TL783C combines standard bipolar circuitry with high-voltage
double-diffused MOS transistors on one chip to yield a device capable of withstanding voltages far higher than
standard bipolar integrated circuits. Because of its lack of secondary breakdown and thermal runaway
characteristics usually associated with bipolar outputs, the TL783C maintains full overload protection while
operating at up to 125 V from input to output. Other features of the device include current limiting,
safe-ope rating-area (SOA) protection, and thermal shutdown. Even if the adjustment terminal is inadvertently
disconnected, the protection circuitry remains functional.
Only two external resistors are required to program the output voltage. An input bypass capaCitor is necessary
only when the regulator is situated far from the input filter. An output capaCitor, although not required, improves
transient response and protection from instantaneous output short circuits. Excellent ripple rejection can be
achieved without a bypass capaCitor at the adjustment terminal.
AVAILABLE OPTIONS
PACKAGED DEVICE
TJ
O°C to 125°C
PRODUCTION DATA Infonnation Is current II of publication dale.
Products conform to specifications per: the terms of Texas Instruments
slsntisrd WlITIJI!y. Production procooslng doaa not _ I y Include
testing of all parameters.
HEAT-SINK MOUNTED
(3-PIN)
(KC)
TL783CKC
CHIP
FORM
(Y)
TL783Y
I~TEXAS
NSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
3-79
· TL783C, TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
TL783Y chip information
This chip, when properly assembled, dil?plays characteristics similar to the TL783C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
INPUT
9
1)
(2)
OUTPUT
TL783Y
(3)
ADJUSTMENT
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
~TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
fun.ctional block diagram
~r-----------------+-----------~---r------1r-----'~--VO
OUTPUT
R1
Vref
ADJUSTMENT
R2
absolute maximum ratings over operating temperature range (unless otherwise noted)t
Input-to-output differential voltage, V,- Vo ............ ,. . .... .... . . ......... . . ... . . . . ... ... 125 V
Continuous total power dissipation at (or below) TA 25°C (see Note 1) .......................... 2 W
Continuous total power dissipation at (or below) T C = 70°C (see Note 1) ......................... 20 W
Operating free-air, TA, case, T C, or virtual junction, T J, temperature range ................. O°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
=
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: For operation above TA = 2SoC or TC = 70°C, refer to Figures 1 and 2, respectively. To avoid exceeding the design maximum virtual
junction temperature, these ratings should not be exceeded. Due to variations in individual device electrical characteristics and thermal
reSistance, the built-in thermal overload protection may be activated at power levels slightly above or below the rated dissipation
CASE TEMPERATURE
DISSIPATION DERATING CURVE
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
~I
i
'0;
is...
~
2000
1800
1600
1400
D~rating F~ctor =16iw,oC
1000
0
800
~0
600
.
'j(
::iii
~
r'\.
'\
is
16
'~
75
~
0
::I
C
r'\.
~
100
0
8
\
(J
E
::I
E
"-
125
TA - Free-Air Temperature - °C
Figure 1
\
12
::I
"-
50
20
I..
200
25
i
11.
400
o
I
'0;
(J
E
::I
E
~
c
~
::I
::I
24
_
RaJA ~ 62.5°CJW
1200
.
0
11.
.l"\.
.'\
.
'j(
"
Derating Factor
4 -- Above 70°C
\..
RaJC~4°CJW
::iii
150
=250 mill r'C
o
25
'I
50
75
100
125
\
150
TC - Case Temperature - °C
Figure 2
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-81
TL783C, TL783Y
.
.
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST1995
recommended operating conditions
-
MIN
Input-to-output voltage differential, VI - Vo
Output current, 10
Operating virtual junction temperature, TJ
MAX
UNIT
125
V
15
700
mA
0
125
°C
electrical characteristics at V,- Vo = 25 V, 10 = 0.5 A, TJ = ooe to 125°C (unless otherwise noted)
PARAMETER
TL783C
TEST CONDITIONSt
MIN
0.001
0.01
TJ = O°C to 125°C
0.004
0.02
VI-VO=20Vto 125 V,
P " rated dissipation
Ripple rejection
.lVIfPPt = 10 V,
VO= 10V,
f= 120 Hz
TJ = 25°C
VO" 5V
VO;" 5V
P " rated dissipation
VO" 5V
VO;" 5V
10 = 15 mA to 700 mA,
10= 15mAto 700 mA,·
66
Output voltage change with
temperature
76
UNIT
%IV
dB
7.5
25
0.15%
0.5%
20
70
0.3%
1.5%
mV
mV
0.4%
Output voltage long-term drift
1000 hours'atTJ = 125°C, VI- Vo = 125 V,
Output noise voltage
f = 10 Hz to 10 kHz,
Minimum output current to
maintain regulation
VI- VO=125V
Peak output current
MAX
TJ = 25°C
Input voltage regulation:!:
Output voltage regulation
TVP
See Note 2
0.2%
0.003%
TJ = 25°C
15
VI-VO =25 V,
t=l ms
VI- VO=15V,
t=30ms
VI-VO=25 V,
t=30ms
700
900
VI- VO=125V,
t",30ms
100
250
1100
715
Adjustment-terminal current
Change in adjustmentterminal current
VI- VO=15Vto125V,
10 = 15 mA to 700 mA, p" rated dissipation
Reference voltage
(OUTPUT to ADJUSTMENT)
VI-VO = 10Vto 125 V,
See Note 3
10= 15 mAt0700 mA, p" rated dissipation,
mA
1.2
mA
83
110
~
0.5
5
~
1.27
1.3
V
t Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature· as pOSSible. Thermal effects must be taken Into
account separately.
:!: Input voltage regulation is expressed here as the percentage change in output voltage per 1-V change at the input.
NOTES: 2. Since long-term drift cannot be measured on the individual devices prior to shipment, this specification is not intended to be a
guarantee or warranty. It is an engineering estimate of the average drift to be expected from lot to lot.
3, Due to the dropout voltage and output current-limiting characteristics of this device, output current is limited to less than 700 mA
.
at input-to-output voltage differentials of less than 25 V.
~TEXAS
INSTRUMENTS
3--82
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
electrical characteristics at V,- Vo
=25 V, 10 =0.5 A, TJ =25°C (unless otherwise noted)
PARAMETER
Input voltage regulationt
VI-VO=20Vto 125 V,
P S rated dissipation
Ripple rejection
.1VIlPPl = 10 V,
VO= 10V,
10= 15 mAt0700 mA
Output voltage regulation
10 = 15 mA to 700 mA,
Output voltage change
temperature
TL783Y
TEST CONDITIONSt
o
P S rated dissipation
MIN
0.001
Peak output current
MAX
UNIT
%N
f= 120 Hz
76
dB
Vos 5V
7.5
mV
Vo? 5V
0..15%
VOs 5V
20
VO? 5V
0.3%
w~h
Output noise voltage
TYP
mV
0.4%
f=10Hztol0kHz
0.003%
VI- VO=25V,
t=l ms
1100
VI- VO=15V,
t=30ms
715
VI-VO =25 V,
t=30ms
900
VI- VO=125V,
t=30ms
250
Adjustment-terminal current
Change in adjustmenttenninal current
VI- VO=15Vto125V,
10;' 15mAt0700 mA, P S rated dissipation
Reference voltage
(OUTPUT to ADJUSTMENT)
VI- VO=10Vto125V,
See Note 3
10= 15 mAto 700 mA, P S rated dissipation,
mA
83
IlA
0.5
IlA
1.27
V
t
Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as poSSible. Thennal effects must be taken Into
account separately.
t Input voltage regulation is expressed here as the percentage change in output voltage per I-V change at the input.
NOTES: 2 Since long-term drift cannot be measured on the individual devices prior to shipment, this specification is not intended to be a
.
guarantee or warranty. It is an engineering estimate of the average drift to be expected from lot to lot.
3 Due to the dropout voltage and output current-limiting characteristics of this device, output current is limited to less than 700 mA
at input-to-output voltage differentials of less than 25 V.
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3-83
TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OUTPUT CURRENT LIMIT
OUTPUT CURRENT LIMIT
VB
VB
INPUT-TO-QUTPUT VOLTAGE DIFFERENTIAL
INPUT-TO-OUTPUT VOLTAGE DIFFERENTIAL
2~--~-----T-----r----~--~
2~--~-----T-----r--~~--~
1.8
1.6
1.8
~
1.4 I---M~~-+---+---t-----l
i:J
1.2 I--H-/----""<:"k:---.--+---t-----l
c(
~
0.8
O
0.6.
0.4
I
1.41---I:-----+---+---t----I
:J
1.2 t---f'I~--+----t----+--___l
:=
E
TC= O°C
c3_
t
1.61---Ic-----+---+---t----I
I-----tl~--+---+---t-----l
~
1---+--+---,......,.--"""'''''''"'--\----1
c3"S
0.81----.yp.,.-~~--+-
O~
0.61-1--j.---"'tt-~""'k:_+-+-----l
H1'----r---t-r-r---"""........I;;;::::::::::j
0.41--11~-+-_+-+-::>"""'+...::!oo"'""'~-.......d
0.2 H--j.---!f-----+---+----I
0.2
H--~r-----+----t----+==--.........!
o~--~----~----~----~--~
o
25
50
75
100
125
50
25
VI- Vo -Input-to-Output Voltage Dlfferentlal- V
Figure 3
c(
VB
TIME
OUTPUT VOLTAGE
"S
!
120
-
1
ID
"1:1
I
80
0.8
ia:
60
0.6
ta.
1\
'\
c
'Ii'
~
1
1 .1
VI(AV) - Vo = 25 V
~VI(PP) = 10 V
lo=100mA
f= 120 Hz
CO=o
TJ=25°C
100
~
j
j
1
VI-VO= 25V
TC=25°C
"-
1.2
I
125
RIPPLE REJECTION
VB
1.6
:=
100
Figure 4
OUTPUT CURRENT LIMIT
1.4
75
VI- Vo -Input-to-Output Voltage Differentlal- V
"-
~
-
40
0.4
20
0.2
o
o
10
20
30
40
o
o
10
TIme-ms
20
30
40
50
60
70
Vo - Output Voltage - V
Figure 5
Figure 6
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DAI.\.AS, TEXAS 75265
80
90 100
TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
RIPPLE REJECTION
RIPPLE ReJECTION
va
va
OUTPUT CURRENT
FREQUENCY
100
100
90
80
m
"a
I
c
80
-r--.....
-V
m
"a
c
60
'fi...
'fi...
50
a:
a:
0
60
0
'iii
ia.
a:
"iii
...
40
100
"
30
20
10
o
300
200
400
500
700
600
800
0.01
0.1
10
va
FREQUENCY
VIRTUAL JUNCTION TEMPERATURE
1.30
VI = 3dv
VO=10V
10 =500 mA
TJ = 25°C
/
...I
g
....
"a
/
"$
i
0
10-2
J
f"......./
1000
REFERENCE VOLTAGE
va
102
oS
100
Figure 8
OUTPUT IMPEDANCE
a. 10-1
"
""
I'\.
f - Frequency - kHz
Figure 7
a
~
VI(AV)=25 V
,WI(PP) = 10 V
VO= 10V
10 = 500 mA
TJ=25°C
10 - Output Current - mA
101
.rIl.
CO~O
a.
a:
CO=1~IlF
'\.
40
i5.
VI(AV)=25 V
,WI(PP) = 10 V
VO=10V
20
f = 120 Hz
CO=O
TJ = 25°C
o
o
.........
70
I
V
/'
1.29
>
I
1.28
~
....
1.27
J
'/
I
'/
I
i!
I
.,!i
>
VI=20V
10= 15 mA
-
I---
i"-
1.26
1.25
1.24
10-3
1.23
1.22
102
103
104
105
106
-75 -50 -25
f - Frequency - kHz
0
25
50
75 100 125 150 175
TJ - Virtual Junction Temperature - °C
Figure 9
Figure 10
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3-85
TL783C, TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B-SEPTEMBER 1981-REVISEDAUGUST1995
TYPICAL CHARACTERISTICS
ADJUSTMENT-TERMINAL CURRENT
vs
VIRTUAL JUNCTION TEMPERATURE
VIRTUAL JUNCTION TEMPERATURE
90
VI=25V
vO=Vret
10=5OOmA
88
cc::l.
I
C
~
86
'"
(.)
c
~
84
'&i
~'"
I
'6' 82
~
80
I
o
DROPOUT VOLTAGE
vs
/
/
/
V
V
/
AVO = 100 mV
V
/'
20b-~---+---r--~--+---r-~--~
10 =700 mA
10 = 600 mA
10 = 500 mA ..;-=+---!f----+---+---I
10 = 250 mA
10 = 100 mA
10=15mA
i=~=:j:=~=e::J
o~~--~--~--~~--~--~~
25
50
75
100
-75 -50
125
-25
0
OUTPUT VOLTAGE DEVIATION
75
100
125
OUTPUT CURRENTt
vs
vs
VIRTUAL JUNCTION TEMPERATURE
VI=2~V
50
Figure 12
Figure 11
0
25
TJ - Virtual Junction Temperature - °C
TJ - Virtual Junction Temperature - °C
INPUT VOLTAGE
12r-----r----,r----,r----,-----,
I
VO=5V
10 = 15 mA to 700 mA
~
I
-0.1
c
IJ.
~
r--. ...............
-0.2
..........
" ""
-0.3
'S
So
'"
0
I
-0.4
0
4r-----r-----r---~r---~r---_;
2b---~f----~----~----~----~
>
I
0.4
rCo=O
4
C
0
2
~
-2
I
c
tI!
>
i
0.2
0
~ -4
~ -0.2
'C"
I
>
I
CD
Dl
C
as
.c
U
">
0
0:11
0
2
Time-Ils
4
3
I
-6
0.8
~
::I 0.6
VI =35V
vo= 10V
CO=lIlF
TJ = 25°C
u
:; 0.4
~
0
I
.9
0.2
0
0
40
80
120
160
200
240
T1me-lls
Figure 15
Figure 16
DESIGN CONSIDERATIONS
The internal reference (see functional block diagram) generates 1.25 V nominal (Vref) between the output and
adjustment terminals. This voltage is developed across R1 and causes a constant current to flow through R1
and the programming resistor R2, giving an output voltage of:
Va = Vred1 + R2IR1) + ladj (R2)
or
Va - Vred1 + R2IR1).
The TL783C was designed to minimize ladj and maintain consistency over line and load variations, thereby
minimizing the ladj (R2) error term.
To maintain ladj at a low level, all quiescent operating current is returned to the output terminal. This quiescent
current must be sunk by the external load and is the minimum load current necessary to prevent the output from
rising. The recommended R1 value of 82 Q provides a minimum load current of 15 mAo Larger values can be
used when the input-to-output differential voltage is less than 125 V (see output current curve) or when the load
sinks some portion of the minimum current.
bypass capacitors
The TL783C regulator is stable without bypass capacitors; however, any regulator becomes unstable with
certain values of output capacitance if an input capacitor is not used. Therefore, the use of input bypassing is
recommended whenever the regulator is located more than four inches from the power-supply filter capacitor.
A 1-!1F tantalum or aluminum electrolytic capacitor is usually sufficient.
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TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995,
DESIGN CONSIDERATIONS
bypass capacitors (continued)
Adjustment-terminal capacitors are not recommended for use on the TL783C because they can seriously
degrade load transient response as well as create a need for extra protection circuitry. Excellent ripple rejection
is presently achieved without this added capacitor.
Due to the relatively low gain ,of the MOS output stage, output voltage dropout may occur under large load
transient conditions. The addition of an output bypass capacitor greatly enhances load transient response as
well as prevent dropout. For most applications, it is recommended that an output bypass capacitor be used with
a minimum value of:
Co (IlF)
= 15NO
Larger values provide proportionally better transient response characteristics.
protection circuitry
The TL783C regulator includes built-in protection circuits capable of guarding the device against most overload
conditions encountered in normal operation. These protective features are current limiting, safe-operating-area
protection, and thermal shutdown. These circuits are meant to protect the device under occasional fault
conditions only. Continuous operation in the,current limit or thermal shutdown mode is not-recommended.
The internal protection circuits of the TL783C protect the device up to maximum-rated VI as long as certain
precautions are taken. If VI is instantaneously switched on, transients exceeding maximum input ratings may
occur, which can destroy the regulator. These are usually caused by lead inductance and bypass capacitors
causing a ringing voltage on the input. In addition, when rise times in excess of 10 VIns are applied to the input,
a parasitic npn transistor in parallel with the DMOS output can be turned on causing the device to fail. If the
device is operated over 50 V and the input is switched on rather than ramped on, a low-Q capacitor, such as
tantalum or aluminum electrolytic should be used rather than ceramic, paper, or plastic bypass capacitors. A
Q factor of 0.015 or greater usually provides adequate damping to suppress ringing. Normally, no problems
occur if the input voltage is allowed to ramp upward through the action of anac line rectifier and filter network.
Similarly, when an instantaneous short circuit is applied to the outputs, both ringing and excessive fall times can
result. A tantalum or aluminum electrolytic bypass capacitor is recommended to eliminate this problem.
However, if a large output capacitor is used and the input is shorted, addition of a protection diode may be
necessary to prevent capacitor discharge through the regulator. The amount of discharge current delivered is
dependent on output voltage, size of capacitor, and fall time of VI. A protective diode (see Figure 17) is required
only for capacitance values greater than:
Co (IlF) = 3 x 104/(VO)2.
Care should always be taken to prevent insertion of regulators into a socket with power on. Power should be
turned off before removing or inserting regulators.
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TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATpRS
SLVS036B-SEPTEMBER 1981-REVISEDAUGUST1995
DESIGN CONSIDERATIONS
protection circuitry (continued)
TL783C
VI ----tl---IINPUT
OUTPUT
~-e-+--
___-
Vo
ADJUSTMENT
R1
Figure 17. Regulator With Protective Diode
load regulation
The current set resistor (R1) should be located close to the regulator output terminal rather than near the load.
This eliminates long line drops from being amplified through the action of R1 and R2 to degrade load regulation.
To provide remote ground sensing, R2 should be near the load ground.
INPUT
TL783C
OUTPUT
RUne
Vo
[C
ADJUSTMENT
R1
I
R2
-
Figure 18. Regulator With Current-Set Resistor
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-89
TL783C, TL783Y
HI~H-VOLTAGE ADJUSTABLE
REGULATORS
SLVS0368 - SEPTEMBER 1981 - REVISED AUGUST 1995
APPLICATION INFORMATION
_ VI
=145 to 200 V
r
TIP150
TL783C
OUTPUT
---< t-- INPUT
ADJUSTMENT
7.5 k!l, 1 W
L
R1
820
120V,1.5W
INPUT
+
;::::: 10l1F
+
;:::::
/.
I
I
I
I
OUTPUT 1--..........._ - 125 V
ADJUSTMENT
~R2
TL783C
Ot08kn
R1
820
R2
8.2 k!l, 2W
t
Needed if device Is more than 4 inches from fi~er capacitor
,Figure 19. 1.25-V to 115-V Adjustable Regulator
Figure 20. 125-V Short-Circult-Protected
Off-Line Regulator
125V
VI
10
=70 to 125 V
100
100
1 kn
TlPL762
1 kn
TL783C
TL783C
IN~UT
OUTPUT
l--~t-4If---.
INPUT
VO=50V
at 0.5 A
ADJUSTMENT
OUTPUT
1--_-..._-....
ADJUSTMENT
820
3.3 kn, 1W
R2
Figure 21. 50-V ,Regulator With Current Boost
,
Figure 22. Adjustable Regulator With Current
Boost and Current Limit
~TEXAS
INSTRUMENTS
3-90
POST OFFICE SOX 655303 • ,PALLAS, TEXAS 75265
TL783C,TL783Y
HIGH-VOLTAGE ADJUSTABLE REGULATORS
SLVS036B - SEPTEMBER 1981 - REVISED AUGUST 1995
APPLICATION INFORMATION
VI
I
I
TL783C
~
r=t
I
Load
111FT
v ref
1=-
INPUT
-=
R
OUTPUT f - - ADJUSTMENT
R
INPUT
OUTPUT
I
ADJUSTMENT
~
=
V~efi
._------'
R
C¥J
Figure 23. Current-Sinking Regulator
Figure 24. Current-Sourcing Regulator
VCC
TL783CI
INPUT
TL783C
OUTPUT -
INPUT
OUTPUT t----e-- 'U
ADJUSTMENT
OUTPUT
820
ADJUSTMENT
6.250
TL783C
INPUT
OUTPUT
R2
ADJUSTMENT
820
'U
3.9kQ
INPUT
-
V-
Figure 25. High-Voltage Unity-Gain Offset Amplifier
J
I
.48V
Figure 26. 48-V, 200-mA Float Charger
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-91
3-92
.
TL1431C,TL1431Q, TL1431V
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
•
•
•
•
•
•
•
08
o PACKAGE
0.4% Initial Voltage Tolerance
0.1-0 Typical Output Impedance
Fast Turn On ••• 500 ns
Sink Current Capability ••• 1 mA to 100 mA
Low REF Current
Adjustable Output Voltage ..• Vref to 36 V
Available In Two High-Density Packaging
Options:
- Small Outline (D)
- TO-226AA (LP)
(TOP VIEW)
CATHODE
ANODE
ANODE
NC
2
3
4
7
6
5
REF
ANODE
ANODE
NC
NC - No internal connection
ANODE terminals are internally connected.
LPPACKAGE
(TOP VIEW)
description
The TL 1431 is a precision programmable reference
with specified thermal stability over applicable
automotive and commercial temperature ranges.
The output voltage may be set to any value between
VI(ref) (approximately 2.5 V) and 36 V with two
external resistors (see Figure 16). These devices
have a typical output impedance of 0.1 O. Active
output circuitry provides a very sharp turn-on
characteristic, making these devices excellent
replacements for zener diodes and other types of
references in applications such as on-board
regulation, adjustable power supplies, and
switching power supplies.
CATHODE
ANODE
REF
application schematic
5-V Precision Regulator
V+
VO=5V
27.4 k.Q
0.1%
The TL1431 is offered in a wide variety of
high-density packaging options. It is also available
in both the automotive temperature range and the
commercial temperature range. The TL 1431 C is
characterized for operation over the commercial
temperature range of O°C to 70°C. The TL 1431 Q is
characterized for operation over the automotive
temperature range of -40°C to 125°C.
27.4 k.Q
0.1%
NOTE A: Rb should provide cathode current
TL1431.
~
l-mA to the
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
Ta-226AA
(LP)
O°C to 70°C
TL1431CD
TL1431CLP
-40°C to 125°C
TLl4310D
TL14310LP
CHIP FORM
(V)
TL1431Y
The D and LP packages are available taped and reeled. Add R suffix to device
type (e.g., TL 1431 CDR). Chip lonns are tested at 25°C.
=~:o::s==:s~~en:::=~~~~
standard warranty. ProducHon processing dOe8 not.necessarlly Include
testing of all parameters.
-!11
Copyright © 1995, Texas Instruments IncOrporated
TEXAS'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-93
TL1431C, TL1431Q, TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
symbol
functional block diagram
CATHODE
REF
ANODE
---1~""L--
CATHODE
ANODE
TL1431Y chip information
This chip, when properly assembled, displays characteristics similar to the TL 1431. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chi,", may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
REF
fJ:
3
)
ANODE ...,.<2..:-)_ _......
'L_<_1) CATHODE
11
.:.:: 46
)j~~
14
66
.,
111111111111111111111111111111111111111111111111111111II
~1EXAS
3-94
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±100/0.
ALL DIMENSIONS ARE IN MILS.
TL1431C,TL1431Q,TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
equivalent schematic
CATHODE~1~~.-----------------~~-------.---.----~~--------.---,
8000
20pF
3.28kQ
4kQ
10kQ
2.4kQ
7.2kQ
1 kQ
8000
ANODE~2~3~.6~7~~
____~__________~________~~________________~~~
NOTE A: All component values are nominal.
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS. TEXAS 75265
3-95
TL1431C, TL1431Q, TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
cathode voltage,VKA (see Note 1) ........................................................... 37 V
Contiriuous cathode current range, IKA ......................................... -100 rnA to 150 rnA
Reference input current range, II(REF) ............................................ -50 J.IA to 10 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix ...................................... O°C to 70°C
Q suffix .................................. -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other condnions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to ANODE unless otherwise noted.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=105°C
POWER RATING
TA= 125°C
POWER RATING
PACKAGE
TA:O;25°C
POWER RATING
D
725mW
5.8mW/oC
464mW
261 mW
145mW
LP
n5mW
6.2 mW/oC
496mW
279mW
155mW
recommended operating conditions
cathode voltage, VKA
--
CSUFFIX
QSUFFIX
MIN
MAX
MIN
MAX
UNIT
VI(ref)
36
VI(ref)
36
V
cathode current, I KA
1
100
1
100
mA
Operating free-air temperature, TA
0
70
-40
125
°C
~TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL1431C, TL1431Q,TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, IKA = 10 mA (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TAt
TL1431C
TEST
CIRCUIT
25°C
VI(ref)
Reference input voltage
~
VKA= VI(ref)
1
TYP
MAX
MIN
TYP
MAX
2490
2500
2510
2490
2500
2510
2520
2470
2480
range
TL1431Q
MIN
UNIT
mV
2530
VI(dev)
Deviation of reference
input voltage over full
temperature range:!:
VKA = VI (ref)
Full
range
1
4
20
17
55
mV
.1Vllref)
.1VKA
Ratio of change in
reference input voltage
to the change in
cathode voltage
.1VKA=3Vt036V
Full
range
2
-1.1
-2
-1.1
-2
mVN
1.5
2.5
1.5
2.5
II(ref)
Reference input current
Rl = 10 Idl,
25°C
R2==
~
2
3
range
II(dev)
loff
IZKAI
Deviation of reference
input current over full
temperature range:!:
Rl = 10 kn,
Minimum cathode
current for regulation
VKA = VI (ref) to 36 V
Off-state cathode
current
VKA=36V,
Output impedance§
VKA = VI(ref), f " 1 kHz,
IKA=l mAtol00mA
R2==
I1A
Full
range
2
0.2
1.2
0.5
1.2
I1A
25°C
1
0.45
1
0.45
1
rnA
0.18
0.5
0.18
0.5
25°C
VI(ref)=0
3
~
3
2
range
25°C
1
0.1
0.2
2
. 0.1
I1A
0.2
n
t Full range is O°C to 70°C for C-suffix devices and -40°C to 125°C for Q-suffix devices.
:!:The deviation parameters VI(dev) and II(dev) are defined as the differences between the maximum and minimum values obtained over the rated
temperature range. The average full-range temperature coefficient of the reference input voltage IXVf(ref) is defined as:
(
VI(r::)(:~~50C
I
)
x
MaXVI(retr
106
------~-----~----t~
.1TA
I VI(dev)
where .1TA is the rated operating temperature range of the device. Min VI(ref) -
______________ ~-l
I
1
4 ---14
IXVref is positive or negative depending on whether minimum VI(ref) or maximum VI(ref), respectively, occurs at the lower temperature .
.1V
§ The output impedance is defined as: IZKAI = .11 KA.
KA
When the device is operating with two external resistors (see Figure 2), the total dynamic impedance of the circuit is given by:
Iz'l =
~y, which is approximately equalt0lzKAI
(1 + ~~).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-97
TL1431C,TL1431Q, TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at IKA = 10 rnA, TA
=25°C
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
2490
2500
2510
-1.1
-2
2
1.44
2.5
jU\
1
- 3
0.45
1
mA
0.18
0.5
jU\
1
0.1
0.2
Q
VI(ref)
Reference input voltage
VKA = VI (ref)
1
<1Vllref)
<1VKA
Ratio of change in reference input voltage to the
change in cathode voltage
<1VKA=3Vt036V
2
II(rel)
Reference input current
R1 =10kn,
IKAmin
Minimum cathode current for regulation
VKA = VI(rel) to 36 V
loff
Off-state cathode current
VKA=36V,
Output impedancet·
VKA = VI(ref), f ,,; 1 kHz,
IKA=1mAt0100mA
IZKAI
t The output impedance is defined as: Iz'l =
R2 = 00
Vref=O
TL1431Y
TEST
CIRCUIT
UNIT
mV
mVN
~y
When the device is operating with two external resistors (see Figure 2), the total dynamic impedance of the circuit is given by
IZKAI =
:~:
,which is approximately equal to IZKAI (1
+
~) .
PARAMETER MEASUREMENT INFORMATION
Input -~Wlr--~"""--- VKA
Input - W l r - - . I - - - - - VKA
R1
R2
V KA = VI(ref) (1
Figure 1. Test Circuit for V(KA)
=Vref
=~) + 11(ref) x R1
Figure 2. Test Circuit for V(KA) > Vref
Input -WIr---.I-----VKA
Figure 3. Test Circuit for loff
~TEXAS
INSTRUMENTS
3-98
+
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL1431C,TL1431Q,TL1431V
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VI(re!)
Reference voltage
vs Free-air temperature
4
Illretl
Reference current
vs Free-air temperature
5
6,7
IKA
Cathode current
vs Cathode voltage
IKAloff}
Off-state cathode current
vs Free-air temperature
aVllref)
Ratio of delta reference voltage to delta cathode voltage
vs Free-air temperature
9
vs Frequency
10
8
Vn
Equivalent input noise voltage
Over a 10-second time period
11
AV
Small-signal voltage amplification
vs Frequency
12
Reference impedance
vs Frequency
13
IZKAI
Pulse response
14
Stability boundary conditions
15
~TEXAS
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3-99
TL1431C, TL1431Q, TL1431Y
PRECISION .PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
2.52
I
REFERENCE· CURRENT
vs
FREE-AIR TEMPERATURE
2.5
I
IKA=10mA
R1 = 10kO
R2 =00
VI(ret) = VKA
IKA=10mA
<:I.
>
2.51
I
t
-
~
I
.;
.-
2.5
a:
I
i
:='
>
2
I
~
..............
~
2.49
2.48
-50
-25
0
25
.........
u::I
8c
50
1.5
--
- -
............
!
~
75
~
I
i
"\
100
: : 0.5
o
125
-50
-25
TA - Free-Air Temperature - °C
50
75
100
0
25
TA - Free-Air Temperature - °C
CATHODE CURRENT
vs
CATHODE VOLTAGE
CATHODE CURRENT
vs
CATHODE VOLTAGE
150
800
VKA=V~raf)
TA=25°
VKA=V~ref)
TA = 25°
100
<
600
<:I.
E
I
I
50
~
::I
..
125
Figure 5
Figure 4
1:
~
-
400
..
::I
U
U
0
:g
(
.t:.
~
-50
I
'8
.t:.
200
u1ii
~
0
-100
-150
-3
/v
I
~
-2
-1
o
VKA - cathode Voltage - V
•
-200
2
J
3
-2
o
-1
2
3
VKA - Cathode Voltage - V
Figure 6
Figure 7
~
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
-!!1TEXAS
INSTRUMENTS
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POST OFfICE BOX 655303 • DALLAS. TEXAS 75265
4
TL1431C,TL1431Q,TL1431V
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
RATIO OF DELTA REFERENCE VOLTAGE TO
DELTA CATHODE VOLTAGE
vs
FREE-AIR TEMPERATURE
OFF-STATE CATHODE CURRENT
vs
FREE-AIR TEMPERATURE
0.4
"'--"'T'"""-"T""--r-....,...-....,..--.,.---,
::l.
-0.85
VKA = 3 V to 36 V
VKA=36V
VI(ret) 0
c(
=
0.35
-0.95
I
~
8
0.3
-1.05
-8
0.25
~
0.2
r-=1==t~~:P:::r=j1
0.15
1--+---+--+--+--+---+---1
I
I
£
~
"'"
1--+---+--+--+--+---+---1
0.1
0.05
I
I--+---+---+--t---+--t---t
:!
~
~
>
0
25
50
75
100
~
-1.25
""f'..
~
-1.35
OL-_~~~-~-_=-~-~~~
-25
"'" "
~
I
4
GO
Q
3
~
2
!
0
'5
CI.
oS
-1
C
-2
.!!
u
•
II I~
'v
'
IUllaalV"
A
111\
=:
I
ill
'\0.
l
IV
"W"·
"
I
~:::I -3
,ff -4
II
l'
'll
I
I
hO.1to 10 Hz
IKA=10mA
TA = 25°C
I
>c
•
~
-5
-6
o
2
4
6
t-Tlme-s
8
10
19.1 V .
VCC
VCC
SOOIlF
8200
160
-::-
0.11lF
VEE
VEE
TEST CIRCUIT FOR 0.1-Hz TO 1Q-Hz EQUIVALENT INPUT NOISE VOLTAGE
Figure 11
~TEXAS
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL1431C,TL1431Q,TL1431V
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
SMALL-SIGNAL VOLTAGE AMPLIFICATION
vs
FREQUENCY
60
"I~=10mA
III
'0
I
C
i
TA = 25°C
50
u
E
"
\
!E
i5.
r - - - - -____-:---~>--- Output
40
CC
230n
Gl
Dl
:ll!
30
~
c
~fti
20
Ul
I
10
+
\
fti
\
L---~------~
__--~-GND
E
~
TEST CIRCUIT FOR VOLTAGE AMPLIFICATION
t\.
o
1k
10 k
100 k
1M
10M
f - Frequency - Hz
Figure 12
REFERENCE IMPEDANCE
vs
FREQUENCY
100
IKA = 1 mA to 100mA
TA = 25°C
a
I
8c
01
I.5
1 kQ
Output
10
I(K)
8c
son
I!!
+
~
a:
I
~
~--~--------__--~------
!!
GND
I
0,1
1k
TEST CIRCUIT FOR REFERENCE IMPEDANCE
10k
100k
1M
1M
f - Frequency - Hz
Figure 13
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TL1431C,TL1431Q, TL1431Y
PRECISION· PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 19!11 J REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
PULSE RESPONSE
6
I
TA = 25°C
VI
Input
>
220(.1
=---.J\III\r---+-.__-- Output
r - - -.....
5
I
:Ien
4
~
Pl.!lse
Generator
1= 100 kHz
~
'S
Q.
'S
·3
Output
0
~
•
/
2
III
50 (.I
.....-----GND
'SQ,
L---~--------.__--
.5
TEST CIRCUIT FOR PULSE RESPONSE
o
o
2
4
3
t-Time - /1S
6
5
7
Figure 14
150(.1
STABILITY BOUNDARY CONDITIONSt
100~TT~~~~~~~~~'-lnlrrrn
A VKA = VI(ref)
I~I~ ~~ ~~
90 B VKA = 5 V C ffH-IH+-+-H+f++lI TA = 250C
VKA=10VD
1111'"
80 VKA=15V
III
70
+
VBATT
1--t--t--t+H++llllll--++tti-lrt+t++-I+t+HtIH--+++tII-ttt-t111
IIII
Stable
6Ort+++s~t~ab~l-er+f+~B~HrHrC~~-H~++H
TEST CIRCUIT FOR CURVE A
A
30rt++~~~~+H+h~+rHW~~+r~
D
20~HK~~~*+~~~~~~~H+~+H
150(.1
10 1-+-+-+++++++-~-++-bIH-hl'-++IH-f\I-H-.,+\,~\1I-H-1-H-H
I~
II
£0~0~1~~~0~.0~1~~~0~.~1~~~~~~~10
VBATT
CL - Load Capacitance - I!F
t The areas under the curves represent conditions th!lt may cause
the device to oscillate. For curves B, C, .and D, R2 and V+ are
adjusted to establish the inRial VKA and IKA condiiions with CL = O.
VBATTandCLarethenadjustedtcideterminetherangesofs~bility.
TEST CIRCUIT FOR CURVES B, C, AND D
Figure 15
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TL1431C,TL1431Q,TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
APPLICATION INFORMATION
Table of Application Circuits
FIGURE
APPLICATION
Shunt regulator
16
Single-supply comparator with temperature-compensated threshold
17
Precision high-current series regulator
18
Output control of a 3-terminal fixed regulator
19
Higher-current shunt regulator
20
Crowbar
21
Precision 5-V, 1.5-A, 0.5% regulator
22
Efficient 5-V precision regulator
23
PWM down converter with 0.5% reference
24
Voltage monitor
25
Delay timer
26
Precision current limiter
27
Precision constant-current sink
28
V(BATT)
R
}-'Wv--_.---.....- -
Vo
'---Vo
Von~2V
Voff ~ V (BATT)
TL1431
Input ---'Wv---h&
R2
0.1%
VIT
Vo
= (1 +
=~)v.(ref)
TL1431
=2.5 V
GND
NOTE A: R should provide cathode current" l-mA to the TLI431
at minimum V(BATT.)
Figure 17. Single-Supply Comparator With
Temperature-Compensated Threshold
Figure 16. Shunt Regulator
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TL1431C, TL1431Q, TL1431Y
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
APPLICATION INFORMATION
V(BATJ') - . - - - - - - - - - - ,
Vo =
(1
-!,
=~h(ref)
v
'NOTE A: R should provide cathode current ~ l-mA to the TL 1431
at minimum V(BATJ').
Figure 19. Output Control of a 3-Terminal
Fixed Regulator
Series Regulator
R
+ =~h(ref)
Min V = VI(ref) + 5 V
Figure 18. Precision High-Current
V(BATJ')--'I/I./'v--....- - -...-----1......-
= (1
Vo
V(BATJ')
-----<._---......-
710....
Vo
R1) VI(ref)
Vtrip = ( 1 + R2
Figure 20. Higher-Current Shunt Regulator
NOTE A: Refer to the stability boundary conditions on
Figure 15 to determine allowable values for the
capacitor.
Figure 21. Crowbar
~TEXAS
INSTRUMENTS
3--106
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL1431C, TL1431Q,TL1431V
PRECISION PROGRAMMABLE REFERENCES
SLVS062B - DECEMBER 1991 - REVISED AUGUST 1995
APPLICATION INFORMATION
)r----..- Vo =5 V
Out
V(BATI)
1---..-- Vo =5 V, 1.5 A, 0.5%
27.4k!l
0.1%
2430
0.1%
27.4k!l
0.1%
2430
0.1%
NOTE A: Rb should provide cathode current;;, 1- rnA to
the TLl431.
Figure 22. Precision 5-V, 1.5-A, 0.5% Regulator
Figure 23. 5-V Precision Regulator
12V
Vee
10k!l
10kU
0.1%
TL59S
X
Not
Used
10k!l
0.1%
-=-=-
Feedback
Figure 24. PWM Converter With 0.5% Reference
~lExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
3-107
TL1431C, TL1431Q, TL1431Y
PRECISION PROGRAMMABLE· REFERENCES
SLVS062B- DECEMBER 1991 - REVISED AUGUST 1995
APPLICATION INFORMATION
6800
12V--~~------~~~~
R1B
R1A
R4
R
TL1431
R2A
R2B
Off
Low Limit
= (1
+ =~:)VI(ref)
LED on When
12 V
Delay = R x C x 11(12 V) _ V
R1A)
Low Limit < V(BATT) < High Limit
High Limit = ( 1 + R2A VI(ref)
I(ref)
Figure 26. Delay Timer
NOTE A: R3 & R4 are selected to provide the desired LED intensity
and cathode current ~ 1 rnA to the TL 1431.
Figure 25. Voltage Monitor
V(BATT)
VI(ref)
10 = - - + I KA
RCL
R1 =
V
(BATT)
(~~E) +
VI(ref)
10=~
IKA
Figure 28. Precision Constant-Current Sink
Figure 27. Prec:ision Current Limiter
~1ExAs
3-108
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSl30-0CTOBER 1995
DBVS PACKAGE
(TOP VIEW)
•
Low-Voltage Operation ••• to 1.24 V
•
1% Reference Voltage Tolerance
•
•
Adjustable Output Voltage,
Vo = Vrefto 6 V
Low Operational Cathode Current .•• 80
•
•
0.25 n Typical Output Impedance
SOT-23 Package
NC
J.IA
ANODE
NC
REF
CATHODE
description
NC • No internal connection
The TLV431 A is a low·voltage 3·terminal
adjustable voltage reference with specified
thermal stability over applicable industrial and
commercial temperature ranges. Output voltage
may be setto any value between Vref (1.24 V) and
6 V with two external resistors (see Figure 2). The
TLV431A operates from a lower voltage (1.24 V)
than the widely used TL431 and TL1431 shunt
regulator references.
LPPACKAGE
(TOP VIEW)
CATHODE
ANODE
REF
When used with an optocoupler, the TLV431A is an ideal voltage reference in an isolated feedback circuit for
3-Vto 3.3-V switching-mode power supplies. This device has a typical output impedance of 0.25!l Active output
circuitry provides a very sharp turn-on characteristic, making the TLV431A an excellent replacement for
low-voltage zener diodes in many applications, including on-board regulation and adjustable power supplies.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
TO·92
(LP)
SOT·23
(DBVS)
O°C to 70°C
TLV431 ACLP
TLV431 ACDBV5
-40°C to 85°C
TLV431AILP
TLV431AIDBV5
CHIP FORM
(V)
TLV431AY
The LP package is available taped and reeled. Add R suffix to device type (e.g., TLV431 ACLPR).
The DBV5 is only available taped and reeled (no R suffix is required).
symbol
functional block diagram
CATHODE
REF
Anode
--.~~f--
Cathode
ANODE
~::.:n.:.:: =.:',.';.~o:::m...:.
:==-=
standard warranty. ProcIuC/lon processing does not .-nrily In,'ude
IeSllng of III para_
,
~TEXAS
Copyright © 1995, Texas Instrumems Incorporated
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
3-109
TLV431 A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSl30-OCTOBER 1995
equivalent schematic
Cathode
REF
Anode
~TEXAS·
INSTRUMENTS
3-110
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV431 A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130-0CTOBER 1995
TLV431AY chip information
This chip, when properly assembled, displays characteristics similar to the TLV431 A. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CATHODE
(3)
REF
(4)
TLV431AY
(5) ANODE
CHIP THICKNESS: 10 TYPICAL
BONDiNG PADS: 4 x 4 MINIMUM
TJmax=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~
~
II I I I II I I I II I I I II I I I II I I I
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-111
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130 - OCTOBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Cathode voltage, VKA (see Note 1) ........................................................... 7 V
Continuous cathode current range, IK ............................................ -20 mA to 20 mA
Reference current range, Iref ................................................... -0.05 mA to 3 mA
Power dissipation, Po ................................................ See Dissipation Rating Table
Operating free-air temperature range, TA: C-suffix ............... , ..................... O°C to 70°C
.
I-suffix ................................... -40°C to 85°C
Storage temperature range, Tstg ............. ~ ...... ' ............................. -65°C to 150°C
Lead temperature 1,6 mm (1116 inch) from case for10 seconds ................... , ........... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to the anode terminal, unless otherwise noted.
DISSIPATION RATING TABLE
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
=
=
TA 70°C
POWER RATING
=
TA 85°C
POWER RATING
LP
n5mW
6.2mWrC
496mW
403mW
DBV5
150mW
1.2mW/oC
96mW
78mW
recommended operating conditions
Cathode voltage, VKA
Cathode current, IK
Operating free·air temperature range, TA
ITLV431AC
I TLV431 AI
~TEXAS
3-112
INSTRUMENTS
POST OFFICE BOX 655303 • oALLAS. TEXAS 75266
MIN
MAX
Vref
6
UNIT
V
0.1
15
mA
0
70
-40
85
°C
TLV431A
LOW·VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130 - OCTOBER 1995
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
Vref
TEST CONDITIONS
VKA= Vref.
IK=10mA.
See Figure 1
Reference voltage
TLV431AI
TLV431AC
MIN
TYP
MAX
MIN
TYP
MAX
TA = 25°C
1.228
1.240
1.252
1.228
1.240
1.252
TA = full range
1.221
1.259
1.215
UNIT
V
1.265
Vref(dev)
Vref deviation over full
temperature range
(see Note 3)
IK= 10 mAo
VKA= Vref.
See Note 2 and Figure 1
4
12
6
20
mV
INref
INKA
Ratio of Vref change in
cathode voltage change
IK=10mA.
See Figure 2
,WKA = Vref to 6 V.
-1.5
-2.7
-1.5
-2.7
V-
Iref
Reference terminal
current
IK=10mA.
R2 = 00.
R1 = 10kQ,
See Figure 2
0.15
0.5
0.15
0.5
I1A
Iref(dev)
II(ref) deviation over full
temperature range
(see Note 3)
IK=10mA.
R1 = 10kn.
R2 = 00.
See Note 2 and Figure 2
0.05
0.3
0.1
0.4
I1A
IK(min)
Minimum cathode current
for regulation
VKA= Vref.
See Figure 1
55
80
55
80
I1A
loff
Off-state cathode current
VKA=6V.
See Figure 3
Vref=O.
0.001
0.1
0.001
0.1
I1A
IZkal
Dynamic impedance
(see Note 4)
f,;; 1 kHz.
VKA=Vref.
IK=0.1mAt015mA
See Figure 1
0.25
0.4
0.25
0.4
{1
mV
NOTES: 2. Full temperature range is-40°C to 85°C for TLV431 AI. and O°C to 70°C for the TLV431AC.
3. The deviation parameters Vref(dev) and lref(dev) are defined as the differences between the maximum and minimumvaluesobtained
over the rated temperature range. The average full-range temperature coefficient of the reference input voltage. aVref.
is defined as:
where .iTA is the rated operating free-air temperature range of the device.
aVref can be positive or negative depending on whether minimum Vref or maximum Vref. respectively. occurs at the lower
temperature.
.iV
4. The dynamic impedance is defined as: IZk I =
a
IKA
.i K
When the device is operating with two extemal resistors (see Figure 2). the total dynamic impedance of the circuit is given by:
iZkal=
~y =
IZkal x (1
+
=~)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
3-113
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSl30 - OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
Input ---'lNv-.--
Input
Vo
----'l/V'v-~t---
Vo
R1
i
R2
vre,
vre,
-=-
-*Figure 1. Test Circuit for VKA = Vref
Vo
Vo
=VKA =Vref x (1 + R1/R2)+lref x R1
Vo
Figure 3. Test Circuit for loff
~TEXAS
INSTRUMENTS
3-114
-=-
Figure 2. Test Circuit for VKA > Vref
=VKA =Vref
Input --JlNv-+--
-*-
POST· OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130-0CTOBER 1995
PARAMETER MEASUREMENT INFORMATION
REFERENCE VOLTAGE
1.254
I
REFERENCE INPUT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
250
1_
I
1.252
0(
c
>
I
1.250
&
:!l!
1.248
u
1.246
'$
a..
.5
~
3c
I!!
ila:
1.244
i
1.242
I
C
~
./
1.240
V
u
c
I!!
ila:
I
V
-25
"""'"
100
i
./
1.238
-SO
150
II
/'
I
>
200
'"
i"""
I
IK = 10 mA
R1=10kn
R2 =00
IK=10mA
0
25
50
75
100
125
50
-50
150
-25
TJ - Junction Temperature - °C
'""
i'-...
0
25
50
75 100 125
TJ - Junction Temperature - °C
Figure 4
150
Figure 5
CATHODE CURRENT
CATHODE CURRENT
vs
vs
CATHODE VOLTAGE
CATHODE VOLTAGE
15
250
VKA = Vref
TA=25°C
VKA = Vref
200 I- TA = 25°C
10
150
0(
0(
E
I
::t
5
I
C
~
C
~
'"
U
0
(
II
'C
0
.c
1;j
u
'"
u
II
'C
0
I
50
~
0
.c
-50
I
-100
1;j
U
-5
100
J!.
.J!.
-150
-10
-200
-15
-1
I
-0.5
o
0.5
VKA - Cathode Voltage - V
1.5
-250
-1
Figure 6
-0.5
0.5
o
VKA - Cathode Voltage - V
1.5
Figure 7
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-115
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130 - OCTOBER 1995
PARAMETER MEASUREMENT INfORMATION
RATIO OF DELTA REFERENCE VOLTAGE
TO DELTA CATHODE VOLTAGE
OFF-STATE CATHODE CURRENT
40
va
va
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
o
V~ =5~
J
Vret =" V
c(
r
C
3c ~E
30
f
~
S
CD
i i
-0.3
! ~
- - - --
~
g .S! -0.4
"0 is
20
,gIII ui
Sl
~
5
-0.2
I
II
u
-80
-0.1
~
c
II:
:a
o-SO
-25
0
25
50
75
100
125
\
-0.6
~ S
~
-0.7 ~
-0.8
)
\
-0.5
.I!!
I~!
10
I
~
150
-50
IK=10mA
~VKA=Vrett06V
I· I
-25
T J - Junction Temperature - °C
0
I
25
50
75
100
TJ - Junction Temperature -
Figure 8
125
°c
Figure 9
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
350
~
,
IK=1 mA
TA = 25°C
:>c
I
II
300
~
1!0
z
=
C
1g.
3V
J~~I~:
~
250
,
TP
a.
oS
200
180kO
"
1600
W
I
.;
Test circuit for equivalent noise voltage
150
10
100
1k
10 k
f- Frequency - Hz
100k
Figure 10
~TEXAS
3-116
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
150
TLV431 A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130 - OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
EQUIVALENT INPUT NOISE VOLTAGE
OVER A 10-SECOND PERIOD
10
>:::l
8
I
t
6
~
4
z=
2
'0
1
.5
li
~
Ifi'
-I
rr-
!
.1
f=0.1 Hz to 10 Hz
IK=1 mA
TA=25°C
II
..
II.N
IV,
-2
o
Mil
~~ VI
.Alii
[PII
II
II IAI
fl Jl1q.(i
-4
~
,yv
~
-6
-;;
2
4
6
t-TIme-s
8
10
3V
2.2!1F
TP
·1'~
820n
16n
Test circuit for 0.1-Hz to 1D-Hz equivalent noise voltage
Figure 11
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-117
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130-0CTOBER 1995
PARAMETER MEASUREMENT INFORMATION
SMALL-SIGNAL VOLTAGE GAIN
!PHASE MARGIN
vs .
FREQUENCY
80
III
'0
I
i
IK= 10 rnA
TA = 25°C
r------.f---.......-
I'...
60
i
I'-...
50
Output
1800
40
~
" ,
30
t
20
~
J
m
u:
r- ....
70
C
10
-=L -_ _ _ _- - -_ _
~._
_ _-
5V
GND
o
-10
TEST CIRCUIT FOR VOLTAGE GAIN
AND PHASE MARGIN
> -20
CC
100
10 k
1k
100k
1M
f - Frequency - Hz
Figure 12
REFERENCE IMPEDANCE
vs
FREQUENCY
.100
IK=0.1 rnA to 15 rnA
TA=25°C
a
I
I
1000
I-
10
r----.>-A.Jvv--.---.---
IJ
1000
J
I
1!
l!
Output
'--____- - - - - . -.......- - - GND
0.1
TEST CIRCUIT FOR REFERENCE IMPEDANCE
0.01
1k
10 k
100k
1M
10M
f - Frequency - Hz
Figure 13
~TEXAS
3-118
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLV431A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVS130 - OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
PULSE RESPONSE 1
3.5
Input
3
>
I
&
!!
~
:;
8:>
18kQ
,----__.JV\/\r--e--__.--
2.5
2
1.5
0
Output
:;
Q.
Pulse
Generator
f= 100 kHz
Output
SOQ
I
IIII
.5
R =18kn
TA = 25°C
II
\
0.5
GND
\.-
0
TEST CIRCUIT FOR PULSE RESPONSE 1
-0.5
02345
t-Time-Ils
6
7
8
Figure 14
PULSE RESPONSE 2
3.5
3
>
I
I_I
R=1.8kn
TA=25°C
Input
1.8kn
Output
2.5
CD
I»
.l!I
~
:;
8:>
2
1.5
0
Pulse
Generator
f= 100 kHz
Output
50Q
"CI
C
III
:;
Q.
.5
GND
0.5
0
\
TEST CIRCUIT FOR PULSE RESPONSE 2
-0.5
023
456
t-Time-IJ.S
7
8
Figure 15
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
3-119
TLV431 A
LOW-VOLTAGE ADJUSTABLE PRECISION SHUNT REGULATORS
SLVSI30 - OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
STABILITY BOUf'.!DARY CONDITIONt .
16
1~11
JlIlll
TA = 25°C
111111
14
I
t
~
-;
0.1 1----t--f---t----l.,c;--t---t-:7'''''P'''''-t-+_--I
i
Q
0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
10 - Output Current - A
Figure 1. Dropout Voltage Versus Output Current
Power good (PG) reports low output voltage and can be used to implement a power-on reset or a low-battery
indicator.
The TPS71xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version). The TPS71xx family is available in POIP
(8 pin), SO (8 pin), and TSSOP (20 pin) packages. The TSSOP has a maximum height of 1.2 mm.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
3-129
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS7101 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
AVAILABLE OPTIONS
OUTPUT VOLTAGE
PACKAGED DEVICES
(V)
TJ
MIN
,
-55°C to 150°C
..
TYP
MAX
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
TSSOP
(PW)
CHIP FORM
(V)
4.9
5
5·1
TPS7150QD
TPS7150QP
TPS7150QPWLE
TPS7150Y
4.75
4.85
4.95
TPS7148QD
TPS7148QP
TPS7148QPWLE
TPS7148Y
3.23
3.3
3.37
TPS7133QD
TPS7133QP
TPS7133QPWLE
TPS7133Y
TPS7101QD
TPS7101QP
TPS71 01 QPWLE
TPS7101Y
Adjustable§
1.2 Vt09.75 V
The 0 package IS available taped and reeled. Add R SuffiX to deVice type (e.g., TPS715OQDR). The PW package IS only available
left-end taped and reeled and is indicated by the LE suffix on the device type (i.e., TPS715OQPWLE). The TPS7101 Q is programmable
using an external resistor divider (see application information). The chip form is tested at 25°C.
TPS71xxPW·20
VI -
__-
__- -81
IN
PG
9
17
PG
15
IN
SENSE
IN
OUT
EN
OUT
10
O.l.IlF
6
GND
Vo
---~
COlll
+ 10llF
I
ESR
I
_ _ _ .JI
11 Capacitor selection is nontrivial. See application information section
for details.
Figure 2. Typical Application Configuration
~TEXAS
3-130
INSTRUMENTS
POST OFFICE.BOX 655303. DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q,TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TPS71xx chip information
These chips, when properly assembled, display characteristics similar to the TPS71 xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
(5)
BONDING PAD ASSIGNMENTS
IN
EN
SENSEt
(3)
(2)
(6)
TPS71xx
(4)
(7)
FBt
OUT
PG
(1)
GND
CHIP THICKNESS: 15 MILS TYPICAL
r
BONDING PADS: 4 x 4 MILA MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10'Yo.
ALL DIMENSIONS ARE IN MILS.
t
SENSE - Fixed voltage options only (TPS7133, TPS7148,
and TPS7150)
:j: FB - Adjustable version only (TPS71 01)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possible to the device;
for other implementations, refer to SENSE-pin
connection discussion in the applications
information section of this data sheet.
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
functional block diagram
IN --------~---.------+_
__
~~--------.
RESISTOR DIVIDER OPTIONS
EN --------_>--~
....---+---
PG
DEVICE
R1
TPS7101
TPS7133
TPS7148
TPS7150
0
420
726
756
R2
00
233
233
233
UNIT
(1
kO
k(1
kO
NOTE: Resistors are nominal values only.
1---....-
OUT
SENSEi/FB
R1
R2
GND
§ For most applications, SENSE should be externally connected to OUT as close as possible to the device. For other implementations, refer to
SENSE-pin connection discussion in applications infonnation section.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-131
.TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 ~ REVISED AUGUST 1995
absolu~ maximum ratings over operating free-air temperature range (unless otherwise noted)t
Input voltage range:!:, VI, PG, SENSE, EN .............................................. -0.3 to 10 V
Output current, 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2 A
.Continuous total power dissipation ......... ;................... See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ .................................... ~55°C to 150°C
Storage temperature range, Tstg ............................ ;..................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Stresses beyond those listed under "absolute maximum ratings' may ~use permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
:): All voltage values are with respect to network terminal ground.
t
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Figure 3)
PACKAGE
TAS25°C
POWER RATING
DERATING FACtoR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA=125~C
POWER RATING
725mW
1175mW
700mW
5.8mW/oC
9.4mW/oC
5.6mW/oC
464mW
752mW
448mW
145mW
235mW
140mW
D
P
PW§
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 4)
PACKAGE
TCS25°C
POWER RATING
DERATING FACTOR
ABOVE TC 25°C
TC=70°C
POWER RATING
TC = 125°C
POWER RATING
2188mW
2738mW
4025mW
17.5mW/oC
21.9mWfOC
32.2mWfOC
1400mW
1752mW
2576mW
438mW
548mW
805mW
D
P
PW§
=
§ Refer to thermal information section for detailed power dissipation considerations when using the
TSSOP package.
DISSIPATION DERATING CURVE
vs
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
vs
CASE TEMPERATURE
14oo~----r-----~----~----~----~
~I
I..
5:::I
C
~
8
§
e
~
I
fi
75
100
125
TA - Free-Air Temperature - 9C
Figure 3
Figure 4
~TEXAS
3-132
TC - Case Temperature - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75255
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
recommended operating conditions
Input voltage, Vlt
MIN
MAX
TPS7101Q
2.5
10
TPS7133Q
3.77
10
TPS7148Q
5.2
10
TPS7150Q
5.33
10
High-level input voltage at EN, VIH
2
Low-level input voltage at EN, VIL
Output current range, 10
Operating virtual junction temperature range, TJ
UNIT
V
V
0.5
V
0
500
mA
-40
125
°C
t Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To
calculate the minimum input voltage for your maximum output current, use the following equation:
VI(min) = VO(max)
+ VOO(max load)
Becausethe TPS71 01 is programmable, rOS(on) should be used to calculate VOO before applying the above equation. Theequationforcalculating
VOO from rOS(on) is given in Note 2 in the electrical characteristics table. The minimum value of 2.5 V is the absolute lower limit for the
recommended input voltage range for the TPS71 01.
=
=
=
=
electrical characteristics at 10 10 rnA, EN 0 V, Co 4.7l!F/ESRt 1 n, SENSE/FB shorted to OUT
(unless otherwise noted)
PARAMETER
TEST CONDITIONS*
TJ
TPS7101Q,TPS7133Q
TPS7148Q, TPS7150Q
MIN
EN:S:0.5 V,
25°C
VI=VO+ 1 V,
Ground current (active mode)
o mA:S: 10:S:500 mA
Input current (standby mode)
EN=VI,
2.7V:S:VI,,10V
Output current limit
VO=OV,
VI= 10V
Pass-element leakage current
in standby mode
EN=V"
2.7V"VI,,10V
PG leakage current
Normal operation,
VPG=10V
285
25°C
0.5
2
25°C
1.2
-40°C to 125°C
0.5
1
-40°C to 125°C
0.02
25°C
-40°C to 125°C
61
75
165
2.5 V"VI,,6 V
6v:S: VI,,10V
2.7V"VI,,10V
-40°C to 125°C
OV:S:VI,,10V
25°C
0.5
0.5
50
-0.5
0.5
-40°C to 125°C
-0.5
0.5
25°C
-40°C to 125°C
A
!lA
!lA
ppm/"C
2.05
2.5
2.5
1.06
V
mV
25°C
-40°C to 125°C
IpG = 300 !lA
!lA
V
2.7
-40°C to 125°C
25°C
!lA
°C
2
25°C
Minimum VI for active pass element
Minimum VI for valid PG
0.5
0.5
-40°C to 125°C
EN hysteresis voltage
EN input current
2
2
Thermal shutdown junction temperature
EN logic low (active mode)
350
460
-40°C to 125°C
UNIT
MAX
-40°C to 125°C
25°C
Output voltage temperature coefficient
EN logic high (standby mode)
TYP
1.5
1.9
l1A
V
V
t ESR refers to the eqUivalent reSistance, including Intemal resistance and senes resistance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thennal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-133
TPS71 01 Q,TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
=
=
electrical characteristics at 10 10 mA, VI 3.5 V, EN
OUT at device leads (unless otherwise noted)
PARAMETER
Reference voltage
(measured at FB with OUT
connected to FB)
=0 V, Co =4.7 jlFIESRt == 10, FBshorted.to
VI = 3.5 V,
10= 10 mA
2.5 V:S:VI:S: 10V,
See Note 1
5 mA:S:10:S:500mA,
Reference voltage
temperature coefficient
50~:S:10:S:150mA
VI = 2.4 V,
VI =2.4 V,
150 mA:s: 10:S: 500 rnA
Pass-element series
resistance (see Note 2)
Input regulation
MIN
MAX
1.178
25°C
-40°C to 125°C
TYP
1.143
_40°C to 125°C
61
75
25°C
0.7
1
0.63
1.3
0.52
0.85
-40°C to 125°C
1.3
-40°C to 125°C
25°C
50~:S:10:S:500 rnA
25°C
0.32
VI=5.9V,
50~:S:10:S:500mA
25°C
0.23
5O~:S:10:S:5OOmA,
25°C
18
-40°C to 125°C
25
-40°C to 125°C
25°C
14
-40°C to 125°C
25
10 = 50 ~ to 500 mA, 2.5 V:s: VI:S: 10 V,
See Note 1
25°C
22
-40°C to 125°C'
54
10 = 500 mA,
See Note 1
Output noise-spectral
density
f=120Hz
Output noise voltage
10 Hz:s:f:s: 100 kHz,
ESRt=10
48
44
25°C
45
_40°C to 125°C
44
25°C
95
CO=10~
25°C
89
CO= 100~F
25°C
74
PG hysteresis voltage§
Measured at VFB
VI=2.13V
FB input current
0 ..92 x
VFB(nom}
12
25°C
0.1
-10
-20
mV
~Vrms
0.1
V
mV
0.4
0.4
-40°C to 125°C
25°C
mV
~V!;iHz
0.98 x
VFB(nom}
25°C
-40°C to 125°C
mV
dB
54
CO=4.7~F
-40°C to 125°C
0
59
2
VFB voltage decreasing from above VPG
IpG=400~,
25°C
-40°C to 125°C
25°C
PG trip-threshold VOltage§
ppm/"C
0.85
10 = 5 rnA to 500 mA, 2.5V:S:VI:S:l0V,
See Note 1
f=120Hz
V
1
25°C
VI = 3.!l V,
VI = 2.5 Vto 10 V,
See Note 1
UNIT
V
1.213
5O~:S:10:S:5OOmA
10=50~
PG output low voltage§
TJ
VI =2.9 V,
Output regulation
Ripple rejection
TPS7101Q
TEST CONDITIONs*
10
20
V
nA
t ESR refers to the eqUivalent resistance Including Internal resistance and senes resistance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
§ Output voltage programmed to 2.5 V with closed-loop configuration (see application information).
NOTES: 1. When VI < 2.9 V and 10 > 150 mA simultaneously, pass element rOS(on} increases (see Figure 31) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range. .
.
2. To calculate dropout voltage, use equation:
VOO = 10· rOS(on}
rOS(on) is a function of both output current and input voltage. The parametric table lists rOS(on} for VI '" 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values; refer to Figure 30.
~TEXAS
3-134
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SlVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
electrical characteristics at 10 =10 mA, VI =4.3 V, EN =0 V, Co =4. 71!F/ESRt =1 I), SENSE shorted
to OUT (unless otherwise noted)
PARAMETER
VI =4.3V,
10=10mA
4.3V:,>VI:,>10V,
5 mA:'> 10 :'> 500 mA
10= 10mA,
VI =3.23V
10=100mA,
VI = 3.23 V
10 =500 mA,
VI = 3.23 V
Pass-element series resistance
(3.23 V - VO)IIO,
10 = 500 mA
VI = 3.23 V,
Input regulation
VI=4.3Vt010V,
50 !lA :'> 10 :'> 500 mA
Output voltage
Dropout voltage
Output regulation
10 = 50!lA to 500 mA, 4.3 V:'> VI:'> 10 V
10 =50!lA
f=120Hz
10 =500 mA
Output noise-spectral density
Output noise voltage
PG trip-threshold voltage
TJ
0.02
25°C
47
25°C
-40°C to 125°C
235
25°C
60
mV
300
400
0.47
25°C
0.6
0.8
25°C
20
-40°C to 125°C
27
21
25°C
38
75
-40°C to 125°C
30
25°C
60
120
-40°C to 125°C
25°C
43
-40°C to 125°C
40
25°C
39
-40°C to 125°C
36
Q
mV
mV
mV
54
dB
49
2
25°C
274
CO=10jlF
25°C
228
CO= 100jlF
25°C
159
0.92 x
VO(nom)
jlvr./HZ
jlVrms
0.98 x
VO(nom)
25°C
35
25°C
0.22
-40°C to 125°C
V
6
80
-40°C to 125°C
-40°C to 125°C
UNIT
8
Co = 4.7 jlF
VI =2.8V
MAX
3.37
25°C
Vo voltage decreasing from above VPG
IpG= 1 mA,
3.23
-40°C to"125°C
PG hysteresis voltage
PG output low voltage
TYP
3.3
25°C
-40°C to 125°C
f= 120Hz
10 Hz:'>f:'> 100kHz,
ESRt= 1 Q
MIN
-40°C to 125°C
10 = 5 mAt0500 mA, 4.3V:,>VI:,>10V
Ripple rejection
TPS7133Q
TEST CONDITIONS*
V
mV
0.4
0.4
V
*t
ESR refers to the equivalent resistance including internal resistance and series resistance.
Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-135
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148Y, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
electrical characteristics at 10 =10 mA, VI =5.85 V, EN =0 V, Co =4.7 J.1F/ESRt =1 n, SENSE shorted
to OUT (unless otherwise noted)
PARAMETER
Output voltage
VI = 5.85 V,
10 = 10mA
5.85V"VI,,10V,
5 rnA" 10" 500 mA
10= 10mA,
VI =4.75V
10=lOOmA,
VI=4.75V
10 =500 mA,
VI=4.75V
Pass-element series resistance
(4.75 V - VO)/lO,
10 = 500 rnA
VI = 4.75 V,
Input regulation
VI = 5.85 Vto 10 V,
50!1A" 10" 500 mA
Dropout voltage
Output regulation
10 = 50!1A to 500 mA, 5.85 V" VI" 10 V
10 = 50!1A
1= 120 Hz
10 = 500 mA
Output noise-spectral density
Output noi!l8 voltage
PG trip-threshold voltage
TJ
4.75
25°C
4.95
0.08
6
30
37
54
-40°C to 125°C
150
25°C
25°C
0.32
0.35
0.52
25°C
27
-40°C to 125°C
37
25°C
12
42
-40°C to 125°C
80
42
25°C
60
-40°C to 125°C
130
25°C
42
-40°C to 125°C
39
25°C
39
-40°C to 125°C
35
Q
mV
mV
mV
53
dB
50
2
25°C
410
CO= 10l1F
25°C
328
CO=looI1F
25°C
212
I1V/..fHz
I1Vrms
0.92 x
VO(nom)
0.98 x
VO(nom)
25°C
50
25°C
0.2
V
mV
0.4
.0.4
-40°C to 125°C
t ESR relers to the equivalent resistance Including Intemal resistance and senes resistance.
mV
250
Co = 4.7 I1F
VI =4.12 V
V
180
-40°C'to 125°C
-40°C to 125°C
UNIT
8
25°C
25°C
Vo voltage decreasing lrom above VPG
IpG = .1.2 mA,
MAX
-40°C to 125°C
PG hysteresis voltage
PG output low voltage
TYP
4.85
25°C
-40°C to 125°C
1=120Hz
10 Hz "1,, 100 kHz,
ESRt= 1 Q
MIN
-40°C to 125°C
10 = 5 mA to 500 mA, 5.85 V" Vp; 10 V
Ripple rejection
TPS7148Q
TEST CONDITIONS:!:
V
.
:I: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
3-136
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
=
electrical characteristics at 10 10 mA, VI
to OUT (unless otherwise noted)
PARAMETER
Output voltage
=6 V, EN =0 V, Co =4.7 /!F/ESRt =1 n, SENSE shorted
TEST CONDITIONs*
VI=6V,
10= 10 mA
6V",VI",10V,
SmA", 10 ",SOO mA
10=10mA,
VI=4.88V
10= 100mA,
VI=4.88V
10=500mA,
VI=4.88V
Pass-element series resistance
(4.88 V - VO)1I0,
10= 500 mA
VI = 4.88 V.
Input regulation
VI=6Vt010V,
50 IlA '" 10 '" 500 mA
Dropout voltage
Output regulation
10 =501lA to 500 mA, 6 V",VI '" 10V
10= 501lA
f= 120 Hz
10=500mA
Output noise-spectral density
Output noise voltage
PG trip-threshold voltage
25°C
0.13
6
27
32
47
-40°C to 125°C
146
25°C
-40°C to 125°C
mV
170
0.29
0.32
0.47
25°C
25
-40°C to 125°C
32
30
25°C
45
86
-40°C to 125°C
45
25°C
65
140
-40°C to 125°C
25°C
45
-40°C to 125°C
40
25°C
42
-4OOC to 125°C
36
n
mV
mV
mV
55
dB
52
2
25°C
430
CO= 1O I1F
250C
345
CO= 1OO I1F
25·C
220
0.92 x
VO(nom)
I1V/VHz
I1Vrms
0.98 x
VO(nom)
25°C
53
25°C
0.2
-40°C to 125°C
V
230
25°C
-40°C to 125°C
UNIT
8
25°C
CO=4.7I1F
VI = 4.25 V
MAX
5.1
25°C
Vo voltage decreasing from above VPG
IPG= 1.2mA,
4.9
-40°C to 125°C
PG hysteresis voltage
PG output low voltage
TYP
5
25°C
-40°C to 125°C
f=120Hz
10Hz",f", 100kHz,
ESRt= 1 n
TPS71500
MIN
-40°C to 125°C
10= 5 mA to SOO mA, 6V",VI",10V
Ripple rejection
TJ
V
mV
0.4
0.4
V
'.
t ESR refers to the eqUIvalent resistance Including Intemal resistance and senes resistance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as pOSSible to ambient temperature; thermal effects must be
taken into account separately.
.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-t37
TPS71 01 Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
=
electrical characteristics at 10 10 mA,EN
shorted to OUT (unless otherwise noted)
=0 V, Co =4.7 f..lF/ESRt =1 n, TJ =25°C, SENSE/FB
PARAMETER
'TPSn01Y, TPS7133Y
TPS7148Y, TPS7150V
TEST CONDmONS*"
MIN
ENSO.5V,
TYP
VI=VO+ 1 V,
Ground current (active mode)
o mAS 10 S 500 mA
Output current limit
VO=OV,
VI = 10 V
PG leakage current
Normal operation,
VPG= 10V
Thermal shutdown junction temperature
1.2
A
IJA
0,02
Minimum VI for active pass element
Minimum VI for valid PG
IJA
285
,
EN hysteresis voltage
IPG =300 IJA
UNIT
MAX
165
°C
50
inv
2.05
V
1.06
V
t ESR refers to the equIvalent reSIstance, IncludIng Internal resIstance and senes resIstance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
TPS7101Y
PARAMETER
Reference voHage (measured at FB with OUT
connected to FB)
Pass-element series resistance (see Note 2)
TEST CONDITIONS*
VI = 3.5 V,
10= 10 mA
MIN
TYP
1.178
50lJA SloS150mA
150mASIoS500mA
VI =2.9V,
50 IJA S 10 S 500 mA
0.52
V
0.83
VI=3.9V,
50
IJA S 10 S 500 mA
VI =5.9 V,
50 IJA S 10 S 500 mA
0.23
VI =2.5 Vto 10V,
See Note 1
50 IJA S 10 S 500 mA,
2.5VSVIS10V,
See Note 1
10 =5 mA to 500 mA,
2.5 V S VI S 10 V,
See Note 1
10 = 50 IJA to 500 mA,
Ripple rejection
VI = 3.5 V,
10 = 50 IJA
f = 120 Hz,
Output noise:spectral density
VI = 3.5 V,
f=120Hz
CO=4.7I1F
Output noise voltage
VI = 3.5 V,
10 Hzsfs 100 kHz,
ESRt= 1 n
PG hysteresis voltage§
VI = 3.5 V,
Measured at VFB
PG output low voltage§
VI=2.13V,
IpG =400 IJA
FB input current
VI =3.5V
Output regulation
UNIT
0.7
VI =2.4 V,
VI =2.4V,
0.32
Input regulation
MAX
g
18
mV
14
mV
22
mV
59
dB
2
I1V1VHz
95
CO= 1O I1F
89
CO= 100l1F
74
12
I1Vrms
mV
0.1
V
0,1
nA
t ESR refers to the eqUIvalent resIstance IncludIng Internal resIstance and senes resIstance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
§ Output voltage programmed to 2,5 V with closed-loop configuration (see application information),
NOTES: 1 When VI < 2.9 V and 10> 150 mA simultaneously, pass element rDS(on) increases (see Figure 31) to a point such thatlhe resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2 To calculate dropout voltage, use equation:
VDO = 10' roS(on)
rDS(on) is a function of both output current and input voHage. The parametric table lists rDS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
p~grammed values, refer to Figure 30.
~TEXAS
INSTRUMENTS
3--138
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
electrical characteristics at 10 = 10 rnA, EN = 0 V, Co = 4. 71lF/ESRt = 1 n, TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
PARAMETER
Output voltage
TEST CONDITIONS*
TPS7133Y
MIN
TYP
VI=4.3V,
10= lOrnA
3.3
V,=3.23V,
10= lOrnA
0.02
MAX
UNIT
V
VI = 3.23 V,
10= 100 rnA
47
VI = 3.23 V,
10= 500 mA
235
(3.23 V - VO)1I0,
10= 500 rnA
VI = 3.23 V,
4.3V,;;VI,;;10V,
10 = 5 rnA to 500 rnA
21
mV
4.3 V ,;; VI ,;; 10 V,
10 = 50 !1A to 500 rnA
30
mV
Ripple rejection
VI=4.3V,
f=120Hz
10 = 50!1A
54
10 =500 rnA
49
Output nOise-spectral density
VI=4.3V,
f=120Hz
VI =4.3V,
10 Hz,;;f,;; 100kHz,
ESRt= 1 Q
CO=4.7IlF
274
CO= lO IlF
228
CO= lOO IlF
159
Dropout voltage
Pass-element series resistance
Output regulation
Output noise voltage
PG hysteresis voltage
VI =4.3V
PG output low voltage
VI =2.8V,
mV
0.47
Q
dB
2
IlVNHz
IlVrms
35
mV
0.22
IpG= 1 rnA
V
t ESR refers to the equivalent resistance including internal resistance and series resistance.
; Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
PARAMETER
Output voltage
TEST CONDITIONS;
TPS7148Y
MIN
TYP
MAX
UNIT
VI = 5.85 V,
10= lOrnA
4.85
VI =4.75 V,
10=10mA
0.08
VI = 4.75 V,
10= 100 rnA
30
VI = 4.75 V,
10 = 500 rnA
150
(4.75 V - VO)1I0,
10=500 rnA
VI = 4.75 V,
5.85V,;;VI,;;10V,
10 = 5 rnA to 500 rnA
12
mV
5.85 V,;;VI';; 10V,
10 = 50 !1A to 500 rnA
42
mV
Ripple rejection
VI = 5.85 V,
f=120Hz
10 = 50!1A
53
10 = 500 rnA
50
Output noise-spectral density
VI = 5.85 V,
f=120Hz
VI =5.85 V,
10 Hz,;;f,;; 100kHz,
ESRt= 1 Q
CO=4.7IlF
410
CO= lOIlF
328
CO= lOO IlF
212
Dropout voltage
Pass-element series resistance
Output regulation
Output noise voltage
PG hysteresis voltage
VI = 5.85 V
PG output low voltage
VI = 4.12 V,
V
mV
0.32
Q
dB
IlV/v'Hz
2
IlVrmS
50
IpG= 1.2mA
0.2
mV
0.4
V
t ESR refers to the equivalent resistance including internal resistance and series resistance.
; Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
.
~TEXAS
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
3-139
TPS7101Q,TPS7133Q,TPS714SQ,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVI,SED AUGUST 1995
electrical characteristics at 10 = 10 mA, EN = 0 V, Co = 4.7 IlF/ESRt = 1 Q, TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted) (continued)
PARAMETER
Output voltage
TEST CONDITIONS* .
TPS7150V
MIN
TVP
VI=6V,
10= lOrnA
5
VI = 4.88 V,
10= lOrnA
0.13
MAX
UNIT
V
VI = 4.88 V,
10 = 100 rnA
27
VI = 4.88 V,
10= 500!lA
146
(4.88 V - VO)/IO,
10=500 rnA
VI = 4.88 V.
6V:SVI:Sl0V,
10= 5 rnA to 500 rnA
30
mV
6V:SVI:Sl0V,
10 = 50!lA to 500mA
45
mV
Ripple rejection
VI=6V,
1= 120 Hz
10 = 50!lA
55
10 =500 rnA
52
Output noise-spectral density
VI=6V,
l=l20Hz
VI=6V,
10 Hz:sI:s 100kHz,
ESRt=ln
Co =4.7 J.lF
Dropout voltage
Pass-element series resistance
Output regulation
Output noise voltage
PG hysteresis voltage
VI=6V
PG output low voltage
VI = 4.25 V,
0.29
2
mV
n
dB
J.lV/VHi
430
CO=10J.lF
345
CO= 100J.lF
220
53
mV
IPG= 1.2mA
0.2
V
J.lVnns
t ESR relers to the eqUivalent resistance Including Internal resistance and series resistance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thennal effects must be
taken into account separately.
.
~TEXAS
3--140
INSTRUMENTS
POST OFFICE BOX 655303 • OAu.AS. TEXAS 75265
TPS71 01 Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
I Minimum input voHage for active-pass element
vs Free-air temperature
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
I Minimum input voHage for valid PG
vs Free-air temperature
30
vs Free-air temperature
31
32
33
vs Output current
IQ
Quiescent current
vs Input voltage
VDO
Dropout voltage
vs Output current
,WDO
Change in dropout voltage
vs Free-air temperature
INO
Change in output voltage
vs Free-air temperature
Vo
Output voltage
vs Input voltage
AVO
Change in output voltage
vs Input voltage
Vo
Output voltage
vs Output current
Ripple rejection
vs Frequency
Output spectral noise density
vs Frequency
roS(on)
Pass-element resistance
vs Input voltage
R
Divider resistance
vs Free-air temperature
II(SENSE)
SE:NSE current
vs Free-air temperature
FB leakage current
vs Free-air temperature
vs Free-air temperature
VI
II (EN)
Input current (EN)
Output voltage response from Enable (EN)
VPG
Power-good (PG) voltage
vs Output voltage
Total ESR
vs Output current
Total ESR
vs Ceramic capacitance
Total ESR
vs Output current
TotalESR
vs Ceramic capacitance
34
35
36
37
38
39
40
41
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-141
TPS7101.Q, TPS7133Q, TPS7t48Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
OUTPUT CURRENT
INPUT VOLTAGE
355
TA'=25°C
345
::1.
I---
~I---
335 -
CC
QUIESCENT CURRENT
vs
TPS71xx,VI=10V
-
400
i.--
cc::1.
I
C
~
::s
(.)
C
CD
..
u
::s
300
-
325
315
C
~
::s
250
C
200
..
3
.!!!
295 -
TPS7133
Y ~ ~k'"'" T~S7148
I
I
285
• l ~r
I
I
I
I
I
50
TPS7133, VI = 4.3 V
J
o
J
/
/
300
/
C
200
150
-50
/
/'
>
I
t
/:
~'5
i
0
25
50
75
100
TA - Free-Air Temperature - °C
0.21---+--I-+--+-+-+--I--:ifL-+---I
0.15 I---+--I--+--+--I-----,t/L-
0.1
1---+---+-+-~'--+--+::;0"'9""""'+--+---;
125
50 100 150 200 250 300 350 400 450 500
Figure 7
3-142
10
0.251---+---+-+--+--+--+---+-+--+-'71
/'
-25
9
0.3 r---r----r--r---,--r----r----r-..,---,----,
I
(.)
8
DROPOUT VOLTAGE
vs
350
9
7
OUTPUT CURRENT
.1
250
6
FREE-AIR TEMPERATURE
I
j::s
5
vs
VI = VO(nom) + 1 V
10=10mA
aI
4
Figure 6
TPS7148Q
QUIESCENT CURRENT
C
~
::s
3
VI - Input Voltage - V
Figure 5
cc::1.
~
2
10 - Output Current - mA
400
-
~
o
o
50 100 150 200 250 300 350 400 450 500
I I
TPS7101 With Vo
Programmed to 2.5 V
I lll'
100
TPS7148, VI = 5.85 V
275
TPS7150
~~
150
::s
a
I
9
TPS7150, VI = 6 V
.....-:
~~~~/
I
-
(.)
305
265
~
I
.!!!
a
I
9
TA=25°C
350 f- RL=100
10 - Output Current - mA
Figure 8
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
10
E
I
4
~
'S
2
!
0
11.
e
c
.5
III
CI
.
c
.c
U
,/
6
III
CI
V
0
/
/
-8
-10
-50
.
I
10
CI
!
~
'5
11.
'5
5
III
CI
U
V
-10
I
~
/
-15
75
CHANGE IN OUTPUT VOLTAGE
\
INPUT VOLTAGE
5
,50
Figure 10
OUTPUT VOLTAGE
TA = 25°C
RL=10Q
25
TA - Free-Air Temperature - °C
Figure 9
vs
../
/
L
V
/'
-5
c
\\I
.c
0
25
50
75
100
TA - Free-Air Temperature - °C
./
0
0
.5
V
-25
VI = VO(nom) + 1 V
10=10mA
E
/1'
-6
15
>
/
/
-2
-4
20
/'
10 = 100mA
8
>
CHANGE IN OUTPUT VOLTAGE
vs
/
K
-
TPS7150
Ji.
TPS7148
~
'- TPS7133
J
~
'\
'0
~
o
o
-15
-20
2
3
,4
5
6
7
8
9
10
4
5
VI - Input Voltage - V
Figure 11
6
7
8
VI - Input Voltage - V
9
10
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-143
TPS71 01 Q, TPS7133Q, TPS1148Q, TPS7150Q
TPS71 01 V, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISEO AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7101Q
TPS7133Q
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
v$
OUTPUT CURRENT
2.52
3.34
TA = 25°C
2.515 r Vo Programmed to 2.5 V
>
2.51
I
GI
,
2.505
'$
~
~ 2.495
~
,
>
3.32
&
!
3.31
I
2.5 ~
~
~
_ V,=3.5V
3.3
1
'$
~
0
~ r--VI =10V
~
3.29
I
VI= 10V
~
2.49
3.28
2.485
2.48
-~
TA=25°C
3.33
3.27
o
100
200
300
400
3.26
500
o
100
10 - Output Current - mA
Figure 13
4.92
TPS7148Q
TPS7150Q
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
5.06
I
4.89
>
4.88
:!l!
4.87 ~
'$
4.86
~
~
4.85
I
4.84
0
~ 4.83
I
GI
DI
"'-.
5.01
'$
5
:::I
4.99
I
4.98
.e-
"
0
VI=10V
5.02
:!l!
~
V,=5.85V
5.03
~
4.96
4.81
4.95
o
100
200
300
500
400
~
Vi=6V
'-.:
r---J.
VI=10V
4.97
4.82
4.8
I
5.04
II
DI
4.94
o
100
200
300
10 - Output Current -
10 - Output Currant -mA
Figure 15
Figure 16
~TEXAS
3-144
500
5.05 - TA=25°C
TA = 25°C
4.9
>
400
300
Figure 14
I
4.91
200
10 - Output Currant - mA
INSTRUMENTS
POST OFFICE
eox 655303 •
DAUAS, TEXAS 75265
400
mA
500
TPS71 01 Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7133Q
TPS7101Q
RIPPLE REJECTION
RIPPLE REJECTION
vs
vs
FREQUENCY
FREQUENCY
70
lMH-W1111
~W~I~1~~~\
60
m
50
50
c
t
40
~CD
30
.!!
TA=25°C
VI=3.5V
20 Co = 4.711F (ESR = 1 Q)
No Input Capacitance
10 Vo Programmed to 2.5 V +fttitlll--H+lfIIIII--III+
'a;'
'i'
,
RL=500Q
111111 l i
a:
a:
8:
'0
1
c
40
a:
I-
m
'0
1
-!a.
=10Q
1K
10K
100K
1M
Figure 17
TPS7148Q
TPS7150Q
RIPPLE REJECTION
RIPPLE REJECTION
vs
vs
FREQUENCY
FREQUENCY
m
'0
·1
c
50
70
~
40
0
~
CD
I
-!a.
30
I-
~
-I-
RL=10Q
V
10
0
-10
10
~
m
'0
i'-RL = 100 kn
0
1SCD
1\
I- RL= 100 kn
50
40
RL= 10Q
a:
~
TA=25°C
VI=3.5V
Co =4.7 I1F (ESR = 1 Q)
No Input Capacitance
'"''''
1k
"""
10k
-!a.
a:
I....
I-
~
V
100k
1M
~
30
RL=500Q
~
20
10
10M
r\
~
'i'
I-
100
I-
1
c
I-
"""
l-
60
"'"
RL=500Q
20
10 M
~
,
a:
1M
Figure 18
70
~
100 k
~
f - Frequency - Hz
f - Frequency - Hz
60
~
-10 111111111 111111111 111111111
10
100
1k
10 k
10M
RL= 10Q
TA = 25°C
VI =3.5V
Co = 4.7 I1F (ESR = 1 Q)
No Input Capacitance
0
O~~~~~~~~~~~~~
100
I~
10
1111111111
10
20
a:
~
TA=25°C
VI=3.5V
CO=4.7I1F (ESR=1 Q)
No Input Capacitance
o
10
,,'"
100
1\
,,"',
1k
"""10 k
~
100 k
~
1M
10 M
f - Frequency - Hz
f - Frequency - Hz
Figure 19
Figure 20
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-145
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7101Q
TPS7133Q
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
I!SO
'\
::l
fc
I!SO
Co = 4.71lF (ESR = 1 Q
I·
~,
1\
I
10
TA = 25°C
No Input Capacitance
VI=3.5V
Vo Programmed to 2.5 V
..
'0
I\,
z
~
1)
II
II
Co = 4.71lF (ESR = 1 Q)
CD
,~
C
CO= 100 IlF(ESR=1 Q}
.§
z
i8-
\~
0.1
CD
111111
~v CO=10IlF(ES~,~1 n}
\
fc
",
CD
II
~
::l
Co = 10 IlF (ESR = 1 Q
8
TA = 25°C
No Input Capacitance
Vr=4.3V
a.
~
0.1
UI
UI
"$
a.
"$
"$
~
~
0
~
0
Co= 100 IlF (ESR = 1 Q}-V
0.01
"'
0.01
10
10
f - Frequency - Hz
f - Frequency - Hz
Figure 21
Figure 22
TPS7150Q
TPS7148Q
OUTPUT SPECTRAL NOISE DENSITY
OUTPUT SPECTRAL NOISE DENSITY
vs
vs
FREQUENCY
FREQUENCY
10
10
I!SO
TA -25°C
No Input Capacitance
VI = 5.85 V
II 111111111 1 1 0 0
Co = 10 IlF (ESR = 1 n)
~
::l
I
\
..
~
c
~
I
I , '" III'
, ,
Co = 4.7 IlF (ESR = 1 Q)
Co =
I!SO
\
::l
I
~
fc
.,
c
C
~
3l
z
"0
r\
Z
~
U
CD
a.
UI
"$
a.'
"$
0
0.01
10
~
U
CD
a.
"
0.1
Cf
100
II
\
0.1
~
0
10k
100k
-
-"'
Co = 100 IlF (ESR = 1 Q)
0.01
10
f - Frequency - Hz
Figure 23
'"'100
.10k
1k
f - Frequency - Hz
Figure ;24
~TEXAS'
3-146
II IIIII
"$
I 11111
1k
I
UI
i ~~,it~(~S~'l ~I~}
II IIIII
I I, .
Co = 4.7 IlF (ESR = 1 Q)
TA=25°C
No Input Capacitance
VI=6V
CD
CD
/
1?,~~ (ESR = 1,~~
~1I111
I I '111111
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100k
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS7101 Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
PASS·ELEMENT RESISTANCE
DIVIDER RESISTANCE
vs
vs
INPUT VOLTAGE
FREE·AIR TEMPERATURE
1.1
c:
I
3c
1
a:
1:
•E
.!
w
'"'"
1.2
TA = 25°C
VI(FB) = 1.12 V
0.9
c:
::E
0.8
0.7
~ r--....TPS7150
0.6
TPS7;;a-..:
c
0.9
a:
0.8
1
~V
~
0.5
\ 1\
0.4
;- 10=100mA
0.3
~
0.7
a:.
0.6
........... r-....
I
~
C
~
VI = VO(nom) + 1 V
VI(sense) = VO(nom)
I
3
10 =500 mA
L
II
D.
I
"..........
1.1
2
3
4
5
6
7
8
VI -Input Voltage - V
9
0.4
-50
10
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
ADJUSTABLE VERSION
FB LEAKAGE CURRENT
vs
vs
FREE·AIR TEMPERATURE
FREE·AIR TEMPERATURE
6
(.)
VI = VO(nom) + 1 V
Vl(sense) VO(nom)
=
5.6
c
ii:
=:c
Jl
I
5.2
5
Gi'
'"
c
GI
4.8
~
4.6
4.4
-50
/'
0.6
/
I
/
/
/
I
VFB=2.5V
0.5
V
5.4
I
/
II
0(
c
I
0.4
1:
V
~
::I
(.)
8.
0.3
.:
:I
....I
...m
0.2
0.1
V
/
0
25
50
75
100
125
-50
I
./
o
-25
125
Figure 26
FIXED-oUTPUT VERSIONS
SENSE PIN CURRENT
~::I
-
TPS77a;-
Figure 25
1:
r--
r--
-.......:
0.5
0.1
0(
:::l.
I
- .:::::
...... ,,:-........
0.2
5.8
F=:::: t:-
-25
TA - Free·Air Temperature - °C
0
25
50
75
100
125
TA - Free·Air Temperature - °C
Figure 27
Figure 28
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3--147
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL·CHARACTERISTICS
MINIMUM INPUT VOLTAGE FOR ACTIVE
PASS ELEMENT
vs
FREE-AIR TEMPERATURE
MINIMUM INPUT VOLTAGE FOR VALID
POWER GOOD (PG)
vs
FREE-AIR TEMPERATURE
1.1
2.1
RL=500n
2.09
>
I
8.
:l1!
~
:;
CI.
.5
2.07
/
2.06
2.04
i
2.03
/
I
, ./
V
/
:l1!
~
-25
V
-'-
1.08
:;
CI.
.5
E
:s
E
1/
1.07
C
i
V
I
0
25
50
75
100
1.05
-50
125
-25
0
Figure 29
EN INPUT CURRENT
vs
FREE-AIR TEMPERATURE
90
v I
J =10.! V
1= VI(EN)
II
80
/I
C
I
70
C
~:s
60
:;
50
.5
40
(.)
I
/
CI.
I
Iffi
=
V
30
20
-~
10
!---
V
o
-40 -20
0
20
40
60
80
100 120 140
TA - Free-Air Temperature - °C
Figure 31
~TEXAS
3-148
25
50
Figure 30
100
V
75
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
c
V
L
.......
>" 1.06
2
-50
I
1.09
I
III
CD
/
>" 2.02
2.01
V
>
. . .V
2.05
E
:s
E
C
/
2.08
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
100
125
i
TPS7101Q,TPS7133Q,TPS7148Q, TPS7150Q
TPS7101Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
>
VO(nom) - 1-'
I
t
J'"
1
~
'5
V
~
oI
~
TA = 25°C
RL=500Q
Co = 4.71lF (ESR = 1Q)
No Input Capacitance
6
4
::;-
2
t
~
o Iffi
o
-2
20
40
60
80 100 120 140
Time-flS
Figure 32
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE
6~--~----~----~--~-----'
TA = 25°C
PG Pulled Up to 5 V With 5 kQ
::;-
5~---+----~?--'~~~----~
~
t
g
4~---+----~r---+;--~----~
~
3~---+-----H~--++--~----~
~
J
2~---+-----H----~--~----~
I
~ 1~---+----~----+r--~----~
>
Vo - Output Voltage [Vo as a percent of VO(nom)l- %
Figure 33
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-149
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 19115
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
TOTALESR
TOTALESR
VB
OUTPUT CURRENT
va
OUTPUT CURRENT
100
c:
10 _
_
I
II:
ffi
J
I
0.1
o
50 100 150 200 250 300 35It 400 450 500
50 100 150 200 250 300 350 400 450 500
10 - Output Current - mA
10'" Output Current - mA
Figure 35
Figure 34
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
TOTALESR
TOTALESR
va
va
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
c:
I
II:
ffi
~
F
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0.1 0.2 0.3 0.4
Ceramic Capacitance - I1F
Figure 37
Figure 36
~1EXAS
3-150
O.!! 0.6 0.7 0.8 0.9
Ceramic Capacitance - I1F
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TPS71 01 Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILlTYt
TYPICAL REGIONS OF STABILITyt
TOTALESR
TOTALESR
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
Cl
Cl
I
I
II:
UI
II:
ffi
S
W
S
~
~
0.1 '---'---'-........--'--.................- - ' -........--'---'
o 50 100 150 200 250 300 350 400 450 500
0.1
L...-....L..--1_...I.----L._L...-....L..--1_...I.----L.----I
o
50 100 150 200 250 300 350 400 450 500
10 - Output Current - mA
10 - Output Current - mA
Figure 38
Figure 39
TYPICAL REGIONS OF STABILlTYt
TYPICAL REGIONS OF STABILITYt
TOTALESR
TOTALESR
vs·
vs
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
c::
Cl
I
I
II:
ffiw
ffi
S
~
~
0.1 '---'---'_........--'--.................- - ' _........--'---'
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.1 ................- - ' _........--'-_.................- - ' _........--'---'
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Ceramic Capacitance -IlF
Ceramic Capacitance - IlF
Figure 40
Figure 41
t ESR values below 0.1 n are not recommended.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
3-151
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VO.LTAGE REGULATORS
SLVS092C - NOVEMBER 1994:- REVISED AUGUST 1995·
TYPICAL CHARACTERISTICS
To Load
IN
OUT 1---...._---.---+
SENSE
+co·--Bc.
r
t e ·RL
ESR
~-*~~-------*--
t Ceramic capacitor
Figure 42. Test Circuit for Typical Regions of Stability (Figures 39 through 46)
~TEXAS
INSTRUMENTS
3-152
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and fine-pitch
surface-mount packages. Implementation of many of today's high-performance devices in these packages requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat
sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation
limits of a given component.
Three basic approaches for enhancing thermal performance are illustrated in this discussion:
•
•
•
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
Figure 43 is an example of a thermally enhanced PWB layout for the 20-lead TSSOP package. This layout involves
adding copper on the PWB to conduct heat away from the device. The RaJA for this component/board system is
illustrated in Figure 44. The family of curves illustrates the effect of increasing the size of the copper-heat-sink surface
area. The PWB is a standard FR4 board (L x W x H 3.2 inch x 3.2 inch x 0.062 inch); the board traces and heat
sink area are 1-oz (per square foot) copper.
=
Figure 45 shows the thermal resistance for the same system with the addition of a thermally conductive compound
between the body of the TSSOP package and the PWB copper routed directly beneath the device. The thermal
conductivity for the compound used in this analysis is 0.815 W/m . °C.
Using these figures to determine the system RaJA allows the maximum power-dissipation limit to be calculated with
the equation:
.
TJ(max) - T A
PO(max)
= RSJA(system)
Where
TJ(max) is the maximum allowable junction temperature, (i.e., 150°C absolute maximum and
125°C maximum recommended operating temperature for specified operation).
This limit should then be applied to the internal power dissipated by the TPS71xx regulator. The equation for
calculating total internal power dissipation of the TPS71 xx is:
PO(total) = (VI - V O ) . 10
+ VI
. IQ
Because the quiescent current of the TPS71 xx family is very low, the second term is negligible, further simplifying
the equation to:
PO(total) = (VI - V O ) . 10
For a 20-lead TSSOP/FR4 board system with thermally conductive compound between the board and the device·
body, where TA = 55°C, airflow = 100 ft/min, copper heat sink area = 1 cm 2 , the maximum power-dissipation limit can
be calculated. As indicated in Figure 45, the system RaJA is 94°C/W; therefore, the maximum power-dissipation limit
is:
= T J(max)
Po
(max)
- TA
RSJA(system)
= 125°C -
55°C
94°C/W
= 745
mW
If the system implements a TPS7148 regulator where VI = 6 V and 10 = 385 mA, the internal power dissipation is:
,
PO(total)
= (VI
- V O ) . 10
= (6
- 4.85) . 0.385
= 443
mW
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-153
TPS7101Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE· REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
Comparing PO(total) with PO(max) reveals that the power dissipation in this example does not exceed the maximum
limit. When it does, one of two corrective actions can be taken. The power-dissipation limit can be raised by increasing
the airflow or the heat-sink area. Alternatively, the internal power dissipation of the regulator can be lowered by
reducing the input voltage or the load current. In either case, the above calculations should be repeated with the new
system parameters.
r----------------~
1
1
'I
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
L_-i
1 ___ -1
L ________ -.J
Figure 43. Thermally Enhanced PWB Layout (not to scale) for the 20-Pin TSSOP
THERMAL RESISTANCE, JUNCnON-TO-AMBIENT
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
vs
AIRFLOW
AIRFLOW
190r----r----r---~--~----~--~
Component/Board System
2o-Lead TSSOP
I
C
~ 190r---~--~r---~--~----,---~
P
I
.!!
5i
E
:is
J:I
i.
~or
c
~
.
C
:::J
:::J
f
f~
I
J
70r---~----~--~--~----~--~
I
}
ComponentlBoard System
2o-Lead TSSOP
170 Includes Thermally Conductive
Compound Between Body and Board
50~--~----~--~--~----~--~
o
50
100
150
200
250
300
J~ 50c=~Jt:::JE::::t::=3==~~~~
~
0
Air Flow - ft/min
100
150
200
Air Flow - ft/mln
Figure 44
Figure 45
~TEXAS
3-154
50
INSTRUMENTS
POST OFFice BOX 655303 • DALLAS, TeXAS 75265
250
300
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS7101V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
The TPS71 xx series of low-dropout (LDO) regulators is designed to overcome many of the shortcomings of
earlier-generation LDOs, while adding features such as a power-saving shutdown mode and a power-good
indicator. The TPS71 xx family includes three fixed-output voltage regulators: the TPS7133 (3.3 V), the TPS7148
(4.85 V), and the TPS7150 (5 V). The family also offers an adjustable device, the TPS7101 (adjustable from
1.2 V to 9.75 V).
device operation
The TPS71 xx, unlike many other LDOs, features very low quiescent currents that remain virtually constant even
with varying loads. Conventional LDO regulators use a pnp-pass element, the base current of which is directly
proportional to the load current through the regulator (Is = IcI~). Close examination of the data sheets reveals
that those devices are typically specified under near no-load conditions; actual operating currents are much
higher as evidenced by typical quiescent current versus load current curves. The TPS71 xx uses a PMOS
transistor to pass current; because the gate of the PMOS element is voltage driven, operating currents are low
and invariable over the full load range. The TPS71 xx specifications reflect actual performance under load.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in ~ forces an increase in Is to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS71 xx quiescent current remains low even when the regulator drops out, eliminating both problems.
Included in the TPS71xx family is a 4.85-V regulator, the TPS7148. Designed specifically for 5-V cellular
systems, its 4.85-V output, regulated to within ± 2%, allows for operation within the low-end limit of 5-V systems
specified to ± 5% tolerance; therefore, maximum regulated operating lifetime is obtained from a battery pack
before the device drops out, adding crucial talk minutes between charges.
The TPS71 xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to under 2 J.LA. If the
shutdown feature is not used, EN should be tied to ground. Response to an enable transition is quick; regulated
output voltage is reestablished in typically 120 Jls.
minimum load requirements
The TPS71xx family is stable even at zero load; no minimum load is required for operation.
SENSE-pin connection
The SENSE pin of fixed-output devices must be connected to the regulator output for proper functioning of the
regulator. Normally, this connection should be as short as possible; however, the connection can be made near
a critical circuit (remote sense) to improve performance at that point. Internally, SENSE connects to a
high-impedance wide-bandwidth amplifier through a resistor-divider network and noise pickup feeds through
to the regulator output. Routing the SENSE connection to minimize/avoid noise pickup is essential. Adding an
RC network between SENSE and OUT to filter noise is not recommended because it can cause the regulator
to oscillate.
external capacitor requirements
An input capaCitor is not required; however, a ceramic bypass capacitor (0.047 pF to 0.1 JlF) improves load
transient response and noise rejection if the TPS71 xx is located more than a few inches from the power supply.
A higher-capacitance electrolytiC capacitor may be necessary if large(hundreds of milliamps) load transients
with fast rise times are anticipated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-155
TPS71 01 Q, TPS7133Q, TPS7148Q, TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW~DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994- REVISED AUGUST 1995
\
APPLICATION INFORMATION
external capacitor requirements (continued)
As with most LDO regulators, the TPS71 xx family requires an output capacitor for stability. A low-ESR 1O-~F
solid-tantalum capacitor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 46). Adding high-frequency ceramic or film capacitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capacitor is less than 1.2 0 over temperature. Capacitors with published ESR specifications such as the
AVX TPSD106K035R0300 and the Sprague 593D106X0035D2W work well because the maximum ESR at
25°C is 300 mO (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to -40°C). Where component height and/or mounting area is a problem,
physically smaller, 1O-~F devices can be screened for ESA. Figures 34 through 41 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance « 0.2 ~F), the output capacitance can be
reduced to 4.7~F, provided ESR is maintained between 0.7 and 2.5 O. Because minimum capacitor ESR is
seldom if ever specified, it may be necessary to add a 0.5-0 to 1-0 resistor in series with the capacitor and limit
ESR to 1.50 maximum. As show in the ESR graphs (Figures 34 through 41), minimum ESR is not a problem
when using 10-~F or larger output capacitors.
Below is a partial listing of surface-mount capacitors usable with the TPS71 xx family. This information (along
with the ESR graphs, Figures 34 through 41) is included to assist in selection of suitable capacitance for the
user's application. When necessary to achieve low height requirements along with high output current and/or
high ceramic load capacitance, several higher EgR capacitors can be used in parallel to meet the guidelines
above.
All load and temperature conditions with up to 1 ~F of added ceramic load capacitance:
PART NO.
MFR.
T421C226M010AS
593D156X0025D2W
593D106X0035D2W
TPSD106M035R0300
Kemet
Sprague
Sprague
AVX
VALUE
22~F,
MAX ESRt
10V
0.5
0.3
0.3
0.3
15~F,25V
10~F,35V
10~F,35V
SIZE (H x .L x W)t
2.8 x 6 x 3.2
2.8 x 7.3 x 4.3
2.8 x 7.3 x 4.3
2.8 x 7.3 x 4.3
Load < 200 rnA, ceramic load capacitance < 0.2 ~F, full temperature range:
PART NO.
MFR.
592D156X0020R2T
595D156X0025C2T
595D106X0025C2T
293D226X0016D2W
Sprague
Sprague
Sprague
Sprague
VALUE
15 ~F, 20V
MAX ESRt
SIZE (H x L x W)t
1.1
1.2 x 7.2 x 6
2.5 x 7.1 x 3.2
2.5 x 7.1 x 3.2
2.8 x 7.3 x 4.3
15 ~F, 25 V
1
10~F,25V
1.2
22~F,
1.1
16V
Load < 100 rnA, ceramic load capacitance < 0.2 ~F, full temperature range:
t
PART NO.
MFR.
195D106X06R3V2T
195D106X0016X2T
595D156X0016B2T
695D226X0015F2T
695D156XOQ20F2T
695D106X0035G2T
Sprague
Sprague
Sprague
Sprague
Sprague
Sprague
VALUE
MAX ESRt
SIZE (H x L x W)t
1.5
1.5
1.8
1.4
1.5
1.3
1.3 x 3.5 x 2.7
1.3 x 7 x 2.7
1.6 x 3.8 x 2.6
1 .8 x 6.5 x 3.4
1.8 x 6.5 x 3.4
2.5 x 7.6 x 2.5
10 ~F, 6.3 V
10~F, 16V
15~F, 16V
22~F, 15V
15 ~F, 20V
10 ~F, 35 V
Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25°C. Listings are sorted by height.
~TEXAS
3-156
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS71 01 V, TPS7133V, TPS7148V, TPS7150V
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
external capacitor requirements (continued)
TPS71xxPW-20
IN
VI
PG
17
IN
Vo
IN
C1
0.1 j.lF
SOV
6
PG
15
EN
GND
---,
+
I
Co
10j.lF
ESR
I
I
I
---..I
Figure 46. Typical Application Circuit
programming the TPS7101 adjustable LOO regulator
Programming the adjustable regulators is accomplished using an external resistor divider as shown in
Figure 9. The equation goveming the output voltage is:
Vo
= Vref '
(1
+ ~~)
(1)
where
Vref = reference voltage, 1.178 V typ
Resistors R1 and R2 should be chosen for approximately 7-J.IA divider current. A recommended value for R2
is 169 ill with R1 adjusted for the desired output voltage. Smaller resistors can be used, but offer no inherent
advantage and consume more power. Larger values of R1 and R2 should be avoided as leakage currents at
FB will introduce an error. Solving equation 1 for R 1 yields a more useful equation for choosing the appropriate
resistance:
R1 =
(V
0 _ 1) . R2
V ref
(2)
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VI--~----------------'
TPS7101
PG I-~"" Power-Good
IndIcator
IN
>2.7 V
2501<0
O.tj.lF T
-
'--
OUT
- - - - - I EN
<0.4 V
1---....,...---.- Vo
FB..--....
GND
R2
OUTPUT
VOLTAGE
2.5V
3.3V
3.6V
4V
5V
6.4V
Rt
R2
UNIT
191
309
169
169
169
169
169
169
k.O
k.O
348
402
549
750
k.O
kO
k.O
kO
Figure 47. TPS7101 Adjustable LOO Regulator Programming
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-157
TPS7101Q,TPS7133Q,TPS7148Q,TPS7150Q
TPS7101 Y, TPS7133Y, TPS7148Y, TPS7150Y
LOW-DROPOUT VOLTAGE REGULATORS
SLVS092C - NOVEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
power-good indicator
The TPS71 xx features a power-good (PG) output that can be used to monitor the status of the regulator. The
internal comparator monitors the output voltage: when the'output drops to between 92% and 98% of its nominal
regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires a pu"up
resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or as a low-battery
indicator. PG does not assert itself when the regulated output voltage falls outside the specified 2% tolerance,
but instead reports an output voltage low, relative to its nominal regulated value.
regulator protection
The TPS71 xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS71 xx also features internal current limiting and thermal protection. During normal operation, the
TPS71 xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
~TEXAS
INSTRUMENTS
3-158
POST OFFICE BOX 655303. DALLAS. TEXAS 75265
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
PWPPACKAGE
(TOP VIEW)
• Thermally Enhanced Surface-Mount
Package (PWP)
• High-Current (500-mA) LDO Regulator
• Very Low-Dropout Voltage ••• Maximum of
60 mV at 10 = 100 mA
• Extremely Low Sleep-State Current
O.5pAMax
• 2% Output-Voltage Tolerance Over Full
Range of Load, Line, and Temperature
• Output Current Range of 0 mA to 500 mA
• Power Good (PG) Status Output
GND/HEATSINK
GND/HEATSINK
GND
NC
EN
IN
IN
NC
GND/HEATSINK
GND/HEATSINK
20
10
GND/HEATSINK
GND/HEATSINK
NC
NC
PG
SENSE
OUT
OUT
GND/HEATSINK
GND/HEATSINK
19
18
17
5
16
15
14
13
9
12
10
11
NC - No internal connection
description
The TPS7133QPWP is a micropower low-dropout
(LOa) voltage regulator with a fixed 3.3-V output
voltage, rated for loads up to 500 rnA .. The device
is ideal for applications that require 3.3 V from a
5-V supply, or a constant output from a battery,
such as alkaline or lithium ion, that drops off
considerably in voltage as it discharges.
Thermal
Pad
To maximize the advantage of its high-outputcurrent capability, the TPS7133QPWP is now
offered in a new thermally enhanced surfacemount power package. Designed to the same
dimensions as the 20-pin TSSOP (just 1.2 mm
high), the part has an innovative thermal pad,
which, when soldered to the printed-wiring board
(PWB), enables the device to dissipate several
watts of power (see Figure 1 and Thermal
Information section).
Using a PMOS transistor as the pass element
keeps the quiescent current very low and
constant, independent of output loading (typically
270 !lA over the full range of output current, 0 rnA
to 500 rnA). Because the PMOS device also
behaves as a low-value resistor, the dropout is
very low - maximum of 60 mV at 100 rnA. These
two key specifications yield a significant improvement in operating life for battery-powered
systems. The LOa also features a sleep mode;
applying a TTL high signal to EN shuts down the
regulator, reducing the quiescent current to
0.5 !lAo
Figure 1. Bottom View of PWP Package,
Showing the Thermal Pad
0.25
TA
V
=25°C
0.2
>
I
&
1l!
0.15
'S
0.1
~
/
B-
e
Q
0.05
V
oV
o 0.05
/
V
/
/
1/
V
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
10 - Output Current - A
Figure 2. Typical Dropout Voltage Versus
Output Current
PRODUCTION DATA InIormatIon Is _
.. 01 pul>UcaIIon date.
Prod.cIs _ 1 0 apecHlcatlona per tho term. 01 Ttxu InstnlllllnlS
slsndanl wansnly. Prod.eIIon processing _ not nscessarIly Inckld.
tesllng 01011 po_ro.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-159
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995- REVISED AUGUST 1995
AVAILABLE OPTIONSt
OUTPUT VOLTAGE
(V)
PACKAGED DEVICES
TJ
MIN
TVP
CHIP FORM
THERMALLY-ENHANCED TSSOP
(PWP)
MAX
(Y)
-55°C to 150°C
3.23·· ·3.3
3.37
TPS7133QPWPPWPLE
TPS7133Y
t The PWP package IS only available left-end taped and reeled (indicated by the LE suffix on the device Iype; e.g."
TPS7133QPWPLE). The chip form is tested at 25OC.
TPS7133QPWP
VI
6
-,--'---1 IN
7
IN
PG
SENSE
16
PO
15
OUT
0.1 IlF
5
EN
OUT
GND
3
Vo
r
I
I
I
I
I
L
---.,I
cot
+
10llF
ESR
I
I
_ _ _ oJI
t Capacitor selection is nontrivial. See application information section
for details.
Figure 3. Typical Application Configuration
functional block diagram
IN
----~-
__---+-e_~~---__,
PG
I--~e--
OUT
SENSE§
420kn
233kn
GND
Resistors are nominal values only.
:t: Switch positions shown with EN active low.
.
§ For most applications, SENSE should be extemally connected to OUT as cioseas possible to the
device. For other implementations, refer to SENSE-pin connection discussion in applications
information section.
~TEXAS
3-160
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
TPS7133QPWP, TPS7133Y
MICRO POWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS10l A- FEBRUARY 1995 - REVISED AUGUST 1995
TPS7133Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS7133QPWP. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
-=
~
~
~
l'l'l'l'l'l'j'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
GNDIHEATSINK
GNDP .EATSINK
GND
EN
IN
IN
GNDIHEATSINK
GND/HEATSINK
(1)
(20)
(2)
(19)
(3)
(16)
(15)
(5)
(6)
(7)
TPS7133Y
(14)
(13)
(9)
(12)
(10)
(11)
GNDIHEATSINK
GNDIHEATSINK
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4
PG
TJmax
SENSE
x 4 MILS MINIMUM
=150°C
TOLERANCES ARE ±1 0%
OUT
ALL DIMENSIONS ARE IN MILS
OUT
GNDlHEATSINK
TERMINALS 4, 8, 17, AND 18 ARE
NOT CONNECTED
GNDIHEATSINK
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-161
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
I
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Input voltage range:!:, VI, PG, SENSE, EN .............................. ~ ............... -0.3 to 10 V
Output current, 10 .................................................. '. . . . . . . . . . . . . . . . . . . . . . . . .. 2 A
Continuous total power dissipation ......................... . . .. See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, TJ .................................... -55°C to 150°C
Storage temperature range, Tstg ........ ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -65°C to 150°C
Lead temperature 1~6,mm (1/1,6 inch) from case for 10 seconds .............. , ................ 260°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanentdamage to the device. These are stress ratings only, and
functional operation of the device at th\1se Or any other conditions beyond those indtcated under "reCommended operating conditions' is not
implied. Exposure to absolute-maximum-rated cOnditions for extended periods may alfect device reliability.
:I: All voltage values are with respect 10 network terminal ground.
"
DiSSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Figure 4)§
PACKAGE
TA,,25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
. TA=70°C
POWER RATING
TA=125°C
POWER RATING
PWP
700mW
5.6mW/oC
448mW
140mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Figure 5)§
PACKAGE
TC,,62.5°C
POWER RATING
DERATING FACTOR
ABOVE TC = 62.5°C
TC=70°C
POWER RATING
TC=125°C
POWER RATING
PWP
25W
285.7mW/oC
22.9W
7.1W
MAXIMUM CONTINUOUS DISSIPATION§
vs
FRE.E-AIR TEMPERATURE
:=e
I
800
30
700
I"ii
600
is
500
"k
0
'c"
~
400
(.)
300
0
e
e'"
.
>C
::E
I
rP
/
RaJA = 178°C/W
"
100
25
5Q
i
25
is..
'c0"
20
"ii
200
o
."
:=I
I
'"
c
·0
.
..'"
MAXIMUM CONTINUOUS DISSIPATION§
vs
CASE TEMPERATURE
""
75
'"
~
e
e'"
"-
100
"
I
K.
125
I
'"
10
r
5
C
a..
150
'"
~"pa~
(.)
TA - Free-Air Temperature - °C
Figure 4
15
0
Measured with the exposed thermal
coupled to an Infinite heat sink with a
thermally conductive compound (the
thermal conductivity of the compound
~
Is 0.815 W/m . °C). The ReJC Is 3.5°CIW.
o
25
50
75
100
125
TC - Case Temperature - °C
FigureS
'"
150
§ Dissipation rating tables and figures are provided for maintenance of ji.mction temperature at or below absolute maximum temperature of 150°C.
For guidelines on maintaining junction temperature within recommended operating range, see the Thennal Information section.
~ThxAs
INSTRUMENTS
3-162
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101 A- FEBRUARY 1995 - REVISED AUGUST 1995
recommended operating conditions
Input voltage, VIt
High-level input voltage at EN, VIH
MIN
MAX
3.77
10
2
Operating virtual junction temperature range, T J
t
V
V
Low-level input voltage at EN, VIL
Output current range, 10
UNIT
0.5
V
0
500
mA
-40
125
°C
Minimum input voltage defined in the recommended operating conditions is the maximum specified output voltage plus dropout voltage VOO:j:
at the maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads.
To calculate the minimum input voltage for your maximum output current, use the following equation:
VI(min) = VO(max)
+ VOO(maxload)
:j: This symbol is not currently listed within EIA or JEDEC standards for semiconductor symbology.
electrical characteristics at 10 = 10 rnA, EN = 0 V, Co = 4.7 ~F/ESR* = 1 n, SENSE shorted to OUT
(unless otherwise noted)
PARAMETER
TPS7133QPWP
TEST CONDITIONSIi
Ground current (active mode)
EN s; 0.5 V,
Os; 10 s; 500 mA
VI=VO+ 1 V,
Input current (standby mode)
EN=VI,
2.7VS;VIS;10V
Output current limit
VO=O,
VI = 10 V
Pass-element leakage current in
standby mode
EN = VI,
2.7VS;VIS;10V
PG leakage current
Normal operation,
VPG=10V
TJ
MIN
25°C
285
25°C
0.5
-40°C to 125°C
2
25°C
1.2
-40°C to 125°C
0.5
1
-40°C to 125°C
25°C
0.02
0.5
0.5
-40°C to 125°C
61
75
165
6VS;VIS;10V
2.7VS;VIS;10V
40°C to 125°C
25°C
0.5
0.5
0S;VIS;10V
-0.5
-40°C to 125°C
-0.5
25°C
MinimumVI for active pass element
0.5
0.5
2.05
-40°C to 125°C
IpG = 300
r.tA
25°C
-40°C to 125°C
r.tA
A
r.tA
r.tA
ppm/DC
2.5
2.5
1.06
V
mV
50
25°C
r.tA
V
2.7
25°C
UNIT
°C
2
'-40°C to 125°C
EN hysteresis voltage
Minimum VI for valid PG
2
2
-40°C to 125°C
2.5VS;VIS;6V
EN input current
350
460
Thermal shutdown junction temperature
EN logic low (active mode)
MAX
-40°C to 125°C
25°C
Output voltage temperature coefficient
EN logic high (standby mode)
TYP
1.5
1.9
r.tA
V
V
§ ESR refers to the eqUivalent senes reSistance, Including Internal and external resistance.
~ Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
3--163
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
=
=
electrical characteristics at 10 10 rnA, VI 4.3 V, EN
to OUT (unless otherwise noted)
PARAMETER
Output voltage
=0 V, Co =4.7 ~FIESRt = 1 0, SENSE shorted
VI =4.3V,
,5 mA,,; 10,,;500 mA
VI = 3.23 V
10= 100 mA,
VI = 3.23 V
10 =500 mA,
VI =3.23 V
Pass-element series resistance
(3.23 V:... VOlIIO,
10 = 500 mA
VI = 3.23 V,
Input voltage regulation
VI = 4.3 Vto 10 V,
50 IiA ,,; 10 ,,; 500 mA
10 = 5 mA to 500 mA, 4.3V,,;VI,,;10V
Output voltage regulation
10 =50 IiAt0500 mA, 4.3 V,,; VI ,,; 10V
10 = 50 IiA
Ripple rejection
f.= 120 Hz
10 = 500 mA
Output noise-spectral density
Output noise voltage
PG trip-threshold voltage
TJ
lo=10mA
4.3V,,;Vp;;10V,
10=10mA,
Dropout voltage
TPS7133QPWP
TEST CONOmONst'
25°C
0.02
6
47
60
-40°C to 125°C
80
25°C
235
_40°C to 125°C
mV
300
0.47
0.6
-40°C to 125°C
0.8
25°C
20
-40°C to 125°C
27
21
25°C
-40°C to 125°C
38
75
25°C
30
-40°C to 125°C
60
120
25°C
43
-40°C to 125°C
40
25°C
39
-40°C to 125°C
36
n
mV
mV
mV
54
dB
49
2
25°C
274
CO= IO I1F
25°C
228
CO= 100l1F
25°C
159
0.92 x
VO(nom)
!lV/1Hz
I1Vrms
0.98 x
VO(nom)
25°C
35
25°C
0.22
-40°C to 125°C
V
400
25°C
-40°C to 125°C
UNIT
8
25°C
Co =4.7 I1F
VI =2.8V
MAX
3.37
25°C
Vo voltage decreasing from above VPG
IPG";1 mA;
3.23
-40°C to 125°C
PG hysteresis voltage
P\3 output low voltage
TYP
3.3
25°C
-40°C to 125°C
f=120Hz
10 Hz,,;f,,; 100kHz,
ESRt= 1 n
MIN
V
mV
0.4
0.4
V
t ESR refers to the equivalent series resistance, including internal and external resistance.
:t: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
3-164
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS7133QPWP, TPS7133V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVSl 01A- FEBRUARY 1995 - REVISED AUGUST 1995
electrical characteristics at 10 = 10 rnA, EN = 0 V, Co =4.7 ~F/ESR* = 1 n, TJ = 25°C, SENSE shorted
to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS!!
Ground current (active mode)
ENSO.5V,
OS 10 S 500 mA
V,=VO+ 1 V,
Output current limit
VO=O,
V, = 10 V
PG leakage current
Normal operation,
VPG= 10V
TPS7133Y
MIN
TYP
MAX
IlA
285
1.2
A
IlA
0.02
Thermal shutdown junction temperature
EN hysteresis voltage
165
°C
50
mV
2.05
Minimum V, for active pass element
UNIT
V
Minimum V, for valid PG
1.06
V
IPG = 300 IlA
§ ESR relers to the equivalent series resistance, including internal and external resistance.
11 Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken, into account separately..
electrical characteristics at 10 = 10 rnA, VI = 4.3 V, EN = 0 V, Co = 4.7 ~F/ESRt = 1 n, TJ = 25°C, SENSE
shorted to OUT (unless otherwise noted)
TEST CONDITIONS;
PARAMETER
Output voltage
Dropout voltage
Pass-element series resistance
Output voltage regulation
10= 10mA
3.3
10= 10mA,
V, = 3.23 V
0.02
10= 100mA,
V, = 3.23 V
47
'0 =500 mA,
V, =3.23 V
235
(3.23 V - VO)/lO,
'O=500mA
V, = 3.23 V,
0.47
MAX
UNIT
V
mV
Q
10 = 5 mA to 500 mA, 4.3 V S V, S 10 V
21
mV
10 = 50llAt0500mA, 4.3VSV,Sl0V
30
mV
1=120Hz
Output noise-spectral density
1= 120Hz
10HzSIS100kHz,
ESRt=lQ
10= 50 IlA
54
10 = 500 mA
49
CO=4.7IlF
274
CO= 10llF
228
CO= l00IlF
159
2
PG hysteresis voltage
PG output low voltage
TYP
V, =4.3V,
Ripple rejection
Output noise voltage
TPS7133Y
MIN
35
'pG=l rnA,
V, =2.8V
0.22
dB
IlVNHz
I1Vrms
mV
V
t ESR relers to the equivalent senes resistance, including Intemal and extemal resistance.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
3-165
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
$LVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
vs Input voltage
IQ
Quiescent current
VOO'
,WOO
Typical dropout voltage
vs Output current
Change in dropout voltage
vs Free-air temperature
!NO
Change in output voltage
vs Free-air temperature
Vo
Output voltage
vs Input voltage
INO
Change in output voltage
vs Input voltage
Vo
Output voltage
vs Output current
Ripple rejection
vs Frequency
Output special noise density
vi; Frequency
rOS(on)
R
Pass-element resistance
vs Input voltage
Divider resistance
vs Free-air temperature
IllSENSEt
SENSE pin current
vs Free-air temperature
vs Free-air temperature
VI
II (EN)
I Minimum input voltage (active-pass element)
vs Free-air temperature
I Minimum input voltage (valid PG)
vs Free-air temperature
vs Free-air temperature
EN Input current
Output voltage response from Enable (EN)
VPG
Power-goOd (PG) voltage
vs Output voltage
Total ESR
vs Output current
Total ESR
vs Added ceramic capacitance
Total ESR
vs Output current
Total ESR
vs Added ceramic capacitance
-!!1 TEXAS
3-166
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
vs
OUTPUT CURRENT
355
T~=25~C
345
~
""
335 f- VI=10V
'E
~
325
U
315
:;.
I
::I
'ECD
..
u
- -
-
r--
400
'E
~
9
285
'ECD
I
200
/
IJ
u
OJ
150
::I
a
I
9
275
100
VI=4.3V
o
I II
50
~
o
o
50 100 150 200 250 300 350 400 450 500
2
3
4
QUIESCENT CURRENT
vs
FREE-AIR TEMPERATURE
0.3
I
I
,/'
:;.
I
U
250
::I
I
9
200
150
-50
>
I
/
300
::I
a
/
V
./
0.2
CD
aI
~
,/
~
"$
0.15
0
Q.
e
Q
0.1
V
0.05
lL'
-25
9
10
I
0.25
./
""
.91
8
TA = 25°C
350
..
7
DROPOUT VOLTAGE
vs
OUTPUT CURRENT
vl=4.3V
10 = 10 mA
'ECD
6
Figure 7
Figure 6
'E
~
5
VI - Input Voltage - V
10 - Output Current - mA
400
,/"
,/"
V
/
I
::I
U
I
265
..,.V
250
.91
295
...".
300
:;.
I
305
a
TA = 25°C
RL=10n
350
""
.91
::I
QUIESCENT CURRENT
vs
INPUT VOLTAGE
0
25
50
75
100
TA - Free-Air Temperature - °C
125
o
o
V
/
V
V
V
/
/
1/
50 100 150 200 250 300 350 400 450 500
FigureS
10 - Output Current - mA
Figure 9
~TEXAS·
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-167
TPS7133QPWP, TPS7133Y
MICROPOWERLOW-OROPOUT (LOO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
10
,10 =100mA
8
~
6
I'"
4
';'
2
0
0
:;
a.
e
Q
.5
&
c
!0
I
-6
/
-8
-10
-50
~
5
0
0
:;
a.
:;
.
.,c
-5
0
-10
01
~
/
/
-15
<1
0
25
50
75
100
TA - Free-Air Temperature - °C
~
:/
,c
I
/'
V
,/
.5
V
-25
,/
10
'"01
!
/V
-4
VI=4.3'V
10=10mA
E
1/
/
15
>
V
-2
20
/'
/
I
~
/
CHANGE IN OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
-20
-50
125
-25
0
25
50
75
100
125
TA - Free-Air Temperature - °C
Figure 10
Figure 11
CHANGE IN OUTPUT VOLTAGE
vs
INPUT VOLTAGE
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
20
4
TA=25°C
RL=100
TA=25°C
RL=100
15
>
E
>
3
I
:;
2
10
J
/
&
!
~
I
II
~
5
i
o
o
~
0
.5
'"
-5
O
-10
J
I
~
/
V-- r-
"
'0
~
o
o
-15
-20
2
3
4
5
6
7
8
9
10
4
5
VI-Input Voltage - V
Figure 12
7
6
8
VI - Input VoHage - V
Figure 13
~TEXAS
3-168
--... ~
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
10
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
RIPPLE REJECTION
OUTPUT VOLTAGE
3.34
va
va
OUTPUT CURRENT
FREQUENCY
70
I
TA=2SoC
>
3.32
J
3.31
I
3.3
.~
I
40
t
30
i
20
c
____VI=lOV
l
,~
3.29
3.28
10
3.27
0
o
100
300
200
TA = 25°C
VI=4.3V
Co =4.7 J.1F (ESR = 10)
No Input Capacitance
Figure 14
,
~
va
FREQUENCY
INPUT VOLTAGE
..
~
c
,
~/"
11111111
I
111111
CO=10 I1F(ESR=1 0)
•
I III
~
::
'0
z
0.1
i
I
8
c
Ia:
100
'EGI
0.8
0.6
..
O.S
'"
t--...
P
'" 10=5OOmA
0.7
E
dic 0.01
10
TA=2SoC
VI(SENSE) = 3.14 V
CI
Co =4.7 I1F (ESR = 1 0)
1111
Co = 100 I1F (ESR = 1 0)
&
10M
1.1
TA=2SoC
No Input CapacItance
VI=4.3V
II
1M
PASS-ELEMENT RESISTANCE
va
10
I
lOOk
Figure 15
OUTPUT SPECTRAL NOISE DENSITY
c
II
~
f - Frequency - Hz
10 - Output Currant - mA
~>
IIiU J.l.
'I1Il~LI=1100
\l
-10 111111111 111111111 I I III liB
100
1k
10k
10
500
400
~W~~l~~\
RL=5000
~
.~
3.26
-
I-
'1:1
-,
;;
SO !!
ID
I
J
'S
f
0
III+WIII
60
3.33
0.3
::--....
0.2
0.1
10 k
lOOk
2
3
f - Frequency - Hz
Figure 16
4
S
6
7
8
VI- Input Voltage - V
9
10
Figure 17
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TPS7133QPWP, TPS7133Y
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SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
DIVIDER RESISTANCE
vs
FREE-AIR TEMPERATURE
0.9
I
I
SENSE PIN CURRENT
vs
FREE-AIR TEMPERATURE
6
I
VI=4.3V
VI(sense) = VO(nom)
c::
5.8
0.8
CC
0.7
C
~::I
I
I
~
"'- r---....
~
iii
GI
II:
Iii
0.6
'tI
~
5.6
c
it
~ f"-..
:c
- 1--
5.2
r1I
5
m-Ol
I
II:
c
4.6
-25
0
25
50
75
100
/
4.8
~
0.5
0.4
-50
V
5.4
(,)
V
V
::I.
::E
IIIc
VI=4.3V
VI(sense) = VO(nom)
1/
V
V
I
I
4.4
125
-50
-25
TA - Free-Air Temperature - °C
0
25
50
75
100
125
TA - Free-Air Temperature - °C
Figure 18
Figure 19
MINIMUM INPUT VOLTAGE
(ACTIVE PASS ELEMENT)
vs
FREE-AIR TEMPERATURE
MINIMUM INPU1 VOLTAGE
(VALID PG)
vs
FREE-AIR TEMPERATURE
1.1
2.1
RL=5OOQ
2.09
>I
GI
DI
!
$!
'S
Q.
.5
E
::I
E
C
/'
2.08
2.07
2.06
2.05
V
2.04
L
I$!
2.02
,/
'SQ.
E
::I
E
·c
1.07
I
->
I'
-25
V
1.08
:i
2
-50
)
1.09
.5
/
I
2.01
V
I
GI
1/
!ii 2.Q3
->
. . .V
./
>
0
25
50
75
100
125
./
1.06
1.05
-50
-250
25
V
50
V
75
TA - Free-Air Temperature - °C
TA - Free-Air Temperature - °C
Figure 20
Figure 21
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V
L
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100
125
TPS7133QPWP, TPS7133V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVSl 01A - FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
EN INPUT CURRENT
vs
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
FREE-AIR TEMPERATURE
100
90
>
Jl
VI = VI(EN) = 10 V
I
I
~
u=
'5
D.
.5
I
Iffi'
::
70
60
50
40
10
o
-40 -20
I
-?
-
~
i--""'"
"'"
TA=25°C
RL=5000
Co = 4.71!F (ESR = 10)
No Input Capacitance
II
30
20
~
o
I
/
1-.
/
V
~
'5
I
ct.
1:
t
I
80
c
VO(nom)
I
6
/
o
0
20 40 60 80 100 120 140
TA - Free-Air Temperature - °C
-2
20
40
60
80 100 120 140
Tlme-I!s
Figure 22
Figure 23
POWER-GOOD (PG) VOLTAGE
vs
OUTPUT VOLTAGE
4r---~----~----~----'-----'
TA=25°C
PG Pulled Up to 3.3 V With 3.3 kQ
>
I
&
:!l!
3
1----f---++---+I--+-----1
2
1----I----+t---++--+-----1
~
~
'8
o
'l
I
I
~
>
Vo - Output Voltage (VO as a Percent of VO(nom» - %
Figure 24
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TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LOO) VOLTAGE REGULATORS
SlVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
100
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF. STABILITY
TOTALESR
TOTALESR
vs
vs
·OUTPUT CURRENT
OUTPUT CURRENT
100plIIIIill!!lIJI!I!iI_ __
V... 4.3 V
No Input Capacitance
Co =4.7 I1F
No Added Ceramic Capacitance
TA=25°C
VI=4.3V
No Input Capacitance
Co = 4.711F + 0.511F of
Ceramic Capacitance
TA = 25°C
CI
CI
I
I
m
m
J
J
50 100 150 200 250 300 350 400 450 500
50 100 150 200 250 300 350 400 450 500
10 - Output Currant - mA
10 - Output Current - mA
Figure 25
Figure 26
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
TOTALESR
TOTALESR
vs
vs
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
100p~~
_ __
100plIIIIill!!~
VI=4.3V
No Input CapaCitance
lo=100mA
Co = 4.7 I1F
TA=25°C
_ __
VI=4.3V
No Input Capacitance
10=500mA
Co = 4.7 I1F
TA = 25°C
CI
I
m
J
0.1
o
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
0~1
o
Added Caramic Capacitance -I1F
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Added Ceramic Capacitance -I1F
Figure 28
Figure 27
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TPS7133QPWP, TPS7133V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS1 01A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILlTYt
TOTALESR
TYPICAL REGIONS OF STABILlTYt
TOTAL ESR
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
100~--~~--------~
VI =4.3V
No Input Capacitance
Co = 10 j!F + O.Sj!Fof
Added Ceramic Capacitance
TA=2SoC
VI=4.3V
No Input Capacitance
CO=10j!F
No Ceramic Capacitance
TA 25°C
=
+--+-+--+---1
0.1 '-----'-_'--....L..---''---'---'_-'---'-_...l.---J
o SO 100 1S0 200 2S0 300 3S0 400 4S0 SOO
0.1
L-....l-_L......-L----IL.........J....---I_...J.....---I_...I.........J
o
SO 100 1S0 200 2S0 300 3S0 400 4S0 SOO
10 - Output Current - mA
10 - Output Current - mA
Figure 29
Figure 30
TYPICAL REGIONS OF STABILITvt
TOTALESR
TYPICAL REGIONS OF STABILl'rvt
TOTALESR
vs
vs
ADDED CERAMIC CAPACITANCE
ADDED CERAMIC CAPACITANCE
100 ......."""""................_
VI=4.3V
NolnputCapacHance
CO=10j!F
10=SOOmA
TA=2SoC
100p~~...","",,,,",,,"'""'9
VI=4.3V
No Input Capacitance
CO= 10j!F
IO=100mA
TA=2SoC
a
a
I
I
II:
III
II:
:3
W
!
!
~
~
0.1 '----'-_'--....L..---''---'---'_-'---'-_...l.---J
o 0.1 0.2 0.3 0.4 O.S 0.6 0.7 0.8 0.9 1
0.1 '---....L..---''---'---'_-'---'_-'---'-_...l.---J
o 0.1 0.2 0.3 0.4 O.S 0.6 0.7 0.8 0.9 1
Added Ceramic capacitance - j!F
Added Ceramic Capacitance - j!F
Figure 31
t
Figure 32
ESR values below 0.1 Q are not recommended.
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TPS7133QPWP, TPS7133Y
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SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
To Load
IN
OUT~-'~'----~B
SENSE
~~~__~
+ Co
ct .
ESR
RL
'
t Ceramic capacitor
Figure 33. Test Circuit for Typical Regions of Stability (Figures 25 through 32)
THERMAL.INFORMATION
The thermally enhanced PWP package is based on the 20-pin TSSOP, but includes a thermal pad [see Figure 34(c)]
to provide an effective thermal contact between the Ie and the PWB.
Traditionally, surface mount and power have been mutually exclusive terms. A variety of scaled-down T0220-type
packages have leads formed as gull wings to make them applicable for surface-mount applications. These packages,
however, suffer from several shortcomings: they do not address the very low profile requirements «2 mm) of many
of today's advanced systems, and they do not offer a pin-count high enough to accommodate increasing integration.
On the other hand, traditional low-power surface-mount packages require power-dissipation derating that severely
limits the usable range of many high-performance analog circuits.
The PWP package (thermally enhanced TSSOP) combines fine-pitch surface-mount technology with thermal
performance comparable to much larger power packages.
The PWP package is,designed to optimize the heat transfer to the PWB. Because of the very small size and limited
mass of a TSSOP package, thermal enhancement is achieved by improving the thermal conduction paths that remove
heat from the component. The,thermal pad is formed using a lead-frame design (patent pending) and manufacturing
technique to provide the user with direct connection to the heat-generating IC. When this pad is soldered or otherwise
coupled to an external heat dissipator, high power dissip~tion in the ultrathin, fine-pitch, surface-mount package can
be reliably achieved.
Side View (a)
Thermal
Pad
End View (b)
Bottom View (e)
Figure 34. Views of Thermally Enhanced PWP Package
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TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS1 01A- FEBRUARY 1995 - REVISED AUGUST 1995
THERMAL INFORMATION
Because the conduction path has been enhanced, power-dissipation capability is determined by the thermal
considerations In the PWB design. For example, simply adding a localized copper plane (heat-sink surface), which
is coupled to the thermal pad, enables the PWP package to dissipate 2.5 W in free air (reference Figure 36(a), 8 cm 2
of Cu heat sink and natural convection). Increasing the heat-sink size increases the power dissipation range for the
component. The power dissipation limit can be further improved by adding airflow to a PWB/IC assembly (see
Figures 35 and 36). The line drawn at 0.3 cm 2 in Figures 35 and 36 indicates performance at the minimum
recommended heat-sink size, illustrated in Figure 38.
The thermal pad is directly connected to the substrate ofthe IC, which forthe TPS7133QPWP is a secondary electrical
connection to device ground. The heat-sink surface that is added to the PWB can be a ground plane or left electrically
isolated. In other T0220-type surface-mount packages, the thermal connection is also the primary electrical
connection for a given terminal which is not always ground. The PWP package provides up to 12 independent leads
that can be used as inputs and outputs (Note: leads 1, 2, 9,10,11,12,19, and 20 are internally connected to the
thermal pad and the Ie substrate).
THERMAL RESISTANCE
vs
COPPER HEAT-SINK AREA
150~--'---~----~---r--~r---~--~---'
125
Natural Convection
--I----+----+----t-----1
100~...~-=
50~~~~
II I
300 ftlmin
00.3
1
2
3
4
5
6
7
8
Copper Heat-Sink Area - cm2
Figure 35
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SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
THERMAL INFORMATION
3.5,....,....----,..--........-r---'---.,.----...,
3.5
r"T"-----r---.....----.,.------,
=
TA 55°C
3·1-+-:----t----+----~--__1
3rr-----r~----~~---+--~~
2.5 rr---+-:.-c---:;;;;...t"''-----r------::::...I
2rr-~~~--~~--~--_1
1.51--b'F-----:>""F----+----~--_1
0.51-+----+---+----+-----/
°0~--~2---~4~--~6---~8
0.3
°0~--~2---~4~--~6---~8
0.3
Copper Heat-Sink Size - cm2
Copper Heat-Sink Size - cm2
(a)
(b)
3.5
TA =105°C
-
3
==I
~
2.5
...i
2
:::i
c
.;;
is
;
1.5
-
150 ft/min
300ft/min
~
~~
~
I
C
A-
0.5
~
~
Natural Convection
~V'
o
o
0.3
2
4
6
Copper Heat-5ink Size - cm2
8
(c)
Figure 36. Power Ratings of the PWP Package at Ambient Temperatures of 25°C, 55°C, and 105°C
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TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
THERMAL INFORMATION
Figure 37 is an example of a thermally enhanced PWB layout for use with the new PWP package. This board
configuration was used in the thermal experiments that generated the power ratings shown in Figures 35 and 36. As
discussed earlier, copper has been added on the PWB to conduct heat away from the device. RaJA for this assembly
is illustrated in Figure 35 as a function of heat-sink area. A family of curves is included to illustrate the effect of airflow
introduced into the system.
1----------------Heal-Sink Area
lozCopper
Board thickness
Board size
Board malerial
Cu trace/heat sink
Exposed pad mounting
I
I
I
I
L----.;_j
62 mils
3.2 in. x 3.2 in.
FR4
1 02
63167 tinllead solder
I ___ ~
L ________ ..J
Figure 37. PWB Layout (Including Cu Heatsink Area) for Thermally Enhanced PWP Package
From Figure 35, RaJA for a PWB assembly can be determined and used to calculate the maximum power-dissipation
limit for the componentlPWB assembly, with the equation:
TJmax - TA
po(max) = RSJA(system)
Where
T Jmax is the maximum specified junction temperature (150°C absolute maximum limit, 125°C recommended
operating limit) and TA is the ambient temperature.
Po (max) should then be applied to the internal power dissipated by the TPS7133QPWP regulator. The equation for
calculating total internal power dissipation of the TPS7133QPWP is:
PO(total) =
(V, - VO ) . '0 + V, . IQ
Since the quiescent current of the TPS7133QPWP is very low, the second term is negligible, further simplifying the
equation to:
.
PO(total)
= (V,
- Vo) . '0
=
=
=
For the case where TA 55°C, airflow 200 ft/min, copper heat-sink area 4 cm 2, the maximum power-dissipation
limit can be calculated. First, from Figure 35, we find the system RaJA is 50°C/W; therefore, the maximum
power-dissipation limit is:
.
TJmax - T A
125°C - 55°C
PO(max) = R
=
50 0 CjW
= 1.4 W
8JA(system)
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TPS7133QPWP, TPS7133Y
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SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
If the system implements a TPS7133QPWP regulator, where VI
is:
PO(total) = (VI - V
o) . 10= (6 -
=6 V and 10 =500 rnA, the internal power dissipation
3.3) . 0.5 = 1.35 W
Comparing PO(total) with PO(max) reveals that the power dissipation in this example does not exceed the calculated
limit. When it does, onecf two corrective actions should be made: raising the power-dissipation limit by increasing
the airflow or the heat-sink area, or lowering the internal power dissipation of the regulator by reducing the input
voltage orthe load current. In either case, the above Calculations should be repeated with the new system parameters.
mounting information
Since the thermal pad is not a primary connection for an electrical Signal, the importance of the electrical
connection is not significant. The primary requirement is to complete the thermal contact between the thermal
pad and the PWB metal. The thermal pad is a solderable surface and is fully intended to be soldered at the time
the component is mounted. Although voiding in the thermal-pad solder-connection is not deSirable, up to 50%
voiding is acceptable. The data included in Figures 35 and 36 is for soldered connections with voiding between
20% and 50%. The thermal analysis shows no significant difference resulting from the variation in voiding
percentage.
Figure 38 shows the solder-mask land pattern for
the PWP package. The minimum recommended
heat-sink area is also illustrated. This is simply a
copper plane under the body extent of the
package, including metal routed under terminals
1, 2, 9, 10, 11, 12;19, and 20.
Minimum Recommended
Heat-Slnk Area
0.27 mm
L..-_--,
~---d::-J
~-------r-
reliability information
This section includes demonstrated reliability test
results obtained from the qualification program.
Accelerated tests are performed at high-stress
conditions so that product reliability can be
established during a relatively short test duration.
Specific stress conditions are chosen to represent
accelerated versions of various deviceapplication environments and allow meaningful
extrapolation to normal operating conditions.
Location of Exposed
Thermal Pad on
PWPPackage
-,----cp
-f--CP
0.65mm
c:p
cp
r---
I
I
I
I
I
I
IL
-,
I
I
I
I
I
I
_ _ _ _ _ .JI
ct:::J
r
1'1.2mm
cP
c:p
c:::p
9
c:±:J
5.72mm
Figure 38. PWP Package Land Pattern
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SLVS10l A- FEBRUARY 1995 - REVISED AUGUST 1995
THERMAL INFORMATION
component level. reliability test results
preconditioning
Preconditioning of components prior to reliability testing is employed to simulate the actual board assembly
process used by the customer. This ensures that reliability test results are more representative of those that
would be seen in the final application. The general form of the preconditioning sequence includes a moisture
soak followed by multiple vapor-phase-reflow or infrared-reflow solder exposures. All components used in the
following reliability tests were preconditioned in accordance with JEDEC Test Method A113 for Level 1 (not
moisture-sensitive) products.
high-temperature life test
High-temperature life testing is used to demonstrate long-term reliability of the product under bias. The potential
failure mechanisms evaluated with this stress are those associated with dielectric integrity and design or
process sensitivity to mobile-ion phenomena. Components are tested at an elevated ambient temperature of
155°C for an extended period. Results are derated using the Arrhenius equation to an equivalent number of unit
hours at a representative application temperature. The corresponding predicted failure rate is expressed in FITs,
or failures per billion device-hours. The failure rate shown in this case is data-limited since no actual failures
were experienced during qualification testing.
PREDICTED LONG-TERM FAILURE RATE
Number of Units
325
I Equivalent Unit Hours at 55°C and 0.7 eV I FITs at 50% CL
I
I
24,468,090
36.2
biased humidity test
Biased humidity testing is used to evaluate the effects of moisture penetration on plastic-encapsulated devices
under bias. This.stress verifies the integrity of the package construction and the die passivation system. The
primary potential failure mechanism is electrolytic corrosion. Components are biased in a low power state to
reduce heat dissipation and are subjected to a 120°C, 85%-relative-humidity environment for 100 hours.
BIASED HUMIDITY TEST RESULTS
Equivalent Unit Hours at 85°C and 85% RH
357,000
I
I
Failures
0
autoclave test
The autoclave stress is used to assess the capabilities of the die and paqkage construction materials. with
respect to moisture ingress and exten,ded exposure. Predominant failure mechanisms include leakage currents
that result from internal moisture accumulation and galvanic corrosion resulting from reactions with any present
ionic contaminants. Components are subjected to a 121°C, 15 PSIG, 1OO%-relative-humidity environment for
240 hours.
AUTOCLAVE TEST RESULTS
Total Unit Hours
I
Failures
54,720
I
0
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THERMAL INFORMATION
thermal shock test
Thermal shock testing is used to evaluate the capability of the component to withstand mechanical stress
resulting from differences in thermal coefficients of expansion among the die and package construction
materials. Failure mechanisms are typically related to physical damage at interface locations between different
materials. Components are cyCled between -65°Gand 150°C in liquid mediums for a total duration of 1000
cycles.
'.
THERMAL SHOCK TEST RESULTS
, Failures
Total Unit Cycles
I
345,000
0
PWB assembly level reliability results
temperature cycle test
Temperature cycle testing of the PWB assembly is used to evaluate the capability of the assembly to withstand
mechanipal stress resulting from the differences in thermal coefficients of expansion among die, package, and
PWB board materials. This testing is also used to sufficiently age the soldered thermal connection between the
thermal pad and the Cu trace on the FR4 board and evaluate the degradation of the thermal resistance for a
board-mounted test unit. The assemblies were cycled betweentemperature extremes of-40°C and 125°C for
a total duration of 730 cycles.
TEMPERATURE CYCLE TEST RESULTS
Total Unit Cycles ,
36,500
I
Failures
0
, Average Change in RaJA(system)
I
-0.41%
solderability test
Solderability testing is used to simulate actual board-mount performance in a reflow process.
Solderability testing is conducted as follows: The test devices are first steam-aged for 8 hours. A stencil is used
to apply a solder-paste terminal pattern on a ceramic substrate (nominal stencil thickness is 0.005 inch). The
test units are manually placed on the solder-paste footprint with proper implements to avoid contamination. The
ceramic substrate and components are subjected to the IR reflow process as follows:
IR REFLOW PROCESS
, Temperature
'Time
PREHEAT SOAK
REFLOW
150°C to 170°C
215°C to 230°C
60 sec
60 sec
After cooling to room temperature, the component is removed from the ceramic substrate and the component
terminals are subjected to visual inspection at. 1OX magnification.
Test results are acceptable if all terminations exhibit a continuous solder coating free of defects for a minimum
95% of the critical surface area of any individual termination. Causes for rejection include: dewetting,
nonwetting, and pin holes. The component leads and the exposed thermal pad were evaluated against this
criteria.
Number of Test Units
,
Failures
22
I
0
SOLDERABILITY TEST RESULTS
X-ray test
X-ray testing is used to examine and quantify the voiding of the soldered attachment between the thermal pad
and the PWB copper trace. Voiding between 20% and 50% was observed on a 49-piece sample.
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SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
APPLICATION INFORMATION
The TPS7133QPWP low-dropout (LOO) regulator is designed to overcome many of the shortcomings of
earlier-generation LOOs, while adding features such as a power-saving shutdown mode and a power-good
indicator.
device operation
The TPS7133QPWP, unlike many other LOOs, features very low quiescent currents that remain virtually
constant even with varying loads. Conventional LOO regulators use a pnp-pass element, the base current of
which is directly proportional to the load current through the regulator (16 IC/~)' Close examination of the data
sheets reveals that those devices are typically specified under near no-load conditions; actual operating
currents are much higher as evidenced by typical quiescent-current versus load-current curves. The
TPS7133QPWP uses a PMOS transistor to pass current; because the gate of the PMOS element is voltage
driven, operating currents are low and invariable over the full load range. The TPS7133QPWP specifications
reflect actual performance under load.
=
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in ~ forces an increase in 16 to maintain the load. Ouring power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS7133QPWP quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS7133QPWP also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent currentto under 2~. EN is pulled
down internally, requiring no external connection for continuous operation. Response to an enable transition is
quick; regulated output voltage is reestablished in typically 120 f.lS.
minimum load requirements
The TPS7133QPWP is stable even at zero load; no. minimum load is required for operation.
sense-pin connection
The SENSE pin must be connected to the regulator output for proper functioning of the regulator. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit (remote
sense) to improve performance at that point. Internally, SENSE connects to a high-impedance wide-bandwidth
amplifier through a resistor-divider network and noise pickup feeds through to the regulator output. Routing the
SENSE connection to minimize/avoid noise pickup is essential. Adding an RC network between SENSE and
OUT to filter noise is not recommended because it can cause the regulator to oscillate.
external capacitor requirements
An input capacitor is not required; however, a ceramic bypass capacitor (0.047-pF to 0.1-JlF) improves load
transient response and noise rejection if the TPS7133QPWP is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
As with most LOO regulators, the TPS7133QPWP requires an output capaCitor for stability. A low-ESR 10-JlF
solid-tantalum capa~itor connected from the regulator output to ground is sufficient to ensure stability over the
full load range (see Figure 39). Adding high-frequency ceramic or film capaCitors (such as power-supply bypass
capacitors for digital or analog ICs) can cause the regulator to become unstable unless the ESR of the tantalum
capaCitor is less than 1.2 n over temperature. CapaCitors with published ESR specifications such as the
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-181
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS1 01A- FEBRUARY 1995 - REVISED AUGUST 1995
APPLICATION INFORMATION
AVX TPS0106K035R0300 and the Sprague 5930106X0035D2W work well because the maximum ESR at
25°C is 300 mO (typically, the ESR in solid-tantalum capacitors increases by a factor of 2 or less when the
temperature drops from 25°C to -40°C). Where component height and/or mounting area is a problem,
physically smaller, 10-IlF devices can be screened for ESA. Figures 25 through 32 show the stable regions of
operation using different values of output capacitance with various values of ceramic load capacitance.
In applications with little or no high-frequency bypass capacitance « 0.2 IlF), the output capacitance can be
reduced to 4.7IiF, provided ESR is maintained between 0.7 and 2.5 Q. Because minimum capacitor ESR is
seldom if ever specified, it may be necessary to add a 0.5-0 to 1~O resistor in series with the capacitor and limit
ESR to 1.50 maximum. As shown in the ESR graphs (Figures 25 through 32), minimum ESR is not a problem
when using 10-IlF or larger output capacitors.
Below is a partiallisUng of surface-mount capacitors usable with the TPS7133QPWP. This information (along
with the ESR graphs, Figures 25 through 32) is included to assist in selection of suitable capacitance for the
user's application. When necessary to achieve low height requirements along with high output current and/or
high ceramic load capacitance, several higher ESR capacitors can be used in parall.el to meet the guidelines
above.
All load and temperature conditions with up to 1 IlF of added ceramic load capacitance:
PART NO.
MFR.
VALUE
MAX ESRt
SIZE (H x L x W)t
T 421 C226M01 OAS
5930156X002502W
5930106X003502W
TPS0106M035R0300
Kemet
Sprague
Sprague
AVX
221lF, 10 V
151lF, 25 V
10 IlF, 35 V
10 IlF, 35 V
0.5
0.3
0.3
0.3
2.8x 6x 3.2
2.8 x 7.3 x 4.3
2.8 x 7.3 x 4.3
2.8 x 7.3 x 4.3
Load < 200 mA, ceramic load capacitance < 0.2 IlF, full temperature range:
PART NO.
MFR.
VALUE
MAX ESRt
SIZE (H x L x W)t
5920156X0020R2T
5950156X0025C2T
5950106X0025C2T
2930226XOO1602W
Sprague
Sprague
Sprague
Sprague
151lF, 20 V
151lF, 25 V
10 IlF, 25 V
221lF, 16 V
1.1
1
1.2
1.1
1.2x7.2x6
2.5 x 7.1 x 3.2
2.5 x 7.1 x 3.2
2.8 x 7.3 x 4.3
Load < 100 mA, ceramic load capacitance < 0.2 IlF, full temperature range:
PART NO.
MFR.
1950106X06R3V2T
1950106X0016X2T
5950156X0016B2T
6950226X0015F2T
6950156X0020F2T
6950106X0035G2T
Sprague
Sprague
Sprague
Sprague
Sprague
Sprague
VALUE
MAX ESRt
10 IlF, 6.3 V
10IlF, 16 V
151lF, 16 V
221lF, 15 V
151lF, 20 V
10IlF, 35 V
1.5
1.5
1.8
1.4
1.5
1.3
SIZE (H x L x W)t
1.3 x
1.3 x
1.6 x
1.8 x
1.8 x
2.5 x
3.5 x 2.7
7 x 2.7
3.8 2.6
6.5 x 3.4
6.5 x 3.4
7.6 x 2.5
t Size is in mm. ESR is maximum resistance at 100 kHz and TA = 25?C. Listings are sorted by height.
~TEXAS
3-182
INSTRUMENTS
POST OFFICE BOX 655303- DALLAS. TEXAS 75265
x
TPS7133QPWP, TPS7133Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS101A- FEBRUARY 1995 - REVISED AUGUST 1995
APPLICATION INFORMATION
external capacitor requirements (continued)
TPS7133QPWP
6
7
C1
0.1 IlF
50V
IN
IN
PG
16
PG
15
Vo
5
EN
---,
Co I
+
10llF
I
ESR I
_ _ _ .JI
Figure 39. Typical Application Circuit
power-good indicator
The TPS7133QPWP features a power-good (PG) output that can be used to monitor the status of the regulator.
The internal comparator monitors the output voltage: when the output drops to between 92% and 98% of its
nominal regulated value, the PG output transistor turns on, taking the signal low. The open-drain output requires
a pullup resistor. If not used, it can be left floating. PG can be used to drive power-on reset circuitry or used as
a low-battery indicator. PG does not assert itself when the regulated output voltage falls out of the specified 2%
tolerance, but instead reports an output voltage low, relative to its nominal regulated value.
regulator protection
The TPS7133QPWP PMOS-pass transistor has a built-in back diode that safely conducts reverse currents
when the input voltage drops below the output voltage (e.g., during power down). Current is conducted from
the output to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting
may be appropriate.
The TPS7133QPWP also features internal current limiting and thermal protection. During normal operation, the
TPS7133QPWP limits output current to approximately 1 A. When current limiting engages, the output voltage
scales back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross
device failure, care should be taken not to exceed the power dissipation ratings of the package. If the
temperature of the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has
cooled, regulator operation resumes.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-183
3-184
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVSl 02C - MARCH 1995 - REVISED AUGUST 1995
DB
DPACKAGE
(TOP VIEW)
• Available in 5-V, 4.85-V, and 3.3-V
Fixed-Output and Adjustallie Versions.
• Dropout Voltage <85 mV Max at
10 100 rnA (TPS7250)
• Low Quiescent Current, Independent of
Load, 155 JJ.A Typ
• 8-Pin SOIC and 8-Pin TSSOP Package
(Product Preview)
=
SENSEt/FS*
OUT
PG270UT
GND 3
6 IN
EN 4
5 IN
PWPACKAGE
(TOP VIEW)
• Output Regulated to ±2% Over Full
Operating Range for Fixed-Output Versions
SENSEt/FS*
PG
GND
EN
• Extremely Low Sleep-State Current,
0.5~AMax
• Power-Good (PG) Status Output
description
t
The TPS72xx family of low-dropout (LDO) voltage
regulators offers the benefits of low-dropout
voltage, micropower operation and miniaturized
packaging. These regulators feature extremely
low dropout voltages and quiescent currents
compared to conventional LDO regulators.
Offered in small-outline integrated-circuit (SOIC)
packages and (product preview only) 8-terminal
thin shrink small-outline (TSSOP), the TPS72xx
series devices are ideal for cost-sensitive designs
and where board space is at a premium.
A combination of new circuit design and process
innovation has enabled the usual pnp pass
transistor to be replaced by a PMOS device.
Because the PMOS pass element behaves as a
low-value resistor, the dropout voltage is very low
- maximum of 85 mV at 100 mA of load current
(TPS7250) - and is directly proportional to the
load current (see Figure 1). Since the PMOS pass
element is a voltage-driven device, the quiescent
current is very low (300 JJ.A maximum) and is
stable over the entire range of output load current
(0 mA to 250 rnA). Intended for use in portable
systems such as laptops and cellular phones, the
low-dropout voltage feature and micropower
operation result in a significant increase in system
battery operating life.
this document contains Information on products In more than one phase
of development. The status of each device 18 indicated on the page(a}
specHyJng Its electrical characteristics.
OUT
OUT
IN
SENSE - Fixed voltage options only
(TPS7233, TPS7248, and TPS7250)
FB - Adjustable version only (TPS7201)
*
400,-----,-----,-----,-----,----,
>
E
.
I
i
~
Ie
Q
I
$
10 - Output Current - mA
Figure 1. Typical Dropout Voltage Versus
Output Current
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-185
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
AVAILABLE OPTIONS
OUTPUT VOLTAGE
(V)
PACKAGED DEVICES
TJ
4.9
5
5.1
TPS7250QD
TSSO~.(.
(P~A ..
TPS7;H ~~
4.75
4.85
4.95
TPS7248QD
TP
3.23
3.3
3.37
TPS7233QD
MIN
-55'C to 150'C
~
TYP
MAX
SMALL OUTLINE
(D)
Adjustable§
1.2 V to 9.75 V
TPS7250Y
LE
TPS724/lY
~PWLE
TPS7233Y
T~7201QPWLE
TPS7201Y
:J"""'.f'i
TPS7201QD
CHIP FORM
(Y)
..
The 0 package IS available taped and reeled. Add R suffix to deVice type (e.g., TPS7250QDR). The PW package
'
is only available left-end taped and reeled. The TPS7201 Q is programmable using an external resistor divider(see
application information). The chip form is tested at 25'C.
description (continued)
The TPS72xx also features a logic-enabled sleep mode to shut down the regulator, reducing quiescent current
to 0.5 ~ maximum at TJ 25°C. Other features include a power-good function that reports low output voltage
and may be used to implement a power-on reset or a low-battery indicator.
=
The TPS72xx is offered in 3.3-V, 4.85-V, and 5-V fixed-voltage versions and in an adjustable version
(programmable over the range of 1.2 V to 9.75 V). Output voltage tolerance is specified as a maximum of 2%
over line, load, and temperature ranges (3% for adjustable version).
TPS72xx
V I -....-
5
....- - I IN
6
IN
2
PG 1-=---....-
PG
SENSE
OUT I-'-.............--VO
O.1IlF
------,
4
OUT
EN
+
GND
~NoteA)
10llF
3
II
I
_ESR
_ _ _ _ _ .JI
NOTE A. Capacitor selection is nontrivial.
information section for details.
See
application
Figure 2. Typical Application Configuration
-!!1 TEXAS
3-186
....
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT 1~~2~Yr2~l~2~~~2~~?~!
TPS72xx chip information
These chips, when properly assembled, display characteristics similar to the TPS72xxQ. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
(5)
BONDING PAD ASSIGNMENTS
(3)
IN
TPS72xx
(2)
EN
SENSEt
(6)
FB*
(4)
OUT
(7)
PG
(1)
GND
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4
TJmax
x 4 MILS MINIMUM
=150°C
TOLERANCES ARE ± 10%•
.ALL DIMENSIONS ARE IN MILS.
t
Fixed-voltage options only (TPS7233, TPlil:7?4!1, .and
TPS7250)
...
:j: Adjustable version only (TPS7201)
NOTE A. For most applications, OUT and SENSE should
be tied together as close as possil:lle to \tie device;
for other implementations, refer to gENSE-pin
connection discussion in . the . appIic~tion
information section of this data sheet. .
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
functional block diagram
IN
EN
RESISTOR DIVIDER OPTIONS
----_>--~
r - - - t - - - . PG
DEVICE
Rl
TPS7201
TPS7233
TPS7248
TPS7250
0
420
726
756
R2
00
233
233
233
UNIT
0
ill
kO
1<.0
,','
NOTE: ReSistors are nominal values only.
I----e--
OUT
SENSEtIFB
Rl
R2
GND
t
For most applications, SENSE should be extemally connected to OUT as close as possible to the device. For other implementations, refer
to the SENSE-pin connection discussion in application information section.
:j: Switch positions are shown with EN low (active).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-187
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH'1995 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Input voltage range*, VJ, PG, SENSE, EN ........................................ : ..... -0.3 to 10 V
Output current, 10 ......................................................................... 1.5 A
Continuous total power dissipation ............................. See Dissipation Rating Tables 1 and 2
Operating virtual junction temperature range, 'TJ ........ ~ . . . . . . .. . . . . . . . . . . . . . .. . . .. -55°C to 1'50°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. Thes.e are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated' under "recommended operating conditions· is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
*
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE (see Note 1 and Figure 3)
=
=
=
PACKAGE
TA';; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA 7QoC
POWER RATING
TA 85°C
POWER 'RATING
TA 125°C
POWER RATING
D
PW§
725mW
525mW
5.8mW/oC
4.2mW/oC
464mW
336mW
377mW
273mW
145mW
105mW
=
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE (see Note 1 and Figure 4)
=
PACKAGE
TC';; 25°C
POWER RATING
DERATING FACTOR
ABOVE TC 25°C
TC 70°C
POWER RATING
TC" 85°C
POWER RATING
TC = 125°C
pOWER RATING
D
PW§
2063mW
2900mW
16.5mW/oC
23.2mW/oC
1320 mW
1856mW
1073mW
15pamW
413mW
580mW
=
§ The PW package information is product preview only and 'is not yet available.
NOTE 1: Dissipation rating tables and figures are provided for maintenance of junction temperature at or below absolute
maximum of 150°C. Forguidelines on maintaining junction temperature within the recommended operating range,
see application information section.
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
800~----~----~----~----~--~
~I
t
c'
'i
700~--1---1---1---1---4
6001--~--_+--_+--_+_---l
is
500~.---t-~~+
g
4001--~~--~.---1---1---4
~E
~E
~
·M
1000 r - - - t -__-I-...3o,..,-P".---If---j
P~ge
"'q;'<'
::l!!
500r---+---+---~-~~~-_i
300 r---+--~u\
I
100~--+---~---r--~~-~
Re.Jl&!.fj8°C/W .-~..,-~-+---I
I
rP
o~
O~----~----~----~----~--~
25
50
75
100
125
150
____
25
TA - Free-Air Temperature - °C
~
50
____
~
____
75
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~
100
__
~~
125
TC - Case Temperature - °C
Figure 4
Figure 3
3-188
C- - t - - - j
""..;s;.::f!.
::Jt~C/W
~~.1°
1500r---+-~~+-~-~---r---;
200
rP
2000 p..,.---j-~-+
c
~
i
!~=.
g
rg
c
~I
__
~
150
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT !b~2t Y,2~!~2~ ~~2~lu~l91~!
recommended operating conditions
Input voltage, Vlt
MIN
MAX
TPS7201Q
2.5
10
TPS7233Q
3.98
10
TPS7248Q
5.24
10
TPS7250Q
5.41
10
High-level input voltage at EN, VIH
2
Low-level inpu1 voltage at EN, VIL
Ou1pu1 current, 10
Operating virtual junction temperature, T J
..
..
..
UNIT
V
V
0.5
V
0
250
mA
-40
125
°c
t MInimum Input voltage defmed In the recommended operating conditions IS the maximum specHled output voltage plus dropout voltage at the
maximum specified load range. Since dropout voltage is a function of output current, the usable range can be extended for lighter loads. To
calculate the minimum input voltage for the maximum load current used in a given application, use the following equation:
V I(min) = V O(max)
+ V OO(max load)
Because the TPS7201 is programmable, rOS(on) should be used to calculate VOO before applying the above equation. The equation for
calculating VOO from rOS(on) is given in Note 3 under the TPS7201 electrical characteristics table. The minimum value of 2.5 V is the absolute
lower limit for the recommended input-voltage range for the TPS7201.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-189
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO)VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
electrical characteristics, 10 = 10 mA, EN = 0 V, Co =4.7 ~F (CSRt = 1 n), SENSElFB shorted to OUT
(unless otherwise noted)
PARAMETER
TEST CONDITIONS*
TJ
TPS7201Q,TPS7233Q
TPS7248Q, TPS7250Q
MIN
Ground current (active 'mode)
EN,,0.5V,
VI =VO+ 1 V,
OmA"IO,,250 rnA
Input current (standby mode)
EN=VI,
2.7 V" VI " 10 V
Output current limit threshold
VO=OV,
VI = 10 V
Pass-element leakage current
in standby mode
EN = VI,
2.7V"VI,,10V
fiG leakage current
VPG = 10V,
Normal operation
Output voltage temperature coefficient
180
25°C
EN logic low (active mode)
25°C
0.5
1
0.6
25°C
1.5
25°C
0.5
-40°C to 125°C
1
0.5
'25°C
0.5
-40°C to 125°C
31
-40°C to 125°C
75
165
2.5 V"VI,,6 V
6V"VI,,10V
2.7V"VI,,10V
40°C to 125°C
OV"VI,,10V
25°C
0.5
0.5
50
IPG = 300 !iA
-0,5
0.5
-40°C to 125°C
-0.5
0.5
25°C
-40°C to 125°C
A
!iA
!iA
ppml"C
1.9
2.5
2.5
0.95
V
mV
25°C
-40°C to 125°C
\
!iA
V
2.7
-40°C to 125°C
25°C
!iA
°C
2
25°C
Minimum VI for active pass element
Minimum VI for valid PG
1
-40°C to 125°C
EN hysteresis voltage
EN input current
225
325
-40°C to 125°C
UNIT
MAX
-40°C to 125°C
Thermlll shutdown junction temperature
§ 100 mA simultaneously, pass element rOS(on) increases (see Figure 10) to a point such thatthe resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3. To calculate dropout voltage, use equation:
VOO = 10' rOS(on)
rOS(on) is a function of both output current and input voltage. The parametric table lists rOS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-191
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
TPS7233Q electrical characteristics, 10 = 10 rnA, VI = 4.3 V, EN =0 V, Co = 4. 7 ~F (CSRt = 1 0), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
VI =4.3 V,
10=10mA
4.3V"VI,,10V,
5 mA" 10 " 250 mA
10=10mA,
VI = 3.23 V
10= 100mA,
VI =3.23V
10=250mA,
VI = 3.23 V
Pass-element series resistance
(3.23 V - VOl/IO,
10=250mA
VI = 3.23 V,
Input regulation
VI = 4.3 V to 10 V,
50!1A" 10 ,,250 mA
Output voltage
Dropout voltage
Output regulation
10 = 50!1A to 250 mA, 4.3 V" VI" 10 V
10 = 50!1A
f= 120 Hz
10 =250 mA
Output noise spectral density
Output noise voltage
PG trip-threshold voltage
TJ
25°C
-40°C to 125°C
10Hz"f,,100kHz,
CSRt=l n
3.37
14
140
25°C
-40°C to 125°C
25°C
360
460
1.5
1.84
2.5
25°C
8
-40°C to 125°C
25°C
32
-40°C to 125°C
mV
41
-40°C to 125°C
n
mV
42
71
25°C
55
mV
98
25°C
40
_40°C to 125°C
38
25°C
35
-40°C to 125°C
33
52
dB
44
2
25°C
265
CO= 10j1F
25°C
212
CO=l00j1F
25°C
135
j1v/1HZ
j1Vrms
0.95 x
VO(noml
25°C
32
25°C
0.22
-40°C to 125°C
25
33
CO=4.7j1F
VI=2.8V
180
610
25°C
to 125°C
V
20
232
-40°C to 125°C
~40°C
UNIT
30
25°C
Vo voltage decreasing from above VPG
MAX
3.3
3.23
25°C
f=120Hz
IpG= 1 mA,
TYP
-40°C to 125°C
PG hysteresis voltage
PG output low voltage
MIN
-40°C to 125°C
10 =5 mA to 250 mA, 4.3V"VI,,10V
Ripple rejection
TPS7233Q
TEST CONDITIONS*
V
mV
0.4
0.41
V
t CSR refers to the total senes resistance, Including the ESR of the capacitor, any senes resistance added extemally, and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
3-192
POST OFFICE BOX 655303 • DALLAS, T~XAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT !b~2tY~~l~2~~~2~l~l~1~!
=
=
=
=
=
TPS7248Q electrical characteristics, 10 10 mA, VI 5.85 V, EN 0 V, Co 4.7 J.lF (CSRt 1 a), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
VI = 5.85 V,
10= 10 rnA
5.85 VSVI S 10 V,
5mASIOS250rnA
10= 10 rnA,
VI =4.75 V
10=1OOmA,
VI =4.75 V
10 =250 mA,
VI = 4.75 V
Pass-element series resistance
(4.75 V - VO)IIO,
10 = 250 rnA
VI = 4.75 V,
Input regulation
VI = 5.85 Vto 10V,
50 lIAS 10 S250 mA
Output voltage
Dropout voltage
10 = 5 mA to 250 mA, 5.85VSVIS10V
Output regulation
10= 50 IIA to 250 rnA, 5.85 V S VI S 10 V
10 = 50 IIA
Ripple rejection
f= 120Hz
10 = 250 mA
Output noise spectral density
Output noise voltage
PG trip-threshold voltage
TPS7248Q
TEST CONDITIONS*
TJ
25°C
-40°C to 125°C
IpG= 1.2 rnA,
4.95
10
25°C
90
-4QOC to 125°C
25°C
216
100
mV
250
285
-40°C to 125°C
25°C
0.8
1
-40°C to 125°C
1.4
25°C
34
-4QOC to 125°C
50
43
25°C
25°C
55
-40°C to 125°C
0
mV
55
95
-40°C to 125°C
75
mV
135
25°C
42
-40°C to 125°C
36
25°C
36
-40°C to 125°C
34
53
dB
46
2
25°C
370
CO= 10ltF
25°C
290
CO=looItF
25°C
168
-40°C to 125°C
0.95 x
VO(nom)
25°C
50
25°C
0.2
-40°C to 125°C
V
19
150
Co = 4.7 ItF
VI=4.12V
UNIT
30
25°C
Vo voRage decreasing from above VPG
MAX
4.85
4.75
25°C
PG hysteresis voltage
PG Ol.iput low voltage
TYP
-40°C to 125°C
f= 120 Hz
10 Hzsfs 100kHz,
CSRt= 10
MIN
ItVNHz
ItVrms
V
mV
0.4
0.4
V
t CSR refers to the total senes resistance, including the ESR of the capacitor, any senes resistance added extemally, and PWB trace resistance
toCO·
t Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
3-193
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
TPS7250Q electrical characteristics, 10= 10 rnA, VI = 6 V, EN = 0 V, Co = 4.7 ~F (CSRt = 1 Q), SENSE
shorted to OUT (unless otherwise noted)
PARAMETER
VI=6V,
10= 10mA
6VSVp:;10V,
5 mAs IOS250 mA
10= 10 mA,
VI=4.66V
10= lOOmA,
VI = 4.88 V
10=250 IJA, •
VI = 4.88 V
Pass-element series resistance
(4.66 V - VO)1I0,
10=250mA
VI =4.88 V,
Input regulation
VI=6Vtol0V,
50 IJA S 10 S 250 rnA
Output v~ltage
Dropout voltage
Output regulation
10= 50 IJAt0250 mA, 6VSVIS10V
10 = 50 IJA
f= 120 Hz
10 =250 rnA
Output noise spectral density
Output noise voltage
PG trip-threshold voltage
f= 120 Hz
10HzSfSIOOkHz,
CSRt= 10
25°C
-40°C to 125°C
TYP
25°C
5.1
6
-40°C to 125°C
76
25°C
-40°C to 125°C
V
12
85
136
25°C
190
-40°C to 125°C
mV
206
312
25°C
0.76
0.825
1.25
25°C
28
-40°C to 125°C
35
46
25°C
-40°C to 125°C
59
-40°C to 125°C
0
mV
61
100
25°C
. 79
mV
150
25°C
41
-40°C to 125°C
37
25°C
36
-40°C to 125°C
32
52
dB
46
2
390
CO= 10llF
25°C
300
Co = 100!1F
25°C
175
-40°C to 125°C
0.95 x
VO(nom)
25°C
50
25°C
0.19
-40°C to 125°C
UNIT
30
25°C
VI=4.25V
MAX
5
4.9
CO=4.7IlF
Vo voltage decreasing from above VPG
IPG = 1.2 mA,
MIN
25°C
PG hysteresis voltage
PG output low voltage
TJ
-40°C to 125°C
10 =5 rnA to 250 mA, 6VSVIS10V
Ripple rejection
TPS72S0Q
TEST.CONOITIONS*
IlV/VRZ
IlVrms
V
mV
0.4
0.4
V
t CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
3-194
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT i~~2tY.2~!~2~~~2~~191~!
=
electrical characteristics, 10 10 rnA, EN
shorted to OUT (unless otherwise noted)
PARAMETER
=0 V, Co =4.7 ~F (CSRt =1 n), TJ =25°C, SENSE/FB
TEST CONDITIONS:!:
TPS7201 Y, TPS7233Y
TPS7248Y, TPS7250Y
MIN
Ground current (active mode)
EN~0.5V,
VI =VO+ 1 V,
o mA~ IO~250 mA
Output current limit threshold
VO=OV,
TYP
180
UNIT
MAX
~
0.6
A
165
°C
EN hysteresis voltage
50
mV
Minimum VI for active pass element
1.9
V
0.95
V
VI=10V
Thermal shutdown junction temperature
Minimum VI for valid PG
IpG = 300 j1A
t
CSR(compensatlon senes resistance) refers to the total senes resistance, Including the equivalent senes resistance (ESR) of the capaCitor, any
series resistance added externally, and PWB trace resistance to CO.
:I: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-195
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TP$7248Y, TPS7250Y
.
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995- REVISED AUGUST1995
electrical characteristics, 10 = 1OmA, EN = 0 V; Co = 4.7 IJ.F (CSRt =1 il), TJ = 25°C, FB shorted to
OUT at device leads (unless otherwise noted)
PARAMETER
TEST CONDITIONS*
Reference voltage (measured at FB with OUT
connected to FB)
Pass-element series resistance (see Note 3)
Output regulation
VI =2.4 V,
50 1lA,;; 10';; 100 rnA
2.1
VI = 2.4 V,
100 rnA,;; 10';; 200 rnA
2.9
VI=2.9V,
50 IlA ,;; 10 ,;; 250 rnA
1.6
VI = 3.9 V,
50 1lA,;; 10 ,;;250 rnA
1
VI = 5.9. V,
50 IlA ,;; 10 ,;; 250 rnA
0.8
2.5 V ,;;VI';; 10 V,
See Note 2
10 = 5 rnA to 250 rnA,
2.5V,;;VI·,;;10V,
See Note 2
10 = 50 IlA to 250 rnA,
50
f= 120 Hz
Co = 4.7 IlF
Output noise voltage
FB input current
..
2
190
CO= l00IlF
125
Measured at VFB
VI=2.13V,
IpG =4001lA
VI = 3.5 V
g
dB
IlV/...[Hz
235
CO= 10llF
VI = 3.5 V,
V
mV
60
VI=3.5V,
10 Hz,;;f,;; 100kHz,
CSRt= 1 g
UNIT
17
10 =50 IlA
VI =3.5V,
MAX
15
10=250 rnA,.
See Note 2
Output noise spectral density
,
1.188
10= lOrnA
VI=3.5V,
f= 120Hz
PG output low voltage§
TYP
VI = 3.5 V,
Ripple rejection
PG hvstelesis voltage§
TPS7201Y.
MIN
12
IlVrms
mV
0.1
V
0.1
nA
t CSR refers to the total senes resistance, Including the ESR of the capacitor, any senes resistance added externally, and PWB trace resistance
to Co.
:I: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
§ Output voltage programmed to 2.5 V w~h closed-loop configuration (see application information).
NOTES: 2 When VI < 2.9 V and 10 > 100 rnA simultaneously, pass element rOS(on) increases (see Figure 10) to a point such that the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
3 To calculate dropout voltage, use equation:
VOO = 10· roS(on)
roS(on) is a function of both output current and input voltage. The parametric table lists rOS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V, respectively. For other
programmed values, refer to Figures 10 and 11.
~TEXAS
INSTRUMENTS
3--196
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT !b~~l Yr2~l~2~~~2~1u~l9~!
=
electrical characteristics, 10 10 rnA, EN
to OUT (unless otherwise noted)
=0 V, Co =4.7 J.LF (CSRt =1 il), TJ =25°C, SENSE shorted
TEST CONDITIONS:!:
PARAMETER
Output voltage
Dropout voltage
Pass-element series resistance
TPS7233Y
MIN
TYP
VI=4.3V,
10=10mA
3.3
VI = 3.23 V,
10=10mA
14
VI = 3.23 V,
10=100mA
140
VI = 3.23 V,
10 =250 mA
360
(3.23 V - VOl/IO,
10=250mA
VI = 3.23 V,
VI=4.3Vtol0V,
50 !1A s 10 S 250 mA
8
10=5 mA to 250 mA
32
4.3 V S VI S 10 V,
10 = 50 !1A to 250 mA
41
Ripple rejection
VI=4.3V,
1= 120 Hz
10= 50!1A
52
10=250mA
44
Output noise spectral density
VI =4.3V,
1=120Hz
Output regulation
Output noise voltage
VI =4.3V,
10HzsIsl00kHz,
CSRt=1 n
mV
n
mV
mV
dB
2
CO=4.7IlF
265
CO= IOIlF
212
CO= IOO IlF
135
IPG= 1 mA
PG hysteresis voltage
VI=4.3V
32
PG output low voltage
VI=2.8V,
0.22
UNIT
V
1.5
4.3 V S VI S 10 V,
Input regulation
MAX
IlV/v'Hz
IlVrms
mV
V
t CSR relers to the total series resistance, including the ESR 01 the capacitor, any series resistance added extemally, and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effeCts must be
taken into account separately.
.
PARAMETER
Output voltage
Dropout voltage
Pass-element series resistance
TEST CONDITIONS:!: '
TPS7248Y
MIN
TYP
VI = 5.85 V,
10= 10mA
4.85
VI = 4.75 V,
10= tOmA
10
VI = 4.75 V,
10= 100mA
90
VI = 4.75 V,
10= 250 mA
216
(4.75 V - VOlIIO,
10= 250 mA
VI = 4.75 V,
0.8
MAX
UNIT
V
mV
n
5.85 V S VI S 10 V
10= 5 mA to 250 mA
43
5.85VSVIS10V
10 = 50 !1A to 250 mA
55
Ripple rejection
VI = 5.85 V,
1= 120 Hz
10= 50!1A
53
10=250mA
46
Output noise spectral density
VI = 5.85 V,
1= 120 Hz
VI = 5.85 V,
10HzSIS100kHz,
CSRt= Hl
Co =4.7IlF
370
CO= IO IlF
290
CO= IOO IlF
168
50
mV
IpG=I.2mA
0.2
V
Output regulation
Output noise voltage
PG hysteresis voltage
VI=5.85V
PG output low voltage
VI=4.12V,
2
mV
dB
IlV/v'Hz
IlVrms
t CSR refers to the total series resistance, including the ESR of the capaCitor, any series resistance added extemally, and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-197
TPS7201Q, TPS7233Q, TPS7248Q, TPS7250Q
TPS7201 Y,·TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE .REGULATORS
SLVS1020- MARCH 1995 - REVISED AUGUST 1995
=
=
=
eleCtrical cbaracterlstics, 10 10 mA, EN 0 V, Co 4.7 J.LF (CSRt
to OUT (unless otherwise noted) (continued)
PARAMETER
Output voltage
=1 Q),TJ =25°C, SENSE shorted
TEST CONomONs*
TPS7250Q
TYP
MAX
MIN
VI=6V,
10=10mA
5
VI = 4.88 V,
10= 10 rnA
8
VI = 4.88 V,
10= 100 rnA
76
VI = 4.88 V,
10=250 I1A
190
Pass-element series resistance
(4.88 V - Vo)/Io,
10 =250 mA
VI ,;,4.88 V,
Input regulation
VI=6Vtol0V,
50 11A" 10" 250 mA
6 V"VI" 10V,
10= 5mAt0250rnA
46
6V"VI,,10V,
10 = 50 I1A to 250 mA
59
VI=6V,
1=120Hz
10= 50 I1A
52
10=250mA
46
VI=6V,
I" 120Hz
VI,,6V,
10Hz"I,,100kHz,
CSRt=10
CO=4.7ILF
390
CO= lOILF
300
CO=l00ILF
175
IpG= 1.2 rnA
0.19
Dropout voltage
Output regulation
Ripple rejection
Output noise spectral density
Output noise voltage
PG hysteresis voltage
VI=6V
PG output low voltage
VI = 4.25 V,
0.76
UNIT
V
mV
0
mV
2
50
mV
dB
ILV/..JHz
ILVrms
mV
V
t CSR relers to the total series resistance, including the ESR 01 the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
:I: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS .
INSTRUMENTS
3-198
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT ~~~2tY~~l~2~~~2~lu~l9~!
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
5
vs Input voltage
6
IQ
Quiescent current
dlQt
Change in quiescent current
vs Free-air temperature
7
VOO
Oropout voltage
vS: Output current
8
.WOO
Change in dropout voltage
vs Free-air temperature
VOO
Dropout voltage (TPS7201 only)
vs Output current
rOSlon)
Pass-element series resistance
vs Input voltage
11
dVO
Vo
Change in output voltage
vs Free-air temperature
12
Output voltage
vs Input voltage
13
9
10
Line regulation
14
Load regulation (TPS7233)
15
Load regulation (TPS7248)
16
Load regulation (TPS7250)
17
VO(PG)
Power-good (PG) voltage
vs Output voltage
roS(on)PG
Power-good (PG) on-resistance
vs Input voltage
19
V,
Minimum input voltage for valid PG
vs Free-air temperature
20
18
Output voltage response from enable (EN)
21
Load transient response (TPS7201/TPS7233)
22
Load transient response (TPS72481TPS7250)
23
Line transient response (TPS7201)
24
Line transient response (TPS7233)
25
Line transient response (TPS72481TPS7250)
26
Ripple rejection
vs Frequency
Output Spectral Noise Oensity
vs Frequency
vs Output current (CO
Compensation series resistance (CSR)
27
28
=4.7 ~F)
vs Added ceramic capacitance (CO
vs Output current (CO
29
=4.7 ~F)
30
=10 I!F)
32
=10 I!F)
vs Added ceramic capacitance (CO
31
t This symbol is not currently listed within EIA or JEOEC standards for semiconductor symbology.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-199
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
QUIESCENT CURRENT
vs
vs
OUTPUT CURRENT
230
INPUT VOLTAGE
250
TP~7248 V, ~ 10 V
TA=25°C
TPS7248
TA25°C
'0 =250 mA
220
200
"'
"'1:
210
:l.
I
:l.
I
1:
~
200
TPS7233 V,= 10 V -
1:
190
TP~7250 V, ~ 10 V
::I
(,)
I
§
.!!!
a
I
100
::I
I
..!.
rpS7250
160
150
.fl
.!!!
a
170
.9
150
1:
I
TPS7248 V, = 5.85 V _
180
::I
~
::I
(,)
.9
v, = 6.0 V
I
50
TPS7233 V, = 4.3 V
o
50
100
150
200
. '0 - c;>utput Current - mA
0
250
0
Figure 5
DROPOUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
OUTPUT CURRENT
400
50
40
1:
~
30
:l.
'O=10mA
V,=VO+1 V
/
/
I
::I
(,)
/
20
1:
.fl
a
.
/
10
•!!!
::I
/
0
-10
(,)
-20
.c
I
a
:a
I'
I'
~
I
t
/
~
/
I
//
.5
III
c
to
-30
I
//
g
>
V
V
-40
-40 -20
0 20
40 60
80 100 120 140
TA - Free-Air Temperature - °C
Figure 7
'0 - Output Current - mA
Figure 8
~TEXAS'
3-200
4
5
7
3
6
V, - 'nput Vo'tage - v
Figure 6
CHANGE IN QUIESCENT CURRENT
"'
2
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8
9
10
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT !b~2tY~~l~2;'~~2~lu~l91~!
TYPICAL CHARACTERISTICS
TPS7201
DROPOUT VOLTAGE
VB
OUTPUT CURRENT
1.6...----,.--...,.---..,---.,..----,
CHANGE IN DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
0.05
>
0.04
;
0.03
I
~
0.02
8.
e
c
0.01
.5
0
OJ
&
c
!(J
TPS72~
./
~
,/"
I
-0.02
~
<]
-0.03
V
/
OJ
0.81----+-
I
~
~ TPS72481TPS7250
1
0.61---+---+------r..¥'<--+'<---:7'~
$
0.41---+---+--~~~"M:-e.,..,c:....--::I
I
:/
-0.04
-40 -20
;
1.21---+---+--+--+--+-1
VI=2.9V
I
VI=3.2V
>
4"-
-0.01
0
~V
1 . 4 1 - - - + - - - + - - + - VI = 2.4 V
V.
0.2~~~
00
0
20 40 60 80 100 120 140
TA - Free-Air Temperature - °C
50
100
150
200
10 - Output Current - mA
Figure 9
Figure 10
CHANGE IN OUTPUT VOLTAGE
VB
FREE-AIR TEMPERATURE
PASS ELEMENT SERIES RESISTANCE
vs
INPUT VOLTAGE
c::
15
6
TA = 25°C
VFB=1.12V
I
CD
u
c
I
II:
Il
5
>
4
;
eCD
I
3
.....
\
2
C 1
.2-
o
2
0
!
0
-5
CD
Dl
1\
.
c
I
4
-15
0
~
I I
3
-10
.c
(J
10=100m7:'- ~
III
...C
~
5
6
7
8
9
10
I
I
10= 10mA
VI=VO+1 V
"""-,
.5
'~
IL
I
5
OJ
IO=250mA
E
.!!
w
10
-....
E
.;:
~
250
-20
-25
-40 -20
VI - Input Voltage - V
Figure 11
"'r\\
\
""
I\.
0
20 40 "60
80 100 120 140
TA - Free-Air Temperature - °C
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAL!.AS, TEXAS 75265
3-201
/
TPS7201 Q, TPS7233Q"TPS7248Q, TPSi250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
,
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE
vs
INPUT VOLTAGE
5.5
T~72~
TAI=25~C
5
IO=250mA
/
4.5
>
4
III
3.5
~
f/
/J.
'I
'I
~
'
&
I,
3
!0=
TPS7248 _ I---
II
I
r
LINE REGULATION
25
r- TPS7201 With
Vo Programmed to 2.5 V
0
0.5
~~
~
2
3
4
5
6
7
8
9
TPS7250
4
4.5 5 5.5
Figure 13
TPS7233
TPS7248
LOAD REGULATION
50
TA = 25°C
>
E
I
III
:ll!
20
=
i
10
~
0
0
.5
&
c
01
aJ
", r--
r.
-20
I
-30
20
=
t
10
--- -
0
.5
&
c
01
(J
~
'
.........
TPS~_
0
-10
~
I
5
r.
I
I
TPS7201 With--,
Vo Programmed to 2.5 V
10
&
c
(J
I
15
-5
01
TA=25°C
10 = 250 mA
20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
250
TPS7201 Q, TPS7233Q, TPS7248Q, TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT ~~~2t Y~~l~2~ ~~2~lu~l?1~9~
TYPICAL CHARACTERISTICS
POWER·GOOD (PG) VOLTAGE
I
8.
t:;
t
0
..
.5
1:11
C
1\1
&.
(.)
I
.p
-
o
2.5
3
3.5
4
VI - Input Voltage - V
4.5
5
,
r-.... r--- V
1.110
-40 -20
Figure 19
/
/
0
20
40 60
80 100 120 140
TA - Free·Air Temperature - °C
Figure 20
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-203
TPS720,1 Q, JPS7233Q, JPS7248Q, JPS7250Q ,
JPS7201Yj JPS7233Y,. JPS7248Y, JPS7250Y
MICROPOWER LOW~OaOPOUJ (LOO) VOLJAGE REGULATORS
SLVS102C ~ MARCH. 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
,
TA=25°C
CI=O
_
Co = 4.7 IlF (ESR = 1 Q)
,
>
10
!
S ~
lifi
o !-.
~
A
.-
Vonom
r-
>
T
/
/
I
V
o
150
100
50
t-Tlme-/lS
Figure 21
TPS7201 (WITH Vo PROGRAMMED TO 2.S V), TPS7233
LOAD TRANSIENT RESPONSE
>
E
I
t
i
o
~
.5
200
100
I"
0
-100
''
TA=2SoC
VI=6V
CI=O
Co = 4.7 IlF (ESR = 1 Q)
8,
c
!
u
~
-200
I
~
<:I
10S,
I
C
55
S
~
:::I
U
J
I
o
100
200
300
400
t-Tlme-/lS
Figure 22
~TEXAS
3-204
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
SOO
.9
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201Y,TPS7233Y,TPS7248Y,TPS7250Y
MICROPOWER LOW-DROPOUT ib~91Y.2~!~2~~~2~~l?1~9~
TYPICAL CHARACTERISTICS
TPS7248JTPS7250
LOAD TRANSIENT RESPONSE
=e
200
I
&
i
100
I
~,
&
0
I"
.5
TA = 25°C
VI=6V
CI=O
Co = 4.7 I1F (ESR = 1 n)
& -100
!0-200
I
o
~
105
55
5
1
I
i
a
I
I
o
100
200
300
t-Time-j1S
400
500
.9
Figure 23
TPS7201 WITH Vo PROGRAMMED TO 2.5 V
=e ,
LINE TRANSIENT RESPONSE
I
100
~
50
J
i
o
\.
o
.E
& -50
_
!o
_
-100
v
...
V
TA=25°C
CI=O
Co = 4.7 I1F (ESR = 1 n)
I
o
~
6.5
>
6.25
J
6
I
~
'!i
a.
.5
I
o
200
t-Time- j1S
100
300
400
:>
Figure 24
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-205
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7233
>
LINE TRANSIENT RESPONSE
E
I
OIl
200
DI
:Ill
~
100
'S
t
0
0
.5
OIl
DI
\,.
V
I\.
V
-50
TA = 25°C
C,=O
CO=4.7I1F (ESR=10)
c
os
J:.
0
-100
I
~
<1
6.5
::;-
6.25
I_
6
o
100
.200
300
400
5.75
500
~
'5CL
.5
I
:>
t-TIme-l1s
Figure 25
T.PS72481TPS7250
>
LINE TRANSIENT RESPONSE
E
I
OIl
100
DI
:Ill
~
'5
50
'S
0
0
CL
.5
OIl
DI
1\ .-
,
V
0
V
-50
c
os
.c
I\.
1
TA=25°C
CI=O .
Co = 4.7 I1F (ESR = 1 0)
-100
I
0
~
6.5
::;-
6.25
I_
6
~
~
.5
I
o
100
200
300
400
t-TIme-l1s
Figure 26
~TEXAS . .
3-206
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
500
:>
TPS7201 Q, TPS7233Q, TPS7248Q, :TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT 1~~2tYr2~l~2~~~2~~~l91~!
TYPICAL CHARACTERISTICS
RIPPLE REJECTION
vs
FREQUENCY
60
TA=25~C
TPS7233
50
m
"g
I
l'
40
j
.-
III~
TPS72481
TPS7250
c
30
II
ii:
~IIIIIIIIIIIIIIIIIIIII
TPS7201 With
Vo Programmed
to 2.5 V
I
II:
a.
Co
'"''''
No Input
Capacitance Added
VI=VO+ 1 V
10 = 100 mA
Co = 4.71!F (ESR = 1)
20
II~
10
~
o
10
100
1K
10 K
100 K
1M
10 M
f - Frequency - Hz
Figure 27
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
10
TA=25°C
No Input Capacitance Added
VI=VO+1 V
1$S;
I f 111111
!\
::l.
I
I I 1111111
I
. \ CO=4.7I!F(ESR=1 Q)
..
~
C
II
Co = 10 I!F (ESR = 1 Q)
0
II
'"
'0
z
!,
to
8II)
\
0.1
:;
~
0
Co = 100 I!F (ESR = 1 Q)
0.01
10
1"11111111
100
I 11111111
1k
10 k
100 k
f - Frequency - Hz
Figure 28
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-207
TPS7201 Q, TPS7233Q, TPS7248Q, TPS7250Q
TPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C- MARCH 1995- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTA~CE (CSR)t
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)t
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
c:I
3c
c:I
3c
I
i
.f!
i
c
ic
a:
TA=25°C
VI=VO+1 V
IO=250mA
Co = 4.7 I1F
No Input Capacitor Added
a:
OJ
"l
11)
c
t
OJ
c
B-
E
8I
0.1
a:
rJ
0.01
B-
TA=2S0C
VI=VO+1 V
Co =4.7 I1F
No Added Ceramic Capacitance
No Input Capacitance Added
0
~~
so
100
1S0
E
8I
rJ
2S0
200
0.1
a:
0.01
o
0.1
10 - Output Current - mA
0.2 0.3 0.4" O.S
0.6 0.7 0.8 0.9
1
Added Ceramic Capacitance - I1F
Figure 29
Figure 30
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)t
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE (CSR)t
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
100
TA=2S0C
VI=VO+1 V
10 = 2S0 mA
CO= 10 I1F
No Input Capacitor Added
c:I
II 1D~~~~~~~~~~~~
1------1-- TA = 2S0C
VI=VO+1 V
VI
~~~~~ Co
= 10 I1FCeramic Capacitance
No Added
c
;;;0
:
8E
No Input Capacitor Added
0.1
I
~
50
100
150
200
2S0
0.1
".2 0.3 0.4 O.S
0.6 0.7 0.8 0.9
1
Added Ceramic Capacitance - I1F
10 - Output Current - mA
Figure 32
Figure 31
t CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
~TEXAS
3-208
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201 V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT !b~2~Y,2~l~2~~~2~lu~l9~~
APPLICATION INFORMATION
The design of the TPS72xx family of low-dropout (LOO) regulators is based on the higher-current TPS71xx
family. These new families of regulators have been optimized for use in battery-operated equipment and feature
extremely low dropout voltages, low supply currents that remain constant over the full-output-current range of
the device, and an enable input to reduce supply currents to less than 0.5 jJA when the regulator is turned off.
device operation
The TPS72xx uses a PMOS pass element to dramatically reduce both dropout voltage and supply current over
more conventional PNP-pass-element LOO designs. The PMOS transistor is a voltage-controlled device and,
unlike a PNP transistor, does not require increased drive current as output current increases. Supply current
in the TPS72xx is essentially constant from no-load to maximum.
Current limiting and thermal protection prevent damage by excessive output current ancl/or power dissipation.
The device switches into a constant-current mode at approximately 1 A; further load increases reduce the output
voltage instead of increasing the output current. The thermal protection shuts the regulator off if the junction
temperature rises above 165°C. Recovery is automatic when the junction temperature drops approximately 5°C
below the high temperature trip point. The PMOS pass element includes a back diode that safely conducts
reverse current when the input voltage level drops below the output voltage level.
A logic high on the enable input, EN, shuts off the output and reduces the supply current to less than 0.5
EN should be grounded in applications where the shutdown feature is not used.
JJA.
Power good (PG) is an open-drain output signal used to indicate output-voltage status. A comparator circuit
continuously monitors the output voltage. When the output drops to approximately 95% of its nominal regulated
value, the comparator turns on and pulls PG low.
A typical application circuit is shown in Figure 33.
TPS72xx PW-8
PG ..,,2=--_..._ _ PG
SENSE 1
OUTt-'8,--~....._ - Vo
O'1~:T
OUT 7
---,
+10!1F II
ESR=1
_ _ _ .J
~e----~.-----
__
Figure 33. Typical Application Circuit
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-209
TPS7201 Q, TPS7233Q, TPS"1248Q, TPS7250Q
tPS7201Y, TPS7233Y, TPS7248Y, TPS7250Y
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C-MARCH 1995-REVISEDAUGUST1995
..
..
.
APPLICATION INFORMATION
external capacitor requirements
Although not required, a 0.047-IlF to 0.1-IlF ceramic bypass input capacitor,connected between IN and GNO
and located close to the TPS72xx, is recommended to improve transient response and noise rejection. A
higher-value electrolytic input capacitor may be necessary if large, fast-rise-time load transients are anticipated
and the device is located several inches from the power source.
An output capacitor is required to stabilize the internal feedback loop. For most applications, a 1O-IlF to 15-IlF
solid-tantalum capacitor with a 0.5-0 resistor (see capacitor selection table) in series is sufficient. The maximum
capacitor ESR should be limited to 1.3 a to allow for ESR doubling at cold temperatures. Figure 34 shows the
transient response of a 5-mA to 85-mA load using a 10-IlF output capacitor with a total ESR of 1.7 n
A 4.7-IlF solid-tantalum capacitor in series with a 1-0 resistor may also be used (see Figures 29 and 30)
provided the ESR of the capacitor does not exceed 1 a at room temperature and 2 a over the full operating
temperature range.
f
. . 1 ..
1:.,.
+
...
. • • • • . . • • • • • . . . -j_ • • . . . • . . . • • . .
+
.
1~:+1.'HH-H:+'~
Yo
·t-
...-· ..
·~t
f
"-t... ,... ,.. ,." ........ ',.
'LL
10=85mA
4:
2~ ~
Ch1
f.v..;'!,tNoI"'-~,"".."".~.':"..,.....~
'IIi.!"'......",,'. . . "".
.............. """,'r""
50mV
Ch2
50mA
10
=5 mA
100 IUIIdiv
Figure 34. Load Transient Response (ESR total
=1.7 a), TPS7248Q
A partial listing of surface-mount capacitors usable with the TPS72xx family is provided below. This information
(along with the stability graphs, Figures 29 through 32) is included to assist the designer in selecting suitable
capacitors.
CAPACITOR SELECTION
PART NO.
5920156X0020R2T
5950156X0025C2T
5950106X0025C2T
6950106XOO35G2T
t
MFR.
Sprague
Sprague
Sprague
Sprague
VALUE
151lF, 20
151lF, 25
10 IlF, 25
10 IlF, 35
MAX ESRt
V
V
V
V
1.1
1
1.2
1.3
2.5 x 7.6 x 2.5
Size is in mm. ESR is maximum resistance in ohms at 100kHz and TA = 25°C. Listings are sorted by height
~TEXAS
3-210
SIZE (H x L x W)t
1.2 x 7.2 x 6
2.5 x 7.1 x 3.2
2.5 x 7.1 x 3.2
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75255
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT 1~~2tY,2~l~2f- ~~2~~~l91~!
APPLICATION INFORMATION
sense-pin connection
SENSE must be connected to OUT for proper operation of the regulator. Normally this connection should be
as short as possible; however, remote sense may be implemented in critical applications when proper care of
the circuit path is exercised. SENSE internally connects to a high-impedance wide-bandwidth amplifier through
a resistor-divider network, and any noise pickup on the PCB trace will feed through to the regulator output.
SENSE must be routed to minimize noise pickup. Filtering SENSE using an RC network is not recommended
because of the possibility of inducing regulator instability.
output voltage programming
The output voltage of the TPS7201 adjustable regulator is programmed using an external resistor divider as
shown in Figure 35. The output voltage is calculated using:
(1 )
where
Vref = 1.188 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 7-JlA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
.R2 = 169 kQ to set the divider current at 7 JlA and then calculate R1 using:
R1 =
(V0 _
1) . R2
(2)
V ref
OUtPUT VOLTAGE
PROGRAMMING GUIDE
DIVIDER RESISTANCE
OUTPUT
(ka)t
VOLTAGE
(V)
R1
R2
3.3
191
309
3.6
348
4
402
5
549
2.5
6.4
750
169·
169
169
169
169
169
TPS7201
5
VI
>2.7V 0.1 JlF
250 ka
IN
2
PG 1-"-_..... Power-Good
Indicator
8
OUT
IN
~
L-<0.4 V
4
Vo
OUT
EN
FB
GND
3
R2
I'"
---,
IL
10JlF
_
_ _ oJ
ESR=11
'I+
I
-::-
t 1% values shown.
Figure 35. TPS7201 Adjustable LOO Regulator Programming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-211
TPS7201Q,TPS7233Q,TPS7248Q,TPS7250Q
TPS7201V, TPS7233V, TPS7248V, TPS7250V
MICROPOWER LOW-DROPOUT (LDO) VOLTAGE REGULATORS
SLVS102C - MARCH 1995 - REVISED AUGUST 1995
APPLICATION INFORMATION
power dissipation and Junction temperature
Specified regulator operation is assured to a junction temperature of 125°C; the maximum junction temperature
allowable to avoid damaging the device is 150°C. These restrictions limit the power dissipation that the regulator
can handle in any given application. To ensure the junction temperature is within acceptable limits, calculate the
maximum allowable dissipation, PO(max), and the actual dissipation, Po, which must be less than or equal to
PO(max)·
The maximum-power-dissipation limit is determined using the following equation:
P
TJmax - TA
--=-~-~
O(max) -
RSJA
Where
TJmax is the maximum allowable junction temperature, Le.,150°C absolute maximum and 125°C
recommended operating temperature.
RaJA is the thermal resistance junction-to-ambient for the package, Le:, 172°C/W for the 8-terminal
SOIC and 238°C/W for the 8-terminal TSSOP.
.
TA is the ambient temperature.
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible.
~TEXAS
INSTRUMENTS
3-212
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVSI24A-JUNE 1995-
SEPTEMBER 1995
DPACKAGE
(TOP VIEW)
• Available in 3.3-V, 4.85-V, and 5-V
Fixed-Output and Adjustable Versions
• Integrated Precision Supply-Voltage
Supervisor Monitoring Regulator Output
Voltage
• Active-Low Reset Signal with 200-ms Pulse
Width
• Very Low Dropout Voltage ••• Maximum of
35 mVat 10 = 100 mA (TPS7350)
• Low Quiescent Current - Independent of
Load •.. 340 ~ Typ
• Extremely Low Sleep-State Current,
0.5 ~AMax
• 2% Tolerance Over Full Range of Load,
Line, and Temperature for Fixed-Output
Versions
• Output Current Range of 0 mA to 250 mA
• TSSOP Package Option Offers Reduced
Component Height For Critical Applications
G N O [ ] 8 RESET
EN
2
7 SENSEt/FB:j:
IN
IN
3
4
6
5
GNO
OUT
OUT
RESET
SENSEt/FB:j:
EN
IN
OUT
5
IN
OUT
PWPACKAGE
(TOP VIEW)
description
The TPS73xx devices are members of a family
of micropower low-dropout (LOO) voltage
regulators. They are differentiated from the
TPS71 xx and TPS72xx LOOs by their integrated
delayed microprocessor-reset function. If the
precision delayed reset is not required, the
designer should consider the TPS71xx and
TPS72xx.t
NC - No internal connection
t SENSE - Fixed voltage options only
(TPS7333, TPS7348, and TPS7350)
:j: FB - Adjustable version only (TPS7301)
AVAILABLE OPTIONS
OUTPUT VOLTAGE
M
-40°C to
125°C
NEGATIVE-GOING
RESET THRESHOLD
VOLTAGE
(V)
PACKAGED DEVICES
CHIP FORM
(V)
MIN
TYP
MAX
MIN
TYP
MAX
SMALL OUT·
LINE
(D)
PLASTIC DIP
(P)
4.9
5
5.1
4.55
4.65
4.75
TPS73500D
TPS73~~.. TPS735O<; ~E
TPS7350Y
4.75
4.85
4.95
4.5
4.6
4.7
TPS73480D
TP}l".V' f! 150 rnA simultaneously, pass element rOS(on) increases (see Figure 32) to a point where the resulting
dropout voltage prevents the regulator from maintaining the speCified tolerance range.
2. To calculate dropout voltage, use equation: VOO = 10 . rOS(on)
rOS(on) is a function of both output current and input voltage. The parametric table lists rOS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 32.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-219
TPS7301Q,lPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVSI24A.., JUNE 1995 - REVISED AUGUST 1995
=
TPS7333Q electrical characteristics at 10 10 mA, VI
SENSE shorted to OUT (unless otherwise noted)
TPS7333Q
PARAMETER
Output voltage
=4.3 V, EN =0 V, Co =4.7 J.LF(CSRt =1 n),
TEST CONDITIONSt:
TJ
VI = 4.3 V,
10= lOrnA
4.3 V S VI S 10 V,
5mASIOS250mA
10= 10mA,
VI = 3.23 V
25°C
-40°C to 125°C
VI = 3.23 V
Pass-element series I'$sistance
(3.23 V - VOllIO,
10 = 250 mA
VI = 3.23 V,
Input regulation
VI = 4.3 V to 10 V,
fiO iJAS lOS 250 mA
25°C
108
0.44
25°C
6
-40°C to 125°C
21
31
25°C
46
44
25°C
39
-40°C to 125°C
36
2
CO=4.7I1F
274
CO= 4O I1F
25°C
228
CO= 100I1F
25°C
159
-40°C to 125°C
Vo increasing
-40°C to 125°C
RESET hysteresis voltage
10(RESET) = -1 rnA
mV
mV
I1VNHz
I1Vrms
2.868
V
V
25°C
18
25°C
0.17
-40°C to 125°C
mV
dB
49
25°C
Vo decreasing
60
0
51
25°C
RESET trip-threshold voltage
32
120
-40°C to 125°C
RESET trip-threshold voltage
23
60
. 25°C
1=120Hz
0.6
29
-40°C to 125°C
IO=250mA
mV
150
0.8
-40°C to 125°C
1= 120 Hz
V
200
25°C
10 = 50 iJA
VI=2.8V,
60
-40°C to 125°C
10 = 50 iJA to 250 rnA, 4.3 V S VI S 10 V
RESET output low voltage
44
-40°C to 125°C
Output regulation
10 HzsIs 100 kHz,
CSRt=10
7
80
. 25°C
Output noise voltage
4.5
-40°C to 125°C
10 = 5 mA to 250 mA, 4.3 V S VI S 10 V
Output noise-spectral density
3.37
UNIT
8
25°C
10 = 250 mA,
MAX
3.3
3.23
25°C
VI=3.23V
Ripple rejection
TYP
-40°C to 125°C
10=100mA,
Dropout voltage
MIN
mV
0.4
0.4
V
t CSR refers to the total senes reSistance, .Includlng the ESR 01 the capacitor, any senes resistance added externally, and PWB trace resistance
to Co.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
.
INSTRUMENTS
3-220
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
TPS7301 Q., TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
=
TP$7348Q electrical characteristics at 10 10 mA, VI
SENSE shorted to OUT (unless otherwise noted)
TPS7348Q
PARAMETER
Output voltage
=5.85 V, EN =0 V, Co =4.7 IlF(CSRt =1 il),
TEST CONDITIONS*
VI = 5.85 V,
10=10mA
5.85 V S;VI S; 10 V,
5 mAs; 10S;25O mA
10= 10 mA,
VI =4.75 V
10= 100mA,
VI = 4.75 V
10=250mA,
VI = 4.75 V
Pass-element series resistance
(4.75 V - VOl/IO,
10=250mA
VI = 4.75 V,
Input regulation
VI=5.85Vtol0V,
50 !lAS; 10 S; 250 mA
Dropout voltage
Output regulation
10 = 50!lA to 250 mA, 5.85 V S; VI S; 10 V
10 = 50!lA
f=120Hz
10= 250 mA
Output noise-spectral density
Output noise voltage
4.75
25°C
2.9
6
28
37
-40°C to 125°C
52
25°C
70
_40°C to 125°C
0.28
25°C
9
25°C
28
25°C
42
25°C
45
39
25°C
39
-40°C to 125°C
35
mV
mV
mV
dB
50
2
CO=4.7I1F
25°C
410
CO= 10l1F
25°C
328
CO= IOO I1F
25°C
212
4.5
IlwJHz
I1Vrms
4.7
V
V
25°C
26
25°C
0.2
-40°C to 125°C
65
Q
53
25°C
10(RESETl = -1.2 mA, VI = 4.12 V
40
130
-40°C to 125°C
RESET hysteresis voltage
35
75
-40°C to 125°C
-40°C to 125°C
0.37
37
-40°C to 125°C
-40°C to 125°C
mV
91
0.52
-40°C to 125°C
Vo increasing
V
130
25°C
Vo decreasing
UNIT
8
25°C
RESET trip-threshold voltage
MAX
4.95
-40°C to 125°C
RESET trip-threshold voltage
RESET output low voltage
TYP
4.85
25°C
-40°C to 125°C
1.= 120 Hz
10HzS;fS;100kHz,
CSRt= 1 Q
MIN
-40°C to 125°C
10= 5 mA to 250 mA, 5.85 V S; VI S; 10 V
Ripple rejection
TJ
mV
0.4
0.4
V
t CSR refers to the total senes reSistance, Includmg the ESR of the capaCitor, any senes resistance added extemally, and PWB trace resistance
to CO.
:t: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303.- DALLAS. TEXAS 75265
3-221
TPS7301 Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TPS7350Q electrical characteristics at to = 10 mA, VI = 6 V, EN = 0 V, Co = 4.7 ~F(CSRt =1 Q), SENSE
shorted to OUT (unless otherwise noted)
TPS73500
PARAMETER
TEST CONDITION!N=
VI=6V,
10.= 10 rnA
6V"VI ~ 10V,
5 mA,;; 10 ,;;250 rnA
10=10mA,
VI =4.88 V
10= 100mA,
, VI =4.88 V
10=250mA,
VI = 4.88 V
Pass-element series resistance
(4,88 V - VOl/IO,
10=250mA
VI = 4.88 V,
Input regulation
VI =6Vto 10V,
50 IIA" 10 " 250 mA
Output voltage
Dropout voltage
Output regulation
10=50IlAto250mA,6V"VI,,10'V
10 =5011A
f=120Hz
10= 250 mA
Output noise-spectral density
Output noise vo~age
25°C
-40°C to 125°C
5.1
2.9
25°C
27
68
25°C
0.27
25°C
4
25°C
28
25°C
41
25°C
43
-40°C to 125°C
38
25°C
41
-40°C to 125°C
36
65
0
mV
mV
mV
53
dB
51
2
CO=4.7IlF
25°C
430
Co= 10llF
25°C
345
CO= 100llF
25°C
220
4.55
1lV/,[Hz
IlVrms
4.75
V
V
25°C
28
25°C
0.15
_40°C to 125°C
40
130
25°C
10(RESET) = -1.2 rnA, VI = 4.25 V
20
75
-40°C to 125°C
RESET hysteresis voltage
0.35
45
-40°C to 125°C
-40°C to 125°C
mV
88
0.5
-40°C to 125°C
-40°C to 125°C
35
125
25°C
Vo increasing
V
6
50
-40°C to 125°C
Vo decreasing
UNIT
8
-40°C to 125°C
RESET trip-threshold voltage
MAX
5
4.9
25°C
RESET trip-threshold voltage
RESET output low voltage
TYP
-40°C to 125°C
f=120Hz
10Hz"f,,100kHz,
CSRt=10
MIN
-40°C to 125°C
10= 5 rnA to 250 mA, 6V"VI" 10V
Ripple rejection
TJ
mV
0.4
0.4
V
t CSR refers to the total senes resistance, Including the ESR of the capacitor, any senes resistance added extemally, and PWB trace resistance
to CO.
:J: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient tempereture; thermal effects must be
taken imo account separately.
~TEXAS
3--222
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE 1995- REVISEDAUGUST1995
switching characteristics
PARAMETER
TEST CONDITIONS
TJ
TPS7301Q,TPS7333Q
TPS7348Q,TPS735OQ
MIN
RESET time-out delay
..
See Figure 5
TYP
25°C
140
-40°C to 125°C
100
UNIT
MAX
200
260
300
ms
electrical characteristics at 10 = 10 rnA, EN = 0 V, Co =4.7 ~F(CSRt = 1 Q), TJ = 25°C, SENSElFB
shorted to OUT (unless otherwise noted)
PARAMETER
TEST CONDITIONS:!:
TPS7301 Y, TPS7333Y
TPS7348Y, TPS7350Y
MIN
Ground current (active mode)
ENSO.5V.
VI=VO+1 V.
o rnA,;; 10,;250 rnA
Input current (standby mode)
EN=VI.
2.7VSVI,;10V
Output current limit
VO=OV.
VI = 10 V
Pass-element leakage current
in standby mode
RESET leakage current
340
tJA
0.01
tJA
A
EN=VI.
2.7V,;;VI,;10V
0.01
tJA
Normal operation.
Vat RESET = 10 V
0.02
tJA
165
°C
50
mV
0.001
tJA
2.7VSVIS10V
EN hysteresis voltage
EN input current
UNIT
MAX
1.2
Thermal shutdown junction temperature
EN logic low (active mode)
TYP
OVSVIS10V
V
2.05
Minimum VI for active pass element
V
1
V
Minimum VI for valid RESET
10(RESEn = -300 tJA
p
) refers to the total series resistance. includingeq
) of thecapacitor. any
CSR (
com ensation
series resistance
the uivalent series resistance (
ESR
series resistance added externally. and PWB trace resistance to CO.
:I: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-223
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TPS7301Yelectricai characteristics at 10 = 10 mA, VI = 3.5 V, EN = 0 V, Co = 4.7 IJ,F(CSRt = 10), TJ
= 25°C, FB shorted to OUT at device leads (unless otherwise noted)
TPS7301Y
PARAMETER
Reference voltage
(measured at FB)
Pass-element series resistance (see Note 2)
Input regulation
Output regulation
TEST CONDITIONS*
TYP
1.182
VI=3.5V,
10= lOrnA
VI =2.4V,
50IlA SIOSl50mA
VI =2.4V,
150 mAS IOS250 rnA
0.83
VI =2.9V,
50 IIA S 10 S 250 rnA
0.52
VI =3.9V,
50 IIA S 10 S 250 rnA
0.32
IIA S 10 S 250 rnA
0.23
VI=5.9V,
50
VI=2.5Vtol0V,
See Note 1
50 IIA S 10 S 250 rnA,
2.5 V S VI S 10 V,
See Note 1
10=5 rnA to 250 rnA,
2.5VSVIS10V,
See Note 1
10 = 50 IIA to 250 rnA,
Ripple rejection
f=120Hz
Output noise-spectral density
f=120Hz
Output noise voltage
MIN
10HzSfSl00kHz,
CSRt=10
RESET hysteresis voltage§
Measured at VO(FB)
RESET output low voltage§
VI=2.13V,
MAX
UNIT
V
0.7
0
3
mV
5
mV
7
mV
10= 50 IIA
59
10=250mA,
See Note 1
54
Co = 4.7 I1F
95
2
dB
I1V/..,[Hz
CO= 1O I1F
89
CO= 1OO I1F
74
10(RESET) = 400 IIA
0.1
V
0.1
nA
12
FB input current
I1Vrms
mV
t CSR refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
§ Output voltage programmed to 2.5 V wHh closed-loop configuration (see application information).
NOTES: 1. When VI <2.9Vand 10 > 150 rnA simultaneously, pass element rOS(on) increases (see Figure 32) to a point where the resulting
dropout voltage prevents the regulator from maintaining the specified tolerance range.
2. To calculate dropout voltage, use equation: VOO = 10 . rOS(on)
rOS(on) is a function of both output current and input voltage. The parametric table lists rOS(on) for VI = 2.4 V, 2.9 V, 3.9 V, and
5.9 V, which corresponds to dropout conditions for programmed output voltages of 2.5 V, 3 V, 4 V, and 6 V respectively. For other
programmed values, refer to Figure 32.
~TEXAS
INSTRUMENTS
3--224
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
=
=
TPS7333Yelectricai characteristics at 10 10 rnA, VI 4.3 V, EN
= 25°C, SENSE shorted to OUT (unless otherwise noted)
TPS7333Y
PARAMETER
Output vo~age
=0 V, Co =4.7IlF(CSRt =1 fJ), TJ
TEST CONDITIONS*
MIN
TYP
V,=4.3V,
10= 10 rnA
3.3
10=10mA,
V, = 3.23 V
4.5
10= 100 rnA,
V, = 3.23 V
44
10=250 rnA,
V, = 3.23 V
108
Pass-element series resistance
(3.23 V - VOl/IO,
10 = 250 rnA
V, = 3.23 V,
Input regulation
V, = 4.3 Vto 10V,
50 1lA,;; 10 ,;;250 rnA
Dropout voltage
Output regulation
UNIT
V
mV
Q
6
mV
10 = 5 rnA to 250 rnA, 4.3 V ,;; V, ,;; 10 V
21
mV
10 = 50 IlA to 250 rnA, 4.3 V,;; V,,;; 10 V
31
mV
Ripple rejection
1= 120Hz
Output noise-spectral density
1=120Hz
Output noise voltage
0.44
MAX
'0 = 50 IlA
51
10 =250 rnA
49
CO=4.7IlF
274
CO= 1O IlF
228
CO= 1OO IlF
159
2
10 Hz,;;l,;; 100 kHz,
CSRt= 1 Q
RESET hysteresis voltage
18
dB
IlV/..JHi
IlVrmS
mV
0.17
V
'OIRESETI = -1 rnA
t CSR refers to the total series resistance, including the ESR 01 the capacitor, any series resistance added externally, and PWB trace resistance
toCO·
:\: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; thermal effects must be
taken into account separately.
RESET output low voltage
V, =2.8 V,
~TEXAS
INSTRUMENTS
POST OFFICE
aox 655303 •
DALLAS, TEXAS 75265
3-225
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
=
TPS7348Yelectricai characteristics at 10 10 mA, VI
SENSE shorted to OUT (unless otherwise noted)
TPS7348Y
PARAMETER
Output voltage
=5.85 V, EN =0 V, Co =4.7IlF(CSRt =1 il),
TEST CONDITIONs*
MIN
TVP
VI = 5.85V.
10= 10mA
4.85
10=10mA.
VI = 4.75 V
2.9
10=100mA.
VI =4.75 V
28
10 =250 mA.
VI=4.75V
70
Pass-element series resistance
(4.75 V - VOl/IO.
10 =250 mA
VI = 4.75 V.
Input regulation
VI = 5.85 Vto 10V.
50 IIA s 10 S 250 mA
Dropout voltage
Output regulation
Ripple rejection
Output noise-spectral density
Output noise voltage
UNIT
V
mV
D
9
mV
10 = 5 mA to 250 mAo 5.85 V S VI S 10 V
28
mV
10 = 50 IIA to 250 mAo 5.85 V S VI S 10 V
42
mV
f= 120 Hz
10= sOlIA
53
10=250mA
50
CO=4.7I1F
410
CO= 10l1F
328
CO= lOO I1F
212
f= 120 Hz
10 Hz sfs 100 kHz.
CSRt=l D
2
RESET hyst,eresis voltage
RESET output low voltage
0.28
MAX
10(RESEn =-1.2 mAo VI =4.12 V
dB
I1V1VHZ
I1VnnS
26
mV
0.2
V
t CSR refers to the total senes resistance. Including the ESR of the capacitor. any senes resistance added externally. and PWB trace resistance
to CO.
:j: Pulse-testing techniques are used to maintain virtual junction temperature as close as possible to ambient temperature; !hennal effects must be
taken into account separately.
'~TEXAS
;INSTRUMENTS
3-226
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Vo
VI
---+----1 IN
RESET 1--'-*- Reset
I
I
I
I
EN
.......~-VO
0.111F
__
'+- Timeout
RESET
----"'
I
Delay -
10l1F
I
I
CSR
t .
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 5. Test Circuit and Voltage Waveforms
To Load
IN
OUTI--'-e-........
+--.
C
'---=r---...I
_!'J3cer
t
RL
CSR
~-.~~------~-
t Ceramic capacitor
Figure 6. Test Circuit for Typical Regions of Stability (Refer to Figures 28 through 31)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-227
TPS7301 Q,TP.S7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE1995-REVISED.,..UGUST1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
vs Output current
7
vs Input voltage
8
IQ
Quiescent current
IQ
Quiescent current
vs Free-air temperature
VOO
Oropout voltage
vs Output current
,WOO
Change in dropout voltage
vs Free-air temperature
11
VOO
Oropout voltage (TPS7301 only)
vs Output current
12
/lVO
Chimge in output voltage
vs Free-air temperature
13
Vo
Output voltage
vs Input voltage
14
9
10
Line regulation
15
Load regulation (TPS7301)
16
Load regulation (TPS7333)
17
Load regulation (TPS7348)
18
Load regulation (TPS7350)
19
Output voltage response from enable (EN)
20
Load transient response (TPS7301 or TPS7333)
21
Load transient response (TPS7348 or TPS7350)
22
Line transient response (TPS7301)
23
Line transient response (TPS7333)
24
Line transient response (TPS7348 or TPS7350)
25
Ripple rejection
vs Frequency
Output spectral noise density
vs Frequency
vs Output current (CO
26
27
=4.7I1F)
vs Added ceramic capacitance (Cd
Compensation series resistance (CSR)
vs Output current (CO
28
=4.7 I1F)
=10 I1F)
vs Added ceramic capacitance (CO
29
30
=10 11F)
31
Pass-element resistance
vs Input voltage
32
VI
Minimum input voltage for valid RESET
vs Free-air temperature
33
VIT-
Negative-going reset threshold
vs Free-air temperature
34
IOl(RESETI
RESET output current
vs Input voltage
35
Id
Reset time delay
vs Free-air temperature
36
td
Oistribution for reset delay
rOS(on)
,
~TEXAS
INSTRUMENTS
3-228
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
37
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
QUIESCENT CURRENT
QUIESCENT CURRENT
vs
vs
OUTPUT CURRENT
450
INPUT VOLTAGE
500
i---
.1.
TA = 25°C
I
425
C
::l.
I
~=
400
1:
375
8
c::l.
400
I
350
1:
~
=
(.)
TPS7350, V, = 6 V _
250
j
200
I
I
9
TPS7348, V, = 5.65 V _
325
I
o
100
50
100
150
50
o
250
200
o
1
2
3
vs
FREE·AIR TEMPERATURE
OUTPUT CURRENT
::l.
I
400
=
(.)
350
250
V
200
-50
L
9
10
V
/
V
TA = 25°C
./
..
c
9
8
0.15 ~---"'---'---"-----r--'"
I
300
7
DROPOUT VOLTAGE
450
I
6
vs
V,= 5.85 V
'0=250mA
§
.!!
0=
5
Figure 8
TPS7348Q
QUIESCENT CURRENT
1:
4
V,-Input Voltage - V
Figure 7
1:
~
TPS7348
II IJJ
I I(
150
'0 - Output Current - mA
500
K
A. ~ TPS7350 _
~~
I I
WI~h V~
b~ " TPS7301
Programmed to 2.5 V -
I
TPS7333, V, = 4.3 V
300
~ ~~K
y
0
9
......
I I
300
1:
=
350
I
,.,~ ~
TPS7333
(.)
3
~
0
TA = 25°C
10 = 250 mA
450
TPS73xx, V, = 10 V -
I'
V
>
I
8.
£!
0.1
~
15
&.
1/
~
I
0.05
8
>
/
-25
0
25
50
75
100
125
TA - Free-Air Temperature - °C
'0 - Output Current - mA
Figure 9
Figure 10
~1ExAs
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-229
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
CHANGE IN
D~OPOUT
TPS7301
DROPOUT VOLTAGE
VOLTAGE
vs
vs
OUTPUT CURRENT
1.6...------.----,-----.----.-----.
FREE-AIR TEMPERATURE
10
>
E
I
III
6
~
!i
4
8.
2
0
e
0
I
)~
II
CD
-2
.c
-4
c
(,)
1A~--4---+--~--
>
10
/
-8
-10
-50
V
/
V
1.21----1---+---+---+---/-1
I
;
"
/
>0 -6
.:__;,;L-j
I
$
0.41----1---+-~~~~-f>"..,£.----J
0.2~~~
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
00
125
50
100
150
Figure 11
OUTPUT VOLTAGE
vs '
vs
INPUT VOLTAGE
FREE-AIR TEMPERATURE
20
6
VI = VO(nom) + 1 V
10 = 100 mA
TA = 25°C
10 =250 mA
10
~
5
!
o
-
I
~
V
.5
f
r
..
5
=e
t
250
Figure 12
CHANGE IN OUTPUT VOLTAGE
I
200
10 - Output Current - mA
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
9
10
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7301Q
LINE REGULATION
2.52
20
TA=25°C
10 = 250 mA
15
>
LOAD REGULATION
TA=25°C
2.515
I- Vo Programmed to 2.5 V
E
I
t
~
i
10
I
5
~
.5
&
!
(J
-\
TPS7348
-5
,/
K
i""""
~
'-- TPS7333
-10
2.51
f
2.505
'$
2.5
~
1
o
o
>
I
III
TPS7350
~
0
I
~
'0
~
,
~
-15
2.495
..... VI=3.5V
VI=10V
2.49
2.485
-20
6
7
8
VI - Input Voltage - V
5
4
9
2.48
10
o
100
50
Figure 15
3.34
TPS7333Q
TPS7348Q
LOAD REGULATION
LOAD REGULATION
4.92
_I
I
:!!
~
'$
CL
'$
0
I
~
TA=25°C
4.9
3.32
>
I
3.31 ~
3.3
250
_I
4.91
3.33
III
CI
200
Figure 16
TA = 25°C
>
150
10 - Output Current - mA
~
III
CI
-
-.!!.=10V
4.87 ~
'$
4.86
~
4.85
I
4.84
0
~
3.28
4.88
:!!
~
VI=4.3V
3.29
4.89
~
VI = 5.85 V
1'r--
VI=10V
4.83
4.82
3.27
3.26
4.81
o
4.8
50
100
150
200
250
o
50
100
150
200
250
10 - Output Current - mA
10 - Output Current - mA
Figure 17
Figure 18
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-231
TPS7301 Q, TPS7333Q, TPS7348Q, TPS7350Q
LOW-DROPOUTVOLTAGE REGULATORS·
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TPS7350Q
OUTPUT VOLTAGE RESPONSE FROM
ENABLE (EN)
LOAD REGULATION
5.06
5.05 -
>
!
8.
5.02
5.01
5
'5
~
4.99
I
4.98
0
~
l'...
io
VI=6V
'-..
I tv
I
~
>. 5.03
:!1!
~
....
t
5.04
I
VO(nom) -
I
TA=25°C
V
I
~
I
TA = 25°C
RL=5000
Co = 4.71lF (CSR = 10)
No Input Capacitance
VI= 10V
,
6
4.97
4.96
4.95
4.94
o
50
100
150
200
10 - Output Current - mA
o
250
-2
20· 40
60
llme-1lS
Figure 19
Figure 20
TPS7301 (WITH Vo PROGRAMMED TO 2.5 V) OR TPS7333
LOAD TRANSIENT RESPONSE
=e
200
1
=
100
I
~
io
0
~
I"
TA = 25°C
VI=6V
CI=O
Co = 4.7 IlF (CSR = 10)
.5 -100
8.
5
oJ
-200
I
~
'
LOAD TRANSIENT RESPONSE
E
I
CD
Cl
200
!!
~
100
S,.
O
~
0
c
ic
1!
U
l~
&
IF
I"
TA=25°C
VI=6V
CI=O
CO=4.7!1 F (CSR=111)
-100
-200
I
o
~
105
~
55
C
~
5
I
,.
U
~
~
o
o
100
200
300
400
-45
500
_~
t- Tlme-!1S
Figure 22
TPS7301 WITH Vo PROGRAMMED TO 2.5 V
~
LINE TRANSIENT RESPONSE
I
100
~
50
t
~
.g-
.5
8.
-50
6
-100
c
I
I\.'\I'"
0
o
~
V
r-
TA=25°C
CI=O
r- Co = 4.7 !1F (CSR = 1 11)
.
~
400
t-TIme-!1s
Figure 23
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-233
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED ~ESET FUNCTION
SLVS124A-JUNE 1995-REVISEDAUGUSTl995
TYPICAL CHARACTERISTICS
,.
TPS7333
LINE TRANSIENT RESPONSE
~
I
200
~
100
5
S::>
1\V..
O
0
. .5
.f
z;
(J
I
A.
V
-50
TA=25°C
CI=O
Co = 4.7 I1F (CSR = 10)
-100
~
<:l
6.5
>
6.25
t
=
~
6
o
100
200
300
t-Tlme-l1s
400
5.75
500
I
i
>I
Figure 24
TPS7348 OR TPS7350
LINE TRANSIENT RESPONSE
~
I
t
~
i5
0
.5
.8.
100
50
\
0
I\.
V
V
-50
c
z;
(J
TA=25°C
CI=O
Co = 4.7 I1F (CSR = 10)
-100
I
~
<:l
I
'.
o
5.75
100
200
300
400
Figure 25
3-234
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
500
>
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE 1995-REVISEDAUGUST1995
TYPICAL CHARACTERISTICS
RIPPLE REJECnON
va
FREQUENCY
~~nm~Tmm-~mr~mr~mm-n~
""'"
=
'"
TA 25~C
No Input
50 H-H+IIIN-+!#IIIH+I+H Capacitance Added
VI=VO+1 V
lo=100mA
f-+-.................-++tt......H+ltLCO = 4.7 jtF (CSR = 1)
TPS7333
~
11
'II
I
40
I
TPS7348/
!IINl~
11111111 111111110 III
TPS7301 With
Vo Programmed
30 I--+l+ttHlI--+tttt/Ilt-t~lltifIft-+ to 2.5 V
i
TPS7350
20H-HffiIlH+m~~a.+H~~~-H~
II~
O~~~.w~~~~WL~WW-U~
10
100
1K
10 K
100 K
1M
10 M
f - Frequency - Hz
Figure 26
OUTPUT SPECTRAL-NOISE DENSITY
va
FREQUENCY
10
~S
TA = 25°C
No Input Capacitance Added
VI=VO+1 V
,
1\
::I.
I
~
co
c
11111111
I 11111111
I
. \ Co =4.7 jtF (CSR = 10)
..
~
.!
CO=10jtF(CSR=10)
Z
..I.
I!
I
~
0.1
I/)
!i
~
0
=
Co 100 jtF (CSR = 1 0)
I 11111111 I 11111111
0.01
10
100
1k
10k
f - Frequency - Hz
100k
Figure 27
~TEXAS- INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-235
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW;.DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS1~4A -
JUNE 1995 - REVISED AUGUST 1995
TYPICA~
CHARACTERISTICS
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE {CSR)t
COMPENSATION SERIES RESISTANCE {CSR)t
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
100
c:I
3c
~
~
~
~
=
10
~
::
I
t
o
i
iQ.
g
E
0.1
u
I
II:
0.1
I
II:
~
III
U
so
1S0
100
200
0.01
250
o
0.1
10 - Output Current - mA
0.2 0.3 0.4 O.S
0.6 0.7 O.B 0.9
1
Added Ceramic Capacitance - I1F
Figure 28
Figure 29
TYPICAL REGIONS OF STABILITY
TYPICAL REGIONS OF STABILITY
COMPENSATION SERIES RESISTANCE {CSR)t
COMPENSATION SERIES RESISTANCE {CSR)t
vs
vs
OUTPUT CURRENT
ADDED CERAMIC CAPACITANCE
c:I
TA=2S0C
VI=VO+1 V
10=2S0mA
CO= 10 I1F
c:I
I 10~~~~~~~~~~~~
·1
1----+-
i15
~~~g~ CO=
III
TA = 2S0C
VI=VO+1 V
~
~
I
u
0.1
I
NblnputCepacHorAdded
~
I
10 F
No Added
I1 Ceramic Capacitance
No Input Capacitor Added
c
~
~
.
No Input Capacitor Added
~
c
8
TA=2S0C
VI=VO+1 V
10 =2S0mA
Co 4.711F
c:I
0.1
I
II:
~
~
50
100
1S0
200
2S0
10 - Output Current - mA
0.1
0.2 0.3 0.4 O.S
0.6 0.7 O.B 0.9
1
Added Ceramic Capacitance -I1F
Figure 30
Figure 31
t CSA refers to the total series resistance, including the ESR of the capacitor, any series resistance added externally, and PWB trace resistance
taCO·
~TEXAS
~236
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A- JUNE 1995 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
PASS-ELEMENT RESISTANCE
MINIMUM INPUT VOLTAGE FOR VALID RESET
vs
vs
INPUT VOLTAGE
FREE-AIR TEMPERATURE
1.1
c::
I
8c:
~
1Ie
C
ell
E
ell
iii
.'"
fIl
11.
I
TA=25°C
VI(FB) = 1.12 V
0.9
0.8
£I
j
~,/
0.6
0.5
~1 r
~
0.4
'C
~
lo=250mA
,/
0.7
0.3
lo=l00mA
1.07
.5
E
"
.~
~
""'"
0.2
&.
V
./
1.06
I
>" 1.05
2
3
4
5
6
7
8
VI -Input Voltage - V
9
10
-50
-25
0
25
50
75
1.00
TA - Free-Air Temperature - °C
Figure 32
RESET OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE
4
15
>
E
I
l-
10
5
i
Ie
DI
c:
0
'0
t
iDI
-5
ell
Z
I
t!.
/
/
V
V
.-""
V
/
V
J
3.5
<
E
u"
IL = 10 mA
VOL,,0.4 V
TA = 25°C
3
I
C
~
2.5
s-
1.5
I
1m
I
.9
0.5
0
25
50
75
100
125
o
o
r--
I
...J
-25
r- TPS7350
I(
0
>"
L
I
2
"
/
I
'$
-10
-15
-50
125
Figure 33
NEGATIVE-GOING RESET THRESHOLD
!!!
.c
/
:i
0.1
:!i!
0
.c
V
/
I
/
~
-
r--
~PS)348
~PS7~33
~
2
TA - Free-Air Temperature - °C
Figure 34
3
4
5
6
7
VI - Input Voltage - V
8
9
10
Figure 35
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-237
TPS7301Q,TPS7333Q,TPS7~,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE 1995-REVISED AUGUST 1995 ..
TYPICAL CHARACTERISTICS
RESET DELAY TIME
va
DISTRIBUTION FOR RESET DELAY
FREE-AIR TEMPERATURE
5O~--~--T---~--~--~--~
197
451----i----
196
10
E
I
I
l'
1=
!
I
19;
194
193
'\
"","'
~
I
II:
I
:9
~
'S
25
:;)
i'...
192
"'- r--........ -.......
t
20
II
I:!
II
Do
191
190
-50
35
~
c
15
10
5
-25
0
25
50
75
100
TA - Free-Air Temperature _oC
125
0
180
185
Figure 36
195
Figure 37
~1EXAS
3-238
190
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
200
1c:I- Reset Delay TIme -
205
ms
210
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A-JUNE 1995 - REVISED AUGUST 1995
I"',
THERMAL INFORMATION
<,
",
In response, to system-miniaturization trends, integrated circuits are being offered in J()V(;e'rQ~ and fine-pitch
surface-mount packages. Implementation of many of today's high-performance devices ii\!~iij)ac~ges requires
special attention to power dissipation. Many system-dependent issues such as therma~C(.llJ~'9;ailfloW, added heat
sinks and convection surfaces, and the presence of other heat-generating componery'l$aff~the'P9wer-dissipation
limits of a given component.
/ ?
"""-",j
! /' /,. . ,
Three basic approaches for enhancing thermal performance are illustrated in th~(squ~or-'!
•
•
•
)'>'',,,'" ',("j /
Improving the power-dissipation capability of the PWB design
Improving the thermal coupling of the component to the PWB
Introducing airflow in the system
« '''-'''-""'" /
Z~
"'' <
~'soP
",,>'"
Figure 38 is an example of a thermally enhanced PWB layout for the 20-lead
package. This layout involves
adding copper on the PWB to conduct heat away from the device. Thr~.iQlo!~ component/board system is
illustrated in Figure 39. The family of curves illustrates the effect of incre,as,iligthesiz~t9'f the copper-heat-sink surface
area. The PWB is a standard FR4 board (L x W x H = 3.2 inch x 3.o/inCh ,0.062 inch); the board traces and heat
sink area are 1-oz (per square foot) copper.
I ( /
rI /)
Figure 40 shows the thermal resistance for the same system WithJ~e~~~Ja thermally conductive compound
between the body of the TSSOP package and the PWB copger rCiu.te~,tllyy beneath the device. The thermal
conductivity for the compound used in this analysis is 0.815 W/rri)d:~"~
Using these figures to determine the system RaJA allows th~~{~'~er-dissiPation limit to be calculated with
/'",>
,,,-,0,>,
the equation:
/
"-.,
( /'c. \
'"
T JCmax) - T A
PO(max) = R
<\'" " Y . j
6JA(system)
"'''- "'""
~"~
Where
f)
TJ(max) is the maximum allowable juncti¢l~perature or 125°C i.e., 150°C absolute maximum and 125°C
maximum recommended operating te~~41~pecified operation.
"
/! })
This limit should then be applied to the i,~
,,'. I pow,er'i1issipated by the TPS73xx regulator. The equation for
calculating total internal power dissipatioryof't!fEi T~1 xx is:
"
PO(total) =
,
"\
(V, - VO). '0 + ~, \t~",))
f. )'''' """",:,/
Be.::ause the quiescent current of the ~~familY is very low, the second term is negligible, further simplifying
/'~; \
the equation to:
"'" ,"Ii
PO(total) =
(V, - Vokctg:~~::/
IFR4A~~~~~
For a 20-lead TSSOP
with thermally conductive compound between the board and the device
body, where TA 55°C, airfl~~n, and copper heat sink area 1 cm2, the maximum power-dissipation limit
c,.a~t~ calculated. As in,?~!~1V"~~ 40, the system RaJA is 94°CIW; therefore, the maximum power-dissipation
=
=
F/''''\\
Iml IS:
J~
_ 125"C - SS"C _
"
94 CjW
- 745 mW
_ T
PO(max)
-~"~"
0
/~'i-p~
m)
,,"-.
If the system illi~IeJ:!1~.:tPS7348 regulator where V,
!!
,
o~~~o) .1 0
PO,etC
{".:;
=6 V and 10 =385 rnA, the internal power disaipationis:
= (6 - 4.85)·0.385 = 443 mW
{.!
,
'
~1ExAs
INSTRUMENTS ,
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-239
TPS7301Q, TPS7333Qj TPS7348Q, TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WiTH INTEGRATED 'DELAYED RESET FUNCTION
8lVS124A- JUNE 1995 -'REVISED AUGUST 1995
THERMAL U'IIFORMATIO,N
A
ComparingPO{total) with PO{max),rellealsthat the power dissipation in this example doesJlOL
the maximum
limit. When itdoes, one oftwo <;or~'ilctiye actions c~n, be taken. The power-dissipation limit ~, •
", y increasing
either the airflow or the heat-sink area. Alternatively; the internal power dissipation of tl:l~rSg~to"t'Can be lowered
by reducing ,either the input voltage orthe load current. In either case, th~ above calcuJ~~.~~f6ge repeated with
/ / '. "~''-.-J
the new system parameters.
1-----:------------1
ji 1/
~"J
"~':J
1
I
I
I
I
I
I
I
I
I
IL
i)
I ";,"'/! / ;
".,"'v, '/
I '
I
A",
! /~',0-'",
- - --,
/' /
I
!,-c::;:-"r-'
(~,,/II"!
I
L------,-""'.... :J'.:
.".""_'"
'v..;"-"'~ '"''
Figure 38. Thermally Enhanced PWB L~puf~of~$'cale) for the 2D-Pin TSSOP
/ / ))
;J( THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
THERMAL RESISTANCE, JUNCTION-TO-AMBIEN....
,
~
I
C
.!!
.a
e
.,:
190
~~
~
I
C
.!!! 170
.a
E
"i'
~"i'
~c
'G
0
c
.
:::I
2.7 V
0.111F
L-<0.5V
T
RESET 1--_........ To System
Reset
-=EN
OUTI----~--~~Vo
FBi---'"
GND
R2
OUTPUT
VOLTAGE
R1
R2
UNIT
2.5V
191
169
kQ
3.3V
309
169
kQ
3.6V
348
169
kQ
4V
402
169
kQ
5V
549
169
kQ
6.4V
750
169
kQ
Figure 42. TPS7301 Adjustable LOO Regulator Programming
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-243
TPS7301Q, TPS7333Q,TPS7348Q, TPS7350Q
LOW-DRO·POUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A~JUNE 1995-REVISEDAUGUST 1995
APPLICATION INFORMATION
undervoltage supervisor function
The RESET output of the TPS73xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS73xx monitors the output voltage ofthe regulator
to detect the undervoltage condition. When that occurs. the RESET output transistor turns on taking the RESET
signal low.
On power-up, the output voltage tracks the input voltage. The RESET output becomes active (low) as VI
approaches the minimum required for a valid RESET signal (specified at 1.5 V for 25°C and 1.9 V over full
recommended operating temperature range). When the output voltage reaches the appropriate positive-going
input threshold (VIT+), a 200-ms (typ) timeout period begins during which the RESET output remains low. Once
the timeout has expired, the RESET output become inactive. Since the RESET output is an open-drain NMOS,
a pull-up resistor should be used to ensure that a logic-high signal is indicated.
The supply-voltage-supervisor function is also activated during power-down. As the input voltage decays and
after the dropout voltage is reached, the output voltage tracks linearly with the decaying input voltage. When
the output voltage drops below the specified negative-going input threshold (VIT- - see electrical
characteristics tables), the RESET output becomes active (low). It is important to note that if the input voltage
decays below the minimum required for a valid RESET, the RESET is undefined.
Since the circuit is monitoring the regulator output voltage, the RESET output can also be triggered by disabling
Examples of fault conditions
include a short circuit on the output and a low input voltage. Once the output voltage is reestablished, either by
reenabling the regulator or removing the fault condition, then the internal timer is initiated, which holds the
RESET signal active during the 200-ms (typ) timeout period.
the regulator or by any fault condition that cauSes the output to drop below VIT_
NOTE:
VIT+ = VIT _ +Hysteresis
output noise
The TPS73xx has very low output noise, with a spectral noise density < 2 J.l.V/..JFiZ. This is important when
noise-susceptible systems, such as audio amplifiers, are powered .by the regulator.
regulator protection
The TPS73xx PMOS-pass transistor has a built-in back diode that safely conducts reverse currents when the
input voltage drops below the output voltage (e.g., during power down). Current is conducted from the output
to the input and is not internally limited. If extended reverse voltage is anticipated, external limiting might be
appropriate.
The TPS73xx also features internal current limiting and thermal protection. During normal operation, the
TPS73xx limits output current to approximately 1 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 165°C, thermal-protection circuitry shuts it down. Once the device has cooled, regulator
operation resumes.
~TEXAS
3-244
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TPS7301Q,TPS7333Q,TPS7348Q,TPS7350Q
LOW-DROPOUT VOLTAGE REGULATORS
WITH INTEGRATED DELAYED RESET FUNCTION
SLVS124A - JUNE 1995 - REVISED AUGUST 1995
APPLICATION INFORMATION
power dissipation and junction temperature
The junction temperature must be held to 150°C or less to ensure proper regulator operation, which limits the
power dissipation the regulator can handle in any given application. To ensure the junction temperature is within
acceptable limits, calculate the maximum allowable dissipation, PO(max), and the actual dissipation, Po, which
must be less than or equal to PO(max)'
The maximum-power-dissipation limit is determined using the following equation:
P
-
O(max) -
TJmax - TA
--"--=-----''-'
RSJA
Where
TJmax is the maximum allowable junction temperature, i.e.,150°C absolute maximum and 125°C
recommended operating temperature.
RaJA is the thermal resistance junction-to-ambient for the package, i.e., 172°CIW for the 8-terminal
SOIC and 238°CIW for the 8-terminal TSSOP.
TA is the ambient temperature.
The regulator dissipation is calculated using:
Power dissipation resulting from quiescent current is negligible.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-245
3-246
f.U\723C, J.U\723M, IlA723Y
PRECISION VOLTAGE REGULATORS
• 150-mA Load Current Without External
Power Transistor
!1A723C ••• 0 OR N PACKAGE
!1A723M •.. J PACKAGE
(TOP VIEW)
• typically 0.02% Input Regulation and
0.03% Load Regulation (1JA723M)
• Adjustable Current Limiting Capability
CURR LIM
CURRSENS
• Input Voltages to 40 V
• Output Adjustable From 2 V to 37 V
• Direct Replacement for Fairchild 1JA723C
and 1JA723M
NC
FREOCOMP
2
Vcc+
Vc
3
OUTPUT
IN+
REF
Vz
NC
description
!1A723M ••• U PACKAGE
(TOP VIEW)
The lJA723C and lJA723M are precision monolithic integrated circuit voltage regulators featuring
high ripple rejection, excellent input and load
regulation, excellenttemperature stability, and low
standby current. The circuit consists of a
temperature-compensated reference voltage amplifier, an error amplifier, a 150-mA output
transistor, and an adjustable output current limiter.
CURRSENS
IN-
8 Vcc+
Vc
Vcc-
The lJA723C and lJA723M are designed for use in
positive or negative power supplies as a series,
shunt, switching, or floating regulator. For output
currents exceeding 150 rnA, additional pass
elements may be connected as shown in
Figures 4 and 5.
The lJA723C is characterized for operation from
O°C to 70°C. The lJA723M is characterized for
operation over the full mifltary temperature range
of -55°C to 125°C.
CURR LIM
FREOCOMP
2
OUTPUT
!1A723M ••• FK PACKAGE
(TOP VIEW)
11.
~
~
::::i
0
a:
0
§ooo~
OZZZu.
CURRSENS
NC
INNC
IN+
4
5
6
7
8
3 2 1 2019
18
17
16
15
14
9 10 11 12 13
U.
W
a:
Vcc+
NC
Vc
NC
OUTPUT
000 N
OZZ>
>
NC - No internal connection
~TEXAS ..
Copyrtght © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-247
J,JA723C, J.lA723M, J,JA723V
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
functional block diagram
FREQCOMP
TemperatureCompensated
Reference Diode
Vc
IN-
SerlesPasa
Transistor
REF
IN+
Regulated
Output
r----...,
VCC-
CURR
CURR
SENS
LIM
I
I
D, FK, J, and N
~~ckages Only
I
I
L _ _ _ _ ..J
schematic
5000
1 kn
25kn
1 kn
15kn
OUTPUT
--.---,
6.2 V
Vz
1000
D, FK, J, and N
Packages Only
I
L _ _ _ _ _ ..J
30kn
+ - - - - - - - FREQ COMP
3000
5kn
2OkO
J-------CURR LIM
1500
L-------CURRSENS
VCCREF
IN+
IN-
Resistor and capacitor values shown are nominal.
~TEXAS
3-248
INSTRUMENTS
POST OFFICE BOX 655303. 9ALLAS, TEXAS 75265
~A723C,~723M,~A723Y
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
~723Y
chip i.,formation
This chip, when properly assembled, displays characteristics similar to the JlA723C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
~-------------------47------------------~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
NC
CURR LIM
CURRSENS
ININ+
REF
VCC-
(1)
(14)
(2)
(13)
(3)
(12)
(4)
IlA723Y
(11)
(5)
(10)
(6)
(9)
(7)
(8)
NC
CHIP THICKNESS: 15 MILS TYPICAL
FREQCOMP
BONDING PADS: 4 x 4 MILS MINIMUM
VCC+
TJmax
Vc
TOLERANCES ARE ±10%.
=150°C
OUTPUT
ALL DIMENSIONS ARE IN MILS.
Vz
TERMINALS 1, 8, AND 14 ARE NOT
CONNECTED
NC
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3--249
~723C, ~723M, ~723Y
PRECISION VOLTAGE REGULATORS
SLVS057B :"AUGUST 1972 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwlse'tloted)t
Peak voltage from VCC+ to VCC- (tw ::; 50 ms). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. SO V
Continuous voltage from VCCi-'to VCC- ....•............. ,.................................. 40 V
InpuHo-output voltage differential . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . .. . .. . . . . .. . . . . . . . .. 40 V
Differential input voltatle toerrQ~ amplifier .................................................... ±S V
• Voltage between noninverting input and Vcc- : ...........................,...................... 8 V
Current from Vz ................ .' .... '. . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . .. . . .. 25 rnA
Current from REF ........................... ~ ....... : ....................... '............. 1S'mA
Continuous total dissipation (see Note 1): ............................... See Dissipation Rating Table
Operatingfree-airtemperature range, TA: ~723C ...................................... O°C to 70°C
,
~723M
........................... : ..... -5S0Ct0125°C
Storage temperature range, Tstg ...........................................-....... -6SoC to 150°C
Case temperature for 60 seconds, T c: FK package ........................... , ... ,.......... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or U package ................. 300°C
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: D or N package .. . . . . . . . . . . . . . 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the devica. These are slress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilitY.
NOTE 1: Power dissipation [~standby) + I(refjl VCC + [Vc - Vol 10·
=
DISSIPATION RATING TABLE
PACKAGE
TA s; 25"C pOWER
RATING
DERATING FACTOR
DERATE
ABOVETA
TA=70OC
POWER RATING
0
950mW
'7.6mWI"C
25°C
608mW'
FKandJ
1000mW
11.0mWI"C
59°C
879mW
N
1000mW
675,mW
'9.2rriW1"C
5.4mW/oC
41°C
733mW
25°C
432mW
U
TA=125°C
POWER RATING
274mW
135mW
recommended operating conditions
MIN
MAX
9.5
40
V
Output voltage, Vo
2
37
V
Input-Io-outpul voltage differential, Vc - Vo
3
38
V
150
mA
Input voltage, VI
Outpul current, 10
:IITEXAS "
, 'INSTRUMENTS
3-250
POST OFFIC(E sox 6s5303 • PAlLAS, TEXAS 75265
UNIT
~723C,~723M,~A723Y
PRECISION VOLTAGE REGULATORS
SLVS057B-AUGUST 1972- REVISED AUGUST 1995
electrical characteristics at specified free-air temperature (see Notes 2 and 3)
PARAMETER
Input regulation
Ripple rejection
TEST CONDITIONS
VI=12VtoVI =15V
VI = 12 V to VI = 40 V
25°C
1
VI=12VtoVI =15V
Full
range
-
MAX
MIN
JU\723M
TVP
0.1
1
5
0.2
2
3
3
Cre! = 0
25°C
74
74
1=50 Hz to 10 kHz,
Crel'" 51lF
25°C
86
86
25°C
-0.3
-2
-0.3
UNIT
mVN
dB
-1.5
-6
-6
Full
range
MAX
1
1=50 Hz to 10 kHz,
mVN
7.15
7.5
7.15
7.35
V
25°C
2.3
4
2.3
3.5
rnA
Full
range
0.003
0.Q15
0.002
0.015·
RSC=10Q,
VO=O
BW = 100 Hz to 10 kHz,
Cref=O
25°C
65
65
25°C
20
20
BW = 100 Hz to 10 kHz,
Cref=5IlF
25°C
2.5
2.5
25°C
VI = 30 V,
10=0
Temperature coefficient 01
output voltage
Output noise voltage
JU\723C
TVP
0.1
Relerence voltage, Vrel
Short-circuit output current
MIN
25°C
Output regulation
Standby current
TAt
6.8
6.95
°IorC
mA
IlV
·On products compliant to MIL-STD-883, Class B, thiS parameter IS not production tested.
t Full range tor 1lA723C is O°C to 70°C and tor 1lA723M is -55°C to 125°C.
NOTES: 2. For all values in this table, the device is connected as shown in Figure 1 with the divider resistance as seen by the error amplifier
'" 10 kO. Unless otherwise specified, VI = VCC+ = Vc = 12 V, Vee- = 0, Vo = 5 V, 10 = 1 rnA, Rse = 0, and Cret = O.
3. Pulse-testing techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
3-251
jlA723C, jlA723M, jlA723Y
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
=
electrical characteristics, TA 25°C (see Notes 2 and 3)
PARAMETER
Input regulation
Ripple rejection
TEST CONDITIONS
/1A723Y
MIN
TYP
0.1
VI=12VtoVI =15V
1
VI=12VtoVI =40V
f =50 Hz to 10 kHz,
Cref=O
74
f = 50 Hz to 10 kHz,
Cref = 511F
86
MAX
UNIT
mVN
dB
Output regulation
-0.3
Reference voltage, Vref
7.15
V
2.3
rnA
rnA
Standby current
VI=30V,
Short-circuit output current
RSC=10Q,
VO=O
BW = 100 Hi to 10 kHz,
Cref=O
65
BW = 100 Hz to 10 kHz,
Cref= 511F
2.5
Output noise voltage
10=0
mVN
20
I1V
NOTES: 2. For all values in this table, the device is connected as shown in Figure 1 with the divider resistance as seen by the error amplifier
,,; 10 kQ. Unless otherwise specified, VI = VCC+ = Vc = 12 V, VCC- = 0, Va = 5 V, 10 = 1 rnA, RSC.= 0, and Cref = O.
3. Pulse-testirig techriiques must be used that will maintain the junction temperature as close to the ambient temperature as possible.
~1ExAs
3-252
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~723C,~723M,~A723Y
PRECISION VOLTAGE REGULATORS
SLVS057B -AUGUST 1972 - REVISED AUGUST 1995
APPLICATION INFORMATION
Table 1. Resistor Values (kn) for Standard Output Voltages
OUTPUT
VOLTAGE
(V)
3.0
APPLICABLE
FIGURES
(SEE NOTE 4)
1,5,6,9,11,
FIXED
OUTPUT
±5%
OUTPUT
ADJUSTABLE
±10% (SEE NOTE 5)
OUTPUT
VOLTAGE
(V)
R1
R2
R1
P1
P2
(1Ul)
(1Ul)
(1Ul)
(1Ul )
(1Ul )
4.12
3.01
1.8
0.5
1.2
100
3.57
3.65
1.5
0.5
1.5
2.15
4.99
0.75
0.5
2.2
APPLICABLE
FIGURES
(SEE NOTE 4)
FIXED
OUTPUT
±5%
OUTPUT
ADJUSTABLE
±10% (SEE NOTE 5)
R1
R2
R1
(1Ul)
(1Ul)
(1Ul)
P1
(kQ)
(1Ul )
7
3.57
105
250
7
3.57
-6
3,10
R2
2.2
10
91
255
2.2
10
240
3.57
2.43
1.2
0.5
0.75
12(4)
3.6
1,5,6,9,11,
12(4)
5.0
1,5,6,9,11,
12(4)
6.0
1,5,6,9,11,
(Note 6)
1.15
6.04
0.5
0.5
2.7
-9
3, 10
3.48
5.36
1.2
0.5
2.0
1.87
7.15
0.75
1.0
2.7
-12
3, 10
3.57
8.45
1.2
0.5
3.3
4.87
7.15
2.0
1.0
3.0
-15
3, 10
3.57
11.5
1.2
0.5
4.3
7.87
7.15
3.3
1.0
3.0
-28
3, 10
3.57
24.3
1.2
0.5
10
21.0
7.15
5.6
1.0
2.0
-45
8
3.57
41.2
2.2
10
33
12(4)
9.0
2,4,(5,6,
9,12)
12
2,4,(5,6,
9,12)
15
2,4,(5,6,
9,12)
28
2,4,(5,6,
9,12)
45
7
3.57
48.7
2.2
10
39
-100
8
3.57
95.3
2.2
10
91
75
7
3.57
78.7
2.2
10
68
-250
8
3.57
249
2.2
10
240
NOTES: 4. 4The Rl/R2 divider may be across ei1her Vo or V(re!). If the divider is across V(ref), use the figure numbers without parentheses.
If the divider is across VO, use the figure numbers in parentheses.
5. To make the voltage adjustable, the Rl/R2 divider shown in the figures must be replaced by the divider shown below.
R1
PI
R2
Adjustable Output Circuit
6. For Figures 3,8, and 10, the device requires a minimum of 9 V between Vee + and Vee- when Vo is equallo or more positive than
-9V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
3-253
!lA723C, !lA723M, !lA723Y
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
APPLICATION INFORMATION
Table 2. Formulas for Intermediate Output Voltages
Outputs from 2 V to 7 V
See Figures 1,5,6,9, II, 12 (4)
and Note 4
Vo
= V(rl(t)
x Rl ~ R2
Outputs from 4 V to 250 V
See Figure 7
and Note 4
V _ V(ret)
R2 - Rl
0--2- x
Rl
R3
Outputs from 7 V to 37 V
See Figures2,4,(5,6,9,II, 12)
and Note 4
_
Vo - V(ret)
X
Rl
+ R2
R2
Current Limiting
I
- 0.65 V
RSC
(limit) -
= R4
Outputs from -6 V to -250 V
See Figures 3, 8, 10 and
Notes 4 and 6
Vo
R3
=
V (ret)
- - 2 - x Rl
+ R2
Rl
= R4
Foldback Current Limiting
See Figure 6
V OR3
I (knee) ""
I
OS
+ (R3 + R4) 0.65 V
RSCR4
"" 0.65 V x R3 + R4
R4
RSC
NOTES: 4. The Rl/R2 divider may be across either Vo or V(ref). If the divider is across V(ref), use figure numbers without parentheses. If the
divider is across VO, use the figure numbers in parentheses.
6. For Figures 3, 8, and 10, the device requires a minimum of 9 V between VCC+ and VCC- when Vo is equal to or more positive than
-9V.
~TEXAS
3-254
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
~723C,~723M,~723Y
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
APPLICATION INFORMATION
VCC+
Vc
VCC+
OUTPUT
REF !lA723·
Vz
REF !lA723
CURR UM ~~IV\,._ Output,
CURRSENS
C(ref)I
Vo
IN+
Vz
RSC
Regulated
R1
Vc
OUTPUT
Regulated
CURR UM t--_-'V'rv-_ Output,
R3
(see Notes
A and B)
Vo
CURRSENS
IN+
INVCC- FREQ COMP
R2
R1
R2
100pF
Figure 1. Basic Low-Voltage Regulator
(Vo 2 V to 7 V)
Figure 2. Basic High-Voltage Regulator
(Vo = 7 V to 37 V)
=
' A
NOTES.
.
R3
x R2 I
..
= Rl
Rl + R2 or minimum aVO
B. R3 may be eliminated lor minimum component count. Use direct connection (i.e., R3
2ka
(aee Note C)
Vc
OUTPUT
REF !lA723
VZHI----t-l
= 0).
VCC+
R4
3ka
IN+
R3=
REF
!lA723
CURRUM
CURR UM
CURRSENS
IN-
2N3997
Vz
CURRSENS
J---"
IN+
INVCC- FREQ COMP
Regulated
Output, Vo
VCC- FREQ COMP
3ka
OUTPUT
2N5001
Regulated
Output, Vo
R1
R1
500pF
100pF
R2
Figure 3. Negative-Voltage Regulator
Figure 4. Positive-Voltage Regulator
(External N-P-N Pass Terminator)
NOTE C: When 10-lead J,lA723U devices are used in applications requiring VZ, an external 6.2-V regulator diode must be connected in series
with OUTPUT.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-255
IlA723C, J,1A723M, JlA723Y
PRECISION VOLTAGE REGULATORS
SLVS057B -AUGUST 1972 - REVISED AUGUST 1995
APPLICATION INFORMATION
60n
2NSOO1
, VCC+
Rse
Ve
OUTPUT
REF !lA723
Vz
OUTPUT
!lA723
REF
Vz
CURRSENS
INFREQCOMP
RSC
Regulated
Output, Vo
R3
CURRLlM
R1
CURR LIM
R1
Regulated
Output, Vo
CURRS,ENS
R4
R2
R2
Vo
~
-=-
-=-
-=-
FIg!Jre 5. Positive-Voltage Regulator
(External P-N-P Pass Transfstor)
Figure 6. Foldback Current Limiting
10kn
2NS241
{see Note A)
1N1826
10kO
Vz
R4
3kO
CURR LIM
R1
IN+
R3
3kO
R2
-=
CURRSENS
R2
RSC=1
n
eURRLlM
+-+--t-IIN+
IN-
VCC- FREQ COMP
R1
Regulated
Output, Vo
2NS241
(see Note A)
CURRSENS
INVCC- FREQ COMP
SOOpF
R3
3kO
R4
SOOpF
'---i~HII-3_kO_....._ _-t-_ _~l-~_ Regulated
Figure 7. Positive Floating Regulator
Output, Vo
Figure 8. Negative Floating Regulator
NOTE A: When 10-lead f,lA723U devices are used in applications requiring VZ, an extemal 6.2-V regulator diode must be connected in series
with OUTPUT.
~TEXAS
INSTRUMENTS
3--256
POST OFFICE I19X 655303 • DALlAS, TEXAS 75265
~723C,~A723M,~A723Y
PRECISION VOLTAGE REGULATORS
SLVS057B - AUGUST 1972 - REVISED AUGUST 1995
APPLICATION INFORMATION
3kn
Vc
VCC+
II
OUTPUT
I1A723
Vz
REF
Regulated
Output, Vo
CURRLIM
R1
CURRSENS
1 kQ
L=1.2mH
(see Note C)
IN+
0.111F
T
1 MQ
R2
-=- -=-
-=-
-=-
Figure 9. Positive Switching Regulator
(see Note A)
VCC+
R2
Vc
OUTPUT
REF
0.111F
!lA723
1 kQ
R3
3kQ
2N3997
220Q
(see Note B)
Vz 1---1---+-1
2NS004
CURRLlM
1 kn
CURRSENS
IN+
R1
1 MQ
INVCC- FREQCOMP
R4
3kn
1SpF
II
1N4005
L=1.2mH
(see Note C)
Regulated
Output, Vo
Figure 10. Negative Switching Regulator
NOTES: A. The device requires a minimum of 9 V between VCC+ and VCC- when Vo is equal to or more positive than -9 V.
B. When 1O·lead !lA723U devices are used in applications requiring VZ, an extemaI6.2-V regulator diode must be connected in series •
with OUTPUT.
C. Lis 40 turns of No. 20 enameled copper wire wound on Ferroxcube P36122·3B7 potted core or equivalent, with a 0.009-inch air gap.
~TEXAS .
INSTRUMENTS
- POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-257
/-lA723C, !-LA723M, !-LA723Y
PRECISION VOLTAGE REGULATORS
SLVS057B -AUGUST 1972": REVISED AUGUST 1995
APPLICATION INFORMATION
RSC'
REF
R~ulated
OUTPUT
1lA723
Output, Vo
Vz
CURR LIM.,
R1
CURRSENS
IN+
R2
2k.O
Input From
Series 54174 LogIc
=
NOTE A: A current-limit transistor may be used for shutdown if current limiting is not required.
Figure 11. Remote Shutdown Regulator With Current Limiting
VI
1000
VCC+
REF
Vc
(_Note A)
OUTPUT
1lA723
V2: t-_",1",k.Ov--+-I
2N3997
CURI'ILIM
R1
IN+
Regulated
Output, Vo
CURRSENS
R2
NOTE A: When 1Q-lead 1lA723U devices are used in applications requiring Vz. an extemal 6.2-V regulator diode must be connected in series
with OUTPUT.
.
Figure 12. Shunt Regulator
~TEXAS
3-258
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
.
J.lA7800 SERIES
POSITIVE·VOLTAGE REGULATORS
•
•
•
•
•
•
•
KCPACKAGE
(TOP VIEW)
3-Terminal Reg\.llators
Output Current Up to 1.5 A
Internal Thermal Overload Protection
High Power Dissipation Capability
Internal Short-Circuit Current LImiting
Output Transistor Safe-Area Compensation
Direct Replacem,nts for Fairchild J1A7800
Series
The common lerminal is in electrical
contact with Ihe mounting base.
TO-220AB
description
This series of fixed-voltage monolithic integratedcircuit voltage regulators is designed for a wide
range of applications. These applications include
on-card regulation for elimination of noise and
distribution problems associated with single-point
regulation. Each ofthese regulators can deliver up
to 1.5 A of output current. the internal current limiting and thermal shutdown features of these regulators make
them essentially immune to overload. In addition to use as fixed-voltage regulators, these devices can be used
with external components to obtain adjustable output voltages and currents and also used as the power-pass
element in precision regulators.
'The 'J.lA7800C series is characterized for operation over the virtual junction temperature .range of O°C to
125°C. The IIA78050 and 1lA78120 are characterized for operation over the virtual junction temperature range
of -40°C to 125°C.
TJ
AVAILABLE OPTIONS
PACKAGED DEVICES
VO(nom)
PLASnC FLANGE-MOUNT
(V)
eKC)
CHIP FORM
(V)
O°Clo 125°C
5
6
8
8.5
10
12
15
18
24
!lA7805CKC
!lA7806CKC
!lA7808CKC
!lA7885CKC
!lA7810CKC
!lA7812CKC
!lA7815CKC
!lA7818CKC
!lA7824CKC
!lA7805Y
!lA7806Y
!lA7808Y
!lA7885Y
!lA7810Y
!lA7812Y
!lA7815Y
!lA7818Y
!lA7824Y
-40°C 1012~oC
5
12
!lA780SOKC
!lA7812QKC
-.........
~lExAs
~
,
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-259
JlA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVSD56A - MAY 1976 - REVISED AUGUST 1995
schematic
r-~--------~----~~~~--~~INPUT
H-----t--<~----*-.--4-
~1ExAs
3-260
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
IlA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
~78xxY
chip information
These chips, when properly assembled, display characteristics similar to the J,lA78xxC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
COMMON
-::' 90
--=
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
--=
TJmax=150°C
TOLERANCES ARE ±10%.
--=
ALL DIMENSIONS ARE IN MILS.
~14r----------------70-----------------.~1
1'1'1',1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-261
J.tA7800 SERIES
,
POSITIVE.;VOLTAGE REGULATORS
SLVS056A- MAY i976 - REVISED AUGUST 1995
absolute maximum ratings over operating temperature ranges (~nless otherwise noted)t
Input voltage, VI:
~7824C
.......... ;...................................................... 40 V
All others .......................................................... ;...... 35 V
Continuous total power diSSipation at (or below) 25°C free-air temperature (see Note 1) ............. 2 W
Continuous total power dissipation at (or bE!low) 90°C case temperature (see Note 1) .............. 15 W
Operating free-air, TAl case, T6, or virtual junction, TJ, temperature range ................. -40 to 150°C
Storage temperature range, Tstg ..................................................... -65 to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratlngll· may cause pem1anent damage to the ~ice. These are stress ratlngll only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute·maximum·rated,conditions for extended periods may affect device reliability.
NOTE 1: For operation above 25°C free-air or 90°C case temperature, refer- to Figures 1 and 2. To avoid exceeding the design maximum virtual
junction temperature, these ratings shouldnot be exceeded. 'Due to variations inindividual device el8ctrical characteristics and them1a1
resistance, the built-in them1ar overload protection may be activated at power levels slightly above or below the rated dissipation.
FREE-AIR TEMPERATURE
DISSIPATATION DERATING CURVE
CASE TEMPERATURE
DISSIPATION DERATING CURVE
16
2000
1800 I"\.
,
1600
I,
.§
,.,i
1400
1200
'"
;=
"\.
,C5g1000
i!
c
.2 12
"\.
I
"\.
600
g
"\.
I'\.
I- Derating factor = 16 mWrC
200 RaJA ~ 62.5°C/W
10
50
is
75
::J
,
400
25
i
,
~600
~
\
14
I
100
C
~E
"\.
"-"\.
125
8
6
4
::II
2
150
\
10
::J
I
~
....... _.uswrc _ _
25
TA - Free-Air Temperature - °C
Figure 1
50
_
75
100
INSTRUMENTS
POST OFFICE BOX 655303 • OAu.AS, TEXAS 75265
125
TC - Case Temperature - °C
Figure 2
~TEXAs
3-262
\
:\
RaJA ~ 4°C/W
o
\
~
150
IlA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
recommended operating conditions
MIN
7
8
10.5
10.5
12.5
14.5
17.5
21
27
1iA7805C
1iA7806C
1iA7808C
1iA7885C
1iA7810C
1iA7812C
1iA7815C
1iA7818C
1iA7824C
Input voltage, VI
1iA7800C Series
1iA7805Q, 1iA7812Q
Operating virtual junction temperatura, TJ
electrical characteristics at specified virtual junction temperature, VI
otherwise noted) .
PARAMETER
TEST CONDITIONS
Ripple rejection
Output voltage regulation
Output rasistance
Temperature coefficient of output voltage
Output noise voltage
Dropout voltage
Bias currant
Bias current change
10=5mAtolA,
PS15W
VI = 7Vt020 V,
VI =7Vto25V
VI=8VtoI2V
VI=8Vto 18V,
f=120Hz
10=5rnAtol.5A
10 = 250 rnA to 750 rnA
f=lkHz
10=5mA
f= 10 Hz to 100kHz
10=1 A
VI=7Vt025V
10=5mAtol A
0
-40
UNIT
V
30
30
33
38
~25
125
A
°C
=10 V, 10 =500. mA (unless
TJt
25°C
Input voltage ragulation
25
28
1.5
Output current, 10
Output voltage:l:
MAX
25
25
25
Full range§
JJA.7805C, JJA.780SQ
TYP MAX
MIN
4.8
5.2
5
4.75
25°C
Full range9_
25°C
Full range9
FuUrange9
25°C
25°C
25°C
Full range§
62
5.25
3
1
78
15
100
50
5
0.017
-1.1
40
2
4.2
50
UNIT
V
mV
dB
100
mV
n
mV/"C
8
1.3
0.5
v.V
V
rnA
mA
Short-circuit output currant
750
rnA
25°C
Peak output current
2.2
25°C
A
t Puise-tesUng techniques maintain the junction temperature as close to the ambient temperature as pOSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-IlF capacitor across the input and a O.I-IlF capacitor across the output.
:I: This specHicetion applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature is OOC to 125°C for the 1iA7805C and -40°C to 125°C for the 1iA7805Q.
'~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
J.1A7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI
,
otherwise noted)
, PARAMETER
Output voltage=l:
Input voltage regulation
Ripple rejection
Output voltage regulation
TEST CONDITiONS
10=5 rnA to 1 A,
P:S;15W
VI = 8Vt021 V,
TJt
MIN
25°C
5.75
O°Cto 125°C
5.7
VI=8Vt025V
25°C
VI=9Vt013V
VI=9Vt019V,
=11 V, 10 =500 mA (unless
f=120Hz
O°Cto 125°C
10=5 mA to 1.5A
59
25°C
10 = 250 mA to 750 mA
1lA7806C
TYP
MAX
6
UNIT
6.25
6.3
5
120
1.5
60
75
V
mV
dB
14
120
4
60
mV
Output resistance
f=1kHz
O°Cto 125°C
0.019
n
Temperature coefficient of output voltage
O°C to 125°C
-0.8
mV/oC
Output noise voltage
10=5mA
f=10Hzt0100kHz
Dropout voltage
10=1A
Bias current
Bias current change
VI=8Vt025V
25°C
45
25°C
2
25°C
4.3
8
1.3
O°Cto 125°C
10=5mAto 1 A
ltV
V
0.5
mA
mA
Short-circuit output current
25°C
550
mA
Peak output current
25°C
2.2
A
t
Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as poSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-ItF capacitor across the input and a 0.1-ItF capacHor across the output.
=I: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 14 V, 10 = 500 mA (unless
,
otherwise noted)
PARAMETER
Output voltage=l:
Input voltage regulation
Ripple rejection
Output voltage regulation
TEST CONDITIONS
'0=5mAt01 A,
P:S;15W
V,=10.5Vt023V,
TJt
TVP
MAX
25°C
7.7
8
8.3
O°Cto 125°C
7.6
V, = 10.5 V to 25 V
25°C
V, = 11 Vto 17V
V, = 11.5 Vto 21.5 V,
1lA7808C
MIN
f=120Hz
O°C to 125°C
10=5 mAto 1.5A
25°C
10=250 rnA to 750 A
55
8.4
6
160
2
80
72
UNIT
V
mV
dB
12
160
4
80
mV
Output resistance
f = 1 kHz
O°Cto 125°C
0.016
n
Temperature coefficient of output voltage
O°C to 125°C
-0.8
mVloC
Output noise voltage
'0=5mA
f = 10 Hz to 100 kHz
Dropout voltage
10=1A
Bias current
Bias current change
V, = 10.5 Vto 25 V
'0=5mAt01A
25°C
52
25°C
2
25°C
4.3
ltV
V
8
1
O°Cto 125°C
0.5
mA
mA
Short-circuit output current
25°C
450
rnA
Peak output current
25°C
2.2
A
t
Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-ItF capacitor across the input and a 0.1-ItF capacitor across the output.
=I: This specification applies only foi dc power dissipation permitted by absolute maximum ratings.
,3-264
:II
TEXAS
INSTRUMENTS
POST OFFICE sox 655303. DALLAS, TEXAS 75265
!lA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVSQ56A- MAY 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
Output voltage:!:
Input voltage regulation
Ripple rejection
Output voltage regulation
TEST CONDITIONS
VI = 11 Vt023.5 V,
10= 5 mAto 1 A,
PS;15W
=15 V, 10 =500 mA (unless
TJt
MIN
25°C
8.15
O°Cto 125°C
8.1
VI=10.5Vt025V
25°C
VI=ll Vto17V
VI = 11.5 Vto 21.5 V,
1= 120Hz
O°Cto 125°C
10= 5 mAto 1.5A
54
25°C
10 = 250 mA to 750 mA
11A7885C
TYP MAX
8.5
UNIT
8.85
8.9
6
170
2
85
70
V
mV
dB
12
170
4
85
mV
Output resistance
I=lkHz
O°Cto 125°C
0.D16
n
Temperature coefficient 01 output voltage
10=5mA
O°Cto 125°C
-0.8
mV/"C
Output noise voltage
1= 10 Hz to 100 kHz
25°C
55
Dropout voltage
10=1 A
25°C
2
25°C
4.3
Bias current
Bias current change
VI = 10.5 Vie 25 V
8
1
O°C to 125°C
10=5mAtolA
I1V
V
0.5
mA
mA
Short-circuit output current
25°C
450
mA
Peak output current
25°C
2.2
A
t Pulse-testing techniques maintain the junction temperature as close Ie the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured With a O.33-I1F capacitor across the input and a O.l-I1F capacitor across the output.
:!: This spacilication applies only lor dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
Output voltage:!:
Input voltage regulation
Ripple rejection
Output voltage regulation
TEST CONDITIONS
10=5mAtolA,
PS;15W
VI = 12.5 Vto 25 V,
TJt
MIN
9.6
10
10.4
O°Cto 125°C
9.5
10
10.5
7
200
2
100
25°C
VI = 14 Vto 20V
1= 120Hz
11A781OC
TYP MAX
25°C
VI=12.5Vt028V
VI = 13 Vt023V,
=17 V, 10 =500 mA (unless
O°Cto 125°C
10 = 5 mA to 1.5 A
25°C
10 = 250 mA to 750 mA
55
71
UNIT
V
mV
dB
12
200
4
100
mV
n
Output resistance
1=1 kHz
O°C to 125°C
0.D18
Temperature coefficient 01 output voltage
10=5mA
O°C to 125°C
-1
mVloC
Output noise voltage
1= 10 Hz to 100 kHz
25°C
70
Dropout voltage
10=1 A
25°C
2
I1V
V
25°C
4.3
Bias current
Bias current change
VI = 12.5 V to 28 V
10=5mAtolA
8
1
O°Cto 125°C
0.5
mA
mA
Short-circuit output current
25°C
400
mA
Peak output current
25°C
2.2
A
t Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:!: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
3-265
~7800
SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A - MAY 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 19 V, 10 = 500 mA (unless
otherwise noted)
.
PARAMETER
Output voltage:J:
10=5mAtolA,
P~15W
Input voltage regulation
Ripple rejection
Output voltage regulation
j.iA7812C
TEST CONDITIONS
VI = 14.5 Vto 27 V,
,
TJt
MIN
TYP
MAX
25°C
11.5
12
12.5
Full range§
11.4
VI = 14.5 Vt030V
25°C
VI=16Vt022V
VI=15Vt025V,
Full range!i
1= 120 Hz
10=5 mAto 1.5A
55
25°C
10 = 250 mA to 750 mA
12.6
10
240
3
120
71
UNIT
V
mV
dB
12
240
4
120
mV
n
Output resistance
1= 1 kHz
Full range§
0.018
Temperature coefficient 01 output voltage
10=5mA
Full range!i
-1
mV/"C
Output noise voltage
1= 10 Hz to 100 kHz
25°C
75
Dropout voltage
10=lA
25°C
2
!LV
V
25°C
4.3
Bias current
Bias current change
VI = 14.5 Vto 30 V
10=5mAtolA
8
1
Full range§
0.5
mA
mA
Short-circuit output current
25°C
350
mA
Peak output current
25fC
2.2
A
t Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured with a 0.33-!LF capacitor across the input and a O.l-!LF capacitor across the output.
:I: This specilication applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature Is O°C to 125°C lorthe j.iA7812C and -40°C to 125°C lor the 1!A78120..
electrical characteristics at specified virtual Junction temperature, VI
otherwise noted)
PARAMETER
Output voltage:l:
VI=17.5Vt03OV
P~15W
Input voltage regulation
Ripple rejection
Output voltage regulation
j.iA7815C
TEST CONDITIONS
10=5 mA to 1 A,
TJt
MIN
TYP
MAX
25°C
14.4
15
15.6
O°C to 125°C
14.25
VI = 17.5 Vto 30 V
25°C
VI =20Vt026 V
VI = 18.5 Vto 28.5 V,
=23 V, 10 =500 mA (unless
1=120Hz
O°C to 125°C
10=5 mA to 1.5A
25°C
10 = 250 mA to 750 mA
54
15.75
11
300
3
150
70
UNIT
V
mV
dB
12
300
4
150
mV
n
Output resistance
1= 1 kHz
O°C to 1.25°C
0.019
Temperature coefficient 01 output voltage
10=5mA
O°Cto 125°C
-1
mV/"C
Output noise voltage
1=10HztolOOkHz
25°C
90
!LV
Dropout voltage
10=1 A
25°C
2
25°C
4.4
Bias current
Bias current change
VI = 17.5 Vto 30 V
10",5mAtolA
V
8
1
O°Cto 125°C
0.5
mA
mA
Short-circuit output current
25°C
230
mA
Peak output current
25°C
2.1'
A
t Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as pOSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-!LF capacitor across the input and a O.l-!LF capacitor across the output.
:I: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
3-266
':IIlExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
J,LA7800 SERIES
POSITIVE·VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 27 V, 10 = 500 mA (unless
otherwise noted)
PARAMETER
Output voltage:!:
TEST CONDmONS
10=5mAtolA,
VI = 21 V to 33 V,
P~15W
Input voltage regulation
Ripple rejection
Output voltage regulation
MIN
TYP
MAX
25°C
17.3
18
18.7
O°Cto 125°C
17.1
VI = 21 V to 33 V
25°C
VI = 24 V to 30 V
VI = 22 V to 32 V,
!!A7818C
TJt
f=120Hz
O°Cto 125°C
10= 5 mA to 1.5A
53
25°C
10 = 250 mA to 750 mA
18.9
15
360
5
'180
69
UNIT
V
mV
dB
12
360
4
180
mV
g
Output resistance
1=lkHz
O°Cto 125°C
0.022
Temperature coefficient of output voltage
10=5mA
O°Cto 125'C
-1
mV/oC
Output noise voltage
1=10Hztol00kHz
25°C
110
Dropout voltage
10=IA
25°C
2
I1V
V
25°C
4.5
Bias current
Bias current change
VI = 21 V to 33 V
1
O°Cto 125'C
10=5mAtol A
8
0.5
mA
rnA
Short-circuit output current
25°C
200
mA
Peak output current
25°C
2.1
A
t Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
TEST CONDITIONS
=33 V, 10 =500 mA (unless
TJt
25°C
Output voltage:!:
VI = 27 V to 38 V,
10=5 mA to 1 A,
P~15W
Input voHage regulation
Ripple rejection
Output voltage regulation
O°Cto 125°C
VI = 27 V to 38 V
TYP
MAX
23
24
25
22.8
25°C
VI = 30 Vto 36 V
VI = 28 V to 38 V,
!!A7824C
MIN
f=120Hz
O°Cto 125°C
10 =5 mAto 1.5A
25'C
10 = 250 mA to 750 mA
50
25.2
18
480
6
240
66
UNIT
V
mV
dB
12
480
4
240
mV
Output resistance
1= 1 kHz
O°Cto 125°C
0.028
g
Temperature coefficient 01 output voltage
10=5mA
O°Cto 125°C
-1.5
mVI"C
Output noise voltage
f= 10 Hz to 100 kHz
25°C
170
Dropout voltage
10=1 A
25°C
2
I1V
V
25°C
4.6
Bias current
Bias current change
VI = 27 V to 38 V
1
O°C to 125°C
10=5mAtolA
8
0.5
mA
mA
Short-circuit output current
25°C
150
mA
Peak output current
25°C
2.1
A
t Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured with a 0.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 •
DALLAS, TEXAS 75265
3-267
~7800
SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
=
=
=
electrical characteristics at specified virtual junction temperature,V. 10 V, 10 500 mA, TJ 25°Ct
(unless otherwise noted)
PARAMETER
/1A7805Y
TEST CONDITIONS
MIN
TYP
Output voltage;
Input voltage regulation
Ripple rejection
Output voltage regulation
UNIT
MAX
5
3
1
78
15
5
0.017
-1.1
VI=7Vt025V
VI=8Vto12V
f= 120Hz
VI=8Vto18V,
10= 5 mA to 1.5A
10 = 250 mA to 750 mA
1=lkHz
V
mV
dB
mV
Q
Output resistance
mV/oC
Temperature coefficient of output voltage
,10=5mA
Output noise voltage
f= 10 Hz to 100kHz
40
/tV
Dropout voltage
2
V
10=1 A
Bias current
4.2
mA
Short-circuit output current
750
mA
Peak output current
2.2
A
t Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as poSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-/tF capacitor across the input ahd a O.I-/tF capacitor across the output.
:t: This specification applies only lor dc power dissipation permitted by absolute maximum r a t i n g s . '
=
=
=
electrical characteristics at specified virtual junction temperature, VI 11 V, 10 500 mA, TJ 25°Ct
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output voltage:J:
/1A7806Y
MIN
TYP
MAX
UNIT
V
6
5
Input voltage regulation
mV
1.5
Ripple rejection
75
dB
14
Output voltage regulation
mV
4
Q
Output resistance
0.019
Temperature coefficient 01 output voltage
-O.B
mVfOC
10=5mA
Output noise voltage
45
1= 10 Hz to 100kHz
/tV
Dropout voltage
2
V
10=IA
mA
Bias current
4.3
Short-circuit output current
550
rnA
Peak output current
2.2
A
t Pulse-testing techniques maintain the JUnction temperature as close to the ambient temperature as poSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-/tF capacitor across the input and a O.I-/tF capaCitor across the output.
~ This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
VI =BVt025 V
VI=9VtoI3V
1=120Hz
VI = 9Vto 19V,
10=5 mAto 1.5A
10 = 250 mA to 750 rnA
1= 1 kHz
~TEXAS
3--268
INSTRUMENTS
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
IlA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
=
=
electrical characteristics at specified virtual Junction temperature, VI 14 V, 10 500 mA, TJ
(unless otherwise noted)
PARAMETER
l1A7808V
TEST CONDITIONS
MIN
TVP
Output vottage;
MAX
Input voltage regulation
Ripple rejection
6
VI = 11 Vto 17V
2
VI = 11.5 V to 21.5 V.
Output vottage regulation
1= 1 kHz
Temperature coefficient 01 output vottage
10=5mA
Output noise voltage
1=10Hztol00kHz
Dropout voltage
10=IA
dB
12
10 =250 mA to 750 A
Output resistance
mV
72
1= 120 Hz
10 =5mAto 1.5A
mV
4
0.Q16
Q
-0.8
mV/oC
52
Bias current
UNIT
V
8
VI = 10.5 Vto 25 V
=25°Ct
2
I1V
V
4.3
mA
Short-circuit output current
450
mA
Peak output current
2.2
A
t
Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:I: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
=
=
electrical characteristics at specified virtual Junction temperature, VI 15 V, 10 500 mA, TJ
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output voltage;
Input voltage regulation
Ripple rejection
Output voltage regulation
l1A7885V
MIN
TVP
8.5
VI = 10.5 V to 25 V
6
2
VI=11 Vto17V
VI = 11.5 V to 21.5 V.
1= 120 Hz
10=5mA to 1.5A
10 = 250 mA to 750 mA
Output resistance
1= 1 kHz
Temperature coefficient 01 output voltage
10=5mA'
Output noise vottage
1= 10 Hz to 100kHz
Dropout voltage
10=1 A
Bias current
70
12
4
MAX
=25°Ct
UNIT
V
mV
dB
mV
0.016
Q
-0.8
mV/oC
55
2
I1V
V
4.3
mA
Short-circuit output current
450
mA
Peak output current
2.2
A
.. the Junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
t Pulse-testing techniques maintain
account separately. All characteristics are measured with a 0.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:I: This specWication applies only lor dc power dissipation permitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
3-269
~7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtuallunction temperature, VI = 17 V, 10 = SOO mA, TJ = 2soCt
(unless otherwise noted)
.
PARAMETER
TEST CONDITIONS
MIN
Output voltagei
VI = 12.5 Vto28 V
Input voltage regulation
VI'" 14Vt020V
VI = 13Vt023V,
f=120Hz
10= 5 mAto 1.5 A
10 = 250 mA to 750 mA
f=lkHz
l'Iipple rejection
Output voltage regulation
1lA7810Y
TYP MAX
10
7
2
71
12
4
0.018
-1
70
2
4.3
UNIT
V
mV
dB
mV
Output resistance
n
mV/oC
coefficient of output voltage
10=5rnA
Output noise voltage
f = 10 Hz to 100 kHz
I1V
Dropout voltage
V
10=1 A
Bias current
rnA
Short-circuit output current
mA
400
Peak output current
2.2
A
t Pulee-tesling techmquas maintain the Junction temperature as close to the ambient temperature as possible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-j.tF capacitor ecross the input and a O.l-I1F capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
Tem~rature
electrical characteristics at specified virtual Junction temperature, VI =19 V, 10 = SOO mA, TJ = 2soct
(unless otherwl$e noted)
.
.
.
-
1lA7812Y
UNIT
TYP MAX
Output voltagei
12
V
10
VI = 14.5 Vto30V
Input voltage regulation
mV
3
VI = 16Vt022 V
Ripple rejection
VI=15Vto25V,
f=120Hz
71
dB
12
10=5mAto 1.5A
Output voltage regulation
mV
4
10 = 250 rnA to 750 rnA
Output resistance
n
f=l kHz
0.018
-1
Temperature coefficl!lnt of output voltage
mVtoC
10= 5 rnA
Output noise voltage
f = 10 Hz to 100 kHz
75
IlV
Dropout vQltage
V
2
10=1 A
Bias current
4.3
rnA
Short-circuit output current
mA
350
Peak output current
A
2.2
t Pulee-testlng techniques maintain the Junction temperature as close to the ambient temperature as possible. Thermal effects mu$l be taken Into
account separately. All characteristics are measured with a O.33-IlF capecltor across the input and a O.l-j!F capacitor across the output.
:j: This specification applies only for de power dissipation permitted by Bbsolute maximum ratings.
PARAMETER
TEST CONDITIONS
..
~TEXAS
'3-270
INSTRUMENTS
POST OfFICE BOX 655303 • DAlLAS. TEXAS 75285
MIN
J,LA7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
=
=
electrical characteristics at specified virtual junction temperature, VI 23 V, 10 500 rnA, TJ
(unless otherwise noted)
PARAMETER
11A7815Y
TEST CONDITIONS
MIN
TYP
Output voltage;
MAX
15
Input voltage regulation
Ripple rejection
VI = 20 V to 26 V
VI = 18.5 V to 28.5 V,
Output voltage regulation
mV
3
70
1= 120 Hz
dB
12
10= 5mAto 1.5A
10 = 250 mA to 750 mA
UNIT
V
11
VI = 17.5 V to 30 V
=25°Ct
mV
4
n
Output resistance
f= 1 kHz
0.019
Temperature coefficient 01 output voltage
10=5mA
-1
mVrC
Output noise voltage
1=10 Hz to 100 kHz
90
Dropout voltage
10= 1 A
I1V
V
2
Bias current
4.4
mA
Short-circuit output current
230
mA
Peak output current
2.1
A
t Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as poSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a 0.33-I1F capacitor across the input and a 0.1-I1F capacitor across the output.
:j: This specilication applies only lor de power dissipation permitted by absolute maximum ratings.
=
=
electrical characteristics at specified virtual junction temperature, VI 27 V, 10 500 rnA, TJ
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output voltage;
Input voltage regulation
Ripple rejection .
Output voltage regulation
11A7818Y
MIN
TYP
18
VI = 21 V to 33 V
15
VI =24 Vto30V
5
VI = 22 V to 32 V,
1=120Hz
10= 5 mAto 1.5A
10 = 250 mA to 750 mA
69
12
4
0.022
MAX
=25"Ct
UNIT
V
mV
dB
mV
n
Output resistance
1= 1 kHz
Temperature coefficient 01 output voitage
10=5mA
-1
mVrC
Output noise voltage
1=10Hzt0100kHz
110
Dropout voltage
10=1 A
I1V
V
2
Short-circuit output current
200
mA
mA
Peak output current
2.1
A
Bias current
4.5
t Pulse-testing techniques maintain the Junction temperature as close to the ambient temperature as poSSible. Thermal effects must be taken Into
account separately. All characteristics are measured with a O.33-I1F capacitor across the input and a 0.1-I1F capacitor across the output.
:j: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75285
3--271
J,LA7800 SERIES
.
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
electrical characteristi'cs at specified virtual junction temperature, VI = 33 V, 10 = 500 mA, TJ = 25°Ct
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Output voltage=!'
Input voltage regulation
Ripple rejection
Output voltage regulation
jJA7824Y
MIN
TYP
24
,VI =27Vto38 V
18
VI = 30 V to 36 V
6
VI = 28 V to 38 V,
f= 120 Hz
10 = S mA to 1,S A
10 = 2S0 mA to 7S0 mA
Output resistance
f= 1 kHz
Temperature coefficient of output voltage
10=SmA
Output noise voltage
f=10Hztol00kHz
DropoUt voltage
10=lA
66
12
4
,0.028
-l.S
170
2
MN<
UNIT
V
mV
dB
mV
0
mV~C
jlV
V
Bias current
4.6
mA
Short-circuit outpui current
150
mA
Peak output current
2.1
A
t
Pulse-testing techniques maintain the junction temperature as close to the ambient temperature as possible. Thermal effects must be taken into
account separately. All characteristics are measured with a 0.33-jlF capacitor across the input and a O.l-jlF capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
~TEXAS .
INSTRUMENTS
3-272
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
~7800 SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
+VI~
0.33 11Ft
11A78xx
~
'L.-""TI--.. . . '.
+
IN
1----.--
+----i
+VO
G
VI
0.1 I1F
------4~----~- -VO
Figure 4. Positive Regulator in Negative
Configuration (VI Must Float)
Figure 3. Fixed Output Regulator
H"----4"- Output
Input
Input-.....- - i
R1
R1
'---_--'IL---<..... Output
R2
--+
10
10
NOTE A.
=(V()IR1) + 10 Bias Current
The following fonnula is used when Vxx is
the nominal output voltage (output to
common) of the fixed regulator.
Vo
=
Vxx +
(~~x + 10) R2
Figure 5. Adjustable Output Regulator
Figure 6. Current Regulator
1N4001
20-V
Input --i....- I___......,r--..uI--4ll.....- - -.....-
Vo = 15 V
1N4001
1N4001
-2o-V--i~H
Input
....
'--_
-_---4-- Vo =-15 V
H .....
1N4001
Figure 7. Regulated Dual Supply
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-273
J,tA7800 SERIES
.
POSITIVE-VOLTAGE REGULATORS
SLVS056A- MAY 1976 - REVISED AUGUST 1995
APPLICATION INFORMATIoN
+vo
Figure 8. Output Polarity-Reversal Protection Circuit
operation with a load common to a voltage of opposite polarity
In many cases, a regulator powers a load that is not connected to ground but instead is connected to a voltage
source of opposite polarity (e.g., op amps, level-shifting Circuits, etc.). In these cases, a clamp diode should be
connected to the regulator output as shown in Figure 8. This protects the regulator from output polarity reversals
during startup and short-circuit operation.
Figure 9. Reverse-Bias Protection Circuit
reverse-bias protection
Occasionally, there exists the possibility that the input voltage to the regulator can collapse faster than the output
voltage. This could occur, for example, when the input supply is crowbarred during an output overvoltage
condition. If the output voltage is greater than approximately 7 V, the emitter-base junction of the series pass
element (internal or external) could break down and be damaged. To prevent this, a diode shunt can be
employed as shown in Figure 9.
~1ExAs
3-274
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
JlA78LOO SERIES
POSITIVE·VOLTAGE REGULATORS
SLVS010D -JANUARY 1976 - REVISED OCTOBER 1995
•
•
•
•
•
•
3-Terminal Regulators
Output Current Up to 100 mA
No External Components
Internal Thermal Overload Protection
Internal Short-Circuit Current Limiting
Direct Replacements for Fairchild !lA78LOO
Series
DPACKAGE
(TOP VIEW)
OUTPUT[]S INPUT
COMMON 2
7 CO.MMON
COMMON 3
6 COMMON
NC45NC
Nc-No intemal connection
description
LPPACKAGE
(TOP VIEW)
This series of fixed-voltage monolithic integratedcircuit voltage regl,llators is designed for a wide
range of applications. These applications include
INPUT
on-card regulation for elimination of noise and
COMMON
distribution problems associated with single-point
OUTPUT
regulation. In addition, they can be used with
power-pass elements to make high-current
TO-226AA
voltage regulators. One of these regulators can
deliver up to 100 mA of output current. The internal
limiting and thermal shutdown features of these
regulators make them essentially immune to overload. When used as a replacement for a zener diode-resistor
combination, an effective improvement in output impedance can be obtained together with lower-bias current.
AVAILABLE OPTIONS
VO(nom)
(V)
TJ
O°C to 125°C
2;6
5
6.2
S
9
10
12
15
PLASTIC DIP
(D)
PACKAGED DEVICES
PLASTIC CYLINDRICAL
(LP)
.
OUTPUT VOLTAGE TOLERANC,"
5"JLA7SL02ACD
JLA7SL05ACD
JLA7SL06ACD
JLA7SL08ACD
JLA7SL09ACD
JLA7SL10ACD
JLA7SL12ACD
JLA7SL15ACD
10%
5%
JLA7SL02CD
JLA7SL05CD
JLA7SL06CD
JLA7SLOSCD
JLA7SL09CD
JLA7SL1OCD
JLA7SL12CD
JLA7SL15CD
JLA7SL02ACLP
JLA7SL05ACLP
JLA7SL06ACLP
JLA7SLOSACLP
JLA7SL09ACLP
I1A7SL10ACLP
JLA7SL12ACLP
JLA7SL15ACLP
JLA7SL05AOD
JLA7SL050D
JLA7SL050LP
JLA7SLOSOLP
JLA7SL120LP
JLA7SL12AOP
JLA7SL120D
JLA7SL120LP
D and LP packages are available taped and reelec!. Add R SuffiX to devise type (e.g., JLA7SL05ACDR).
-40°C to 125°C
5
12
10%
JLA7SL02CLP
JLA7SL05CLP
JLA7SL06CLP
JLA7SLOSCLP
JLA7SL09CLP
JLA7SL1OCLP
JLA7SL12CLP
JLA7SL15CLP
~TEXAS.
CHIP FORM
(Y)
JLA7SL02Y
JLA7SL05Y
JLA7SL06Y
JLA7SLOSY
JLA7SL09Y
JLA7SL10Y
JLA7SL12Y
JLA7SL15Y
-
copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
poST OFFICE BOX 655303 • DALLAS. TEXAS 75265
\
\
3-275
J.lA78LOO SERIES
POSITIVE·VOLTAGEREGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
schematic
.---_.---------------------------.-------.------.-----~-INPUT
20kn
.-----t------+-+-+------4I...----<*_
QUTPUT
1 kOto 14 kn
1.4kn
L---------+-~----__4I~--~--_.--~----__<~--------~-----COMMON
Resistor values shown are nominal.
~TEXAS
3-276
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
J,LA78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
/lA78xxY chip information
These chips, when properly assembled, display characteristics similar to the 11A78xxY. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
.
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
INPUT
COMMON
(8)
(2)
11A78Lxx
(1)
OUTPUT
CHIP THICKNESS: 15 MILS TYPICAL
BONDII'fG PAD.S: 4 x 4 MILS MINIMUM
t Jmax =150°C
TOLERAN.CES ARE ±100/0.
ALL DIMENSIONS ARE IN MILS.
TERMINALS 2,3,6, AND 7 ARE
CONNECTED TOGETHER
TERMiNALS 4 AND 5 ARE NOT
CONNECTED·
.
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
~·TEXAS
INSTRUMENTS
POST OFFICE BOX 655S03 • DALLAS. ~ 75265
JlA78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
!!A78LxxC absolute maximum ratings over operating temperature ra~ge (unless otherwise noted)
~78L02C,~78L02AC
~78L12C, ~78L12AC
THROUGH
~78L15C, ~78L15AC
~78L10C, ~78L10AC
Input voltage
35
30
Continuous total power dissipation (see Note 1)
UNIT
V
See Dissipation Rating Tables 1 and 2
Operating free-air, TA, case, TC, or virtual junction, TJ, temperature range
,
Storage temperature range, Tsta
o to 125
Oto 125
°c
-65 to 150
-65 to 150
°C
260
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
NOTE 1: To avoid exceeding the design maximum virtual Junctlon'temperature, these ratings should not be exceeded. Due to vanatlons In
individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be activated at power
levels slightly above or below the rated dissipation.
IlA78LxxQ absolute maximum ratings over operating temperature range (unless otherwise noted)
~78L05Q, IlA78L05AQJ~78LI2Q, ~78L12AQ I UNIT
Input voltage
I
30
Continuous total power dissipation (see Note 1)
35
V
See Dissipation Rating Tables 1 and 2
Operating free-air, TA, case, TC, or virtual junction, TJ, temperature range
-'40 to 150
-40 to 150
Storage temperature range, Tsta
-65 to 150
-65 to 150
°C
260
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
°C
NOTE 1: To avoid exceeding the deSign maximum vlrtualluncllon temperature, these ratings should not be exceeded. Due to vanations In
individual device electrical characteristics and thermal resistance, the built-in thermal ove~oad protection may be activated at power
levels slightly above or below the rated dissipation.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE
DERATING
FACTOR
DERATE
ABOVETA
TA = 70°C
POWER RATING
725mW
5.8mWfDC
25°C
464mW
775mW
6,2mW/oC
25°C
496mW
PACKAGE
TA s; 25°C
POWER RATING
D
LPt
t The LP package dissipation rating is based on thermal resistance RaJA measured in still air with the
device mounted in an Augat socket. The bottom olthe package is 10 mm (0.375 in) above the socket.
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
DERATING
FACTOR
TA s; 25°C
POWER RATING
D
1600 mW
19.6mW/oC
424mW
LP
1600 mW
28.6 mW/oC
713mW
~TEXAS
3-278
DERATE
ABOVE TC
PACKAGE
"
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TC=125°C
POWER RATING
J.U\78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVSD1DD - JANUARY 1976 - REVISED OCTOBER 1995
recommended operating conditions
~78L02C,~78L02AC
~78L05C, ~78L05AC,
~78L05Q,~78L05AQ
~78L06C,~78L08AC
~78L08C,~78L08AC
Input voltage, VI
~78L09C,~78L09AC
~78Ll0C,~78Ll0AC
~78L12C, ~78L12AC,
~78L12Q, ~78L12AQ
~78L15C, ~78L15AC
MIN
4.75
MAX
7
20
8.5
10.5
11.5
12.5
20
23
24
25
14.5
27
17.5
30
100
125
125
Output current, 10
~78LxxC
thru ~78LxxAC
~78LxxQ and ~78LxxAQ
Operating virtual junction temperature, TJ
0
-40
UNIT
20
V
rnA
·C
··~TEXAS
INSTRUMENTS
POST OFl'ICE BOX 655303 • DAllAS, TEXAS 75265
3-279
~78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
TEST CONDITIONS
j.iA78lO2C
TJt
25°C
Output voltag&l=
VJ=4.75 Vto20 v,
10=lmAto40mA
10=1 mAto70mA
Input voltage
regulation
VI =4.75Vt020V
Ripple rejection
VI =6Vt020V,
Output voltage
regulation
10=1 mAtol00mA
Output noise voltage
f = 10 Hz to 100 kHz
f=120Hz
TVP
2.4
2.6
25°C
Bias current
j.iA78L02AC
MAX
2.6
MAX
2.6
2:5
2,.45
2.75
2.35
2.85
2.45
2.75
42
125
20
100
16
100
16
75
43
51
12
50
6
25
51
50
6
25
30
30
25°C
1.7
1.7
25°C
3.6
mV
mV
j.iV
V
3.6
6
V
dB
12
25°C
UNIT
2.7
20
6
5.5
Full range§
10=1 mAt040rnA
TVP
~.85
125°C
VI =5Vt020V
MIN
2.35
25°C
10=1 mAto40rnA
Dropout voltage
Bias current change,
Full range§
MIN
25°C
VI =5Vt020V
=9 V, 10 =40 mA (unless
5.5
2.5
2.5
0.2
0.1
rnA
mA
t
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
'
'
measured with a 0.33-I1F capacitor acroSSJtheinput and a O.l-I1F capacitor across the output.
:j: This specification applies only for de power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperatUre is O°Cto 125°C for j.iA78L02, j.iA78L02AC, j.iA78L05C, and j.iA78L05AC and-400C to 125°C forj.iA78L05Q
and j.iA78L05AQ.
electrical characteristics at specified virtual junction temperature, VI = 10 V, 10 = 40 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TJt
25°C
Output voltage:j:
VI = 7 Vto 20 V,
10= 1 mAto40mA
10=1 rnAt070mA
Input voltage
regulation
VI =7Vt020V
VI =8Vto 18 V,
Output voltage
regulation
10 = lmA to 100 rnA
Output noise voltage
f = 10 Hz to 100 kHz
10 = 1 rnA to 40 mA
Dropout voltage
Bias current
Bias current change
MIN
TVP
MAX
,4.6
5
f=120Hz
25°C
lo=lmAto40mA
TVP
5
UNIT
MAX
5.4
4.8
5.5
4.75
5.25
4.5
M
4.75
5.25
40
25°C
200
32
150
26
150
26
100
49
41
15
60
8
30
49
60
8
30
42
25°C
1.7
1.7
25°C
3.8
6
3.8
V
mV
dB
15
42
FUll range§
5.2
32
25°C
125°C
VI,= 8 Vto 20 V
MIN
4.5
25°C
VI =8Vto20V
Ripple rejection
Full range§
j.iA78L05AC,
j.iA78L05AQ
j.iA78L05C,
j.iA78L05Q
mV
I1V
V
6
5.5
5.5
1.5
1.5
0.2
0.1
rnA
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal.effects must be taken into account separately. All characteristics are
measured with a 0.33-I1F capacitor across the input and a O.l-I1F capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absoluta l1II!Ximum ratings.
§ Full range virtual junction temperature is O°C to 125°C for j.iA78L02, j.iA78L02AC, j.iA78L05C, and j.iA78L05AC and-40°C to 125°C forj.iA78L05Q
and j.iA78L05AQ.
~TEXAS
INSTRUMENTS
3-280
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
JJA78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVSOl 00 -JANUARY 1976 - REVISED OCTOBER 1995
electrical characteristics at specified virtual junction temperature, VI = 12 V, 10 = 40 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TJt
25°C
Output voltaget
VI = 8.5 Vto 20 V.
10=1 rnA to 40 rnA
10=1 rnA to 70 rnA
VI = 8.5 V to 20 V
Input voltage
regulation
VI =9Vt020V
Ripple rejection
VI = 10Vt020V.
Output voltage
regulation
10 = 1 rnA to 100 rnA
10=1 rnA to 40 rnA
Output noise voltage
f= 10 Hz to 100kHz
MIN
TYP
MAX
6.2
6.2
6.45
6.7
5.95
5.6
6.8
5.9
6.5
5.6
6.8
5.9
6.5
5.7
25°C
f= 120 Hz
25°C
39
25°C
Dropout voHage
Bias current
Bias current change
Full range§
35
200
35
175
29
150
29
125
48
48
16
80
9
40
9
40
25°C
46
46
25°C
1.7
1.7
25°C
3.9
V
mV
mV
ltV
V
3.9
6
UNIT
dB
80
6
5.5
5.5
Full range§
10 = 1 rnA to 40 rnA
40
16
125°C
VI=9Vt020V
1JA78L06AC
1JA78L06C
MIN
TYP MAX
1.5
1.5
0.2
0.1
rnA
rnA
t
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a O.33-ItF capacitor across the input and a 0.1-!1F capacitor across the output. .
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature is O°C to 125°C for 1JA78L06C.11A78L06AC.11A78L08C. and 11A78L08AC.
electrical characteristics at specified virtual junction temperature, VI = 14 V, 10 = 40 mA (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TJt
25°C
Outputvoltaget
VI = 10.5 Vto23 V.
10=1 rnA to 40 rnA
10=1 rnA to 70 rnA
Input voltage
regulation
VI = 10.5 Vt023 V
Ripple rejection
VI = 13Vt023V.
10= 1 rnA to 100 rnA
10=lmAt04OmA
Output noise voHage
f=10HztolookHz
Dropout voltage
Bias current
Bias current change
TYP
MAX
MIN
TYP
MAX
7.36
8
8
8.3
8.64
7.7
7.2
8.8
7.6
8.4
7.2
8.8
7.6
8.4
25°C
VI = 11 V to 23 V
Output voltage
regulation
Full range§
f= 120 Hz
25°C
36
25°C
10=1 rnA to 40 rnA
42
200
42
175
36
150
36
125
46
37
46
80
18
80
10
40
10,
40
25°C
54
54
1.7
1.7
25°C
4
Full range§
6
5.5
4
UNIT
V
mV
dB
18
25°C
125°C
VI=5Vt020V
1JA78L08AC
1JA78LOSC
MIN
mV
ltV
V
6
5.5
1.5
1.5
0.2
0.1
rnA
rnA
t Pulse-tesllng techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-ItF capacitor across the input and a O.l-ItF capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature is O°C to 125°C for 11A78L06C.11A78L06AC.11A78L08C. and 11A78L08AC.
'~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-281
f.!A78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
electrical characteristics at specified virtual junction temperature, VI = 16 V, 10= 40 mA (unless
otherwise noted)
PARAMETER
,
TEST CONDITIONS
TJt
25°C
Output voltage=l:
VI= 12Vt024V,
10 = 1 mA to 40 mA
10 = 1 mA to 70 mA
Input voltage
regulation
VI=12Vt024V
Ripple rejection
VI=15Vt025V,
10 = 1 mA to 100 mA
Output noise voltage
1= 10Hzto 100kHz
f= 120 Hz
MAX
8.3
9
Bias current
9
MAX
8.6
9.9
8.55
9.45
8.1
9.9
8.55
9.45
36
225
45
175
40
175
40
125
45
38
19
90
11
40
45
90
11
40
58
58
25°C
1.7
1.7
25°C
4.1
mV
mV
JlV
V
4.1
6
V
dB
19
25°C
UNIT
9.4
45
6
5.5
Full range§
10 = 1 mA to 40 mA
TYP
9.7
125°C
VI=13Vt024V
MIN
8.1
25°C
10 = 1 mA to 40 mA
Dropout voltage
Bias current change
25°C
!lA78L09AC
TYP
25°C
VI=13Vt024V
Output voltage
regulation
Full range§
JlA78L09C
MIN
5.5
1.5
1.5
0.2
0.1
mA
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-JlF capacitor across the input and a O.I-JlF capacitor across the output.
=I: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature is O°C to 125°C for !lA78L09C, !lA78L09AC, !lA78L 10C, and !lA78L10AC.
electrical characteristics at specified virtual junction temperature, VI = 14 V, 10 = 40 mA(unless
otherwise noted}
PARAMETER
TEST CONDITIONS
TJt
25°C
Output voltage=l:
VI= 13Vt025V,
10 = 1 mA to 40 mA
10=1 mAto 70 mA
Input voltage
regulation
VI=13Vt025V
Ripple rejection
VI = 15 Vto 25 V,
Output voltage
regulation
10=1 mAtol00mA
Output noise voltage
1= 10 Hz to 100 kHz
Dropout voltage
Bias current
Bias current change
1=120Hz
25°C
MAX
MIN
TYP
9.2
10
10
10=1 mAt040mA
MAX
10.8
9.6
9
11
9.5
10.5
9
11
9.5
10.5
36
25°C
51
225
51
175
175
42
125
44
37
44
90
20
90
11
40
11
40
62
62
1.7
1.7
25°C
4.2
Full range§
6
5.5
4.2
V
mY'
dB
20
25°C
UNIT
10.4
42
25°C
1256C
VI = 14 V to 25 V
!lA78L10AC
·TYP
25°C
VI=14Vt025V
10=1 mAt04bmA
Full range§
!lA78L10C
MIN
mV
JlV
V
6
5.5
1.5
1.5
0.2
0.1
mA
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-JlF capacitor across the input and a O.I-JlF capacitor across the output.
=I: This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
.
§ Full range virtual junction temperature is O°C to 125°C for !lA78L09C, !lA78L09AC, !lA78L10C, and !lA78L toAC.
~TEXAS
INSTRUMENTS
3--282
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
J,tA78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
=19 V, 10 =40 mA (unless
electrical characteristics at specified virtual junction temperature, VI
otherwise noted)
PARAMETER
TEST CONDITIONS
TJt
25°C
Output voltage:!:
VI = 14 Vt027V,
10= 1 mAt040mA
10=1 rnAt070mA
Input voltage
regulation
VI=14.5Vt027V
Ripple rejection
VI=15Vt025V,
10=lrnAtol00mA
Output noise voltage
f=10Hztol00kHz
f= 120Hz
TYP
11.1
12
25°C
Bias current
MIN
TYP
12
UNIT
MAX
12.9
11.5
11.4
12.6
10.8
13.2
11.4
12.6
36
12.5
55
250
55
250
49
200
49
200
42
37
42
100
22
100
13
50
13
50
25°C
70
70
25°C
1.7
1.7
25°C
4.3
6.5
V
mV
dB
22
mV
I1V
V
4.3
6.5
6
Full range§
10 = 1 rnA to 40 rnA
MAX
13.2
125°C
VI=16Vt027V
1!A78L12AC,
1!A78L12AQ
10.8
25°C
10=1 mAt040mA
Dropout voltage
Bias current change
MIN
25°C
VI=16Vt027V
Output voltage
regulation
Full range§
1!A78L12C,
1!A78L12Q
6
1.5
1.5
0.2
0.1
mA
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Themnal effects must be taken into account separately. All characteristics are
measured with a 0.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range Virtual junction temperature is O°C to 125°C for JlA78L12C, JlA78L 12AC, JlA78L15C, and JlA78L 15AC.
electrical characteristics at specified virtual junction temperature, VI
otherw.ise noted)
PARAMETER
TEST CONDITIQNS
TJt
25°C
Output voltage:!:
VI = 17.5Vt030V,
10 = 1 mA to 40 mA
10=1 mAt070mA
Input voltage
regulation
VI = 17.5 V to 30 V
Ripple rejection
VI = 18.5 V to 28.5 V,
10=1 mAto 100 rnA
Output noise voltage
f=10Hztol00kHz
10 = 1 mA to 40 rnA
Dropout voltage
Bias current
Bias current change
f=120Hz
25°C
TYP
13.8
15
10=1 rnAt040mA
MAX
MIN
TYP
15
MAX
16.2
14.4
13.5
16.5
14.25
15.75
13.5
16.5 14.25
15.75
65
58
33
25°C
65
300
250
58
250
34
39
25
150
15
75
150
15
75
82
25°C
1.7
1.7
25°C
4.6
Full range§
6.5
6
4.6
V
!"flV
dB
39
25
82
UNIT
15.6
300
25°C
·125°C
VI = 10Vto30V
1!A78L15AC
1!A78L15C
MIN
25°C
VI = 20 V to 30 V
Output voltage
regulation
Full range§
=23 V, 10 =40 mA (unless
mV
I1V
V
6.5
6
1.5
1.5
0.2
0.1
mA
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Themnal effects must be taken into account separately. All characteristics are
measured with a 0.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
:!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
§ Full range virtual junction temperature is O°C to 125°C for JlA78L12C, JlA78L 12AC, JlA78L15C, and JlA78LI5AC.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-283
~78LOO
SERIES
POSITIVE~VOLTAGE
,
REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
electrical characteristics at specified virtual Junction temperature, VI = 9 V, 10 = 40 rnA, TA = 25°C
{unless otherwise noted}
,"
PARAMETER
TEST CONDITIONST
1JA78L02Y
MIN
Output voltage:!:
TYP
MAX
2.6
Input voltage
regulation
VI = 4.75 Vto 20 V
Ripple rejection
VI =6Vt020V,
Output voltage
regulation
10=1 mAto loomA
12
10.=1 mA't04OmA
6
Output noise voltage
f,,10Hztol00kHz
V
20
mV
16
VI =5Vt020V
51
f= 1,20 Hz
UNIT
dB
mV
30
Dropout voltage
1.7
I1V
V
Bias current
3.6
,mA
.. are
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken Into account separately. All charactenstlcs
*
measured with a O.33-I1F capacitor across the input and a O.I-I1F capacitor across the output.
This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 10 V, 10 = 40 rnA; TA = 25°C
{unless otherwise n o t e d } ·
,
PARAMETER
TEST CONDITIONST
/1A78L05Y
MIN
Output voltage:!:
t
TYP
MAX
5
Input voltage
regulation
VI =7Vt020V
32
VI =8Vt020V
26
Ripple rejection
VI=8VtoI8V,
Output voltage
regulation
10 = 1 mAto 100 mA
10 = 1 mA to 40 mA
Output noise voltage
f=10Hztol00kHz
V
mV
dB,
49
f=120Hz
UNIT
15
mV
8
42
Dropout voltage
1.7
I1V
V
Bias current
3.8
mA
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken Into account separately. All charactenstics are
measured with a O.33-I1F CapaCitor across the input and a O.I-I1F ,capacitor across the output.
This specification applies only for dc power dissipation permitted by absolute maximum ratings.
*
electrical characteristics at specified virtual junction temperature, VI = 12 V, 10 = 40 rnA, TA= 25°C
{unless otherwise noted}
,
PARAMETER
TEST CONDITIONST
Output voltage:!:
t
1JA78L06Y
MIN
TYP
6.2
Input voltage
regulation
VI = 8.5 V to 20 V
35
VI =9 Vt020 V
29
Ripple rejection
VI=10Vt020V,
Output voltage
regulation
10=lmAtol00mA
10=1 mAto 40 mA
9
Output noise voltage
f=10Hztol00kHz
46
f= 120 Hz
48
16
MAX
UNIT
V
mV
dB
mV
I1V
Dropout voltage
1.7
V
Bias current
3.9
mA
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All charactenstlcs are
measured With a O.33-I1F capacitor across the input and a 0.1-/lF capacitor across the output.
This specification applies only for dc power dissipation permitted by absolute maximum ratings.
*
~TEXAS
INSTRUMENTS
3-284
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
IlA78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS01 DO - JANUARY 1976 - REVISED OCTOBER 1995
electrical characteristics at specified virtual junction temperature, VI = 14 V, 10 = 40 mA, TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONST
11A78L08Y
MIN
Output voltage'"
TYP
MAX
V
8
Input voltage
regulation
VI = 10.5 V to 23 V
42
VI=ll Vt023V
36
Ripple rejection
VI=13Vt023V,
Output voltage
regulation
10 = 1 mA to 100 mA .
Output noise voltage
f= 120 Hz
UNIT
mV
46
dB
10=1 mAt040mA
18
10 .
mV
f = 10 Hz to 100 kHz
54
Dropout voltage
Bias current
1.7
IlV
V
4
mA
t
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken Into account separately. All characteristics are
measured with a 0.33-IlF capacitor across the input and a O.l-IlF capacitor across the output.
:I: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 16 V, 10 = 40 mA, TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONST
11A78L09Y
MIN
Output voltage:J:
TYP
MAX
9
VI = 12 Vt024 V
V
45
Input voltage
regulation
VI=13Vt024V
Ripple rejection
VI = 15 Vt025 V,
Output voltage
regulation
10=1 mAtol00mA
19
10 = 1 mA to 40 mA
11
Output noise voltage
f=10Hztol00kHz
mV
40
f= 120Hz
UNIT
45
dB
mV
58
Dropout voltage
1.7
IlV
V
Bias current
4.1
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-IlF capacitor across the input and a O.l-IlF capacitor across the output.
:I: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 14 V, 10 = 40 mA, TA = 25°C
(unless otherwise noted)
PARAMETER
TEST CONDITIONST
Output voltage'"
11A78Ll0Y
MIN
TYP
10
Input voltage
regulation
VI=13Vt625V
51
VI=14Vt025V
42
Ripple rejection
VI=15Vt025V,
Output voltage
regulation
10= 1 mA to 100 mA
20
10=1 mAt040mA
11
Output noise voltage
f=10Hztol00kHz
f= 120 Hz
44
62
MAX
UNIT
V
mV
dB
mV
Dropout voltage
1.7
IlV
V
Bias current
4.2
mA
t Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a 0.33-IlF capacitor across the input and a O.l-IlF capacitor across the output.
:I: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-285
JJ,A78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS010D-JANUARY 1976- REVISED OCTOBER 1995
electrical characteristics at specified virtual junction temperature, VI
(unless otherwise noted)
PARAMETER
TEST CONDITIONST
=19 V, 10 =40 mA, TA =25°C
j1A78L12Y
MIN
Output voltage;
TYP
MAX
12
Input voltage
regulation
VI = 14.5 Vt027 V
55
VI = 16 Vto 27V
49
Ripple rejection
VI=15Vt025V,
Output voltage
regulation
10= 1 mAto 100 mA
f=120Hz
22
10=1 mAt040mA
13
Output noise voltage
f=10 Hz to 100kHz
UNIT
V
mV
42
dB
mV
70
Dropout voltage
1.7
I1V
V
Bias current
4.3
mA
t
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All characteristics are
measured with a O.33-I1F capacitor across the input and a 0.1-I1F capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI
(unless otherwise noted)
PARAMETER
TEST CONDITIONST
Output voltage;
=23 V, 10 =40 mA,
TA =25°C
.
j1A78L15Y
MIN
TYP
15
Input voltage
regulation
VI = 17.5 V to 30 V
65
VI = 20 Vto 30 V
58
Ripple rejection
VI = 18.5 Vto 28.5 V,
Output voRage
regulation
10= 1 mAto 100mA
10= 1 mAto 40 mA
15
Output noise voltage
f=10Hzt0100kHz
82
f= 120 Hz
39
25
MAX
UNIT
V
mV
dB
mV
I1V
Dropout voltage
1.7
V
BiaS current
4.6
mA
t
Pulse-testing techniques maintain TJ as close to TA as possible. Thermal effects must be taken into account separately. All charactenstics are
measured with a 0.33-I1F capacitor across the input and a O. 1-I1F capacitor across the output.
:j: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
3-286
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
f.1A78LOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVSOl 00 - JANUARY 1976 - REVISED OCTOBER 1995
APPLICATION INFORMATION
~
---r-I ..,.... h-
..f
IN
+ -----/
Vo
~ 0.1 ILF
0.33ILFTl..-_'_ _
-----~------
G
-yo
Figure 2. Positive Regulator in Negative
Configuration (VI Must Float)
Figure 1. Fixed Output Regulator
Input
1----.--
.......--+- Output
Input
R1
-...---1
R1
' - - - - L - - e - Output
R2
--+
10
10
=(VoIR1) + 10 Bias Current
Figure 4. Current Regulator
Figure 3. AdJustable Output Regulator
1N4001
20·V
Input
---.---i.._'T""""--II-4I....- - - + - -
Vo
=15 V
1N4001
- 20·V
Input
1N4001
---.-.--1
I - . - -........--~___ Vo = - 15 V
L....._ _.....
1N4001
Figure 5. Regulated Dual Supply
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-287
J.lA78LOO SERIES·
POSITIVE-VOLTAGE REGULATORS
SLVS010D - JANUARY 1976 - REVISED OCTOBER 1995
APPLICATION INFORMATION
:~
-r
I
-vo
Figure 6. Output Polarity-Reversal Protection Circuit
operation with a load common to a volta~e of opposite polarity
In many cases, a regulator powers a load that is not connected to ground but instead is connected to a voltage
source of opposite polarity (e.g., operational amplifiers, level-shifting circuits, etc.). In these cases, a clamp
diode should be connected to the regulator output as shown in Figure 6. This protects the regulator from output
polarity reversals during startup and short-circuit operation.
H ....-VO
Figure 7. Reverse-Bias Protection Circuit
reverse-bias protection
Occasionally, there exists the possibility that the input voltage to the regulator can collapse faster than the output
voltage. This could occur, for example, when the input supply is crowbarred during an output overvoltage
condition. If the output voltage is greater than approximately 7 V, the emitter-base junction of the series pass
element (internal or external) could break down and be damaged. To prevent this, a diode shunt can be
employed as shown in Figure 7.
~TEXAS· .
3-288
INSTRUMENTS
POST OFFICE BOX 655303 .. DALLAS. TEXAS 75265
~78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED
•
•
•
•
•
•
•
•
3-Terminal Regulators
Output Current Up to 500 mA
No External Components
Internal Thermal Overload Protection
High Power Dissipation Capability
Internal Short-Circuit Current Limiting
Output Transistor Safe-Area Compensation
Direct Replacements for Fairchild 11A78MOO
Series
KCPACKAGE
(TOP VIEW)
Ir I
:
OUTPUT
~...L_...J=:===: ~~~~ON
The common terminal is in electrical
contact with the mounting base.
To-220AB
description
This series of fixed-voltage monolithic integratedcircuit voltage regulators is designed for a wide
range of applications. These applications include
on-card regulation for elimination of noise and
distribution problems associated with single-point
regulation. Each of these regulators can deliver
up to 500 rnA of output current. The internal
current limiting and thermal shutdown features of
these regulators make them essentially immune
to overload. In addition to use as fixed-voltage
regulators, these devices can be used with
external components to obtain adjustable output
voltages and currents and also as the power pass
element in precision regulators.
AVAILABLE OPTIONS
PACKAGED DEVICES
HEAT-SINK MOUNTED
(KC)
5
f,1A78M05CKC
6
I1A78M06CKC
8
f,1A78M08CKC
9
f,1A78M09CKC
O°Cto 125°C
10
I1A78M10CKC
12
f,1A78M12CKC
15
f,1A78M15CKC
20
f,1A78M20CKC
f,1A78M20CKTP
24
f,1A78M24CKC
f,1A78M24CKTP
t The KTP package is only available in tape and reel.
TA
Vo(nom)
(V)
~TEXAS
CHIP
FORM
(Y)
f,1A78M05Y
f,1A78M06Y
f,1A78M08Y
f,1A78M09Y
f,1A78M10Y
f,1A78M12Y
f,1A78M15Y
f,1A78M20Y
f,1A78M24Y
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
3-289
~78MOO SERIES
.
POSITIVE-VOLTAGE REGULATORS
SLVS059A-JUNE 1976- REVISED AUGUST 1995
schematic
140 k.Q
Flesistor values shown are nominal.
~1EXAS
3-290
INSTRUMENTS
POST OFFICE BOX 65S303 • DALLAS. TEXAS 75265
JlA78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
1lA78MxxY chip information
This chip, when properly assembled, displays characteristics similar to the ~78MxxC. Thermal compression
or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
OUTPUT
COMMON
. CHIP THICKNESS: 11 MILS TYPICAL
BONDING PADS: 7 X 7 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
1111111111111111111111111111111111111111111111111111111111
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3-291
~78MOO
SERIES
.
.
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
absolute maximum ratings over operating temperature range (unless otherwise noted)t
UNIT
!lA78Mxx
-40
Input voltage, V,
V
35
I All others
Continuous total power diSSipation (see Note 1)
See Dissipation Rating Tables 1 and 2
·C
oto 150
Operating free-air (fAl, case (TC),orvirtual juncti9n.(TJ) temperature range
-65t0.150
Storage temperature range, Tstg
°c
Lead temperature 1,6 mm(1/16 inch) from case for 10 seconds .
260
°c
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the deVice. These are stress ratings only, and
functional operation of the device at these or any other Conditions beyond those indicated under "recOmmended operating conditions· is not
implied. Exposure to absolute-maXi mum-rated conditions for extended periods may affect device reliability. .
NOTE 1: To avoid exceeding the design maximum virtual junction temperature, these ratings should not be exceeded. Due to variations in
individual device electrical characteristics lind thermal resistance, the buiH-in thermal overload protection may be activated at power
levels Slightly above or below the rated dissipation.
I !lA78M20, !lA78M24
DISSIPAnoN RAnNG TABLE 1 ...; FREE-AIR TEMPERATURE
TA~25°C.
PACKAGE
POWERRAnNG
DERAnNG FACTOR
.ABOVE TA = 25°C
TA =70·C
POWER RAnNG
16mW/oC
1280mW
KC
2000mW
KTpt
t The KTP package is product preview only and derating information is not yet available.
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
PACKAGE
TC~50°C
POWER RATING
KC
KTpt
20W
DERAnNG FACTOR
ABOVE TC 50°C
TC= 125°C
POWERRAnNG
200mWfOC
..
5W
=
t The KTP package Is product preview only and derating information is not yet available.
recommended operating conditions
!lA78M05
!lA78M06
!lA78M08
!lA78M09
!lA78M10
!lA78M12
1lA78M15
!lA78M20
!lA78M24
Input voltage, V,
Output current, 10
Operating virtual junction temperature, TJ
MAX
7
8
10.5
11.5
12.5
14.5
17.5
23
27
25
25
25
26
28
30
30
35
38
500
125
0
~··.TEXAS
3-292
MIN
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
UNIT
V
mA
·C
~78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A - JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 10 V, 10 = 350 mA, TJ = 25°C
(unless otherwise noted)
11A78M05C
PARAMETER
TEST CONDITIONSt
Output voltage=!:
V, = 7 V to 20 V,
TJ = O°C to 125°C
MIN
TYP
4.S
5
4.75
V, =7Vt025V
Input voltage regulation
10=200 rnA
V,=SVtolSV,
f=120Hz
Ou1pu1 vo~age regulation
3
100
1
50
10= 100 rnA,
TJ = O°C to 125°C
62
10 =300 rnA
62
dB
20
100
10
50
'0=5mA
f = 10 Hz to 100 kHz
Bias current
mV
mV/oC
-1
TJ = O°C to 125°C
Dropout voltage
40
200
2
2.5
IlV
V
6
rnA
4.5
Short-circuit ou1pu1 current
V
SO
10= 5 rnA to 200 rnA
Temperature coefficient of output voltage
UNIT
mV
10= 5 rnA to 500 rnA
Output noise voltage
Bias current change
5.2
5.25
V, =SVt020V
V,=SVt025V
Ripple rejection
MAX
10=200 rnA,
TJ = O°C to 125°C
V, = S V to 25 V,
O.S
10= 5 rnA to 350 rnA
TJ = O°C to 125°C
0.5
rnA
V, =35V
Peak outpu1 current
300
rnA
0.7
A
t All characteristics are measured With a 0.33-IlF capacitor across the Inpu1 and a O.l-IlF capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
=!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 11 V, 10 = 350 mA, TJ = 25°C
(unless otherwise noted)
.
PARAMETER
Output voltage =!:
MIN
5.75
10=5 rnA to 350 rnA,
V, = S V to 21 V,
=200 mA
Input voltage regulation
10
Ripple rejection
V,=9Vto19V,
Output voltage regulation
11A78M06C
TEST CONDITIONSt
f=120Hz
TJ = O°C to 125°C
6.25
6.3
V, =SVt025V
5
100
V, =9Vt025V
1.5
50
10= 100 rnA,
TJ = O°C to 125°C
59
10=300 rnA
59
120
10
60
'0=5mA,
TJ =O°Cto 125°C
Dropou1 vo~age
10 =200 rnA,
mV/"C
IlV
V
6
O.S
TJ=0°Cto125°C
10 = 5 rnA to 350 rnA, TJ = O°Cto 125°C
0.5
V, =35V
Peak output current
mV
45
4.5
V, =9Vt025 V,
mV
-1
2
Bias current
V
dB
20
f = 10 Hz to 100 kHz
UNIT
SO
10= 5 mAto 500 rnA
Ou1pu1 noise voltage
Short-circuH output current
6
5.7
MAX
10=5 mA to 200 mA
Temperature coefficient of output voltage
Bias current change
TYP
rnA
rnA
270
rnA
0.7
A
t All characteristics are measured with a 0.33-IlF capacitor across the input and a O.l-IlF capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects rriust be taken into account separately.
=!: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3--293
~78MOO SERIES
,,
POSITIVE-VOLTAGE REGULATORS
SLVso59A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI
(unless otherwise noted)
,
PARAMETER
=14 V, 10 =350 rnA, TJ =25°C
TEST CONomoNst
MIN
11A78M08C
TYP
MAX
7.7
Output voltage:l:
VI = 10.5 Vto 23 V,
TJ = O°C to 125°C
Input voltage regulation
10 =200 rnA
Ripple rejection
VI = 11.5 V to 21.5 V,
10 = 5 rnA to 350 rnA,
f=I20Hz
8
7.6
8.3
8.4
VI = 10.5 Vto 25 V
6
100
VI=IIVt025V
2
50
'10= 100 rnA,
TJ =O°C to 125°C
56
56
10 = 300 rnA
UNIT
V
mV
dB
80
10 =5mAt05oornA
25
160
10= 5 rnA to 200 rnA
10
80
Temperature coefficient of output voltage
10=5rnA,
-1
mVrC
Output noise voltage
f = 10 Hz to 100 kHz
52
!IV
V
Output voltage regulation
TJ = O°C to 125°C
2
Dropout VOltage
Bias current
4.6
Bias current change
Short"l:ircuit output current
10 =200 rnA, .
VI = 10.5 V to 25 V,
6
0.8
TJ = O°C to 125°C
10 = 5 rnA to 350 rnA, TJ=0°CtoI25°C
0.5
VI=35V
Peak output current
mV
rnA
rnA
250
rnA
0.7
A
t All characteristics are measured with a 0.33-!lF capacitor across the input and a O.I-!lF capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
:I: This specification applies only for dc power diSSipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperatur~, VI
(unless otherwise noted)
PARAMETER
=16 V,IO =350 rnA, TJ =25°C
TEST CONomoNst
MIN
11A78M09C
TYP
MAX
8.6
Output voltage:l:
VI. = 11.5 Vt024 V,
TJ=0°CtoI25°C
Input voltage regulation
10=200 rnA
Ripple rejection
VI = 13Vt023 V,
Output voltage regulation
10 = 5 rnA to 350 rnA,
f=120Hz
VI = 11.5 Vt026 V
6
100
VI = 12Vto26V
2
50
10= 100 rnA,
TJ = O°C to 125°C
56
10 = 300 rnA
56
180
10
90
Output noise voltage
f=10Hztol00kHz
Dropout voltage
Pea~
mVrC
58
!IV
V
4.6
VI = 11.5 V to 26 V,
10 =200 rnA,
0.5
10 =5 rnA to 350 rnA, TJ = O°C io 125°C
VI,=35V
6
0.8
TJ = O°C to 125°C
output Cl!rrent
mV
-1
2
Bias current
mV
dB
25
TJ = O°C to 125°C
V
80
10 = 5mA to 200 rnA
10=5mA,
Short"l:ircuit output current
9.5
10=5mA to 500 rnA
Temperature coefficient of output voltage
Bias current change
9
8.5
UNIT
9.4
rnA
rnA
250
rnA
0.7
A
tAli charactenstlCll are measured with a O.33-!lF capacitor across the Input and a O.I-!lF capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
:I: This specification applies only for dc power dissipation permitted by absolute maximum ratings.
~TEXAS
3-294
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
J,LA78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 17 V, 10 = 350 rnA, TJ = 25°C
(unless otherwise noted)
PARAMETER
Output voltage
*
MIN
TYP
9.6
VI=12.5Vt025V,
TJ = O°C to 125°C
Input voltage regulation
10 = 200 mA
Ripple rejection
VI=15Vt025V,
Output voHage regulation
I1A78M10C
TEST CONDITIONSt
10 = 5 mA to 350 mA,
f= 120Hz
10
9.5
10.5
VI = 12.5 V to 28 V
7
100
VI = 14 Vto 28 V
2
50
10=100mA,
TJ = O°C to 125°C
59
10=300mA
55
200
10
100
10-5mA,
TJ - O°C to 125°C
Dropout voltage
mV/oC
64
I1V
V
4.7
Short-circuit output current
VI = 12.5Vt028V,
10=200mA,
6
0.8
TJ = O°C to 125°C
10 =5 mAt0350 mA, TJ = O°C to 125°C
0.5
VI=35V
Peak output current
..
mV
-1
2
Bias current
mV
dB
25
f=10Hztol00kHz
V
80
10= 5 mAto 500 mA
Output noise voltage
UNIT
10.4
10=5 mAt0200 mA
Temperature coefficient of output voltage
Bias current change
MAX
mA
mA
245
mA
0.7
A
tAli charactenstics are measured With a 0.33-IlF capacitor across the Input and a O.l-I1F capaCitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
This specification applies only for dc power dissipation permitted by absolute maximum ratings.
*
electrical characteristics at specified virtual junction temperature, VI = 9 V, 10 = 350 rnA, TJ = 25.o C
(unless otherwise noted)
PARAMETER
Output voltage
*
TEST CONDITIONSt
VI = 14.5 Vto 27 V,
TJ = O°C to 125°C
Input voltage regulation
10=200mA
Ripple rejection
VI=15Vt025V,
10 = 5 mA to 350 mA,
f= 120 Hz
11A78M12C
MIN
TYP
MAX
11.5
12
12.5
11.4
12.6
VI = 14.5 Vto 30 V
8
100
VI = 16Vt030V
2
50
10=100mA,
TJ = OOQ to 125°C
55
10 =300 mA
55
UNIT
V
mV
dB
80
10 = 5 mA to 500 mA
25
240
10= 5 mAt0200 mA
10
120
Temperature coefficient of output voltage
10=5mA
-1
mV/oC
Output noise voltage
f=10Hztol00kHz
75
I1V
V
Output voltage regulation
Dropout voltage
2
Bias current
4.8
Bias current change
Short-circuit output current
VI = 14.5 Vto 30 V,
10 =200 mA,
10 = 5 mA to 350 mA, TJ = O°C to 125°C
VI =35V
Peak output current
..
6
0.8
TJ = O°C to 125°C
0.5
mV
mA
mA
240
mA
0.7
A
tAli charactenstlcs are measured With a O.33-IlF capacitor across the Input and a O.l-I1F capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.'
This specification applies only for dc power dissipation permitted by absolute maximum ratings.
*
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
3-295
~78MOO
SERIES
POSITIVE-VOLTAGE REGULATORS
/
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 23 V, 10 =350 mA, TJ = 25°C
(unless otherwise noted)
PARAMETER
Output voltage
!1A78M15C
TEST.CONoinoNst
MIN
TYP
14.4
*
VI = 17.5 V to 3OV,
TJ = O°C to 125°C
10= 5 mAt0350 mA,
10=200mA
Ripple rejection
VI = 18.5 V to 28.5 V,
Output voltage regulation
VI =20Vt03OV
1=120Hz
15
14.25
VI = 17.5 V to 30 V
Input voltage regulation
MAX
10= 100mA,
TJ = O°C to 125°C
54
10=300mA
54
15.75
10
100
3
50
25
300
10
150
Output noise voltage
1= 10 Hz to 100kHz
TJ = O°C to 125°C
Dropout voltage
mV/oC
90
I1V
V
4.8
"1= 17.5V to 30 V,
Bias current change
10=200mA,
0.5
10=5 mA to 350 mA, TJ = O°C to 125°C
Short-circuit output currerit
6
0.8
TJ = O°C to 125°C
VI=35V
Peak output current
mV
-1
2
Bias current
mV
dB
10=5 mAt0200 mA
10=5mA,
V
70
10=5 mAtoSOOmA
Temperature coefficient of output voltage
UNIT
15.6
mA
mA
240
mA
0.7
A
t All characteristics are measured with a O.33-I1F capacitor across the input and a 0.1-I1F capacitor across the output. Pulse-testing techniques.
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
This specification applies only lor de power dissipation permitted by absolute maximum ratings.
*
electrical characteristics at specified virtual junction temperature, VI = 29 V, 10 = 350 mA, TJ = 25°C
(unless otherwise noted)
PARAMETER
Output voltage
!1A78M20C
TEST CONOITIONSt
19.2
*
VI - 23 V to 35 V,
TJ = O°C to 125°C
Input voltage regulation
10=200mA
Ripple rejection
VI =24 Vto34 V,
10 =5 mA to 350 mA,
1= 120 Hz
Output voltage regulation
19
10
100
5
50
.53
53
400
10
200
10.=.5mA,
-1.1
TJ = O°C to 125°C
I1V
V
2
Bias current
4.9
VI = 23 V to 35 V,
10=5mAt03~mA,
.10=200mA,
0.5
TJ = O°C to 125°C
I
VI =35V
Peak output current
6
0.8
TJ = O°C to 125°C
mV
mVI"C
110
.'
mV
dB
30
1= 1{) Hz to 100 kHz
V
70
10 '" 5 mA to 200 mA
Temperature Coeffieilent ()I output voltage
Bias current change
21
VI=23Vto.35V
10= 100mA,
TJ = O°C to 125°C
UNIT
20.8
10",5mAto500mA
Output nols,! voltage
Short'-circuit output currerit
20
MAX
VI =24 Vt035V
10=300mA
Dropout voltage
TYP
MIN
mA
mA
240
mA
0.7
A
tAli charactenstlcs are measured With a O.33-I1F capacitor across the Input and a 0.1-I1F capacitor' across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
This specification applies only lor dc power dissipation permitted by absolute maximum ratings.
*
'~TEXAS
.
INSTROMENTS
3-296
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
J.LA78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 33 V, 10 = 350 rnA, TJ = 25°C
(unless otherwise noted)
PARAMETER
1!A78M24C
TEST CONDITIONSt
MIN
23
Output voltage:l:
VI = 27 V to 38 V,
TJ = O°C to 125°C
Input voltage regulation
10=200 rnA
Ripple rejection
VI = 28 V to 38 V,
Outpu1 voltage regulation
10 = 5 rnA to 350 rnA,
f= 120Hz
TYP
24
22.8
25.2
VI = 27 V to 38 V
10
100
VI = 28 V to 38 V
5
50
10= 100 rnA,
TJ = O°C to 125°C
50
10=300 rnA
50
480
10
240
10=5mA,
TJ = O°C to 125°C
Dropout voltage
mV/"C
170
I1V
V
5
Bias current change
VI = 27 V to 38 V,
10 =200 rnA,
10= 5 rnA to 350 rnA, TJ = O°C to 125°C
Peak output current
..
6
0.8
TJ = O°C to 125°C
VI=35V
mV
-1.2
2
Bias current
mV
dB
30
f=10Hzto1ookHz
V
70
10= 5 rnA to 200 rnA
Output noise voltage
UNIT
25
10= 5 rnA to 500 rnA
Temperature coefficient of outpu1 voltage
Short-circuit output current
MAX
0.5
rnA
rnA
240
rnA
0.7
A
tAli charactenstlcs are measured With a 0.33-I1F capacitor across the Input and a O.l-I1F capacitor across the Ou1put. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
:I: This specification applies only for dc power dissipation permitted by absolu1e maximum ratings.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-297
~A78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
electrical characteristics at specified virtual junction temperature, VI = 10 V, 10 = 350 rnA, TJ = 25°C
(unless othe.rwise noted)
PARAMETER
ILA78MOSY
TEST CONDITIONSt
MIN
Output voltage =1=
MAX
10 =200 rnA
Ripple rejection
VI = 8 Vto 18 V,
I VI = 7 V to 25 V
l VI = 8 V to 25 V
10=300 rnA,
3
mV
1
f=120Hz
dB
80
10 =5mA to 500 rnA
UNIT
V
5
Input voltage regulation
Output voltage regulation
TYP
20
mV
10= 5 rnA to 200 rnA
10
Temperature coefficient of output voltage
10=5mA
-1
mV/oC
Output noise voltage
f=10Hztol00kHz
40
ILV
V
Dropout voltage
2
Bias current
Short-circuit output current
VI =35V
Peak output current
4.5
rnA
300
rnA
0.7
A
tAli characterrstlcs are measured With a 0.33-ILF capacItor across the Input and a O.I-ILF capaCItor across the output Pulse-testIng technIques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
:I: This specilication applies only lor dc power dissipation permitted by absolute maximum ratings.
electrical characteristics at specified virtual junction temperature, VI = 11 V, 10 = 350 rnA, TJ = 25°C
(unless otherwise noted)
PARAMETER
1!A78M06Y
TEST CONDITIONSt
MIN
Input voltage regulation
10=200 rnA
Ripple rejection
VI=9VtoI9V,
Output voltage regulation
Temperature coefficient 01 output voltage
Output noise voltage
I VI = 8 V to 25 V
I VI = 9 V to 25 V
10=300 rnA,
1= 120 Hz
5
1.5
80
10= 5 rnA to 500 rnA
20
10 =5 rnA to 200 mA
10
10=5mA
1= 10 Hz to 100 kHz
Dropout voltage
VI =35V
Peak output current
MAX
UNIT
V
mV
dB
mV
-1
mV/oC
45
ILV
V
2
Bias current
Short-circuit .output current
TYP
6
Output voltage =1=
4.5
rnA
270
rnA
0.7
A
tAli characterrstlcs are measured WIth a 0.33-ILF capacItor across the Input and a O.I-ILF capacItor across the output Pulse-testmg techmques
maintain TJ as close to TA as possible. Thennal effects must be taken into account separately.
:I: This specification applies onlY for dc power dissipation pennitted by absolute maximum ratings.
~TEXAS
INSTRUMENTS
3-298
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~A78MOO SERIES
POSITIVE-VOLTAGE REGULATORS
SLVS059A- JUNE 1976 - REVISED AUGUST 1995
=
=
electrical characteristics at specified virtual junction temperature, VI 14 V, 10 350 rnA, TJ
(unless otherwise noted)
PARAMETER
1lA78M08Y
TEST CONDITIONSt
MIN
Output voltage;
MAX
8
Input voltage regulation
10 =200 mA
Ripple rejection
VI = 11.5 V to 21.5 V,
Output voltage regulation
TYP
10=300mA,
! VI = 10.5 Vto 25 V
6
IVI=11Vt025V
2
f= 120 Hz
UNIT
V
mV
80
dB
25
10 = 5 mAto500 mA
=25°C
mV
10=5mA to 200 mA
10
Temperature coefficient of output voltage
10=5mA
-1
mV/"C
Output noise voltage
f = 10 Hz to 100 kHz
52
2
flV
V
Dropout voltage
Bias current
Short-circu~
output current
VI =35V
Peak output current
4.6
mA
250
mA
0.7
A
t All characteristics are measured With a 0.33-flF capac~or across the Input and a 0.1-flF capacitor across the output. Pulse-testing techniques
maintain TJ as close to TA as possible. Thermal effects must be taken into account separately.
:t: This specification applies only for
:e~
:!!
-~
rg
O~
'" en<
t
en
electrical characteristics over recommended operating free-air temperature range, Vee =20V, f = 20 kHz
(unless otherwise noted)
!<
~
error amplifier section
I
PARAMETER
TEST CONDITIONSt
i~~d
~f
i~
~
TYP*
MAX
MIN
SG3524Y
TYP*
MAX
MIN
TYP*
MAX
UNIT
Input offset voltage
VIC=2.SV
O.S
S
2
10
2
mV
liB
Input bias current
VIC=2.SV
2
10
2
10
2
IIA
80
dB
VICR
Common-mode input voltage range
CMMR
Common:mode rejection ratio
72
TA=2SoC
Output swing
TA=2SoC
60
80
1.8
to
3.4
80
1.8
to
3.4
V
70
70
dB'
3
3
3
MHz
O.S
3.8
0.5
3.8
O.S
3.8
V
t For conditions shown as MIN or MAX, use the appropriate yalue specified under recommended operating conditions.
:j: All typical values, except for temperature coefficients, are at TA = 25°C
TEST CONDlTlONSt
SG2534, SG3524
SG3524Y
UNIT
MAX
VCE=4OV
0.01
SO
0.01
IIA
Collector-emitter saturation voltage
IC=50mA
1
2
1
V
Vo
Emitter output voltage
VC=20V,
IE =-250 IIA
tr
Turn-off voltage rise time
tf
Tum-on voltage fall time
Collector off-state current
Vsat
MIN
MIN
TYP*
MAX
·40
Collector-emitter breakdown voltage
17
V
18
18
V
RC=2kn
0.2
0.2
J.IS
RC=2kn
0.1
0.1
J.IS
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values, except for temperature coeffiCients, are at TA = 25°C
comparator section
PARAMETER
SG2534, SG3524
TEST CONDITIONSt
VIT
Input threshold voltage at COMP
liB
Input bias current
MIN
TYP*
MAX
SG3524Y
MIN
TYP*
MAX
UNIT
45%
Maximum duty cycle, each output
Zero duty cycle
Maximum duty cycle
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values, except for temperature coeffiCients, are at TA = 2SoC
~
:ll
~
en
m
o
~
Gl
C
~
r'I:t!.~
::len
zC)
C)w
UI
'V.~
C~
r-en
enC)
'1'w
UI
:E
_N
=I~
:::t:
5:
o
C
C
!i
o
TYpt
VIBRlCE
;=
CUI
N
r-
output section
PARAMETER
:ll
~
70
Unity-gain bandwidth
. Bl
~z""
~(I)".
MIN
SG3524
VIO
Open-loop voltage amplification
~
SG2524
?t;
:Jun
mC)
C)N
1
1
3.5
3.S
-1
-1
V
IIA
~
electrical characteristics over recommended operating free-air temperature range, vee = 20 V, f = 20 kHz
(unless otherwise noted)
current limiting section
PARAMETER
TEST CONDITIONS
Input voltage range (either input)
VI
V(SENSE)
Sense voltage at TA = 25°C
V(lN+) - V(IN-);?; 50 mY,
Temperalurecoefficient of sense voltage
V(COMP)=2V
SG2524
MIN
TYpt
SG3524
MAX
MIN
-1
to
-1
to
1
1
175
200
225
175
TYpt
SG3524Y
MAX
MIN
MAX
UNrr
V
200
225
175
0.2
0.2
TYpt
200
225
0.2
mV
mV/"C
t All typical values, except for temperature coefficients, are at TA = 25°C.
total device
PARAMETER
~
0_...
~~~
~i1g~
~t:
1st
Standby current
TEST CONDITIONS
VCC=40V,
IN+at2V,
IN -, CURR LIM +, CT, GND, CaMP, EMIT 1, EMIT 2 grounded
All other inputs and outputs open
SG2524, SG3524
MIN
SG3524Y
TYpt
MAX
8
10
MIN
TYpt
8
MAX
UNrr
mA
t All typical values, except for temperature coefficients. are at TA = 25°C.
':~
::IJ
!~
m
G')
C
r
!i
~
~
Z
III
(Jl
<
(Jl
0
...,
~
I
G')
"V
C
r(/)
(/)G')
mN
..,> :e~
-~
Jl
F
::l
....C-
~
O~
eo
I
Jl
(Jl
m
c
c>
G>
c
~
t
(/)
::CG')
s:W
C~
C(/)
rG')
!iw
O~
'" ~~
CD
CD
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A- APRIL 1977 - REVISED AUGUST 1996
PARAMETER MEASUREMENT INFORMATION
VREF
Vce =8Vt040V
I
2kn ? 10kg
1
115
VCC
SG2524 or SG3524
2kg
La--o----!Q. SHUTDOWN
2
10kn
~
4
1 kg
5
IN+
OSCOUT L-(Open)
REF OUr
INCOMP
CURRLlM+
CURRlIM-
COL 2 13
COL 1
EMIT 2
2kn
~
II
16
.1
T
2kn
lW
:2 kn
1W
VREF
O.lJ.1F
-=-
12
Outputs
..!!...
EMIT 1 ~
7
6
CT
RT
GND
RT
81
Figure 1. General Test Circuit
VCC
Circuit Under Test
2kn
=VCC
..___t--+-- Output
~10~%.;..._ _.....;1~O%J' ______
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 2. Switching Times
~TEXAS
4-10
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
=0V
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A- APRIL 1977 - REVISED AUGUST 1996
TYPICAL CHARACTERISTICS
OPEN-LOOP VOLTAGE AMPLIFICATION
OF ERROR AMPLIFIER
vs
FREQUENCY
CD
'V
I
90
RL=
1M
I I I ~I
1111111
co
OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
VCC=20V
TA = 25°C
400k
1"\
60
RL=1 Mil
50
RL=300kn
I
C
II
40k
:;,
40
RL
I
I'G
=100 kn
RL=30kn
30
4k
CT= 0.03 !IF
I
1k
1k
10k
lOOk
........
......
40
VCC=20V
TA=25°C
RL Is resistance from COMP to ground
-10
100
.......
CT=0.1!1F
.,2
I"
.......... ......
........
0
~
o
........
......... ~
10k
..
I"
r--.....
100 k
{;'
CT='O
CT = 0.001 !IF't
CT = 0.003 !IF
CT = 0.01 !IF
.....
~
10
1M
10M
1
2
Frequency - Hz
4
7
10
20
40
70 100
RT - Timing Resistance - kn
Figure 3
Figure 4
OUTPUT DEAD TIME
vs
TIMING CAPACITANCE
10
..
4
::i
I
I
1=
V
'i
c!
s
t
0
,;
./
-
i""'"
0.4
0.1
0.001
0.004
0.01
0.04
CT - Timing Capacitance - !IF
0.1
FigureS
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-11
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLvsonA-APRIL 1977 - REVISED AUGUST 1996
PRINCIPLES OF OPERATIONt
The SG2524 is a fixed-frequency pulse-wiclth-modulation voltage-regulator control circuit. The regulator operates at
a fixed frequency that is programmed by one timing resistor, RT, and one timing capacitor CT. RT establishes a
constant charging current for CT. This results in a linear voltage ramp at CT, which is fed to the comparator providing
linear control of the output pulse duration (width) by the error amplifier. The SG2524 contains an on-board 5-V
regulator that serves as a reference as well as supplying the SG2524 internal regulator control circuitry:The internal
reference voltage is divided externally by a resistor ladder network to provide a reference within the common-mode
range of the error amplifier as shown in Figure 6, or an external reference may be used. The output is sensed by a
second resistor divider network and the error signal is amplified. This voltage is then compared to the linear voltage
ramp at CT. The resulting modulated pulse out of the high-gain comparator is then steered to the appropriate output
pal?s transistor (01 or 02) by the pulse-steering flip-flop, which is synchronously toggled by the oscillator output. The
oscillator output pulse also serves as a blanking pulse to ensure both outputs are never on simultaneously during the
transition times. The duration of the blanking pulse is controlled by the value of CT. The outputs may be applied in
a push-pull configuration in which their frequency is half that of the base oscillator, or paralleled for single-ended
applications in which the frequency is equal to that of the oscillator. The output of the error amplifier shares a common
input to the comparator with the current-limiting and shut-down circuitry and can be overridden by signals from either
of these inputs. This common point is .also available externally and may be employed to control the gain of, to
compensate the error amplifier, or to provide additional control to the regulator.
APPLICATION INFORMATIONt
oscillator
The oscillator controls the frequency of the SG2524 and is programmed by RT and CT as shown in Figure 4.
f=~
RTC T
where RT is in kQ
CT is in I1F
f is in kHz
Practical values of CT fall between 0.001 and 0.1 11F. Practical values of RT fall between 1.8 and 100 kil. This
results in a frequency range typically from 130 Hz to 722 kHz.
blanking
The output pulse of the oscillator is used as a blanking pulse at the output. This pulse duration is contrOlled by
the value of CT as shown in Figure 5. If small values of CT are required, the oscillator output pulse duration may
still be maintained by applying a shunt capacitance from OSC OUT to ground.
synchronous operation
When an external c.lock is desired, a clock pulse of approximately 3 V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is approximately 2 kil. In this configuration, RT CT must
be selected for a clock period slightly greater than that of the external clock.
t Throughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
4-12
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A - APRIL 1977 - REVISED AUGUST 1996
APPLICATION INFORMATIONt
synchronous operation (continued)
If two or more SG2524 regulators are to be operated synchronously, all oscillator output terminals should be
tied together. The oscillator programmed for the minimum clock period is the master from which all the other
SG2524s operate. In this application, the CTRT values of the slaved regulators must be set for a period
approximately 10% longer than that of the master regulator. In addition, CT (master) 2 CT (slave) to ensure
that the master output pulse, which occurs first, has a longer pulse duration and subsequently resets the slave
regulators.
=
voltage reference
The 5-V internal reference may be employed by use of an external resistor divider network to establish a
reference common-mode voltage range (1.8 V to 3.4 V) within the error amplifiers as shown in Figure 6, or an
external reference may be applied directly to the error amplifier. For operation from a fixed 5-V supply, the
internal reference may be bypassed by applying the input voltage to both the Vee and VREF terminals. In this
configuration, however, the input voltage is limited to a maximum of 6 V.
5kO
,-------4...._- REF OUT
To Positive
Output Voltage
REF OUT
5kO
R2
2.5V
5 kg
R1
2.5V
5 kg
R1
R2
To Negative
Output Voltage
VO=2.5VR1~R2
Figure 6. Error Amplifier Bias Circuits
error amplifier
The error amplifier is a differential-input transconductance amplifier. The output is available for dc gain control
or ac phase compensation. The compensation node (CaMP) is a high-impedance node (RL = 5 MO). The gain
of the amplifier is Av (0.002 0-1)RL and can easily be reduced from a nominal 10,000 by an external shunt
resistance from CaMP to ground. Refer to Figure 3 for data.
=
compensation
CaMP, as discussed above, is made available for compensation. Since most output filters introduce one or more
additional poles at frequencies below 200 Hz, which is the pole of the uncompensated amplifier, introduction
of a zero to cancel one of the output filter poles is deSirable. This can best be accomplished with a series RC
circuit from CaMP to ground in the range of 50 kQ and 0.001 /IF. Other frequencies can be canceled by use
of the formula f '" 1IRC.
t Throughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-13
SG2524, S,G3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A-APRIL 1977 - REVISED AUGUST 1996
APPLICATION INFORMATIONt
shut-down circuitry
COMP can also be employed to introduce extemal control of the SG2524. Any circuit that can sink 200 J.IA can
pull the compensation terminal to ground and thus disable the SG2524.
In addition to constant-current limiting. CURR LIM + and CURR LlM- may also be used in transformer-coupled
circuits to sense primary current and shorten an output pulse should transformer saturation occur. CURR LlMmay also be grounded to convert CURR LlM+ into an additjonal shut-down terminal.
current limiting
A current-limiting sense amplifier is provided in the SG2524. The current-limiting sense amplifier exhibits a
threshold of 200 mV ±25 mV and must be applied in the ground line since the voltage range ofthe inputs is limited
to 1 V to -1 V. Caution should be taken to ensure the -1 V limit is not exceeded by either input. otherwise
damage to the device may result.
Foldback current limiting can be provided with the network shown in Figure 7. The current-limit schematic is
shown in Figure 8.
EMIT 1
EMIT 2
11
~
Va
~~
1 (
10(max) = Rs 200 mV
R1
;;:
SG2524
r:
I
R2
CURR LlM-
Rs
5
T
CURR LlM+ 4
_2oomV
Rs
as -
rt7
Figure 7. Foldback Current Limiting for Shorted Output Conditions
CaMP
Comparator
Constant-Current Source
Error AmplHier
CURR LlM-
CURR LlM+
Figure 8. Current-limit Schematic
t Throughout these discussions. references to the SG2524 apply also to the SG3524.
~TEXAS
4-14
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 71;265
+
Va R2 )
R1 + R2
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A- APRIL 1977 - REVISED AUGUST 1996
APPLICATION INFORMATIONt
output circuitry
The SG2524 contains two identical npn transistors, the collectors and emitters of which are uncommitted. Each
transistor has antisaturation circuitry that limits the current through that transistor to a maximum of 100 mA for
fast response.
general
There are a wide variety of output configurations possible when considering the application of the SG2524 as
a voltage regulator control circuit. They can be segregated into three basic categories:
1. Capacitor-diode-coupled voltage multipliers
2. Inductor-capacitor-implemented single-ended circuits
3. Transformer-coupled circuits
Examples of these categories are shown in Figures 9, 10 and 11 respectively. Detailed diagrams of specific
applications are shown in Figures 12 through 15.
D1
-vo
Figure 9. Capacitor-Diode-Coupled
Voltage-Multipli~r Output Stages
Figure 10. Single-Ended Inductor Circuit
t Throughout these discussions. references to the SG2524 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS, TEXAS 75285
4-15
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A - APRIL 1977 - REVISED AUGUST 1996
APPLICATION INFORMATIONt
Vo
PUSH-PULL
FLYBACK
Figure 11. Transformer-Coupled Outputs
VCC= 15V
15
15kO
5k!l
O.1IlF
~I
5kO
5k!l
1
2k!l
SG2524
/I
O.01IlF
7CT
EMIT 1
COL 1
2 IN+
16
REF OUT
11
..ll....
CURRLIM+
t-- -5V
20mA
Ilo..l
' ... 1
I~
+1\
4
COMP ~
OSCOUT
....
Ii
~ SHUTDOWN CURRLIM- 5
-----.!
1N916
20llF
COL 2 13
EMIT 2 14
6 RT
'1l
1N916
VCC
1 IN-
~~
1N916
:::: ~ 50llF
+
GND
8
rt7
Figure 12. Capacitor-Diode Output Circuit
\
tThroughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
4-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SG2524, SG3524, SG3524Y
REGULATING PULSE-WIDTH MODULATORS
SLVS077A- APRIL 1977 - REVISED AUGUST 1996
APPLICATION INFORMATIONt
VCC=5V
-1
~3000
115
VCC
1 IN5kU
2
5kO
SG2524
IN+
~ REF OUT
6
RT
2kU
___----)\\11------------'7'-1
/I
0.02 ~F
~
EMIT 1
..!L I--
COL 1
~
0.1
~F
1
~.50T
20mA
SOIlF:::-::!
~ .........
IP\
COL 2 ~
;916
14
EMIT 2 ~--~----~------------~~~~ TI~9A
CURR LIM+
~
SHUTDOWN CURR LIM-
~
CT
f
1 MO
l
-15V
6200
9
20SCOUT
COMP
~100
GND
10
Input
Return
Figure 13. Flyback Converter Circuit
TlP115
VCCI26V
0.9mH
r-=---~
5kU
5kU
1
5kU
0.1
\1
2
5kU~
~F
~I
15
3kU
16
6
7
II
0.021lF
VCC
IN-
EMIT 1
SG2524
COL 1
IN+
REF OUT
COL 2
RT
EMIT 2
CT
CURR LIM +
11
I
I
I~
I
--
I~I
L:_
.J
~
13
;::
n
5V
1A
r:+ 50
1N3660
3kO
14
4
~ SHUT
--.-!
CURR LlM- 5
DOWN
9
OSCOUT
COMP GND
8
*0.001
~F
SOkU
;h
0.10
Input Retum
Figure 14. Single-Ended LC Circuit
tThroughout these discussions, references to the SG2524 apply also to the SG3524.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-17
SG2524, SG3524, SG3524Y
REGULATING PULSE~WIDTH MODULATORS
SLvsonA-APRIL 19n - REVISED AUGUST 1996
APPLICATION INJ=ORMATlONt
VCC=28V
15
1 kO
lW
Vee
11
5kO
5kO
1
5kO
O~II1F
II
HI
5kO~
2kO
O.OlI1F
IN-
2 IN+
16
6
7
EMIT 1
SG2524
COLI
REF OUT
CT
T1P31A
r:,~lmH
10~
~
20T
115T'
-20T
5TI
~
R~
1000
CURRLlM+
TIR101A
O~)
COL 2 r1LEMIT 2
RT
1 kO
lW)
14
+
I 1500I1F ;::
I
"
I---
:J
"-h- )
4
~
I-- +
ITIP31A
--1!l
SHUT CURR L1M- 15
3 DOWN
9
---"- OSC OUT
COMP r----, 0 001 F
GND
8
*'
0.10
11
20kO
,..
""= " 100 I1F
fi7
Figure 15. Push-Pull Transformer-Coupled Circuit
tThroughout these discussions, references to the SG2524 apply also to the.SG3524.
~TEXAS
4-18
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
5V
5A
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
•
Complete PWM Power Control Circuitry
•
Uncommitted Outputs for 200-mA Sink or
Source Current
•
Output Control Selects Single-Ended or
Push-Pull Operation
•
•
TL494C, TL4941 .•• D, N, OR PW PACKAGE
TL494M •.• J PACKAGE
(TOP VIEW)
11N+
16
21N+
11N-
15
21N-
FEEDBACK
14
REF
13
OUTPUTCTRL
12
VCC
C2
Internal Circuitry Prohibits Double Pulse at
Either Output
Variable Dead Time Provides Control Over
Total Range
•
Internal Regulator Provides a Stable 5-V
Reference Supply With 5% Tolerance
•
Circuit Architecture Allows Easy
Synchronization
RT
11
GND
10
E2
C1
9
E1
TL494M • •• FK PACKAGE
(TOP VIEW)
I
+
+
I
~~~~~
description
FEEDBACK
DTC
NC
CT
RT
The TL494 incorporates on a single monolithic
chip all the functions required in the construction
of a pulse-width-modulation control circuit.
Designed primarily for power supply control, this
device offers the systems engineer the flexibility to
tailor the power supply control circuitry to a
specific application.
2
3
1 20 19
18
6
16
REF
OUTPUTCTRL
NC
7
15
VCC
8
14
9 1011 1213
4
17
5
C2
~u~w~
C!'
The TL494 contains two error amplifiers, an
on-chip adjustable oscillator, a dead-time control
(DTC) comparator, a pulse-steering control
flip-flop, a 5-V, 5%-precision regulator, and
output-control circuits.
NC - No internal connection
FUNCTION TABLE
The error amplifiers exhibit a common-mode
voltage range from -0.3 V to VCC -2 V. The
dead-time control comparator has a fixed offset
that provides approximately 5% dead time. The
on-chip oscillator may be bypassed by terminating
RT to the reference output and providing a
sawtooth input to CT, or it may drive the common
circuits in synchronous multiple-rail power
supplies.
INPUT TO
OUTPUT
CTRL
OUTPUT FUNCTION
VI=GND
VI =Vref
Single-ended or parallel output
Normal push-pull operation
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SURFACE MOUNT
(D)t
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
PLASTIC DIP
(N)
SHRINK
SMALL OUTLINE
(PW)*
TL494CPW
0°Cto70°C
TL494CD
-
-
TL494CN
-40°C to 85°C
TL4941D
-
TL494IN
-55°C to 125°C
-
TL494MFK
TL494MJ
-
-
-
CHIP
FORM
(V)
TL494Y
-
tThe D package is available taped and reeled. Add R suffix to device type (e.g., TL494CDR).
:j: The r>w package is only available left-end taped and reeled.
-!I1TEXAS
copyright © 1995, Texas Instruments Incorporated
On prod"" compliant .. IIILoSTJIoI83, CIMIa,IU~'"
. . - u..... OIherwt.. noIod. On 111_ prod..... producIIOn
procouIng _ not _
..~Iy InclUdollltklg 01 all penmeI8rL
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
4-19
TL494C, TL4941, TL494M, TL494V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
description (continued)
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. The
TL494 provides for push-pull or single-ended output operation, which may be selected through the outputcontrol function. The architecture of this device prohibits the possibility of either output being pulsed twice during
push-puli operation.
The TL494C is characterized for operation from O°C to 70°C. The TL4941 is characterized for operation from
-40°C to 85°C. The TL494M is characterized for operation from -55°C to 125°C.
functional block diagram
OUTPUTCTRL
(see Function Table)
13
-r:=::::J
RT ~6~_ _
CT~S~--~--~__--J
4
=0.1 V
DTC - - - - f , - , - ,......
Error Amplifier 1
11N+ ....:...-----1
Pulse-Steering
Flip-Flop
11N-....:2=-------t
r -_ _ _ _ _ _ _ _ _ _ _ _ _
12 Vee
Error AmplHier 2
16
21N+ ....:..::-----1
~-----------14
REF
r-_______~--------------------~7
GND
21N--1,."S'------1
---+
FEEDBACK_3_ _ _ _ _ _ _-' 0.7 mA
NOTE A. The terminal numbers indicated apply only to the D. J. N. and PW packages.
4-20
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL494C, TL4941, TL494M, TL494V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A - JANUARY 1983 - REVISED AUGUST 1995
TL494Y chip information
This chip, when properly assembled, display characteristics similar to the TL494C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=
-=-=
-=
CHIP THICKNESS: 15 MILS TYPICAL
-=-=
-=
-=-=-=
-=
-=-=
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
-=
-=-=-=
-=-=
-=
1+-----------94-----------+1
I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I' I ~ I' I' I' I' I' I' I' I' I' I' I' 1'1' I' I' I' I' I' I' I' I' I' I' I' I' I
l1N+
l1NFEEDBACK
DTC
CT
RT
GND
Cl
(1)
(16)
(2)
(15)
(3)
(14)
(4)
(13)
(5)
TL494Y
(12)
(6)
(11)
(7)
(10)
(8)
(9)
21N+
21NREF
OUTPUTCTRL
VCC
C2
E2
El
-!/} TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-21
/"
TL494C, TL4941, TL494M, TL494Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUSt 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
TL494C
TL4941
TL494M
UNIT
41
41
41
V
VCC+0.3
VCC+0.3
VCC+0.3
V
Collector output voltage, Vo
41
41
41
V
Collector output current, 10
250
250
250
mA
Supply voltage, VCC (see Note 1)
Amplifier Input voltage, VI
Continuous total power dissipation
See Dissipation Rating Table
Ot070
-40 to 85
-55 to 125
°C
-65 to 150
-65 to 150
-65 to 150
°C
Case temperature for 60 seconds, TC: FK package
-
-
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D, N, or PW
package
260
260
-
°C
-
-
300
°C
Operating free-air temperature range, TA
Storage temperature range, Tsta
Lead temperature 1,6 mm (1116 inch) from case for 10 seconds: J package
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVETA
TA " 70°C
POWER RATING
25°C
558mW
444mW
25°C
880mW
715mW
275mW
25°C
880mW
715mW
275mW
595mW
D
900mW
FK
1375mW
J
1375mW
7.6mW/oC
11.0 mW/oC
11.0mW/oC
N
l000mW
9.2mW/"C
41°C
733mW
PW
700mW
5.6mW/"C
25°C
448mW
TA=85°C
POWER RATING
TA= 125°C
POWER RATING
recommended operating conditions
TL494C
MIN
Collector output voltage, Vo
MAX
UNIT
40
7
40
7
40
V
-0.3
VCC-2
-0.3
VCC-2
V
:
AO
40
40
V
200
200
200
mA
0.3
0.3
mA
1
300
1
300
1
300
kHz
0.47
10000
0.47
10000
0.47
10000
nF
1.8
500
1.8
500
1.8
500
k.Q
0
70
-40
85
-55
125
°c
0.3
Oscillator frequency, fosc
Operating free-air temperature, TA
~TEXAS
INSTRUMENTS
4-22
MIN
VCC-2
Current into feedbaCk terminal
liming resistor, RT
TL494M
MAX
7
Collector output current (each transistor)
liming capacitor, CT
MIN
-0.3
Supply voltage, VCC
Amplifier input voltage, VI
TL4941
MAX
POST OFFICE BOX s5s303 • DALlAS, TE~S 75265
TL494C, TL4941, TL494M, TL494Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
Vcc = 15 V,
electrical characteristics over recommended operating free-air temperature range,
f = 10kHz (unless othelWise noted)
reference section
TL494C. TL4941
TEST CONDITIONst
PARAMETER
Output voltage (REF)
10=1 rnA
Input regulation
Vee =7 V to 40 V
TL494M
MIN
TYP*
MAX
MIN
TYP*
MAX
4.75
5
5.25
4.75
5
5.25
2
25
2
25
UNIT
V
mV
Output regulation
10=1 rnA to lOrnA
1
15
1
15
mV
Output volUige change with temperature
aTA = MIN to MAX
2
10
2
30·
mVN
Short~ircuit output currem§
REF.OV
-25
25
mA
* On products compliant to MIL-STD-8B3. Class B. thiS parameter IS not production tested.
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j: All typical values except for parameter changes with temperature are at TA _ 25°C.
§ Duration of the short circuit should not exceed one second.
oscillator section, CT
=0.01 p.F, RT =12 kO (see Figure 1)
PARAMETER
TL494C.TL494I
TEST CONDlTlONSt
MIN
TYP*
Frequency
Standard deviation of frequency.
All values of VCC. CT. RT. and TA constant
Frequency change with voltage
VCC -7 Vto 40 V.
TA-25°C
MAX
TL494M
MIN
TYP*
MAX
UNIT
10
10
kHz
100
100
HzlkHz
1
1
Frequency change with temperature# ATA =MIN to MAX
10
* On products compliant to MIL-STD-883. Class B. thiS parameter IS not production tested.
t For conditions shown as MIN or MAX. use the appropriate value specified under recommended operating conditions.
:j: All typical values except for parameter changes with temperature are at TA _ 25°C.
• Standard deviation Is a measure of the statistical distribution about the mean as derived from the formula:
# Temperature coefficient of timing capacitor and timing resistOr not taken into account.
a =
HzlkHz
10·
HzlkHz
N
2: (Xn -
X)2
n-l
N-1
error amplifier section (see Figure 2)
PARAMETER
TEST CONDITIONS
TL494C, TL4941
TL494M
MIN
TYP*
UNIT
MAX
Input offset voltage
Va (FEEDBACK) = 2.5 V
2
10
mV
Input offset current
Va (FEEDBACK) • 2.5 V
25
250
nA
Input bias current
Va (FEEDBACK) .2.5 V
0.2
1
jIA
-0.3 to
VCC-2
Common-mode input voltage range
VCC - 7 V to 40 V
Open-loop voltage amplification
Unity-gain bandwidth
AVO=3V.
RL - 2 kn,
Va. 0.5 V to 3.5 V.
Common-mode rejection ratio
AVO-40V.
65
80
dB
Output sink current (FEEDBACK)
VID - -15 mV to -5 V.
V (FEEDBACK) - 0.7 V
0.3
0.7
rnA
Output source current (FEEDBACK)
VID = 15 mVto5 V.
V (FEEDBACK) • 3.5 V
-2
Va - 0.5 V to 3.5 V
70
RL-2kn
TA-25°C
V
95
dB
800
kHz
rnA
:j: All typical values except for parameter changes with temperature are at TA - 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-23
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH~MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
Vee = 15 V,
electrical characteristics over recommended operating free-air temperature range,
f = 10kHz, TA = 25°C (unless otherwise noted)
..,
.
reference section
TL494Y
TEST CONDITIONS
PARAMETER
MIN
TYpt
MAX
UNIT
Output voltage (REF)
10=1 rnA
5
V
Input regulation
VCC =7Vto 40V
2
mV
Output regulation
10=1 rnA to lOrnA
I Short-circu~ output current=l:
REF=OV
1
mV
25
rnA
oscillator section, CT = 0.01 !1F, RT = 12 k.Q (see Figure 1)
TL494Y
PARAMETER
TEST CONDITIONS
~
MIN
Frequency
Standard deviation of frequency§
All values of VCC, CT, RT, and TA constant
Frequency change with voltage
Vec = 7Vt040V,
TYpt
MAX
UNIT
10
kHz
100
Hz/kHz
1
HzlkHz
TA = 25°C
error amplifier section (see Figure 2)
TL494Y
PARAMETER
TEST CONDITIONS
MIN
TYpt
MAX
UNIT
Input offset voltage
Vo (FEEDBACK) = 2.5 V
2
Input offset current
Vo (FEEDBACK) = 2.5 V
25
nA
Input bias current
Vo (FEEDBACK) = 2.5 V
0.2
!tA
Open-loop voltage amplification
I1VO': 3 V,
Unity-gain bandwidth
Vo =0.5 Vt03.5 V,
Common-mode rejection ratio
I1VO=40V,
Output sink current (FEEDBACK)
V,D=-15 mVto-5 V,
RL=2kO,
Vo = 0.5 V to 3.5 V
95
dB
RL=2kn .
800
kHz
80
dB
V (FEEDBACK) = 0.7 V
0.7
rnA
TA = 25°C
t All typical values except for parameter changes with temperature are at TA
25°C.
N
L (Xn -
=I: Duration of the short circuit should not exceed one second.
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the fonnula:
a
~TEXAS
INSTRUMENTS
4-24
mV
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
=
n=1
N-1
X)2
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
electrical characteristics over recommended operating free-air temperature range,
f = 10 kHz (unless otherwise noted)
Vee = 15 V,
output section
PARAMETER
TL494C, TL4941
TL494M, TL494Y
TEST CONDITIONS
MIN
TYpt
Collector off-state current
VCE=40V,
VCC = 40 V
Emitter off-state current
VCC = Vc =40 V,
VE=O
VE=O,
Ic=200mA
1.1
1.3
VO(Cl or C2) = 15 V,
IE=-2oomA
1.5
2.5
Collector-emitter saturation voltage
l Common emitter
I Emitter follower
Output control input current
2
UNIT
MAX
100
J.lA
-100
J.lA
3.5
VI=Vref
· . are at TA = 25°C.
t All tYPical values except for temperature coefficient
V
mA
dead-time control section (see Figure 1)
PARAMETER
TEST CONDITIONS
TL494C, TL4941
TL494Y
MIN
Input bias current (DEAD-TIME CTRL)
VI = 0 to 5.25 V
Maximum duty cycle, each output
VI (DEAD-TIME CTRL) = 0,
CT=O.l J.lF, RT=12kn
TYpt
MAX
-2
-10
.
t
MIN
45%
3.3
3
Zero duty cycle
Input threshold voltage (DEAD-TIME CTRL)
TL494M
Maximum duty cycle
UNIT
TYpt
MAX
-2
-10
45%
50%·
3
3.3
V
O'
0
J.LA
On products compliant to MIL-STD-883, Class B, thiS parameter IS not production tested.
All typical values except for temperature coefficient are at TA = 25°C.
PWM comparator section (see Figure 1)
PARAMETER
TL494C, TL4941
TL494M, TL494Y
TEST CONDITIONS
Input threshold voltage (FEEDBACK)
Zero duty cycle
Input sink current (FEEDBACK)
V (FEEDBACK) = 0.7 V
UNIT
MIN
TYpt
MAX
4
4.5
0.3
0.7
V
mA
· . are at TA = 25°C.
t All typical values except for temperature coeffiCient
total device
PARAMETER
TL494C, TL4941
TL494Y
TEST CONDITIONS
MIN
Standby supply current
Lvcc= 15V
RT=Vref,
All other inputs and outputs open VCC = 40 V
Average supply current
VI (DEAD-TIME CTRL) = 2 V,
TYPt
I
See Figure 1
~TEXAS
MIN
UNIT
TYpt
MAX
6
10
6
21
9
15
9
26
7.5
· . are at TA = 25°C.
t All typical values except for temperature coeffiCient
TL494M
MAX
7.5
mA
mA
'
INSTRUMENTS
POST OFACE BOX 655303 • DALLAS, TEXAS 75265
4-25
TL494C,TL4941, TL494M, TL494Y
PULSE-WIDT.H-MODULATION CONTROL CIRCUITS
SLVS074A-JANUARY 1983- REVISED AUGUST 1995
electrical characteristics over recommended operating free-air temperature range, Vee
f = 10 kHz (unless otherwise noted) (continued)
=15 V,
switching characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
TL494C, TL4941
TL494Y
MIN
TYPT
MAX
100
25
100
200
100
200
100
Rise time
Common-emitter configuration, See Figure 3
Fal/time
Rise time
See Figure 4
Emitter-follower configuration,
Fal/time
* On products compliant to MIL-STD-883, Class e, this parameter IS not production tested.
t AI/ typical values except for temperature coefficient are at TA = 25°C.
~TEXAS
4-26
INSTRUMENTS
POST OFF1GE BOX 665303 • DALLAS. TEXAS 75265
40
TL494M
MIN
UNIT
TYPT
MAX
100
25
100
40
200·
100·
200·
100·
ns
ns
ns
ns
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
VCC=15V
J.
I
1500
2W
12
VCC
4
Test {
Inputs
3
8
C1
DTC
FEEDBACK
E1
RT
C2
CT
E2
-=
~
16
1
15
----1!
"N}
11N21N +
Output 1
9
12kO 6
5
\1
II
0.011lF
1
? 1500
~ 2W
11
-b
Output 2
~
Error
Amplifiers
21NOUTPUT
CTRL
REF
--1.L
GND
5OkQ ?
j,?
TEST CIRCUIT
VCC
Voltage
at C1
--------
OV
VCC
Voltage
atC2
- - - - - - OV
Voltage
atCT
DTC
OV
FEEDBACK
VOLTAGE WAVEFORMS
Figure 1. Operational Test Circuit and Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-27
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995 ,
PARAMETER MEASUREMENT INFORMATION
Amplifier Under Test
FEEDBACK
Vret - - - - I
Figure 2. Amplifier Characteristics
15V
~tf
I
I
I
CL= 15 pF
(See Note A)
L _ _ _ .J
TEST CIRCUIT
NOTE A. CL includes probe and jig capacitance.
I
I
I
I
I
I
Output
~tr
I
OUTPUT VOLTAGE WAVEFORM
Figure 3. Common-Emitter Configuration
15V
I
I
L _ _ _ .J
I
68£1
:
~tr
2W
CL = 15 pF
,I
I
I
I
I
~tf
(See Note A)
OUTPUT VOLTAGE WAVEFORM
TEST CIRCUlr
NOTE A. CL includes probe and jig capacitance.
Figure 4. Emitter-Follower Configuration
~TEXAS
4-28
INSTRUMENTS
POST OfFICE BOX 655303 • DALLAS. TEXAS 75265
TL494C, TL4941, TL494M, TL494Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS074A- JANUARY 1983 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATIONt
va
TIMING RESISTANCE
:5:! 100 k
I
Vee = 15 V
TA=25°e
c
o
40k
i
-" -
r---2%
~
10 k ~ E -1%
r;
!
...e
i
0%= ~
4k
CJ'
I
1k
f
e
,,
-,-
"
0.0011lF
....
0.011lF
..... f-
0.11lF
400
...
100
I'is
40
..a
~
~=1IlF
I I 1111
10
1k
I
af t = 1%
;
CJ'
40 k 100 k
4k
10 k
RT - TIming Resistance - Q
400 k
1M
Figure 5
t Frequency variation (41) is the change in oscillator frequency that occurs over the full temperature range.
AMPLIFIER VOLTAGE AMPLIFICATION
VB
FREQUENCY
100
ID
90
"0
I
c
80
1i
70
---
'" "
r\.
0
..
!E
is. 60
"-
E
CC
II)
DI
~
.
~
50
40
!E 30
is.
E
"
'\.
II)
CC
Vee=1 15V
aVO=3V TA=25°e _
........
20
"
'\.
I
CC
10
10
100
1k
10k
f - Frequency - Hz
100k
Figure 6
"
1M
-!I1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-29
4-30
TL496C, TL496Y
9-V POWER-SUPPLY CONTROLLERS
SLllS012B - AUGUST 1978 - REVISED AUGUST 1995
o OR P PACKAGE
• Internal Step-Up Switching Regulator
(TOP VIEW)
• Fixed g-V Output
• Charges Battery Source During
Transformer-Coupled-Input Operation
FEEDBACK[]S
2C INPUT 2
7
1C INPUT 3
6
T INPUT 4
5
• Minimum External Components Required
(1 Inductor, 1 Capacitor, 1 Diode)
• 1- or 2-Cell-lnpLit Operation
OUTPUT
GND
SW
GND
Terminals 5 and 7 are connected together internally.
description
The TL496C power-supply control circuit is designed to provide a 9-V regulated supply from a variety of input
sources. Operable from a 1- or 2-cell battery input, the TL496Cperforms as a switching regulator with the
addition of a single inductor and filter capacitor. When ac coupled with a step-down transformer, the TL496C
operates as a series regulator to maintain the regulated output voltage and, with the addition of a single catch
diode, time shares to recharge the input batteries.
The design of the TL496C allows minimal supply current drain during standby operation (1251!A typical). With
most battery sources, this allows a constant bias to be maintained on the power supply. This makes power
instantly available to the system, thus eliminating power-up sequencing problems.
AVAILABLE OPTIONS
I
PACKAGED DEVICES
TA
SURFACE MOUNT
(D)
DOC to 7DoC
TL496CD
PLASTIC DIP
(P)
I
TL496CP
CHIP
FORM
M
TL496Y
functional block diagram
~~_ _~_ _~_~8 OUTPUT
T INPUT 4
..:..-....1--1
FEEDBACK
2C INPUT ~2--e--.rs;;;;iicl;i;;;:;--,
..._----.....:6:... SW
1C INPUT -3--e--L~~~.....J
5
See Note 1
GND
7
GND
NOTE 1: Terminals 5 and 7, though connected together internally, must both be terminated to ground to ensure proper circuit operation.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4--31
TL496C, TL496Y
9-VOLT POWER-SUPPLY CONTROLLERS
SLVS012B - AUGUST 1978 - REVISED AUGUST 1995
TL496Y chip information
This chip, when properly assembled, displays characteristics similar to the TL496C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax= 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
FEEDBACK
2CINPUT
1CINPUT
TINPUT
(1)
(8)
(2)
(7)
TL496Y
(3)
(6)
(4)
(5)
OUTPUT
GND
SW
GND
·~TEXAS
.
INSTRUMENTS
4-32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL496C,TL496Y
9-VOLT POWER-SUPPLY CONTOLLERS
SLVS012B - AUGUST 1978 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Input voltage, VI: 2C INPUT ................................................................ 3.5 V
1C INPUT ................................................................ 2.5 V
TINPUT ................................................................. 20V
Output voltage, Vo (SW) ................................................................... 12 V
Diode reverse voltage (OUTPUT) ........................................................... 12 V
Switch current (SW) ....................................................................... 1.2 A
Diode current (OUTPUT) .............................. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2 A
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
DERATING
FACTOR
TA
=70°C
POWER RATING
D
725mW
5.8mW/oC
464mW
P
1000mW
8.0mW/oC
640mW
recommended operating conditions
Input voltage, one-celi operation (2C and 1C INPUTS to ground)
Input voltage, two-ceil operation (2C INPUT to ground)
Input voltage, one-celi or two-celi operation (T INPUT to ground)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MIN
1.1
MAX
1.5
UNIT
V
2.3
3
V
VO+2
20
V
TL496C,TL496Y
9';VOLT POWER-SUPPLY CONTROLLERS
SLVS012B - AUGUST 1978 - REVISED Al)GUST199!!
ro.
electrical characteristics over recommended operating conditions, TA
noted)
=25°C (unless· otherwise
.
series regulator section (T INPUT)
PARAMETER
Dropout voltage
TEST CONDITIONS
VI=5V,
10=-50 IlA
VI =20V,
Regulated output voltage
MIN
TYP
MAX
1.5
2
9.5
10.1
11.2
10=-50 rnA
9
10
11
8.5
9
9.7
6.7
8.6
10=-80mA
VI =20V,
FEEDBACK shorted to OUTPUT
10 = -50 IlA .
10=-80 rnA
UNIT
V
V
9.5
Standby current, T INPUT
VI =20V,
OUTPUT = 12V
400
Reverse current through T INPUT
VI =-1.5 V,
1 rnA into OUTPUT
-25
IlA
IlA
output switch
PARAMETER
TEST CONDITIONS
800 rnA into SW,
MIN
2C INPUT = 2.25 V
TYP
MAX
0.35
0.6
diode (SW to OUTPUT)
PARAMETER
VF
IR
I Forward voltage
LReverse current through SW
TEST CONDITIONS
MIN
IF=1.5A
SWatOV,
TYP
MAX
1.6
2.5
V
-20
IlA
1 rnA into OUTPUT
UNIT
control section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
60
UNIT
On·state current (2C INPUT)
FEEDBACK and OUTPUT = 0 V,
2C INPUT=3V
100
rnA
Standby current (FEEDBACK)
FEEDBACK = 8.65 V, 2C INPUT and SW = 3 V
40
Standby current (2C INPUT and SW)
FEEDBACK = 8.65 V, 2C INPUT and SW = 3 V
400
IlA
IlA
Start-up current (current into SW to inHiate cycle)
FEEDBACK, 2C INPUT, SW, and OUTPUT = 2.25 V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
rnA
TL496C,TL496Y
9-VOLT POWER-SUPPLY CONTOLLERS
SLVS012B - AUGUST 1978 - REVISED AUGUST 1995
APPLICATION INFORMATION
L
CIRCUIT COMPONENT INFORMATION
01: 1N4001
CO: 330 IlF to 470 IlF, 10 V, electrolytic
L: 40IlH to 50 IlH, Q ~ 3, R < 0.15 0
Tl: Vsec = 6.B V RMS typ, Rsec = 11 0 typ
~
6
3
T1
2
~~U~II ~
-J- BATT
1CINPUT SW
2CINPUT
OUTPUT
8
OUTPUT
TL496C
4
1
TINPUT FEEDBACK
GND
GND
d~
7
D
;::::::::; C
o
5
GND
Figure 1. One-Cell Operation
L
CIRCUIT COMPONENT INFORMATION
01· lN4001
CO: 3 30 IlF to 470 IlF, 10 V, electrolytic
L: 40 /LH to 50 /LH, Q=3, R <0.150
Tl: Vsec = 6.B V RMS typ, Rsec = 11 0 typ
rYVY"""
T1
,...
~~U~II ~
2
13
1CINPUT
2CINPUT
6
SW
OUTPUT
8 ,...
OUTPUT
TL496C
4
TINPUT FEEDBACK
GND
GND
7
D1.n
f-!o
;;:::::; C
5
o
)
I
BATT
GND
Figure 2. Two-Cell Operation
electrical characteristics for one- and two-cell input operations
PARAMETER
Input current
Output voltage
No load
ONE-CELL OPERATION
(see Figure 1)
TWO-CELL OPERATION
(see Figure 2)
125/LA
125/LA
525 rnA
405 rnA
No ac input
7.2 V
B.6V
With ac input
B.6V
10V
40mA
BOmA
RL= 1200
Output current capability
Efficiency
Battery life (AA NiCad) no load
66%
66%
60 days
166 days
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-35
TL496C,TL496Y
9-VOLT POWER-SUPPLY CONTROLLERS
SLVS012B - AUGUST 1978 - REVISED AUGUST 1995
functional description
The TL496C is designed to operate from either a single-cell or two-cell battery source. To operate the device
from a single cell (1.1 V tp 1.5 V), the source must be connected to both inputs 1C INPUT and 2C INPUT as
shown in Figure 1. For a two-cell operation (2.3 V to 3 V), the input is applied to 2C INPUT only and 1C INPUT
is left open (see Figure 2).
'
battery operatIon-_
The TL496C operates as a switching regulator from a battery input. The cycle is initiated when a low-voltage
condition is sensed by the internal feedback (the thresholds at terminals 1 and 8 are approximately 7.2 and 8.6 V
respectively). An internal latch is set and the outputtransistor is turned on. This causes the current in the external
inductor (L) to increase linearly until it reaches a peak value of approximately 1 A. WhelJ the peak current is
sensed, the internal latch is reset and the output transistor is turned off. The energy developed in the inductor
is then delivered to the output storage capacitor through the blocking diode. The latch remains in the off state
until the feedback signal indicates the output voltage is again deficient.
transformer-coupled operation
The TL496C operates on alternate half cycles of the ac input during transformer-coupled operation to first
sustain the output voltage and second to recharge the batteries. The TL496C performs like a series regulator
to supply charge to the output filter/storage capacitor during the first half cycle. The output voltage of the series
regulator is slightly higher than that created by the switching circuit. This maintains the feedback voltage above
the switching regulator control circuit threshold, effectively inhibiting the switching control circuitry. During the
second half cycle, an external diode (1 N4001) is used to clamp the negative-going end of the transformer
secondary to ground, thus allowing the positive-going end (end connected to V+ side of battery) to pump a
charge into the standby batteries.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL497AC, TL497AI, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVS009C - JUNE
•
•
High Efficiency ••• 60% or Greater
•
•
Input Current Limit Protection
•
•
•
•
995
TL497AC, TL497AI ••• D, N, OR PW PACKAGE
(TOP VIEW)
Output Current ... 500 mA
COMP INPUT I
INHIBIT
FREQ CONTROL
SUBSTRATE
GND
CATHODE
ANODE
TTL-Compatible Inhibit
Adjustable Output Voltage
Input Regulation ..• 0.2% Typ
Output Regulation ••• 0.4% Typ
Soft Start-Up Capability
1
V
14
2
13
3
12
4
11
5
10
6
9
7
8
VCC
CUR LIM SENS
BASE DRIVEt
BASEt
J COL OUT
NC
EMIT OUT
NC - No.intemal connection
BASE (11) and BASE DRIVE (12) are used for device testing only.
They are not normally used in circuit applications of the device.
t
description
The TL497AC and TL497AI incorporate on a single monolithic chip all the active functions required in the
construction of switching voltage regulators. They can also be used as the control element to drive external
components for high-power-output applications. The TL497AC and TL497AI were designed for ease of use in
step-up, step-down, or voltage inversion applications requiring high efficiency.
The TL497AC and TL497AI are fixed-on-time variable-frequency switching-voltage-regulator control circuits.
The switch-on time is programmed by a single external capacitor connected between FREQ CONTROL and
GND. This capacitor, CT, is charged by an internal constant-current generator to a predetermined threshold. The
charging current and the threshold vary proportionally with VCC. Thus, the switch-on time remains constant over
the specified range of. input voltage (4.5 V to 12 V). Typical on times for various values of CT are as follows:
TIMING CAPACITOR, CT (pF)
ON TIME (Ils)
The output voltage is controlled by an external resistor ladder network (R1 and R2 in Figures 1, 2, and 3) that
provides a feedback voltage to the comparator input. This feedback voltage is compared to the reference
voltage of 1.2 V (relative to SUBSTRATE) by the high-gain comparator. When the output voltage decays below
the value required to maintain 1.2 V at the comparator input, the comparator enables the oscillator circuit, which
charges and discharges CT as described above. The internal pass transistor is driven on during the charging
of CT The internal transistor may be used directly for switching currents up to 500 rnA. Its collector and emitter
are uncommitted, and it is current driven to allow operation from the positive supply voltage or ground. An
internal Schottky diode matched to the current characteristics of the internal transistor is also available for
blocking or commutating purposes. The TL497AC and TL497AI also have on-chip current-limit circuitry that
senses the peak currents in the switching regulator and protects the inductor against saturation and the pass
transistor against overstress. The current limit is adjustable and is programmed by a single sense resistor, RCL,
connected between VCC and CUR LIM SENS. The current-limit circuitry is activated when 0.7 V is developed
across RCL. External gating is provided by the INHIBIT input. When the INHIBIT input is high, the output is turned
off.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SURFACE MOUNT
(D)
PLASTIC DIP
(N)
DOC to 7DoC
TL497ACD
TL497ACN
-40°C to 85°C
TL497AID
TL497AIN
PRODUcnoN DATA Infonnation is current as of publication date.
Products conform to speclftcaUons per the terms of Texas Instruments
standard warranty. Production pr0C888lng does not neceuarily Include
testing of all porarMers.
SHRINK
SMALL OUTLINE
(PW)
TL497ACPW
-
-!!1
CHIP
FORM
(Y)
TL497AY
-
Copyright © 1995, Texas Instruments Incorporated
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-37
1;L497AC,TL497AI, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 -REVISED AUGUST 1995
description (continued)
Simplicity of design is a primary feature of the TL497AC and TL497AI. With only six external components (three
resistors, two capacitors, and one inductor), the TL497AC and TL497AI operates in numerous voltage
conversion applications (step-up, step-down, invert) with as much as 85% of the source power delivered to the
load. The TL497AC and TL497AI replace the TL497 in all applications.
The TL497AC is characterized for operation from O°C to 70°C, and the TL497 AI is characterized for operation
from -40"C to 85°C.
functional block diagram
BASEt
BASE DRIVEt
~11~____________________________________~
-;::::;:=:=:::;;______________1
_12____
. CUR LIM SENS -=1.::.3_-1
FREQ CONTROL ..:3=--__________________--1
Oscillator
INHIBIT
COMPINPUT
10 COL OUT
SUBSTRATE
CATHODE
EMIT OUT
--------------~i~.~----------------------------~7
ANODE
t BASE and BASE DRIVE are used for device testing only. They are not normally used in circuit applications of the device.
~TEXAS
INSTRUMENTS
4-38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL497AC, TL497AI, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 - REVISED AUGUST 1995
TL497AV chip information
This chip, when properly assembled, displays characteristics similar to the TL497AC. Thermal compression or
ultrasonic bohding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
-=
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax= 150°C
TOLERANCES ARE ±10%
-=
ALL DIMENSIONS ARE IN MILS
I"
115
.1
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
CUR
LIM
BASE
SENS DRIVEt
FREQ CONTROL (3)
INHIBIT (2)
COM!> INPUT (1)
(10) COL
OUT
TL497AY
(8)
EMIT
OUT
(7)
ANODE
(4)
SUBSTRATE (6)
CATHODE
'----r-:=~"T"l'!:(l~4)~
GND
t
VCC
BASE (11) and BASE DRIVE (12) are used for device testing
only. They are not normally used in circuit applications of the
device.
-!/}TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-39
TL497AC, TL4.97A1, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVS.OO9C - JUNE 1976- REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supplyvoltage,Vcc(seeNote1) .................. ; ......................................... 15V
Output voltage, Vo ...................................................... :................. 35 V
Input voltage, VI(COMP INPUT) .............................................................. 5 V
. Input voltage, VI (INHIBIT) .....•............................................................. 5 V
Diode reverse voltage ................................. ,................................... 35 V
Power switch current ..............................•......•................... ,........... 750 rnA
Diode forward current ............ '............... '.' .•.. ." ... , .... " . . . . . . . . . . . . . . . . . . . . . . . . .. 750 rnA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range; TA: TL497AC .................................... O°C to 70°C
TL497AI ...... ; ............................ -40°C to 85°C
Storage temperature range, Tstg .. : ............................ ; ......... ,... ..... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximumfatings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating condHions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliabilHy.
NOTE 1: All voltage values except diode voltages are with respect to network ground terminal.
.
DISSIPATION RATING TABLE
POWER RATING
DERATING
FACTOA
DERATE
ABOVETA
D
950mW
7.6mW/oe
25°e
608mW
494mW
N
1000mW
9.2mW/oe
41°e
733mW
595mW
PW
700mW
5,6mW/oe
25°e
448mW
PACKAGE
TAS;25°C
TA=70°C
POWER RATING
TA=85°C
POWER RATING
recommended operating conditions
MIN
MAX
Supply voltage, Vee
4.5
12
High-level input VOltage, VIH INHIBIT
2.5
LOW-level input voltage, VIL INHIBIT
Output voltage
Step-down configuration (see Figure 2)
Inverting regulator (see Figure 3)
V
V
0.8
Step-up configuration (see Figure 1)
UNIT
VI+2
30
Vref
VI-1
-Vref
-25
V
V
Power switch current
500
rnA
Diode forward current
500
mA
Operating free-air temperature, TA
I TL497Ae
ITL497AI
~TEXAS
4-40
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0
70
-40
85
°e
TL497AC, TL497AI, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVS009C - JUNE 1976 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, vee = 6 V (unless otherwise
noted)
TEST CONDITIONS
PARAMETER
TL497AC
TAt
MIN
TL497AI
TVP*
MAX
MIN
TVP*
MAX
UNIT
High-level input current, INHIBIT
VI(I)=5V
Fu" range
0.8
1.5
0.8
1.5
rnA
LOW-level input current, INHIBIT
VI(I)=OV
Fu" range
5
10
5
20
llA
Comparator reference voltage
VI = 4.5 V to 6 V
Fu" range
1.2
1.32
1.2
1.26
V
Comparator input bias current
VI=6V
Fu" range
40
100
40
100
llA
Switch on-state voltage
Ilo=100mA
I
10 =500 rnA
0.2
0.13
0.2
VI =4.5V
Switch off-state current
VI = 4.5 V,
VO=30V
Sense voltage, CUR LIM SENS
VI=6V
Diode forward voltage
Diode reverse voltage
1.08
0.13
25°C
1.14
0.85
Fu" range
25°C
10
1
50
10
200
Fu" range
0.45
25°C
1
0.45
0.85
1
0.75
Fu" range
10= 100 rnA
Fu"range
0.9
1
0.9
1.1
10= 500 rnA
Fu" range
1.33
1.55
1.33
1.75
10 = 500 llA
Fu" range
llA
Fu"range
30
11
25°C
Off-state supply current
14
11
15
Fu" range
14
16
9
6
6
10
Fu"range
V
V
V
30
25°C
On-state supply current
llA
0.95
10=10mA
10 = 200
0.75
50
500
V
9
11
rnA
rnA
t Fu" range for the TL497 AC IS O°C to 70°C and full range for the TL497 AIls -40°C to 85°C.
:I: A" typical values are at TA = 25°C.
electrical characteristics over recommended operating conditions, Vee = 6 V, TA = 25°C (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
TL497AV
MIN
TVP
MAX
UNIT
High-level input current, INHIBIT
VI(I)=5V
0.8
rnA
Low-level input current, INHIBIT
VIm = 0 V
5
llA
Comparator reference voltage
VI = 4.5 V to 6 V
1.2
V
Comparator input bias current
VI=6V
40
Switch on-state voltage
VI =4.5V,
10= 100 rnA
0.13
IlA
V
Switch off-state current
VI = 4.5 V,
VO=30V
10
llA
10=10mA
Diode forward voltage
0.75
10=100mA
0.9
10 = 500 rnA
1.33
V
On-state supply current
11
rnA
Off-state supply current
6
rnA
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-41
TL497AC, TL497AI, TL497AV
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
RCL
i
14
L
.~
v-..
13
10
Vo
r
8
R1
TL497A
1
2
4
3
6 7
I
;;: ,;::::Or
I
;;:
5
DESIGN EQUATIONS
r--
R2
r::
[~~]
•
I(PK) = 2 lOmax
•
L(i!H) = -I-ton (f'S)
(PK)
Co
VI
=1.2 k!l
Choose L (SO to 500 ILH). calculate
Ion (25 to 150 IJ.S)
r-
BASIC CONFIGURATION
(Peak Switching Current = l(pK) <.500 mAl
RCL
L
•
R1 = (VO -
•
R
1.2) kg
_ 0.5 V.
CL -
l(pl<)
[
]
; ; l(pl<)
Co
TL497A
F!2
•
EXTENI)ED POWER CONFIGURATION
(using external transistor)
Figure 1. Positive Regulator, Step-Up Configurations
~TEXAS
4-42
POST OFFICE BOX 655303. DAUAS. TEXAS 75265
10 .
Co (!IF) "" ton(f'S)V .
(PK)
npple
=1.2 kO
INSTRUMENTS
+
TL497AC, TL497AI, TL497AV
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
L
RCL
Vo
T
14
13
DESIGN EQUATIONS
8
10
R1
TL497A
1
3
2
:;:::::::
4
5
lCT
T
I
7
6
•
I(PK) = 2 lOmax
•
VI - Vo
L (~) = -1--ton(!J.S)
(PK)
Co
R2=1.2k1l
Choose L (50 to 500 IlH), calculate
Ion (10 to 150!J.S)
I
1
BASIC CONFIGURATION
(Peak Switching Current = l(pl<) < 500 rnA)
•
R1 = (VO - 1.2) kQ
L
Vo •
A¥
14
AI'-
8
2
4
3
:;::r:;
5
6
7
I(PK)
Co (1lF) = ton(!J.S)
[~ I(PK) + 10]
V.
(PK)
npple
R1
TL497A
1
_ 0.5 V
CL -
•
10
13
R
Co
R2=1.2k1l
I
lCT
I'
1
EXTENDED POWER CONFIGURATION
(using external transistor)
Figure 2. Positive Regulator, Step-Down Configurations
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAu.AS. TEXAS 75265
4-43
TL497AC, JL497AI, TL497AV
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
L
RCL
---
~
14 13
I
10
8
R1
~ .. t
•
2
4
3
:;;:
Vo
BASIC CONFIGURATION
(Peak Switching Current = I(PK) < 500 mAl
•
J:.
'v
13
10
8
R1
.. t
:;;: f:;:Co
TL497A
2
3
4
5
R2=1.2kQ
~
I
Vo
:;;::::: CT
-=EXTENDED POWER CONFIGURATION
(using external transistor)
t
R1
R
.¥.
1
IVoI]
v;-
Choose L (50 to 500 I!H), calculate
ton (10to 1501!S)
L
14
+
R2 = 1.2 kQ
5
I
r:er
~
[
I(PK) = 2 lOmax 1
:;;:r: Co
TL497A
1
DESIGN EQUATIONS
-b
Use external catch-diode, e.g., 1N4001, when building an inverting supply with the TL497A.
Figure 3. Inverting Applications
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
(lvoI- 1.2) kQ
=
_ 0.5 V
CL -
I(PK)
TL497AC, TL497AI, TL497AY
SWITCHING VOLTAGE REGULATORS
SLVSOO9C - JUNE 1976 - REVISED AUGUST 1995
APPLICATION INFORMATION
Switching
Circuit
Vo
I
"
/
Control
\
TL497A
5
EXTENDED INPUT CONFIGURATION WITHOUT CURRENT UMIT
Switching
Circuit - -
Vo
l'\0mA
r--+_______v~~~__
......_.,-_...
~-~"~----..\
Control
DESIGN EQUATIONS
_ V 6E (01)
CL - llimit (PK)
•
R
•
Rt + - -
• R2
R1
TL497A
5
CURRENT UMIT FOR EXTENDED INPUT CONFIGURATION
Figure 4. Extended Input Voltage Range (VI> 12 V)
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VI
16 (02)
=
(V reg - 1) 10 kQ
4-46
TL499AC, TL499AY
WIDE-RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1
- REVISED AUGUST 1995
o OR P PACKAGE
(TOP VIEW)
• Internal Series-Pass and Step-Up Switching
Regulator
• Output Adjustable From 2.9 V to 30 V
• 1-V to 10-V Input for Switching Regulator
• 4.5-V to 32-V Input for Series Regulator
• Externally-Controlled Switching Current
• No External Rectifier Required
SERIES I N 1 [ ] 8
REF 2
7
SW REG IN2 3
6
SW CURRENT CTRL 4
5
OUTPUT
GND (PWR)
SW IN
GND
description
The TL499AC is a monolithic integrated circuit designed to provide a wide range of adjustable regulated supply
voltages. The regulated output voltage is adjustable from 2.9 V to 30 V by adjusting two external resistors. When
the TL499AC is ac-coupled to line power through a step-down transformer, it operates as a series de voltage
regulator to maintain the regulated output voltage. With the addition of a battery from 1.1 V to 10 V, an inductor,
a filter capacitor, and two resistors, the TL499AC operates as a step-up switching regulator during an ac-line
failure.
The adjustable regulated output voltage makes the TL499AC useful for a wide range of applications. Providing
backup power during an ae-line failure makes the TL499AC extremely useful in microprocessor memory
applications.
The TL499AC is designed for operation from -20°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
-20°C to 85°C
SURFACE MOUNT
(D)
TL499ACD
PLAsnCDIP
(P)
CHIP
FORM
(V)
TL499ACP
TL499AY
functional block diagram
SWIN
Blocking Diode
r -__~6__
-e____-e~~__e-______~8
SW REG IN2 .,.,3......______________-,
OUTPUT
Start-Up
'-JVV'Ir---l----------7=- GND (PWR)
' -__________....____________1--______......;4:... SW CURRENT
CTRL
Current Sense
1--+-......f---"2
REF
SERIES IN1 . .,;1_______- -...----1
5
GND
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-47
TL499AC, TL499AY
WIDE-RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUST 1995
TL499AY chip information
This chip, when properly assembled, displays characteristics similar to the TL499AC. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a' gold~silicon preform.
BONDING PAD ASSIGNMENTS
-=-=
-=
-=-=
-=-=
-=-=
-=
-=
CHIP THICKNESS:
11 MILS TYPICAL
BONDING PADS:
7X7 MILS MINIMUM
TJmax=150°C
-=
TOLERANCES ARE ±10%.
ALL DIMENSIONS
ARE IN MILS.
-=-=
-=-=
-=
-=-=
-=-=
10lil
85
.1
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
SERIESIN1
REF
SWREGIN2
SW CURRENT CTRL
(1)
(8)
(2)
(7)
TL499AY
(3)
(6)
(4)
(5)
OUTPUT
GND(PWR)
SWIN
GND
~TEXAS
INSTRUMENTS
4-48
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL499AC, TL499AY
WIDE-RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Output voltage, Va (see Note 1) ............................................................ 35 V
Input voltage, series regulator, VI1 .......................................................... 35 V
Input voltage, switching regulator, VI2 ....................................................... 10 V
Blocking diode reverse voltage ............................................................. 35 V
Blocking diode forward current ................................................................ 1 A
Power switch current (SW IN) ................................................................ 1 A
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ............................................ -20°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network ground terminal.
DISSIPATION RATING TABLE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
D
825mW
6.6mW/oC
429mW
P
1oo0mW
8mW/oC
520mW
PACKAGE
TA=85°C
POWER RATING
recommended operating conditions
MIN
NOM
MAX
UNIT
Output voltage, Vo
2.9
30
V
Input voltage, VI1 (SERIES IN1)
4.5
32
V
Input voltage, V,2 (SW REG IN2)
1.1
10
V
Output-to-input differential voltage, switching regulator, Vo - VI2 (see Note 2)
1.2
28.9
V
Continuous output current, 10
100
rnA
Power switch current (at SW IN)
500
rnA
Current-limiting resistor, RCL
150
1000
0
Filter capacnor
100
470
JlF
JlF
50
150
JlH
-20
85
°C
Pass capacitor
0.1
Inductor, L (dcr s 0.1 0)
Operating free-air temperature, TA
NOTE 2: When operating temperature range is TA S 70°C, minimum Vo - VI2 is '" 1.2 V. When operating temperature range is TA S 85°C,
minimum Vo - VI2 is '" 1.9 V.
'!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-49
TL499AC, TL499AY
WIDE-RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TL499AC
TEST CONDmONS
MIN
Voltage deviation (see Note 3)
20
Switching regulator
Dropout voltage
Series regulator
V
1.9
V
1.8
V
10=SOmA
VO=3V.
Reference voltage change with temperature
TA = -20°C to 85°C
10=lmA
1.2
10=1 rnA to 50 rnA
VI2 = 1.1 V.
TA = 25°C
VO= 12V.
RCL= lSOn,
VI2 = 1.5 V.
TA=25°C
VO=15V.
RCL= 150n,
VI2 = 6 V.
TA = 25°C
VO=30V.
RCL = 150 n,
Switching regulator
VI2 = 3 V.
VO=9V.
TA = 25°C
Series regulator
VII =15V.
VO=9V.
Re2 =4.7 kO
1.26
1.32
5
10
mVN
10
30
mVN
V
10
15
rnA
65
Series regulator
Standby current
mVN
TA = -20°C to 85°C
VI2=5V.
Switching regulator
30
UNIT
1.2
VII = 15V.
Output regulation (of reference voltage)
MAX
TA = -20°C to 70°C
Reference voltage (internal)
Output current (see Figure 1)
TYP
100
15
80
IlA
0.8
1.2
rnA
NOTe 3: Voltage deviation is the output voltage differences that occurs in a change from series regulation to switching regulation.
voltage deviation = Vo (series reg) - (switching reg)
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
TL499AY
TEST CONDITIONS
PARAMETER
MIN
Voltage deviation (see Note 3)
Dropout voltage
Reference voltage (internal)
VII =15V.
10=50mA
VI2=5V.
VO=3V.
10= 1 rnA
1.2
Reference voltage change with temperature
Output regulation (of reference voltage)
10= 1 rnA to SO rnA
VI2 = 1.1 V.
Output current (see Figure 1)
MAX
20
30
mVN
1.2
V
1.9
V
1.8
V
Switching regulator
Series regulator .
Switching regulator
VO= 12V.
RCL=1500
1.26
1.32
5
10
mVN
10
30
mVN
VI2 = 1.5 V.
VO= 15V.
RCL=1500
15
VI2=6V.
VO=3OV.
RCL=1500
65
Switching regulator
VI2=3V.
VO=9V
Series regulator
VII = 15 V.
VO=9V.
rnA
100
Re2 =4.7 kO
15
80
IlA
0.8
1.2
rnA
NOTe 3: Voltage deviation is the output voltage differences that occurs in a change from series regulation to switching regulation.
voltage deviation = Vo (series reg) - (switching reg)
~TEXAS
INSTRUMENTS
4-50
V
10
Series regulator
Standby current
UNIT
TYP
POST OFFICE BOX 655303 • OALlAS. TEXAS 75265
TL499AC, TL499AY
WIDE·RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUST 1995
APPLICATION INFORMATION
~
TL499AC
SERIESIN1
1
1
SERIESIN1
SW REG IN2
3
3
4
OUTPUT
8
8
GND(PWR) 2-
~ REF
SW REG IN2
SWCURRENT
CTRL
SWIN
GND
6
~
Cp ...., ' "
t
I
RCL = 500 0
OUTPUT
+
-..
RE1
Ie
RE2=4.7kQ
-
-'-
Figure 1. TL499AC Basic Configuration
Table 1. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL = 150 Q
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2) (V)
1.1
1.2
1.3
1.5
1.7
2
2.5
3
5
6
9
OUTPUT CURRENT (mA)
30
25
50
20
15
65
90
80
100
20
25
30
80
100
100
15
20
30
45
55
100
100
100
100
12
10
15
20
25
30
40
55
70
100
100
10
15
20
25
30
35
45
65
80
100
100
100
100
9
20
25
25
35
40
50
70
90
6
30
35
40
45
55
75
95
100
5
35
40
45
55
70
85
100
100
Circuit of Figure 1 except:
4.5
35
45
50
60
75
95
100
100t
RCL= 1500
3
55
65t
75t
95t
100t
CF=330~F
CE'=0.1 ~F
t The difference between the output and input voltage for these combinations is greater than the minimum output-to-input differential voltage
specification at 70°C (1.2 V). but less than the minimum at 85°C (1.9 V).
2.9
60t
70t
75t
100t
100t
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • [)ALLAS, TEXAS 75265
4-51
TL499AC, TL499AV
WIDE-RANGE POWERSUPPLV CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUSr 1995
APPLICATION INFORMATION
Table 2. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL 200 n
=
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2) (V)
1.1
'1.2
1.3
1.5
1.7
2
2.5
3
5
30
25
so
9
so
100
70
100
100
15
25
90
15
25
35
30
45
70
10
90
100
100
15
20
25
35
45
60
100
100
100
40
55
70
100
100
45
60
so
100
100
20
15
10
10
10
15
20
20
25
9
20
20
25
30
30
35
12
6
OUTPUT CURRENT (mA)
6
25
30
35
45
50
65
90
5
30
40
55
60
75
100
100
4.5
35
35
40
45
55
65
85
100
lOOt
3
50
55t
65t
sot
90t
2.9
50t
60t
65t
85t
lOOt
Circuit of Figure 1 except:
RCL=200n
CF = 330 IlF
Cp =0.1 IlF
..
t The difference between the output and Input voltage for these combinations IS greater than the minimum output-to-Input differential voltage
specification ilt 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
.
Table 3. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL 300 n
=
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2) (V)
1.1
1.2
1.3
1.5
1.7
2
2.5
3
5
9
40
70
40
55
100
30
25
20
15
10
15
20
55
70
100
10
10
20
30
35
75
95
100
100
12
10
10
10
15
20
25
3s
45
95
100
10
15
15
15
20
25
30
45
55
100
100
60
90
100
100
9
15
ls
20
25
30
35
50
6
25
25
30
35
45
55
70
5
30
30
35
45
50
65
85
100
Circuit of Figure 1 except:
4.5
30
35
40
45
55
70
95
lOOt
RCL = 300 n
3
45
sot
55t
70t
90t
2.9
45t
sot
60t
75t
95t
t The difference between the output and Input voltage for these combinations
specification at 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
CF= 33O IlF
IS
..
Cp=O.l IlF
greater than the minimum output-te-Input differential voltage
~TEXAS
4-52
6
OUTPUT CURRENT (mA)
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
TL499AC, TL499AY
WIDE-RANGE POWER SUPPLY CONTROLLERS
SLVS029B - JANUARY 1984 - REVISED AUGUST 1995
APPLICATION INFORMATION
Table 4. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL = 510 Q
OUTPUT
VOLTAGE
(V)
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2) (V)
1.1
1.2
1.3
1.5
1.7
2
2.5
3
5
6
9
30
50
25
40
75
OUTPUT CURRENT (mA)
30
25
20
15
12
10
10
40
55
90
15
20
55
70
100
100
10
15
25
35
65
80
20
25
30
40
70
85
75
100
9
10
10
10
15
20
25
35
45
6
15
20
20
25
30
35
50
60
5
20
20
25
30
35
45
55
70
Circuit of Figure 1 except:
4.5
20
25
30
35
40
50
65
90t
RCL=510n
3
35
35t
40t
50t
75t
2.9
35t
sst
40t
55t
80t
CF=330J.1F
Cp=O.l J.1F
..
t The difference between the output and Input voltage for these combinations is greater than the minimum output-to'lnput differential voltage
specification at 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
Table 5. Maximum Output Current vs Input and Output Voltages
for Step-Up Switching Regulator With RCL = 1 k.Q
OUTPUT
VOLTAGE
SWITCHING REGULATOR INPUT VOLTAGE (SW REG IN2) (V)
1.1
1.2
1.3
1.5
(V)
1.7
2
2.5
3
5
6
9
OUTPUT CURRENT (mA)
30
35
25
35
20
35
60
45
65
85
15
9
6
10
10
30
20
40
45
15
25
40
55
45
60
12
10
10
10
10
15
25
30
10
15
20
20
30
35
5
10
10
15
20
20
25
35
40
4.5
15
15
15
20
25
30
40
45t
3
20
25t
25t
30t
35t
2.9
20t
25t
25t
30t
45t
50
Circuit of Figure 1 except:
RCL = 1 kf.l
CF = 330 J.1F
..
Cp=O.1 J.1F
t The difference between the output and Input voltage for these combinations IS greater than the minimum output-to· Input differential voltage
specification at 70°C (1.2 V), but less than the minimum at 85°C (1.9 V).
-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4--53
4-54
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
• Complete PWM Power Control Circuitry
• Uncommitted Outputs for 200-mA Sink or
Source Current
• Output Control Selects Single-Ended or
Push-Pull Operation
• Internal Circuitry Prohibits Double Pulse at
Either Output
• Variable Dead Time Provides Control Over
Total Range
• Internal Regulator Provides a Stable 5-V
Reference Supply Trimmed to 1%
• Circuit Architecture Allows Easy
Synchronization
• Undervoltage Lockout for Low Vee
Conditions
o OR N PACKAGE
(TOP VIEW)
l1N+
21N+
l1N-
21N-
FEEDBACK
REF
OUTPUTCTRL
VCC
C2
RT
GND
E2
Cl
El
FUNCTION TABLE
INPUT
OUTPUT
CTRL
OUTPUT FUNCTION
VI=O
VI=Vref
Single-ended or parallel output
Normal push-pull operation
description
The TL594 incorporates on a single monolithic
chip all the functions required in the construction
of a pulse-width-modulation control circuit. Designed primarily for power supply control, these devices offer the
systems engineer the flexibility to tailor the power supply control circuitry to a specific application.
The TL594 contains two error amplifiers, an on-chip adjustable oscillator, a dead-time control (DTC) comparator,
a pulse-steering control flip-flop, a 5-V regulator with a precision of 1%, an undervoltage lockout control circuit,
and output control circuitry.
The error amplifiers exhibit a common-mode voltage range from -0.3 V to Vee -2 V. The DTC comparator has
a fixed offset that provides approximately 5% dead time. The on-chip oscillator may be bypassed by terminating
RT to the reference output and providing a sawtooth input to CT, or it may be used to drive the common circuitry
in synchronous multiple-rail power supplies ..
The uncommitted output transistors provide either common-emitter or emitter-follower output capability. Each
device provides for push-pull or single-ended output operation with selection by means of the output-control
function. The architecture of these devices prohibits the possibility of either output being pulsed twice during
push-pull operation. The undervoltage lockout control circuit locks the outputs off until the internal circuitry is
operational.
The TL594C is characterized for operation from O°C to 70°C. The TL5941 is characterized for operation from
-40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINEt
(D)
O°C to 70°C
TL594CD
TL594CN
-40°C to 85°C
TL5941D
TL5941N
t The D package
TL594CDR).
IS
PRODUCTION DATA Information 18 current as ot publication date.
Products conform to specifications per the tenns of Texas Instruments
standard warranty. Production processing does not necessarily InclUde
testing of aU parameter•.
PLASTIC DIP
(N)
CHIP FORM
(Y)
TL594Y
available taped and reeled. Add "R" suffiX to device type (e.g.,
,
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4--55
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION'CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
functional block diagram
OUTPUTCTRL
(see Function Table)
13
RT
~6----jr:::::=::J
CT·~5_t--L_ _.J
Error Amplifier 1
Pulse-Steering
Flip-Flop
12
Error Amplifier 2
VCC
Undervoltage
Lockout
Control
IN+
IN-
14
' - -_ _ _ _ _....._ _ _-...0.:
7
FEEDBACK ..;:3=--_ _ _ _-41----{
----+
O.7mA
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
REF
GND
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
TL594Y chip information
This chip, when properly assembled, displays characteristics similar to the TL594C (see electrical tables).
Thermal compression or ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=-=
-=
-=-=
-=-=
-=-=
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
TJmax
-=-=
-=-=
-=-=
-=-=
-=-=
-=-=
-=-=
=150°C
TOLERANCES
ARE ±10%.
ALL DIMENSIONS
ARE IN MILS.
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
11N+
11NFEEDBACK
DTC
CT
RT
GND
C1
(1)
(16)
(2)
(15)
(3)
(14)
(4)
(13)
21N+
21N-
(5)
TL594Y
(12)
(6)
(11)
(7)
(10)
(8)
(9)
REF
OUTPUTCTRL
VCC
C2
E2
E1
~
~TEXAS
'
INSTRUMENTS
POST OFF'CE BOX 655303 • DALLAS. TEXAS 75265
4-57
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988'- REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
TL594C
Tl5941
UNIT
41
41
V
VCC+0.3
VCC+0.3
V
Collector output voltage
41
41
V
Collector output current
250
250
rnA
Supply voltage, VCC (see Note 1)
Amplifier input voltage
Continuous total dissipation
See Dissipation Rating Table
Operating free-airtemperature range, TA
Storage temperature range, Tsta
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Ot070
-401085
-65 to 150
-65 to 150
°C
260
260
°C
°c
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device, These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network gro),Jnd tennina!.
DISSIPATION RATING TABLE
TA,;;25°C
POWER RATING
DERATING
FACTOR
D
950mW
7,6mW/oC
608mW
494mW
N
loo0mW
9.2 mWfOC
733mW
595mW
PACKAGE
DERATE
ABOVETA
TA=70°C
POWER RATING
TA=85°C
POWER RATING
recommended operating conditit;ms
TL5941
TL594C
MIN
Supply voltage, Vce
Amplifier input voltage, VI
40
7
40
V
-0.3
VCC-2
V
40
V
200
200
rnA
0.3
rnA
0.47
10000
0.47
10000
nF
1,8
500
1.8
500
kQ
1
300
1
300
kHz
0
70
-40
85
°C
Operating free-air temperature, TA
~TEXAS
INSTRUMENTS
4--58
40
0.3
.,
UNIT
VCC-2
Current into feedback terminal
Timing capacitor, CT
MAX
7
Collector output current (each transistor)
Oscillator frequency, fosc
MIN
-0.3
Collector output voltage, Vo
Timing resistor, RT
MAX
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL594C, TL5941, TL594V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, VCC = 15 V, (unless otherwise
.
noted)
reference section
PARAMETER
TL594C, TL5941
TEST CONDITIONSt
MIN
TYP;
MAX
4.95
5
5.05
UNIT
Output voltage (REF)
10=1 rnA,
TA = 25°C
Input regulation
VCC = 7Vto 40 V,
TA=25°C
2
25
TA = 25°C
14
35
mV
2
10
mVN
35
50
rnA
Output regulation
10 = 1 to 10 rnA,
Output voltage change with temperature
.:\TA = MIN to MAX
Short-circuit output currents
Vref=O
10
V
mV
*
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
All typical values except for parameter changes with temperature are at TA = 25°C.
§ Duration of the short circuit should not exceed one second.
amplifier section (see Figure 1)
TL594C, TL5941
TEST CONDITIONS
PARAMETER
TYpt
MIN
UNIT
MAX
mV
Input offset voltage, error amplifier
FEEDBACK = 2.5 V
2
10
Input offset current
FEEDBACK = 2.5 V
25
250
nA
Input bias current
FEEDBACK = 2.5 V
0.2
1
IlA
Common-mode input voltage range,
error amplifier
VCC= 7 Vt040V
0.3
to
VCC-2
Open-loop voltage amplification, error
amplifier
.:\VO=3V,
RL = 2 kil,
Unity-gain bandwidth
Vo = 0.5 V to 3.5 V,
RL=2k!l
Common-mode rejection ratio, error
amplifier
VCC=40V,
TA = 25°C
Output sink current, FEEDBACK
VID = -15 mV to -5 V,
Output source current, FEEDBACK
VID=15mVt05V,
V
70
Vo =0.5 Vt03.5 V
95
dB
800
kHz
65
80
dB
FEEDBACK = 0.5 V
0.3
0.7
rnA
FEEDBACK = 3.5 V
-2
rnA
t All typical values except for parameter changes with temperature are at TA = 25°C.
oscillator section, CT = 0.01 IlF, RT = 12 k.Q (see Figure 2)
PARAMETER
TL594C, TL5941
TEST CONDITIONst
MIN
TYP=F
10
kHz
100
Hz/kHz
Frequency
Standard deviation of frequency9
All values of VCC, CT, RT, and TA constant
Frequency change with voltage
VCC =7Vt040V,
Frequency change with temperature'l
':\TA = MIN to MAX
*
..
HzlkHz
1
TA=25°C
50
..
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditIOns .
All typical values except for parameter changes with temperature are at TA =' 25°C.
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
N
'1/ Temperature coefficient of timing capacitor and timing resistor not taken into account.
I
(J
=
,
UNIT
MAX
Hz/kHz
(Xn - X)2
n=l
N-1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-59
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1.995
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
=15 V,
dead-time control section (see Figure 2)
PARAMETER
TEST CONDITIONS
Input bias current
VI = 0 to 5.25 V
Maximum duty cycle, each output
DTC=OV
TL594C, TL5941
MIN
TYPT
MAX
-2
-10
Maximum duty cycle
3
3.3
l1A
0.45
Zero duty cycle
Input threshold voltage
UNIT
0
V
t All typical values except for parameter changes with temperature are at TA = 25°C.
output section
PARAMETER
TEST CONDITIONS
VC=40V, VE=OV,
TL594C, TL5941
MIN
MAX
2
100
4
200
l1A
-100
l1A
VCC=40V
DTC and OUTPUT CTRL = 0 V,
VC=15V,
VE=OV,
VCC= 1 t03V
Collector off-state current
,
Emitter off-state current
Collector-emitter saturation voltage
VCC =VC =40V,
VE=O'
LCommon emitter
VE=O,
IC = 200 rnA
1.1
1.3
I Emitter follower
VC=15V,
IE =-200 rnA
1.5
2.5
Output control input current
UNIT
TYPT
3.5
VI = Vref
V
rnA
t All typical values except for parameter changes with temperature are at TA = 25°C.
pwm comparator section (see Figure 2)
PARAMETER
t
TEST CONDITIONS
Input threshold voltage, FEEDBACK
Zero duty cycle
Input sink current, FEEDBACK
FEEDI?ACK = 0.5 V
TL594C, TL5941
TYpt
MAX
MIN
4
0.3
4.5
0.7
UNIT
V
rnA
All typical values except for parameter changes with temperature are at TA = 25°C.
undervoltage lockout section (see Figure 2) .
PARAMETER
TEST CONDITIONST.
TL594C, TL5941
MIN
MAX
3.5
6
6.9
TA = 25°C
Threshold voltage
l1TA = MIN to MAX
Hysteresis;
UNIT
V
mV
100
t
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: Hysteresis is the difference between the positive-going input threshold voltage and the negative-going input threshold voltage.
total device (see Figure 2)
PARAMETER
TEST CONDITIONS
Standby supply current
RTat Vref,
All other inputs and outputs open
Average supply current
DTC=2V,
TYPT
MAX
IVCC=15V
9
15
IVCC=40V
See Figure 2
11
18
t All typical values except for parameter changes with temperature are at TA = 25°C.
~TEXAS
4-60
TL594C, TL5941
INSTRUMENTS
POin OFFICE BOX 655303 • DALLAS, TEXAS 7526,
MIN
12.4
UNIT
rnA
rnA
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS0528 - APRIL 1988 - REVISED AUGUST 1995
electrical characteristics over recommended operating free-air temperature range, Vee = 15 V,
(unless otherwise noted) (continued)
switching characteristics, TA = 25°C
PARAMETER
Output voltage rise time
Output voltage fall time
Output voltage rise time
Output voltage fall time
t
TL594C, TL5941
TEST CONDITIONS
Common-emitter configuration,
See Figure 3
Emitter-follower configuration,
See Figure 4
MIN
UNIT
TYpt
MAX
100
200
ns
30
100
ns
200
400
ns
45
100
ns
All typical values except for parameter changes with temperature are at TA = 25°C.
electrical characteristics over recommended operating conditions, Vee = 15 V, TA = 25°C (unless
otherwise noted)
.
reference section
PARAMETER
t
Output voltage (REF)
Input regulation
TL594Y
TEST CONDITIONS
MIN
10=1 mA,
5
V
VCC = 7 Vl040 V,
2
mV
Output regulation
10=1 t010mA,
14
mV
Short-circuit output currentt
Vref= 0
35
mA
Duration of the short CIrcUIt should not exceed one second.
oscillator section,
er =0.01
I1F,
Rr =12 kn (see Figure 2)
PARAMETER
TL594Y
TEST CONDITIONS
MIN
TYP
Frequency
t
UNIT
MAX
TYP
Standard deviation of frequencyt
All values of VCC, CT, RT, and TA constant
Frequency change with voltage
VCC = 7Vt040 V,
Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
a
..
kHz
100
HzlkHz
1
Hz/kHz
N
I
=
(Xn - X)2
n=1
N-1
amplifier section (see Figure 1)
PARAMETER
TL594Y
TEST CONDITIONS
UNIT
MAX
10
MIN
TYP
MAX
UNIT
Input offset voltage, error amplifier
FEEDBACK = 2.5 V
2
Input offset current
FEEDBACK = 2.5 V
25
nA
,Input bias current
FEEDBACK = 2.5 V
0.2
j.tA
Open-loop voltage amplification, error
amplifier
1WO=3V,
RL=2 kQ,
95
dB
800
kHz
Vo = 0.5 V to 3.5 V
mV
Unity-gain bandwidth
Vo = 0.5 V to 3.5 V,
RL=2 kQ
Common-mode rejection ratio, error
amplifier
VCC=40V,
TA=25°C
80
dB
Output sink current, FEEDBACK
VID = -15 mV to -5 V,
FEEDBACK = 0.5 V
0.7
mA
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
4-61
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
electrical characteristics over recommended operating free-air temperature range, Vee = 15 V,
TA
=25°C (unless otherwise noted)
dead-time control section (see Figure 2)
TEST CONDITIONS -
PARAMETER
TL594Y
MIN
TYP
MAX
UNIT
Input bias current
VI = 0 to 5.25 V
-2
tJA
Input threshold voltage
Zero duty cycle
3
V
output section
PARAMETER
TEST CONDmONS
VC=40V, VE=OV,
TL594Y
MIN
Emitter off-state current
Collector-emitter saturation voltage
MAX
UNIT
2
VCC=40V
DTC and OUTPUT CTRL = 0 V,
VC= 15V,
VE=OV,
VCC= 1 t03V
Collector off-state current
TYPT
tJA
4
tJA
VCC =VC =40V,
VE=O
I Common emitter
VE=O,
IC=200 mA
1.1
I Emitter follower
VC=15V,
IE=-200mA
1.5
V
pwm comparator section (see Figure 2)
PARAMETER
TEST CONDITIONS
Input threshold voltage, FEEDBACK
Zero duty cycle
Input sink current, FEEDBACK
FEEDBACK = 0.5 V
TL594Y
MIN
TYP
MAX
4
UNIT
V
0.7
mA
total device (see Figure 2)
PARAMETER
TEST CONDITIONS
Standby supply current
All other inputs and outputs open
Average supply current
DTC=2V,
TL594Y
MIN
RTat Vref,
See Figure 2
TYP
MAX
UNIT
9
rnA
12.4
mA
switching characteristics, TA = 25°C
PARAMETER
Output voltage rise time
Output voltage fall time
Output voltage rise time
Output voltage fall time
TEST CONDITION~
Common-emitter configuration,
Emitter-follower configuration,
See Figure 3
See Figure 4
~TEXAS
INSTRUMENTS
4-62
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL594Y
MIN
TYP
MAX
UNIT
100
ns
30
ns
200
ns
45
ns
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
Amplifier Under Test
>---e-----
FEEDBACK
Vref - - - - I
Figure 1. Amplifier Characteristics Test Circuit
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-63
TL594C, TL5941, TL594V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
VCC=15V
J.
112
4
Test {
Inputs
3
12 kO
~~
-=-
l
-
DTC
C1
FEEDBACK
E1
TL594
6
5
0.011!F
1
2
LJ!
15
RT
C2
CT
E2
IN.}
ININ+
150
1 50
2W
2W
Output 1
n
VCC
8
n
9
-b
11
n
Output 2
Error
Amplifiers
IN-
13
, . - OUTPUT
REF
CTRL
r-1L
GND
l7
5 OkO
TEST CIRCUIT
~CC
Voltage
atC1
--------
VCC
Voltage
atC2
-----Voltage
atCT
DTClnput
OV
Feedback
Input
I
I
I+-
0.7 V
Duty Cycle
0%
VOLTAGE WAVEFORMS
Figure 2. Operational Test Circuit and Waveforms
~TEXAS
INSTRUMENTS
4--64
OV
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0% ......
OV
TL594C, TL5941, TL594Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B - APRIL 1988 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
15V
~tf
680
I
2W
Output
....--I----t.....-
CL=15pF
I4--*--
I
I
I
I
I
I
I
I
I
(Includes probe and
jig capacitance)
Lr--_.J
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
Figure 3. Common-Emitter Configuration
15V
----1----___-
L _ _ _ .J
Output
......-
680
2W
CL = 15 pF
I
I
I . II
~tr
I
I
I
I
I
~tf
(includes probe and
jig capacitance)
TEST CIRCUIT
OUTPUT VOLTAGE WAVEFORM
Figure 4. Emitter-Follower Configuration
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tr
TL594C, TL5941, TL594V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS052B -APRIL 1988 - REVISED AUGUST 1995
TYPICAL CHARACTeRISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATIONt
vs
TIMING RESISTANCE
100 k
VCC'=15V
TA = 25°C
40k
1-N
:I:
%
10 k I=;=l =;
,-
1%
I
[j'
c
4k
~
1k
j
400
u
y.,- -~
.01 F
til
::I
.--
0.1 IlF
II.
~
1 IlFI
~-
aft =1%
100
~
=(
/
~,=1 J.l
40
10
1k
40 k 100 k
4k
10 k
.RT -liming Resistance - g
400 k
1M
Figure 5
AMPLIFIER VOLTAGE AMPLIFICATION
vs
FREQUENCY
100
90
80
---
"
'\.
m
'I:J
I
70
t
60
c
!E
i5.
50
cc
&
40
E
:!
:i
vcc=115V
aVO=3V TA = 25°C
r-....
'\
\.
'\
30
\.
20
\.
I\.
10
.~
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
Figure 6
t
Frequency variation (al) is the change in oscillator frequency that occurs over the full temperature range.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
TL598C, TL598Q,TL598M, TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED
D, J, OR N PACKAGE
(TOP VIEW)
• Complete PWM Power Control Function
• Totem-Pole Outputs for 200-mA Sink or
Source Current
ERROR
AMP 1
• Output Control Selects Parallel or
Push-Pull Operation
21N+ }ERROR
21NAMP 2
1
{1IN+
11N-
REF
FEEDBACK
• Internal Circuitry Prohibits Double Pulse at
Either Output
DTC
• Variable Dead-Time Provides Control Over
Total Range
OUTPUTCTRL
CT
VCC
RT
Vc
POWERGND
SIGNALGND
• Internal Regulator Provides a Stable 5-V
Reference Supply, Trimmed to 1"10
Tolerance
oun
OUT2
FKPACKAGE
• On-Board Output Current-Limiting
Protection
(TOP VIEW)
a:
a: a.
a::;
0-
• Undervoltage Lockout for Low Vee
Conditions
W«
a:
0 N
a: a.
a::;
W«
V~
;::~~~~
• Separate Power and Signal Grounds
• TL598Q Has Extended Temperature
Range .•. -40°C to 125°C
4
1 2019
18
5
17
3
description
The TL598 incorporates all the functions required
in the construction of pulse-width-modulated
(PWM) controlled systems on a single monolithic
chip. Designed primarily for power supply control,
the TL598 provides the systems engineer with the
flexibility to tailor the power supply control circuits
to a specific application.
The TL598 contains two error amplifiers, an
internal oscillator (externally adjustable), a
dead-time control (DTC) comparator, a pulsesteering flip-flop, a 5-V precision reference,
undervoltage lockout control, and output control
circuits. Two totem-pole outputs provide exceptional rise and fall time performance for power FET
control. The outputs share a common source
supply and common power ground terminals,
which allow system designers to eliminate errors
caused by high current-induced voltage drops and
common-mode noise.
2
REF
OUTPUTCTRL
6
16
NC
7
15
VCC
8
14
9 10 11 12 13
Vc
()~
i= z::>
z ::>
z
C)
0
C)
..J
«
z
0
0
0
a:
w
~a.
C)
1i)
NG-No intemal connection
FUNCTION TABLE
INPUT
OUTPUT
CTRL
OUTPUT FUNCTION
VI=GND
VI = REF
Single-ended or parallel output
Nonnal push-pull operation
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
O°C to 70°C
TL598CD
-40°C to 125°C
TL598QD
-55°C to 125°C
-
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
TL598MFK
PLASTIC
DIP
(N)
-
TL598CN
-
TL598QN
TL598MJ
CHIP FORM
M
TL598Y
-
Chip forms are tested at 25°C.
_Ing_
~':':I:==.lsper~':::~':
_
WllTOnly. Prvducllon
not n.......lly lncIucIa
taatlngolallparametors.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
4--67
TL598C,TL598Q, TL598M, TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
The error amplifier has a common-mode voltage range from 0 V to Vcc -2 V. The DTC comparator has a fixed
offset that prevents overlap of the outputs during push-pull operation. A synchronous multiple supply operation
may be achieved by connecting RT to the reference output and providing a sawtooth input to CT.
The TL598 device provides an output control function to select either. push-pull or parallel operation. Circuit
architecture prevents either output from being pulsed twice during push-pull operation. The output frequency
for push-pull applications is one-half the oscillator frequency (fa = 2
fa
=
R"} CT) . For single-ended applications:
1
RT CT
The TL598C is characterized for operation from O°C to 70°C. T~e TL598Q is characterized for operation from
-40°C to 125°C. The TL598M is characterized for operation from -55°C to 1 2 5 ° C . '
functional block diagram
OUTPUTCTRL
(see Function Table)
13
RT
j!6!...------r:==J
11 Vc
CT -=5'----t--L_ _..J
8 0UT1
~~----iI>C1
11N+
11N-
2
9
21N+
16
21N-
15
FEEDBACK
Pulse-Steering
Flip-Flop
OUT2
10 POWER
12 GND
r-----------+--------~VCC
3
Undervoltage
Lockout Control
~
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _~14REF
)-_--........-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-'-7 SIGNAL
GND
---.
0.7mA
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598C, TL598Q,TL598M, TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
TL598Y chip information
This chip, when properly assembled, displays characteristics similar to the TL598C. Thermal compression or
ultrasonic bonding can be used on the doped aluminum bonding pads. The chip can be mounted with conductive
epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=
-=
-=-=
-=-=
-=-=
-=-=
-=-=
-=-=
-=-=
I"
.1
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
11N+
11NFEEDBACK
DTC
CT
RT
(1)
(16)
(2)
(15)
(3)
(14)
(4)
(5)
(12)
(6)
(11)
(7)
(10)
SIGNALGND
OUT1
(13)
TL598Y
(8)
(9)
21N+
CHIP THICKNESS:
15 MILS TYPICAL
21NREF
BONDING PADS:
4 x 4 MILS MINIMUM
=150°C
OUTPUTCTRL
TJmax
VCC
TOLERANCES
ARE ±100/0.
Vc
POWERGND
ALL DIMENSIONS
ARE IN MILS.
OUT2
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-69
TL598C, TL598Q,' TL598M, TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Supply voltage, VCC (see Note 1) .............................................. ,............ 41 V
Amplifier input voltage, VI ............................................................ Vcc+ 0.3 V
Collector voltage .................................................................. ; ...... ,. 41 V
Output current (each output), sink or source, 10 ............................................. 250 rnA
Continuous total power dissipation .................. \ ... , . . . . . . . . . . . . .. See Dissipation Rating Table
Operating virtual junction temperature range, T J: TL598C .............................. O°C to 150°C
TL598Q ....... ;................... -40°C to 150°C
TL598M .............. ,............ -55°C to 150°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 60 seconds, T C: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or N packages ............... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 6.0 seconds: J packag~ ..................... 300°C
t
Stresses beyond· those listed under ;absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Allvollage values, except differential voltages; are with respect to the signal ground terminal.
DISSIPATION RATING TABLE
0
950mW
DERATING FACTOR
ABOVE TA == 25°C
7.SmW/oC
FK
1375mW
11 mW/oC
J
1375mW
11 mW/oC
800mW
275mW
N
1150mW
9.2mWrC
736mW
230mW
PACKAGE
' TA:<;;25°C
POWER RATING
TA= 125°C
POWER RATING
TA=70°C
POWER RATING
S08mW
190mW
880mW
275mW
recommended operating conditions
MIN
MAX
Supply voltage, VCC
7
40
V
Amplifier input vo~age, VI
0
VCC-2
40
V
Collector voltage
Output current (each output), sink or source, 10
TIming resistor,
R-r
Oscillator frequency, fosc
Operating free-air temperature, TA
0.3
mA
10
1.8
500
IlF
kn
kHz
1
300
0
70
TL598Q
-40
125
TL598M
-55
125
~TEXAS
4-70
mA
TL598C
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
V
200
0.00047
Current into feedback terminal, IlL
TIming capacitor, CT
UNIT
°C
TL598C,TL598Q,TL598M,TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B- FEBRUARY 1988- REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, VCC = 15 V
(unless otherwise noted)
reference section (see Note 2)
10=1 rnA
Input regulation
VCC = 7 V to 40 V
4.95
10=1 rnA to lOrnA
Output voltage change with
temperature
L\TA = MIN to MAX
Short-circuit output current§
REF=OV
5
4.9
TA = MIN to MAX
Output regulation
TYP;
MIN
TA = 25°C
Output voltage (REF)
TL598Q
TL598C
TEST CONDITIONSt
PARAMETER
MAX
MIN
TVP=I'
MAX
5.05
4.95
5
5.05
5.1
4.9
2
25
2
22
TA = 25°C
1
15
1
15
50
2
-10
V
5.1
TA=25°C
TA = MIN to MAX
UNIT
mV
mV
80
10
-10
-48
mVN
10
2
-48
rnA
t For conditions shown as MIN .or MAX, use the appropriate value specified under recommended operating conditions.
:I: All typical values except for parameter changes with temperature are at TA = 25°C.
§ Duration of the short circuit should not exceed one second.
NOTE 2: Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
oscillator section, CT = 0.001
~F,
RT = 12 kQ (see Figure 1) (see Note 2)
PARAMETER
TL598C, TL598Q
TEST CONDITIONSt
MIN
TYP;
Frequency
Standard deviation of frequency'l
Frequency change with voltage
All values of VCC, CT,
AT, TA constant
VCC = 7 Vto 40 V,
TA=25°C
L\TA = MIN to MAX
Frequency change with temperaturelt
L\TA = MIN to MAX,
CT=O.OI ~F
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:I: All typical values except for parameter changes with temperature are at TA = 25°C.
11 Standard deviation is a measure of the statistical distribution about the mean as derived from the formula: 0
=
UNIT
MAX
100
kHz
100
Hz/kHz
1
10
70
120
50
80
HzlkHz
Hz/kHz
N
I
(Xn - X)2
n-1
N- 1
# Effects of temperature on external AT and CT are not taken Into account.
NOTE 2: Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
error amplifier section (see Note 2)
PARAMETER
TL598C, TL598Q
TEST CONDITIONS
MIN
TYp:t:
MAX
UNIT
Input offset voltage
FEEDBACK = 2.5 V
2
10
mV
Input offset current
FEEDBACK = 2.5 V
25
250
nA
Input bias current
FEEDBACK = 2.5 V
0.2
1
~
Common-mode input voltage range
VCC =7Vt040V
Open-loop voltage amplification
L\VO (FEEDBACK) = 3 V,
0
to
VCC-2
Vo (FEEDBACK) = 0.5 V to 3.5 V
70
Unity-gain bandwidth
~VIC=6.5V,
Common-mode rejection ratio
VCC=40V,
Output sink current (FEEDBACK)
FEEDBACK = 0.5 V
Output source current (FEEDBACK)
FEEDBACK = 3.5 V
Phase margin at unity gain
FEEDBACK = 0.5 V to 3.5 V,
Supply voltage rejection ratio
FEEDBACK = 2.5 V,
TA=25°C
65
0.3 .
V
95
dB
800
kHz
80
dB
0.7
rnA
rnA
-2
~VCC=33V,
RL=2kn
RL=2kn
65°
100
dB
:I: All typical values except for parameter changes with temperature are at TA = 25°C.
NOTE 2: Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
="TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-71
TL598C, TL598Q, ,TL598M, TL598Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, Vee = 15 V
(unless otherwise noted)
undervoltage lockout section (see Note 2)
Threshold voltage
TL598C
TEST CONDITIONst
PARAMETER
MIN
TA = 25°C
~TA
= MIN to MAX
TA = 25°C
Hysteresis:!:
TA= MIN to MAX
TL598Q
MAX
MAX
MIN
4
6
4
6
3.5
6.9
3
6.9
100
100
50
30
UNIT
V
mV
t For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: Hysteresis is the difference between the positive-going input threshold voltage and the negative-going input thleshold voltage.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
output section (see Note 2)
PARAMETER
High-level output voltage
Low-level output voltage
Output control input current
TL598C, TL598Q
TEST CONDITIONS
VCC= 15V,
10=-200mA
12
VC= 15V
10 =-20 mA
13
VCC=15V,
10 =200 mA
VC= 15'V
10=20mA
MAX
MIN
UNIT
V
2
0.4
VI=Vref
VI =0.4V
V
3.5
mA
100
l1A
NOTE 2: Pulse-testing techmques must be used that maintain the Junction temperature as close to the ambient temperature as possible.
dead-time control section (see Figure 1) (see Note 2)
TEST CONDITIONS
PARAMETER
Input bias current (DTC)
VI = 0 to 5.25 V
Maximum duty cycle, each output
DTC=OV
Input threshold voltage (DTC)
TL598C
MIN
TL598Q
TYP9
MAX
-2
-10
0.45
Zero duty cycle
0
TYP9
MAX
-2
-25
3
3.2
UNIT
l1A
0.45
3
Maximum duty cycle
MIN
3.3
0
V
§ All typical values except for parameter changes with temperature are at r A = 25°C.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
pwm comparator section (see Note 2)
PARAMETER
TEST CONDITIONS
Input threshold voltage (FEEDBACK)
DTC=OV
Input sink current (FEEDBACK)
V(FEEDBACK) = 0.5 V
TL598C,TL598Q
MIN
0.3
TYP§
MAX
3.75
4.5
0.7
UNIT
V
mA
§ All typical values except for parameter changes with temperature are at TA = 25°C.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
total device (see Figure 1) (see Note 2)
PARAMETER
TEST CONDITIONS
Standby supply current
RT = Vref,
All other inputs and outputs open
Average supply current
DTC=2V
TL598C, TL598Q
TYP9
MAX
IVCC=15V
15
21
I VCC =4QV
20
26
MIN
15
UNIT
mA
mA
§ All tYPical values except for parameter changes with temperature are at TA = 25°C.
NOTE 2:
Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
-!!1TEXAS
INSTRUMENTS
4-7;1
POST OFFICE BOX 655303 • DAU.AS, TEXAS 75265
TL598C,TL598Q,TL598M, TL598V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, Vcc = 15 V
(unless otherwise noted)
switching characteristics, TA = 25°C (see Note 2)
PARAMETER
Output voltage rise time
OutpUl voltage fall time
TL598C, TL598Q
TEST CONDITIONS
CL = 1500 pF,
See Figure 2
VC= 15V,
MIN
TYP
MAX
60
150
35
75
VCC=15V,
UNIT
ns
NOTE 2: Pulse-testing techniques must be used that maintain the Junction temperature as close to the ambient temperature as possible.
reference section (see Note 2)
PARAMETER
t
TEST CONDITIONSt
TA=25°C
Output voltage (REF)
10=1 mA
Input regulation
VCC = 7 V to 40 V
TA = MIN to MAX
Output regulation
10=1 mAtol0mA
Output voltage change with temperature
.iTA = MIN to MAX
Short-circuit output current!i
REF=O
..
TL598M
MIN
TYP*
MAX
4.95
5
5.05
4.9
5.1
TA = 25°C
2
22
TA = 25°C
1
15
TA = MIN to MAX
80
UNIT
V
mV
mV
0.5%
-10
-48
..
..
mA
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
:j: All typical values except for parameter changes with temperature are at TA = 25°C.
§ Duration of the short circuit should not exceed one second.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
oscillator section, CT =0.001 IlF, RT =12 kn (see Figure 1) (see Note 2)
PARAMETER
TEST CONDITIONSt
TL598M
MIN
TYP*
Standard deviation of frequency'll
MAX
100
Frequency
All values of VCC, CT,
Frequency change with voltage
VCC = 7Vto 40 V,
Frequency change with temperature#
.iTA = MIN to MAX
kHz
AT, TA constant
10%
TA = 25°C
0.1%
1%
7%
150/0*
• On products compliant to MIL-STD-883, Class B, thiS parameter IS not production tested.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
:j: All typical values except for parameter changes with temperature are at TA = 25°C.
'Il Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
a
# Effects of temperature on external RT and CT are not taken into account.
UNIT
t
N-1
NOTE 2: Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-73
TL598C,TL598Q, TL598M,TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 "" REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, Vee
(unless otherwise noted)
=15 V
error amplifier section (see Note 2)
PARAMETER
TL598M
TEST CONDmONS
TYpt
MIN
UNIT
MAX
Input offset voltage
FEEDBACK at 2.5 V
2
10
Input offset current
FEEDBACK at 2.5 V
25
250
nA
Input bias current
FEEDBACK at 2.5 V
0.2
I
IJ.A
Common-mode input vo~age range
VCC = 7 V to 40 V
Open-loop voltage amplnication
INO (FEEDBACK) = 3 V,
0
to
VCC-2
Vo (FEEDBACK) = 0.5 V to 3.5 V
Common-mode rejection ratio
VCC=40V,
FEEDBACK at 0.5 V
LWIC = 6.5 V,
TA=25°C
V
70
Unity-gain bandwidth
Output sink current (FEEDBACK)
mV
95
dB
800
kHz
65
80
dB
0.3
0.7
rnA
Output source current (FEEDBACK)
FEEDBACK at 3.5 V
Phase margin at unity gain
FEEDBACK at 0.5 V to 3.5 V,
RL=2k(.l
-2
65°
Supply voltage rejection ratio
FEEDBACK at 2.5 V,
RL = 2 kg
100
L\VCC=33V,
rnA
dB
t All typical values except for parameter changes with temperature are at TA = 25°C.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
undervoltage lockout section (see Note 2)
TL598M
PARAMETER
Threshold voltage
TEST CO"'OITIONs*
MIN
TA=25°C
4
6
L\TA = MIN to MAX
3
6.9
100
TA = 25°C
Hysteresis§
MAX
TA = MIN to MAX
..
..
..
:I: For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions .
UNIT
V
mV
30
§ Hysteresis is the difference between the positive-going input threshold voltage and the negative-going input threshold vo~age.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
output section (see Note 2)
PARAMETER
Collector off-state current
High-level output voltage
Low-level output voltage
Output control input current
TEST CONDITIONS
TL598M
MIN
DTC connected to 0 V
VCE=40V,
VCC =40 V,
VCC=15V,
10=-200 rnA
12
VC= 15V
10=-20 rnA
13
VCC=15V,
10 =200 rnA
VC= 15V
10=20mA
TYP
MAX
2
100
UNIT
IJ.A
V
2
0.4
V
VI = REF
3.5
rnA
VI =0.4 V
100
IJ.A
NOTE 2: Pulse-testing techniques must be used that maintain the Junction temperature as close to the ambient temperature as possible.
~lExAs
INSTRUMENTS
4-74
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598C,TL598Q,TL598M,TL598Y
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
electrical characteristics over recommended operating free·air temperature range, Vee = 15 V
(unless otherwise noted)
dead-time control section (see Figure 1) (see Note 2)
PARAMETER
TEST CONDITIONS
Input bias current (DTC)
VI = 0 to 5.25 V
Maximum duty cycle, each output
DTCatOV
TL598M
MIN
MAX
-2
-25
3
3.2
UNIT
I1A
45%'
Zero duty cycle
Input threshold voltage (DTC)
TVPt
Maximum duty cycle
0'
V
* On products compliant to MIL-STD-883, Class B, this parameter IS not production tested.
t All typical values except for parameter changes with temperature are at TA = 25°C.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
pwm comparator section (see Note 2)
PARAMETER
TEST CONDITIONS
Input threshold voltage (FEEDBACK)
DTC=OV
Input sink current (FEEDBACK)
V(FEEDBACK) = 0.5 V
TL598M
MIN
0.3
TYPt
MAX
3.75
4.5
0.7
UNIT
V
mA
t All typical values except for parameter changes with temPl1rature are at TA = 25°C.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
total device (see Figure 1) (see Note 2)
TEST CONDITIONS
PARAMETER
Standby supply current
RTatREF,
All other inputs and outputs open
Average supply current
DTCat2V
NOTE 2:
TL598M
MIN
TVPt
MAX
IVCC=15V
15
21
I VCC=40V
20
26
15
UNIT
mA
mA
Pulse-testing techniques must be used that maintain the junction temperature as close to Ihe ambient temperature as possible.
switching characteristics, TA
=25°C (see Note 2)
TEST CONDITIONS
PARAMETER
Output voltage rise time
Output voltage fall time
CL = 1500 pF,
See Figure 2
VC= 15V,
VCC= 15V,
TL598M
MIN
TYP
MAX
150'
75'
UNIT
ns
* On products compliant to MIL-STD-883, Class B, this parameter IS not production tested.
NOTE 2: Pulse-testing techniques must be used that maintain the junction temperature as close to the ambient temperature as possible.
-!!1 TEXAS
.
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS. TEXAS 75265
4-75
TL598C, TL598Q,TL598M, TL598Y
PULSE-WIDTH-MODULATIQN CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
electrical characteristics, Vcc = 15 V, TA = 25°C
reference section (see Note 2)
PARAMETER
TL598Y
tEST CONDITIONS
MIN
UNIT
MAX
TYpt
Output voltage (REF)
10=1 rnA
5
V
Input regulation
VCC= 7 Vt040V
2
mV
Output regulation
10=1 mAt010mA
1
mV
Output voltage change with temperature
.t.TA = MIN to MAX
2
mVN
Short-circuit output current'
REF=OV
,
-48
rnA
t All typical values except for parameter changes with temperature are at TA = 25°C.
:t: Duration of the short circuit should not exceed one second.
NOTE 2 Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
oscillator section, CT
=0.001 IlF, RT = 12 k.Q (see Figure 1) (see Note 2)
TL598Y
TEST CONDITIONS
PARAMETER
MIN
,
Frequency
Standard deviation of frequency§
All values of VCC, CT, RT, TA constant
Frequency change with voltage
VCC= 7 Vt040 V,
§ Standard deviation is a measure of the statistical distribution about the mean as derived from the formula:
MAX
UNIT
100
kHz
100
Hz/kHz
1
HzlkHz
N
L (X
a =
NOTE 2
TYP
n -
X)2
n=1
N- 1
Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
error amplifier section (see Note 2)
PARAMETER
TL598Y
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Input offset voltage
Feedback = 2.5 V
2
Input offset current
Feedback = 2.5 V
25
nA
Input bias current
Feedback = 2.5 V
0.2
ItA
Open-loop voltage amplification
.t.VO (FEEDBACK) = 3 V,
Vo (FEEDBACK) = 0.5 V to 3.5 V
Unity-gain bandwidth
95
dB
800
kHz
80
dB
0.7
rnA
Common-mode rejection ratio
VCC=40V,
Output sink current (FEEDBACK)
FEEDBACK = 0.5 V
Phase margin at unity gain
FEEDBACK = 0.5 V to 3.5 V,
RL=2kD
65°
Supply voltage rejection ratio
FEEDBACK = 2.5 V,
RL=2 kD
100
NOTE 2
.t.VIC = 6.5 V,
.t.VCC=33V,
dB
Pulse-testing techniques that maintain the Junction temperature as close to the ambient temperature as poSSible must be used.
~TEXAS
.
INSTRUMENTS
4-76
mV
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL598C, TL598Q, TL598M,TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
electrical characteristics, Vee = 15 V, TA = 25°C
dead-time control section (see Figure 1) (see Note 2)
PARAMETER
TEST CONDITIONS
Tl598Y
MIN
TYP
Input bias current (DTC)
VI = 0 to 5.25 V
-2
Input threshold vo~age (DTC)
Zero duty cycle
3
NOTE 2
MAX
UNIT
IJ.A
V
Pulse-testing techniques that maintain the Junction temperature as close to the ambient temperature as possible must be used.
pwm comparator section (see Note 2)
PARAMETER
TEST CONDITIONS
Input threshold voltage (FEEDBACK)
DTC=OV
Input sink current (FEEDBACK)
FEEDBACK = 0.5 V
NOTE 2
Tl598Y
MIN
TYP
MAX
3.75
UNIT
V
0.7
rnA
Pulse-testing techniques that maintain the Junction temperature as close to the ambient temperature as possible must be used.
total device (see Figure 1) (see Note 2)
PARAMETER
TEST CONDITIONS
Standby supply current
RT=Vref.
All other inputs and outputs open
Average supply current
DTC=2V
NOTE 2
TL598Y
MIN
TYP
IVcc= 15V
15
IVCC=40V
20
15
MAX
UNIT
rnA
rnA
Pulse-testing techniques that maintain the junction temperature as close to the ambient temperature as possible must be used.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-77
TL598C, TL598Q, TL598M, TL598Y,
PULSE-WIDTH-MOPULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
Output
15V
VCC
1
2
3
TelSt{
InputlS
4
5
6
.__-t--+- Vc
IN} ERROR
IN- AMP1
16
ERROR {IN+
AMP 2
IN- 15
50kQ
FEEDBACK
DTC
REF
CT
OUTPUTCTRL
RT
Vc
0.0011lF
OUT1
12kQ
7
OUT2
SIGNALGND
POWERGND
14
13
11
8
9
15V
OUTPUT 1
VI
FEEDBACK
OUTPUT 2
10
MAIN DEVICE TEST CIRCUIT
ERROR AMPLIFIER TEST CIRCUIT
Figure 1. Test Circuits
-r----VC
. - - - - . - - Output
OV
-=- POWERGND
OUTPUT CONFIGURATION
OUTPUT VOLTAGE WAVEFORM
Figure 2. Switching Output Configuration and Voltage Waveform
~TEXAS
4-78
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL598C,TL598Q,TL598M,TL598Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS053B - FEBRUARY 1988 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY AND
FREQUENCY VARIATION t
va
TIMING RESISTANCE
AMPLIFIER VOLTAGE AMPLIFICATION
vs
FREQUENCY
60
100 k
Vee = 15 V
40k
-2%
N
J:
I
...
>c
!!
~
IL
j
..
.....
..9
'i:j
,
~/
10k ~ == -1%
-
0%- -
4k
1k
I
ox'"
.-
60
:I:
ii
E
c(
CD
40
:l!
400
.1f t = 1%
100
40
r:=
10
1k
t
I
CIt
0
I
"c
0.0011lF
... O.011lF
0.11lF
~ Vee=15V
I- AVO=3V
I- TA = 25°e
III
~
I:!!
"
~
~
ii
E
eT=1IlF
20
c(
111111
'"
o
4k
10k
40k 100k
RT - Timing Resistance - Q
400k
1M
1k
10 k
100k
1M
f - Frequency - Hz
Frequency variation (AI) is the change in predicted oscillator
frequency that occurs over the full temperature range.
Figure 4
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
4-79
4-80
TL1451AC,TL1451AV
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C-
•
•
•
•
•
•
•
Complete PWM Power Control Circuitry
Completely Synchronized Operation
Internal Undervoltage Lockout Protection
Wide Supply Voltage Range
Internal Short-Circuit Protection
Oscillator Frequency .•• 500 kHz Max
Variable Dead Time Provides Control Over
Total Range
• Internal Regulator Provides a Stable 2.5-V
Reference Supply
1983 - REVISED OCTOBER
DB, N, NS, OR PW PACKAGE
(TOP VIEW)
REF
SCP
CT
RT
ERROR {1IN+
AMPLIFIER 1 11N1FEEDBACK
5
1DTC
6
21N~ ERROR
21N-j' AMPLIFIER 2
2FEEDBACK
20UT
description
The TL1451AC incorporates on a single monolithic chip all the functions required in the construction of two
pulse-width-modulation (PWM) control circuits. Designed primarily for power supply control, the TL1451AC
contains an on-chip 2.5-V regulator, two error amplifiers, an adjustable oscillator, two dead-time comparators,
undervoltage lockout circuitry, and dual common-emitter output transistor circuits.
The uncommitted output transistors provide common-emitter output capability for each controller. The internal
amplifiers exhibit a common-mode voltage range from 1.04 V to 1.45 V. The dead-time control (DTC)
comparator has no offset unless externally altered and can provide 0% to 100% dead time. The on-chip oscillator
can be operated by terminating RT and CT. During low VCC conditions, the undervoltage lockout control circuit
feature locks the outputs off until the internal circuitry is operational.
The TL 1451AC is characterized for operation from -20°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(DB)t
PLASnCDIP
(N)
SMALL OUTLINE
(NS)
TSSOP
(PW)t
-20°C to 85°C
Tl1451ACDB
TL1451ACN
TLl451ACNS
TL1451ACPW
CHIP FORM
(Y)
TL1451AY
tThe DB and PW packages are only available left·end taped and reeled (add LE SUffiX, I.e., TL1451ACPWLE).
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-81
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
functional block diagram
VCC RT
2DTC
CT
~11~~__________________-+9~~2~~~~_____
ERRORjIN+ 14
AMPLIFIER 2 ~N- 13
+
2 FEEDBACK -"12"---__--i~---_I
1 FEEDBACK -'<5----i~-+-_i
~------+_-----+-----~~~~16 REF
SCP .'-'1S"--__-+-t-...-...-__-,
ERROR JlN+ 3
AMPLIFIER 1 ~N- 4
1DTC
~6
71 OUTPUT
__________r-______________________"'-__- J
~________________________________________~8
COMPONENT COUNT
Resistors
65
Capacitors
8
Transistors
105
JFETs
18
~TEXAS
4-82
INSTRUMENTS
POST oFFice Box 655303. DALLAS, TexAS 75265
GND
TL1451AC,TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TL1451AY chip information
This chip, when properly assembled, displays characteristics similar to the TL 1451AC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
CT
RT
11N+
11N1 FEEDBACK
(1)
(16)
(2)
(15)
(3)
(14)
(4)
(13)
(5)
TL1451Y
(12)
(6)
(11)
(7)
(10)
GND (8)
(9)
1DTC
10UT
REF
SCP
21N+
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
21N2FEEDBACK
TJmax
=150 e
0
2DTC
TOLERANCES
ARE ±10%.
20UT
ALL DIMENSIONS
ARE IN MILS.
Vee
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-83
TL1451AC,TL1451AY
DUAL PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
absolute maximum ratings over operating free-air temperature ranget
Supply voltage, Vee ................................................................. . . . . .. 51 V
Amplifier input voltage, VI .................... ,............................................. 20 V
Collector output voltage, Vo ................................................................ 51 V
Collector output current, 10 ................................•............................•.. 21 mA
Continuous power total dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ................ ,........................... -20°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION R~TING TABLE
TA:S;25°C
POWER RATING
DERATING FACTOR
ABOVE TA" 25°C
DB
775mW
N
1000mW
NS
PW
PACKAGE
=
=
TA 70°C
POWER RATING
TA 85°C
POWER RATING
6.2mW/oC
496mW
403mW
8.0mW/oC
640mW
520mW
500mW
4.0mW/oC
320mW
260mW
700mW
5.6mW/oC
448mW
364mW
recommended operating conditions
MIN
MAX
3.6
50
1.05
1.45
V
Collector output voltage, Vo
50
V
Collector output current, 10
20
rnA
Current into feedback terminal
45
ItA
Supply voltage, VCC
Amplifier input voltage, VI
UNIT
V
kn
Feedback resistor, RF
100
liming capacitor, CT
150
15000
pF
5.1
100
kG
1
500
kHz
-20
85
°C
Timing resistor,
Ftr
Oscillator frequency
Operating free-air temperature, TA
electrical characteristics over recommended operating free-air temperature range, Vee = 6 V,
f = 200 kHz (unless otherwise noted)
reference section
TL1451Y
TL1451AC
PARAMETER
Output voltage (pin 16)
Output voltage change with temperature
TEST CONDITIONS
MIN
TYPt
MAX
MIN
TYpt
2.5
2.6
2.5
TA = -20°C to 25°C.
-0.1%
±1"10
-0.1%
TA = 25°C to 85°C
10=1mA
2.4
MAX
UNIT
V
-0.2%
±1"10
-0.2%
Input voltage regulation
VCC =3.6 Vt040V
2
12.5
2
mV
Output voltage regulation
10=0.1 rnA to 1 rnA
1
7.5
1
mV
Short-circuit output current
VO=O
10
30
10
rnA
3
t All typical values are at TA = 25°C.
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
undervoltage lockout section
TL1451AC, TL1451AY
PARAMETER
TEST CONDITIONS
TYpt
MIN
MAX
UNIT
Upper threshold voltage (Vee)
2.72
Lower threshold voltage (Vee)
2.6
V
80
120
mV
1.5
1.9
V
10(ref) = 0.1 rnA,
Hysteresis (Vee)
TA=25°e
Reset threshold voltage (Vee)
V
t All typical values are at TA = 25°e.
short-circuit protection control section
PARAMETER
TEST CONDITIONS
TL1451AC
MIN
TL1451AY
TYpt
MAX
MIN
0.65
Input threshold voltage (SCP)
TA=25°C
0.65
0.7
0.75
Standby voltage (SCP)
No pullup
140
185
230
60
120
-10
-15
-20
Latched input voltage (SCP)
No pullup
Input (source) current
VI=0.7V,
TA = 25°C
Comparator threshold voHage (FEEDBACK)
TYpt
MAX
0.7
0.75
185
1.18
-15
V
mV
mV
60
-10
UNIT
-20
1.18
I1A
V
t All typical values are at TA = 25°C.
oscillator section
TEST CONDITIONS
PARAMETER
TL1451AY
TL1451C
TYPt
MIN
MAX
TYpt
MIN
Frequency
CT=330pF,
Rpl0kQ
200
200
Standard deviation of frequency
CT=330pF,
RT=10kQ
10%
10%
Frequency change with voltage
Frequency change with temperature
VCC = 3.6 V to 40 V
1%
TA = -20°C to 25°C
-0.4%
±2%
-0.4%
TA = 25°C to 85°C
-0.2%
±2%
-0.2%
MAX
UNIT
kHz
1%
t All typical values are at TA = 25°C.
dead-time control section
PARAMETER
TEST CONDITIONS
TL1451AC
MIN
TYPt
TA = 25°C
-80
-145
10 =40 I1A
2.3
Input bias current (DTC)
Latch mode (source) current (DTC)
Latched input voltage (DTC)
Input threshold voltage at f = 10kHz (DTC)
TL1451AY
MAX
MIN
TYpt
-80
-145
1
Zero duty cycle
Maximum duty cycle
UNIT
I1A
I1A
V
2.05
1.2
MAX
1.45
2.25
2.05
1.45
V
t All typical values are at TA = 25°C.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-85
TL1451AC,TL1451AY
DUAL PULSE·WIDTH·MODULATION CONTROL CIRCUITS
<
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
error-amplifier section
PARAMETER
TL1451AY
TL1451AC
TEST CONDITIONS
TYpt
MIN
MAX
Input offset voltage
Vo (FEEDBACK) = 1.25 V
±6
Input offset current
Va (FEEDBACK) = 1.25 V
±100
Input biaS current
Vo (FEEDBACK) = 1.25 V
Common-mode input voltage range
VCC = 3.6 Vto40V
Open-loop voltage amplHication
RF= 200 kil
160
TYpt
MIN
MAX
mV
nA
500
160
nA
1.05
to
1.45
V
70
Unity-gain bandwidth
Common-mode rejection ratio
60
Positive output voltage swing
Vref- 0.1
80
80
dB
1.5
1.5
MHz
80
80
dB
V
Negative output voltage swing
V
1
Output (Sink) current (FEEDBACK)
VID=-0.1 V.
VO=1.25V
0.5
Output (source) current (FEEDBACK)
VID=0.1 V.
VO=1.25V
-45
UNIT
<
1.6
1.6
rnA
-70
-70
!iA
t All typIcal values are at TA = 25°C.
output section
PARAMETER
TEST CONDITIONS
TL1451AC
MIN
TYPt
Collector off-state current
VO=50V
Output saturation voltage
IO=10mA
1.2
Short-circuit output current
VO=6V
90
TL1451AY
MAX
TYpt
MIN
MAX
UNIT
!iA
10
2
1.2
V
90
rnA
t All typIcal values are at TA = 25°C.
pwm comparator section
PARAMETER
TEST CONDITIONS
Input threshold voltage at f = 10kHz (FEEDBACK)
TL1451AC
MIN
MAX
2.05
2.25
Zero duty cycle
Maximum dUty cycle
TL1451AY
TYpt
1.2
TYpt
MIN
MAX
2.05
1.45
1.45
UNIT
V
t All typIcal values are at TA = 25°C.
total device
PARAMETER
TEST CONDITIONS
TL1451AC
TYpt
MAX
MIN
TL1451AY
TYpt
MAX
MIN
UNIT
Standby supply current
Off-state
1.3
1.8
1.3
rnA
Average supply current
RT=10kO
1.7
2.4
1.7
rnA
t All typical values are at TA = 25°C.
~TEXAS
4-86
INSTRUMENTS
POST OFFICE BOX 65530&. DALLAS. TEXAS 75265
TL1451AC,TL1451AV
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983- REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
Test
Input
Vcc = 5 V
~
CPEI 0.47 IlF
RL
4.7kO
rh
I
I
T
OUT1
RL
OUT2
4.7kO
16 15 14 13 12 11 10 9
D
1
TL1551AC
2
3
I
7
I
~± ~
330pF
456
8
I
10kO
,rt7
rt7 '-y-I
rt7
Test
Input
Figure 1. Test Circuit
"Oscillator Triangle Waveform
+
ErrorAmplifieroutPut~f!!srl.~~~~A-.~~A..:;~~~~A-J.A~E~
Dead-l1melnputVoltage-;
~
~
~
Short-Circuit Protection
Comparator Input Voltage
PWM Comparator Output Voltage
1
1
Short-Circuit Protection
Comparator Output
Power Supply Voltage
1
1
1¥
I.....
r
U
I
1
1
#
Ulv
H
L
1
1
_+_
".
LI~
1
1
- - -
1.6V
2.0V
I " Dead Time 100%
1 1
_1 _ _ "_ _ _ _ _ _
Protection Enable
Terminal Waveform
I~
1 I"
Output Transistor Collector
Waveform
1
- O.6V
.A
~~
,...............
~
14- t t ~
I.
H
,--- L
pe
1
1
t--
-
-
0v
H
L
UV
L 2.8 V TYP
~--~------------------------------------------------OV
t Protection Enable TIme, Ipe = (0.051 x 106 x Cpe) in seconds
Figure 2. TL1451 AC Timing Diagram
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-87
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATIONCONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
. TYPICAL CHARACTERISTICS
TRIANGLE OSCILLATOR FREQUENCY
vs
TIMING RESISTANCE
OSCILLATOR FREQUENCY VARIATION
vs
FREE-AIR TEMPERATURE
3~--~----~-----r----~--~
1M
VCC=3.6V
RT=10kn
Cr=330pF
fosc 200 kHz
VCC=5V
TA=25°C
~
I
2
f
"
(lOOk
IL
j
=
CT=150pF
~
" ~ I'
~
Cr=l500pF
J
10k
I
J
-2~--~~---+-----r----~----1
Cr=l50oopF
~I"IIIIII
"I
mllll
1k
1k
4k
10 k
40k lOOk
RT - TIming Resistance -
400k
~~--~----~----~----~--~
-25
1M
0
25
50
75
TA - Free-Air Temperature - °c
n
Figure 3
Figure 4
TRIANGLE WAVEFORM PERIOD
vs
TIMING CAPACITANCE
TRIANGLE WAVEFORM SWING VOLTAGE
vs
TIMING CAPACITANCE
2.6
>I
GO
aI
102
2.4 ~
2.2
,
••
I
'8
·c
2
:.
1.8
1.6
i
~
1.4
.!!
"'
c
1\1
~
aI
C
101
V
0.8
101
,/
100
~
/,'
1.2
jE
103
104
105
Cr - TIming Capacitance - pF
CT - TIming capacitance - pF
FigureS
Figure 6
~T~.
INSTRUMENTS
4-88
I
E
0
E
i
~
::I.
aI
C
III
VCC=5V
RT=5.1kn
TA = 25°C
.
...........
J!
$!
VCC=5V
RT=5.1 kn
TA = 25°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100
TL1451AC,TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
REFERENCE OUTPUT VOLTAGE VARIATION
va
FREE-AIR TEMPERATURE
REFERENCE OUTPUT VOLTAGE VARIATION
va
FREE-AIR TEMPERATURE
30r----,-----,-----,-----.----,
~
I
Vee = 3.6 V
c
11(ref)
I
~I
=1 mA
I
J
i
~
I
~
Or-~~~~~~~7b~~~~__;
o
§ -10r-~~----_+----_+~~~~__4
g
j
I
!
.p
75
-·e
11(ref)
=1I. mA
I
J
i
o
~
I
>~
>
I
2~~--__+_--+_--t__~--_+--_r__i
c
0
~
0.9
...............
~
1.5 t-t-t----t----t---+---1---+----+-___l
GI
CI>
0.8
~
'!i0
a.
0.7
~
~
-.....
~
r--
e
Q
0.5 H--+----+---+---t__~--_+--4___i
0~.....J..
o
5
__...l__ _
_ _.....J...__
10
15
20
25 30
Vee - Supply Voltage - V
~__L
~~
__
35
0.6
~
40
-25
o
25
50
TA - Free-Air Temperature
Figure 9
75
-·e
100
Figure 10
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4--89
TL1451AC,TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
UNDERVOLTAGE LOCKOUT
HYSTERESIS CHARACTERISTICS
6
>
5
&
:Il!
4
I
~
j
'0
(J
i
!
UNDERVOLTAGE LOCKOUT CHARACTERISTIC
,
'I TA=250C
I
TA = 85°e
TA = -20oe
3.5
300
& 3.25
:Il!
250
>
I
~
J
150
j
~
2
0
W
1.VOE
8
~
2.5
100
t
2.25
50
~III
2
!I"
1=10
7,1
I
0
::)
10=10mA
2
3
4
Vee - SUpply Voltage - V
-25
5
o
75
25
50
TA - Free-Air Temperature - °e
Figure 11
Figure 12
SHORT-CIRCUIT PROTECTION CHARACTERISTICS
3
1.30
>
~
~
~
..............
1.20
j
!.
E
0
(J
Short-CIrcuit Protection
Latch Reset Supply Voltage
(Right Scale)
1.25
z:
~
>
I
I
&
:Il!
-
hi
I
o
-
t
2.5 ~
~
Q.
:::0
III
2
..... ~
I
I
a:
z:
ShortJLUit Protection
..........
1.15 I- Comparator Threshold Voltage
(Lett Scale)
1.10
-25
f
-8c
::)
I
o
1
~
"c
I
I
:I:
'$
5V
o
i
2.75
I-
3
I
III
200 ~
3
""0z:
,
~
~
I
25
50
75
TA - Free-Air Temperature - °e
Figure 13
~TEXAS "
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
1.5
~I
~
1
100
100
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983- REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
PROTECTION ENABLE TIME
vs
PROTECTION ENABLE CAPACITANCE
18
.
15
I
~
1=
~III
12
./
C
w
c
1
9
6
V
II.
I
J.
3
o
V"
/
./
/
o
100
150
50
200
CPE - Protection Enable Capacitance - I1F
SCP
15
250
Vref
16 .
170 len
Vref
Vref
Short-cIrcuit
Protection
Comparator
ERROR AMP 1
ERROR AMP 2
1.25 V
Figure 14
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
4-91
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OPEN·LOOP VOLTAGE AMPLIFICATION
ERROR AMP MAXIMUM OUTPUT VOLTAGE SWING
2.25
vs
vs
FREQUENCY
FREQUENCY
90
Jc~~IJI~1
TA=25°c
DI
I
r---.r-.
c
70
i!IE
60
is.
E
V
C
40
Go
0
30
.9
c
B0
0.25
o
",
50
t
~
1k
TA=25°c
'a
0
i
V~~~I~I~
"\..
80
."r.....
I" . .
20
10
'\
o
10k
100k
1M
f - Frequency - Hz
10M
1k
100
Figure 15
Figure 16
GAIN (AMPLIFIER IN
UNITY-GAIN CONFIGURATION)
vs
FREQUENCY
10
,_'"'
Vcc=5V
TA = 25°C
5
0
1\
DI
'a
I
c
ii
-S
1\
CI
I
CI
10k
100k
f - Frequency - Hz
-10
-15
-20
1k
10k
100k
1M
f - Frequency - Hz
Figure 17
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10M
1M2M
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE SHIFT
vs
FREQUENCY
70
60
III
v
VCC=5V
Rref= 1500
Cref=470pF
TA=25°C
50
I
c
ii
CJ
CX: 0 47pF
• 470pF
/::,. 4700pF
/
1/
40
!
,\0
30
1u
2q
10
o
100
,....
I'~
Closed-Loop Gain
(Left Scale)
1-'
1\
-
~ ....
-
~
~~
~
, ,
Ir Phase Shift
(Right Scale)
0°
l'
V
" '"
~ " DRs
.... P>- r-.' :::::::-~
::::::
~
10k
f - Frequency - Hz
39kn
r-- r--
100k
Rref
39kn
Test Circuit
Figure 18
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
!III
_20°:
r- I"- r--
V
~
1k
-10°
.......
-30°
-40°
"'1"-
r--. t--.ro-
_50°
_60°
_70°
-80°
-90°
1M
.!
1:1.
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE SHIFT
vs
FREQUENCY
70
60
III
'0
CX: 0 47pF
• 470pF
/:;. 4700pF
VCC=5V
Rref= 15 Q
Cref = 470 pF
TA=25"C
c
ii
CI
kr
40
~..
30
13
20
0
-
i--"f-"
~
...-
o
100
V
~
=>K r--..
--"-
J.
10
/
Closed-Loop Gain
(Left Scala)
Q.
8
1
r-
50
I
1k
[) ~ t--.~~
-
.JI'
~~
Phasa Shift
(Right Scale)
-
-100
II .......r--. .....
~ ,/'
r--
~
--
_soo
-700
~~
-800
-90
1M
0
10k
100k
39kQ
Rref
Cref
39kQ
TestClrcuh
Figure 19
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAL1.AS. TEXAS 75265
~
f/)
=
-20
-300 !
IL
_40 0
0
_60 0
.....
t - Frequency - Hz
4-94
00
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE SHIFT
VB
FREQUENCY
70
60
m
"c
cx: 0
VCC=SV
Rref=1S0
Cref = 470 pF
TA=25°C
47pF
• 470pF
/:;. 4700pF
I
SO
I
'iii
CI
40
V /11
I
a.
0
i..
~
30
-e-
c----
I.
I
r------
20
10
o
--
100
/
Closed-Loop Gain
(Left Scale)
..........
r-.-
-
------- ~
-
'r"'"
...l--1k
y
~
~
'":::--
.
..... r-~
~
'6i'
Phase Shift
(Right Scale)
\
~
............
......
-
"""- r--
10k
f - Frequency - Hz
39kn
--r-....
..... ......
'7
100k
0°
-10° ~
III
_20° CD
...
-30°
_40°
1"- ....
_60°
::
if
_soo
-70°
_80°
_90°
1M
Rref
39kO
Test Circuit
Figure 20
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAu.AS, TEXAS 75265
4-95
TL1451AC, TL1451AV
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN AND PHASE SHIFT
vs
FREQUENCY
70
60
ID
'U
r-
VCC=5V
Cref=470pF
TA=250C
50
I
00
c:
"ii
CJ
40
a.
0
~..
30
c3
20
..
10
o
100
Closed-Loop Gain
(Left Scale)
Phase Shift
(Right Scale,!...-
r--. ........
---
~
......
~~
.......
...
1k
.........
........
1-"-
F~ency
--r-
-30°.l!
Q.
"'"500
-700
100k
- Hz
391<0
Cref
391<0
TestClrcuH
Figure.21
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
~
III
-200 ::
-400
t-.
Vref
4-96
1-1-
-600
10k
f-
II-- I-"
-100
-800
-900
1M
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OUTPUT SINK CURRENT
vs
COLLECTOR OUTPUT SATURATION VOLTAGE
120
TA=-20°C
110
100
~
I
fII
50
'S
8:::I
0
I
80
70
...•05
I /
90
C
~:s
.....-- :::::--
V/
II
TA=25°C
/~=85OC./
I J /
II /
II V
/1
1/
60
40
,
30
l
20
10
VCC=3.6V
o/
o
5
10
15
Collector Output Saturation Voltage - V
20
Figure 22
MAXIMUM OUTPUT VOLTAGE SWING
vs
FREE-AIR TEMPERATURE
VO(ref) -0.01
>
>
I
8'
~
.
J
0.9
VO(ref) -0.02
c
33k!l
"i
..
fII
0.8
VO(ref) -0.03
~
!'S
I
DI
DI
~
33 k!l
~
0.7
VO(ref) -0.04
'SQ.
'S
0
0
E
:s
E VO(raf) -0.05
E
:::I
E
0.6
'j(
1\1
-=
:E
:E
l:. VO(ref) -0.06
0.5
~
I
:E
~
VO(raf) -0.07
-25
0
25
75
50
TA - Free-Air Temperature - °C
Vvom -1
VCC=3.6V
RL= 100kn
VOM+1 = 1.25 V
YOM -1 = 1.15 V (Right Scale)
YOM -1 = 1.35 V (Left Scale)
TEST CIRCUIT
100
Figure 23
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-97
TL1451AC, TL1451AY
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OUTPUT TRANSISTOR "ON" DUTY CYCLE
vs
DEAD-TIME INPUT VOLTAGE
0
ilI
!
~
,I
VCC=3.6V
RT=10kQ
Cp 330 pF
10
TA=25°C
oC
...
40
'c
50
~
60
'iii
c
~
70
f
0
80
"S
I
I
I
I
I
I
II
30
0
C
1.5
.!'
"Q
1.25
I
i
"Q
c
@.
1.5
2
0.75
0.5
U
I
0.5
~
;l
9
o
1.75
~
::I
u
c
90
100
2
E
20
::I
Q
STANDBY CURRENT
vs
SUPPLY VOLTAGE
2.5
3
3.5
0.25
o !)
o
4
Figure 24
Figure 25
MAXIMUM CONTINUOUS POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
STANDBY CURRENT
vs
FREE-AIR TEMPERATURE
I
oC
1.75
E
I
C
~
u
1.5
~
1.25
-aa.
~
Stand-By Current, VCC = 40 v,'N;;toad
,-
I
,
I
~
Stand-By Current, VCC = 3.6 V, No Load
::I
III
,
U
9
ii
is
J
0.5
o
25
50
75
Thermal Resistance
~25°CIW
800
700
600
~
400
8
300
::I
200
I
100
E
I"
900
500
E
0.25
-25
16-Pln N Plastic Dip
1000
&
::I
C
0.75
o
1100
I
c
I-+--
I
_
1200
I
Average Supply Current
VCC=6V,RT=10kQ,
CT=330pF
-
2
16-Pln NS Plastic SO
o
-25
100
TA - Free-Air Temperature - °c
Figure 26
...............
Thermal
INSTRUMENTS
POST OFFICE
sox 655303 •
DALLAS, TEXAS 75265
"" "
Resista~
250°CIW
o
-..
75
25
50
TA - Free-Air Temperature
Figure 27
~TEXAS
4-98
40
10
20
30
VCC - Supply Voltage - V
Dead-Time Input Voltage - V
100
TL1451AC,TL1451AV
DUAL PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS024C - FEBRUARY 1983 - REVISED OCTOBER 1995
APPLICATION INFORMATION
Vcc
220kn
4700
33kn
-=-
-=-
-=C2 Step-Up
Output
33kn
Vref
16 15 14 13 12 11 10
9
TL1451AC
C4 Step-Down
Output
NOTE A. Values for Rl through R7, Cl through C4, and L1 and L2 depend upon individual application.
Figure 28. High-Speed Dual Switching Regulator
~TEXAS
INSTRUMENTS
l'OST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-99
4-100
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A-
• Two Complete PWM Control Circuits
1995 - REVISED OCTOBER 1995
D, N OR PW PACKAGE
(TOP VIEW)
• Outputs Drive MOSFETs Directly
• Oscillator Frequency .•. 50 kHz to 2 MHz
!1
16
2
15
3
14
IN1+ [ 4
IN1- 5
13
CT
• 3.6-V to 2G-V Supply-Voltage Range
RT
• Low Supply Current ••• 3.5 mA Typ
• Adjustable Dead-Time Control, 0% to 100%
DTC1
• 1.25-V Reference
COMP1
GND
description
oun
I
I!
I
12
REF
SCP
DTC2
IN2+
IN2-
6
11
COMP2
7
10
Vee
8
9
OUT2
The TL1454 is a dual-channel pulse-widthmodulation (PWM) control circuit, primarily
intended for low-power, dc/dc converters.
Applications include LCD displays, backlight
inverters, notebook computers, and other products requiring small, high-frequency, dc/dc converters. Each
PWM channel has its own error amplifier, PWM comparator, dead-time control comparator, and MOSFET driver.
The voltage reference, oscillator, undervoltage lockout, and short-circuit protection are common to both
channels.
Channel 1 is configured to drive n-chann~1 MOSFETs in step-up or flyback converters, and channel 2 is
configured to drive p-channel MOSFETs in step-down or inverting converters. The operating frequency is set
with an extemal resistor and an external capacitor,and dead time is continuously adjustable from 0 to 100%
duty cycle with a resistive divider network. Soft start can be implemented by adding a capacitor to the dead-time
control (OTC) network. The error-amplifier common-mode input range includes ground, which allows the
TL1454 to be used in ground-sensing battery chargers as well as voltage converters.
AVAILABLE OPTIONS
PACKAGED DEVICESt
CHIP FORM
TA
SMALL OUTLINE
(D)
-20·C to 85·C
TL1454CD
TL1454CN
TL1454CPWLE
TL1454Y
-40·C to 85·C
TL1454ID
TL1454IN
-
-
PLASTIC DIP
(N)
TSSOP
(PW)
(V)
t The 0 package IS available taped and reeled. Add the SuffiX R to the deVice name (e.g., TL 1454CDR). The
PW package is available only left-end taped and reeled (indicated by the LE suffix on the device type; e.g.,
TL1454CPWLE).
~TEXAS
Copyright © 1995, Texas InSiruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4-101
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SL.VS086A- APRIL 1995 - REYISED OCTOBER 1995
functional block diagram
vcc
RT CT
10
rv~;;r::1~.2~5~V____________~~========~
Internal
L-":':;"J-2_.5_V"t"--. To
Circuitry
__~~~~~~__~16 REF
M-
GND ...:7__________•
--
PWM
COMP1 - " - - - - ,
1.8 V
1.2V
VCC
PWM
Comparator 2
COMP2 -'-'-------,
IN2+
VCC
IN2-
Error
Amplifier 2
UVLO
and
, SCPLatch
0.65 V
15
SCP
3
~TEXAS
4-102
14
DTC1 'DTC2
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
TL1454Y chip Information
This chip, when properly assembled, displays characteristics similar to the TL1454C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-=
-=
I..
108
.1
1'1'1'1'1'1'1')'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'I
RT
CT
DTC1
IN1+
IN1COMP1
GND
(1)
(16)
(2)
(15)
(3)
(14)
(13)
(4)
(5)
TL1454Y
(12)
(6)
(11)
(7)
(10)
OUT1 (8)
REF
SCP
DTC2
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
IN2+
TJmax = 150°C
IN2-
TOLERANCES ARE ±10"/o.
COMP2
ALL DIMENSIONS ARE IN MILS.
VCC
(9)
OUT2
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75~65
4-103
Tl~454,
Tl1454Y
DUAL-CHANNEL PUlSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A-APRIL t995-REVISED OCTOBER t995
theory of operation
reference voitage
A linear regulator operating from Vee generates a 2.5-V supply for the internal circuits and the 1.25-V reference,
which can source a maximum of 1 mA for external loads. A small ceramic capacitor (O.047I1F to O.111F) between
REF and ground is recommended to minimize noise pickup.
error amplifier
The error amplifier generates the error. signal used by the PWM to adjust the power-switch duty cycle for the
desired converter output voltage. The signal is generated by comparing a sample of the output voltage to the
voltage referenc:e and amplifying the difference. An external resistive divider connected Iletween the converter
output and ground, as shown in Figure 1, is generally required to obtain the output voltage sample.
The amplifier output is brought out on COMP to allow the frequency response of the amplifier to be shaped with
an external RC network to stabiliie the feedback loop of the converter. DC loading on the COMP output is limited
to 4511A (the maximum amplifier source current capability).
Figure 1 illustrates the sense-divider network and error-amplifier connections for converters with positive output
voltages. The divider network is connected to the non inverting amplifier input because the PWM has a phase
inversion; the duty cycle decreases as the error-amplifier output increases .
. ~~--TU454
Compensstion
Network
R3
Converter
Output
Vo
---'-A,/'I!v-----<.-F'-'--I
Rl
>-e---
To PWM
R2
Figure 1. Sense DlvlderJError Amplifier
Configuration for Converters with Positive Outputs
The output voltage is given by:
V0
= V ref
(1
+ ~~)
where Vref'= 1.25 V.
The dc source resistance of the error-amplifier inputs should be 10 k.Q or less and approximately matched to
minimize output voltage errors caused by the input-bias current. A simple procedure for determining appropriate
values for the resistors is to choose a convenient value for R3 (10 kQ or less) and calculate R1 and R2 using:
R
_
R3V O
1 - VO-V ref
~TEXAS .
4-104
INSTRUMENTS
POST OFFICE BOX 665303 • DALLAS. TEXAS 75265
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A-APRIL 1995- REVISED OCTOBER 1995
error amplifier
R1 and R2 should be tight-tolerance (±1 % or better) devices with low andlor matched temperature coefficients
to minimize output voltage errors. A device with a ±5% tolerance is suitable for R3.
r:-----REF
R2
Compensation
Network
>-.....R1
ToPWM
R3
Converter V
Output 0
Figure 2. Sense DividerlError Amplifier Configuration for Converters with Negative Outputs
Figure 2 shows the divider network and error-amplifier configuration for negative output voltages. In general,
the comments for positive output voltages also apply for negative outputs. The output voltage is given by:
V
o
= _ R1V ref
R2
The design procedure for choosing the resistor value is to select a convenient value for R2 (instead of R3 in the
procedure for positive outputs) and calculate R1 and R3 using:
R1 = -
R
R2 V O
V ref
_ R1R2
3 - R1 + R2
Values in the 1O-kn to 20-kn range work well for R2. R3 can be omitted and the noninverting amplifier connected
to ground in applications where the output voltage tolerance is not critical.
oscillator
The oscillator frequency can be set between 50 kHz and 2 MHz with a resistor connected between RT and GND
and a capacitor between CT and GND (see Figure 3). Figure 6 is used to determine RT and CT for the desired
.operating frequency. Both components should be tight-tolerance, temperature-stable devices to minimize
frequency deviation. A 1% metal-film resistor is recommended for RT, and a 10%, or better, NPO ceramic
capacitor is recommended for CT.
TL1454
RT
2
Figure 3. Oscillator Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-105
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REViSED .OCTOBER 1995
dead-time control (DTC) and soft start
The two PWM channels have independent dead-time control inputs so that the maximum power-switch duty
cycles can be limited to less then 100%. The dead-time is set with a voltage applied to DTC; the voltage is
typically obtained from a resistive divider connected between the reference and ground as shown in Figure 4.
Soft start is implemented by adding a capacitor between REF and DTC.
The voltage, VOT, required to limit the duty cycle to a maximum value is given by
V DT
= V O(max) -
D( V O(max) - V O(min») - 0.65
where VO(max) and VO{min) are obtained from Figure 9, and D is the maximum duty cycle.
Predicting the regulator startup or rise time is complicated because it depends on many variables, including:
input voltage, output voltage, filter values, converter topology, and operating frequency. In general, the output
will be in regulation within two time constants of the soft-start circuit. A five-to~ten millisecond time constant
usually works well for low-power converters.
The DTC input can be grounded in applications where achieving a 100% duty cycle is desirable, such as a buck
converter with a very low input-to-output differential voltge. However, grounding DTC prevents the
inplementation of soft start, and the output voltage overshoot at power-on is likely to be very large. A better
arrangement is to omit ROT1 (see Figure 4) and choose ROT2 = 47 kil. This configuration ensures that the duty
cycle can reach 100% and still allows the designer to implement soft start using CSS.
,-_.---=-=16'-1 REF
Css
RDT1
TL1454
._-._----1 DTC
'-------'
Figure 4. Dead-Time Control and Soft Start
PWM comparator
Each of the PWM comparators has dual inverting inputs. One inverting input is connected to the output of the
error amplifier; the other inverting input is connected to the DTC terminal. Under normal operating conditions,
when either the error-amplifier output or the dead-time control voltage is higher than that for the PWMtriangle
wave, the output stage is set inactive (OUT1 low and OUT2 high), turning the external power stage off.
undervoltage-Iockout (UVLO) protection
The undervoltage-Iockout circuit turns the output circuit off and resets the SCP latch whenever the supply .
voltage drops too low (to approximately 2.9 V) for proper operation. A hysteresis voltage of 200 mV eliminates
false triggering on noise and chattering.
short-circuit protection (SCP)
The TL1454 SCP function prevents damage to the power switches when the converter output is shorted to
ground. In normal operation, SCP comparator 1 clamps SCP to approximately 185 mY. WhlJn one of the
converter outputs is shorted, the error amplifier output (COMP) will be driven below 1 V to maximize duty cycle
and force the converter output back up. When the error amplifier output drops below 1 V, SCP comparator 1
releases SCP, and capacitor, CSCPo which is connected between SCP and GND, begins charging. If the
error-amplifier output rises above 1 V before Cscp is charged to 1 V, SCP comparator 1 discharges Cscp and
normal operation resumes. If CSCP reaches 1 V, SCP comparator 2 turns on and sets the SCP latch, which turns
off the output drives and resets the soft-start circuit. The latch remains set until the supply voltage is lowered
to 2 V or leSS, or CSCP is discharged externally.
~TEXAS
4-106
INSTRUMENTS
POST OFFICE BOX &55303 • DALlAS, TEXAS 75265
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A-APRIL 1995 - REVISED OCTOBER 1995
short-circuit protection (SCP) (continued)
The SCP time-out period must be greater than the converter start-up time or the converter will not start. Because
high-value capacitor tolerances tend to be ±20% or more and IC resistor tolerances are loose as well, it is best
to choose an SCP time-out period ten-to-fifteen times greater than the converter startup time. The value of Cscp
may be determined using Figure 6, or it can be calculated using:
TSCp
CSCP = 80.3
where CSCP is in JlF and TSCP is the time-out period in ms.
output stage
The output stage of the TL1454 is a totem-pole output with a maximum source/sink current rating of 40 mA and
a voltage rating of 20 V. The output is controlled by a complementary output AND gate and is turned on (sourcing
current for OUT1 , sinking current for OUT2) when all the following conditions are met: 1) the oscillator triangle
wave voltage is higher than both the DTC voltage and the error-amplifier output voltage, 2) the
undervoltage-Iockout circuit is inactive, and 3) the short-circuit protection circuit is inactive.
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-107 .
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 23 V
Error amplifier input voltage: IN1+, IN1-, IN2+, IN2- .......-: . .. . . . . . . . . . .. . . .. . . . . . . . . .. . . . . .. 23 V
Output voltage: OUT1, OUT2 ............................................................... 20 V
Continuous output current: OUT1, OUT2 ................................................. ±200 mA
Peak output current: OUT1 ,OUT2 ........................................... ' ................ , 1 A
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix .................................... -20°C to 85°C
I suffix ..................................... -40°C to 85°C
Storage temperature range, Tstg .................................. .'............... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated condnions for extended periods may affect device reliability.
NOTE 1: All voltage values are wnh respect to network GND.
DISSIPATION RATING TABLE
PACKAGE
TA:<>25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
494mW
D
950mW
7.6mW/"C
608mW
N
1250mW
10.0mW/oC
800mW
650mW
PW
500mW
4.0mW/oC
320mW
260mW
recommended operating conditions
Supply voltage, VCC
Error amplifier common-mode input voltage
MIN
MAX
3.6
20
V
-0.2
1.45
V
Output voltage, Vo
20
UNIT
V
Output current, 10
±40
rnA
COMP source current
-45
COMP sink current
100
I1A
I1A
1
rnA
Reference output current
Timing capacitor, CT
Timing resistor, RT
Oscillator frequency
Operating free-air temperature, TA
10
4000
pF
5.1
100
kn
kHz
50
2000
LTL1454C
-20
85
ITLI4541
-40
85
~TEXAS
4-108
kn
100
COMP dc load resistance
INSTRUMENTS
POST OFFICE BOX 6ss303 • DALLAS, TEXAS 75265
°C
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A ,...APRIL 1995 - REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, VCC = 6 V,
fosc = 500 kHz (unless otherwise noted)
reference
PARAMETER
Vref
TEST CONDITIONS
10=1 rnA,
Output voltage, REF
Input regulation
VOC =3.6 Vto 20 V,
Output regulation
10 = 0.1 rnA to 1 rnA
Short-circuit output current
TYP
1.23
1.25
1.2
10=1 rnA
Output voltage change with temperature
lOS
TA = 25°C
TL1454
MIN
10=1 rnA
MAX
1.28
1.31
V
2
6
mV
1
7.5
mV
TA = TA(min) to 25°C,
10=1 rnA
-12.5
-1.25
12.5
TA = 25°C to 85°C,
10=1 rnA
-12.5
-2.5
12.5
mV
rnA
30
Vref=OV
UNIT
undervoltage lockout (UVLO)
PARAMETER
TEST CONDITIONS
VIT+
Positive-going threshold voltage
VIT-
Negative-going threshold voltage
Vhys
Hysteresis, VIT + - VIT _
TL1454
MIN
TYP
MAX
2.9
TA = 25°C
100
UNIT
V
2.7
V
200
mV
short-circuit protection (SCP)
PARAMETER
TEST CONDITIONS
VIT
Input threshold voltage
Vstbvt
Standby voltage
VI (latched)
Latched-mode input voltage
VIT(COMP)
Comparator threshold vOltage
COMP1, COMP2
Input source current
TA=25°C,
.
TA=25°C
.
No pullup
TL1454
MIN
MAX
0.95
1
1.05
V
140
185
230
mV
60
120
mV
1
VO(SCP)=0
UNIT
TYP
-5
-15
V
-20
I1A
t ThiS symbol IS not presently listed within EIA! JEDEC standards for semiconductor symbology.
oscillator
PARAMETER
fosc
Frequency
TEST CONDITIONS
CT':'120pF,
RT=10kQ
Standard deviation of frequency
Frequency change with voltage
Frequency change with temperature
VCC = 3.6 V to 20 V,
TA= 25°C
TA = TA(min) to 25°C
TA = 25°C to 85°C
TL1454
MIN
TYP
MAX
UNIT
500
kHz
50
kHz
kHz
5
-2
±20
-10
±20
kHz
Maximum ramp voltage
1.8
V
Minimum ramp voltage
1.1
V
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-109
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A - APRIL 1995 - REVISED OCTOBER 1995
electrical characteristics over recommended operating free-air temperature range, VCC
fosc = 500 kHz (unless otherwise noted) (continued)
=6 V,
dead-time control (OTC)
PARAMETER
TEST CONDITIONS
Duty cycle = 0%
Input threshold voltage
VIT
TL1454
MIN
Duty cycle = 100%
VICIatchedl
Latched-mode input voltagl!
liB
Common-mode input bias current
DTC1, IN1+ = 1.2 V
Latched-mode (source) current
TA= 25°C
TYP
MAX
1
1.1
1.2
0.4
0.5
0.6
UNIT
V
V
1.2
4
-100
ItA
ItA
error-amplifier
PARAMETER
TEST CONDITIONS
VIO
Input offset voltage
110
Input offset current
liB
Input bias current
VICR
Input voltage range
VCC =3.6 Vt020V
AV
Open-loop voltage gain
RFB=200kQ
CMRR
VO=1.25V,
TL1454
MIN
TYP
VIC = 1.25 V
-160
MAX
UNIT
6
mV
100
nA
-500
nA
-0.2 to 1.45
V
70
80
dB
3
MHz
Common-mode rejection ratio
60
80
VOM(maxl
Positive output voltage swing
2.3
2.43
VOM(min)
Negative output voltage swing
Unity-gain bandwidth
-
0.63
dB
0.8
V
10+
Output sink current
VID=-O.l V,
VO= 1.20 V
0.1
0.5
mA
10-
Output source current
VID=O.l V,
VO=l.80V
-45
-70
ItA
output
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
try
Output voltage rise time
tlv
Output voltage fall time
TEST CONDITIONS
TL1454
MIN
TYP
10=-8mA
VCC-2
4.5
10 =-40 mA
VCC-2
4.4
MAX
V
10=8mA
0.1
0.4
10=40mA
1.8
2.5
CL = 2000 pF,
220
TA = 25°C
UNIT
V
ns
220
supply current
PARAMETER
ICC(stdby)
ICC(average)
Standby supply current
Average supply current
TEST CONDITIONS
RTopen,
CT= 1.5 V,
Vo (COMP1, COMP2) '= 1.25 V,
RT= 10 kQ,
CT= 120pF,
Outputs open
No load
50% duty cycle,
~TEXAS
4-110
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TL1454
MIN
UNIT
TYP
MAX
3.1
6
mA
3.5
7
mA
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A - APRIL 1995 - REVISED OCTOBER 1995
electrical characteristics, VCC = 6 V, fosc =500 kHz, TA = 25°C (unless otherwise noted)
reference
PARAMETER
Vref
TEST CONDITIONS
Output voltage. REF
10= 1 rnA.
Input regulation
Vee = 3.6 V to 20 V.
Output regulation
Short-circuit output current
TYP
MAX
UNIT
V
1.25
10=1 rnA
'0=0.1 rnA to 1 rnA
Output voltage change with temperature
lOS
TL1454Y
MIN
2
mV
1
mV
10=1 rnA
-1.25
10=1 rnA
-2.5
Vref=OV
30
mV
rnA
undervoltage lockout (UVLO)
PARAMETER
TEST CONDITIONS
TL1454Y
MIN
TYP
MAX
UNIT
V
VIT+
Positive-going threshold voltage
2.9
V,r-
Negative-going threshold voltage
2.7
V
Vhys
Hysteresis. Vir + - Vir _
200
mV
short-circuit protection (SCP)
PARAMETER
TEST CONDITIONS
V,T
Input threshold voltage
Vstbvt
Standby voltage
V, (latched)
Latched-mode input voltage
V'T(COMP)
Comparator threshold voltage
COMP1. COMP2
Input source current
VO(SCP)=0
.
TL1454Y
MIN
TYP
MAX
1
.
Nopullup
UNIT
V
185
mV
60
mV
1
V
~
-15
t This sYmbol IS not presently hsted within EIAI JEDEC standards for semICOnductor symbology.
oscillator
PARAMETER
fose
Frequency
TEST CONDITIONS
CT= 120 pF.
RT= 10kO
Standard deviation of frequency
Frequency change with voltage
Vee = 3.6 Vto 20 V
TL1454Y
MIN
TYP
MAX
UNIT
500
kHz
50
kHz
5
kHz
-2
Frequency change with temperature
-10
kHz
Maximum ramp voltage
1.8
V
Minimum ramp voltage
1.1
V
~TEXAS·
. INSTRUMJ;:NTS
!'OST OFFice ·BOX 655303 • DAlLAS. TEXAS.75265
4-111
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION(PWM) CONTROL CIRCUITS
SLVS086A-APRIL 1995 - REVISED OCTOBER 1995.
=
=
=
electrical characteristics, Vcc 6 V, 'ose 500kHz, TA 25°C (unless otherwise noted) (continued)
. dead-time control (DTC)
PARAMETER
TEST CONDITIONS
VIT
Input threshold voltage
VI(latched)
Latched-mode input voltage
TL1454Y
MIN
.TYP
Duty cycle = 0%
1.1
Duty cycle = 100%
0.5
Latched-mode (source) current
MAX
UNIT
V
1.2
V
-100
IIA
error-ampllfler
PARAMETER
TEST CONDITIONS
liB
Input bias current
VO=1.25V,
AV
Open-loop voltage galn
RFB =200 kn
TL1454Y
MIN
VIC=1.25V
Unity-galn bandwidth
TYP
nA
80
dB
3
Common-mode rejection ratio
80
VOM(max)
Positlve output voltage swing
2.43
VOMlminl
Negative output voltage swing
0.63
10+
Output sin" current
Output source current
,
UNIT
-160
CMRR
10-
MAX
MHz
dB
V
VID=-0.1 V,
VO=·1.20V
0.5
mA
VID=0.1 V,
VO=1.80V
-70
IIA
output
PARAMETER
VOH
High-level output voltage
VOL
Low-level output voltage
Irv
Output voltage rise time
ttv
Output voltage fall time
TEST CONDITIONS
TL1454Y
MIN
TYP
10=-BmA
4.5
10=-40mA
4.4
10=BmA
0.1
10=40mA
1.B
MAX
V
V
220
CL=2000pF
UNrr
ns
220
supply current
PARAMETER
TEST CONDITIONS
ICC(Stdby)
Standby supply current
ATopen,
CT.d.5V,
Vo (COMP1, COMP2) = 1.25 V,
ICC(average)
Average supply current
CT=120pF,
RT=10kn,
Outputs open
No load
50% duty cycle,
~TEXAS
4-112
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TL1454Y
MIN
TYP
MAX
UNIT
3.1
mA
3.5
mA
TL1454, TL1454V
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
osc~~:;:;;ty-A/\A1\YT-A~
DTC
SCP Reference
/\ /\tyA /\ /\ /\
-~I \ V;~VVVV-V--'¢~
r'""
I
1.8V
\cVV\ 1.2V
"10::::= _» <' 1 V
H
Dead-11me 100%
LZ._ _ L
OUTl
.......- - H
OUT2
SCP Comparator
Output
Dead-11me 100%
L
I
-T1- - -
I
I
I
I I
I
I
-I----I-+----....._-----------------L--I--I
I I ",,I
I ",.-
H
L
2.5 V
i---~----------------------t?f===~~
SCP
VCC
I
I
I I
I I
(tpe)..j.-.!
Al!lo~~~~~ __________________________
OV
Figure 5. Timing Diagram
TYPICAL CHARACTERISTICS
OSCILLATOR PERIOD
OSCILLATOR FREQUENCY
vs
vs
TIMING RESISTANCE
TIMING CAPACITANCE
10M
VCC=6V
TA = 25°C
:S!
~
1M
I
.....
Cy= 300 pF
lOOk
j
..~
I
IIJ
::I.
I
Cy=120pF
I
1
VCC ... 6V
RT=5.1 kg
TA = 25°C
Cy=10pF
............
"8
i
I
....... ....
c
Cy= 1000 pF
~
ci.r=39oo~
10 k
J
10 1
j
10 0
0
-
~
I
10-1
1k
1k
10k
AT -11mlng Resistance -
lOOk
g
10 1
10 2
10 3
Cy -11mlng Capacitance - pF
Figure 7
Figure 6
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-113
TL1454,TL1454Y
DUAL·CHANNEL PULSE.WIDTH·MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
PWM TRIANGLE WAVEFORM AMPLITUDE
va
va
FREE-AIR TEMPERATURE
TIMING CAPACITANCE
530
N
:Iii
2
VCC=6V
RT=10kn
CT=120pF
1.9
j
~
510
J
1.7
1.6
~
500
~
I
()
i
:=
!E
r;
1
1.8
I
520
I
C
III
::I
>
>
-
~
.!!
m
~
490
f
480
o
-SO
100
50
r-.....
111111 I I
VO(max) ,
1.5
1.4
1.3
1.2
1.1
VO(min)
1
0.9
V"
0.8
VCC=6V
RT=5.1kn
0.6 TA=25~~,
0.5
10 0
0.7
TA - Free-Air Temperature _·C
Timing Capecitance - pF
Figure 9
Figure 8
DTC INPUT THRESHOLD VOLTAGE
SCP TIME-OUT PERIOD
va
va
FREE~AIR TEMPERATURE
1.4
>
SCP CAPACITANCE
2
VCC=6V
RT=5.1kn
CT=1000pF
1.2
I
t
Vrr (00/0 Duty Cycie)
~
-
I
I
l
~
~
:;
a.
.5
0.8
~
0.6
,/
"1.5
i
.c
!
I
VCC=6V
TA=25·C
/
II.
~
I
~
VIT (100% Duty Cycle)
0.4
-SO
o
50
TA - Free-Air Temperature _·C ,
100
0.5
V
o
o
Figure 10
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
/
~
5
10
15
SCP Capecltance -IlF
Figure 11
~TEXAS
4-114
V
/
/
20
25
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A - APRIL 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
SCP LATCH RESET VOLTAGE
SCP THRESHOLD VOLTAGE
1.04
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
-
3.5
-
VCC=6V
I
VCC=6V
----
>
I
3
t
~
)
3
2.5
.c
a.
r--
-
.......
2
~
I
I
1.5
">
0.94
-50
o
50
TA - Free-Air Temperature - °c
1
-50
100
-25
o
25
50
75
TA - Free-Air Temperature - °C
Figure 12
Figure 13
UVLO THRESHOLD VOLTAGE
3.5
3
2.5
DUTY CYCLE
vs
vs
FREE-AIR TEMPERATURE
DTC INPUT VOLTAGE
120
I
~
~ :::::::
100
:::::::~
........... "'
I
60
l:
2
::I
Q
1.5
1
\
~
!
I
VCC=6V
CT= 120 pF
RT= 10 kU
TA = 25°C
1\
80
~
-so
100
40
~
\
20
-25
o
25
50
75
TA - Free-Air Temperature - °C
100
o
o
\
0.25
Figure 14
0.5
0.75
1.25
1.5
VI(DTC) - DTC Input Vohage - V
Figure 15
.~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-115 .
TL1454, TL1454Y
DUAL-CHANNEL PULSE·WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
ERROR-AMPLIFIER MAXIMUM OUTPUT VOLTAGE
>
I
;
~
I
1
va
SOURCE CURRENT
SINK CURRENT
>
2.5
VCC=6V
VIO=0.1 V
TA = 25°C
"\
2
J
~
VCC=6V
VIO = 0.1 V
2
i
o
1.5
E
:::I
E
1.5
~~
:5
:E
I
w
2.5
I
:i
f
ERROR-AMPLIFIER MINIMUM OUTPUT VOLTAGE
va
./
~
is.
i
0.5
I
/'
0.5
I
I
o
o
40
120
80
:E
~
0
Figure 16
Figure 17
ERROR AMPLIFIER MAXIMUM
PEAK-TO-PEAK OUTPUT VOLTAGE SWING
va
VCC=6V
TA=25°C
f
0.8
~
2
t
0.7
1.5
I
0.6
EI
:::I ell
I"ell
..
va
FREE-AIR TEMPERATURE
I
IL>
EC
'iC!
ERROR·AMPLIFIER MINIMUM OUTPUT
VOLTAGE SWING
>
FREQUENCY
2.5
1.5
0.5
Sink Current - mA
0
Source Current - jiA
!1
~
E
VCC=6V
No Load
Amplifier 1
-----...
~ ...........
~
:5:IE
I:!l!
is.~
.......
"'- i'..
~1
""5
~o
~
0.5
it'
i\
IL
;ff
0
1k
10k
100 k
1M
10M
100M
f -Frequency - Hz
Figure 18
Figure 19
~TEXAS
4-116
o
25
50
75
TA - Free-Air Temperature - °C
-25
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
100
TL1454, TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER OPEN-LOOP GAIN AND PHASE SHIFT
va
FREQUENCY
80 I-
r-..
III
I
c
80
'ii
"~
\
40
!.
~
Phase Shift
0
.!
:t:
a.
TA=25°C
Gain
Do
/:.
II~~C~~V"
\
'a
~
20
~
E
c
~
i
0
-20
100
1k
10k
100k
f - Frequency - Hz
1M
180°
10M
Figure 20
ERROR-AMPLIFIER POSITIVE OUTPUT
VOLTAGE SWING
>
I
gt
'!i
II)
vs
FREE-AIR TEMPERATURE
2.5
VCC=6V
No Load
Ampllfter1
t
~
I
2.45
~
i
i
IE
-
-......... ~
~
I-
2.4
c
~
.%i
I
~ 2.35
-SO
~
25
SO
75
o
-25
TA - Free-Air Temperature - °C
100
Figure 21
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
4-117
TL1454, TL1454Y
.
. .
DUAL-CHANNEL PULSE-WIDT~-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A- APRIL 1995 - REVISED OCTOBER 1995
tyPICAL CHARACTERISTICS .
HIGH-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
vii
va
FREE~AIR TEMPERATURE
OUTPUT CURRENT
5~5
6
VCC=6V
VCC=6V
TA=25DC
>
I
t
~
io
1
>
I
5
-
i\
t-- -....
4
••6,..
1
.'1!
:c
I
:c
~
CII
:c
~
4.5
,
3
:i:
I
t
~
'5
a.
2
1
3.5
3.
o
20
40
60
10 - Output Current - mA
80
-SO
-25
25
75
0
50
TA - Free-Air Temperature - DC
Figure 23
Figure 22
LOW-LEVEL OUTPUT VOLTAGE
LOW-LEVEL OUTPUT VOLTAGE
VB
VB
OUTPUT CURRENT
FREE-AIR TEMPERATURE
250
6
VCC=6V
TA=25DC
r
~
"CC=6V
10=8mA
--
--
J
1
~
o
V
20
40
60
10L - Low-Level Output Current - mA
Figure 24
4-118
100
60
o
-50
o
~
..-
25
75
-25
50
TA - Free-Air Temperature - DC
Figure 25
100
TL1454, TL1454V
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A - APRIL 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
6
3
VCC=6V
lo=40mA
>
I
&
ll!
I
2
~
:::I
...........
U
............
0
~
5 -
C
~
'Sa.
'S
E
.............
1.5
aa.
III
CD
CD
............
~
4
:::I
.............
I!!
CD
........
I
I
c(
2.5
I
VCC=6V
RT=10kO
CT=I.5V
COMP1, COMP2 = 1.25 V
No Load
-r--
3
~
-----
I---...
I
I
§
....I
~
2
E
0.5
-50
-25
o
25
50
75
TA - Free-Air Temperature - °C
1
-50
100
o
-25
25
50
75
100
TA - Free-Air Temperature - °C
Figure 26
Figure 27
STANDBY SUPPLY CURRENT
STANDBY SUPPLY CURRENT
vs
vs
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
6
6
VCC=6V
RT = Open
CT=I.5V
COMP1, COMP2 = 1.25 V
No Load
TA=25°C
I
5
c(
E
I
5
C
~
:::I
U
4
aa.
4
:::I
III
~
c
3
"
3
~
VCC=6V
CT=I.5V
RT=Open
COMP1, COMP2 = 1.25 V
No Load
---
r----
I
~
2
--~
2
U
E
1
o
1
5
10
15
20
25
-so
VCC - Supply Voltage - V
o
50
100
TA - Free-Air Temperature - °C
Figure 28
Figure 29
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-119
TL1454,TL1454Y
DUAL-CHANNEL PULSE-WIDTH-MODULATION (PWM) CONTROL CIRCUITS
SLVS086A-APRIL 1995- REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS,
REFERENCE VOLTAGE
vs
SUPPLY VOLTAGE
REFERENCE VOLTAGE
vs
SUPPLY "O.LTAGE
1.5
1.26 ...----...-I---.--"""T'"--.........----.
-~
TA=25°e
10=1mA
TA=25°e
I
>
I
i
>
J
I
~
1.25
~
8
J
I
I
I
0.5
1.24
J
2!
)i
o
o
5
25
10
15
20
Vee - Supply Voltage - V
1.23 L..-_--L_ _...L._ _.l..-_--...l._ _--1
10
15
20
25
5
o
Vee - Supply Voltage - V
Figure 31
Figure 30
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
1.26
Vee=6V
10=-1 mA
>
I
III
I
1.25
~
~
2l
c
I!!
ila:
I
--
r--. r-
1.24
!
>
1.23
-50
-25
50
75
o
25
TA - Free-Air Temperature - °e
Figure 32
~TEXAS
INSTRUMENTS
4-120
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100
TL5001, TL5001 V
PULSE·WIDTH·MODULATION CONTROL CIRCUITS
SLVS084C - APRIL 1994 - REVISED SEPTEMBER 1995
•
•
•
•
•
•
Os
o OR P PACKAGE
Complete PWM Power Control
3.6-V to 40-V Operation
Internal Undervoltage-Lockout Circuit
Internal Short-Circuit Protection
Oscillator Frequency ... 40 kHz to 400 kHz
Variable Dead Time Provides Control Over
Total Range
(TOP VIEW)
OUT
VCC
COMP
FB
2
7
3
4
6
5
GND
RT
DTC
SCP
description
The TLS001 incorporates on a single monolithic chip all the functions required for a pulse-width-modulation
(PWM) control circuit. DeSigned primarily for power-supply control, the TLS001 contains an error amplifier, a
regulator, an oscillator, a PWM comparator with a dead-time-control input, undervoltage lockout (UVLO),
short-circuit protection (SCP), and an open-collector output transistor.
The error-amplifier common-mode voltage ranges from 0 V to 1.S V. The noninverting input of the error amplifier
is connected to a 1-V reference. Dead-time control (DTC) can be set to provide 0% to 100% dead time by
connecting an external resistor between DTC and GND. The oscillator frequency is set by terminating RT with
an external resistor to GND. During low V CC conditions, the UVLO circuit turns the output off until VCC recovers
to its normal operating range.
The TLS001 C is characterized for operation from -20°C to 8SoC. The TLS0011 is characterized for operation
from -40°C to 8SoC.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CHIP FORM
(V)
TL5001Y
-20°C to S5°C
TL5001CD
TL5001CP
-40°C to S5°C
TL50011D
TL50011P
-
The D package IS aVailable taped and reeled. Add the suffiX R to the deVice type
(e.g., TL5001CDR). Chip forms are tested at TA = 25°C.
schematic for typical application
VI --~---.-------.---.
+
T
2
VCC
5 SCP
Vo
COMP
3
TL5001
6
7
DTC
FB
4
RT
GND
8
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-121
TLSOO1, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
~LVS084C -APRIL 1994 - REVISED SEPTEMBER 1995
functional block diagram
Vee
2
RT
OTC
OUT
7
6
1
lOT
~----~~~::~~--~--~-+~~
FB
COMP~------'---------+-----~++~--------~
SCp~5~---------------+------__~~~
8
GNO
4-122
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
TL5001, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084C -APRIL 1994 - REVISED S.EPTEMBER 1995
TL5001 V chip information
This chip, when properly assembled, displays characteristics similar to the TL5001 C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
OUT
Vec
COMP
FB
(1)
(8)
(2)
(7)
TL5001Y
(3)
(6)
(4)
(5)
GND
RT
DTC
SCP
CHIP THICKNESS:
11 MILS TYPICAL
BONDING PADS:
7X7 MILS MINIMUM
TJ max = 1500 e
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFF'CE BOX 655303 • DALLAS, TEXAS 75265
4-123
TL5001, TL5001Y
PULSE-WIDTH-MODULATIONCONTAOL CIRCUITS
SLVSOl14C -APRIL 1994 - REVISED SEPTEMBER 1995
detailed description
voltage reference
A 2:5-V regulator operating from VCC is used to power the internal circuitry of the TL5001 and as a reference
for the error amplifier and SCPcircuits. A resistive divider provides a 1-V reference for the error .amplifier
noninverting input. The 1-V reference remains within 5% of nominal over the operating temperature range.
error amplifier
The error amplifier compares a sample of the dc-to-dc converter output voltage to the 1-V reference and
generates an error signal for the PWM comparator. The dc-to-dc converter output voltage is set by selecting
the error-amplifier gain (see Figure.1), using the following expression:
Va = (1 + R1/R2) (1 V)
r-~~-~-----~-----'
1
31 COMP
Compensation
Network
R1
1
I
I
I
TL5IJ!)
I
--=+=-=-----I
VI(FB) -Wv---........
ToPWM
Comparator I
R2
I
I
I
I
I
~----------------~
Figure 1. Error-Amplifier Gain Setting
error amplifier (continued)
The error-amplifier output is brought out.as COMP for use in compensating the dc-to-dc converter control loop
for stability. Because the amplifier can only source 45 !lA, the total dc load resistance should be 100 kil or more.
os.clllator/PWM
The oscillator frequency (fosC> can be set between 40 kHz and 400 kHz by connecting a resistor between RT
and GND. Acceptable resistor values range from 15 kil to 250 kil. The oscillator frequency can be determined
by using the graph shown in Figure 5.
The oscillator output is a triangular wave with a minimum value of approximately 0.7 V and a maximum value
of approximately 1.3 V. The PWM comparator compares the error-amplifier output voltage and the DTC input
voltage to the triangular wave and turns the output transistor off whenever the triangular wave is greater than
the lesser of the two inputs.
dead-time control (DTC)
DTC provides a means of limiting the output-switch duty cycle to a value less than 100%, which is critical for
boost and flyback converters. A current source generates a reference current (lOT) at DTC that is nominally
equal to the current at the oscillator timing terminal, RT. Connecting a resistor between DTC and GND generates
a dead-time reference voltage (VOT), which the PWM/DTC comparator compares to the oscillator triangle wave
as described in the previous section. Nominally, the maximum duty cycle is 0% when VOT is 0.7 Vor less and
100% when VOT is 1.3 V or greater. Because the triangle wave amplitude is a function of frequency and the
source impedance of RT is relatively high (12500), choosing ROT for a specific maximum duty cycle, D, is
accomplished using the following equation and the voltage limits for the frequency in question as found in
Figure 11 (Voscmax and Voscmin are the maximum and minimum oscillator levels):
~TEXAS
4-124
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TL5001, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084C -APRIL 1994 - REVISED SEPTEMBER 1995
where
ROT and Rt are in ohms, D in decimal
Soft start can be implemented by paralleling the DTC resistor with a capacitor (COT) as shown in Figure 2. During
soft start, the voltage at DTC is derived by the following equation:
V DT = IDTRDT ( 1-e (-VR DTC DT))
.---411--....6.... DTC
50
1.6
~
o
i
25
Figure 6
REFERENCE OUTPUT VOLTAGE
I
o
TA - Ambient Temperature - °C
Figure 5
>
'"
"
Rt - Timing Resistance -
2
~
0.4
i
0.2
!
I
o
o
~
2
3
4
7
8
5
6
VCC - Power-Supply Voltage - V
9
10
-
0.6 ,,",~+--I---+---l---+---I
-0.8 L...._.....I..._ _'--_...J...._--'_ _...J...._--'
100
-50
-25
0
25
50
75
TA - Ambient Temperature - °C
Figure 7
Figure 8
~TEXAS·
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-133
TL5001, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084C - APRIL 1994 - REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
vs
POWER·SUPPLY VOLTAGE
2
AVERAGE SUPPLY CURRENT
vs
AMBIENT TEMPERATURE
1.3
~
,I
Rt=100kn
TA=25°C
C
E
'"
1.5
I
-........
1.2
..........
E
I
C
C
~::I
~
::I
0
1.1
0
~
0.
............
~
::I
I/)
I/)
CD
&
1:11
I!
~I
I!
0.9
0
0.8
~I
0.5
0
9
o
o
.9
J
o
10
20
-50
40
30
-25
Figure 9
&
1.5
~
>
I
...-~i-"
~
is.
E
1.2
~
0.9
~
.!!
1:11
c
~
~
::&
f
~
2
i
1.5
0
~
--
is.
E
c
~
g
W
I
0.3
0.5
~
o
10 k
lOOk
1M
fose - Oscillator Frequency - Hz
10M
o
o
0.2
--
V
I
I
J
0.4
10 - Output (Sink) Current - mA
Figure 11
Figure 12
~T~S··
4-134
100
r-
~
Voscmin (zero duty cycle)
0.6
VCC';'SV
VI(FB) = 1.2 V
2.5 TA=25°C
&
Voscmax (100% duty cycle)
CD
'tI
75
3
VCC=6V
TA=25°C
~
50
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
OUTPUT (SINK) CURRENT
1.8
I
25
Figure 10
PWM TRIANGLE WAVE AMPLITUDE VOLTAGE
vs
OSCILLATOR FREQUENCY
>
o
-
TA .,. Ambient Temperature - °c
VCC - Powe....Supply Voltage - V
c
"'~
~
0.
::I
1
1
VCC=6V
Rt=l00kO
DT Resistance = 100 kQ -
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
O.S
TL5001, TL5001 V
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084C - APRIL 1994 - REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
ERROR AMPLIFIER OUTPUT VOLTAGE
ERROR AMPLIFIER OUTPUT VOLTAGE
vs
vs
OUTPUT (SOURCE) CURRENT
AMBIENT TEMPERATURE
2.46
3
>
..
2.5
~
'5
2
I
VCC=6V
VI(FB) = 0.8 V
TA=25°C
>
::
!
0
.
..
2.45
~
'5
2.44
I
...........
DI
1.5
i
"
VCC=6V
VI(FB) = 0.8 V
No Load
- r-....
So
~
0
2.43
~
~
'a
'a
"'I:
"'I:
E
g
w
I
..g
0.5
-?
o
o
E
2.42
w
I
2.41
-?
\
20
40
,60
80
100
10 - Output (Source) Current -/lA
2.40
-50
120
ERROR AMPLIFIER CLOSED-LOOP GAIN AND
PHASE SHIFT
vs
vs
AMBIENT TEMPERATURE
OSCILLATOR FREQUENCY
240
.
I
220
40
VCC=6V
VI(FB) = 1.2 V
No Load
III
"0
I
c
DI
:ll!
~
'5
200
:;;
180
!
0
./
:e
'a
E
.g
"'I:
160
W
I
-?
140
L
V
V
/
·iii
~
............
30
V~C~~~I
""-
r.....
c:J
Q.
0
0
V
...
..J
-c
.!2
..
~
Co)
'a
E
20
0
:e.c
III
r-...AV
\
-270°
-20
10 k
100 k
.31
.c
\
D..
I
\
i\ ",
g
w -10
I
100
I\~
"
10
"'I:
-25
o
25
50
75
TA - Ambient Temperature - °C
TA=25°C
1\
>
"'I:
120
-50
100
Figure 14
ERROR AMPLIFIER OUTPUT VOLTAGE
E
.....
-25
o
25
75
50
TA - Ambient Temperature - °c
Figure 13
>
'""',""
1M
-300° -e-
-360°
10M
fosc - Oscillator Frequency - Hz
Figure 15
Figure 16
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-135
TL5001, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SlVS084C -APRIL 1994 - REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SCP TIME-OUT PERIOD
OUTPUT DUTVCYCLE
vs
vs
SCP CAPACITANCE
DTCVOLTAGE
12
120
VCC=6V
At= 100kD
TA=25°C
100
/I.
I
80
i
60
0
40
!
1
I
/
o
/
I
'8
'C
t.
8
6
d.
1=
E
II.
~
/
j
4
I
II.
CJ
.!!I
0.5
1.5
2
/
o
o
2
vs
OUTPUT (SINK) CURRENT
2~----~----~------~----~
/
~
CJ
~I
-20
j
-10
VCC=6V
TA=25°C
,/
-50
-40
/
o
o
/
/
>
I
t
V
1.5 f-------+----+---::::.-F-------f
~
I
i
I
I
W
~
OL---__
-10
-20
-30
-40
-50
-60
o
10 - RT Oulpul Current - jiA
~
____
~
______
~
____
10
15
10 - Oulpul (Sink) Current - mA
Figure 19
5
Figure 20
~TEXAS
4-136
120
OUTPUT SATURATION VOLTAGE
RT OUTPUT CURRENT
I
-30
100
vs
DT Voltage = 1.3 V
TA=25°C
0
80
Figure 18
-60
i
60
CSCP - SCP capacitance - nF
DTC OUTPUT CURRENT
~
V
40
20
Figure 17
::L
V
V
DTC Voltage - V
C
/"
tI'
/
'S
0
/
20
o
/
10
~
/
VCC=6V
Rt=100kD
DT Resistance = 200 kD
TA=25°C
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
~
20
TL5001, TL5001Y
PULSE-WIDTH-MODULATION CONTROL CIRCUITS
SLVS084C -APRIL 1994 - REVISED SEPTEMBER 1995
APPLICATION INFORMATION
,oo~t
R1..,
470Q
10V
~
GND
-=-
Q1
TPS1101
L1
20~H
1
~
\1
"~CR1
~ .. MBRS140T3
C3
0.1 ~F
II
2
5
SCP
10V
1
-
Vo
R2
56kQ
3
COMP
U1
TL5001
II
6
GND
J-
C5
\1 0.1 ~F
+
100~F
C2T
VCC
C4
\1 1 ~F
11+
3.3 V
*C6
0.012
R5
7.50kQ
1%
~F
~ R4
DTC
5.1 kQ
R3
43kQ
7
R6
3.24kQ
1%
GND
8
Partial
U1
Q1
LI
C1
C2
CR1
Bill of Materials.
TL5001;
TPS1101
CTX20-10r
23 turns of #28 wire on
Micrometals No. T5D-26B core
TPSD107M010R0100
TPSD107M010R0100
MBRS140T3
NOTES: A.
B.
C.
D.
;::~C7
O. 0047~F
4
FB
RT
R7
2.0
--'--
Texas Instruments
Texas Instruments
Coiltronlcs
AVX
AVX
Motorola
Frequency = 200 kHz
Duty cycle = 90% max
Soft-start time constant (TCl = 5.6 ms
SCP TC = 70 msA
Figure 21. Step-Down Converter
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-137
4-138
TPS67341
FIXED 12-V 12D-mA BOOST-CONVERTER SUPPLY
•
•
•
•
Pin-for-Pln Compatible With MAX734
Programming Voltage for Flash Memory
2.7-V to 11-V Input Operating Range
Output Current of 120 mA or Greater From
3.75-V or Higher Input
•
3-1JA Maximum Supply Current in
Shutdown
Only S External Components Required
High Efficiency .•• 85% Typical (S-V Input,
12D-mA Output)
•
•
•
•
o OR P PACKAGE
{TOP VIEW)
ENDs
REF
2
7
Vee
FB
SS
CaMP
3
6
5
OUT
GND
4
8-Pln SOIC and DIP Packages
-40°C to 85°C Free-Air Operating
Temperature Range
description
The TPS6734 is a fixed 12-V output boost converter capable of delivering 120 rnA from inputs as low as
3.75 V. The device is pin-for-pin compatible with the MAX734 regulator and offers the following advantages:
lower supply current; wider operating input-voltage range, and higher output currents. As shown in Figure 1,
the only external components required are: an inductor, a Schottky rectifier, an output filter capacitor, an input
filter capacitor, and a small capacitor for loop compensation. The entire converter occupies less than 0.7 in2 of
PCB space when implemented with surface-mount components. An enable input is provided to shut the
converter down and reduce the supply current to 3 !lA when 12 V is not needed.
The TPS6734 is a 170-kHz current-mode PWM (pulse-width modulation) controller with an n-channel MOSFET
power switch. Gate drive for the switch is derived from the 12-V output after start-up to minimize the die area
needed to realize the 0.7-0 MOSFET and improve efficiency at input voltages below 5 V. Soft start is
accomplished with the addition of one small capacitor. A 1.22-V reference (pin 2) is brought out for external use.
High efficiency at low supply voltages and low supply current in shutdown make the TPS6734 particularly
attractive for flash 'memory programming supplies, PCMCIA cards, and operational amplifiers in
battery-powered equipment. The TPS6734 is available in 8-pin DIP and SOIC packages and operates over a
free-air temperature range of -40°C to 85°C.
VI
3.75 Vto 12 v
TPS6734
EN
ENABLE
2
I
3
4
vcc
FB
REF
ss
OUT
GND
8
7
6
5
33
O.OOlI1F
-=
JLF
Vo
12V, 120 mA
Figure 1. Typical Operating Circuit
~1!,=,I;"":::",,,,:
=,c,n:,,:
_.Wlrnnty. Production processing does not noceosarily Include
testing 01 all parameters.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
4-139
TPS67341
FIXED 12-V 120~mA BOOST-CONVERTER SUPPLY
SLVS127 - AUGUST1995
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
-40°C to 85°C
TPS6734ID
PLASTIC DIP
(P)
TPS6734IP
The D package IS available taped and reeled. Add the suffix R
to the device type (e.g., TPS6734IDR).
TPS6734 chip information
Thermal compression or ultrasonic bonding can be used on the doped-aluminum bonding pad. Chips can be
mounted with conductive epoxy or a gold-silicon preform. Contact factory for die sales.
BONDING PAD ASSIGNMENTS
8
EN
REF
SS
COMP
2
3
7
TPS6734
4
6
5
VCC
FB
OUT
GND
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4X4 MILS MINIMUM
=
TJmax 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS.
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS
4-140
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS67341
FIXED 12-V 12D-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
functional block diagram
VCC
FB
~.-_ _ _ _ _ _~8~ VCC
~7_.-___~______________________________~~-e
r------,
Power Switch
COMP
1
4
1
JI
6
OUT
1
1
1
.J
REF -,,2=--.-_ _~-t
Sense Amplifier
SS
. -_____--'5~ GND
3
Clamp
~'-------<
l .
Overcurrent
Comparator
Terminal Functions
TERMINAL
NAME
DESCRIPTION
NO.
EN
1
Enable. EN :2: 2 V turns on the TPS6734. EN S 0.4 V turns it off and reduces the supply current to 3 ItA max.
REF
2
1.22-V reference voltage output. REF can source 100 ItA for extemalloads.
SS
3
Soft Start. A capacitor between SS and GND brings the output voltage up slowly at power-up.
COMP
4
Compensation connection. A O.OOl-J.lF capacitor between COMP and FB stabilizes the feedback loop.
GND
5
Ground
OUT
6
N-channel MOSFET drain connection
FB
7
Feedback voltage. FB is connected to the converter output for the feedback loop.
VCC
8
Supply voltage input
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-141
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
detailed description
The following descriptions refer to the functional block diagram.
reference
The internaI1.22-V reference is brought out on REF and can source 100 ~ maximum to external loads. A
0.01-IlF to 0.1-IlF decoupling capacitor connected b!3tween REF and GND is recommended to minimize noise
pickup.
oscillator and ramp generator
The oscillator circuit provides a 170-kHz clock, to set the converter operating frequency, and a timing ramp for
slope compensation. The clock waveform is a pulse, a few hundred nanoseconds in duration, that is used to
limit the maximum power-switch duty cycle to 95%. The timing ramp is summed with the current-sense signal
at the input to the current-sense amplifier.
driver latch
The latch, which consists of a seVreset flip-flop and associated logiC, is used to control the state of the power
switch by turning the driver on and off. A high output from the latch turns the switch on; a low output from the
latch turns it off. In normal operation, the flip-flop is set high during the clock pulse, but gating keeps the latch
output low until the clock pulse is over. The latch is reset when the PWM comparator output goes high.
currerit-sense amplifier
The current-sense amplifier has a fixed gain of 6. It amplifies the slope-compensated current-sense voltage (a
summation of the voltage on the ,current-sense resistor and the oscillator ramp) and feeds it to the PWM
comparator.
error amplifier
The error amplifier is a high-gain differential amplifier used to regulate the converter output voltage. The
amplifier generates an error signal, which is fed to the PWM comparator. The error signal is generated when
a sample of the output voltage is compared to the internal reference and the difference is amplified. The output
sample is obtained from a resistive divider connected between FB and GND. FB is externally connected to the
converter output, and the divider output is connected to both the error amplifier input and COMPo A 0.001-IlF
capacitor connected between FB and COMP stabilizes the voltage control loop.
PWM comparator
The PWM comparator resets the drive latch and turns off the power switch whenever the slope-compensated
current-sense signal from the current-sense amplifier exceeds the error signal.
power switch'
The power switch is a 0.7-n n-channel MOSFETwith current-sensing. The drain is connected to OUT and the
current sense is connected to a resistor. The voltage across the resistor is proportional to the current in the
power switch and is tied to the overcurrent comparator and the current-sense amplifier. In normal operation,
the power switch is turned on at the start of each clock cycle and turned off when the PWM comparator resets
the drive latch.
SSclamp
The SS (soft-start) clamp circuit limits the signal level on error-amplifier output during start-up. The voltage on
SS is amplified and used to momentarily override the error-amplifier output until it rises above that output, at
which pOint the error-amplifier takes over. This prevents the input to the PWM comparator from exceeding its
common-mode range (the error-amplifier output too high to be reached by the current ramp) by limiting the
maximum voltage on the error-amplifier output during start-up.
~TEXAS
4-142
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
soft start
Soft start causes the output voltage to increase to the regulation point at a controlled rate of rise. The voltage
on the charging soft-start capacitor gradually raises the clamp on the error-amplifier output voltage, limiting
surge currents at power-up by increasing the current-limit threshold on a cycle-by-cycle basis. Even if SS has
no capacitor installed, some distributed capacitance will always be present. A soft-start cycle is initiated when
either the enable signal (EN) is switched high, or an overcurrent fault condition triggers the discharge of the
soft-start capacitor.
overcurrent comparator
The overcurrent comparator monitors the current in the power switch. The comparator trips and initiates a
soft-start cycle if the power-switch current exceeds 1.5-A peak. On each clock cycle, the power switch turns on
and attempts todeliver current until the overcurrent limits are exceeded.
enable (EN)
A logic low on EN puts the TPS6734 in shutdown mode. In shutdown, the output power switch, voltage
reference, and other functions are shut off, the supply current is reduced to 31lA maximum, and the soft-start
capacitor is discharged through a 1-MQ resistance. The output voltage falls to a diode drop below the input
voltage because of the current path from input to output through the inductor and diode.
DISSIPATION RATING TABLE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
D
725mW
P
1175mW
PACKAGE
TA=70°C
POWER RATING
TA=85°C
POWER RATING
5.8mW/oC
464mW
377mW
9.4mW/OC
752mW
611mW
absolute maximum ratings over operating free-air temperature range {unless otherwise noted)t
Pin voltages: Vee, OUT (see Note 1) ............................................... -0.3 V to 15 V
SS, COMP, EN (see Note 1) ................................... -0.3 V to Vee+ 0.3 V
Peak switch current ....................................................................... 1.5 A
Reference current ........•............................................................ .'. 2.5 mA
Continuous power dissipation ......................................... See Dissipation Rating Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 s ...................................... 260°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network terminal ground.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-143
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVSI27-AUGUST 1995
recommended operating conditions
Supply voltage
MIN
NOM
MAX
2.7
5
12
Compensation capacitor
100
0
Reference capacitor
-40
iJ.A
~F
0.01
Operating free-air temperature, TA
V
~F
0.001
Output current at REF
UNIT
85
'c
electrical characteristics over recommended operating free-air temperature range, Vee =5 V,
IO(LOAD) = 0 mA, EN 5 V, typical values are at TA = 25°C (unless otherwise noted) (refer to circuit
shown in Figure 13)
=
PARAMETER
TEST CONDITIONS
Supply current
MIN
TYP
MAX
1.2
2.5
mA
EN = 0.4 V, entire circuit
3
EN = 0.4 V, into VCC
3
iJ.A
iJ.A
Entire circuit
Operating
Standby
High-level input threshold voltage at EN
2
V
low-level input threshold voltage at EN
0.4
Shutdown input IEiakage current at EN
-1
On resistance at OUT
Current at OUT = 500 rnA
leakage current at OUT
VOS=12V
Reference drift
1
0.7
TA = -40'C to 85°C
Oscillator frequency
iJ.A
o·
1.22
V
6.7
ppm/"C
170
kHz
0
7500
Compensation pin impedance
V
iJ.A
1
Reference voltage
UNITS
performance characteristics over recommended operating free-air temperature range, typical
circuit connected as shown in Figure 13, typical values are at TA = 25°C (unless otherwise noted)
PARAMETER
Output voltage
load current
TEST CONDITIONS
VCC=4.75V,
o rnA < 10(lOAD) < .120 mA
VCC=3.75V
VCC=3.0V,
Figure 11
Line regulation
VCC=5VtoI2V,
10IlOADl = 50 mA
load regulation
10(lOAD) = 0 mA to 120 mA
Efficiency
VCC=5V,
10(lOAD) = 120 mA
~TEXAS
4-144
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN
TYP
MAX
UNITS
11.64
12.12
12.6
V
120
150
150
0.20%
0.0042%
86%
mA
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
TYPICAL CHARACTERISTICS
LOAD TRANSIENT RESPONSE
'E"
I
1:
~
:::J
0
200
150
VI=5V
VO=12V
IL=OmAto 120 mA
100
'1:1
.9
I
50
.::
0
,
>
I
,
12.1
,
J
J
12
11.9
III
~
'S
~
0
I
~
o
2
4
6
8
10 12
t-Tlme-me
14
16
18
Figure 2
LINE TRANSIENT RESPONSE
>
8
,
I
t
I
~
I
6
J
4
J
2
>"
o
,
>
I
12.05
12
11.95
III
~
l5
0
I
~
o
2
4
6
8
10 12
t-Tlme-ms
14
16
18
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
4-145
TPS67341
FIXED 12-V 12D-mA BOOST-CONVERTER SUPPLY
SLVS127.,. AUGUST 1995
TYPICAL CHARACTERISTICS
OSCILLATOR FREQUENCY
vs
SUPPLY VOLTAGE
EN RESPONSE TIME
I
14
I
12
>
200
I
VI=5V
VO=5Vto12V
IL = 120 rnA at 12 V
i
I
I
I
1\ Output
10
f
\voltage
\
I
&
!
~
8
\
6
4
190
I
\
'-
!~
180
1
..
170
~
160
~
-- -
I
I>
u.'8
EN Voltage
150
2
o
o
2
3
4
5
t-Tirne-rnS
-
6
,....-
140
4
3
789
5
Figure 4
. SUPPLY VOLTAGE
18
14
I
C
~:::I
(J
~
a.
a.
:::I
UI
'$
a.
.5
1\
\
oC
,
12
10
I
C
~
:::I
8
'$
a.
'$
0
E
:::I
E
\
6
4
r
2
J
140
120
/~
(J
r\
\
I'-..
f".. \
l
J ,Pica
o
'=
100
80
60
---
/
V
-
i'-.
I
r--
40
20
o
3
3.5
4
4.5
Vee - Supply Voltage - V
Figure 7
Figure 6
)
~TEXAS
4-146
~
~
:E
.9
0.1 0.5 0.9 1.3 1.7 2.1 2.5 2.9 4.5 6.5 8.5
Vee - Supply Voltage - V
)
10
./
160
E
\ . Bootstrap
I
(J
E
9
180
10=0
E
8
MAXIMUM OUTPUT CURRENT
VB
SUPPLY VOLTAGE
vs
oC
7
Figure 5
INPUT SUPPLY CURRENT
16
6
Vee - Supply Voltage - V
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
APPLICATION INFORMATION
The TPS6734 operates in a boost circuit as shown in Figures 1 and 11. Figure 1 shows the typical application
circuit, which generates 12 V from a nominalS-V source. The circuit is ideal for processor interface for energy
management, because EN can be controlled by logic signals to place the 12-V source into the shutdown mode
(3-~ current drain) when 12 V is not needed. An example of such an application is a flash memory device that
, requires 12 V for the erase cycle .
. discontinuous mode
The circuit shown in Figure 1 operates in discontinuous mode over most of the range of input voltage and output
current. In discontinuous mode, current through the inductor begins at zero, rises to a peak value, then ramps
down to zero each cycle as shown by the voltage and current waveforms in Figure 8. The ringing in the voltage
waveform on OUT results from a resonance between the inductor and the power switch capacitance and is
normal for discontinuous operation.
DISCONTINUOUS MODE
VI=5V
>
I
:;
15
vo= 12V
IL=50mA
o
1;;
t
~
«
I
'E
~
,.
0.5
(J
0
,.
".5I
...
0
tl
o
2
4
6
8
10
12
14
16
18
t-Time- JlS
FigureS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-147
TPS67341
FIXED 12-V 12D-mA BOOST-CONVERTER SUPPLY
SLVSl27 - AUGUST 1995
APPLICATION INFORMATION
continuous mode
When the converter is delivering heavy loads from low voltage sources, it operates in continuous mode. As
shown in Figure 9, the inductor current does not drop to zero and the ringing is gone from the OUT voltage
waveform.
CONTINUOUS MODE
>
20
I
8
15
VI=5V
Vo= 12V
IL=150mA
-
~
I10
-
5
o
C
I
/
'v
/
o
~
"~
2
4
6
/ \
8
/'
\ V'
10
12
!\V
14
16
0.5
0
18
C
~
::s
(.)
~::s
I
J.
t-TIme"118
Figure 9
pulse-skipping mode
At very light load currents, the TPS6734 cannot generate drive pulses sufficiently narrow to maintain regulation
and operate at 170 kHz. Under these circumstances, the converter operates in a pulse-skipping mode, in which
cycles are skipped. In pulse-skipping mode, the waveforms are irregular and the output ripple contains a
low-frequency component that may exceed 50 mV peak-to-peak.
~TEXAS
4-148
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
APPLICATION INFORMATION
efficiency
Typical efficiency for the converter circuit shown in Figure 13 is plotted in Figure 10. The efficiency falls off
rapidly at very light currents because the supply current is a significant percentage of the load.
EFFICIENCY
va
OUTPUT CURRENT
88
86
84
>u
c
82
ffi1
80
.
'u
,
J,~
~
~~
".
-
,I
I
VCC=5.5V
'",
.1
VCC=4.5V
VciC=5V
;!.
78
76
74
10 20 30 40 50 60 70 80 90100 110120 130140
10 - Output Current - rnA
Figure 10
inductor selection
Inductance value is directly proportional to the input voltage and inversely proportional to the output power. The
18 J.lH shown in the typical circuit is the proper value for operation from 5-V sources up to 2-W loads. A lower
inductance value should be used when operating from 3-V sources. Operation from 7 V and higher sources may
require inductance values greater than 18 J.lH. The inductor's saturation current rating should be greater than
three times the dc load current for 5-V inputs and five times the dc load for 3-V inputs.
output filter capacitor selection
The output filter capacitor should be selected for minimum ESR (equivalent series reSistance). Capacitor
ESR x ~IL (change in inductor current) determines the amplitude of the high-frequency ripple on the output
voltage. The ESR of the capacitor should be less than 0.25 n to keep the output ripple less than 50 mV
peak-to-peak over the entire current range (using 18-J.lH inductor).
diode
A Schottky diode or a high-speed silicon rectifier should be used. The continuous current rating of the diode
.
should be at least 300 mA for full load (120 mA) operation.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
4-149
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
APPLICATION INFORMATION
soft-start capacitor
Soft-start timing is controlled by the value of the SS capacitor. Table 1 lists soft-start time intervals for selected
capacitor values and circuit conditions. If the circuit starts up with no load (e.g. in flash-memory programming
supplies), no soft start is needed. Omitting the soft-start capacitor provides a minimum output-voltage rise time
from the shutdown state, improving the output start-up time.
Table 1. Typical Soft-Start Times
t
SOFT-START TIMEt (ms) VERSUS CAPACITANCE (I.tF)
SUPPLY
VOLTAGE (V)
NO. CAP
0.047
0.1
0.47
1.0
5
0.70
22
42
220
400
7
0.46
15
37
185
225
9
0.38
10
17
88
155
Soft-start times are ±35%
printed-circuit layout
Printed-circuit-board (PCB) layout is critical to quiet operation. A ground plane is recommended. Special
attention should be given to minimizing the lengths of the switching loops. The first loop is formed by OUT, the
diode, the output capacitor, and GND, the length of which can be minimized by connecting the anode ofthe diode
. close to OUT. The output capacitor should be connected, directly between the diode cathode and GND with the
shortest possible path. The second loop is formed by OUT, the inductor, the input capacitor, and GND. This loop
is less critical than the first; however, the connection of OUT, the inductor and the anode of the diode must be
minimized. Bypass capacitors should be located as close to the device as possible to prevent instability and
noise pickup. If a large V cc-to-GND bypass capacitor cannot be placed adjacent to the IC pins, the pins should
be bypassed directly with a small ceramic capacitor (e.g., 0.1 IlF). The recommended layout shown in
Figures 14 through 17 can provide guidance for PCB configuration (the ground plane beneath the TPS6734 and
the short loops should be noted).
Plastic plug-in-type proto boards, or any construction scheme that allows long leads and. the possibility of noise
pickup, should not be used when assembling a breadboard or prototype application circuit implementing the
TPS6734.
~TEXAS
INSTRUMENTS
4-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
APPLICATION INFORMATION
bootstrapped output circuit
For operation below 2.7 V, the TPS6734 may be connected in a bootstrap configuration as shown in Figure 11.
The bootstrap configuration is less efficient (requires more supply current and suffers a loss in efficiency at
voltages below 5 V; see Figure 12) and is not recommended except for very low voltage operating conditions.
Because the output-driver stage, which benefits most from higher voltages, is diode-coupled to the output
voltage (see Figure 2), the bootstrapped configuration provides no benefit except at very low voltages. In the
shutdown mode (EN = low), no-load quiescent current is unchanged (31JA max) whether in the bootstrap or the
typical configuration.
VI
2Vto12V
ENABLE - - - r - - - 4
0.0047 11F
I
Figure 11. TPS6734 Bootstrap Configuration
EFFICIENCY
vs
OUTPUT CURRENT FOR TYPICAL AND BOOTSTRAP
86
TyPiC'!d:
84
82
80
t';'
c
78
!i
76
.~
.,.
I
74
/
II /
L I
krt1
VCC=5V
Bootstrap
I
II
72
70
68
6610 20 30 40 50 60 70 80 90 100110120130 140
10 - Output Current - mA
Figure 12
-!!1 TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-151
TPS~7341
.
FIXED 12..V 120.. mA BOOST-CONVERTER SUPPLY
SLVS127 - AUGUST 1995
APPLICATION INFORMATION
TPS6734 converter design with recommended layout
The following schematic (Figure 13) and.a required-components table are provided for a 12-V-output boost
converter. The converter is capable of delivering 120 mA of output current over an input voltage range of 3.75 V
to 12 V. Recommended layout and detailed artwork for a PCB are provided in Figures 14 through 17.
Pl
VI
Rl
10kg
GND
GND
ENABLE
TPS6734
3
8
EN
Cl
3311F,20V
4
2
VCC
FB
REF
7
Vo
Ul
3
SS
OUT
6
Vo
C5
5
GND
C2
0.01 11FT
-=
-=
3
+
C3
3311F,20V
TO.047 I1F_
-=
F~D
GND
C40.00111F
-=
-=
-=
NOTE A: A jumper between pins Pl-3 and Pl-4 shuts off the TPS7634. Remove the jumper to resume normal operation.
Figure 13. Schematic for Printed Circuit Board (shown in Figures 14 through 17)
Required Components
QTY.
1
DESCRIPTION
REF DES
MANUFACTURER'S
PART NO.
TPS6734ID
Ul
1
Diode, Schottky
Dl
SS12
General Instruments
1
Inductor, 18 I1H, 150 mg, 1.23 A(DC)
L1
CD54180MC
Sumida
2
Capacitor, 33 I1F, 20 V, tantalum
TAPSD336M020R0200
AVX
1
Capacitor, 0.01 I1F, 50 V, ceramic, 0805
C2
1
Capacitor, 0.047I1F, 50 V, ceramic, 1206
C3
1
Capacitor, 0.001 I1F, 50 V, ceramic, 0805
2
Connector, header, 4-pin
1
PCB, TPS6734
Cl,5
C4
Pl,2
~TEXAS
INSTRUMENTS
4-152
MANUFACTURER
Texas Instruments
IC, power supply, 12 V for flash memory
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Molex
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127-AUGUST 1995
REDUCE TO 2.500 +/- .005
~
I~T[xAS INSTRUMENTS
I
~
P1. CJ R1
...!.
1
8C\i
O
+
~
w
:::>
o
w
u
I
J() SLVP081
C1
L1 P2D 1
C2C30D10
rnDc~~51
4
)
4
UPS6734 EVALUATION BOARD ~
II:
SILKSCREEN - TOP
Figure 14. Component Placement
REDUCE TO 2.500 +/- .005
~
J..
+
8C\i
~
w
:::>
o
w
u
II:
~ TEXAS
1~
~
•
•
I_
P1.D R1
C2 C3
•
INSTRUMENTS
•
.)=SLVP08~
C1
L1
P2~
:f"1: • ..-- •
:::Lj:D1~ •
U1
I:II:lr-!C4
•4
SS.~ C5, - •
JMPR.
• TPS6734 EVALUATION BOARD
4•
SILKSCREEN - TOP
Figure 15. Solder Paste Mask
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
4-153
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SlVS127 - AUGUST 1995
REDUCE TO 2.500 +/- .005
~
-L
+
§
<\i
~
w
u
:::>
o
w
a:
COMPONENT SIDE
Figure 16. Printed Circuit, Component Side
REDUCE TO 2.500 +/- .005
It)
0
C!
-L
+
0
0
0
<\i
0
lW
u
:::>
0
w
a:
I
~
.....
•
••
~
••
r1
.-J
3012A30J02
Figure 17. Printed Circuit, Wiring Side
(Viewed from Component Side)
~TEXAS
4-154
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127 - AUGUST1995
MECHANICAL DATA
o (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
1-$-1 0.010 (0,25) ® 1
14
T
0.244 (6,20)
0.228 (5,BO)
0.157 (4,00)
0.150 (3,81)
b-----------~~
rt lillUUllUllrl-*
0.010(0,~
0.069 (1,75) MAX
0.004 (0,10)
4040047/B 10194
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0.15).
Four center pins are connected to die mount pad
Falls within JEDEC MS-012
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4-155
TPS67341
FIXED 12-V 120-mA BOOST-CONVERTER SUPPLY
SLVS127 - AUGUST 1995
MECHANICAL DATA
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE PACKAGE
o
JL
4
R
0.070 (1,78) MAX
0.020(0,51) MIN
14-------.1-- 0.310 (7,87)
0.290 (7,37)
0.200 (5,08) MAX
----r---+JL..
JL
t
~
0.100(2,54) 1
1-$-1
Seating Plane
0.125(3,18)MIN
t
1
0.021 (0,53)
0.010 (0 25) 1M"
0.015 (0,38)··
'
~.
JL
~OO_150
0.010 (0,25) NOM
4040082/8 10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
~TEXAS
INSTRUMENTS
4-156
POST OFFICE BOX 655303 • DAU.AS. TEXAS 75265
UC284x, UC384x, UC384xY
CURRENT-MODE PWM CONTROLLERS
SLVS038B-
- REVISED AUGUST 1995
o PACKAGE
• Optimized for Off-Line and dc-to-dc
Converters
(TOP VIEW)
• Low Start-Up Current ( < 1 rnA)
• Automatic Feed-Forward Compensation
• Pulse-by-Pulse Current Limiting
• Enhanced Load-Response Characteristics
• Undervoltage Lockout With Hysteresis
1
NC
2
13
VFB
NC
ISENSE
3
4
5
12
11
10
NC
RT/CT
6
7
9
B
• Double Pulse Suppression
• High-Current Totem-Pole Output
u
CaMP
140 REF
gNC
VCC
VC
OUTPUT
GND
POWER
1...-_--1 GROUND
NC- No internal connection
• Internally Trimmed Bandgap Reference
u
PPACKAGE
(TOP VIEW)
• SOo-kHz Operation
• Error Amplifier With Low Output
Resistance
COMP
VFB
ISENSE
RT/CT
• Designed to Be Interchangable With
Unitrode UC2842 and UC3842 Series
2
3
4
8
REF
7
6
5
VCC
OUTPUT
GND
description
The UC2842 and UC3842 series of control integrated circuits provide the features that are necessary to
implement off-line or dc-to-dc fixed-frequency current-mode control schemes with a minimum number of
external components. Some ofthe internally implemented circuits are an undervoltage lockout (UVLO) featuring
a start-up current of less than 1 mA and a precision reference trimmed for accuracy at the error amplifier input.
Other internal circuits include logic to ensure latched operation, a pulse-width modulation (PWM) comparator
(which also provides current-limit control), and a totem-pole output stage designed to source or sink high-peak
current. The output stage, suitable for driving N-channel MOSFETs, is low when it is in the off state.
The primary difference between the UC2842-series devices and the UC3842-series devices is the ambient
operating temperature range. The UC2842-series devices operate between -40°C and 85°C; the
UC3842-series devices operate between O°C and 70°C. Major differences between members of these series
are the UVLOthresholds and maximum duty cycle ranges. Typical UVLOthresholds of 16 V (on) and 10 V (off)
on the UCx842 and UCx844 devices make them ideally suited to off-line applications. The corresponding typical
thresholds for the UCx843 and UCx845 devices are 8.4 V (on) and 7.6 V (off). The UCx842 and UCx843 devices
can operate to duty cycles approaching 100%. A duty cycle range of 0 to 50% is obtained by the UCx844 and
UCx845 by the addition of an internal toggle flip-flop, which blanks the output off every other clock cycle.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
O°C to 70°C
UC3842D
UC3843D
UC3844D
UC3845D
UC3842P
UC3843P
UC3844P
UC3B45P
-40°C to 85°C
UC2842D
UC2843D
UC2844D
UC2845D
UC2842P
UC2843P
UC2844P
UC2845P
CHIP
FORM
(V)
UC3842Y
UC3843Y
UC3844Y
UC3845Y
-
-
The DW package IS available taped and reeled. Add the suffix R to the device type, (I.e.,
LT1054CDWR).
PRODUCTION DATA Infonnatlon Is ."rront as of ,publication date.
Products contonn to specifications per the tenns of Texas Instruments
standard warranty. Production processing does not necessarily include
tasting of all parameters.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-157
UC284x, UC384x, UC384xY
CURRENT-MODE PWM CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
functional block diagram
vcc
~1=2____~____~~____~__________________~
34V
NOM
UVLO
14
GND ...::9_~_ _--{
11
RT/CT -.;7-+-_ _ _ _;
REF
VC
OUTPUT
POWER
GROUNd
VFB
3
COMP
Current
Sense
Comparator
ISENSE 5
t The toggle flip-flop is present only in UC2844, UC2845, UC3844, and UC3845.
NOTE A: Terminal numbers apply to the D package only.
-!11
TEXAS .
INSTRUMENTS
'4--158
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UC284x, UC384x, UC384xY
CURRENT-MODE CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
UC384xY chip information
This chip, when properly assembled, displays characteristics similar to the UC384x. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
COMP
VFB
ISENSE
RT/CT
(1)
(8)
(2)
(7)
UC384xY
REF
VCC
(3)
(6)
(4)
(5)
OUTPU
GND
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
TJmax=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~
~
~
1111111111111111111111111111111111111111111111111111111111111111111111
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
4-159
UC284x, UC384x, UC384xY
CURRENT-MODE PWM CONTROLLERS
SLVS038B -JANUARY 1989 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage (see Note 1) (Icc < 30 mAl ............................................. Self Limiting
Analog input voltage range, VI (VFB and ISENSE terminals) ........................... - 0.3 V to 6.3 V
Output voltage, Vo (OUTPUT terminal) ...................................................... 35 V
Input voltage, VI, (VC terminal, D package only) .............................................. 35 V
Supply current, IcC ...................................................................... 30 mA
Output current, 10 .......................................... ,.............................. ±1 A
Error amplifier output sink current .......................................................... 10 mA
Continuous total power dissipation ..................................... See Dissipation Rating Table
Output energy (capacitive load) ............................................. !................ 5 iW
Operating free-air temperature range, TA: UC284x .......................... . . . . . . .. - 40°C to 85°C
UC384x .......................... . . . . . . . . . .. O°C to 70°C
Storage temperature range, Tstg ............................................. ;.... - 65°C to 150°C
Lead temperature, 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions lor extended periods may affect device reliability.
NOTE 1: All voltages are with respect to the device GND terminal.
DISSIPATION RATING TABLE
TA,,25°C
POWER RATING
DERATE
ABOVE TA = 25°C
TA=70°C,
POWER RATING
TA = 85°C
POWERRAnNG
D
950mW
494mW
l000mW
7.SmW/oC
8.0mW/oC
S08mW
P
640mW
520mW
PACKAGE
recommended operating conditions
UC284x
MIN
NOM
UC384x
MAX
NOM
MAX
UNIT
30
v
Input voltage, VI, RT/CT
0
5.5
0
5.5
V
Input voltage, VI, VFB and ISENSE
0
5.5
0
5.5
V
Output voltage, VO, OUTPUT
0
30
0
30
V
-Q.l
1
-0.1
1
30
Supply voltage, VCC and VCr
Output voltage, VO, POWER GROUNDT
V
Average output current, 10
200
200
Reference output current, IQ(ref)
-20
-20
rnA
rnA
rnA
500
kHz
70
°C
Supply current, externally limited, ICC
1
100
Oscillator frequency, losc
-40
Operating free-air temperature, TA
These recommended voltages for Vc and POWER GROUND apply only to the D package.
~TEXAS
INSTRUMENTS
4-160
25
25
Timing capacitance, CT
t
MIN
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
85
nF
100
500
0
UC284x, UC384x, UC384xY
CURRENT-MODE CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
electrical characteristics, Vee
(unless otherwise specified)
=15 V (see Note 2),
RT
=10 kn, CT =3.3 nF, TA =full
range
reference section
PARAMETER·
TEST CONDITIONS
Output voltage
10=1 mA,
Line regulation
Vee=12Vt025V
Load regulation
10 = 1 mA to 20 mA
TJ = 25°C
Vee=12Vt025V,
10=1 mAt020mA
Output noise voltage
f= 10 Hz to 10kHz,
Output voltage long-teon drift
After 1000 h at TA = 25°C
MAX
MIN
TYPt
MAX
4.95
5
5.05
4.9
5
5.1
V
6
20
6
20
mV
6
25
6
25
mV
0.2
0.4
0.2
0.4
mV-J°e
5.18
V
4.9
5.1
Short-circuit output current
4.82
50
TJ = 25°C
-30
t All typical values are at TJ = 25°C.
NOTE 2: Adjust Vee above the start threshold before setting it to 15
UNIT
TYPt
Temperature coefficient of output voltage
Output voltage with worst-case variation
UC384x
UC284x
MIN
~V
50
5
25
-100
-180
25
mV
-30
5
-100
-180
mA
UC384x
TypT
MAX
v.
oscillator section
PARAMETER
TEST CONDITIONS
Oscillator frequency (see Note 3)
TJ = 25°C
Frequency change with supply voltage
Vee=12Vt025V
Frequency change w~h temperature
TA = TMIN to TMAX
UC284x
MIN
TYPT
MAX
MIN
47
52
57
47
2
10
Peak-to-peak amplitude at RT/eT
UNIT
52
57
kHz
2
10
Hz/kHz
50
50
Hz/kHz
1.7
1.7
V
t All typical values are at TJ = 25°C.
NOTES: 2. Adjust Vee above the start threshold before setting it to 15 V.
3. Outputfrequency equals oscillator frequency for the Uex842 and Uex843. Outputfrequency is one-half oscillator frequency for the
Uex844 and Uex845.
error amplifier section
PARAMETER
Feedback input voltage
TEST CONDITIONS
eOMPat2.5V
UC284x
MIN
TYPT
MAX
MIN
2.50
2.55
2.42
-0.3
-1
2.45
Input bias current
Open-loop voltage amplification
VO=2 Vt04 V
Gain-bandwidth product
Supply voltage rejection ratio
Output sink current
Vee = 12 V to 25 V
VFB at 2.7 V,
eOMPat1.1 V
Output source current
VFB at 2.3 V,
eOMP at5 V
High-level output voltage
VFB at 2.3 V,
RL= 15 kQto GND
"Low-level output voltage
VFB at 2.7 V,
Rl = 15 kQto GND
UC384x
TYPt
MAX
UNIT
2.50
2.58
V
-0.3
-2
~
dB
90
65
90
65
0.7
1
0.7
1
60
70
60
70
dB
2
6
2
6
mA
-0.5
-0.8
-0.5
-0.8
mA
5
6
5
6
0.7
1.1
0.7
MHz
V
1.1
V
t All typical values are at TJ= 25°C.
NOTE 2: Adjust Vee above the start threshold before setting it to 15 V.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-161
UC284x, UC384x, UC384xY
CURRENT-MODE PWM CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
=
electrical characteristics, Vee 15 V (see Note 2), RT
otherwise specified) (continued)
=10 kn, CT =3.3 nF, TA =full range (unless
current sense section
PARAMETER
Vo~age
amplification
TEST CONDITIONS
See Notes 4 and 5
Current sense comparator thre.shold
COMPat5V,
Supply voltage rejection ratio
VCC = 12 V to 25 V, See Note 4
See Note 4
MIN
UC284x
TYpt
MAX
MIN
UC384x
TYpt
MAX
2.85
3
3.13
2.85
3
3.15
0.9
1
1.1
0.9
1
1.1
70
Input bias current
Delay time to output
70
UNIT
VN
V
dB
-2
-10
-2
-10
!lA
150
300
150
300
ns
t
All typical values are at TJ = 25°C.
NOTES: 2. Adjust VCC above the start threshold before setting it to 15 V.
4. These parameters are measured at the trip point of the latch with VFB at 0 V.
5. Voltage amplification is measured between ISENSE and COMP w~h the input changing from 0 V to 0.8 V.
output section
PARAMETER
High-level output voltage
TEST CONDITIONS
UC284x
MIN
TYPT
'OH=-20mA
13
'OH=-200mA
12
Low-level output voltage
'OL=20mA
IOL= 200 mA
Rise time
CL= 1 nF,
Fall time
CL= 1 nF,
UC384x
MIN
TYPT
13.5
13
13.5
13.5
12
13.5
MAX
MAX
UNIT
V
0.1
0.4
0.1
0.4
1.5
2.2
1.5
2.2
TJ = 25°C
50
150
50
150
ns
TJ = 25°C
50
150
50
150
ns
V
t All typical values are at TJ -- 25°C.
NOTE 2. Adjust VCC above the start threshold before setting it to 15 V.
undervoltage lockout section
TEST CONDITIONS
PARAMETER
Start threshold vo~age
Minimum operating voltage after start-up
UC284x
MIN
TYPT
UC384x
MAX
MIN
TYPT
MAX
16
17
14.5
16
17.5
8.4
9
7.8
8.4
9
UCx842,
UCx844
15
UCx843,
UCx845
7.8
UCx842,
UCx844
9
10
11
8.5
10
11.5
UCx843,-
UCx845
7
7;6
8.2
7
7.6
8.2
MAX
MIN
TYpt
MAX
UNIT
V
V
t
All typical values are at TJ = 25°C.
NOTE 2. Adjust VCC above the start threshold before setting it to 15 V.
pulse-wldth-modulator section
PARAMETER
Maximum duty cycle
TEST CONDITIONS
MIN
UC284x
TYpt
UC384x
UCx842,
UCx843
95%
97%
100%
95%
97%
100%
UCx844,
UCx845
46%
48%
50%
46%
48%
50%
Minimum duty cycle
0
UNIT
0
t
All tYPical values are at TJ = 25°C.
NOTE 2. Adjust VCC above the start threshold before setting it to 15 V.
supply voltage
PARAMETER
TEST CONDITIONS
UC384x
UC284x
MIN
TYPT
Start-up current
MAX
MIN
TYPT
MAX
UNIT
0.5
1
0.5
1
mA
Operating supply current
VFB and ISENSE at 0 V
11
17
11
17
mA
Limiting voltage
ICC=25mA
34
t
All typical values are at TJ = 25°C.
NOTE 2. Adjust VCC above the start threshold before setting ~ to 15 V.
~TEXAS
4-162
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
34
V
UC284x, UC384x, UC384xY
CURRENT-MODE CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
electrical characteristics, vee = 15 V (see Note 2), RT= 10 kn, CT = 3.3 nF, T J = 25°C (unless otherwise
specified)
.
reference section
PARAMETER
TEST CONDITIONS
UC384xY
MIN
TYP
MAX
UNIT
Output voHage
10=1 rnA
5
V
Line regulation
VCC=12Vt025V
6
mV
Load regulation
10=1 rnA to 20 rnA
6
Temperature coefficient of output voltage
Output noise voHage
f = 10 Hz to 10 kHz
Output voltage long-term drift
After 1000 h at TA = 25°C
Short-circuit output current
mV
0.2
mV-J°C
50
5
ltV
mV
-100
rnA
NOTE 2. Adjust VCC above the start threshold before setting It to 15 V.
oscillator section
PARAMETER
TEST CONDITIONS
UC384xY
MIN
TYP
Oscillator frequency (see Note 3)
Frequency change with supply voHage
VCC=12Vt025V
Frequency change with temperature
Peak-to-peak amplitude at RT/CT
NOTES:
MAX
UNIT
52
kHz
2
HzlkHz
5
HzlkHz
1.7
V
2. Adjust VCC above the start threshold before setting it to 15 V.
3. Output frequency equals oscillator frequency for the UCx842 and UCx843. Output frequency is one-half oscillator frequency for the
UCx844 and UCx845.
error amplifier section
PARAMETER
Feedback input voltage
TEST CONDITIONS
UC384xY
MIN
COMP at 2.5 V
Input bias current
Open-loop voltage amplification
TYP
MAX
V
-0.3
ItA
90
VO=2Vt04V
Gain-bandwidth product
dB
1
Supply voltage rejection ratio
VCC=12Vt025V
Output sink current
VFB at 2.7 V,
COMPatl.l V
UNIT
2.50
MHz
70
dB
6
rnA
-0.8
rnA
Output source current
VFB at 2.3 V,
COMPat5V
High-level output voHage
VFBat2.3V,
RL = 15 kQ to GND
6
V
Low-level output voHage
VFB at 2.7 V,
RL = 15 kQ toGND
0.7
V
NOTE 2. Adjust VCC above the start threshold before setting it to 15 V.
current sense section
PARAMETER
TEST CONDITIONS
UC384xY
MIN
TYP
MAX
UNIT
VN
Voltage amplification
See Notes 4 and 5
Current sense comparator threshold
COMPat5V,
See Note 4
1
V
Supply voltage rejection ratio
VCC = 12 Vto 25 V, See Note 4
70
dB
-2
ItA
150
ns
3
Input bias current
Delay time to output
NOTES:
2. Adjust VCC above the start threshold before setting it to 15 V.
4. These parameters are measured at the trip point of the latch with VFB at 0 V.
5. Voltage amplification is measured between ISENSE and COMP with the input changing from 0 V to 0.8 V.
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
4-163
UC284x, UC384x, UC384xY
CURRENT-MODE PWM·CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
electrical characteristics; Vee = 15 V (see Note 2), RT = 10kn, CT = 3.3 nF, TJ = 25°C (unless
otherwise specified) (continued)
output section
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
UC384xY
MIN
TYP
IOH=-20mA
13.5
IOH =-200mA
13.5
IOL=20mA
0.1
MAX
UNIT
V
V
IOL= 200 mA
1.5
Rise time
CL= 1 nF
50
ns
Fall time
CL= 1 nF
50
ns
NOTE 2. Adjust VCC above the start threshold before setting It to 15 V.
undervoltage lockout section
UC384xY
TEST CONDITIONS
PARAMETER
MIN
Start threshold voltage
Minimum operating voltage after start-up
TYP
UC3842Y,
UC3844Y
16
UC3843Y,
UC3845Y
8.4
UC3842Y,
UC3844Y
10
UC3843Y,
UC3845Y
7.6
MAX
UNIT
V
V
NOTE 2. Adjust VCC above the start threshold before setting It to 15 V.
pulse-width-modulator section
PARAMETER
Maximum duty cycle
TEST CONDITIONS
UC384xY
MIN
TYP
UC3842Y,
UC3843Y
97%
UC3844Y,
UC3845Y
48%
MAX
UNIT
NOTE 2. Adjust VCC above the start threshold before setting it to 15 V.
supply voltage
TEST CONDITIONS
PARAMETER
Start-up current
Operating supply current
Limiting voltage
VFB and ISENSE at 0 V
' Icc=25mA
NOTE 2. Adjust VCC above the start threshold before setting It to 15 V.
~TEXAS
4-164
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
UC384xY
MIN
UNIT
TYP
MAX
0.5
1
mA
11
17,
mA
34
V
UC284x, UC384x, UC384xY
CURRENT-MODE CONTROLLERS
SLVS0388 - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
2.5V
~O.5mA
VFB
COMP
NOTE A.
Error amplifier can source or sink up to 0.5 rnA.
Figure 1. Error Amplifier Configuration
Error
Amp
liS
(see Note A)
n
Rf
2R
.Jl
COMP
1V
Current
Sense
Comparator
ISENSE
Ct
RS
GND
NOTE A: Peak current (IS) is determined by the formula:
1 V
IS(max) =
RS
A small RC filter formed by resistor Rf and capacitor Cf may be required to suppress switch transients.
Figure 2. Current Sense Circuit
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4--165
UC284x, UC384x, UC384xY
CURRENT-MODE PWM CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
REF
RT
(see Note A)
RT/CT
:;::t=::
GND
-..=-
NOTE A: For RT > 5 KQ
Figure 3. Oscillator Section
TIMING RESISTANCE
DEAD TIME
vs
vs
TIMING CAPACITANCE
FREQUENCY
100
100
VCC = 15 V
RT,,5kQ
40
'\
TA=25°C
40
...
C;
i.-'~
.. 10
:::I.
I
CP
E
i=
1\
"
\~
I
3c
01
4
'Iii
1/
'iii
/
CP
I!:
./
]
1
0.4
c
·s'"
~:.-
-
lI!:
_
4
III
CT=47nF
1111111
CT~,loo nF
-
CT=4.7nF
CT=2.2 n F
IIIII
\.
~\
[\
,
\.
~
\.
CT= 1 nF
1\ \
IIIIIII
I 11111111
1
4
10
CT - Timing Capacitance - nF
40
100
100
1k
Figure 4
10 k
100 k
f - Frequency - Hz
Figure 5
~'TEXAS
4-166
CT=10nF7~
VCC=15V
TA=25°C
O. 1
1
-
i=
I
CT=22n/>(\
10
,
'\
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1M
UC284x, UC384x, UC384xY
CURRENT-MODE CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
open-loop laboratory test fixture
In the open-loop laboratory test fixture shown in Figure 6, high-peak currents associated with loads necessitate
careful grounding techniques. Timing and bypass capacitors should be connected close to the GND terminal
in a single-point ground. The transistor and 5-kQ potentiometer sample the oscillator waveform and apply an
adjustable ramp to the ISENSE terminal.
r--------.--~.-------------------._------------------REF
VCC
4.7kn
r-VVv--+----+--I COMP
OUT
REF
1 kn
Error Amp >4---*-----+-----1-1 VFB
UC284x VCC 1-+-__'"
Adjust
UC384x
0.1 IlF
1 kil, 1 W
5 kO ~----+--I ISENSE
OUTPUT 1----+----+------_----- Output
ISENSE
4.7kn
Adjust _
RT/CT
GNO
~------------------
GNO
CT
Figure 6. Open-Loop Laboratory Test Fixture
shutdown technique
Shutdown of the PWM controller (see Figure 7) can be accomplished by two methods: either raise the voltage
at ISENSE above 1 V or pull the COMP terminal below a voltage two diode drops above ground. Either method
causes the output of the PWM comparator to be high (refer to block diagram). The PWM latch is reset dominant
so that the output remains low until the next clock cycle after the shutdown condition at the COMP or ISENSE
terminal is removed. In one example, an externally latched shutdown may be accomplished by adding an SCR
that resets by cycling Vee below the lower UVLO threshold. At this point the reference turns off, allowing the
SCR to reset.
,------'V0.--_._---IREF
___--IISENSE
3300
5000
Shutdown ---.
To Current
Sense Resistor
Figure 7. Shutdown Techniques
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
4-167
UC284x, UC384x, UC384xV
CUR.RENT-MODE PWM CONTROLLERS
SLVS038B - JANUARY 1989 - REVISED AUGUST 1995
APPLICATION INFORMATION
A fraction of the oscillator ramp can be resistively summed with the current sense signal to provide slope
compensation for converters requiring duty cycles over 50% (see Figure 8). Note that capacitor C forms a filter
with R2 to suppress the leading-edge switch spikes.
REF~--~--------
RT/CT
__------~
1-------------.
+ISENSE
ISENSE ~------------------___---e-----,\NIr-----e
RSENSE
Figure 8. Slope Compensation ..
~TEXAS
'ill'
4-168
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-1
Contents
Page
TL77xxA Supply Voltage Supervisors .................................. 5-3
TL77xxB Supply Voltage Supervisors ................................ 5-15
TL7757
Supply VoltageSupeniisor and Precision Voltage
Protector ..................................................... 5-25
TL7759
'Supply Voltag,e Supervisors ................................ 5-37
TL7770-xx Dual Power-Supply Supervisors ........................... 5~43
TLC7705 Micropower Supply Voltage Supervisors ................. 5-53
•
en
c
"C
"C
<"
~';
.m-..
ca
o
CD
en
c
"C
_.
CD
~
til
o
U1
5-2
TL7702A,TL7705A, TL7709A,TL7712A,TL7715A
TL7702AY, TL7705AY, TL7709AY, TL7712AY, TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C -APRIL 1983 - REVISED AUGUST 1995
•
Power-On Reset Generator
•
Automatic Reset Generation After
Voltage Drop
•
Wide Supply Voltage Range
•
Precision Voltage Sensor
•
Temperature-Compensated Voltage
Reference
•
True and Complement Reset Outputs
FKPACKAGE
•
Externally Adjustable Pulse Duration
()za:z>z
It () go
D, JG, OR P PACKAGE
(TOP VIEW)
REF(J8
RESIN 2
7
. CT 3
6
GND 4
5
VCC
SENSE
RESET
RESET
(TOP VIEW)
description
4 3 2 1 20 1918 NC
NC
The TL77xxA family_ of monolithic integrated
RESIN
5
17 SENSE
circuit supply voltage supervisors are specifically
16 NC
NC
6
designed for use as reset controllers in micro15 RESET
CT 7
computer and microprocessor systems. The
14 NC
NC 8
supply voltage supervisor monitors the supply for
9 10 11 12 13
undervoltage conditions at the SENSE input.
During power up, the RESET output becomes
active (low) when V CC attains a value approaching
3.6 V. At this point (assuming that SENSE is above
VIT+), the delay timer function activates a time
NC - No internal connection
delay after which outputs RESET and
RESET go inactive (high and low respectively). When an undervoltage condition occurs during normal
operation, outp,uts RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs
remain active for a time delay after the voltage at the SENSE input exceeds the positive-going threshold value.
The time delay is determined by the value of the external capaCitor CT: td 1.3 x 104 x CT, where CT is in farads
(F) and td is in seconds (s).
.
=
During power down (assuming that SENSE is below VIT-), the outputs remain active until the VCC falls below
a maximum of 2 V. After this, the outputs are undefined.
An external capacitor (typically 0.111F for the'TL77xxAC and TL77xxAI and typically 0.0211Ffor the TL77xxAM)
must be connected to REF to reduce the influence of fast transients in the supply voltage.
The TL77xxAC series are characterized for operation from O°C to 70°C. The TL77xxAl series are characterized
for operation from -40°C to 85°C. The TL7702AM and TL7705AM are characterized for operation over the full
military range of -55°C to 125°C.
AVAILABLE OPTIONS
TA
SMALL OUTLINE
(D)
O°Cto
70°C
-40°C to
850C
-55°C to
125°C
PACKAGED DEVICES
CHIP CARRIER
CERAMIC DIP
(FK)
(JG)
PLASTIC DIP
(P)
TL7702ACD - TL7715ACD
TL7702ACP - TL7715ACP
TL7702AID - TL7715AID
TL7702AIP - TL7715AIP
TL7702AMFK
TL7705AMFK
~:wcn.:.,~':1! ~==.~'::1!r:: l:~~::':
standard warranty. Production pro....1ng does not necessarily Include
testing of 811 parameters.
CHIP FORM
(Y)
TL7702ACY - TL7715ACY
TL7702AMJG
TL7705AMJG
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1995. Texas Instruments Incorporated
On producto compliant to MIL.sTlH83, Class B, all parameters ora
=~":":':-"'=iY~~~d:'l:C.u~":lrp!'=
5-3
TLn02A, TLn05A, TL7709A, TLn12A, TLn15A
TLn02AY, TLn05AY, TL7709AY, TL7712AY, TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C ,-APRIL 1983 - REVISED AUGUST 1995.
TLnxxAY chip information
This chip, when properly assembled, displays characteristics similar to the TL77xxAC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold~silicon preform.
BONDING PAD ASSIGNMENTS
REF
RESIN
CT
GND
(1)
(8)
(2)
(7)
(3)
TL77xxAY
(6)
(5)
(4)
VCC
SENSE
RESET
RESET
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4
TJmax
x 4 MILS MINIMUM
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~
n
~
1'1'1'1'1'1'1'1'1'1'1'1'1"1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1,'1'1'1'1'1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
TL7702A, TL7705A, TL7709A, TL7712A, TL7715A
TL7702AY, TL7705AY, TL7709AY, TL7712AY, TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C - APRIL 1983 - REVISED AUGUST 1995
functional block diagram
The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming
network to adjust the reference voltage and sense comparator trip pOint.
Vee
8
~ =100~
eT
3
SENSE
7
"--_----"-6 RESET
~_ _
5
RESET
R1
(see Note A)
,
R2
(see Note A)
\
RESIN
2
-+_______
L -_ _ _ _ _ _ _ _ _
GND
-+_~1
REF
4
NOTES: A. TL7702A: R1 = 0 Q, R2 = open
TL7705A: R1 = 7.8 k!l, R2 = 10 kQ
TL7709A: R1 = 19.7 kg, R2 =.10 k!l
TL7712A: RI = 32.7 kQ, R2 = 10 kQ
TL7715A: R1 = 43.4 kg, R2 = 10 k!l
B. Terminal numbers shown are for the D, JG, or P package.
C. Resistor values shown are nominal.
timing diagram
Vee and SENSE
-tn-
Threshold Voltage
Vee=3.6V-
11
~-
I
II
I
~1~1~___--~I-Ir_--------~I_4~---~~ Vee=2V
II
II
I I
~ ~:-r-----i'
td
, i++f- td
RES=lJET
I
U
'I
j - '_ _ _
Output
Undefined
I
I
ILJf'~
l[
~~:~~ed
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-5
TL7702A,TL7705A,TL7709A,TL7712A,TL7715A
TL7702AY, TL7705AY,TL7709AY,TL7712AY,TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C -APR.IL 1983 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage, Vee (see Note 1) .. ..... ....... ..... ............. .... . . ............. ... .... 20 V
Input voltage range, V" RESIN .................................................... -0.3 V to 20 V
Input voltage range, V" SENSE:TL7702A (see Note 2) ................................ -0.3 V to 6 V
TL7705A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 20 V
TL7709A •........................................... -0.3 V to 20 V
TL7712A, TL7715A ................................... -0.3 V to 20 V
High-level output current, IOH' RESET ......................... . . . . . . . . . . . . . . . . . . . . . . . . .. -30 mA
Low-level output current, IOL' RESET ..................................................... 30 mA
Continuous total power dissipation .................................... See Dissipation Rating Table
Operating free-air temperature range, TA: TL77xxAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
TL77xxAi ................................... -40°C to 85°C
TL7702AM, TL7705AM ..................... -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 60 seconds, T e: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case fori 0 seconds: D or P package ................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package .................... 300°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAs25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA=125°C
POWER RATING
0
725mW
5.8mW/"C
464mW
377mW
145mW
FK
1375mW
11.0mW/oC
880mW
715mW
275mW
JG
1050mW
8.4mW/"C
672mW
546mW
210mW
p
1000mW
8.0mW/oC
640mW
520mW
200mW
recommended operating conditions
TL77xxAC, TL77xxAI
Supply voltage, VCC
UNIT
MAX
MIN
MAX
3.5
18
3.6
10
V
0.6
V
High-level input voltage at RESIN, VIH
2
Low-level input voltage at RESIN, VIL
Input voltage, SENSE, VI
TL77xxAM
MIN
2
0.6
V
TL7702A
0
See Note 2
0
See Note 2
TL7705A
0
10
0
10
TL7709A
0
15
TL7712A
0
20
TL7715A
0
High-level output current, RESET, IOH
V
20
-16
-16
mA
Low-level output current, RESET, IOL
16
16
mA
liming capacitor, CT
10
10
f.lF
TL77xxAC
Operating free-air temperature range, TA
TL77xxAi
0
70
-40
85
TL7702AM, TL7705AM
°C
-55
125
NOTE 2: For proper operation of the TL7702A, the voltage applied to the SENSE terminal should not exceed VCC-1 V or 6 V, whichever IS less.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7702A,TL7705A,TL7709A, TL7712A, TL7715A
TL7702AY,TL7705AY, TL7709AY, TL7712AY, TL7715AY
SUPPLY
VOLTAGE SUPERVISORS
SLVS028C - APRIL 1983 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (unless otherwise noted)
TL77xxAC,TL77xxAI
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage, RESET
IOH=-16 mA
VOL
Low-level output voltage, RESET
IOL=16mA
Vref
Reference voltage
TA = 25°C
VIT-
Negative-going input threshold voltage,
SENSE
MIN
V
V
V
2.53
2.58
TL7702A
2.48
2.53
2.58
TL7705A
4.5
4.55
4.6
7.5
7.6
7.7
TL7712A
10.6
10.8
11
TL7715A
13.2
13.5
13.8
TL7709A
TL7709A
TA = 25°C
15
mV
20
TA=25°e
35
TL7715A
45
20
VI =2.4 VtoVee
II
Input current, RESIN
II
Input current, SENSE
IOH
High-level output current, RESET
VO= 18V
IOL
low-level output current, RESET
VO=O
ICC
Supply current
All inputs and outputs open
-100
VI =0.4V
. .
V
10
TL7712A
TL7702A
UNIT
0.4
2.48
TL7705A
Hysteresis, SENSE (VIT + - VIT _)
MAX
Vee-1.5
TL7702A
Vhys
TYP
0.5
Vref < VI < Vee -1.5 V
1.8
I1A
SO
-SO
I1A
I1A
I1A
3
mA
2
tAli electncal charactenstlcs are measured With O.l-j1F capacitors connected at REF, eT, and Vee to GND.
switching characteristics over recommended operating conditions (unless otherwise noted)
TL77xxAC,TL77xxAI
PARAMETER
TEST CONDITIONtN
Output pulse duration
eT=O.lj1F
Input pulse duration at RESIN
iw(S)
Pulse duration at SENSE input to switch outputs
VIH = VIT _ +200 mV,
VIL = VIT _ -200 mV
tpd
Propagation delay time from RESIN to RESET
Vee=5V
RESET
tr
RESET
RESET
TYP
MAX
0.65
1.2
2.6
UNIT
j1S
0.4
j1S
2
j1s
1
j1S
0.2
Vee = 5 V, See Note 3
RESET
tf
MIN
3.5
3.5
0.2
. .
j1S
j1S
tAli sw~chlng charactenstics are measured with O.l-j1F capacitors connected at REF and Vee to GND .
NOTE 3: The rise and fall times are measured with a 4.7-kQ load resistor at RESET and RESET.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
5-7
TL7702A,TL770SA,TL7709A, TL7712A,TL771SA
TL7702AY, TL770SAY, TL7709AY, TL7712AY, TL771SAY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C -APRIL 1983 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (unless otherwise noted)
TL7702AM, TL7705AM
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage, RESET
10H =-16mA.
VOL
Low-level output voltage, RESET
10L= 16 rnA
Vref
Reference voltage
VIT-
Negative-going input threshold voltage,
SENSE
Vhys
Hysteresis SENSE (VIT + - VIT -)
II
Input current, RESIN
TL7702AM
TL7705AM
TL7702AM
TL7705AM
MIN
TYP
VCC = 3.6 V to 10 V
0.4
V
V
2.38
2.53
2.63
2.38
2.53
2.63
4.25
4.55
4.7
10
VCC=3.6Vt010V
20
-100
II
10H
High-level output current, RESET
VO= 10V
10L
low-level output current, RESET
VO=O
Ice
Supply current
All inputs and outputs open
0.5
Vref < VI < VCC-1.5 V
2
IIA
-50
IIA
IIA
IIA
3
rnA
50
1.8
V
mV
15
VI =0.4 V
Input current, SENSE
UNIT
V
VCC-lo5
VI =2.4 Vto Vec
TL7702AM
MAX
t All electrical characteristics are measured with 0.02-I1F capacitors connected at REF, CT, and Vec to GND.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS:j:
tw(S)
Pulse duration at SENSE input to switch outputs
VIH = VIT _ +200 mV,
VIL = VIT _ -200 mV
tpd
Propagation delay time, RESIN to RESET
Vee=5V
RESET
RESET
tf
TYP
MAX
2-
UNIT
I1s
I1S
0.2-
Vee = 5 V,
See Note 3
3.5-
~TEXAS'
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
I1S
3.50.2-
RESET
- On products compliant to MIL-STD-883, Class B, thIS parameter is not productIon tested.
:j: All switching characteristics are measured with 0.02-I1F capacitors connected at REF and Vee to GND.
NOTE 3: The rise and fall times are measured with a 4.7-kO load resistor at RESET and RESET.
5-8
MIN
1.5
RESET
tr
TL7702AM, TL7705AM
I1S
TL7702A,TL7705A,TL7709A,TL7712A,TL7715A
TL7702AY, TL7705AY, TL7709AY, TLn12AY, TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C - APRIL 1983 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
TL77xxAY
PARAMETER
Vref
VIT-
TYP
MIN
Negative,going input threshold voltage,
SENSE
'Hysteresis, SENSE (VIT + - VIT _)
TL7702A
2.53
TL7705A
4.55
TL7709A
7.6
TL7712A
10.8
TL7715A
13.5
TL7702A
10
TL7705A
15
TL7709A
20
TL77l2A
35
TL7715A
t
II
Input current, SENSE
ICC
Supply current
MAX
2.53
Reference voltage
,
Vhys
TEST CONDITIONSt
TL7702A
UNIT
V
V
mV
45
Vref--4......----~2 RESIN
2 RESIN
3
TL7712A
6
RESET
REF 1
CT
GND
RESET'1-'5~t--
10kn
3
CT
10kn
10kO
CrtF) =
8
VCC
7 SENSE
td(s)
1.3x 1()4
2 RESIN
10kn
O.lI1F
-12 V - - - -__- - - -___
----~t__----'
Figure 6. Multiple Power Supply System Reset Generation
5V
81
.---!
VCC
S,!!NSE .
--...!
RESIN
3
r--
10kO
RESET 5
REF
GND
CT ;;;:
i='
?
41
VCC
RESET
TMS7000
TL7705A
6
RESET
CT
.1.
10kn ;>
VSS
;;;:r: O.lI1F
GND
CrtF) =
Id{s)
1.3 x 104
Figure 7. Reset Controller for TMS7000 System
Tenninal numbers shown are for the 0, JG, and P packages.
~TEXAS
5-12
System Reset
TL7705A
RESET 6
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
TL7702A,TL7705A,TL7709A,TL7712A, TL7715A
TL7702AY, TL7705AY, TL7709AY, TL7712AY, TL7715AY
SUPPLY VOLTAGE SUPERVISORS
SLVS028C - APRIL 1983 - REVISED AUGUST 1995
APPLICATION INFORMATION
r----------+------~~----~~--+SV
!1A780S
INPUT
8
Vee
OUTPUT
System RESET
._--'7'--1 SENSE
Input
RESET ....S'----*"_---'G=-f-t41+--'
COMMON
TL770SA
6
RESET
4.7kn
Q1
2N3994
-=-
Figure 8. Eliminating Undefined States Using a P-Channel JFET
Vee
10kn
7S0Q
Q1
2N4036
8
Vee
SENSE Input _+--,7, SENSE
2.7 kn
. - - - . System RESET
RESET S
TL77xxA
2
RESIN
RESET 6
10kQ
1 kn
-=Figure 9. Eliminating Undefined States Using a pnp Transistor
Terminal numbers shown are for the D, JG, and P packages.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-13
5-14
TL7702B, TL7705B, TL7702BY,TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
•
Power-On Reset Generator
•
Automatic Reset Generation After
Voltage Drop
•
RESET Output Defined From Vee
•
Precision Voltage Sensor
•
Temperature-Compensated Voltage
Reference
•
True and Complement Reset Outputs
•
Externally Adjustable Pulse Duration
TL77xxBC ... P OR D PACKAGE
TL77xxBM ... JG PACKAGE
{TOP VIEW)
~
1V
R E F D 8 VCC
RESIN 2
7 SENSE
CT 3
6 RESET
GND 4
5 RESET
TL77xxBM .. ; FK PACKAGE
{TOP VIEW)
U
It
u Su
za:z;;:;:z
description
3 2 120 19
NC
The TL77028 and TL77058 are monolithic
4
18 NC
RESIN
17 SENSE
integrated circuit voltage supervisors designed for
5
use as reset controllers in microcomputer and
NC
16 NC
6
microprocessor systems. The supply voltage
CT
7
15 RESET
supervisor monitors the supply for undervoltage
NC
8
14 NC
9 10 11 12 13
conditions at the SENSE input. During power up,
the RESET output becomes aCtive (low) when
VCC attains a value approaching 1 V. As VCC
approaches 3 V (assuming that SENSE is above
VT+) , the delay timer function activates a time
delay after which outputs RESET and RESET go
NC-No intemal connection
inactive (high and low respectively). When an undervoltage condition occurs during normal operation, outputs
RESET and RESET go active. To ensure that a complete reset occurs, the reset outputs remain active for a time
delay after the voltage at the SENSE input exceeds the positive-going threshold value. The time delay is
determined by the value of the external capacitor CT: td '" 1.3 x 104 x CT, where CT is in farads (F) and td is in
seconds (s).
An external capacitor (typically 0.1 IlF) must be connected to REF to reduce the influence of fast transients in
the supply voltage.
The TL77028C and TL77058Care characterized from O°C to 70°C. The TL770281 and TL77058i are
characterized for operation from -40°C to 85°C. The TL77028Q and TL77058Q are characterized for operation
from -40°C to 125°C. The TL77028M and TL77058M are characterized for operation from -55°C to 125°C.
TA
O°Cto 70°C
-40°C to 85°C
-40°C to 125°C
SMALL OUTLINE
(D)
TL7702BCD, TL7705BCD
TL7702BID,TL7705BID
TL7702BQD, TL7705BQD
-55°C to 125°C
-
~~~:: sl=~au:81~~::n:::,e:~~ug~n!:;
standard warranty. Production processing does not necessartly include
testing of all parameters.
AVAILABLE OPTIONS
PACKAGE
CHIP CARRIER CERAMIC DIP
(FK)
(JG)
TL7702BMFK
TL7702BMJG
TL7705BMFK
TL7705BMJG
-
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
PLASTIC DIP
(P)
TL7702BCP, TL7705BCP
TL7702BIP, TL7705BIP
TL7702BQP, TL7705BQP
CHIP FORM
(Y)
TL7702BY
TL7705BY
-
Copyright © 1995; Texas Instruments Incorporated
5-15
TL7702B, TL7705B, TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989,.. REVISED AUGUST 1995
TL7702BY and TL7705BY chip information
These chips, when properly assembled, display characteristics similar to the TL7702BC and the TL7705BC.
Thermal compression Or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may
be mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
REF
RESIN
CT
GND
(1)
(8)
(2)
(7)
(3)
TL77xxBY
(4)
(6)
(5)
VCC
SENSE
RESET
RESET
CHIP THICKNESS: 15 MILS TYPICAL
, BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
-=
~
"
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
~TEXAS
5-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL7702B,TL7705B,TL7702BY,TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
functional block diagram
The functional block diagram is shown for illustrative purposes only; the actual circuit includes a trimming
network to adjust the reference voltage and sense comparator trip point.
Vee~8------------~~-------------.~-----------------------.
CT
SENSE
~3
______________~____+-______~~________~~
,-_-=-6 RESET
7
5
-r-_ _
RESET
R1
(see Note A)
R2
(see Note A)
-r__________~____+-____~
RESIN ~2__
+-____________~--___1
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
REF
4
GND----~--------~~------------------------~------------~
NOTE A: TLn02B: R1 = 0 Q, R2 = open
TLn05B: R1 = 23 kQ, R2 = 10 kQ, nominal
typical timing diagram
Vee and
,
SENSE
VIT+
Vres
i7r,
JztJ.
I
o I I
--I I
VIT-
RESET I ~Id
Output
Undefined
~
M
U
HI
-..I
I
I
:
I
I
r- 1d-1
_
~
1 \ 1 VIT-
VIT+
Vres
I I
I I
II
IlJ-
o
~utput
Undefined
~TEXAS·
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
5-17
TL7702B,TL7705B, TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range {unless otherwise noted}t
~
Supply voltage, Vee (see Note 1) ........................................................... 20 V
Input voltage range, VI (RESIN) .........• :......................................... -0.3 V to 20 V
Input voltage range, VI (SENSE) ................................................... -0.3 V to 20 V
High-level output current, IOH (RESET) ................................................... -30 mA
Low-level output current, IOL (RESET) ...........'. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA: TL770xBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O°C to 70°C
TL770xBI ................................... -40°C to 85°C
TL770xBQ ................................ -40°C to 125°C
TL770xBM ................................ -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Case temperature for 60 seconds, T e: FK package .......................................... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG package .................... 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P packages ................ 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implilid. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the network ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=70°C
POWER RATING
TA = 85°C
POWER RATING
TA=125°C
POWER RATING .
0
725mW
5.8mW/"C
464mW
377mW
145mW
FK
1375mW
11.0mW/oC
880mW
715mW
275mW
JG
p
1050mW
8.4mW/"C
672mW
546mW
210mW
1000 mW
8.0mW/oC
640mW
520mW
200mW
recommended operating conditions
Supply voltage, VCC
MIN
MAX
3.6
18
UNIT
V
High-level input voltage, VIH
RESIN
2
18
V
Low-level input voltage, VIL
RESIN
0
0.8
V
Input voltage, VI
SENSE
0
18
High-level output current, IOH
RESET
_16
mA
Low-level output current, IOL
RESET
16
mA
10
IlF
TIming capacitor. CT
TL770xBC
Operating free-air temperature range, TA
70
TL770xBI
-40
85
TL770xBQ
-40
125
TL770xBM
-55
125
~TEXAS
INSTRUMENTS
5-18
0
POST OFFice BOX 655303 • DALLAS, TeXAS 75265
V
°C
TLn02B, TLn05B, TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONSt
TL77xxBC, TL77xxBI
TL77xxBQ
MIN
VOH
High-level output voltage, RESET
IOH=-16mA
VOL
Low-level output voltage, RESET
IOL=16mA
Vref
Reference voHage
lref = 500 !lA,
VIT-
Negative-going input threshold
voltage, SENSE
TL7702B
TL7705B
Vhys
Hysteresis, SENSE (VIT+ - VIT-)
V
0.4
TA=25°e
TA = 25°C
TA = Full range:j:
2.48
2.53
2.58
2.505
2.53
2.555
4.5
4.55
4.6
2.48
2.53
2.58
4.45
4.55
4.65
TL7702B
Vee=3.6VtoI8V,
10
TL7705B
TA=25°e
30
Vres§
Power-up reset voltage
IOL at RESET = 2 mA, TAl = 25°C
II
Input current, RESIN
VI=0.4V toVee
TL7702B
UNIT
MAX
Vee-1.5
TL7702B
TL7705B
TYP
1
-0.1
II
Input current, SENSE
IOH
High-level output current, RESET
VO=laV,
See Figure 1
50
IOL
Low-level output current, RESET
VO=OV,
See Figure 1
-50
ICC
Supply current
VSENSE = 15 V,
RESIN;;,2V
Vee = lav
TA = Full range:j:
l.a
V
mV
-10
VI = Vref to18V
V
-2
3
3.5
V
!lA
!lA
!lA
!lA
mA
tAli electncal characteristics are measured With O.I-IlF capacitors connected at REF, eT, and Vee to GND.
:j: Full range for the e-suffix device is ooe to 70°C, full range for the I-suffix is -40°C to a5°e, and full range for the Q-suffix device is -40°C to
125°C.
§ This is the lowest voltage at which RESET becomes active.
switching characteristics, Vee
FROM
(INPUT)
TO
(OUTPUT)
Propagation delay time from
low-to-high-Ievel output
RESIN
RESET
Propagation delay time from
high-to-Iow-Ievel output
RESIN
PARAMETER
tpLH
tpHL
=5 V, CTopen, TA =25°C
tw
Effective pulse duration
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
TEST CONDITIONS
TL77xxBC, TL77xxBI
TL77xxBQ
MIN
UNIT
TYP
MAX
270
500
ns
270
500
ns
See Figures 1, 2, and 3
RESET
RESIN
See Figure 2
150
SENSE
See Figure 2
100
ns
75
RESET
See Figures 1 and 3
RESET
150
200
75
150
50
ns
ns
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
5-19
TL7702B, TL7705B, TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SlVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (unless otherwise noted)
TLn02BM, TLn05BM
PARAMETER
TEST CONDITIONSt
VOH
High-level output voltage, RESET
IOH=-16mA
VOL
Low-level output voltage, RESET
IOL=16mA
Vref
Reference voltage
Iref = 500 J.tA,
VIT-
Negative-going input threshold
voltage at SENSE input
TLn02B
TLn05B
TYP
TA = 25°C
TA = Full range:!:
2.48
2.53
2.58
2.505
2.53
2.555
4.5
4.55
4.6
2.48
2.53
2.58
4.45
4.55
4.65
TLn02B
VCC=3.6Vto18V,
10
TLn05B
TA = 25°C
30
Vhys
Hysteresis, SENSE (VIT + - VIT _)
Vres§
Power-up reset voltage
IOl at RESET = 2 mA,
II
Input current, RESIN
VI = 0.4 V to VCC
II
Input current, SENSE
High-level output current, RESET
TLn02B
VO= 18V
IOL
Low-level output current, RESET
VO=O
ICC
Supply current
TA=25°C
-0.1
VI = Vrefto VCC -1.5 V
1.8
RESIN;;,2V
1
V
J.tA
J.tA
J.tA
J.tA
-2
3
4
TA = Full range:!:
. .
tAli electncal charactenstlcs are measured with O.l-IlF capacitors connected at REF, CT, and VCC to GND.
V
-10
50
VSENSE = 15 V,
V
mV
-so
VCC=18V
UNIT
V
0.4
TA = 25°C
IOH
MAX
VCC-l.5
TLn02B
TLn05B
MIN
mA
:!: Full range for the M-suffix device is -55°C to 125°C.
§ This is the lowest value at which RESET becomes active.
switching characteristics, Vee
PARAMETER
tpHL
Propagation delay time from
low-to-high-Ievel output
Propagation delay time from
high-to-Iow-Ievel output
tw
Effective pulse duration
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
tpLH
=5 V, CT open, TA =25°C
FROM
(INPUT)
TO
(OUTPUT)
RESIN
RESET
TEST CONDITIONS
MIN
UNIT
TYP
MAX
270
500'
ns
270
500"
ns
See Figures 1, 2, and 3
RESIN
RESET
RESIN
See Figure 2
150
SENSE
See Figure 2
100
ns
75'
RESET
See Figures 1 and 3
RESET
'For products compliantto MIL-STD-883, Class B, these parameters are not production tested.
~TEXAS
5-20
TLn02BM, TL7705BM
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
150
200'
75
1SO"
SO'
ns
ns
TLn02B, TLn05B, TLn02BY, TLn05BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
electrical· characteristics over recommended operating conditions, TA = 25°C (unless otherwise
. noted)
PARAMETER
TEST CONDITIONST
VOH
High-level output voltage, RESET
'OH=-16mA
VOL
Low-level output voltage, RESET
'OL= 16mA
Vref
Reference voltage
'ref = 500 !tA
VITVhys
Vres:l:
Negative-going input threshold
SENSE
v~ltage,
Hysteresis, SENSE (V,T+ - VIT_)
TL7702Y, TL7705Y
MIN
TYP
MAX
V
Vee-1.5
0.4
2.48
2.53
2.58
TL7702Y
2.505
2.53
2.555
TL7705Y
4.5
4.55
4.6
TL7702Y
TL7705Y
10
Vee=3.6Vto18V
Power-up reset voltage
IOL at RESET = 2 mA
Input ClIrrent, RESIN
V,=0.4V to Vee
UNIT
V
V
mV
30
1
V
"
IOH
High-level output current, RESET
VO=18V,
See Figure 1
50
IOL
Low-level output current, RESET
VO=OV,
See Figure 1
-50
!tA
!tA
!tA
!tA
lee
Supply current
VSENSE = 15 V,
RESIN;,,2V
3
mA
"
Input current, SENSE
TL7702Y
. .
-10
-0.1
V,=Vref to18V
-2
1.8
tAli electncal charactenslics are measured with O.1-!J.F capacitors connected at REF, eT, and Vee to GND.
:I: This is the lowest voltage at which RESET becomes active.
switching characteristics,
Vee =5 V, CTopen, TA =25°C
FROM
(INPUT)
TO
(OUTPUT)
Propagation delay time from
low-to-high-Ievel output
RESIN
RESET
tPHL
Propagation delay time from
high-to-Iow-Ievel output
RESIN
tw
Effective pulse duration
PARAMETER
tpLH
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
TEST CONOmONS
TL7702Y,TL7705Y
MIN
UNIT
TYP
MAX
270
500
ns
270
500
ns
See Figures I, 2, and 3
RESET
RESIN
See Figure.2
150
SENSE
See Figure 2
100
ns
75
RESET
See Figures 1 and 3
RESET
150
200
75
150
50
ns
ns
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAbLAS. TEXAS 75265
5--21
TL7702B, TL7705B; TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
5V
RL
(see Note A)
RESET
e------,
-OOT-~ ~ t~_.,
------
I
RESET
15 pF
(see Note B)
RL
GND
(see Note A)
-=-
RESET OUTPUT CONFIGURATION
RESET OUTPUT CONFIGURATION
NOTES: A. For IOl and IOH, Rl'7 10 kn. For all switching characteristics, Rl = 511 Q.
B. This figure includes jig and probe capacitance.
Figure 1. RESET and RESET Output Configurations
I4--tw -.J
14-- tw ---.!
~
'\---~t-:.:v
---OV
V-
~==
RESIN
SENSE
WAVEFORMS
Figure 2. Input Pulse Definition
SENSE
vrr;1
_ _--to
Undefined
I
Voltage
Fault
I
\~ ir~-IT-+--~\ \
L _________ ..J__________________
I
I
OV
,t;-_ _t2:!.. ____
VIL
I:
\~\----~--------\
I
I
RESET
Figure 3. Voltage Waveforms
~TEXAS
5-22
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
VIH
TL7702B,TL7705B,TL7702BY,TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS037D - SEPTEMBER 1989 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
DEASSERTION TIME
ASSERTION TIME
20
.
c
va
LOAD RESISTANCE
LOAD RESISTANCE
700
I
VCC=5V
18 f- CT=0.1IlF
CL=10pF
TA=25D C
16
"-
I
til
E
va
1=
c
14
t!
:
12
I
10
..
500
c
RESETtr
I
~
i=
c
400
~
0
~
..
J..
I
I
\
8
300
200
100
RESETtf
'-
VCC=5V
CT=0.1IlF
CL=10pF
TA=25DC
600
0
6
0
2
10
4
6
8
RL - Load Resistance-Idl
0
2
Figure 4
FigureS
ASSERTION TIME
DEASSERTION TIME
va
va
LOAD CAPACITANCE
LOAD CAPACITANCE
36
2.1
.
..
~
1.9 1.7 -
C
I
til
1.5
c
1.3
:
1.1
~
E
i=
IS
~
i=
1
~I
I
/
/
0.9
0.5
0.3
50
75
100 125 150
CL - Load Capacitance - pF
175
200
lL
/
/
0.7
/
/ ' RESET tf and RESET tr
/
/
o
25
Figure 6
t
/
II
VCC=5V
CT=0.1IlF
RL = 4.71dl
TA=25 DC
I
25
10
4
6
8
RL - Load Resistance -Idl
50
75
100 125 150
CL - Load Capacitance - pF
175
200
Figure 7
For proper operation. both RESET and RESET should be terminated with resistors of similar value. Failure to do so may cause unwanted
plateauing in either output waveform during switching.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-23
TLn02B, TL7705B, TL7702BY, TL7705BY
SUPPLY VOLTAGE SUPERVISORS
SLVS0370 - SEPTEMBER 1989 -'REVISED AUGUST 1995
APPLICATION INFORMATION
vS
System Supply
81
'-L
2
Reset Input
(from system)
1
RT
0.111F ;::::[=:;
+'--
3
10 k!l ~
VCC
5
SENSE
RESET
To System
Reset
RESIN
REF
CT
CT
l
RESET
GND
6
r
To System
Reset
10kO ~
Figure 8. System Reset Controller With Undervoltage Sensing
When the TL770xB SENSE terminal is used to monitor Vcc, a current-limiting resistor in series with CT is
recommended. During normal operation, the timing capacitor is charged by the on-board current source to
approximately Vcc or an internal voltage clamp ('" 7.1-V zener), whichever is less. When the circuit is then subjected
to an undervoltage condition during which V CC is rapidly slewed down, the voltage on CT exceeds that on Vcc. This
forward biases a secondary path internally, which falsely activates the outputs. A fault is indicated when Vcc drops
below V(CT), not when VSENSE falls below VT-·
Texas Instruments performs a 100% electrical screen to verify that the outputs do not switch with 1 mA forced into
the CT terminal. Adding the external resistor, RT, prevents false triggering. Its value is calculated as follows:
V(CT) - VT _
RT
< 1 mA
where:
V(CT) = Vcc or 7.1 V, whichever is less
VT- = 4.55 V (nom)
value of series resistor required
RT
forVcc =5 V:
5 - 4.55 < 1 mA
RT
Therefore,
RT>450Q
Using a 20% tolerance resistor, RT Should be greater than 560 Q.
Adding this series resistor changes the duration of the reset pulse by no more than 10%. RT extends the discharge
of CT, but also skews the V (CT) threshold. These effects tend to cancel one another. The precise percentage change
can be derived theoretically, but the equation is complicated by this interaction and is dependent upon the duration
of the supply voltage fault condition.
Both outputs of the TL770xB should be terminated, with similar value resistors, even when only one is being used.
This prevents unwanted plateauing in either output waveform during switching, which may be interpreted as an
undefined state or delay system reset.
-!I1TEXAS
5-24
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
available features
•
•
Power-On Reset Generator
Automatic Reset Generation After Voltage
Drop
•
Complementary Reset Output
•
Precision Threshold Voltage
4.55 V ±120 mV
•
Low Standby Current .•• 20 ~
•
High Output Sink Capability ••. 20 mA
•
Reset Output Defined When Vee
Exceeds 1 V
•
Comparator Hysteresis Prevents Erratic
Resets
TYPICAL TIMING DIAGRAM
TYPICAL APPLICATION DIAGRAM
5V -
Vres
.....----~.-----.,
Vres
1 kQ
O~~-r-------+--~------~~~
RESET 1---+--System
Reset
GND
TL7757
O~~~
__________________
~~L-
description
The TL7757 is a monolithic supply voltage supervisor designed for use in microcomputer and microprocessor
systems. The supervisor monitors the supply voltage for undervoltage conditions. During power up, when the
supply voltage, Vee,attains a value approaching 1 V, the RESET output becomes active (low) to prevent
undefined operation. If at any time, the supply voltage drops below threshold voltage level (VIT-), the RESET
output goes to the active (low) level until the supply undervoltage fault condition is eliminated.
The e-suffix device is characterized for operation from O°C to 70 o e. The I-suffix device is characterized for
operation from -40 o e to 85°e. The M-suffix device is characterized for operation from -55°e to 125°e.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)
TO-226AA
(LP)
SOT-89
(PK)
CHIP FORM
(Y)
DOC to 70°C
TL7757CD
TL7757CLP
TL7757CPK
-40°C to 85°C
TL7757ID
TL7757ILP
TL7757IPK
-55°C to 125°C
TL7757MD
TL7757MLP
-
TL7757Y
D and LP packages are available taped and reeled. Add R suffix to device type (e.g., TL7757CDR).
Chips are tested at 25°C.
~TEXAS
COpyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-25
TLn57,TLn57V
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041D - SEPTEMBER 1991 - REVISED AUGUST 1995
LPPACKAGE
(TOP VIEW)
DPACKAGE
(TOP VIEW)
GJ
u
RESET[]a NC
VCC
2
7 NC
NC36NC
GND 4
5 NC
o
o
PKPACKAGE
(TOP VIEW)
GND
VCC
RESET
VCC
NC-No internal connection
GND RESET
GND is in electrical contact with the tab.
TL7757Y chip information
This chip, when properly assembled, displays characteristics similar to the TL7757C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(2)
VCC
(3)
'-----'___t>-------lt----.....-
t Backside
GND
of chip has an internal electrical
connection to pad 4.
CHIP THICKNESS: 11 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
~
~
~
1I11111111111111111111111111111111111111111111111111
TJmax= 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
NO BACKSIDE METALlZATION
~ThXAS
5-26
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
t
TLn57, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED AUGUST 1995
equivalent schematic '
R1
GND
ACTUAL DEVICE
COMPONENT COUNT
Transistors
27
Resistors
Capacitors
20
2
~ThXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5--27
TLnS7, TLnS7Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED. AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Vcc (see Note 1) ............................................. -0.3 V to 20 V
Offstate output voltage range (see Note 1) .................. ,~. . . . . . . . . . . . . . . . . . ... . . .. -0.3 V to 20. V
Output current, 10 ..........................•......•...................................... 30 mA
Operating free-air temperature range, TA: C-suffix ....................................... O°C to 70°C
I-suffix ...................................... -40°C to 85°C
M-suffix ................................... -55°C to 125°C
Continuous total power dissipation .................................... See Dissipation Rating Tables
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...... . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure 10 absolute-maximum-raled conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE 1 - FREE-AIR TEMPERATURE
PACKAGE
TAS25°C
POWER RATING
DERATING
FACTOR
DERATE
ABOVE
TA = 70°C
TA = 85°C
TA=I2s°C
0
725mW
5.8mW/oe
TA=25°e
464mW
3nmW
145mW
LP'
n5mW
6.2mW/oe
TA=25°e
496mW
403mW
155mW
PK
500mW
4.0mW/oe
TA=25°e
320mW
260mW
DISSIPATION RATING TABLE 2 - CASE TEMPERATURE
PACKAGE
TA S 25°C
POWER RATING
PK
3125 mW
DERATING
FACTOR
DERATE
ABOVE
TA
25mwre
=70"C
2000.mW
1625mW
,recommended operating conditions
C-SUFFIX
!-SUFFIX
MIN
MAX
MIN
7
1
1
Supply voHage, vee
M-8UFFIX
MAX
MIN
7
1
MAX
7
UNIT
V
High-level output VOltage, VOH
15
15
15
V
Low-level output current, IOL
20
20
20
mA
125
°C
Operating free-air temperature, TA
0
~TEXAS
INSTRUMENTS
5-:-28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
70
-40
85
-55
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041D - SEPTEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature
PARAMETER
VIT-
Negative-going input threshold
voltage at Vee
Vhys+
Hysteresis at Vee
VOL
Low-level output voltage
IOH
High-level output current
Vres§
Power-up reset voltage
ICC
Supply current
TEST CONDITIONS
TAt
TL7757C
MIN
TYP
MAX
25°C
4.43
4.55
4.67
Full range
4.4
25°C
40
Full range
30
Vee=4.3V
Vee=7V,
See Figure 1
VOH= 15V,
RL= 2.2 kQ,
Vee slew rate:;; 5 V/Jls
Vee=5.5V
60
70
0.8
Full range
0.8
25°C
1
Full range
1
25°C
0.8
1
Full range
1.2
1400
25°C
Vee = 4.3 V
50
0.4
25°C
IOL=20 mA,
4.7
UNIT
V
mV
V
!IA
V
2000
Full range
2000
Full range
40
!IA
t Full range IS ooe to 70°C.
:j: This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT _.
§ This is the lowest voltage at which RESET becomes active.
switching characteristics at TA = 25°C (unless otherwise noted)
PARAMETER
t
TEST CONDITIONS
TAt
Full range
tpLH
Propagation delay time, low-to-high-Ievel output
Vee slew rate s; 5 V/JlS,
See Figures 2 and 3
tpHL
Propagation delay time, high-to-Iow-Ievel output
See Figures 2 and 3
tr
Rise time
Vee slew rate :s; 5 VIJlS,
See Figures 2 and 3
tf
Fall time
See Figures 2 and 3
tw(min)
Minimum pulse duration at Vee for output response
25°C
25°C
TL7757C
MIN
TYP
3.4
2
0.4
25°C
Full range
JlS
1
1
0.05
JlS
5
5
Full range
UNIT
5
5
Full range
25°C
MAX
JlS
1
1
25°C
5
Full range
5
JlS
Jls
Full range IS ooe to 70°C.
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
5-29
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041D - SEPTEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature
PARAMETER
TEST CONDITIONS
VIT-
'Negative-going input threshold
voltage at Vee
Vhys:J:
Hysteresis at Vee
VOL
Low-level output voltage
IOL=20mA,
Vce=4.3V
IOH
High-level output current
Vee=7V,
See Figure 1
VOH= 15V,
V res§
Power-up reset voltage
RL=2.2 ko,
Vee slew rate S 5 VIlIS
ICC
Supply current
TL77571
TAt
MIN
TYP
MAX
25°C
4.43
4.55
4.67
Full range
4.4
25°C
40
Full range
30
60
70
0.8
Full range
0.8
25°C
1
Full range
1
25°C
0.8
1.2
1400
V
mV
V
IIA
1
Full range
25°C
Vee = 5.5 V
50
0.4
25°C
Vee=4.3V
4.7
UNIT
V
2000
Full range
2100
Full range
40
IIA
t Full range IS -40°C to 85°C.
:j: This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT _.
§ This is the lowest voltage at which RESET becomes active.
switching characteristics at TA = 25°C (unless otherwise noted)
PARAMETER
tpLH
Propagation delay time, low-to-high-Ievel output
tpHL
Propagation delay time, high-to-Iow-Ievel output
tr
Rise time
TEST CONDITIONS
TAt
Vee slew rate S 5 V/IlS,
See Figures 2 and 3
Full range
See Figures 2 and 3
Vee slew rate s 5 V/IlS,
See Figures 2 and 3
tl
Fall time
tw(min)
Minimum pulse duration at Vee I~r output response
See Figures 2 and 3
25°C
25°C
TL77571
MIN
TYP
3.4
2
25°C
Full range
lIS
5
5
0.4
1
0.05
1
Full range
UNIT
5
5
Full range
25°C
MAX
1
1
25°C
5
Full range
5
lIS
lIS
lIS
lIS
t Full range IS -40°C to 85°C.
)
~TEXAS
INSTRUMENTS
5--30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLnS7,TLnS7Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature
PARAMETER
TEST CONOmONS
VIT-
Negative-going input threshold
voltage at Vee
Vhys:(:
Hysteresis at Vee
VOL
Low-level output voltage
IOL=20mA,
Vee=4.3V
10H
High-level output current
Vee=7V,
See Figure 1
VOH=15V,
Vres!i
Power-up reset voltage
RL=2.2kn,
Vee slew rate:s; 5 V/Jls
ICC
Supply current
TAt
TL7757M
MIN
TYP
MAX
25°C
4.43
4.55
4.67
Full range
4.35
25°C
40
Full range
30
VCC=5.5V
60
50
70
0.4
25°C
0.8
Full range
0.8
25°C
1
Full range
1
25°C
0.8
1
Full range
1.2
1400
25°C
VCC=4.3V
4.7
UNIT
V
mV
V
I1A
V
2000
Full range
2500
Full range
40
I1A
t Full range IS -55°C to 125°C.
:(: This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT _.
§ This is the lowest voltage at which RESET becomes active.
switching characteristics at TA
=25°C (unless otherwise noted)
PARAMETER
TEST cONomONS
TAt
Full range
tpLH
Propagation delay time, low-to-high-Ievel output
VCC slew rate:s; 5 VlJlS,
See Figures 2 and 3
tPHL
Propagation delay time, high-to-Iow-Ievel output
See Figures 2 and 3
tr
Rise time
Vee slew rate:s; 5 V/JlS,
See Figures 2 and 3
tf
Fall time
See Figures 2 and 3
tw(min)
Minimum pulse duration at Vee for output response
25°e
25°C
TL7757M
MIN
TYP
MAX
3.4
5"
5"
2
Full range
25°e
0.4
25°C
Full range
JlS
l'
l'
0.05
JlS
5'
5'
Full range
UNIT
JlS
1"
1
25°C
5"
Full range
5'
JlS
Jls
'On products compliant to MIL-ST0-883, Class B, thiS parameter IS not production tested.
t Full range is -55°C to 125°e.
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • OALLAS. TEXAS 75265
5-31
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041D - SEPTEMBER 1991 - REVISED AUGUST 1995
electrical characteristics at TA = 25°C
PARAMETER
VIT-
Negative-going input threshold
voltage at Vee
Vl}yst
Hysteresis at Vee
TEST CONDITIONS
TYP
MAX
4.55
V
0.4
Low-level output voltage
IOL=20 rnA,
Vee=4.3V
IOH
High-level output current
Vee=7V,
VOH=15V,
Vres:t:
Power-up reset voltage
RL = 2.2 kn,
Vee slew rate :5 5 V/jlS
V
I1A
See Figure 1
V
0.8
1400
Vee =4.3 V
Supply current
UNIT
mV
50
VOL
lee
TL7757Y
MIN
I1A
Vee = 5.5 V
..
This IS the difference between positive-going Input threshold voltage, VIT+, and negative-going Input threshold voltage, VIT- .
t
:t: This is the lowest voltage at which RESET becomes active.
,
switching characteristics at TA = 25°C
PARAMETER
TEST CONDITIONS
tpLH
Propagation delay time, low-to-high-Ievel output
Vee slew rate:5 5 V/IlS,
See Figures 2 and 3
tpHL
Propagation delay time, high-to-Iow-Ievel output
See Figures 2 and 3,
tr
Rise time
Vee slew rate:5 5 V/jlS,
See Figures 2 and 3
tf
FaUtime
See Figures 2 and 3
~TEXAS
INSTRUMENTS
5-32
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TL7757Y
MIN
TYP
MAX
UNIT
3.4
Ils
2
IlS
0.4
jlS
0.05
jlS
TL7757,TL7757V
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED AUGUST1995
PARAMETER MEASUREMENT INFORMATION
Vcc
TLnS7
Pulse
Generator
+
OUT
S.SV
CL=1OOpF
(see Note A)
GND
NOTE A: Includes jig and probe capacitance.
Figure 2. Test Circuit for RESET Output
Switching Characteristics
Figure 1. Test Circuit for Output
Leakage Current
Vee
(seeNoteA)
4.3 V
VI:'~~
~
tpLH
__
RESET
.
.
~ J+- ~
I+-
tPHL
~O%I
190%
SO%
SO%
I
1
I I
tr ~
NOTE A:
VIT_
-L
1
I
l4--
1 10%
1 I
---.I 14-- tf
Vee slew rate S 5 lis
Figure 3. Switching Diagram
~TEXAS'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
5-33
TLnS7, TLnS7Y
SUPPLY VOLTAGE SUP,ERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041D - SEPTEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
table of graphs
FIGURE
Supply voltage
Vee
Supply current
ICC
loW-level output voltage
VOL
vs RESET output voltage
4
vs Supply voltage
5
vs Free-air temperature
6
vs Low-level output current
7
vs Free-air temperature
8
IOL
Output current
vs Supply voltage
9
VITVres
,Input threshold voltage (negative-going Vee)
vs Free-air temperature
10
Power-up reset voltage
vs Free-air temperature
11
Vres
Power-up reset voltage and supply voltage
vs Time
12
Propagation delay time
13
SUPPLY VOLTAGE
8
6
i
5
>is.
4
VB
RESET OUTPUT VOLTAGE
SUPPLY VOLTAGE
2
I
TA=25°e
10=0
7
>
I
~
c..
SUPPLY CURRENT
VB
I'
V
/
, ~ 1.5
I
~
0
0
>
V
3
3
ir1l
2
-
::I
til
I
I
TA=25°e
10=0
V
H
./
1
g
/l
o
o
0.5
\
2
3
4
5
6
7
o
o
RESET Output Voltage - V
2
3
4
5
6
Vee - Supply Voltage - V
Figure 4
FigureS
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
5-34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
SUPPLY CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
1.52
1.48
1
~
I
c3
~
8:
r
Vee=4.3V
1.44
1.4
./
1.36
1.32
1.28
:::
0.040
~ 0.036
I
.?
....-
I
RL=O
0.032
0.028
0.024
., . /
---
./"
L
LOW-LEVEL OUTPUT CURRENT
-
120
>
100
I
90
E
&
./
~
~
"5Do
"5
0
--
~
~
~ Vee=7V
~
~
i'......
0.020
-75 -50 -25
I ........... r--
,~V
0
25
50
-
75
--
100
TA - Free-Air Temperature - °e
r-
110
I
oJ
--
~
/
//
Vee=1 V
80
70
......:::
60
/Y
50
~
40
30
~
20
10
~
,/ '
o
E
vs
SUPPLY VOLTAGE
0.02
I
TA=25°e
IOL=20mA
I
0.018
,..,1"""""
100
20
OUTPUT CURRENT
FREE-AIR TEMPERATURE
>
V
Figure 7
vs
I
_
Vee =4.3 V
4
12
16
8
IOL - Low-Level Output Current - mA
LOW-LEVEL OUTPUT VOLTAGE
Vee = 4.3 V
V
/
Figure 6
120
/ /'
//
0
125
TA=25°e
0.016
I
II
III
~
~
0(
80
E
60
C
~
::I
"5
~
0
~
~
~
20
I
oJ
(J
"5
IOL=8mA
40
I
0.006
o
50
0.004
I
0.002
L
-50
0.01
O.ooa
IOL=1 mA
o
0.012
~
0
9
, -100
0.014
I
o
100
150
0.75
/
0.8
0.85
0.9
0.95
1.05
Vee - Supply Voltage - V
TA - Free-Air Temperature - °e
Figure 9
Figure 8
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-35
TL7757, TL7757Y
SUPPLY VOLTAGE SUPERVISOR
AND PRECISION VOLTAGE DETECTOR
SLVS041 D - SEPTEMBER 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERJSTICSt
INPUT THRESHOLD VOLTAGE
(NEGATIVE GOING Vee)
POWER-UP RESET VOLTAGE
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1000
4.6
.1
RL =2.2 ka
RL=O
4.59
>
I
>
J
~
II>
CI
4.56
-r---.-
.c
~
4.55
t:.
-
~
~
---
-
4.54
a
'~
I
4.57
~
950
E
4.58
~ 4.53
i
II>
II:
Q.
;:)
.:.
J.
I
t!. 4.52
'>"
900
850
800
750
"
700
4.51
4.5
-100
100
-50
o
50
TA - Free-Air Temperature -·e
650
600
-100
150
""
"\
I!!
>
~
r'\.
-50
o
50
100
TA - Free-Air Temperature - ·e
Figure 10
150
Figure 11
POWE.R-UP RESET VOLTAGE
AND SUPPLY VOLTAGE
vs
PROPAGATION DELAY TIME
TIME
>
2
6
I
J
~
TA=25·e
RL = 2.2 kQ
ia!
J
/
~
~
Ii
J
4
.5
Vee
5
1.5
i
I
TA=25·e
RL = 2.2 kfi
VI
:;-
Vee
~I
J
R~ET
\
~
1..
3
-
RESET
2
0
I
g-0.5
o
>
Ii
~
-1
-1
o
0.5
1.5
2
t-Time-1.lS
2.5
3
o
2
Figure 12
4
6
8
10 12
t-Time-1.lS
14
16
Figure 13
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TL7759, TL7759Y
SUPPLY VOLTAGE SUPERVISORS
SLVS042B - JANUARY 1991 - REVISED AUGUST 1995
o OR P PACKAGE
• Power-On Reset Generator
• Automatic Reset Generation After Voltage
Drop
• Precision Input Threshold Voltage
4.55 V ±120 mV
(TOP VIEW)
N c u e RESET
NC 2
7 RESET
NC 3
6 NC
GND
• Low Standby Current ... 20 J.LA
• Reset Outputs Defined When Vee
Exceeds 1 V
• True and Complementary Reset Outputs
• Wide Operating Temperature Range
O°Cto 70°C
• Wide Supply Voltage Range ... 1 V to 7 V
4
5
VCC
NC - No internal connection
description
The TL7759C is a monolithic supply voltage supervisor designed for use as a reset controller in microcomputer
and microprocessor systems. The supervisor monitors the supply voltage for undervoltage conditions. During
power-up, when the supply voltage, Vcc, attains a value approaching 1 V, the RESET and RESET outputs
become active (high and low, respectively) to prevent undefined operation. If at any time the supply voltage
drops below the input threshold voltage level (V IT_ ), the reset outputs go to the reset active state until the supply
voltage has returned to its nominal value.
The TL7759C is characterized for operation from DOC to 7DoC.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
Vlomax
AT 25°C
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
O°C to 70°C
2.5mV
TL7759CD
TLC7759CP
CHIP
FORM
(V)
TL7759Y
The 0 packages are available taped and reeled. Add R suffix to deVice type (e.g.,
TL7759CDR). Chips are tested at 25°C.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-37
TL7759, TL7759Y
SUPPLY VOLTAGE SUPERVISORS
SLVS042B - JANUARY 1991 - REVISED AUGUST 1995
functional block diagram
r---------e---------~~~5 Vcc
RESET
RESET
L-__~----~--------~~_4~ GND
timing diagram
VCC
Output Undefined
Output Undefined
for Vcc·less than 1 V
TL7759Y chip information
This chip, when properly assembled, displays characteristics similar to the TL7759C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
GND
----i
1
VCC - - 1 2
4 1 - - RESET
3
~
RESET
'-------'
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150 C
a
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
TERMINALS 1, 2, 3, AND 6 ARE NOT
CONNECTED.
~
~
~
/111111111/111111111/111111111/111111111/11111111111
~TEXAS
INSTRUMENTS
5--38
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
TLnS9, TL77S9Y
SUPPLY VOLTAGE SUPERVISORS
SLVS042B -JANUARY 1991 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ........................................................... 20 V
Off-state output voltage range: RESET voltage ...................................... -0.3 V to 20 V
RESET voltage ...................................... -0.3 V to 20 V
Low-level output current, loL 5 V/IlS.
electrical characteristics, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
I
Low-level output voltage
RESET
Input threshold voltage (negative-going Vee)
Vee=4.3V
VITVrest
Power-up reset voltage
RL = 2.2 k!l
Vhvs'l'
Hysteresis at Vee input
ICC
Supply current
VOL
Vcc=4.3V,
IOL=24mA
No load
*
TLnS9Y
MIN
TYP
~TEXAS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
0.4
V
4.55
V
O.B
V
50
mV
1400
ItA
t This is the lowest voltage at which RESET becomes active, Vee slew rate;" 5 V/IJS.
This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold vo~age, VIT,...
INSTRUMENTS
MAX
TL7759, TL7759Y
SUPPLY VOLTAGE SUPERVISORS
SLVS042B-JANUARY 1991- REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
15V
4.8V
VCC
(see Note A)
4.3 V
tpLH
-+I
RESE''D----'
+
7V
I
TLn59C
-+:
I+- tpHL
___ .!r----~I 90%
I 50%
1:10%
II
-+I I+-tf
NOTE A: Vee slew rate> 5 V/!1S.
Figure 1. Test Circuit for Output Leakage Current
Pulse
Generator
~
Figure 2. Switching Diagram
I
VCC
Pulse
Generator
TLn59C
RESET
GND
RL = 1 kf.l ;: ::::: CL= 100 p,"*
J.
tel Includes jig and probe capacitance.
teL Includes jig and probe capacitance.
Figure 3. Test Circuit for RESET Output
Switching Characteristics
Figure 4. Test Circuit for RESET Output
Switching Characteristics
APPLICATION INFORMATION
1T
5 V -.....- - - - , ' 5
0.111F
VCC
7
RESET 1--''--._- System Reset
TLn59C
RESET~
1 kf.l
GND
4_----'
~
Figure 5. Power Supply System Reset Generation
-!!1TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DAlLA;. TEXAS'75265
5-41
5-42
TL7770-5, TL7770-12, TLmO-15
TL7770-5Y, TLmO-12Y, TL7770-15Y
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
• Power-On Reset Generator
OW, J, OR N PACKAGE
(TOP VIEW)
• Automatic Reset Generation After Voltage
Drop
• RESET Defined When V CC Exceeds 1 V
• Wide Supply Voltage Range ••. 3.5 V
to 18 V
• Precision Overvoltage and Undervoltage
Sensing
• 250-mA Peak Output Current for Driving
SCRGates
lRESIN
lCT
lRESET
lRESET
lVSU
lVSe
lSCR DRIVE
Vee
2RESIN
2CT
2RESET
2RESET
2VSU
2vse
2SCR DRIVE
3
4
7
9
• 2-I1lA Active-Low SCR Gate Drive for False
Trigger Protection
FKPACKAGE
(TOP VIEW)
• Temperature-Compensated Voltage
Reference
z
Cii
IZCii
I
~e:z~gj
• True and Complementary Reset Outputs
• Externally Adjustable Output Pulse
Duration
I-WOOW
1RESET
1RESET
NC
1VSU
lvse
description
4
3 2
1 20 19
18
5
17
6
16
2CT
2RESET
NC
2RESET
2VSU
The TL7770 is a monolithic integrated circuit
7
15
system supervisor designed for use as a reset
8
14
9 1011 1213
controller in microcomputer and microprocessor
power supply systems. This device contains two
WOOWO
independent supply-voltage supervisors that
~~Z~~
monitor the supplies for overvoltage and under~
~C\I
c:::
c:::
voltage conditions at the VSO and VSU terminals
o
0
en
en
respectively. When VCC attains the minimum
C\I
voltage of 1V during power-up, the RESET output
NC-No internal connection
becomes active (low). As VCC approaches 3.5 V,
the delay timer function activates latching RESET
and RESET active (high and low, respectively) for a time delay, ~, after system voltages have achieved normal
levels. Above VCC = 3.5 V, taking RESIN low activates the time delay function, RESET and RESET, during
normal system voltage levels. To ensure that the microcomputer system has reset, the outputs remain active
until the voltage at VSU exceeds the threshold value V IT+ for a time delay, td, which is determined by an external
timing capacitor such that
~ '" 20 x 103 x capacitance
where
~
is in seconds and capacitance is in farads.
The overvoltage-detection circuit is programmable for a wide range of user designs. During an overvoltage
condition, an internal silicon-controlled rectifier (SCR) is triggered, providing 250-mA peak instantaneous
current and 25-mA continuous current to the SCR gate drive terminal, which can drive an external high-current
SCR gate or an overvoltage warning circuit.
The TL7770C is characterized for operation from O°C to 70°C. The TL7770M series is characterized for
operation from - 55°C to 125°C. The TL7770Q series is characterized for operation from - 40°C to 125°C.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-43
TLmo-s, TLn70-12, TL7nO-1S \
T17no-SY, TL7nO-12Y, TLn70-1SY
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
CHIP CARRIER
(FK)
(OW)
O°C to 70°C
TL7770-SCDW
TL7770-12CDW
TL7770-1SCDW
-40°C to 12SoC
TL7770-5QDW
TL777Q-12QDW
TL777Q-1SQDW
-5SoC to 125°C
-
CERAMIC DIP
(J)
-
-
-
CHIP FORM
(Y)
-
TL7770-SCN
TL7770-12CN
TL7770-1SCN
TL7770-SY
TL7770-12Y
TL777Q-1SY
-
TL777Q-SQN
TL777Q-12QN
TL7770-1SQN
-
-
TL7770-5MFK
TL7770-12MFK
TL7770-15MFK
PLASTIC DIP
(N)
TL7770-5MJ
TL777Q-12MJ
TL777Q-1SMJ
-
functional block diagram {each channel}
VCC -------.-------------.----------------------~--~
~ 651lA (TYP)
CT-----+-+------4------.---------.~~
RESET
RESET
VSU
R1
R2
RE~N-----+-------------J
VSO--------------------------------1
1 VSU
2VSU
DEVICE
TL7770-5
TL777Q-12
TL777Q-15
R1t
R2t
Rl
24k(l
70kQ
90kO
10kQ
10kQ
10kQ
Short
Short
Short
R2
Open
Open
Open
SCRDRIVE
t The values listed are nominal.
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS. TEXAS 75265
TLn70-5, TLn70-12, TLn70-15
TLn70-5Y, TLn70-12, TLn70-15Y
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D-OCTOBER 1987-REVISEDOCTOBER 1995
. TL7770-xxY chip information
These chips, when properly assembled, display characteristics similar to the TL7770-xxC. Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be
mounted with conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'l'j'l'l'l'l'l'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
1RESIN
lCT
1RESET
1RESET
1VSU
lVSO
lSCR DRIVE
GND
(1)
(16)
(2)
(15)
(3)
(14)
(4)
(13)
(5)
TL7770-xxY
(12)
(6)
(11)
(7)
(10)
(8)
(9)
VCC
2RESIN
2CT
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
2RESET
TJmax=150°C
2RESET
TOLERANCES ARE ±10%.
2VSU
ALL DIMENSIONS ARE IN MILS.
2VSO
2SCRDRIVE
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TeXAS 75265
5-45
TLmO-5, TLn7D-12, TL777D-15
TLn70-5Y, TLn70-12Y, TL7770-15V.
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
typical timing diagram
VIT+-~
VIT---~
I'
I
I
L.---.t- .lei
I
--~-..-:--~--~-..:.--r_~ 1'--_-'
VSU
lei
14
I
~I
I
I
I
I
I
I
I
I
I
I
I
I
) I
-+-----~ lei
I
I
Vce = 1 V (TYP)
1 - - - - VOH
r
......_ _01.-
Undefined Operation
for Vec Less Than t V
~----------~--
,...-----'1I ------
I
I
I
I
I
I
I
I
I
VSO
SCR
DRIVE
..
i
t
VOH
VOL
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
"
Supply voltage, Vee (see Note 1) ' ............................. L • • . • ; . . : . . . . . . • • • • • • • • • • •••• 20 V
Input voltage range, VI: 1VSU, 2VSU, 1VSO, and 2VSO (see Note 1) ...•••.............. -0.3 V to 18 V
Low-level output current (1 RESET and 2RESET), IOL ......................................... 20 mA
High-level output current (1 RESET and 2RESET); IOH .. . . . . . . . . . . . . • . . . . . . .. . . . . . . . . . . . . . .. -20 mA
Continuous total power dissipation ..•........ , ................... ;.. . .. See Dissipation Rating Table
Operating free-air temperature range, TA: lL7770_C .................................... O°C to 70°C
TL777Ci_M ................................. -55°C to 125°C
TL7770-Q ................................. -40°C to 125°C
Operating virtual junction temperature range, TJ . ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 150°C
Storage temperature range, Tstg .......•.................•.......... ,.............. ~5°C to 150°C
Case temperature for 60 seconds: FK package. . . . . .. . . . . . .. . . . . . . . . . . .. . . . . . . . . . . . . . . . .. ... 260°C
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds: OW or N package ... . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 in) from case for 60 seconds: J package ....................... 300°C
t Stresses beyond those listed under"absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indiCated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the networi< ground terminal.
DISSIPATION RATING TABLE
PACKAGE
TA~25°e
POWER RATING
DERATING
FACTOR
TA=70oe
POWER RATING.
TA=125°e
POWER RATING
205mW
OW
1025mW
8.2mW/oC
656mW
533mW
FK
1375mW
11.0mW/oC
880mW
715mW
275mW
J
N
1375mW
11.0mW/oC
880mW
715mW
275mW
1150mW
9.2mW/oC
736mW
598mW
230mW
~TEXAS
5-46
TA=85°e
POWER RATING
INSTRUMENTS
POST OFFICE BOX 655303. DAlLAS. TEXAS 75265
TL7770-S, TL7770-12, TL7770-1S
TL7770-SY, TL7770-12, TL7770-1SY
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
recommended operating conditions
UNIT
MIN
MAX
3.5
18
V
0
18
V
5
V
High-level input voltage range, VIH, 1RESIN, 2RESIN
2
18
V
Low-level input voltage range, VIL, 1RESIN, 2RESIN
0
0.8
V
Supply voltage, VCC
Input voltage range, VI (see Note 2)
1VSU, 2VSU, 2VSO, 1VSO
Output voltage (1CT and 2CT), Vo
Output sink current (1 CT and 2CT), 10
High-level output current (1 RESET and 2RESET), 10H
50
IlA
-16
mA
Low-level output current (1 RESET and 2RESET, 10L
16
mA
Continuous output current (1 SCR DRIVE and 2SCR DRIVE), 10
25
mA
10
I1F
Timing Capacitor, CT
Operating free-air temperature, TA
TLn70C Series
0
70
TL7nOM Series
-55
125
TL7nOQ Series
-40
125
..
..
°c
NOTE 2: The algebraiC convention, In which the least positive (most negative) value IS designated minimUm, IS used In thiS data sheet for logic
voltage levels only.
""TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-47
TLn70-5, TL7nO-12, TL7770-15
TL7nO-5Y, TLn70-12Y,TLn7Q-15Y
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
electrical characteristics over recommended ranges of supply voltage, input. voltage, output
current, and free-air temperature (unless otherwise noted)
supply supervisor section
TEST CONDITIONST
PARAMETER
TL777o-5C, TL7770-12C
TL7770-15C, TL7770-5Q
TL7770~12Q, TL777o-15Q
TYP'i'
MIN
VOH
VOL
High-level output voltage
Low-level output voltage
RESET
IOH=-15mA
Vee-1.5
SeRDRIVE
IOH=-20mA
Vee-1.5
RESET
4.5
TL7770-12 (12-V sense, 1VSU)
TA=25°e
TL7770-15 (15-V sense, lVSU)
VIT-
Undervoltage input thresh010 at VSU (negative-going)
TL7770-5, TL7770-12, TL7770-15
(programmable sense, 2VSU)
TL7770-5 (5-V sense, lVSU)
TA = MIN to MAX
TL7770-15 (15-V sense, 1VSU)
TL7770-5, TL7770-12, TL7770-15
(programmable sense, 2VSU)
Vhys
VT
Hysteresis at VSU
(VIT+-VIT-)
Overvoltage threshold at
VSO
V
4.55
10.8
10.9
11.02
13.64
13.77
1.485
1.5
1.515
4.64
10.68
11.12
13.36
13.91
1.47
1.53
TL7770-5 (5-V sense, lVSU)
15
TL7770-12 (12-V sense, lVSU)
36
TA=25°C
TL7770-15 (15-V sense, lVSU)
V
mV
45
TL7770-5, TL7770-12, TL7770-15
(programmable sense, 2VSU)
V
4.6
13.5
4.46
TL7770-12 (12-V sense, 1VSU)
MAX
0.4
IOL=15mA
TL7770-5 (5-V sense, lVSU).
UNIT
5
TL7770-5, TL7770-12, TL7770-15 TA = 25°C
(VSO)
TA = MIN to MAX
RESIN
VI = 5.5 V or 0.4 V
VSO
VI =2.4V
II
Input current
IOH
High-level output current
RESET
VO= 18V
IOL
Low-level output current
RESET
IOH
Peak output current
SeRDRIVE
VO=O
Duration - 1 ms
2.53
2.58
2.48
2.63
2.68
-10
0.5
2
50
-50
250
V
!!A
!!A
!!A
rnA
..
t For conditions shown as MIN or MAX, use the appropriate value specified in the recommended operating conditions .
:I: Typical values are at Vee = 5 V, TA = 25°C.
total device
PARAMETER
TEST CONDITIONST
TL777o-5C, TL7770-12C
TL7770-15C, TL777o-5Q
TL7770-12Q, TL7770-15Q
TYP;
MIN
Vres§
ICC
Power-up reset voltage
Supply current
..
Vee=VSU
lVSU = 18 V,
2VSU = 2 V,
1RESIN and 2RESIN at Vee,
1VSO and 2VSO at 0 V
0.8
..
~TEXAS
INSTRUMENTS
5-48
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1
6.5
..
t For conditions shown as MINor MAX, use the appropriate value specified In the recommended operating condlllOns .
:I: Typical values are at Vee = 5 V, TA = 25°C.
§ This the lowest voltage at which RESET becomes active.
MAX
V
5
TA = 25°C
TA = MIN to MAX
UNIT
rnA
TL7770-S, TL7770-12, TL7770-1S
TL7770-SY, TL7770-12, TL7770-1SY
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCljOBER 1995
electrical characteristics over recommended ranges of supply voltage, input voltage, output
current, and free-air temperature (unless otherwise noted)
supply supervisor section
TEST CONDITIONST
PARAMETER
TL777o-SM, TL7770-12M
TL7770-1SM
MIN
VOH
High-level output voltage
VOL
Low-level output voltage
RESET
IOH=-15mA
Vee-1.5
SeRDRIVE
IOH=-20mA
Vee-1.5
RESET
10L= 15 mA
TL7770-5M (5-V sense, 1VSU)
TA=25°e
TL7770-15M (15-V sense, tvSU)
VIT- Undervoltage input
threshold at VSU
(negative-going)
TL7770-SM, TL7770-12M. TL7770-15M
(programmable sense. 2VSU)
TL7770-5M (5-V sense. lVSU)
V
4.S5
TL7770-12M (12-V sense. lVSU)
TA
=MIN to MAX
TL7770-5M. TL7770-12M. TL7770-15M
(programmable sense. 2VSU)
10.9
11.07
13.5
13.64
13.866
1.485
1.5
1.527
4.646
10.62
11.12
13.36
13.916
VT
Hysteresis at VSU
(VIT+-VIT-)
Overvoltage threshold
atVSO
II
Input current
10H
High-level output current
V
1.542
1.47
15
TL7770-5M (5-V sense. tvSU)
Vhys
V
4.632
10.8
4.4
TL7770-15M (IS-V sense. lVSU)
UNIT
MAX
0.4
4.5
TL7770-12M (12-V sense, lVSU)
TYP;
TL7770-12M (12-V sense. lVSU)
36
TA = 25°C
TL7770-15M (15-V sense. lVSU)
mV
45
TL7770-5M. TL7770-12M. TL7770-15M
(programmable sense. 2VSU)
5
TL7770-5M. TL7770-12M. TL7770-15M
(VSO)
TA = 25°C
TA
=MIN to MAX
RESIN
VI = 5.5 V or 0.4 V
VSO
VI=2.4 V
RESET
Vo=Vee
10L
LOW-level output current
RESET
VO=1
10H
Peak output current
SeRDRIVE
Duration = 1 ms
2.53
2.58
2.63
2.68
2.48
-10
O.S
2
50
-50
V
tJ.A
tJ.A
tJ.A
mA
250
t For conditions shown as MIN or MAX. use the appropriate value specified in the recommended operating conditions.
tTypical values are at Vee = 5 V. TA = 25°C.
total device
PARAMETER
TEST CONDITIONST
TL7770-SM, TL777o-12M
TL777o-1SM
MIN
VreS§
ICC
Power-up reset voltage
Supply current
Vee
VOL =0.4 V. 101. = 1 mA
tvSu 18V.
2VSU =2V.
1RESIN and 2RESIN at Vee.
1VSO and 2VSO at 0 V
TA=25°e
TYP;
0.8
UNIT
MAX
1
V
S
mA
TA = MIN to MAX
6.5
t For conditions shown as MIN or MAX. use the appropriate value specified in the recommended operating conditions.
tTypical values are at Vee = S V. TA = 2Soe.
~TEXAS
INSTRUMENTS
POST OFFICE
aox 655303 •
OALLAS, TEXAS 75265
5-49
TL7no-s, TL7no-12, TL7770-15 ~
TLmo-5Y, TL7770-12Y, TLn70-15Y
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
electrical characteristics over recommended ranges of supply voltage, input voltage, and output
current (unless otherwise noted)
,
.
supply supervisor section
PARAMETER
TEST CONDITIONS
TL777D-5Y, TL7770-12Y
TL777D-15Y
TYPT
MIN
TLn70-5 (5-V sense, 1VSU)
VIT-
TL7770-12 (12-V sense, lVSU)
Undervoltage input
threshold at VSU
(negative-going)
TA=25 oe
TL7nO-15 (15-V sense, lVSU)
TL7nO-5, TL7770-12, TLn70-15
(programmable sense, 2VSU)
4.5
4.55
4.6
10.8
10.9
11.02
13.5
13.64
13.77
1.485
1.5
1.515
TLn70-5 (5-V sense, lVSU)
Vhys
V
15
TLn70-12 (12-V sense, lVSU)
Hysteresis at VSU
(VIT+ - VIT-)
UNIT
MAX
36
TA = 25°C
TLn70-15 (15-V sense, lVSU)
mV
45
TL7nO-5, TL7nO-12, TL7770-15
(programmable sense, 2VSU)
5
VT
OvervoHage threshold at
VSO
TL7770-5, TL7nO-I2, TLn70-15
TA = 25°C
(VSO)
II
Input current
VSO
2.53
2.58
2.63
V
IIA
0.5
VI =2.4V
tTYPlcal values are at Vee = 5 V, TA = 25°C.
total device
TLn70-5Y, TL777D-12Y
TL7nD-15y.
TEST CONDITIONS
PARAMETER
MIN
Vres'l=
Power-up reset voltage
ICC
Supply current
Vec
lVSU = 18 V,
2VSU = 2 V,
1RESIN and 2RESIN at Vec,
lVSO and 2VSO at 0 V
TYPT
UNIT
MAX
0.8
VOL = 0.4 V, IOL= 1 rnA
V
5
TA = 25°C
rnA
tTYPlcal values are at Vec = 5 V, TA = 25°C.
:j: This the lowest voltage at which ('lESET becomes active.
switching characteristics,
Vee = 5 V, CT open, TA = 25°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
MIN
TYP
MAX
UNIT
tpLH
Propagation delay time, low-to-high-Ievel output
RESIN
RESET
270
SOO'
ns
tpHL
Propagation delay time, high-to-Iow-Ievel output
RESIN
RESET
270
500'
ns
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
tw(min)
Minimum effective pulse duration
RESET
See Figure 1
150
75
RESET
50'
RESIN
See Figure 2(a)
150
VSU
See Figure 2(b)
100
'On products compliant to MIL-STD-883, Class B, thiS parameter IS not production tested.
~TEXAS
5-50
75'
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
ns
ns
ns
TL7nO-5, TLn70-12, TL7nO-15
TL7nO-5Y, TL7nO-12, TL7nO-15Y
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
5V
5V
,
VCC
---- 1-1
511 Q
RESET
I
I
_ _ _ _ _ .J
I
I
I
1
.J
15pF
RESET ...----,
(see Note A)
511
15 pF
Q
(see Note A)
GND
-=-
RESET OUTPUT CONFIGURATION
RESET OUTPUT CONFIGURATION
NOTE A: This includes jig and probe capacitance.
Figure 1. RESET and RESET Output Configurations
~tw-1
\-----1--- :v
- - - - OV
(8) RESIN
(b)VSU
WAVEFORMS
Figure 2. Input Pulse Definition
~TEXAS
INSTRUMENTS
. POST OFFICE BOX 655303 • DAI.l.AS. TEXAS 75265
5-51
TL7770-S, TL777D-12; TLmO-1S
TL777D-SY, TL7770-12Y, TL777D-1SY
DUAL POWER-SUPPLY SUPERVISORS
SLVS019D - OCTOBER 1987 - REVISED OCTOBER 1995
APPLICATION INFORMATION
vS
System Supply
16I
~ 1VSU
1
Reset Input
(from system)
R,-
(see Note
B) . 2
.A,v-
;::
::::::er
10
Vee
1RESET
4
"
To System
Reset
1RESIN
leT
1RESET
GND
1
3
To SyStem
Reset
10 k!l
8
l
NOTES: A. Terminal numbers shown are for the OW, J, and N packages.
B. When VCC and 1VSU are connected to the same point, it is recommended that series resistance (RT) be added between the time
delay programming capacitor (CT) and the vo~age supervisor device terminal (1 CT).
The suggested RT values is given by:
RT >
V -V
I
T- , where VI ,,; (the lesser of 7.1 V or V )
I-3
S
1 x 10
When this series resistor is used, the td calculation is as follows:
1.3 t
d
=
[(6.5~) x 10-5) x RT]
6.5 x 10-5
xC
T
Figure 3. System Reset Controller With Undervoltage Sensing
~TEXAS
5-52
INSTRUMENTS
POST OFFICE BOx 655303 • DALlAS, TEXAS 75265 .
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B- DECEMBER 1994- REVISED AUGUST 1995
o OR P PACKAGE
• Power-On Reset Generator
(TOP VIEW)
• Automatic Reset Generation After
Voltage Drop
CONTROL[]8 VDD
RESIN 2
7 SENSE
CT 3
6 RESET
GND 4
S RESET
• Precision Voltage Sensor of 1.5% Maximum
Accuracy, Compensated Over Full
Temperature Range
• Programmable Delay Time By External
Capacitor
• Minimum Supply Voltage of 2 V
• Defined RESET Output from Voo ~1 V
• Power-Down Control Support for Static
RAM With Battery Backup
• Maximum Supply Current of 251JA
• Power Saving Totem-Pole Outputs
description
The TLC7705 is a micropower supply voltage supervisor designed for reset control, primarily in microcomputer
and microprocessor systems.
During power·on, RESET is asserted when VDD reaches 1 V. After minimum VDD is established, the circuit
monitors SENSE voltage and keeps the reset outputs active as long as SENSE voltage (VI (SENSE» remains
below the threshold voltage. An internal timer delays return of the output to the inactive state to ensure proper
system reset. The delay time, td, is determined by an external capacitor:
td
=21 x CT
where
CT is in Ilf
td is in ms
The TLC7705 has a fixed SENSE threshold voltage set by an internal voltage divider. When SENSE voltage
drops below the threshold voltage, the outputs become active and stay in that state until SENSE voltage returns
to above threshold voltage.
The TLC7705 is a low-power enhancement of the TL7705A. When CONTROL is tied to GND, RESET will act
as active high. The voltage monitor contains additional logic intended for control of static memories with battery
backup during power failure. By driving the chip select (CS) of the memory circuit with the RESET output of the
TLC7705 and with the CONTROL driven by the memory bank select signal (CSH1) of the microprocessor (see
Figure 4), the memory circuit is automatically disabled during a power loss. (In this application the TLC7705
power has to be supplied by the battery.)
The TLC7705 is characterized for operation over a temperature range of -40°C to 85°C.
AVAILABLE OPTIONS
TA
THRESHOLD
VOLTAGE
-40°C to 8SoC
4.SSV
PACKAGED DEVICES
SMALL OUTLINE
(D)
TLC770SID
PLASTIC DIP
(P)
TLC770SIP
CHIP FORM
(V)
TLC770SY
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC770SIDR).
The chip form is tested at 2SoC.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-53
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B.,. DECEMBER 1994 - REVISED AUGUST 1995
FUNcnON TA",LE
CONTROL
RESIN
RESET
RESET
L
L
False
H
L
L
L
True
H
L
L
H
False
H
L
H
True
Lt
L
Ht
H
t
logic sYl1lbol*
VI(SENSE)
>VIT+
L
False
H
SENSE
L
True
H
L
H
H
False
H
H
H
True
H
L
Ht
n
3
CT
COMPE
,S S1
1 .
1
CONTROL
..n..
CX
~1
2
~1
~1
Z1
Z2
Z3
5
6
RESET
3
RESET and RESET states shown are valId for t > !d.
:I: This symbol is in accordance with ANSI/IEEE Std 91-1984 and
lEe Publication 617-12.
functional block diagram
VDD
CONTROL~1~----~~--~--------------~~----------~
RESET!
R1
7 910kn'll
SENSE --'--'VI.fIr-..-+----+---t
R2
290kn'll
GND
3
CT
§ Outputs are totem-pole configuration. Extemal pullup or pulldown resistors are not required.
'II Nominal value
timing diagram
Threshold Voltagee
Vres -
1
14
1
14
1
1
1
Output
Undefined
1
1
1
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST 1995
TLCn05Y chip information
This chip, when properly assembled, displays characteristics similar to the TLC7705. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
-;:
-::
-;:
-;:
CONTROL
-;:
RESIN
-;:
-;:
CT
-::
GND
-;:
(1)
(8)
(2)
(7)
TLC7705Y
(3)
(6)
(4)
(5)
VDD
SENSE
RESET
RESET
-;:
-;:
-;:
-=
-=
-=
-;:
-;:
-;:
-;:
-;:
CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJmax
-;:
=150°C
TOLERANCES ARE ±10%
-;:
-;:
ALL DIMENSIONS ARE IN MILS
-;:
-;:
-;:
-;:
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-55
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST1995
absolute maximum ratings over operating free-air temperature {unless otherwise noted)t
Supply voltage, Voo (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage range (see Note 1) .................................................... -0.3 V to 7 V
Maximum low output current, IOL ........................................................... 10 mA
Maximum high output current, IOH ....................................................... -10 mA
Input clamp current, 11K (VI < 0 or VI> Voo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ±10 mA
Output clamp current, 10K (Vo < 0 or Vo > Voo) ........................................... ±10 mA
Continuous total dissipation . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating free-air temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Stresses beyond those listed under "absolute maximum ratings' may cause penniment damage to the de~ice. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure tei absolute-maximum-rated conditions for extended perio(ls may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
t
DISSIPATION RATING TABLE
PACKAGE
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
TA=85°C
POWER RATING
D
725mW
5.8mW/"C
3nmW
p
1000mW
8.0mWloC
520mW
recommended operating conditions at specified temperature range
I .. ,
Supply voltage, VDD
TIming capacitor,
MIN
MAX
2
6
V
100
IlF
6
V
Ct (see Note 2)
Input voltage, VI
0
High-level input voltage at RESiN and CONTROL:!:, VIH
Low-level input voHage at RESIN and CONTROL:!:, VIL
High-level output current, IOH
Low-level output current, IOL
High-level input pulse duration at SENSE
VDD=2V
1.7
VDD '" 2.7 V
VDD=4.5V·
1.8
V
2
VDD=2V
0.3
VDD=2.7V
0.4
VDD=4.5V
0.8
VDD=2.7V
-2.5
VDD=4.5V
-3
VDD=2.7V
2.5
VDD=4.5V
3
V
rnA
rnA
20
Low-level input pulse duration at SENSE
2
High-level input pulse duration at RESIN
20
Low-level input pulse duration at RESIN
2
Input transition rise and fall rate at RESIN and CONTROL, /WaV
Operating free-air temperature range, TA
-40
:!:To ensure a low supply current, VIL should be kept <0.3 V and VIH > VDD -0.3 V.
NOTE 2: Limited by the leakage current of the capacitor
~TEXAS
5-56
UNIT
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Ils
100
nsIV
85
°C
TLC7705, TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions (see Note 3) (unless otherwise
noted)
.
PARAMETER
VOH
High-level output voltage
TEST CONDITIONS
IOH=-20!1A
IOH=-3mA
TLC77051
MIN
VOO=2V
1.8
VOO=2.7V
2.5
VOO=4.5V
4.3
VOO =4.5 V
3.7
TYpt
0.1
VOO=2.7V
0.1
VOO=4.5V
0.1
VOO=4.5 V
0.4
VOL
LOW-level output voltage
VIT-
Negative-going input threshold voltage, SENSE
(see Note 4)
VOO =2Vto 6V
Vhys
Hysteresis, SENSE
VOO=2Vto 6 V
Vres
Power-up reset voltage:t:
IOL=20 !1A
IOL=3mA
RESIN
II
100
Input current
4.48
4.55
4.62
40
-1
VI=VOO
5
10
SENSE
VI=5V
4
8
TA = -40°C to 85°C
RESIN=VOO,
SENSE = VOO > VIT+§,
Outputs open
CONTROL = 0 V,
9
25
9
20
120
150
IOO(d)
Supply current during Id
VOO = 5 V,
RESIN = VOO,
CONTROL = 0 V,
CI
Input capacitance, SENSE
VI=OVtoVoO
VCT=OV,
SENSE=VOO,
Outputs open
V
V
1
CONTROL
TA = O°C to 70°C
V
mV
1
VI=OVtoVoO
Supply current
UNIT
V
VOO=2V
IOL=20 !1A
MAX
50
!1A
!1A
!1A
pF
t TYPical values apply at TA = 25°C.
:t:The lowest supply voltage at which RESET becomes active. The symbol Vres is not currently listed within EIA or JEOEC standards for
semiconductor symbology.
§VIT+ = VIT-+ Vhys
NOTES: 3. All characteristics are measured with CT = 0.1 !1F.
4. To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 !1F) should be placed near the supply terminals.
\
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5--57
TLC7705, TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, TA
otherwise noted)
PARAMETE;R
=25°C, CT =0.1 /IF(unless
TEST CONDITIONS
TLC7705Y
MIN
TYP
VIT-
Negative-going input threshold voltage, SENSE
(see Note 4)
VOO =2Vt06 V
4.55
Vhys
Hysteresis, SENSE
VDO=2Vt06V
40
MAX
UNIT
V
mV
ICONTROL
VI = VOO
5
I SENSE
VI=5V
4
9
IlA
120
IlA
50
pF
II
Input current
100
Supply current
RESIN = VOO,
SENSE = VOO > VIT+t,
CONTROL = 0 V,
Outputs open
IOO(d)
Supply current during Id
VOO=5V,
RESIN = VOO,
CONTROL = 0 V,
CI
Input capacitance, SENSE
VI =OVto VOO
VCT=O V,
SENSE = VOO,
Outputs open
IlA
tVIT+ = VIT-+ Vhys
NOTE 4 To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 ItF) should be placed near the supply terminals.
switching characteristics at VOO = 5 V, RL = 500 n, CL = 50 pF, TA = 25°C
MEASURED
PARAMETER
Id
Oelaytime
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
low-to-high-Ievel output
tPHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tPHL
TO
(OUTPUT)
VI (SENSE) '?: VIT+
RESET
and
RESET
Propagation delay time,
low-to-high-Ieveloutput
tPHL
Propagation delay time,
high-to-Iow-Ievel output
tpLH
Propagation delay time,
low-to-high-Ievel output
tpHL
Propagation delay time,
high-to-Iow-Ievel output
tr
Rise time
tf
Fall time
RESIN = 2.7 V,
CONTROL = 0.4 V,
CT = 100 nF,
See timing diagram
TYP
MAX
1.5
2.1
3.5
VIH = VIT+max + 0.2 V,
VIL = VIT...min - 0.2 V,
RESIN = 2.7 V,
CONTROL = 0.4 V, CT = NCt
SENSE
UNIT
ms
2
I!S
2
RESET
20
20
ItS
RESET
35
VIH=2.7V,
VIL=0.4V,
SENSE = VIT+max + 0.2 V,
CONTROL = 0.4 V, CT = NCt
RESIN
ns
45
RESET
20
CONTROL
RESET
RESET
and
RESET
ns
35
10% to 90%
8
90% to 10%
4
nsN
~TEXAS
INSTRUMENTS
POST OFFICE
I!S
30
VIH =2.7V,
VIL=0.4 V,
SENSE'= VIT+max + 0.2 V,
RESIN = 2.7 V,
CT = NCt
t NC equals no capacitor and Includes up to 100-pF probe and jig capacitance.
5-58
MIN
20
Propagation delay time,
high-to-Iow-Ievel output
tPLH
TEST CONDITIONS,
RESET
Propagation delay time,
high-to-!ow-Ievel output
tPLH
TLC77051, TLC7705Y
FROM
(INPUT)
eox 655303 •
OALLAS, TEXAS 75265
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
.,
SV
J
I
I
I
J
I
I
I
RL
(see Note A)
.J
-=-
-=-
I
CL
(see Note B)
-=-
NOTES: A. For switching characteristics, RL = 500 Q.
B. CL = 50 pF includes jig and probe capacitance.
Figure 1. RESET AND RESET Output Configurations
14I
tw(L)
-Jl
. I
~ tw(L)-.I
~
I.
I
2.7 V
1.SV
~
VIT--
0.4 V
---
(a) RESIN
.
Vrr+max + 200 mV
Vrr+
VIT.J11in-200mV
(b) SENSE
WAVEFORMS
Figure 2. Input Pulse Definition
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5-59
TLC7705,TLC7705Y
MICROPOWER SUPPLY VOLTAGE SUPERVISORS
SLVS087B - DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
5V
i
10Okn
q
O•1I1F
-=-
VOO
SENSE RESET I - - NC
TMS70C20
CONTROL r - -
rCT
T~
-=-
VOO
RESET
TLC7705
RESIN RESET
RESE
0.111F
T·
GNO
GNO
1
1
Figure 3. Reset Controller ina Microcomputer System
..
5V
Il0..l.
~
..... 1
I
I
1""""1
±
0.111 F
Voo
1
-
-=
I
TLC7705
'--
-=
RESIN
q O . 1 I1F
± 0 . 1 I1F
SENSE
-=
-=
RESET
,---- CONTROL
RESET
RESET
CTrl
GNO
CSH1 r---
T
J.
TMS370
Lcs
8
OATAO-7
32K x 8
CMOS RAM
-=-
16/
AOOO-15
VOO
AO-A15
00-07
R/W
R/W
GNO
GNO
.1
.1
Figure 4. Data,Retention During Power Down Using Static CMOS RAMs
.
5-60
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
6-1
J
Contents
"tJ
o
.c~_.
....._.
til
C"
S.
_.o
~
_.
en
=e
....
(')
::r
CD
til
6-2
Page
TPS1100 Single P-Channel Enhancement-Mode MOSFETS ......... 6-3
TPS1101 Single P-Chan~el Enhancement-Mode MOSFETS ........ 6-13
TPS1110 Single P-Channel Logic-Level MOSFETS ................. 6-23
TPS1120 Dual P-Channel Enhancement-Mode MOSFETS .......... 6-35
TPS20xx Power-Distribution Switches ............................... 6-47
TPS2201 Dual-Slot PC Card Power-Interface Switches For Parallel
PCMCIA Controllers _ ........................................ 6-65
TPS2202 Dual-Slot PC Card Power-Interface Switches For Serial
PCMCIA Controllers ........................................ 6-87
TPS2201 A Dual-Slot PC Card Power-Interface Switch With Reset
For Serial PCMCIA Controller ............................ 6-107
TPS2205 Dual-Slot PC Card Power-Interface Switch With
Suspend Mode For Parallel PCMCIA Controller ........ 6-127
)
TPS11 00, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
- DECEMBER 1993 - REVISED AUGUST
•
•
Low rOS(on) ••• 0.18 OTyp at VGS = -10 V
3 V Compatible
•
•
Requires No External Vee
TTL and CMOS Compatible Inputs
•
•
VGS(th) -1.5 V Max
Available in Ultrathin TSSOP Package (PW)
•
ESD Protection Up to 2 kV Per
MIL-STD-883C, Method 3015
08
D OR PW PACKAGE
(TOP VIEW)
SOURCE
SOURCE
SOURCE
GATE
=
2
3
4
7
6
5
DRAIN
DRAIN
DRAIN
DRAIN
DPACKAGE
PWPACKAGE
description
The TPS1100 is a single - P-channel
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution in
battery-powered systems by means of Texas
Instruments LinBiCMOSTM process. With a
maximum VGS(th) of -1.5 V and an loSS of only
0.5 ~, the TPS11 00 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low rDS{on) and excellent ac
characteristics (rise time 10 ns typical) make the
TPS1100 the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated, (PWM) controllers or
motorlbridge drivers.
The ultrathin thin shrink small-outline package or
TSSOP (PW) version with its smaller footprint and
reduction in height fits in places where other
P-channel MOSFETs cannot. The size advantage
is especially important where board real estate is
at a premium and height restrictions do not allow
for an small-outline integrated circuit (SOIC)
package.
schematic
SOURCE
~
r - -ESD--II Protection
L _Circuitry
___ _
GATE
~
DRAIN
NOTE A. For all applications, all source pins should be connected
and all drain pins should be connected.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
-40°C to 85°C
SMALL OUTLINE
(D)
TPSll000
PLASnCDIP
(P)
TPSll00PWLE
CHIP FORM
(V)
TPSll00Y
The 0 package IS available taped and reeled. Add an R suffiX to device type (e.g.,
TPSll000R). The PW package is available only left-end taped and reeled
(indicated by the LE suffix on the device type; e.g., TPSll OOPWLE). The chip form
is tested at 25°C.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or· electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESO) of up to 2 kV according to
MIL-STO-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
Copyright © 1995. Texas Instruments Incorporated
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS.
SLVS078C - DECEMBER 1993 - REVISED AUGUST 1995
description (continued)
Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and
PCMCIA cards. For existing designs, the D-packaged version has a pinout commOn with other p-channel
MOSFETs in SOIC packages.
TPS1100Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS11 00. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
SOURCE
SOURCE
I
SOURCE
GATE
(1)
(8)
(2)
(7)
(3)
TPS1100Y
(4)
(6)
(5)
DRAIN
DRAIN
DRAIN
DRAIN
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~
M
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
TPS1100, TPS1100Y
SINGLE P·CHANNEL ENHANCEMENT·MODE MOSFETS
SLVS078C - DECEMBER 1993 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t '
UNIT
Drain-to-source voltage, VDS·
-15
V
Gate-to-source voltage, VGS
20r-15
V
D package
VGS=-2.7V
PWpackage
D package
VGS=-3V
PWpackage
Continuous drain current (TJ = 150°C), ID:t:
Dpackage
VGS=-4.5V
PWpackage
D package
VGS=-10V
PWpackage
TA = 25°C
±0.41
TA= 125°C
±0.28
TA = 25°C
TA= 125°C
TA=25°C
±0.4
±0.23
±0.6
TA= 125°C
±0.33
TA = 25°C
±0.53
TA= 125°C
±0.27
TA = 25°C
±1
TA= 125°C
±0.47
TA = 25°C
±0.81
TA= 125°C
±0.37
TA = 25°C
TA= 125°C
A
±1.6
±0.72
TA = 25°C
±1.27
TA= 125°C
±0.58
Pulsed drain current, ID:t:
TA=25°C
±7
Continuous source current (diode conduction), IS
TA = 25°C
-1
A
Storage temperature range, Tstg
-55 to 150
°C
Operating junction temperature range, TJ
-40 to 150
°C
Operating free-air temperature range, TA
-40 to 125
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
A
t
Stresses beyond those listed under "absolute maximum rallngs" may cause permanent damage to the deVice. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
:t: Maximum values are calculated using a derating factor based on RaJA = 158°C/W for the D package and RaJA = 248°C/W for the PW package.
These devices are mounted on an FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
=70°C
POWER RATING
DERATING FACTOR:t:
ABOVE TA = 25°C
POWER RATING
D
791 mW
6.33mW/oC
PW
504mW
4.03mW/oC
PACKAGE
TA,;;25°C
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
506mW
4tlmW
158mW
323mW
262mW
101mW
TA
:t: Maximum values are calculated using a derating factor based on RaJA = 158°C/W for the D package and RaJA = 248°C/W
for the PW package. These devices are mounted on an FR4 board wHh no special thermal considerations when tested.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-5
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993- REVISED AUGUST 1995
electrical characteristics at T J
=25°C (unless otherwise noted)
static
PARAMETER
TPS1100
TEST CONDITIONS
TPS1100Y
MIN
TYP
MAX
-1
-1.25
-1.50
MIN
.TYP
VGS(th)
Gate-to-source
threshold voltage
VOS= VGS,
10 =-250 f,lA
VSO
Source-to-drain
voltage (diodeforward voltage)t
IS =-1 A,
VGS=OV
IGSS
Reverse gate current,
drain short circuited
to source
VOS=OV,
VGS=-12V
lOSS
Zero-gate-voltage
drain current
VOS=-12V,
VGS=OV
VGS=-10V
10=-1.5A
180
VGS=-4.5V
10=-0.5A
291
400
291
r~Ston)
Static drain-to-source
on-state resistance t
476
700
476
606
850
606
VGS=-3V
VGS=-2.7V
Forward
transconductancet
9fs
VOS=-10V,
-0.9
MAX
-1.25
V
-0.9
V
nA
±100
ITJ=25°C
-0.5
I TJ = 125°C
-10
10=-O.2A
f,lA
180
2.5
10=-2A
UNIT
mO
2.5
S
t Pulse test: pulse duratIOn:;; 300 j!S, duty cycle:;; 2%
dynamic
PARAMETER
Og
Total gate charge
Ogs
Gate-to-source charge
Ogd
Gate-to.:c:!rain charge
Id(on)
Tum-on delay time
Id(offl
Tum-off delay time
tr
Rise time
tf
Fall time
trr(SO)
Source-to-drain reverse recovery time
6-6
TPS1100, TPS1100Y
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5.45
VOS=-10V,
VGS=-10V,
10=-1
A
0.87
nC
1.4
VOO=-10V,
RG=6n,
RL=100,
See Figures 1 and 2
IF=S.3A,
dVdt = 100 A/j!S
lo=-lA,
4.5
ns
13
ns
10
2
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 65S303 • DALlAS, TEXAS 75265
16
ns
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
,...--OV
VGS
~%--~r-------~----------~~-----
VOS
+
Voo
10%----r-~~.-~--------~--+_--~~
Vos
I
-10V
I
lcI(on)~
I
tr --foiI14f----+l~1
Figure 1. Switching-Time Test Circuit
Figure 2. Switching-Time Waveforms
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Drain current
vs Drain·to-source voltage
Drain current
vs Gate-to-source voltage
4
Static drain-ta-source on-state resistance
vs Drain current
5
CapaCitance
vs Drain-to-source voltage
6
Static drain-to-source on-state resistance (normalized)
vs Junction temperature
7
Source-to-drain diode current
vs Source-to-drain voltage
8
Static drain-t'o-source on-state resistance
vs Gate-to-source voltage
Gate-to-source threshold voltage
vs Junction temperature
Gate-to-source voltage
vs Gate charge
3
9
10
11
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-7
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
-7
~I
-6
~VG~~
-S
c(
-4
0
c
'!
C
-3
,.. V
I
E
-2
-1
r/
VOS=-10V
~
I
-6
c(
-
VGS =-3 V
I--
~
C
~;:,
I
-S
-4
C
C
-3
I
E
VGS=-2V
-2
If!
-1
T~ = 2~OC
o
-2 -3 -4 -S -6 -7 -8 -9 -10
VOS - Oraln-to-,Source Voltage - V
.J
o
-1
-2
~
I
VGS= -2.7~
VGS=-3V
ii
I
;0
.
.
a:
1l
mD}!
I
.~
0.2
\
/
I-'
u..
..
<>
C
<>
!
~
I
0
0.1
o
-0.1
1S0
I
VGS=-10V
100
I-
" -- i'...
200
:§
-)
-- r-
\.
2S0
I
L
I
VGS= -4.SV
0.3
I
cC
,2.0
......
300 ~
Q.
3
~ c 0.4
~<>
r-
r-
-7
VGS=O
f=1 MHz
TJ=2SoC
-
Clsst
Coss
I
*
cras -
SO
-1
-10
o
0-1 -2 -3 -4 -S -6 -7 -8 -9 -10-11 -12
10 - Drain Current - A
VOS - Orain-to-Source Voltage - V
t Ciss
FigureS
=
Cgs
+ Cgd • Cds(Shorted)
Cgs Cgd
+ C ~ Cds
gs
gd
:I: Crss = C gd• Coss = Cds + C
Figure 6
~TEXAS
6-8
-6
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
/ J
I
c::: O.S
I
-S
3S0
I
TJ =2S0C
0.6
-4
Figure 4
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
~
;:,
-3
VGS - Gate-to-Source Voltage - V
Figure 3
0.7
ITJ = 150°C
TJ=-40°C
0
'f
I '/
fI
'/ /
h'I
Iill
I
TJ = 2SoC
I
-
o :...o -1
-7
VGS=-4V
'Ii ~GS~-S~
V ...- ...-
I
C
~;:,
J--
VGS=-8V
VGS=-7V
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
+ C gd
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
1.5
.2 'S
1.4
-10
VGS=-10V
10=-lA
C
'j!
Q
u
i
Ui
.
.s.
u
1.1
I
a:
/
0.9
Cs
.2.(1)
(I),
Q C
... 0
0.8
0.7
-1.5
0.7
10=-1 A
TJ = 25°C
0.6
i!l
J
i!
\
0.3
0.2
-1.4
-1.3
f=
~ -1.2
l
~
I
10 =-250 iJA
I
0.5
\
'"
-1.1
"Iii
CJ
I
~
0.1
o
-1
~
-3
-11 -13
VGS - Gate-to-Source Voltage - V
-5
-7
r--
I I
o
Figure 7
0.4
TJ=-40°C -
I
I I
I
Q
!!!
0.6
-50
,.-
';'
/'
'/
-9
-15
-1
-0.9
-50
Figure 9
~
'" "
"
o
50
100
TJ - Junction Temperature - °C
Figure 10
'"
150
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-9
TPS1100,. TPS11 OOY
SINGLE P~CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE
. vs
GATE CHARGE
-10
>
..
:Ill
..e
I
I
VDS=-10V
ID=-1 A
TJ = 25°C
-8
III
~
J
-6
:::I
a;
0
1
1ii
/
-4
I
~ -2
/
V
o
o
V
/
CJ
1/1
/
/
/
2
3
4
5
Qg - Gate Charge - nC
Figure 11
~TEXAS 6-10
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
6
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C - DECEMBER 1993 - REVISED AUGUST 1995
THERMAL INFORMATION
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
DRAIN CURRENT
vs
vs
DRAIN-TO-SOURCE VOLTAGE
PULSE DURATION
-10
100
Single Pulse
See Note A
0.001 s
'\..
ct
I
~
-1
0.01 s
II
1\
./
10
0.1 s
C
~
::J
:""1\
(J
~
....
'"
1s
........ ~
1\1 1
Q
-0.1
I
Single Pulse
See Note A
10s
E
DC
TJ =
150°C
-0.001
-0.1
Trl~~",
-1
-10
-100
0.1
0.001
0.01
0.1
10
tw - Pulse Duration - s
VDS - Drain-ta-Source Voltage - V
Figure 12
Figure 13
NOTE A. Values are for the D package and are FR4-board mounted only.
APPLICATION INFORMATION
1--_4_V---I GaAs FET
Amplifier
Figure 14. Notebook Load Management
Figure 15. Cellular Phone Output Drive
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-11
TPS1101, TPS1101V
SINGLE P·CHANNEL ENHANCEMENT·MODE MOSFETS
SLVS079C - DECEMBER 1993 - REVISED AUGUST 1995
•
•
Low rOS(on)' .. 0.09 n Typ at VGS = -10 V
3 V Compatible
•
•
Requires No External Vee
TTL and CMOS Compatible Inputs
•
•
VGS(th) =-1.5 V Max
Available in Ultrathin TSSOP Package (PW)
•
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
D8
o PACKAGE
(TOP VIEW)
SOURCE
SOURCE
SOURCE
GATE
2
7
3
6
4
5
DRAIN
DRAIN
DRAIN
DRAIN
o PACKAGE
description
The TPS1101 is a single, 10w-rDS(on), P-channel,
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution in
battery-powered systems by means of the Texas
Instruments LinBiCMOSTM process. With a
maximum VGS(th) of -1.5 V and an IDSS of only
0.51lA, the TPS11 01 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low rDS(on) and excellent ac
characteristics (rise time 5.5 ns typical) of the
TPS 1101 make it the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated (PWM) controllers or
motor/bridge drivers.
PWPACKAGE
PWPACKAGE
(TOP VIEW)
NC
SOURCE
SOURCE
SOURCE
SOURCE
SOURCE
GATE
NC
10
16
2
3
4
5
6
7
8
15
14
13
NC
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
DRAIN
NC
The ultrathin thin shrink small-outline package or
12
TSSOP (PW) version fits in height-restricted
11
places where other P-channel MOSFETs cannot.
10
The size advantage is especially important where
9
board height restrictions do not allow for an
small-outline integrated circuit (SOIC) package.
NC - No internal connection
Such applications include notebook computers,
personal digital assistants (PDAs), cellular
telephones, and PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other
P-channel MOSFETs in SOIC packages.
AVAILABLE OPTIONS
PACKAGED DEVICESt
TJ
SMALL OUTLINE
(D)
TSSOP
(PW)
-40°C to 150°C
TPSll01D
TPSll01PWLE
CHIP FORM
(Y)
TPSll01Y
t The D package IS available taped and reeled. Add an R suffiX to deVice type (e.g.,
TPSll 01 DR). The PW package is only available left-end taped and reeled (indicated by
the LE suffix on thEi device type; e.g., TPSll 01 PWLE). The chip form is tested at 25°C.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA Information I. current I I of publlcallon dBlO.
ProdUell conform to _ _ Ions per !he tenns 01 Tsus Instruments .
otandsrd warranty. Production procsssIng _ not necessarily Include
1081109 of all psramota...
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
,6-13
TPS1101,TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079C - DECEMBER 1993 - REVISED AUGUST 1995
schematic
SOURCE
~
r----I ESDIL _Protection
Circuitry
___ _
GATE
~
DRAIN
NOTE A. For all applications, all source tenninals should be
connected and all drain tenninals should be connected.
TPS11.01Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS11 01. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
SOURCE
SOURCE
SOURCE
GATE
(1)
(8)
(2)
(7)
(3)
TPS1100Y
(4)
(6)
(5)
DRAIN
DRAIN
DRAIN
DRAIN
~ 80
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~1ExAs
6-14
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS1101,TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079B - DECEMBER 1993 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
UNIT
Drain-to-source voltage, VDS
-15
V
Gate-to-source voltage, VGS
2 or-15
V
D package
VGS=-2.7V
PWpackage
D package
VGS =-3 V
PWpackage
Continuous drain current (TJ = 150°C), ID:J:
D package
VGS =-4.5 V
PWpackage
D package
VGS=-10V
PWpackage
TA=25°C
iO.62
TA= 125°C
iO.39
TA=25°C
iO.61
TA= 1250C
iO.38
TA = 25°C
iO.88
TA= 125°C
iO.47
TA=25°C
iO.86
TA= 125°C
iO.45
TA = 25°C
il.52
TA= 125°C
.TA = 25°C
A
iO.71
il.44
TA= 125°C
iO.67
TA = 25°C
i2.30
TA= 125°C
il.04
TA = 25°C
i2.18
TA= 125°C
iO.98
Pulsed drain current, ID:J:
TA = 25°C
il0
Continuous source current (diode conduction), IS
TA = 25°C
-1.1
A
Storage temperature range, Tstg
:-55 to 150
°C
Operating junction temperature range, TJ
-40 to 150
°C
Operating free-air temperature range, TA
-40 to 125
°C
260
°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
A
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
:J: Maximum values are calculated using a derating factor based on RaJA = 158°C/W for the D package and RaJA = 176°C/W for the PW package.
These devices are mounted on an FR4 board with no special thermlll considerations.
DISSIPATION RATING TABLE
TA,,25°C
POWER RATING
DERATING FACTOR:J:
ABOVE TA = 25°C
TA = 70°C
POWER RATING
D
791 mW
6.33mW/oC
PW
710mW
5.68mW/oC
PACKAGE
TA=85°C
POWER RATING
TA = 125°C
POWER RATING
506mW
411mW
158mW
454mW
369mW
142mW
:J: Maximum values are calculated using a derating factor based on RaJA = 158°C/W for the D package and RaJA = 176°C/W
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6--15
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
l
SLVS079C - DECEMBER 1993 - REVISED AUGUST1995
electrical character.istics at TJ = 25°C (unless otherwise noted)
static
PARAMETER
TPS1101Y
TPS1101
TEST CONDITIONS
MIN
TYP
MAX
-1
-1.25
-1.5
MIN
TYP
VGS(th)
Gate-to-source
threshold voltage
VOS= VGS,
10 = - 250 J.1A
VSO
Source-to-drain
voltage (diode-Iorward voHage)t
IS=-l A,
VGS=OV
IGSS
Reverse gate current,
drain short circuited
to source
VOS=OV,
VGS=-12V
lOSS
Zero-gate-voltage
drain current
VOS=-12V,
VGS=OV
VGS=-10V
10=-2.5A
90
VGS=-4.5V
10=-1.5A
134
190
134
rOS(on)
Static drain-to-source
on-state resistance t
198
310
198
232
400
232
VGS=-3V
VGS=-2.7V
Forward
transconductancet
9ls
VOS=-10V,
-1.04
MAX
-1.25
V
-1.04
V
±100
ITJ=25°C
-0.5
ITJ = 125°C
-10
10 =-0.5A
nA
J.1A
90
4.3
10=-2A
UNIT
mQ
4.3
S
t Pulse test: pulse duration::; 300 IJ.S, duty cycle::; 2%
(dynamic
PARAMETER
Og
Total gate charge
Ogs
Gate-to-source charge
Ogd
Gate-to-drain charge
Iel(on)
Tum-on delay time
IelCofl)
Tum-off delay time
tr
Rise time
tl
Fall time
trrCSOI
Source-to-drain reverse recovery time
MIN
TYP
MAX
UNIT
11.25
VOS=-10V,
VGS=-10V,
10=-1 A
1.5
nC
2.6
VOO=-10V,
RG=6Q,
RL= 10n,
See Figures 1 and 2
IF=5.3A,
dVdt = 100 A/IJ.S
10=-1 A,
6.5
ns
19
ns
5.5
13
~I
'l TEXAS
NSTRUMENTS
6-16
TPS1101, TPS1101Y
TEST CONDITIONS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
16
ns
TPS1101, TPS1101V
SINGLE P·CHANNEL ENHANCEMENT·MODE MOSFETS
SLVS079B - DECEMBER 1993 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
, - - - - OV
VGS
~--~r-------~~----------~~-----
VOS
Voo
+
10%----r-~~.-~--------~--+_--~~
I
Vos
tr
Figure 1. Switching-Time Test Circuit
-10V
I
td(on) --;.--..:
lc:t(off)
14
Figure 2. Switching-Time Waveforms
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
3
Drain current
vs Drain-to-source voltage
Drain current
vs Gate-to-source voltage
4
Static drain-to-source on-state resistance
vs Drain current
5
Capacitance
vs Drain-to-source voltage
6
Static drain-to-source on-state resistance (normalized)
vs Junction temperature
7
Source-to-drain diode current
vs Source-to-drain voltage
8
Static drain-to-source on-state resistance
vs Gate-to-source voltage
Gate-to-source threshold voltage
vs Junction temperature
Gate-to-source voltage
VS
~TEXAS
Gate charge
9
10
11
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-17
TPS1101, TPS1101V
SINGLE P·CHANNEL ENHANCEMENT·MODE MOSFETS
SLVS079C - DECEMBER 1993 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
DRAIN CURRENT
-10
-7
-8
c
f
Q
_10~--~-----r-----M-T--~--~
-- -
VGS=-5V
'/VGS=-4V
C
~
::I
(J
GATE-TO-SOURCE VOLTAGE
11
-8
I
vs
DRAIN-TO-SOURCE VOLTAGE
~ I""VGS=-8V
-9
c
DRAIN CURRENT
vs
l,...--' ~ ~S=-3V
I .,
/
-5
I
E
C
I
~
-6~--~-----+~~~----+----1
~I
-4~--~-----+~~-r----+----1
c3c
I
-4
-8~--~-----+--~~~~+---~
Q
-3
-2
-1
~
o
o
--
VGS= 2V
-2~--~----~----~----+---~
TJ = 25°C
o~--~~--~----~----~--~
o
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10
-2
-1
VDS - Drain-ta-Source Voltage - V
Figure 4
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
i
~
0
=1
5·(,) :I
lie
CAPACITANCEt
vs
vs
DRAIN CURRENT
DRAIN-TO-SOURCE VOLTAGE
800
I
700
0.4
V
V..... /
0.3
VGS= -2.7 V
0.2
VGS= -3V
C-
\
I
8
c
L---
i
VGS= -4.5 V
I
----
l '........
600
II.
Co
500
Q
. VGr
o
-0.1
TOI
-1
~
200
100
-10
o
ID - Drain Current - A
FigureS
t-- r-
r-
300
0.1
.
\ \,Coss
r-....
t
C iss
Crss
_
- -
t-::r-_
..........
(J
'=1 MHz
TJ .. 25°C
Cisst
400
01
(J
I
i
v~s~oJ
TJ = 25°C
~
~?
~I
-5
VGS - Gate-to-Source Voltage - V
Figure 3
0.5
-4
-3
r- '""'-
-
*
-1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11-12
VDS - Draln-to-Source Voltage - V
= Cgs + Cgd•
CdS(Shorted)
Cgs Cgd
:j: Crss = Cgd • Coss = Cds
+ C gs + Cgd ~
Figure 6
6-18
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
CdS
+ C gd
TPS1101, TPS1101V
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079B - DECEMBER 1993 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
1.5
1.4
-10
I
g
"fi
Q c
1.2
1.1
!
11 .-
.2
a:
c-I
m ::
I
1i~C
0.9
0.8
Q
.. 0
/
/
/
'/
C
/
" ]I 1.3
~
Pulse Test
/
VGS=-10V
10=-1A
~ ;;
~iiE
SOURCE-TQ-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
/
1/"//
7 77
I
'E
~
/
/
"CD
0
~
C
"f
Q
oi
TJ= 150
-1
I
I
Q
I
!!!
o
100
50
TJ - Junction Temperature - °C
-0.1
-0.1
150
C
I
10=-1 A
TJ=25°C
~I
0.2
!a:
I
C-
.i
0.1
o
-1
-1.4
~
.c
-1.3
f=
§
-1.2
'"f
0.3
..
.2:
t
~
0.4
~
C
I
_
TJ=-40°C _
,
-1.3
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
> -1.5
I
0
"o c:
tgl
... CD
II
I- TJ=25°C
Figure 8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
GATE-TO-SOURCE VOLTAGE
,
I
-0.3
-0.5 -0.7
-0.9 -1.1
VSO - Source-to-Oraln Voltage - V
Figure 7
0.5
,.
I
~I
/ I
~
0
i
0.7
0.6
-50
/
"
\
~
"
i
..............
I
10 =-250 IlA
'"
~
-1.1
I
:c
e
"'-"-
-1
m
~
-3
-5
-7
-9 -11 -13
VGS - Gate-to-Source Voltage - V
-15
-0.9
-50
Figure 9
o
'"'"
50
100
TJ - Junction Temperature - °C
Figure 10
150
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-19
TPS1101, TPS1101Y
SINGLE P-CHANNEL ENftANCEMENf.·MODE MOSFETS
SLVS079C - DECEMBER 1993 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
-10
VOS=-10V
10,!,-1 A
TJ = 25°C
> -8
I
L
CD
I
~
~
/
-6
:::I
a;
....0
;
/
-4
I
~ -2
I
V
o
o
V
/
/
CJ
en
V
2
4
6
8
10
Qg - Gate Charge - nC
Figure 11
~TEXAS
6-20
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
12
TPS11 01, TPS11 01 Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS079B- DECEMBER 1993 - REVISED AUGUST 1995
THERMAL INFORMATION
TRANSIENT JUNCTION-TO-AMBIENT
THERMAL IMPEDANCE
DRAIN CURRENT
vs
vs
DRAIN-TO-SOURCE VOLTAGE
PULSE DURATION
-100
100
Single Pulse
See Note A
-10
0.001 s
'ii'
I:! .~ 1.4
:::I
0
11,1
0
";'
1
-100
VGS=-4.5V
10=-6A
Pulse Test
/
1.3
c S
'j!
. !B
Q
!
I
c
1.2
/
'iii 1.1
GI
II:
~.!I
cs
.2.(/)
(/)'
Q C
.. 0
0.9
0.8
0.7
-50
/
V
/
/
VGS=O
Pulse Test
<
,
I
C
~:::I
U
GI
/
~
is
L6
-10
C
"i!
1/
~";'
/
1/
GI
I:!:::I
TJ = 150°C
TJ = 25°C
-1
0
(/)
I
Q
~
o
50
100
TJ - Junction Temperature - °C
150
_ TJ=-40°C
-0.1
-0.1
Figure 7
-1
-10
VSO - Source-ta-Orain Voltage - V
Figure 8
-!11
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-29
TPS1110, TPS1110Y
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
SLVS100A- OCTOBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
>
-1
I
J
~
-0.9
1-"
~ -0.7
ii
";S
VOS=VGS
10 =-25011A
>
'"
J
~
-0.6
~
$'
o
-51---+--
I -.~--~--~~~~
§ - 41----+--+--->
-0.5
-50
50
"
""
100
~
-2r---+~~~--+--~--~
~
-1~~-+--~--+--~--~
150
TJ - Junction Temperature - °C
2
3
Qg - Gate Charge - nC
Figure 9
Figure 10
~TEXAS
INSTRUMENTS
6--30
=
~
I
> -0.4
-6
I
10=-3A
TJ 25°C
PulsaTast
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
4
5
TPS1110, TPS1110Y
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
SLVS100A- OCTOBER 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
Table of Graphs
FIGURE
Maximum drain current
vs Orain-to-source voltage
11
Junction-to-pin thermal resistance (normalized)
vs Pulse duration
12
Junction-to-ambient thermal resistance (normalized)
vs Pulse duration
13
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
-100
Single Pulse
1 ms
C
I
!
. / ~oms
-10
~ ~1ooms
()
~
.......
E
::s
E
-1
......
~
./
Q
"
/
~
DC Conditions.....
=
:E
I
E
TJ = 150°C
Tp=25°Ct
-0.1
-0.1
-1
-10
VDS - Drain-to-Source Vohage - V
t Tp - Temperature of drain pins measured close to the package
Figure 11
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-31
TPS1110, TPS1110V
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
SLVS100A- OCTOBER 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
JUNCTION-TO-PIN THERMAL RESISTANCE (NORMALIZED)
va
PULSE DURATION
d=0.5
~
/. ~
I I
'6'
.~
II
'ii
S
~
CD
u
d =0.1
0.1
....-
e
I
-.......
...
d=0.2
-
~
~
/ ' ~~
~
~~
~
d =0.05
a:
I I
I I
'ii
i
d=0.02 I-'
f..-t-I
.c
l-
e
ii:
....e0
.S!
0.01
t;
e
...
0.~
::I
I----c
I
~
2'
'/.
//. I'
7
V Single Pulse
/
1111 ~~
L-.-.....L.......L....L..J.....lJ.I..----L---L-J....L...I.J.J.JJ.-...L-..L.....I..J...L..L.I.I..~.J.....L...I..LIIII~.I.....I..IJ...U.
1I.I..Ll-
0.001
0.0001
0.001
0.01
0.1
tw - Pulse Duration - s
NOTE A: Z9JP(t) = rJp(t) , 9Jp
tw = pulse duration
Ie = cycle time
d = duty cycle = tw/tc
peakTJ = PD' ZSJP(I) + Tp
Figure 12
~TEXAS
INSTRUMENTS -6--32
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
10
100
TPS1110, TPS1110Y
SINGLE P-CHANNEL LOGIC-LEVEL MOSFETS
SLVS100A- OCTOBER 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
JUNCTION-TO-AMBIENT THERMAL RESISTANCE (NORMALlZED)t
vs
PULSE DURATION
,.,.
d=0.5
]
iii
E
0
~
8c
I-- I--"r-
d=l o)
0.1
!
....
OJ
til
d=0.05
II:
.c
-
l-
d=l o•ok
til
1
c
f....
';"
d
0.01
~ ""'"
~~
V ::;;; ~
Vr"
E
til
e
f..-
V k::~
i"""
iii
:is
E
--I--
d=1 0•21
100IIII
=Io.o~
~
V
.......
~
"
~~
/. "I
-'
:0
I
~
;:>
i/
!/
tw-r~1
1/ Single Pulse
JLIT
/
III
0.001
0.0001
0.001
0.01
0.1
PD
0
II IIII
10
100
tw - Pulse Duration - s
t
Device mounted on FR4 printed-circuit board with no speciallhermal considerations.
NOTE A: ZeJA(I) = rJA(t) . BJA
tw = pulse duration
Ie = cycle lime
d duty cycle twlle
peak TJ = PD' ZaJA(I) + TA
=
=
Figure 13
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-33
6-34
TPS1120, TPS1120V
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
MARCH
=
•
•
•
•
Low rOS(on)'" 0.18 nat VGS -10 V
3-V Compatible
Requires No External Vee
TTL and CMOS Compatible Inputs
•
•
VGS(th) -1.5 V Max
ESD Protection Up to 2 kV per
MIL-STD-883C, Method 3015
OS
o PACKAGE
(TOP VIEW)
1S0URCE
1GATE
2S0URCE
2GATE
=
2
3
4
7
6
5
1DRAIN
1DRAIN
2DRAIN
2DRAIN
description
The TPS1120 incorporates two independent
p-channel enhancement-mode MOSFETs that
have been optimized, by means of the Texas
Instruments LinBiCMOSTM process, for 3-V or 5-V
power distribution in battery-powered systems. With a maximum VGS(th) of -1.5 V and an IDSS of only 0.5 !lA,
the TPS1120 is the ideal high-side switch for low-voltage portable battery-management systems, where
maximizing battery life is a primary concern. Because portable equipment is potentially subject to electrostatic
discharge (ESO), the MOSFETs have built-in circuitry for 2-kV ESO protection. End equipment for the TPS1120
includes notebook computers, personal digital assistants (POAs), cellular telephones, bar-code scanners, and
PCMCIA cards. For existing designs, the TPS11200 has a pinout common with other p-channel MOSFETs in
small-outline integrated circuit SOIC packages.
The TPS1120 is characterized for an operating junction temperature range, TJ, from -40°C to 150°C.
AVAILABLE OPTIONS
PACKAGED DEVICESt
TJ
SMALL OUTLINE
(D)
-40°C to 150°C
TPS11200
CHIP FORM
(Y)
TPSl120Y
t The 0 package is available taped and reeled. Add an R suffix to device
type (e.g., TPS11200R). The chip form is tested at 25°C.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESO) of up to 2 kV according to
MIL-STO-S83C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA Information Is CUmlll! as 01 publication date.
P_ _ to apacHlcationa per \he terms 01 Texas Ina1rumen1s
standard W8IJIIIIIy. Production procoaalng does not naces..~1y Include
testing 01 a" parameters.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRuMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-35
TPS1120, TPS1120Y
DUAL P·CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A- MARCH 1994 - REVISED AUGUST 1995
schematic
1S0URCE
2S0URCE
r------
r-----I
I
I
I
I
I
ESD-
Proiection
Circuitry
1...------
ESD-
Protection
Circuitry
1...------
1GATE - - - * " _ ,
2GATE - - - * " _ ,
'--v--J
'-v---J
1DRAINt
t
2DRAINt
.
For all applications, both dr/iin pins for each device should be connected.
.
TPS1120Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1120C. Thermal compression
.or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
condu¢ive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
1S0URCE
1GATE
2S0URCE
2GATE
(1)
(8)
(2)
(7)
(3)
TPS1120Y
(4)
(6)
(5)
1 DRAIN
1 DRAIN
2DRAIN
2DRAIN
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±100f0
ALL DIMENSIONS ARE IN MILS
~
M
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
~TEXAS'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS ••TEXAS 75265
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS08OA- MARCH 1994 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)f
UNIT
-15
Drain-to-source voltage, VDS
20r-15
Gate-to-source voltage, VGS
VGS=-2.7V
TA = 25°C
±0.39
TA= 125°C
±0.21
TA = 25°C
VGS =-3 V
Continuous drain current, each device (TJ = 150°C), ID
VGS=-4.5V
VGS=-10V
V
±0.5
TA= 125°C
±0.25
TA = 25°C
±0.74
TA= 125°C
±0.34
TA = 25°C
±1.17
TA= 125°C
±0.53
A
Pulse drain current, ID
TA = 25°C
±7
A
Continuous source current (diode conduction), IS
TA = 25°C
-1
A
Continuous total power dissipation
See Dissipation Rating Table
Storage temperature range, Tstg
-55 to 150
Operating junction temperature range, T J
-40 to 150
°C
Operating free-air temperature range, TA
-40 to 125
°C
'Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
t
V
260
°C
°C
Stresses beyond those listed under "absolute maximum rallngs' may cause permanent damage to the deVice. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA s: 25°C
POWER RATING
DERATING FACTOR:j:
ABOVE TA 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D
840mW
6.71 mW/oC
538mW
437mW
169mW
=
:j: Maximum values are calculated using a derating factor based on RaJA = 149°CIW for the package. These devices are
mounted on an FR4 board with no special thermal considerations.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6--37
TPS1120"TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A- MARCH 1994 - REVISED AUGUST 1995
electrical characteristics at TJ = 25°C (unless otherwise noted)
static
PARAMETER
TPS1120
TEST CONDITIONS
MIN
TYP
MAX
-1
-1.25
-1.50
VGS(th)
Gate-to-source threshold voltage
VOS=VGS.
10 =-250/1A
VSO
Source-to-drain voltage (diode forward
voltage)t
IS=-l A.
VGS=OV
IGSS
Reverse gale currenl. drain short circuiled 10
source
VOS=OV.
VGS=-12V
lOSS
Zero-gale-voltage drain currenl
VOS=-12V.
VGS=OV
VGS=-10V
10 =-1.5A
180
VGS=-4.5V
10 =-0.5A
291
400
476
700
606
850
Static drain-la-source on-stale resistance t
rOS(on)
VGS=-3V
VGS=-2,7V
Forward transconductancet
9fs
VOS=-10V.
-0.9
UNIT
V
V
±100
nA
-0.5
ITJ=25°C
I TJ = 125°C
-10
10=-0,2A
2.5
10=-2A
/1A
rna
S
t Pulse lest: pulse width oS 300 liS. duty cycle oS 2%
static
PARAMETER
VGSllhl
Gale-la-source Ihreshold voltage
VOS= VGS.
10 =-250/1A
VSO
Source-la-drain voltage (diode forward
voltage)t
IS =-1 A.
VGS=OV
Stalic drain-la-source on-slale resislancet
rOS(on)
MIN
TYP
-0.9
V
10 =-1.5A
180
10 =-0.5A
291
VOS=-10V.
mn
476
10 =-0.2A
UNIT
V
VGS=-4.5V
VGS =-3 V
MAX
-1.25
VGS=-10V
VGS=-2.7V
Forward transconductancet
9fs
TPS1120Y
TEST CONDITIONS
606
2.5
10=-2A
S
t Pulse lest: pulse width oS 300 liS. duty cycle oS 2%
dynamic
. TPS1120, TPS1120Y
PARAMETER
Og
Total gale charge
Ogs
Gate-Io-source charge
Ogd
Gate-la-drain charge
Ic:i(on)
Turn-on delay lime
Ic:i(off)
Turn-off delay time
Ir
Rise lime
If
Fail time
trr(SO)
Source-to-drain reverse recovery lime
TEST CONDITIONS
TYP
MAX
UNIT
5.45
VOS=-10V.
VGS=-10V.
10=-1 A
0.87
nC
1.4
VOO=-10V.
RG=60,
RL= 100.
See Figures 1 and 2
IF=5.3A.
dVdt = 100 AlliS
10=-1 A.
4.5
ns
13
ns
10
2
:II
TEXAS
,INSTRUMENTS
6--38
MIN
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
ns
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVSOSOA- MARCH 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
~-OV
VGS
~--~------~--------~~----
VOS
VOO
+
1~---r--~.-~-----.~-+--~r-
VOS
I
fd(on>-*1
tr
Figure 1. Switching-Time Test Circuit
-10V
1
i
-11."-+1.1
Figure 2. Switching-Time Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6--39
TPS1120, TPS1120Y
DUAL P~CHANNEL ENHANCEMENT~MODEMOSFETS
SLVS080A- MARCH 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
Table of Graphs
FIGURE
Drain current
vs Drain-to-source voHage
Drain current
vs Gate-to-source voltage
4
Static drain-to-source on-state resistance
vs Drain current
5
Capacitance
vs Drain-to-source voltage
Static drain-to-source on-state resistance (nonnalized)
vs Junction temperature
vs Source-to-drain voltage
Static drain-ta-source on-state resistance
vs Gate-to-source voltage
Gate-to-source threshold voltage
vs Junction temperature
10
Gate-to-source voltage
vs Gate charge
11
"'C
DRAIN CURRENT
~~
-4
c
-3
,.
I
E
-2
-1
'r/-
VGS = -8 V
~ VGS=-7V
-7
J-t-
VGS=-6V
-
VGS =-3 V
I.,...- ~
~ I--'
rJ
~
~
TJ=-40°c
-4
(,)
c
'f
Q
E
VGS=-2V
o ~I-o -1 -2
I
I
-2
-1
I
TJ=25°c
-3 -4 -5 -6 -7 -8 -9 -10
VOS - Orain-to-SOurce Voltage - V
o
o
./
-1
'/ /
-2
-3
t All characteristics data applies for each independent MOSFET incorporated on the TPS1120.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
-4
-5
-6
VGS - Gate-to-Source Voltage - V
Figure 4
Figure 3
6--40
I
/TJ = 150°C
'1hll
'I,
/II
J
-3
I
.I
-Ii
TJ = 25°C
-5
I
VGS=-5V
~~
/ '/
-6
"'C
I
I
VOS=-10V
~-- ~GS=-4V
V
(,)
'i!
Q
vs
GATE·TO·SOURCE VOLTAGE
iiilL
I
9
DRAIN-TO-SOURCE VOLTAGE
'1
-5
8
vs
~
-6
6
.. 7
Source-to-drain diode current
DRAIN CURRENT
-7
3
-7
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVSOBOA- MARCH 1994- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
0.7
T =12S0~
J I
I
0.6
I
3S0
V/
l
vGS= -2.7'!...!-"
V
"-
't-- r\
I\.
2S0
300
/
II.
I
I
fl
.:
I
1S0
III
(J
J
I
VGS=-10V
i'...
200
e
~II
VGS= -4.SV
r-
a.
II
VGS =-3 V
I
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
~
--r- -
100
Cisst
Coss
I
tJ-
......
I
(J
r-
VGS=O
f=1 MHz
TJ = 2SoC
f--
SO
o
-0.1
-1
o
-10
10 - Drain Current - A
t
:I:
0-1 -2 -3 -4 -S -6 -7 -8 -9 -10-11 -12
VOS - Oraln-to-Source Voltage - V
C iss = Cgs
+ Cgd '
Cds(Shorted)
Cgs C gd
Crss = C gd ' Coss = Cds + C
+ C ~ Cds
gs
gd
Figure 6
FigureS
STATIC DRAIN-TO-SOURCE
ON-STATE RESISTANCE (NORMALIZED)
vs
JUNCTION TEMPERATURE
1.S
1.4 -
e=s.~
:s
0
III0
e
j
I
_CD
0.9
elj
.2.0
o C 0.8
~O
0.7
0.6
-50
/
'"
V
0(
/'
1.3
/
0
I
Pulse Test
/
iii
Q
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
-10
I
VGS=-10V
10=-1A
... ~E 1.2
e g 1.1
/
I
H
C
~
:s
/
L
/1
(J
!
TJ=1S00C /
e
e
-1
Q
b
1
I
:s
I
cSl
I
I
Q
~
o
+ C gd
J
-0.1
50
100
1S0
o
I
I
I
'/
,....
I'l
TJ=2SoC
TJ=-40°C -
-
I
-0.2-0.4 -0.6 -0.8 -1 -1.2 -1.4 -1.6 -1.8
TJ - Junction Tempersture - °C
Figure 7
VSO - Source-to-Orsin Voltage - V
Figure 8
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-41
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A- MARCH 1994 - REVISED AUGUST 1995
TYPICAL CH"ARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
GATE-TO-SOURCE VOLTAGE
JUNCTION TEMPERATURE
vs
>
0.7
ID=-1 A
TJ = 25°C
0.6
-1.5
!
I
ID=-2501lA
J-u
~
'"
1-
I
0.5
\
\
I
J
-1.3
~
§
~
-1.2
~
1,
.
I
5
0.1
o
-1
-1
If -0.9
'"
.......
~
~
>'
-3
-5
-7
-9
-11 -13
VGS - Gate-to-Source Voltage - V
o
-50
-15
Figure 9
Figure 10
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
-10
>
I
I
VDS=-10V
ID=-1 A
TJ=25°C
-8
i'"
/
~::I -6
i"
-4
I
}
50
-2
7
/
V
o
o
100
TJ - Junction Temperature - °C
2
J
V
/
V
V
3
4
5
Qg - Gate Charge - nC
Figure 11
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
150
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS080A- MARCH 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
DRAIN CURRENT
va
DRAIN·TO·SOURCE VOLTAGE
-10
Single Pulse
See Note A
0.001 s
"-
C
~
-1
I
0.01 s
I
1\
0.1 s
'E
~
ij
1'-
"-
1\
c:
1!
Q
'"
-0.1
I
oF
r
r
1s
I I
10s
DC
TJ = 150°C
TA=25°C
I
-0.001
-0.1
111111
-10
-1
-100
VDS - Draln·ta-Source Voltage - V
Figure 12
TRANSIENT JUNCTlON·TO·AMBIENT
THERMAL IMPEDANCE
va
PULSE DURATION
100
Single Pulse
See Note A
""
...... i--'
0.1
0.001
0.01
0.1
10
tw - Pulse Duration - s
Figure 13
NOTE A: FR4-board-mounted only
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-43
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVSOSOA- MARCH 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
The profile of the heat sinks used for thermal measurements is shown in Figure 14. Board type is FR4 with 1-oz copper
and 1-oz tin/lead (63/37) plate. Use of vias or through-holes to enhance thermal conduction was avoided.
Figure 15 shows a family of RaJA curves. The RaJA was obtained for various areas of heat sinks while subject to air
flow. Power remained fixed at 0.25 W per device or 0.50 W per package. This testing was done at 25°C.
As Figure 14 illustrates, there are two separated heat sinks for each package. Each heat sink is coupled to the lead
that is internally tied to a single MOSFET source and is half the total area, as shown.in Figure 15. For example, if the
total area shown in Figure 15 is 4 cm 2, each heat sink is'2 cm 2.
I------~-----------------I
The Combined Area
of These Two Heat
Sinks Is 4 cm2
I
I
I
I
I
I
I
I
I
I
I
I
1DRAIN
I
_ _RIll 2DRAIN II
I..
L ___ -,
2GATE
I
I
I
I
I
~
'=2cm
TPS1120D IC
HS:4cm2 ,
I
,
I
_ _ _ --.J
L __ ~~~C~~~a~~I~~ _ _ _'
Figure 14. Profile of Heat Sink's
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
~
I
C
~
E
CC
0
~
~c::
...
AIRFLOW, 25°C
150
=
=
TJ 25°C
140 I-~::---+----+----+-----+-- P 0.5 W
Heat Sink Areas
130 1:---"""'"'''''''''::-----+------+-----+-- as Shown
120
110
:I
2ic::
I
iii
~
.c::
lI
...
CC
~
II:
100
90
80
70
60
4cm2
50
0
50
100
150
200
Airflow, 25°C - ft/min
Figure,1S
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 ., DALLAS, TEXAS 75265
250
300
TPS1120, TPS1120Y
DUAL P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVSOBOA- MARCH 1994 - REVISED AUGUST 1995
THERMAL INFORMATION
Figure 16 illustrates the thermally enhanced (SO) lead .frame. Attaching the two MOSFET dies directly to the source
terminals allows maximum heat transfer into a power plane.
Lead 8
Lead 1
Lead 2
Lead 7
Lead 3
Lead 6
Lead 4
leadS
Figure 16. TPS1120 Dual MOSFET SO-8 Lead Frame
APPLICATION INFORMATION
I
1--_-4_ V
--t GaAs FET
Amplifier
Figure 17. Notebook Load Management
Figure 18. Cellular Phone Output Drive
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
6-45
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010V
POWER·DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
DPACKAGE
(TOP VIEW)
• 9S-mQ Max (S.S-V Input) High-Side MOSFET
Switch With Logic Compatible Enable Input
• Short-Circuit and Thermal Protection
• Typical Short-Circuit Current Limits:
0.4 A, TPS2010; 1.2 A, TPS2011;
2 A, TPS2012; 2.6 A, TPS2013
• Electrostatic-Discharge Protection, 12-kV
Output, 6-kV All Other Terminals
• Controlled Rise and Fall Times to Limit
Current Surges and Minimize EMI
• SOIC-8 Package Pin Compatible With the
Popular LlttlefootTM Series When GND Is
Connected
GNDDa OUT
IN 2
7 OUT
IN 3
6 OUT
EN 4
5 OUT
PWPACKAGE
(TOP VIEW)
GND
IN
IN
IN
IN
IN
EN
• 2.7-V to S.S-V Operating Range
• 10-j.LA Maximum Standby Current
• Surface-Mount SOIC-8 and TSSOP-14
Packages
• -40°C to 12SoC Operating Junction
Temperature Range
OUT
OUT
OUT
OUT
OUT
OUT
OUT
description
The TPS201x family of power-distribution switches is intended for applications where heavy capacitive loads
and short circuits are likely to be encountered. The high-side switch is a 95-mQ N-channel MOSFET. Gate drive
is provided by an internal driver and charge pump designed to control the power switch rise times and fall times
to minimize current surges during switching. The charge pump operates at 100 kHz, requires no external
components, and allows operation from supplies as low as 2.7 V. When the output load exceeds the current-limit
threshold or a short circuit is present, the TPS201x limits the output current to a safe level by switching into a
constant-current mode. Continuous heavy overloads and short circuits increase power dissipation in the switch
and cause the junction temperature to rise. If the junction temperature reaches approximately 180°C, a thermal
protection circuit shuts the switch off to prevent damage. Recovery from thermal shutdown is automatic once
the device has cooled sufficiently.
The members of the TPS201 x family differ only in short-circuit current threshold. The TPS201 0 is designed to
limit at O.4-A load; the other members of the family limit at 1.2 A, 2 A, and 2.6 A (see the available options table).
The TPS201x family is available in 8-pin small-outline integrated circuit (SOIC) and 14-pin thin shink
small-outline (TSSOP) packages and operates over a junction temperature range of -40°C to 125°C. Versions
in the 8-pin SOIC package are drop-in replacements for Silicon ix's LittlefootTM power PMOS switches, except
that GND must be connected.
AVAILABLE OPTIONS
TJ
RECOMMENDED MAXIMUM
CONTINUOUS LOAD CURRENT
(A)
TYPICAL SHORT-CIRCUIT
OUTPUT CURRENT LIMIT AT 25°C
(A)
0.2
0.6
-40°C to 125°C
PACKAGED DEVICES
SOIC'
(D)t
TSSOP
(PW)*
CHIP
FORM
(Y)
0.4
TPS2010D
TPS2010PWLE
TPS2010Y
1.2
TPS2011D
TPS2011PWLE
TPS2011Y
1
2
TPS2012D
TPS2012PWLE
TPS2012Y
1.5
2.6
TPS2013D
TPS2013PWLE
TPS2013Y
*
tThe D package IS available taped and reeled. Add an R SuffiX to deVice type (e.g., TPS2010DR).
The PW package is only available left-end taped and reeled (indicated by the LE suffix on the device type; e.g., TPS2010PWLE).
Littlefoot is a trademark of Siliconix.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-47
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097 - DECEMBER 1994- REVISED AUGUST 1995
functional block diagram
IN
---...--+--*....,
~,..---{
OUT
EN --__*------c:.l
GND~
t
Current sense
Terminal Functions
TERMINAL
NAME
EN
GND
IN
OUT
NO.
VO
DESCRIPTION
D
PW
4
1
2,3
5-8
7
I
Enable input. Logic low turns power switch on.
1
2-6
8-14
I
Ground
I
Input voltage
0
Power-switch output
detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 95 mn (VI(IN)
configured as a high-side switch.
=5.5 V),
charge pump
An internal 1~O-kHz charge pump supplies power to th~ driver circuit and provides the necessary voltage to pull
the gate of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and
requires very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range instead of the
microsecond or nanosecond range for a standard FET.
enable (EN)
A logic high on the EN input turns off the power switch and the bias forthe charge pump, driver, and other circuitry
to reduce the supply current to less than 10 J.IA. A logic zero input restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
~TEXAS
INSTRUMENTS
6-48
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
current sense
A sense FET monitors the current supplied to the load. The sense FET is a much more efficient way to measure
current than conventional resistance methods. When an overload or short circuit is encountered, the
current-sense circuitry sends a control signal to the driver. The driver in turn reduces the gate voltage and drives
the power FET into its linear region, which switches the output into a constant current mode and simply holds
the current constant while varying the voltage on the load.
thermal sense
An internal thermal-sense circuit shuts the power switch off when the junction temperature rises to
approximately 180°C. Hysteresis is built into the thermal sense, and after the device has cooled approximately
20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is removed.
TPS201xY chip information
This chip, when properly assembled, displays characteristics similar to the TPS201 xC. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
GND
IN
IN
EN
(1)
(8)
(2)
(7)
(3)
TPS201xY
(4)
(6)
(5)
OUT
OUT
OUT
OUT
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-49
TPS2010,TPS2011,TPS2012,TPS2013,TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097 - DECEMBER 1994 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted}t
Input voltage range, VI{IN) (see Note 1) ............................................... -0.3 V to 7 V
Output voltage range, Vo (see Note 1) ................... ,................... -0,.3 V to VI{IN) +0.3 V
Input voltage range, VI at EN ........................................................ -0.3 V to 7 V
Continuous output current, 10 ..................................................... internally limited
'Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ .................................... -40°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds ....................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "reCommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE
D
PW
=
=
TA:S; 25°C
POWER RATING
DERATING FACTOR
ABOVE TA 25°C
TA 70°C
POWER RATING
TA 125°C
POWER RATING
725mW
700mW
5.8mW/OC
464mW
448mW
145mW
140mW
=
5.6mW/oC
recommended operating conditions
MIN
MAX
2.7
5.5
V
0
5.5
V
TPS2010
0
0.2
TPS2011
0
0.6
TPS2012
0
1
Input VOltage, VIIINI
Input vonage, VI at EN
Continuous output current, 10
TPS2013
Operating virtual junction temperature, T J
~TEXAS
INSTRUMENTS
6--50
POST OfFICE sox 655303 • DALLAS. TEXAS 75265
0
1.5
-40
125
UNIT
A
°C
TPS2010,TPS2011,TPS2012,TPS2013,TPS2010Y
POWER-DISTRIBUTION SWITCHES
SlVS097A- DECEMBER 1994- REVISED AUGUST 1995
electrical characteristics over recommended operating Junction temperature range, VI(IN)
10 rated current, EN = 0 V (unless otherwise noted)
=
=5.5 V,
power switch
PARAMETER
TPS2010, TPS2011
TPS2012, TPS2013
TEST CONDfTIONSt
MIN
On-state resistance
t
tr
Output rise time
tf
Output fall time
UNIT
MAX
VIC IN) = 5.5 V,
TJ = 25°C
75
95
VI (IN) = 4.5 v,
TJ = 25°C
80
110
VI(lN)=3V,
TJ = 25°C
120
175
TJ = 25°C
140
215
TJ = 25°C
0.001
VI(lNJ = 2.7 V,
Output leakage current
TVP
I
EN = VI (IN)
I
1
10
-40°C",TJ",125°C
VI (IN) = 5.5 V,
TJ = 25°C,
CL= 111F
4
VIClN) = 2.7 V,
TJ = 25°C,
CL= 111F
3.8
VICIN) = 5.5 V,
TJ = 25°C,
CL= 111F
3.9
VI(IN)=2.7V,
TJ = 25°C,
CL= 111F
3.5
mn
pA
ms
ms
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
enable input
, (EN)
PARAMETER
TPS2010, TPS2011
TPS2012, TPS2013
TEST CONDITIONS
MIN
High-level input voltage
UNIT
MAX
2
2.7 V '" VIClN) '" 5.5 V
LOW-level input voltage
TVP
V
4.5 V '" Vl{INi'" 5.5 V
0.8
2.7 V '" VI (IN) < 4.5 V
0.4
Input current
EN = 0 Vor EN = VIC IN)
tpLH
Propagation (delay) time, low-to-high-Ievel output
CL= 111F
-0.5
20
tpHL
Propagation (delay) time, high-to-Iow-Ievel output
CL= 111F
40
0.5
V
pA
rns
current limit
PARAMETER
TJ = 25°C,
VI(IN) = 5.5 V,
OUT connected to GND, device
enabled into short circuit
Short-circuit current
t
TPS2010, TPS2011
TPS2012, TPS2013
TEST CONDmoNst
UNIT
MIN
TVP
MAX
TPS2010
0.22
0.4
0.6
TPS2011
0.66
1.2
1.8
TPS2012
1.1
2
3
TPS2013
1.65
2.6
4.5
A
Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.
supply current
PARAMETER
TEST CONDITIONS
TPS2010, TPS2011
TPS2012, TPS2013
MIN
TJ = 25°C
Supply current, lOW-level output
EN=VI(IN)
Supply current, high-level output
EN=OV
TVP
0.015
TJ = 25°C
1
10
-40°C", TJ'" 125°C
-40°C", TJ '" 125°C
UNIT
MAX
73
100
100
pA
pA
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-51
TPS2010, TPS2011, TPS2012, TPS2013,TPS2010Y
POWER-DISlRIBUTION SWITCHES
SLVS097 - DECEMBER 1994 - REVISED AUGUST 1995
electrical characteristics over recommended operating junction temperature range, VI(IN)
10 rated current, EN 0 V, TJ 25°C (unless otherwise noted)
=
=
=
=5.5 V,
power switch
. PARAMETER
TEST CONDITIONSt
TPS2010Y, TPS2011Y
TPS2012Y, TPS2013Y
MIN
On-state resistance
VI(lN) = 5.5 V,
75
VI(lN) = 4.5 V.
80
IlA
0.001
EN=VICIN)
Output fall time
mQ
140
VICIN) = 2.7 V,
Output rise time
UNIT
MAX
120
VI(lN)=3V,
Output leakage current
TYP
VI(lN) = 5.5 V.
Cl= 1IJ.F
4
VWN)=2.7V,
Cl= 1IJ.F
3.!!
VI(lN) = 5.5 V,
Cl= 1IJ.F
3.9
VIClN) = 2.7 V,
Cl= 1IJ.F
3.5
ms
ms
t Pulse-testing techl)iques maintain junction temperature close to ambient temperature; thermal effects must be taken Into account separately.
current limit
PARAMETER
TEST CONDITIONSt
TPS2010Y, TPS2011Y
TPS2012Y, TPS2013Y
MIN
VI(IN) = 5.5 V,
OUT connected to GND,
Device enabled into short circuit
Short-circuit current
t
TYP
UNIT
MAX
A
0.4
...
Pulse-testing techniques maintain Junction temperature close to ambient temperature; thermal effects must be taken Into account separately.
supply current
PARAMETER
TEST CONDITIONS
TPS2010Y, TPS2011Y
TPS2012Y, TPS2013Y
MIN
Supply current. lOW-level output
Supply current, high-level output
0
EN = VIClN)
EN=OV
~TEXAS
6-52
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TYP
0.D15
73
UNIT
MAX
IlA
IlA
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
>
>
6 ~
I
t
&4
!!
~
W
0
>
6
4
~
2
t
6
I
2
.!!!
i
I
&4
!!
~
j
2
i
o
I
o
r
./~
.5
0
>
6
,,
I
&4
!!
~
2
!
0
>
-1
'!5
/
0
b
> -1
o
2
3
4
5
~
7
8
9
o
5
10
t-Time-ms
Figure 1. Propagation Delay and
Rise Time With 1-I!F Load, VI(IN) = 5.5 V
>
~
2
W
-
40
45
Figure 2. Propagation Delay and
Fall Time With 1-I!F Load, VI(IN) 5.5 V
=
~
2
i.5
0
0
>
I
&4
4
~
2
5
b
0
>
35
!!
I
1
30
&4
>
8.
!!
25
I
4
t
20
>
I
&
!!
15
t-Tlme-ms
!!
~
.;
,
\
2
15 0
V
I
o
-1
o
234
5
6
7
8
9
>
-1
o
5
t-Time-ms
10
15
20
25
30
35
40
45
t-Tlme-ms
Figure 3. Propagation Delay and
Rise Time With 1-I!F Load, VI(IN) = 2.7 V
Figure 4. Propagation Delay and
Fall Time With 1-I!F Load, VI(IN) = 2.7 V
~TEXAS
INSTRUMENTS
POST OFFICE SOX 855303 • DALLAS, TEXAS 75285
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097 - DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
>
J 5F~=9~~-+--~1-~--+--r~--;
I
~_~l~==~*=~~~~~~~
i'S
0 t-
!
8r--r~--+--r~--~-+--~1--;
>
I
t
~
o
~
C
C
CI
~
8
8-
8
6
I
4r-~~--+-~~--+--+--r-~-4
C 4
2r-~~--+--r~--~-+--~1--;
B
0~41-+~~t=~=+~==+=~~
8
I
2_1~~~~~~~~~~~~~~
o
0.5
1
1.5
2
2.5.
3
3.5
4
4.5
-
'5 0
> 6~~~~~~~~~~~~~~
b
5
~
~
2
!c5
".,
V
0
I
o
-
-1
o
0.5
1
I-TIme-ms
1.5
2
2.5
3
3.5
4
4.5
I-TIme-ms
Figure 5. TPS2010, Short-Circuit Current.
Short is Applied to Enabled Device, VI(IN) 5.5 V
=
Figure 6. TPS2011, Short-Circuit Current.
Short Is Applied to Enabled Device, VI(IN) 5.5 V
=
>
I
I•
""'-
~
5
~
'S 0
!
8
b
>
6
6
C
C
~ 4
C 4
8
B
I
I
~
2
Jb
-
-1
J
,.,/:
0
2
,,/
0
I
o
o
- -1
0.5
1
1.5
2
2.5
3
3.5
4
4.5
o
0.5
1
1.5
2
2.5
3
3.5
4
4.5
I-TIme-ms
I-Tlme-ms
Figure 7. TPS2012, Short-Circuit Current.
Short is Applied to Enabled Device, VI(IN) 5.5 V
=
Figure 8. TPS2013 - Short-Circuit Current.
Short is Applied to Enabled Device, VI(IN) 5.5 V
~TEXAS
6-54
V
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
=
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
>
I
&5
l!
~
!i 0
t
o
I
~
3
C
I
./
C 2
~~
o
7
I
C 2
V~
1
!i
a.
~
3
C
./
0
~~
o
,/
V
/
1
/:
7
i 0V
J
J
5
I
I
o
-
-1
o
o
2
4
6
8
10
12
14
16
18
20
- -1
o
2
4
6
t-lime-mB
Figure 9. TPS2010 - Threshold Current,
VI(IN)
5
j
!i 0
1
ot 0
b
-
>
/
C 2
!i
20
=5.5 V
/
8
6
C
I
C
V
1/
~~
4
o 2
i 0V
/'
V
;'
v
5
I
o
-1
5
t
9o
/
3
I
~
18
!i 0
J
4
C
o
16
CD
f
~
~
14
I
I
ell
I
12
>
>
t
o
10
Figure 10. TPS2011 - Threshold Current,
VI(IN) =5.5 V
J
8
t-lime-ms
o
2
4
6
8
10
12
14
16
18
20
-
-1
o
2
t-Time-mB
6
8
10
12
14
16
18
20
t-Tlme-mB
Figure 11. TPS2012 - Threshold Current,
VI(IN)
4
=5.5 V
Figure 12. TPS2013 - Threshold Current,
VI(IN) = 5.5 V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
6-55
TPS2010,TPS2011,TPS2012,TPS2013,TPS2010Y
POWER..DISTRIBUTION SWITCHES
2LVS097 - DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
3
c
I
I
C
~
!:I
(J
'$
c.
'$
0
-
I
2.5
2
TPS2013 -
I
TPS2012
1 ,I
1.5
TPS2011
I I
I
,5)
0.5
~
0
-1 0
2
3
TPS2010
,
4
5
6
7
8
9
10
t-Tlme-ms
Figure 13. Turned-On (Enabled) Into Short Circuit, VI(IN) = 5.5 V
VI
-._---1
IN
IN
OUT J-----e- Vo
OUT
TPS201x OUT
OUT
ENABLE - - - d EN
GND
TEST CIRCUIT
VOLTAGE WAVEFORMS
Figure 14. Test Circuit and Voltage Waveforms
~TEXAS
6-56
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2010, TPS2011, TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
TURN·ON DELAY TIME
vs
INPUT VOLTAGE
INPUT VOLTAGE
4.9
.
e
I
I
TJ = 25°C
4.7 ,- RL=50n
CL= 111F
4.5
CD
e
1=
1:
!c
~
~
/'
4.3
/
4.1
TURN·OFF DELAY TIME
vs
v---
...--
/
----
25
..e
I
TJ = 25°C
RL=50n
CL=1I1F
20
I
CD
e
lCD
1=
Q
./
15
=
~
/
~
3.9
/
V'
/"
,/
10
/
/
3.7
3.5
2.5
3
3.5
4
4.5
VI - Input Voltage - V
5
5
2.5
5.5
4.5
3.5
4
VI- Input Voltage - V
3
Figure 15
FALL TIME
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
5
4
TJ = 25°C
CL=1I1F
3.6
4
I
CD
.
a:
-.
3.5
I
3
.".,.. /
VI=~V'
~1=2.7V
~
V
..e
I
...
e
t=
~
.,..
I
./
2.5
3.4
o
VI=5.5V
3
.......V
2.B
/
2.6
0.6
0.9
1.2
10 - Output Current - A
1.5
i--""'""
I V
/
2.4
2
0.3
~
3.2
2.2
2
TJ = 25°C
CL=1I1F
3.B
4.5
e
i=
...
5.5
Figure 16
RISE TIME
..e
5
v.-
/" ~
/
VI=2.7V
1/
o
Figure 17
0.3
1.2
0.6
0.9
10 - Output Current - A
1.5
Figure 18
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-57
TPS2010, TPS2011,,TPS2012, TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097 - DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT (OUTPUT ENABLED)
SUPPLY CURRENT (OUTPUT DISABLED)
vs
va
--
JUNCTION TEMPERATURE
80
Io=OA
VI=5.5V
JUNCTION TEMPERATURE
oC
::l.
I
i
:is
'$
e.~
~
0.1 ~--t----t----+----I7'--t7''--+---I
lJ
I
VI=2.7V
0.01
~--t---t---rt---+-+---+---+---I
0.001
~--,"""""'--",---J-",---_ _~_ _.L.-_ _.L.----'
I
8
20
-50
-25
o
25
50
75
100
TJ - Junction Temperature - °C
125
-50
o
-25
Figure 19
vs
INPUT VOLTAGE
INPUT VOLTAGE
::l.
I
I
70~--~---+----+---~---1~~
I.
TJ
is
8O~---r---+----+---~~~--~
e.
'$
0.1
15
~
::J
!
(.)
i
i
0.01
::J
Ul
I
I
C
2.5
~
3
__
~
____
~
__
~
__
3.5
4.5
4
VI-Input Voltage - V
~
__
5
-
~
e.
J
I
=125°C
-
OJ
__
125
10
oC
:i.
H~
100
SUPPLY CURRENT (OUTPUT DISABLED)
IO=OA
~
75
va
8O.---~---.----~---r---'----'
II
50
Figure 20
SUPPLY CURRENT (OUTPUT ENABLED)
oC
25
TJ - Junction T&mperature - °C
E
~
5.5
0.001
2.5
-- ~ --
Figure 21
3
3.5
4.5
4
VI - Input Voltage - V
Figure 22
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
~
i"""
5
5.5
TPS2010, TPS2011, TPS2012,TPS2013, TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097A- DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
ON-STATE RESISTANCE
ON-8TATE RESISTANCE
vs
vs
JUNCTION TEMPERATURE
INPUT VOLTAGE
190
a
eI
GI
u
140
170
a
eI
150
.
130
110
\~
GI
a:
~
100
'"
90
0
90
I
C
..0
c
80
..0
70
60
2.5
3
vs
INPUT VOLTAGE
INPUT VOLTAGE
3
I
GI
~
0
0.15
GI
'"
0.1
Do
.5
I
~
S
">
cc
I
~ ~.5A
~ f'...
S
~
~
'$
2.5
"-~
0.05
o
-'"
2.5
r---
3
r--
4.5
C
~
:::I
2
~
1.5
-
T~S2013
TPS2012
J
U
T~S2011
~
0
t:
~lA
j..,
5.5
5
SHORT-CIRCUIT CURRENT
0.25
'S
4
vs
>
0.2
3.5
Figure 24
INPUT VOLTAGE TO OUTPUT VOLTAGE
'"
""'-
VI - Input Voltage - V
Figure 23
~
~
70
TJ - Junction Temperature - °C
~
=25°C
I,
Ui
E 110
I
_\
c
-;;
a:
'0Z
120
I
TJ
GI
U
c
I
130
\
0
&;
1/1
10 =600mA
0.5
10 =200mA
3.5
4
4.5
VI - Input Voltage - V
TPS2010
5
5.5
0
2.5
I
3
Figure 25
3.5
4
4.5
VI - Input Voltage - V
5
5.5
Figure 26
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
6-59
TPS2010,TPS2011,TPS2012, TPS2013,TPS2010Y
POWER-DISTRIBUTION SWITCHES
SLVS097 - DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
SHORT-CIRCUIT CURRENT
THRESHOLD TRIP CURRENT
vs
vs
INPUT VOLTAGE
JUNCTION TEMPERATURE
5.5
3
5
2.5
_PGM (2 Vldlv)
,.
xVPP (5 Vldiv) -
/
o
xVPP (5 Vldlv)
~
/
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
2
t-Time-ms
3
4
5
I
I
I
6
7
8-
9
t-Time-ms
Figure 10. xVPP Propagation Delay and
Rise Times With 1-IlF Load, 12-V Switch
Figure 11. xVPP Propagation Delay and
Fall Times With 1-IlF Load, 12-V Switch
r-x_VPP_PGM (2 Vldiv)
x_VPP _PGM (2 Vldlv)
./
xVPP (5 Vldiv)
/
o
V
2
/-
3
V
4
'\
5
6
789
o
5
t-Time-ms
10
15
xVPP (5 V/dlv)
20
25
30
35
40
45
t-Time-ms
Figure 12. xVPP Propagation Delay and
Rise Times With 100-IlF Load, 12-V Switch
Figure 13. xVPP Propagation Delay and
Fall Times With 100-IlF Load, 12-V Switch
~TEXAS
INSTRUMENTS
6-74
1"- ......
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
Table of Graphs
FIGURE
100
Supply current
vs Junction temperature
14
rOS{on)
Static drain-source on-state resistance. 3-V switch
vs Junction temperature
15
rOS(on)
Static drain-source on-state resistance. S-V switch
vs Junction temperature
16
rOSlon)
Static drain-source on-state resistance. 12-V switch
vs Junction temperature
17
VO(xVCC)
Output voltage. S-V switch
vs Output current
18
VO(xVCC)
Output voltage. 3-V switch
vs Output current
19
xVpp
Output voltage. Vpp switch
vs Output current
20
ISC(xVCC)
Short-circuit current. S-V sw~ch
vs Junction temperature
21
ISC(xVpP)
Short-circuit current. 12-V switch
vs Junction temperature
22
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
100
VO(AVCC) = VO(BVCC) = 5 V
VO(AVPP) = VO(BVPP) = 12 V
No load
95
0(
::l
I
C
~::I
90
U
~
a.
a.
::I
85
III
I
C
E
80
75
-50
./
./'
--
o
~
50
V
./
100
150
T J - Junction Temperature - °C
Figure 14
t t = pulse tested
~TEXAS .
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS. TEXAS 75265
6-75
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B -AUGUST 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
3-YSWITCH
5-VSWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-80URCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
250
-
..".
200
.;
220
i
200
,;/
~
/
!
.-../ "
~
~c: l
I~
100
50
I
o
-50
I
VOO=5V
VCC=5V
g
",-
~
240
I
I
VOO=5V
VCC=3.3V
150
a
E
400
o
-25
.25
50
75
100
TJ - Junction Temperature - °C
125
0
'[
..0
180
160
140
./
120
~
I
~
o
~::I
i
100
80
-50
-25
5-VSWITCH
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1700
VOO=5V
Vpp=12V
1500
>
I
1300
.JIll'"
1100
lii
700
",-
/
V
./
;'
J
~
5
!
4.9r---r---r---+---+-~~~~~~
I
U
V"
~
~
V
4.8i---i---t---r---r---r---+---I
,,/
o
25
50
75
100
125
TJ - Junction Temperature - °C
4.75 L -__L -__.L.-_ _.L.-_ _-'--_-'--_-'------'
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IO(xVCC) - Output Current - A
Figure 17
Figure 18
t I = pulse lesled
-!I1TEXAS
6-76
125
Figure 16
12-VSWITCH
~
I
75
o
25
50
100
TJ - Junction Temperature - °C
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
900
.S!
1ii
V
/'
/'"
Figure 15
a
/'
./
./
./
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
3.35
3-VSWITCH
VppSWITCH
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
.----'T"""-...,--.---.--,---,---,
12.05
.-----,---.-----r----,--.----,
VOO=5V
Vpp=12V
VOO=5V
VCC = 3.3 V
>
3.3
"""'-+--+---/---+---1---+--1
_
i
..
3.25
~
i
_
3.2
o
I
I
~
12~~~--1__--+--~---/--_1
>
I
I
I-_-+~~~~~_I__~~
I_
I---+-~-~~~~~~~~~
3.15
I---+--+---+---+---"~-"'o"+--""'I
3.1
I__-+--+---/---l---:A---+~-I
~
'5
~
~
11.951----t---"'k""'...-=......;:---'''''''''I''"'''"-r-
11.90 I---t---I---+----'"I~~d--=-!
::c8:.
11.851--~--1__--,--~1--_j,L-~
11.80'---_......L.._ _'--_--'-___'--_-'-_--'
0.02
0.04
0.06
0.08
0.1
0.12
o
3.05 '---_-'--_-'-_-'-_--'-_......L.._--'-_---'
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IO(xVpp) - Output Current-A
IO(xVCC) - Output Current - A
Figure 19
Figure 20
5-VSWITCH
12-VSWITCH
SHORT-CIRCUIT CURRENT
SHORT-CIRCUIT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
400
2
VOO=5V
VCC=5V
00(
7
I
1:
~
:::I
0
VOO=5V
Vpp=12V
00(,
350
1:
1.5
:=
:::I
e
~
~
(3
'0I!:
~
.c
<3
300
~
250
:se
............
~
III
I
I
60
~
j
~
.!fI
0.5
-50
o
50
100
TJ - Junction Temperature - °c
150
200
---.r-
r--
150
100
-50
Figure 21
100
o
50
TJ - Junction Temperature - °c
150
Figure 22
t I = pulse'lesled
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-77
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold: modems, wireless LANs, GPS systems,
multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the
engineering comm!Jnity quickly recognized the need for a standard to ensure compatibility across platforms.
To this end, the PCMCIA (Personal Computer Memory Card International Association) was established and was
comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key
goal was to realize the concept of plug and play - cards and hosts from different vendors should be compatible
and able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the PC Card connector's 68 pins. This power interface consists of two Vee, two Vpp, and four ground
pins. Multiple Vee and ground pins are used to minimize connector-pin and line resistance. The two Vpp pins
were originally specified as separate signals but are commonly tied together in the host to form a single node
to minimize voltage losses. Card primary power is supplied through the Vee pins; flash-memory programming
and erase voltage is supplied through the Vpp pins. As each pin is rated to 0.5 A, Vee and Vpp can theoretically
supply up to 1 A, assuming equal pin resistance and no pin failure. A conservative design would limit current
to 500 mAo Some applications, however, require higher Vee currents; disk drives, for example, may need as
much as 750-mA peak current to create the initial torque necessary to spin up the platter. Vpp currents, on the
other hand, are defined by flash-memory programming requirements, typically under 120 mAo
future power trends
The 1-A physical-pin current alluded to in the PC Card specification has caused some host-system engineers
to believe they are required to deliver 1 A within the voltage tolerance of the card. Future applications, such as
RF cards, could use the extra power for their radio transmitters. The 5 W required for these cards will require
very robust power supplies and special cooling considerations. The limited number of host sockets that will be
able to support them makes the market for these high-powered PC Cards uncertain. The vast majority of the
cards require less than 600 mA continuous current and the trend is towards even lower-powered PC Cards that
will assure compatibility with a greater number of host systems. Recognizing the need for power derating, an
adhoc committee of the PCMCIA is currently working to limit the amount of steady-state dc current to the
PC Card to something less than the currently implied 1 A. If a system is designed to support 1 A, then the switch
rOS(on), power supply requirements, and PC Card COOling need to be carefully considered.
designing around 1-A delivery
Delivering 1 A means minimizing voltage (and power) losses across the PC Card power interface, which
requires that designers trade off switch resistance and the cost associated with large-die (lOW rOS(on» MOSFET
transistors. The PC Card standard requires that 5 V ±5%, or 3.3 V ±0.3 V be supplied to the card. The
approximate 10% tolerance for the 3.3-V supply makes the 3.3-V rOS(on) less critical than the 5-V switch. A
conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and terminal-resistance
drops, which leaves 2% (100 mY) voltage drop for the 5-V switch, and at least 6% (198 mY) for the 3.3-V switch.
Calculating the rOS(on) necessary to support a 100 mV or 198 mV switch loss, using R = Ell and setting I = 1 A,
the 5-V and 3.3-V switches would need to be 100 mil and 198 mil respectively. One solution would be to pay
for a more expensive switch with lower rOS(on)' A second, less expensive approach is to increase the headroom
of the power supply-for example, to increase the 5-V supply 1.5% or to 5.075 ±2%. Working through the
numbers once more, the 2% for the regulator plus 1 % for etch and terminal losses leaves 97% or 4.923 V. The
allowable
~TEXAS
INSTRUMENTS
6-78
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
designing around 1-A delivery (continued)
voltage loss across the power distribution switch is now 4.923 V minus 4.750 V or 173 mY. Therefore, a switch
with 173 mil or less could deliver 1 A or greater. Setting the power supply high is a common practice for
delivering voltages to allow for system switch, connector, and etch losses and has a minimal effect on overall
battery life. In the example above, setting the power supply 1.5% high would only decrease a 3-hour battery life
by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running a 5-W PC
Card.
heat dissipation
A greater concern in delivering 1 A or 5 W is the ability of the host to dissipate the heat generated by the PC
Card. For desktop computers the solution is simpler: locate the PC Card cage such that it receives convection
cooling from the forced air of the fan. Notebooks and other handheld equiprnent will not be able to rely on
convection, but must rely on conduction of heat away from the PC Card through the rails into the card cage. This
is difficult because PC Card/card cage heat transfer is very poor. A typical design scenario would require the
PC Card to be held at 60°C maximum with the host platform operating as high as 50°C. Preliminary testing
reveals that a PC Card can have a 20°C rise, exceeding the 10°C differential in the example, when dissipating
less than 2 W of continuous power. The 60°C temperature was chosen because it is the maximum operating
temperature allowable by PC Card specification. Power handling requirements and temperature rises are topics
of concern and are currently being addressed by the PCMCIA committee.
overcurrent and over-temperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. This can be particularly frustrating to the
consumer who has already experienced problems with shortened battery life due to improper Nicad conditioning
or memory effect. Most hosts include fuses for protection. The reliability of fused systems is poor, though, as
blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2201 takes a two-pronged
approach to overcurrent protection. First, instead of fuses, sense FETs monitor each of the power outputs.
Excessive current generates an error signal that linearly limits the output current, preventing host damage or
failure. Sense FETs, unlike sense resistors or polyfuses, have the added advantage that they do not add to the
series resistance of the switch and thus produce no additional voltage losses. Second, when an overcurrent
condition is detected, the TPS2201 asserts a signal at OC that can be monitored by the microprocessor to initiate
diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists,
causing the IC to exceed its maximum junction temperature, thermal-protection circuitry engages, shutting
down all power outputs until the device cools to within a safe operating region.
12-V supply not required
Most PC Card switches use the externally supplied 12-V Vpp power for switCh-gate drive and other chip
functions, requiring that it be present at all times. The TPS2201 offers considerable power savings by using an
internal charge pump to generate the required higher voltages from the 5-V VDD supply; therefore, the external
12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery
lifetime. Additional power savings are realized by the TPS2201 during a software shutdown, in which quiescent
current drops to a maximum of 1 J.IA.
voltage transitioning requirement
PC Cards, like portables, are migrating from 5 V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2201 is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering
the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-79
TPS2201, TPS2201 Y
.
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
voltage transitioning requirement (continued)
capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2201 offers a selectable Vee and Vpp ground state, per PCMCIA 3.3-V/5-V switching specifications, to fully
.
discharge the card capacitors while switching between Vee voltages.
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of Vee within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100 kn resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to over 2 seconds. The only way to ensure timing compatibility with PC Card standards
is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add
an external groundFET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2201 is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2201 offers functionality, power savings, overcurrent and thermal· protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2201 has multiple terminals for each of its 3.3 V, 5 V, and 12 V power inputs and for the switched Vee
outputs. Any individual terminal can conduct the rated input or output current. Unless all terminals are connected
in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops
and lost power. Both 12 V inputs must be connected for proper Vj:lP switching; it is recommended that all input
and output power terminals be paralleled for optimum operation. The Voo input lead must be connected to the
5V input leads.
Although the TPS2201 is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-I!F electrolytiC or tantalum capacitor paralleled by
a 0.047-I!F to 0.1-I!F ceramic capacitor. It is strongly recommended that the switched Vee and Vpp outputs be
bypassed with a 0.1-I!F or larger capacitor; doing so improves the immunity of the TPS2201 to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2201 and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance.
The TPS2201 , unlike other PC Card power-interface switches, does not use the 12-V power supply for switching
or other chip functions. Instead, an internal charge pump generates the necessary voltage from Voo, allowing
the 12-V input supply to be shut down except when the Vpp programming or erase voltage is needed. Careful
system design making use of this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Doing so, though nondestructive, results
in high current flow into the device, and could 'result in abnormal operation. In any case, this occurrence indicates
a malfunction of one input voltage or both, which should be investigated.
Similarly, no terminal should be taken below -0.3 V; forward biasing the parasitic-substrate diode results in
substrate currents and unpredictable performance.
~TEXAS
.
INSTRUMENTS
6-80
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
overcurrent and thermal protection
The TPS2201 uses sense FETs to check for overcurrent conditions in each of the Vee and V pp outputs. Unlike
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent senlling is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
During power up, the TPS2201 controls the rise time of the Vee and Vpp outputs and limits the current into a
faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2201 engages. If the Vee
or Vpp outputs are driven below ground, the TPS2201 may latch nondestructively in an off state. Cycling power
will reestablish normal operation.
Overcurrent limiting for the Vee outputs is designed to engage if powered up into a short in the range of
0.75 A to 1.9 A, typically at about 1.3 A; the Vpp outputs limit from 120 rnA to 400 rnA, typically around 200 rnA.
The protection circuitry acts by linearly limiting the current passing through the switch, rather than initiating a
full shutdown of the supply. Shutdown occurs only during thermal limiting .
... ... ...
.." .
Thermafiimifmgprevents dEistiliCtiori orthe"Ie from overheating when the package power-dissipation ratings
are exceeded. Thermal limiting, disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rOS(on), is dependent on the junction temperature, TJ, ofthe die. The junction temperature
is dependent on both rOS(on) and the current through the switch. To calculate TJ, first find rOS(on) from Figures
16, 17, and 18 using an initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P D = rDS(on) . 12
Next, sum the power dissipation and calculate the junction temperature:
TJ =
(~
PD' RaJA)
+ T A'
RaJA = 108°C/W
Compare the calculated junction temperature with the initial temperature estimate. If they are not within a few
degrees of each other, reiterate using the calculated temperature as the initial estimate.
logic input and outputs
The TPS2201 was designed to be compatible with most popular PCMCIA controllers and current PCMCIA and
JEIDA standards. However, some controllers require slightly counterintuitive connections to achieve desired
output states. The TPS2201 control logic inputs A_VCC3, A_VCC5, B_VCC3 and B_VCC5 are defined active
low (see Figure 23 and control-logic table). As such, they are directly compatible with the Cirrus Logic
CL-PD6720 controller's logic outputs (see Figure 24). The TP$2201 separate Vpp power good indicators can
be ORed together to provide a single input to the Cirrus controller.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-81
TPS2201,TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
r---------------------------,
B.-c
,
TP52201
,
,
,
57
58
51
~o---<
0-52
1101
53
c~
-v
16
3V
!
17 i
3V
~S4
56
-0-
1
!
!
30 i
5V
151
i 20
17
VPP2
VCC
lLvcc
____ _
I
i211511
~~
i 221
~-~
2 i
5V
11
I
I
I
rC;;-dS--
j
55
17
!
C~
~o---<
5V
'9
59
-0-
~o---<
3V~
'8
~
I
I
vce
VCC
Q
VPP1
512
j23
521
LVPP2
____ _
7i
24 i
12V
12V
Internal
Current Monitor
I
CPU
Controller
I
14
i
5HON
Logic
3
4
5
6
29
28
27
26
::
..
.
19
13 ,
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
H
"
,I
i 25
VOO
BPWR_GOOO
oe
GNO
L ________ ~ ____________
m
______ J
12
Figure 23. Internal Switching Matrix
~TEXAS
INSTRUMENTS
6--82
I
;> 00-07
APWR_GOOO
18
Thermal
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
TPS2201 control logic
AVPP
SHDN
1
1
1
1
CONTROL SIGNALS
A_VPP_VCC
A_VPP_PGM
0
0
0
0
1
1
1
0
X
X
1
INTERNAL SWITCH SETTINGS
S7
S8
S9
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OUTPUT
VAVPP
OV
vcct
VPP(12V)
Hi-Z
Hi-Z
BVPP
SHDN
1
1
1
1
CONTROL SIGNALS
B_VPP_PGM
B_VPP_VCC
0
0
0
1
1
0
1
1
X
X
CONTROL SIGNALS
A_VCC3
A_VCC5
0
0
0
INTERNAL SWITCH SETTINGS
S11
S12
S10
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
OPEN
OUTPUT
VBVPP
OV
VCC:!:
VPP(12V)
INTERNAL SWITCH SETTINGS
Sl
S2
S3
CLOSED
OPEN
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
OUTPUT
VAVCC
OV
3V
5V
OV
INTERNAL SWITCH SETTINGS
S5
S6
OPEN
CLOSED
OPEN
OPEN
CLOSED
OPEN
OPEN
OPEN
CLOSED
CLOSED
OPEN
OPEN
OPEN
OPEN
OPEN
OUTPUT
VBVCC
OV
3V
5V
OV
Hi-Z
Hi-Z
Avec
SHDN
1
1
1
1
0
1
1
1
0
x
X
CONTROL SIGNALS
B_VCC3
B_VCC5
0
0
0
1
Hi-Z
BVCC
SHDN
1
1
1
1
0
0
1
1
1
0
x
X
1
S4
Hi-Z
t Output depends on AVCC
:!: Output depends on BVCC
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
6-83
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B -AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
logic input and outputs (continued)
TPS2201
Cirrus Logic
CL-PD6720
A_VPP_PGM
A_Vpp_PGM
A_VPP_VCC
A_VCC3
A_Vpp_VCC
A_VCC_3
A_VCC5
A_VCC_5
B_Vpp_PGM
B_VPP_PGM
B_VPP_VCC
..
B_Vpp.-VCC
B_VCC3
B_VCC_3
B_VCC5
B_VCC_5
APWR_GOOD
)
BPWR_GOOD
OC
GND
---+---
To CPU
-
Vpp_Valid
1
Figure 24. Logic Connections to CL-PD6720
Intel's 82365SLDF controller uses active-high control logic for Vee selection, which requires connecting the
82365SLDF'S 3-V control outputs (A_VCC_ENO, B_VCCENO) to the TPS2201 's 5-V control inputs (A_VCC5,
B_VCC5) and the 5-V control outputs (AVCC_EN1, B_VCC_EN1) to the 3-V control inputs (A_VCC3, B_VCC3),
as illustrated in Figure 25. Examination of the control logic tables on page 16 will confirm that these connections
will in fact select the correct output voltage. An alternative approach would be to invert the Intel Vee control logic
signals before routing them to the TPS2201.
The separate Vpp power-good indicators of the TPS2201 can be connected directly to the Intel controller as
shown in Figure 25.
Cirrus Logic defines a (1, 1) on the Vee select lines to be the PC Card no connect state; Intel chose (0, 0) to
select this state. As ~he tables show, either combination switches the Vee outputs to 0 V. The decision to provide
V versus a high Impedance for the no connect state eliminates potential charging at the switch-to-card
interface. Feedback from the PC Card design community favors this approach.
o
Vpp logic allows forO-V or high-impedance output for no connect (0,0) or reserved (1, 1) logic inputs, respectively
(refer to AVPP and BVPP control-logic tables on page 16). Both the Cirrus Logic and Intel controllers interface
directly with the V pp control inputs of the TPS2201.
The shutdown input of the TPS2201, SHDN, when held at a logic low places all Vee and Vpp outputs in a
high-impedance state and reduces chip quiescent current to 1 !lA to conserve battery power.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the Vee or Vpp supplies
(see discussion above).
ESD protection
All TPS2201 inputs and outputs incorporate ESD-protection circuitry deSigned to withstand a 2-kV
human-body-model discharge as defined in.MIL-STD-883C. The Vee and Vpp outputs can be exposed to
potentially higher discharges from the external environment through the PC card connector. Bypassing the
outputs with 0.1-~F capacitors protects the devices from discharges up to 10 kV.
~TEXAS
&-84
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2201, TPS2201Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR PARALLEL PCMCIA CONTROLLERS
SLVS094B - AUGUST 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
5V
I
VDD
12V
L
12V
AVCC
AVCC
AVCC
~
BVCC
BVCC
=t
i
-=-
BVCC
AVPP
3V
t
t
AVPP
5V
VCC
PC Card
Connector A
~)
i
O.1I1 F
-=-
----1
±O.1I1F
L
VCC
VCC
-
Vpp1
t-- Vpp2
PC Card
ConnectorB
f}
-=-
5V
5V
BVPP
BVPP
3V
3V
t
----.J
A_VCC5
3V
A_VCC3
A_VPP_VCC
A_VPP_PGM
INTEL
823658LDF
O.1I1F
-=-
A_VCC_ENO
A_VCC_EN1
A_Vpp_ENO
-
A_Vpp_EN1
B_VCC5
B_VCC3
B_VPP_VCC
B_VCC_ENO
B_VCC_EN1
B_Vpp_ENO
B_Vpp_EN1
A:GPI
B_VPP_PGM
APWR_GOOD
BPWR_GOOD
OC
8hutdown
81g nal
From CPU
VCC
Vpp1
Vpp2
12V
TP82201
5V
O.1I1F
...
L
GND
8HDN
~
I
~
---+--
B:GPI
To CPU
C8
~
1
J
Figure 25. Detailed Operating Circuits Using Intel 82365SLDF Controller
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6--85
6-86
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
DB OR DF PACKAGE
(TOP VIEW)
• Fully Integrated Vee and Vpp Switching for
Dual-Slot PC Card Interface
• Saves PCMCIA Controller 110 Leads by
Utilizing 3-Lead Serial Interface
• Meets PCMCIA Standards
• Internal Charge Pump (No External
Capacitors Required) - 12-V Supply Can Be
Disabled Except for Flash Programming
• Short Circuit and Thermal Protection
• Space-Saving 30-Pin SSOP(DB) Package
• Compatible With 3.3-V, 5-V and 12-V PC
Cards
•
•
•
•
5V
5V
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
APWR_GOOD
NC
3V
Power Saving 100 = 83 ~A Typ, 10 = 1 ~
Low rOS(on) (160-mn Vee Switch)
Break-Before-Make Switching
ESD Protection Up to 2 kV Per
Mil-STD-883C, Method 3015
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
5V
NC
NC
NC
NC
Voo
12V
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
3V
3V
NC - No internal connection
description
The TPS2202 PC Card (PCMCIA) power-interface switch provides an integrated power-management solution
for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, thermal protection, and
power-good reporting for PC Card control are combined on a single integrated Circuit (IC), using Texas
Instruments LinBiCMOSTM process. The circuit allows the distribution of 3-V, S-V, and/or 12-V card power by
means of a reduced I/O serial interface. The current-limiting feature eliminates the need for fuses, which reduces
component count and improves reliability; current-limit reporting can help the user isolate a system fault to a
bad card.
The TPS2202 maximizes battery life by using an internal charge pump to generate its own switch-drive voltage.
Therefore, the 12-V supply can be powered down and only brought out of standby when flash memory needs
to be written to or erased. End equipment for the TPS2202 includes notebook computers, desktop computers,
personal digital assistants (PDAs), digital cameras, handiterminals, and bar-code scanners.
typical PC-card power-distribution application
VDD
I
Power Supply
12V
5V
3V
12V
5V
3V
3
PCMCIA
Controller
TPS2202
AVPP
AVCC
AVCC
AVCC
Serial Interface
APWR_GOOD
BPWR_GOOD
OC
I"
L
p
BVPP
BVCC
BVCC
BVCC
L
L
8
L
Vpp1
V pp2
VCC
VCC
PC
CardA
Vpp1
Vpp2
VCC
Vcc
PC
CardB
i'<-
V'-
CJ
linBiCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information Is cu".nt as 01 publication dale.
Products conform to apeclftcaflons per the terms or Texas Instruments
_ r d warranty. Production processing does net necessarily Include
lesltng 01 all peramelers.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-87
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
AVAILABLE OPTIONS
PACKAGED DEVICES
TJ
-40°C to 150°C
t
SHINK SMALL"()UTLINE
(DB)
SMALL"()UTLINE
TPS220210B
TPS220210F
(OF)
CHIP FORM
(Y)
TPS2202Y
The OF package IS only available left-end taped and reeled (Indicated by the LE suffix on the device type; e.g.,
TPS220210FLE).
Terminal Functions
TERMINAL
NAME
NO.
UO
DESCRIPTION
3V
15, 16, 17
I
3-V VCC input for card power
5V
1,2,30
I
5-V VCC input for card power
12V
AVCC
7,24
I
12-V VPP input for card power
9,10,11
0
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
8
0
13
0
Logic·level power-ready output that stays low as long as AVPP is within limits.
BVCC
20,21,22
0
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
BVPP
23
0
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
BPWR_GOOO
19
0
Logic·level power-ready output that stays low as long as BVPP is within limits.
4
I
Logic-level clock for serial data word
DATA
3
I
GNO
12
AVPP
APWR_GOOO
CLOCK
LATCH
NC
5
I
6,14,26,
27,28,29
OC
18
VOO
25
Logic·level serial data word
Ground
Logic-level latch for serial data word
No internal connection
0
Logic-level overcurrent reporting output that goes low when an overcurrent condition exists.
5-V power to chip
~TEXAS
6-88
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
TPS2202Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS2202. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
SV
SV
DATA
CLOCK
LATCH
NC
12V
AVPP
AVCC
AVCC
AVCC
GND
APWR_GOOD
NC
3V
(1)
(30) SV
(2)
(29) NC
(3)
(28) NC
(4)
(27) NC
(S)
(26) NC
(6)
(2S)
(7)
VDD
(24) 12V
(8)
TPS2201Y
(23) BVPP
(9)
(22) BVCC
(10)
(21) BVCC
(11)
(20) BVCC
(12)
(19) BPWR_GOOD
(13)
(18) OC
(14)
(17) 3V
(1S)
(16) 3V
CHIP THICKNESS: 1S MILS TYPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
TERMINALS 6,14,26,27,28, AND 29
ARE NOT CONNECTED
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-89
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Supply voltage range, Voo ............................. ,............................ -0.3 V to 7 V
Input voitage range for card power: VI(5V) ............................................. -0.3 V to 7 V
VI(3V) ........................................... -0.3 V to VI(5V)
VI(12V) ........................................... -0.3 V to 14 V
Logic input voltage ................................................................. -0.3 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Output current (each card): IO(xVCC) ............................................. internally limited
IO(xVpp) ............................................. internally limited
Operating virtual junction temperature range, T J ................................... : -40°C to 150°C
Operating free-air temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ........... f" • • • • • • • • • • • • • • • • • •• 260°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA S 25°C
POWER RATING
DB
1024mW
OF
1158mW
DERATING FACTOR*
ABOVE TA 25°C
=
=
TA 70°C
POWER RATING
TA 85°C
POWER RATING
8.2mW/OC
655mW
532mW
9.26mW/oC
741 mW
602mW
=
values are calculated using a derating factor based on RaJA = 108°C/W for the package.
These devices are mounted on an FR4 board with no special thermal considerations.
:1= Maximum
recommended operating conditions
MIN
MAX
UNIT
4.75
5.25
V
VI(5V)
0
5.25
V
VI(3V)
0
v
VI(12V)
0
VI(5V)t
13.5
Supply voltage, VOO
Input voltage range, VI
Output current, 10
V
10(xVCC) at 25°C
1
10(xVpp) at 25°C
150
mA
0
2.5
MHz
-40
125
°C
Clock frequency, 'clock
Operating virtual junction temperature, TJ
t VI(3V) should not be taken above VI(5V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
A
TPS2202,TPS2202V
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
electrical characteristics, TA
dc characteristics
=25°C, VDD =5 V (unless otherwise noted)
PARAMETER
Switch resistances t
TPS2202
TEST cONomONS
MIN
MAX
5VtoxVCC
160
3VtoxVCC
225
5VtoxVPP
6
3 VtoxVPP
6
12VtoxVPP
1
UNIT
mO
0
Clamp low voltage
Ipp at10mA
0.8
V
Clamp low voltage
ICC at 10mA
0.8
V
Ipp High-impedance state
Leakage current
ICC High-impedance state
1
TA=25°C
1
100
100 in shutdown
VO(BVCC) = VO(AVCC) = VO(AVPP)
= VOCBVPP) = high Z
83
Power-ready threshold, PWFLGOOO
IO(xVCC)
IO(xVpp)
10
I1A
50
TA=85°C
10.72
Power-ready hysteresis, PWR_GOOO (12-V mode)
Short-circuit output-current limit
10
50
TA=85°C
TA = 25°C
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
Input current
t
TYP
11.05
150
I1A
1
I1A
11.4
TJ = 85°C,
Output powered up into a short to GNO
V
mV
50
0.75
1.3
1.9
A
120
200
400
mA
Pulse-testing techniques maintain Junction temperature close to ambient temperature; thermal effects must be taken Into account separately.
switching characteristics*
PARAMETER
tr
tf
Output rise time
Output fall time
Propagation delay (see Figure 1§)
MIN
TYP
VO(xVCC)
1.2
VO(xVPP)
5
VO(xVCC)
10
VO(xVPP)
14
LATCHi to VO(xVPP)
Ipd
TPS2202
TEST CONomONS
-
LATCHi to xVCC (3 V)
LATCHi to xVCC (5 V)
Ion
5.8
Ioff
18
Ion
5.8
toff
28
Ion
4
loll
30
MAX
UNIT
ms
rns
ms
ms
ms
:j: Refer to Parameter Measurement Information
§ Propagation delays are with CL = 100 I1F.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655300 • DALLAS. TEXAs 75265
6-91
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
electrical characteristics, TA
=25°C, Voo =5 V {unless otherwise noted} {continued}
logic section
PARAMETER
TPS2202
TEST CONDITIONS
MIN
MAX
Logic input current
1
Logic input high level
2.7
0.8
10=1 rnA
Logic output low level
IIA
V
Logic input low level
Logic output high level
UNIT
V
V
VDD-0.4
0.4
V
dc characteristics
PARAMETER
Leakage current
Input current
TPS2202Y
TEST CONDITIONS
MIN
TYP
Ipp High-impedance state
1
ICC High-impedance state
1
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
100
MAX
IIA
IIA
83
Power-ready threshold, PWR..GOOD
11.05
Power-ready hysteresis, PWR GOOD (12-V mode)
UNIT
V
50
mV
switching characteristicst
PARAMETER
tr
tf
Output rise time
Output fall time
Propagation delay (see Figure fi:)
TYP
1.2
VO{xVPP)
5
VO(xVCC)
10
VO{xVPP)
14
LATCHi to xVCC
LATCHi to xVCC
*t
Refer to Parameter Measurement Information
Propagation delays are with CL = 100 !-IF.
~TEXAS
6-92
MIN
VO(xVCC)
LATCHi to VO(xVPP)
tpd
TPS2202Y
TEST CONDITIONS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Ion
5.8
loft
18
Ion
5.8
loft
28
Ion
4
loft
30
MAX
UNIT
ms
ms
ms
ms
ms
TPS2202,TPS2202V
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
1
Vpp
1
Vcc
TCl
TCl
-::
-::
lOAD CIRCUIT
lATCH
-1
lOAD CIRCUIT
~
50%
\
- - - - - :::
LATCH
I+-- toff~
Ion~
VO(XVPP)
.1
VDD
GND
l'--toff~
ton~
:
~--- VI(12V)
---./
1______
1\50%
~
GND
V
O(xVCC)
.:
:
---VI(5V)
I
~
VOLTAGE WAVEFORMS
0%
10%
GND
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Serial-Interlace Timing
2
xVCC Propagation Delay and Rise Times With 1-I1F Load, 3-V Switch
3
xVCC Propagation Delay and Fall Times With l-I1F Load, 3-V Switch
4
xVCC Propagation Delay and Rise Times With 100-I1F Load, 3-V Switch
5
xVCC Propagation Delay and Fall Times With 100-I1F Load, 3-V Switch
6
xVCC Propagation Delay and Rise Times With l-I1F Load, 5-V Switch
7
xVCC Propagation Delay and Fall Times W~h l-I1F Load, 5-V Switch
8
xVCC Propagation Delay and Rise Times With 100-I1F Load, 5-V Switch
9
xVCC Propagation Delay and Fall Times With 10o-l1F Load, 5-V Switch
10
xVPP Propagation Delay and Rise Times With l-I1F Load, 12-V Switch
11
xVPP Propagation Delay and Fall Times With l-I1F Load, 12-V Switch
12
xVPP Propagation Delay and Rise Times With 100-I1F Load, 12-V Switch
13
xVPP Propagation Delay and Fall Times With 100-I1F Load, 12-V Switch
14
DATA
LATCH
------------------------~~
CLOCK
NOTE A. Data is clocked in on the a positive leading edge of the clock. The latch should occur before next positive leading edge of
the clock. For definition of DO-D8, see control logic table.
Figure 2. Serial-Interface Timing
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-93
TPS2202, TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 Vldlv)
LATCH (2 Vldlv)
of.
I
I
lJ
xVCC (1 Vldlv)
I
I
o
2
3
4
xVCC (1 Vldiv)
5
678
9
o
5
10
15
20
25
35
40
t-TIme-ms
Figure 3. xVCC Propagation Delay and
Rise Times With 1-IlF Load, 3-V Switch
Figure 4. xVCC Propagation Delay and
Fall TImes With 1-IlF Load, 3-V Switch
LATCH (2 V/div)
\
~
II
o
2
3
"
~VCC (1 Vldlv)
J
xVCC (1 Vldiv)
4
45
LATCH (2 Vldiv)
/
5
6
7
8
o
9
5
t-TIme-ms
10
15
20
25
J.I
I
30
40
35
45
t-Time-ms
Figure 5. xVCC Propagation Delay and
Rise Times With 100-IlF Load, 3-V Switch
Figure 6. xVCC Propagation Delay and
Fall Times With 100-IlF Load, 3-V Switch
~TEXAS
INSTRUMENTS
6-94
30
t-TIme-ms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/dlv)
LATCH (2 V/dlv)
/'1"'"
/
V
)
xVCC (1 V/div)
~
xVCC (1 V/dlv)
o
2
o
4
3
5
10
t-Tlme-ms
15
20
Figure 7. xVCC Propagation Delay and
Rise Times With 1-I1F Load; S-V Switch
x~CC t1 v/~IV)
/
\
\
V
xVCC (1 V/div)
1
3
45
.\,
/
2
40
LATCH (2 V/dlv)
1
,I
35
~
I
o
30
Figure 8. xVCC Propagation Delay and
Fall Times With 1-I1F Load, SOV Switch
LATCH (2 V/dlv)
J
25
t-TIme-ms
4
5
6
7
8
o
9
5
t-TIme-ms
10
15
20
"
25
30
35
40
45
t-TIme-ms
Figure 9. xVCC Propagation Delay and
Rise Times With 100-I1F Load, SOV Switch
Figure 10. xVCC Propagation Delay and
Fall Times With 10D-I1F Load, S-V Switch
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-95
TPS2202,TPS2202Y
DUAL·SLOT PC CARD POWER·INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 Vldiv)
LATCH (2 V/dlv)
,-
xVPP (5 Vldiv) -
/
o
xVPP (5 Vldiv)
L
J
I
~
/
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
2
3
4
5
Figure 11. xVPP Propagation Delay and
Rise Times With 1-~F Load, 12-V Switch
xVPP (5 Vldlv)
V
.,/
o
2
/-
3
4
-
-
678
9
o
1\
5
t-Time-ms
9
"-
10
xVPP (5 Vldlv)
r--...
15
20
25
30
35
40
45
t-11me-ms
Figure 13. xVPP Propagation Delay and
Rise Times With 100-~F Load, 12-V Switch
Figure 14. xVPP Propagation Delay and
Fall Times With 100-~F Load, 12-V Switch
~TEXAS
INSTRUMENTS
6-96
8
LATCH (2 Vldiv)
./
5
7
Figure 12. xVPP Propagation Delay and
Fall Times With 1-~F Load, 12-V Switch
LATCH (2 Vldiv)
V
6
t-Time-ms
t-11me-ms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
Table of Graphs
FIGURE
IDD
Supply current
vs Junction temperature
15
rD~Lon)
Static drain-source on-state resistance, 3-V switch
vs Junction temperature
16
roS(on)
Static drain-source on-state resistance, 5-V switch
vs Junction temperature
17
rD~9n)
Static drain-source on-state resistance, 12-V switch
vs Junction temperature
VO(xVCC)
Output voltage, 5-V switch
vs Output current
18
19
20
VO(xVCC)
Output voltage, 3-V switch
vs Output current
xVpp
Output voltage, Vpp switch
vs Output current
21
ISC(xVCC)
Short-circuit current, 5-V switch
vs Junction temperature
ISC(xVPP)
Short-cIrcuit current, 12-V switch
vs Junction temperature
22
23
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
100
VO(AVCC) = VO(BVCC) = 5
v
VO(AVPP) = VO(BVPP) = 12 V
No load
95
t
I
1300
.;I"
1100
900
/
700
./'
500
-50
V
/
V
/
~
I
.",
I
~
oj>
V
-25
0
25
50
75
100
TJ - Junction Temperature - ·C
4.99
125
4.9 1----j----t---+---+-"""",j,L-'........:I---~
4.851----j----t---+---+----.+----h'''--l
4.81----j----j----+---+---+--+-----I
4.75'--_'--_'--_"--_"--_"--_"'-----'
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IO(xVCC) - Output Current - A
Figure 18
Figure 19
t t = pulse tested
~TEXAS
INSTRUMENTS
6-98
V
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
c;
I
o
TJ -
Figure 16
r;:
./
/'
/"
/'
POST OFFICE SOX 655303 • DALlAS, TEXAS 75265
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A - DECEMBER 1994 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
3-VSWITCH
VppSWITCH
OUTPUT VOLTAGE
OUTPUT VOLTAGE
vs
vs
OUTPUT CURRENT
OUTPUT CURRENT
12.05 r---r---r---,..-----,---r----,
3.35 r---r---r--...,.---,---r---,----,
VOO=5V
Vpp=12V
VOO=5V
VCC=3.3V
>
3.3
~--t---t---t--__t__---I---+--l
>
I
&
!!
I
3.25
~
io
_
I
3.2
i_
I-----t-~,.po.....-:""'""";;::-__t__--¥-
f----+-~--1~~~~~~~~
i
~
I
-:9
11.951-----l---"'...,.....,...::"""":--=""""I""""'~
~
3.15 I-----t---t---t--__t__--"'d--"'o,,.+--"'I
11.90 I---t---I---t---"'I~~d--"""f
~'6.
11.851-----t---1-----,----l---IT----"'I
3.1 \---t---t--__t__--'--7"'+--t-"IC:--l
3.05
11.80 '--_-'-_ _'--_-'-_--'_ _-'-_--.1
0.02
0.04
0.06
0.08
0.1
o
0.12
L-_-'-_-'-_~_-'-_--L_--L_--'
o
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IO(xVpp) - Output Current- A
IO(xVCC) - Output Current - A
Figure 20
Figure 21
5-VSWITCH
12-VSWITCH
SHORT-CIRCUIT CURRENT
SHORT-CIRCUIT CURRENT
vs
vs
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
400
2
VOO=5V
VCC=5V
00(
E
I
I
C
~
:I
CJ
1.5
:t=
:I
l:!
U
VOO=5V
Vpp=12V
00(
~
i:0
C
~
:I
CJ
r----
.c
1/1
I
U
CJ
~
350
300
"3
l:!
U
"
i:0
250
.c
1/1
I
200
--......... """-
iL
a..
~
CJ
1/1
r--
150
..!!'
0.5
-50
100
o
50
100
TJ - Junction Temperature - °C
150
-so
Figure 22
100
o
50
TJ - Junction Temperature - °C
150
Figure 23
t t = pulse tested
-!II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655:J03 • DALLAS, TEXAS 752~5
6-99
TPS2202,TPS2202V
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold: modems, wireless LANs, GPS systems,
multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the
engineering community quickly recognized the need for a standard to ensure compatibility across platforms.
To this end, the PCMCIA (Personal Computer Memory Card I nternational Association) was established and was
comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key
goal was to realize the concept of plug and play - cards and hosts from different vendors should be compatible
and able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the ,PC Card connector's 68 pins. This power interface consists of two Vee, two Vpp' and four ground
pins. Multiple Vee and ground pins minimize connector-pin and line resistance. The two Vpp pins were originally
specified as separate signE:!ls but are commonly tied together in the host to form a single node to minimize
voltage losses. Card primary power is supplied through the Vee pins; flash~memory programming and erase
voltage is supplied through the Vpp pins. As each pin is rated to 0.5 A, Vee and Vpp can theoretically supply up
to 1 A, assuming equal pin resistance and no pin failure. A conservative design would limit current to 500 rnA.
Some applications, however, require higher Vee currents; disk drives, for example, may need as much as
750-mA peak current to create the initial torque necessary to spin up the platter. Vpp currents, on the other hand,
are defined by flash-memory programming requirements, typically under 120 rnA.
future power trends
The 1-A physical-pin current alluded to in the PC Card specification has caused some host-system engineers
to believe they are required to deliver 1 A within the voltage tolerance of the card. Future applications, such as
RF cards, could use the extra power for their radio transmitters. The 5 W needed for these cards will require
very robust power supplies and special cooling considerations. The limited number of host sockets that will be
able to support them makes the market for these high-powered PC Cards uncertain. The vast majority of the
cards require less than 600 rnA continuous current and the trend is towards even lower-powered PC Cards that
will assure compatibility with a greater number of host systems. Recognizing the need for power derating, an
adhoc committee of the PCMCIA is currently working to limit the amount of steady-state dc current to the
PC Card to something less than the currently implied 1 A. If a system is designed to support 1 A, then the switch
rOS(on), power supply requirements, and PC Card cooling need to be carefully considered.
designing around 1-A delivery
Delivering 1 A means minimizing voltage (and power) losses across the PC Card power interface, which
requires that designers trade off switch resistance and the cost associated with large-die (lOW rOS(on) MOSFET
transistors. The PC Card standard requires that 5 V ±5%, or 3.3 V ±O.3 V be supplied to the card. The
approximate 10% tolerance for the 3.3-V supply makes the 3.3-V rOS(on) less critical than the 5-V switch. A
conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and terminal-resistance
drops, which leaves 2% (100 mY) voltage drop for the 5-V switch, and at least 6% (198 mY) for the 3.3-V switch.
=
=
Calculating the rOS(on) necessary to support a 100 mV or 198 mV switch loss, using R Ell and setting I 1 A,
the 5-V and 3.3-V switches would need to be 100 mO and 198 mO respectively. One solution would be to pay
for a more expensive switch with lower rOS(on)' A second, less expensive approach is to increase the headroom
of the power supply-for example, to increase the 5-V supply 1.5% or to 5.075 ±2%. Working through the
numbers once more, the 2% for the regulator plus 1 % for etch and terminal losses leaves 97% or 4.923 V.
~TEXAS
6-100
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
designing around 1·A delivery (continued)
The allowable voltage loss across the power distribution switch is now 4.923 V minus 4.7S0 V or 173 mY.
Therefore, a switch with 173 mil or less could deliver 1 A or greater. Setting the power supply high is a common
practice for delivering voltages to allow for system switch, connector, and etch losses and has a minimal effect
on overall battery life. In the example above, setting the power supply 1.S% high would only decrease a 3-hour
battery life by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running
a S-W PC Card.
heat dissipation
A greater concern in delivering 1 A or S W is the ability of the host to dissipate the heat generated by the PC
Card. For desktop computers the solution is simpler: locate the PC Card cage such that it receives convection
cooling from the forced air of the fan. Notebooks and other handheld equipment are not be able to rely on
convection, but must rely on conduction of heat away from the PC Card through the rails into the card cage. This
is difficult because PC Card/card cage heat transfer is very poor. A typical design scenario would require the
PC Card to be held at 60°C maximum with the host platform operating as high as SO°C. Preliminary testing
reveals that a PC Card can have a 20°C rise, exceeding the 10°C differential in the example, when dissipating
less than 2 W of continuous power. The 60°C temperature was chosen because it is the maximum operating
temperature allowable by PC Card specification. Power handling requirements and temperature rises are topics
of concern and are currently being addressed by the PCMCIA committee.
overcurrent and over-temperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. This can be particularly frustrating to the
consumer who has already experienced proplems with shortened battery life due to improper Nicad conditioning
or memory effect. Most hosts include fuses for protection. The reliability of fused systems is poor, though, as
blown fuses require troubleshooting and repair, usually by the manufacturer. The TPS2202 takes a two-pronged
approach to overcurrent protection. First, instead of fuses, sense FETs monitor each of the power outputs.
Excessive current generates an error signal that linearly limits the output current, preventing host damage or
failure. Sense FETs, unlike sense resistors or polyfuses, have the added advantage that they do not add to the
series resistance of the switch and thus produce no additional voltage losses. Second, when an overcurrent
condition is detected, the TPS2202 asserts a signal at DC that can be monitored by the microprocessor to initiate
diagnostics and/or send the user a warning message. In the event that an overcurrent condition persists,
causing the Ie to exceed its maximum junction temperature, thermal-protection circuitry engages, shutting
down all power outputs until the device cools to within a safe operating region.
12·V supply not required
Most PC Card switches use the externally supplied 12-V Vpp power for switch-gate drive and other chip
functions, requiring that it be present at all times. The TPS2202 offers considerable power savings by using an
internal charge pump to generate the required higher voltages from the S-V Voo supply; therefore, the external
12-V supply can be disabled except when needed for flash-memory functions, thereby extending battery
lifetime. Additional power savings are realized by the TPS2202 during a software shutdown, in which quiescent
current drops to a maximum of 1 !lA.
voltage transitionlng requirement
PC Cards, like portables, are migrating from S V to 3.3 V to minimize power.consumption, optimize board space,
and increase logic speeds. The TPS2202 is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/S-V systems by first powering
the card with S V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
6-101
TPS2202,TPS2202Y
DUAL·SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
voltage transitioning requirement (continued)
capacitors on 3.3-V compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions'as a power reset. The
TPS2202 offers a selectable Vee and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching
specifications, to fully discharge the card capacitors while switching between Vee voltages.
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of Vee within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100 kO resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to over 2 seconds. The only way to ensure timing compatibility with PC Card standards
is to use a power-distribution switch that has an internal ground switch, like that of the TPS22xx family, or add
an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2202 is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in 5-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2202 offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2202 has multiple terminals for each of its 3.3 V, 5 V, and 12 V power inputs and for the switched Vee
outputs. Any individual terminal can conduct the rated input or output current. Unless all terminals are connected
in parallel, the series resistance is significantly higher than that specified, resulting in increased voltage drops
and lost power. Both 12 V inputs must be connected for proper Vpp switching; it is recommended that all input
and output power terminals be paralleled for optimum operation. The Voo input lead must be connected to the
5V input leads.
Although the TPS2202 is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-I1F electrolytic or tantalum capacitor paralleled by
a 0.047-I1F to 0.1-I1F ceramic capacitor. It is strongly recommended that the switched Vee and V pp outputs be
bypassed with a 0.1-I1F or larger capacitor; doing so improves the immunity of the TPS2202 to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2202 and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance.
The TPS2202, unlike other PC Card power-interface switches, does not use the 12-V power supply for switching
or other chip functions. Instead, an internal charge pump generates the necessary voltage from Voo, allowing
the 12-V input supply to be shut down except when the Vpp programming or erase voltage is needed. Careful
system design making use of this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Doing so, though nondestructive, results
in high currentflow into the device, and could result in abnormal operation. In any case, this occurrence indicates
a malfunction of one input voltage or both, which should be investigated.
Similarly, no terminal should be taken below -0.3 V; forward biasing the parasitic-substrate diode results in
substrate currents and unpredictable performance.
~.TEXAS'
INSTRUMENTS
6-102
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
overcurrent and thermal protection
The TPS2202 uses sense FETs to check for overcurrent conditions in each of the Vee and V pp outputs. Unlike
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
During power up, the TPS2202 controls the rise time of the Vee and Vpp outputs and limits the current into a
faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2202 engages. If the Vee
or V pp outputs are driven below ground, the TPS2202 may latch nondestructively in an off state. Cycling power
reestablishes normal operation.
Overcurrent limiting for the Vee outputs is designed to engage if powered up into a short in the range of
0.75 A to 1.9 A, typically at about 1.3 A; the Vpp outputs limit from 120 mA to 400 mA, typically around 200 mAo
The protection circuitry acts by linearly limiting the current passing through the switch, rather than initiating a
full shutdown of the supply. Shutdown occurs only during thermal limiting.
Thermal limiting prevents destruction of the IC from overheating when the package power-dissipation ratings
are exceeded. Thermal limiting, disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rOS(on), is dependent on the junction temperature, TJ, ofthe die. The junction temperature
is dependent on both rOS(on) and the current through the switch. To calculate T J, first find rOS(on) from Figures
16, 17, and 18 using an Initial temperature. estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
P D = rDS(on) • 12
Next, sum the power dissipation and calculate the junction temperature:
TJ
= (~
P D . RaJA)
+ T A'
RaJA
=
108°C/W
Compare the calculated junction temperature with the initial temperature estimate. If they are not within a few
degrees of each other, reiterate using the calculated temperature as the initial estimate.
logic input and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading
edge of the clock (see Figure 2). The 9-bit (DO through D8) serial data word is loaded during the positive edge
of the latch signal. The latch signal should occur before the next positive leading edge of the clock.
The shutdown bit of the data word places all Vee and Vpp outputs in a high-impedance state and reduces chip
quiescent current to 1 !lA to conserve battery power.
The TPS2202 serial interface is designed to be compatible with serial-interface PCMCIA controllers and current
PCMCIA and JEIDA standards.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the Vee or Vpp outputs,
as previously discussed.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-103
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
r---------------------------,
TPS2202
.
/
I,:h
S7
~
~Sl
1
18
'I
Ie
52
53
3V
3V
~S4
3V
S5
~S10
S6
SV
Sll
2
SV
S12
30
SV
12V
12V
CS
7
24
Internal
Current Monitor
1----0:'-+---+-------1
~~~~K}
I----'S'-1-----..-----i LATCH
Serial
Interface
25
1--------1--Controller
r-~le~---._----1BPWR_GOOD
13
1
r-=--jl----+------I APWR_GOOD
r-~18~--~----~OC
GND 1--_---,
1
1
_ ____ J
~_____________________
12
Figure 24. Internal Switching Matrix
~TEXAS
6-104
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
VDD
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONfROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
TPS2202 control logic
AVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8SHDN
DO A_VPP _PGM
D1 A_VPP VCC
S7
S8
S9
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
vcct
VAVPP
1
1
0
OPEN
OPEN
CLOSED
VPP(12V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
BVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8SHDN
D4 B_VPP_PGM
D5 B_VPP_VCC
S10
Sll
S12
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
VCC:!:
1
1
0
OPEN
OPEN
CLOSED
VPP(12V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
VBVPP
Avec
INTERNAL SWITCH SETTINGS
CONTROL SIGNALS
OUTPUT
D8SHDN
D3A_VCC3
D2A_VCCS
Sl
S2
53
VAVCC
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
BVCC
CONTROL SIGNALS
OUTPUT
INTERNAL SWITCH SETTINGS
D8SHDN
D6B_VCC3
D7B_VCC5
54
S5
S6
VBVCC
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
t
Output depends on AVCC
:!: Output depends on BVCC
ESD protection
All TPS2202 inputs and outputs incorporate ESO-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STO-883C, Method 3015. The Vee and Vpp outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-~F capacitors protects the devices from discharges up to 10 kV.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-105
TPS2202,TPS2202Y
DUAL-SLOT PC CARD POWER-INTERFACE SWITCHES
FOR SERIAL PCMCIA CONTROLLERS
SLVS103A- DECEMBER 1994 - REVISED AUGUST 1995
APPLICATION INFORMATION
SV
I
vDD
AVCC
12V
L
AVCC
AVCC
12V
±
p
O.1IlF
BVCC
±
O.1IlF
AVPP
3V
t
t
AVPP
vcc
1 o.
1 o.
W
PC Card
Connector A
~)
R
TPS2202
SV
vcc
Vpp1
Vpp2
12V
BVCC
BVCC
SV
...
L
-=-
L
VCC
VCC
r-- Vpp1
PC Card
ConnectorB
.--- Vpp2
1 1lF
~}
-=-
SV
SV
BVPP
BVPP
3V
3V
W
1 1lF
DATA
3V
DATA
CLOCK
CLOCK
LATCH
LATCH
PCMCIA
Controller
APWR_GOOD
AVPPGOOD
BVPPGOOD
BPWR_GOOD
OC
f----.--
To CPU
GND
CS
J.
Shutdown Signal
From CPU
Figure 25. Detailed Interconnections and Capacitor Recommendations
~TEXAS
'6-106
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
I
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SEPTEMBER 1995
OF OR DB PACKAGE
• Fully Integrated Vee and Vpp Switching for
Dual-Slot PC Card™ Interface
• p2CTM 3-Lead Serial Interface Compatible
With CardBus™ Controllers
• Meets PC Card Standards
• RESET Allows System Initialization of PC
Cards
• 12-V Supply Can Be Disabled Except
During 12-V Flash Programming
• Short Circuit and Thermal Protection
• Space-Saving 30-Pin SSOP (DB) Package
• Compatible With 3.3-V, 5-Vand 12-V PC
Cards
• Power Saving 100 = 83 J.lA Typ, IQ = 1 J.lA
• Low rOS(on) (160-mn Vee Switch)
• Break-Before-Make Switching
(TOP VIEW)
5V
NC
NC
NC
NC
5V
5V
DATA
CLOCK
LATCH
RESET
12V
AVPP
AVCC
AVCC
AVCC
GND
APWR_GOOD
RESET
Voo
12V
BVPP
BVCC
BVCC
BVCC
BPWR_GOOD
OC
3.3V
3.3V
3.3V
NC - No internal connection
description
The TPS2202AI PC Card power-interface switch provides an integrated power-management solution for two
PC Cards. All of the discrete power MOSFETs, a logic section, current limiting, thermal protection, and
power-good reporting for PC Card control are combined on a single integrated circuit (IC), using the Texas
Instruments LinBiCMOSTM process. The circuit allows the distribution of 3.3-V, S-V, and/or 12-V card power by
means of the P2C (PCMCIA Peripheral-Control) Texas Instruments nonproprietary serial interface. The
current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability.
Current-limit reporting can help the user isolate a system fault to a specific card.
The TPS2202AI incorporates a reset function, selectable by one of two inputs, to help alleviate system errors.
The reset function enables PC Card initialization concurrent with host platform initialization, allowing a system
reset. Reset is accomplished by grounding the VCC and Vpp (flaSh-memory programming voltage) outputs,
which discharges residual card voltage.
End equipment forthe TPS2202AI includes notebook computers, desktop computers, personal digital assistants
(PDAs), digital cameras, handiterminals, and bar-code scanners. The TPS2202AI is only available taped and
reeled (either TPS2202AIDFLE or TPS2202AIDBLE).
LinBiCMOS and P2C are trademarks of Texas Instruments Incorporated.
PC Card and CardBus are trademarks of PCMCIA (Personal Computer Memory Card International Association).
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-107
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123 - SEPTEMBER 1995
typical PC card power-distribution application
VDD
Power Supply
12V
12V
sv
AVPP
3.3V
3.3 V
Supervisor
TPS2202AI
sv
~
3
RESET
RESET
Serial Interface
APWR_GOOD
BPWR_GOOD
oc
PCMCIA
Controller
AVCC
AVCC
II
AVCC
L
p
L
BVPP
BVCC
BVCC
BVCC
L
L
8
Vpp1
Vpp2
VCC
VCC
PC
CardA
Vpp1
Vpp2
VCC
Vce
PC
CardB
I'r-
V'I'r-
Terminal Functions
TERMINAL
NAME
3.3V
5V
12V
AVCC
NO.
VO
DESCRIPTION
15,16, 17
I
3.3-V VCC input for card power
1,2,30
I
5-V VCC input for card power
7,24
I
12-V Vpp input for card power
9,10,11
Switched output that delivers 3.3 V, 5 V, low or high impedance to card
Logic-level power-ready output that remains low as long as BVPP is within limits
BVCC
20,21,22
BVPP
23
0
0
0
0
0
BPWR_GOOD
19
0
CLOCK
4
I
Logic-level clock for serial data word
DATA
3
I
Logic-level serial data word
GND
12
AVPP
APWR GOOD
LATCH
8
13
5
NC
26,27,
28,29
OC
Switched output that delivers 3.3 V, 5 V, 12 V, low or high impedance to card
Logic-level power-ready output that stays low as long as AVPP is within limits
Switched output that delivers 3.3 V, 5 V, low or high impedance
Switched output that delivers 3.3 V, 5 V, 12 V, low or high impedance
Ground
I
Logic-level latch for serial data word
No il1temal connection
18
0
RESET
6
I
RESET
14
I
Logic-level RESET input active low. Do not connect if tenninal 6 is used.
VDD
25
I
5-V power to chip
Logic-level overcurrent reporting output that goes low when an overcurrent condition exists
Logic-level RESET input active high. Do not connect if tenninal 14 is used.
~TEXAS
INSTRUMENTS
6-108
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted}t
Supply voltage range, Voo .......................................................... -0.3 V to 7 V
Input voltage range for card power: VI(5V) ............................................. -0.3 V to 7 V
VI(3.3V) ......................................... -0.3 V to VI(5V)
VI(12V) ........................................... -0.3 V to 14 V
Logic input voltage ................................................................. -0.3 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Output current (each card): IO(xVCC) ............................................. internally limited
IO(xVpp) ............................................. internally limited
Operating virtual junction temperature range, TJ .................................... -40°C to 150°C
Operating free-air temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ......... . . . . . . . . . . . . . . . . . . . . .. 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated condHions for extended periods may affect device reliabilHy.
DISSIPATION RATING TABLE
=
=
PACKAGE
TA,,25°C
POWER RATING
DERATINGFACTOR*
ABOVE TA 25°C
TA 70°C
POWER RATING
TA 85°C
POWER RATING
OF
1158mW
9.26mW/oC
741 mW
602mW
DB
1024mW
8.2mW/oC
655mW
532mW
=
* These devices are mounted on an FR4 board with no special thermal considerations.
recommended operating conditions
MIN
MAX
UNIT
4.75
5.25
V
VI(5~
0
5.25
V
VI(3.3V)
0
VI(5V)§
V
VI1121f)
0
13.5
V
Supply voltage, VDD
Input voltage range, VI
Output current
IO(xVCC) at 25°C
1
IO(xVpp) at 25°C
150
A
rnA
0
2.5
MHz
-40
125
°C
Clock frequency
Operating virtual junction temperature, TJ
§ VI(3.3V) should not be taken above VI(5V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-109
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER1995
electrical characteristics, TA
=25°C, Voo =5 V (unless otherwise noted)
dc characteristics
PARAMETER
Switch resistances t
TEST CONDITIONS
TYP
MAX
160
3.3VtoxVCC
225
5VtoxVPP
6
3.3 Vto xVPP
6
12VtoxVPP
1
UNIT
mn
n
VO(xVPPl
Clamp low voltage
IDDat 10mA
0.8
V
VO(xVCC)
Clamp low voltage
Iccat10mA
0.8
V
TA = 25°C
Ipp High-impedance
state
Ilkg
II
1
TA=25°C
ICC High-impedance
state
Power-ready hysteresis,
PWR_GOOO
Short-circuit outputcurrent limit
VO(AVCC) = VO(BVCC) = 5 V,
VOiAVPP)=VO(BVPP)=12V
100 Supply current
in shutdown
VO(BVCC) = VO(AVCC)= VO(AVPP)
= VO(BVPP) = Hi-Z
83
10.72
11.05
12-Vmode
10(xVpp)
..
10
IiA
50
TA = 85°C
100 Supply current
10(xVCC)
10
50
TA=1l5°C
Leakage current
Input current
1
Power-ready threshold,
PWR..GOOO
t
MIN
5VtoxVCC
150
IiA
1
IiA
11.4
50
TJ = 85°C,
Output powered up into a short to GNO
V
mV
0.75
1.3
1.9
A
120
200
400
rnA
Pulse-testing techniques are used to maintain Junction temperature close to ambient temperature; thermal effects must be taken Into account
separately.
logic section
TEST CONDITIONS
PARAMETER
MIN
Logi(l input current
1
Logic input high level
2
Logic input low level
10=1 mA
Logic output low level
~TEXAS
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS, TEXAS 75265
IiA
V
V
VOO-0.4
0.4
1
Logic input minimum pulse width
UNIT
V
0.8
Logic output high level
6-110
MAX
V
IJ.S
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
switching characteristicst
PARAMETER
tr
tf
Output rise times
Output fall times
TEST CONDITIONS
MIN
VO(xVPP)
5
VO(xVCC\
10
LATCHt to VO(xVPP)
Propagation delay (see Figure 1:j:)
LATCHt to xVCC (3 V)
LATCHt to xVCC (5 V)
MAX
UNIT
ms
14
VO(xVPP)
tpd
TYP
1.2
VO(xVCC\
ton
5.8
ms
loft
18
ms
Ion
5.8
ms
toft
28
ms
Ion
4
ms
loft
30
ms
t
Refer to Parameter Measurement Information
:j: Propagation delays are with CL = 100 j!F.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-111
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
Vpp
1
Vcc
TCl
TCl
-=-
-=-
lOAD CIRCUIT
lATCH J , 5 0 %
\ - - - - - - :::
~
ton
VO(xVPP)
r4
lOAD CIRCUIT
.1
~
1\50%
LATCH
I...
tOff---+l
%
:
I
I'll
ton
~
10%
, - - - VI(12V)
VO(xVCC)
GND
1______
.1
VDD
GND
Ioff~
I
I
I
90%
, - - - . VI(5V)
~
10%
VOLTAGE WAVEFORMS
GND
VOLTAGE WAVEFORMS
Figure 1. Test Circuits and Voltage Waveforms
Table of Timing Diagrams
FIGURE
Serial-Interface Timing
2
xVCC Propagation Delay and Rise Time With l-!1F load, 3.3-V Switch
3
xVCC Propagation Delay and Fall Time With l-!1F Load, 3.3-V Switch
4
xVCC Propagation Delay and Rise Time With 100-!1F Load, 3.3-V Switch
5
xVCC Propagation Delay and Fall Time With l00-!1F Load, 3.3-V Switch
6
xVCC Propagation Delay and Rise Time With l-!1F Load, 5-V Switch
7
xVCC Propagation Delay and Fall Time With l-!1F Load, 5-V Switch
8
xVCC Propagation Delay and Rise Time With 100-!1F Load, 5-V Switch
9
xVCC Propagation Delay and Fall Time With 10Q-!1F Load, 5-V Switch
10
xVPP Propagation Delay and Rise Time With l-!1F Load, 12-V Switch
11
xVPP Propagation Delay and Fall Time With l-!1F Load, 12-V Switch
12
xVPP Propagation Delay and Rise Time With 100-!1F Load, 12-V Switch
13
xVPP Propagation Delay and Fall Time With 100-!1F Load, 12-V Switch
14
DATA
LATCH
------------------------~~
CLOCK
NOTE A. Data is clocked in on the positive leading edge of the clock. The latch should occur before next positive leading edge of the
clock. For definition of DO to D8, see the control logic table.
Figure 2. Serial-Interface Timing
~TEXAS
INSTRUMENTS
6-112
POST OFFICE BOX 655303 • OALlAS, TEXAS 75265
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/div)
LATCH (2 V/div)
,f,
I
I
~
xVCC (1 V/div)
I
o
2
3
4
xVCC (1 V/div)
5
6
7
8
9
o
5
10
15
20
25
30
35
40
t-TIme-ms
t-Tlme-ms
Figure 3. xVCC Propagation Delay and
Rise Time With 1-I.lF Load, 3.3-V Switch
Figure 4. xVCC Propagation Delay and
Fall Time With 1-I.lF Load, 3.3-V Switch
LATCH (2 V/div)
/
o
2
3
LATCH (2 V/div)
,
I
~
'KVCC (1 V/div)
J
xVCC (1 V/dlv)
4
45
5
6
7
8
o
9
5
t-TIme-ms
10
15
20
25
J..
I
I
30
35
40
45
t-TIme-ms
Figure 5. xVCC Propagation Delay and
Rise TIme With 100-I.lF Load, 3.3-V Switch
Figure 6. xVCC Propagation Delay and
Fall TIme With 100-I.lF Load, 3.3-V Switch
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
6-113
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 V/dlv)
/
LATCH (2 V/div)
/'
V
I
/
j
xVCC (1 V/div)
xVCC (1 V/dlv)
o
o
4
3
2
5
10
t-Time-ms
15
20
25
30
35
40
45
t-Time-ms
Figure 7. xVCC Propagation Delay and
Rise nme With 1-IlF Load, S-V Switch
Figure 8. xVCC Propagation Delay and
Fall nme With 1-IlF Load, S-V Switch
x~CC ~1 v/~Iv)
LATCH (2 V/dlv)
I
V
LATCH (2 V/div)
~
:.\.
\,
J
/
V
I"
xVCC (1 V/dlv)
1
o
,I
,I
2
3
4
5
6
7
8
o
9
5
t-Time-ms
15
20
25
30
35
40
45
t-Tinie-ms
Figure 9. xVCC Propagation Delay and
Rise Time With 10o-IlF Load, S-V Switch
Figure 10. xVCC Propagation Delay and
Fall Time With 100-IlF Load, S-V Switch
~TEXAS
6-114
10
INSTRUMENTS
POST OFACE BOX 655303 • DAUAS. TEXAS 75265
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
LATCH (2 Vldiv)
LATCH (2 Vldiv)
'\
xVPP (5 Vldlv) -
/~
J
o
xVPP (5 Vldlv)
\
o
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
2
t-Tlme-ms
3
4
I
5
I
I
678
9
t-Tlme-ms
Figure 11. xVPP Propagation Delay and
Rise TIme With 1-J,tF Load, 12-V Switch
Figure 12. xVPP Propagation Delay and
Fall TIme With 1-J,tF Load, 12-V Switch
LATCH (2 Vldlv)
LATCH (2 Vldlv)
~
xVPP (5 VldIv)
V
o
/'
2
V
3
V
4
1\
5
6
7
8
9
o
5
t-Tlme-ms
'"
10
xVPP (5 Vldlv)
~
15
20
25
30
35
40
45
t-Tlme-ms
Figure 13. xVPP Propagation Delay and
Rise TIme With 1QO-J,tF Load, 12-V Switch
Figure 14. xVPP Propagation Delay and
Fall TIme With 10G-J,tF Load, 12-V Switch
~TEXAS
INSTRUMENTS
POST OFFICE BOX 8S5303 • DALLAS. TEXAS 75265
6-115
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123- SEPTEMBER 1995
TYPICAL CHARACTERISTICSt
Table of Graphs
FIGURE
100
Supply current
vs Junction temperature
15
roS(ol'lt
roS(on)
Static drain-source on-state resistance. 3-V switch
vs Junction temperature
16
Static drain-source on-state resistance. 5-V switch
vs Junction temperature
17
rOS(on)
Static drain-source on-state resistance. 12-V switch
vs Junction temperature
18
VOlxVCC)
Output voltage. S-V switch
vs Output current
19
VO(xVCC)
Output voltage. 3.3-V switch
vs Output current
20
xVpp
Output voltage. Vpp switch
vs OUtput current
21
ISC(xVCC)
Short-circuit current. S-V switch
vs Junction temperature
22
ISC(xVPP)
Short-circuit current. 12-V switch
vs Junction temperature
23
SUPPLY CURRENT
va
JUNCTION TEMPERATURE
100
VO(AVCC)
VO(AVPP)
No load
=VO(BVCC) =5 V
=VO(BVPP) =12 V
95
c(
::I.
I
i
90
::J
U
~
DD::J
85
III
I
Q
E
80
75
-50
.".,....
---"'.....
.--
./
./
o
50
100
TJ - Junction Temperature - °C
Figure 15
t t =pulse tested
~TEXAS
6-116
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
150
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123 - SEPTEMBER 1995
TYPICAL CHARACTERISTICSt
a
3.3-V SWITCH
S-VSWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
E
400
I
I
-=II:
I
I
Voo=5V
VCC =3.3V
350
2SO
.,./
200
V
~
V
,
!
220
VOO=5V
VCC=5V
!
200
~
........V'"
1SO
240
i
./
300
a
~
flc
S
100
50
o
-50
o
25
so 75 100
TJ - Junction Temperature - °C
-25
125
160
U}c
140
&
.2
!
120
ic
..iii
80
I
V
./
180
/"
~
I
i
100
-so
-25
12-VSWITCH
S-VSWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
125
5.05,---,---,....--,....--r---r---,...---,
1700
VOO=5V
Vpp= 12V
1500
>
J
I
./
V
~
o 25 50 75 100
TJ - Junction Temperature - °C
Figure 17
V
~
V
."
/"
Figure 16
a
V
./
/
soo
-50
/'
."
4.95
~
./
."
V
-25
0
25
so 75
TJ - Junction Temperature -
100
125
°c
4.75 L--_'--_'--_'--_.L.-_.L.-_.l.---I
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
IO(xVCC) - Output Current - A
Figure 18
Figure 19
t t = pulse tested
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-117
TPS2202AI
DUAL·SLOT PC CARD POWER·INTERFACE/SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123- SEPTEMBER 1995
TYPICAL CHARACTERISTICSt
3-VSWITCH
VppSWITCH
OUTPUT VOLTAGE
OUTPUT VOLTAGE
va
va
OUTPUT CURRENT
OUTPUT CURRENT
12.05 ...----,.....---,.--..----,.....---,.----,
3.35 ...---...--...--...--..----'-..---..-----,
VOO=5V
VCC = 3.3.3 V
3.3 10.:::-+--+--+--+--+--+---1
>
3.25
!=
12M=-4---4---I--4---4---4
t
I---+~~~~=--+--¥~
~
3.2 I----t----t---,....,..".".::t-"""'::I-a''----'.......,..---\
I
~
>
I
I
-~...~
VOO=5V
Vpp =12 V
3.15
.J'
I--+--+--+--+-~r-::~+-----"'"I
1'.951---t---"'Ioo?-.o:""''k::-=''''fo;;d-
i
o
1_ 1'.901---t---+--+--~~~--=-i
Do
Do
~
>'
3.1
1'.B51---4---4---.---4----j,.L----"I
I----+--+---I---I---/--I--.p,~
85°C
3.05 L-_..L.-_..L.-_..L.-_..L.-_..L.-_..L.---..I
o 0.1 0.2 0.3 0.4 0.5 0.6 0.7
1'.BOL-_...I-_--I._ _..L.-_...I-_--I._--..I
0.02
0.04
0.06
0.08
0.1
0.12
o
IO(xVpp) - Output Current - A
IO(xVCC) - Output Current - A
Figure 20
Figure 21
5-VSWITCH
12-VSWITCH
SHORT·CIRCUIT CURRENT
SHORT·CIRCUIT CURRENT
va
va
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
400
2
VOO=5V
VCC=5V
200
>
5-
5-til
.!!'
0.5
-50
o
50
100
TJ - Junction Temperature - °C
150
r--
150
100
-50
Figure 22
o
100
50
TJ - Junction Temperature - °C
Figure 23
t I = pulse lested
~TEXAS
6-118
------
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
150
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
APPLICATION INFORMATION
overview
PC Cards were initially introduced as a means to add EEPROM (flash memory) to portable computers with
limited on-board memory. The idea of add-in cards quickly took hold; modems, wireless LANs, GPS systems,
multimedia, and hard-disk versions were soon available. As the number of PC Card applications grew, the
engineering community quickly recognized the need for a standard to ensure compatibility across platforms.
To this end, the PCMCIA (Personal Computer Memory Card International Association) was established,
comprised of members from leading computer, software, PC card, and semiconductor manufacturers. One key
goal was to realize the "plug and play" concept. Cards and hosts from different vendors should be compatible able to communicate with one another transparently.
PC Card power specification
System compatibility also means power compatibility. The most current set of specifications (PC Card Standard)
set forth by the PCMCIA committee states that power is to be transferred between the host and the card through
eight of the PC Card connector's 68 terminals. This power interface consists of two Vee, two Vpp , and four
ground terminals. Multiple Vee and ground terminals minimize connector-terminal and line resistance. The two
Vpp terminals were originally specified as separate signals but are commonly tied together in the host to form
a single node to minimize voltage losses. Card primary power is supplied through the Vee terminals;
flash-memory programming and erase voltage is supplied through the V pp terminals. As each terminal is rated
to 0.5 A, Vee and Vpp can theoretically supply up to 1 A, assuming equal terminal resistance and no terminal
failure. A conservative design would limit current to 500 mAo Some applications, however, require higher Vee
currents. Disk drives, for example, may need as much as 750-mA peak current to create the initial torque
necessary to spin up the platter. Vpp currents, on the other hand, are defined by flash-memory programming
requirements, typically under 120 mAo
future power trends
The 1-A physical-terminal current alluded to in the PC Card specification has caused some host-system
engineers to believe they are required to deliver 1 A within the voltage tolerance of the card. Future applications,
such as RF cards, could use the extra powerfortheir radio transmitters. The 5 W required for these cards require
very robust power supplies and special cooling considerations. The limited number of host sockets that are able
to support cards makes the market for these high-powered PC Cards uncertain. The vast majority of the cards
require less than 600 rnA continu.ous current and the trend is towards even lower powered PC Cards that assure
compatibility with a greater number of host systems. Recognizing the need for power derating, an ad hoc
committee of the PCMCIA is currently working to limit the amount of steady-state dc current to the
PC Card to something less than the currently implied 1 A. When a system is designed to support 1 A, the switch
rOS(on), power-supply requirements, and PC Card cooling need to be carefully considered.
designing around 1-A delivery
Delivering 1 A means minimizing voltage and power losses across the PC Card power interface, which requires
that designers trade off switch resistance and the cost associated with large-die (low rOS(on») MOSFET
transistors. The PC Card standard requires that 5 V ±5% or 3.3 V ±0.3 V be supplied to the card. The
approximate 10% tolerance for the 3.3-V supply makes the 3.3-V rOS(on) less critical than the 5-V switch. A
conservative approach is to allow 2% for voltage-regulator tolerance and 1% for etch- and pin-resistance drops,
which leaves 2% (100 mV) for voltage drop at the 5-V switch and at least 6% (198 mV) for the 3.3-V switch.
=
=
Calculating the rOS(on) necessary to support a 100 mV or 198 mV switch loss, using R Ell and setting I 1 A,
the 5-V and 3.3-V switches would need to be 100 rna and 198 rna respectively. One solution would be to pay
for a more expensive switch with lower rOS(on)' A second, less expensive approach is to increase the headroom
ofthe power supply-for example, to increase the 5 V supply 1.5% or to 5.075 ±2%. Working through the numbers
once more, the 2% for the regulator plus 1 % for etch and terminal losses leaves 97% or 4.923 V. The allowable
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-119
TPS2202AI'
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123 - SEPTEMBER 1995
APPLICATION INFORMATION
designing around 1-A delivery (continued)
voltage loss across the power distribution switch is now 4.923 V minus 4.750 V or 173 mV. Therefore, a switch
with 173 mQ or less could deliver 1 A or greater. Setting the power supply high is a common practice for
delivering voltages to allow for system switch, connector, and etch losses. This practice has a minimal effect
on overall battery life. In the example above, setting the power supply 1.5% high would only decrease a 3-hour
battery life by approximately 2.7 minutes, trivial when compared with the decrease in battery life when running
a 5-W PC Card.
heat dissipation
A greater concern in delivering 1 A or 5 W is the ability of the host to dissipate the heat generated by the PC
Card. For desktop computers the solution is simpler: locate the PC Card cage such that it receives convection
cooling from the forced air of the fan. Notebooks and other handheld equipment will not be able to rely on
convection, but on conduction of heat away from the PC Card through the rails into the card cage. This is difficult
because PC Card/card cage heat transfer is very poor. A typical design scenario would require the PC Card to
be held at 60°C maximum with the host platform operating as high as 50°C. Preliminary testing reveals that a
PC Card can have a 20°C rise, exceeding the 10°C differential in the example, iNhen dissipating less than 2 W
of continuous power. Sixty degrees centigrade was chosen because it is the maximum operating temperature
allowable by PC Card specification. Power handling requirements and temperature rises are topics of concern
and are currently being addressed by the PCMCIA committee.
overcurrent and over-temperature protection
PC Cards are inherently subject to damage that can result from mishandling. Host systems require protection
against short-circuited cards that could lead to power supply or PCB-trace damage. Even systems sufficiently
robust to withstand a short circuit would still undergo rapid battery discharge into the damaged PC Card,
resulting in the rather sudden and unacceptable loss of system power. This can be particularly frustrating to the
consumer who has already experienced problems with shortened battery life due to improper Nicad conditioning
or memory effect. Most hosts include fuses for protection. The reliability of fused systems is poor though, as
blown fuses require troubleshooting and repair, usually by the manufacturer.
The TPS2202AI takes a two-pronged approach to overcurrent protection. First, instead of fuses, sense FETs
monitor each of the power outputs. Excessive current generates an error signal that linearly limits the output
current, preventing host damage or failure. Sense FETs, unlike sense resistors or polyfuses, have an added
advantage in that they do not add to the series resistance of the switch and thus produce no additional voltage
losses. Second, when an overcurrent condition is detected, the TPS2202AI asserts a signal at OC that can be
monitored by the microprocessor to initiate diagnostics and/or send the user a warning message. In the event
that an overcurrent condition perSists, causing the IC to exceed its maximum junction temperature,
thermal-protection circuitry activates, shutting down all power outputs until the device cools to within a safe
operating region.
12-V supply not required
Most PC Card switches use the externally supplied 12-V Vpp power for switch-gate drive and other chip
functions, which requires that power be present at all times. The TPS2202AI offers considerable power savings
by using an internal charge pump to generate the required higher voltages from the 5-V Voo supply; therefore,
the external 12-V supply can be disabled except when needed'for flash-memory functions, thereby extending
battery lifetime. Additional power savings are realized by the TPS2202AI during a software shutdown in which
quiescent current drops to a maximum of 1 /lA.
'~TEXAS
INSTRUMENTS
6-120
POST OFFICE BOX 655303 e. DALLAS, TEXAS 75265
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
APPLICATION INFORMATION
voltage transitioning requirement
PC Cards, like portables, are migrating from S V to 3.3 V to minimize power consumption, optimize board space,
and increase logic speeds. The TPS2202AI is designed to meet all combinations of power delivery as currently
defined in the PCMCIA standard. The latest protocol accommodates mixed 3.3-V/5-V systems by first powering
the card with 5 V, then polling it to determine its 3.3-V compatibility. The PCMCIA specification requires that the
capacitors on 3.3-V-compatible cards be discharged to below 0.8 V before applying 3.3-V power. This ensures
that sensitive 3.3-V circuitry is not subjected to any residual 5-V charge and functions as a power reset. The
TPS2202AI offers a selectable Vee and Vpp ground state, in accordance with PCMCIA 3.3-V/5-V switching
specifications, to fully discharge the card capacitors while switching between Vee voltages.
output ground switches
Several PCMCIA power-distribution switches on the market do not have an active-grounding FET switch. These
devices do not meet the PC Card specification requiring a discharge of Vee within 100 ms. PC Card resistance
can not be relied on to provide a discharge path for voltages stored on PC Card capacitance because of possible
high-impedance isolation by power-management schemes. A method commonly shown to alleviate this
problem is to add to the switch output an external 100 kQ resistor in parallel with the PC Card. Considering that
this is the only discharge path to ground, a timing analysis will reveal that the RC time constant delays the
required discharge time to more than 2 seconds. The only way to ensure timing compatibility with PC Card
standards is to use a power-distribution switch that has an internal grounc;! switch, like that ofthe TPS22xx family,
or add an external ground FET to each of the output lines with the control logic necessary to select it.
In summary, the TPS2202AI is a complete single-chip dual-slot PC Card power interface. It meets all currently
defined PCMCIA specifications for power delivery in S-V, 3.3-V, and mixed systems, and offers a serial controller
interface. The TPS2202AI offers functionality, power savings, overcurrent and thermal protection, and fault
reporting in one 30-pin SSOP surface-mount package for maximum value added to new portable designs.
power supply considerations
The TPS2202AI has multiple pins for each of its 3.3-V, S-V, and 12-V power inputs and for the switched Vee
outputs. Any individual pin can conduct the rated input or output current. Unless all pins are connected in parallel,
the series resistance is significantly higher than that specified, resulting in increased voltage drops and lost
power. Both 12-V inputs must be connected for proper V pp switching; it is recommended that all input and output
power pins be paralleled for optimum operation. The VDD input lead must be connected to the 5-V input leads.
Although the TPS2202AI is fairly immune to power input fluctuations and noise, it is generally considered good
design practice to bypass power supplies typically with a 1-~F electrolytic or tantalum capacitor paralleled by
a 0.047-~F to 0.1-~F ceramic capacitor. It is strongly recommended that the switched Vee and Vpp outputs be
bypassed with a 0.1-~F or larger capacitor; doing so improves the immunity of the TPS2202AI to electrostatic
discharge (ESD). Care should be taken to minimize the inductance of PCB traces between the TPS2202AI and
the load. High switching currents can produce large negative-voltage transients, which forward biases substrate
diodes, resulting in unpredictable performance.
The TPS2202AI, unlike other PC Card power-interface switches, does not use the 12-V power supply for
switching or other chip functions. Instead, an internal charge pump generates the necessary voltage from VDD,
allowing the 12-V input supply to be shut down except when the Vpp programming or erase voltage is needed.
Careful system design using this feature reduces power consumption and extends battery lifetime.
The 3.3-V power input should not be taken higher than the 5-V input. Though doing so is nondestructive, this
results in high current flow into the device and could result in abnormal operation. In any case, this occurrence
indicates a malfunction of one input voltage or both which should be investigated.
Similarly, no pin should be taken below -0.3 V; forward biasing the parasitic-substrate diode results in substrate
currents and unpredictable performance.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
6-121
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER.1995
APPLICATION INFORMATION
RESET or RESET inputs
To ensure that cards are in a known state after power brownouts or system initialization, the PC Cards should
be reset at the same time as the host by applying a low impedance to the Vee and Vpp terminals. A
low-impedance output state allows discharging of residual voltage remaining on PC Card filter capacitance,
permitting the system (host and PC Cards) to be powered up concurrently. The RESET or RESET input will close
internal switches S 1, S4, S7, and S1 0 with all other switches left open (see TPS2202AI control-logic table). The
TPS2202AI remains in the low-impedance output state until the signal is deasserted and further data is clocked
in and latched. RESET or RESET is provided for direct compatibility with systems that use either an active-low
or active-high reset voltage supervisor. The unused pin is internally pulled up or down and should be left
unconnected.
overcurrent and thermal protection
The TPS2202AI uses sense FETs to check for overcurrent conditions in each of the Vee and V pp outputs. Unlike
sense resistors or polyfuses, these FETs do not add to the series resistance of the switch; therefore, voltage
and power losses are reduced. Overcurrent sensing is applied to each output separately. When an overcurrent
condition is detected, only the power output affected is limited; all other power outputs continue to function
normally. The OC indicator, normally a logic high, is a logic low when any overcurrent condition is detected,
providing for initiation of system diagnostics and/or sending a warning message to the user.
Ouring power up, the TPS2202AI controls the rise time of the Vee and Vpp outputs and limits the current into
a faulty card or connector. If a short circuit is applied after power is established (e.g., hot insertion of a bad card),
current is initially limited only by the impedance between the short and the power supply. In extreme cases, as
much as 10 A to 15 A may flow into the short before the current limiting of the TPS2202AI engages. If the Vee
orVpp outputs are driven below ground, the TPS2202AI may latch nondestructively in an off·state. Cycling power
will reestablish normal operation.
Overcurrent limiting for the Vee outputs is designed to activate if powered up, into a short in the range of
0.75 A to 1.9A, typically at about 1.3A. The Vppoutputs limit from 120 mA to 400 mA, typically around 200 mAo
The protection circuitry acts by linearly limiting the current passing through the switch rather than initiating a full
shutdown of the supply. Shutdown occurs only during thermal limiting.
Thermal limiting prevents destruction of the IC from overheating if the package power-dissipation ratings are
exceeded. Thermal limiting disables all power outputs (both A and B slots) until the device has cooled.
calculating junction temperature
The switch resistance, rOS(on), is dependent onthe junction temperature, TJ, ofthe die. The junction temperature
is dependent on both rOS(on) and the current through the switch. To calculate TJ, first find rOS(on) from Figures
16, 17, and 18 using an Initial temperature estimate about 50°C above ambient. Then calculate the power
dissipation for each switch, using the formula:
Po = rOS(on) x 12
Next, sum the power dissipation and calculate the junction temperature:
TJ
= (~
Po x RaJA)
+ T A'
RaJA
= 108°C/W
Compare the calculated junction temperature with the initial temperature estimate. If the temperatures are not
within a few degrees of each other, recalculate using the calculated temperature as the initial estimate.
6-122
-!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
APPLICATION INFORMATION
logic input and outputs
The serial interface consists of DATA, CLOCK, and LATCH leads. The data is clocked in on the positive leading
edge of the clock (see Figure 2). The 9-bit (DO through 08) serial data word is loaded during the positive edge
of the latch signal. The latch signal should occur before the next positive leading edge of the clock.
The shutdown bit of the data word places all Vee and Vpp outputs in a high-impedance state and reduces chip
quiescent current to 1 ItA to conserve battery power.
The TPS2202AI serial interface is designed to be compatible with serial-interface PCMCIA controllers and
current PCMCIA and Japan Electronic Industry Development Association (JEIDA) standards.
An overcurrent output (OC) is provided to indicate an overcurrent condition in any of the Vee or Vpp outputs as
previously discussed.
W
==
:;
w
a:
Q.
ti
;::)
c
oa:
Q.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
6-123
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123-SEPTEMBER 1995
APPLICATION INFORMATION
r---------------------------,
I
TPS2202AI
B-cS7
~o-----<
0-3.3V
3.3V
3.3V
!
5V
12V
12V
I
Supervisor
I
S6
1
-0--
I
120
B---~
VCC
I
VCC
-~
~
S12
I
I
VCC
Q
Vpp1
j23
52J
pp2
LV____
_
71
24
I
i
I
I
I
I
Internal
Current Monitor
6
14 :
3
4
5
RESET
RESET
H
I
I
DATA
}
CLOCK
!
!
LATCH
Thermal
19
I
I
I
I
I
13
!
18
I
Controller
II
I
Serial
Interface
I
;25
' ~
BPWR_GOOD
APWR_GOOD
GND
m
OC
,
~---------------------
______ J
12
Figure 24. Internal Switching Matrix
~TEXAS
6-124
j221
S11
I
17
1211511
~
30
Vpp2
r"Ca--;dS--
U
S5
5V
17
I
I
I
T51 lLVCC
____ _
i
B-cS4
2
!
C~
~o-----<
5V
11
CS
"V
16
17
1101
S3
I
Vpp1
19
S9
-0--
,.,....--~
15
18
I
I
S8
S1
r----CardA
18
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
Voo
TPS2202AI
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVSI23-SEPTEMBER 1995
APPLICATION INFORMATION
TPS2202AI control logic
AVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
08SHON
DO JLVPP_PGM
01 A_VPP_ VCC
S7
S8
S9
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
vcct
1
1
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
VAVPP
BVPP
CONTROL SIGNALS
OUTPUT
INTERNAL SWITCH SETTINGS
D8SHDN
D4 B_VPP_PGM
05 B_VPP_VCC
.810
S11
S12
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
VCC:!:
1
1
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
VBVPP
Avec
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8SHDN
D3A_VCC3
D2A_VCC5
SI
S2
S3
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
3.3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
VAVCC
BVCC
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
D8SHDN
D6B_VCca
07B_VCCS
S4
S5
S6
1
0
0
CLOSED
OPEN
OPEN
VBVCC
OV
1
0
1
OPEN
CLOSED
OPEN
3.3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
t Output depends on AVCC
:!: Output depends on BVCC
ESC protection
All TPS2202AI inputs and outputs incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C, Method 3015. The Vee and Vpp outputs can be
exposed to potentially higher discharges from the external environment through the PC Card connector.
Bypassing the outputs with 0.1-I1F capacitors protects the devices from discharges up to 10 kV.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-125
TPS2202AI
DUAL·SLOT PC CARD POWER·INTERFACE SWITCH
WITH RESET FOR SERIAL PCMCIA CONTROLLER
SLVS123 - SEPTEMBER 1995
APPLICATION INFORMATION
5V
I
VDD
12V
L
12V
8
BVCC
R
3.3 V
L
0.111F
5V
Vcc
Vcc
Vpp1
Vpp2
PC Card
Connector A
<)
i
AVPP
W
1::
BVPP
BVPP
W
1::
AVPP
t
t
....
12V
BVCC
BVCC
TPS2202AI
5V
i
AVCC
AVCC
AVCC
L
0.111F
-
-=-
VCC
VCC
Vpp1
PC card
ConnectorB
I - - - Vpp2
0.1!1F
~}
5V
5V
3.3V
3.3V
3.3V
0.111F
DATA
CLOCK
DATA
CLOCK
LATCH
LATCH
RESET 1-- - RESET
J--+
System Voltage
Supervisor
or
Bus Reset
PCMCIA
Controller
--""
APWR_GOOD
BPWR_GOOD
OC
AVPPGOOD
BVPPGOOD
-+--
ToCPU
GND
CS
~
Shutdown Signal
From CPU
Figure 25. Detailed Interconnections and Capacitor Recommendations
~TEXAS
6-126
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 752115
I
TPS22051
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLER
1995
• Fully Integrated Vee and Vpp Switching for
Dual-Slot PC Card™ Interface
• Suspend Mode (3.3 V only)
• Compatible With Controllers From Cirrus,
Intel, and Texas Instruments
• Meets PCMCIA Standards
• Internal Charge Pump (No External
Capacitors Required) -12-V Supply Can Be
Disabled Except for Programming
• Short Circuit and Thermal Protection
• SSOP (30) Package Less than 2 mm High
• Compatible With 3.3-V, 5-V and 12-V PC
Cards
• Power Saving 100 = 8311A Typ, IQ = 1 IIA
• Low rOS(on) (1SQ-mn 5-V Switch; 200-mn
3.3-V SWitch)
• Break-Before-Make Switching
DF or DB PACKAGE
(TOP VIEW)
5V
B_VPP_PGM
B_VPP_VCC
B_VCC5
B_VCC3
NC
12V
BVPP
BVCC
BVCC
BVCC
NC
5V
5V
A_VPP_PGM
A_VPP_VCC
A_VCC5
A_VCC3
12V
AVPP
AVCC
AVCC
AVCC
GND
NC
SHDN
3.3V
DC
3.3V
3.3V
NC - No Intemal Connection
;:
description
W
The TPS2205 PC Card (PCMCIA) power interface switch provides an integrated power-management solution
for two PC Cards. All of the discrete power MOSFETs, a logic section, current limiting and reporting, and thermal
protection for PC Card control are combined on a single integrated circuit (IC), using the Texas Instruments
LinBiCMOSTM process. The circuit allows the distribution of 3.3-V, 5-V and/or 12-V card power and is compatible
with most PCMCIA controllers. The suspend mode allows the TPS2205 to operate off of 3.3-V input pins during
modem or pager operations. The current-limiting feature eliminates the need for fuses, which reduces
component count and improves reliability; current-limit reporting can help the user isolate a system fault to a
bad card.
The TPS2205 maximizes battery life by generating its own switch-drive voltage using an internal charge pump.
Therefore, the 12-V supply can be powered down and only brought out of standby when flash memory needs
to be written to or erased. End equipment for the TPS2205 includes notebook computers, desktop computers,
personal digital assistants (PDAs), digital cameras, handiterminals, and bar-code scanners.
The TPS22051 is only available in the DB package, left-end taped and reeled (indicated by the LE suffix on the
device type; when ordering, specify TPS2205IDBLE).
linBiCMOS is a trademark of Texas Instruments Incorporated.
PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association).
PRODUCT PREVIEW information concoms prod_In the _
or
_
phIae 01 _pment. _ o t i c data .... on..
spoclftcailons
......._
lgngoals. lDaI_...... _therightlo
change ... d_
~wllhoutnotlc:o.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DA~, TEXAS 752115
6-127
s:w
a:
Q.
I(.)
~
C
oa:
Q.
TPS22051
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLER
SLVS128-OCTOBEF\ 1995
typical PC Card power distribution application
vDD
Power Supply
V TPS2205IDB
12
AVPP
5V
3.3V
AVCC
AVCC
SHDN';
AVCC
12V
5V
3.3 V
CPU
I
8
Control Lines
BVPP
OC
BVCC
BVCC
BVCC
PCMCIA
Controller
fr
L
L
=f
L
L
=+
Vpp1
Vpp2
VCC
VCC
PC
CardA
Vpp1
Vpp2
VCC
VCC
PC
CardB
'v--
}-
J
absolute maximum ratings over operating free-air temperature (unless otherwise noted}t
."
:II
o
C
c:
o-I
."
:II
m
-
<
m
:IE
Supply voltage range, Voo .......................................................... -0.3 V to 7 V
Input voltage range for card power: VI(5V) ............................................. -0.3 V to 7 V
VI(3.3V) ......................................... -0.3 V to VI(5V)
VI(12V) ..................... : ..................... -0.3 V to 14 V
Logic input voltage .........•....................................................... -0.3 V to 7 V
Continuous total power diSsipation .......•............................. See Dissipation Rating Table
Output current (each card): IO(xVCC) ...... ;...................................... internally limited
IO(xVpp) ............................•................ internally limited
Operating virtual junction temperature range, TJ .................................... -40°C to 150°C
Operating free-air temperature range, TA ............•............................... -40°C to 85°C
Storage temperature range, Tstg ................................................. .-55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA S 25°C
POWER RATING
OF
1158mW
DB
1024mW
=
TA 70°C
POWER RATING
9.26mW/OC
741 mW
602mW
8.2mW/oC
655mW
532mW
=
,
TA 85°C
POWER RATING
:I: These devices are mounted on an FR4 board with no special thermal considerations.
~TEXAS
6-128
=
DERATING FACTOR*
ABOVE TA 25°C
INSTRUMENTS
POST OFFICE BOX 655303 • OAUAS, TEXAS 75265
TPS22051
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLER
SLVS128-OCTOBER 1995
Terminal Functions
TERMINAL
NO,
NAME
UO
DESCRIPTION
A_vee3
6
I
Logic input that controls voltage on AVeC (see control-logic table)
A..Vee5
5
I
Logic input that controls voltage on AVeC (see control-logic table)
Logic input that controls voltage on AVPP (see control-logic table)
A_VPP_PGM
3
I
A VPP vee
4
I
Logic input that controls voltage on AVPP (see control-logic table)
0
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
AVeC
9,10,11
AVPP
8
0
B_Vee3
26
I
Logic input that controls voltage on BVee (see control-logic table)
B_Vee5
27
I
Logic input that controls voltage on BVee (see control-logic table)
B..:VPP_PGM
29
I
Logic input that controls voltage on BVPP (see control-logic table)
B_Vpp_vee
28
I
Logic input that controls voltage on BVPP (see controHogic table)
BVee
20,21,22
0
Switched output that delivers 0 V, 3.3 V, 5 V, or high impedance
BVPP
23
0
Switched output that delivers 0 V, 3.3 V, 5 V, 12 V, or high impedance
SHON
14
I
Logic input that shuts down the TPS2205 and set all power outputs to high-impedance state
0
Logic-level overcurrent reporting output that goes low when an overcurrent condition exists
oe
18
VOO
25
5-V power to chip
GNO
12
Ground
3.3V
15,16,17
I
3.3-V Vee in for card power
5V
1,2,30
I
5-V Vee in for card power
12V
7,24
I
12-V VPP in for card power
Ne
13,19
3:
w
:;:
w
a:
Q.
~
(J
recommended operating conditions
:::)
Supply voltage, VOO
Input voltage range, VI
Output current
MAX
UNIT
TBO
TBO
V
VI(5V)
0
5.25
V
VJL3.3V~
0
VIl5V1 t
V
VI(12V)
0
13.5
V
10(xVeel at 25°C
1
10(xVpp) at 25°C
150
mA
125
°e
Operating virtual junction temperature, TJ
t
MIN
-40
A
VI(3 V) should not be taken above VI(5 V).
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6-129
C
oa:
Q.
TPS22051.
.' , ,.
,
DUAL-SLOT PC CARD POWt:R-INTERFAC,E SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLE'R
SLVS128-OCTOBER 1995
electrical characteristics, TA = 25°C, Voo = 5 V (unless otherwise noted)
dc characteristics
PARAMETER .,
Switch resistances
TEST CONDITIONS
MIN
TYP
MAX
UNIT
5 VtoxVCC
150
ma
3.3VtoXVCC
200
ma
3.3VtoxVCC
500
Suspend mode
5 VtoxVPP
ma
6
6
(
3.3V to xVPP
a
1
12 VtoxVPP
VO(xVPP)
Clamp low voltage
IIJI)at10mA
0.8
V
VOLxVCCl
Clamp /ow voltage
ICC at 10mA
0.8
V
Leakage current
Input current
Ipp High-impedance
state
TA = 25°C
icc
TA = 25°C
VO(AVCC) = VO(BVCC) = 5 V,
VO(AVPP) = VO(BVPP) = 12 V
100 Supply current
in shutdown
VO(BVCC) = VO(AVCC) = VO(AVPP)
= VO(BVPP) = high Z
Short-circuit outputcurrent limit
12-Vmode
IO(xVpp)
83
150
IIA
1
IIA
11.4
V
11.05
mV
50
TJ=85°C,
Output shorted to GNO
~TEXAS
6-130
10
50
10.72
IO(xVCC)
INSTRUMENTS
POST OFFICE BOX 855303 • DALlAS. TEXAS 75265
IIA
1
TA = 85°C
100 Supply current
10
50
TA=85°C
High-impedance
state
Power-ready threshold,
PWR_GOOO
Power-ready hysteresis,
PWR_GOOO
1
1
120
A
200
400
mA
TPS22051
DUAL-SLOT PC CARD POWER-INTERFACE SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLER
SLVS128-OCTOBER 1995
electrical characteristics, TA = 25°C, Voo = 5 V (unless otherwise noted) (continued)
logic section
PARAMETER
TEST CONDITIONS
MAX
MIN
Logic input current
1
Logic input high level
2
0.8
lo=lmA
Logic output low level
!1A
V
Logic input low level
Logic output high level
UNIT
V
V
VOO-O.4
0.4
V
switching characteristicst
PARAMETER
tr,tf
Output rise and fall times
TEST CONDITIONS
Propagation delay (see Figure 1'1:)
TYP
MAX
UNIT
1.2
ms
VO(xVCCl fall time
10
ms
VO(xVPP\ rise time
5
ms
VO(xVPPl fall time
14
ms
Ion
5.8
ms
Ioff
18
ms
ton
5.8
ms
Ioff
28
ms
Ion
4
ms
Ioff
30
ms
VI(lLVPP_PGMl to VO(xVPP)
tpd
MIN
VO(xVCC\ rise time
VI(x_VCC3) to xVCC
VI (x_VCC5) to xVCC
t Refer to Parameter Measurement Information
W
==
:;
w
a:
a..
:j: Rise and fall times are with CL = 100 ~F.
I-
o
:::»
c
o
a:
a..
~TEXAS
INSTRUMENTS
POST OFACE BOX 655303 • OALLAS, TEXAS 75265
6-131
TPS22051
DUAL·SLOT PC CARD POWER·INTERFACE SWITCH
WITH SUSPEND MODE FOR PARALLEL PCMCIA CONTROLLER
SLVS128-0CTOBER 1995
APPLICATION INFORMATION
TPS2205 control logic
AVPP
CONTROL SIGNALS
INTERNAL SWITCH SETTINGS
OUTPUT
SHDN
A VPP PGM
A VPP VCC
S7
S8
S9
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
vcct
1
1
0
OPEN
OPEN
CLOSED
VPP(12 V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
OPEN
OPEN
OPEN
Hi-Z
,
VAVPP
BVPP
INTERNAL SWITCH SETTINGS
CONTROL SIGNALS
OUTPUT
SHDN
B_VPP_PGM
B_VPP_VCC
510
S11
S12
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
VCc:j:
1
1
0
OPEN
OPEN
CLOSED
VPP(12V)
1
1
1
OPEN
OPEN
OPEN
Hi-Z
0
X
X
,OPEN
OPEN
OPEN
Hi-Z'
o"
:D,
C
VBVPP
c: Avec
o-t
CONTROL SIGNALS
A_VCC3
A_VCC5
51
52
S3
VAVCC
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
":Dm
-
<
m
~
OUTPUT
INTERNAL SWITCH SETTINGS
SHDN
BVCC
CONTROL SIGNALS
OUTPUT
INTERNAL SWITCH SETTINGS
SHDN
B_VCC3
B_VCC5
54
55
56
1
0
0
CLOSED
OPEN
OPEN
OV
1
0
1
OPEN
CLOSED
OPEN
3V
1
1
0
OPEN
OPEN
CLOSED
5V
1
1
1
CLOSED
OPEN
OPEN
OV
0
x
X
OPEN
OPEN
OPEN
Hi-Z
t Output depends on AVCC
:j: Output depends on BVCC
~TEXAS
6--132
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VBVCC
I Optoisolators
7-1
Contents
•
o
-g,
o
iii"
o
-o...
...
m
tn
Page
4N2x
Optocouplers ................................................. 7-3
4N3x
Optocouplers .................................................. 7-7
6N13x
OptocouplersiOptoisolators .............................. , 7-13
. HCPL4502 OptocouplersiOptoisolators ............................... 7-13
MCT2
Optocouplers ................................................ 7-23
MCT2E
Optocouplers ............ , ................................... 7-23
MOC3009 Optocouplers/Optoisolators ............................... 7-29
MOC301x Optocouplers/Optoisolators ............................... 7-29
MOC302x Optocouplers/Optoisolators ................. : ............. 7-35
TIL 19x
Optocouplers ................................................ 7-41
TIL19xA Optocouplers ................................................ 7-41
TIL 19xB Optocouplers ................................................ 7-41
TIL300
Precision Linear Optocoupler .............................. 7-47
TIL300APrecision Linear Optocoupler .............................. 7-47
TIL3009
OptocouplersiOptoisolators ............................... 7-51
TIL301 x
Optocouplers/Optoisolators ............................... 7-51
TIL302x
Optocouplers/Optoisolators ............................... 7-57
TPS5904 Opto-Isolated Feedback Amplifiers ........................ 7-63
TPS5904A Opto-Isolated Feedback Amplifiers ........................ 7-63
7-2
4N25,4N26,4N27,4N28
OPTOCOUPLERS
SOES020 - SEPTEMBER 1978 - REVISED OCTOBER 1995
COMPATIBLE WITH STANDARD TTL INTEGRATED CIRCUITS
• Gallium-Arsenide-Diode Infrared Source
Optically Coupled to a Silicon npn
Phototransistor
• High Direct-Current Transfer Ratio
• High-Voltage Electrical Isolation
2.S-kV, 1.S-kV, or O.S-kV Rating
• Plastic Dual-Inline Package
• High-Speed Switching
tr = 2 ~s, tf = 2 ~s Typical
4N25, 4N26, 4N27, OR 4N28 •.. PACKAGE
(TOP VIEW)
ANODE
CATHODE
NC
01
2
3
6
5
4
BASE
COLLECTOR
EMITTER
NC - No intemal connection
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)f
4N25 .................................................... ± 2.5 kV
4N26, 4N27 .................................. _. . . . . . . . . .. ± 1.5 kV
4N28 ........................ _. . . . . . . . . . . . . . . . . . . . . . . . . .. ± 0.5 kV
Collector-base voltage:t .................................................................... 70 V
Collector-emitter voltage:\: (see Note 1) ...................................................... 30 V
Emitter-collector voltage:t .................................................................... 7 V
Emitter-base voltage ........................................................................ 7 V
Input-diode reverse voltage:t ............................................................ _. . .. 3 V
Input-diode continuous forward current at (or below) 25°C free-air temperature:t (see Note 2) ...... 80 mA
Input-diode peak forward current:t (tw =300 I1s, duty cycle = 2 %) ...... _............ _. . . . . . . . . . . .. 3 A
Continuous power dissipation at (or below) 25°C free-air temperature:t:
Infrared-emitting diode (see Note 3) ................................................. 150 mW
Phototransistor (see Note 3) ........................................................ 150 mW
Total, infrared-emitting diode plus phototransistor (see Note 4) .......................... 250 mW
Storage temperature range,Tstg:t ....... _. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds:t ............................ _. 260°C
Peak input-to-output voltage:t:
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure 10 absolute-maximum-rated conditions for extended periods may affect device reliability.
:t: JEDEC registered data. This data sheet contains all applicable JEDEC-registered data in effect at the lime of publication.
NOTES: 1. This value applies when the base-emitter diode is open-circulated.
2. Derate linearly to 100 °C free-air temperature at the rate of 1.33 mAloC.
3. Derate linearly to 100°C free-air temperature at the rate of 2 mW/oC.
4. Derate linearly to 100°C free-air temperature at the rate of 3.33 mW/oC.
~TEXAS
Copyright © 1995, Texas Inslruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
7-3
4N25,4N26,4N27,4N28
OPTOCOUPLERS
SOES020 - SEPTEMBER 1978 - REVISED OCTOBER 1995
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
4N25,4N26
TEST CONDITIONS
MIN
TYP
4N27,4N28
MAX
MIN
TYP
MAX
UNIT
V(SR)CSOt
Collector-base
breakdown voltage
IC.= lOOI1A• IE=O.
IF=O
70
70
V
V(SR)CEOt
Collector-emitter
breakdown voltage
IC=l mAo
le=O.
IF=O
30
30
V
V(SRECO)t
Emitter-collector
breakdown voltage
IE = 100 1lA. IS=O.
IF=O
7
7
V
IRt
Input diode static
reverse current
VR=3V
IC(on)t
On-state collector
current (phototransistor
operation)
VCE=10V. IS=O.
IF= 10mA
IC(on)
On-state collector
current (phototransistor
operation)
Vce=10V. IE=O.
IF=10mA
IC(Off)t
Off-state collector
current (phototrahsistor
operation)
VCE= 10V. le=O.
IF=O
1
50
1
50
nA
IC(off)t
Off-state collector
current (photodiode
operation)
Vce=10V. IE=O.
IF=O
0.1
20
0.1
20
nA
VFt
Input diode static
forward voltage
IF=10mA
1.25
1.5
1.25
1.5
V
VCE(sat)t
Collector-emitter
saturation voltage
IC=2mA.
0.25
0.5
0.25
0.5
V
qO
Input-to-output internal
resistance
Vin-out = ±2.5 kV for 4N25.
±1.5 kV for 4N26. 4N27.
±D.5 kV for 4N28.
See Note 5
Clo
Input-to-output
capacitance
Vin-out=O.
See Note 5
100
100
IS=O,
2
1
5
20
IF=50mA
1011
1012
f=l MHz.
1011
1
IlA
3
mA
20
IlA
1012
Q
pF
1
t JEDEC registered data
NOTE 5: These parameters are measured between both input diode leads shorted together and all the phototransistor leads shorted together.
switching characteristics
PARAMETER
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
TEST CONDITIONS
TYP
Phototransistor operation
2
PhotodiOde operation
VCC=10V.IE=0.
IC(on) 20 IlA
RL = 1 kCl, See Test Circuit e of Figure 1
1
·~TEXAS
7-4
MIN
VCC= 10V. le=O,
IC(on)2mA
RL = 100 Cl, See Test Circuit A of Figure 1
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
2
1
MAX
UNIT
I1S
I1S
4N25,4N26,4N27,4N28
OPTOCOUPLERS
SOES020 - SEPTEMBER 1978 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
47g
"'-+---4"--- Output
(see Note B)
VCC=10V
47g
Input
r---'''-''''-'''<~f\/'v- Input
RL=100g
OV
L
.J
~ 14- tr Output
--.t 14- tf
!~!
jflO%
TEST CIRCUIT A
PHOTOTRANSISTOR OPERATION
10%'l
Output
'----4/>-- (see Note B)
+
-=- Vee = 10V
VOLTAGE WAVEFORMS
RL = 1 kr.I
TEST CIRCUIT B
PHOTODIODE OPERATION
NOTES: A. The input waveform is supplied by a generator with the foUowing characteristics: Zo = 50 g, tr:!> 15 ns, duty cycle'" 1%.
B. The output waveform is monItored on an oscilloscope with the following characteristics:, tr :!> 12 ns, Ain 20 pF.
MECHANICAL INFORMATION
The package consists of a gallium-arsenide infrared-emitting diode and an npn silicon phototransistor mounted
on a 6-lead frame encapsulated within an electrically nonconductive plastic compound. The case can withstand
soldering temperature with no deformation and device performance characteristics remain stable when
operated in high-humidity conditions. Unit weight is approximately 0.52 grams.
9,40 (0.370) '4
.,
::a
0®®
(see Note C)
5,48 (0.215)
2,92 (0.115)
1,78(0.010)
o51 (0 020)
14-------l*_ 7,82 (0.300) T.P.
14--.,..-W+- 8,61 (0.260)
8,09 (0.240)
seaUng Plane
--+I /4- 1,78 (0.070) MAX
. _____~'t~1
1J-..II.-
----r-
+_____ _
2,29 (0.090)
3,81 (0.150) 1,27(0.050)
-'
8Placea
1_
~ ~ 1,01 (0.040) MIN
0,534 (0.021)
0,381 (0.018)
3,17 (0.125\ 2,54 (0.100) T.P.
8 Places
(see Note A)
NOTES: A. Leads are within 0,13 (O.OOS) radius' of true position (T.P.) with maximum material condition and unit installed.
B. Pin 1 identified by index dot.
C. Terminal connections:
1. Anode (part of the infrared-emitting diode)
2. Cathode (part of the infrared-emitting diode)
3. No intemal connection
4. Emitter (part of the phototransistor)
5. Collector (part of the phototransistor)
6. Base (part of the phototransistor)
D. The dimensions given fall within JEDEC MO-o01 AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 1. Mechanical Information
~TEXAS
INSTRUMENTS
POST OFFICE BOX 656303 • DALLAS, TEXAS 75265
7-5
7-6
4N35,4N36,4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED
1995
COMPATIBLE WITH STANDARD TTL INTEGRATED CIRCUITS
• Gallium-Arsenide-Diode Infrared Source
Optically Coupled to a Silicon npn
Phototranslstor
• High Direct-Current Transfer Ratio
• High-Voltage Electrical Isolation
1.5-kV, 2.5-kV, or 3.55-kV Rating
4N35,4N36, OR 4N37 ••• PACKAGE
(TOP VIEW)
ANODE [ ] 6 BASE
CATHODE 2
5 COLLECTOR
NC 3
4 EMITTER
• Plastic Dual-In-Line Package
NC - No intemal connection
• High-Speed Switching
tr = 7 118, It = 7 118 Typical
• Typical Applications Include Remote Terminal
Isolation, SCR and Triac Triggers, Mechanical
Relays and Pulse Transformers
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)"t*
Input-to-output peak voltage (8-ms half sine wave): 4N35 ................................... 3.55 kV
4N36 .................................... 2.5 kV
4N37 .................................... 1.5 kV
Input-to-output root-mean-square voltage (8-ms half sine wave): 4N35 ......................... 2.5 kV
AN36 ........................ 1.75 kV
4N37 ....................... 1.05 kV
Collector-base voltage ..................................................................... 70 V
Collector-emitter voltage (see Note 1) ....................................................... 30 V
Emitter-base voltage ........................................................................ 7 V
Input-diode reverse voltage ..................................................'.............. " 6 V
Input-diode forward current: Continuous ................................................... 60 mA
Peak (1 118, 300 pps) ............................................ 3 mA
Phototransistor continuous collector current ................................................ 100 rnA
Continuous total power dissipation at (or below) 25°C free-air temperature:
Infrared-emitting diode (see Note 2) '................................................. 100 mW
Phototransistor (see Note 3) ........................................................ 300 mW
Continuous power dissipation at (or below) 25°C lead temperature:
Infrared-emitting diode (see Note 4) ................................................. 100 mW
Phototransistor (see Note 5) ........................................................ 500 mW
Operating temperature range, TA ................................................. -55°C to 100°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seco,nds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the devica. These are stress ratings only, and
functional operation of the deVice at these or any other condHions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
:j: JEDEC registered data. This data sheet contains all applicable registered data In effect at the time of publication.
NOTES: 1. This value applies when the base-emitter diode is open-circulated.
2. Derate linearly to 100°C free-air temperature at the rate of 1.33 mW/oC.
3. Derate linearly to 100°C free-air temperature at the rate of 4 mWPC.
4. Derete linearly to 100°C lead temperature at the rate of 1.33 mWPC. Lead temperature is measured on the collector lead
0.8 mm (1/32 inch) from the case.
5. Derate linearly to 100°C lead temperature at the rate of 6.7 mWPC.
as
P_""""
warrsnIJ. p-...-mg _
PROOUCllON DATA information Is _
01 publication _ .
to apocIIlcdmIs patlhe flnnsolTasu 1nIflu......
llandlrd
not_8BIIIy Include
tosIIng 01 aU parIIIIIIerB.
~TEXAS
Copyrtght © 1995. Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS, TEXAS 75265
7-7
4N35, 4N36, 4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED OCTOBER 1995
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V(BRICBO
Co"ector-base breakdown voltage
IC = 100 ItA, IE=O,
IF=O
70t
V
V(BR)CEO
Co"ector-emitter breakdown voltage
Ic=10mA,
IB=O,
IF=O
30t
V
V(BRIEBO
Emitter-base breakdown voltage
IE = 100 ItA, IC=O,
IF=O
7t
IR
Input diode static reverse current
VR=6V
lOt
ItA
110
Input-to-output current
VIO = rated peak value, t = 8 ms
100
mA
IC(on)
On-state collector current
IC(oll)
Off-state collector current
hFE
Transistor Static Forward Current Transfer Ratio
VCE= 10V, IF=10mA,
IB=O
lOt
VCE=10V, IF= 10mA,
TA=-55°C
IB=O,
4t
VCE=10V, IF= 10mA,
TA= 100°C
IB=O,
4t
VCE=10V, IF=O,
IB=O
VCE=30V, IF=O,
TA= 100°C
IB=O,
VCE=5V,
IF=O
VCE(sat)
Input diode static iorward voltage
Collector-emitter saturation voltage
mA
1
IC= 10mA,
IF= 10mA
VF
V
50
nA
500t
ItA
500
o.at
1.5t
IF=10mA,
TA=-55°C
0.9t
1.7t
IF=10mA,
TA= l000C
0.7t
1.4t
Ic=0.5mA, IF= 10mA,
IB=OmA
riO
Input-to-output intemal resistance
VIO= 500 V,
Cio
Input-to-output capacitance
VIO=O,
See Note 6
See Note 6
0.3t
V
g
1011t
f=l MHz,
V
1·
2.5t
pF
t JEDEC registered data
NOTE 6: These parameters are measured between both input-diode leads shorted together and a" the phototransistor leads shorted together.
switching characteristics at 25°C free-airtemperaturet
PARAMETER
ton
Time-on time
Turn-off time
toff
t JEDEC registered data
TEST CONDITIONS
VCC=10V,
RL = l00!l,
IC(on), = 2 rnA,
See Figure 1
~TEXAS
7-8
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MIN
TYP
MAX
UNIT
10
10
JlS
4N35, 4N36, 4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
47n
Input
,----,"'-i. .~......IIJ'I!Ir- Input
r-t---iJ-- Output
OV~
(see Note B)
~ toft
./
10"10'l
~!
RL=100n
VCC = 10V
~
I4---*- Ion Output
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input wavefonn is supplied by a generator with the following characteristics: Zo = 50 n, tr " 15 ns, duty cycle"'" 1%
tw= 10011s.
B. The output waveform is monitored on an oscilloscope with the following characteristics: t r " 12 ns, Rin '" 1 Mn, Cin " 20 pF
Figure 1. Switching Times
TYPICAL CHARACTERISTICS
OFF-STATE COLLECTOR CURRENT
10,000
C 4,000
VB
VB
FREE-AIR TEMPERATURE
ON-STATE COLLECTOR CURRENT
E VCE= 10V
IB=O
IF=O
c
I
C 1,000
~ 400
:I
/'
./
CJ
~
.!!
"0
CJ
!
~
'L
/
100
40
0.8 , , /
/
./
10
0.6
4
I
j
TRANSISTOR STATIC FORWARD
CURRENT TRANSFER RATIO (NORMALIZED)
0.41-++++HttI-+-+-l-t1ftH1I----t--HI-+I+HI
/
0.4
0.1
/
o
10
20 30 40 50 60 70 80
TA - Free-Air Temperature - °C
90 100
0.21--I--+-l-+ItHt-+-l-+ Normalized to 1 V
atlC=1 mA
O~~~~~~~~lul~IIII~O_~II~I~II~~1i1i1
0.1 0.2 0.4
2
4
10 20 40 100
IC(on) - On-State Collector Current - mA
Figure 2
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
7-9
4N35, 4N36, 4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
COLLECTOR CURRENT
INPUT-DIODE FORWARD
CONDUCTION CHARACTERISTICS
va
MODULATION FREQUENCY
160
10
VCC= 10V
18=0
TA=25°C
4
"'
E
140
RL=1oof.l
2
I
C
~
::I
RL=1 f.l
0.4
"
"-
(,)
j
0.2
;3
0.1
120
C
~
::I
100
,
(,)
'E
E
TA = 70°C
80
.2
60
.!-
40
I
0.04
20
0.02
o
o
0.01
4
10
40
100
400
1000
0.2 0.4 0.6 0.8
COLLECTOR CURRENT
C
4
E
vs
COLLECTOR-EMITTER VOLTAGE
60
VCE=10V
18=0
TA = 25°C
"'
I
1/
C
~
::I
40
j
30
-
0.4
20
C Ipl15m~
(,)
"0
(,)
I
I
"0
E
"
E
0.1
IF=20mA
'r-I
Max Continuous
Power DlsSlpatl~___
' .... ~ '--
.... , ....
I
Ip10mA
~
10
0.04
h==5mA
J
0.01
0.1
I I
\
(,)
1)
.!!
18=0
TA = 25°C
See Note A
~\
E
/
IS
\\
50
'"
(,)
2
COLLECTOR CURRENT
INPUT-DIODE FORWARD CURRENT
I
~::I
1.2 1.4 1.6 1.8
vs
100
"'
1
TA=25°C
·1
I
Figure 5
Figure 4
10
lJ
l& '/
VF - Forward Voltage - V
fmod - Modulation Frequency - kHz
40
J
IJ I
I
RL = 475 f.l
1
~
I
\
I
E
~
I
I
T
TA=25°C
0.4
4
10
40
IF - Input-Diode Forward Current - mA
o
100
I/'
o
2
4
6
8
10
12
14
16
18
20
VCE - Collector-Emitter Voltage - V
NOTE A. Pulse operation of input diode is required for operation
beyond limits shown by dotted lines.
Figure 7
Figure 6
~TEXAS
7-10
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
4N35, 4N36, 4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
ON-8TATE COLLECTOR CURRENT
(RELATIVE TO VALUE AT 25°C)
vs
FREE-AIR TEMPERATURE
1.6
1.4
9
clQ
~ II
1.2
VCE=10V
la=O
IF-10mA
See Note A
~~
i:
==
0-
0.8
u~
'S0.e..
~
c'ji
0.6
V
....
...........
V
~
0.4
0.2
o
-75
-50 -25
0
25
50
75
100
TA - Free-Air Temperature _·C
125
NOTE A. These parameters were measured using pulse
techniques, tw = 1 ms, duty cycle,,; 2 %.
FigureS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
7-11
4N35, 4N36, 4N37
OPTOCOUPLERS
SOES021 - NOVEMBER 1981 - REVISED OCTOBER 1995
MECHANICAL INFORMATION
The package consists of a gallium-arsenide infrared-emitting diode and an npn silicon phototransistor mounted
on a 6-lead frame encapsulated within an electrically nonconductive plastic compound. The case can withstand
soldering temperature with no deformation and device performance characteristics remain stable when
operated in high humidity conditions. Unit weight is approximately 0.52 grams.
14
.1
~::O:0-o)
@®@
9,40 (0.370)
I*i_ _""*i_ 7,82 (0.300) T.P.
5,46 (0.215)
2,92(0.115)
1,78 (0.070)
0,51 (0.020)
(_Note A)
114----.lft- 8,81 (0.280)
8,09 (0.240)
(D@@
(_Note C)
~
J+-
1,78 (0.070) MAX
~t~1
(_Note B)
Seating Plane - - r - -
-lJ--.II..1
~
2,29 (0.090)
3,81 (0.150) 1,27(0.050)
3,17(0.125) 4Places
2,54 (0.100) T.P.
(_NoteA)
8 Places
1,01 (0.040) MIN
G,534 (0.021)
0,381 (0.015)
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) with maximum material condition and unit installed.
B. Pin 1 identified by index dot.
C. Terminal connections:
1. Anode (part of the infrared-emitting diode)
2. Cathode (part of the infrared-emitting diode)
3. No intemal connection
4. Emitter (part of the phototransistor)
5. Collector (part of the phototransistor)
6. Base (part of the phototransistor)
D. The dimensions given fall within JEDEC MO-o01 AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 9. Mechanical Information
~TEXAS
7-12
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
6 Places
6N135, 6N136, HCPL4502
OPTOCOUPLERSIOPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
• Compatible with TTL Inputs
6N135, 6N136, OR HCPL4502 PACKAGE
(TOP VIEW)
Ncue
• High-Speed Switching ...• 1 Mbitls Typ
• Bandwidth ••• 2 MHz Typ
• High Common-Mode Transient
Immunity ••.• 1000 V/IJ.S "iYP
ANODE
CATHODE
NC
• High-Voltage Electrical
Insulation ••• 3000 VDC Min
2
3
4
7
6
5
Vcc
BASE/OPENt
OUTPUT
GND
tTenninal 7 is BASE on the 6N135 and
6N136 and OPEN on the HCPL4502
• Open-Collector Output
• UL Recognized. .• File Number 65085
NC - No intemal connection
description
These high-speed optocouplers are designed for use in analog or digital interface applications that require
high-voltage isolation between the input and output. Applications include line receivers that require high
common-mode transient immunity, and analog or logic circuits that require input-to-output electrical isolation.
The 6N135, 6N136, and HCPL4502 optocouplers each consists of a light-emitting diode and an integrated
photon detector composed of a photodiode and an open-collector output transistor. Separate connections are
provided for the photodiode bias and the transistor-collector output. This feature, which reduces the transistor
base-to-collector capacitance, results in speeds up to one hundred times that of a conventional phototransistor
optocoupler.
The 6N135 is designed for TTUCMOS, TTULSTTL, and wide-band analog applications.
The 6N136 and HCPL4502 are designed for high-speed TTUTTL applications. The HCPL4502 has no base
connecti!)n.
schematic
8
ANODE ] 2
CAllIODE 3
=:
VCC
1 -- - -
7
BASE: 6N135, 6N136
OPEN: HCPL4502
I
I
6
OUTPUT
GND
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-13
6N135, 6N136, HCPL4502
OPTOCOUPLERSJOPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)1'*
Supply and output voltage range, Vee and Vo ..................................••.... -0.5 V to 15 V
Reverse input voltage' .........................................................•............. 5 V
Emitter-base reverse voltage. ................................................................. 5 V
Peak input forward current (pulse duration = 1 ms, 50% duty cycle, see Note 1) .................. 50 mA
Peak transient input forward current (pulse duration 1 J.lS, 300 Hz) ................................. 1 A
Average forward input current(see Note 2) .................................................. 25 mA
Peak output current ..............................•. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 16 mA
Average output current .................................................................... 8 mA
Base current ..................................................' . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 mA
Input power dissipation at (or below) 700 free-air temperature (see Note 3) .................... 45 mW
Output power dissipation at (or below) 700 free-air temperature (see Note 4) ................. 100 mW
Storage temperature range, Tstg .................................................. -55°e to 125°e
Operating free-air temperature range', TA .......................................... -55°e to 1000 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260,oe
e
\
e
t Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated condHlons for extended periods may affect device reliabllHy.
:l:JEDEC registered data for 6N135 and 6N136
NOTES: 1. Derate linearly above 70·C free-air temperature at the rate of 1.67 mArC.
2. Derate linearly above 70·C free-air temperature at the rate of 0.83 mA/"C.
3. Derate linearly above 70·C free-air temperature at the rate of 1.50 mW/·C.
4. Derate linearly above 70ac free-air temperature at the rate of 3.33 mWrC.
~1ExAs
7-14
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265 i
6N135,6N136,HCPL4502
OPTOCOUPLERS/OPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
electrical characteristics over operating free-air temperature range of O°C to 70°C (unless
otherwise noted)
TEST CONDITIONS
PARAMETER
6N135
MIN
MAX
1.S
1.7
VF*
Input forward voltage
IF= lSmA,
~VF
Temperature coefficient of
forward voltage
IF=ISmA
V8R*
Input breakdown voltage
IR = 10 ItA,
TA=25°e
10l=1.lmA
lOW-level output voHage
Vee=4.5V,
IF=lSmA,
18=0
IF=O,
18=0,
TA=25°C
Vee =Vo= 5.5 V
3
VCC=VO= 15V
0.01
VOL
6N136, HCPL4502
TYpt
TA=25°e
MIN
TYpt
MAX
1.S
1.7
-1.8
-1.8
UNIT
V
mVre
V
5
5
0.1
0.4
V
0.1
0.4
500
3
500
nA
1
0.01
1
ItA
50
ItA
1
ItA
2
ItA
IOl=2.4mA
10H*
High-level output current
10H
High-level output current
VCC=15V,
IF=O,
VO= 15V,
18=0
ICCH*
Supply current, high-level
output
VCC=15V,
IF=O,
TA = 25°C
10=0,
18=0,
ICCH
Supply current, high-level
output
Vee = 15V,
IF=O,
10=0,
18=0
ICCl
Supply current, low-level
output
Vce=15V,
IF=lSmA,
10=0,
18=0
50
0.02
0.02
1
2
40
40
100
100
(SN13S
only)
ItA
hFE
Transistor forward current
transfer ratio
VO=5V,
10=3mA
CTR*
Current transfer ratio
Vec=4.5V,
IF= lSmA,
TA=25°C,
VO=0.4V,
18=0,
See Note 5
CTR
Current transfer ratio
VCC=4.5V,
IF=lSmA,
See NoteS
Vo =0.5 V,
18=0,
110
Input-output resistance
VIO=500V,
See NoteS
TA = 25°C,
110*
Input-output insulation
leakage current
VI0=3000V,
TA = 25°C,
See NoteS
t=5 s,
RH=45%,
ei
Input capacitance
VF=O,
f=l MHz
SO
SO
pF
Cio
Input-output capacitance
f= 1 MHz,
See NoteS
O.S
O.S
pF
7%
18%
19%
24%
15%
5%
1012
1012
Q
1
1
ItA
t All typical values are at TA = 25°C.
* JEDEC registered data for SN135 and SNl36
NOTES: 5. Currenttransfer ratio is defined as the ratio of output collector current 10 to the forward lED input current IF times 100%.
S. These parameters are measured with terminals 2 and 3 shorted together and terminals 5, S, 7, and 8 shorted together.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-15
6N13S, 6N136, HCPL4s02
OPTOCOUPLERS/OPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
operating characteristics, Vee = 5 V, IF = 16 mA, TA = 25°C (unless otherwise noted)
PARAMETER
BW
Bandwidth (-3 dB)
TEST CONDITIONS
RL= 1000,
6N135
MIN
See Note 7
6Nl36, HCPL4502
TYP
MAX
MIN
TYP
2
MAX
2
UNIT
MHz
NOTE 7: Bandwidth is the range of frequenCies within whICh the ac output voltage IS not more than 3 dB below the low-frequency value.
switching characteristics at Vee = 5 V, IF = 16 mA, TA = 25°C
PARAMETER
tpLHt
tPHLt
dV
~(H)
dt
dV
~(L)
dt
TEST CONDITIONS
Propagation
delay time,
low-to-high-Ievel
output
RL=4.1 kn,
See Figure 1
See NoteS,
RL= 1.9kn,
See Figure 1
See Note 9,
Propagation
delay time,
high-to-Iow-Ievel
output
RL = 4.1 kn,
See Figure 1
See NoteS,
RL = 1.9 kn,
See Figure 1
See Note 9,
AVCM= 10V,
RL=4.1 kn,
See Figure 2
IF=O,
See Notes Sand 10,
AVCM= 10V,
RL= 1.9kn,
See Figure 2
IF=O,
See Notes 9 and 10,
AVCM= 10V,
See Notes 9 and 10,
RL=4.1 kn,
See Figure 2
AVCM= 10V,
See Notes 9 and 10,
RL = 1.9 kQ,
See Figure 2
Common-mode
input transient
immunity,
high-level output
Common-mode
input transient
immunity,
lOW-level output
6N135
MIN
6N136, HCPL4502
TYP
MAX
1
1.5
MIN
TYP
MAX
0.6
0.8
0.6
O.S
UNIT
IlS
0.7
1.5
IlS
1000
V/IlS
-1000
-1000
VlIlS
-1000
t JEDEC registered data for 6N135 and 6N136
NOTES: 8. The 4.1-kQ load represents one LSTTL unit load of 0.36 rnA and a 6.1-kn pull up resistor.
9. The 1.9-kn load represents one TTL unit load of 1.6 rnA and a 5.6-kn pullup resistor.
10. Common-mode transient immunity, high-level output, is the maximum rate of ril;e of the common-mode input voltage that does not
cause the output voltage to drop below 2 V. Common-mode input transient immunity, lOW-level output, is the maximum rate of fall
of the common-mode input voltage that does not cause the output voltage to rise above O.S V.
~TEXAS
7-16
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6N135, 6N136, HCPL4502
OPTOCOUPLERS/OPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
r---------,
.--------r----~-5V
Pulse
Generator
ZO=500
tr 5 ns
=
Output
Input Current ____~+-'
Monitor
1000
CL=15pF
(see Note A)
L---------....----*--------4t- GND
TEST CIRCUIT
Input
Current
IF
~
~--OV
I
Output
Voltage
I
I
I
5V
'-------~~:I
tpHL~
VOL
j+- tPLH
WAVEFORMS
NOTE A. CL includes probe and stray capacitance.
Figure 1. Switching Test Circuit and Waveforms
~TEXAS
INSTRUMENTS
POST OFFICE aox 655303 • DALLAS, TEXAS 75265
7-17
6N135, 6N136, HCPL4502
OPTOCOUPLERS/OPTOISOLATORS .
SOES022 - JULY 1986 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
~
1"'---------,
I
I
I
I
I
I
I
5V
-.
-.
RL
Output
-------
L.
Open
.J
GND
-=TEST CIRCUIT
dVCM
Generator
10:O:f19O%
~
Output
I+-tr
90%
h-10%
-.I 14- tf
0
Switch at B: IF =
16
Output
~VOL
mA
VOLTAGE WAVEFORMS
Figure 2. Transient Immunity Test Circuit and Waveforms
~TEXAS
7-18
INSTRUMENTS
POST OFFICE BOX 6S5303 • DALLAS, TEXAS 75265
8V
=-tr or tf
t r =8nsTYP
OV 1f=8nsTYP
5V
~
Switch at A: IF =
Cit
6N135, 6N136, HCPL4502
OPTOCOUPLERS/OPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
INPUT-DIODE FORWARD CURRENT
vs
6N135
FORWARD VOLTAGE
CURRENT TRANSFER CHARACTERISTICS
20
CC
E
I
18
16
C
~
14
1!
12
:..
10
1E;
6
.5
4
::I
(.)
~
~
8
c.
I
..!!-
12
I
I
I
II
I
2
/
CC
E
I
I
/
I--- -
8
/ r
7
(.)
6
'$
5 ~-
t
0
J
~
IF=25mA
4
IF = 20mA
3
IF=15mA
2
IF = 10mA
1.4
1.5
1.6
VF - Forward Voltage - V
o
1.7
IF=5mA
o
2
4
6
8
10
12
Vo - Output Voltage - V
vs
FREE-AIR TEMPERATURE
!0
~
.2
1i
II:
0.5
fi
0.3
I
0.2
(.)
II:
t
I
I:f'
--
I
.....
i
i
II:
W
b
lQ'
0.4
/
0.8
I
C
~
::I
VCC=5V
VO=0.4V
TA = 25°C
Normalized to IF = 16 mA
0.1
o
1
0.9
I:
~
(.)
I
--
VCC=5V
VO=0.4V
IF=16mA
0
~
/. '/6N135
0.7
~
I
h'
0.8
0.6
C
6N~36
HCPL4502
0.9
i
I:
1.1
_
1
16
CURRENT TRANSFER RATIO (NORMALIZED)
1.2
1i
14
Figure 4
CURRENT TRANSFER RATIO (NORMALIZED)
VB
INPUT DIODE FORWARD CURRENT
i
IF=4OmA
IF=35mA IF=30mA -
....
- ...1L ~-(- '-:-r--r
f--:J: ::c
--
Figure 3
1.1
-
I
.9
1.3
1.2
9
C
~
::I
./
0
1.1
VCC=5V
TA = 25°C
11
10
/
~
V ,./"
//
V
-
6N135
I- 6N136.
HCPL4502
r".
~i'..'-,
""- ......
~
I
0.7
~
0.6
2
4
7
10
20
40 70 100
~~
IF - Input Dlocle Forward Current - mA
FigureS
~
0
~
40
~
~
100
TA - Free-Air Temperature - °C
Figure 6
~1EXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-19
6N135, 6N136, HCPL4502
OPTOCOUPLERS/OPTOISOLATORS
SOES022-JULYl986'-REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
DIFFERENTIAL CURRENT TRANSFER RATIO
HIGH-LEVEL OUTPUT CURRENT
vs
vs
FREE-AIR TEMPERATURE
INPUT-DIODE QUIESCENT FORWARD CURRENT
10,000
4000
cC
c
I
1000
C
~
:::I
400
!I
100
CJ
t
0
l
.S!'
30
VCC=5V
VO=5V
IF=O
I
I
40
15~~---r------r------+~~~
/
10
10~----~------~-----+--~--1
4
:t:
/
I
:t:
.9
25
5~----~------~-----+------1
0.4
0.1
-75
,./
-50 -25
0
25
50
75
100
TA - Free-Air Temperature - °c
O~----~------~----~----~
o
125
10
15
20
5
IF -Input-Diode Quiesclint Forward Current - mA
Figure 7
FigureS
FREQUENCY RESPONSE (NORMALIZED)
0
i
~
0
......
-5
8.
FREE-AIR TEMPERATURE
1.2
r---" i' ~ ~
"
~
IIc
vs
FREQUENCY
RL=4700
RL = 1 kO -.-/
-15
:I
a:
(;'
c
!II
::L
~ i\.
1\
-20
E
iii
c
t
e
II.
!..
:t:
-25
-,:5
0.2
II.
(
0.4
0.7 1
2
f - Frequency - MHz
4
7 10
/
6N135tPHY
0.7
- ---....-
.........
0.6 ~6N136tPHL
HCPL4502""'-:::===
0.5
0.4
",
/'1
~~
~r
0
V
/
....
~TEXAS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
-
6N136tPLH
HCPL4502
~
0
~
Figure 10
INSTRUMENTS
/
V
./
~
~
TA - Free-Air Temperature - °c
Figure 9
7-20
6N135tpLH -
./
,
Ii
~
II.
-30
0.1
0.8
./
......
zV
io"'"
V
0.9
c
i\
IF=16mA
TA = 25°C
VCC=5V
IF= 16 mA
RL = 4.1 kO for 6N135
RL = 1.9 kO for6N136
1.1
1=
i;'
1\
GI
:::I
1
I
GI
~ ~ ~~
RL:1000 ::/:
1\
RL=2200 . . /
-10
PROPAGATION DELAY TIME
vs
~
100
6N135, 6N136, HCPL4502
OPTOCOUPLERSIOPTOISOLATORS
SOES022 - JULY 1986 - REVISED OCTOBER 1995
MECHANICAL INFORMATION
r;
Index Dot
9,91 (0.390) ~
9,49 (0.370)
® ®
® ®
CD ®
®
o
@)
0,89 (0.035) MIN
1,78 (0,070)
1,14 (0.045)
f
~
~
90°
8 Places
Seating Plane ---+---'i'=-F'"
Gauge Plane
0,76 (0.030)
J [ ' O O (0.000)
3,17 (0.125) MIN
0, 457 ± 0,076
(0.018 ± 0.003)
8 Places
0,33 (0.013)
0,18 (0.007)
NOTES: A. JEDEC registered data. This data sheet contains all applicable registered data in effect at the time 01 publication.
B. Tem1inal connections:
1. No internal connection (part 01 the light-emitting diode)
2. Anode (part 01 the light-emitting diode)
3. Cathode (part 01 the light-emitting diode)
4. No internal connection
5. GND (Emitter) (part 01 the light-emitting diode)
6. Output (part 01 the detector)
7. Base: 6Nl35, 6N136 (part 01 the detector)
Open: HCPL4502 (part 01 the detector)
8. VCC (part 01 the detector)
C. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 11. Mechanical Information
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OAlLAS. TEXAS 75265
7-21
7-22
MCT2,MCT2E
OPTOCOUPLERS
1995
COMPATIBLE WITH STANDARD TTL INTEGRATED CIRCUITS
MCT2 OR MCT2E ••• PACKAGE
• Gallium Arsenide Diode Infrared Source Optically
Coupled to a Silicon npn Phototranslstor
• High Direct-Current Transfer Ratio
• Base Lead Provided for Conventional Transistor
Blasing
• High-Voltage Electrical Isolation . .• 1.5-kV, or
3.55-kV Rating
• Plastic Dual-In-Line Package
• High-Speed Switching:
tr 5 IJ.S, If 5 IJ.S Typical
• Designed to be Interchangeable with
General Instruments MCT2 and MCT2E
=
(TOP VIEW)
ANODE [ ] 6 BASE
CATHODE 2
5 COLLECTOR
NC 3
4 EMITTER
NC - No intemal connection
=
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)t
Input-to-output voltage: MCT2 ........................................................... ± 1.5 kV
MCT2E ........................................................ ± 3.55 kV
Collector-base voltage ..................................................................... 70 V
Collector-emitter voltage (see Note 1) ....................................................... 30 V
Emitter-collector voltage ..................................................................... 7 V
Emitter-base voltage ........................................................................ 7 V
Input-diode reverse voltage .......... :....................................................... 3 V
Input-diode continuous forward current ..................................................... 60 rnA
Input-diode peak forward current(tw ~ 1 ns, PRF ~ 300 Hz) ...................................... 3 A
Continuous power dissipation at (or below) 25°C free-air temperature:
Infrared-emitting diode (see Note 2) ................................................. 200 mW
Phototransistor (see Note 2) ........................................................ 200 mW
Total, infrared-emitting diode plus phototransistor (see Note 3) .......................... 250 mW
Operating free-air temperature range, TA .......................................... -55°C to 100°C
Storage temperature range, Tstg .................................................. -55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are strass ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "racommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value applies when the base-emitter diode is open-circulated.
2. Derate linearly to 100°C free-air temperature at the rate of 2.67 mW/oC.
3. Derate linearly to 100°C free-air temperature at the rate of 3.33 mWrC.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
.
INSTRUMENTS
POST OFFICE eox 655303 • DAUAS. TEXAS 75265
71-23
MCT2, MCT2E
OPTOCOUPLERS
SOES023 - MARCH 1983 - REVISED OCTOBER 1995
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
MIN
TYP
MAX
UNIT
V(BR)CBO
Collector-base breakdown voltage
IC = 10 jJA,
IE=O,
IF=O
70
V
VCBRICEO
Collector-emitter breakdown voltage
IC=1 rnA,
IB=O,
IF=O
30
V
V(BRECO)
Emitter-collector breakdown voltage
IE = 100 jJA, IB=O,
IF=O
7
IR
Input diode stalic reverse currenl
VR=3V
IC(on)
On-state collector current
IC(off)
HFE
Off-state collector current
Phololransislor
operalion
VCE= 10V, IB=O,
IF=10mA
Photodiode operation
VCB= 10V, IE=O,
IF=10mA
Phototransistor
operation
VCE=10V, IB=O,
IF=O
Photodiode operation
VCB=10V, IE=O,
IF=O
Transistor static forward current transfer ratio
V
10
VCE=5V,
IC = 100 jJA,
IF=O
2
VF
Input diode static forward voltage
IF=20mA
VCE(sat)
Collector-emitter saturation voltage
Ic=2mA,
rJO
Input-to-output internal resistance
Vin-out = ±1.5 kV for MCT2,
±3.55 kV for MCT2E,
See Note 4
Cio
Inpul-Io-output capacitance
Vin-out=O,
See Note 4
IB=O,
5
mA
20
jJA
1
50
nA
0.1
20
nA
1.25
1.5
V
0.25
4
V
250
MCT2.
MCT2E
jJA
100
IF=16rnA
300
n
1011
f=1 MHz,
1
pF
NOTE 4: These parameters are measured between both input diode leads shorted together and all the phototransistor leads shorted together.
switching characteristics
PARAMETER
tr
Risetirne
tf
Fall time
tr
Rise time
If
Fall time
TEST CONDITIONS
TYP
MAX
UNIT
Phototransistor operation
5
IJ.S
Photodiode operation
VCC = 10 V, IC(on) 20 jJA,
RL=1 kO, See Test Circuit B of Figure 1
1
IJ.S
-!!1TEXAS
INSTRUMENTS
7-24
MIN
VCC=10V,IC(on)=2mA,
RL = 100 n, See Test Circuit A of Figure 1
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
MCT2,MCT2E
OPTOCOUPlERS
SOES023 - MARCH 1983 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
470
Inpm
r-1r---4~- Ompm
(see Note B)
VCC=10V
470
Inpm
r-~~~~~~--
RL=I00a
TEST CIRCUIT A
PHOTOTRANSISTOR OPERATION
ov ..J
-+i I+- tr
L
Outpm
--.t 14- tf
!~!
jtlO%
.-----r--._--->o,,.-I\i'V\r- Input
10%'l
VOLTAGE WAVEFORMS
'---__-.1-+
-=- VCC= 10V
Output
(see Note B)
RL=1 kO
TEST CIRCUIT B
PHOTODIODE OPERATION
NOTES: .A. The input waveform is supplied by a generator with the following characteristics: Zo = 50 a, tr :s; 15 ns, duty cycle "" 1%,
Iw = 100/18.
B. The output waveform is monitored on an oscilloscope with the following characteristics: tr :s; 12 ns, Ain ~ 1 Ma, Cin :s; 20 pF.
Figure 1. Switching Times
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-25
MCT2,MCT2E
OPTOCOUPLERS
SOES023- MARCH 1983 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
COLLECTOR CURRENT
COLLECTOR CURRENT
va
va
INPUT-DIODE FORWARD CURRENT
COLLECTOR-EMmER VOLTAGE
100
40
1
10
'E
~
4
60
VCE= 10V
IB=O
TA .. 25°C
50
V
I
'E
~
a
0.4
/
I
9
\
40
\
u
J
8
I
0.01
0.1
20
10
0.04
/
o
0.4
10
4
40
IF -Input-Diode Forward Current - mA
Max Continuous
~. Power Dissipation
30
9
0.1
IB=O
TA=25°C
See Note A
1\
1
I
J
8
~
100
"\
I
IF=4OmA
~ :.--
IF=30mA
~
~IF=20mA
rr
o
2
4
6
va
1.6
1.2
VCE = 0.4 Vto 10 V
IB=O
IF=10mA
See Note A
a~
I:
~i
i~
eli
°l
0.8
0.6
V
-...... ..........
V
0.4
0.2
o
-75
-50
-25
0
25
,50
75
100
125
TA - Free-Air Temperature - °C
NOTE A. These parameters were measurad using pulse
techniques, Iw = 1 ms, duty cycle s 2 %.
Figure 4
~lExAs
7-26
8
10
Figure 3
FREE·AIR TEMPERATURE
p-
-.... 'o-
12
14
16
18
20
VCE - Coliector·Emltter Voltage - V
NOTE A. Pulse operation of input diode is requirad for operation
beyond limits shown by dotted lines.
ON-8TATE COLLECTOR CURRENT
(RELATIVE TO VALUE AT 25°C)
'E ...
~~
f--
IF=20mA
Figure 2
1.4
-- .--- --....-
INSTRUMENTS
POST OFFICE BOX 655303 • OAU.AS. TEXAS 75265
MCT2, MCT2E
OPTOCOUPLERS
SOES023 - MARCH 1983 - REVISED OCTOBER 1995
MECHANICAL INFORMATION
The package consists of a gallium-arsenide infrared-emitting diode and an npn silicDn phototransistor mounted
on a 6-lead frame encapsulated within an electrically nonconductive plastic compound. The case can withstand
soldering temperature with no deformation and device performance characteristics remain stable when
operated in high-humidity conditions. Unit weight is approximately 0.52 grams.
9,40 (0.370)
8,38 (0.330)
14 ® ® @.1
IndexDotO
i
i
i4----I0f- 7,62 (0.300) T.P.
14----.,+_ 6,61 (0.260)
6,09 (0.240)
(see Note B)
CD®@
(see Note C)
1J--.II.-
0,534 (0.021)
0,381 (0.015)
f
\\
~\+-
14- 1,78 (0.070) MAX
6 Places
Seating Plane .....
0,305 (0.012)
~
~tmtl
90'
0,203 (0.008)
5,46 (0.215)
2,92 (0.115)
1,78 (0.070)
0,51 (0.020)
3,81 (0.150)
3,17 (0.125)
_11-
-1 I- 1,01 (0.040) MIN
2,29 (0.090)
1,27(0.050)
2,54 (0.100) T.P.
6 Places
(see Note A)
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) with maximum material condition and unit installed.
B. Pin 1 identified by index dot.
C. Terminal connections:
1. Anode (part of the infrared-emitting diode)
2. Cathode (part of the infrared-emitting diode)
3. No internal connection
4. Emitter (part of the phototransistor)
5. Collector (part of the phototransistor)
6. Base (part of the phototransistor)
D. The dimensions given fall within JEDEC MO-o01 AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 5. Mechanical Information
-!!1TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-27
7-28
MOC3009 THRU MOC3012
OPTOCOUPLERSIOPTOISOLATORS
MOC30209-MOC3012 •.. PACKAGE
(TOP VIEW)
• 250 V Phototriac Driver Output
• Gallium-Arsenide-Dlode Infrared Source and
Optically Coupled Silicon Traic Driver
(Bilateral Switch)
ANODE
CATHODE
NC
• UL Recognized .•• File Number E65085
• High Isolation '"
01
2
3
6
5
4
MAIN TERM
TRIAC suet
MAIN TERM
7500 V Peak
• Output Driver Designed for 115 V ac
t Do not connect this terminal
• Standard 6-Terminal Plastic DIP
NC - No internal connection
• Directly Interchangeable with Motorola
MOC3009, MOC3010, MOC3011, and MOC3012
logic diagram
• Direct Replacements for:
TRW Optron OPI3009, OP13010, OP13011,
and OPI3012j
General Instrument MCP3009, MCP3010,
MCP3011j
General Electric GE3009, GE3010,
GE3011, and GE3012
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)t
Input-to-output peak voltage,S s maximum duration, 60 Hz (see Note 1) ........................ 7.5 kV
Input diode reverse voltage .................................................................. 3 V
Input diode forward current, continuous ..................................................... 50 mA
Output repetitive peak off-state voltage ..................................................... 250 V
Output on-state current, total rms value (50-60 Hz, full sine wave):TA 25°C ..................• 100,mA
TA 70°C .................... 50 mA
Output driver nonrepetitive peak on-state current (tw 10 ms, duty cycle 10%, see Figure 7) ..... 1.2 A
Continuous power dissipation at (or below) 25°C free-air temperature:
Infrared-emitting diode (see Note 2) ....................• . . . . . . . . . . . . . . . . . . . . . . . . . . .. 100 mW
Phototriac (see Note 3) ............................................................ 300 mW
Total device (see Note 4) ........................................................... 330 mW
Operating junction temperature range, TJ .......................................... -40°C to 100°C
Storage temperature range, Tstg .................................................. -40°C to 150°C
Lead temperature 1,6 (1/16 inch) from case for 10 seconds ................................... 260°C
=
=
=
=
t
Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Input-to-output peak voltage is the intemal device dielectric breakdown rating.
2. Derate linearly to 100°C free-air temperature at the rate of 1.33 mW/oC.
3. Derate linearly to 100°C free-air temperature at the rate of 4 mW/oC.
4. Derate linearly to 100°C free-air temperature at the rate of 4.4 mW/oC.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-29
MOC3009 THRU MOC3012
OPTOCOUPLERS/OPTOISOLATORS
SOES024 -AUGUST 1985 - REVISED OCTOBER 1995
electrical characteristics at 25°C free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IR
Static reverse current
VR=3V
VF
Static forward voltage
IF=10mA
IORM
Repetitive off-state current. either direction
VORM = 250 V,
dv/dl
Critical rate of rise of off-state voltage
See Figure 1
dv/dt(c)
Critical rate of rise of commutating voltage
10= 15 mAo
See Note 5
MOC301 0
Input trigger current.
either direction
VTM
Peak on-state voltage. either direction
Output supply voltage = 3 V
MOC3011
TVP
MAX
0.05
100
1.2
1.5
V
10
100
nA
12
See Figure 1
MOC3009
1FT
MIN
!IA
V/IJB
0.15
V/IJB
15
30
8
15
5
10
MOC3012
UNIT
mA
5
ITM= l00mA
Holding current. either direction
IH
NOTE 5: Test voltage must be applied within dv/dt rating.
1.8
100
3
V
!IA
PARAMETER MEASUREMENT INFORMATION
Vcc
VI=30Vrms
2
Input
(see Note A)
10kO
NOTE A. The critical rate of rise of off-state voltage.dv/dl. is measured with the input at 0 V. The fraquency of Yin is increased until the
phototriac just tums on. This frequency is then used to calculate the dv/dl according to the formula:
dv/dt = 2 ./27tfV in
The critical rate of rise of commutating voltage. dv/dt(c). is measured by applying occasional5-V pulses to the input and increasing
the frequency of Yin until the phototriac stays on (latches) after the input pulse has ceased. With no further input pulses. the
frequency ofVin is then gradually decreased until the phototriac tumsoff. The frequency at which tum-off occurs may then be used
to calculate the dv/dt(c) according to the formula shown above.
Figure 1. Critical Rate of Rise Test Circuit
~TEXAS
7-30
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
MOC3009 THRU MOC3012
OPTOCOUPLERSJOPTOISOLATORS
SooSOOl -AUGUST 1985
TYPICAL CHARACTERISTICS
EMIITING-DIODE TRIGGER CURRENT (NORMALIZED)
vs
ON-STATE CHARACTERISTICS
FREE-AIR TEMPERATURE
1.4
i
800
iii
1.3
'E"
S
~
400
I
1.2
~
:::I
~ 1.1
i
C
~
~
200
!i
0
CI,I
c
0
-200
~
t!
:::I
....
:.
I
~
iii 0.9
0.8
-50
-600
L
-800
o
-25
-400
25
75
50
100
-3
/
V
V
/
-2
-1
/
J
o
V
2
3
VTM - Peak On-8tate Voltage - V
TA Free-Air Temperature - °C
Figure 2
Figure 3
CRITICAL RATE OF RISE OF OUTPUT VOLTAGE
CRITICAL RATE OF RISE OF OUTPUT VOLTAGE
OFF-8TATE dv/dt AND COMMUTATING dv/dt(c)
OFF-STATE dv/dt AND COMMUTATING dv/dt(c)
14
vs
vs
LOAD RESISTANCE
FREE-AIR TEMPERATURE
12 ......- - - - - , , . . . . . . - - - - - . - - - - - - , 0.24
- - t - dv/dt
-- dv/dt(c)
I--~---If-----j-----l 0.2
0.24
!
J
TA=25°C
See Figure 1
Off-State
12
0.20
01
<>'
01
:::I.
~
I
I 10
~
.!!
~
I
(J
II
"
is
i
/
Output tw = 80 J.IS
IF=20mA
f=60Hz
TA=25°C
600
---
Commutati~..
8
~
....
....... ....
1-----
0.16
i
~
CII
c
0.12
~
E
E
8
0.08
/'
6
1/1
~
01
:::I.
~ 8 1 - - - - - - " I , . . . . - 1 f - - - - - - - f - - - - - t 0.16.!..
.2-
I
i>'
'1:1
i>'
6 I------'='____-If-----""oc----f-----t 0.12 :
c
4
5
4
I---~_i=--+----"~~..,_---I
~
0.08 E
RL=5100
~
2 I------If----==----j-----'=! 0.04
- - dv/dt
- - - dv/dt(c)
4
I
o
0.4
0.8
1.2
0.04
1.6
2
0'--------''-------'------'0
~
50
~
100
TA - Free-Air Temperature - °C
RL - Load Resistance - kQ
Figure 4
FigureS
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DAlLAS, TEXAS 75265
7-31
MOC3009 THRU MOC3012
OPTOCOUPLERS/OPTOISOLATORS
SOES024 -AUGUST 1985 - REVISED OCTOBER 1995
TYPICAL· CHARACTERISTICS
RMS APPLIED VOLTAGE
(FOR dv/dt(c) = 0.15 V/1lS)
VB
FREQUENCY
NON REPETITIVE PEAK ON-STATE CURRENT
VB
PULSE DURATION
1000
3
RL=1 kn
TA=25°C
dv/dt = 2 -.12m VI
400
>
I
J
100
i
'a.
40
~
"
2
II:
...
........
~I--
~
r-- "'1'-
,dV/dt = 0.15 VlIJS
III
:E
Tl~~o~1
10
I
;>
4
r'\.
1
100
400
1k
4k
10 k
f - Frequency - Hz
o
40k 100k
0.01
tw - Pulse Duration - ms
Figure 6
Figure 7
~TEXAS
7-32
10
0.1
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
100
MOC3009 THRU MOC3012
OPTOCOUPLERSIOPTOISOLATORS
SOOSool - AUGUST 1985
APPLICATIONS INFORMATION
MOC3009, MOC3012
RL
6
1800
VCC --'VVv--.!.-f-...,
---+
---+
220V,60Hz
2
Figure 8. Resistive Load
MOC3009, MOC3012
6
1800
VCC --'VVv---'-t---,
---+
---+
0.1 j.lF
220 V, 60 Hz
4
2
IGT",15mA
Figure 9. Inductive Load With Sensitive-Gate Triac
MOC3009, MOC3012
Rin
6
1800
VCC ---'VVv--"'-J--.
---+
---+
2
0.2j.lF
220 v, 60 Hz
4
15mAi
j4-
II
--+II+-
• "'-
0,534(0.021)
0,381 (0.015)
6 Places
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) with maximum material condition and unit installed.
B. Pin 1 identified by index dot.
C. Terminal connections:
1. Anode (part of the infrared-emitting diode)
2. Cathode (part of the infrared-emitting diode)
3. No internal connection
4. Main terminal (part of the phototransistor)
5. Triac Substrate (DO NOT connect) (part of the phototransistor)
6. Main tenninal (part of the phototransistor)
D. The dimensions given fall within JEDEC MO-OOl AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 8. Mechanical Information
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
7-39
7-40
TIL191, TIL192, TIL193, TIL191A, TIL192A, TIL193A
TIL191B, TIL192B, TIL193B
OPTOCOUPLERS
SOES026 - APRIL 1989 - REVISED OCTOBER 1995
• Gallium-Arsenide-Diode Infrared Source
• Source Is Optically Coupled to Silicon npn
Phototransistor
• Choice of One, Two, or Four Channels
• Choice of Three Current-Transfer Ratios
• High-Voltage Electrical Isolation 3.535 kV
Peak (2.5 kV rms)
• Plastic Dual-In-Line Packages
• UL Listed - File #E65085
description
These optocouplers consist of a gallium-arsenide light-emitting diode and a silicon npn phototransistor per
channel. The TIL 191 has a channel in a 4-terminal package, the TIL 192 has two channels in an 8-terminal
package, and the TIL 193 has four channels in a 16-terminal package. The standard devices, TIL 191, TIL 192,
and TIL 193, are tested for a current-transfer ratio of 20% minimum. Devices selected for a current-transfer ratio
of 50% and 100% minimum are designated with the suffix A and B respectively.
schematic diagrams
g
TIL193
TIL191
ANODE
CATHODE
2
--+
1ANODE 1
3
EMITTER
1CATHODE
-2ANODE
2CATHODE
2
3
4
1CATHODE
2ANODE
TIL192,
1ANODE 1
16
COLLECTOR
2CATHODE
8
7
6
5
1COLLECTOR
3ANODE
1EMITTER
3CATHODE
2COLLECTOR
2EMITTER
1EMITTER
2
3
2COLLECTOR
4
2EMITTER
5
3COLLECTOR
3EMITTER
6
7
3COLLECTOR
4ANODE
4CATHODE
1COLLECTOR
9
8
3EMITTER
absolute maximum ratings at 25°C free-air (unless otherwise noted)t
Input-to-output voltage (see Note 1) .............................. ±3.535 kV peak or dc (±2.5 kV rms)
Collector-emitter voltage (see Note 2) ....................................................... 35 V
Emitter-collector voltage ..................................................................... 7 V
Input diode reverse voltage .................................................................. 5 V
Input diode continuous forward current at (or below) 25°C free-air temperature
(see Note 3) ................... ;...................................................... 50 mA
Continuous total power dissipation at (or below) 25°C free-air temperature:
Phototransistor (see Note 4) .......................................................... 150 mW
Input diode plus phototransistor per channel (see Note 5) ................................. 200 mW
Storage temperature range, Tstg .................................................. -55°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions· is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This rating applies for sine-wave operation at SO Hz or60 Hz. This capability is verified by testing in accordance with UL requirements.
2. This value applies when the base-emitter diode is open circuited.
3. Derate linearly to 100°C free-air temperature at the rate of 0.67 mArC.
4. Derate linearly to 100°C free-air temperature at the rate of 2 mW/oC.
S. Derate linearly to 100°C free-air temperature at the rate of 2.67 mW/oC.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-41
TIL191, TIL192, TIL193, TIL191A, TIL192A, TIL193A
TIL191 B, TIL192B, TIL193B
OPTOCOUPLERS
SOES026 - APRIL 1989 - REVISED OcTOBER 1995
electrical characteristics 25°C free-air temperature range (unless otherwise noted)
PARAMETER
MIN
TEST CONDITIONS
V(BR)CEO
Collector-emitter breakdown voliage
Ic=0.5mA,
IF=O
35
V(BR)ECO
Emitter-collector breakdown voltage
IC = 100 !lA,
IF=O
7
IR
Input diode static reverse current
VR=5V
IClolI)
Off-state collector current
VCE=24V,
TIL191A,
TIL192A,
TIL193A
Current transfer ratio
MAX
UNIT
V
V
IF=O
TIL191 ,
TIL192,
TIL193
CTR
TYP
10
!lA
100
nA
1.4
V
20%
IF=5rnA
50%
VCE=5V
TIL191B,
TIL192B,
TIL193B
100%
VF
Input diode static forward voltage
IF=20mA
VCElsat)
Collector-emitter saturation voltage
.IF=5mA
IC=1 rnA
Cio
Input-to-output capacitance
Vin-out = 0 mA
f=1 MHz,
1]0
Input-to-output intemal resistance
Vin-out = ±1 rnA
See Note 6
V
0.4
pF
1
1011
0
NOTE 6: These parameters are measured between all input diode leads shorted together and all phototransistor leads shorted together.
switching characteristics at 25°C free-air temperature
PARAMETER
tr
tf
TEST CONDITIONS
I Rise time
IFall time
VCC=5V,
RL=1000,
TYP
UNIT
6
1C(0~=2 mA,
See igure 1
----a
PARAMETER MEASUREMENT INFORMATION
470
.---/-;'-f-->,,--WIr-- Input (see Note A)
Input...)
r-If-e-- Output (see Note 8)
VCC=5V
RL= 100 0
Output
-+I 14- Ir
-+I 14- tf
.)'10%
10%'l
!~!
NOTE C. Adjust amplitude of input
pulse for IC(on) = 2 mA
TEST CIRCUIT
VOLTAGE WAVEFORMS
NOTES: A. The input waveform is supplied by a generator with the following characteristics: ZoUT = 50 n, tr :s;: 15 ns, tw 100 IJS.
B. The output waveform is monitored on a oscilloscope with the following characteristic: tr :s;: 12 ns, Rin ;:: 1M IJS, Cin :s;: 20 pF.
Figure 1. Switching Times
~TEXAS ~
7-42
INSTRUMENTS
POST OFFICE eox 655303 • DALLAS, TEXAS 75265
IJS
TIL191, TIL192, TIL193, TIL191A, TIL192A, TIL193A
TIL191 B, TIL192B, TIL193B
OPTOCOUPLERS
SOES026 -APRIL 1989 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
TlL191, TIL192, TlL193
COLLECTOR CURRENT
FORWARD CURRENT
va
va
FORWARD VOLTAGE
COLLECTOR-EMITTER VOLTAGE
160
16
II
/', I
I, I
, rH :1
T~=7~oC III
rl I
JIII
140
et:
E
120
I
1:
~
a
1!
100
et:
I
1:
g
u
"
J
60
.!!-
40
I
I
12
E
TA=25°C 80
18=0
TA = 25°C
14
j
I
!:!
IF=12mA
-
I I
IF=10mA
1
/-
10
IF=8mA
I
8
I
1
6
I
4 1/
IFl2m~
2
~V
o
o
0.2 0.4 0.6 0.8
1
II"
1.2 1A 1.6 1.8
2
3
4
5
6
7
8
9
VCE - Collector-Emitter Voltage - V
VF - Forward Voltage - V
ON-STATE COLLECTOR CURRENT
(RELATIVE TO VALUE AT 25°C)
ON-5TATE COLLECTOR CURRENT (NORMALIZED)
~
vs
vs
INPUT DIODE FORWARD CURRENT
FREE-AIR TEMPERATURE
100
1.2
VCE=5V
Normalized to IF = 5 mA
TA=25°C
10
1.1
1:
~::I
U
~
0
1: ....
~c;:
::let:
~I-
0.9
=::1
0.8
~S
0.7
51!5.
0.6
i:
j
"
1,,\
8;i
1/
0.1
I
~1
/
0.01
I
~ 0.001
-
0.1
VCE=5V
IF=5mA
18=0
-......
./
?
~
8
10
Figure 3
Figure 2
1
r-
1
o
o
2
r-
IF=5mA
TA=-55°C
20
-
"-
"'\
f\.
0.5
I
40
0.4
4
10
IF -Input Diode Forward Current - mA
100
0.4
-50
-25
25
75
o
50
TA - Free-Air Temperature - °C
\
100
FigureS
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7--43
TIL191,TIL192, TIL193, TIL191A,TIL192A, TIL193A
TIL191B, TIL192B, TIL193B
OPTOCOUPLERS
SOES026 -APRIL 1989 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
. COLLECTOR-EMITTER SATURATION VOLTAGE
VB
FREE·AIR TEMPERATURE
>
0.24
~
I
IF=5mA
10=1 mA
J
0.20
i
0.16
~
j
I
j
0.12
........ ~
0.08
~
~
/"
/
8
I
J
0.04
0
-50
-25
o
25
75
50
100
TA - Free·Alr Temperature - °0
Figure 6
APPLICATION INFORMATION
5 V --------,
, - - - - - - - - Vee
=5 V
" X ) - - OUTPUT
SN7404
INPUT
Figure 7
~TEXAS
7-44
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
TIL191, TIL192, TIL193, TIL191A, TIL192A, TIL193A
TIL191 B, TIL192B, TIL193B
OPTOCOUPLERS
SOES026 -APRIL 1989 - REVISED OCTOBER 1995
MECHANICAL INFORMATION
TlL191
Pin 1
TlL192
o
Pin 1
21,1 (0.831)
18,5 (0.728)
,......., ,.......,,....., ,.......,.-..,......
TlLl93
14---~
7,62 (0.300) T.P.
(see Note A)
o
Pin 1
i4---.!+- 6,76 (0.266)
=:1
6,25 (0.246)
:::~lg:~:l
to'51(OS·125)MI~N
5,84 (O.230>tAX
seating Plane
;
_
t
j.- 1,27 (0.050)
_
3,81 (0.150)
2,54 (0.100)
~
~ ~
I
2,79 (0.110)
2,29 (0.090)
jI*t
1,12(0.017)
0,58 (0.023)
0,43 (0.017)
NOTES: A. Each pin center1ine is located within 0,25 (0.010) of its true longitudinal position.
B. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 8. Mechanlcallnfonnatlon
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
7-45
TIL300, TIL300A
PRECISION LINEAR OPTOCOUPLER
SOES019-OCTOBER 1995
•
•
•
•
,•
PPACKAGE
(TOPV1EW)
ac or de Signal Coupling
Wide Bandwidth ••• >200 kHz
High Transfer-Galn Stability •.• iO.05%/"C
3500 V Peak Isolation
UL Approval Pending
LEDK
LEDA
PDK1
PDA1
• Applications
- Power-Supply Feedback
Medical-Sensor Isolation
- Opto Direct-Access Arrangement (DAA)
- Isolated Process-Control Transducers
NC - No internal connection
description
The TIL300 precision linear optocoupler consists of an infrared LED irradiating an isolated feedback photodiode
and an output photodiode in a bifurcated arrangement. The feedback photodiode captures a percentage of the
flux of the LED and generates a control signal that can be used to regulate the LED drive current. This technique
is used to compensate for the nonlinear time and temperature characteristics of the LED. The output-side
photodiode produces an output Signal that is linearly proportional to the servo-optical flux emitted from the LED.
A typical application circuit (shown in Figure 1) uses an operational amplifier as the input to drive the LED. The
feedback photodiode sources current through Ri, which is connected to the inverting input of the input
operational amplifier. The photocurrent Ip1 assumes a magnitude that satisfies the relationship Ip1 = VI/Ri. The
magnitude of the current is directly proportional to the LED current through the feedback transfer gain
Ki (VllRi = Ki x IF)' The operational amplifier supplies LED current to produce sufficient photocurrent to keep
the node voltage Vb equal to node voltage Va.
3=
w
5>
w
a:
Q.
~
TIL300
::;:)
C
oa:
R3
+
Q.
1VCeVo = K3(R2/R1) VI
NOTES: A. K1 is servo current gain. the ratio of the feedback photodiode current (lP1) to the input LED current (IF). i.e. k1 =.IP1/IF.
B. K2 is forward gain. the ratio of the output photodiode current (lp2) to the input LED current (IF). i.e. K2 Ip2"lf'.
C. K3ls transfer gain. the ratio of the forward gain 10 the servo gain. i.e. K3 K21K1.
=
=
Figure 1. TYpical Application Circuit
===
PRODUCTPREVIEW _ _ ...-mlnlllo_or
01 cIeveIopnaL,
_
and
-.
118d101ang0af8.
___
Il10 rIFt'"
~
or_lhaIo,-_notIoe.
~TEXAS
Copyright © 1995. Texas Instruments Incorporated
.
INSTRUMENTS
POST OFFICE BOX 655303 • DAUAS. TEXAS 75265
7-47
TIL300, TIL300A
PRECISION LINEAR OPTOCOUPLER
SOES019-0CTOBER 1995
Terminal Functions
TERMINAL
NAME
NO.
DESCRIPTION
110
LEDK
1
LEDA
2
LED cathode
LED anode
PDK1
3
Photodiode 1 cathode
PDA1
4
Photodiode 1 anode
PDA2
5
Photodiode 2 anode
PDK2
6
Photodiode 2 cathode
Ne
7
No intemal connection
Ne
8
No intemal connection
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Emitter
Continuous power dissipation (see Note 1) ................................................ 160 mW
Input LED forward current, 'F .............................................................. 60 rnA
Surge current with pulse width < 10 ~ ..................................................... 250 rnA
Reverse voltage, VR ........................................................................ 5 V
Reverse current, 'R ....................................................................... 10 ~
"U
::D
o
Detector
C
c:
Continuous power dissipation (see Note 2) ................................................. 50 mW
Reverse voltage, VR ...................................................................... 50 V
~
Coupler
Continuous power dissipation (see Note 3) ................................................ 210 mW
Storage temperature, Tstg ........................................................ -55°C to 150°C
Operating temperature, TA ....................................................... -55°C to 100°C
Input-to-output voltage ............................................................... 3500 Vpeak
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...... . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
"U
::D
m
<
-
m
:e
NOTES: 1. Derate linearly from 25°e at a rate of 2.66 mW/oe.
2. Derate Iinear1y from 25°e at a rate of 0.66 mW/oe.
3. Derate Iinear1y from 25°e at a rate of 3.33 mW/oe.
~TEXAS
7-48
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. :rEXAS 75265
TIL300, TIL300A
PRECISION LINEAR OPTOCOUPLER
SOES019-OCTOBER 1995
electrical characteristics at TA = 25°C
Emitter
PARAMETER
VF
CONDITIONS
Forward voltage
MIN
IF=10mA
TYpt
MAX
1.25
1.SO
V
mV/oC
-2.2
VF temperature coefficient
UNIT
IR
Reverse current
VR=5V
tr
Rise time
IF=10mA,
Ll.IF=2mA
1
J.1S
tf
Fall time
IF= 10 rnA,
Ll.IF=2mA
1
Cj
Junction capacitance
VF=O,
f= 1 MHz
J.1S
pF
10
15
!LA
Detector
PARAMETER
CONDITIONS
MIN
TYpt
MAX
25
UNIT
Dark current
VR=15V,
Open circuit voltage
IF=10mA
0.5
V
lOS
Short circuit current limit
IF=10mA
80
!LA
Cj
Junction capacitance
VF=O,
12
pF
IDKt
IF=O
f=1 MHz
nA
Coupler
PARAMETER
K1:t:
Servo current gain
K2§
Forward current gain
Detector bias
voltage=-15V
TIL300
K311
Transfer gain
TIL300A
Gain temperature coefficient
Ll.K3'
Transfer gain linearity
MIN
TYpt
MAX
IF=1 rnA
0.3%
0.5%
0.8%
IF=10mA
0.5%
0.8%
1.1%
IF=1 rnA
0.3%
0.5%
0.8%
IF=10mA
0.5%
0.8%
1.1%
IF=1 rnA
0.75
1
1.25
IF=10mA
0.75
1
1.25
IF= 1 rnA
0.9
1
1.10
IF=10mA
0.9
1
1.10
CONDITIONS
K11K2
K3
-0.5
IF= 10mA
to.OD5
TA=Ot075°C
Bandwidth
IF= 10 rnA,
IF(MODULATION)
RL=50n,
Rise time
IF=10mA,
IF(MODULATION)
RL= SOn,
tf
Fall time
IF= 10 rnA,
IF(MODULATION)
RL= 50 n,
Visot
Peak Isolation voltage
110 = 10 !LA,
f=60Hz
tr
w
a.
'Yorc
200
kHz
1.75
J.1S
1.75
~s
V
~lExAs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
C
o
fX
t This symbol is not currentiy listed within EIA or JEDEC standards for semiconductor symbology.
:t:Servo current gain (K1) is the ratio of the feedback photodiode current (lp1) to the input LED current (IF) current (IF), i.e. K1 = Ip1/1F
§ Forward gain (K2 is the ratio of the output photodiode current (lp2) to the input LED current (IF), i.e. K2 = IP2/IF.
11 Transfer gain (K3) is the ratio of the forward gain to the servo gain, i.e. K3 = K21K1.
# Transfer gain linearity (Ll.K3) is the percent deviation of the transfer gain K3 as a function of LED input current (IF) or the package temperature.
INSTRUMENTS
13
::l
a.
to.5%
3500
3:
w
5>
fX
to.25%
IF=1t010mA
IF = 1 to 10 rnA,
BW
UNIT
7--49
7--50
TIL3009 THRU TIL3012
OPTOCOUPLERSIOPTOISOLATORS
SOES027 - DECEMBER 1987 - REVISED OCTOBER 1995
TIL30209- nL3012 ..• PACKAGE
(TOP VIEW)
• 25O-V Phototrlac Driver Output
• Galllum-Arsenlde-Dlode Infrared Source
and Optlcally-Coupled Silicon Triac Driver
(Bilateral Switch)
• UL Recognized. .. File Number E65085
• High Isolation ••• 3535 V peak
• Output Driver Designed for 115 V AC
• Standard 6-Pin Plastic DIP
ANODE
CATHODE
NC
01
2
3
6
5
4
MAIN TERM
TRIAC SUBt
MAIN TERM
t Do not connect this terminal
NC - No intemal connection
description
logic diagram
.Each device consists of a gallium-arsenide
infrared-emitting diode optically coupled to a
silicon phototriac mounted on a 6-pin lead frame
encapsulated within an electrically nonconductive
plastic compound. The case withstands soldering
temperature with no deformation. Device performance characteristics remain stable when
operated in high-humidity conditions.
absolute maximum ratings at 25°C free-air (unless otherwise noted)t
Input-to-output peak voltage, 5 s maximum duration, 60 Hz (see Note 1) ...................... 3.535 kV
Input diode reverse voltage .................................................................. 3 V
Input diode forward current, continuous ..................................................... 50 mA
Output repetitive peak off-state voltage ..................................................... 250 V
Output on-state current, total rms value (50-60 Hz, full sine wave):
TA = 25° .............................................................................. 100 mA
TA=70° ., ............................................................................ 50mA
Output driver non repetitive peak on-state current
(tw = 10 ms, duty cycle = 10%, see Figure 7) ............................................. 1.2 mA
Continuous power diSSipation at (or below) 25°C free-air temperature:
Infrared-emitting diode (see Note 2) .................................................... 100 mW
Phototriac (see Note 3) ............................................................... 300 mW
Total device (see Note 4) ............................................................. 330 mW
Operating junction temperature range, TJ .......................................... -40°C to 100°C
Storage temperature range, Tstg .................................................. -40°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommanded operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Input-Io-output peak voltage is the intemal device dielectric breakdown rating.
2. Derate linearly to 100·C free-air temperature at the rate of 1.33 mW/·C.
3. Derate linearly to 100·e free-air temperature at the rate of 4 mW/·e.
4. Derate linearly to 1aa·e free-air temperature at the rate of 4.4 mWFC.
~TEXAS
copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 •
DALLAS. TEXAS 75265
7-51
TIL3009 THRU TIL3012
OPTOCOUPLERSIOPTOISOLATORS
SOES027 - DECEMBER 1987 - REVISED OCTOBER 1995
electrical characteristics 25°C free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IR
Static reverse current
VR=3V
VF
Stalic forward voltage
IF= 10mA
IORM
Repetitive off-state currerit, either direction
VORM=250V,
dv/dt
Critical rate of rise of off-state voltage
See Figure 1
dv/dt(c)
Critical rate of rise of communication voltage
IO=15mA,
See Note 5
Input trigger current either direction
VTM
Peak on-state voltage, either direction
IH
Holding current, either direction
Tll301 0
TIL3011
l)'P
MAX
0.05
100
1.2
1.5
V
10
100
nA
12
See Figure 1
TIL3009
1FT
MIN
Output supply voltage = 3 V
V/jJ.s
30
8
15
5
10
1.8
3
TIl3012
)1A
VljJ.s
0.15
15
UNIT
5
ITM= 100 rnA
100
NOTE 5: Test voltage must be applied within dv/dt rating.
PARAMETER MEASUREMENT iNFORMATION
Vce
Vln=30V finS
Input
(see Note A)
_ - '10
lMkn
,-f-l
NOTE A. The critical rate of rise of off-state voltage, dv/dt, is measured with the input of 0 volts. The frequency of Yin is increased until
the phototriac turns on. This frequency is then used to calculate the dv/dt accOrding to the following formula:
dv/dt = 2J21tfV in
The critical rate of rise of commutating voltage, dv/dt(c), is measured by applying occasional 5-volt pulses to the input and
increasing the frequency of Yin until the phototriac remains on (latches) after the input pulse has ceased. With no further input
pulses., the frequency of Yin is then gradually decreased until the phototriac turns off. The frequency at which tum-off occurs
can then be used to calculate the dv/dt(c) according to the formula shown above.
Figure 1. CRITICAL RATE OF RISE TEST CIRCUIT
~TEXAS
7-52
rnA
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
)1A
TIL3009 THRU TIL3012
OPTOCOUPLERS/OPTOISOLATORS
SOES027 - DECEMBER 1987 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
EMITTING DIODE TRIGGER CURRENT (NORMALIZED)
vs
ON-STATE CHARACTERISTICS
FREE-AIR TEMPERATURE
1.4
BOO
iu
600
_
1.2
~
d..
g
1.1
1I
200
iI
"
~
I
I
~
aI
c
i!
400
1
1\
~
0.9
E
-200
-400
-600
-BOO
o
-25
25
75
50
100
L
V
/
/'
/
-1
o
2
VTM - Pesk On-state Voltage - V
Figure 2
Figure 3
CRITICAL RATE OF RISE OF OUTPUT VOLTAGE
CRITICAL RATE OF RISE OF OUTPUT VOLTAGE
OFF-STATE dv/dt AND COMMUTATING dv/dt(c)
vs
vs
LOAD RESISTANCE
FREE-AIR TEMPERATURE
r------,r-----.....,------,
!
---1-
-l.state
12
0.20
II
::I.
S
.!
Commutatl~..
8
...."
6
........
....
....'"
1------
0.16
-
0.24
dv/dt
dv/dt(c)
I - - T - - _ i f - - - - - - - / - - - - - - / 0.2
II
II
~
~
..!..
I
10
'U
~
3
OFF-STATE dv/dt AND COMMUTATING dv/dt(c)
TA = 25°C
See Figure 2
i:Ii
~
-2
-3
TA - Free-Air Temperatura - °C
I
/
/
/
o
III
0.8
-50
L
Output tw = 80 IJ.S
IF=20mA
f=60Hz
TA = 25°C
i - - - - - - - ' I , . - - - - I f - - - - - - - f - - - - - I 0.16
i
u
I'
~
1--~
'U
.~
:Ii
_____if----30..,.._--/------/ 0.12 -:,
,I
0.12 ~
I-___-=O'-Ji=-+-----=='-I~..:::_----/ 0.08 E
E
~
~
0.08
21----_if-----='-----/----.:=:::t 0.04
0.04
OL.....-----''-------'------'0
RL=510n
- - dv/dt
- - - dv/dt(c)
4
o
0.4
0.8
1.2
1.6
2
~
n
~
100
TA - Free-Air Temperature - °C
RL - Load Resistance - len
Figure 4
Figure 5
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-53
TIL3009 THRlJITIL3012
OPTOCOUPLERSIOPTOISOLATORS
SOES027 - DECEMBER 1987 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
RMS APPLIED VOLTAGE
(FOR dv/dt(c) = 0.15 VlllS)
NONREPETInVE PEAK ON-STATE CURRENT
vs
vs
FREQUENCY
PULSE DURATION
1000
3
RL=1 ItO
,..
dv/cIt = 2..J27t1 VI
>
I
100
~
:I
40
"
2
......
,dv/cIt=O.
II)
II:
r--
r--- ...
J
lIE
Tl~~~o~1
TA .. 25°C
400
IllS
"'r-
.....
10
"
I
>"
4
1
100
400
1k
4k
"
10k
o
40k 100k
0.01
f - Frequency - Hz
10
tw - Pulse Duretion - ms
Figure 6
Figure 7
~TEXAS
INSTRUMENTS
7--54
0.1
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
100
TIL3009 THRU TIL3012
OPTOCOUPLERS/OPTOISOLATORS
SOES027 - DECEMBER 1987 - REVISED OCTOBER 1995
APPLICATION INFORMATION
TIL3009, TIL3012
6
1800
220 V, 60 Hz
4
2
Figure 8. Resistive Load
TIL3009, TIL3012
6
1800
0.111F
220 V, 60 Hz
4
2
IGT,,;15mA
Figure 9. Inductive Load With Sensitive-Gate Traic
TIL3009, TIL3012
, Rin
6
1800
0.211F
220 V, 60 Hz
4
2
15mA'-15'
2,29 (0.090)
1 ,27 (0.050)
4 Places
2,54 (0.100) T. .
0.010 (0,25) NOM
(see Note A)
NOTES: A. Leads are within 0,13 mm (0.005 inch) radius of true position (T.P.) with maximum material condition and unit installed.
B. 'Pin 1 identified by index dot.
C. Terminal connections:
1. Anode (part of infrared-emitting diode)
2. Cathode (part of infrared-emitting diode)
3. No internal connection
4. Main terminal (part of phototriac)
5. Triac Substrate (DO NOT connect) (part of phototriac)
6. Main tenninal (part of phototriac)
O. The dimensions given fall within JEOEC MO-001 AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 11. Mechanical Information
~TEXAS
7-56
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TIL3020 THRU TIL3023
OPTOCOUPLERSIOPTOISOLATORS
SOES028 - DECEMBER 1987 - REVISED OCTOBER 1995
T1L3020 - T1L3023 ... PACKAGE
• 400-V Phototriac Driver Output
(TOP VIEW)
• Gallium-Arsenide-Diode Infrared Source
and Optically-Coupled Silicon Triac Driver
(Bilateral Switch)
ANODE [ ] 1
6 MAIN TERM
CATHODE 2
5 TRIAC sust
NC 3
4 MAIN TERM
• UL Recognized. .. File Number E65085
• High Isolation . .. 3535 V peak
• Output Driver Designed for 220 V AC
t
Do not connect this tenninal
NC - No intemal connaction
• Standard 6-Pin Plastic DIP
description
Each device consists of a gallium-arsenide
infrared-emitting diode optically coupled to a
silicon phototriac mounted on a 6-pin lead frame
encapsulated within an electrically nonconductive
plastic compound. The case withstands soldering
temperature with no deformation. Device performance characteristics remain stable when
operated in high-humidity conditions.
logic diagram
absolute maximum ratings at 25°C free-air (unless otherwise noted)t
Input-to-output peak voltage, 5 s maximum duration, 60 Hz (see Note 1) ...................... 3.535 kV
Input diode reverse voltage .................................................................. 3 V
I,nput diode forward current, continuous ..................................................... 50 rnA
Output repetitive peak off-state voltage ..................................................... 250 V
Output on-state current, total rms value (50-60 Hz, full sine wave):
TA = 25°C ................................................................ " .......... 100 mA
TA=70°C ............................................................................ 50mA
Output driver non repetitive peak on-state current
(tw = 10 ms, duty cycle = 10%, see Figure 7) ............................................. 1.2 mA
Continuous power dissipation at (or below) 25°C free-air temperature:
Infrared-emitting diode (see Note 2) .................................................... 100 mW
Phototriac (see Note 3) .....•......................................................... 300 mW
Total device (see Note 4) ............................................................. 330 mW
Operating junction temperature range, TJ .......................................... -40°C to 100°C
Storage temperature range, Tstg .................................................. -40°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings" may cause pennanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other condHions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affact device reliability.
NOTES: 1. Input-to-output peak voltage is the intemal device dielectric breakdown rating.
2. Derate linearly to 100°C free-air temperature at the rate of 1.33 mW/oC.
3. Derate linearly to 100°C free-air temperature at the rate of 4 mW/oC.
4. Derate linearly to 100°C free-air temperature at the rate of 4.4 mW/oC.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655300 • DALlAS, TEXAS 75265
7-'57
TIL3020 THRU TIL3023
OPTOCOUPLERSIOPTOISOLATORS
SOES028 - DECEMBER 1987 -: REVISED OCTOBER 1995
electrical characteristics' 25°C free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IR
Static reverse current
VR=3V
VF
static fOlWard voltage
IF= lOrnA
IORM
Repetitive off-state current, either direction
VORM = 250 V,
dv/dt
Critical rate of rise of off-state voltage
See Figure 1
dv/dt(c)
Critical rate of rise of communication voltage
lo=15mA,
MIN
See Note 5
Input trigger current, either direction
VTM
Peak on-state voltage, either direction
IH
Holding current, either direction
TIL3021
TIL3022
MAX
0.05
100
1.2
1.5
V
10
100
nA
100
See Figure 1
TIL3020
1FT
UNIT
TYP
Output supply voltage = 3 V
TIL3023
ITM= 100 rnA
I1A
V/o,JS
0.15
V/o,JS
15
30
8
15
5
10
3
5
1.4
3
100
NOTE 5: Test voltage must be applied at a rate no higher than 12 V/o,JS.
PARAMETER MEASUREMENT INFORMATION
Vee
6
Vln=30Vrms
Ok{l'
Input.
(see Note A)
~
4
2
2N3904
NOTE A. The critical rate of rise of off-state voltage, dv/dt, is measured with the input of 0 volts. The frequency of Yin is increased until
the phototriac turns on. This frequency is then used to calculate the dv/dt according to the following formula:
dv/dt = 2v'23tfVin
The critical rate of rise of commutating voltage, dv/dt(c), is measured by applying occasional 5-volt pulses to the input and
increasing the frequency of Yin until the phototriac remains on (latches) after the input pulse has ceased. With no further input
pulses., the frequency of Yin is then gradually decreased until the phototriac turns off. The frequency at which tum-off occurs
can then be used to calculate the dv/dt(c) according to the formula shown above.
Figure 1. Critical Rate of Rise Test Circuit
~TEXAS
7-58
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
rnA
V
I1A
TIL3020 THRU TIL3023
OPTOCOUPLERS/OPTOISOLATORS
SOES028 - DECEMBER 1987 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
EMITTING DIODE TRIGGER CURRENT (NORMALIZED)
vs
FREE-AIR TEMPERATURE
ON-STATE CHARACTERISTICS
800
1.4
'6'
=
1.3
!.
1.2
1
'E
~
i
!
200
!i
1.1
1'--...
II
1\
11\
0.9
0.8
-SO
-25
o
o
25
75
50
I
~
/
V
-400
-600
-800
-3
100
/
/
-200
~
~w
400
:::s
r
c
I
U
:::s
U
1
7
7
Output tw = 800 jlS
IF=20mA
f=60Hz
TA = 25°C
600
/
I
o
-2
2
3
VTM - Peak On-8tete Voltage - V
TA - Free-Air Temperature - °c
Figure 3
Figure 2
NONREPETITIVE PEAK ON-STATE CURRENT
vs
PULSE DURATION
3
Tl~J~o~1
2
~
..... 1--
f"r-.
..........
o
0.01
0.1
Iw -
10
100
Pulse Duration - ms
Figure 4
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-59
TIL3020 THRU TIL3023
OPTOCOUPLERS/OPTOISOLATORS
SOES028 - DECEMBER 1987 - REVISED OCTOBER 1995
APPLICATION INFORMATION
TIL3020, TIL3023
Rin
vee
-.
-.
220
v, 60 Hz
2
Figure 5. Resistive Load
TlL3020, TlL3023
Rin
vee
-.
-.
220
v, 60Hz
2
IGT~15mA
Figure 6. Inductive Load With Sensitive-Gate Traic
TIL3020, TIL3023
6
1800
0.211F
4
2
15 mA < IGT < 50 mA
Figure 7. Inductive Load With Nonsensitive-Gate Triac
~TEXAS
INSTRUMENTS
7-60
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
220V,60Hz
TIL3020 THRU TIL3023
OPTOCOUPLERS/OPTOISOLATORS
SOES028 - DECEMBER 1987 - REVISED OCTOBER 1995
MECHANICAL INFORMATION
9'40(0.370)~
8,38 (0.330)
000
Index Dot
(see Note B)
7,62 (0.300) T.P.
(see Note A)
,
I
(2) ® CD
6,61 (0.260)
6,09 (0.240)
(see Note C)
1,78 (0.070) MAX
6 Places
(r
J
\
1105°
l ...... 90°
JL
-
Seeting Plane
U
---. ~ 0°_15°
0.010 (0,25) NOM
2,29 (0.090)
1,27 (0.050)
4 Places
2,54 (0.100) T. •
(see Note A)
NOTES: A. Leads are within 0,13 (0.005) radius of true position (T.P.) with maximum material condition and unit installed.
B. Pin 1 identnied by index dot.
C. Terminal connections:
1. Anode (part of the infrared-emitting diode)
2. Cathode (part of the infrared·emitting diode)
3. No internal connection
4. Main terminal (part of the phototransistor)
5. Triac Substrate (DO NOT connect) (part of the phototransistor)
6. Main terminal (part of the phototransistor)
D. The dimensions given fall within JEDEC MO-oOl AM dimensions.
E. All linear dimensions are given in millimeters and parenthetically given in inches.
Figure 8. Mechanical Information
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
7-61
7-62
TPS5904,TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIFIERS
• TL431 Precision Programmable Reference
and an Optocoupler in a Single Package
• 0.4% Voltage-Reference Tolerance
• Controlled Optocoupler CTRs:
TPS5904
100% to 400%
TPS5904A
150% to 300%
• High Withstand Voltage (WTV), 7500 V Peak
,for 1 Minute
• UL Recognized - File #E65085
• VOE 884 Agency Approval Pending
PPACKAGE
(TOP VIEW)
LEoDa
COMP
GNO
FB
2
3
4
7
6
5
NC
C
E
NC
NC - No internal connection
description
The TPS5904 and TPS5904A opto-isolated feedback amplifiers consist of the industry standard TL431
precision programmable reference with a 0.4% reference voltage tolerance, and an optocoupler. The devices
are primarily intended for use as the error-amplifier/reference/isolation-amplifier element in isolated ac-to-dc
power supplies and dc-to-dc converters. The optocoupler is a gallium-arsenide (GaAs) light-emitting diode that
emits at a wavelength of 940 nm, combined with a silicon phototransistor. The current transfer ratio (CTR)
ranges from 100% to 400% in the standard version. The TPS5904A version with a 150%-to-300% CTR is
available for higher-performance applications. When using the TPS5904 or TPS5904A, power-supply
designers can reduce component count and save space in tightly packaged designs. The tight-tolerance
reference eliminates the need for adjustments in many applications.
The TPS5904 and TPS5904A are characterized for operation from -40°C to 100°C. Each device is supplied
in an S-pin DIP package.
typical application
+
Vo
PWM
Control
1
r------,
L-~_ _ _ _ _ _ _·~7+o
I
II
r-~11~--~~----~
~
R1
61
TPS5904P : CTR Range, 100% to 400%
TPS5904AP : CTR Range, 150% to 300%
I
I
3
II.. _
TPS5904
_ _ _ _ _ .J
~TEXAS
R2
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS, TEXAS 75265
7-63
TPS5904, TPS5904A
OPTO-tSOLATEDFEEDBACK AMPLIFIERS
SOES016A- MAY 1995 - REVISED OCTOBER 1995
functional block diagram
:.~
LED
1
COMP
2
(7C
~
BE
Terminal Functions
TERMINAL
NAME
NO.
C
7
COMP
2
E
6
Fa
4
GND
3
LED
NC
1
5,8
VO
DESCRIPTION
Phototransistor collector
0
Light·emitting diode and TL431 cathodes
Phototransistor emitter
I
Feedback
Ground
I
Light-emitting diode anode
No connection
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)t
Input power dissipation at (or below) TA =25°C (see Note 1) ................................ 250 mW
Input LED current, II(LED) .............................................................. ;.. 50 mA
Input LED voltage, VI(LED) . ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 37 V
Input diode reverse voltage .................................................................. 6 V
Output power dissipation at (or below) TA = 25°C (see Note 2) ............................... 150 mW
Output collector-to-emitter voltage .......................................................... 35 V
Output emitter-to-collector voltage ............................................ '.. . . . . . . . . . . . . .. 7 V
Output collector current ................................................................... 50 mA
Total continuous power dissipation at (or below) TA = 25°C (see Note 3) ...................... 350 mW
Operating free-air temperature range, TA .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -40°C to 100°C
Storage temperature range, Tstg .................... ,............ ... ..... ... . ...... -55°C to 150°C
Total input-to-output voltage .......................................... 7.5 kV peak or dc (5.3 kVrms)
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
Flammability ................................................................... , ... (see Note 4)
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those Indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Derate linearly from 25°C at a rate of 2.95 mW/"C.
2. Derate linearly from 25°C at a rata of 1.76 mW/oC.
3. Derate linearly from 25°C at a rate of 4.12 mW/"C.
4. Optocoupler total-package flame retardancy is tested to IEC695-2-2 using a flame application time of 30 seconds. Outer mold
compound is verified to meet UL 94V-O.
~TEXAS
7-64
INSTRUMENTS
PQST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPS5904, TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIFIERS
SOES016A - MAY 1995 - REVISED OCTOBER 1995
electrical characteristics, TA = 25°C (unless otherwise noted)
input
PARAMETER
TEST CONDITIONS
VF
Light-emitting diode forward voltage
VO(COMP) = VI(FB),
See Figure 1
IR
Light-emitting diode reverse current
VR=6V
MIN
II(LED) = 10 mA,
TYP
MAX
1.2
1.4
V
10
I!A
2.51
V
UNIT
Vref
Reference voltage
VO(COMP) = VI(FB),
See Figure 1
II(LED) = 10 mA,
Vref(dev)
Deviation of reference voltage over
temperature
VO(COMP) = VI(FB),
TA = 25°C to 100°C,
II(LED) = 10 mA,
See Figure 1
t.Vref
t.VI(LED)
Ratio of reference voltage change-tochange in input light-emitting-diode voltage
t.VI(LED) = 4 V to 37 V,
See Figure 2
II(LED) = 10 mA,
II(FB)
Feedback input current
II(LED) = 10 mA,
See Figure 2
R3=10kel,
Iref(dev)
Deviation of reference input current over
temperature
II(LED) = 10 mA,
TA = 25°C to 100°C,
R3= 10kel,
See Figure 3
0.5
IDRV(min)
Minimum drive current
VO(COMP) = VI(FB),
See Figure 1
0.45
1
mA
II(off)
Off-state input light-emitting-diode current
VI (LED) = 37 V,
See Figure 4
VI(FB) =0,
0.18
0.5
I!A
IZkalt
Regulator output impedance
VO(COMP) = VI(FB),
I,;; 1 kHz,
10(COMP) = 1 mA to 50 mA
t This symbol
IS
2.49
2.5
25
,
mV
-1.1
-2
1.5
3
mVIV
I!A
I!A
0.1
el
not currently listed Within EIA or JEDEC standards lor semiconductor symbology.
output
PARAMETER
TEST CONDITIONS
ICEO
Collect dark current
VCE = 35 V,
V(BR)ECO
Emitter-collector voltage breakdown
IE= 1OO I!A
MIN
TYP
See Figure 5
MAX
UNIT
100
nA
7
V
coupler
PARAMETER
CTR
Current transler ratio
TEST CONDITIONS
I TPS5904
I TPS5904A
VO(COMP) = VI(FB),
VCE = 5 V,
II(LED) = 5 mA,
See Figure 6
VO(COMP) = VI(FB),
IC=1 mA,
II(LED) = 10 mA,
See Figure 6
VCE(sat)
Collector-emitter saturation voltage
Visot
Isolation voltage
110 = 10!!A,
1= 60 Hz
Cio
Input to output capacitance
VIO=O,
f = 1 kHz
t This symbol
IS
MIN
TYP
MAX
100%
400%
150o/~
300%
0.1
7500
0.2
UNIT
V
V
0.6
pF
not currently listed Within EIA or JEDEC standards for semiconductor symbology.
"!!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7--65
TPS5904,TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIFIERS
SOES016A- MAY 1995 - REVISED OCTOBER 1995
PARAMETER MEASUREMENT INFORMATION
v
v
Figure 2. ~Vref/~V'{LED) Test Circuit
Figure 1. Vref, VF, 'min Test Circuit
'~)+-'(~) 'l--~-~-r
A
v
2
I
.......
I
I
~~~~~
6
I
I
I
L _ _ _ _ _ _ ..J.
v
Figure 4. "(off) Test Circuit
Figure 3. "(FB) Test Circuit
ICEO
-.
II(LED)
Figure 6. CTR, VCE{sat) Test Circuit
Figure 5. 'CEO Test Circuit
~TEXAS
INSTRUMENTS
7'-66
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
+-
TPS5904, TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIFIERS
SOES016A- MAY 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
INPUT L1GHT-EMITTING-DIODE CURRENT
vs
REFERENCE VOLTAGE
CC
INPUT L1GHT-EMITTING-DIODE CURRENT
vs
REFERENCE VOLTAGE
60
1400
:I.
~
VO(COMP) = VI(FB)
TA=25·C
I
VO(COMP) = VI(FB)
TA=25·C
I
~
50
:::I
(.)
GI
800
40
E
30
is
ill
c
600
.D..:.
.c
400
200
o
i
/
y
o
- '1.5
0.5
20
~
'5
D-
.5
10
I
S"
W
2
.....C-
3
2.5
O
RATIO OF DELTA REFERENCE
VOLTAGE TO DELTA LED VOLTAGE
vs
FREE-AIR TEMPERATURE
2.53
J
VO(COMP) = VI(FB)
II(LED) = 10 mA
~
2.52
J
e3
il
2.51
~
a:
I
J
2.5
2.49
2.48
" '"
'" "
"
2.47
-50
~
............
i'..
-25
o
3
FigureS
REFERENCE VOLTAGE
vs
FREE-AIR TEMPERATURE
I
2.5
2
Vref - Reference Voltage - V
Figure 7
>
1.5
0.5
0
Vref - Reference Voltage - V
25
S
-0.95
........
-1.05
l=r
a: &
J!I!
",
-1.15
""'-
~
1I~
..............
eo
ow
.S!
~I
I
VI(LED) = 4 V to 37 V
II(LED) = 10 mA
S -1.25
~~
aB
::!
~
_1.35
~
i
>,:
100....
-1.45
-50
-25
TA - Free-Air Temperature _·C
o
25
50
75
100
TA - Free-Air Temperature _·C
Figure 9
Figure 10
~1ExAs
INSTRUMENTS
POST OFFICE BOX ·655303 • DAUAS. TEXAS 75265
7-67
TPS5904, TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIfiERS
SOES016A- MAY 1995 - REVISED OCTOBER 1995
, TYPICAL CHARACTERISTICS
OFF-STATE INPUT
LIGHT-EMITTING-DIODE CURRENT
REFERENCE CURRENT
2.5
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
0.25
I
II(LED) = 10 mA
R3 = 10 kQ
<::!.
C
~
::s
GI
"8
2
I
1.5
.
0
is
-
-------
GI
c
I!!
ilII:
m
~
E
11;1
<
--:'
0.15
1:
::!.
Dli
:J
C
.5
c3
------
'S
I!! 0.1
Q. ~
o
0.5
0.2
c
!
I
.:
_~
I
VI(LED) = 37 V
0.05
I
}
o
-25
o
25
75
50
100
o
-50
o
-25
TA - Free-Air Temperature - °C
25
50
Figure 11
NORMALIZED CURRENT TRANSFER RATIO
RELATIVE TO VALUE AT TA = 25°C
vs
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
1.2
10000
VC=5V
VO(COMP) = VI(FB)
IA=5mA
f= .vCE=35 V
/
~ , 1000
~'"
/'
I
C
100
j
10
100
Figure 12
COLLECTOR DARK CURRENT
a~
75
TA - Free-Air Temperature - °C
L
~
/
8
I
"
/
5l
~
0.1
-50
-25
o
25
75
50
100
o
-50
Figure 13
o
25
Figure 14
~TEXAS
7-68
-25
50
TA - Free-Air Tempeniture - °C
TA - Free-Air Temperature - °C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
75
100
TPS5904,TPS5904A
OPTO-ISOLATED FEEDBACK AMPLIFIERS
SOES016A- MAY 1995 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
COLLECTOR-TO-EMITTER SATURATION VOLTAGE
vs
FREE-AIR TEMPERATURE
CURRENT TRANSFER RATIO
vs
INPUT LIGHT-EMITTING-DIODE CURRENT
300
I
I
VCE=5V
tJl.
V)
250
I
0
~
~c
~
~
\\
C
~:::I
u
t
i
~
/
150
I
....
/
200
>
I
100
i
!E
r\.
""
I
a::
t;
50
o
1
2
3
5
10
20
30
50
j
I
!u
:::;;
0.20
II(LED) = 10 mA
IC=1 mA
0.18
J
[7
0.16
0.14
V
V
/
/
./
0.12
0.10
.-/
V
V
/
0.08
o
-50-25
25
50
75
100
TA - Free-Air Temperature - °C
II(LED) - Input Light-Emltting-Dlode Current - mA
Figure 15
Figure 16
INPUT LlGHT-EMITTING-DIODE FORWARD CURRENT
VS,
LlGHT-EMITTING-DIODE FORWARD VOLTAGE
60~--~---T----~--~--~----'
40~--4----+----~--~--~~~
201-----l----+----!---I---H~_I+----I
0.9
1.1
1.3
1.4
VF - Llght-Emltting-Diode Forward Voltage - V
Figure 17
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7-69
7-70
8-1
Contents
LT1054
TL-SCSI285
TL2217-285
TL2218-285
. TLE2425
TLE2426
TPS28xx
TPS9103
OJ
_.
-_.
:::J
c
a.
(Q
-o
n
OJ
rI
m
:::J
a.
en
"C
_.
."
(1)
n
I»
C
...o_.
:::J
n
,:::J
tn
8-2
Switched-Capacitor Voltage Converters With Regulator
Fixed-Voltage .Regulators For SCSI Active Termination
Fixed-Voltage Regulators For SCSI Active Termination
Excalibur Current-Mode SCSI Terminator ...............
Precision Virtual Grounds ................................
The "Rail Splitter" Precision Virtual Ground ............
Dual High-Speed MOSFET Drivers .......................
Power Supply For GaAs Power Amplifiers ..............
Page
8-3
8-27
8-33
8-39
8-47
8-61
8-79
8-81
LT1054,LT1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
•
•
•
•
Output Current •.. 100 mA
Low Loss ••• 1.1 Vat 100 mA
Operating Range ••. 3.5 V to 15 V
Reference and Error Amplifier for
Regulation
PPACKAGE
(TOP VIEW)
F B / s o D 8 Vee
CAP+ 2
7 esc
GNO
CAP-
• External Shutdown
• External Oscillator Synchronization
6
5
VREF
VOUT
DWPACKAGE
(TOP VIEW)
• Devices Can Be Paralleled
• Pin Compatible With the LTC104417660
NC
NC
16
description
NC
The LT1 054 also provides regulation, a feature not
previously available in switched·capacitor voltage
converters. By adding an external resistive
divider, a regulated output can be obtained. This
output is regulated against changes in both input
voltage and output current. The LT1054 can also
be shut down by grounding the feedback terminal.
Supply current in shut-down is typically 100 JlA.
The internal oscillator of the LT1 054 runs at a
nominal frequency of 25 kHz. The oscillator
terminal can be used to adjust the switching
frequency or to externally synchronize the
LT1054.
PACKAGED DEVICES
CHIP
FORM
(V)
SMALL
OUTLINE
(OW)
PLASTIC
DIP
(P)
O°C to 70°C
LT1054CDW
LT1054CP
LT1054Y
-40°C to 85°C
LT105410W
LT10541P
-
Vee
esc
13
VREF
VOUT
NC
NC - No internal connection
VOLTAGE LOSS
vs
OUTPUT CURRENT
2
.1
I
I
J
3.5 V,;; VCC';; 15 V
1.8 I - CI=Co =100IlF
1.6
TJ=11~
1.4
1.2
I - - r- TJ = 25°C
1"-
0.8
0.6
0.4
AVAILABLE OPTIONS
15
14
FB/SO
The LT1 054 is a monolithic, bipolar, switched·
capacitor voltage converter with regulator. It
provides higher output current and significantly
lower voltage losses than previously available
converters. An adaptive switch drive scheme
optimizes efficiency over a wide range of output
currents. Total voltage drop at 100·mA output
current is typically 1.1 V. This holds true over the
full supply voltage range of 3.5 V to 15 V.
Quiescent current is typically 2.5 mA.
TA
3
4
0.2
l.......:: ~
~~V
"
o
o
10
20
V V
......
1/~ V
V V
K
./
~
,..,.
.........
/
..,
"
".......,.-
"-
TJ=-55°C
I J
30
40
50
60
70
80
90 100
Output Current - mA
The OW package is available taped and reeled. Add the suffix R to the
device type, (i.e., LT1054COWR).
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE sox 655303 • DALLAS. TEXAS 75265
8-3
-LT1054,TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
functional block diagram
Vcc
8
2.5 V
FBISD -'-.....-t---If---I
OSC-7~--~~--~~
3
GND
COUTt
5
VOUT
t External capacitors
NOTE A. Terminal numbers shown are for the P package only.
-!I1TEXAS
INSTRUMENTS
8-4
POST OFFICE BOX 655303 • OAUAS. TEXAS 75265
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
LT1054Y chip information
This chip, when properly assembled, displays characteristics similar to the LT1054. Thermal compression or
ultrasonic bonding may. be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
(8)
FBISD
CAP+
-=
-=
CAP-
(1)
(2)
(7)
LT1054Y
(4)
(6)
VCC
OSC
VREF
(5)
VOUT
(3)
-=
-=
-=
-=
GND
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%.
-=
ALL DIMENSIONS ARE IN MILS.
TERMINAL NUMBERS SHOWN
ARE FOR THE P PACKAGE ONLY
-=
-=
~
~
~
1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111I111
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-5
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (se~ Note 1) .......................................................... 16 V
Input voltage range, VI (FB/SO terminal) ................................................ OV to Vee
Input voltage range, VI (OSe terminal) ... ~.............................................. 0 V to Vref
Junction temperature (see Note 2) TJ: LT1054e ............................................ 125°e
LT10541 ............................................ 135°e
Operating free-air temperature range, TA: LT1054e ......... :.......................... ooe to 700 e
LT10541 .................................. -40oe to 85°e
Storage temperature range, Tstg ........... '...................... , . . . . . . . . . . . .. . .. -55°e to 1500 e
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds .......... : ........ _. .. . .. . . . .. 2600 e
t Stresses beyond those listed under "absolute maximum ratings' may Gause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other cond~ions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
,NOTES: 1. The absolute maximum supply voltage rating of 16 V is for unregulated circuits. For regulation mode circu~s w~ VOUT:;; 15 V, this
rating may be increased to 20 V.
2. The devices are functional up to the absolute maximum junction temperature.
recommended operating conditions
Supply voHage. VCC
I LT1054C
Operating free-air temperature range, TA
I m0541
MIN
MAX
3.5
15
0
70
-40
85
UNIT
V
°C
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
Vo
Vrei
LT1054C, LT10541
TEST CONDITIONS
TAt
Regulated output voltage
VCC=7V, TJ=25°C,
RL = 500 Q,
See Note 3
25°C
Input regulation
VCC=7Vto12V,
RL = 500 0.
See Note 3
Full range
Output regulation
VCC=7V,
See Note 3
RL = 100 n to 500 n,
VoHage loss, VCC -I VOl
(see Note 4)
CI = Co = 100 I1F tantalum
Output resistance
AIO = 10 mA to 100 mA
Oscillator frequency
VCC = 3.5 V to 15 V
Reference voltage
I(REF) = 60 I1A
Supply current
Supply current in
shut-down
10=0
-4.7
MAX
.:.5
-5.2
5
25
mV
mV
Full range
10
50
110=10mA
0.35
0.55
110= l00mA
Full range
1.1
1.6
See Note 5
V
V
10
15
n
15
25
35
kHz
25°C
2.35
2.5
2.65
Full range
2.25
Full range
Full range
2.75
V
mA
25°C
300
I VCC=3.5 V
Full range
2.5
3.5
IVcc=15V
Full range
3
4.5
Full range
100
150
V(FBlSO) = 0 v
UNIT
TY~
Fullrange
Maximum switch current
ICC
MIN
mA
I1A
tFull range isO°C to 70°C for the LT1054C and-40°C to 85°C for the LT10541.
:I: All typical values are at TA = 25°C.
NOTES: 3. All regulation speCifications are for a device connected as a posmve-to-negative converter/regulator w~ Rl = 20 kQ,
R2 = 102.5 ko, extemal capacitorCIN = 10 I1F (tantalum), extemalcapacitorCOUT= 100 I1F (tantalum) and Cl =0.002I1F (see Figure
15).
4. For voltage-loss tests, the device is connected as a voltage inverter, w~h terminals 1, 6, and 7 unconnected. The voltage losses may
be higher in other configurations. CIN and COUT are external capacitors.
5. Output resistance is defined as the slope of the curve (AVO versus AIO) for output currents of 10 mA to 100 mAo This represents the
linear portion of the curve. The incremental slope of the curve wiu be higher at currents less than 10 mA due to the characteristics
of the switch transistors.
~TEXAS
8-6
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
electrical characteristics over recommended operating conditions, TA = 25°C (unless otherwise
noted)
PARAMETER
Vo
Vref
LT1054Y
TEST CONDITIONS
MIN
UNIT
VCC = 7 V, TJ = 25°C,
RL=500n,
See Note 3
-5
Input regulation
VCC=7Vto12V,
RL= 500 n,
See Note 3
5
mV
Output regulation
VCC=7V,
See Note 3
RL=100nt0500n,
10
mV
Voltage loss, VCC -I Vol (see Note 4)
CI = Co = 100 IlF tantalum
Output resistance
~IO
Oscillator frequency
VCC=3.5Vto 15V
Reference voltage
Supply current
Supply current in shut-down
NOTES:
MAX
Regulated output voltage
= 10 mA to 100 mA
110=10mA
0.35
110=100mA
1.1
See Note 5
' I(REF) = 60 I!A
Maximum switch current
ICC
TYP
10=0
V
10
n
25
kHz
2.5
V
300
mA
I VCC =3.5 V
2.5
IVCC=15V
3
100
V(FB/SD) = 0 V
V
mA
I!A
3 All regulation specifications are for a device connected as a positive-to-negative converter/regulator with Rl = 20 kn, R2 = 102,5
kn, external capacitorCIN = 10 IlF (tantalum), external capacitorCOUT = 100 IlF (tantalum) and Cl = 0.0021lF (see Figure 15).
4 For voltage-loss tests, the device is connected as a voltage inverter, with terminals 1,6, and 7 unconnected. The voltage losses may
be higher in other configurations, CIN and COUT are extemal capacitors.
5 Output resistance is defined as the slope olthe curve (~VO versus ~IO) for output currents of 10 mA to 100 mAo This represents the
linear portion of the curve, The incremental slope of the curve will be higher at currents less than 10 mA due to the characteristics
of the switch transistors.
~TEXAS
INSTRUMENTS
POST OFFICE
eox 655303 •
DALLAS, TEXAS 75265
8-7
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
'WITH REGULATOR
SLVS033B - FEBRUARY 1990 '- REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Shutdown threshold voltage
vs Free-air temperature
1
ICC
Supply current
vs Input voltage
2
fOSC
Oscillator frequency
vs Free-air temperature
3
Supply current in shutdown
vs Input voltage
4
Average supply current
vs Output current
5
Output voltage loss
vs Input capacitance
6
Output voltage loss
vs Oscillator frequency (10 I!F)
7
8
Output voltage loss
vs Oscillator frequency (100 I!F)
Vo
Regulated output voltage
vs Free-air,temperature
9
.6.Vre f
Reference voltage change
vs Free-air temperature
10
Table of Figures
FIGURE
SWitched-Capacitor Building Block
Switched-Capacitor Equivalent Circuit
Circuit With Load Connected From VCC to VOUT
Extemal C,lock System
Basic Regulation Configuration
Power-Dissipation-Limiting Resistor in Series With CIN
Motor Speed Servo
Basic Voltage Inverter
Basic Voltage Inverter/Regulator
Negative Voltage Doubler
Positive Doubler
100-mA Regulating Negative Doubler
Dual Output Voltage Doubler
5-V to ±12-V Converter
Strain Gage Bridge Signal Conditioner
3.5-V to 5-V Regulator
Regulating 200-mA +12-V to -5-V Converter
Digitally Programmable Negative Supply
Positive Doubler With Regulation (5-V to 8-V Converter)
Negative Doubler With Regulator
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEl\AS 75265
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WitH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
SHUTDOWN THRESHOLD VOLTAGE
va
FREE-AIR TEMPERATURE
SUPPLY CURRENT
va
INPUT VOLTAGE
5
0.6
0.5
,
...........
...............
~
0.4
V(FBlSD)
I
10=0
CC
e
4
I
-....... ~
C
~
::I
3
-
0
a
0.3
r::L
::I
Ul
I
0.2
2
0
E
0.1
o
-50
-25
o
25
50
TA - Free-Air Temperature -
o
100
75
o
15
5
10
Vee - Input Voltage - V
°e
Figure 1
Figure 2
OSCILLATOR FREQUENCY
va
FREE-AIR TEMPERATURE
SUPPLY CURRENT IN SHUTDOWN
va
INPUT VOLTAGE
120
35
33
N
:r:
....
31
I
..
(;'
c
::I
29
l
27
l5
25
IL
.i
~
0
cc::1.
~
........
100
I
"
r--.....
i
Vee=15V
~
Vee=3.5V -.........
23
21
... ......
80
"....--
~i"""'
"""--V(FBlSD)
=0
.c
Ul
~
.5
-~
~
40
i~
20
c3
19
60
17
15
-50
-25
o
75
25
50
TA - Free-Air Temperature.;. °e
o
100
o
Figure 3
10
5
Vee - Input Voltage - V
15
Figure 4
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-9
L11 054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B,... FEBRUARY 1990 - REVISED AUGUST 19Q5
TYPICAL CHARACTERISTICS
AVERAGE SUPPLY CURRENT
OUTPUT VOLTAGE LOSS
vs
vs
OUTPUT CURRENT
INPUT CAPACITANCE
140
1.4
120
CC
I
C
~
100
-a
80
.
60
/
::I
(J
D.
::I
en
..~
~
40
V
L
>
,..
I
/V
.9
r
~
/
10';' 100 rnA
~
10=50mA
1.0
0.8
0.6
J
'$
~
0
20
I I I
Inverter Configuration
COUT = 100 ~F Tantalum
fOSC= 25 kHz
o
100
40
60
80
10 - Output Current - rnA
o
10
20
30 40 50 60 70 80
Input Capacitance - ~F
Figure 5
OUTPUT VOLTAGE LOSS
vs
vs
OSCILLATOR FREQUENCY
OSCILLATOR FREQUENCY
2.5
2.5
Inverter Configuration
CIN = 10 ~F Tantalum
COUT = 100 ~F Tantalum
I
1.75
VI
..
:Ill=
I
1\
1.5
.9
\
\
~
'$
D.
'$
0
0.75
0.5
1\
\, .....
.==
0
..J
,110=~00tt
r'\
\
1.25
:Ill
T
f'.....1j0=50mA
I I ,
\
1.5
1.25
~
~
0
1~=1ml
"'-
0.75
0.5
I _~ I I I
o
100
.........
-
10= 100 rnA
...... I"'"
I
,/
:~=50~A
a--
o
10
Oscillator Frequency - kHz
\
1\
'$
0.25
10 = 10 rnA
1
Figure 7
liT
~TEXAS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
10
Oscillator Frequency - kHz
Figure 8
INSTRUMENTS
8-10
~. I
1.75 ~
0.25
1
-.!
2
>
90 100
Figure 6
OUTPUT VOLTAGE LOSS
2.25
I
J.
10=10mA _
0.4
0.2
~
o
I'
VI
VI
./
20
o
V
/
~
1.2
/
E
100
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
REFERENCE VOLTAGE CHANGE
va
FREE-AIR TEMPERATURE
REGULATED OUTPUT VOLTAGE
va
FREE-AIR TEMPERATURE
-4.7
>
I
II
i
~
100
-4.8
-4.9
5
'S
.&
-5. 1
-
I
'-
-11.6
i
-11.8
i'
a::
I
60
!
f.-
40
t
i
:s
i
80
=e
~
...............
-1 2
~-12.2
--
-12.6
-50
~
-20
-40
I
f
V
./
V
i."
VREF at 0
=2.500 V
-80
'-100
-50
100
~
~
-60
~
-25
50
75
o
25
TA - Free-Air Temperature - °C
~
0
ila::
-12.4
~
20
-25
0
25
50
75
100
TA - Free-Air Temperature - °C
125
Figure 9
Figure 10
t Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.
PRINCIPLES OF OPERATION
A review of a basic switched-capacitor building block is helpful in understanding the operation of the LT1054.
When the switch shown in Figure 11 is in the left position, capacitor C1 charges to the voltage at V1. The total
charge on C1 is q1 = C1 V1. When the switch is moved to the right, C1 is discharged to the voltage at V2. After
this discharge time, the charge on C1 is:q2 =C1 V2. The charge has been transferred from the source V1 to the
output V2. The amount of charge transferred is as shown in equation 1.
~q
=q1 -
q2 =C1 (V1 - V2)
(1)
If the switch is cycled f times per second, the charge transfer per unit time (Le., current) is as shown in equation 2.
I =fx ~q
=f x C1 (V1 -
(2)
V2)
To obtain an equivalent resistance for a switched-capacitor network, this equation can be rewritten in terms of
voltage and impedance equivalence as shown in equation 3.
I
=
V1 - V2 _ V1 - V2
(1 /fC1) - REQUIV
(3)
V1~:UV2
1.
r--
C1
RL
r
C2
--
--
Figure 11. Switched-Capacitor Building Block
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS. TEXAS 75265
8-11
lT1054, TL1054Y
.
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
PRINCIPLES OF OPERATION
A new variable, REQUIV, is defined as REQUIV = 1 + fG1. The equivalentcircuitforthe switched-capacitor network
is as shown in Figure 12. The LT1054 has the same switching action as the basic switched-capacitor building
block. Even though this simplification does not include finite switch-on resistance and output-voltage ripple, it
provides an insight into how the device operates.
These simplified circuits explain voltage loss as a function of oscillator frequency (see Figure 7). As oscillator
frequency is decreased, the output impedance is eventually dominated by the 1/fG1 term and voltage losses
rise.
Voltage losses also rise as oscillator frequency increases. This is caused by internal switching losses that occur
due to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied
by the switching frequency, becomes a current loss. At high frequency, this loss becomes significant and voltage
losses again rise.
The oscillator of the LT1054 is designed to run in the frequency band where voltage losses are at a minimum.
Figure 12. Switched-Capacitor Equivalent Circuit
terminal functions (see functional block diagram)
Supply voltage Vee alternately charges GIN to the input voltage when GIN is switched in parallel with the input
supply and then transfers charge to GOUT when GIN is switched in parallel with GOUT. Switching occurs at the
oscillator frequency. During the time that GIN is charging, the peak supply current is approximately 2.2 times the
output current. During the time that GIN is delivering a charge to GOUT, the supply current drops to approximately
0.2 times the output current. An input supply bypass capacitor supplies part of the peak input current drawn by
the LT1054, and averages out the current drawn from the supply. A minimum input supply bypass capacitor of
21lF, preferably tantalum or some other low equivalent-series-resistance (ESR) type, is recommended. A larger
capacitor is desirable in some cases. An example is when the actual input supply is connected to the LT1054
through long leads or when the pulse currents drawn by the LT1054 might affect other Circuits through supply
coupling.
In addition to being the output terminal, VOUT is tied to the substrate of the device. Special care must be taken
in LT1054 circuitsto avoid making VOUT positive with respect to any of the other terminals. For circuits with the
output load connected from Vee to VOUT or from some external positive supply voltage to VOUT, an external
transistor must be added (see Figure 13). This transistor prevents VOUT from being pulled above GND during
start-up. Any small general-purpose transistor such as a 2N2222or a 2N2219 device can be used. Resistor R1
should be chosen to provide enough base drive to the external transistor so that it is saturated under nominal
output voltage and maximum output current conditions.
(4)
~TEXAS
INSTRUMENTS
8-12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
VIN
2
elN
+
3
-=-
4
FBISD
Vce
CAP+
ose
LT1054
GND
VREF
CAP-
VOUT
8
7
6
-=5
iT COUT
Figure 13. Circuit with Load Connected from Vee to VOUT
The voltage reference (Vref) output provides a 2.5-V reference point for use in LT1054-based regulator circuits.
The temperature coefficient (TC) of the reference voltage has been adjusted so that the TC of the regulated
output voltage is near zero. As seen in the typical performance curves, this requires the reference output to have
a positive TC. This non-zero drift is necessary to offset a drift term inherent in the internal reference divider and
comparator network tied to the feedback terminal. The overall result of these drift terms is a regulated output
that has a slight positive TC at output voltages below 5 V and a slight negative TC at output voltages above 5
V. For regulator feedback networks, reference output current should be limited to approximately 60 !lA. Vref
draws approximately 100 !lA when shorted to ground and does not affect the internal reference/regulator. This
terminal can also be used as a pullup for LT1054 circuits that require synchronization.
CAP+ is the positive side of input capacitor CIN and is alternately driven between Vee and ground. When driven
to Vee, CAP+ sources current from Vee. When driven to ground, CAP+ sinks current to ground. CAP- is the
negative side of the input capaCitor and is driven alternately between ground and VOUT' When driven to ground,
CAP-sinks current to ground. When driven to VOUT, CAP- sources current from COUTo In all cases, current flow
in the switches is unidirectional, as should be expected when using bipolar switches.
esc
can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock.
The
Internally,
is connected to the oscillator timing capaCitor (Ct "" 150 pF), which is alternately charged and
discharged by current sources of ±7 !lA, so that the duty cycle is approximately 50%. The LT1054 oscillator is
designed to run in the frequency band where switching losses are minimized. However, the frequency can be
raised, lowered, or synchronized to an external system clock if necessary.
esc
The frequency can be increased by adding an external capacitor (C2 in Figure 14) in the range of 5 pF - 20 pF
from CAP+ to
This capaCitor couples a charge into Ct at the switch transitions. This shortens the charge
and discharge time and raises the oscillator frequency. Synchronization can be accomplished by adding an
to Vref' A 20-ka pullup resistor is recommended. An open-collector gate or
external pullup resistor from
an NPN transistor can then be used to drive
at the external clock frequency as shown in Figure 14.
esc.
esc
esc
The frequency can be lowered by adding an external capaCitor (Cl in Figure 14) from
increases the charge and discharge times, which lowers the oscillator frequency.
esc to ground. This
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8--13
LT1 054,TL1 054V
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995 .
APPLICATION INFORMATION
r-------------------~
iI
I
FB/sD
VCC
CAP+
OSC
2
+
3
8
VIN
t
7
I
C2
I
LT1054
GND
4
'------I CAP-
VOUT
Figure 14. External Clock System
The feedback/shutdown (FB/SD) terminal has two functions. Pulling FB/SD below the shutdown threshold ( '"
0.45 V) puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops.
The switches are set such that both GIN and GOUT are discharged through the output load. Quiescent current
in shutdown drops to approximately 100 J.IA . Any open-collector gate can be used to put the LT1054 into
shutdown. For normal (unregulated) operation, the device will restart when the external gate is shut off. In
LT1 054 circuits that use the regulation feature, the external resistor divider can provide enough pulldown to keep
the device in shutdown until the output capacitor (GOUT) has fully discharged. For most applications where the
LT1 054 is run intermittently, this does not present a problem because the discharge time of the output capacitor
is short compared to the off time of the device. In applications where the device has to start-up before the output
capacitor (GOUT) has fully discharged, a restart pulse must be applied to FB/SD of the LT1054. Using the circuit
shown in Figure 15, the restart signal can be either a pulse (tp > 100 ~s) or a logic high. Diode coupling the restart
signal into FB/SD allows the output voltage to rise and regulate without overshoot. The resistor divider R3/R4
shown in Figure 15 should be chosen to provide a signal level at FB/SD of 0.7 V - 1.1 V.
FB/SD is also the inverting input of the LT1054 error amplifier and, as such, can be used to obtain a regulated
output voltage.
:IITEXAS .
INSTRUMENTS
8-14
pOST OFFICE BOX 655303 • DALLAS. TEXAS 75265
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
Jl
< R3
VIN
1
.... 1
R4
-=
~<
2
CIN ;;:
10l1F
Tantalum
-
estart
:::::r
+
3
4
~
1 It;}
8
FB/sD
Vcc
CAP +
7
OSC f---
LT1054
GND
VREF
CAP-
VOUT
+
6
R1
5
R2
VOUT~
I vOUTI
+).
VREF
- - -40mV
2
=20kn
(
I -5vl
If
C1
1\
~
(
-=
Shutdown
For example: To get Vo = -5 V
referred to the ground terminal of the LT1054
R2=R1
2'~I1F
+)
L.-
+T
= 102.6 kot
J.
COUT
100I1F
Tantalum
2.5V
- - -40mV
2
Where: R1 = 20 kn
VREF = 2.5 V Nominal
t Choose the closest 1% value
Figure 15. Basic Regulation Configuration
regulation
The error amplifier of the LT1054 drives the pnp switch to control the voltage across the input capacitor (CIN),
which determines the output voltage. When the reference and error amplifier of the LT1054 are used, an
external resistive divider is all that is needed to set the regulated output voltage. Figure 15 shows the basic
regulator configuration and the formula for calculating the appropriate resistor values. R1 should be 20 kQ or
greatet because the reference current is limited to ± 100 jJA. R2 should be in the range of 100 kQ to 300 kQ.
Frequency compensation is accomplished by adjusting the ratio of CIN to COUT.
For best results, this ratio should be approximately 1 to 10. Capacitor C1, required for good load regulation,
should be 0.002 I1F for all output voltages.
The functional block diagram shows that the maximum regulated output voltage is limited by the supply voltage.
For the basic configuration, I VOUT I referred to the ground terminal of the LT1054, must be less than the total
of the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due
to the switches can be found in the typical performance curves. Other configurations, such as the negative
doubler can provide higher voltages at reduced output currents.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-15
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B"': FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
capacitor selection
While the exact values of GIN and GOUT are non-critical, good-quality low-ESR capacitors, such as solid
tantalum are necessary to minimize voltage losses at high currents. For GIN, the effect of the ESR of the
capacitor is multiplied by four, since switch currents are approximately two times higher than output current.
Losses occur on both the charge and discharge cycle, which means that a capaCitor with 1 n of ESR for GIN
has the same effect as increasing the output impedance of the LT1054 by 4 n. This represents a significant
increase in the voltage losses. GOUT is alternately charged and discharged at a current approximately equal
to the output current. The ESR of the capacitor causes a step function to occur in the output ripple at the switch
transitions. This step function degrades the output regulation for changes in output load current and should be
avoided. A technique used to gain both low ESR and reasonable cost is to parallel a smaller tantalum capacitor
with a large aluminum electrolytic capacitor.
output ripple
The peak-to-peak output ripple is determined by the output capacitor and the output current values.
Peak-to-peak output ripple is approximated as shown:
I'!V =
I
OUT
2 fG OUT .
(5)
where:
I'!V = pop ripple
fose = oscillator frequency
For output capacitors with significant ESR, a second term must be added to account for the voltage step at the
switch transitions. This step is approximately equal to:
(6)
power dissipation
The power dissipation of any LT1 054 circuit must be limited so that the junction temperature of the device does
not exceed the maximum junction temperature ratings. The total power dissipation is calculated from two
components, the power loss due to voltage drops in the switches, and the power loss due to drive current losses.
The total power dissipated by the LT1054 is calculated as shown.
P ... (V GG -
I V OUT I ) lOUT
+
(V GG) (lOUT) (0.2)
(7)
where both Vee and VOUT are referenced to ground. The power dissipation is equivalent to that of a linear
regulator. Limited power handling capability of the LT1 054 packages causes limited output current requirements
or steps can be taken to dissipate power external to the LT1 054 for large input or output differentials. This is
accomplished by placing a resistor in series With GIN as shown in Figure 16. A portion of the input voltage is
dropped across this resistor without affecting the output regulation. Since switch current is approximately 2.2
times the output current and the resistor causes a voltage drop when GIN is both charging and discharging, the
resistor chosen is as shown:
where:
Vx ... V GG - [(LT1054 voltage loss) (1.3)
.and lOUT
+
I VOUT I]
=maximum required output current. The factor of 1.3 allows some operating margin for the LT1054.
~TEXAS
8-16
(8)
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
LT1054, TL1054Y
SWITCHED·CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
When using a 12-V to -5-V converter at 100-mA output current, calculate the power dissipation without an
external resistor.
P
P
= (12 V - 1-5 V I )(100 mA) + (12
= 700mW + 240 mW = 940 mW
Rx 2
V) (100 mA) (0.2)
FB/SD
VCC
CAP+
OSC
8
7
LTt054
CrN
+
3
-=-
4
GND
VREF
CAP-
VOUT
6
R1
5
R2
T
VOUT
C1
Figure 16. Power-Dissipation-Limiting Resistor in Series with elN
At RaJA of 130°C/W for a commercial plastic device, a junction temperature rise of 122°C is seen. The device
exceeds the maximum junction temperature at an ambient temperature of 25°C. To calculate the power
dissipation with an external-resistor (Rx), determine how much voltage can be dropped across Rx. The
maximum voltage loss of the LT1054 in the standard regulator configuration at 100 mA output current is 1.6 V.
and
Vx
Rx
=
=
12 V - [(1.6 V) (1.3)
4.9 V/(4.4) (100 mA)
+ 1-5 VI] =
= 11 g
4.9 V
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-17
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
1;he resistor reduces the power dissipated by the LT1054 by (4.9 V) (100 mA) == 490 mW. The total power
dissipated by the LT1054 is equal to (940 mW - 490 mW) 450 mW. The junction temperature rise is 5aoC.
Although commercial devices are functional up to a junction temperature of 125°C, the specifications are tested
to a junction temperature of 100°C. In this example, this means limiting tl:!e ambient temperature to 42°C. To
allow higher ambient temperatures, the thermal resistance numbers for. the LT1054 packages represent
worst-case numbers with no heat-sinking and still air. Small clip-on heat sinks can be used to lower the thermal
resistance of the LT1054 package. Airflow in some systems helps to lower the thermal resistance. Wide PC
board traces from the LT1054 leads help to remov~ heat from the device. This is especially true for plastic
packages.
=
10V
1 N4002
100 kn
VCC
FB/sD
2
OSC
CAP +
3
10llF
-=
Tach
4
LT1054
8
+
7
511FT
6
GND
VREF
CAP-
VOUT
5
Motor
NOTE: Motor-Tach Canon CKT26-T5-3SAE
. Figure 17. Motor Speed Servo
1 - _.....__ -VOUT
100llF
~TEXAS
8-18
INSTRUMENTS
POST OFFICE BOX 655303 • DAllAS. TEXAS 75265
100kQ
Speed Control
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST. 1995
APPLICATION INFORMATION
VIN
-
1
2
+
10 ~F ;;:~
r
VCC
CAP+
OSC
-
LT1054
3
1
8
FB/SO
GNO
f 2~F
7
6
R1
5
R2
20kQ
VREF
-
4
CAP-
VOUT
VOUT - - l
+1/
+1/
~O~F
1\
1\
R2= R1
(IVOO,I .)
o:20kQ
VREF
- - -40mV
2
0.002 ~F
(
I vOUTI
1.21 V
-)
Figure 19. Basic Voltage Inverter/Regulator
8
FB/SO
VCC
CAP+
OSC
2
10 ~F +
7
LT1054
3
GNO
1
vo",
6
VREF
4
CAP-
-=-
Qx
5
VOUT
RX
VIN = -3.5 V TO -15 V
VOUT = 2 VIN + (LT1054 Voltage Loss) + (QX Saturation Voltage)
Figure 20. Negative Voltage Doubler
~TEXAS
.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-19
LT1054, TL 1054V
SWITCHEO:'CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVI!lj:D AUGUST 1995
APPLICATION INfORMATION
VIN
3.5 Vto 15 V
1N4001
1N4001
+
+
10 r.tF
VOUT
-=-
2
3
-
VIN =3.5 VTO 15 V
VOUT = 2 VIN - (VL + 2 V Diode)
VL = LT1054 Voltage Loss
4
8
FB/sD
VCC
CAP +
OSC
LT1054
T
+
6
GND
VREF
CAP-
VOUT
5
-=-
Figure 21. Positive Doubler
~TEXAS
8-20
7
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
2r.tF
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
VIN
3.5 Vto 15 V
FBISD
2
+ 10J.lF
10 J.lF
3
+
"::"
4
VCC
CAP+
OSC
LT1054 #1
GND
1,
8
7
VOUT
SET
6
2
+
10 J.lF
3
VREF
"::" 4
5
FBISD
VCC
CAP+
OSC
LT1054 #2
GND
VREF
CAP-
VOUT
1N4002
8
HP5082-2810
CAP+of
LT1054 #1
20kn
5
+J 10J.lF
__---------.-----------.----~~~---- VOUT
lOUT 100 mA MAX
1N4002
=
VIN = 3.5 to 15 V
VOUT MAX = -2 VIN + [LT1054 Voltage Loss +2 (VDiode»
R2=R1
1.21 V
Figure 22. 100-mA Regulating Negative Doubler
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-21
LT1054, TL1054Y
.
SWITCHED-CAPACITOa VOLTAGE CONVERTERS
WITH REG.ULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
VI
3.5 Vto 15 V
1N4001
1N4001
8
FB/SO
VCC
CAP+
OSC
2
3
LT1054
GNO
7
6
VREF
lOOI1F
-:::-
4
5
CAP-
VOUT
1N4001
~-=
1N4001
VI = 3.5 V to 15 V
+Vo ~ 2 VIN - (VL + 2 VOiode)-VO =-2 VI+ (VL + 2 VOlode)
VL = LT1054 Voltage Loss
1N4001
Figure 23. Dual Output Voltage Doubler
VI=5V
5 11F
T
+
-:::-
1N914
1N914
VO~+1.2V
FBISO
2
3
+
CAP +
lo=25mA
8
VCC
OSC
LT1054 #1
GNO
VREF
CAP-
VOUT
T
+
100l1F
7
+
6
2
5
3
-:::-
4
4
-::-
8
FB/SO
VCC
CAP+
OSC
LT1054 #2
GNO
CAP-
7
6
VREF
20kll
5
VOUT
-::-
100I1F
Figure 24. 5-V to ±12-V Converter
~TEXAS
8-22
.
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265.
VO~-12V
IO=25mA
"E
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
SV
10k.Q
InpUt TTL or
CMOS Low
for On
+
T
400
2N2907
~~JVI/I...--I
10kO
ZeroTrim
10 k.Q
-=Gain
Trim
Sk.Q
301k.Q
O.022IlF
10llF
VOUT
200kO
FBISD
VCC
2
,-------1 CAP+
OSC
8
SV
7
3k.Q
+
3
4
LT10S4#1
GND
' - - - - - - I CAP-
VREF
6
n-:;-
2N2222
Tantalum
S
VOUT . -_
_-+_____- - - l
Adjust Gain Trim
For3VOut
From Full-Scale Bridge
Output of 24 mV
Figure 25. Strain Gage Bridge Signal Conditioner
~TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-23
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
VI
3.5Vto5.5V
-
20kn
1
2
a...J
11"'"1
111F
~~ 1N914
-' (ALL)
~~
2
-=10l1F ;;:
1
-
+
3
r::.r-
8
FB/SD
VCC
CAP+
OSC
LT1054
-
VREF
CAP-
VOUT
- 4
7
=
~.~ (~~mv
4
r--
CAP +
OSC
-
7
-
6
LTC1044
GND
VREF
CAP-
VOUT -
O.OO2I1f::::
r::
'} '"'1<
+
R2 -::: F::: 100I1F
125 kn .-
3kn
-~ r
,
~ ..,.
~
-=-
')
5
R1
20kn
.R' (
IVOUTI
1.21 V
Figure 26. 3.5-V to 5-V Regulator
~TEXAS
8--24
r-
Vee
R2
125kn
5 11F f
-5
1N5817
3
-
6
GND
VI 3.5 Vto 5.5 V
VO=5V
loMAX=50mA
!: r::
8
FB/SD
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
1N914
Vo
-=-
+
LT1054, TL 1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
12V
511F
1
p:+
~
2
10(1
112W
3
,r+ II 4
1\
FB/sD
VCC
CAP+
OSC
-
LT1054 #1
GND
8
1
7
10(1
112W 2
6
VOUT -
R1
;;:
0.00211F
i='
1011F
39.2kn
+
R2
200kn
r
3
4
~~
HP5082-2810
OSC
LT1054 #2
+
:::: f:::
5
8
VCC f-----
7
CAP +
VREF
CAP-
FB/SO
6
GND
VREF
CAP-
5
VOUTil
20~~
1011F
VO=-5V
Io=0-200mA
.... t...-
2OO11FT+
IVOUTI
R2= R1
1.21 v
Figure 27. Regulating 200-mA + 12-V to -S-V Converter
15V
11
16
20kn
2
8
FB/SD
VCC
CAP+
OSC
LT1054
-=-
4
GND
VREF
CAP-
VOUT
7
6
5
,..{
}
Digital
Input
LT1004-2.5
13
12
20kn
-=Vo = - vI (Programmed)
Figure 28. Digitally Programmable Negative Supply
~TEXAS
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS, TEXAS 75265
8-25
LT1054, TL1054Y
SWITCHED-CAPACITOR VOLTAGE CONVERTERS
WITH REGULATOR
SLVS033B - FEBRUARY 1990 - REVISED AUGUST 1995
APPLICATION INFORMATION
VI=5V
50kO
2
V08V
+
T
100llF
10kO
0.031lF 10 kO
4
5V
5.5kQ
VCC
CAP+
OSC
LT1054
3
-=-
-=-
8
FB/SD
GND
VREF
CAP-
VOUT
7
6
5
10kO
-=-
2.SkO
0.1
11FT
Figure 29. Positive Doubler with Regulation (S-V to a-v Converter)
VI
3.5 Vto 15 v
1
2
;:::~
r
-
3
8
FB/sD
Vcc
CAP+
OSC r - LT1054
GND
VREF
CAP-
VOUT
1 +:~
21lF
7
-=-
6
R1
60kO
~O.
100ilF
4
5
;::F
\~ '.
II
-=-
~
R2
1 MQ/.
1N4001 ~ ~
I....
....
VI=3.5Vto15V
Vo MAX ~ 2 VIN + (VL + 2 V·
DIode)
VL = LT1054 Voltage Loss
.R2=R1
(
I vOUTI
V~EF
1N4001
+~
-40mV )
= R1 . (
I vOUTI
1.21 V
1
+~
)
Figure 30. Negative Doubler with Regulator
~TEXAS
8-26
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
-VO
TL-SCSI285, TL-SCSI285Y
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991 - REVISED AUGUST 1995
NPACKAGE
(TOP VIEW)
• Fully Matches Parameters for Alternative 2
SCSI Active Termination
• Fixed 2.85-V Output
• ± 1% Maximum Output Tolerance at
TJ = 25°C
• O.7-V Maximum Dropout Voltage
•
•
•
•
•
NC
NC
NC
OUTPUT
GND
GND
GND
INPUT
GND
620-mA Output Current
±2% Absolute Output Variation
Internal Overcurrent Limiting Circuitry
Internal Thermal Overload Protection
Internal Overvoltage Protection
PWPACKAGE
(TOP VIEW)
NC
NC - No internal connection
description
~I~{
}~~:
GND
INPUT
GND
OUTPUT
~~:
{-......._ _..r
>~:
HEAT SINK - These terminals have
an internal resistive connection to
ground and should be grounded or
electrically isolated.
The TL-SCSI285 is a low-dropout (O.7-V)
fixed-voltage regulator specifically designed for
small computer systems interface (SCSI)
alternative 2 active signal termination. The
TL-SCSI285 O.7-V maximum dropout ensures
compatibility with existing SCSI systems while
providing a wide TERMPWR voltage range. At the
same time the ±1% initial tolerance on its 2.85-V
output voltage ensures a tighter line driver current
tolerance, thereby increasing system noise
margin.
KCPACKAGE
(TOP VIEW)
The fixed 2.85-V output voltage of the TL-SCSI285 supports the SCSI alternative 2 termination standard while
reducing system power consumption. The O.7-V maximum dropout voltage brings increased TERMPWR
typical application schematic
Connector
TERMPWR
!;:::::T:~:S:C:SI:285::::~----------------~11~0~Q~------
5-V
Logic -~-..
1%
DB(O)
Supply
DB(1)
I
I
0.11!F
Ceramic
ATN
BSY
ACK
RST
MSG
SEL
c/D
REQ
221!F
Tantalum
VO
AVAILABLE OPTIONS
I
PACKAGED DEVICES
TJ
PLASTIC POWER
(KC)
QoCto 125°C
TL-SCSI285KC
I
PLASTIC DIP
(N)
TL-SCSI285N
JI
SURFACE MOUNT
(PW)t
CHIP
FORM
(Y)
TL-SCSI285PWLE
TL-SCSI285Y
t The PW package is only available left-end taped and reeled.
~:=..cn':'~:1! ~==~"u.rr;m"':':1g=.:
aIIndard warranty. Production _Ing does not .......rily Include
testing 01 all parameters.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
8-27
TL·SCSI285, TL·SCSI285Y
FIXED·VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991 - REVISED AUGUST 1995
description (continued)
isolation, making the device ideal for battery-powered systems. The TL-SCSI285, with internal current limiting,
overvoltage protection, ESO protection, and thermal protection offers designers enhanced system protection
and reliability.
When configured as a SCSI active terminator, the TL-SCSI285 low-dropout regulator eliminates the 220-0 and
the 330-0 resistors required for each transmission line with a passive termination scheme, reducing significantly
the continuous system power drain. When placed in series with 110-0 resistors, the device matches the
impedance level of the transmission cable and eliminates reflections.
The TL-SCSI285 is characterized for operation from O°C to 125°C virtual junction temperature.
TL-SCSt285Y chip information
This chip, when properly assembled, displays characteristics similar to the TL-SCSI285. Thermal compression
or ultrasonic bonding can be used on the doped aluminum pads. The chips can be mounted with conductive
epoxy or a gold-silicon preform.
INPUT(1) ......-
BONDING PAD ASSIGNMENTS
.....--------1~-----.
OUTPUT
(4,5)*
Bandgap
GND(2,3)t
t Connect pads 2 and 3 together.
t Connect pads 4 and 5 together.
CHIP THICKNESS: 11 MILS TYPICAL
BONDING PADS: 7X7 MILS MINIMUM
TJmax=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~
~
~
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'
~TEXAS
INSTRUMENTS
,8-28
POST OFFICE BOX 655303 • DALLAS; TEXAS 75265
TL-SCSI285, TL-SCSI285Y
. FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991 - REVISED AUGUST 1995
absolute maximum ratings over operating virtual junction temperature range (unless otherwise
noted)t
Continuous input voltage, VI ................................................................ 7.5 V
Continuous total dissipation (see Note 1) ................................ See Dissipation Rating Table
Operating virtual junction temperature range, TA .................................... -55°C to 150°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1 /16 inch) from case for 60 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Refer to Figures 1 and 2 to avoid exceeding the design maximum virtual junction temperature; these ratings should not be exceeded.
Due to variation in individual device electrical characteristics and thermal resistance, the built-in thermal overload protection may be
activated at power levels slightly above or below the rated dissipation.
DISSIPATION RATING TABLE
t
PACKAGE
POWER RATING
AT
T,,;25°C
POWER RATING
DERATING FACTOR
ABOVE T = 25°C
T= 70°C
POWER RATING
T=85°C
POWER RATING
T = 125°C
POWER RATING
KC
TA
TC
2000mW
20000mW
16.0mW/oC
182.0 mW/oCt
1280mW
11810mW
1040mW
9080mW
400mW
1800mW
N
TA
TC
2250mW
11850mW
18.0mW/oC
94.8mW/oC
1440mW
7584mW
1170mW
6162mW
450mW
2370mW
PW
TA
TC
950mW
4625mW
7.6mW/oC
37.0mW/oC
608mW
2960mW
494mW
2405mW
190mW
925mW
Derate above 40°C
MAXIMUM CONTINUOUS DISSIPATION
vs
CASE TEMPERATURE
MAXIMUM CONTINUOUS DISSIPATION
vs
FREE-AIR TEMPERATURE
25~----~-----r----~------~----,
2400
~
2200
I
2000
E
c
.S!
'&i
1800
II-
'iii
III
1600
is 1400
III
,.
,.0c
i0
C..)
,.
E
E
.
'j(
:::;;
I
Q
II-
~
"'-
I
""
5
,",,- I"~
~
""
1200
1000
.............
800
600
:---........
,.
~
75
C..)
~
~
...............
100
15~----+---~~----
,.oc
i
~,
o
50
is
N
RaJA = 55.6°CIW
f'.....'(
PW
400 tRaJA = 132°CIW1-"'"'""'
200
25
'i
III
f\...
20~--~+-----+-----r-----r---~
I
KC
RaJA = 62.5°CIW
KC
RaJC = 5.5°CIW
10~--~~--r--T----~r-----+-----1
,.
E
E
"~
125
~
5~~--~-----+--~~b---~~----1
I
Q
II-
150
TA - Free-Air Temperature - °C
O~----~----~----~----L-~=100
125
150
25
50
75
TC - Case Temperature - °C
Figure 1
Figure 2
~TEXAS
INSTRUMENTS
POST OFFiCE BOX 655303 • DALLAS. TEXAS 75265
8-29
TL-SCSI285, TL-SCSI285Y
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991- REVISED AUGUST 1995
recommended operating conditions
MIN
MAX
3.55
5.5
I KC and N packages
0
620
I PW package·
0
500
0
125
Input voltage. VI
Output current. 10
Oparatlng virtual junction temperature range. TJ
UNIT
V
rnA
°C
electrical characteristics, VI = 4.5 V, 10= 500 mA, TJ = 25°C (unless otherwise noted)
PARAMETER
Output voltage
Bias current
2.85
2.88
TJ=25°C
2.82
VI = 3.65 V to 5.5 V.
TJ =0 to 125°C
2.79
VI = 3.55 Vto 5.5 V
Dropout voltage
MAX
VI = 3.55 V to 5.5 V.
1= 120Hz.
Output noise voltage
TYP
10 = 500 rnA to 620 rnA.
Ripple rejection
UNIT
MIN
10 = 20 rnA to 500 rnA.
Input regulation
Output regulation
TL-SCSI285KC
TL-SCSI285N
TEST CONDITIONSt
2.91
15
5
-62
Vripple = 1 VPP
mV
dB
10 = 20 rnA to 620 rnA
5
30
10 = 20 rnA to SOO rnA
5
30
1=10Hztol00kHz
V
500
mV
I1V
10 = 500 rnA
0.7
10=620mA
0.8
10=0
2
10 = 27 rnA. equivalent 1 line asserted
3
6
10 = SOO rnA. equivalent 18 lines asserted (8 bit)
26
49
10 = 620 rnA
37
62
V
5
rnA
t Pulse-testing techniques are used to mamtaln the virtual Junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a O.l-I1F capacitor across the input and a 22.0-I1F tantalum capacitor
with equivalent series resistance 01 1.5 Q on the output.
electrical characteristics, VI = 4.5 V, 10 = 500 mA, TJ = 25°C (unless otherwise noted)
TL-SCSI285PW
PARAMETER
Output voltage
TEST CONDITIONSt
10 = 20 rnA to 500 rnA. ,VI = 3.55 V to 5.5 V
Input regulation
V, = 3.55 V to 5.5 V
Ripple rejection
1= 120 Hz.
Output regulation
10 = 20 rnA to 500 rnA
Output noise voltage
1= 10 Hz to 100 kHz
Dropout voltage
10=500 rnA
Bias current
MIN
TYP
MAX
ITJ=25°C
2.82
2.85
2.88
ITJ=Oto125°C
2.79
2.91
5
Vripple = 1 VPP
mV
30
mV
0.7
I1V
V
dB
500
10=0
2
10 = 27 rnA. equivalent 1 line asserted
3
6
~6
49
10 = SOO rnA. equivalent 18 lines asserted (8 bit)
V
15
-62
5
UNIT
5
rnA
t Pulse-testing techniques are used to maintain the virtual junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a O.l-I1F capacitor across the Input and a 22.0-I1F tantalum capacitor
with equivalent series resistance 01 1.5 Q on the output.
~.1ExAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS75265
TL-SCSI285, TL-SCSI285Y
FIXED-VOLTAGE REGULATORS FOR
,SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991 - REVISED AUGUST 1995
electrical characteristics, VI = 4.5 V, 10 = 500 rnA, T J = 25°C
TL·SCSI285Y
PARAMETER
TEST CONDITIONSt
Output voltage
10 = 20 rnA to 500 rnA, VI = 3.55 V to 5,5 V
Input regulation
VI = 3.55 V to 5.5 V
Ripple rejection
f=120Hz,
Output regulation
Output noise voltage
Vripple = 1 Vpp
t
TYP
2.85
UNIT
V
mV
-62
dB
5
10 =20 rnA to 500 rnA
5
f=10Hztol00kHz
MAX
5
10 =20 rnA to 620 rnA
500
mV
I!V
2
10=0
Bias current
MIN
10 = 27 rnA, equivalent 1 line asserted
3
10 = 500 rnA, equivalent 18 lines asserted (8 bit)
26
10 =620 rnA
37
rnA
Pulse-testing techniques are used to maintain the virtual Junction temperature as close to the ambient temperature as pOSSible. Thermal effects
must be taken into account separately. All characteristics are measured with a O.l-I!F capacitor across the input and a 22.0-I!F tantalum capacitor
with equivalent series resistance of 1.5 Q on the output.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • OALLAS, TEXAS 75265
8-31
TL-SCSI285, TL-SCSI285V
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS065C - NOVEMBER 1991 - REVISEpAUGUST 1995
COMPENSATION CAPACITOR SELECTION INFORMATION
The TL-SCSI285 is a low,dropout regulator. This means that the capacitance loading is important to the
performance of the regulator because it is a vital part of the control loop. The capacitor value and the equivalent
series resistance (ESR) both affect the control loop and must be defined for the load range and the temperature
range. Figures 3 and 4 can establish the capacitance value and ESR range for best regulator performance.
ESR OF· OUTPUT CAPACITOR
VB
LOAD CURRENT
STABILITY
VB
ESR
0.04
c:
0.035
I
II
0.03
0.025
1.1
IM
0.02
0.015
0.01
I
m
0.005
0
0.1
0.2
0.4
0.3
Il - load Current - A
0.5
0.5
Load
Voltage
"["I
.~~
Figure 3
~TEXAS
8-32
1.5
2
2.5 3
llESR
Figure 4
all
Applied load
Current
1
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
3.5
4
4.5
5
TL2217-285, TL2217-285Y
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS066C-
NPACKAGE
(TOP VIEW)
• Fully Matches Parameters for Alternative
2 SCSI Active Termination
• Fixed 2.S5-V Output
• ±1.S% Maximum Output Tolerance
atTJ=2So
•
•
•
•
1-V Maximum Dropout Voltage
SOO-mA Output Current
± 3% Absolute Output Variation
Internal Overcurtent Limiting
1991-
PWPACKAGE
(TOP VIEW)
NC
NC
NC
OUTPUT
GND
GND
GND
GND
. GND
INPUT
INPUT
8
/
lHm
1
SINK
GND
• Internal Thermal Overload Protection
• Internal Overvoltage Protection
H~T{
NC
H~T{
SINK
GND
OUTPUT
6
lH~T
SINK
SINK
NC - No internal connection
description
HEAT SINK - These pins have an
internal resistive connection to
ground and should be grounded or
electrically isolated.
The TL2217-285 is a low-dropout (1-V) fixed-voltage regulator specifically designed for small
computer systems interface (SCSI) alternative 2
active signal termination. The TL2217-285 1-V
maximum dropout ensures compatibility with
existing SCSI systems, while providing a wide
TERMPWR voltage range. At the same time, the
± 1.5% initial tolerance on its 2.85-V output voltage
ensures a tighter line driver current tolerance,
thereby increasing system noise margin.
KCPACKAGE
(TOP VIEW)
typical application schematic
TERMPWR
Logic -
Connector
,--------------------------------------110n
S-V
....-
..
1%
OB(O)
OB(1)
Supply
ATN
BSV
ACK
RST
MSG
SEL
C/O
Vo =2.85 V
I
I
0.111F
Cerarnlc
2211F
Tantallurn
REQ
110
AVAILABLE OPTIONS
PACKAGE
TA
PLASTIC
POWER
(KC)
PLASTIC
DIP
(N)
SURFACE
MOUNT
(PW)t
QoCto 125°C
TL2217-285KC
TL2217-285N
TL2217-285PWLE
CHIP
FORM
(V)
TL2217-285Y
t The PW package is only available left-end taped and reeled.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright © 1995, Texas Instruments Incorporated
TL2217-285, TL2217-285Y
FIXED~VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS066C - NOVEMBER 1991 - REVISED AUGUST 1995
description (continued)
The fixed 2.85-V output voltage of TL2217-285 supports the SCSI alternative 2 termination standard while
reducing system power consumption .. The 1-V maximum dropout voltage brings increased TERMPWR
isolation, making the device ideal for battery-powered systems. The TL2217-285, with internal current limiting,
overvoltage protection, ESO protection, and thermal protection, offers designers enhanced system protection
and reliability.
•
When configured as a SCSI active terminator, the TL2217-265 low-dropout regulator eliminates the 220-0 and
330-0 resistors required for each transmission line with a passive termination scheme, reducing significantly
the continuous system power drain. When placed in series with 110-0 resistors, the device matches the
impedance level of the transmission cable and eliminates reflections.
The TL2217-285 is characterized for operation from O°C to 125°C virtual junction temperature.
TL2217-285Y chip information
These chips, properly assembled, display characteristics similar to the TL2217-285. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
INPUT (1)
BONDING PAD ASSIGNMENTS
~--~----------~--------,
OUTPUT
(4,5>*
Bandgap
GND(2,3)t
CHIP THICKNESS:
11 MILS TYPICAL
BONDING PADS:
7X7 MILS MINIMUM
TJ max
=150°C
TOLERANCES
ARE±10%.
ALL DIMENSIONS
ARE IN MILS.
104
92
~
t Must connect pads 2 an9 3 together
:j: Must connect pads 4 and 5 together
1'1'1'1'1'1'1"""'1'1"""'1""""'1'1'
~TEXAS·
INSTRUMENTS
&-34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL2217-285, TL2217-285Y
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS066C - NOVEMBER 1991 - REVISED AUGUST 1995
absolute maximum ratings over operating virtual junction temperature range (unless otherwise
noted}t
Continuous input voltage, VI ................................................................ 7.5 V
Continuous total power dissipation (see Note 1) .......................... See Dissipation Rating Table
Operating virtual junction temperature range, TJ .................................... -55°C to 150°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ............................... 260°C
t
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Refer to Figures 1 and 2 to avoid exceeding the design maximum virtual junction temperature; these ratings should not be exceeded.
Due to variation in individual device electrical characteristics and thermal resistance. the built-in thermal overload protection may be
activated at power levels slightly above or below the rated dissipation.
DISSIPATION RATING TABLE
PACKAGE
POWER RATING
AT
POWER RATING
Ke
TA
Tet
2000mW
20000mW
TA
Te
TA
Te
2250mW
11850mW
N
PW
t Derate above 40
0
TA~25°C
=
TA 85°C
POWER RATING
TA 125°C
POWER RATING
16.0mW/oe
182.0mW/oe
18.0mW/oe
94.8mW/oe
7.6mW/oe
37.0mW/oe
1280mW
14540mW
1040mW
11810mW
400mW
4530mW
1440mW
7584mW
608mW
2960mW
1170 mW
6162mW
494mW
2405mW
450mW
2370mW
190mW
925mW
950mW
4625mW
e
CASE TEMPERATURE
DISSIPATION DERATING CURVE
25.-----,-----,------,-----,-----,
2400
~
~
I
E
c
0
I
c
ia.
'ii
is
!a.
.
.
20r---~+-----1------r-----r----~
'ii
is..
15~----+-~~+----
:::I
N
RaJA
:::I
0
=55.6°CIW
:::I
C
0
KC
ROJC
=5.5°CIW
:::I
C
~
0
i0
(,)
600
E
E
.
400
:;
I
200
II..
(J
:::I
'=
5~=----r-----+--~~~--~rr-----~
I
c
C
II..
=
TA 70°C
POWER RATING
=
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
E
:::I
E
;c
:;
=
DERATING FACTOR
ABOVE TA 25°C
o~----~----~----~----~--=-
0
25
50
75
100
125
150
25
TA - Free-Air Temperature - °C
Figure 1
50
75
100
125
TC - Case Temperature - °C
150
Figure 2
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-35
TL2217-285, TL2217-285V
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS066C - NOVEMBER 1991 - REVISED AUGUST 1995
recommeneded operating conditions
MIN
MAX
3.85
5.5
V
Output current, 10
0
500
rnA
Operating virtual junction temperature range, TJ
0
125
·C
Input voltage, V,
UNIT
electrical characteristics over recommended operating conditions, VI = 4.S V, 10 = SOO mA, TJ = 2Soc
(unless otherwise noted)
TL2217-285
PARAMETER
Output voltage
TEST CONDITIONSt
V, = 3.85 V to 5.5 V
10 = 20 rnA to 500 rnA,
Input voltage regulation
V, = 3.85 V to 5.5 V
Ripple rejection
1= 120Hz,
Output voltage regulation
10 = 20 rnA to 500 rnA
Output noise voltage
1= 10 liz to 100 kHz
ITJ=25·C
I TJ = O·C to 125·C
MIN
TYP
2.81
2.85
MAX
2.89
2.935
2.765
5
30
mV
500
IN
1
Dropout voltage
Bias current
mV
dB
5
2
10=0
10 = 27 rnA, equivalent 1 line asserted
10 = 500 rnA, equivalent 18 lines asserted (8 bit)
V
15
-62
Vrioole = 1 VPP
UNIT
V
5
3
6
26
49
rnA
t Pulse-testing techniques are used to maintain the virtual junction temperature as close to the ambient temperature as possible. Thermal effects
must be taken into account separately. All characteristics are measured with a O.l-!lF capaCitor across the input and a 22-!lF tantalum capacitor
with equivalent series resistance 01 1.5 n on the output.
electrical characteristics over recommended operating conditions, VI = 4.S V, 10 = SOO mA, TJ= 2Soc
(unless otherwise noted)
TL2217-285Y
PARAMETER
TEST CONDITIONSt
Output voltage
10 = 20 rnA to 500 rnA,
Input voltage regulation
V, = 3.85 V to 5.5 V
Ripple rejection
1= 120Hz,
Output voltage regulation
10 = 20 rnA to 500 rnA
Output noise voltage
1=10Hztol00kHz
Dropout voltage
10=500 rnA
Bias current
V, = 3.85 V to 5.5 V
Vripple = 1 VPP
TYP
MAX
2.81
2.,85
2,89
5
15
mV
30
mV
1
!IV
V
-62
5
V
dB
500
10=0
2
10 = 27 rnA, equivalent 1 line asserted
3
6
26
49
10 = 500 rnA, equivalent 18 lines asserted (8 bit)
UNIT
MIN
5
rnA
t Pulse-testing techniques are used to maintain the Virtual Junction temperature as close to the ambient temperature as poSSible, Thermal effects
must be taken into account separately. All characteristics are measured with a O.l-!lF capacitor across the input and a 22-!lF tantalum capacitor
with equivalent series resistance 01 1.5 n on the output.
~TEXAS
INSTRUMENTS
8-36
POST OFFICE BOX 655303 • PAlLAS, TEXAS 75265
TL2217-285, TL2217-285Y
FIXED-VOLTAGE REGULATORS FOR
SCSI ACTIVE TERMINATION
SLVS066C - NOVEMBER 1991 - REVISED AUGUST 1995
COMPENSATION CAPACITOR SELECTION INFORMATION
The TL2217 -285 is a low-dropout regulator. This means that the capacitance loading is important to the performance
of the regulator because it is a vital part of the control loop. The capacitor value and the equivalent series resistance
(ESR) both affect the control loop and must be defined for the load range and the temperature range. Figures 3 and
4 can be used to establish the capacitance value and ESR range for best regulator performance.
ESR (OUTPUT CAPACITOR)
vs
LOAD CURRENT
STABILITY
vs
ESR
0.04
0.035
c;
I
~
c
0.03
I
0.025
11
:l
j
.
c
0.02
0.015
~,.
~
0.01
I
II:
ffl
0.005
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
1/ESR
IL - Load Current - A
Figure 4
Applied Load
Current
Load
Voltage
Figure 3
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-37
8-38
TL2218-285, TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
available features
•
•
•
•
•
•
•
•
Fully Integrated 9-Channel SCSI
Termination
No External Components Required
Maximum Allowed Current Applied at First
High-Level Step
6-pF Typical Power-Down Output
Capacitance
Wide Vterm t (Termination Voltage)
Operating Range, 3.5 V to 5.5 V
TTL-Compatible Disable Feature
Compatible With Active Negation
Thermal Regulation
PWPACKAGE
(TOP VIEW)
TERMPWR
TERMPWR
NC
DISABLE
NC
NC
DO
D8
D1
D7
D2
NC
D3
D4
D6
D5
NC
NC
GND ~t;::;::;;;;;;;;;;;;;;;;;;;;;;:r- GND
NC - No internal connection
description
The TL2218-285 is a current-mode 9-channel monolithic terminator specially designed for single-ended
small-computer-systems-interface (SCSI) bus termination. A user-controlled disable function is provided to
reduce standby power. No impedance-matching resistors or other external components are required for its
operation as a complete terminator.
The device operates over a wide termination-voltage (Vlerm t) range of 3.5 V to 5.5 V, offering an extra 0.5 Vof
operating range when compared to the minimum termination voltage of 4 V required by other integrated active
terminators. The TL2218-285 functions as a current-sourcing terminator and supplies a constant output current
of 23 mA into each asserted line. When a line is deasserted, the device senses the rising voltage level and begins
to function as a voltage source, supplying a fixed output voltage of 2.85 V. The TL2218-285 features
compatibility with active negation drivers and has a typical sink current capability of 20 mAo
The TL2218-285 is able to ensure that maximum current is applied at the first high-level step. This performance
means that the device should provide a first high-level step exceeding 2 V even at a 10-MHz rate. Therefore,
noise margins are improved considerably above those provided by resistive terminators.
A key difference between the TL2218-285 current-mode terminator and a Boulay terminator is that the
TL2218-285 does not incorporate a low dropout regulator to set the output voltage to 2.85 V. In contrast with
the Boulay termination concept, the accuracy of the 2.85 V is not critical with the current-mode method used
in the TL2218-285 because this voltage does not determine the driver current. Therefore, the primary device
specifications are not the same as with a voltage regulator but are more concerned with output current.
The DISABLE terminal is TTL compatible and must be taken low to shut down the outputs. The device is
normally active, even when DISABLE is left floating. In the disable mode, only the device startup circuits remain
active, thereby reducing the supply current to just 500 IJA. Output capacitance in the shutdown mode is typically
6 pF.
The TL2218-285 has on-board thermal regulation and current limiting, thus eliminating the need ·for external
protection circuitry. A thermal regulation circuit that is designed to provide current limiting, rather than an actual
thermal shutdown, is included in the individual channels of the TL2218-285. When a system fault occurs that
leads to excessive power dissipation by the terminator, the thermal regulation circuit causes a reduction in the
asserted-line output current sufficient to maintain operation. This feature allows the bus to remain active during
a fault condition, which permits data transfer immediately upon removal of the fault. A terminator with thermal
shutdown does not allow for data transfer until sufficient cooling has occurred. Another advantage offered by
the TL2218-285 is a design that does not require costly laser trimming in the manufacturing process.
The TL2218-285 is characterized for operation over the virtual junction temperature range of O°C to 125°C.
t This symbol is not presently listed within EIAIJEDEC standards for letter symbols.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-39
TL2218-285, TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
AVAILABLE OPTIONS
SURFACE MOUNT
(PW)t
TJ
O°Cto 125°C
Tl2218-285PWLE
CHIP FORM
(V)
Tl2218-285Y
t The PW package IS only available left-end taped and reeled.
TL2218-285Y chip information
This chip, when properly assembled, displays characteristics similar to the TL2218-285. Thermal compression
or ultrasonic bonding may be used on the doped aluminum bonding pads. The chip may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
r--------,
I
I
I
I
II
19
DISABLE
[-=-11
I
L
I _ _ _ _ _ _-=-_ _ .JI
. _ -. . .....:!...
Common to All Channels
CHIP THICKNESS: 11 MILS TVPICAL
BONDING PADS: 4 x 4 MILS MINIMUM
TJmax
=150°C
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.
~
M
~
1111111111111111111111111111111111111111111
~TEXAS
8-40
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
DO
TL2218-285, TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
functional block diagram (each channel)
...-_ _ _ _ _ _ _ _....;.:1,..,::2"'0 TERMPWR
r---------,
1
1
I1 _ _
19
DISABLE
1
1
1
1
1
1
1L. _ _ _ _ _ _-=-_ _ _ .J1
4
DO
Common to All Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
(see Figures 1, 2, and 3)f
Continuous termination voltage ............................................................. 10 V
Continuous output voltage range ...................................................... 0 V to 5.5 V
Continuous disable voltage range ...................................................... 0 V to 5.5 V
Continuous total power dissipation .............................•....... See Dissipation Rating Table
Operating virtual junction temperature range, TJ .................................... -55°C to 150°C
Storage temperature range, Tstg ••••••••••••••••••••••••••••.•••••••••••••••.•••.. -60°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
t Stresses beyond those listed under "absolute maximum ratings· may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
POWER RATING
AT
T:;;25°C
POWER RATING
DERATING FACTOR
ABOVE T = 25°C
TA
828mW
430mW
166mW
TC
4032mW
6.62mW/oC
32.2mW/oC
530mW
PW
2583mW
2100mW
812mW
TL:I:
2475mW
19.8mWrC
1584mW
1287mW
495mW
T=70°C
POWER RATING
T=85°C
POWER RATING
T= 125°C
POWER RATING
:I: RaJL is the thermal resistance between the junction and device lead. To determine the virtual junction temperature (TJ) relative to the device lead
temperature, the following calculations should be used: TJ = PD x RaJL + TL, where PD is the intemal power dissipation of the device and TL is
the device lead temperature at the point of contact to the printed wiring board. ROJL is 50.5°CIW.
~1ExAs .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-41
TL2218-~85, TL2218-285V
c
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
FREE-AIR TEMPERATURE
DISSIPATION DERATING CURVE
~
CASE TEMPERATURE
DISSIPATION DERATING CURVE
2400
t
'ii
4800
~
E
E 2200
I
c 2000
4400
I
c
4000
t
1800
II
'-....
3600
'iii
II
is 1600
1400
is
3200
I
2800
a.. 1200
I
a..
II
II
0
=
c
=
0
2000
I
1600
= 1000
c=
""8c 800
...................
600
.......... I"'--..
E
= 400
E
)C
!
200 r-
o
25
2400
1200
(J
Jt' ............
RSJA = 151°C/W ---./
E
E
=
i::Ii
b......
50
75
100
125
TA - Free-Air Temperature - °C
"
1'-....
"-
'""-
R6JC = 31°C/W ./
800
400
o
150
25
50
~
" "-'-....
75
100
125
TC - Case Temperature - °C
Figure 1
150
Figure 2
LEAD TEMPERATURE
DISSIPATION DERATING CURVE
~
4800
E 4400
I
c 4000
i
'iii
3600
II
is 3200
2800
I
a.. 2400
'" "
II
g= 2000
c
i
8
E
E
=
'1<
!
1600
1200
800
I'....
...........
tR6JL= 50.5°CJW ~
400
o
25
50
~
"
75
100
125
TL - Lead Temperature - °C
~
150
Figure 3
t R6JL is the thennal resistance between the junction and device lead. To detennine the virtual junction temperature (TJ) relative to the device lead
temperature, the following calculations should be used: TJ = Po x R6JL + TL, where Po is the internal power dissipation of the device, and TL is
the device lead temperature at the point of contact to the printed wiring board. R6JL is 5O.5°CIW.
~TEXAS
8-42
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 .
TL2218-285, TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
recommended operating conditions
MIN
MAX
3.5
5.5
High-level disable input voltage, V,H
2
Vterm
V
Low-level disable input voltage, V,L
0
0.8
V
Operating virtual junction temperature, TJ
0
125
DC
MIN
TYP
MAX
2.5
2.85
Termination voltage
electrical characteristics, Vterm
UNIT
V
=4.75 V, Vo =0.5 V, TJ =25°C
PARAMETER
TEST CONDITIONS
Output high voltage
-20.5
-23
DISABLE = 4.75 V
Disable input current (see Note 1)
DISABLE=OV
Output capacitance, device disabled
VO=OV,
Termination sink current, total
VO=4V
1 MHz
-24
1
DISABLE=OV
Output leakage current
!LA
500
DISABLE=OV
Output current
mA
228
All data lines = 0.5 V
TERMPWR supply current
V
9
All data lines open
600
100
UNIT
mA
!LA
nA
6
pF
20
mA
NOTE 1: When DISABLE IS open or high, the terminator IS active.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-43
TL2218-285, 'TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992- REVISED OCTOBER 1995
THERMAL INFORMATION
The need for smaller surface-mount packages for use on compact printed-wiring boards (PWB) causes an
increasingly difficult problem in the area of thermal dissipation. In order to provide the systems designer with a better
approximation of the junction temperature rise in the thin-shrink small-outline package (TSSOP). the junction-to-Iead
thermal resistance (R9JL) is provided along with the more typical values of junction-to-ambient and junction-to-case
thermal resistances, RaJA and RaJc.
R9JL is used to calculate the device junction temperature rise measured from the leads of the unit. Consequently, the.
junction temperature is dependent upon the board temperature at the leads, R9JL, and the internal power dissipation
of the device. The board temperature is contingent upon several variables, including device packing denSity,
thickness, material, area, and number of interconnects. The RaJL value depends on the number of leads connecting
to the die-mount pad, the lead-frame alloy. area ofthe die, mount material, and mold compound. Since the power level
at which the TSSOP can be used is highly dependent upon both the temperature rise ofthe PWB and the device itself,
the systems designer can maximize this level by optimizing the circuit board. The junction temperature of the device
can be calculated using the equation TJ =(Po X R9JL)+ TL where TJ =junction temperature, Po =power dissipation,
RaJL = junction-to-Iead thermal resistance, and TL = board temperature at the leads of the unit.
The values of thermal resistance for the TL2218-285 PW are as follows:
Thermal Resistance
RaJA
R9JC
'~
R9JL
Typical Junction Rise
151°C/W
31 °C/W
50.5°C/W
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
10
Output current
vs Input voltage
4
Vo
Output voltage
vs Input voltage
5
10
Output current
VB
Junction temperature
6
vo
Output voltage
VB
Junction temperature
7
-!!1 TEXAS .
INSTRUMENTS
POST OFFICE SOX 655303 • DALLAS. TEXAS 75265
TL2218-285, TL2218-285Y
EXCALIBUR CURRENT-MODE SCSI TERMINATOR
SLVS072C - DECEMBER 1992 - REVISED OCTOBER 1995
TYPICAL CHARACTERISTICS
OUTPUT CURRENT
24
TJ
If
E
20
-
TJ
>
18
0
I
.9
=25°C
3
V
I
&
V
~
/
/
:::I
0
16
4~--~J~--~---T----~--~
J
I
'$
1:1.
'$
INPUT VOLTAGE
/"
22
1:
~
vs
INPUT VOLTAGE
J
=25°C
0(
OUTPUT VOLTAGE
vs
~
'$
2
~
0
I
~
V
14
3
3.5
4
4.5
5
O~--~----~----~----~----J
5.5
4 .
3.5
3
VI - Input Voltage - V
Figure 4
vs
JUNCTION TEMPERATURE
25
0(
20
0
4
I
~
I
1:
~
:::I
i
I
3.5
I
GI
~
'$
~
~
'$
3
~
·0
"..-
I
0
~
I
.9
,
>
I~
15
JUNCTION TEMPERATURE
Vterm = 4.75 V
TA=TJ
Vterm = 4.75 V
TA=TJ
E
5.5
OUTPUT VOLTAGE
vs
~
5
Figure 5
OUTPUT CURRENT
V
4.5
VI - Input Voltage - V
10
5
2.5
2
o
25
50
75
100
125
o
25
50
75
100
TJ - Junction Temperature - °C
TJ - Junction Temperature - °C
Figure 6
Figure 7
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
125
(
8-46
TLE2425,TLE2425Y
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
• 2.5-V Virtual Ground for 5-VlGND Analog
Systems
• Excellent Regulation Characteristics
- Output Regulation
-45 j.LV Typ at 10 = 0 to -10 mA
+15 j.LV Typ at 10 0 to +10 mA
- Input Regulation 1.5 j.LVN Typ
• Low-Impedance Output .•• 0.0075 n Typ
• Macromodellncluded
• Self-Contained in Small-Outline,
Dual-tn-Line or 3-Terminal TO-226AA
Packages
=
=
• High Output-Current Capability
Sink or Source ••• 20 mA Typ
• Micropower Operation ••• 170 j.LA Typ,
OUTPUT REGULATION
description
100
V,=5V
In signal-conditioning applications using a single
power source, a reference voltage is required for
termination of all signal grounds. To accomplish
this, engineers have typically used solutions
consisting of resistors, capacitors, operational
amplifiers, and voltage references. Texas Instruments has eliminated all of those components with
one easy-to-use 3-terminal device. That device is
the TLE2425 precision virtual ground.
80
>:1.
f
i
i
o
/
60
I
TA=-40°C
40
TA=-55°C-~
20
TA=o°C
J~
~ .e::~
o
~
W
V"
TA = 25°C
-20
l
lA ~
J.
TA=125°C
TA=25°C _
/~ 'fI'"
Use of the TLE2425 over other typical circuit
-40
I
i"'"
solutions gives the designer increased dynamic '>o
TA=1250C
-60 -"
C
250
250
Full range
25°C
CL=O
Output voltage response to output current step
25°C
25°C
MAX
2.53
Full range
Output voltage regulation (source current)+
Long-term drift 01 output voltage
2.5
2.47
25°C
VI = 4 Vto40V
Output voltage regulation (sink current)+
2.48
25°C
I
1= 120Hz,
TYP
Full range
VI = 4.5 Vto 5.5 V
Ripple rejection
I
MIN
I1V
235
ppm
22.5
ma
mA
I1V
110
25°C
115
180
IJ.S,
180
CL=100pF
25°C
25°C
12
30
I1S
125
210
IJ.S
t Full range is -40°C to 85°C.
+ Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambienttemperature as possible. Thermal
effects must be taken into account separately.
~'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-51
TLE2425,TLC2425Y
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI = 5 V, 10 = 0 (unless otherwise rioted)
TEST CONDITIONS
PARAMETER
Output voltage
Temperature coefficient 01 output voltage
Bias current
10=0
AVI(PP)= 1 V
10= Oto-20 mA
10=Ot03 mA
10= Ot020 rnA
Noncumulative
Output impedance
Short-circuit output current (sink current)
VO=5V
Short-circuit output current (source current)
VO=O
Output noise voltage, rms
1=10Hztol0kHz
Output voltage response to output current step
Output voltage response to input voltage step
Output voltage tum-on response
2.5
20
25°C
170
1.5
1.5
CL=O
VOtoO.Ol%,
10=±10mA
CL=O
VI = 4.5 to 5.5 V,
VOtoO.l%
VI = 4.5 to 5.5 V,
VOtoO.Ol%
CL=100pF
VI =Ot05V,
VOtoO.l%
VOtoO.Ol%
t
20
-250
25°C
-450
-150
15
25°C
-160
Full range
-250
25°C
-235
15
25°C
7.5
30
55
-30
-50
100
~V
~VN
~V
450
160
250
25°C
ItA
160
250
65
V
dB
80
-45
Full range
~V
235
ppm
22.5
mO
mA
~V
110
25°C
115
180
~
180
CL= 100pF
V,=Ot05V,
20
100
-160
UNIT
ppml"C
250
100
25°C
25°C
VOtoO.l%,
10=±10mA
2.52
250
25°C
25°C
MAX
2.53
25°C
25°C
10=Oto-l0mA
At= 1000 h,
2.48
2.47
Full range
Output voltage regulation (source current):j:
Long-term drift 01 output voltage
25°C
Full range
25°C
VI = 4.5 V to 40 V
Output voltage regulation (sink current):j:
TYP
Full range
Input voltage regulation
1= 120 Hz,
MIN
Full range
VI = 4.5 V to 5.5 V
Ripple rejection
TLE2425M
TAt
25°C
25°C
12
30
~
125
210
~
Full range IS -55°C to 125°C.
:j: Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
8-52
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLE2425,TLE2425V
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
electrical characteristics VI
=5 V, 10 =0, TA =25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2425Y
MIN
TYP
MAX
UNIT
Output voltage
2.5
V
Temperature coefficient of output voltage
20
ppm/"C
10=0
170
I!A
VI = 4.5 Vto 5.5 V
1.5
IlV
VI =4 Vt040V
1.5
IlVN
80
dB
Bias current
Input voltage regulation
Ripple rejection
Output voltage regulation (source current)t
Output voltage regulation (sink current)t
f= 120 Hz,
aVI(PP)= 1 V
10=Oto-l0mA
-45
10=Oto-20 mA
-150
10=Oto 10mA
15
10=Oto 20mA
65
Output impedance
7.5
Short-circuit output current (sink current)
VO=5V
Short-circuit output current (source current)
VO=O
Output noise voltage, rrns
f=10Hztol0kHz
Vo to 0.1%,10 = ±10 mA
Output voltage response to output current step
Vo to 0.01%,10 = ±10 mA
Output voltage response to input vo~age step
Output voltage tum-on response
55
-50
100
CL=O
IlV
IlV
mn
mA
IlV
110
CL= l00pF
115
CL=O
180
CL= 100 pF
180
VI = 4.5 to 5.5 V,
Vo to 0.1%
12
VI = 4.5 to 5.5 V,
Vo to 0.01%
30
VI=Ot05V,
VOtoO.l%
125
VI =Ot05 V,
VOtoO.Ol%
210
IlS
IlS
IlS
t Sample tested. Pulse testing techniques are used to maintain the Junction temperature as close to the ambient temperature as possible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS, TEXAS 75265
8-53
TLE2425C, TLE24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table Of Graphs
FIGURE
Distribution
Output voltage
vs Free-air temperature
Output voltage hysteresis
vs Free-air temperature
vs Input voltage
Input bias current
vs Free-air temperature
Input voltage regulation
vs Frequency
7
Output impljdance
vs Frequency
9
10
Ripple rejection
Output voltage. regulation
B
Short-circuit output current
vs Free-air temperature
Spectral noise voltaglj density
vs Frequency
11
Wide-band noise voltage
vs Frequency
Output voltage change with current step
vsTime
Output voHage change with voltage step
vsTime
12
13
14
15
16
Output voHage power-up response
vs Time
Output current
vs Load capacitance
~TEXAS
8-54
1
2
3
4
5
6
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2425C, TLE24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
OUTPUT VOLTAGE
DISTRIBUTION OF
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
24r-----~-------r------~----_,
2.53
100 Units Tested
From 1 Wafer Lot
VI=5V
10=0
2.52
>
".
I
I
II>
Cl
Jc
2.51
!
::I
'0
~
121-----+-
:;
2.5
~
f
81----+-
I
~
41----1
2.49
2.49
2.5
2.47
-75
2.52
2.51
-50 -25
Vo - Output Voltage - V
I!!
,
-2
J::
~
:;
c.
:;
-4
-6
0
-8
vs
II
10=0
TA = 25°C
.J,..c-
Vs~~p~~
~ ~dPOI~t
~'1
cr:
200
::l.
"""'"
I
\.
C
~
,~
\
,
~
~
~
0
~
100
125
35
40
250
I
VI=5V
Normalized to First 25°C Vo
,,
75
INPUT BIAS CURRENT
,
..
::0
(,)
150
~
~
100
/'
III
--
~~
~
--
iii
:;
c.
100
.5
I
~
-10
~
50
INPUT VOLTAGE
0
'ii
25
FREE-AIR TEMPERATURE
E
I
0
vs
>
.
..
i
..
~
Figure 2
OUTPUT VOLTAGE HYSTERESIS
2
-.......
TA - Free-Air Temperature - °C
Figure 1
4
-
2.48
oL..--2.48
V
/
0
1~
50
o
o
5
TA - Free-Air Temperature - °C
Figure 3
10
15
20
25
30
VI - Input Voltage - V
Figure 4
t Data at high and low temperatures are applicable within rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-55
TLE2425C, TLE24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SLOS065B- MARCH 1991- REVISED AUGUST 1995
TYPICAL CHARACTER1STICSt
INPUT BIAS CURRENT
vs
FREE-AIR TEMPERATURE
INPUT VOLTAGE REGULATION
80
172
VI=5V
170 I- 10 = 0
/
168
cC
:::I.
I
166
~
164
::I
(,)
162
U)
160
..
,;
I
.5
I
~
/
154
/
10=0
TA = 25°C
" "-
-'-
>:::I.
II
,.. / '
III
C
01
.c
40
(,)
II
V
III
:Ill
~
I
20
'S
I
~
0
I
I
~
I
, ./
0
/
:::I.
70
~
'a
I
c
60
'ii'
SO
t
40
i
.
\
.eli:
I
60
i
40
.c
(,)
t
,
II:
10 k
'S
.&
::I
-20
I
-40
V"
>
:1.
,
GI
aI
v~J~tlllll
"'"
60
30
,
,
.!
o
1k
10k
100k
'I
/"
V
20
~;
10
VI=5V
TA = 25°C
100
L
'1:1
C
~
10
"0
:
\
200
~
/
1Ip~,~'(M~ pJs~
50
40
z
I
11111111
TA = 25°C
" I """
I. I
1 Hz to Frequency Indicated
:Ill
400
o
125
~~
10
rrnPo'j ~o~ iIilis
I I II illill
100
1k
10k
100k
f - Frequency - Hz
f - Frequency - Hz
Figure 11
Figure 12
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-57
TLE2425C, Tl.,E24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
OUTPUT VOLTAGE RESPONSE
TO INPUT VOLTAGE STEP
vs
TIME
OUTPUT VOLTAGE RESPONSE
TO OUTPUT CURRENT STEP
vs
TIME
I ill I
IT
1.5V
T
4
>
E
I
OIl
CII
~
0.1%
~
~
0
OIl
CII
-1
1\1
G
-2
0
-3
c
I
>
VI=5V
CL= 100pF
TA=25°C
1
3
500
I ill 1
IT
-
~ 0.1%
I
VI=4.5V
T
50
Figure 13
100
t-Time - JUI
150
200
Figure 14
STABILITY RANGE
OUTPUT VOLTAGE POWER-UP RESPONSE
vs
TIME
3
OUTPUT CURRENT
vs
LOAD CAPACITANCE
20
10=0
CL=100pF
TA=25°C
0.1%
.J.
r
15
2
>
t
g'S
~
1
CC
E
Voltage Response
'V
I
5
C
~
:::I
0
'S
-5
~
Stable
0
0
I
5
Input Voltage Step
0
o
10
t-Time - JUI
20
~
.9
130
-10
-15
-20
10-610-5 10-4 10-310-2 10-1 100
CL- Load Capacitance - f1F
Figure 15
Figure 16
~TEXAS
8-58
~
r--- , /
(,)
I
~
1
Unstable
10
~ ~ut
I
VI='5V '
TA=25°C -
'
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10 1 10 2
TLE2425C, TLE24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SLOS065B - MARCH 1991 - REVISED AUGUST 1995
macromodel information
*
*
*
*
*
*
*
TLE2425 OPERAT:IONAL AHPL:IF:IER "MACROMODELR SUBCIRCU:IT
CREATED USING PARTS RELEASE 4.03 ON 08/21/90 AT 13.51
REV (N/A)
SUPPLY VOLTAGE. 5 V
CONNECTIONS. :INPUT
*
+
I ir
pUT
.SUBCK'l' TLE2425
.*
3
4
5
OPAHP SECTION
Cl
11 12 21.66E-12
C2
6 7
30.00E-12
C3
87 0
10.64E-9
CPSR
85 86 15.9E-9
DCII+
81 82 ox
DCII83 81 ox
DC
5 53 ox
DE
54 5
ox
DLN
92 90 ox
DLP
90 91 ox
DP
4 3
ox
ECIIR
84 99 (2,99) 1
POLY(2)
(3,0) (4,0) 0
EGND
99 0
.5 .5
POLY(l)
(3,4) -16.22E-6 3.24E-6
EPSR
85 0
POLY (1)
(88,0) 120E-6 1
ENSE
89 2
FB
7 99 POLY(6)
VB va VB VLPVLNVPSR
0
-10E6 74E6
GA
6 0
11 12 320.4E-6
10 99 1.013E-9
GeM
0 6
GPSR
85 86 (85,86)
100E-6
GRCl
4
11 (4,11) 3.204:&:-4
4
GRC2
12 (4,12) 3.204:&:-4
GREl
13 10 (13,10)
1.038E-3
GRE2
14 10 (14,10)
1.038:&:-3
HL:III
90 0 VL:III
lit
HCIIR
80 1
POLY(2)
veM+
lE21E2
veM0
IRP
3 4
146E-6
:IEE
3 10 DC 24.05E-6
no
2 0
.2E-9
I1
88 0
lE-21
11 89 13 ax
Ql
Q2
12 80 14 QX
R2
6 9
100.0E3
ReM
84 81 lit
REB
10 99 8.316E6
2.55:&:8
RNl
87 0
RN2
87 88 11. 67:&:3
74. 8E6 -10E6
101:6
10:&:6
:II
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS,,TEXAS 75265
8-59
TLE2425C, TLE24251, TLE2425M
PRECISION VIRTUAL GROUNDS
SL0S065B - MARCH 1991 - REVISED AUGUST 1995
macromodel information (continued)
1lO1
1lO2
VCII+
8 5
63
7 99 62
82 99 1.0
VOI83 99 -2.3
VB
90
DCO
VC
3 53 DC 1.400
VE54 4
DC 1.400
VLIII
7 8
DC 0
VLP
91 0
DC 30
VLR
0 92 DC 30
VPSR
0 86 DC 0
RFB
5 2
lK
RIN
30 1
lK
RCOM
34 4
.1
*REGULATOR SBCTIOH
RGl
30 0
20llBG
RG2
30 31 .2
RG3
31 35 400K
RG4
35 34 411K
RG5
31 36 2511BG
HRBG
31 32 POLY(2)
VPSft 'VNSBT 0
lB21B2
VRBG
32 33 DC OV
BRBG
33 34 POLY(l)
(36,34)
1.23 1
VADJ
36 34 1.27V
HPSBT 37 0 VRBG
1.030B3
VPSH 38 0
DC 20V
BNSft 39 0 VRBG
6.11B5
'VNSH 40 0
DC -20'17
DSUB
4 34 DX
DPOS
37 38 DX
DIII!IBG 40 39 DX
.IIODBL DX D{IS-800.0B-18)
.IIODBL QJt PHP{IS-800.0B-18 BP-480)
.Bl!lDS
.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLE2426,TLE2426Y
THE "RAIL SPLITIER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED AUGUST
• 1/2 VI Virtual Ground for Analog Systems
• Self-Contained 3-terminal TO-226AA
Package
• Micropower Operation •. , 170 IJA Typ,
VI=5V
• Wide VI Range ... 4 V to 40 V
• High Output-Current Capability
- Source ••. 20 mA Typ
- Sink ••. 20 mA Typ
• Excellent Output Regulation
- -451lV Typ at 10 = 0 to -10 mA
- +151lV Typ at 10 = 0 to +10 mA
• Low-Impedance Output ••• 0.0075 Q Typ
• Noise Reduction Pin (0, JG, and P
Packages Only)
INPUT/OUTPUT TRANSFER CHARACTERISTICS
10
description
In signal-conditioning applications utilizing a
single power source, a reference voltage equal to
one-half the supply voltage is required for
termination of all analog signal grounds. Texas
Instruments introduces a precision virtual ground
whose output voltage is always equal to one-half
the input voltage, the TLE2426 "rail splitter."
>
I
J
~
The unique combination of a high-performance,
2~-----4------~----~~~--~
micropower operational amplifier and a precisiontrimmed divider on a single silicon chip results in
a precise VoNl ratio of 0.5 while sinking and
sourcing current. The TLE2426 provides a low0~0------0~.2~5~----70.~5----~0~.7~5~----~
impedance output with 20 mA of sink and source
t-Tlme-s
capability while drawing less than 280 IJA
of supply current over the full input range of 4 V to 40. V. A designer need not pay the price in terms of board
space for a conventional signal ground consisting of resistors, capacitors, operational amplifiers, and voltage
references. The performance and precision of the TLE2426 is available in an easy-to-use, space saving,
3-terminal LP package. For increased performance, the optional 8-pin packages provide a noise-reduction pin.
Wtih the addition of an external capacitor (CNR), peak-to-peak noise is reduced while line ripple rejection is
improved.
Initial output tolerance for a single S-Vor 12-V system is better than 1% with 3.6% overthefull40-V input range.
Ripple rejection exceeds 12 bits of accuracy. Whether the application is for a data acquisition front end, analog
signal termination, or simply a precision voltage reference, the TLE2426 eliminates a major source of system
error.
The C-suffix devices are characterized for operation from O°C to 70°C. The I suffix devices are characterized
for operation from -40°C to 85°C. The M suffix devices are characterized over the full military temperature range
of -55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
O°C to 70°C
SMALL
OUTLINE
(D)
TLE2426CD
-40°C to 85°C
TLE24261D
-55°C to 125°C
TLE2426MD
CERAMIC
DIP
(JG)
TLE2426MJG
PLASTIC
(LP)
PLASTIC
DIP
(P)
TLE2426CLP
TLE2426CP
TLE2426ILP
TLE24261P
TLE2426MLP
TLE2426MP
CHIP
FORM
(V)
TLE2426Y
The 0 and LP packages are available taped and reeled In the commerCial temperature range only. Add R suffiX
to the device type (e. g., TLC2426CDR). Chips are tested at 25°C.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-61
TLE2426, TLE2426Y
THE "RAIL SPUTTER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED. AUGUST 1995
D8
LPPACKAGE
(TOP VIEW)
D, JG, OR P PACKAGE
(TOP VIEW)
OUT
COMMON
IN
NC
2
7
3
6
4
5
NOISE REDUCTION
NC
NC
NC
IN
COMMON
OUT
NC - No internal connection
TLE2426Y chip information
This chip, properly assembled, displays characteristics similar to the TLE2426C. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
IN
(3)
NOISE (8)
REDUCTION -'--'-......-:t
CHIP THICKNESS:
15 MILS TYPICAL
BONDING PADS:
4 x 4 MILS MINIMUM
TJrn8x
(2)
COMMON
--=
--=
--=
--=
-=
--=
--=
NOTE A.
I~
88 - - - - - - - + 1
1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1'1
TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN
MILS.
Both bonding pads numbered 1, both numbered 2,
and both numbered 3, must be bonded out to the
corresponding functions pin.
~TEXAS
8-62
=150°C
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2426,TLE2426V
THE "RAIL SPLITIER"
PRECISION VIRTUAL GROUND
SLOS098B -AUGUST 1991 - REVISED AUGUST 1995
absolute maximum ratings over operating free-air temperature (unless otherwise noted)t
Continuous input voltage, VI ................................................................ 40 V
Continuous filter trap voltage ............................................................... 40 V
Output current, 10 ...................................................................... ±80 mA
Duration of short-circuit current at (or below) 25°C (see Note 1) .............................. unlimited
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA: C suffix ...................................... O°C to 70°C
I suffix ..................................... -40°C to 85°C
M suffix .................................. -55°C to 125°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package ................. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: JG or LP package .............. 300°C
t
Stresses beyond those listed under "absolute maximum ratings' may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions' is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The output may be shorted to either supply. Temperature and/or supply voltages must be limited to ensure that the maximum dissipation
rating is not exceeded.
DISSIPATION RATING TABLE
TA = 70°C
POWER RATING
TA=85°C
POWER RATING
5.8mW/oC
464mW
377mW
145mW
8.4mW/oC
672mW
546mW
210mW
TAS25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
0
725mV
JG
1050mV
LP
775mV
6.2mW/oC
496mW
403mW
155mW
P
1000mV
8.0mW/oC
640mW
520mW
200mW
PACKAGE
TA = 125°C
POWER RATING
recommended operating conditions
CSUFFIX
I SUFFIX
MSUFFIX
MIN
MIN
MIN
MAX
MAX
MAX
UNIT
Input voltage, VI
4
40
4
40
4
40
V
Operating free-air temperature, TA
0
70
-40
85
-55
125
°C
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-63
TLE2426,TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI = 5 V, 10 = 0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLE2426C
TAt
V,=4V
Output voltage
V,=5V
25°C
V, =40V
Full range
VI=5V
Temperature coefficient of output voltage
VI=5V
Supply current
No load
Output voltage regulation
(sourcing current)=I=
10=Oto-10mA
IVI =4t040V
TYP
1.98
2
2.02
2.5
2.52
19.8
20
20.2
2.475
25
25°C
170
-45
±250
-150
±450
25°C
15
±160
±250
65
±235
22.5
Output impedance
25°C
7.5
Noise-reduction impedance
25°C
110
Short-circuit current
Output noise voltage, rms
Sinking current,
VO=5V
Sourcing current,
VO=O
f=10Hzt010kHz
CNR=O
25°C
25°C
CNR= 11lF
Vo to 0.1%,
10=±10mA
Output voltage current step response
Vo to 0.01%, 10=±10mA
Step rel>ponse
VI =Oto 5 V, VOtoO.1%
VI =Ot05V, Vo to 0.01%
CL=O
CL= 100 pF
CL=O
CL= 100pF
CL= 100pF
25°C
25°C
25°C
20
26
-20
-47
IJ.A
±160
25°C
25°C
V
pprn/"C
300
400
Full range
Full range
10=Ot020mA
UNIT
2.525
Full range
25°C
10=Oto 10mA
MAX
2.48
Full range
10= Oto-20 rnA
Output voltage regulation
(sinking current)=I=
MIN
IlV
IlV
mQ
kQ
rnA
120
30
IlV
290
275
400
1!5
390
20
160
1!5
t Full range IS O°C to 70°C.
=1=
Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal
effects must be taken into account separately.
-!!1 TEXAS
INSTRUMENTS
lHi4
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLE2426, TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B -AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI = 12 V, 10 = 0 (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TLE2426C
TAt
VI=4V
Output voltage
25°C
VI = 12 V
VI=40V
Full range
VI = 12 V
Temperature coefficient of output voltage
Supply current
Output voltage regulation
(sourcing current):!:
VI = 12 V
No load
VI =4to40V
TYP
MAX
1.98
2
2.02
5.95
6
6.05
19.8
20
20.2
35
25°C
195
300
-45
±160
Full range
±250
25°C
-150
±450
25°C
15
±160
Full range
±250
25°C
10=Ot020mA
65
±235
22.5
Output impedance
25°C
7.5
Noise-reduction impedance
25°C
110
Short-circuit current
Output noise voltage, rms
Sinking current,
VO= 12V
Sourcing current,
VO=O
f = 10 Hz to 10 kHz
CNR=O
25°C
25°C
CNR= l/lF
Vo to 0.1%,
10=±10mA
Output voltage current step response
Vo to 0.01%, 10=±10mA
Step response
VI=Oto12V, VOtoO.l%
VI = 0 to 12 V, Vo to 0.01%
CL=O
CL=l00pF
CL=O
CL= 100 pF
CL=100pF
25°C
25°C
25°C
V
pprn/"C
400
Full range
10=Oto 10mA
UNIT
6.055
5.945
Full range
25°C
10=Oto-l0rnA
10 = 0 to-20 rnA
Output voltage regulation
(sinking current):!:
MIN
20
31
-20
-70
l1A
/lV
/lV
mO
kO
mA
120
30
/lV
290
275
400
!!S
390
20
120
!!S
t FuUrange IS O°C to 70°C.
:!: Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thennal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-65
TLE2426,TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SL0S098B -AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI =5 V, 10 =0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLE24261
TAt
VI=4V
Output voltage
25°C
VI=5V
VI =40V
Full range
VI=5V
Temperature coefficient of output voltage
VI=5V
Supply current
No load
Output voltage regulation
(sourcing current):!:
10=Oto-l0mA
VI = 4to 40 V
TYP
MAX
1.98
2
2.02
2.48
2.5
2.52
19.8
20
20.2
2.47
25
25°C
170
Fun range
-45
±250
-150
±450
10=Oto 10 mA
25°C
15
±160
10=Ot08mA
Full range
±250
25°C
65
±235
22.5
Output impedance
25°C
7.5
Noise-reduction impedance
25°C
110
Short-circuit current
Output noise voltage, rms
Sinking current,
VO=5V
Sourcing current,
VO=O
f=10Hztol0kHz
CNR=O
25°C
25°C
CNR= lltF
VOtoO.l%,
10=±10mA
Output voltage current step response
VOtoO.Ol%, 10=±10mA
Step response
VI=Ot05V,
Vo to 0.1%
VI =Ot05V,
Vo to 0.01%
CL=O
CL=l00pF
CL=O
CL= l00pF
CL= 100 pI'
25°C
25°C
25°C
20
26
-20
-47
120
30
J!A
±180
25°C
10=Ot020mA
V
ppml"C
300
400
25°C
UNIT
2.53
Full range
Full range
10 = 0 to -20 mA
Output voltage regulation
(sinking current):!:
MIN
ltV
ltV
mO
kO
mA
ltV
290
275
400
ItS
390
20
160
ItS
t Full range is -40°C to 85°C.
.
.:!: Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature aspossible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLE2426,TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI =12 V, 10 =0 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TAt
VI=4V
Output voltage
25°C
VI=12V
VI=40V
Full range
VI = 12 V
Temperature coefficient of output voltage
VI= 12V
Supply current
No load
Output voltage regulation
(sourcing current):!:
10=Oto-l0mA
VI =4to40V
TVP
1.98
2
2.02
6
6.05
19.8
20
20.2
5.935
35
25°C
195
Full range
-45
±250
-150
±450
25°C
15
±160
±250
65
±235
22.5
Output impedance
25°C
7.5
Noise-reduction impedance
25°C
110
Short-circuit current
Output noise voltage, rrns
Sinking current,
VO= 12V
Sourcing current,
VO=O
f=10Hztol0kHz
CNR=O
25°C
25°C
CNR= 11lF
Vo to 0.1%,
10=±10mA
Output voltage current step response
Vo to 0.01%, 10=±10mA
Step response
VI=Oto12V, VOtoO.l%
VI = 0 to 12 V, Vo to 0.01%
CL=O
CL=100pF
CL=O
CL= 100 pF
CL=100pF
25°C
25°C
25°C
20
31
-20
-70
IJ.A
±160
25°C
25°C
10=Ot020mA
V
ppm/DC
300
400
Full range
10=Ot08 rnA
UNIT
6.065
Full range
25°C
10=Otol0rnA
MAX
5.95
Full range
10 =Oto-20mA
Output voltage regulation
(sinking current):!:
TLE24261
MIN
IlV
IlV
mQ
kQ
mA
120
30
IlV
290
275
400
i!S
390
20
120
Ils
t Full range IS -40°C to 85°C.
:!: Sample tested. Pulse testing techniques are used to maintain. the junction temperature as close to the ambient temperature as possible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-07
TLE2426, TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B -AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at speci.fied free-air temperature, VI = 5 V, 10 = 0 (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TAt
VI=4V
'Output voltage
25°C
VI=5V
VI =40V
Full range
VI=5V
Temperature coefficient of output voltage
VI=5V
Supply current
No load
Output voltage regulation
(sourcing currentl:l=
10=Oto-10mA
VI =4t040V
MAX
2.02
1.98
2
2.48
2.5
2.52
19.8
20
20.2
2.465
25
25°C
170
Full range
-45
±250
-150
±450
15
±160
10=Ot010mA
25°C
Full range
10=Ot020mA
25°C
±250
65
±235
22.5
25°C
7.5
Noise-reduction impedance
25°C
110
Output noise voltage, rms
Sinking current,
VO=5V
Sourcing current,
VO=O
f=10Hzt010kHz
CNR=O
25°C
25°C
CNR= 11lF
VOtoO.1%,
10=±10mA
Output voltage current step response
Vo to 0.01%, 10=±10mA
Step response
Full range
IS
VI =Ot05V,
VOtoO.1%
VI=Ot05V,
Vo to 0.01%
CL=O
CL=100pF
CL=O
CL=100pF
CL=100pF
25°C
25°C
25°C
20
26
-20
-47
~
±160
25°C
10=Ot03mA
V
pprn/°C
300
400
25°C
UNIT
2.535
Full range
Output impedance
Short-circuit current
t
TYP
Full range
10=Oto-20 mA
Output voltage regulation
(sinking currentl:l=
TLE2426M
MIN
IlV
IlV
mO
kO
rnA
120
30
IlV
290
275
400
I!S
390
20
120
I!S
-55°C to 125°C.
:1= Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as possible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
8-68.
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
TLE2426,TLE2426V
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED AUGUST 1995
electrical characteristics at specified free-air temperature, VI =12 V, 10 =0 (unless otherwise noted)
TEST CONDITIONS
PARAMETER
TLE2426M
TAt
VI=4V
25°C
VI= 12V
Output voltage
VI =40V
Full range
VI= 12V
Temperature coefficient of output voltage
VI= 12V
Supply current
No load
Output voltage regulation
(sourcing current):j:
10 = 0 10 -10 mA
VI = 4t040V
Short-circuit current
Output noise voltage, mns
2
2.02
6
6.05
19.8
20
20.2
5.925
35
25°C
195
Full range
-45
25°C
15
Full range
10=01020mA
25°C
Sourcing current,
VO=O
f=10Hzlol0kHz
10=±10mA
Output voltage current slep response
VOtoO.Ol%, 10=±10mA
VI=OtoI2V, VOtoO.l%
VI=OtoI2V, VOtoO.Ol%
CNR=O
CNR= 1 ~F
CL=O
CL= 100pF
CL=O
CL= 100pF
CL= 100pF
±160
65
±235
25°C
7.5
22.5
25°C
110
25°C
25°C
25°C
25°C
25°C
31
-20
-70
120
30
~V
±450
±250
20
IlA
±160
±250
10=Ot08mA
VO= 12V
V
ppm/oC
250
350
10=Otol0mA
Sinking current,
UNIT
6.075
Full range
-150
VOtoO.l%,
Step response
1.98
25°C
Noise-reduction impedance
MAX
5.95
25°C
Output impedance
.
TYP
Full range
10 =Oto-20 mA
Output voltage regulation
(sinking current):j:
MIN
~V
mQ
kQ
mA
~V
290
275
400
~
390
12
120
~s
t Full range IS -55°C to 125°C.
:j: Sample lesled. Pulse lesting techniques are used to maintain the junction temperature as close 10 the ambienttemperature as possible. Themnal
effects must be taken into account separately.
-!!I TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-69
TLE2426, TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLQS098B - AUGUST 1991 - REVISED AUGUST 1995
=5 V, 10 = 0, TA =25°C (unless
electrical characteristics at specified free-air temperature, VI
otherwise noted)
TLE2426Y
TEST CONDiTIONS
PARAMETER
MIN
TYP
MAX
UNIT
Output voltage
VI=5V
2.5
V
Supply current
No load
170
IIA
Output voltage regulation (sourcing current)t
Output voltage regulation (sinking current)t
10 = Oto-l0 rnA
-45
10=Oto-20 mA
-150
10=Otol0mA
15
10 =Ot020mA
65
I1V
I1V
Output impedance
7.5
mn
Noise-reduction impedance
110
kn
Short-circuit current
Output noise voltage, rms
Sinking current,
VO=5V
Sourcing current,
VO=O
-47
CNR=O
120
f=10Hztol0kHz
VOtoO.l%,
10=±10rnA
Output voltage current step response
Step response
VOtoO.Ol%,
10=±10mA
VI =Ot05V,
VOtoO.l%
VI =Ot05V,
Vo to 0.01%
26
mA
I1V
30
CNR= ll1F
CL=O
290
CL= l00pF
275
CL=O
CL= l00pF
400
I1S
390
20
CL=100pF
I1S
160
t Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as poSSible. Thermal
effects must be taken into account separately.
= 12 V, 10 =0, TA =25°C (unless
electrical characteristics at specified free-air temperature, VI
otherwise noted)
Output voltage
VI=12V
Supply current
No load
Output voltage regulation (sourcing current)t
Output voltage regulation (sinking current)t
TLE2426Y
TEST CONDITIONS
PARAMETER
MIN
-45
15
65
Noise-reduction impedance
Output noise voltage, rms
110
kn
31
Sourcing current,
VO=O
-70
CNR=O
120
CNR= ll1F
30
10=±10mA
CL=O
CL=100pF
290
VOtoO.Ol%,
10=±10mA
CL=O
CL=100pF
VI =Oto 12V,
VOtoO.l%
VI=OtoI2V,
VOtoO.Ol%
Output voltage current, step response
CL= l00pF
I1V
mn
VO= 12V
f=10Hztol0kHZ
I1V
7.5
Sinking current,
Vo to 0.1%,
Step response
V
IIA
-150
10=Ot020mA
UNIT
6
10 = Oto-20 mA
10=Ot03mA
MAX
195
10=Oto-l0mA
Output impedance
Short-circuit current
TYP
mA
I1V
275
400
I1S
390
12
120
I1S
t Sample tested. Pulse testing techniques are used to maintain the junction temperature as close to the ambient temperature as poSSible. Thermal
effects must be taken into account separately.
~TEXAS
INSTRUMENTS
8-70
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLE2426,TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B -AUGUST 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
Table Of Graphs
FIGURE
1,2
Output voltage
Distribution
Output voltage change
vs Free-air temperature
Output voltage error
vs Input voltage
4
vs Input voltage
5
vs Free-air temperature
6
Input bias current
3
Output voltage regulation
vs Output current
7
Output impedance
vs Frequency
8
Short-circuH output current
vs Input voltage
9,10
vs Free-air temperature
11,12
Ripple rejection
vs Frequency
Spectral noise voltage density
vs Frequency
14
Output voltage response to output current step
vsTime
15
Output voltage power-up response
vs Time
16
Output current
vs Load capacitance
17
13
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALlAS. TEXAS 75265
8-71
TLE2426, TLE2426Y
THE "RAIL SPLITIER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
DISTRIBUTION
OF
OUTPUT VOLTAGE
DISTRIBUTION
OF
OUTPUT VOLTAGE
40~~--~-------r------~------'
3r-----~------~------~----~
98 Units Tested
98 Units Tested
From 2 Wafer Lots
VI=5V
TA = 25°C
2.5
#.
#.
21------+--
I
~
~
c
5
;:)
'0
301-----+-
I
1.5 1 - - - - - + - -
f
0.5
'0
201------+-
J
101----+-
I------+~
0 ' - - - -..........
2.48
2.49
2.5
2.51
Vo - Output Voltage - V
0'----2.52
6.025
6.05
6.075
Vo - Output Voltage - V
6
Figure 1
Figure 2
OUTPUT VOLTAGE ERROR
OUTPUT VOLTAGE CHANGE
150
>
E
I
..&
~
VB
FREE-AIR TEMPERATURE
INPUT VOLTAGE
I
0
5Q.
5
'"
t"'-- ~
Error Equals VO/VI Deviation From 50~
2
""" ' -r--...- r-=:::
'"
-75
-150
-75
/
o
-1
-50
-25
0
25
I
1
3
0
~
:::t
I
100
10
V
I
0
8c
'5
~
ia.
i
II
01
0
V~
.5
III
CI
'$
:!l!
~
:!l
0.1
0
/
I
0
'$
~
VI=5'Vor12V
10=0
TA=25°C
Cl
250
c
a:
125
N
-250
0
-500~
-20
______
~
______
~
______
~
-10
o
10
10 -Output Current - mA
____
~
20
0.01
0.001
10
100
1k
10 k
100 k
1M
f - Frequency - Hz
Figure 8
Figure 7
t Data at high and low temperatures are applicable within the rated operating free-air temperature ranges of the various devices.
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-73
TLE2426, TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B - AUGUST 1991- ReVISED AUGUST 1995
TYPICAL CHARACTERISTICSt
SHORT-CIRCUIT OUTPUT CURRENT
vs
INPUT VOLTAGE
.SHORT-CIRCUIT PUTPUT CURRENT
VS
INPUT VOLTAGE
0
I
CNR",1I1F
\
VI ",S Vor 12 V
TA",2SoC
>c
o
~
10
1M
100
.n
>
E
.
I
01
:!l!
~
..
.5
.
..... 0.1%
oJtput Volta e Respon1se
>
2
\
0
0.0 %
-1
.c
-2 I--- 10mA
I
10 Step
-3
r
I
/
"
\
0.01%
!
~
'5Q.
'5
o
~
f--lumA
o
1000
2000
3000
1.5
10=0
CL = 100 pF
TA=2SoC
O.S
I
,..-
10.1%
-4
-1.SV
2
I
&
:!l!
\
C
~
<3
0.01%
2.S
0.1%
01
U
100k
OUTPUT VOLTAGE POWER-UP RESPONSE
t
~
'5
0
10 k
3
VI"'SV
CL=100pF
TA=2SoC
3
1k
Figure 14
OUTPUT VOLTAGE RESPONSE
TO OUTPUT CURRENT STEP
4
CNR "'111F
f - Frequency - Hz
Figure 13
1.SV
CNR"'O
4000
o
:I I
lime-11II
o
'+-I- I I
SO
100
1S0
200
lime-l1s
Figure 15
Figure 16
~TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-75
TLE2426, TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS09SB - AUGUST 1991 - REVISED AUGUST 1995
TYPICAL CHARACTERISTICS
STABILITY RANGE
OUTPUT CURRENT
vs
LOAD CAPACITANCE
20
I
15
VI=1 5V
TA=25°C -
I
Unstable
10
ct
E
I
5
C
~
:::s
0
'Sa.
'S
-5
r--
.....
,,/
U
Stable
0
I
.9
-10
-15
-20
10-610-5 10-4 10-310-2 10-1 100
CL- Load Capacitance - J!F
Figure 17
~TEXAS
8-76.
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10 1 10 2
TLE2426,TLE2426Y
THE "RAIL SPLITTER"
PRECISION VIRTUAL GROUND
SLOS098B -AUCWST 1991 - REVISED AUGUST 1995
macromodel information
*
*
*
*
*
*
TLE2426 OPERATIONAL AMPLIFIER "MACROMODEL n SUBCIRCUIT
CREATED USING PARTS RELEASE 4.03 ON 08/21/90 AT 13:51
REV (N/A)
SUPPLY VOLTAGE: 5 V
CONNECTIONS:
FILTER
INPUT
COMMON
iUTPUT
I I I
.SUBCKT TLE2426
C1
C2
C3
CPSR
DCM+
DCM-
11
6
87
85
81
83
5
54
90
92
4
84
99
85
89
7
6
0
85
4
4
13
14
90
80
3
3
2
88
11
12
6
84
10
87
87
8
7
82
83
9
3
54
7
91
1
3
4
5
12 21.66E-12
7 30.00E-12
10.64E-9
86 15.9E-9
82 DX
81 DX
DC
53 DX
DE
5 DX
DLP
91 DX
DLN
90 DX
DP
3 DX
ECMR
99 (2,99)" 1
POLY(2)
(3,0) (4,0)
EGND
.5 .5
EPSR
POLY(l)
(3,4) -16.22E-63.24E-6
ENSE
2 POLY(l)
(88,0) 120E-61
FB
99 POLY(6)
VB VC VE VLPVLNVPSR
74.8E6 -10E6
GA
0 11 12 320.4E-6
GeM
6 10 99 1.013E-9
GPSR
100E-6
86 (85,86)
GRC1
11 (4,11) 3.204E-4
GRC2
12 (4,12) 3.204E-4
GRE1
10 (13,10)
1.038E-3
GRE2
10 (14,10)
1. 038E-3
HLIM
1K
0 VLIM
HCMR
1 POLY(2)
VCM+
VCM0
1E2
1E2
IRP
4 146El- 6
IEE
10 DC 24.05E-6
no
.2E-9
I1
1E-21
Q1
89 13 QX
Q2
80 14 QX
R2
9 100.0E3
RCM
81 1K
REE
99
8.316E6
RN1
0 2.55E8
RN2
88 11. 67E3
R01
5 63
R02
99 62
VCM+
99 1.0
VCM99 -2.3
VB
0 DC 0
VC
53 DC 1.400
VE
4 DC 1.400
VLIM
8 DC
VLP
0 DC 30
VLN
92 DC 30
VPSR
0 86 DC 0
RFB
5
2 lK
RIN1
3
1 220K
RIN2
1
4 220K
.MODEL DX D(IS=800.0E-18)
.MODEL QX PNP(IS=800.0E-18BF=480)
. ENDS
°
°
°°
°
°
10E6
10E6
-10E6
74E6
°°
°
~1ExAs
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8-77
8-78
TPS2811, TPS2812, TPS2814, TPS2815
DUAL HIGH·SPEED MOSFET DRIVERS
• Industry-Standard Driver Replacement
• 20-ns Max Rise/Fall Times and 30 ns Max
Propagation Delay -1-nF Load
TPS2811, TPS2812, TPS2813 ••• D, P, AND PW
PACKAGES
• 2-A Peak Output Current
• 100-!JA Supply Current - Inputs High or
Low
• 4-V to 14-V Driver Supply Voltage Range;
Internal Regulator Extends Range to 34 V
• -40°C to 150°C Junction Temperature
Operating, Range.
0'
(TOP VIEW)
REG_IN
11N
GND
21N
2
3
4
a
7
6
5
REG_OUT
10UT
Vee
20UT
TPS2814, TPS2815 ••• D, P, AND PW
PACKAGES
(TOP VIEW)
description
The TPS2811 series of dual high-speed MOSFET
drivers are capable of delivering peak currents of
2 A into highly capacitive loads. This performance
is accompanied by supply currents an order of
magnitude lower than those of competitive
products. The deSign inherently minimizes
shoot-through current.
1 I N Q a GND
21N
2
7 10UT
31N 3
.6 Vee
41N 4
5 20UT
~
W
Each of the TPS2811, TPS2812, and TPS2813 drivers include a regulator to allow operation with supply inputs
between 14 V and 34 V. The regulator output can be used to power other circuitry, provided power dissipation
does not exceed package limitations. Supply voltagesbelow 14 V may be connected directly to V ee, REG_OUT,
and REG_IN, or REG_IN can be left open.
The TPS2811 series are available in 8-pin PDIP, SOIC, and TSSOP packages and operate over a junction
temperature range of -40°C to 150°C.
:;
w
a:
Q.
~
o
::l
o
oa:
Q.
PRODUCT PREVIEW Information concemo products In Ihe formative or
d88ign p/l888 of ~. Ch.......rlslic data and oilier
spooHI...I... 0,. duign goals. Tox88ln81rumanls _ _ tho ~ fo
change or dl8COnlinUl1he88 products without notlco.
~TEXAS
Copyright © 1995, Texas Instruments Incorporated
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265
8-7,9
TPS2811, TPS2812, TPS2814, TPS2815
DUAL HIGH-SPEED MOSFETDRIVERS
SLVS132'-OCTOBER 1995
logic diagrams (positive logic)
TPS2811
REG_IN'~
.,
VREG
TPS2812
~
REG_OUT
REG_IN
~vee
~
.,
11N~10UT
11N~10UT
2IN~.20UT
21N~20UT
GND
GND
TPS2813
REG_IN
TPS2814
~
•
REG_OUT
6 Vee
o
'IN~'0UT
3
8
GND
GND
C
c:
~
'
31N~20UT
41N 4
21N~20UT
"tI
6 Vee
21N~
11N~10UT
:D
TPS2815
6 Vee
11N~
2
7 10UT
21N
"tI
:D
31N~3
4
5
m
<
m
-=e
20UT
41N
8
GND
~TEXAS
INSTRUMENTS
8-80
REG_OUT
~vee
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
..
TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVSI31-
•
•
•
•
•
•
•
On-chip Charge Pump Provides Negative
Gate Bias for Depletion-Mode GaAs Power
Amplifiers
Buffered Clock Output to Drive Additional
External Charge Pump
200-mO High-Side Switch With LogicCompatible Enable Input Controls Supply
Voltage to the GaAs Power Amplifier
Power-Good Circuitry Prevents High-Side
Switch Turn-on Until Negative Gate Bias is
Present
Charge Pump Can Be Driven From the
Internal Oscillator or An External Clock
1o-~ Maximum Standby Current
Low-Profile (1.2-mm Max Height), 20-Pin
TSSOP Package
1995
PWPACKAGE
(TOP VIEW)
GATE_BIAS
Vee
ClCl+
BATT_IN
BATT_IN
BATT_IN
PGP
PG
GND
10
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VDD
ClK
BClK
GND
BATT_OUT
BATT_OUT
BATT_OUT
SW EN
OSC_EN
EN
description
The TPS91 03 is a highly integrated power supply for depletion-mode GaAS power amplifiers (PA) in cellular
handsets and other wireless communications equipment. Functional integration and low-profile packaging
combine to minimize circuit-board area and component height requirements. The device includes: a p-channel
MOSFET, configured as a high-side switch to control the application of power to the PA; a driver for the high-side
switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent
turn-on of the high-side switch until gate bias is present. The high-side switch has a maximum on-state
resistance of 200 mO.
The TPS91 03 is available in a 20-pin TSSOP package and operates over an ambient temperature range of
-40°C to 85°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA
TSSOP
(PW)
-40o e to 85°e
TPS91031PWLE
CHIP FORM
(V)
TPS9103Y
The PW paclevice ....................................................
2
Principle of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2
5-V Reference Regulator ............................................
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Frequency .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Above 150 kHz. . . .. .. . . . .. . . . .. . . .. . ....... . . . . . . . . . . . .
Dead-Time-ControllPWM Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dead-Time Control ................................ : . . . . . . . . . . . . . .
Pulse-Width Modulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .
Error Amplifiers ........................................ , . . . . . . . . . .
Output-Control Logic ................................ . ... . . . . . . . . . . .
Output-Control Input ............................................
Pulse-Steering Flip-Flop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Transistors . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . .
3
4
5
5
7
7
8
8
8
11
11
12
13
Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Regulator . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Boosting the 5-V Regulator.. . .. .. ..... ... ... .. . . .. .. ..... .
Applications of the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronizing . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master/Slave Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Clock Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fail-Safe Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Amplifier Bias Configuration. . . . . . . . . .. . . . . . . . . .. . . . . . . . . . . . . . .
Current Limiting . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fold-Back Current Limiting. . ... . . .. . . . . .. ....... .. ...... . .... . . .
Pulse-Current Limiting. . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . .
Applications of the Dead-Time Control ...............................
Soft Start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Modulation of Turn-Off Transition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
14
14
15
15
15
16
17
17
18
18
19
21
22
22
23
9-5
List of Dlustrations
Figure
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Page
TIA94 Block Diagram ........ :................................
1
TIA94 Modulation Technique ...................................
2
5-V Reference Regulator. . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . .
3
4
Reference RegUlator Output vs Input Voltage. . . . . . . . . . . . . . . . . . . . . . .
Internal Oscillator Schematic ....................................
4
Oscillator Frequency vs RT/CT ... , .......... , ............. ;.....
6
Variation of Dead Time vs RT/CT , ........ ,. . .... ... .. .. .... . . ..
6
PWM/Oead-Time-Control Comparator .......... ,:................
7
Error Amplifiers ................... , ................. ,........
9
Multiplex Structure of Amplifiers " ..... , ......... , ............. ,
9
Error Amplifier Bias Configurations for Controlled ,Gain
Applications ........ ".,", .. ,., .. ,.,.,., .. ".,., .. , .. ,....
10
Amplifier Transfer Characteristics , , ..... , ..... , , . , , ',' . , ...... , . .
10
11
Amplifier Bode Plot .. , ....... , ........ , ... , ...... ,.,""", ..
Output-Steering Architecture ...... , .................. , ... ,' ... , ,12
Pulse-Steering Flip-Flop, ... , ... ', . , .. , .. , , .... , . , .. , , , . , ..... , .
13
Output Transistor Structure ............................. ,. . .. . . .
13
Conventional 3-Terminal Regulator Current-Boost
Technique. .. .. .... . . . .... .. .. .... .. ..... .. .. .. .. . .. .... . . .
14
TIA94 Reference Regulator Current-Boost Technique. . . . . . . . . . . . . . .
15
Master-Slave Synchronization ....... ; ............... , . . . . . . . . . . .
15
External Clock Synchronization ............................. ". . .
16
Oscillator Start-Up Circuit ... , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Fail-Safe Protection ..... , ........ , . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17
Error Amplifier Bias Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
Fold-Back Current Limiting ................ , .. , , . , ....... , .. , . .
18
Fold-Back Current Characteristics. . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .
19
Error Signal Considerations .. ~ ............................... , .
20
Peak-Current Protection ... ; .......... , .. " . . . . . . . . . . . . . . . . . . . . .
20
Dead-Time-Control Characteristics ........ , ........... ,.........
21
Tailored Dead Time ...........................................
22
Soft-Start Circuit, ........ '................... , .............. ',' .
22
Overvoltage Protection Circuit ....................... , . , , , , , , .. ,
23
Tum-On Transition , . , .. , ... , . , ......... , ....... , ......... , , . .
23
Tum-Off Transition ....... , ...................... , .. , . . . . . . . . .
24
Abstract
In this application report,· the TlA94 switching power supply control is discussed
in detail. A general overview of the device's architecture presents the primary functions
contained in the 16-pin dual-in-line package and its features. An in-depth study of each
of the device's primary building blocks highlights the versatility and limitations of the
control circuit and gives a thorough understanding of their interrelationship. Applying the
control circuit to several basic applications demonstrates the circuits' usefulness and outlines
some still unresolved problems.
Introduction
Over the past few years, a series of monolithic integrated circuits for the control
of switching power supplies have been introduced. One of these, the TlA94, combines
many of the features previously requiring several control circuits. The TlA94 simplifies
many design problems with its unique architecture. It is the purpose of this application
report to give the reader a thorough understanding of the TlA94, its features, its
performance characteristics, and its limitations.
VI
VREF
OUTPUT
CONTROL
RT-!==r====='-r==±==~~r=jC=L==;:=--:~
________
CT--t1~
C1
~
E1
C2
E2
DEAD·TIME
CONTROL
AMPLIFIER
INPUTS
' r - - - - 4 - - GNtl
FEEDBACK
Figure 1. TIA94 Block Diagram
9-7
The Basic Device
The design of the TLA94 not only incorporates the primary building blocks required
for the control of a switching power supply but also addresses many basic problems and
reduces the amount of additional circuitry required in a total des~gn. Figure 1 shows a
block diagram of the TLA94.
Principle of Operation
The TLA94 is a fixed-frequency pulse-width-modulation (PWM) control circuit.
Modulation of output pulses is accomplished by comparison of the sawtooth waveform,
created by the internal oscillator on the. timing capacitor (CT), to either of two control
signals. The output stage is enabled during that portion of time when the sawtooth voltage
is greater than the control signals. As the control signals increase, the period of time the
sawtooth input is greater decreases; therefore the output pulse duration decreases. A pulsesteering flip-flop alternately directs the modulated pulse to each of the two output transistors.
Figure 2 illustrates the relationship between the pulses and signals.
CONTROL
SIGNAL
k::::
Figure 2. TIA94 Modulation Technique
The control signals are derived from two sources: the dead-time (off-time) control
circuit and the error amplifier circuit. The dead-time-control input is compared directly
by the dead-time-control comparator. This comparator has a fixed l()()..mV offset. With
'the control input biased to ground, the output is inhibited during the portion of time the
sawtooth waveform is below 110 mV. This provides a preset dead time of approximately
3 %, which is the minimum dead time that can be programmed. The PWM comparator
compares the control signal created by the error amplifiers. One function of the error
9-8
amplifier is to monitor the output voltage and provide sufficient gain so that millivolts
of error at its input will result in a control signal of sufficient amplitude to provide 100%
modulation control. The error amplifiers can also be used to monitor the output current
and provide current limiting to the load.
5-V Reference Regulator
The TLA94 internal 5-V reference regulator is shown in Figure 3. In addition to
providing a stable reference, it acts as a preregulator and establishes a stable supply from
which the output-control logic,pulse-steering flip-flop, oscillator, dead-time-control
comparator, and PWM comparator are powered. The regulator employs a band-gap circuit
as its primary reference to maintain a thermru. stability ofless than l00-mV variation over
the operating free-air temperature range of 0 °C to 70°C. Short-circuit protection is provided
to protect the internal circuit from excessive load or short-circuit conditions. Designed
primarily as an internal reference and preregulator, 10 rnA of load current is available
for additional bias circuits. The reference is internally programmed to an initial accuracy
of ± 5 % and maintains a stability of less than 25-mV variation over an input voltage range
of 7 V to 40 V. For input voltages less than 7 V, the regulator saturates within 1 V of
the input voltage and tracks it, as shown in Figure 4.
.
.--_-..-+__......._~----+-.......-
VREF
15 VI
Figure 3. 5- V Reference Regulator
9-9
"II
I,
V
o
1
V
V
V
II
V
"II
"
"
"
"
"
"
"
II
2
3
4
5
6
7
40
VI-INPUT VOLTAGE-V
Figure 4. Reference Voltage vs Input Voltage
Oscillator
A schematic of the TIA94 internal oscillator is presented in Figure 5. The oscillator
provides a positive sawtooth waveform to the dead-time and PWM comparators for
comparison to the various control signals.
Figure 5. Internal Oseillator Schematic
9-10
Operation Frequency
The frequency of the oscillator is programmed by selection of the timing components
RT and CT. The oscillator charges the external timing capacitor, CT, with a constant current
- the value of which is determined by the external timing resistor, RT. This produces
a linear-ramp voltage waveform. When the voltage across CT reaches 3 V, it is discharged
by the oscillator circuit and the charging cycle is reinitiated. The charging current is
determined by the formula:
ICHARGE
=3V
RT
The period of the sawtooth is:
t
3 V·CT
= ---"'-ICHARGE
The frequency of the oscillator then becomes:
fOSC=-RpCT
The oscillator frequency. however, is only equal to the output frequency for single-ended
applications; for push-pull applications, the output frequency is one-half the oscillator
frequency:
= ---
Single-ended applications:
f
Push-pull applications:
f=--2RpCT
The oscillator is programmable over a range from 1 kHz to 300 kHz. Practical values
for RT and CT range from I kO to 500 kO and 470 pF to 10 pF, respectively. A plot
of the oscillator frequency versus RT and CT is shown in Figure 6. The stability of the
oscillator, for free-airtemperature variations from O°C to 70°C for various ranges of RT
and CT, is also indicated in Figure 6.
OperatUm Above 150 kHz
At an operation frequency of 150 kHz, the period of the oscillator is 6.67 /AS; The
dead time established by the internal offset of the dead-time comparator ( '"' 3 % period)
yields a blanking pulse 0[200 ns. This is the minimum blanking pulse acceptable to assure
proper toggling of the pulse-steering flip-flop. For frequencies above 150 kHz, additional
9-11
1 M ~~---r~----r-----~------~~---'
c:
I
~
z
~
100 k ~,....-_-+"
en
iii
~
(l).
s::
:E
t=
1.0 k 1------4i1!r----4!"r---q....
I
i£
1 k
10
100
, k
10 k
100 k
1 M
f-fREQUENCY-Hz
NOTE: The percent of oscillator frequency variation over the ODC to
70 DC free-air temperature range is represented by dashed lines.
Figure 6. Oscillator Frequency vs RT/CT
dead time (above 3 %) is provided internally to assure proper triggering and blanking of.
the internal pulse-steering flip-flop. Figure 7 shows the relationship of internal dead time
(expressed in percent) provided for various values of RT and CT.
1M
c:
I
w
(.)
Z
~ 100 k
!!l
ff3
a:
(l)
~ 10 k
t=
I
i£
1k
10
100
1k
10 k
100 k
f-fREQUENCY - Hz
Figure 7. Variation of Dead Time vs RT/CT
9-12
, M
Dead-Time-Control/PWM Comparator
The functions of the dead-time-control comparator and the PWM comparator are
incorporated in a single comparator circuit, as shown in FigureS. Since the two functions
are totally independent, each function is discussed separately.
Comparator
The comparator is biased from the 5-V reference regulator. This provides isolation
from the input supply for improved stability. The input of the comparator does not exhibit
any hysteresis, so caution should be observed to protect against false triggering near the
threshold. The comparator exhibits a response time of 400 ns from either of the control
signal inputs to the output transistors, with only lOO-mV overdrive. This assures positive
control of the output, within a half cycle, for operation within the recommended 300-kHz
range.
Q1
02
4 _ _ _ _ _ _ _ _ _ _- l
DEAD.TIME_
CONTROL
ERROR
tinternal offset
AMPLIFIERS
-<
FEEDBACK _-"3_.......
Figure 8. PWM/Dead-Time-Control Comparator
9-13
Dead- Time Control
The dead-time..control input provides control of the minimum dead time (off time).
The output of the comparator inhibits switching transistors Q 1 and Q2 whenever the voltage·
at its input is greater than the ramp voltage of the oscillator (see Figure 28). An internal
offset of 110mV assures a minimum dead time of = 3 % with the dead-time-control input
grounded. Additional dead time can be imposed by applying a voltage to the dead-timecontrol input. This provides a linear control of the dead time from its minimum of 3 %
to 100% as the input voltage is varied from 0 V to 3.3 V, respectively. With full range
control, it allows control of the output from external sources without disrupting the error
amplifiers. The dead-time-control input is a relatively high-impedance input
(II = < 10 p,A) and should be used where additional control of the output duty cycle is
required. The input,however, must be terminated for proper control. An open circuit
is an undefined condition.
Pulse-Width Modulation
The comparator also provides modulation control of the output pulse width. For
this, the ramp voltage across timing capacitor CT is compared to the control signal present
at the output of the error amplifiers, The timing capacitor input incorporates a series diode
which is omitted from the control signal input. This requires--the control signal (error
amplifier output) to be =0.7 V greater than the voltage across CT to inhibit the output
logic, and assures maximum duty cycle operation without requiring the control voltage
to sink to a true ground potential. The output pulse width varies from 97% of the period
to 0 as the voltage present at the error amplifier output varies from 0.5 V to 3.5 V,
respectively.
Error Amplifiers
A schematic of the error amplifier circuit is shown in Figure 9. Both high-gain error
amplifiers receive their bias from the VI supply rail. This permits a common-mode input
voltage range from -0.3 V to 2 V less than VI. Both amplifiers behave characteristically
of a single-ended single-supply amplifier in that each output is active high only. This allows
each amplifier to pull up independently for a decreasing output pulse-Width demand. With
both outputs ORed together at the inverting input node of the PWM comparator, the
amplifier demanding the minimum pulse out dominates. The amplifier outputs are biased
low by a current sink to provide maximum pulse width out when both amplifiers are biased
off.
9-14
VI _ _ _ _~~----__,
VREf _ _ _ _
~
AMP2
INVERTING INPUT - - - - - - - / - - 1
NONINVERTING INPUT
------t---t--1i----+--1i---J
'--,,-CT
......- - - f .•.
Figure 9. Error Amplifiers
Figure 10 shows the output structure of the amplifiers operating into the 300-ItA
current sink. Attention must be given to this node for biasing considerations in gain control
and external control interface circuits. Since the amplifier output is biased low only through
a current sink (ISINK = 0.3 rnA), bias current required by external circuitry into the
feedback terminal must not exceed the capability of the current sink, otherwise, the
maximum output pulse width will be limited. Figure 11 illustrates the proper biasing
techniques for feedback gain control.
300pA
FEEOBACII
CT
Figure 10. Multiplex Structure of Amplifiers
9-15
TO OUTPUT
VREF
R1
R2
1
RI
RI
VREF
R1
R2
RF
RF
-=
TO OUTPUT
NEGATIVE OUTPUT
POSITIVE OUTPUT
Figure 11. Error Amplifier Bias Configurations for Controlled Gain Applications
A plot of amplifier transfer characteristics is shown in Figure 12. This illustrates
the linear gain charactenstics of the amplifiers over the active input range of the PWM
comparator (0.5 V to 3.5 V). This is important for overall circuit stability. The open-loop
gain of the amplifiers, for output voltages from 0.5 V to 3.5 V, is 60 dB. A Bode plot
of the amplifiers' gain characteristics is shown in Figure 13. Both amplifiers exhibit a
response time of approximately 400 ns from their inputs to their outputs. Precautions should
be taken to minimize capacitive loading of the amplifiers' outputs. Since they employ active
pull-up only, the amplifiers' ability to respond to an increasing load demand can be severely
degraded by capacitive loads.
----
!'-
4
I
>I
~
:!
3
~
~
5I
o
>
f'"
I
II
II
2
I
I
o I
o
1
10
20
VI-INPUT VOLTAGE-mV
Figure .12. Amplifier Transfer Characteristics
9-16
80
60
III
'0
I
40
"
20
z
C
0
1K
10 K
100 K
1 M
f- FREQUENCY - Hz
Figure 13. Amplifier Bode Plot
Output-Control Logic
The output-controllogic is structured to provide added versatility through external
control. Designed for either push-pull or single-ended applications, circuit performance
can be optimized by selection of the proper conditions applied to the various control inputs.
Output-Control Input
The output-control input determines whether the output transistors operate in parallel
or push-pull fashion. This input is the supply source for the pulse-steering flip-flop, as
shown in Figure 14. The output-control input is asynchronous and has direct control over
the output, independent of the oscillator or pulse-steering flip-flop. The input condition
is intended to be a fixed condition that is defined by the application. For parallel operation,
the output-control input must be grounded. This disables the pulse-steering flip-flop and
inhibits its outputs. In this mode, the pulses seen at the output of the dead-time-controIIPWM
comparator are transmitted by both output transistors in parallel. For push-pull operation,
the output-control input must be connected to the internal5-V reference regulator. Under
this condition, each of the output transistors is enabled, alternately, by the pulse-steering
flip-flop.
9-17
1D
INPUT CONTROL
PWM COMPARATOR
CONTROL
SIGNAL
CTI
I " ""
CONTROL
S~NAL
C1
~.~
10 I
"I-I_ _--IoL-........_
F.F.
",-I_ _ _ _
Q2
CONTROL SIGNAL
__~~__~~~~__~~~-&__~~L-~___
COMP
Q1
"
LDJ
_..w.........&..II_ _
~__Io
LDJ
......._
LJ
_..I.oI_.._
I
~I____-w
U______~U______~~
Ir
II ____~'___
--''---_......a---'-_ _-'--_ _ _ _.o.-.-
1------,I I
IJ
1I
Figure 14. Output-Steering Architecture
Paise-Steering Flip-Flop
The pulse-steering flip-flop is a positive-edge-triggered D-type flip-flop that changes
state synchronously with the rising edge of the comparator output (see Figure 14). The
dead time provides blanking during this period to ensure against the possibility of having
both outputs on, simultaneously, during the transition of the pulse-steering flip-flop outputs.
A schematic of the pulse-steering flip-flop is shown in Figure 15. Since the flip-flop receives
its trigger from the output of the comparator, not the oscillator, the output always operates
in a push-pull manner. The flip-flop will not change state unless an output pulse occurred
in the previous period of the oscillator. This architecture prevents either output from double
pulsing, but restricts the application of the control signal sources to de feedback signals
(for additional detail read 'Pulse-Current Limiting' in this application report).
9-18
OUTPUT
CONTROL
-+-----+---41...----,
.---r-------TOQ1
.----t---;r----- TO Q2
TRANSISTOR
OFF
ON
COMPARATOR_e-_ _ _ _ _ _ _ _ _ _ _ _ _ _---'
OUTPUT
Figure 15. Pulse-Steering Flip-Flop
Output Transistors
There are two output transistors available on the TLA94. The output structure is
illustrated in Figure 16. Both transistors are configured open collector/open emitter and
each is capable of sinking or sourcing up to 200 rnA of current. The transistors exhibit
a saturation voltage of less than 1.3 V in the common-emitter configuration and less than
2.5 V in the emitter-follower configuration. The outputs are protected against excessive
power dissipation to prevent damage but do not employ sufficient current limiting to allow
them to be operated as current-source outputs.
FLIP-FLOP _.,.,..,...,
~
__....._
OUTPUT
COLLECTOR
OUTPUT
COMPARATOR_""""....-;
OUTPUT
' - _...._
...._EMITTER
OUTPUT
Figure 16. Output Transistor Structure
9--19
Applications
Reference Regulator,
The internal 5-V reference regulator is designed primarily to provide the internal
circuitry with a stable supply rail for varying input voltages. The regulator provides
sufficient drive to sustain up to 10 rnA of supply current to additional load circuitry.
Excessive loading, however, may degrade the performance of the TIA94 since the 5-V
reference regulator establishes the supply voltage of much of the internal control circuitry .
Current Boosting the 5-V Regulator
Conventional bootstrap techniques for three-terminal regulators, such as the one
shown in Figure 17, are not recommended for use on the TIA94. Referring to Figure 17:
Normally, the bootstrap is programmed by resistor RB so that transistor Q1 turns on as
the load current approaches the capability of the regulator. This works quite well where
the current in the input (through RB) is determined by the load current. This is not
necessarily the case with the TIA94. The input current not only reflects the load current
but includes the current drawn by the internal control circuit, which is biased from the
reference regulator as well as the input rail itself. As a.result, the bias of shunt transistor
Q1 is not controlled by the load current drawn by the reference regulator.
v+
3·TERMINAL
REGULATOR
I - - -...-ILOAD
Figure 17. Conventional 3-Terminal Regulator Current-Boost Technique
Figure 18 shows the bootstrapping technique that is preferred for the TIA94. This
technique provides isolation between 'any bias-circuit load and the reference regulator output
and provides a sufficient amount of supply current without affecting the stability ofthe
internal reference regulator. This technique should be applied for bias circuit drive only
since the regulation of the high-current output is solely dependent on the load.
9-20
VI
Q1
TO
INTERNAL
CKT
RB
BIAS
REFERENCE
-=Figure 18. TIA94 Reference Regulator Current-Boost Technique
Applications of the Oscillator
The design of the internal oscillator allows a great deal of flexibility in the operation
of the TIA94 control circuit.
Synchronizjng
Synchronizing two or more oscillators in a common system is easily accomplished
with the architecture of the TIA94 control circuits. Since the internal oscillator is used
for no other purpose than creation of the sawtooth waveform on the timing capacitor, the
oscillator can be inhibited as long as a compatible sawtooth is provided externally to the
timing capacitor terminal. The internal oscillator can be inhibited by terminating the RT
terminal to the reference supply output.
Master/Slave Synchroniz!Jtion
For synchronizing two or more TIA94s, establish one device, as the master and
program its oscillator normally. Disable the oscillators of each slave circuit as explained
above and use the sawtooth created by the master for each of the slave circuits, tying all
CT pins together as shown in Figure 19.
MASTER
SLAVE
....----e_-- SLAVE
TO ADDT'L
CKTS
Figure 19. Master/Slave Synchronization
9-21
Master Clock Operation
To synchronize the TLA94 to an external clock, the internal oscillator can be used
as a sawtooth-pulse generator. Program the internal oscillator for a period that is 85 %
to 95 % of the master clock and strobe the internal oscillator through the timing resistor,
as shown in Figure 20. Ql is turned on by a positive pulse applied to its base. This initiates
the internal oscillator by grounding RT and pulls the base of Q2 low. Q 1 is latched on
through the collector of Q2 and, as a result, the internal oscillator is locked on. As CT
charges, a positive voltage is developed across Cl. Ql forms a clamp on the trigger side
of C 1. At the completion of the period of the internal oscillator, the timing capacitor is
discharged to ground and C 1 drives the base of Q 1 negative, causing Q 1 and Q2 to tum
off in tum. With the latch of QI/Q2 turned off, RT is open circuited and the internal
oscillator is disabled until another trigger pulse is experienced.
,..----------VREF
~.....'VV'I__-
01
RT
.._
n --It------tt-~t
-C-T CT
Figure 20. External CIO(:k Synchronization
A common problem when synchronizing the power supply to a system clock occurs
during start up. Normally, an additional start-up oscillator is required. Here again, the
internal oscillator can be used by modifying the previous circuit slightly, as shown in
Figure 21. During power up, when the output voltage is low, Q3 is biased on causing
Ql to stay on and the internal oscillator to behave normally. Once the output voltage has
increased sufficiently (VO > VREF for Figure 21), Q3 is no longer biased on and the
QlIQ2 latch becomes dependent of the trigger signal, as previously discussed.
9-22
. . . . - - - - - - - - - VREF
Vo
Figure 21. Oscillator Start-Up Circuit
Fail-Safe Operation
With the modulation scheme employed by the TlA94 and the structure of the
oscillator, the TlA94 will inherently tum off if either timing component fails. If timing
resistor RT opens, no current is provided by the oscillator to charge CT. The addition
of a bleeder resistor, as shown in Figure 22, assures the discharge of CT. With the CT
input at ground, or if CT short circuits, both outputs are inhibited.
RT
~RT
,~
:1 fey ey
Figure 22. Fail-Safe Protection
Error-Amplifier-Bias Conf"JgUraton
The design of the TlA94 is aligned to employ both amplifiers in a noninverting
configuration. Figure 23 illustrates the proper bias circuits for negative and positive output
voltages. The gain control circuits, shown previously in Figure 11, can be integrated into
the bias circuits.
9-23
OUTPUT
R1
Vo - VREF (I+R2)
R1
VREF
R1
R2
"::"
R2
R1
VO" -IVREF-I
R2
VREF
OUTPUT
POSITIVE OUTPUT CONFIGURATION
NEGATIVE OUTPUT CONFIGURATION
Figure 23. Error Amplifier Bias Configurations
Current Limiting
Either amplifier provided on the TLA94 can be used for current Ijmi$g. Application
of either amplifier is limited primarily to load current control. The architecture of the
TLA94 defines that these amplifiers be used for dc control applications. Both amplifiers
have a broad common-mode voltage range which allows direct current sensing at the output
voltage rails. Several techniques can be employed for current limiting.
Fold-Back Current Limiting
Figure 24 illustrates the proper bias technique for f,?ld-back current limiting. Initial
current limiting occurs when sufficient voltage is developed across RCL to compensate
for the base-emitter voltage of Q I plus the voltage across RI. When current limiting occurs,
the output voltage will drop. As the output decays, the voltage across RI decreases
proportionally. This results in less voltage required across RcL to maintain current limiting.
The resulting output characteristics are illustrated in Figure 25.
RCL
-:r:-
R1
Figure 24. Fold-Back Current Limiting
9-24
Vo
7
~--------~------~---'LOAD
'K _ Vo R1 + VBEIQ111R1 +R21
RCL R2
,
_ VBEIQ111R1 + R21
SC
RCL R2
Figure 25. Fold-Back Current Characteristics
Pulse-Current Limiting
The internal architecture of the TIA94 is not aligned to accommodate direct pulsecurrent limiting. The problem arises from two factors: 1. The internal amplifiers do not
function as a latch, they are intended for analog applications. 2. The pulse-steering flipflop sees any positive transition of the PWM comparator as a trigger and toggles its outputs
prematurely, i.e., prior to the completion of the oscillator period. As a result, a pulsed
control voltage occurring during a normal on time not only causes the output transistors
to tum off but also toggles the pulse-steering flip-flop. With the outputs off, the excessive
current condition decays and the control voltage returns to the quiescent-error-signallevel.
When the pulse ends, the outputs are again enabled and the residual on-time pulse appears
on the opposite output. The resulting waveforms are shown in Figure 26. The major problem
here is the lack of dead-time control. A sufficiently narrow pulse may result in both outputs
being on concurrently, depending on the delays of the external circuitry. A condition where
insufficient dead time exists is a destructive condition. Pulse-current limiting, therefore,
is best implemented externally, as shown Figure 27.
The current in the switching transistors is sensed by RcL. When sufficient current
is experienced, the sensing transistor QI is forward biased, the base of Q2 is pulled low
through Qt, and the dead-time control input is pulled to the 5-V reference. Drive for the
base of Q3 is provided through the collector of Q2. Q3 acts as a latch to maintain Q2
in a saturated state when Ql turns off, as the current decays through RcL. The latch will
remain in this state, inhibiting the output transistors, until the oscillator completes its period
and discharges CT to 0 V. When this occurs, the Schottky diode, DI, will forward bias
and turn off Q3 and Q2, allowing the dead-time control to return to its programmed voltage.
9-25
r~~~T~Q1
PULSE SIGNAL RESPONSE
CONTROL:
' LOGIC ! - C O 2
DEAD-TIME
CONTROL
L ___ .J
ERROR
SIGNAL - - - - I
CONTROL SIGNAL
CONTROL
SIGNALI
CT
lz::?v4Jhv4/1v Jrv:1
EXPECTED OUTPUTS
Q1
Q2
tu
,<-____
_.."
__-_-_--l,........r_-_-_-_-_·_-_".=,i~-_-_-_-_-.
_
LL_..1
4J
ACTUAL OUTPUTS
Q1
02
tJ
t.
U I
I U
lD
0
Figure 26. Error Signal Considerations
. SWITCHING
CIRCUIT
DEADTIME
CONTROL
RCL
Figure 27. Peak-Current Protection
9-26
[
Applications of the Dead-Time Control
The primary function of the dead-time control is to control the minimum off-time
exhibited by the output of the TIA94. The dead-time-control input provides control from
5% to 100% dead time, as illustrated in Figure 28.
r- - OUTPUT
CONTROL
LOGIC
~
I
~
~
I
DEADTIME --I
CONTROL
5% DEAD TIME
CONTROL
INPUT
OUTPUT
Figure 28. Dead-Time Control Characteristics
The TIA94 can therefore be tailored to the specific power transistor switches that
are used to assure that the output transistors never experience a common on-time. The
bias circuit for the basic function is shown in Figure 29. The dead-time control can be
used for many additional control signals.
9-27
R1
_ _ _ D.T.C.
IN
TD - RT CT (0.05
R2 In kO
R1 + R2 - 5 kO
+
0.36 R2)
R2
Figure 29. Tailored Dead Time
Soft Start
With the availability of the dead-time control, input implementation of a soft-start
circuit is relatively simple; Figure 30 shows one example. Initially, capacitor Cs forces .
the dead-time-control input to follow the 5-V reference regulator which disables both
outputs-, i.e., 100% dead time. As the capacitor charges through Rg, the output pulse slowly
increases until the control loop takes command. If additional control is to be introduced
at this input, a blocking diode should be used to isolate the soft-start circuit. If soft start
is desired in conjunction with a tailored dead time, the circuit in Figure 29 can be used
with the addition of capacitor CT across resistor RI.
The use of soft-start protection is recommended. Not only does such circuitry prevent
large current surges during power-up, it also protects against any false signals which might
be created by the control circuit as power is applied.
DEAD-TIME
CONTROL
Figure 30. Soft-Start Circuit
Overvoltage Protection
The dead-time control also provides a convenient input for overvoltage protection
which may be sensed as an output voltage condition or input protection. Figure 31 employs
a TIA30 as the sensing element. When the supply rail being monitored increases to the
9-28
point that 2.7 V is developed at the driver node of Rl and R2, the TlA30 goes into
conduction. This forward biases QI, causing the dead-time control to be pulled up to the
reference voltage, disabling the output transistors.
MONITORED SUPPLY RAIL
r - - -....- - vREF
R1
DEAD-TIME
CONTROL
R2
n430
Figure 31. Overvoltage Protection Circuit
Modulation of Tum-Off Transition
Modulation of the output pulse by the TlA94 is accomplished by modulating the
turn-on transition of the output transistors. The tum-off transition is always concurrent
with the falling edge of the oscillator waveform. Figure 32 shows the oscillator output
as it is compared to a varying control signal and the resulting output waveforms. If
modulation of the turn-off transition is desired, an external negative slope sawtooth, as
shown in Figure 33, can be used without degrading the overall performance of the TIA94.
VOlTAGE/
CONTftOL
INTERNAL
OSCILLATOR
k~
I
OUWUT
~
I
I
---'
~
OFF
~
_ _ CONTROl
VOLTAGE
~l
_____________",--t=_
I
p~_~h
ON
(ON TRANSITION MODULATEDI
Figure 32. Turn-On Transition
9-29
CONTROL
VOLTAGEI
INTERNAL
OSCILLATOR
I
I
OFF
OUTPUT
I
I. . . . .~D_____I ___..1___
I ~L
ON
(OFF TRANSITION MODULATED)
Figure 33. Turn-OtT Transition
Designing Switching Voltage Regulators
with TL497A
John Spencer
Linear IC AppUcatjons Eosinee.
LINEAR PRODUCTS DEPARTMENT
INTRODUCTION
The TL497 represents a revolution in the impleinentation of
a monolithic, highly efficient switching regulator.
Conventional series regulators employ an active
element, usually a transistor operating in a linear mode,
which functions as a variable resistor. The product of this
resistance and the load current create a changing differen·
tial voltage required to step down from an unregulated
input voltage to a fixed output voltage. In this type of
circuit, current 'requirements defined by the load, must be
experienced by the pass element. As the input to output
voltage differential or load current requirement increases
the power dissipated in the pass element increases proportionally. This power represents a loss to the system and
limits the efficiency of series regulators.
The switching regulator, on the other hand, does not
operate in the linear mode and is capable of achieving hi~
efficiency power conversion even at large input/output
voltage differentials. In the past the complexity of the
circuitry required to construct a switching regulator
negated the advantage of efficiency gained over series pass
regulators. Use of the TL497A, however, eliminates the
complex circuit designs previously required and offers
marked performance improvements in efficiency over
systems using series pass regulators.
PRINCIPLE OF OPERATION
The principle of operation and the method by which
voltage conversion at high efficiencies can be achieved using
switching regulators can best be demonstrated by analyzing
the basic, configuration of a step-down switching voltage
regulator (Figure 1).
Ql is the switch transistor which is turned on and off
by the regulator's ~ontrol circuitry at a frequency and duty
cycle required to maintain the desired output. Because this
transistor is always in the saturated state when it is
conducting, or otherwise completely nonconducting, the
power diSsipated in the switch is much lower than that
dissipated in a series regulator whose pass transistor is
continuously operated in the linear region_ This is the
primary contributor to the increased efficiency experienced
Eugene J. Tobaben
Linear IC AppUeationB Engineer
LINEAR PRODUCTS DEPARTMENT
L
FIGURE 1. Step-Down Switching Voltage Regulator
with a switching voltage regulator. The transfer of energy
from the input to the output is achieved through the
inductor L. During the time Q I is on (ton) the input
voltage is applied to the LC filter and the current in the
inductor increases_ When Q 1 is turned off the energy
developed in the inductor during the previous half cycle,
maintains the current flow to the load through the catch
diode D I and delivers that energy to the load_
The output voltage is determined by the input
voltage (VIN) and the duty cycle of the switch Q I.
VOUT = VIN toN
T
where T = tON + tOFF
Therefore, by controlling the duty cycle (ton/T), changes in
the input voltage can be compensated for. If VIN increases,
the control circuit will cause a corresponding reduction in
the duty cycle and thereby maintain a constant VOUT,
without increasing the amount of power dissipated
internally in the regulator.
THETL497A
General
The TL497A incorporates on a single monolithic chip
all the active functions required in the construction of a
Switching Voltage Regulator: a preciSion lo22-volt reference, a pulse generator, a high-gain comparator, current
limit sense and shut-down circuitry, a catch diode, and
a series pass transistor. The TL497A was designed to
offer versatility and to optimize the ease of its use in the
various step-up, step-down, and voltage inversion applications requiring high efficiency.
9-31
r----..
L
-"Y"'It"\... .-~~OVOUT ...
R2
TL497A
1-___
FIGURE 2. TL497A Block Diagram
v
Programming
A block diagram of the TL497A is shown in Figure 2.
The internal 1. 22-volt precision band-gap reference is
internally connected between the substrate terminal and
the inverting input of the high-gain comparator. The output
of the circuit is sensed through a resistor ladder-network
(Rl-R2) by the noninverting input of the comparator and is
programmed by the resistors R I and R2 such that the
feedback voltage equals the 1.22 volt reference. Thus;
R2
VOUT RI + R2 = 1.22 volts
To keep it simple the voltage across R2 is 1.22 volts. For
lniA programming current R2 becomes 1.22 Kn. Therefore:
SET
R2= 1.22 Kn
AND CALCULATE Rl
=(VOUT -
1.22) Kn
Oscillator
The oscillator is composed of a current pulse generator which charges and discharges the external timing
capacitor (Ct} at fixed current rates whenever the feedback
voltage is less than 1.22 v. The charging rate is 1/6
that of the discharge rate which results in - the voltage
waveform shown in Figure 3. The total period of the
charge/ discharge cycle is determined by the external timing
capacitor (Ct} and-is constant for all input voltages within
the T1A97 A recommended operating ranges.
The charge/discharge period (T) varies with Ct as
shown in Table I.
./
FIGURE 3. Ct Voltage Wavefonn
The dotted line of Figure 3 shows the timing
capacitor waveform under continuous operation conditions.
Only under these conditions does T determine the oscillators frequency (Fmax =lIT). These conditions exist during
initial power-up of the system or whenever the comparator
indicates the output voltage is less than the desired
voltage-out. After the timing capacitor is discharged, the
oscillator control circuit will sample the output of the
comparator to determine if the output voltage is at a
satisfactory level. If the comparator indicates the output is
deficient, the current generator will retrigger and the
oscillator will go through another Ct charge/discharge cycle;
after which it will sample the comparator again and so
forth. If on the other hand, the comparator indicates the
output voltage is satisfactory, the current generator will be
on standby until it is triggered by the comparator as
illustrated in Figure 4. The pass transistor is turned "ON"
during the charging portion (te) and turned "OFF" during
the discharge portion (tn) and any subsequent standby
Tabla I. Charge/Discharge Period Vs. Ct
Ct (pFI
T (I'sl
9-32
"\
./ ...... \
200
250
350
400
500
750
1000
1500
2000
23
27
32
39
50
70
95
140
230
~A/J
?--f1
?-+-\
~
'c
I
I
I~
I
.
I
I
I
I
I
I
:
I
I
I
I
VPROGRAMMED~______________~~~__________~~~~~__~:'~~~______~__~~____
I
I
VOUT
~~
______________
I
I
I
I__________________________________________________
~I
I
~START-UP------.~.....t-----QUIESCENT
OPERATION---------
I
FIGURE 4. Typical Ct Voltage Waveform During Start-Up and Quiescent Operation
Table II. On-Time Vs.
Ct
Ct (pF)
200
250
350
400
500
750
1000
1500
2000
tc (".1
19
22
26
32
44
56
80
120
180
period after the charge/discharge cycle of Ct. Under these
conditions the operating frequency becomes dependent
on the load requirement and Or only determines the ON
time (tON) which remains constant. Thus the duty cycle
is modulated by the changing frequency. The on-time of
the switching transistor coincides with tc as shown in
Table II.
Current Limiting
Current limiting is accomplished with the currentlimit control provided. The voltage developed across the
user selected series current limit resistor (ReO is sensed.
When this voltage becomes greater than one VBE drop
(0.5 V typically) the current limit circuitry provides an
additional current path to charge the timing capacitor. This,
in effect, shortens the on-time of the switching transistor
and reduces the amount of energy developed in the
inductor. This can be observed as an increase in the slope of
the charging portion of the charge/discharge cycle of the
timing capacitor (Figure 5). With current limiting, saturation of the power inductor may be prevented and soft
start-up achieved. If not used, the current limit sense
should be tied to Vcc + (pin-14).
Pass Transistor
The switching transistor provided in the TL497A is a
high-gain device designed to switch up to 500 rnA peak
using the base drive circuitry provided by the TL497A.
Access to the internal base current iimiting resistor is made
available, however, it is not recommended the base drive
circuitry be tampered ·with. The emitter and collector are
brought out also, for user versatility.
'\;,.EFFECT OF CURRENT LIMITING ON C,
_"\
VOLTAGE WAVEFORM
VTH -
-
-- - -
-;~:-;l\:-:I~E:i~~
,,"
\
WAVEFORM
\
\
~~-----------r-....L--~--~--T
FIGURE 5. Ct Voltage Waveform
Catch Diode
An uncommitted catch diode capable of operating
at peak currents to 500 rnA is available for commutation
and blocking purposes, however, an external diode may
be desired for optimum circuit performance.
Enable Circuitry
Shutdown circuitry is provided for external control
which allows the user to enable and disable the TL497A by
an external TTL logic command. A logic high disables the
TL497A and turns off the switching transistor. A logic low
enables the TL497A and allows it to operate according to
the previous discussion.
9-33
DESIGN AND OPERATION
ofa
STEP-DOWN SWITCHING VOLTAGE REGULATOR
The circuit in Figure 6 shows the; basic configuration
for a step-down switching voltage regulator. A thorough
understanding of this circuit is necessary to optimize the
design of a step-down switching voltage regulator using the
TL491A.
81
For a constant VIN, VOUT, and L, I varies linearly with t.
The current increases while S 1 is closed according to
the waveform shown in Figure 7. The peak current in the
inductor, therefore, is dependent on the period of time 81
is closed, which is the on-time of the switch (tON).
. I = Vin-Vout tON
.. pk
L
L
IPK~
___ L
.i
FIGURE 6. Basic Step-Down Regulator
First, define the initial conditions (prior to the
closing of S1).
Initial Conditions (t = 0-):
VC=VOUT
IL=O
When the switch SI is closed, the current in the
inductor and the voltage across the ftIter capacitor (C)
cannot change instantaneously.
at 81 closed (t = 0+):
.(.
SI-j~'---II-·----*l_.
~+
l:TC+
. tD
'c
.~HARGE
DISCHARGE
FIGURE 7. Inductor Cu"ent Wweform
When SI opens (t = tC+), the current through the
inductor is Ipk since the current cannot change instantaneously, the voltage across the inductor inverts, and the
blocking diode (D 1) is forward biased to provide a current
path for the discharge of the inductor into the load and
filter capacitor. The inductor current then discharges
linearly as illustrated in Figure 7.
Prior to SI open (t = TC-)
iL= Ipk
VC=VOUT
Writing a loop equation around the circuit
At SI open (t = TC+)
IL =Ipk
Substituting 11 = 0 and Vc = Vout at t = 0+
Yin = L
Therefore
d/l
dt
d/l
dt
+ YOU!
Writing a loop equation for il
Vf+L
Yin - Vout
=
L
The current through the inductor (it) at any given time (t)
is
Vin- Vout
1=
L
t
9-34
VC=VqUT
dil
lit
+VC=O
Substituting the conditions at t = TC+ and assuming Vf of
D1 isOV:
L
dil
dt
=-VOUT
:. the current through the inductor for t > TC
IpK -ILOAD
B_
1.1'
The discharge time of the inductor then is that time
required for it = O. Therefore
to=
IpK-:r:D T
bP,~~~~~.c---~
ILOAD -t-- --------- --f---
Vour .
iL=Ipk- - L - (t-Te)
Tc+tO
jL
I
FIGURE 9. Capacitor Cumnt Waveform ( AQ+)
Ink
-=L
VOUT
Analyzing for a moment the currents at the inductor/
capacitor/output node.
FIGURE 10. CapaCitor Cu"ent Waveform ( AQ-)
iL =Ie +lload
B = Ipk - Iload (1: + t )
Ipk
e
0
if lload is considered constant.
/lie
=AiL = Ipk
AOt
when
it =[load; ie = 0
when
iL =0; ie = -lioad
=1.. (Ipk- IIoad)2
2
AQ- = [lload til +
Thus the inductor and capacitor current waveforms
relate to each other as shown in Figure 8.
-
IPK~
,,
IL
(TC + to)
lpk
t
[(Te + to)
l
Ipk - lload
Ipk
(Te + to)J lload
Setting AOt equal to /lQ- and solving for ti
'
IINDUCTOR CURRENT)
o
~
t
,
t. - (Ipk - 2Iload)(TC + to)
12110ad
40.
1"-'LOAD~2f=:s-
Ie
(CAPAt;ITOR CURReNT~
4Q_=="
'LOAD •
-'
.........., ___.....;_...J1
TC
FIGURE 8. Inductor Current and
Capacitor Cu"ent Waveforms
For the output voltage to remain constant, the net
charge delivered to the filter capacitor must be zero. This
means that the charge delivered to the capacitor from the
inductor must be dissipated in the load. Since the charge
developed in the inductor is fixed (constant on time), the
time required for the load to dissipate that charge will vary
with the load requirements. The actual operating frequency
is therefore dependent on the load requirements. The actual
frequency can be determined by studying the current
waveform of the filter capacitor. The charge delivered to
the capacitor and the charge dissipated by the load are
equal to the areas under the capacitor current waveform
above and below ie =0 respectively, as shown in Figures 9
and 10.
To determine the frequency of oscillation, total the
durations of the previous portions of the regulator'S cycle,
T=TC+tD+ti
1 ~II
:.T=(TC+ tD)-2
k
load
Knowing the period
frequency =
1
T
The AQ calculations also yield the voltage change experienced by the output capacitor C.
Vc = lridt or AQ
C
C
A V =.!.. (Ipk - Iload)2 TC VIN
C 2C
Ipk
VOUT
Note this accounts for the ripple voltage contributed by the
ripple current present in the switching regulator seen by
an ideal capacitor. Realistically the capacitor will have an
equivalent series resistance (ESR) which establishes the
minimum ripple voltage achievable.
9-35
When the' filter capacitor s~e has been fucreased such
that. f1VC '::! VRIPPLE (MIN) addit:\onalfucreases in C
will net fusignificant reduction fu VRIPPLE. It is important therefore to employ a filter capacitor with mfuimal
BSR. Note, however, due to its architecture some ripple'
voltage is required for proper operation of the regulation
circuit.
Where Ix is the load current at which the fuductor current
is continuous and the regulator enters the continuous
mode.
FIGURE 11. Capacitor Current Waveform
SUMMARY
The previous derivations have assumed that the
regulator is operating in the discontfuuous mode. This
means the fuductor current is discontinuous (IL =0). When
the load is continually increased, the idle time (tj in
Figure 10) decreases to the pofut where the regulator
initiates a charge cycle at or before the complete discharge
of the fuductor. This condition is called the continuous
mode of operation (IL never equals 0, ti =0). In this mode
a dc idle current is passed through the fuductor. The
TL497A is not designed to operate fu this mode Without
special considerations given to the circuit design. To
determine the load current where the circuit transforms
from the discontinuous mode to the contfuuous mode of
operation, refer to Figure 8. The point of transition occurs,
when the inductor starts charging as soon as it completes
the previous discharge, cycle Hi = 0). Under these conditions the capacitor current waveform is as shown fu
Figure Il. Setting ti = 0 and solving for lOUT;
(Continuous Mode)
Summarizing:
for the step-down switchilig regulator
Ipk;' 2 Iload (for discontinuous operation)
L = VIN - VOUT tON
Ipk
f
where:
- 2 Iload
o-
tD=
lpk
VOUT
TON VIN
Ink
-==L
VOUT
1; =[Ipk - 2 Iloadl
2IIoad
Ink
IOur= -=:.
2
Hence
Ix =
!.I!!.
2
C
= (Ipk -
Iload)2
VRIPPLE 2 lpk
TONVIN
VOUT
TONVIN
VOUT
A STEP-DOWN SWITCHING REGULATOR
To program TL497A for 5 VOUT:
DESIGN EXERCISE
with
R2= 1.2kn
(fixed)
TL497A
Rl = (5 - 1.2) kn = 3.8 kn
A schematic of the basic step-down regulator is
shown in Figure 12.
To set current limiting:
~N~----~~-----,
RcL = 0.5/Ilimit
On
0.5
-
-1
",-L - 500 X 10-3 -
n
For the on-time chosen above, Ct can be approximated;
Ct (pO
FIGURE 12. Basic Step-Down Regulator
~
12 tON (p.s)
Ct ~240 pf
or it can be selected from Table II, page 5.
Conditions:
To determine Cfilter for desired ripple voltage:
VIN=15V
C - (Ipk - Iload)2 . TON VIN
VRIPPLE2 Ipk
VOUT
VOUT=5V
lour =200 rnA
Vripple < 1.0%
for constant C, VRIPPLE increases as Iload descreases.
C = 45 p.F (for 200 mAIl % ripple)
Calculations:
The maximum operating frequency is encountered under
maximum load conditions.
Ipk ;> 2 Iload = 400 rnA
This is the limit condition for discontinuous operation. For
design margin, Ipk will be designed for SOO rnA which is
also the limit of the internal pass transistor and catch diode.
f
_ 2 Iload (max). VOUT
max Ipk
TON VIN
The minimum operating frequency occurs under minimum
load conditions.
:. Ipk ... 500 rnA
Iload (min)
mm - max lload (max)
f . - f
VIN- VOUT
L=
I
tON
pk
L=
10V
t
500 X 10-3 ON
<
<
Recommended on-time is; 19 p.s toN
150 p.s, thus the
range of acceptable inductance is, 380 lIB to 3 mHo
choosing L = 390 p.H
390 X 10-6 X 500 X 10- 3
toN = .
10
19.5 X 10-6 sec.
Figure 13 illustrates the regulator with the above
values applied to it.
Waveforms at Ct for indication of proper circuit
performance are shown in Figure 14.
For peak currents greater than 500 rnA, it is
necessary to use an external transistor and diode. Several
techniques are shown in Figure 15.
Figure 16 shows the TL497A in high-voltage-highcurrent applications.
9-37
"","
~N o-----~----------------~~~----------,
C16V)
VOlTt-SV
'OUT = 200 rnA
Vripple < 60 mY
E,Iy- 65%
TL497A
3.8k
....
IIN=105mA
PIN "'1.S7W
ACTUAL TIMES: toN· 18pI, tD" lep50 ti" 3,..$, '0 -18kHt
NOTE: 13 III ON-TIME RESUL11 IN I.... 433 ntA. RECALCULATING tD.'i AND fa WILL CONCUR
WITH ACTUAL TIMES OBSERVED.
FIGURE 13. 15 Volt to 5 Volt Switching Regulator for Output Currents to 200 rnA
~
.) CORRECTCtWAVEFORM
ton "'16~1
r:CLl
C
VON~O~L
TL497,""TH EXT£RNAt.
I\IfIN PA!SS TRANSISTOR.
20",_
1TU97A _
LOMOTEDTOy,.<16V
,
T
YOUT
,.,
COMPARATOR INPUT tPiN 11 IS
~~_~_a
• READIlCTIONIONVOLTAGE
COMPARATOR AND DEStaN
VARIATfONS' FOR IMPIfOYED
PeRFORMANCE.
[fjji fT-
ct:.INCriRMREC'AVEFORM
~;;:E?~:~
~
•
•
'bl
lNCREASEC.
DeCREASE LOAD
DeCREASE L
='PEAK
WILL INCREASE.
Y,.'o-.....>-------.......
11.4t7 WITH EXTERNAl.
PM' PASS TRANSISTOR
AND 11 V REGULATOR
FOR APPLICAllONS
VIN>15V:
,,
,""\
\
THE RESULT WILl,. BE A SHORTENED
ON·TIME WHICH MAY RESULT IN
CONTINUOUS MODE OPERATION, ALSO
\
\
\
\
\
..
\
\
.
DECREASE RCL
INCREABEL
OECREASE Ct
4d) CI RCUIT IS CURREN1' LIMITING.
FlGURE 14. Orcuit Performance Waveforms
FlGURE 15. TechniquesforObtainingPeak
Currents Greater Than 500 rnA
30 VOLTS TOSV
ILOAO· 2.SA
®
0.1 n
100n
Q1
.....u:
r-
3.Bkn
'='
1.2kn
TL497A
VOUT=SV
lOUT = 2.5 A
POUT 12.5W
Vrjpple 0.2 V
=
=
VIN=30V
'IN-600mA
PIN =18W
EFFICIENCY
=70%
ACTUAL TIMES: t., = 20 "', tD - 80 "', tj • 10 //,S, f • 9.1 kHz
® THE USE OF THE INTERNAL DIODE (PINS 8 AND 71 TO CLAMP THE FEEDBACK
AND PROTECT AGAINST NOISE IS DISCUSSED IN A LATER CHAPTER (DESIGN
VARIATIONS FOR IMPROVED PERFORMANCE).
FIGURE 16. TL497A in High·Voltage-High·Current Applications
9-39
The advent of logic or gate array devices brings
about the need of a good regulated low voltage power
supply. These arrays may hilve up to 800 inverters or
gates per array. Normally the power requirements are 20
volts at about 200 rnA, per array. The input requirement
is usually 5.0 volts. This circuits meets the above requirements at an overall efficiency of 72%.
+
Figure 18 is another step-down regulator. With an
input of from 7V to 12V it ha,s an output of 5 volts at 2.0
amps. The TIP34 is a plastic TO-220 PNP transistor of 10
amp capacity. The INSI87D- is a 3.0 amp fast recovery
diode.
lso,.H
IICL
0.1
6VIN~o------------1~~~-----'
470
111
'10
112
Uk
-
NOTE - ADD,,,,,, CAPACITOR AT THE INPUT AND
OUTPUT FOR IMPROVED TRANSIENT
RESPONSE AND BETTER RIPPLE REJECTION.
FIGURE 17. TL497A Logic Ami)' Power Supply, Step-Down Circuit
VOUT
VIN
7V·TO·12V
5V
+
+
O.Hl
IN5187D
14
1000pF
150pF
TL497A
1.2K
3.8K
FIGURE 18. Step-Down Regulator
9-40
DESIGN AND OPERATION
ofa
STEP-UP SWITCHING VOLTAGE REGULATOR
In the step-up regulator, the formulaes change
slightly. Note the basic circuit configuration in Figure 19.
r--'
v'{L..-_i_L---..1_S1_i_ClI
_ _ _ _~~
01
r------'~......~1t--it>l
Iload
Studying the current waveforms (IL and IC) and
recalling AQt must equal AQ- for the potential across the
load capacitor to remain constant, the relation of peak
current to load current can be determined. Approaching it
as AQ is the area· under the respective curves, maximum
load current for discontinuous operation (ti = 0) relates to
the peak current as:
_ Ipk tD
Iload - 2 (tD + tt)
FIGURE 19. Basic Step-UP Regulator Circuit
During the charging cycle (S 1 closed) the inductor
(L) is charged directly by the input potential.
.
'L=
VIN
L
Peak inductor current can be related to load current
by:
tc
I
thus
Ipk=
VIN
L
pk=
tON
In the step-up application however, the peak current
is not related to the load current as in the previous
application. This is attributed to the fact that during the
inductor charge cycle the blocking diode Dl is reverse
biased and no charge is delivered to the load. The circuit in
Figure 19 delivers power to the load only during the
discharge cycle of the inductor (when Sl is open). The
diode Dl is forward biased and the inductor discharges into
the load capacitor. The potential across the inductor
during this phase of the charge/discharge cycle is
VOUT - VIN. The discharge time of the inductor then
becomes:
t
=
D
_2...::II:::.;oa==d:..,:(,-,tD::..+-.,;tC:.:,)
tD
Ipk
L
VOUT-VIN
To ease calculation of Ipk without prior calculation of tD,
tc and tD may be substituted for by their voltage ratios.
Equating the charge/discharge times (tC/tD), it will be
noted that the charge to discharge ratio is proportional to
the ratio of the input/output differential to input voltage
ratio.
tD =
VIN
tc
VOUT-VIN
t
-t
VIN
D- C VOUT- VIN
To determine the peak current relation to the load
current, review the inductor and capacitor current waveforms shown in Figure 20.
..
setting tD = 1
'
tC=
VOUT- VIN
VIN'
(FOR tJ.V ... 3 VIN' iL
(INDUCTOR C:URRENTI
.. jo--CLOSE.
o
TC
~N~
I
:. Ipk
=2 Iload
[ 1+
VOUT- VIN ]
VIN
'-r---HARGE_-or - r--'~LE
~"'.CHA••E
""'-"-' ~----------~
ie
.
.l.Ot
'.
which reduces to:
VOUT
Ipk =2 Iload VIN
JCAPACITOR CURRENTI
.,.... 0
J%ZI11I/17II~
tI"{l11l1ll1ll1
'_ _ _-'_'-.lQ..
FTGURE 20. Inductor and Capacitor Current Step-Up
Regulator
9-41
From the capacitor current waveform of Figure 20,
the remaining performance factors may be determined.
Setting ~Q+ equal to ~Q- and solving for ti where
Iload < IJoad(max) (ti is not 0).
ti = 2IPIk tD - (tD + tc)
load
Conditions:
VIN=5V
VOUT= 15 V
lOUT
=75 rnA
Vripple
V· 1 - (Ipk - Iload)2 Tn
rlpp e 2 C lpk
< 1%
Calculations:
Summarizing:
Ipk;;;' 2 Iload
~ouil
L
VIN]
For the step-up voltage regulator
Ipk = 2 Iload
Ipk~4S0rnA
t~~
For design margin Ipk -+ 500 rnA
L= VIN tON
Ipk
f
VIN
L= -tON
Ipk
2110ad
O=lpk tn
C - (Ipk - Iload)2 . Tn
Vripple 2 Ipk
Tn
6.
VIN
=toN ~VOUT -
]
VI~
L5
t
- 500 X 10-3 ON
<
<
Recommended on-time is; 19 j.!s toN
ISO /As, thus the
range of acceptable inductance is; 190/AH to 1.5 mH
choosing L '" 200 /AH
A STEP-UP SWITCHING REGULATOR
DESIGN EXERCISE
with
TL497A
To program the TL497:
R2= 1.2 kO
Rl
Figure 21 is the basic step-up regulator using the
TL497A.
=(15 -
1.2) kO =13.8 kO
To set the current limiting:
RcL = 0.5/Ilimit
0.5
RCL= 500 X 10-3
= 10
For on-time chosen above (20 jJ.s) Ct can be estimated;
Ct (pf)
':!!
12 tON (/As)
Ct::=:,240pF
or it can be selected from Table II, page 5.
FIGURE 21.
Basic Step-Up Regulator Using the TL497A
9-42
\,
The nominal operating frequency fO is:
To determine Cfilter for desired ripple voltage
f _ I _ 2IIoad
O-f- Ipk TO
C = (lpk - IloacJ}2 TO
Vripple 2 Ipk
&OUTV~VI~
to=tON
fO = 30 kHz
= 10J.Ls
C= 12.0J.LF
Applying these values to the TL497 A results in a
schematic as shown in Figure 22.
Figure 23 shows another step-up circuit which will
supply 12 volts output at 80 rnA with an input of 5 volts.
2OOJ.LH @
111
VOUT=15V
\ 1'2J.LF
lOUT = 75mA
POUT 1.125W
1.2kll
13.8 kll
EFFICIENCY
=71%
FIGURE 22. 5 Volt to 15 Volt Switching Regulator
,0
-t5 V
I&OJ.LH
o--....- -...~...-"fTlI'----.....- - - -...
r----4I1---4I1---~+'2V
10.8K
47J.LF
+
+
220jJF
1.2K
FIGURE 23. TL497A Step-Up Circuit, 5 V Input to 12 V @ SOmA Output
To simplify calculation of Ipk from Iload;
Ipk =VIN tc
L
DESIGN AND OPERATION OF
SWItCHING VOLTAGE REGULATOR
IN INVERTING CONFIGURATION
The inverting regulator is similar to the step-up
regulator in that during the charging cycle of the inductor,
the load is isolated from the input. The only difference is in
the potential across the inductor during its discharge. This
can best be demonstrated by a review of the basic inverting
regulator circuit (figure 24).
r
.tn_
""iC -
J
Vour ltD
L
VIN
VOUT
Substituting this into the expression for IL max and
simplifying;
Ipk
= 2110ad
( I + JVOUT\)
VIN
The current waveforms in the inverting configuration
look identical to those demonstrated in the step·up
configuration. The same formulaes therefore apply for ti,
IL max (discontinuous) and Vripple.
S1
L
FIGURE 24. /Jasic Inverting Regukltor Orcuit
Summarizing:
For the inverting regulator:
During the charging cycle (S 1 closed) the inductor
(L) is charged only by the input potential.simiiar to the
step-up confIgUration.
Ipk;;;'2Iload
(I
+ JV~\)
VIN
Ipk= LtON
VIN
L= tON
Ipk
Uke the step-up configuration, in the inverting
configuration (Figure 25) the input provides no contribution to the load current during the charging cycle and thus
the maximum load current for discontinuous operation will
be limited by the peak current, in accordance with that
observed in the step-up configuration.
.
.
_ IpktO
IL max (discontmuous) - 2 (to + tc)
The discharge rate (to) however differs due to the
difference in the potential across the inductor during its
discharge which is Vour.
'
t - 2 Iload
O-Ipk
tn
C =(lpk - Iload)2 " TD
Vripple 2lpk·
where:
Rcl
V.No------._.-----,
l'
TL497A
FIGURE 25. Basic Inverting Regullltor
AN INVERTING REGULATOR
DESIGN EXERCISE
with
TL497A
To set the current limiting:
ReL =O.5/Ilimit
Conditions:
Re -
0.5
-1
L- 500 X 10-3 -
VIN=5V
VOUT=-5V
n
For the toN chosen above (20 lis) Ct can be estimated;
lOUT =100mA
Ct (pO
Calculations:
~
12 toN (jls)
:.Ct= 240pF
Ipk;> 2 110ad (1 +
IV~:'
)
or it can be selected from Table II, page S.
To determine Cfilter for desired ripple voltage:
Ipk;;;'400 mA
C = {Ipk - Iloadl 2 . TD
V ripple 2 Ipk
For design margin Ipk -+ 500 rnA
tD=toN~ =20 lis
VIN
L= -tON
VOUT
Ipk
Cfilter = 64 jlF
L-
5
t
- 500 X 10-3 ON
<
<
Recommended on-time: 19 liS
toN
150 liS, thus the
rsnge of acceptable inductance is; 190 IlH to 1.5 MH
The nominal operating frequency fO is:
choosing L
toN
=200 jlH
=20 liS
To program the TL497:
R2=
f - 2 Iload
0- Ipk Tn
fo= 20kHz
1.an
Applying these values to the TL497 A will give results
as shown in Figure 26.
Rl
=(5 -
L2) '" 3.8 kn
9-45
IN4001
1.11
V OUT --6V
VIN~----er--------~~~er----------~
16 V)
TL497A
IOUT-100mA
POUT-500mW
IIN-166mA
PIN=B25mW
Vripple
< 60 mV
Effy = 61%
3.B k
1.2 k
-NOTE - DO NOT USE INTERNAL DIODE IPINs-&, 7) FOR CATCH DIODE ON
AN INVERTING CIRCUIT.
FIGURE 26. +5 Volt to -5 Volt Switching, Regulator
SPECIAL TL497 A CIRCUITS
The following are several TL497A circuits that do
not fall strictly ina step-up or step down categpry but
rather a combination of both types.
Figure 27 is an automotive power supply built to
supply 8.5 volts regulated to power a microprocessor
board. During low voltage conditions (4 volts) it Bcts as a
step-up circuit producing about 11 volts at the positive
side of the 1000 p.F capacitor. When a high voltage
FIGURE 27. 12V To 8.5V Step-Up/Down Circuit
9-46
condition exists (15 volts) it acts as a step-down circuit
still giving about II volts to the capacitor. This II volts
then is regulated to the desired 8.5 volts by a p.A 7885
3-terminal regulator.
Figure 28 is a dual output circuit producing both a
+12V B.nd -12V from a +5 voit input to the supply. While
not supplying a large amount of current it will put out
about 12 rnA of current of each voltage polarity.
FIGURE 28. TL497A Dual Supply
+12 Volts anti -12 Volts From +5 Volts
DESIGN VARIATIONS FOR
UMPROVEDPERFORMANCE
VOUT
R2
Improving Efficiency
The dominant contribution by the TL497A to the
overall efficiency of the switching regulator is tbe VCE
(SAT) of the transistor switch. Recall, the previous sections
have considered the switch to be ideal (VCE (SAT) =0 V),
this is not the case in the real world. As the V CE (SAT)
increases the circuit efficiency decreases. Consider for a
moment tbe basic architecture of the three applications
presented herein (see Figure 29).
INVERTING REGULATOR
Rl = (VIN - 1.5) hFE
Ipk
R2=
10RI
VIN - 1.5
FIGURE 30(b). TL497A With External PNP Switch
For Improved Performance
STEp·DOWN REGULATOR
Improving on Time Stability
The on time is determined by the timming capacitor
(CT) and its associated circuitry. The on time cycle
(charging of Cy) is initiated when the voltage at the feedback input (pin 1) is less than 1.2 volts. During the on time
as the timming capacitor is being charged to its internally
prescribed peak voltage, the error comparator remains
active. If during this period the feedback voltage is
increased above 1.2 volts, the on-time cycle will be
interrupted. This condition can be the result of a noise
spike fed back when the switching transistor turns on;
The resulting Cy waveform is as illustrated in Figure 31.
INVERTING REGULATOR
STEP·UP REGULATOR
FIGURE 29. Basic RegulJztor Architectures
Note in all but the step-up regulator the switching
transistor is applied to the positive input rail. In these
configurations it is impossible to drive the NPN transistor
switch into saturation since its base drive circuit resides
at a potential lower than its collector potential. Improved
performance can be achieved by using an external PNP
transistor driven by tbe internal NPN. (See Figure 30(a, b).)
I
FIGURE 30(a). Step-DownRegulJztor
CORRECT WAVEFORM
INTERRUPTED WAVEFORM
FIGURE 31. CT Waveforms
9-47
Note the appearance of the charging ramp of the CT
waveform. It can appear as a few easily defined steps or as
numerous, almost undetectable, smaller steps.. Another
evident condition of the presence of thiS problem is a jittering on time. This severely degrades tbe efficiency of tbe
converter circuit as power is lost during each transition
of the switching transistor. Solution of this problem is
quite simple, clamp the feedback node (pin 1) to less than
1.2 volts during tbe on-time cycle. Figure 32 shows how
this can easily be accomplished witb the addition of a
single feedback diode.
VOUT
The function of tbe feedback diode is simple. When
the on-time cycle is initiated, tbe internal switching transistor turns on. Note tbat in all' three configurations of
Figure 32 the emitter of tbe internal switch is tied to· the
substrate pin [ground or VOUT (-)J. When the internl!i
switch. turns on, the feedback diode is forward biased and
tbe feedback signal is clamped at approximately 0.8 volt
(VCE (SAT) - 0.3 V, VF - 0.5 V), which is less than the
1.2 volts reference. Voltage spikes or noise appearing at tbe
output' will not be reflected at pin 1 as the diode
clamp holds the feedback at 0.8 volt. Thus a clean on-cycle
will result. At the conclusion of the on cycle, the internal
switch turns off the diode reverse biases and the feedback
voltage returns to its voltage prescribed by the resistor
ladder and VOUT. If not used as the flyback diode the
internal diode is quite satisfactory for this application.
Ringing
An oscilloscope is a must when building a SWitching
power supply with this or any other circuit. It is good to
fust obtain the correct waveform on the oscillator ramp
(pin # 3). (See Figure 32 and Figure 14.) Next look at the
switched waveform on the collector of switch (pin 10).
See Figure 33. These must be correct or tbe circuit will
not function properly. If ringing is noticed on the switched
waveform (pin 10) it can be reduced by placing a 470 to
1000 ohm resistor directly across the inductor to more
rapidly dump the coil current when tbe switch is off.
STEP..I)OWN REGULATOR
PIN 1
SWITCHEO
WAVEFORM
PIN NO. 10
INVERTING REGULATOR
VOUT
OSCILLATOR
WAVEFORM
PIN NO. 3
PIN 1
STEP·UP REGULATOR
FIGURE 32. Basic Regullltor with Feedback Diodes
FIGURE 33.
EXTENDED VOLTAGE OPERATION
o-__
It is sometimes desirable to operate the TL497A
from a voltage higher than the maximum voltage rating
of 15.0 volts as per· the specification. This may be
accomplished with few parts, chiefly a TL783 regulator
and a diode as shown in Figure 34. The TL 783 output
voltage chosen should be lower than the output voltage of
the supply. The TL783 will provide a reference voltage to
the TL497A until the VOU'!' comes up. DFB then forward
biases, thus supplying the TL497A and shutting back the
TL783 regulator. The residual power consumption is only
about 5.0 rnA in the TL 783 circuit.
,-~~~
________________
~~
__--oVOUT
>5V<12V
I
14
1L497A
HV.INPUT
f·:
:
I
!
NOTE·' • SINCE ONLY THE OSCILLATOR SECTION WILL
FUNCTION ON A 3.0 VOLT SUPPLY. THE RE·
MAINDER OF THE CHIP IS INOPERATIVE. THE
COMPLETE CIRCUIT WILL FUNCTION WHEN VOUT
REACHES ABOUT 4.6 VOLTS.
,
DF8
i
!I
FIGURE 35.
l __.... ___ .. ___ .. _ ___ J
OtJT1'UT
SWI1CHING REGULATOR DESIGN TIPS
FIGURE 34;
LOW VOLTAGE OPERATION
In some occasions there is a need to operate from
a voltage lower than the minimum voltage rating of the
TL497A which is 4.5 volts. Since the oscillator will run
with less than 3 volts Vee, regulation may be accomplished
with a circuit similar to Figure 35. With the application
of 3 volts, the diode DPB forward biases furnishing Vee
to the oscillator of the TL497A. This causes the SWitching
transistor to operate and steps the voltage up to its designed
output. (4.5 V - 15 V) Once VOU'!' comes up higher
than 3.0 volts, DFB is reversed biased and Vee to the
TL497A is now furnished by its own output voltage.
The TL497A being a fixed on-time, variable fr&quency device does not need a "HI-Q" type of inductor."
"HI-Q" coils are not desirable due to the TL497A's broad
frequency· range of operation. If the "Q" is too high,
excessive ringing will occur on the output pulse. If when
using a coil with a typical "Q" of greater than I 0 ringing
does occur, a shunt resistance may be placed across the
coil to dampen the waveform.
While not necessary, it is highly desirable to use a
toroid inductor as opposed to a CYlindrical wound coil.
The toroid type of winding helps to contain the flux
closer to the core and reduce the possible radiation from
the supply. A typical inductor of ISO pH inductance and
capable of handling 0.5 amperes of current would have a
D.C. resistance of about 0.6 n. Below is a list of possible
inductor sources.
Care should be used in placement of parts and
routing of ground connections similiar to practices used
in constructing R.F. circuits. These technique's will help
to prevent unwanted oscillations due to positive feedback
or ground loops.
"NOTE: See page 22 for possible inductor sources.
9-49
INDucroR SOURCES-
Reliability, Inc.
P.O. Box 218370
Houston, TX 77218
(71l) 492"()550
Coil Craft
1102 Silver Lake Rd.
Cary,Ill 60013
(312) 639-2361
Mini-Magnetics
453 Ravendale Dr. Unite E
Mountain View, CA 94043
(408) 255-7160
Ferroxcube
5083 Kings Higl1way
Saugerties, N.Y. 12477
(914) 246-2811
Pulse Engineering, Inc.
P.O. Box 12235
San Diego, CA 92112
(714) 279-5900
TRW Inductive Products
Mr. Austin Profeta
150 Variek St.
New York, N.Y.
(212) 255-3500
West Coast Magnetics. Inc.
140 San Lazaro
Surinyvale, CA 94086
(408) 733.9853
MiCrotran Company, Inc.
145 E. Mineola Avenue
P.O. Box 236
Valley Stream, N.Y. 11582
(516) 561-6050
Cambion
445 Concord Ave.
Cambridge, MA 02138
Telex: 92-1480
(617) 491-5400
Soutll Hliven Coil, Inc.
P.O. Box 409 Blue Star Highway
Soutll Haven, Michigan 49090
AC 616 #637-5201
.Texas Instruments. does not endorse or warrant tile
suppliers referenced.
9-50
APPENDIX
Tables I and 2 illustrate the operating range of
the TL497A without the addition of an external power
transistor. Standard inductor values have been used giving
maximum operating frequencies (discontinuous mode) in
the range 9 kHz - 103 kHz. Worst case 'figures for transistor
on-state voltage, VeE (SAT), and diode forward voltage
drop, V f, have been assumed throughout giving a conservatively rated output current, 10 (max), in the majority
of cases.
9-51
O~tput
Input
Voltage
Vin
(VI
Voltage
Vo
Output
Current
Ime~
/vi
(rnA
Power
Transfer
P. ma..
/WI
Feedback
Inductor
Resistors
Rl
R2
L /IlHI
Timing
Capacitor
Ct (pFI
Operatin9
Frequency
f max
(kHzl
150
220
18.9
6
152
143
0.91
4.8K 1.2K
5.0
4.75
12
79
74
0.95
lcl.8K 1.2K
150
220
33
5.0
4.75
15
64
50
0.96
13.8K 1.2K
150
220
35.7
5.0
4.75
18
53
50
0.95
16.8K 1.2K
150
220
38.5
5.0
4.75
24
40
38
0.96
22.8K 1.2K
150
220
40
,5.0
4.75
30
32
30
0.96
28.8K 1.2K
150
220
41.7
5.0
4.75
·5
96
90
0.48
3.8K 1.2K
150
220
30
5.0
4.75
·12
!i7
54
0.68
10.8K 1.2K
150
220
37
5.0
4.75
·24
34
32
0.82
22.8K 1.2K
150
22I'l
41.7
5.0
4.75
The following a_mptiona have been made:
1. Power awiteh operation at maximum peak CUmlnt.
2. Worst ca. transistor and diode COI\duction losses.
3. Use of standard 150"H inductor and 220 pF timing capacitor.
,
\
No-. The 30V and ·24V supplies wUl not give the fuR outpUt in the WOI'St case since the ratio tel te + td exceeds the maximum limit 01 0.85 defined
bythet.C.
Table 1. TL497A Operation from a 5V Supply
Input
Voltage
Vin
(VI
Output
Voltage
Vo
(VI
Output
Current
lmax
!mAI
Power
Transfer
P max
/WI
Feedback
ResistoB
Rl
R2
L (IlHI
Timing
Capacitor
Ct (pFI
Inductor
12
5
250
1.2
3.8K 1.2K
256
220
22.7
12
10
250
2.5
8.8K 1.2K
73
220
45.5
12
15
180
2.7
13.8K 1.2K
439
220
9.8
12
18
161
2.7
16.8K 1.2K
439
220
16.6
12
24
114
2.7
22.8K 1.2K
439
220
24.9
12
30
91
2.7
28.8K 1.2K
439
220
29.8
12
·5
159
0.8
3.8K 1.2K
439
220
14.5
12
·12
114
1.4
10.8K 1.2K
439
220
24.9
12
·24
76
1.8
22.8K 1.2K
439
220
33.2
Nota: Use e standard 220 pI; timing capacitor. The assumptions of maximum peak current operation end
WOBt case transistor and diode losses applv.
, Table 2. TL497A Operatioh from a 12V Supply.
9-52
Operating
Fraquencv
f max
(kHzl
Designing With the TL5001
PWM Controller
~TEXAS
INSTRUMENTS
IMPORTANT NOTICE
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Copyright © 1995, Texas Instruments Incorporated
Contents
Title
Page
ABSTRACT •.••••••••••••••••••••••••••••••••••••••••••••••••••.••••••••••••••••••••••• 9-59
INTRODUCTION •••••••••••••••••••••••••••••••••••••••••••••••.••.•••••••••••••••••••• 9-59
-EXAMPLE 1: 12·V to 5·Vat 3·A STEP·DOWN CONVERTER. • • • • • • • • • • • . • • • • • • • • • • • • • • . • • • • •
Design Criteria. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Specifications ....................................................................
Duty-Cycle Estimates ..............................................................
Output Filter ......... ............... ...................... .................. . .......
Inductor ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Capacitor. . . . . . . .. . . .. . . . . . . . . . . . . . . . .. . . . ... . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
Power-Switch Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Switch ...................... '. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Catch Rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Catch-Rectifier Snubber Network . . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . .. . . . . . . . .. . . . . ..
Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Oscillator Frequency .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dead-Time Control ................................................................
Soft-Start Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
SCP Timing ....... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Output Sense Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Loop Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Summary ...........................................................................
9-(;1
9-61
9-61
9-61
9-61
9-61
9-62
9-63
9-63
9-64
9-64
9-64
9-64
9-65
9-66
9-66
9-66
9-67
9-70
EXAMPLE 2: 12-V to 3.3-V at 3·A STEP·DOWN CONVERTER .••••••••••••••••••••••••••••••
Design Criteria. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . .. . . . . . . ..
Specifications ....................................................................
Duty-Cycle Estimates ..............................................................
OutputFilter ................ .. .. ..... ....... .............. . .......... . . .......... . ..
Inductor .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power-Switch Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Power Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Catch Rectifier. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Catch-Rectifier Snubber Network. . .. . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. ..
Controller Design. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
Oscillator Frequency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Dead-TimeControl ................................................................
Soft-Start Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
SCPTiming ......................................................................
Output Sense Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Loop Compensation. .. .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ..
Summary ..... '... ....... ..... ..... ..... . ........... ........... .... . ..... . .... . .....
9-72
9-72
9-72
9-72
9-72
9-72
9-72
9-73
9-73
9-73
9-73
9-74
9-74
9-74
9-74
9-74
9-74
9-74
9-75
9-55
Contents (Continued)
Title
Page
EXAMPLE 3: 5·V to 3.3·Vat O.15·A STEP·DOWN CONVERTER.............................. 9-77
Design Criteria. . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . ... ... . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. 9-77
Specifications .................................................................... 9-77
Duty-Cycle Estimates .............................................................. 9-77
Output Filter .... ....................... .................. ... ... . ..... ... . .. ... . ..... 9-77
Inductor .................................... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-77
Capacitor ......... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-78
Power-Switch Design. .. . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-78
Power Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-78
Catch Rectifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
Controller Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
Oscillator Frequency ........ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
Dead-TImeControl ................................... ; ............................ 9-79
Soft-Start Timing.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
SCP Timing .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
Output Sense Network. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-79
Loop Compensation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-80
Summary .......................................................................... 9-82
Acknowledgement........... . ...... .. ....... ...... .... ................. ...... ... . ... 9-91
Appendices
Title
Appendix A
9-56
Page
5·V Prototype Board Wavefonns ••.•••••.••••••••.••••••••••••••••.••.••••.• 9-85
Figure
2
3
4
5
6
7
8
9
10
11
12
13
List of llIustrations
Title
Package Layout ...................................................................
Functional Block Diagram ..........................................................
Oscillator Frequency Versus Timing Resistance .........................................
PWM Triangle-Wave-Amplitude Voltage Versus Oscillator Frequency .......................
Uncompensated Open-Loop Response .................................................
Compensation Network ............................................................
Compensated-Loop Response .......................................................
12-V to 5-V at 3-A Converter... ...... . . . . ... . ..... . ..... . . . . .. . . .... . ... . . ..........
12-V to 3.3-Vat 3-A Converter ............ '" .................................... '"
Uncompensated Open-Loop Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Compensation Network ............................................................
Compensated-Loop Response .......................................................
5-V to 3.3-V/0.75-A Converter ......................................................
List of Tables
Title
Table
1
2
3
4
5
6
Example 1: Bill of Materials ...................................................... .
Example 1: Test Results .......................................................... .
Example 2: Bill of Materials ...................................................... .
Example 2: Thst Results .......................................................... .
Example 3: Bill of Materials ...................................................... .
Example 3: Test Results .......................................................... .
Page
9-59
9-60
9-65
9--66
9-67
9-68
9-69
9--70
9-75
9-80
9--81
9-82
9-82
Page
9-71
9-71
9-76
9-76
9-83
9-83
9-57
9--58
ABSTRACT
Electrical and electronic products today are required to be lighter and smaller, use less power, and cost less. Because
of these requirements, manufacturers are turning more and more to small high-frequency dc-to-dc converters for
power-supply solutions. The TL5001 is a pulse-width-modulation (PWM) control integrated circuit, which with a few
external components can be used to implement such converters that can operate at frequencies up to 400 kHz.
INTRODUCTION
The TL5001 integrated circuit incorporates all the PWM-control functions in a compact 8-pin package, including:
•
Oscillator/triangle-wave generator
'
•
PWM comparator with adjustable dead-time control input
•
Open-collector output-drive transistor
•
1-V temperature-stable reference
• Wide-bandwidth error amplifier
• Short-circuit protection (SCP)
•
Undervoltage lockout (UVLO)
In addition, the TL5001 operates over a 40-kHz to 400-kHz frequency range with supply voltages ranging from 3.6 V
to 40 V and typically consumes only 1 rnA of supply current.
This application report demonstrates the design of three simple step-down (buck) converters. The designs include: two
converters operating from 12 V and delivering 5 V at 3 A, 3.3 V at 3 A, and one that operates from 5 V and delivers
3.3 V at 0.75 A, using the TL5001 and a few external components.
D OR P PACKAGE
(TOP VIEW)
O U T D s GNO
Vee
2
7
COMP
3
RT
FB
4
OTC
5SCP
6
Figure 1. Package Layout
9-59
Vee
2
RT
DTe
7
6
OUT
1
IDT
~----~~==~~--~~~-+
FB
4
eOMP~3~------~--------~------~~+---------~
m
.sep-5------------------~------~~e_~
SCP = Short-circuit protection
UVLO = Undervoltage lockout protection
Figure 2. Functional Block Diagram
GND
EXAMPLE 1: 12-V to S-V at 3-A STEP-DOWN CONVERTER
Design Criteria
The schematic of the final design is provided in Figure 8.
Specifications
Input voltage range, VI ......................................................... 10 V to 15 V
Output voltage, V0 ................................................................... 5 V
Output current, Io ............................................................... 0 A to 3 A
Output ripple voltage ............................................................... S; 50 m V
Regulation ............................................................................ 1%
Efficiency ........................................................................ ;:: 80%
Ambient temperature range, TA ................................................... O°C to 55°C
Surface-mount components should be employed wherever feasible. The dcldc converter is implemented with a
continuous-mode, fixed-frequency-PWM step-down converter operating at 200 kHz.
Duty-Cycle Estimates
Before starting the detailed design, it is useful to estimate the duty cycle, D (ratio of the power-switch conduction time
to the period of the operating frequency), for various input voltages. The duty cycle for a step-down converter operating
in continuous mode is approximately:
Where
V d =catch-rectifier conduction voltage (assume V d =0.6 V)
V sat = power-switch conduction voltage (assume V sat = 0.5 V)
The results can be recalculated if actual values are too far from the initial estimate.
The duty cycle for VI = 10, 12, and 15 V is 0.59, 0.49, and 0.39, respectively.
Output Filter
The output filter is a single-stage LC design.
Inductor
Choose the inductance value to maintain continuous-mode operation down to 10% of rated output current.
dI O = 2 x 0.1 x IO(max) = 2 x 0.1 x 3 = 0.6 A peak-to-wak
The ripple current is simply the product of the inductor voltage and ton' the power-switch conduction time, divided by
the inductor value.
dIO
where Ts
=
V ind x ton
Ll
=
VindDTs
Ll
=period of the converter operating frequency.
The inductor voltage during ton is the input voltage minus V sat' the power-switch conduction voltage, minus the output
voltage. Solving for Ll,
Ll =
(VI - V sat - VO)(D) (t)
(15 - 0.5 - 5) (0.39) (5 x 10- 6 )
dI O
=
0.6'
= 30.87
!AH
Because the core is too large, there are not many off-the-shelf surface-mount devices for this design. A 27 -J.IH inductor
(27 turns of 22-gauge magnet wire on a Micrometals T50-26B powdered-iron toroid) was selected because it was readily
available.
9-61
Capacitor
The output capacitor is selected to limit ripple voltage to the level required by the specification. The three elements of
the capacitor that contribute to ripple are: equivalent series resistance (ESR), equivalent series inductance (ESL), and
capacitance. Normally, in designs of this type, it is necessary to provide a great deal of capacitance to get ESR to
acceptable levels. ESL, which can be a problem at high frequencies, can be controlled by choosing low ESL capacitors,
limiting lead length (pcB and capacitor), and replacing one large device with several smaller ones connected in parallel.
Assuming all the inductor ripple current flows through the filter capacitor and the ESR is zero, the capacitance needed
to limit the ripple to 50 mV peak-to-peak is:
C =
~I
0
8 x fs x ~V 0
=
0.6
= 75
(8) (200 x 103 ) (0.05)
.
!IF
Assuming the capacitance is very large, the ESR needed to limit the ripple to 50 mV peak-to-peak is:
~V
ESR = ~ = 0.05·= 83 mQ
MO
0.6
Capacitor ripple current is seldom a problem in low-voltage converters unless a large number of devices are paralleled.
However, to be on the safe side, the rms current is established as:
MO(rms) = 0.6 x 0.289 = 0.17 Arms
The output-filter capacitor(s) should be rated for: at least ten times the calculated minimum capacitance, an ESR 30%
to 50% lower than the calculated maximum, a 0.5-Arms-or-greater ripple-current rating at 100 kHz and 85°C, and a
7.5-V or greater voltage rating.
Use one 220-fJF lO-V OS-CON SA-series device, even though it is ill Ii lead-mounted radial package. The ESR is
35 mQ (at 100 kHz) and the 85°C ripple-current rating is 2.36 Arms. Where package height and/or surface-mount
packaging is critical, two solid tantalum-chip l00-fJF lO-V devices with l00-mQ ESR and l.l-Arms ripple-current
rating from either the AVX TPS series or the Sprague 593D series connected in parallel work well.
9-62
Power-Switch Design
The power-switch design includes: selecting the power switch, catch rectifier, and rectifier-snubbing network (if
needed), calculating power dissipations and junction temperatures, and ensuring the semiconductors have proper heat
sinking.
Power Switch
The design uses a p-channel MOSFET to simplify the drive-circuit design and minimize component count. Based on
the preliminary estimate, lbS(on) should be less than 0.5 V-+-3 A = 167 mO with a IO-V gate drive and the
drain-to-source breakdown voltage appropriate for a 15-V supply. Surface-mount packaging is also desirable.
The IRF9Z34S is a 60-V p-channel MOSFET in a power surface-mount package with lbS(on) =140 rna maximum with
a 10-V gate drive.
Power dissipation, which includes both conduction and switching losses, is given by:
PD
= IJ'X rDS(on)
x D
+ 0.5
x VI x 10 x tr + f X fs
=total MOSFET switching time (turn-on and turnoff) and lbS(on) is adjusted for temperature.
Assuming the drive circuit is adequate for tr+f = 100 ns and the junction temperature is 125°C with a 55°C ambient,
Where tr+f
the lbS(on) adjustment factor is 1.6.
P D = (3 2 )(0.14 X 1.6)(0.59)
P D = 1.19
+ 0.30
+
(0.5)(10)(3)(0.1 X 10-6)(200 X 10 3 )
= 1.49 W
Conduction losses are dominant in this application but may not be in others. It is good practice to check dissipation at
the extreme limits of input voltage to find the worst case.
The thermal impedance RaJA =4Q°CIW for FR-4 with 2-oz copper and a one-inch-square pattern.
TJ =TA + (ReJAx PO) =55 + (40 x 1.49) =115°C
.aacb'9f~~4esignspresentedin this report could.be implemented with bipolar Or MOSFETtfansistors Jl~'thi'
'POwer"sW~tcll, Bipolars are inexpensive and.ca.n performweU in low-voltage applications such as these, but designing
aQriv~cjrcui.tto re~ fueperfoJ:tAance is not It trivial effort. Furtllermore, complex bage..drivesc;h~e$Ca.Ii
~limitl~.mucb".ifnQt.all;ofthe cost.;tdvantage.. M.QS,FETs.were selected for this application ~ecau~.eifue.f#t.
switching· times required for high-frequency operation "are acheived with relatively simPle, 10w-CQmponel,lt~~
the controller design,
·'0 "
gateQii,,~circuits, l;mdthefoc;us iI,l this rep~is
9--63
Catch Rectifier
The catch rectifier conducts when the power switch turns off and provides a path for the inductor current. Important
criteria for selecting the rectifier include: fast switching, breakdown voltage, current rating, low-forward voltage drop
to minimize power dissipation, and appropriate packaging. Unless the application justifies the expense and complexity
of a synchronous rectifier, the best solution for low-voltage outputs is usually a Schottky rectifier.
The breakdown voltage must be 20 V or greater to handle the 15-V input; the current rating must be atleast 3 A (normally
the current rating will be much higher than the output current because the power limits the number of acceptable
devices); and a surface-mount package is extremely desirable.
'
The 50WQ03F is a 5.5-A, 30-V Schottky in a DPAK, power surface-mount package. Care must betaken to ensure that
the rectifier maximum junction temperature is not exceeded. The first step in determining the rectifier junction
temperature is to estimate worst-case power dissipation. Neglecting leakage current and assuming the ripple current in
the inductor is much less than the output current, the catch-rectifier power dissipation is:
PD = 10 x V d x (1 - D)
where Vd is the rectifier conduction drop. Worst-case dissipation occUrs at high line where D is minimum. The
50WQ03F has a maximum forward drop of 0.55 V at a forward current of3 A and a junction temperature of 125°C.
PD
=3
x 0.55 x (1 - 0.39)
=1W
The thermal impedance ReJA = 50°CIW when mounted on FR-4 with 2-oz copper and a one"inch-square pattern.
TJ = TA + (ReJAx PD) = 55 + (50 x 1) = 105°C
Catch-Rectifier Snubber Network
Step-down converters almost universally suffer from ringing on the voltage waveform at the, node where the
power-switch drain, output inductor, and catch-rectifier cathode connect. The ringing, which results from driving
parasitic inductances and capacitances with fast rise-time waveforms, ranges in severity from objectionable to
unacceptable depending on component selection and PCB layout. An RC-snubber damping network in parallel with the
catch rectifier is by far the simplest way to minimize or eliminate the problem. Since deleting components from a
printed-ci,rcuit layout is usually easier than adding them, the safest strategy is to include the network in the initial design
and delete the components if they prove unnecessary.
The initial design is straightforward, but the PCB layout may necessitate component-value adjustments during the
prototype phase. The capacitor value chosen is 4 to 10 times greater than the rectifier junction capacitance; higher values
improve the snubbing but dissipate more power. The 50WQ03F has a typical junction capacitance of 180 pF, and a
snubber-capacitor value should be between 750 pF and 1.8 nE Use C8 = 1.2 nF for convenience. Rectifiers normally
ring in the range from 1 to 50 MHz. Choose the snubber resistor, RIO, for a 50-ns time constant:
RIO
=
50 x 1O~9
C8
=
50 x 10-9
1.2 x 10-9
= 41.7
Q
= Use 43 Q
Because the capacitor is charged and discharged each cycle, the power dissipation in RIO is:
Controller Design
The controller-design procedure involves choosing the components required to program the TL5001 and includes
setting the oscillator frequency, the dead-time control voltage, the soft-start timing, and the short-circuit-protection
timing. The sense-divider network and loop-compensation designs are also addressed in this section.
Oscillator Frequency
Resistance value R1 is selected to set the oscillation frequency to 200 kHz. Select R1
in Figure 3.
=43 ill from the graph shown
1M
Vcc=6V
=
TA 25°C
'
.......
"-
r-.
"'
10k
10k
1M
100k
RT - Timing Resistance -
(.I
Figure 3. Oscillator Frequency Versus Timing Resistance
Dead-Time Control
Dead-time control provides a minimum period of time during each cycle when the power switch cannot be on; i.e., it
limits the duty cycle to some value less than 100%. Even though dead time is not necessary in this application, a small
amount is provided to minimize ,the surge current that would result from a short circuit while the protection circuit is
timing out.
The dead time is set by counecting a resistor, R2, between DTC and GND. A constant current IDT flows out of DTC
generating a voltage, VDT' IDT is controlled by the current IT that flows out ofRT (this current is normally equal to IT,
but varies slightly with frequency and the peak amplitude of V DT). The maximum duty cycle is 0.59. Typically, the actual
duty cycle is set slightly higher to allow for parameter tolerances. For this design, a duty cycle of 0.70 is chosen.
See Figure 4 to find the maximum and minimum ramp-voltage levels, V 0(100%) and V 0(0%); R2 is calculated from the
following expression (RDT, R t in kn, D in decimal):
R2 = (RI
+ 1.25)
[D(VO(lOO%) - VO(O%»)
= (43 + 1.25)[0.7(1.4 -
0.6)
+ 0.6] = 51.3
+ VO(O%)]
kQ
A value of 51 kn is used for R2.
9-65
1.8
VCC=6V
TA=25°C
>
I
1.5
CD
,,~
D)
~
All
~
VO(100%)
1.2
CD
'C
~
is.
E
1;r.
.
..
~
0.9
VO(O%)
0.6
.....
'5l
c
0.3
:;;
~
o
100k
1M
fosc - Oscillator Frequency - Hz
10 k
10M
Figure 4. PWM Triangle-Wave-Amplitude Voltage Versus Oscillator Frequency
Soft-Start Timing
Soft start is implemented by adding a capacitor in parallel with the dead-time control resistor, R2. A start-up time of
5 ms is chosen.
C5
=~=5
R2
x 10-3
51 x 103
= 0.1
!-IF
SCPTiming
, In normal operation, SCP and the timing capacitor, C4, are clamped to approximately 185 mY. Under short-circuit
conditions, C4 is allowed to charge. If the voJtageacross C4 reaches 1 V, the SCP latch is activated and the converter
is shut down. The protection-enable period, tpe' must be longer than the dc/dc converter start-up time, or the converter
will never come up. Because the soft start is designed to bring the converter up within 5 ms, tpe = 75 ms should work
well. C4 is given by (tpe in s, C4 in flF');
C4
=
12.46 x tpe
=
12.46 x 0.075
=
0.935 !-IF => 1 !-IF
Output Sense Network
The output sense network is a resistive divider connected between the converter output and ground with the divider
output connected to the TL5001 FB terminal (referto Figure 6). The dividerratio is chosen for a I-V output (the TL5001
reference voltage) when the converter output is at the desired value.
Establishing the proper divider ratio is critical, but selecting values for the sense network is somewhat arbitrary.
Choosing the values too high can result in converter-output-voltage accuracy problems because the error-amplifier
input-bias current loads the network. Values that are too low can dissipate too much power, drain too much power from
limited power sources such as batteries, or lead to loop-compensation-capacitor values that are too high to be practical.
As a rule, a divider current approximately 1000 times greater than the maximum error-amplifierinput current is chosen.
Resistors with I % tolerances and low andlor reasonably well-matched temperature coefficients are recommended to
minimize the output voltage tolerance.
Because the worst-case TL5001 input bias current is 0.5 !lA, the divider current should be approximately
1000 x 0.5 I1A = 0.5 rnA. In regulation, the voltage across R6 is 1 V and the voltage across R5 is V0 - 1 V = 4 V.
1V
R6
= 0.5 rnA = 2 kQ
R5
=
(VO - 1 V)
0.5 rnA
=
5 - 1
0.5 x 10-3
=
8 kQ
Since they are readily available and provide the right divider ratio, R5
9-66
=7.50 kQ and R6 = 1.87 kQ are used.
Loop Compensation
The loop-compensation design procedure consists of shaping the error-amplifier frequency response with external
components to stabilize the dc/dc converter feedback control loop without destroying the control-loop ability to respond
to line and/or load transients. A detailed treatment of dc/dc converter stability analysis and design is well beyond the
scope of this report; however, several references on the subject are available. The following is a simplified approach to
designing networks to stabilize continuous-mode buck converters that works well when the open-loop gain is below
unity at a frequency much lower than the frequency of operation.
Ignoring the error-amplifier frequency response, the response of the pulse-width modulator and power switch operating
in continuous mode.can be modeled as a simple gain block. The magnitude of the gain is the change in output voltage
for a change in the pulse-width-modulator input voltage (error-amplifier COMP voltage). Typically, increasing the
COMP voltage from 0.6 V to 1.4 V increases the duty cycle from 0 to 100% and the output voltage from 0 V to
approximately 12 V at the nominal input voltage. The gain, ApWM' is:
ApWM
=
!:J.V
!:J.VO
O(COMP)
=(
(12-0)
1.4 - 0.6
) = 15
..
=> 24 dB at nommal mput
Similarly, the gain is 22 dB at low line and 25 dB at high line. Converters with wider input ranges, 2: 1 or more, need
to check for stability at several line voltages to ensure that gain variation does not cause a problem.
The output filter is an LC filter and functions accordingly. The inductor and capacitor produce an underdamped
complex-pole pair at the filter resonant frequency and the capacitor ESR (Rs) puts a zero in the response above the
resonant frequency. The complex poles are located at:
I
1
2n
j(27 x 10-6)(220 x 10-6)
=
2.06 kHz
The zero is located at:
__
1_
2 n RsC
=
1
(2 n)(0.035)( 220 x 10-6)
= 20.7
kHz.
.
Figure 5 includes gain and phase plots of the open-loop response (error amplifier not included) obtained from a simple
SPICE simulation.
40
Ga\n
20
270°
V\
180°
\
ID
"U
I
0
"'-
c
·ii
"
"
I
Phase
-20
1\
-40
10
100
GI
:I
.c
""
II.
I
0°
..a-
_90°
I\.
-60
90°
1k
~
...... f-"
10k
_180°
100k
f - Frequency - Hz
Figure 5. Uncompensated Open-Loop Response
The presence of the complex-pole pair is evident from the resonant peaking in the gain at 2 kHz and the rapid phase
transition in the vicinity of 2 kHz. The zero is hard to see in the gain plot but shows up well in the phase response; the
complex poles provide -180° of phase shift at 20 kHz and the zero adds 45° for a net of -135°.
.9-67
Unless the designer is trying to meet an unusual requirement, such as very wide band response, many of the decisions
regarding gains, compensation pole and ~ro locations, and unity-gain bandwidth are largely arbitrary. Generally, the
gain at low frequencies is very high to minimize error in the output voltage; compensation ~ros are added near the filter
poles to correct for the sharp change in phase encountered near the filter-resonant frequency; and an open-loop
unity-gain frequency is selected well beyond the filter-resonant frequency but 10% or less than the converter operating
frequency. In this instance, a unity-gain frequency (fT) of approximately 20 kHz is chosen to provide good transient
response. Figure 6 shows a standard compensation network chosen for this example.
C1
R4
C3
Vo
C2
........+<
-~---'Vvv---
ToPWM
Figure 6. Compensation NetWork
Assuming an ideal amplifier, the transfer function is:
A (S) = _[
I
ea
S RS(C2
+ CI)
][[S(R5 + R7) C3 + I] (S R4 C2 + I)]
(SR7 C3 + I)[S R4 (CIII C2) + I J
The integrator gain, l/[RS . (C2 + CI)], establishes the open-loop unity-gain frequency. The zeros are located at
approximately the same frequency as the output-filter poles to compensate for the gain reduction and phase shift. The
pole at 1/(21t· R7 . C3) is positioned at approximately the same frequency as the ~ro in the output filter to maintain the
20 dB-per-decade roll-off in the gain response. The final pole at 1/(21t . R4 . CIII C2) is placed at a frequency between
half of the operating frequency and the operating frequency to minimize high-frequency noise at the pulse~
width-modulator input. The last pole is not always necessary but should be included in the design until the need is
established.
The sum of the gains of the modulator, the LC filter, and the error amplifier is 0 dB at the unity-gain frequency. The gain
of the modulatorlLC filter at 20 kHz may be calculated or obtained from a bode plot using straight-line approximations
or from a simple SPICE simulation. As shown in Figure 5, the modulator/filter gain is -12 dB at 20 kHz.
The compensation network has two zeros at 2 kHz to cancel out the LC filter poles. These two ~ros contribute a gain
of 40 dB at 20 kHz; therefore, the gain contributed by the compensation-network integrator needs to be
-28 dB [0-,(-12 +40) =-28]. The imegrator gain of -28 dB translates to a voltage gain of 0.0398.
_--;---;----'1'--_--:-._ == 0.0398 (at fT = 20 kHz)
(2 n:>(rT)(RS)(C2 + Cl)
.
In practice, C2» Cl,
C2=
1
=
1
=0027t-tF
(23t)(fT )(RS)(0.0398)
(6.28)(20 x 103 )(7.5 x 103 )(0.0398)
.
R4 is chosen to position a ~ro at 2 kHz.
R4 =
9-68
1
=
1
= 2.95 kQ
(23t)(f)(C2)
(6.28)( 2 X 10 3)(0.027 X 10-6)
=
Use 3.0 kQ
R7 and C3 are chosen to provide a zero, fZI, at 2 kHz and a pole, fpI, at 20 kHz.
f
f
-
ZI - 2Jt(R5
I
+ R7) C3
[(2Jt)(RS)(C3)]
1
+ [(2Jt)(R7)(C3)]
1
PI - (2Jt) (R7) (C3)
After algebraic manipulation:
(2Jt)(R7)(C3) =
C3
=
R7
=
1 1
fZ-fp
(2 )(R5)
Jt
lP
=
1
(2Jt)(fp )(C3)
[_1 _ _
1 ]
2X10 3 20X10 3
(
3)
(6.28) 7.5 x 10
=
= 0.0096 !IF
1
(6.28)(20 x 103)(0.01 x 10- 6 )
=>
Use C3
= 796 Q
= 0.01 t.tF
=>
Use 820 Q
Cl is chosen to provide the pole, fP2, at 100 kHz. Assuming C3» Cl.
Cl
=
1
(2Jt)(fP2 )(R4)
=
1
(6.28)(100 x 10 3)(3000)
= 531
pF => Use 470 pF
Results of the compensated-loop response are shown in Figure 7.
60
.....
40
III
"c
900
r"- ...... 1'
...... .....
0°
Gal"/
20
~
"
I
Oi
CI
I
CI
0
Phase
.... 1--
-20
-900
.....
I
......
~
I\. ..... 1--
100
180°
...... 1'
_270 0
-40
10
1k
::.,
.c
Go
10k
f - Frequency - Hz
Figure 7. Compensated-Loop Response
....
Summary
The schematic (Figure 8), bill of materials, and test reslilts for the completed design are provided in this summary.
~
(10Vlo15V)
~
Ql
(5V,3A)
RB
10kg
C7
l00IlF
20V
+
Rl0
43g
Cl
470pF
G N D - - -___
CB
0.0012 !iF
R4
C2
0.027 1lF
R6
1.B7kQ
1%
3.0kQ
4
3
2
Ul
TL5001
7
C4
1.01lF
R2
51 kg
B
Rl
43kQ
01 - IRF9Z34S
02 - PMBT2222APH
03 - PMBT2907APH
All diodes are PMBD914PH, unless otherwise specified.
R3- Not used
Figure 8. 12-V to S-V at 3-A Converter
9-70
Table 1. Example 1: Bill of Materials
REF DES
Ul
PART NO.
TL5001
DESCRIPTION
MFG
Texas Instruments
IC, PWM Controller
Cl
Capacitor, Ceramic,
470 pF,
50 V,
10%
C2
Capacitor, Ceramic,
0.027 IlF,
50 V,
10%
C3
Capacitor, Ceramic,
O.OlIlF,
50 V,
10%
C4
Capacitor, Tantalum,
1.0IlF,
20 V,
10%
C5
Capacitor, Ceramic,
0.10IlF,
50 V,
10%
C6
Capacitor, Ceramic,
220 pF,
50 V,
10%
Capacitor, Aluminum,
lOOIlF,
20 V,
20%
Capacitor, Ceramic,
0.0012IlF,
50 V,
10%
20%
C7
20SA100M
C8
C9
10SA220M
Capacitor, Aluminum,
22OIlF,
10V,
CRl
50W003F
Diode, Schottky,
30V,
5.5A
CR2-4
PMBD914PH
Diode, Switching,
100 V,
200mA
Sanyo
Sanyo
International Rectifier
Ll
T50·26B
Core, Inductor,
271lH,
27 Turns #22
01
IRF9Z34S
Transistor, MOSFET,
p-ch,
60 V,
02
PMBT2222APH
Transistor, NPN,
30 V,
150mA
03
PMBT2907APH
18A,
Transistor, PNP,
40 V,
150mA
Rl
Resistor, CF,
43 kf.!,
1/4W,
5%
R2
Resistor, CF,
51 kf.!,
1/4W,
5%
R4
Resistor, CF,
3.0 kf.l,
1/4W,
5%
R5
Resistor, MF,
7.50 kf.l,
1/4W,
1%
R6
Resistor, MF,
1.87 kf.l,
1/4W,
1%
R7
Resistor, CF,
820f.!,
1/4W,
5%
R8
Resistor, CF,
10 kf.l,
1/4W,
5%
R9
Resistor, CF,
2.2 kf.l,
1/4W,
5%
Rl0
Resistor, CF,
43f.!,
1/4W,
5%
MicroMetals
0.14f.!
International Rectifier
Tabl.e 2. Example 1: Test Results
PARAMETER
TEST CONDITIONS
MEASUREMENT
Load regulation
VI= 12V,
10=0-3A
line regulation
10= 1.5A,
VI=10-15V
0.4%
0.4%
Output ripple (peak-to-peak)
VI= 12V,
10=3A
10mV
·Efficiency
VI=12V,
10=3A
81.7%
9-71
EXAMPLE 2: 12-V to 3.3-V at 3-A STEP-DOWN CONVERTER
Design Criteria
The schematic of the final design is provided inFigure 9. This design is very similar to that in Example 1 and thus much
of the detail is not repeated.
Specifications
Input voltage range, VI ......................................................... 10 V to 15 V
Output voltage, Vo .................................................................. 3.3 V
Output current, 10 ............................................................... 0 A to 3 A
Output ripple voltage ............................................................... ~50 mV
Efficiency ......................................................................... >70%
Ambient temperature range, TA ................................................... O°C to 55°C
Surface-mount components· should be employed wherever feasible. The dc/dc converter is implemented with a
continuous-mode, fixed-frequency-PWM step-down (buck) topology operating at 200kHz.
Duty-Cycle Estimates
Estimate the power-switch duty cycle over the range of input voltages using:
D =
Where
VO+Vd
VI - V sat
-;--;-'''---;-;-=-
Vd =catch-rectifier conduction voltage (assume Vd =0.6 V)
V sat = power-switch conduction voltage (assume V sat = 0.5 V)
The results can be recalculated if actual values are too far from the initial estimate.
The duty cycle for VI =10, 12, and 15 V is 0.41, 0.34, and 0.27, respectively.
Output Filter
The output filter is a single-stage LC design.
Inductor
Choose Ll to limit the peak-to-peak ripple current to 10% of the maximum output current.
~IO
=2
x 0.1 x IO(max)
=2
x 0.1 x,3
= 0.6
A peak-to-peak
Inductance is given by:
Ll = (VI - V sat - yO) x D x
~~
o
Maximum ripple current occurs at the maximum input voltage. Solving for Ll:
Ll
=
(VI - V sat - VO)(D)(t)
~IO
=
(15 - 0.5 - 3.3)(0.27)(5 x 10-6)
0.6
For convenience, use the same inductor as in example 1; therefore, Ll
=
25.2 ItH
=27 IlH.
Capacitor
Assuming all the inductor ripple current flows through the capacitor and ESR is negligible, calculate the capacitance
needed to limit the ripple voltage to 50 mV peak-to-peak.
C
9-72
=
~I
0
8 x fs x ~VO
=
'
0.6
(8)(200 x 103)(0.05)
= 75
.
ItF
Assuming the capacitance is at least 10 times greater than the calculated value, the ESR to limit the ripple to 50 mV
peak-to-peak is:
t:.v.
= ~ = 0.05 = S3
ESR
MO
0.6
mg
The rms capacitor-ripple current is:
Capacitor current = 0.289 x
t:.Ia
= 0.289 x 0.6 = 0.17 Arms
For convenience, use the same 220-1JP, 10-V, 35-mO OS-CON SA-series device that was used in Example 1. Alternate
choices include a l00-IJP, 16-V, 45-mO device in the same family but one case-size smaller, and two of the solid tantalum
l00-IJP, 10-V devices described in example I.
Power-Switch Design
The power-switch design procedure includes selecting the power switch, the catch rectifier, and the rectifier-snubbing
network (if needed), calculating power dissipations and junction temperatures, and ensuring the semiconductors have
proper heat sinking.
Power Switch
The surface-mount p-channel device used in Example 1 should work in this design also. The IRF9Z34S has a 60-V
drain-to-source breakdown and a 140-mO maximum IbS(on) with a 10-V gate drive.
Assume that the worst-case junction temperature is l25°C in a 55°C ambient temperature and the drive circuit provides
a IOO-ns total switching time (tum-on and turnoff). IbS(on) increases by a factor of 1.6 at 125°C.
=
PD
(3 2 )(0.14 x 1.6)(0.41)
P D = 0.S3
+ 0.30
+
(0.5)(10)(3)(0.I'X 10- 6 )(200 x 103 )
= 1.13 W
The thermal impedance RaJA = 400 C/W for FR-4 with 2-oz copper and a one-inch-square pattern.
TJ
=TA + (RaJAx PD) =55 + (40 x 1.13) =100°C
Catch Rectifier
Since the requirements are so similar, consider the same device used in Example 1, the 50WQ03F. The device is a 5.5-A,
30-V Schottky diode in a DPAK, power surface-mount package.
Worst-case dissipation occurs at high line where D is minimum. The 50WQ03F has a maximum forward drop of 0.55 V
at a forward current of 3 A and a junction temperature of l25°e.
P D = 3 x 0.55 x (I - 0.39) = I W
The thermal impedance RaJA
TJ
=50°C/W when mounted on FR-4 with 2-oz copper and a one-inch-square pattern.
=55 + (50 x I) =105°C
Catch-Rectifier Snubber Network
The capacitor value chosen is 4 to 10 times greater than the rectifier junction capacitance; higher values improve the
snubbing but dissipate more power. The 50WQ03F has a typical junction capacitance of ISO pF, and the
snubber-capacitor value should be between 750 pF and 1.8 nF. Use CS 1.2 nF for convenience. Rectifiers normally
ring in the range from I to 50 MHz. Choose the snubber resistor, RIO, for a 50-ns time constant:
=
RIO
= 50 x
10-9
C8
= 50
x 10-9
1.2 x 10-9
= 41.7
g => Use 43 g
9-73
Because the capacitor is charged and discharged each cycle, the power dissipation in RIO is:
Controller Design
The controller-design procedure involves choosing the components required to program the TL5001 and includes
setting the oscillator frequency, dead-time control voltage, soft-start timing, and short-circuit-protection timing. The
sense-divider network and loop-compensation designs are also addressed in this section.
Oscillator Frequency
Select resistor Rl = 43 ill using the graph in Figure 3 to set the oscillator frequency to 200 kHz.
Dead-Time Control
The dead-time-control resistor, R2, is .chosen to limit the duty cycle to approximately 0.55, well above the anticipated
0.41 maximum duty cycle. See Figure 4 to find the maximum and minimum ramp-voltage levels, V 0(100%) and V 0(0%)'
R2 is calculated from the following expression (RDT, R t in ill, n in decimal):
R2
= (Rl + 1.25)
[n(V0(100%) - VO(O%»)
+ VO(O%)]
where Rl and R2 are in ill.
R2
=
(43
+
1.25)[0.55 (1.4 - 0.6)
+ 0.6] = 46
kO => 47 kO
Soft-Start Timing
As in Example 1, choose C5
=0.1 j.LF to bring the oUlput voltage into regulation in approximately 5 ms.
SCPTlming
As in Example 1, choose C4
=1.0 j.LF to set the protection enable period to approximately 75 rns.
Output Sense Network
The worst-case input bias current for the TL5001 is 0.5 fJA; therefore, the divider current should be approximately
1000 x 0.5 fJA = 0.5 rnA. In regulation, the voltage across R6 is 1 V and the voltage across R5 is Vo - 1 V = 2.3 V.
Choose R5 7.50 ill so that the cOIl).pensation values in Example 1 can be used in this design as welL
=
_ (Vo - 1 V) _
Idivider R5
-
3.3 _ 1
7.5 x 10
_
3 - 0.307 rnA
_
1V
_
R6 - 0.307 rnA - 3.26 kO => Use 3.24 kO
Loop Compensation
Because the output-filter components, the PWM gain, and R5 are the same as in Example 1, the same compensation
design can be used for this application (refer to Example 1 for details).
9-74
Summary
The schematic (Figure 9), bill of materials, and test results for the completed design are provided in this summary.
VI
(10 V 1015 V)
RS
10kn
C7
lOOIlF
20V
Vo
Q1
(3.3 V, 3 A )
Ll
271lH
C9
220llF
10V
+
C1
470pF
GND
R4
CRl
50WQ03F
C3
O.OlIlF
C2
0.027 1lF
R6
3.0kn
3.24kn
1%
4
3
2
U1
TL5001
6
C4
1.01lF
R2
47kn
7
S
R1
43kQ
01 - IRF9Z34S
02 - PMBT2222APH
03 - PMBT2907APH
All diodes are PMBD914PH, unless otherwise specified.
R3-Notused
Figure 9. 12-V to 3.3-V at 3-A Converter
9-75
Table 3. Example 2: Bill of Materials
REF DES
U1
DESCRIPTION
PART NO.
MFG
IC, PWM Controller
TL5001
Texas Instruments
C1
Capacitor, Ceramic,
470pF,
50 V,
10%
C2
Capacitor, Ceramic,
0.027 11F,
SO V,
10%
C3
Capacitor, Ceramic,
O.G1I1F,
50 V,
10%
C4
Capacitor, Tantalum,
1.011F,
20 V,
10%
C5
Capacitor, Ceramic,
0.1011F,
50 V,
10%
C6
Capacitor, Ceramic,
220pF,
_ SO V,
10%
Capacitor, Aluminum,
100l1F,
20 V,
20%
Capacitor, Ceramic,
0.001211F,
SO V,
10%
20%
C7
20SA100M
CB
C9
10SA220M
Capacitor, Aluminum,
22OI1F,
10V,
CR1
50W003F
Diode, Schottky,
30 V,
5.5 A
200mA
Sanyo
Intemational Rectifier
CR2-4
PMBD914PH
Diode, Switching,
100 V,
L1
TSO·26B
Core; Inductor,
2711H,
27 Tuins #22
01
IRF9Z34S
Transistor, MOSFET,
p-ch,
60 V,
02
PMBT2222APH
Transistor, NPN,
30 V,
150mA
03
PMBT2907APH
Transistor, PNP,
40 V,
1SOmA
Resistor, CF,
43k(.!,
1/4W, 5%
R1
Sanyo
1BA,
R2
Resistor, CF,
-47k(.!,
1/4W, 5%
R4
Resistor, CF,
3.0 k(.!,
1/4W, 5%
R5
Resistor, MF,
7.SOk(.!,
R6
Resistor, MF,
3.24k(.!,
1/4W, 1%
1/4W, 1%
R7
Resistor, CF,
B20(.l,
RB
Resistor, CF,
10k(.!,
1/4W, 5%
1/4W, 5%
R9
Resistor, CF,
2.2 k(.l,
1/4W, 5%
R10
Resistor, CF,
43(.1,
1/4W, 5%
MicroMetals
0.140
Intemational Rectifier
Table 4. Example 2: Test Results
PARAMETER
9-76
TEST CONDITIONS
MEASUREMENT
Load regulation
VI=12V,
IO=0-3A
Line regulation
IO=1.5A,
VI = 10 -15A
0.70/0
0.9%
Output ripple (peak·to-peak)
VI=12V,
IO=3A
BmV
Efficiency
VI = 12V,
IO=3A
74.7"1.
EXAMPLE 3: 5-V to 3.3-V at O.75-ASTEP-DOWN CONVERTER
Design Criteria
The schematic of the final design is provided in Figure 13 . Example I gives a more detailed explanation of the same
design procedure used in this section.
Specifications
Input voltage range, VI ...................................................... 4.75 V to 5.25 V,
Output voltage, V0 .................................................................. 3.3 V
Output current, 10 ............................................................ 0 A to 0.75 A
Output ripple voltage ............................................................... :5;50 mV
Regulation ........................................................................... 1%
Efficiency ......................................................................... >70%
Ambient temperature range, TA ................................................ -20°C to 65°C
Surface-mount components should be employed wherever feasible. The dc/dc converter is implemented with a
continuous-mode, fixed-frequency-PWM step-down (buck) converter operating at 200 kHz.
Duty-Cycle Estimates
Estimate the power-switch duty cycle over the range of input voltages using:
D
= Vo + Vd
VI - V sat
Where
V d = catch-rectifier conduction voltage (assume V d = 0.5 V)
Vsat power-switch conduction voltage (assume Vsat 0.25 V)
=
=
The results can be recalculated if actual values are too far from the initial estimate.
The duty cycle for Vi
=4.75,5, and 5.25 V is 0.84, 0.80, and 0.76, respectively.
Output Filter
The output filter is a single-stage LC design.
Inductor
Choose Ll to maintain continuous-mode operation to 20% of the rated output current.
MO = 2
x
0.2
x IO(max)
= 2
x
0.2
x
0.75 = 0.3 A peak-to-peak
The inductor value is calculated using
(VI - V sat - VO)DTs
Ll = -'-----;-;---"-'-, MO
where Ts is the period of the converter operating frequency.
Maximum ripple current occurs at the maximum input voltage. Solving for Ll:
(5.25 - 0.25 - 3.3)(0.76)(5 X 1O-{i)
=
0.3
= 21.5 IlH
Use Ll = 20 J.tH (Coiltronics CTX20-1, 1.15 A dc-current rating, surface-mount package). Using the new value for Ll,
Ll
Me is recalculated:
MO =
(VI - V sat - VO)DTs
(5.25 - 0.25 - 3.3)(0.76)(5 x 1O-{i)
Ll
=
20 x 1O-{i
= 323 rnA peak-to-peak
9-77
Capacitor
Assuming all the inductor ripple current flows through the capacitor and ESR is zero, the capacitance needed to limit
the ripple voltage to 50 mV peak-to-peak is:
C
=
AlO
8 X fs X ~V 0
=
0.323
(8)(200 X 103 )(0.05)
= 4 04 ~
.
If the capacitance is at least ten times greater than the calculated value, the ESR to limit the ripple to 50 mV peak-to-peak
is:
ESR
~VO
= ~IO =
0.05
0.323
=
155 mO
Capacitor ripple current is seldom a problem in low-voltage converters unless a large number of devices are paralleled.
However, the capacitor current is calculated as follows:
Irms
= 0.289
X
AlO
= 0.289
X
0.323
= 0.093
Arms
The output filter capacitor(s) should provide at least ten times the calculated minimum capacitance and an ESR 30% ,
to 50% lower than the calculated maximum to provide some margin for ESL, PCB leads, temperature, and aging. The
200-kHz, 85°C ripple current should be 0.25 Arms or greater, and the voltage rating should be at least 6.3 V.
For this case, a
100~~,
10-V tantalum electrolytic with an ESR of 0.100 Q maximum was chosen.
Power-Switch Design
The power-switch design procedure includes selecting the power switch, the catch rectifier, and the rectifier-snubbing
network (if needed); calculating power dissipations and junction temperatures; and ensuring the semiconductors have
proper heat sinking.
Power Switch
This design uses a p-channel MOSFET to simplify the drive-circuit design and minimize component count. Based on
the preliminary estimate, roS(on) should be less than 0.25 V + 0.75 A = (333 mn) with a 5-V gate drive and a
drain-to-source breakdqwn voltage appropriate for a 5-V supply. A low gate-to-soUrce threshold voltage and '
surface-mount packaging are also desirable.
The TPS110lD is a 15-V p-channel MOSFET in an SO-8 package withroS(on) = 0.19 mnmaximum, with a4.5-V gate
drive.
PD
= I6 X rDS(on)
X
D + 0.5 X VI X 10 X tr+f X fs
Where tr+f = total MOSFET switching time (turn-on and turnoff) and roS(on) is adjusted for temperature. Assuming
the drive circuit is adequate for tr+f = 100 ns and the jnnction temperature is 100°C with a 65°C ambient, the adjustment
factor is 113 and roS(on) = 1.3 x 0.19 =0.25.
PD
PD
= [(0.75 2 )(0.25)(0.80)] +
= 113 + 38 = 151 mW
[(0.5)(5)(0.75)(0.1
X
10-6)(200
X
10 3 )]
The thermal impedance RaJA = 158°CIW for FR-4 with no special heat-sinking considerations.
TJ = TA + (RaJA x PD) = 65 + (158 x 0.151) = 89°C
9-78
Catch Rectifier
The power dissipation in this design is very low because of a relatively low output-current requirement and the
high-power-switch duty cycles. Consequently, a small surface-mount Schottky device such as the MBRS 140T3 is more
than adequate. The MBRS l4OT3 is rated for 1 A offorward current and a 40-V breakdown. The conduction drop, Vd,
is 0.35-V at I-A forward current and a 100°C junction. The power dissipation is:
PD = 10 X V d x (1 - D)
PD = 0.75
x 0.35 x
(1 - 0.76) = 63 mW
In the absence of thermal-impedance data for this package with FR-4 mounting, a reasonable estimate of junction
temperature is not practical. However, some assurance can be derived from considering the thermal impedance
necessary to limit the junction to 100°C which is comfortably below the 125°C maximum rating. The thermal
impedance, RaJA, needed to raise the junction temperature from the 65°C ambient to 100°C with 63 mW of dissipation
is:
_ T J - T A _ 100 - 65 _
°
R6JA PD
0.063 - 556 C/W
There should be no problem since even signal diodes are in the 300°C to 4OO°CIW range. Some preliminary testing to
establish thermal performance is highly recommended for applications where the margins are lower.
Controller Design
The controller-design procedure involves choosing the components required to program the TL5001 and includes
setting the oscillator frequency, dead-time control voltage, soft-start timing, and short-circuit-protection timing. The
sense-divider rietwork and loop-compensation designs are also addressed in this section.
Oscillator Frequency
From the graph in Figure 3, choose R2 =43 ill to set the oscillator frequency to 200 kHz.
Dead-Time Control
The maximum duty cycle in this application is 84% and because there is no benefit in limiting the duty cycle a few points
below 100%, the dead-time control resistor is omitted.
Sofl-5tart Timing
The DTC input can be used to soft stru:t the converter even though dead-time control is not implemented. The soft-start
capacitor is charged with a constant current approximately equal to the current flowing from the RT terminal. The output
voltage should be in regulation by the time C5 has charged to 1.4 V. Choose C5 such that the output voltage comes up
'
in 6 ms.
Charging current
C5
=
= 4~ ~Q = 23.3 J1A.
(23.3 x 10- 6 )(6 X 10-3 )
1.4
= 0.1 !AF
SCPTimlng
As in Example 1, choose C4 = 1 J.lF to set the protection enable period to approximately 75 ms.
Output Sense Network
The worst-case input bias current for TLSOOI is 0.5 JlA; therefore, the divider current should be approximately
l000x 0.5 JlA =0.5 rnA. In regnlation, the voltage across R6 is 1 V and the voltage across R5 is Vo - 1 V =2.3 V. For
this design, R5 is set at 7.50 kQ.
_ (Vo - 1V) _
Idivider R6
R5
-
3.3 _
1_
7.5 X 10
= 0.3~7VrnA = 3.26
kQ
=
3 - 0.307 rnA
Use 3.24 kQ
9-79
Loop Compensation
Refer to Example 1 for more detailed explanation.
The open-loop response without the error amplifier consists ofthe gain ofthePWMlpower switch, ApWM, and the output
filter response. The gain, APWM, is:
ApWM = AV
~~~MP) (l~~ =~~6) =
6.25
= 15.9 dB at nominal input
Similarly, the gain is 15.5 dB at low line and 16.3 dB at high line.
The output filter produces an underdamped complex-pole pair at the filter's resonant frequency, and the capacitor ESR
puts a zero in the response above the resonant frequency. The complex poles are located at:
1
2
1t
j (20 x 10-6)( 100 x 10-6)
= 3.56 kHz
The zero is located at:
_1_
21t RsC
=
1
(21t)(0.1)( 100 x 10- 6)
= 15.9 kHz.
.
Figure 10 includes gain and phase plots of the open-loop response (error amplifier not included) obtained from a simple
SPICE simulation.
III
"c
60
270°
40
180"
I
..a
.c
I
Phase
CJ
I
90°
J
·ii
CJ
,.h
Gain
20
IL
I
-0
"-i'
\
-20
1\
"....,.
0°
..... ~
....
~
-40
-&-
-goo
-180°
10
100
1k
10k
100k
f - Frequency - Hz
Figure 10. Uncompensated Open-Loop Response
Choose a unity-gain frequency of approximately 20 kHz to provide good transient response. Figure 11 shows a standard
compensation network chosen for this example.
9-80
C7
I
R3
C8
R4
C6
Vo --*---A./I/v---*--'-+-<
ToPWM
R6
Figure 11. Compensation Network
Assuming an ideal amplifier, the transfer function is:
A (S) _ [
1
. ea
- - 8 RS(C6
+ C7)
][[8(RS + R4) C8 + 1] (8 R3 C6
(8 R4 C8 + 1) [8 R3 (C6ii C7)
+
+
1)]
1]
The integrator gain, lI[RS . (C6 + C7)], is used to set the open-loop unity-gain frequency. The zeros are located at
approximately the same frequency as the output-filter poles to compensate for the gain reduction and phase shift. The
pole at 1/(21t . R4 . C8) is positioned at approximately the same frequency as the zero in the output filter to maintain the
20 dB-per-decade roll-off in the gain response. The final pole at 1I(21t . R3 . C611 C7) is placed between half the operating
frequency and the operating frequency to minimize noise at the pulse-width-modulator input.
The sum of the gains of the modulator, the LC filter, and the error amplifieris 0 dB at the unity-gain frequency. The gain
of the modulatorlLC filter at 20 kHz may be calculated or obtained from a bode plot using straight-line approximations
or from a simple SPICE simulation. As shown in Figure 10, the modulatorlLC filter gain is -8 dB at 20 kHz.
The compensation network has two zeros at 3.6 kHz to cancel out the LC filter poles. These two zeros contribute a gain
of 29 dB at 20 kHz; therefore, the gain contributed by the compensation-network integrator needs to be
-21 dB [0 - (-8 + 29) -21]. The integrator gain of -21 dB translates to a voltage gain of 0.089.
=
_--;--;----'1'--_ _
(2J1:>(tT)(RS)(C6 + C7)
C6
=
= 0.089
=
(at t
20 kHz)
T
1
.=
1
(21t)(fT )(RS)(0.089)
(6.28)(20 x 10 3 )(7.5 x 103 )(0.089)
= 0.0119 IJP => Use
C6
0.012
IJP.
R3 is chosen to position a zero at 3.6 kHz.
R3
=
=
1
(2:rc)(f)(C6)
1
(6.28)(3.6 x 10 3 )(0.012 x 10- 6 )
= 3.69
kg => Use 3.6 kg
R4 and C8 are chosen to provide an additional zero, fz, at 3.6 kHz and a pole, fp, at 15.9 kHz.
f~ f~
-
C8
= (21t)(RS) =
R4
=
L.6
1
(2:rt)(fp )(C8)
~
10 3 - 15.9
(
~
(6.28) 7.5 x 10
=
103 ]
3)
= 0.0046 IJP
1
(6.28)(15.9 x 103 )(0.0047 x 10- 6 )
=> Use C8
= 2.13
= 0.0047 IJP
kg => Use 2.0 kg
C7 is chosen to provide the pole at 100 kHz. Assuming C6» C7,
C7
=
1
(21t)( fp )(R3)
=
1
(6.28)( 100 x 103 )(3600)
= 442
pF => Use 470 pF
Results of the compensated-system response are shown in Figure 12.
9-81
SO
......
, ..... r-.
90°
, r-.. .... r-.
40
In
0°
Gain
-
20
'a
I
....
"
c:
·iii
CJ
I
Do
I
r.....
h
Phase
-20
-180°
~
..... 1"-270°
\1"-
"C
-40
CD
.c:
........
-
0
CJ
...
90°
-3S0°
10
100
1k
100 k
10k
'
f - Frequency - Hz
Figure 12. Compensated-Loop Response
Summary
The schematic (Figure 13), bill of materials, and test results for the completed design are provided in this summary.
VI
SV
R1
4700
c11
~.
~
10V
GND
-=-
Q1
TPS1101D
L1
20~H
--
~
'-;~
CR1
~~ MBRS140T3
C3
\1 0.1 ~F
)1
-=-
VCC
C4
S
)1
SCP
OUT
COMP
CS
\1 0.1 ~F
6
)1
R2
43kO
7
100~F
10V
~
-=-
3
U1
TLS001
;;:; ::;: CS
0.012 ~F
DTC
FB
1
I
4
RS
7.S0kO
1%
;;:;r:: C7
470pF
0 .0047~F
RT
RS
3.24kO
1%
8
~
NotES: A
Frequency = 200 kHz
B. Duty cycle = 100% MAX
C. Soft-start timing =6 ms
D. SCP timing = 75 ms
Figure 13. 5-V to 3.3-V/O.75-A Converter
,>R4
< 2.OkO
;:]r::C8
R3
3.SkO
GND
9-82
Vo
3.3V
+
C2
2
_\L 1.0 ~F
"
Table 5. Example 3: Bill of Materials
PART NO.
REF DES
DESCRIPTION
U1
TL5001
IC, PWM Controller
C1, C2
TPSD107M010R0100
MFG
Texas Instruments
Capacitor, Tantalum,
100 !IF,
10V,
20%
C4
Capacitor, Ceramic,
1.0 !IF,
50 V,
10%
C3,C5
Capacitor, Ceramic,
0.1 !IF,
50 V,
10%
C6
Capacitor, Ceramic,
0.012 !lF,
50 V,
10%
C7
Capacitor, Ceramic,
470 pF,
50 V,
10%
C8
Capacitor, Ceramic,
0.OO47 !lF,
50 V,
10%
1A
CR1
MBRS140T3
Diode, Schottky,
20 V,
L1
CTX20-1
Inductor, Toroid,
2O!lH
01
TPS1101D
Transistor, MOSFET,
p-ch,
15 V,
AVX
Motorola
Coiltronics
0.19(.1
R1
Resistor, CF,
470(.1,
1/4W, 5%
R2
Resistor, CF,
43 k(.l,
1/4W, 5%
R3
Resistor, CF,
3.6 kQ,
1/4W, 5%
R4
Resistor, CF,
2.0kQ,
1/4W, 5%
R5
Resistor, MF,
7.50kQ,
1/4W, 1%
R6
Resistor, MF,
3.24 k(.l,
1/4W, 1%
Texas Instruments
Table 6. Example 3: Test Results
PARAMETER
TEST CONDITIONS
Load regulation
VI=5V,'
Output ripple (peak-to-peak)
10 = 750 mA
Efficiency
MEASUREMENT
1.4%
10=0 -750 mA
<20mV
VI=5V,
10=750mA,
01 =S19405
74.4%
VI=5V,
10=750mA,
01 =TPS1101
84.1%t
tThe higher efficiency achieved with the TPS1101 is due to lower gate capacitance, which speeds up
switching and reduces switching loss.
Appendix A
5-V Prototype-Board Waveforms
The following photos were taken using the 12-V to 5-V prototype breadboard that was designed and documented as
presented in the first section of this application report. The results are typical of those seen on the other designs in this
paper.
Minimum Dead TIme (maximum duty cycle)
The dead time of the output switch was measured with the feedback resistance disconnected.
Vertical: 2 V/div
Horizontal: Ills/div
Coupling: dc
~I~--- 823 Acqs ---.~I
Stop: 50 MSls
T
..
'
t'r
Ch1 ..Duty
83.8%
1
+ .....
Ch1
2V
M111S
Figure A-1
: '---:
Ch1...r
...
OV
Output Switch Drain to Ground Voltage·
The input of the low-pass output filteris shown in Figure A-2. The high-level voltage is equal to the input voltage minus
VDS(on)' The low-level voltage is one diode drop below ground.
Vertical: 2 V/div
Horizontal: I I1s/div
Coupling: de
1<11141---- 528 Acqs ---"~I
T
Stop: 50 US/s
.
..
...
. .: :
: : : :................ :........ :........ :......... :....... .
............ :.... :... - ... : .... : ... ; .... :....
...... ........ ........ ........
.... : ..... : ....
:
:
;
.... :
.... :
.
- .... : ...... : .... .:.... :....
;
•••• ;
.... ;
... H
-
'.
;
;
. .
...........
.-.
.... :.... :.... :.... :...
.
.... :.... :.... :.... ;... ~ .... :.... ;... : .... : ....
;
Ch1
2V
;
.1
M 11lS
FigureA-2
9-86
Ch1..r
;
5.2V
Output Voltage Rise Time (electronic load)
The soft-start circuit slows the rise of the output voltage to prevent excessive overshoot.
Vertical: I V/div
Horizontal: 2 ms/div
Coupling: dc
~'''I---- Sample - - - -...,
Run: 25 kS/s
T
. . .
... '" ....................................
- ......... .
. .
.......................
Ch1
1V
M2ms
Ch1/
4.04 V
FigureA-3
9-87
Output Voltage Rise Time (resistive load)
This photo shows the response to a resistive load.
Vertical: 1 V/div
Horizontal: 2 ms/div
Coupling:dc
11<11111--- Sample ----~~I
Riln:25 kSfs
T
. ...................... .
................· .... ........
· . .
..........................
· . .
........................
. . .
..........................
1~-----·
Ch1
. . .
........................
1V
M 2 ms
FigureA-4
9-88
Ch1 .;/"
4.04 V
Output Voltage Ripple
The output ripple is shown in Figure A-5. The triangular-shaped ripple is clearly a function of the ESR of the output
capacitor.
Vertical: 2 mV/div
Horizontal: 2 Ils/div
Coupling: ac
1<1111111---- 262 Acqs ---.t~1
Stop: 25 Ms/s
1
Ch1
2mV...r
M2J1S
Ch1...r
ov
FigureA-5
9-89
Output Dynamic Response
The response of the output to step-load changes is sbown in Figure A-6. The electronic load was stepped from 1.5 A
to 3 A.
Top Waveform: Vo
Vertical: 100 mV/div
Horizontal: 0.5 ms/div
Coupling: ac
Bottom Waveform: 10
Vertical: 1 Aldiv
Horizontal: 0.5 ms/div
Coupling: dc
~14r-----48~A~s-----.~1
Stop: 100 kSls
T
1
2 ......... : .... : .... : ... .
.
Ch1
100 mV
.
Ch2
10 mV
Figure A-6
9-90
M 500 lIB
Ch1 ..r
66 mV
Acknowledgement
This application report is the synergistic result of many individual efforts. The work involved included characterization
of the controller chip; design, breadboarding, and debugging of application examples; and preparation of the report
itself. Every effort has been made to provide a document that is useful and understandable to the customer/designer. The
following list, though not all inclusive, represents the major contributors to this document:
Co-authors and Engineering
Bill Johnston, Power Supply Systems Engineering Manager
Philip Rogers, Power Supply Systems Engineer
John Vincent, Vmcent Enterprises, Consultant
Documentation
Ron Eberhart, Technical Writer
Fran Caldwell, Publications Specialist/Formatter
Jim Schrader, Technical lllustrator
Proofreading and Suggestions
Kazu Kudoh, Product Specialist
Jeff Hooker, Product Specialist
Bob Newton, Product Specialist
Rob Saunier, Applications Engineer
9-91
9-92
Component Selection and PCB
Layout Guidelines for Low-Power
DC/DC Converters
Contents
Section
Page
Title
Component Selection Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. g.;..94
Output-Filter Inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-94
Output-Filter Capacitor ................................................ 9-94
Input-Filter Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-95
Power Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-95
Output Rectifiers ..................................................... 9-95
Snubber Network . . . . . . . . . . . . ., . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-96
PCB Layout Considerations ....•................................. g.;..97
Power Stage Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 9-97
Output Stage Considerations ........................................... 9-99
Controller Layout Considerations ....................................... 9-100
Trace Width Considerations ........................................... 9-101
Thermal 'Considerations for Surface-Mount Semiconductors ......... g.;..104
Example ...................................................... g.;..107
List of Illustrations
Figure
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
Title
Page
Buck Power Stage Layout Considerations ............................. 9-98
Boost Power Stage Layout Considerations ............................. ·9-99
Continuous vs. Discontinuous-Mode Inductor Current ................... 9-99
Output Layout Considerations ........................................ 9-100
Controller Layout Considerations ..................................... 9-101
Thermally Enhanced PWB Layout for the 20-Pin TSSOP ................ 9-105
Thermal Resistance, Junction-to-Ambient vs. Air Flow ................... 9-106
Thermal Resistance, Junction-to-Ambient vs. Air Flow ................... 9-106
Dual Regulator Schematic ........................................... 9-107
Top Side Ground Plane .............................................. 9-108
Solder Side and Component Layout ................................... 9-108
List of Tables
Table
9-1
9-2
Title
Page
Derating Factors .................................................... 9-101
Maximum Derating Current for aTA:5: 20°C ............................. 9-102
9-93
Component Selection Guidelines
Due to the wide variation in current levels in the typical power supply, the range of size of the components is
usually extensive. Even in low-power dc-to-dc converters the power switch, rectifier, and output capacitor
may range from very small surface-mounted parts to D-Paksize. The inductor is usually the largest component in low-power situations and determines the overall size of the supply.
Output-Filter Inductor
The key parameters to consider in selecting an inductor for an output filter application are inductance, continuous and peak current ratings, series resistance (OCR), and packaging. The inductance and current rating
requirements are determined during the electrical design and depend heavily on:
•
•
•
•
•
Input and output voltages, output current
Converter topology
Operating frequency
Operating mode ( continuous or discontinuous)
Designer's preference
Inductance decreases as current increases in all inductors, but the slope and frequency onset of this
decrease varies depending upon the core material, air gaps, and ac flux. Some inductors hold a relatively
constant value out to a point where the inductance suddenly collapses, while others decrease slowly and
continually over a wide range. Even within families of cores, the change in inductance over frequency with
a change in permeability can be great. Inductance in ferrites is largely unaffected by ac flux. Some iron
powder materials are strongly affected by ac flux changes that cause large inductance increases at higher
flux levels. To ensure adequate performance, design the inductor for the peak current and at the lowest
operating frequency. Pulse width modulator (PWM) tolerances can be 15% or more before considering the
external timing component tolerances.
The series resistance (OCR) must be low enough to limit the heat rise to acceptable levels. The resistance
of copper increases with temperature and can cause a degenerating condition on the output. Heat rise in
inductors is hard to calculate; the easiest way to determine this is to use the manufacturers recommended
current ratings at maximum temperature. The OCR may have to be lower than that necessary for heat rise
in order to meet the efficiency and regulation specifications at low line.
Core losses are generally low enough that they do not cause a thermal problem in these applications except
at high operating frequencies and at high ripple current.
Magnetic component manufacturers offer a wide range of off-the-shelf inductors suitable for dc/dc converters, sOme of which are surface mountable. There are many types of inductors available; the most popular
core materials are ferrites and powdered iron. Bobbin or rod-core inductors are readily available and inexpensive, but care must be exercised in using them because they are more likely to cause noise problems
than are other shapes. Custom designs are also feasible, provided the volumes are sufficiently high.
Output-Filter Capacitor
Unless the converter is to be subjected to large load transients, the filter capacitor is chosen to limit the output ripple voltage to specification levels. Most low-power converters utilize single-stage filter designs.
The filter capacitor passes most (ideally all) theac components of the inductor current and the impedance
must be low enough to limit the ripple voltage. The impedance consists of a capacitance in series with a
resi~tance (equivalent series resistance, ESR) and an inductance (equivalent series inductance, ESL), and
depending on the capacitor technology, the overall impedance is dominated by either the capacitance or the
ESR at the frequencies of interest. Besides impedance, the voltage rating must be greater than the maximum output voltage and the ripple current must be within ratings.
9-94
Four capacitor technologies, low-impedance aluminum, organic semiconductor, solid tantalum, and multilayer ceramic, are suitable for low-cost commercial applications. Low-impedance aluminum electrolytics are
the lowest cost and offer high capacitance in small packages, but the ESR is higher than the other three.
Organic semiconductor electrolytics, such as the Sanyo OS-CON series, have become very popular for the
power-supply industry in recent years. These capacitors offer the best of both worlds - a low ESR that is
stable over the temperature range and high capacitance in a small package. Most of the OS-CON units are
supplied in lead-mounted radial packages; surface-mount devices are available but some of the size and
performance advantage is sacrificed. Solid tantalum chip capacitors and ceramic capacitors are probably
the best choices if a surface-mounted device is an absolute must. Products such as the AVX TPS family and
the Sprague 5930 family were developed for power-supply applications. These products offer a low ESR
that is relatively stable over the temperature range, high ripple-current capability, low ESL, surge-current
testing, and a high ratio of capacitance to volume.
Now, high-capacitance multilayer-ceramic capacitors are available. These have very low ESR (less than 5
mQ), but the capacitance tolerance is very broad (typically +80% to -200/0 and varies with bias). In addition,
the larger values (221lF and larger) have ESL problems that must be considered in use. The ESR is so low
that the resulting zero in the loop response generally can be ignored, but the capacitance is too variable to
rely on for the output filter response and should be paralleled with another more stable, higher ESR capacitor. Wide variations in the output capacitance affects the open loop filter poles and makes the power supply
more sensitive to external factors. When using 22-IlF or greater ceramic, it is recommended that a 0.47-IlF
capacitor or larger be used in parallel to reduce the effects of the internal ESL.
Input-Filter Capacitor
Input filters supply the surge current needed during the power-switch on time. They must supply the current
without significant voltage droop for the maximum turn-on time. In addition, the current surge when the input
voltage is applied must be considered. Buck and buck-derived configurations have a step function input current waveform with large harmonic content. Boost and flyback regulators have triangular or ramp waveforms. These instantaneous step changes require large surge capability. Low ESR capacitors allow a much
greater surge than high-ESR capacitors. Tantalum capacitors do not tolerate this surge and so should not be
used in input filter applications. Aluminum electrolytics are excellent here due to their large capacitance-tovolume ratio and surge current capabilities. For surface mount, ceramics work well and their low ESR prevents the input voltage from having a voltage step.
Power Switches
Many converters can be implemented with bipolar or MOSFET transistors as the power switch. Bipolars are
inexpensive and can perform well in low-voltage applications, but designing a drive circuit to realize the performance is not a trivial effort. Furthermore, complex base-drive schemes can eliminate mUCh, if not all, of
the cost advantage. MOSFETs offer the fast switching times required for high-frequency operation, using
relatively simple, low-component-count gate-drive circuits.
Output Rectifiers
The output rectifier is critical to good converter performance. Rectifier conduction losses are generally a
significant percentage of the total converter dissipation, and either high-conduction loss or poor-switching
performance increases dissipation in other components. The key parameters to consider in selecting the
rectifier include the:
•
•
•
•
Current rating
Voltage breakdown
Forward voltage drop
Switching speed
9-95
•
•
•
Junction capacitance
Thermal re~istance
Packaging
After voltage rating, the primary concern is usually power dissipation, either to ensure that the rectifier operates within its junction temperature rating or to optimize the overall converter efficiency. A low forward voltage drop reduces power dissipation that minimizes the use of heatsinks to maintain junction temperature to
acceptable levels and optimizes power converter efficiency. Fast switching speeds are essential to minimize
dissipation. Schottky rectifiers are popular choices in low-power, low-voltage applications for their characteristic low forward drop and fast switching.
"
Current rating is a secondary concern for most designs. Typically, the device required to limit dissipation to
acceptable levels has current rating that is a factor of two or more greater than the application requires.
a
The breakdown voltage rating must at least equal the maximum input voltage in buck converters and the
output voltage in boost converters. Some margin for the voltage surges, spikes, and ringing typically encountered in practical applications is also advisable.
Low junction capacitance minimizes component size and power dissipation in snubbing networks.
Rectifiers are readily available in a wide range of packages for both lead and surface mount applications.
The surface mount packages tend to perform better than the lead mounts due to the reduced parasitics;
however, they are harder to heatsink when external heatsinking is required at higher power levels.
The output rectifier can be replaced with a low ROS(on) MOSFET (synchronous rectifier) in applications
where efficiency overrides cost concerns.
Snubber Network
Converters almost universally suffer from ringing on the voltage waveform at the node where the powerswitch, output inductor, and rectifier are connected. The ringing results from driving paraSitic inductances
and capacitances with fast rise-time waveforms and ranges in severity from objectionable to unacceptable
depending on component selection and printed-circuit board (PCB) layout. A series RC-snubber network in
parallel with the rectifier is the simplest way to minimize the problem. Since deleting components from a PCB
layout is usually easier than adding them, the safest strategy is to include the network in the initial design and
delete it, if it is not needed.
High frequency ceramic or film capacitors and film resistors should be selected for snubber applications;
avoid wire-wound resistors because they tend to be inductive.
9-96
PCB Layout Considerations
Electrical design is only half the work in the creation of a reliable power supply. Unlike digital circuits, power
circuits handle a broad range of currents -from the microampere control current to the tens (or hundreds) of
amperes flowing in the power stage. The production of clean output power with minimal noise depends critically upon PCB layout. Power supply circuits also produce high-frequency signals that may cause many
problems within the load or the source if not properly handled. Even though a power supply can operate at
50 kHz to 500 kHz, the switching edges can have rise and fall times in the order of
10 ns or faster, correlating to frequencies of up to 100 MHz. Without proper layout, radiation can be a major
problem. Proper layout techniques generally include minimizing high-current loops within the power stage,
proper grounding of the control stage, and proper sizing of the traces to adequately handle the peak currents. Ground planes are useful but cannot solve every problem. The control of current flow within the supply
is more important.
Magnetic coupling between adjacent circuitry is a major source of noise pickup. The magnetic field produced
by a current is proportional to the area of the loop in which it circulates. Thus, noise coupling can be greatly
reduced by minimizing the loop areas.
A ground plane is extremely useful in satisfying this goal. On thru-hole boards, a top-surface ground plane
with strategiC cutouts to control the flow of output currents and control-section currents is ideal. Surfacemount boards usually have minimal top-surface area for a ground plane.
Other pOints to consider during the PCB layout process are selection of the proper components, separation
of the ground plane to reduce cross-conduction, snubbers on the commutation/output rectifiers, proper
placement of EMI suppressing components to reduce noise pickup/transmission, and thermal considerations.
.
Power Stage Considerations
The power stage includes the low-pass output filter, the power SWitch, and the input filter. It contains very
h!gh circulating currents and, therefore, should be given the highest priority when laying out the. PCB.
Figure 9-1 shows the current paths for a typical buck converter. The charging (forward) current, 11, flows
through the input capacitor, the power switch, and the inductor before splitting between the output capacitor
and the load. The inductor discharge (com mutating) currenth, flows through the commutating diode and the
inductor, then to the output capacitor and the load. The peak value of these currents is the same. The paths
for these currents should be as short as possible.
The input filter capacitor should be close to the power switch and the commutating rectifier. In buck regulators, the inpul.current waveform from the input capacitor to the power switch is a step function. This contains
large harmonics that are difficult to filter out. The closer that the input filter is to the power switch, the less the
radiation. Flyback regulators have a ramp input waveform that has a high-frequency trailing edge.
Next in priority, due to its relathlely high current level, is the drive circuit for the power stage. It should be
placed as close to the power switch as possible. The power switch generally has a large input capacitance
associated with its gate. High peak currents achieve the very fast rise and fall times required for high efficiency. If the gate lead trace is longer than approximately 2 inches, a small (approximately 10 Q) resistor should
be placed in the trace near the FET to damp the LC tank formed by the inductance of the trace and the gate
capacitance of the FET. Current 101 is the turn-on current that charges the gate capacitance and current 102
is the turn-off current that discharges this capacitance. When using bipolar power switches, base capacitance is not a problem, but the average drive current is much higher, resulting in the same requirement for
short current paths.
9-97
Vee
Minimize These Loop
Areas and Lead Lengths
DRV
Figure 9-1. Buck Power Stage Layout Considerations
In continuous-mode boost converters, the input current is higher than the output current by the ratio of the
output voltage to the input voltage divided by the efficiency. In a 5-V to 15-V, 5-ampere, 90% efficient boost
coiwerter,the currentthrough the inductor and power switch is over 16amps! Discontinuous-mode converters (of any type) ha~e much higher currents than their continuous-mode counterparts.·
In converters with high voltages present, such as offline switchers and in some boost or flyback converters,
care must be exercised to ensure that proper isolation of the high voltage is done. Various safety standards
from safety agencies (such as UL and VDE) specify the required creepage distance between high-voltage
pOints and the user. In some cases, the effects of high-voltage transients ( from startup, lightning, or static)
must also be considered. Converters operating from the ac mains usually have input EMI filters. To be effective, these filters must be physically located close to the input source and laid out in a very tight configuration
noting, however, that the high-voltage transients mentioned previously may be doing their best to try to bypass the filter.
9-98
Vee
Minimize These Loop
Areas and Lead Lengths
DRV
eo,...-........,
Figure 9-2. Boost Power Stage Layout Considerations
Power stage currents are dependent upon the output requirements, input voltage, and operating mode of
the power supply. Figure 9-3 shows the inductor-current waveforms for a continuous-mode and a discontinuous-mode power supply with the same output current and input voltage. The peak current of the discontinuous supply is much higher and varies with duty cycle.
I(AVG)
Figure 9-3. Continuous VS. Discontinuous-Mode Inductor Current
Output Stage Considerations
In a Buck regulator, the output-filter capacitor placement is not as critical as the input filter. Output current
flows through the output inductor to tlJe load. Additional trace length in this path acts as additional capacitance as long as the power and return traces are physically close to each other. The trace length from the
output capacitor to the main output trace should be kept as short as possible. This minimizes the series resistance and inductance between the capacitor and the main trace. In many cases, parallel capacitors are used
in the output filter to reduce the equivalent series resistance (ESR). If the capacitors are connected at equal
intervals along the output path, the effective ESR of the first capacitor is much lower than the last capacitor.
Care must be used in this configuration to make sure that the first capacitor in the string is not overloaded by
the higher ripple current that it must conduct.
9-99
Discontinuous-mode boost regulators have large current pulses in the output capacitor. Here, the capacitor
should be close to the power switch to reduce magnetic radiation.
The ideal configuration on multilayer boards is for the output and return traces to be directly over each other
to minimize the enclosed loop inductance and to increase coupling capacitance. This technique can be
beneficial when applied to almost any closed signal path. On single-sided boards, the optimum solution is
closely-paralleled traces, see Figure 9-4.
Long Leads Increase
Capacitor ESR and ESL
From Power
Switch
Closely Paralleled Traces Increase Output Capacitance
and Reduce Inductive Noise Coupling
Figure 9-4. Output Layout Considerations
Controller Layout Considerations
Ground connections are very critical in the control stage of a power supply. Any voltage difference between
the feedback divider ground and controller ground results in an error in the output voltage. Noise pickup in
the sensing circuit is amplified and fed directly to the output. Ideally, the controller supply current should not
flow through the feedback path. This is not always possible, though, and the next best choice is to have the
controller referenced to the output ground as close as possible. The supply voltage should be bypassed to
prevent transient currents from the controller from being propagated across the PCB. The bypass capacitor,
C(bp)' should be located as close as possible to the controller with short leads to the Vee and ground terminals. Surface-mount chip capacitors mounted next to the controller give the shortest possible routing. Again,
current loops should be minimized with parallel traces to reduce noise radiation and pickup.
The feedback path from the low-impedance output through the resistor divider to the high impedance operational amplifier inputs should be as short as possible and should consist of parallel paths to reduce noise
pickup. The divider ground point should be close to the output ground, but more importantly, the center point
of the divider should be close to the input error amplifier due to its high impedance and noise susceptibility.
Sometimes breaking the ground plane into two or more sections with a single common connection point can
help in keeping the high output-return current from flowing around or near the controller circuit. This technique .can greatly reduce.
noise .
pickup by the sensitive controller circuitry.
Many controllers today ha~e the driver stage built in. This compounds the problems of ground currents, especially when the driver does not have its own power ground terminal. It is even more important, in this case,
to locate the controller close to the output !o reduce the effects of error currents.
In both the cases discussed previously, close to the output does not imply close to the power stage. The
switching elements in a modern high-ftequency power supply generate large amounts of EMI. that can be
magnetically coupled into the high-impedance input of the controller. The further away from these elements
the controller is, the harder it is for the signals to couple. In the small circuits oftoday, this is becoming harder
to do. If at all possible keep the error amplifier and reference voltage terminals away from the power stage.
9-100
VCC
Minimize This Loop
Area and Lead Lengths
VCC
DRV
FB
GND
High Impedance Trace
(High Noise Pickup)
-::-
Low Impedance Traces
(Low Noise Pickup)
Both Controller Power and
Feedback Current Flows In
This Path
Minimize These Loop Areas
and Lead Lengths
Figure 9-5. Controller Layout Considerations
Trace Width Considerations
Trace widths on a power supply board are a compromise among minimum loop area for noise reduction,
maximum trace widths for low IR drops, and available board area. Outside layers of PCBs are generally
available with 1-ounce and 2-ounce copper, a reference to the weight of the copper per square foot of board.
Inner layers of multilayer boards can have 1/2-ounce copper. One-ounce copper is nominally 1.3435 mils or
0.0013435 inch thick. Wire is generally measured in circular mils. A circular mil is the area of a circle that is 1
mil in diameter. To convert circular mils to square mils, multiply by the factor 1t/4. In order to have the same
current density as 20-gauge wire (1022 circular mils) using 1-ounce copper, a trace width of 597 mils is required! However, flat traces on a PCB can carry more current than the same amount on copper wire due to
the greater surface area of the trace for heat radiation into the air and heat conduction onto the board itself.
Good design practice limits the temperature rise on FR4 board to 20°C (MIL-STD-275C). The current flowing through the traces is derated to account for several fac;:tors. The recommended derating factors are as
shown in Table 9-1.
Table 9-1. Derating Factors
Condition
Current Multiplication Factor
Tin/lead surface or auto soldering
1.42
Solder mask or insulating surface
1.18
Copper thickness;:: 3 Oz.
1.18
Base material ~ 0.031 in.
1.18
9-101
The information in Table 9-2, taken from MIL-STD-275C (commercial equivalent is ANSIIIPC-D-275),
shows the maximum derated current to achieve a temperature rise of 20°C or .Iess.
Table 9-2. Maximum Derating Current for ilTA::;; 20°C
Trace Width
(Inches)
Current
(Amps)
0.025
2
0.075
5
0.200
10
0.440
20
The information given in Table 9-2 is the maximum recommended current. The resistance of the trace still
needs to be calculated to verify that the voltage drop is satisfactory for the application.
The resistance of a 10-mil trace of one-ounce copper is 502 mQ per inch. For any given trace width, the
resistance is:
R = 0.00502L
WT
Where:
R is the trace resistance in ohms
L is the length of the trace in mils
W is the width of the trace in mils
T is the copper weight of the board in ounces per square foot
Two useful variations of this formula are:
W =
0.0~~2 L
W
---oVT-=-- gives the required width in mils for a desired voltage drop.
gives the required width in mils for a desired trace resistance.
0.00502L1
Where:
W is the width of the trace in mils
L is the length of the trace in mils
I is the current in amps
V is the voltage drop in volts
T is the copper weight of the board in ounces per square foot
9-102
Example:
When a circuit with 10 amps and a 100 mV drop is desired on a 1-inch trace, the trace width is
calculated as follows:
W = (0.00502)(1000)(10)
(0.1)(1)
W
502 mils using l-ounce copper
(0.00502)(1000)(10) = 251 milsusing2-ouncecopper
(0.1 )(2)
W = (0.00502)(1000)(10) = 167 mils using 3-ounce copper
(0.1 )(3)
As can be seen in the previous example, heavier-weight copper is very useful in power supply circuits. A
secondary advantage to heavy copper traces is the heat-sinking ability of copper. This can come into play
when calculating the junction temperature (discussed later in this chapter). Generally, the resistance of the
circuit traces should be insignificant compared with the rest of the circuit. The power stage of a converter
may contain a MOSFET with less than 50 mO of on-resistance, an inductor with less than 100 mO of dc
resistance (OCR) and an output capacitor with 100 mO of ESA. The trace resistance for this circuit should be
in the order of 25 mO (both signal and return path) to meet this requirement.
9-103
Thermal Considerations for Surface-Mount Semiconductors
In response to system-miniaturization trends, integrated circuits are being offered in low-profile and finepitch surface-mount packages. Implementation of many of today's high-performance devices in these packages requires special attention to power dissipation. Many system-dependent issues. such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given component.
.
Three basic approaches for enhancing thermal performance are:
•
•
•
Improving the power-dissipation capability of the PCB design
Improving the thermal coupling of the component to the PCB
Introducing airflow in the system
Once the power dissipated in each device is calculated, the operating junction temperature must be determined to verify a safe operating environment. Junction temperature is found using the formula:
TJ = TA + (PO x RaJA)
If the junction temperature is higher than the desired maximum, one of the three approaches listed previously can be used to reduce RaJA.
Improving the power-dissipation capability generally means adding a thermal conduction plane or heatsink
to the PCB. Both choices require extra board space, but can be better than adding multiple or larger devices.
Heat flows from warmer surfaces to cooler surfaces. If a naturally cooler surface is available, it would be an
ideal heat sink.
Increasing the thermal coupling of the component to the PCB can reduce RaJA. This can be implemented by
the use of thermal compound or soldering of the component to the copper.
The use of forced airflow in low-power converters is generally an undesirable solution due to the added power useage of the fan. Natural convection airflow can be enhanced by the proper placement of the components and any vents that are available. Since warm air rises, vertical surfaces tend to transmit heat to the air
better than horizontal surfaces. The hottest devices should be located at the top of the board or toward the
output side of the airflow so as to reduce their effect on other components.
If RaJA cannot be reduced to a satisfactory level and power dissipation cannot be reduced, the only other
alternative is to select a larger device that can dissipate the power.
Figure 9-6 is an example of a thermally enhanced layout for a surface-mount power package with graphs
showing the effects of airflow and thermal conduction planes of various sizes.
9-104
L __ ,
,--1--.1
L ________ -.J
Figure H. Thermally Enhanced PWB Layout (not to scale) for the 2o-Pin TSSOP
9-105
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIRFLOW
190r-----~--------~----~~-----r--------~----~
Component/Board System
2o-Lead PW Package
170 I--~~--t--::= 0 cm2
150~-~--~--~~~~--+--~
130p-~~--rF~~~--r---+--~
70r--~---+---+---r--~-~
50~----~------~--~----~--~--~
o
50
100
150
200
250
300
Air Flow - ft/min
Figure 9-7
THERMAL RESISTANCE, JUNCTION-TO-AMBIENT
vs
AIR FLOW
~ 190~--~--~----~--~--~--~
Component/Board System
2o-Lead PW Package
Includes Thermally Conductive
Compound Between Body and Board
ir
I
il
:
:s
170
c::
o
~
c::
..,
~
~
c::
~
~
~
~cr: t~==r=~~~~~
~
II:
50
0
50
100
150
200
Air Flow - ft/min
Figure 9-8
9-106
250
300
Example
Figure 9-9 is an example schematic and layout of a dual output regulator using the TL 1454 controller chip.
Using the techniques discussed in this document resulted in a regulator with very clean outputs that produced little noise.
Note that the top side ground plane (Figure 9-10) is cut into two sections to keep the return currents in the
power section from flowing in the control section ground. The common point for the two sections of the
ground plane is at the bypass capacitor for the controller chip. This was done because the outputs are located at opposite sides of the board. Usually, the common point should be located as close as possible to the
output. Also note the short distance between the power switches 01 and 02 (Figure 9-11), the input capacitor C1, and the output capacitors C12 and C13. Heavy traces were used in the power section. The drive
circuits were located so as to minimize the distance between the controller and the drive transistors and
between the drive transistors and the power switches. In this layout the feedback traces are longer than is
usually desired, but with the separated ground planes and low inductance path, this configuration worked
very well. A better solution would have the feedback resistors closer to the controller.
R83.32kn
1%
R6
2.00kn
1%
C9
0.022 ~F
L2
Q2
TPSll0l0
5V~~---------------------+--------'-----~~'---'-~
C6
0.1 ~F
C15
0.1 ~F
R13
14
11
R14
3.3kn
13
12
Cl
R2
20 kU
+
C4
1500 pF
3
6
4
5
220~F
25V
R15
2.7kn
C2
0.1
2
~F
R4
10.0kn
1%
3.3V
@
750mA
R9
150U
+
-=-
VCC
C13
02
lN5817MC
REF
Cll
330pF
47~F
15V
OTC2
COMP2
OUT2 9
IN2+
IN2-
II ~~~H
TL1454
OTCl
COMPl
OUTl
-=-
Rl0
Cl0
330~F
8
12V
IN1+
IN1-
@
200mA
SCP
15
7
Ql
IRLD014
C7
1 ~F
-=-
GNO~e----.--~.-------~--~.-+-----~-----e
R5
2.49 kn
1%
\
-Rll
62U
10
16
22~H
R7 21.5 kn
1%
C8
0.Q15 ~F
Figure 9-9. Dual Regulator Schematic
9-107
Top Side (Ground Plane)
Control
••
Ground
• • •• •
Cutin
•
•
GP
,.
•• ••• ••• • e"", .......
"
• •• • • •
•
•
•
•
• • •• •• • • • •
• •• •
• •
•
"
•
•
""
•
• •
..........
,. ,.
~
..... .....
,...... ,, , •• •
••••
•
••
Power •
Ground ""
••••
• •
•
•• •
•• •
• •
"
."
. ."
"
,,~
... ...
~~
.
"
",
.....
'
"'.
"
;<
.~~~~.
""
""
"
" 1''''
Figure 9-10. Top Side Ground Plane
Bottom Side (Top View With Top Silk Screen)
TL1454
Demo Board
Outputs
3.3 V, 750mA
12V,200mA
Figure 9-11. Solder Side and Component Layout
9-108
10-1
Contents
Page
Tape and Reel Information .............................................. 10-3
Mechanical Information ............................ : .................... 10-7
10-2
TAPE AND REEL
OCTOBER 1995
0.031 (0,790) --f4-~
0.000 (0,00)
1.260 (32,00) MAX
0.031 (0,790)
0.000 (0,00)
0.031 (0,790)
0.000 (0,00)
0.539 (13,70) - - I + - - - t - - . !
0.430 (11,70)
0.031 (0,790) -+----!04f-+1
0.000 (0,00)
0.610 (15,50) MIN
0.696 (17,70)
\
I
\ I
\ I
\
II
II
II
U U U
II
II
0.242 (6,15)
0.230 (5,84)
0.020 (0,50) MIN
II
U U U
0.748 (19,00)
0.689 (17,50)
0.433 (11,00)
0.335 (8,SO)
0.114 (2,90)
0'1l!!4(2,4O)
0.114 (2,90)
0.094 (2,40)
14--.....-
0.512 (13,00) -i+-----~
0.488 (12,40)
0.266 (6,75)
0.234 (5,95)
0.169(4,30) DIA
0.146 (3,70)
:1
0.035 (0,90)
L
I~T
0.055 (1,40) MAX
0 ,50)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
Figure 10-1. Lead Taping Detail for TO-226-A (TO-92 Package)
~.TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10-3
TAPE AND REEL
OCTOBER 199&
i+----.r-
0.161 (4,10)
0.154 (3,91)
cp 0.063 (1,60)
0.063 (1,60)
0.055 (1,40)
0.059 (1,50)
0.161 (4,10)t
0.154 (3,91)
0.323 (8,20)
0.307 (7,80)
0.012 (0,30)
0.~(O,20)
I----CD
+
0.130 (3,30) -H~--~
0.122 (3,10)
t
0.043 (1,10)
0.039 (1,00)
Over 10 parts the range is 1.654 (42,00) .
1.496 (38,00)
0.567 (14,40)
0.457 (11,60)
----j4----+I
I .' I
I
0.858 (21 ,eO)
0.795 (20,20)
7.087 (180,00)
6.968 (177,00)
2.402 (61,00)
2.362 (60,OO)
~
0.520 (13,20)
0.504 (12,80)
0.366 (9,30)
0.343 (8,70)
I I
-H
Figure 10-2. Tape and Reel Information For the SOT-23 (OBV Package)
~TEXAS
10-4
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TAPE AND REEL
OCTOBER 1995
/+-_ _...... 0.161 (4,10)
0.154 (3,91)
rI\ 0.063 (1 ,60)
'P 0.059 (1,50)
0.319{8,10) - - .
0.311 (7,90)
0.0315 (O,80) MIN
~
r-
i
0.480 (12,20)
0.465 (11 ,80)
+
0.185{4,70)MIN
--f
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