1996_TI_Wireless_and_Telecommunications_Products_Data_Book 1996 TI Wireless And Telecommunications Products Data Book

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~TEXAS

INSTRUMENTS

Wireless and
Telecommunications Products
Central Office, Telemetry RF Receivers, and
Personal Communications Solutions

1996

Mixed-Signal Products

1IDI

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io_n________________
Telecommunications Circuits

Central Office Codecs

iii

Transient Voltage Suppressors

lEI

RF for Telemetry and RKE

•

Wireless Communications Circuits

Processors for Analog Cellular

•

Voice-Band Audio Processors.

III

RF for Personal Communications

•

Baseband Interface Circuits

III

Digital Signal Processors
Mechanical Data

Wireless and
Telecommunications Products
Data Book
Central Office, Telemetry RF Receivers, and
Personal Communications Solutions

~TEXAS

INSTRUMENTS

IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any
semiconductor product or service without notice, and advises its customers to obtain the latest
version of relevant information to verify, before placing orders, that the information being relied
on is current.
TI warrants performance of its semiconductor products and related software to the specifications
applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality
control techniques are utilized to the extent TI deems necessary to support this warranty.
Specific testing of all parameters of each device is not necessarily performed, except those
mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,
personal injury, or severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES
OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer.
Use of TI products in such applications requires the written approval of an appropriate TI officer.
Questions concerning potential risk applications should be directed to TI through a local SC
sales office.
In order to minimize risks associated with the customer's applications, adequate design and
operating safeguards should be provided by the customer to minimize inherent or procedural
hazards.
TI assumes no liability for applications assistance, customer product design, software
performance, or infringement of patents or services described herein. Nor does TI warrant or
represent that any license, either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or relating to any combination,
machine, or process in which such semiconductor products or services might be or are used.

Printed in U.S.A. by
Custom Printing Company
Owensville, Missouri

INTRODUCTION
The 1996 Wireless and Telecommunications Products Data Book has been created to showcase
our growing line of analog and digital components for telecommunications and wireless
applications. Featured in this data book are most of the components found in the 1993
Telecommunications Circuits Data Book, plus many new and exciting wireless communications,
telecom, and RF for telemetry and remote keyless entry products introduced since then.
This new data book is more than a collection of data sheets; it is a tool for locating the best
wireless and telecommunications components for a successful design effort. It has been
structured into two parts, first telecommunications, then wireless, to help you quickly find the
devices best suited to your application.
A complete alphanumeric index at the beginning of the data book makes locating data sheets for
known part numbers easy, and separate selection guides for telecom and wireless have
abbreviated application information and technical data to assist in your selection process. An
extensive glossary is provided for referencing, defining, and clarifying terms used by Texas
Instruments and the semiconductor industry that may be new, unfamiliar, or confusing.
While this data book offers design and specification data only for wireless and
telecommunications products, complete technical data for any TI semiconductor product is
available from your nearest TI Field Sales Office, local authorized TI distributor or by writing
directly to:
Texas Instruments, Incorporated
LITERATURE RESPONSE CENTER
Post Office Box 809066
Dallas, TX 75380-9066
or by visiting TI's web site at http://www.tLcom
A complete list of sales offices, distributors, and technology centers is located in the back of this
book.
We sincerely believe that the new 1996 Wireless and Telecommunications Circuits Data Book
is a valuable and useful addition to your collection of technical literature.

PRODUCT STAGE STATEMENTS
Product stage statements are used on Texas Instruments data sheets to indicate the development
stage(s) of the product(s) specified in the data sheets.

If all products specified in a data sheet are at the same development stage, the appropriate statement
from the following list is placed in the lower left corner of the first page of the data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty. Production processing
does not necessarily include testing of all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of
development. Characteristic data and other specifications are subject to change without notice.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products without notice.
If not all products specified in a data sheet are at the PRODUCTION DATA stage, then the first
statement below is placed in the lower left corner of the first page of the data sheet. Subsequent pages
of the data sheet containing PRODUCT PREVIEW information or ADVANCE INFORMATION are then
marked in the lower left-hand corner with the appropriate statement given below:
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information
current as of publication date. Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not necessarily include testing of
all parameters.
ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of
development. Characteristic data and other specifications are subject to change without notice.
PRODUCT PREVIEW information concerns products in the formative or design phase of
development. Characteristic data and other specifications are design goals. Texas Instruments
reserves the right to change or discontinue these products without notice.

General Information
Telecommunications Circuits

Transient Voltage Suppressors

II
lEI

RF for. Telemetry andRKE

•

Central Office Codecs

Wireless Communications Circuits

Processors for Analog Cellular

Voice-Band Audio· Processors

RF for Personal Communications

•

Baseband Interface Circuits

ill

Digital. Signal Processors

•

MechanicalOata

1-1

Contents
Page
Alphanumberic index. . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1-3
Telecom Introduction ......................................................• 1-5
Wireless Introduction ........................•..................•........... 1-7
Wireless Selection Guide .................................................. 1-11
Wireless Product Briefs .................................................... 1-25
Glossary .................................................................. 1-33

:::J

-h

o
3Q)
~

:::J

1-2

ALPHANUMERIC INDEX

DEVICE

PAGE

MARCSTARTM RF Application Report • • • • • • • • • • • •• 4-29

TCM8010-50

5-53

TCM1030 •••••••••••••••••••••••••••••••• 3-3

TCM8030 •••••••••••••••••••••••••••••••• 5-79

TCM1060 •••••••••••••••••••••••••••••••• 3-5

TLV320AC36 •••••••••••••••••••••••••••••• 6-63

TCM129C13 •••••••••••••••••••••••••••••• 2-3

TLV320AC37 •••••••••••••••••••••••••••••• 6-63

PAGE

TCM129C13A ••••••••••••••••••••••••••••• 2-27

TLV320AC40 •••••••••••••••••••••••••••••• 6-83

TCM129C14 •••••••••••••••••••••••••••••• 2-3

TLV320AC41 •••••••••••••••••••••••••••••• 6-83

TCM129C14A ••••••••••••••••••••••••••••• 2-27

TLV320AC56 •••••••••••••••••••••••••••••• 6-103

TCM129C16 •••••••••••••••••••••••••••••• 2-3

TLV320AC57 •••••••••••••••••••••••••••••• 6-103

TCM129C16A ••••••••••••••••••••••••••••• 2-27

TMS320C209 ••••••••••••••••••••••••••••• 9-3

TCM129C17 •••••••••••••••••••••••••••••• 2-3

TMS320C5x •••••••••••••••••••••••••••••• 9-67

TCM129C17A ••••••••••••••••••••••••••••• 2-27

TMS320C54x ••••••••••••••••••••••••••••• 9-149

TCM129C18 •••••••••••••••••••••••••••••• 2-51

TMS320LC5x ••••••••••••••••••••••••••••• 9-67

TCM129C19 •••••••••••••••••••••••••••••• 2-51

TMS320LC54x •••••••••••••••••••••••••••• 9-149

TCM129C23 •••••••••••••••••••••••••••••• 2-69

TMS320VC203 •••••••••••••••••••••••••••• 9-3

TCM29C13 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-3

TMS320VC54x

9-149

TCM29C13A • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-27

TP13054A

2-145

TCM29C14 •• • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-3

TP130548

2-161

TCM29C14A • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-27

TP13057A

2-145

TCM29C16 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-3

TP130578

2-161

TCM29C16A •••••••••••••••••••••••••••••• 2-27

TP13064A

2-177

TCM29C17 ••• • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-3

TP130648

2-197

TCM29C17A •••••••••••••••••••••••••••••• 2-27

TP13067A

2-177

TCM29C18 ••••••••••••••••••••••••••••••• 2-51

TP130678

2-197

TCM29C19 ••••••••••••••••••••••••••••••• 2-51

TP3054A

2-145

TCM29C23 •• • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-69

TP30548

2-161

TCM320AC36 •• • • • • • • • • • • • • • • • • • • • • • • • • • •• 6-3

TP3057A

2-145

TCM320AC37 • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 6-3

TP30578

2-161

TCM320AC38 ••••••••••••••••••••••••••••• 6-23

TP3064A

2-177

TCM320AC39 ••••••••••••••••••••••••••••• 6-23

TP30648

2-197

TCM320AC54 • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 2-89

TP3067A

2-177

TCM320AC56 ••••••••• • • • • • • • • • • • • • • • • • • •• 6-43

TP30678

2-197

TCM320AC57 • • • • • • • • • • • • • • • • • • • • • • • • • • • •• 6-43

TPS9103

7-65

TCM37C13 ••••••••••••••••••••••••••••••• 2-105

TRF1015

7-3

TCM37C14 ••••••••••••••••••••••••••••••• 2-105

TRF1400

4-3

TCM37C15 ••••••••••••••••••••••••••••••• 2-105

TRF1410

4-21

TCM38C17 ••••••••••••••••••••••••••••••• 2-125

TRF2040

7-13

TCM4300 •••••••••••••••••••••••••••••••• 8-3

TRF2050

7-25

TCM4301 •••••••••••••••••••••••••••••••• 8-51

TRF3020

7-37

TCM4400 •••••••••••••••••••••••••••••••• 8-113

TRF7000

7-47

TCM8002 •••••••••••••••••••••••••••••••• 5-3

TRF8010

7-57

TCM8010-37 ••••••••••••••••••••••••••••• 5-25
NOTES:

1. ThefoIJowing devices have been deleted from this volume: TCM15018, TCM15068, TCM15128, TCM1520A, TCM1531, TCM1532,
TCM1536, TCM1539, TCM5087, TCM5087, TCM5089, TCM5092, TCM5094, TLC2470ITLC2471 ITLC2472ITLC2047
2. TheTCM3637now appears in the Remote Keyless Entry Data 800k.

MARCSTAR is a trademark of Texas Instruments Incorporated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-3

1-4

TELECOM INTRODUCTION

Introduction
Texas Instruments has been a world leader in central office codec technology since 1979. The combo section
of this data book includes our established product line of codecs with on-chip filtering, primarily used in central
office (line card) applications that perform the AID and D/A conversion and filtering required for voice
communications. The TP30xx series and TCM29Cxx series of combos provide the industry's best noise levels
using Tl's advanced switched-capacitor filter technologies. The TCM1 Oxx family of devices compliments our
line of codecs by providing protection from voltage transients for the codecs as well as the line cards.
Smaller geometry process technology and sigma-delta conversion technologies are combined this year in our
first Advanced Combo™ product offering, the highly integrated QCombo™, TCombo™, and Combo III. The
QCombo and TCombo are single-rail 4-channel (quad) and 2-channel (twin) combos-on-a-chip. The Combo
III features TCM29C13 functionality with the addition of programmable gain. Texas Instruments is rapidly
expanding it's Advanced Combo product family - see our road maps for additional information.
For the past 13 years, Texas Instruments has manufactured an advanced line of fixed-code RKE (remote
keyless entry) products. This year, Texas Instruments is proud to introduce the MARCSTARTM (Multi-Channel
Advanced Remote-Control Signaling Transmitter And Receiver) family of RKE devices. These devices are
advanced ASKIFSK RF receivers and mixed-signal rolling-code encoder/decoders utilizing new and innovative
features that are industry first. The MARCSTAR RF section featured in this data book represents a portion of
that family that provides turn-key receiver solutions on-a-chip. While primarily targeted at the RKE, GOO
(garage door opener), and home security markets, the TRF140xx device family is also well suited to other
low-power remote control and general telemetry applications. The MARCSTAR RF devices require a minimum
of external components, significantly reducing circuit complexity and footprint compared to the current discrete
receiver solutions. Using an RF architecture that is an RKE-industry first, MARCSTAR RF receivers feature no
spurious emissions and infinite image rejection.
The MARCSTAR RFfamily maintains good sensitivity and out-of-band rejection with no manual alignment when
used with external SAW filters. For a reduced-cost solution, the device is also compatible with external UC
components. MARCSTAR RF also includes several on-chip features that would normally require additional
circuitry in a receiver system design. These include an RF amplifier/comparator for detection and shaping of
input signals and decoding logic that provides specially formatted TTL data output, synchronized with a trigger
output, for easy interface to any microcontroller when using Manchester-encoded data. The device also outputs
raw demodulated AM at TTL levels using any ASK data for interface to self-synchronizing devices such as the
TI rolling-code MARCSTAR encoder/decoders (covered in the TI RKE data book).
Texas Instruments is also rapidly expanding its MARCSTAR product family - see our roadmaps in this data
book, as well as our separate RKE data book, for further information on the full MARCSTAR RF and
encoder/decoder device families.

MARCSTAR, Advanced Combo, QCombo, and TCombo are trademarks of Texas Instruments Incorporated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-5

1-6

current Tiline-card codec product offering
TCMxxCxx

Intel Timing
For Central Office Equipment Use
Reduced Noise
(by 50% using a patented TI process)

Direct Intel Replacement

Both Il-Law and
A-Law

Low Cost

§Cl'T1

!~~
l'T1..,1

Extended
Frequency

8th Bit
Signal

Standard

Il- Law

A-Law

8th Bit
Signal

Standard

Il-Law

A-Law

Il- Law
and
A-Law

Il-Law and A-Law
Single Voltage
Supply ( +5V)

Il- Law

Il-Law and
A-Law

2.048
MHz

1.536
1.544
2.048
MHz

2.048
MHz

1.536
1.544
2.048
MHz

2.048
MHz

1.536
1.544
2.048
MHz

2.048 MHz

2.048
MHz

1.536
MHz

upto 4.096
MHz

TCM
29C16

TCM
29C17

TCM
29C14

TCM
29C13

TCM
29C16A

TCM
29C17A

TCM
29C14A

TCM
29C13A

TCM
37C13

TCM
37C15

TCM
37C14

TCM38C17

TCM
29C18

TCM
29C19

TCM
29C23

m(J)

~~d

Quad channel
QCOMBO

A-Law

Programmable Gain
Reduced Noise

Il-Law

O~~
~ 2 _.

Interface For DSP

PAGE NO.
PAGE NO. 2-3
LIT. NO. SCTS011 G

PAGE NO. 2-27
LIT. NO. SCTS030D

PAGE NO. 2-105
LIT. NO. SLWS018

PAGE NO. 2-125
LIT. NO.
SLWS040

PAGE NO.2-51
LIT. NO. SCTS021 C

2~9

LIT. NO.
SCTS029A

~~
>
rJl

~
~

m
rm
o

CJ)

oz
G)

5:
~

c
m

TELECOM SELECTION GUIDE

current TIline-card codec product offering (continued)
TP30xx
National Timing
For Central Office EquIpment Use
Reduced NoIse
(by 50% usIng a patented TI process)

DIrect NatIonal Replacement
DIfferentIal Output

SIngle Ended Output

Differential Output

Interface For
DTAD/DSP
SIngle Ended

J.1-Law

A-Law

J.1-Law

A-Law

J.1-Law

A-Law

J.1-Law

A-Law

J.1-Law

1.536
1.544
2.048
MHz

TP3064A

TP3067B

TP3054A

TP3057B

TP3054B

TP3057A

TP3064B

TP3067A

TCM320AC54

PAGE NO. 2-161
LIT. NO. SCTS042A
PAGE NO.

PAGE NO. 2-145
LIT. NO. SCTS026C

6~3

LIT. NO.
SCTS029A

PAGE NO. 2-197
LIT. NO. SCTS031D
PAGE NO. 2-177
LIT. NO. SCTS025C

transient voltage suppressors
DESCRIPTION

TECHNOLOGY

FUNCTION

Line card suppressor

Dual transient
voltage
suppressor

SUPPLY
VOLTAGE
-5Vto
-65V

Bipolar

DEVICE

PAGE

Firing voltage: -70 V, Max peak surge
current: 35 A

TCM1030

Firing voltage: -70 V, Max peak surge
current: 50 A

TCM1060

PRODUCT FEATURES

remote keyless entry and general telemetry receivers
DESCRIPTION

FUNCTION

VHF/UHF ASK
RZ receiver

Remote
keyless
Entry/General
Telemetry

VHF/UHF ASK
RZ receiver

Remote
keyless
Entry/General
Telemetry

TECHNOLOGY

Submicron
BiCMOS

SUPPLY
VOLTAGE

PRODUCT FEATURES

DEVICE

PAGE

200 Hz to 450 MHz high receiver sensitivity,
500 Hz to 20 KHz data rate,
Internal amplifier comparator,
No emissions,
Infinite image rejection,
No manual alignment,
Internal Manchester decoder

TRF1400

4-3

200 Hz to 450 MHz high receiver sensitivity,
500 Hz to 20 KHz data rate,
Internal amplifier comparator,
No emissions,
Infinite image rejection,
No manual alignment,

TRF1410

4-21

~TEXAS
1-8

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TELECOM SELECTION GUIDE

'x
CI)

C.
E

()

1992

1994

1996

1998

2000

ADVANCED COMBO
ROADMAP

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-9

TELECOM SELECTION GUIDE

D..
E
o

1995

1996

1997

1998

MSP RF Thrust

~TEXAS

INSTRUMENTS
1-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1999

2000

WIRELESS INTRODUCTION

Introduction
Texas Instruments portfolio of digital signal processor (DSP) solutions addresses the key technologies required
to achieve success in today's fast-moving wireless communications market. To help OEMs gain a competitive
edge, TI provides system solutions including components, software modules, development tools,
demonstration platforms and global development support. Our customizable DSP (cDSP) capability can create
highly-integrated, low-power, custom solutions fine-tuned for specific needs.
With worldwide manufacturing capacity and expertise, including high-yielding processes and tight parametric
control, Texas Instruments can supply wireless communications OEMs with the large volumes they need to
meet their production requirements. We continue to invest in manufacturing capacity to keep pace with our
customers' growing needs.
The devices in this databook support the world's most widely adopted standards in analog cellular, digital and
dual-mode cellular, personal communications services (PCS), digital cordless telephones, paging, wireless
local loop systems, wireless data, and more. The product families addressed in this databook include:
•

Baseband Processors for Analog Cellular Handsets

•

Voice-Band Audio Processors (VBAPTM)

•

Radio Frequency (RF) Products For Personal Communcations

•

Baseband Interface Circuits

•

ASICs

•

DSPs

•

Microcontrollers

•

System Solutions

•

Data Converters

•

Operational Amplifiers

•

Low Drop-Out Regulators

•

Power Management Products

The alphanumeric index in this data book provides a means of quickly locating the device type. The selection
guide includes a brief description of each device and references to additional literature items about that product
family. The glossary describes the symbols, terms, and definitions used in this data book.
Additional literature is available from your nearest Texas Instruments Field Sales Office, local authorized TI
distributor, or by writing directly to:
Texas Instruments Incorporated
LITERATURE RESPONSE CENTER
P.O. BOX 809066
Dallas, TX 75380-9066
A list of TI sales offices, distributors, and technology centers is located in the back of this book.
In addition, the latest information on wireless communications products is available on the Internet. Visit the TI
Wireless Communications home page at http://www.ti.com/sc/docs/wireless/home.htm. or access the full range
of Tl's Semiconductor products using the TI home page at http://www.tLcom.
Thank you for your interest in wireless personal communications products from Texas Instruments.
VBAP is a trademark of Texas Instruments Incoporated .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-11

1-12

WIRELESS SELECTION GUIDE

selection guide
Antenna

Cellular Telephone Handset
RFIIF Subsystem
Digital Cellular Baseband Subsystem

Microphone

Data Converters
TLCfTLVXXXX

Signal Conditioning
Operational Amplifiers
TLCfTLV22XX

Power Supplies and Switches
TPSXXXX
Battery

TPSXXX Low Drop-Out Regulators
Power Management Subsystem

baseband processors for analog cellular handsets
VOICE PROCESSOR

PAGE

DATA PROCESSOR

SUPPLY
VOLTAGE

PAGE

TCM8002

5-3

TCM801D-50

5-53

TCM801D-37

3.7V

5-25

2.7-5.5 V

5-59

Voice and Data Processor
TCM8030t

t Product Preview
NOTE 1: TCM8000 is obsolete - replace with TCM8010-50 or TCM8010-37 .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-13

WIRELESS SELECTION GUIDE

VBApTM voice-band audio processor (voice codecs for wireless personal communications)
PRIMARY APPLICATION

IS-19, IS-54/136 and digital cordless

13-BIT LINEAR
MODE AND
Il- LAW

13-BIT LINEAR
MODE AND
A-LAW

MASTER
CLK
(MHZ)

SUPPLY

PAGE

TLV320AC36

TLV320AC37

2.048

6-63

IS-19, IS-54/136 and digital cordless, noise
cancellation disabled

TLV320AC56t

TLV320AC57t

2.048

6-103

DECT

TLV320AC40t

TLV320AC41t

1.152

6-83

IS-19, IS-54/136 and digital cordless, noise
cancellation disabled

TCM320AC56t

TCM320AC57t

2.048

6-103

Reduced spec 'AC36

TCM320AC46:t:

N/A

2.048

GSM

TCM320AC38

TCM320AC39

2.600

6-23

IS-19, IS-54/136 and digital cordless

TCM320AC36

TCM320AC37

2.048

6-3

t Product Preview data
:t: TCM320AC46 is obsolete -

replace with TCM320AC36.

additional VBAP literature
Voice-Band Audio Processors Application Report

radio frequency products for wireless personal communications
PRIMARY APPLICATION

FUNCTION

DEVICE

SUPPLY VOLTAGE

PAGE

Receiver front end

TRF1015t

3.5-5.5 V

7-3

Fractional-N 1 Integer-N
Synthesizer

TRF2040t

2.7-3.6 V

7-13

1.1 GHz: 18-54/IS-136

Fractional-N 1 Integer-N
Synthesizer

TRF2050t

2.7-5.1 V

7-25

900 MHz: Analog, Digital, Dual Mode Cellular;
PCS

I/Q and FM Modulator

TRF3020t

3.6-3.9 V

7-37

900 MHz-1.9 GHz: Analog, Digital, Dual Mode
Cellular; PCS

GaAs MESFET Output
Stage

TRF7000t

3.6VAMPS
4.8 V GSMIIS-54/IS-136

7-47

3.6 VAMPS
4.8 V GSM/IS-54/IS-136

7-57

900 MHz: Analog, Digital, Dual Mode Cellular;
Digital Cordless
900 MHz-1.9 GHz: Analog, Digital, Dual Mode
Cellular; PCS

900 MHz: Analog, Digital, Dual Mode Cellular

Driver Amplifier

TRF8010t

Analog, Digital, Dual Mode Cellular; PCS

Power Supply for GaAs
Power Amplifiers

TPS9103t

t Product Preview data

baseband interface circuits for wireless personal communications
PRIMARY
APPLICATION

PAGE

RFCODEC

PAGE

IS-54B

TCM320AC36 or
TLV320AC36

6-3
6-63

TCM4300t

8-3

IS-136

TCM320AC36 or
TLV320AC36

6-3
6-63

TCM4301t

VOICE CODEC

GSM

TCM4400t

8-51
8-113

t Product Preview data

VBAP is a trademark of Texas Instruments Incorporated.

~TEXAS

INSTRUMENTS
1-14

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2.7-5.5 V

7-65

WIRELESS SELECTION GUIDE

digital signal processors
DSP standard device family roadmap
Multiprocessor

ena.

32-bit
Floating Point

9
u.

~a.

16-bit
Fixed Point

~
C1I
U
I:
I'CI

't:
C1I

Generation

general DSP literature
LIT. NO.

DSP Solutions Selection Guide

SSDVOO4

TMS320

DSP Production Overview (Flipbook)

SPRZ094C

TMS320

DSP Brochure

SPRB113

TMS320

Revised Software Co-op Data Sheet Package

SPRT111B

TMS320

Development Support Brochure

SPRT096B

TMS320

Development Support Reference Guide

SPRU011D

TMS320

Third Party Support Guide

SPRU052C

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-15

WIRELESS SELECTION GUIDE

TMS320C2xx family

TMS320C203/209

PAGE
Data Sheet

9-3

TMS320C2xx product specification guide
RAM

(Words)
ROM

TMS320C203-80

544

Boot

TMS320C204-80

544

TMS320C205-80

4.5

Boot

TMS320C209-57

4.5

TMS320F206-80

4.5

32K

TMS320F207 -80

4.5

32K

DEVICE

FLASH

INSTRUCTION
CYCLE (ns)

MIPS

PACKAGING

100TQFP

28.5

80TQFP

100TQFP

144 TQFP

SER

NOTE 1: All devices: data/program space = 64kB/64kB, DMA = external, timers = 1, parallel port = 64K x 16.

TMS320C2xx additional literature
LIT. NO.
'C2XX

User's Guide

SPRU127A

'C2XX

Product Bulletin

SPRT122A

~TEXAS

INSTRUMENTS
1-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS SELECTION GUIDE

TMS320C5x family
PAGE

Data Sheet

TMS320C5x

9-67

TMS320C5x product specification guide
RAM

(Words)
ROM

SER

TMS320C50-57 t:t

10K

Boot

TMS320C50-80 §

10K

Boot

t:t:

TMS320C51-100 :t:

t:t

INSTRUCTION
CYCLE (ns)

MIPS

28.57

132 PQFP

28.57

132 PQFP
100TQFP

28.57

100 PQFP
100TQFP

TMS320C52-80

100 PQFP
100 TQFP

TMS320C52-100 :t:

100 PQFP
100 TQFP

TMS320C53-80

16K

100 PQFP

16K

28.57

100TQFP

TMS320C53S80

16K

100 TQFP

TMS320LBC56-80

32K

2§

100TQFP

TMS320LBC57 -80

32K

2§

HPI

128 TQFP

TMS320BC57S-80

Boot

2§

HPI

144 TQFP

DEVICE

TMS320C51-57

TMS320C52-57

TMS320C53S57

t:t

COM

PACKAGING

t Extended temperature version available
:t: 3.3 V version available
§ Buffered serial port
NOTE 1: All devices: boot loader available, data/program space

=64kB/16kB, DMA = external, timers = 1, parallel port = 64K x 16.

TMS320C5x additional literature
LIT. NO.
TMS320C5x

User's Guide

SPRU056B

TMS320C5x

Fixed-Point DSP Production Bulletin

SPRT119A

'C5x

Power Dissipation Application Report

SPRA030

'C5x

DSP Seminar Workbook

SPRW017

'C5x

Telecommunications Appliations With 'C5x

SPRA033

'C5x

On-chip Oscillator With External Resonator

SPRA054

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-17

WIRELESS SELECTION GUIDE

TMS320C54x family
PAGE

ITMS320C54xt

9-67

Data Sheet

t Advance Information data

TMS320C54x product specification guide
Device

OAT/PRO

SER

COM

INSTRUCTION

PACKAGING

CYCLE (ns)

MIPS

100 TOFP
128,144 TOFP

HPI

100 TOFP

HPI

128, 144 TOFP

2t:J:

100 TOFP

HPI

128 TOFP

64K164K

100 TOFP

TMS320LC548#-66

4M/64K

3t:!:

HPI

144 TOFP

TMS320VC541 #-50

64K164K

TMS320VC542#-50

64K164K

2t:J:

TMS320VC543#-50

64 Kl64 K

2tt

TMS320VC545#-50

64K164K

TMS320VC546#-50
TMS320VC548#-50

TMS320C541 #-40

64K164K

TMS320C542#-40

64K164K

2t:J:

TMS320LC541 #-50

64K164K

TMS320LC542#-50

64K164K

2t:J:

TMS320LC543#-50

64 Kl64 K

TMS320LC545#-66

64K164K

TMS320LC546#-66

100 TOFP

HPI

128, 144 TOFP

100 TOFP

HPI

128 TOFP

64K164K

100 TOFP

4M/64K

3tt

HPI

144 TOFP

t Buffered serial port (C548 has 2)
:t: 1 TOM serial port
NOTES: 2. All devices: bootloader avaliable, DMA =external, timers = 1, parellel port = 64K x 16, OAT/PRO = data/program space, # =
1 for PLL option 1 or # = 2 PLL for option 2 (see User's Guide for details), LC = 3.3 V, VC = 3 V part

TMS320C54x additional literature
LIT. NO.
TMS320C54x

Product Bulletin

SPRT121A

TMS320C54x

User's Guide

SPRU131

'C54x

Serial Ports User's Guide Addendum

SPRU156

'C54x

Source Debugger User's Guide

SPRU099A

'C54x

Assembly Language Tools User's Guide

SPRU102A

~TEXAS

INSTRUMENTS
1-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS SELECTION GUIDE

custom digital baseband solutions
To allow for higher integration levels and to further reduce chip count, power dissipation, and system cost, TI
offers the capability to create a custom device around DSP and microcontroller cores. TI's customizable DSP
(cDSP) and customizable microcontroller (c470) technologies allow the single-chip integration of the DSP cores
with the TMS470 microcontroller core, additional memory, peripherals, logic gates, and analog modules in the
ASIC backplane.

ASIC standard cell - family roadmap

·iii
c
CI)
Q

1993

1994

1995

1996

1997

1998

1999

Currently, TI is developing the TSC4000 and TSC5000 standard cell ASIC product familes that are optimized
for ultra-low power and highly integrated applications. Designers in the wireless market can take full advantage
of the low power consumption for extended battery life, high density capability to integrate complex functions,
high performance for multiple applications, and leading design tools capabilities that reduce overall design
cycle-time.

additional ASIC literature:
DEVICE

STANDARD CELL LITERATURE

LIT. NO.

TSC20005-V

Product Information

SRSTOO1

TSC30003.3-V

Product Information

SRSTOO2

TSC2000LV 3.3-V

Product Information

SRSTOO3

additional microcontroller literature:
DEVICE

MCU LITERATURE

TMS470R1X-

User's Guide

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-19

WIRELESS SELECTION GUIDE

TSC2000
5-V O.55-f.lm CMOS Standard Cell
Product Information
Overview
•

5-V, O.55-llm Leff, Triple-Level Metal (TLM)
Process

•

Core Cell Library Optimized for Synthesis
and Low Power

•

Digital Signal Processor Cores

•

Clock Tree Synthesis

•

Support for SynopsysTM DesignPower

•

Batch and Graphics Mode Floorplanner

•

Third-Party CAD Signoff

•

Datapath Function Generation with
Interface to Synopsys Through
DesignWare™

Routing channels:
Not always necessary
between cell rows and
can be variable width.
Standard cell rows:
All cells are the same
height but variable width.

D
D

•

Memory Compilers Including Single-Port,
Two-Port, Dual-Port, and ROM

•

TTL, CMOS, SCSI-20, ATA-2, Ultra-LowPower and, Ultra-Low-Noise 1I0s

•

OFP and TOFP Packaging

•

1-IlW/MHzlGate Typical Power Dissipation

•

Typical Gate Delays of 165 ps (2-lnput
NAND, FO = 2)

I/O slot

Bond pad

Features and Benefits
FEATURES

BENEFITS

Robust support for leading CAD tools

Third-party CAD signoff

Synthesis-optimized cell library

High-density synthesis results and lower power

Tight coupling between synthesis, floorplanning, and layout

Shorter design cycle time

Support for Synopsys Design Power

Accurate power analysis

Ultra low noise I/Os

Reduced power pin requirements and lower system noise

Ultra low power 1/05

Low power system solutions

Low power cells

Low power system solutions

Clock tree synthesis

Insertion delay and skew management. Low power clock
distribution. Support for high number of clocks.

Datapath synthesis

Efficient implementation of datapath logic

Analog cells

System integration

SCSI Fast-20, ATA-2 I/Os

Direct interface to SCSI/ATA-buses

~TEXAS

INSTRUMENTS
1-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS SELECTION GUIDE

TSC2000LV
3.3-V O.55-fJ,m CMOS Standard Cell
Product Information
Overview

•

•
•
•
•
•
•
•

•
•
•
•
•

3.3-V, O.55-llm Lett, Triple-Level Metal (TLM)
Process
Core Cell Library Optimized for Synthesis
and Low Power
Analog

Functi~ns

Routing channels:
Not always necessary
between cell rows and
can be variable width.
Standard cell rows:
All cells are the same
height but variable width.

Clock-Tree Synthesis
Support for SynopsysTM DesignPower™
Batch and Graphics Mode Floorplanner
Third-Party CAD Signoff
o

Datapath Function Generation with
Interface to Synopsys Through
DesignWare™

Memory Compilers Including Single-Port,
Two-Port, Dual-Port, and ROM

TTL, LVCMOS, Ultra-Low-Power, and
Ultra-Low-Noise II0s
QFP and TQFP Packaging

O.42-IlW/MHzlGate Typical Power
Dissipation
Typical Gate Delays of 210 ps (2-lnput
NAND, FO =2)
110 slot

Bond pad

Features and Benefits
FEATURES

BENEFITS

Robust support for leading CAD tools

Third-party CAD signoff

Tight coupling between synthesis, floorplanning, and layout

Shorter design cycle time

Support for Synopsys DesignPower

Accurate power analysis

Ultra-low-noise liDs

Reduced power pin requirements and lower system noise

Ultra-low-power liDs

Low-power system solutions

Low-power cells

Low-power system solutions

Clock tree synthesis

Insertion delay and skew management. Low-power clock
distribution. Support for high number of clocks.

Datapath synthesis

Efficient implementation of datapath logic

Analog cells

System integration

Level-shifting liDs

Interface from 3-V core to 5-V signaling environment

Synthesis-optimized library

High-density synthesis results and lower power

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-21

WIRELESS SELECTION GUIDE

TSC3000
3.3-V O.44-fJ,m CMOS Standard Cell
Product Information
Overview
•

3.3-V, 0.44-llm Leff, Triple-Level Metal (TLM)
Process

•

Core Cell Library Optimized for Synthesis
and Low Power

•

Digital Signal Processor and
Microcontroller Cores

•

Clock-Tree Synthesis

•

Support for SynopsysTM DesignPower™

•

Batch and Graphics Mode Floorplanner

•

Third-Party CAD Signoff

•

Datapath Function Generation with
Interface to Synopsys Through
DesignWare™

•

Memory Compilers Including Single-Port,
Two-Port, and Dual-Port

•

TTL, LVCMOS, 5-V-Tolerant, Ultra-LowPower, Ultra-Low-Noise I/Os

Routing channels:
Not always necessary
between cell rows and
can be variable width.
Standard cell rows:
All cells are the same
height but variable width.

•

OFP and TOFP Packaging

•

0.33-IlW/MHzlGate Typical Power

c
c
c

c
c

Dissipation
•

Typical Gate Delays of 120 ps (2-lnput
NAND, FO = 2)

Tight MaxiMin Performance Ratio (2:1
Commercial Conditions)

Bond pad

I/O slot

Features and Benefits
FEATURES

BENEFITS

Robust support for leading CAD tools

Third-party CAD signoff

Tight coupling between syntheSis, floorplanning, and layout

Shorter design cycle time

Support for Synopsys Design Power

Accurate power analysis

Ultra-low-noise I/Os

Reduced power pin requirements and lower system noise

Ultra-low-power I/Os

Low-power system solutions

Low-power cells

Low-power system solutions

Clock-tree synthesis

Insertion delay and skew management. Low-power clock
Support for high number of clocks.

distribution.

Datapath synthesis

Efficient implementation of datapath logic

5-volt-tolerant cells

Interface to external 5-V logic

Tight min/max performance window due to advanced
manufacturing capability

Eases chip and system-level timing issues due to delay spread

1-22

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

operational amplifiers
VIO
mV
(max)

DEVICE

DESCRIPTION

0.001

0.12

0.2

I,M

Dual,low power, rail-to-rail output,low noise

0.063

0.001

0.12

0.2

I,M

Quad, low power, rail-to-rail output, low noise

TLV2252A

0.85

0.5

0.063

0.001

0.12

0.2

I,M

Dual, low voltage, rail-to-rail output, low noise

TLV2254A

0.85

0.5

0.063

0.001

0.12

0.2

I,M

Quad, low voltage, rail-to-rail output, low noise
Dual, low power, rail-to-rail output, low noise

TLC2274

TEMPt
RANGE

0.063

TLC2272A

~~
»
en

(typ)

0.5

~2:

GBW
MHz
(typ)

0.5

TLC2264A

~m(l)

SR
V/~s

0.85

TLC2272

~~d
~em
~~~

Vn (1 kHz)
nV/-#tZ
(typ)

0.85

TLC2264

CMRR
dB
(typ)

TLC2254A

TLC2262

~mt/)
2:

liB
nA
(typ)

TLC2252A

TLC2262A

O~~

(typ)

ICC
mA
(max)

aVIO
~V/oC

TLC2274A
TLV2262
TLV2262A
TLV2264
TLV2264A
t C

2.5

0.25

0.001

0.55

0.82

C,I

0.95

0.25

0.001

0.55

0.82

C,I

Dual, precision, low power, rail-to-rail output

2.5

0.25

0.001

0.55

0.82

Quad, low power, rail-to-rail output, low noise

0.95

0.25

0.001

0.55

0.82

2.5

0.001

3.6

2.18

0.95

0.001

3.6

2.18

Dual, rail-to-rail output, precision

2.5

0.001

3.6

2.18

Quad, rail-to-rail output

Quad, rail-to-rail output, precision

Quad, low power, rail-to-rail output, low noise
Dual, rail-to-rail output

0.95

0.001

3.6

2.18

2.5

0.25

0.001

0.55

0.82

Dual, precision, low voltage, low power, rail to rail

0.95

0.25

0.001

0.55

0.82

Dual, precision, low voltage, low power, rail to rail

2.5

0.25

0.001

0.55

0.82

Quad, precision, low voltage, low power, rail to rail

0.95

0.25

0.001

0.55

0.82

Quad, precision, low voltage, low power, rail to rail

fixed output voltage series pass regulators
DEVICE

Vo
(V) NOM

10
(mA)
MAX

250

TPS7233
TPS7333

3.3

TPS7133

TPS7348

4.85

TPS7148
TPS7250
TPS7350

500
250

TPS7248

500
250

TPS7150
t Supply-voltage supervisor

=O°C to 70°C, I =-40°C to 85°C, M =-55°C to 125°C

TOL

('Yo)

Iq
(mA)TYP

VDO
(V)
TYP-MAX

Vlmax
(V)

LDO

SHUT
DOWN

svst

DESCRIPTION

POSITIVE OUTPUT VOLTAGE

500

5j
2

1551lA

0.14-0.18

340llA

0.044-0.06

2851lA

0.047 - 0.060

-40°C to 125°C

Lowest droput PMOS

1551lA

0.09-0.1

-40°C to 125°C

Very low dropout PMOS

340llA

0.028 - 0.037

-40°C to 125°C

Lowest dropout PMOS with svst

2851lA

0.03-0.037

-40°C to 125°C

Lowest dropout PMOS

1551lA

0.76 - 0.85

-40°C to 125°C

Very low dropout PMOS

340llA

0.27 -0.035

-40°C to 125°C

Lowest dropout PMOS with svst

2851lA

0.27 -0.033

-40°C to 125°C

Lowest dropout PMOS

-40°C to 125°C

Very low dropout PMOS

-40°C to 125°C

Lowest dropout PMOS with

svst

m
r-

en
en
en
m
rm
o

--I

oZ
C)

adjustable series pass regulators

:E
:c

-1>0

DEVICE
TPS7201

Vo
(V)
MIN-MAX

10
(mA)
MAX

1.2-9.75

250

TOl
(%)

Iq
(mA)TYP

VDO
(V)
TYP-MAX

155JlA

0.16-0.27

Vlmax
(V)

lDO

SHUT
DOWN

TPS7301

1.2 - 9.75

250

340JlA

0.052-0.085

TPS7101

1.2-9.75

500

285JlA

0.052-0.085

svst

-40°C to 125°C

DESCRIPTION

en
en
en

Very low dropout PMOS adjustable

svst

-40°C to 125°C

Lowest dropout PMOS with

-40°C to 125°C

Lowest dropout PMOS adjustable

Supply-voltage supervisor

(")

-I

supply voltage supervisors

DEVICE

Vt
(V)

TOL
(%)

TLC7705

4.55

1.5

25JlA

TL7705A

4.55

3.60

Single SVS for 5 V systems with programmable time delay

~~~
62
_.

TL7705B

4.55

Single SVS for 5 V systems with programmable time delay

ffi~mf

~ (TH/)

DEVICE

~.,

~C/)
(fl

PROGRAMMABLE
TIME DELAY

COMPLEMENTARY
OUTPUTS

G')

DESCRIPTION

c
m

Single micropower SVS (5 V) with programmable time delay and
push-pull outputs

---

p-channel MOSFETs

~C><

~~;J>

VI min
(V)

ICC
(mA) MAX

VDS
(V)

rDS(on)
(VGS=-10 V)

rDS(ON)
VGES =-10 V)

rDS(ON)
VGES -2.7 V)

10
(A)

DESCRIPTION

MAX

TYP

MAX

TPS1100

-15

0.18

0.291

0.606

+1.58

Single p-channel enhancement-mode MOSFET

TPS1101

-15

0.09

0.134

0.232

±2.12

Single p-channel enhancement-mode MOSFET
Single p-channel enhancement-mode MOSFET

TPS1110

-7

0.065

0.100

-6

TPS1120

-15

0.18

0.291

0.606

±1.7

Dual p-channel enhancement-mode MOSFET

additional Mixed Signal Products literature:.
LIT. NO.
1996 Designer's Guide and Reference

SLYU001

Data Converter Selection Guide

SLAT079

Data Acquistion Data Book

SLAD001

Understand Data Converters Application Report

SLAA013

Supplement to the Linear Circuits 3-V Family

SLYD013

Power Supply Circuits

SLYD002

Operational Amplifiers and Comparators, Volume A

SLVD011

Operational Amplifiers and Comparators, Volume B

SLYD012

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT001

TCM8010JTCM8002
Analog Cellular System Solutions Product Brief
Analog Cellular Phone

r------------------.
,
,
,

RF Section

Antenna'
,
,
,

,,
I
I
I
I
IL

TCM8010
Audio Processor

ADC2

RSSI'
~----------IF-T-r-im~~ ADC1

~~__~ ~~---~--~-------------o-SC--n-im-+'~

DAC1

1-4--------;...,11--1 DAC 2

User Interface

'---........

r------,

Power Control '

Audio Out'

'-r---~-----J~~~~~~_J DAC3
14-1-----------+..--I Transmit

_ _ _ _ _ _ .1I

______ _

SAT

Data

Control

Synthesizer
Programming I/O
I/O
~------''::'':':':'''::':'''':''':'':''''::'::'':':':'-----I

RFEN
TCM8002
Data Processor

I/O

I
IL _ _ _ _ _ _

IMtltij$It.),M
TI's analog cellular solution consists of the
TCM8010 audio processor and the TCM8002
data processor. Together they comprise a highly
integrated baseband system for Advanced
Mobile Phone Service (AMPS) and Total Access
Communication System (TACS) cellular phones.

development is kept to a minimum. The system
operates from either a 5-V supply
(TCM8010-50) or a 3.7-V supply (TCM8010-37)
and needs only one crystal or an external clock
for operation.

TCM8010 audio processor

The optimized architecture reduces the material
cost of the phone and minimizes the power
consumption in standby mode. Digital trimming
significantly reduces the test time and
manufacturing cost of a phone, ensuring a
competitive, low-cost phone design for the
worldwide consumer cellular phone market.
Since the TCM8002 implements the required
data processing, microcontroller software
PRODucnON DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily Include
testing of all parameters.

•

An on-chip compander to
high-quality voice transmission.

provide

•

Two integrated input amplifiers allow handset
or hands free operation.

•

On-chip DTMF generator provides 16 tones,
programmable for level adjustments.

•

Two integrated ADCs are used to monitor the
RSSI level and battery Voltage.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-25

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT001

•

Three DACs are used to control the transmit
output power, to trim the VCTCXO and to
adjust the response of the first IF stage.

A total of 12 events are microcontroller-interrupt
Programmable. The 4-wire serial interface
minimizes the number of microcontroller pins

required. Programmable 20-pin lID expansion
capabilities provide system support to the
keyboard, display, and the RF section.
An on-chip watchdog timer fulfills the
requirement of the AMPSITACS standard for a
microcontroller-independent watchdog.

•
TEXAS
INSTRUMENTS
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WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT005

15-548
Dual-Mode Cellular Solutions Product Brief

TCM4300

TLV320AC361
TCM320AC36

Audio
Interface
Circuit

Interface Circuit

IM!tfflPAU.],W
The 18-548 technology from Texas Instruments
provides a single-D8P baseband solution for the
18-548 standard. With its high level of integration,
the solution reduces device count, saves space,
and simplifies design, allowing users to design a
competitive product with a fast time-to-market. 8y
supporting the 18-548 dual-mode standard, this
solution allows seamless integration into the
emerging digital cellular telephone market.

80me of the key benefits you can expect by using
the Texas Instruments 18-54B solution include

The 18-548 solution from TI consists of the 18-548
D8P, a 16-bit fixed-point product from TI's leading
family of D8Ps; the TCM4300 Advanced RF
Cellular Telephone Interface Circuit (ARCTICTM),
a high-performance mixed-signal device; and the
TLV320AC36 or TCM320AC36 Voice-Band Audio
Processor (VBApTM), an audio CODEC
manufactured using TI's low-power LinCMO8™
technology.

•

Full compliance with the 18-54B dual-mode
standard

•

Optimized software for complete baseband
operations

•

Minimized overall system cost

•

Flexible microcontroller and RF interfaces

Bit-error-rate
performance
18-54/18-55 requirements

•

V8ELP segmented
(8NR)
performance
requirements

•

TOFP and 80FP packaging

exceeding

signal-to-noise-ratio
exceeding
18-85

ARCTIC, VBAP, and LinCMOS are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products In the formative or
design phase of development Characteristic data and other

~ra~~~~~~~:c~~t~~~~~e~~a~~~~~~~: ~I~~~::;~~\~::.serves the right to

•
TEXAS
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1-27

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT005

TI's IS-54B solution simplifies dual-mode cellular
design by providing a flexible interface to the
microcontrollers and RF designs most commonly
used in cellular phones. In addition, our product
contains drivers for both the speaker and
microphone; no additional buffers or drivers are
needed. A 3.3-V power supply and advanced
power management techniques allow your
products to use smaller, lighter batteries and have
longer operating times.

•

In analog mode, provides all base-band
filtering and transmit O/A conversion and
receive AID conversion

•

Integrated
wide-band
data
(WBO)
demodulator provides DSP power saving in
analog mode .

•

Advanced power control minimizes power
consumption of many dual-mode functional
blocks

•

3.3 V or 5 V single supply operation

TCM320AC36rrLV320AC36
Auido Interface Circuit:

TMS3201S54B DSP:
•

FM voice transmission and reception for
analog mode operation

•

Synchronization and timing control of the
chipset in digital mode

•

n/4 OOPSK decoding and demodulation for

digital operation

•

Single chip audio PCM COOEC that provides
all the filtering and frame sync timing
necessary for a standard voice channel

•

Standard serial interface to a TMS320 or any
other standard DSP

•

Transmit and receive directions can be
operated independently

•

Channel coding/decoding and interleaving

•

VSELP voice coding/decoding

•

Simple microphone and speaker interfaces

Robust channel equalization

•

Operates from a single 5 V (TCM320AC36) or
3 V (TLV320AC36) supply

•

TCM4300 Advanced RF Cellular Telephone
Interface Circuit:
•

•

Single-chip interface to DSP, micro-controller
and RF modulator/demodulator in a
dual-mode IS-54B cellular telephone
Performs
n/4
differential
quadrature
phase-shift keying (rtl4-00PSK) symbol
modulation

In addition, Texas Instruments has development
platforms
(which
include
baseband,
microcontroller and RF subsystems for prototype
and system testing) and thorough documentation
to support you with your digital cellular design.

~TEXAS

INSTRUMENTS
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WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT003

15-136
Dual-Mode Cellular I PCS Solutions Product Brief

TCM4301
TLV320AC36

Audio
Interface
Circuit

Interface Circuit.

IM!tttiPAU.hM
The IS-136 technology from Texas Instruments
provides a single-DSP baseband solution for the
IS-136 standard. With its high level of integration,
the solution reduces device count, saves space,
and simplifies design, giving you a competitive
product with a fast time-to-market. By supporting
the IS-136 dual-mode standard, this solution
allows seamless integration into the emerging
digital cellular telephone market.
The IS-136 solution from TI consists of an IS-136
DSP, a 16-bit fixed-point product based on TI's
leading
family
of
DSPs;
TCM4301
(ARCTlcrM-136) RF Interface Circuit, a
high-performance mixed-signal device; and the
TLV320AC36 Voice-Band Audio Processor,
(VBAPTM) an audio codec manufactured using TI's
low-power LinCMOSTM technology.

Some of the benefits you can expect by using TI's
IS-136 solution include:

•

Full compliance with the TIA IS-136
dual-mode cellular standard for North
America

•

Optimized software for complete baseband
operations

•

Minimized overall system cost

•

Flexible microcontroller and RF interfaces

Bit-error-rate
requirements

•

VSELP segmented signal-to-noise ratio
IS-85
(SNR)
performance
exceeding
requirements

•

TQFP and SQFP packaging

exceeding

IS-136/IS-137

TI's IS-136 solution simplifies dual-mode cellular
design by providing a flexible interface to the
microcontrollers and RF designs most commonly
used in cellular phones. In addition, our product
contains drivers for both the speaker and
microphone; no additional buffers or drivers are
needed. A 3.3-V power supply and advanced

VBAP, ARCTIC, LinCMOS are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW Information concerns products In the formative or
design phase of development Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

•
TEXAS
INSTRUMENTS
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1-29

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSTT003

power management techniques allow your
products to use smaller, lighter batteries and have
longer operating times.

TMS320CIS136 DSP:
•

Digital control channel encoding and
decoding for IS-136 operation as well as
search and channel type determination

•

FM voice transmission and reception for
analog mode operation

•

Control and voice channel processing

•

Synchronization and timing control of the
chipset in digital mode

•

n/4 DQPSK decoding and demodulation for
digital operation

•

Channel coding/decoding and interleaving

•

VSELP voice coding/decoding

•

Robust channel equalization

Single-chip interface to DSP, microcontroller
and RF modulator/demodulator in a
dual-mode IS-136 cellular telephone

•

Performs
n/4
differential
quadrature
phase-shift keying (rt/4-DQPSK) symbol
modulation

•

Sleep mode timer allows the phone to utilize
power saving modes of IS-136 paging classes

In analog mode, provides all baseband
filtering and transmit D/A conversion and
receive AID conversion

•

Integrated
wide-band
data
(WBD)
demodulator provides DSP power savings in
analog mode

•

Advanced power control minimizes power
consumption of many dual-mode functional
blocks

•

3.3 V single supply operation

TLV320AC36 Audio Interface Circuit:

TCM4301 (ARCTICTM-136)
RF Interface Circuit:
•

•

Single chip audio PCM CODEC that provides
all the filtering and frame sync timing
necessary for a standard voice channel

•

Standard serial interface to a TMS320 or any
other standard DSP

•

Transmit and receive directions can be
operated independently

•

Simple microphone and speaker interfaces

•

Operates from a single 3 V supply

~TEXAS

1-30

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSn004

TMS320FLEX
Chipset Product Brief
MOSI ~
Microcontroller

MISO
SCK

2.5V

AV00h-i="" "F

TLV5590
AID
DVDD
CONVERTER

L.......-.-

Receiver

J./\

VIN

[

Track Enable ...

VMID

Mode 1 ...

VOFFSET

ModeO ...

r-- Test

BW Select

GND

ClK

I--

TLV5591
FLEX
DECODER

-=
FLEX Pager Block Diagram

1MtlfflPAit,hW
The TMS320FLEX chipset from Texas Instruments
allows OEMs in a variety of diverse industries to
rapidly develop paging devices conforming with the
FLEXTM paging protocol developed by Motorola Inc. In
addition to providing a turnkey solution for FLEX
pagers, the flexible architecture of the chipset lends
itself to integration into equipment as varied as
computers, automobiles, and smart home electronics.
Embedded paging functionality can open a new realm
of applications.

As paging has become more widely accepted,
Motorola developed the FLEX advanced paging
protocol to provide a robust form of text and data
messaging not previously available with other
protocols. Bringing new levels of functionality and
service to pagers, the FLEX protocol delivers several
key benefits to users:

The '320FLEX chipset consists of the TLV5591, a
signal processor that decodes the FLEX paging
protocol transmission, and the TLV5590, which
converts the analog signal from the receiver into a
digital signal for decoding by the TLV5591.

Longer battery life (up to 5x) than existing
paging standards, enabling improvements in
design and miniaturization because of the
smaller batteries

•

Support for
messages

numeric

and

alphanumeric

FLEX is a trademark of Motorola Incorporated.
PRODUCT PREVIEW Information concerns products In the formative or
design phase of development Characteristic data and other
speclflcatlons are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

~TEXAS

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1-31

WIRELESS SELECTION GUIDE
PRODUCT BRIEF LIT. NO. SSn004

•

Increased signal integrity for error protection
and positive message termination

•

Advanced features, such as group pages
between systems

Paging carriers also realize numerous advantages by
converting to the FLEX protocol:
•

Support for
transmission

1600-,

3200-

•

Carriers can minimize their upgrade costs by
migrating gradually from existing standards to
FLEX 1600 to FLEX 3200 to FLEX 6400

•

Significant increase in the number of
subscribers per channel, consequently
lowering infrastructure costs

•

1600, 3200,
decoding

6400

bits-per-second

•

Any-phase decoding

•

Uses standard serial peripheral interface
(SPI) in slave mode

•

Allows low current STOP mode operation of
host processor

•

Highly programmable receiver control

•

Real-time clock time base

•

FLEX fragmentation and group messaging
support

•

Real-time clock over-the-air update support

•

Compatible with synthesized receivers

•

Low battery indication (external detector)

or 6400-bps

With the substantial benefits of the FLEX protocol,
demand for FLEX pagers has been growing steadily.
FLEX has become the de facto high-speed
paging-protocol standard as 70% of paging operators
worldwide have adopted FLEX technology for their
next-generation upgrades.

and

TLV5590 AID converter:

•

Selectable dual-bandwidth audio filter
3-pole Butterworth lowpass
BW 1 = 1 kHz ±5% (-3db)

Tl's '320FLEX chipset simplifies implementation of
the FLEX protocol in a paging application by
interfacing directly with most popular off-the-shelf
paging receivers and microcontrollers. Paging OEMs
can quickly and easily develop a FLEX-compliant
product by interfacing the TMS320FLEX chipset to
their existing receivers and microcontrollers with
virtually no hardware redesign.
To further simplify matters, purchase of the
TMS320FLEX chipset satisfies all licensing
requirements for the FLEX protocol. No separate
license agreement with Motorola is necessary.
TLV5591 FLEX Decoder:

•

16 programmable user-address words

•

16 fixed-temporary addresses

BW 2 = 2 kHz ±5% (-3db)
•

Peak and valley detectors

•

Two-bit analog-to-digital converter

•

Three modes of operation: fast acquisition,
slow acquisition, and hold

•

2.5-V operation with single power supply

FLEX system software to facilitate application
development is included with the TMS320FLEX
chipset. FLEXstack™ software is specifically designed
to support the FLEX decoder. The software runs on a
host processor, handles communications with the AID
converter, and interprets the code words passed to
the host from the TLV5591.

FLEXstack is a trademark of Motorola Incorporated .

1-32

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS

ADC1
American Digital Cellular (same as USDC)

ADC2
Analog-to-digital converter (also AID). A converter that uniquely represents all analog input values within a
specified total input range by a limited number of digital output codes, each of which exclusively represents a
fractional part of the total analog input range.
NOTE: This quantization procedure introduces inherent errors of one-half LSB (least significant bit) in the
representation since, within this fractional range, only one analog value can be represented free of error
by a single digital output code.

Address
The number dialed by a calling party that identifies the party called. Also a location or destination in a computer
program.

Adjacent Channel Interference
Interference caused by the energy from a transmitting channel spilling over into an adjacent channel. This
interference can be minimized by applying filters to the transmitting and receiving ends or by simply using
non-adjacent frequency channels within a cell. Cellular systems typically transmit on nonadjacent frequencies
within a cell in order to prevent adjacent channel interference.

Alert
Constant 10 kHz signaling tone sent on the reverse voice channel (by the mobile), in an analog cellular
conversation, while the mobile phone is ringing.

Aliasing
The occurrence of spurious frequencies in the output of a PCM system that were not present in the input-due,
to foldover of higher frequencies.

AM (Amplitude Modulation)
A technique for sending information as patterns of amplitude variations of a carrier sinusoid.

Amplifier
An electronic device used to increase signal power or amplitude.

AMPS
A Bell acronym for Advanced Mobile Phone Service, an analog FDMA technology where channels of
information are separated by 30 kHz.

Analog
Information represented by continuous and smoothly varying signal amplitude or frequency over a certain
range, such as in human speech or music.

~TEXAS

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1-33

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Asynchronous
Refers to circuitry and operations without common timing (clock) signals.

Attenuation
Weakening of the signal due to it being partially blocked or absorbed - the decrease in power that occurs when
any signal is transmitted. RF signal attenuation is heavily dependent on the frequency of the RF transmission
and on the physical characteristics of the material that the transmission interacts with. For example, high
frequency microwave transmissions are severely attenuated by rain, but lower frequency cellular transmissions
are not.

ASK (Amplitude Shift Key Modulation)
Refers to transmitter on-off data transmission where data is transmitted by turning a radiation source on and
off to transfer data over a wireless link.

Audio Frequency
Frequencies detectable by the human ear, usually between 20 and 15,000 Hz.

Bandwidth 1
The range of signal frequencies that a circuit or network will respond to or pass.

Bandwidth 2
The amount of frequency allocated for an RF transmission. For example, a cellular channel typically has a
bandwidth of 30 kHz, i.e., a cellular system requires 30 kHz of frequency per channel to transmit its signal. One
of the fundamental problems associated with RF transmissions is the limited amount of electromagnetic
spectrum available. The electromagnetic spectrum is finite, and only a limited portion of the spectrum has been
allocated for cellular use by the FCC (Federal Communications Commission). The FCC has allocated only 50
MHz of spectrum for cellular use. Additional capacity can not be achieved by simply taking up more spectrum.
Since there is a limited amount of spectrum available for cellular use, additional capacity must be obtained by
other means.

BPF
Band-pass filter. Typically used in analog and RF circuitry to pass a specific frequency band and attenuate out
of band frequencies.

Baseband
Refers to the data rate or baseband rate of transmitted data.

Base Station
A multichannel transceiver located at the center of a cell and connected via wireline to the mobile telephone
switching office (MTSO). Its primary purpose is to handle all incoming and outgoing cellular telephone traffic
within the cell.

Baud Rate
Baud rate is the number of carrier signal modulation events (signal changes) per second during data
transmission - not necessarily equal to the number of data bits transmitted per second (bps).

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Baud Rate versus Bit Rate (Bits Per Second -

bps)

Baud rate is the number of carrier signal modulation events (signal changes) per second, which must be within
the bandwidth of the transmission medium. For modems using voice-grade telephone lines, the maximum baud
rate is approximately 3300, which is approximately the pass band of the voice circuit (3300 Hz). Modulation
schemes are employed that provide many bits of data for each carrier modulation event (baud) to increase the
number of bits per second that can be transmitted on a pass band-limited voice telephone circuit. A modem
running at 2400 baud and encoding four bits of data on each carrier transition (baud), for example, is actually
transmitting 9600 bits of data per second.

Bell Tapping
The undesired activation of the ringer circuit of a telephone caused by rotary dial pulses from a parallel
telephone. Also known as tinkling.

BER (Bit Error Rate)
Used as a measure to quantify bit error occurrences in a digital communications link.

Bias (Asymmetrical) Distortion
Distortion affecting a binary modulation scheme whereby the actual mark or space has a longer or shorter
duration than the corresponding theoretical duration.

Bit Rate
Bit rate is the actual number of bits of data that is transmitted or received per second.

BORSCHT
An acronym for the function that must be performed in the central office (on a line card) when digital voice
transmission occurs; Battery, Overvoltage, Ringing, Coding, Hybrid, and Test.

Byte
A group of bits (usually 8) treated as a unit or word. Often equivalent to one alphabetic or numeric character.

Call Forwarding
A feature allowing the subscriber to forward a call to another telephone number.

Call Processing
The complete process of routing, originating, terminating cellular telephone calls, along with the necessary
billing and statistical collection processes.

Call Record
A record stored on tape containing mobile number, dialed digits, time stamp information, and other data needed
to bill or 'ticket' a cellular telephone call.

Call Setup
The call processing events that occur during the time a call is being established, but not yet connected.

~TEXAS

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1-35

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Call Waiting
A feature allowing the subscriber to be alerted to the arrival of another call during the current conversation. The
user can answer the call waiting and then switch between the two calls, but cannot connect all parties together.

CCIT
International Telegraph and Telephone Consultative Committee. An international forum for establishing
communication system standards.

COMA (Code Division Multiple Access)
In a COMA system, each voice circuit is labeled with a unique code and transmitted on a single channel
simultaneously with many other coded voice circuits. The only distinctions between the multiple voice circuits
are the assigned codes. The channel is typically very wide with each voice circuit occupying the entire channel
bandwidth. For example, 64 different voice circuits can be simultaneously transmitted on the same channel, with
each voice circuit identified by its assigned code.

Cell
The RF coverage area in the cellular system resulting from operation of a single multiple-channel set of base
station frequencies. Cell can also refer to the base site equipment servicing this area.

Channel 1
An electronic communication path. In telecommunications, it is usually a voice bandwidth of 4000 Hz.

Channel 2
A unique RF frequency that is used for communication between a subscriber unit and a cell site base station.
Channels must be assigned by the FCC.

Circuit
An interconnected group of electronic devices or, in telecommunications, the path connecting two or more
communications terminals.

Click Tone
A particular progress tone injected onto the forward voice channel (base station transmit, mobile unit receive)
to indicate to the subscriber that the call has not been abandoned by the system.

C-Message Weighting
A noise weighting used to measure noise on a line that would be terminated by a 500-type telephone set or
similar instrument. The resulting noise reading is in dBrnC.

Class 5 Office
See central office

CO (Central Office)1
The switching equipment that provides local-exchange telephone service for a given geographical area and is
designated by the first three digits of the telephone number. This is also known as a Class-5 office.

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS

co (Central Office)2
The switching office that connects the MTSO (mobile telephone switching office) to the PSTN (public-switched
telephone network). The CO is also known as a Class 5 or 'end' office.

Co-channel Interference
Co-channel interference is the interference caused between two cells transmitting on the same frequency within
a network. Since co-channel interference is caused by another cell transmitting the same frequency, the
interference cannot simply be filtered out. The co-channel interference can only be minimized through proper
cellular network design. A cellular network must be designed to maximize the CII ratio, which is the
carrier-to-co-channel interference ratio. One of the ways to maximize the CII ratio is to increase the frequency
re-use distance, i.e., increase the distance between cells using the same set of transmission frequencies. The
CII ratio, in part, determines the frequency re-use distance of a cellular network.

Codec
An assembly comprising an encoder and a decoder in the same unit. A device that produces a digital coded
output from an analog input, and vice versa.

Combo
A single-chip pulse-code-modulated (PCM) encoder and decoder (codec), and PCM line filter.

Common Battery
A system supplying direct current for the telephone set from the central office.

Compander
A combination of a compressor and an expander. The audio signal is compressed at the transmitter, reducing
its dynamic range and thereby reducing the dynamic range of the transmitted signal. An expander at the receiver
restores the recovered signal to its original dynamic range. Companding is used in communications systems
to improve signal-to-noise ratio as a result of the reduced dynamic range that is transmitted. In analog cellular,
2:1 syllabic compression is used to limit the maximum peak voice deviation to ±2.9 kHz.

Constructive Interference
Interference that occurs when waves occupying the same space combine to form a single stronger wave. The
strength of the composite wave depends on the how close in phase the two component waves are. For example,
if two waves of the same phase, each with an amplitude of 10 are transmitted, they would combine into a
composite wave of amplitude 20. Two waves slightly out of phase, however, would combine into a composite
wave with an amplitude less than 20.

Control Channel
A unique RF channel used by each cell base station that is dedicated to the transmission of digital control
information from the base station to the cellular mobile unit. It is used to assign voice channels, control mobile
power, authorize handoffs, etc.

Crossbar Switch
An electromechanical switching machine using a relay mechanism with horizontal and vertical input lines
(usually 10 to 20). Uses a contact matrix to connect any vertical to any horizontal.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-37

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Crosspoint
The element that actually performs the switching function in a telephone system. It may be mechanical using
metal contacts or solid state using integrated circuits.

CT2
Cordless telephone, type 2, or 2 nd generation

CTIA
Cellular Telecommunication Industry Association

Cutoff Frequency
The frequency above or below which signals are attenuated below a specified value by a circuit or network.

DAC
Digital-to-analog converter (also D/A). A converter that represents a limited number of different digital input
codes by a corresponding number of discrete analog output values.

NOTE: Examples of input code formats are straight binary, two's complement, and binary-coded decimal
(BCD).

Data
In telephone systems, any information other than human speech.

Data Set
Telecommunications term for a modem.

dB (Decibel)
A unit of measure of relative power - the logarithmic ratio between two amounts of power, 10 log (P1/P2), or
voltage, 20 log (V1N2), in terms of the ratio of two values. It is typically used in receiver and transmitter
± measurements.

dBm
Decibels referenced to one milliwatt; used in communication work as a measure of absolute power values. Zero
dBm equals one milliwatt. (0 dBm = log 1 mW)

dBmO
Noise power referenced to or measured at a zero transmission level point (OTLP).

dBmOp
Noise power in dBmO, measured by a psophometer or noise measuring set having psophometric weighting.

dBrn
Decibels above reference noise. Rated noise power dB referenced to one picowatt. Zero dBrn equals -90 dBm.

~TEXAS

1-38

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
dBrnC
Noise power in dBrn, measured by a noise measuring set with C-message weighting.

dBrnCO
Noise power in dBrnC referenced to or measured at a zero transmission level point (OTLP).

dBW
Decibels referenced to one Watt.

Decoder
Any device that modifies transmitted information to a form that can be understood by the receiver.

DECT
Digital European Cordless Telephone

Demultiplexer
A circuit that distributes an input signal to a selected output line (with more than one output line available one-to-many).

Destructive Interference
Interference that occurs when waves occupying the same space combine to form a single wave with an
amplitude that is less that any of the component waves. Destructive interference occurs when the waves that
are summed into a single, composite wave are out of phase such that at any given instance, the negative
amplitudes summed with the positive amplitudes result in an amplitude of the composite wave that is less than
of any of the component waves. Destructive interference can result in attenuations ranging up to 100%, which
is the case when two signals of equal amplitude but 180 degrees out of phase are summed together. They
completely cancel each other.

Diversity Receive
A method commonly employed by cellular equipment manufacturers to improve the signal strength of received
signals. The scheme uses two independent antennas that receive signals that differ in phase and amplitude
resulting from the slight difference in antenna positions. These two signals are either summed or the strongest
one is accepted by voting.

DTMF
Dual-tone multifrequency, commonly known as touchtones. This in-band signaling system consists of 12 audio
tones, each created from two different frequencies (out of a group of 8), that correspond to the digits 0 through
9, and * and # on a subscriber telephone key pad.

Dual-Mode Cellular
Dual-mode cellular telephones operate in either digital or analog cellular systems.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-39

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
DTX (Discontinuous Transmission)
A cellular telephone subscriber unit feature that allows the mobile unit to disable its RF power amplifier (PA)
during conversation when the subscriber is not talking. This reduces the power drawn from the battery and thus
increases talk time. The cellular system must support this feature if the subscriber is to be able to use it.

EAMPS
Extended Advanced Mobile Phone Service (AMPS with extended frequency allocation)

EIA
Electronic Industries Association. (2001 Pennsylvania Avenue, N.W., Washington, D.C. 20006)

Electromagnetic Spectrum
The total range of wavelengths or frequencies or electromagnetic radiation, extending from the longest radio
waves to the shortest known cosmic rays.

EMI
Electromagnetic interference.

Encoder
Any device that modifies information into the desired pattern or form for a specific method of transmission.

End Office
See central office

Erlang
A dimensionless quantity used in the statistical measurements of the traffic in a cellular system. One Erlang is
equivalent to the average number of simultaneous calls, and is equal to 3600 call-seconds per hour or 36 CCS
(call century seconds) per hour.

ESN (Electronic Serial Number)
A 32-bit code that is unique to each cellular telephone mobile unit. It is used by the base station to validate the
mobile unit. The ESN is not alterable by either the cellular service provider or the end user.

ESS
Electronic Switching System. A telephone switching machine using electronics, often combined with
electromechanical crosspoints, and usually with a stored-program computer as the control element.

Equalization
The reduction of frequency distortion and/or phase distortion of a circuit by the introduction of networks to
compensate for the difference in attenuation, time delay, or both, at the various frequencies in the transmission
band.

Exchange Area
The territory within which telephone service is provided for a basic charge. Also called the local calling area.

~TEXAS

INSTRUMENTS
1-40

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Fade
A drop in the received signal strength of a cellular RF transmission signal that results from the RF Signal
interactions with the transmission environment.

FCC
Federal Communications Commission. A government agency that regulates and monitors the domestic use of
the electromagnetic spectrum for communications.

FCC Part 68
A government document describing the types of equipment that must be registered and the electrical and
mechanical standards to be met when connecting equipment to the public telephone network.

FDMA (Frequency Division Multiple Access)
A communications scheme where channels of information are separated by frequency and systems transmit
one voice circuit per channel. The channels are relatively narrow, usually 30 KHz or less and are defined as
either transmit or receive channels. A full-duplex conversation requires a transmit and receive channel pair. For
example, if a FDMA system had 200 channels, the system could handle 100 simultaneous full-duplex
conversations (100 channels for transmitting and 100 channels for receiving).

Flash Hook
400 ms of signaling tone sent on the reverse voice channel by the cellular mobile unit to request a hook flash.

FOCC (Forward Control Channel)
A control channel from the cellular base station to the mobile unit; also known as the control channel downlink.

Forced Disconnect
A call processing function that forces termination of a cellular call, usually not at the request of the mobile
subscriber.

Four-Wire Line
A two-way transmission circuit using two pairs of conductors. This allows full-duplex (simultaneous in both
directions) conversation without multiplexing.

Free Space Loss
The power loss of the RF transmission Signal as a result of the signal spreading out as it travels through space.
As a radio wavefront travels through space, its power diminishes according to the inverse-square law - at twice
the distance, there is only one-fourth the power.

FSK (Frequency Shift Keying)
The form of frequency modulation that uses two different audio frequencies to transmit binary ones and zeros
by shifting back and forth between the two frequencies.

Full-Duplex
Simultaneous communication in both directions between two points. It uses two communications paths with
both points being able to transmit and receive simultaneously.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-41

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
FVC (Forward Voice Channel)
A voice channel from the cellular base station to the mobile unit; also known as the voice channel downlink.

Glare Hold and Glare Release
A method of glare resolution. Glare occurs when both the local and distant end of a trunk are seized at the same
instant, usually resulting in deadlock of the trunk. To prevent this, one end of the trunk is assigned a glare hold
status and the other a glare release status. In the event of glare, the glare-hold end holds the trunk and the glare
release-end releases the trunk and attempts to seize another. This scheme is used on the wirelines between
the MTSO and connecting cellular sites.

Grade of Service
A measure of what percentage of calls placed through an exchange fail to be completed due to congestion of
that exchange. In cellular communications, a 2% GOS is usually considered acceptable.

GSM
Groupe Special Mobile (a European format for cellular communications).

Half-Duplex
A circuit that can carry information in both directions but not simultaneously - uses two communicdtions paths
with only one point being able to transmit and receive simultaneously.

Handoff (Intercell)
The process by which cellular mobile units traveling through the system coverage area are switched from one
cell (and its base station) to the next cell (and to a different channel) that has better coverage for that particular
area. The handoff is often triggered by the degradation of the transmission quality due to the mobile unit reaching
the edge of the cell's service area or by adverse RF propagation characteristics in the area through which the
mobile unit is traveling.

Handoff (Intracell)
The process by which cellular mobile units traveling through a cell's coverage area are switched from one sector
in the cell to the next sector in the cell (and to a different channel) that has better coverage for that particular
area. The handoff is often triggered by the degradation of the transmission quality due to the mobile unit reaching
the edge of the sector's service area or by adverse RF propagation characteristics in the area through which
the mobile unit is traveling.

Harmonic Filter
A filter used in the base station and cellular mobile unit transmitter circuits to remove unwanted harmonics
(spurious frequencies) from the transmitted signal.

HPF
High-pass filter. Typically used in analog and RF circuitry to pass high frequencies and attenuate lower
frequencies.

~TEXAS

INSTRUMENTS
1-42

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Hybrid
In telecommunications, a circuit that divides a signal transmission channel into two channels (i.e., one for each
direction) or, conversely, combines two channels into one. Typically telecommunications applications are 2-to-4
or 4-to-2 wire hybrids, with two wires being one communication path. Every telephone contains a hybrid circuit
to separate ear piece and mouthpiece audio and couple both into a 2-wire circuit that connects to the Central
Office. If the hybrid is not balanced properly, echo or 'loop-back' can result in the circuit when the transmitted
signal is reflected back into the receive path.

Idle Channel
A channel that is assigned to a cell base station for use but is not currently in service (being used). All idle
channels for each cell base station are kept in an 'idle-link-list,' which is constantly updated at the MTSO (Mobile
Telephone Switching Office).

Infrastructure
All parts of the cellular system, excluding the subscriber. It includes the MTSO, base stations, cell sites, and
all links between them.

In-Band Signaling
A process in which audio tones between 300 and 3400 Hz provide supervisory and/or address signaling
between the cell base station and the cellular mobile unit.

IS-54/IS-136
TIA standard for dual-mode cellular telephones. IS-136 is the most recent revision of the standard.

JOC
Japanese Digital Cellular

Lineside
Refers to the portion of the central office that connects to the local loop.

Local Loop
The voice-band channel connecting the subscriber to the central office.

Longitudinal Balance
A measure of symmetry impedance of a balanced network. Improper longitudinal balance results in poor
common-mode rejection.

LNA
Low noise amplifier used in data transmission circuits (analog and RF) to set the noise floor of gain stages as
low as possible.

Loop Current
Direct current in the local loop. This indicates that a telephone is off-hook (in use).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-43

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Loss
Attenuation of a signal due to any cause.

LPF
Low-pass filter. Typically used in analog and RF circuitry to pass low frequencies and attenuate higher
frequencies.

Manchester-Encoded Data
Digital data format that reduces noise in RF links.

MARCSTAR
Multichannel Advanced Remote Control Signaling Transmitter and Receiver is a registered trademark of Texas
Instruments, Incorporated. Generally refers to a family of remote control devices produced at TI.

Mark
One of the two possible states of a binary information element. The closed circuit and idle stage in a teleprinter
circuit. See Space.

Microwave Hop
A microwave RF connection between the MTSO and cell sites in remote locations.

MIN1
The 24-bit number that corresponds to the 7 -digit subscriber telephone number.

MIN2
The 10-bit number that corresponds to the 3-digit subscriber area code.

Mobile Attenuation
The power of the cellular mobile unit can be adjusted (or attenuated) dynamically to one of seven discrete power
levels (analog cellular). This is done so that when a mobile unit comes closer to a base receiver, its power is
reduced to prevent the chance of interfering with other mobile units operating on the same voice channel in
another cell (co-channel interference). In addition, this increases the talk usage time of the mobile unit by
reducing the amount of power drawn from its battery.

Mobile Coverage Area
Geographical area in which two-way cellular telephone service can be expected (between the cell base station
and the cellular mobile unit).

Mobile-ID
The 7-digit cellular mobile unit telephone number. It does not include the area code.

Mobile Origination
The initiation of a telephone call by a cellular mobile unit.

~TEXAS

INSTRUMENTS
1-44

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Mobile Unit
The cellular mobile unit is either a handheld or car-mounted transceiver. The mobile unit connects the user to
the base station using RF transmission and reception. The mobile unit is also known as the subscriber.

Modem
A contraction of modulator/demodulator. It is a device to convert digital data into an analog signal and vice versa
so that two electronic devices (e.g., a computer and a data terminal) may communicate over the telephone
system.

MSA (Metropolitan Service Area)
A cellular coverage, defined by the FCC, that resides in a densely populated area.

MTS (Message Telephone Service)
The official name for long distance or toll service.

MTSO (Mobile Telephone Switching Office)
This is the switching office to which all cellular base station sites connect. The MTSO, in turn, interfaces to the
PSTN by connection to a CO. Control of all cell sites, all subscriber records, statistics, and billing is maintained
at the MTSO.

Mu-Law (Il-Law)
An encoding format for the quantization and digitization of analog signals into Pulse Code Modulation (PCM)
signals (AID) and recovery of analog signals from PCM (D/A). Jl-Iaw specifies the parameters for compression
and re-expansion of the Signals during signal transmission and processing. Jl-Iaw PCM encoding is used in
North America. A-law is the European format.

Multipath Fading
Multipath fading, also called Rayleigh fading, occurs when the direct-path transmitted wave destructively
interferes with its reflections at the receiving end. The destructive interference is a result of the reflected waves
arriving at the receiving end later and out of phase with the direct-path transmitted wave. Multipath interference
can vary in intenSity depending on the amount of destructive interference that takes place.

Multiplexer
A device for accomplishing simultaneous transmission of two or more signals over a common transmission
medium (many-to-one).

NADC
North American Digital Cellular

NAMPS
Narrow-band Advanced Mobile Phone Service. An analog FDMA technology in which channels of information
are separated by 10 kHz, and provides three times capacity over AMPS, which has 30 Khz cannel spacing.

NMT
Nordic Mobile Telephone

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-45

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
No-Answer Transfer
A feature that allows calls to a cellular mobile unit to be transferred to a predetermined number if the mobile unit
does not acknowledge an incoming call or is not answered.

NPA (Numbering Plan Area)
The area code

Off-Hook
The circuit condition caused when the handset is lifted from the switch hook of the telephone set. This condition
exists during call setup or conversation.

On-Hook
The normal circuit condition when the handset is on the switch hook of the telephone set.

Operator
In cellular telephony, this is the local service provider that owns the cellular system in that particular area.

Origination
A call that is placed by the cellular mobile subscriber, calling either a land-line circuit or another cellular mobile
subscriber.

PABX
Private Automated Branch Exchange. Small local automatic telephone office serving extensions in a business
complex providing access to the public network.

Page
A message that is broadcast from a group of cell sites that carries a mobile ID for the purpose of alerting the
mobile that a call is waiting.

Parallel Data
The transfer of all bits of a data word simultaneously over two or more wires or transmission links (one for each
bit in the word).

Parity
An error-detection scheme in which an extra bit (the parity bit) is added to each data word to make the total of
all the bits in the word either even or odd according to whether even or odd parity is called-for. Correct parity
(even or odd) of each data word is checked at the receiving end to determine if there were any transmission
errors.

PBX
Private Branch Exchange. A telephone exchange serving an individual organization and having connection to
a public telephone exchange.

•
TEXAS
INSTRUMENTS
1-46

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
PCM (Pulse Code Modulation)
Process in which the modulating signal is sampled, and the magnitude of each sample (with respect to a fixed
reference) is quantized and converted by coding to a digital signal. PCM provides undistorted transmission,
even in the presence of noise. The sample frequency must be at least twice the highest modulating frequency
for full recovery of the original modulating information (Nyquist).

PCN
Personal Communications Network, also known as PCS (Personal Communications System)

Period
The time or angle that a signal is delayed with respect to some reference position.

Phase
The time or angle that a signal is delayed with respect to some reference position.

PL
The transmitting power level of the cellular mobile unit.

Port Change
A channel change from one sector to another, while staying within the same cell, as a mobile unit moves from
one area in a cell to another area in the same cell.

POTS
Plain Old Telephone Service. An acronym used by the telephone industry for conventional telephone service.

PSK (Phase-Shift Keyed Modulation)
A method of placing data on a carrier signal by modifying the phase of the carrier wave.

Psophometric Weighting
A noise-weighting method recommended by the CCITT for use in a noise measuring set or psophometer.

PTP
Point-to-point or line of sight communications link.

Quantization
A process in which the continuous range of values of an analog input signal is divided into nonoverlapping
sub ranges (chords) and to each subrange a discrete value of the output is uniquely assigned a binary number.

Quantizing Distortion
The inherent distortion introduced in the process of quantization.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-47

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
Quantizing Noise
An undesirable random signal caused by the error of approximation in a quantizing process. It may be regarded
as noise arising in the pulse-code modulation process due to the code-derived facsimile not exactly matching
the waveform of the original message.

RECC (Reverse Control Channel)
The control channel that is used from the cellular mobile station to the base station direction, also known as the
control channel uplink.

Reflections
RF waves can reflect off of hills, buildings, moving cars, the atmosphere, and basically almost anything in the
RF transmission environment. The reflections may vary in phase and strength from the original wave.
Reflections allow radio waves to reach their targets around corners, behind buildings, under bridges, in parking
garages, etc. RF transmissions 'bend' around objects as a result of reflections.

Remote Control
A term used to describe wireless control of electronics and the systems controlled by these circuits.

RF
Radio frequency. Used to describe frequencies between audio and infrared that are used in communications
applications.

Ring
The alerting signal to the subscriber or terminal equipment. Also, the name for one conductor of the wire pair
comprising the local loop, deSignated by R.

Ring Trip
During ring signaling, the detection of the off-hook condition and removal of the ring signal from the line by the
switch.

RKE
Remote keyless entry. Primarily used in automobile entry systems, home security systems, and garage door
openers.

Roamer
A cellular mobile station that operates in a cellular system other than the one from which the service is
subscribed (the home system).

Rolling-code
In many communications links, a code is used to identify a user. Rolling-code means this code changes every
time the code is transmitted to improve security of the system or link.

~TEXAS

INSTRUMENTS
1-48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
RSA (Rural Service Area)
A cellular coverage, defined by the FCC, that resides in a less populated area.

RSSI (Relative Signal Strength Indication)
Received signal strength indicator - used in RF circuitry to detect the strength of a received signal. In cellular
telephony, it is a value representing the received signal strength of both the cellular mobile unit and the base
station. This value is used to initiate a power change or handoff.

RVC (Reverse Voice Channel)
The voice channel that is used in the cellular mobile station to base station direction, also known as the voice
channel uplink.

SAT (Supervisory Audio Tone)
One of three tones (5970, 6000, and 6030 Hz) that are transmitted by the cell base station and transponded
by the cellular mobile station. It is used to evaluate the complete radio path, both forward and reverse voice
channels. The SAT received by the mobile unit is actually regenerated by the mobile unit with the same
amplitude and noise associated with the actual received SAT.

SAW (Surface Acoustic Wave)
Resonant devices that are used in many communication applications and are well suited for low power RF.

Scan Receiver
A receiver that resides in the cell base station that is dedicated to measuring the signal strength of the cellular
mobile units that are communicating via the cell. These measurements are used in the handoff process (but
not in the power-up/power-down process, which is handled by each voice transceiver).

SCM (Station Class Mark)
This indicates the cellular mobile station type (mobile/trans/port), and if the station has DTX.

Sector-Receive Cell Site
Six or three directional antennas that are used at a cell site to get the additional gain required to serve cellular
mobile units. A mobile unit could move completely around a sector-receive cell site and never change channels;
but it would change antennas.

Sector-Sector Cell Site
The cell is broken up into two or more independent sectors that each have their own transmit and receive
antennas. A cellular mobile unit moving around a sector-sector cell would change channels (intra-cell handoff).

Sensitivity
A term used to describe the minimum discernible signal a receiver can detect.

Serial Data
The transfer of data over a single wire in a sequential pattern of bits that make up a data word.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-49

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
SID (System Identification)
A unique digital code assigned to each cellular system. The home system of each mobile is stored in its internal
memory so that the mobile unit knows when it is a roamer (outside its normal service area).

Sidetone
An attenuated portion of the transmit audio returned to the originator and subsequently heard in the earpiece
of the sender. Sidetone is common, as all telephones produce some sidetone and is caused by unbalanced
2-to-4 wire hybrids. And, sidetone is often intentional to meet the expectations of the user, who is accustomed
to hearing it on a 'live' telephone set as an indication that it is 'connected.'

Signal-to-Noise
The ratio of the magnitude of the signal to that of the noise with no signal present, usually expressed in dB.

Simplex
A circuit that can carry information in only one direction (e.g., broadcasting, public address, etc.). Uses one
communication path with one only able to transmit and the other end only able to receive.

SLiC
Subscriber line interface circuit. In digital transmission of voice, this circuit that performs some or all of the
interface functions at the central office. See BORSCHT.

Source Cell .
The cell that a cellular mobile unit is leaving during the handoff process.

Source Channel Falsing
A condition that exists when co-channel SAT (supervisory audio tone) exists on the source channel during
handoff, so that the source channel does not squelch during the handoff process. This results in noise during
the handoff process (after the hand-off order) that can be heard by both the landline and cellular mobile unit
parties.

Space
One of the two possible states of a binary information element: the open-circuit or no-current state of a
teleprinter. See Mark.

Spectrum
The electromagnetic spectrum, which is the continuous range of electromagnetic frequencies.

Squelch Circuit
A radio receiver circuit that disables the audio path when the incoming signal strength is below a predetermined
threshold.

1-50

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
ST (Signaling Tone)
A 10kHz tone transmitted by the cellular mobile unit on a voice channel to (1) confirm channel change orders
(HO tone, 50 ms ST), (2) request a flash-hook by the mobile (400 ms ST), (3) mobile alert (continuous ST), and
(4) mobile ending call (1.8 sec ST).

State
A condition of an electronic device, especially a computer, that is maintained until an internal or external
occurrence causes change.

Subscriber
The mobile user of the cellular system.

Subscriber Files
User records stored at the MTSO containing all information pertaining to each subscriber. This includes cellular
mobile unit number, home service location, last known location, type of mobile unit, service denial flags, and
special feature options available to that subscriber.

Subscriber Loop
See local loop.

TACS
Total Area Coverage Systems

Target Cell
The cell that a mobile unit is going to during the hand off process.

Target Channel Falsing
A condition that exists when a co-channel SAT exists on the target channel during handoff, so that the target
channel does not squelch before arrival of the cellular mobile unit during the handoff process. This results in
noise during the handoff process (before the handoff order) that can be heard by both the land line and mobile
unit parties.

TDM (Time Division Multiplexing)
A communication system technique in which each of multiple channels is sequentially connected to a
single-channel transmission link. At the other end, the single-channel transmission link is sequentially
connected to each of connected separates information from multiple channel inputs and places them on a
carrier in specific positions of time to send.

TDMA (Time Division Multiple Access)
TDMA systems are able to transmit multiple voice circuits on each channel. A TDMA channel is a single FDMA
channel divided up into multiple time slots. The channels can vary in bandwidth and, depending on the type of
system and the time slots, can transmit all or part of a voice circuit.

TIA
Telecommunications Industry Association

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1-51

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
TIP
One conductor of the wi re pair composing the local loop and designated by the letter T. Usually, the more positive
of the two conductors.
.

Toll Center
A major telephone distribution center that distributes calls from one major metropolitan area to another. Also
known as a class 4 office.

Toll Ticketing
Subscriber records that are kept at the MTSO for billing purposes. They contain subscriber number, time of call,
called number, location of call origination, location of call termination, and other important statistics for the
proper billing of the subscriber.

Toll Ticketing House
A third-party company that takes the toll ticketing records and actually bills the subscribers. Nonpayment by
subscribers is reported to the operating company so denial of service can be performed.

TPC - (Three-Party Conference Circuit)
A TPC is used in a 3-party conference, but more important, it is used during every handoff so that the
channel-change transition can be made with less noise by connecting the audio of the source and target cells
together before the handoff order is sent. When a handoff is made during a 3-party conference call and the TPC
is being used, 'hard handoffs' occur and the potential for noise during channel changes increases Significantly.

Transmission Link
The path over which information flows from sender to receiver.

Transhybrid Loss
In a telephone hybrid, the measure of the isolation between the receive and transmit ports. It is also a measure
of the balance between the two matched windings of a hybrid transformer.

Transmission Link
The path over which information flows from sender to receiver.

Trunk
A transmission channel connecting two switching machines. In cellular systems, this is the connection between
the MTSO and CO and the connections between the MTSO and cell sites.

Trunkside
That portion of the central office that connects to trunks going to other switching offices.

Tumbling ESN (Electronic Serial Number)
Fraudulent hardware that changes the cellular mobile unit ESN every time a call is originated. Since often only
the FI RST call of a roamer is screened for a bad ESN, an infinite number of fraudulent calls can be placed using
a tumbling ESN.

~TEXAS

INSTRUMENTS
1-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

WIRELESS and TELECOM GLOSSARY
TERMS AND DEFINITIONS
UHF
Ultra high frequency range from 300 to 1000 MHz.

USDC
U.S. Digital Cellular

Validation
The method of determining if a cellular mobile unit should be given service by the cellular system. Validation
often requires matching the ESN (electronic serial number) of the mobile with its mobile 10, and then checking
the mobile unit against files that contain subscribers who should be denied service.

VBAP (Voice-Band Audio Processor)
TI trademark for device that provides AID and OJA conversion, along with the filtering necessary for voice-band
communications.

VHF
Very high frequency range from 100 to 300 MHz.

VMAC (Voice Mobile Attenuation Code)
One of eight discrete cellular mobile unit transmit power levels that are dynamically selected during a cellular
telephone conversation. These power steps are in 4 dB increments.

Voice Circuit
Half of a full-duplex conversation, i.e., one-half of a two-way conversation. For example, if two people are talking
by phone, each of their voices is considered a separate voice circuit.

Voice-Grade Line
A local loop or trunk having a band pass of approximately 300 Hz to 3000 Hz.

Wide-Band Circuit
A transmission facility having a bandwidth greater than that of a voice-grade line.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1-53

1-54

1IDI

~G_e_n_e_ra_I_I_n_fo_r_m_a_t_io_n_______________
Telecommunications Circuits
Central Office Codecs

Transient Voltage Suppressors

III

RF for Telemetry and RKE

•

Wireless Communications Circuits

~P_ro_c_e_s_s_o_rs_·._fo_r_A_n_a_l_o_g_C_e_lI_u_la_r_ _ _

-----'1II
,,"----OR_F_f_o_r_P_e_r_s_o_n_a_1_C_o_m_m_u_n_ic_a_t_io_n_s_ _.-B
~B_a_s_e_b_a_n_d_ln_t_e_rf_a_c_e_C_i_rc_u_i_tS________----JIII
L..--D_iQ_i_ta_I_S_iQ_n_·a_l_p_r_o_c-..;.es_s_o_r_s_ _ _ _----..B
'---V_o_ic_e_-_B_a_n_d_A_u_d_i_o_p_r_o_c_e_s_s_o_rs_ _ _

Mechanical Data

2-1

---It
---It

-n
CD

o
c.

2-2

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

•
•

Reliable Silicon-Gate CMOS Technology

•

Low Power Consumption:
Operating Mode ... 80 mW Typical
Power-Down Mode .•• 5 mW Typical

•

FEATURES TABLE

Replaces Use of TCM2910A In Tandem With
TCM2912C

29C13 29C14 29C16 29C17
129C13 129C14 129C16 129C17

FEATURE
Number of Pins:
24
20
16
~-Law/A-Law
~-Law

Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz

X
X
X

Coding:
X
X

X
X

Gain Timing Rates:
Variable Mode
64 kHz to 2.048 MHz

X
X
X

A-Law

•

No External Components Needed for
Sample, Hold, and Autozero Functions

•

Precision Internal Voltage References

•

Direct Replacement for Intel 2913, 2914,
2916, and 2917

Fixed Mode
1.536 MHz
1.544 MHz
2.048 MHz

•

Recommended for Direct Voice
Applications

Loopback Test Capability

8th-Bit Signaling

description
The TCM29C13, TCM29C14, TCM29C16,
TCM29C17, TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are single-chip PCM codecs
(pulse-code-modulated encoders and decoders) and PCM line filters. They provide all the functions required
to interface a full-duplex (4-wire) voice telephone circuit with a TDM (time-division-multiplexed) system, and are
intended to replace the TCM291 OA in tandem with the TCM2912C. Primary applications include:
•

Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone
systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital voice-band data-storage systems

•

Digital signal processing

TCM29C13, TCM129C13
ow OR N PACKAGE
(TOP VIEW)
VBB
PWRO+
PWROGSR
PDN
CLKSEL
DCLKR
PCMIN
FSR/TSRE
DGTLGND

1 U 20
2
19
3
18
4
17
5
16
15
6
14
7
13
8
12
9
10
11

VCC
GSX
ANLGINANLG IN+
ANLG GND
SIGXlASEL
TSXlDCLKX
PCMOUT
FSXlTSXE
CLKRlCLKX

TCM29C14, TCM129C14
OW PACKAGE
(TOP VIEW)
VBB
PWRO+
PWROGSR
PDN
CLKSEL
ANLG LOOP
SIGR
DCLKR
PCMIN
FSR/TSRE
DGTLGND

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

TCM29C16, TCM29C17,
TCM129C16, TLC129C17
OW OR N PACKAGE
(TOP VIEW)

VCC
GSX
ANLG INANLG IN+
ANLGGND
NC
SIGXlASEL
TSXlDCLKX
PCMOUT
FSXlTSXE
CLKX
CLKR

VBB~

1 U 16
15
PWRO+ [2
PWRO- 3
14
PDN 4
13
DCLKR 5
12
PCM IN 6
11
FSRITSRE 7
10 ~
DGTLGND 8
9]
'"-----'

VCC
GSX
ANLG INANLG GND
TSXlDCLKX
PCM OUT
FSXlTSXE
CLKR/CLKX

NC - No internal connection
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

~~~:~~~o~l: 8~~=~:.1~~U;~!'::: le~::~~~:':n~

standard warranty. Production processing does not necessarily Includa
testing of all parameters.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-3

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

description (continued)
These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are
intended to be used at the analog termination of a PCM line or trunk.
The TCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 provide the band-pass filtering of the analog'signals prior to encoding and after decoding. These
combination devices perform' the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information.
The TCM29C13, TCM29C14, TCM29C16, and TCM29C17 are characterized for operation from O°C to 70°C.
The TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are characterized for operation from -40°C
to 85°C.

functional block diagram

------------------------------------,I
Transmit Section

Sample
and Hold
and DAC

ANLGIN+
ANLGINGSX

I
I
I
I

Successive
ApprOXimation

Comparator

Output
Register

PCM OUT
TSXlDCLKX
SIGXlASEL

-r-~----'

Analogto-Digital
Control
Logic

J - - - - - - - - - " " * - - - . - t - FSXlTSXE

....- - - - - - - - - . . . - 1 I

CLKX

r----------------------- -r----------j---I

GSR

I
I
I

Control

Receive Section

Digitalto-Analog
Control
Logic

PWRO---i--"..----,

PWRO+

CLKSEL
PDN
ANLG
LOOpt

PCMIN
DCLKR

I.----.-t- SIGRt

--+4f-*-----'

tTCM29C14 andTCM129C14 oniy
lTCM29C13, TCM29C16, TCM29C17, TCM129C13, TCM129C16, and TCM129C17 only

~TEXAS

2-4

I Section
Control
I
Logic
IL ________ -,I

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

Terminal Functions
TERMINAL NO.

NAME

TCM29C13
TCM129C13

TCM29C14
TCM129C14

TCM29C16
TCM29C17
TCM129C16
TCM129C17

ANLG GND

ANlG IN+

ANlG IN-

ANlG lOOP

Analog ground return for all internal voice circuits. Not internally
connected to DGTL GND.
I

DESCRIPTION

Noninverting analog input to uncommitted transmit operational amplifier.
Internally connected to ANlG GND on TCM129C16, TCM29C16,
TCM129C17, and TCM29C17.

Inverting analog input to uncommitted transmit operational amplifier.

Provides loopback test capability. When this input is high, PWRO+ is
internally connected to ANlG IN.

Receive master clock and data clock for the fixed-data-rate mode.
Receive master clock only for variable-data-rate mode. ClKR and ClKX
are internally connected together for TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.

Clock-frequency selection. Input must be connected to VBB, VCC, or
ground to reflect the master-clock frequency. When tied to VBB, ClK is
2.048 MHz. When tied to GND, ClK is 1.544 MHz. When tied to VCC,
ClK is 1.536 MHz.

ClKR

CLKSEl

ClKX

Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable-date-rate mode. ClKR and
ClKX are internally connected for the TCM129C13, TCM129C16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.

DClKR

Fixed or variable-data-rate operation select. When connected to VBB,
the device operates in the fixed-data-rate mode. When DClKR is not
connected to VBB, the device operates in the variable-data-rate mode,
and DClKR becomes the receiver data clock. DClKR then operates at
frequencies from 64 kHz to 2.048 MHz.

DGTlGND

FSRfTSRE

Frame synchronization clock inpuVtime-slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and
nonsignaling frames by a double- or single-length pulse, respectively. In
the variable-data-rate mode, this signal must remain high forthe duration
of the time slot. The receive channel enters the standby state when FSR
is TIL low for 300 ms.

FSXfTSXE

Frame-synchronization clock inpuVtime-slot enable for transmit
channel. Operates independently of, but in an analagous manner to,
FSRfTSRE. The transmit channel enters the standby state when FSX is
low for 300 ms.

GSR

Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending on the
voltage at GSR.

GSX

Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.

PCM IN

Receive PCM input. PCM data is clocked in on eight consecutive
negative transitions of the receive data clock, which is ClKR in
fixed-data-rate timing and DClKR in variable-data-rate timing.

PCMOUT

Transmit PCM output. PCM data is clocked out on this output on eight
consecutive positive transitions of the transmit data clock, which is ClKX
in fixed-data-rate timing and DClKX in variable-data-rate timing .

Digital ground for all internal logic circuits. Not internally connected to
ANlG GND.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-5

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986- REVISED JULY 1996

Terminal Functions
TERMINAL NO.

NAME

TCM29C13
TCM129C13

TCM29C14
TCM129C14

TCM29C16
TCM29C17
TCM129C16
TCM129C17

PON

PWRO+

PWRO-

SIGR

DESCRIPTION

Power-down select. The device is inactive with a TTL low-level input to
this terminal and active with a TTL high-level input to the terminal.

Noninverting output of power amplifier. Can drive transformer hybrids or
high-impedance loads directly in either a differential or a single-ended
configuration

Inverting output of power amplifier. Functionally identical with and
complementary to PWRO+.

Signaling bit output, receive channel. In a fixed-data-rate mode, outputs
the logical state of the 8th bit (LSB) of the PCM word in the most recent
signaling frame.

A-law and Il-Iaw operation select. When connected to VSS, A-law is
selected. When connected to VCC or GNO, Il-Iaw is selected. When not
connected to VSS, a TTL-level input is transmitted as the eighth bit (LSS)
of the PCM word during signaling frames on PCM OUT (TCM29C14 and
TCM129C14 only). SIGXlASEL is internally connected to provide Wlaw
operational for TCM29C16 and TCM129C16 and A-law operation for
TCM29C17 and TCM129C17.

110

Transmit channel time-slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, this terminal is an
open-drain output to be used as an enable signal for a 3-state output
buffer. In the variable-data rate mode, OCLKX becomes the transmit
data clock, which operates at TTL level from 64 kHz to 2.048 MHz.

SIGXlASEL

TSXlOCLKX

VSS

Most negative supply voltage. Input is -5 V ±5%.

VCC

Most positive supply voltage. Input is 5 V ±5%

•
TEXAS
INSTRUMENTS
2-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 15 V
Output voltage range, Va .......................................................... -0.3 V to 15 V
Input voltage range, VI ............................................................. -0.3 V to 15 V
Digital ground voltage range ........................................................ -0.3 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature ......................... 1375 mW
Operating free-air temperature range, TA: TCM29Cxx .................................. O°C to 70°C
TCM129Cxx ............................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package .............. 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values for maximum ratings are with respect to VBB.

recommended operating conditions (see Note 2)
Supply voltage, VCC (see Note 3)
Supply voltage, VBB

MIN

NOM

MAX

UNIT

4.75

5.25

-4.75

-5

-5.25

Digital ground voltage with respect to ANGL GND

High-level input voltage, VIH (all inputs except CLKSEL)
Low-level input voltage, VIL (all inputs except CLKSEL)

1.544 MHz
1.536 MHz

Load resistance, RL

Load capacitance, CL

Operating free-air temperature, TA
NOTES:

V
0.8

2.048 MHz
Clock-select input voltage

2.2

GSX
PWRO+ and/or PWRO-

VBB
0
VCC-0.5
10

TCM29Cxx

kn
n
50

PWRO+ and/or PWRO-

TCM129Cxx

0.5
VCC

300

GSX

VBB +0.5

100
0

-40

°C

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-7

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, fOCLK

=2.048 MHz, outputs not loaded

PARAMETER

TEST CONDITIONS

TCM29Cxx
MIN

MAX

Operating
ICC

Supply current
from Vce

Supply current
from VSS

Power dissipation

TYPt

MAX

FSX, FSR = VIL after 300 ms

0.5

0.7

1.5

Power down

PON = VIL after 10 Jls

0.3

0.8

0.4

-7

-9

-8

-13

Standby

FSX, FSR = VIL after 300 ms

-0.5

-1

-0.7

-1.5

Power down

PON = VIL after 10 Jls

-0.3

-0.8

-0.4

-1

Operating
Po

MIN

Standby

Operating
ISS

TCM129Cxx

TYPt

130

Standby

FSX, FSR = VIL after 300 ms

Power down

PON = VIL after 10 Jls

UNIT

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

digital interface
PARAMETER

TEST CONDITIONS

TCM129Cxx

TCM29Cxx
MIN

TYPt

MAX

MIN

lpCM OUT

IOH =-9.6mA

2.4

ISIGR

IOH =-1.2 mA

2.4

TYPt

MAX

UNIT

VOH

High-level output voltage

VOL

Low-level output voltage at PCM OUT,
TSX, SIGR

IOL=3.2 mA

0.4

0.5

IIH

High-level input current, any digital input

VI = 2.2 V to VCC

JlA

IlL

Low-level input current, any digital input

VI = Oto 0.8 V

JlA

Input capacitance

Output capacitance

pF
pF

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

transmit amplifier input
PARAMETER

TEST CONDITIONS

MIN

TYPt

Input current at ANLG IN +, ANLG IN Input offset voltage at ANLG IN +, ANLG IN -

VI = -2.17 V to 2.17 V

Common-mode rejection at ANLG IN +, ANLG IN -

MAX

±25

mV
dS

Open-loop voltage amplification at GSX

UNIT

±100

5000

Open-loop unity-gain bandwidth at GSX

Input current at ANLG IN+, ANLG IN-

MHz

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

receive filter output
PARAMETER

TEST CONDITIONS

Output offset voltage PWRO+, PWRO- (single ended)

Relative to ANLG GND

Output resistance at PWRO+, PWRO-

TYPt

MAX

180

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

~TEXAS

INSTRUMENTS
2-8

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
mV
n

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

gain and dynamic range, Vee
(see Notes 4, 5, and 6)

=5 V,VBB =5 V, TA =25°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

Encoder milliwatt response (transmit gain tolerance)

Signal input = 1.064 Vrms for /l-Iaw,
Signal input = 1.068 Vrms for A-law

Encoder milliwatt response additional tolerance
(nominal supplies and temperature)

TA = O°C to 70°C,

Digital milliwatt response (receive tolerance gain)
relative to zero-transmission-Ievel point

Signal input per CCITT G.711,
Output signal = 1 kHz

Digital milliwatt response variation with temperature
and supplies

TA = O°C to 70°C,
/l-Iaw

-'---

Zero-transmission-Ievel point, transmit channel
(0 dBmO)

A-law

-/l-Iaw
A-law
/l-Iaw

-'---

Zero-transmission-Ievel point, receive channel
(0 dBmO)

A-law
/l-Iaw

-'---

A-law

MIN

TYP

MAX

UNIT

±0.04

±0.02

dBmO

±0.08

±0.02

dBmO

±0.08

Supplies = ± 5%
±0.04

Supplies = ± 5%
2.76

RL = 600 n

2.79

dBm

1
RL = 900n

1.03
5.76

RL= 600 n

5.79

dBm

RL =900 n

4.03

NOTES: 4. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference point of
the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
5. The input amplifier is set for noninverting unity gain. The digital input is a PCM bit stream generated by passing a O-dBmO, 1020-Hz
sine wave through an ideal encoder.
6. Receive output is measured single ended in the maximum gain configuration. To set the output amplifier for maximum gain, GSR is
connected to PWRO- and the output is taken at PWRO+. All output levels are (sin x)/x corrected.

gain tracking over recommended ranges of supply voltage and operating free-air temperature,
reference level -10 dBmO

PARAMETER

TEST CONDITIONS
3 ;:: input level;:: -40 dBmO

Transmit gain-tracking error, sinusoidal input

Receive gain-tracking error, sinusoidal input

MIN

MAX

UNIT

±0.25

-40> input level;:: -50 dBmO

±0.5

-50 > input level;:: -55 dBmO

±1.2

3;:: input level;:: -40 dBmO

±0.25

-40> input level;:: -50 dBmO

±0.5

-50> input level;:: -55 dBmO

±1.2

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-9

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

noise over recommended ranges of supply voltage and operating free-air temperature range
PARAMETER

TEST CONDITIONS

Transmit noise, C-message weighted

ANLG IN+ = ANLG GND,

ANLG IN- = GSX

Transmit noise, C-message weighted with 8-bitsignaling (TCM29C14 and TCM129C14 only)

ANLG IN+ = ANLG GND,
6th frame signaling

ANLG IN- = GSX,

Transmit noise, psophometrically weighted

ANLG IN+ = ANLG GND,

ANLG IN- = GSX

Receive noise, C-message-weighted quiet code

PCM IN = 11111111 (Il-Iaw), PCM IN = 10101010
(A-law), measured at PWRO+

Receive noise, C-message-weighted sign bit toggled

Input to PCM IN is zero code with sign bit toggled at
1-kHz rate

Receive noise, psophometrically weighted

PCM = lowest positive decode level

MIN

MAX

UNIT

dBrnCO

-69

dBmOp

dBrnCO

dBrmCO

-79

dBmOp

'power-supply rejection ratio and crosstalk attenuation over recommended ranges of supply
voltage and operating free-air temperature
PARAMETER
VCC supply-voltage rejection ratio,
transmit channel
VBB supply-voltage rejection ratio,
transmit channel

VCC supply-voltage rejection ratio,
receive channel (single ended)
VBB supply-voltage rejection ratio,
receive channel (single ended)

TEST CONDITIONS
O:;;f < 30 kHz
30:;;f < 50 kHz
0:;; f < 30 kHz
30:;;f < 50 kHz
O:;;f < 30 kHz
30:;;f < 50 kHz
O:;;f < 30 kHz
30:;;f < 50 kHz

MIN

TVPt

Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT

-30

Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT

-30

Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PWRO +

-20

MAX

UNIT
dB

-45

dB
-55

dB
-45

Idle channel,
Supply signal = 200 mV(peak-to-peak),
Narrow band,
f measured at PWRO +

-20
dB
-45

Crosstalk attenuation, transmit to receive
(single ended)

ANLG IN+ = 0 dBmO, f = 1.02 kHz,
Unity gain,
PCM IN = lowest decode level,
Measured at PWRO+

Crosstalk attenuation, receive to transmit
(single ended)

PCM IN = 0 dBmO,
f = 1.02 kHz,
Measured at PCM OUT

t All typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C.

~TEXAS

INSTRUMENTS
2-10

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

o dBmO ~ ANLG IN+ ~ -30 dBmO
Transmit signal-to-distortion ratio, sinusoidal
input (CCITT G.712 - Method 2)

Receive signal-to-distortion ratio, sinusoidal
input (CCITT G.712 - Method 2)

-30 dBmO > ANLG IN+ ~ -40 dBmO

-40 dBmO > ANLG IN+ ~ -45 dBmO

o dBmO ~ ANLG IN+ ~ -30 dBmO

-30 dBmO > ANLG IN+

-40 dBmO

-40 dBmO > ANLG IN+

-45 dBmO

Transmit single-frequency distortion products

AT&T Advisory #64 (3.8), Input signal

Receive single-frequency distortion products

AT&T Advisory #64 (3.8), Input signal

Intermodulation distortion, end-to-end spurious
out-at-band signals, end-to-end

MAX

UNIT

=0 dBmO
=0 dBmO

-46

dBmO

-46

dBmO

CCITT G.712 (7.1)

-35

CCITTG.712 (7.2)

-49

CCITT G.712 (6.1)

-25

CCITT G.712 (9)

-40

Transmit absolute delay time to PCM Ol)T

Fixed-data rate,
fCLKX + 2.048 MHz,
Input to ANLG IN + 1.02 kHz at 0 dBmO

Transmit differential envelope delay time
relative to transmit absolute delay time

=500 Hz to 600 Hz
f = 600 Hz to 1000 Hz
f = 1000 Hz to 2600 Hz
f =2600 Hz to 2800 Hz

Receive absolute delay time to PWRO+

Fixed-data rate,
fCLKR + 2.048 MHz,
Digital input is DMW code

dBmO

Ils

245
170
95

Ils

45
105

f = 500 Hz to 600 Hz

190

Ils

=600 Hz to 1000 Hz
= 1000 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
t All typical values are at VBB =-5 V, VCC =5 V, and TA =25°C.
Receive differential envelope delay time
relative to transmit absolute delay time

TYPt

Ils

110

transmit filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER

TEST CONDITIONS

MIN

f = 16.67 Hz

Input amplifier set for unity gain,
Noninverting maximum gain output,
Input signal at ANLG IN + is 0 dBmO

= 50 Hz

-25
-23

f = 200 Hz

= 300 Hz to 3 kHz
f = 3.3 kHz
f = 3.4 kHz
t = 4 kHz
f = 4.6 kHz and above
f

UNIT

-30

t = 60 Hz

Gain relative to gain at 1.02 kHz

MAX

-1.8

-0.125

-0.15

0.15

-0.35

0.15

-1

-0.1

-14
-32

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-11

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

f < 200 Hz

Gain relative to gain at 1.02 kHz

Input signal at PCM IN is 0 dBmO

=200 Hz

-0.5

0.15

f = 300 Hz to 3 kHz

-0.15

0.15

f = 3.3 kHz

-0.35

0.15

=3.4 kHz
f =4 kHz

-1

-0.1

UNIT

0.15

-14

4.6 kHz

-30

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)

MIN

tc(CLK)

Clock period for CLKX, CLKR (2.048-MHz systems)

tr,tf

Rise and fall times for CLKX and CLKR

tw(CLK)

Pulse duration for CLKX and CLKR (see Note 7)

220

tw(DCLK)

Pulse duration, DCLK (fDCLK = 64 kHz to 2.048 MHz) (see Note 7)

220

TYPt

MAX

488

ns
30

Clock duty cycle, [tw(CLK)itc(CLK)l for CLKX and CLKR

45%

UNIT

ns
ns
ns

50%

55%

All typical values are at VBB =-5 V, VCC = 5 V, and TA = 25°C.
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
MIN

MAX

UNIT

100

tc(CLK) -100

td(FSX)

Frame-sync delay time

tsu(SIGX)

Setup time before bit 7 falling edge of CLKX (TMC29C14 and TCM129C14 only)

th(SIGX)

Hold time after bit 8 falling edge of CLKX (TCM29C13 and TCM129C14 only)

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
PARAMETER

MIN

MAX

100

tc (CLK)-100

UNIT

td(FSR)

Frame-sync delay time

tsu(PCM IN)

Setup time before bit 1 falling edge (TCM129C14 and TCM29C14 only)

th(PCM IN)

Hold time after bit 1 falling edge (TCM129C14 and TCM29C14 only)

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 5)
PARAMETER

MIN

MAX

UNIT

td(TSDX)

Time-slot delay time from DCLKX (see Note 8)

140 td(DCLKX)-140

td(FSX)

Frame-sync delay time

100

tc(DCLKX)

Clock period for DCLKX

488

NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation .

•
TEXAS
INSTRUMENTS
2-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t c (CLK)-100
15620

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MIN

MAX

td(TSDR)

Time-slot delay time from DCLKR (see Note 9)

140

td(DCLKR)-140

td(FSR)

Frame-sync delay time

100

t c (CLK)-100

PARAMETER

tsu(PCM IN)

Setup time before bit 3 falling edge

th(PCM IN)

Hold time after bit 4 falling edge

tcJDCLKR)

Data clock period

tSER

Time-slot end receive time

488

UNIT

ns
ns
15620

NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.

64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-,rate mode
PARAMETER

TEST CONDITIONS

MIN

tFSLX

Transmit frame-sync minimum down time

FSX = TTL high for remainder of frame

488

tFSLR

Receive frame-sync minimum down time

FSR = TTL high for remainder of frame

1952

tw(DCLK)

Pulse duration, data clock

MAX

UNIT
ns
ns

IlS '

switching characteristics
propagation delay times over recommended ranges of supply voltage and operating free-air temperature,
fixed-data-rate mode (see Figures 3 and 4)
MIN

MAX

CL = 0 to 100 pF

145

From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)

CL = 0 to 100 pF

145

tpd3

From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)

CL=O

215

tpd4

From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)

CL = 0 to 100 pF

145

tpd5

From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)

CL=O

190

tpd6

From rising edge of channel time slot to SIGR update (TCM129C14 and
TCM29C14 only)

IlS

PARAMETER

TEST CONDITIONS

tpd1

From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)

tpd2

UNIT

NOTE 10: Timing parameters tpd1' tpd3, and tpd5 are referenced to the high-impedance state.

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Note 11 and Figure 5)
MIN

MAX

tpd7

Data delay time from DCLKX

PARAMETER

CL = 0 to 100 pF

TEST CONDITIONS

100

UNIT
ns

tpd8

Data delay time from time-slot enable to PCM OUT

CL = 0 to 100 pF

tpd9

Data delay time from time-slot disable to PCM OUT

CL = 0 to 100 pF

tpd10

Data delay time from FSX

td(TSDX) = 80 ns

140

NOTE 11: Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-13

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

CLKR and CLKX selection requirements for DSP-based applications
1.

Note that CLKX and CLKR must be selected as follows:
CLKSEL
-5

OV
5V

CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

DEVICE TYPE

=(256) x (frame-sync frequency)

TCM29C13/14/16/17

=(193) x (frame-sync frequency)

TCM29C13/14

=(192) x (frame-sync frequency)

TCM29C13/14

TCM 129C13/14/16/17

TCM129C13/14

e. g., for frame-sync frequency = 9.6 kHz
CLKSEL

-5

CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

=2.4576 MHz

= 1.8528 MHz

= 1.8432 MHz

DEVICE TYPE
TCM29C13/14/16/17
TCM129C13/14/16/17
TCM29C13/14
TCM129C13/14
TCM29C13/14
TCM129C13/14

CLKSEL

.IS .Internally set to -5 V for TCM129C16/17 and TCM29C16/17 .

Corner frequency at 8-kHz frame-sync frequency = 3 kHz
Therefore, the corner frequency = (3/8) x (frame-sync frequency for nonstandard frame sync) .

•
TEXAS
INSTRUMENTS
2-14

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

0.15 dB
Q)

iii
o
en

-0.10 dB 0

'C
Q)

'C
I:

r::s

-1

Typical Filter
Transfer Function

200 Hz
.c
'C

I
N

J:
~

,..

-10

'i;

<
w

-0.15 dB /'"
3000y-:"
-0.35 dB
3300 Hz
-1dB
3400 Hz

300 Hz
-1

.c
'C

-1

..lI:

....

1ii
c

'iij
~

oS
CI)

.2:

1ii

-10

-14 dB

'iij
~

-20

-30

-40

-50~~~----~----~~~~~~------~--~~~~~~~-50

100

1k
f - Frequency - Hz

NOTE A: This is a typical transfer function of the receive filter component.

Figure 2. Transfer Characteristics of the Receive Filter

~TEXAS

INSTRUMENTS
2-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

c
ca
c.

10 k

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

CLKX
FSX Input
(nonsignaling

--.j ~ td(FSX)

frames)~ II
~ I.-

FSX Input
(signaling}f
frames)

1tr

----+1--------------...;..-.:.....--------

1...

-+;

td(FSX)

~\--

td(FSX)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

FRAME SYNCHRONIZATION TIMING

CLKX

TSX Output
tsu(SIGX)

-+I

--IX

SIGX Input _ _ _ _ _ _ _ _ _ _ _ _D_o_n'_t_C_ar_e_ _ _ _ _ _ _ _ _

tpd5

~ r-~--

Ij/

14-

r
X

---.j

Valid

th(SIGX)
Don't Care

OUTPUT TIMING

Figure 3. Transmit Timing (Fixed-Data Rate)

CLKR

FSR
(nonsignaling
frames)
FSR
(signaling
frames)

-+I ~ td(FSR)

-+J

_____i~____________________~~_____________

jt- td(FSR)

!.-td(FSR)

~~I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ____
FRAME SYNCHRONIZATION TIMING

CLKR

PCMIN
Bit 1t
Valid

Bit2
Valid

Bit3
Valid

Bit 4
Valid

Bit 5
Valid

Bit 6
Valid

Bit 7
Valid

Bit st
Valid

SIGR Output _ _ _ _ _ _ _ _ _ _ _ _ _ _
Va_l_id_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~
INPUT TIMING

Figure 4. Receive Timing (Fixed-Data Rate)
t Bit 1 =MSB =sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 =LSB =least significant bit and is clocked in last
on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-17

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
1l1li

4' i/

FSX

1l1li 1 ~I

:'\-

td(TSDX)

"",\18
DCLKX

'--'

*- td(FSX)

2 \

'--'

3 \

'--' I

4 \

'--'

5 \

'--'

6 \

'--'

7 \

~I~

I s \

'--'

'+'

,f:\ /-'\ ,'\ ,'\ /;\ ,r-\, ,r-\, ,r-\, ,r-\, ,r-\, ,'1"', /

CLKX

....J

1 \

1 /

Time Slot

~'-'

\...J

-=!\ : :.- tpd1 0

PdS

PCM OUT

'-'

\...J

---+I

\...J

tpd9

\...J

Bit 1t

Figure 5. Transmit Timing (Variable-Data-Rate)
FSR

DCLKR

CLKR

PCM IN

Don't Care
Bit 1t

Bit2

Bit3

Bit4

Bit5

Bit6

Bit 7

BitSt

Figure 6. Receive Timing (Variable-Data-Rate)

t Bit 1 =MSB =sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 =LSB =least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.

NOTE A: All timing parameters are referenced to VIH and VIL except tpd8 and tp d9, which references the high-impedance state.

~TEXAS

INSTRUMENTS
2-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
General TCM29C13, TCM29C14, TCM29C16, TCM29C17, TCM129C13, TCM129C14, TCM129C16, and
TCM129C17 system reliability and design considerations are described in the following paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM29Cxx and TCM129Cxx are heavily protected against latch-up, it is still possible to cause
latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up
can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage
rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied
but before the ground is connected. This can happen if the device is hot-inserted into a card with the power
applied, or if the device is mounted on a card that has an edge connector, and the card is hot-inserted into a
system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent), between
each power supply and GND (see Figure 7). If it is possible that a TCM29Cxx- or TCM129Cxx-equipped card
that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that
the ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.

device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.

Ensure no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply Vee (most positive voltage).

Force a power down condition in the device.

Connect the clocks.

Release the power-down condition.

Apply FSX and/or FXR synchronization pulses.

Apply signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-19

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC

DGND

Vee
Figure 7. Diode Configuration for Latch-Up Protection Circuitry
internal sequencing
On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for
approximately four frames (500 Ils) after power up or application of VBB or Vee. Afterthis delay, PCM OUT, TSX,
and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Therefore, valid
digital information, such as on/off hook detection, is available almost immediately while analog information is
available after some delay.
On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up
or application of VBB or Vee. SIGR remains low until it is updated by a signaling frame.
To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately
20 J.ls after an interruption of CLKX. SIGR is held low approximately 20 Ils after an interruption of CLKR. These
interruptions could possibly occur with some kind of fault condition.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PON. In the absence of a signal, PON is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 5 mW.
Three standby modes give the user the options of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is
held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the
entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for
power-down and standby procedures.

Table 1. Power-Down and Standby Procedures
DEVICE STATUS
Power down
Entire device on standby
Only transinit on standby
Only receive on standby

TYPICAL POWER
CONSUMPTION

PROCEDURE
PDN low
FSX and FSR are low
FSX is low,

FSR is high

FSR is low,

FSX is high

DIGITAL OUTPUT STATUS

3mW

TSX and PCM OUT are in the high-impedance state; SIGR
goes low within 10 (ls.

3mW

TSX and PCM OUT are in the high-impedance state; SIGR
goes low within 300 ms.

40mW

TSX and PCM OUT are placed in the high-impedance state
within 300 ms.

30mW

SIGR is placed in the high-impedance state within 300 ms.

~TEXAS

2-20

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION

fixed-data-rate timing (see Figure 8)
Fixed-data-rate timing is selected by connecting DCLKR to VBB and uses master clocks CLKX and CLKR,
frame-synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the sampling
frequency and distinguish between signaling and nonsignaling frames by their pulse durations. A frame
synchronization pulse one master-clock period long designates a nonsignaling frame, while a double-length
sync pulse enables the signaling function (TCM29C14 and TCM129C14 only). Data is transmitted on PCM OUT
on the first eight positive transitions of CLKX following the rising edge of FSR. Data is received on PCM IN on
the first eight falling edges of CLKR following FSR. A digital-to-analog (D/A) conversion is performed on the
received digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until
transferred to the receive filter.
The clock-selection pin (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM29C13, TCM29C14,
TCM129C13, and TCM129C14 only). The TCM29C13, TCM29C14, TCM129C13, and TCM129C14 fixeddata-rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz. The TCM29C16,
TCM29C17, TCM129C16, and TCM129C17 fixed-data-rate mode operates at 2.048 MHz only.

!4-------

I
Other
--.!I
~TS1X
.1
1
Time Slots
CLKX~~
1-

4 5

6 7

PCM OUT

~TS1X----.!

4 5

Transmit Signal Frame

1921193/256

FSX

I-

=::::x::x::x::::

,,~L..-.----------

'I',

8788 SIGX

81 82838485868788

TSX~

81 82838485861

~I~,--------~\~-~

_____~I~r-I----

1 Don't Care
SIGX -------------~~----------~l-::x::-------v-~,.--I--------------S~----7-----~l_
Valid
Don't Care

-----

1921193/256

!4------1

Other
--.!
~TS1R
.1
Time Slots
I
CLKR~~
I

4 5

6 7

I-

~TS1R

8 9
Receive Signal Frame

1921193/256

FSRJlL..-.-_ _ _ _ _ _ _4~.r~--------~~~L..-.---------SIGR

peM.N

SIGR

-::::x::x::x::::---------------=
~

B, B2B,B4BSB6B7BS

~~
Previou5 Value

New Value

Figure 8. Signaling Timing (Fixed-Data-Rate Only)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-21

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION

variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to VBB. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 2.048 MHz. Master clocks in the TCM29C13, TCM29C14, TCM129C13, and TCM129C14 are
restricted to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing
mode. The master clock for the TCM29C16, TCM29C17, TCM129C16, and TCM129C17 is restricted to 2.048
MHz.
When the FSXfTSXE is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSRfTSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
The transmitted PCM word is repeated in all remaining time slots in the 125-I1S frame as long as DCLKX is pulsed
and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than
once per frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the
fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling
frame.

signaling
The TCM29C14 (only) provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are independent of each other and are selected by a double-width frame-sync pulse on the
appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for the least
Significant bit (LSS) of the encoded PCM word. In a receive signaling frame, the codec decodes the seven most
significant bits in accordance with CCITT G.733 recommendations and outputs the logical state of the LSS on
SIGR until it is updated in the next signaling frame. Timing relationships for signaling operations are shown in
Figure 8. The signaling path is used to transmit digital signaling information such as ring control, rotary dial
pulses, and off-hook and disconnect supervision. The voice path is used to transmit prerecorded messages as
well as the call progress tones: dial tone, ring-back tone, busy tone, and reorder tone.

~TEXAS

2-22

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION

analog loopback
A distinctive feature of the TCM29C14 and TCM129C14 is the analog loopbackcapability. With this feature, the
user can test the line circuit remotely by comparing the signals sent into the receive channel (PCM IN) with those
generated on the transmit channel (PCM OUT). The test is accomplished by sending a control signal that
internally connects the analog input and output ports. When ANLG LOOP is TTL high, the receive output
(PWRO+) is internally connected to ANLG IN+, GSR is internally connected to PWRO-, and ANLG IN- is
internally connected to GSX (see Figure 9).
r--------------------AN~~O~

I
I
Transmit
,Voice

ANLG IN-

GSX

I
I

b;
I
I

PWRO+
PWRO-

I
I

GSR

PCM OUT
Digitized PCM
Loopback
Response

PCMIN
Digitized PCM
Test Tone

~-------------------------~

Figure 9. TCM129C14 and TCM29C14 Analog Loopback Configuration
Due to the difference in the transmit and receive transmission levels, a O-dBmO code into PCM IN emerges from
PCM OUT as a 3-dBmO code, an implicit gain of 3 dB. Because of this, the maximum signal that can be tested
by analog loopback is 0 dBmO.

precision voltage references
Voltage references that determine the gain dynamic range characteristics of the device are generated internally.
No external components are required to provide the voltage references. A difference in subsurface charge
density between two suitably implanted MaS device is used to derive a temperature- and bias-stable reference
voltage, which is calibrated during the manufacturing process. Separate references are supplied to the transmit
and receive sections, and each is calibrated independently. Each reference value is then further trimmed in the
gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically ±O.04 dB can
be achieved in absolute gain for each half channel, providing the user a significant margin to compensate for
error in other system components.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-23

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G -APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION

conversion laws
The TCM29C13, TCM29C14, TCM129C13, and TCM129C14 provide pin-selectable Il-Iaw or A-law operation
as specified by CCITT G.711 recommendation. A-law operation is selected when ASEL is connected to Vss,
and Il-Iaw operation is selected by connecting ASEL to Vee or GND. Signaling is not allowed during A-law
operation. If Il-Iaw operation is selected, SIGX is a TTL-level input that can be used in the fixed-data-rate timing
mode to modify the LSB of the PCM output is signaling frames.
The TCM29C16 and TCM129C16 are Il-Iaw only; the TCM29C17 and TCM129C17 are A-law only.

transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kn in parallel with less than 50 pF. The input signal on ANLG IN + can be either ac or dc coupled. The input
operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing filter section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.
The pass-band section provides flatness and stop-band attenuation that fulfills the AT&T D3/D4 channel bank
transmission specification and CCITT recommendation G. 712. The device specifications meet or exceed digital
class 5 central office switching-systems requirements.
A high-pass section configuration has been chosen to reject low-frequency noise from 50- and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation
at 200 Hz. This feature allows the use of low-cost transformer hybrids without external components.

encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal
sample-and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor
array. Digital data representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses the
sign-bit-averaging technique. The sign bit from the encoder output is long-term averaged and subtracted from
the input to the encoder. All dc offset is removed from the encoder input waveform.

receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T
D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the
(sin x)/x response of such decoders.

~TEXAS

INSTRUMENTS
2-24

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS011 G - APRIL 1986 - REVISED JULY 1996

PRINCIPLES OF OPERATION
receive output power amplifiers
A balanced-output amplifier is provided to allow maximum flexibility in output configuration. Either of the two
outputs can be used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively,
the differential output directly drives a bridged load. The output stage is capable of driving loads as low as 300-Q
single-ended to a level of 12 dBm or 600 Q differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulation qf the GSR
input. GSR is internally connected to an analog gain-setting network. When GSR is connected to PWRO-, the
receive level is maximum. When GSR is connected to PWRO+, the level is minimum. The output transmission
level is adjusted between 0 and -12 dB as GSR is adjusted (with an adjustable resistor) between PWRO+ and
PWRO-.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-25

TCM29C13, TCM29C14, TCM29C16, TCM29C17,
TCM129C13, TCM129C14, TCM129C16, TCM129C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS011G - APRIL 1986 - REVISED JULY 1996

APPLICATION INFORMATION

output gain-set design considerations (see Figure 9)
PWRO+ and PWRO- are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at PWRO+
VO- at PWROVOD = Vo+ - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap to the GSR input.
A value greater than 10 kn and less than 100 kn for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and RL sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital milliwatt output response (VA = 3.006 Vrms).
VOD=AxVA
1 + (R11R2)
where A = 4 + (R1/R2)
2

i
Vo
<

-*-

~II-

PWRO+

R1 >
4

VOD

GSR

R2~

i
VO-

TCM129C13
TCM129C14
TCM129C16
TCM129C17
TCM29C13
TCM29C14
TCM29C16
TCM29C17

PWRO-

PCMIN

.....
Digital Milliwatt
Sequence Per
CCITTG.711

-*-

Pin numbers shown are for the TCM29C13, TCM29C14, TCM129C13, and TCM129C14 package only.

Figure 10. Gain-Setting Configuration

•
TEXAS
INSTRUMENTS
2-26

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

•

Replace Use of TCM291 OA and TCM2911 A
in Tandem With TCM2912B/C

•

Reliable Silicon-Gate CMOS Technology

•

Low Power Consumption:
Operating Mode ... 80 mW Typical
Power-Down Mode ... 5 mW Typical

FEATURES TABLE
FEATURE
Number of Pins:
24
20
16

29C13A 29C14A 29C16A 29C17A
129C13A 129C14A 129C16A 129C17A
X
X
X

Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz

it-Law/A-Law Coding:
it-Law
A-Law

•

No External Components Needed for
Sample, Hold, and Autozero Functions

Gain Timing Rates:
Variable Mode
64 kHz to 2.048 MHz

4iJ

Precision Internal Voltage References

•

Improved Version of TCM29C13 Series
and TCM129C13 Series

Fixed Mode
1.536 MHz
1.544 MHz
2.048 MHz

X
X
X

X
X

Loopback Test Capability

8th-Sit Signaling

description
The TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A,
and TCM129C17 A are single-chip PCM codecs (pulse-code-modulated encoders and decoders) and PCM line
filters. These devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit
with a time-division-multiplexed (TOM) system. These devices are intended to replace the TCM2910A or
TCM2911 A in tandem with the TCM2912C. Primary applications include:
•
•
•
•
•

Line interface for digital transmission and switching of T1 carrier, PABX, and central office telephone
systems
Subscriber line concentrators
Digital-encryption systems
Digital voice-band data storage systems
Digital signal processing

TCM29C13A, TCM129C13A
ow OR N PACKAGE
(TOP VIEW)
Vss
PWRO+
PWROGSR
PON
CLKSEL
OCLKR
PCM IN
FSRITSRE
OGTLGNO

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VCC
GSX
ANLG INANLG IN+
ANLG GNO
SIGXlASEL
TSXlOCLKX
PCM OUT
FSXlTSXE
CLKR/CLKX

TCM29C14A, TCM129C14A
ow PACKAGE
(TOP VIEW)
Vss
PWRO+
PWROGSR
PON
CLKSEL
ANLG LOOP
SIGR
OCLKR
PCM IN
FSRITSRE
OGTLGNO

1
2
3
4
5
6
7
8
9
10
11
12

TCM29C16, TCM29C16A,
TCM129C16, TCM129C17A
OW OR N PACKAGE
(TOP VIEW)

V 240 VCC
23
22
21
20
19
18
17
16
15
14
13

GSX
ANLG INANLG IN+
ANLG GNO
NC
SIGXlASEL
TSXlOCLKX
PCM OUT
FSXlTSXE
CLKX
CLKR

Vss
PWRO+
PWROPON
OCLKR
PCM IN
FSRITSRE
OGTLGND

1
2
3
4
5
6
7
8

16~ VCC

15 ~
14
13
12
11
10
9

GSX
ANLG INANLG GNO
TSXlOCLKX
PCM OUT
FSXlTSXE
CLKR/CLKX

NC - No internal connection

These devices have limited built-in ESO protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PRODucnON DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-27

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

description (continued)
These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They are
intended to be used at the analog termination of a PCM line or trunk.
The TCM29C13A, TCM29C13A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A, TCM129C16A,
and TCM129C17 A provide the band-pass filtering of the analog signals prior to encoding and after decoding.
These combination devices perform the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information. These devices contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below -55 dBmO.
The TCM29C13A, TCM29C14A, TCM29C16A, and TCM29C17 A are characterized for operation from O°C to
70°C. The TCM129C13A, TCM129C14A, TCM129C16A, and TCM129C17A are characterized for operation
from -40°C to 85°C.

functional block diagram

------------------------------------1I
Transmit Section

I
I
I
I

Sample
and Hold
and DAC

ANLG IN+
ANLG IN-

Successive
. Approximation

Comparator

Output
Register

PCMOUT
TSXlDCLKX
SIGXlASEL

GSX~e------'

Analogto-Digital
Control
Logic

~--------------~--~rFSXlTSXE

....- - - - - - - - - - - - - - - - - 4 - 1 -

CLKX

r----------------------- -r----------j---I

GSR

PWRO-

I
I
I

Control

Receive Section

I Section
I
I
L
Digitalto-Analog
Control
Logic

-i-oI....- - - ,

PWRO+ --T input level

-50 dBmO

±0.5

-50> input level ~ -55 dBmO

±1.2

3 ~ input level ~ -40 dBmO

±0.25

-40> input level ~ -50 dBmO

±0.5

-50> input level

-55 dBmO

UNIT

±1.2

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-33

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

noise over recommended ranges of supply voltage and operating free-air temperature range
PARAMETER

TEST CONDITIONS

Transmit noise, C-message weighted:t:

=ANLG GND,
ANLG IN+ = ANLG GND,
ANLG IN+

MIN

ANLG IN- =GSX

TYPt

MAX

dBrnCO

ANLG IN- =GSX,

UNIT

Transmit noise, C-message weighted with eight-bit
signaling (TCM129C14A and TCM29C14A only)

6th frame signaling

Transmit noise, psophometrically weighted:t:

ANLG IN+

-82

-80

dBmOp

Receive noise, C-message-weighted quiet code

PCM IN = 11111111 (~-Iaw),
PCM IN = 10101010 (A-law),
Measured at PWRO+

dBrnCO

Receive noise, C-message-weighted sigri bit
toggled

Input to PCM IN is zero code with sign bit toggled
at 1-kHz rate

dBrnCO

Receive noise, psophometrically weighted

PCM

-81

dBmOp

= ANLG GND,

ANLG IN- =GSX

= lowest positive decode level

All typical values are at VBS -5 V, VCC = 5 V, and TA 25°C.
:t: This parameter is achieved through the use of patented circuitry and is not recommended for applications in which composite signals on the
transmit side are below -55 dSmO.

power supply rejection ratio and crosstalk attenuation over recommended ranges of supply
voltage and operating free-air temperature
PARAMETER
VCC supply-voltage rejection ratio,
transmit channel

VBS supply-voltage rejection ratio,
transmit channel
VCC supply-voltage rejection ratio,
receive channel (single ended)

VBS supply-voltage rejection ratio,
receive channel (single ended)

TEST CONDITIONS
O:5f < 30 kHz
30:5f < 50 kHz
O:5f < 30 kHz
30:5f < 50 kHz
O:5f < 30 kHz
30:5f < 50 kHz
O:5f < 30 kHz
30:5f < 50 kHz

MIN

TYPt

Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT

-40

Idle channel,
Supply signal = 200 mV(peak-to-peak),
f measured at PCM OUT

-35

Idle channel,
Supply signal = 200 mV (peak-to-peak),
f measured at PWRO+

-40

Idle channel,
Supply signal = 200 mV(peak-to-peak),
Narrow-band f measured at PWRO +

-40

MAX

UNIT
dS

-45

dB
-55

dB
-45

Crosstalk attenuation, transmit to receive (single ended)

ANLG IN+ = 0 dBmO,
Unity gain,
f = 1.02 kHz,
PCM IN = lowest decode level,
Measured at PWRO+

Crosstalk attenuation, receive to transmit (single ended)

PCM IN = 0 dBmO, f = 1.02 kHz,
Measured at PCM OUT

t All typical values are at VSB =-5 V, VCC = 5 V, and TA =25°C.

~TEXAS

INSTRUMENTS
2-34

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
Transmit signal-to-distortion ratio, sinusoidal
input (CCITT G.712 - Method 2)

Receive signal-to-distortion ratio, sinusoidal
input (CCITT G.712 - Method 2)

TEST CONDITIONS

-30 > ANLG IN+ ~ -40 dBmO

-40 > ANLG IN+ ~ -45 dBmO

o ~ ANLG IN+ ~ -30 dBmO

-30 > ANLG IN+ ~ -40 dBmO

-40 > ANLG IN+ ::::: -45 dBmO

Transmit single-frequency distortion products

AT&T Advisory #64 (3.8), Input signal

Receive single-frequency distortion products

AT&T Advisory #64 (3.8), Input signal

Intermodulation distortion, end to end spurious
out-of-band signals, end to end

MIN

o ~ ANLG IN+ ~ -30 dBmO

TYPt

Transmit differential envelope delay time
relative to transmit absolute delay time

=0 dBmO
=0 dBmO

Receive absolute delay time to PWRO+

dBmO

-46

dBmO

-35

CCITT G.712 (7.2)

-49

CCITT G.712 (6.1)

-25

dBmO

-40

Fixed-data rate,
fCLKX 2.048 MHz,
Input to ANLG IN + 1.02 kHz at 0 dBmO

=500 Hz to 600 Hz
=600 Hz to 1000 Hz
f =1000 Hz to 2600 Hz
f =2600 Hz to 2800 Hz

Ils

245

170

Ils

45
105

=2.048 MHz,

=500 Hz to 600 Hz
=600 Hz t01 000 Hz
f =1000 Hz to 2600 Hz
f =2600 Hz to 2800 Hz
t All typical values are at VBB =-5 V, VCC =5 V, and TA =25°C.

190

Ils

Receive differential envelope delay time
relative to transmit absolute delay time

-46

CCITT G.712 (7.1)

Fixed data rate,
fCLKR
Digital input is DMW codes

UNIT

CCITT G.712 (9)
Transmit absolute delay time to PCM OUT

MAX

Ils

85
110

transmit filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 1)
PARAMETER

TEST CONDITIONS

MIN

-30

50Hz

-25

Gain relative to gain at 1.02 kHz

200Hz

-1.8

-0.125

300 Hz to 3 kHz

-0.15

0.15

3.3 kHz

-0.35

0.15

3.4 kHz

-1

-0.1

4 kHz

UNIT

-23

60 Hz
Input amplifier set for unity gain,
Noninverting maximum gain output,
Input Signal at ANLG IN + is 0 dBmO

MAX

16.67 Hz

-14

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-35

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
MIN

TEST CONDITIONS

PARAMETER

Below 200 Hz

Input signal at PCM IN is 0 dBmO

UNIT

0.15

200Hz

Gain relative to gain at 1.02 kHz

MAX

-0.5

0.15

300 Hz to 3 kHz

-0.15

0.15

3.3 kHz

-0.35

0.15

3.4 kHz

-1

-0.1

4 kHz

-14

4.6 kHz

-30

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 3)
MIN
tc(CLK)

Clock period for CLKX, CLKR (2.048-MHz systems)

tr,tf

Rise and fall times for CLKX and CLKR

tw(CLK)

Pulse duration for CLKX and CLKR (see Note 7)
Pulse duration, DCLK (fDCLK

tw(DCLK)

TYpt

MAX

488

ns
30

=64 Hz to 2.048 MHz) (see Note 7)

Clock duty cycle, [tw(CLK)/tc(CLK)l for CLKX and CLKR

220

ns
ns

220
45%

UNIT

ns
50%

55%

t All typical values are at VBB =-5 V, VCC =5 V, and TA =25°C.
NOTE 7: FSX ClK must be phase locked with CLKX. FSR ClK must be phase locked with CLKR.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
MIN

MAX

UNIT

100

tc(CLK) -100

tdJFSX)

Frame-sync delay time

tsu(SIGX)

Setup time before bit 7 falling edge of CLKX (TMC29C14A and TCM129C14A only)

th(SIGX)

Hold time after bit 8 falling edge of CLKX (TCM29C14A and TCM129C14A only)

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 6)
MIN

MAX

UNIT

td(FSR)

Frame-sync delay time

100

tc (CLK)-100

tsu{PCM INl

Receive data setup time

th(PCM IN)

Receive data hold time

PARAMETER

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 5)
PARAMETER

MIN

MAX

UNIT

td(TSDX)

Time-slot delay time from DCLKX (see Note 8)

140 td(DCLKX)-140

tcI{FSXl

Frame sync delay time

100

tc(DCLKX)

Clock period for DCLKX

488

NOTE 8: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.

"TEXAS

INSTRUMENTS

2-36

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

tc(CLK)-100
15620

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
PARAMETER

MIN

MAX

UNIT

td{TSDRl

Time-slot delay time from DCLKR (see Note 9)

140

tdlDCLKR):-140

td(FSR)

Frame-sync delay time

100

t c (CLK)-100

tsuJPCM IN)

Receive data setup time

th(PCM IN)

Receive data hold time

tc(DCLKR)

Data clock period

tSER

Time-slot end receive time

ns
ns
ns

60
488

15620

NOTE 9: tFSLR minimum requirement overrides the td(TSDR) maximum requirement for 64-kHz operation.

64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
PARAMETER

TEST CONDITIONS

tFSLX

Transmit frame-sync minimum down time

tFSLR

Receive frame-sync minimum down time

tw(DCLK)

Pulse duration, data clock

MIN

FSX = TTL high for remainder of frame

MAX

UNIT

488

1952

ns
10

Ils

switching characteristics
propagation delay times over recommended ranges of supply voltage and operating free-air temperature,
fixed-data-rate mode (see Figure 3 and 4)
PARAMETER

TEST CONDITIONS

MIN

MAX

CL = 0 to 100 pF

145

From rising edge of transmit clock bit n to bit n data valid at PCM OUT (data
valid time)

CL =0 to 100 pF

145

tpd3

From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT (data float time
on time-slot exit) (see Note 10)

CL=O

215

tpd4

From rising edge of transmit clock bit 1 to TSX active (low) (time-slot enable
time)

CL = 0 to 100 pF

145

tpd5

From falling edge of transmit clock bit 8 to TSX inactive (high) (time-slot disable
time) (see Note 10)

CL=O

190

tpd6

From rising edge of channel time slot to SIGR update (TCM29C14A and
TCM129C14A only)

Ils

tpd1

From rising edge of transmit clock to bit 1 data valid at PCM OUT (data enable
time on time-slot entry) (see Note 10)

tpd2

UNIT

NOTE 10: Timing parameters t pd1, tpd3, and tpd5 are referenced to the high-impedance state.

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Note 11 and Figure 5)
PARAMETER

TEST CONDITIONS

~d7

Data delay time from DCLKX

tpd8

Data delay from time-slot enable to PCM OUT

tpd9

Data delay from time-slot disable to PCM OUT

t pd10

Data delay time from FSX

CL = 0 to 100 pF

td(TSDX) = 80 ns

MIN

MAX

100

UNIT
ns

140

NOTE 11: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-37

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D- AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

CLKR and CLKX selection requirements for DSP-based applications
1.

Note that CLKX and CLKR must be selected as follows:
CLKSEL

CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

-5Vt

= (256) x (frame-sync frequency)

= (193) x (frame-sync frequency)

= (192) x (frame-sync frequency)

DEVICE TYPE
TCM29C 13A114A116A117A
TCM129C13A114A116A117A
TCM29C 13A114A
TCM 129C13A114A
TCM29C 13A114A
TCM 129C 13A114A

t CLKSEL is internally set to -5 V for TCM29C16A11A7 and TCM129C16A117A.

e. g., for frame-sync frequency = 9.6 kHz
CLKSEL

CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

-5 vt

=2.4576 MHz

= 1.8528 MHz

= 1.8432 MHz

DEVICE TYPE
TCM29C 13A114A116A117A
TCM 129C13A114A116A117A
TCM29C 13A114A
TCM 129C13A114A
TCM29C 13A114A
TCM129C13A114A

t CLKSEL is internally set to -5 V for TCM29C16A11A7 and TCM129C16A117A.

Corner frequency at 8-kHz frame-sync frequency = 3 kHz
Therefore, the corner frequency = (3/8) x (frame-sync frequency for nonstandard frame sync).

~TEXAS

INSTRUMENTS
2-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D- AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
0.15 dB

0.15 dB
Q)

iii

(/).

"c
"c.
Q)
~

Typical Filter
Transfer Function

-1

"
J:
...

3400 Hz

-10

-20

-30

-40

-50

'iij
(!)

.s
Q)

a:
c

'iij
(!)

-60~~--~~~~~~~------~--~--~~~~~~----~--~~-u~~~~-60

100

10k

f - Frequency - Hz

Figure 1. Transfer Characteristics of the Transmit Filter

·.TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-39

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

+
0.15 dB

3000 HZ

'C
CD
'C
C

ca
a.
)(

w
-1

-1

.a
'C

I
N

....

c
16
CJ

>
~

-10

-14dB
4000 Hz

c
16
CJ

-20

-30

-40

~~~------~---~~~~~~~------~~~~~~~~~-50

100

1k
f - Frequency - Hz

NOTE A: This is a typical transfer function of the receive filter component.

Figure 2. Transfer Characteristics of the Receive Filter

~TEXAS

2-40

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10 k

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

14----------- Time-Slot 1 - - - - - - - - - - - - - . t
CLKX

--.!/

td(FSXr+I
FSX Input
(nonslgnallng
frames)

FSX Input
~
(slgnallng};o
frames) ---../

I
I

---+i !+- td(FSX) 1 r
'\

'-----11-------------...:......;.-------

14- td(FSX)

~\...

td(FSX)

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

FRAME SYNCHRONIZATION TIMING
! + - - - - - - - - - - - T l m e - S l o t N ----------~

TSX Output
tsu(SIGX)

-1

--'X

SIGX Input _ _ _ _ _ _ _ _ _ _ _
D_on_'t_C_a_re_ _ _ _ _ _ _ _

tpd5

I
!.-Valid

--+j

r:---

If/
I(

-.I j4- th(SIGX)

Don't Care

OUTPUT TIMING

t Bit 1 .. MSB =sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 .. LSB .. least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.

Figure 3. Transmit Timing (Fixed-Data Rate)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-41

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
~----------Tlme-Slot

CLKR

---------------+1

i+-

-tI

FSR tcf(FSR)-.!
i+-td(FSR) tr-+l
14- tw(CLK)
(nonslgnallng . . • }:
I
~: tc(CLK)
frames)
I
FSR
~ j4- td(FSR) I
~ ~td(FSR)
(signaling
frames)
-./
'""-- - - - - - - - - - - - - - - - - - - - - - FRAME SYNCHRONIZATION TIMING

I
-./1

'III,'+.--___.f-----------------------I
\L

1 4 - - - - - - - - - - - - T l m e - S l o t N ----------~
CLKR

PCMIN
Bit 1t
Valid

Blt2
Valid

Blt3
Valid

Bit 4
Valid

Bit 5
Valid

Bit 6
Valid

Bit 7
Valid

Bit st
Valid

I
I

SIGR Output _ _ _ _ _ _ _ _ _ _ _ _ _V_a_lId_ _ _ _ _ _ _ _ _ _ _ _ _ _~
INPUT TIMING

t Bit 1 .. MSB .. sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.

Figure 4. Receive Timing (Flxed-Oata Rate)

2-42

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

Figure 5. Transmit Timing (Variable-Data Rate)
FSR

DCLKR

CLKR

PCM IN

Don't Care
Bit2

Bit 3

Bit4

Bit 5

Bit6

Bit7

Figure 6. Receive Timing (Variable-Data Rate)

t Bit 1 =MSB =sign bit and is clocked in first on PCM IN or clocked out first on PCM OUT. Bit 8 =LSB =least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: All timing parameters are referenced to VIH and VIL except tpd8 and tpd9, which references the high-impedance state.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-43

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION

system reliability and design considerations
General TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A, TCM129C13A, TCM129C14A,
TCM129C16A, and TCM129C17A system reliability and design considerations are described in the following
paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM29CxxA and TCM129CxxA devices are heavily protected against latch-up, it is still
possible to cause latch-up under certain conditions in which excess current is forced into or out of one or more
terminals. Latch-up can occur when the positive supply voltage drops momentarily below ground, when the
negative supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after
power has been applied but before the ground is connected. This can happen if the device is hot-inserted into
a card with the power applied, or if the device is mounted on a card that has an edge connector, and the card
is hot-inserted into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V -1 N5711 or equivalent), between
each power supply and GND (see Figure 7). If it is possible that a TCM29CxxA- orTCM129CxxA-equipped card
that has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that
the ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.

device power-up sequence
Latch-Up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.

Ensure no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply Ves (most negative voltage).

Apply

Vee

(most positive voltage).

Force a power down condition in the device.

Connect clocks.

Release the power-down condition.

Apply FSX and/or FXR synchronization pulses.

Apply signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

•
TEXAS
INSTRUMENTS
2-44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
SCTS030D- AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC

DGND

Vee
Figure 7. Diode Configuration for Latch-Up Protection Circuitry
internal sequencing
On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for
approximately fourframes (500 Ils) after power up or application of VSS or Vee. After this delay, PCM OUT, TSX,
and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Therefore, valid
digital information, such as on/off hook detection, is available almost immediately, while analog information is
available after some delay.
On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power up
or application of Vss or Vee. SIGR remains low until it is updated by a signalling frame.
To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance state approximately
20 Ils after an interruption of CLKX. SIGR is held low approximately 20 Ils after an interruption of CLKR. These
interruptions could possibly occur with some kind of fault condition.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PON. In the absence of a signal, PON is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced 15 mW.
Three standby modes give the user the options of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is
held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the
entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for
power-down and standby procedures.

Table 1. Power-Down and Standby Procedures
DEVICE STATUS
Power down
Entire device on standby
Only transmit on standby
Only receive on standby

TYPICAL POWER
CONSUMPTION

PROCEDURE
PDN low
FSX and FSR are low
FSX is low,

FSR is high

FSR is low,

FSX is high

DIGITAL OUTPUT STATUS

3mW

TSX and PCM OUT are in the high-impedance state;
SIGR goes low within 10 Ils.

3mW

TSX and PCM OUT are in the high-impedance state;
SIGR goes low within 300 ms.

40mW

TSX and PCM OUT are placed in the high-impedance
state within 300 ms.

30mW

SIGR is placed in the high-impedance state within 300 ms.

•
TEXAS
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2-45

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION

fixed-data-rate timing (see Figure 8)
Fixed-data-rate timing is selected by connecting DCLKR to Vss and uses master clocks CLKX and CLKR,
frame-synchronizer clocks FSX and FSR, and the output TSX. FSX and FSR are 8-kHz inputs that set the
sampling frequency and distinguish between signaling and nonsignaling frames by their pulse durations. A
frame- synchronization pulse one master-clock period long designates a nonsignaling frame, while a
double-length sync pulse enables the signaling function (TCM12914A and TCM29C14A only). Data is
transmitted on PCM OUT on the first eight positive transitions of CLKX following the rising edge of FSX. Data
is received on PCM IN on the first eight falling edges of CLKR following FSR. A digital-to-analog (D/A)
conversion is performed on received digital word, and the resulting analog sample is held on an internal
sample-and-hold capacitor until transferred to the receive filter.
The clock-selection terminal (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM29C13A,
TCM29C14A, TCM129C13A, and TCM129C14A only). The TCM29C13A, TCM29C14A, TCM129C13A, and
TCM129C14A fixed-data-rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or2.048 MHz. The
TCM29C16A, TCM29C17A, TCM129C16A, and TCM129C17A fixed-data-rate mode operates at 2.048 MHz
only.

----*

!4----

1921193/256

1
Other
I~
TS1X
~I
1
Time Slots
I
~TS1X--~
CLKX~~
L1 2 3 4 5 6 7 a
12345
192/193/256
Transmit Signal Frame
FSX -.II
',',
'j~L....-_ _ _ _ _ _ __
1

1l1li

878a SIGX
PCMOUT=~

x x x x x x x

81 828384858687 8a

TSX~

81 82838485861

~',

',',,!

SIGX-------------~t------------\l-->C--------------~T_----__I------\T_-

Don't Care

fl
JI}-I- - -

I~ I

/ x
Valid

Don't Care

-,1--

192/193/256
I~

!4---1

Other
Time Slots

--.!.

~TS1R
~I
I
~TS1R----.!
CLKR~~
L1 2 3 4 5 6 7 a 9
12345
192/193/256
Receive Signal Frame
FSR -.II
',',
'j~L....-_ _ _ _ _ _ __
SIGR
PCMIN-~---------------~===

~GR

~
Previous Value

Figure 8. Signaling Timing (Fixed-Data Rate Only)

~TEXAS

INSTRUMENTS
2-46

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

New Value

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION
variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to Vss. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 2.048 MHz. Master clocks in the TCM129C13A, TCM129C14A, TCM29C13A, and TCM29C14A are
restricted to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing
mode. The master clock for the TCM129C16A, TCM129C17 A, TCM29C16A, and TCM29C17 A is restricted to
2.048 MHz.
When the FSXfTSXE is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSRfTSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
The transmitted PCM word is repeated in all remaining time slots in the 125-/.1s frame as long as DCLKX is pulsed
and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than
once per frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the
fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling
frame.

signaling
The TCM29C14A (only) provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are independent of each other and are selected by a double-width frame-sync pulse on the
appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for the least
significant bit (LSB) of the encoded PCM word. In a receive signaling frame, the codec decodes the seven most
significant bits in accordance with CCITT G.733 recommendations and outputs the logical state of the LSB on
SIGR until it is updated in the next signaling frame. Timing relationships for signaling operations are shown in
Figure 8. The signaling path is used to transmit digital signaling information such as ring control, rotary dial
pulses, and off-hook and disconnect supervision. The voice path is used to transmit prerecorded messages as
well as the call progress tones: dial tone, ring-back tone, busy tone, and reorder tone.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-47

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION

analog loopback
A distinctive feature of the TCM29C14A and TCM 129C14A is the analog loopback capability. With this feature,
the user can test the line circuit remotely by comparing the signals sent into the receive channel (PCM IN) with
those generated on the transmit channel (PCM OUT). The test is accomplished by sending a control signal that
internally connects the analog input and output ports. When ANLG LOOP is TTL high, the receive output
(PWRO+) is internally connected to ANLG IN+, GSR is internally connected to PWRO-, and ANLG IN- is
internally connected to GSX (see Figure 8).
r~-------------------AN~loQp'

I
I
Transmit
Voice

ANLG IN-

GSX

I
I

b;
I
I

PWRO+
PWRO-

b.:

I
______________ I
IL _ _ _ _ _ _ _ _ _ _ _GSR

PCM OUT
Digitized PCM
Loopback
Response

PCMIN
Digitized PCM
Test Tone

Figure 9. TCM29C14A and TCM129C14A Analog Loopback Configuration
Due to the difference in the transmit and receive transmission levels, a O-dBmO code into PCM IN emerges from
PCM OUT as a 3-dBmO code, an implicit gain of 3 dB. Because of this, the maximum signal that can be tested
by analog loopback is 0 dBmO.

precision voltage references
Voltage references that determine the gain dynamic range characteristics of the device are generated internally.
No external components are required to provide the voltage references. A difference in subsurface charge
density between two suitably implanted MOS device is used to derive a temperature- and bias-stable reference
voltage, which are calibrated during the manufacturing process. Separate references are supplied to the
transmit and receive sections, and each is calibrated independently. Each reference value is then further
trimmed in the gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically
±O.04 dB can be achieved in absolute gain for each half channel, providing the user a significant margin to
compensate for error in other system components.

conversion laws
The TCM29C13A, TCM29C14A, TCM129C13A, and TCM129C14A provide pin-selectable Il-Iaw operation as
specified by CCITT G.711 recommendation. A-law operation is selected when ASEL is connected to VBB, and
Il-Iaw operation is selected by connecting ASEL to Vee or GND. Signaling is not allowed during A-law operation.
If Il-Iaw operation is selected, SIGX is a TTL-level input that can be used in the fixed-data-rate timing mode to
modify the LSB of the PCM output is signaling frames.
Ths TCM29C16A and TCM129C16A are Il-Iaw only; the TCM29C17A and TCM129C17A are A-law only.

•
TEXAS
INSTRUMENTS
2-48

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17 A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CO DEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION

transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kn in parallel with less than 50 pF. The input signal on ANLG IN+ can be either ac or dc coupled. The input
operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing filter section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the 'necessary antialiasing function for the
switched-capacitor section of the transmit filter.
The pass-band section provides flatness and stop-band attenuation that fulfills the AT&T 03/04 channel bank
transmission specification and CCITT recommendation G. 712. The device specifications meet or exceed digital
class 5 central office switching-systems requirements.
A high-pass section configuration has been chosen to reject low-frequency noise from 50-Hz and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation
at 200 Hz. This feature allows the use of low-cost transformer hybrids without external components.

receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T
03/04 specification and CCITT recommendation G.712. The filter contains the required compensation for the
(sin x)/x response of such decoders.

~TEXAS '
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-49

TCM29C13A, TCM29C14A, TCM29C16A, TCM29C17A,
TCM129C13A, TCM129C14A, TCM129C16A, TCM129C17 A
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
SCTS030D - AUGUST 1989 - REVISED JULY 1996

PRINCIPLES OF OPERATION
receive output power amplifiers
A balanced-output amplifier is provided to allow maximum flexibility in output configuration. Either of the two
outputs can be used single ended (Le., referenced to ANLG GND) to drive single-ended loads. Alternatively,
the differential output directly drives a bridged load. The output stage is capable of driving loads as low as 300-0
single-ended to a level of 12 dBm or 600 0 differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulation of GSR. GSR
is internally connected to an analog gain-setting network. When GSR is connected to PWRO-, the receive level
is maximum. When GSR is connected to PWRO+, the level is minimum. The output transmission level is
adjusted between 0 and -12 dB as GSR is adjusted (with an adjustable resistor) between PWRO+ and PWRO-.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(Le., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).

APPLICATION INFORMATION

output gain-set design considerations (see Figure 9)
PWRO+ and PWRO- are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at PWRO+
Vo_at PWROVo = Vo+ - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to the GSR input.
A value greater than 10 kQ and less than 100 kQ for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and RL sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital milliwatt output response (VA = 3.006 Vrms).
VOD=AeVA
1 + (A1/A2)
where A = 4 + (A1/A2)
2

lI
<

A1 <>
4

V)D

PWAO+

GSA

A2?
3

TCM29C13A
TCM29C14A
TCM29C16A
TCM29C17A
TCM129C13A
TCM129C14A
TCM129C16A
TCM129C17A

PWAO-

....

vo-

Digital Milliwatt
Sequence Per
CCITT G. 711

Figure 10. Gain-Setting Configuration

~TEXAS

2-50

PCMIN

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021C -AUGUST 1987 -REVISED JULY 1996

•

Reliable Silicon-Gate CMOS Technology

•

Low Power Consumption
- Operating Mode ... 80 mW
- Power-Down Mode ... 5 mW

(TOP VIEW)

•
•

ll-Law Coding
Excellent Power-Supply Rejection Ratio
Over Frequency Range of 0 Hz to 50 kHz

No External Components Needed for
Sample, Hold, and Autozero Functions
Precision Internal Voltage Reference

o
•

ow OR N PACKAGE

VBB
PWRO+
PWROPDN
DClKR
PCM IN
FSRfTSRE
DGTl GND

Single Chip Contains AID, DIA, and
Associated Filters

VCC
GSX
ANlGIN
ANlG GND
TSXlDClKX
PCM OUT
FSXfTSXE
ClK

FEATURES TABLE
Number of Pins:
16

description
The TCM29C18, TCM29C19, TCM129C18, and
TCM129C19 are low-cost single-chip PCM
codecs (pulse-code-modulated encoders and
decoders) and PCM line filters. These devices
incorporate both the AID and D/A functions, an
antialiasing filter (AID), and a smoothing filter
(D/A). They are ideal for use with the TMS320
DSP family members, particularly those featuring
a serial port such as the TMS32020, TMS32011,
and TMS320C25.

Coding law:
Il-law
Variable Mode:
64 kHz to 2.048 MHz
Fixed Mode:
2.048 MHz (TCM29C18, TCM129C18),
1.536 MHz (TCM29C19, TCM129C19)
8-Bit Resolution
12-Bit Dynamic Range

Primary applications include:
•
•
•

Digital encryption systems
Digital voice-band data storage systems
Digital signal processing

These devices are designed to perform encoding of analog input signals (AID conversion) and decoding of
digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a digital
Signal processing system. Both devices also provide band-pass filtering of the analog signals prior to encoding,
and smoothing after decoding.
The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of O°C to 70°C.
The TCM129C18 and TCM129C19 are characterized for operation over the temperature range of
-40°C to 85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

~TEXAS

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2-51

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

functional block diagram

1-------------------------------------1
I

I
I
I

141
ANLG IN

15
GSX

Transmit Section

ilter

I
I
I

111 PCM OUT
Sample
and Hold
and DAC

Comparator

Successive
Approximation

Output
Register

I
I

to-Digital
Control
Logic

I
I
I
I
I
I
I
I
I

I
I
I
I

12 TSX/
DCLKX

1 10 FSXlTSXE
9 CLK

I
.----------------------- -T----------,---I
I

PWRO+

Control Section

Receive Section

I
I
I

L
Digitalto-Analog
Control
Logic

PWRO-

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

NO.

ANLGIN

ANLG GND

DESCRIPTION

I/O

Inverting analog input. Input to uncommitted transmit operational amplifier.
Analog ground return for all voice circuits. Not internally connected to DGTL GND.

CLK

Master clock and data clock input for the fixed-data-rate mode. Master (filter) clock only for variable-data-rate
mode. This clock is used for both the transmit and receive sections.

DCLKR

Fixed data rate mode-variable data rate mode select. When connected to VBB, the device operates in the
fixed-data-rate mode. When DCLKR is not connected to VBB, the device operates in the variable-data-rate mode
and DCLKR becomes the receive data clock, which operates at frequencies from 64 kHz to 2.048 MHz.
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.

DGTLGND

FSRfTSRE

Frame-synchronization clock input/time-slot enable for the receive channel. In the variable-data-rate mode, this
signal must remain high for the duration of the time slot. The receive channel enters the standby state when FSR
is TIL low for 30 ms.

FSXfTSXE

Frame-synchronization clock input/time-slot enable for transmit channel. Operated independently of, but in an
analogous manner to FSRfTSRE. The transmit channel enters the standby state when FSX is low for 300 ms.

GSX

Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit
filter.

Receive PCM input. PCM data is clocked in on eight consecutive negative transitions of the receive data clock,
which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.

Transmit PCM output. PCM data is clocked out of this output on eight consecutive positive transition of the transmit
data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.

PDN

Power-down select. On the TCM29C18 and the TCM129C18, the device is inactive with a TIL low-level input and
active with a TIL high-level input to the terminal. On the TCM29C19 and the TCM129C19, this terminal must be
connected to a TIL high level.

PWRO+

Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or high-impedance loads directly
in either a differential or single-ended configuration.

PCMIN
PCMOUT

PWROTSXlDCLKX

Inverting output of power amplifier-functionally identical to PWRO+.

110

Transmit channel time-slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain
output to be used as an enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the
transmit data clock, which operates at TIL levels from 64 kHz to 2.048 MHz.

VBB

VCC

Negative supply voltage, -5 V ±5%.
Positive supply voltage, 5 V ±5%.

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2-53

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 15 V
Output voltage range, Va .......................................................... -0.3 V to 15 V
Input voltage range, VI ............................................................. -0.3 V to 15 V
Digital ground voltage range ........................................................ -0.3 V to 15 V
Operating free-air temperature range, TA: TCM29C18, TCM29C19 ....................... O°C to 70 0 e
TCM129C18, TCM129C19 .................. -40°C to 85°e
Storage temperature range, Tstg ........................................ ; .......... - 65°e to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

recommended operating conditions (see Note 2)
VCC

Supply voltage (see Note 3)

VSS

Supply voltage

MIN

NOM

MAX

UNIT

4.75

5.25

-4.75

-5

-5.25

DGTL GND voltage with respect to ANLG GND
VIH

High-level input voltage, all inputs except ANLG IN

VIL

Low-level input voltage, all inputs except ANLG IN

VI(PP)

Peak-to-peak analog input voltage (see Note 4)

Load resistance

Load capacitance

Operating free-air temperature

NOTES:

GSX

2.2

V
0.8
4.2

PWRO+ and/or PWRO-

PWRO+ and/or PWROTCM29C18 or TCM29C19
TCM129C18 or TCM129C19

300

GSX

100
0

-40

°C

2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.
.
3. Voltages at analog inputs and outputs and VCC and VSS terminals are with respectto ANLG GND. All other voltages are referenced
to DGTL GND unless otherwise noted.
4. Analog inputs signals that exceed 4.2 V peak to peak may contribute to clipping and preclude correct AID conversion. The digital
code representing values higher than 4.2 V is 10000000. For values more negative than 4.2 V, the code is 0000000 .

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, fOCLK

=2.048 MHz, outputs not loaded
TEST CONDITIONS

PARAMETER

TCM29Cxx
MIN

Operating
ICC

Supply current from VCC

Standby

FSX or FSR at VIL after 300 ms

Power down

PDN at VIL after 10 lis

Operating
ISS

Supply current from VSS

Standby

FSX or FSR at VIL after 300 ms

Power down

PDN at VIL after 10 lis

TCM129Cxx

MAX

MIN

MAX

1.2

1.5

1.2

-10

-14

-1.2

-1.5

-1

-1.2

UNIT

digital interface
PARAMETER
VOH

TEST CONDITIONS

High-level output voltage, PCM OUT

MIN

IOH =-9.6mA

2.4

IOH =-0.1 mA

3.5

VOL

Low-level output voltage, TSX

IOL=3.2 mA

IIH

High-level input current, any digital input

VI = 2.2 V to VCC
VI = 0 to 0.8 V

TVPt

MAX

UNIT
V

IlL

Low-level input current, any digital input

Input capacitance

Output capacitance

0.5

IiA

pF
pF

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C.

~TEXAS

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2-55

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

transmit side (AID) characteristics
PARAMETER

TEST CONDITIONS

Input offset voltage at ANLG IN

VI =-2.17 V to 2.17 V

Input offset current at ANLG IN

VI = -2.17 V to 2.17 V

Input bias current

VI =-2.17 V to 2.17 V

MIN

MAX

UNIT

±25

pA
±100

Open-loop voltage amplification at GSX

5000
1

Unity-gain bandwidth at GSX
Input resistance at ANLG IN

MHz

10
~

dBmO input level

Gain-tracking error with sinusoidal input
(see Notes 5, 6, and 7)

-3

Transmit gain tolerance

Noise

Ref max output level: 200 Hz to 3 kHz

Supply-voltage rejection ratio,
VCCto VBB

f 0 Hz to 30 kHz (measured at PCM OUT) idle channel,
Supply signal 200 mV peak to peak

Crosstalk attenuation, transmit to
receive (single ended)

ANLG IN 0 dBm,
PCM IN lowest decode level,

Signal-to-distortion ratio, sinusoidal
input (see Note 8)

-30 dBmO > ANLG IN

-40 dBmO,

-40 dBmO

-40 dBmO > ANLG IN

-45 dBmO

-40> dBmO input level ~ -50 dBmO,

=1.06 V,

±0.5

=-10 dBmO

±25

Ref level
f

=1.02 kHz

=
=

Fixed data rate,
Input to ANLG IN

=1 kHz at 0 dB

Mil

Ref level = -10 dBmO

f 1 kHz unity gain,
Measured at PWRO +

o dBmO ~ ANLG IN ~ -30 dBmO

Absolute delay time to PCM OUT

TYPt

0.95

1.19

Vrms

-70

-20

fCLKX

=2.048 MHz,

245

Ils

t All typical values are at VBB =-5 V, VCC =5 V, and TA =25°C.
NOTES:

5. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference point
of the channel under test. This corresponds to an analog signal input of 1.064 Vrms or an output of 1.503 Vrms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a O-dBmO, 1020-Hz sine wave
through an ideal encoder.
7. The TCM29C18, TCM29C19, TCM129C18, and TCM129C19 are internally connected to set PWRO+ and PWRO-to 0 dBM. All
output levels are (sin x)/x corrected.
8. CCITT G.712 - Method 2.

•
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TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

receive side (D/A) characteristics (see Note 9)
PARAMETER
Output offset voltage PWRO + and
PWRO- (single ended)

TEST CONDITIONS

MIN

Relative to ANlG GND

Output resistance at PWRO+ and
PWRO-

1
-3 dBmO ~ input level

Gain-tracking error with sinusoidal input
(see Notes 5, 6, and 7)

-40 dBmO > input level

MAX

UNIT

±200

-40 dBmO,

Ref level = -10 dBmO

±0.5

Ref level = -10 dBmO

±25

-50 dBmO,

Receive gain tolerance

VI = 1.06 V,

Noise

Ref max output level: 200 Hz to 3 kHz

Supply voltage rejection ratio,
VCC to VBB (single-ended)

Idle channel,
f = 0 Hz to 30 kHz,
Supply signal = 200 mV peak to peak, Narrow band,
Frequency at PWRO+

Crosstalk attenuation, receive to
transmit (single ended)
Signal-to-distortion ratio, sinusoidal
input (see Note 8)

-30 dBmO > ANlG IN

-40 dBmO

-40 dBmO > ANlG IN

-45 dBmO

Absolute delay time to PWRO+

TYPt

f = 1.02 kHz

1.34

Q
dB

1.69

Vrms

-70

-20

PCM IN = 0 dB,
Frequency = 1 kHz at PCM OUT

o dBmO ~ ANlG IN ~ -30 dBmO

Fixed data rate,

190

fClKX = 2.048 MHz

Il s

t All typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C.
NOTES:

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN
tc(ClK)

Clock period for ClK (2.048-MHz systems)

tr,tf

Rise and fall times for ClK

tw(CLK)

Pulse duration for ClK

tw(DClK)

Pulse duration, OClK (fOClK

TYPt

MAX

Clock duty cycle, [tw(ClK)/tc(ClK)l for ClK

220
45%

ns
ns

220

=64 kHz to 2.048 MHz)

UNIT
ns

488

50%

55%

t All typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C.

~TEXAS

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2-57

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021C -AUGUST 1987 -REVISED JULY 1996

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
Frame-sync delay time

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
PARAMETER

td(FSR)

Frame-sync delay time

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
PARAMETER

MIN

UNIT

MAX

td(TSDX)

Delay time, time-slot from DCLKX (see Note 10)

140 td(DCLKX)-140

td(FSX)

Delay time, frame sync.

100

tc(DCLKX)

Pulse duration, DCLKX

488

t c (CLK)-100

15620

NOTE 10: tFSLX minimum requirement overrides the td(TSDX) maximum requirement for 64-kHz operation.

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
PARAMETER

MIN

MAX

UNIT

td(TSDR)

Delay time, time slot from DCLKR (see Note 11)

140

t w (DCLKR)-140

td(FSR)

Delay time, frame sync T C(CLK)

100

t c (CLK)-100

tsu(PCM IN)

Setup time before bit 7 falling edge

th(PCM IN)

Hold time after bit 8 falling edge

tw(DCLKR)

Pulse duration, DCLKR

tSER

Time-slot end receive time

488

ns
ns
15620

ns
ns

NOTE 11: tFSLR minimum requirement overrides the tc(TSDR) maximum requirement for 64-kHz operation.

64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode
PARAMETER

TEST CONDITIONS

tFSLX

Transmit frame sync, minimum down time

tFSLR

Receive frame sync, minimum down time

tw(DCLK)

Pulse duration, data clock

=TTL high for remainder of frame
FSR =TTL high for remainder of frame
FSX

MAX

488

~TEXAS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT

1952

ns
10

INSTRUMENTS
2-58

MIN

Ils

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021C -AUGUST 1987 -REVISED JULY 1996

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode
(see timing diagrams)
PARAMETER

MIN

MAX

CL = 0 to 100 pF

145

CL = 0 to 100 pF

145

215

145

190

TEST CONDITIONS

tpd1

From rising edge of transmit clock to bit 1 data valid at PCM OUT
(data enable time on time-slot entry)

tpd2

From rising edge of transmit clock bit n to bit n data valid at PCM OUT
(data valid time)

tpd3

From falling edge of transmit ciock bit 8 to bit 8 Hi-Z at PCM OUT
(data float time on time-slot exit)

CL= 0

tpd4

From riSing edge of transmit clock bit 1 to TSX active (low)
(time-slot enable time)

CL = 0 to 100 pF

tpd5

From falling edge of transmit ciock bit 8 to TSX inactive (high)
(time-slot disable time)

CL=O

UNIT

propagation delay times over recommended ranges of operating conditions, variable-data-rate
mode
PARAMETER
tpd6

From DCLKX

tpd7

From time-slot enable to PCM OUT

tpd8

From time-slot disable to PCM OUT

tpd9

From FSX

TEST CONDITIONS

CL = Oto 100 pF

td(TSDX) = 140 ns

UNIT

MIN

MAX

100

140

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TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
0.2 dB
3300Hz

.!!

til
U
(/)

-g
"C
C

[

><
w

Typical Filter
Transfer Function

-1

I
N

:I:
.lII:

-10

-20

-30

-40

-50

B
I\)

c
"iii
CJ

-60~~

__~__~~~~~~____~~__~__~~~~~~~____~__~~~~-u~~-60
50

100

1k
f - Frequency - Hz

NOTE A: This is a typical transfer function of the receiver filter component.

Figure 1. Transfer Characteristics of the Transmit Filter

•
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10k

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021C-AUGUST 1987 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

0.5 dB
3000 HZ

0.5 dB

CI)

iO
u

C/)

"D
CI)

-1

m
I

1'1:1

)(

-0.5 dB
3000y-:
-2dB
3300 Hz
-3.5 dB
3400 Hz

"D
C

-1

.lII:

,..

ii
c

'iii

"g
CI)

.:!

-10

-20

ex:

c
"iii

"
-25 dB
-30

-30

-40

-50~~~----~----~~~~~~~------~--~~~~-U~~-50

100

10 k

f - Frequency - Hz

NOTE A: This is a typical transfer function of the receive filter component.

Figure 2. Transfer Characteristics of the Receive Filter

•
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2-61

TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

FRAME SYNCHRONIZATION TIMING

ClK

PCM OUT

---t-o(

TSX Output
OUTPUT TIMING
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (lSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.

Figure 3. Transmit Timing (Fixed-Data Rate)

FRAME SYNCHRONIZATION TIMING

Bit 1
Valid

Bit2
Valid

Bit3
Valid

Bit 4
Valid

Bit 5
Valid

Bit6
Valid

Bit 7
Valid

Bit 8
Valid

INPUT TIMING
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT output.
Bit 8 is the least significant bit (lSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT output.

Figure 4. Receive Timing (Fixed-Data Rate)

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TCM29C18, TCM29C19, TCM129C18, TCM129C19
ANALOG INTERFACE FOR DSP
SCTS021 C -AUGUST 1987 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

1
1 input level ~ -50 dBmO

±1.5

3 ~ input level ~ -40 dBmO

±0.5

-40 > input level ~ -50 dBmO

±1.5

UNIT
dB

noise over recommended ranges of supply voltage and operating free-air temperature range
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Transmit noise, C-message weighted

ANLG IN+ = ANLG GND,

ANLG IN- = GSX

Transmit noise, psophometrically weighted

ANLG IN+ = ANLG GND,

ANLG IN- = GSX

-72

dBmOp

Receive noise, C-message-weighted quiet code

PCM IN = 11111111 (11-law),
Measured at PWRO+

PCM IN = 10101010 (A-law),

dBrnCO

Receive noise, psophometrically weighted

PCM = lowest positive decode level

-79

dBmOp

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dBrnCO

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

power-supply rejection and crosstalk attenuation over recommended ranges of supply voltage
and operating free-air temperature
PARAMETER

VCC supply-voltage rejection ratio,
transmit channel
VBB supply-voltage rejection ratio,
transmit channel
VCC supply-voltage rejection ratio, receive
channel (single ended)
VBB supply-voltage rejection ratio, receive
channel (single ended)

TEST CONDITIONS

o $f < 30 kHz
30 $f < 50 kHz

MIN

TYPt

Idle channel,
Supply signal =200 mV peak to peak,
f measured at PCM OUT

-30

Idle channel,
Supply signal = 200 mV peak to peak,
f measured at PCM OUT

-30

Idle channel,
Supply signal =200 mV peak to peak,
f measured at PWRO+

-20

Idle channel,
Supply Signal = 200 mV peak to peak,
Narrow-band,
f measured at PWRO+

-20

MAX

UNIT

dB
-45
dB
-55
dB
-45
dB
-45

Crosstalk attenuation, transmit to receive (single ended)

ANLG IN+ ~ 0 dBmO,
f = 1.02 kHz,
Unity gain,
PCM IN = lowest decode level,
Measured at PWRO+

Crosstalk attenuation, receive to transmit (single ended)

PCM IN = 0 dBmO,
Measured at PCM OUT

= 1.02 kHz,

t All typical values are at VBB =-5 V, VCC = 5 V, and TA =25°C.

distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER

TEST CONDITIONS

Transmit signal-to-distortion ratio, sinusoidal input
(CCITT G.712 - Method 2)

Receive signal-to-distortion ratio, sinusoidal input
(CCITT G.712 - Method 2)

MIN

o ~ ANLG IN+ ~ -30 dBmO

-30 > ANLG IN+ ~ -40 dBmO

-40> ANLG IN+ ~ -45 dBmO

o ~ ANLG IN+ ~-30 dBmO

-30> ANLG IN+

-40 dBmO

-40> ANLG IN+

-45 dBmO

TYPt

MAX

UNIT

Transmit single-frequency distortion products

AT&T Advisory #64 (3.8),

Input signal = 0 dBmO

-40

dBmO

Receive single-frequency distortion products

AT&T Advisory #64 (3.8),

Input signal = 0 dBmO

-46

dBmO

t All typical values are at VBB =-5 V, VCC = 5 V, and TA =25°C.
transmit filter transfer over recommended ranges of supply voltage and operating free-air
temperature, fOCLK 4.096 MHz, FSXlFSR 16 kHz (see Figure 1)

PARAMETER

TEST CONDITIONS

50 Hz

Input amplifier set for unity gain,
Noninverting maximum gain output,
Input signal at ANLG IN+ is 0 dBmO

MAX

-1

0.5

-0.5

0.5

6.5 kHz

-4

0.3

6.8 kHz

-6

200 Hz
Gain relative to gain at 1.02 kHz

MIN

-10

300 Hz to 6 kHz

8 kHz

-12

9 kHz and above

-30

UNIT

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2-75

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A-AUGUST 1989 -REVISED JULY 1996

receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER

TEST CONDITIONS
Below 200 Hz

Input signal at PCM IN is 0 dBmO

MAX

-2

0,5

-1

0,5

-0,5

0,5

6,6 kHz

-4

0,3

6,8 kHz

-6

200 Hz
300 Hz to 6 kHz
Gain relative to gain at 1,02 kHz

MIN

8 kHz

-12

9,2 kHz and above

-30

UNIT

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 3)
MIN
tc(CLK)

Clock period, for CLKX, CLKR (2,048-MHz systems)

tr,tf

Rise and fall times for CLKX and CLKR

tw(CLK)

Pulse duration for CLKX and CLKR (see Note 7)

tw(DCLK)

Pulse duration, DCLK (fDCLK

TYPt

=64 kHz to 2,048 MHz) (see Note 7)

110

ns
ns

110
45%

UNIT
ns

Clock duty cycle, [tw(CLK)/tc(CLK)l for CLKX and CLKR

MAX

244

ns
50%

55%

t All typical values are at VBB =-5 V, VCC =5 V, and TA =25°C,
NOTE 7: FSX CLK must be phase locked with CLKX, FSR CLK must be phase locked with CLKR,

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
PARAMETER
Frame-sync delay time

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
PARAMETER
Frame-sync delay time

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
PARAMETER

MIN

MAX

UNIT

td(TSDX)

Time-slot delay time from DCLKX

td(DCLKX)-60

td(FSX)

Frame-sync delay time

t c (CLK)-60

tc(DCLKX)

Clock period for DCLKX

244

15620

~TEXAS

INSTRUMENTS
2-76

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, variable-data-rate mode (see Figure 6)
MAX

UNIT

td(TSDR)

Time-slot delay time from DCLKR

PARAMETER

MIN
60

td(DCLKR)-140

td(FSR)

Frame-sync delay time

t c (CLK)-60

tsu(PCM IN)

Setup time before bit 7 falling edge

th(PCM IN)

Hold time after bit 8 falling edge

tc(DCLKR)

Data clock frequency

tSER

Time-slot end receive time

244

ns
ns
15620

ns
ns

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see
Figure 3)
MIN

MAX

CL = 0 to 100 pF

From rising edge of transmit clock bit n to bit data valid at PCM OUT
(data valid time)

CL = 0 to 100 pF

tpd3

From falling edge of transmit clock bit 8 to bit 8 Hi-Z at PCM OUT
(data float time on time-slot exit) (see Note 8)

CL=O

215

tpd4

From rising edge of transmit clock bit 1 to TSX active (low)
(time slot enable time)

CL = 0 to 100 pF

tpd5

From falling edge of transmit clock bit 8 to TSX inactive (high)
(time-slot disable time) (see Note 8)

CL=O

190

PARAMETER

TEST CONDITIONS

tpd1

From rising edge of transmit clock to bit 1 data valid at PCM OUT
(data enable time on time-slot entry) (see Note 8)

tpd2

UNIT

NOTE 8: Timing parameters tpd1. tpd3. and tpd5 are referenced to the high-impedance state.

propagation delay times over recommended ranges of operating conditions, variable-data-rate
mode (see Note 9 and Figure 5)
PARAMETER

TEST CONDITIONS

tpd7

Data delay time from DCLKX

tpd8

Data delay from time-slot enable to PCM OUT

tpd9

Data delay from time-slot disable to PCM OUT

tpd10

Data delay time from FSX

CL = 0 to 100 pF

td(TSDX) = 80 ns

MIN

MAX

UNIT
ns

NOTE 9: Timing parameters tpd8 and tpd9 are referenced to the high-impedance state.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-77

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

ClK, ClKR, and ClKX selection requirements for DSP-based applications
ClK, ClKR, and ClKX must be selected as follows:
CLKSEL PIN

CLK,CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

=(256) x (frame-sync frequency)
=(193) x (frame-sync frequency)
=(192) x (frame-sync frequency)

-5V
OV
5V

e.g., for frame-sync frequency = 16 kHz
CLKSEL PIN
-5V
OV
5V

CLK,CLKR,CLKX
(BETWEEN 1 MHz to 3 MHz)

=4.096 MHz
=3.088 MHz
=3.072 MHz

•
TEXAS
INSTRUMENTS
2-78

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM29C23, TCM129C23
.VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A- AUGUST 1989 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

CIl

iii
u

(/)

"C
CIl
"C

r:I
Co
)(

w
-5

-5

6800 Hz
III

I
N

,..

c
.;

-10

C!J

.s
CIl

:;
Gi

-20

.;c
C!J

-30

-30
-30d8
9000 Hz

-40

-50

-60~~--~~~~~~~----

____~~~~~~~~____~______~~~~-60

100

10 k

f - Frequency - Hz
NOTE A: CLKR/CLKX =4.096 MHz

Figure 1. Transfer Characteristics of the Transmit Filter

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-79

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A-AUGUST 1989-REVISEDJULY 1996

PARAMETER MEASUREMENT INFORMATION

OdB
6800 Hz
S

0.3 dB
6800 Hz
-O.S dB
6000 Hz

O.SdB
300 Hz

O.SdB
200 Hz
0

S
CIl

iij

t/)

-1 dB
200 Hz

-4dB
-S

-6 dB
6800 Hz

"I
N

:I:
oX

,...
-;

c
.;
CJ

.s
CIl

-10

-20

-30

-40

~~~----~----~~~~~~--------~~--~~~~~-SO

100

1k
f - Frequency - Hz

NOTE A: CLKR/CLKX =4.096 MHz

Figure 2. Transfer Characteristics of the Receive Filter

~TEXAS

INSTRUMENTS
2-80

CIS

><
w

-O.S dB
6000 Hz

-O.S dB
300 Hz

-S

>
~
Qj
c::
.;c

"c
"

CIl

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10 k

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

14------------

Time-Slot 1 - - - - - - - - - - - - - + 1

FSXlnput
(nonsignaling
frames)

-,~

tc(CLK)

TSX Output

t Bit 1 = MSB =sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB =least significant bit and is clocked in last
on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.

Figure 3. Transmit Timing (Fixed-Data Rate)

CLKR

FSR Input
(nonsignaling
frames)

Bit 1t
Valid

Bit 2
Valid

Bit 3
Valid

Bit4
Valid

Bit 5
Valid

Bit6
Valid

Bit7
Valid

Bit at
Valid

t Bit 1 = MSB =sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last
on PCM IN or is clocked outlast on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level is
indicated.

Figure 4. Receive Timing (Fixed-Data Rate)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-81

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
I~

4:/

FSX

1~ 1 ~I

J / Hl'

r--'\

'--J

r--'\

'--J

,~
I~

d8~~

I i

,'\

'-J

'--J

r--'\

'--J

r--'\

'-J

1
1

8 ,

r--

'-+-'

'--J

/1\ ,r-\ ,'\ ,'\ /', ,'\

,'\

'-J

~ t p d10

PCM OUT

r--'\

/',

'-J

r--'\

'--J

~ ~ td(FSX)
CLKX

1',-

td(TSDX)

DCLKX

Time Slot

'-J

--.I

,1', /

'-J

tpd9

'-J

Bit 1t

t Bit 1 = MSB = sign bit and locked in first on the PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: IAII timing parameters referenced to VIH and VIL except tpd7 and tpd8' which reference the high-impedance state.

Figure 5. Transmit Timing (Variable-Data-Rate)

FSR

CLKR

td(TSDR)

d r::\ ~ r:\ r:\ r:\ r:\ r:\ r~1~2~3~4~5~6~7~8~

""\

DCLKR

~ ~ td(FSR)
,~ ,'\

'-J

tsu(PCM IN)~
PCMIN

t(SER)~ ~
,r-\\ ltr-\, ,r-\, ,r-\, ,r-\, ,r-\,
,r-\, /

: :

,'\ ,'\1

t-f--

'-J

~ I~ th(PCM IN)

Don't Care
Bit2

Bit3

Bit4

Bit 5

Bit6

Bit 7

Bltst

t Bit 1 = MSB = sign bit and locked in first on the PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: All timing parameters referenced to VIH and VIL except tpd7 and tpd8, which reference the high-impedance state.

Figure 6. Receive Timing (Variable-Data-Rate)

~TEXAS

INSTRUMENTS
2-82

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
TCM29C23, TCM129C23 system reliability and design considerations are described in the following
paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM29C23 and TCM 129C23 are heavily protected against latch-up, it is still possible to cause
latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up
can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage
rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied
but before the ground is connected. This can happen if the device is hot-inserted into a card with the power
applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a
system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between the
power supply and GND (see Figure 7). If it is possible that a TCM29C23- or TCM129C23-equipped card that
has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the
ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.
device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.

Ensure that no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply Vee (most positive voltage).

Force a power down condition in the device.

Connect clocks.

Release the power down condition.

Apply FS synchronization pulses.

Apply the signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-83

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A -AUGUST 1989 -REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC

DGND

Vee
Figure 7. Latch-Up Protection Diode Connection
internal sequencing
On the transmit channel, digital outputs PCM OUT and TSX are held in the high-impedance state for
approximately four frames (500 Ils) after power up or application of V88 or Vee. After this delay, PCM OUT, TSX,
and signaling are functional and occur in the proper time slot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus valid digital
information, such as on/off hook detection, is available almost immediately while analog information is available
after some delay. To further enhance system reliability, PCM OUT and TSX are placed in the high-impedance
state approximately 20 Ils after an interruption of CLKX.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is interally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 5 mW.
Three standby modes give the user the options of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. to place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is high and FSR is
held low. For receive-only operation (transmit section on standby), FSR is high and FSX is held low. When the
entire device is in standby mode, power consumption is reduced to an average of 3 mW. See Table 1 for
power-down and standby procedures.

Table 1. Power-Down and Standby Procedures
DEVICE STATUS
Power down
Entire device on standby
Only transmit on standby
Only receive on standby

PROCEDURE
PDN low
FSX and FSR are low
FSX is low,

FSR is high

FSR is low,

FSX is high

TYPICAL POWER
CONSUMPTION

DIGITAL OUTPUT STATUS

3mW

TSX and peM OUT are in the high-impedance state; SIGR
goes to low within 10 Ils.

3mW

TSX and peM OUT are in the high-impedance state; SIGR
goes to low within 300 ms.

40mW

TSX and peM OUT are placed in the high-impedance state
within 300 ms.

30mW

SIGR is placed in the high-impedance state within 300 ms.

~TEXAS

INSTRUMENTS
2-84

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PRINCIPLES OF OPERATION
fixed-data-rate timing
Fixed-data-rate timing is selected by connecting DCLKR to Vss.lt uses master clocks CLKX and CLKR, framesynchronizer clocks FSX and FSR, and output TSX. FSX and FSR are inputs that set the sampling frequency.
Data is transmitted on PCM OUT on the first eight positive transitions of CLKX following the rising edge of FSX.
Data is received on PCM IN on the first eight falling edges of CLKR following FSX. A digital-to-analog (D/A)
conversion is performed on the received digital word and the resulting analog sample is held on an internal
sample-and-hold capacitor until transferred to the receive filter.

variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to Vss.lt uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 4.096 MHz. The bit clocks must be asynchronous.
When the FSXlTSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSRITSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
The transmitted PCM word will be repeated in all remaining time slots in the frame as long as DCLKX is pulsed
and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than
once per frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the
fixed-data-rate mode because the variable-data-rate mode provides no means with which to specify a signaling
frame.

asynchronous operation
In order to avoid crosstalk problems associated with special interrupt circuits, the design includes separate
digital-to-analog converters and voltage references on the transmit and receive sides to allow completely
independent operation of the two channels. In either timing mode, the master clock, data clock, and time-slot
strobe must be synchronized at the beginning of each frame. Specifically, in the variable-rate mode, the falling
edge of CLKX must occur within td(FSX) ns after the rise of FSX and the falling edge of DCLKX must occur within
tTSDX ns after the rise of FSX. CLKX and DCLKX are synchronized once per frame but may be of different
frequencies. The receive channel operates in a similar manner and is completely independent of the transmit
timing (see Figure 6). This approach requires the provision of two separate master clocks but avoids the use
of a synchronizer, which can cause intermittent data conversion errors.

precision voltage references
Voltage references that determine the gain and dynamic range characteristics of the device are generated
internally. No external components are required to provide the voltage references. A difference in subsurface
charge density between two suitably implanted MaS devices is used to derive a temperature- and bias-stable
reference voltage, which are calibrated during the manufacturing process. Separate references are supplied
to the transmit and receive sections, and each is calibrated independently. Each reference value is then further
trimmed in the gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically
±0.04 dB in absolute gain can be achieved for each half channel, providing the user a significant margin to
compensate for error in other system components .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-85

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

PRINCIPLES OF OPERATION

conversion laws
The TCM29C23 and TCM129C23 provide pin-selectable A-law or Il-Iaw operation as specified by the CCITT
G.711 recommendation. A-law operation is selected when ASEL is connected to VSS. Signaling is not allowed
during A-law operation. Il-Iaw operation is selected by connecting ASEL to Vee or GND.

transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kn in parallel with less than 50 pF. The input Signal on ANLG IN + can be either ac or dc coupled. The input
operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function forthe
switched-capacitor section of the transmit filter.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sampleand-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital
data representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder using the sign bit averaging
technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the
encoder. All dc offset is removed from the encoder input waveform.

receive operation
decoding
The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog
conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold
capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T
03/04 specification and CCITT recommendation G. 712. The filter contains the required compensation for the
(sin x)/x response of such decoders.
receive output power amplifiers
A balanced output amplifier is provided to allow maximum flexibility in output configuration. Either of the two
outputs can be used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively,
the differential output directly drives a bridged load. The output stage is capable of driving loads as low as
300 n single ended to a level of 12 dBm or 600 n differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulating of the GSR
input. GSR is internally connected to an analog gain-setting network. When GSR is connected to PWRO+, the
level is minimum. The output transmission level between 0 and -12 dB as GSR is adjusted (with an adjustable
resistor) between PWRO+ and PWRO-.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).

~TEXAS

INSTRUMENTS
2-86

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029A - AUGUST 1989 -REVISED JULY 1996

APPLICATION INFORMATION

output gain-set design considerations (see Figure 7)
PWRO+ and PWRO- are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at PWRO+
Vo- at PWROVo = VO+ - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap to the GSR input.
A value greater than 10 kQ and less than 100 kQ for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and RL sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
VAD represents the maximum available digital milliwatt output response (VA = 3.06 V rms).
vOD= A. VAD
1 + (R1/R2)
where A = 4 + (R1/R2)
2

Vo+

~
4

VOD

PWRO+

GSR

TCM19C23
TCM129C23

R2~
~r

i
!

PWRO-

PCMIN

VO-

Digital Milliwatt Sequence
Per CCITT G. 711

Figure 8. Gain-Setting Configuration

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-87

2-88

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

•

Complete PCM Codec and Filtering System •
Includes:
Transmit High-Pass and Low-Pass
Filtering
- Receive Low-Pass Filter With (sin x}/x
Correction
- Active RC Noise Filters
- Il-Law Compatible Coder and Decoder
- Internal Precision Voltage Reference
- Serial I/O Interface
- Internal Autozero Circuitry
oil-Law Coding

•

DTAD and DSP Interface Codec

•
•
•
•
•
•

±5-V Operation
Low Operating Power ... 50 mW Typ
Power-Down Standby Mode ... 3 mW Typ
Automatic Power Down
TTL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density

ow OR N PACKAGE
(TOP VIEW)

VBB
ANlG GND
VFRO
VCC
FSR
DR
BClKR/ClKSEl
MClKR/PDN

1 U 16

15
14
13
12
11
10

3
4
5

VFXI+
VFXIGSX
TSX
FSX
DX
BClKX
MClKX

description
The TCM320AC54 is comprised of a single-chip PCM codec (pulse-code-modulated encoder and decoder) and
PCM line filter. This device provides all the functions required to interface a fUll-duplex (2-wire) voice telephone
circuit with a TOM (time-division-multiplexed) system. Primary applications include:
•

Line interface for digital transmission and switching of T1 carrier,
PABX, and central office telephone systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital signal processing

The device is designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. It is intended to be used
at the analog termination of a PCM line or trunk. The device requires two transmit and receive master clocks
that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are
synChronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TCM320AC54 provides the band-pass filtering of the analog signals prior to encoding
and after decoding of voice and call progress tones.
The TCM320AC54 is characterized for operation from DoC to 70°C.

PRODUCTION DATA Information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-89

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

functional block diagram
14
.-------------------------------------------------------GSX
R2

Analog
Input
15 R1
VFXI- -..JV'V'v-_*--I

SwitchedCapacitor
Band-Pass Filter

VFXI+1_6_ _ _ _---1

Transmit
Regulator

VFRO

SwitchedCapacitor
low-Pass Filter

Receive
Regulator

Power
Amplifier

ClK

Timing and Control
5V

VCC

VBB

ANlG GNO

MClKX

MClKRI
PON

~TEXAS

INSTRUMENTS
2-90

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BClKX BClKRI FSR FSX
ClKSEl

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

ANlG GND

Analog ground. All signals are referenced to ANlG GND.

BClKRlClKSEl

Receive bit (data) clock/clock select terminal for master clock. BClKRlClKSEl shifts data into DR after the FSR
leading edge and can vary from 64 kHz to 2.048 MHz. Alternately, BClKR/ClKSEl can be a logic input that selects
either 1.536 MHzl1.544 MHz or 2.048 MHz for the master clock in the synchronous mode. BClKX is used for both
transmit and receive directions (see Table 1).

Transmit bit (data) clock. BClKX shifts out the PCM data on DX and can vary from 64 kHz to 2.048 MHz, but must
be synchronous with MClKX.

BClKX
DR

FSR

Frame sync clock input for receive channel. FSR is an 8-kHz pulse train that enables BClKR to shift PCM data in DR
(see Figures 1 and 2 for timing details).

FSX

Frame sync clock input for transmit channel. FSX is an 8-kHz pulse train that enables BClKX to shift out the PCM
data on DX (see Figures 1 and 2 for timing detailS).

GSX

Analog output of the transmit input amplifier. GSX is used to externally set gain.

MClKRlPDN

MClKX
TSX

9
13

Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3·state PCM data output that is enabled by FSX

Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). MClKR/PDN may be synchronous with
MClKX but should be synchronous with MClKX for best performance. When the input is continuously low, MClKX
is selected for all internal timing. When the input is continuously high, the device is powered down.
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). MClKX may be asynchronous with MClKR.
Transmit time-slot strobe. TSX is an open-drain output that pulses low during the encoder time slot.

=-5 V ± 10%
=5 V ±10%

VBB

Negative power supply. VBB

VCC

Positive power supply. VCC

VFRO

Analog output of the receive filter

VFXI+

Noninverting input of the transmit input amplifier

VFXI-

Inverting input of the transmit input amplifier

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TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Supply voltage, VBB (see Note 1) ............................................................ -7 V
Voltage range at any analog input or output ............................... Vee +0.3 V to VBB -0.3 V
Voltage range at any digital input or output .......................... Vee +0.3 V to ANLG GND -0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range,T stg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GNO.
DISSIPATION RATING TABLE
PACKAGE
OW

TA::; 25°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

TA 70°C
POWER RATING

TA 85°C
POWER RATING

1025 mW
1150 mW

8.2 mW/oC

656mW
736mW

533mW
598mW

9.2 mW/oC

recommended operating conditions (see Note 2)
MIN

NOM

MAX

Supply voltage, VCC

4.5

5.5

Supply voltage, VSB

-4.5

-5

-5.5

2.2

High-level input voltage, VIH

0.6

±2.5

Common-mode input voltage range, VICR+

V
V

Load capacitance, GSX, CL
Operating free-air temperature, TA

Low-level input voltage, VIL
Load resistance, GSX, RL

UNIT

°C

+ Measured with CMRR > 60 dS.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature
supply current
PARAMETER
ICC

Supply current from VCC

ISS

Supply current from VSS

TEST CONDITIONS
Power down
Active
Power down
Active

No load

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MIN

TYP

MAX

0.5

UNIT
rnA

rnA

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

electrical characteristics at vee
noted)

=5 V ±5%, VBB =-5 V ±5%, GND at 0 V, TA =25°C (unless otherwise

digital interface
TEST CONDITIONS

PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

IH=-3.2 rnA

IL= 3.2 rnA

TSX

IL= 3.2 rnA,

MIN

MAX

2.4

V
0.4
0.4

Drain open

UNIT

IIH

High-level input current

VI = VIH to VCC

±15

Il A

IlL

Low-level input current

All digital inputs

VI = GND to VIL

±15

Il A

VOL

Output current in high-impedance state

Va = GND to VCC

±15

Il A

MAX

UNIT

analog interface with transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current

VFXI + or VFXI -

VI = -2.5 V to 2.5 V

Input resistance

VFXI + or VFXI -

VI = -2.5 V to 2.5 V

Output resistance

MIN

±200
10

Closed loop

Output dynamic range

GSX

Open-loop voltage amplification

VFXI+to GSX

RL~

TYPt

nA
Mn

10 kn

±2.8

5000
1

MHz

Unity-gain bandwidth

GSX

Via

Input offset voltage

VFXI + or VFXI -

CMRR

Common-mode rejection ratio

KSVR

Supply-voltage rejection ratio

±20

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

analog interface with receive filter
PARAMETER
Output resistance

TEST CONDITIONS

VFRO = ±2.5 V

Load resistance
Load capacitance
Output dc offset voltage

MIN

IVFRO

I VFROto GND

IVFROto GND

TYPt

MAX

600

UNIT
n
n

500

±200

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

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TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

operating characteristics, Vee 5 V ±5%, VBB -5 V ±5%, GND at 0 V, VI 1.2276 V, f 1.02 kHz,
TA =oDe to 70 D
C, transmit input amplifier connected for unity gain, noninverting (unless otherwise
noted)
timing requirements
TEST CONDITIONS
fclock(M)

Frequency of master clock (see Table 1)

MCLKX
and
MCLKR
BCLKX

MIN

TYPt

MAX

1.536
1.544
2.048

Depends on BCLKXlCLKSEL

UNIT
MHz

fclock(B)

Frequency of bit clock, transmit

tw1

Pulse duration, MCLKX and MCLKR high

160

tw2

Pulse duration, MCLKX and MCLKR low

160

tr1

tf1

MCLKX
and
MCLKR

Rise time of master clock

MCLKX
and
MCLKR

Fall time of master clock

tr2

Rise time of bit clock, transmit

tf2

Fall time of bit clock, transmit

tsu1

Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKXJ..

BCLKX
\

BCLKX

2.048

kHz

Measured from 20% to 80%

Measured from 20% to 80%
First bit clock after the leading
edge of FSX

100

tW3

Pulse duration, BCLKX and BCLKR high

VIH = 2.2 V

160

tw4

Pulse duration, BCLKX and BCLKR low

VIL = 0.6 V

160

th1

Hold time, frame sync low after bit clock low
(long frame only)

th2

Hold time, BCLKX high after frame synci
(short frame only)

tsu2

Setup time, frame sync high before bit clockJ..
(long frame only)

td1

Delay time, BCLKX high to data valid

Load = 150 pF plus 2 LSTTL loads+

td2

Delay time, BCLKX high to TSX low

Load = 150 pF plus 2 LSTTL loads+

td3

Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled

td4

Delay time, FSX or BCLKX high to data valid
(long frame only)

CL = 0 pF to 150 pF

140

165

tsu3

Setup time, DR valid before BCLKRJ..

th3

Hold time, DR valid after BCLKR or BCLKXJ..

tsu4

Setup time, FSR or FSX high before
BCLKR or BCLKRJ..

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

th4

Hold time, FSX or FSR high after
BCLKX or BCLKRJ..

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

100

th5

Hold time, frame sync high after bit clockJ..

Long-frame sync pulse (from 3 to 8 bit
clock periods long)

100

tW5

Minimum pulse duration of the frame sync
pulse (low level)

64-kbps operating mode

160

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
+ Nominal input value for an LSTTL load is 18 kil.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.

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TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

filter gains and tracking errors
TEST CONDITIONS=!:

PARAMETER
Maximum peak transmit overload level

3.17 dBmO

Transmit filter gain, absolute (at 0 dBmO)

TA= 25°C

MIN

TYPt

-1.5

-25

f = 60 Hz

-21
-2

0.5

-0.5

0.5

f = 3300 Hz

-0.55

0.5

f = 3400 Hz

-1.5

f = 200 Hz
f = 300 Hz to 3000 Hz

1.5
-10

f = 4000 Hz
4600 Hz (measure response from

-25

o Hz to 4000 Hz)
Absolute transmit gain variation with temperature
and supply voltage

V
1.5

f = 50 Hz

UNIT

-35

f= 16 Hz

Transmit filter gain, relative to absolute

MAX

2.501

Relative to absolute transmit gain

-0.1

0.1

Sinusoidal test method,
Reference level = -10 dBmO
Transmit gain tracking error with level

3 dBmO ~ input level

-40 dBmO

-40 dBmO > input level
Receive filter gain, absolute (at 0 dBmO)

-50 dBmO

Input is digital code sequence for
o dBmO signal,
TA = 25°C

-0.5

0.5
0.5

f = 3400 Hz

-1.5

1.5

-0.1

-40 dBmO

-40 dBmO > input level
Receive output drive voltage

0.1

Sinusoidal test method; reference
input PCM code corresponds to an
ideally encoded -10 dBmO signal
3 dBmO ~ input level

-10

f = 4000 Hz
Absolute receive gain variation with temperature
and supply voltage

Receive gain tracking error with level

1.5

-0.55

TA = 25°C

±O.B
-1.5

f = 3300 Hz

f = 0 Hz to 3000 Hz,
Receive filter gain, relative to absolute

±OA

-50 dBmO

RL= 10 kn

±OA
±O.B
±2.5

All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
:j: Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBmO = 4 dBm at f = 1.02 kHz with RL = 600 n.

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TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

envelope delay distortion with frequency
PARAMETER

TEST CONDITIONS

MIN

= 1600 Hz
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f =2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz

Transmit delay, absolute (at 0 dBmO)

Transmit delay, relative to absolute

Receive delay, absolute (at 0 dBmO)

Receive delay, relative to absolute

TYP

MAX

UNIT

290

315

I1s

195

220

120

145

105

130

155

180

200

-40

-25

-30

-20

I1s

100

125

140

175

TYPt

MAX

dBrnCO

I1s

noise
PARAMETER

TEST CONDITIONS

MIN

= OV

Transmit noise, C-message weighted

VFXI

Receive noise, C-message weighted

PCM code equals alternating positive
and negative zero

Noise, single frequency

VFXI+ = 0 V,
f = 0 kHz to 100 kHz,
Loop-around measurement

UNIT

-53

dBmO

MAX

UNIT

t All typical values are at VCC = 5 V, VBB =-5 V, and TA = 25°C.
power-supply rejection
PARAMETER

TEST CONDITIONS

MIN

Positive power-supply rejection, transmit

VCC = 5 V + 100 mVrms,
f = 0 kHz to 50 kHz

VFXI+

=-50 dBmO,

Negative power-supply rejection, transmit

VBB = 5 V + 100 mVrms,
f =0 kHz to 50 kHz

VFXI+

=-50 dBmO,

Positive power-supply rejection, receive

PCM code equals positive zero,
VCC = 5 V + 100 mVrms

Negative supply-voltage rejection, receive

PCM code equals positive zero,
VBB =-5 V + 100 mVrms

Spurious out-of-band signals at the channel output
(VFRO)

dBC::j:

=0 Hz to 50 kHz

dBC::j:

f = 0 Hz to 50 kHz

dBC::j:

o dBmO, 300-Hz to 3400-Hz input applied to DR
(measure individual image signals at VFRO)

-25

f = 4600 Hz to 7600 Hz

-28

=7600 Hz to 100 Hz

-35

f
::j: The unit dBC applies to C-message weighting.

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dB
dB

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

distortion
PARAMETER

MIN

TEST CONDITIONS

=3 dBmO
Level =0 dBmO to -30 dBmO

Signal-to-distortion ratio, transmit or receive half-channel;

ITransmit

Level = -40 dBmO

MAX

UNIT

Level

IReceive

dBCt

25
25

Single-frequency distortion products, transmit

-41

Single-frequency distortion products, receive

-41

-35

Intermodulation distortion

Loop-around measurement,
VFXI + = -4 dBmO to -21 dBmO,
Two frequencies in the range of 300 Hz to 3400 Hz

t The unit dBC applies to C-message weighting.
; Sinusoidal test method. The TCM320A54 is measured using a C-message weighted filter.

crosstalk
TYP§

MAX

UNIT

Crosstalk, transmit-to-receive

f = 300 Hz to 3000 Hz,

DR at steady PCM code

-90

-75

Crosstalk, receive-to-transmit (see Note 4)

VFXI =OV,

f = 300 Hz to 3000 Hz

-90

-75

PARAMETER

TEST CONDITIONS

MIN

§ All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
NOTE 4: Receive-to-transmit crosstalk is measured with a - 50-dBmO activation Signal applied at VFXI +.

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MONOLITHIC SERIAL INTERFACE
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PARAMETER MEASUREMENT INFORMATION
~

TSX

I+- td2

- - - - - - - 1,I

I -\-..._20_%_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

tr1 -+j 14---

II
II

~_--.~~II

-.II.- tf1 I
II

---l ~ td3
I I,
--+I~f20%

I
I
I
I
I
I
I
I
I

fclock(M)

MClKX
MClKR

BClKX

I
I
I
I
I
I

FSX-----

-.! I+- td3

DX _ _ _ _ _ _ _~--'--~·r--~~-~/---~r--'r---~r---L~8~0~~.--' - - _ . . . I '-_---"'___ _ _ 1 ' - - _ . . . 1 ' -_ _ _,

BClKR

' _ _ _ - - ' " - -_ _I\._~

20%
th2

-+I- 1+-11

~
I

II
II
II
II

I
I
I
I

trtsu4

~th4

FSR - - - - - " ' - 20%

'-.---------------*iI-----~I--tsu3

_______

_ J ' _ __ _ _

'~_~~

Figure 1. Short·Frame Sync Timing

•
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~th3

I
I

--.j I.-- th3

~-~~-......I'--~'-----

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
tr1 ---+j ~

tw1 ~I1+.- - - - . t - fclock(M)

I ~~tf1 I Irl

MClKX
MClKR

tsu1 ~
tsu1 -f-.II

20% ,

BClKX

It-

th 1 ---+l

---+j J+- tr2

I.-

td4

~ tW3

I~ t 4
II
w

tf2 I
I

20% 80%

' I

I~
,-+l

-+114-

,% ~ (

FSX

II
II

tw2

14---t---t.'l-1 f clock(B)

tsu2

J+-

th5

00% ,'-_____J..+-l --------------------~r---\--+-2-0%-

td4

td1

-J J.-

-4----.J :

I
--X,--_2-,X,--_3-,X,-_4-,X~-5--t

OX - - - - - ( " " - 1

td3
X

~ r-

KIIj) :~~

II
td3~r
BClKR
th1

FSR

I'
I~ tsu2

-.I J+--

I
th5

-..I I.-

-1- - - - - - - - h =\

!2~~~;.~:o------~8~OO;':"""'O,r-I
---'

~~~~
I I.----.!-

DR _ _ _ _-'X"--_....IX"--_2-....1X

rXD"--__
-----.!

th3
X

th3

Figure 2. Long-Frame Sync Timing

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TCM320AC54
MONOLITHIC SERIAL INTERFACE
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SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
TCM320AC54 system reliability and design considerations are described in the following paragraphs.
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM320AC54 is heavily protected against latch-up, it is still possible to cause latch-up under
certain conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when
the positive supply voltage drops momentarily below ground, when the negative supply voltage rises
momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied but before
the ground is connected. This can happen if the device is hot-inserted into a card with the power applied, or if
the device is mounted on a card that has an edge connector and the card is hot-inserted into a system with the
power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TCM320AC54-equipped card that has an edge
connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge
connector traces are longer than the power and signal traces so that the card ground is always the first to make
contact.

Ensure that no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Vee (most positive voltage).

Apply

Force a power down condition in the device.

Connect clocks.

Release the power down condition.

Apply FS synchronization pulses.

Apply the signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

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",.

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PRINCIPLES OF OPERATION
VCC

DGND

VBB

Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TCM320AC54 when power is first applied, placing it into the power-down
mode. OX and VFRO outputs go into high-impedance states and all nonessential circuitry is disabled. A low level
or clock applied to MCLKRlPON powers up the device and activates all circuits. DX, a 3-state PCM data output,
remains in the high-impedance state until the arrival of the second FSX pulse.

synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PON is used as a power-down control. A low
level on MCLKR/PON powers up the device and a high level powers it down. In either case, MCLKX is selected
as the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKRlCLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX can be in the range from 64 kHz to 2.048 MHz but must be synchronous with
MCLKX.

Table 1. Selection of Master-Clock Frequencies
BCLKRlCLKSEL

MASTER-CLOCK FREQUENCY
SELECTED

Clock input

1.536 MHz or 1.544 MHz

Logic input L (sync mode only)

2.048 MHz

Logic input H (open) (sync mode only)

1.536 MHz or 1.544 MHz

The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled OX output on the rising edge of BCLKX. After eight bit-clock periods, the 3-state OX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via OR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MClKX and MClKA.

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MONOLITHIC SERIAL INTERFACE
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SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

\'1

PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 1.536 MHz or 1.544 MHz and need not be synchronous. For best performance, however, MCLKR should
be synchronous with MCLKX. This is easily achieved by applying only static logic levels to MCLKR/PON. This
connects MCLKX to all internal MCLKR functions. For 1.544-MHz operation, the device compensates for the
193rd clock pulse of each frame. Each encoding cycle is started with FSX and FSX must be synchronous with
MCLKX and BCLKX. Each decoding cycle is started with FSR and FSR must be synchronous with BCLKA. The
logic levels shown in Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from
64 kHz to 2.048 MHz.

short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX
enables the 3-state output buffer, OX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges and the next falling edge disables OX. With FSR high during a falling edge of
BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse can be utilized in either the
synchronous or asynchronous mode.

long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, whichever occurs later, enables the OX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables OX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.

transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low-noise and wide-bandwidth characteristics of this device provide gain in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per Il-Iaw coding conventions, the AOC is a companding
type. A precision voltage reference provides a nominal input overload of 2.5 V peak. The sampling of the filter
output is controlled by the FSX frame-sync pulse. Then, the successive-approximation encoding cycle begins.
The 8-bit code is loaded into a buffer and shifted out through OX at the next FSX pulse. The total encoding delay
is approximately 290 Ils. Any offset voltage due to the filters or comparator is cancelled by sign-bit integration.

~TEXAS

INSTRUMENTS
2-102

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

PRINCIPLES OF OPERATION
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder and the fifth-order low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sampleand-hold circuit. The filter is followed by a second-order RC active post-filter/power amplifier capable of driving
a 600-Q load to a level of 7.2 dBm. The receive section is unity gain. At FSR, the data at DR is clocked in on
the falling edge of the next eight BClKR (BClKX) periods. At the end of the decoder time slot, the decoding
cycle begins and 10 Ils later, the decoder DAC output is updated. The decoder delay is about 10 Ils (decoder
update) plus 110 Ils (filter delay) plus 62.5 Ils (1/2 frame), or a total of approximately 180 Ils.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-103

TCM320AC54
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS043A - NOVEMBER 1994 - REVISED JULY 1996

APPLICATION INFORMATION

power supplies
While the terminals of the TCM320AC54 are well protected against electrical misuse, it is recommended that
the standard CMOS practice be followed, ensuring that ground is connected to the device before any other
connections are made. In applications in which the printed-circuit board can be plugged into a hot socket with
power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and Vss
supplies should be decoupled by connecting O.1-IlF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to Vee and Vss.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation, rather than via a ground bus. This common ground point should be decoupled to Vee
and Vss with 10-IlF capacitors.
1

16
VBB

0.1 IlF ::::::::::
2

J-

VFXI
ANLG GND

15
14 R1

-0.1IlF::::~

GSX
4
VCC

5V
3

To SLIC

Fr om SLIC

VFXI+

1...

R2
v

TCM320AC54

~
Analog Interface

VFRO

- - - - - - - - ------------- r - - - - - - - 5

FSR

FSX
DX

Da ta In

5 Vor GND

8
PDN

NOTE A: Transmit gain

=20

log

12
11

Digital
Interface

DR
BCLKR/CLKSEL

BCLKX

MCLKRlPDN

(R1:2 R2), (R1 + R2)

MCLKX

10 kQ

Figure 4. Typical Synchronous Application

~TEXAS

INSTRUMENTS
2-104

----t--

Da ta
0 ut

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BC KL (2.048 MHz/1.544 MHz)

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018-JUNE 1996

•

•
•
•
•
•
•
•
•
0

Meets CCITT/(D3/D4) Channel Bank
Recommendations for Input Signals
Greater than -55 dBmO
Programmable Transmit and Receive Gain
Control with Pin-Selectable
Gain/Attenuation Levels
Includes Differential Output on the
TCM37C14
Precision Switched-Capacitor Filters and
Converters
Improved Version TCM29C13 Series
COMBOs (CO DEC and Filters)

TCM37C13, TCM37C15 ... ow OR N PACKAGE
(TOP VIEW)

Low Power CMOS
- Operating Mode .... 80 mW Typical
- Power-Down Mode ... 5 mW Typical
Internal Sample-and-Hold and Autozero
Functions
Precision Internal Voltage References
TCM37C14 Features Pin-Selectable Il-Law
or A-Law Companding, TCM37C13 is Il-Law
only, and TCM37C15 is A-Law Only.
Pin-Selectable Master Clock Rate (1.536
MHz, 1.544 MHz, and 2.048 MHz Available)
on the TCM37C14

description

10
2
3
4
5
6
7
8
9
10

VBB
PWRO+
RIN
RS1
RS2
GSR
GS1
GSa
PCMIN
FSR

20
19
18
17
16
15
14
13
12
11

Vee
GSX
TS1
TS2
ANLGIN
AGND
PCMOUT
FSX
MCLK
DGND

TCM37C14 ... ow PACKAGE
(TOP VIEW)

VBB
PWRO+
PWRORIN
RS1
RS2
GSR
GS1
Gsa
CLKSEL
PCMIN
FSR

10
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

Vee
GSX
TS1
TS2
ANLGIN
AGND
TSX
PCMOUT
FSX
ASEL
MCLK
DGND

The TCM37C13, TCM37C14, and TCM37C15 devices are single-chip PCM combos (pulse-code-modulated
COOECs with voice-band filtering). They are designed to perform transmit encoding (AlO conversion) and
receive decoding (O/A conversion), as well as the transmit and receive filtering functions required to meet
CCITT/(03/04) G.711 and G.714 specifications in a PCM system. Each device provides all the functions
required to interface a full-duplex, 4-line voice telephone circuit with a TOM (time-division-multiplexed) system,
and also perform the encoding and decoding of call progress tones. The TCM37C13, TCM37C14, and
TCM37C15 are based on the proven TI TCM29C13 core, and have the added feature of programmable transmit
and receive gain.
Primary applications include line interface for digital transmission and switching of T1 carrier (PABX [private
branch automatic exchange] and central office telephone systems), subscriber line concentrators, digital
encryption systems, and digital signal processing. They are intended to be used at the analog termination of
a PCM line or trunk to the POTS (plain old telephone system) local-loop line.

ADVANCE INFORMATION concerns new products In the sampling or
preproduction phase of development Characteristic data and other
specifications are subject to change without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-105

!i
~

(,)

~
C

t -_ _-t-1_7 PCMOUT

Sample
and Hold
DAC

RS1 ~5+-_ _ _......

PWRO+ --::,2-t-..........- - - ,

PWRO~ ~3+-~~_~

1----4---1-- ASELt
1----4---1-....:.... GSO
1----4---I-~ GS1

RS2 ~6+-_ _ _......

CLKSELt

I
I
I

RIN .....;.:.4+-_ _ _....
GSR -=-7+-_ _ _....

11 PCMIN

vee

AGND

t TCM37C14 only.
NOTE A: Terminal numbers shown are for the TCM37C14.

~TEXAS

2-106

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

12
FSR

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018-JUNE 1996

Terminal Functions
TERMINAL
NAME

'37C13
'37C15

'37C14

110

DESCRIPTION
Analog ground return for all internal voice circuits. AGND is not connected internally to DGND.

AGND

ANLGIN

Analog input to transmit operational amplifier.

ASEL

Selection between A-law and J.l-Iaw operation. When ASEL is connected to VBB, A-law is
selected. When ASEL is connected to VCC or ground, J.l-Iaw is selected.

CLKSEL

Clock frequency selection. Input must be connected to VBB, VCC, or ground to select the master
clock frequency. When tied to VBB, MCLK is 2.048 MHz. When tied to ground, MCLK is at 1.544
MHz. When tied to VCC, MCLK is 1.536 MHz.

Frame synchronization clock input/time slot enable for receive channel. The receive channel
enters the standby state when FSR is held low for 300 ms.

Digital ground for all internal logic circuits. DGND is not internally connected to AGND.

DGND

FSR

FSX

Frame synchronization clock input/time slot enable for transmit.

GSO

Input for first bit of the programmable gain control circuitry. This terminal works in combination
with GS1 to simultaneously control transmit and receive gain, and controls power down
instruction. See Table 1 and 2 for control logic information.

GS1

Input for second bit of the programmable gain control circuitry. This terminal works in
combination with GSO to simultaneously control transmit and receive gain, and controls power
down instruction. See Table 1 and 2 for control logic information.

GSR

Input to gain-setting network of the output power amplifier. Gain is set by external resistors with
three levels of programmable gain or attenuation control. See Figure 6 and Figure 7 for
recommended configuration.

GSX

Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal
input to the transmit filter.

MCLK

Master clock (input). For the TCM37C14, the master clock frequency can be either 2.048 MHz,
1.544 MHz, or 1.536 MHz, and is selected by the CLKSEL pin. MCLK for the TCM37C13 and
the TCM37C15 is 2.048 MHz.

PCMIN

Receive PCM input. PCM data is clocked in on this pin on eight consecutive negative transitions
of the receive data clock, (MCLK).

()

PCMOUT

Transmit PCM output. PCM data is clocked out on this output on eight consecutive positive
transitions of the transmit data clock, (MCLK).

PWRO+

Noninverting output of power amplifier. PWRO+ can drive transformer hybrids or
high-impedance loads directly in a differential or a single-ended configuration.

Inverting output of power amplifier. PWRO- is functionally identical with and complementary
to PWRO+.

PWRO-

Input to receive section amplifiers. See Figure 6 and Figure 7 for recommended Circuitry.

RIN

RS1

Terminal for first gain-control resistor on the receive section. Selected through closure of the first
gain control switch. See Figure 6 and Figure 7 for recommended circuitry.

RS2

Terminal for second gain control resistor on the receive section. Selected through closure of the
second gain control switch. See Figure 6 and Figure 7 for recommended configuration.

TS1

Terminal for gain-control resistor on input of transmit section. Selected through closure of the
first gain-control switch. See Figure 6 and Figure 7 for recommended configuration.

TS2

Terminal for gain-control resistor on input of transmit section. Selected through closure of the
second gain-control switch. See Figure 6 and Figure 7 for recommended configuration.

TSX

VBB

VCC

Transmit channel time slot strobe for the transmit channel (active low).
Most negative voltage supply voltage. Input is -5 V ± 5%.
Most positive supply voltage. Input is 5 V ± 5%.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-107

z
o

:?E

o
LL
W

<3:

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ................................................... -0.3 V to 15 V
Input voltage, VI .................................................................. -0.3 V to 15 V
Digital ground voltage ............................................................. -0.3 V to 15 V
Continuous total dissipation at (or below) 25 0 C free-air temperature ......................... 1375 mW
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW or N package ............... 260°C
t

recommended operating conditions (see Note 2)
Supply voltage, VCC (see Notes 2 and 3)

Supply voltage, VSS

High-level input voltage, VIH

o
m

Load resistance, RL

-z

"'T1

o
s:

MIN

NOM

MAX

UNIT

4.75

5.25

-4.75

-5

-5.25

DGND voltage with respect to AGND
2.2

AtGSX
At PWRO+ and/or PWRO-

Operating free-air temperature, TA

50
100
0

°c

2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedu~e described in the device
power-up sequence paragraphs later in this document should be followed.
3. Voltages at analog inputs and outputs, VCC and VSS terminals, are with respect to the AGND terminal. All other voltages are
referenced to the DGND terminal unless otherwise noted.

o
z

~TEXAS

INSTRUMENTS
2-108

300

At PWRO+ and/or PWRO-

kn
n

AtGSX

Load capacitance, CL

V
0.8

Low-level input voltage, VIL

NOTES:

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (outputs not loaded) (unless otherwise noted)
supply current
PARAMETER

TEST CONDITIONS

MIN

Operating
ICC

Supply current from VCC

Supply current from VSS

FSX or FSR at VIL (after 300 ms)

0.5

Power-down

PON = VIL (after 300 ms)

0.3

0.9

-7

-9

Standby

FSX or FSR at VIL (after 300 ms)

-0.5

-1

Power-down

PON = VIL (after 300 ms)

-0.3

-0.9

Operating
Power dissipation

MAX

Standby

Operating
ISS

TVP

Standby

FSX or FSR at VIL (after 300 ms)

Power-down

PON = VIL (after 300 ms)

TVPt

MAX

UNIT

digital interface
PARAMETER
VOH

TEST CONDITION

High-level output voltage

IpCMOUT

IOH =-9.6mA

MIN
2.4

UNIT
V

VOL

Low-level output voltage at PCMOUT, TSX

IOL=3.2mA

0.4

IIH

High-level input current, any digital input

VI = 2.2 V to VCC

IlA

IlL

Low-level input current, any digital input

VI = Oto 0.8 V

IlA

Input capacitance

Output capacitance

All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C

o
~

o
IJ..
Z

transmit amplifier input
PARAMETER

TEST CONDITION

Input current at ANLGIN

VI =-2.17 V to 2.17 V

Input offset voltage at ANLGIN

VI =-2.17 V to 2.17 V

Common-mode rejection at ANLGIN

VI = -2.17 V to 2.17 V

Open-loop voltage amplification at GSX

MIN

TVPt

MAX

UNIT

±100

(.)

±25

5000

Open-loop unity-gain bandwidth at GSX

MHz

Input resistance at ANLGIN

Mil

t All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C
receive filter output*
PARAMETER

TEST CONDITION

Output offset voltage PWRO+, PWRO- (single-ended),
Relative to AGNO
Output resistance at PWRO+, PWRO-

MIN

TVPt
80
1

MAX

UNIT
mV
il

All typical values are at VSS = -5 V, VCC = 5 V, and TA = 25°C
:j: PWRO- on TCM37C14 only.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-109

~
C

input level input level input level input level input level

±0.5

-50> input level ANLGIN
Transmit signal to distortion ratio, sinusoidal input
(CCITI G.712 - Method 2)

Receive signal to distortion ratio, sinusoidal input
(CCITI G.712 - Method 2)

-30 dBmO

-30> ANLGIN

-40 dBmO

TYP

MAX

36
dB

-40> ANLGIN

o > ANLGIN ~ -30 dBmO

-30> ANLGIN

-40 dBmO

-40> ANLGIN

-45 dBmO

Transmit single-frequency distortion products

AT&T advisory #64 (3.8), Input Signal = 0 dBmO

-46

dBmO

Receive single-frequency distortion products

AT&T advisory #64 (3.8), Input signal = 0 dBmO

-46

dBmO

CCITIG.712 (7.1)

-35

CCITI G.712 (7.2)

-49

CCITI G.712 (6.1)

-25

CCITI G.712 (9)

-40

Intermodulation distortion, end-to-end
Spurious out-of-band signals, end-to-end

o
Z

dBmO

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

oIJ..

2-111

UNIT
~S

245

f = 500 Hz to 600 Hz
Transmit differential envelope delay
time relative to transmit absolute
delay time

MAX

Input signal at PCMIN is 0 dBmO

4 kHz

-14

4.6 kHz and above

-30

UNIT

timing requirments
clock timing (see Figure 3)
MIN

TYP

MAX

Clock period for MCLK (2.048 MHz systems)

Rise time for MCLK

Fall time for MCLK

tw(MCLK)

Pulse duration for MCLK (see Note 7)

220

Clock duty cycle [tw(CLK)/tc(CLK)l for MCLK

All typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C
NOTE 7: FSX CLK and FSR CLK must be phase-locked with MCLK.

transmit timing (see Figure 3)
Delay time (frame sync), FSR high or low before MCLK J,

~TEXAS

INSTRUMENTS
2-112

488

UNIT

tc(MCLK)

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

45%

50%

55%

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018-JUNE 1996

receive timing (see Figure 4)
PARAMETER
td(FSR)

Delay time, frame sync high or low before MCLK

tsu(PCMIN)

Setup time, PCMIN high before MCLK

th(PCMIN)

Hold time, after PCMIN

MIN

J..

MAX

100 tc(MCLK) -100

J..

UNIT
ns

switching characteristics
propagation delay times (see Figure 3 and 4)
PARAMETER

TEST CONDITION

MIN

MAX

UNIT

CL = 0 pF to 100 pF

145

Propagation delay times, MCLK i bit n to bit n data valid at PCMOUT (data
valid time)

CL = 0 pF to 100 pF

145

tpd3

Propagation delay times, MCLK J.. low bit 8 to bit 8 Hi-Z at PCMOUT
(data float time on time slot exit) (see Note 8)

CL= 0 pF

215

tpd4

Propagation delay times, MCLK i bit 1 to TSX active (low)
(time slot enable time)

CL = 0 pF to 100 pF

145

tpd5

Propagation delay times, MCLK J.. to bit 8 to TSX inactive (high)
(timeslot disable time) (see Note 8)

CL= 0 pF

190

tpd1

Propagation delay times, MCLK i to bit 1 data valid at PCMOUT
(data enable time on time slot entry) (see Note 8)

tpd2

NOTE 8: Timing parameters tpd1' t pd3, and tpd5 are referenced to the high-impedance state.

!i:a:
a:

oLL
Z

o
Z

~
C

.~ -10

Z
0

c
'ia

-Z

-10

-14dB
4000 Hz

>
~

~ -20

-20

CJ
I

Typical Filter
Transfer Function

-30

-40

-50

s:
~
Z

-60~~--~~~~~~~~----~--

100

__~~~~~~~~____~__~~~~~~~-60
1k
10 k
f - Frequency - Hz

NOTE A: For this figure, gain (voltage amplification) is defined as gain relative to gain at 1 kHz in dB.

Figure 1. Transmit Filter Transfer Characteristics

•
TEXAS
INSTRUMENTS
2-114

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018-JUNE 1996

0.15 dB
20 Hz

0.15 dB
200 Hz

.........

0.15 dB
3000 HZ

0.15 dB
300 Hz

-0.10 dB
3400 Hz
-0.15 dB
20 Hz

1
CIl

(ij

-0.15 dB
200Hz

rJ)

CIl

-0.15 dB
300 Hz

-1

III

c.
><

I
N

:I:

...

.::t.

iii

-10

'iii

-14dB

(!)

CIl

iii

-20

:a:

'iii

(!)

Typical Filter
Transfer Function

-30

L1.

Z
-40

-40

-50

0
Z

~
C

«
-60
10

100

-60
10 k

f - Frequency - Hz
NOTE A: For this figure, gain (voltage amplification) is defined as gain relative to gain at 1 kHz in dB.

Figure 2. Receive Filter Transfer Characteristics

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-115

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

MCLK
td(FSX)

1 :.-

FSX---"~----~ ~____~___________________~_-___
-_-_-_~~I~t_C(_M_C_L_K)____________
: ____
1

tpd1

tpd3~1

*-tpd2
1

1.-

PCMOUT--------~~

TSX

OUTPUT

Figure 3. Transmit Timing

MCLK

111

~
Z

,...---..-rl. I',1

FSR

tsu(PCMIN) -4l

o
z

t
td(FSR) r

1
j4-

I l-.j

i+- th(PCMIN)

PCMIN

o
:c
S

l'i 1

(")

-z

Bit 1t
Valid

Bit2
Valid

Blt3
Valid

Bit4
Valid

Bit 5
Valid

Bit6
Valid

Bit7
Valid

BitS*
Valid

t Bit 1 = MSB = most significant bit (sign bit) and is clocked in first on the PCMIN pin or clocked out first on the PCMOUT terminal.
:j: BIT 8

LSB least significant bit and is clocked in last on the PCMIN or is clocked out last on the PCMOUT terminal.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V when the high level is indicated and 0.8 V when the low
level is indicated.

Figure 4. Receive Timing

~TEXAS

INSTRUMENTS
2-116

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
General TCM37C13, TCM37C14, and TCM37C15 system reliability and design considerations are described
in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TCM37C13, '14, and '15 are heavily protected against latch-up, it is still possible to cause
latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up
can occur when the positive supply voltage drops momentarily below ground, when the negative supply voltage
rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied
but before the ground is connected. This can happen if the device is hot-inserted into a card with the power
applied, or if the device is mounted on a card that has an edge connector, and the card is hot-inserted into a
system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent), between
each power supply and GND (see Figure 5). If it is possible that a TCM37C13-, '14-, or '15-equipped card that
has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the
ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.

ou.
Z

device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A Signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.

o
~

Ensure no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply

(.)

Vee (most positive voltage).

Force a power down condition in the device.

Connect the master clock.

Release the power-down condition.

Apply FSX and/or FXR synchronization pulses.

Apply signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

•
TEXAS
INSTRUMENTS
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2-117

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

PRINCIPLES OF OPERATION

Vee
DGND

Vee
Figure 5. Latch-Up Protection Diode Connection
internal sequencing
On the transmit channel, digital outputs PCMOUT and TSXt are held in the high-impedance state for
approximately four frames (500 Jls) after power up or application of VBB or Vee. After this delay, PCMOUT and
TSXt are functional and occur in the proper timeslot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus, valid digital
information, such as for on/off hook detection, is available almost immediately, while analog information is
available after some delay.

To further enhance system reliability, PCMOUT and TSX t are placed in a high-impedance state approximately
20 Ils after an interruption of MCLK. This interruption could possibly occur with some kind of fault condition
elsewhere in the system.

o
m
z-

o
:c

TCM37C14 only.

"TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS01B - JUNE 1996

PRINCIPLES OF OPERATION

miscellaneous functions
Miscellaneous functions of the TCM37C13, TCM37C14, and TCM37C15 are described in the following
paragraphs.

gain/attenuation control
On-chip logic is included on the TCM37C13, '14, and '15 to control the channel gain or attenuation, and
power-down functions with minimum terminal allocation. The operational amplifiers in the receive and transmit
sections can be configured to either attenuate or amplify the signal depending on how external resistors are
connected to the device.
Two control input terminals (GSa and GS 1) select one of three levels of gain or attenuation in the transmit and
receive path, and power-down. Note that the gain for both the transmit and receive sides are set together and
that the device enters the power-down mode when both GSa and GS1 are held low

gain adjustment
If gain is used on the receive side, the input PCM data levels must be properly limited to prevent saturation of
the output amplifier. Refer to the gain and dynamic range table in the electrical characteristics section of this
document.
The gain of the transmit and receive amplifiers is set by external resistors connected to the device as shown
in Figure 6 and can be adjusted using internal switching elements as shown in Table 1.
PWRO+

:aE

a:
o
LL
Z

RSF
RSIN

RIN

(.)

RSA
RSB

z
o

RS1

S1
RS2

-----,
-=
AGND

~
o

-Z

A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power lines,
17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise.
Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at 200
Hz. This feature allows the use of low-cost transformer hybrids without external components to be used in
systems.

-n

s:
~

encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal
sample-and-hold capacitor. The encoder performs an AID conversion on a switched-capacitor array. Digital
data representing the sample is then transmitted on the first eight data clocks bits of the next frame.

o
z

The autozero circuit corrects for dc offset on the input signal to the encoder, using the sign bit averaging
technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the
encoder, removing all dc offset from the encoder input waveform.

receive operation
The receive operation is described in the following paragraphs.
decoding
The serial PCM word is received at the PCMIN terminal on the first eight data clock bits of the frame. D/A
conversion is performed and the corresponding analog sample is held on an internal sample-and-hold capacitor.
The sample voltage is then transferred to the receive filter.
receive filter
The receive filter provides passband flatness and stopband rejection that fulfills both the AT&T D3/D4
specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin x)/x
response of such decoders.

~TEXAS

INSTRUMENTS
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TCM37C13, TCM37C14, TCM37C15
PCM COMBO WITH PROGRAMMABLE GAIN CONTROL
SLWS018 - JUNE 1996

Transmission levels are specified relative to the receive channel output under digital milliwatt conditions (Le.
when the digital input at PCMIN is the 8-code sequence specified in CCITT recommendation G.711).

z
o

o
L1.
Z

o
Z

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-123

2-124

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

•
•
•
o

•
e

•
•

Single 5-V Supply
Replaces Four TCM29C13 Combos
(CODEC and Filters)
Reliable Submlcron Silicon-Gate CMOS
Technology
Low Power Consumption (per Channel)
- Operating Mode ... 40 mW Typical
- Power-Down Mode ... 1 mW Typical
Meets CCITT/(D3/D4) G.711 and G.714
Channel Bank Specifications
Differential Signal Processing Architecture
for Low Idle-Channel Noise and Good
Power Supply Rejection
Single PCM 1/0 for Simplified PCM Interface
Advanced Switched-Capacitor Filters and
Sigma-Delta AID and DIA Converter
Technology

description

The TCM38C17 QCombo is a 4-channel single-chip
PCM combo (pulse-code-modulated CODEC with
voice-band filtering) device. It performs the transmit
encoding (AID conversion) and receive decoding (D/A
conversion), as well as the transmit and receive filtering
functions required to meet CCITT G.711 and G.714
specifications in a PCM system. Each channel provides
all the functions required to interface a full-duplex,
4-line voice telephone circuit with a TDM
(time-division-multiplexed) system. The TCM38C17 is
specifically designed for fixed-data-rate applications
and is intended to replace four TCM29C13 devices.

DGG PACKAGE
(TOP VIEW)

RBIAS
AGND
AVSS
OGSX
OANLGINOANLGIN+
OPWRO+
OGSR
OPWRO1GSX
1ANLGIN1ANLGIN+
1PWRO+
1GSR
1PWROOPDN
1PDN
VSS
DVSS
DVDD
DVDDPLL
MCLK
DVSSPLL
ASEL

1°
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48 REFLTR1
47 REFLTR2
46 AVDD
45 2GSX
44 2ANLGIN43 2ANLGIN+
42 2PWRO+
41 2GSR
40 2PWRO39 3GSX
38 3ANLGIN37 3ANLGIN+
36 3PWRO+
35 ] 3GSR
34 J3PWRO33 J3PDN
32 ] 2PDN
31 OFS
30 1FS
29 2FS
28 3FS
27 PCMOUT
26 RESET
25 ] PCMIN

The TCM38C17 is available in a 48-pin plastic DGG TSSOP (thin shrink small-outline package) and is
characterized for operation from -40°C to 85°C.

TI and QCombo are registered trademarks of Texas Instruments, Inc.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

0..
I-

Other applications include any PCM digital-audio interface such as voice-band data storage systems and many
digital signal processing applications that can benefit from the reduced footprint of a quad codec configuration
and single-rail operation. Dynamic range and excellent idle-channel noise performance are maintained using
the TI advanced 4Vt process technologies.

PRODUCT PREVIEW Information concerns products In the formaUva or
d2s1n phase of development CharacterisUc data and other
s flcatlons are d.slgn goals. Teuslnstrumenta rlSlrvlS the right to
c ang. or dlscontinuethlSl products without noUct.

:>
W
::»
c

Primary applications include digital transmission and switching of T1 carrier PABX (private automatic branch
exchange) and central office telephone systems and subscriber line concentrators. The device serves as the
analog termination of a PCM line or trunk to the POTS (plain old telephone system) local-loop line.

•

2-125

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TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

functional block diagram
GSX

Transmit Section

ANGLlN-

PCMOUT

ANGLIN +

1+..-......- -.....r--t---
w
a:
c..
Io
::)

2-127

c
o
a:
c..

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

3PDN

Power-down select for channel 3. This channel of the device is inactive with a CMOS low-level input to
3PND and active with a CMOS high-level input to the terminal (digital).

OPWRO+

Noninverting output of channel 0 power amplifier, able to drive 600 n II 100 pF load (analog).

OPWRO-

Inverting output of channel 0 power amplifier, able to drive 600 n 11100 pF load (analog).

1PWRO+

Noninverting output of channel 1 power amplifier, able to drive 600 n II 100 pF load (analog).

1PWRO-

Inverting output of channel 1 power amplifier, able to drive 600 n 11100 pF load (analog).

2PWRO+

Noninverting output of channel 2 power amplifier, able to drive 600 n 11100 pF load (analog).

2PWRO-

Inverting output of channel 2 power amplifier, able to drive 600 n 11100 pF load (analog).

3PWRO+

Noninverting output of channel 3 power amplifier, able to drive 600 n 11100 pF load (analog).

3PWRO-

RBIAS

Inverting output of channel 3 power amplifier, able to drive 600 n II 100 pF load (analog).
Bias current setting resistor. A 100 kn, ± 5% resistor should be connected between terminals RBIAS
and AVSS to set the bias current of the device.

REFLTR1

Voltage reference. A 1-j.1F external decoupling capacitor should be connected from REFLTR1 to AVSS
for filtering purposes.

-a

REFLTR2

Voltage reference. A 1-!-lF external decoupling capacitor should be connected from REFLTR2 to AVSS
for filtering purposes

o
c

RESET

Reset. Reset for all internal registers is initiated when RESET is brought high and held high for eight
clock cycles (digital).

VSS

Substrate bias. This terminal should be externally connected to AVSS.

(1 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t

-f

Supply voltage range, VDD (see Note 1) ............................................... -0.3 V to 7 V
Input voltage range, VI .............................................................. -0.3 V to 7 V
Digital ground voltage range, Va ..................................................... -0.3 V to 7 V
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C

-a
J]
m

<
-

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to AVSS.

recommended operating conditions (see Notes 2 and 3)
Supply voltage, VDD
High-level input voltage, VIH

MIN

NOM

MAX

4.5

5.5

0.2 x VDD

Load resistance between PWRO+and AVSS (single ended), RL

600

Load capacitance between PWRO+ and AVSS, (single ended) CL
-40

Operating free-air temperature, TA
NOTES:

V
n

100

°C

~TEXAS

INSTRUMENTS
2-128

V
V

0.8 xVDD

Low-level input voltage, VIL

UNIT

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current, total device, MCLK =2.048 MHz, outputs not loaded, Voo
PARAMETER
IDD

=5 V, TA =25°C

TEST CONDITIONS

MIN

! Operating

Supply current from VDD

I Power down

PDN (all channels)

TYP

MAX

UNIT

rnA

digital interface
PARAMETER

TEST CONDITIONS

MIN

TYP

VOH

High-level output voltage

!PCMOUT

IOH=-3.2 rnA

4.6

VOL

Low-level output voltage

!PCMOUT

IOL= 3.2 rnA

0.2

IIH

High-level input current, any digital input

=0.8 xVDD
VI =0.2 xVDD
VI

IlL

Low-level input current, any digital input

Input capacitance

Output capacitance

MAX

UNIT
V

0.4

IlA

IlA
pF

transmit amplifier input (unless otherwise noted)
PARAMETER

TEST CONDITION

MIN

TYP

Input current at ANLGIN+ and ANLGINInput offset voltage at ANLGIN+ and ANLGINCommon-mode rejection at ANLGIN+ and ANLGIN-:Open-loop voltage amplification at ANLGIN+ and ANLGIN-

Internal gain control set to 0 dB

MAX

±20

5000

Open-loop unity-gain bandwidth at ANLGIN+ and ANLGIN-

MHz

Input resistance at ANLGIN+ and ANLGIN-

UNIT

±100

>
w

a:
a..

I-

receive filter output
PARAMETER

TEST CONDITION

Output offset voltage PWRO+

MIN

TYPt

Relative to AGND

MAX
80

Output resistance at PWRO+
t All typical values are at VDD

UNIT
mV
n

=5 V, and TA =25°C

transmit and receive gain and dynamic range, Voo
PARAMETER

TEST CONDITION

=0.75 Vrms

Signal input

Encoder milliwatt response (nominal supplies and temperature)

Digital milliwatt response (receive tolerance gain)
relative to zero-transmission-Ievel point

Signal input per CCIIT G.711,
Output signal = 1 kHz
'

Digital milliwatt response variation with temperature
and power supplies

TA = O°C to 70°C,
Supplies =±5%

Transmit overload signal level (3 dB),
peak-to-peak centered at AGND

Input buffer is configured in unity gain

Receive reference-signal level at PWRO,

o dB level (3 dB is full scale)

Overload-signal level, (3 dB level) fully differential
(see Note 4)

MIN

TYP

MAX

UNIT

±0.04

±0.18

dBmO

±0.08

±0.18

dBmO

±0.08

Vpp

=O°C to 70°C, Supplies = ±5%
±0.04

RL = 600 n @ maximum gain
(Load resistance is connected
between PWRO+ and PWRO-)

Vrms

RL = 600 n @ maximum gain
(Load resistance is connected
between PWRO+ and PWRO-)

Vpp

NOTE 4: Maximum voltage swing (single-ended) is 3.5 V when VDD is 4.5 V.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

a:
a..

=5 V, TA =25°C (unless otherwise noted)

Encoder milliwatt response (transmit gain tolerance)

:::l

2-129

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

transmit and receive gain tracking over recommended ranges of supply voltage and operating free-air
temperature, reference level = -10 dBmO
PARAMETER

TEST CONDITION

MIN

TYP

3 > input level> -40 dBmO
Transmit gain tracking error,
sinusoidal input

-40 > input level> -50 dBmO

±0.5

-50> input level> -55 dBmO

±1.2

3 > input level> -40 dBmO
Receive gain tracking error,
sinusoidal input

MAX

UNIT

±O.25
dB

±O.25

-40 > input level> -50dBmO

±0.5

-50> input level> -55 dBmO

±1.2

noise over recommended ranges of supply voltage and operating free-air temperature
PARAMETER

TEST CONDITION

Receive noise, C-message-weighted quiet code

measured at PWRO+

Receive noise, psophometrically weighted

oC
C

"'tJ

PCM

PARAMETER

VDD supply voltage rejection, transmit
channel

VDD supply voltage rejection, receive
channel (single-ended)

TEST CONDITION

o ANLGIN > -30 dBmO

-30> ANLGIN > -40 dBmO

-40> ANLGIN > -45 dBmO

o > ANLGIN > -30 dBmO

-30> ANLGIN > -40 dBmO

-40> ANLGIN > -45 dBmO

TYP

MAX

UNIT

Transmit single-frequency distortion products

AT&T Advisory #64 (3.8),
Input signal = 0 dBmO

-46

dBmO

Receive single-frequency distortion products

AT&T Advisory #64 (3.8),
Input signal = 0 dBmO

-46

dBmO

CCITT G.712 (7.1)

-35

CCITT G.712 (7.2)

-49

CCITT G.712 (6.1)

-25

CCITT G.712 (9)

-40

Intermodulation distortion, end-to-end
Spurious out-of-band signals, end-to-end

dBmO

transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1)
PARAMETER

TEST CONDITION

MIN

16.67 Hz

-30

50 Hz

-25

60 Hz
Gain (voltage amplification) relative to gain at
1.02 kHz

Input amplifier set for unity gain,
Noninverting maximum gain output,
Input signal at ANLGIN is 0 dBmO

MAX

200 Hz

UNIT

-23
-1.8

-0.125

300 Hz to 3 kHz

-0.15

0.15

3.3 kHz

-0.35

0.15

3.4 kHz

-1

-0.1

receive filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 2)
PARAMETER

TEST CONDITION

Gain (voltage amplification) relative to gain at 1.02 kHz

Input signal at PCMIN
is 0 dBmO

MIN

MAX

Below 20 Hz

-0.15

0.15

20 Hz

-0.15

0.15

200 Hz

-0.15

0.15

300 Hz to 3 kHz

-0.15

0.15

3.3 kHz

-0.35

0.15

3.4 kHz

-1

-0.1

4 kHz

-14

4.6 kHz and above

-30

UNIT

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

->w
W

a:
a.

t::>
C
0
O

-14

4 kHz

2-131

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TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figures 3 and 4)
MIN
tc(MCLK)

Clock period for MCLK 2.048 MHz systems

Rise time for MCLK

Fall time for MCLK

tw(MCLK)

Pulse duration for MCLK (see Note 5)

NOMt

MAX

488

220
45%

Clock duty cycle [tw(MCLK)/tclMCLK)l for MCLK

UNIT

ns
50%

55%

t All nominal values are at VDD =5 V, and TA =25°C.
NOTE 5:

FS clock must be phase-locked with MCLK

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
Delay time, frame sync

"'tJ

-I
"'tJ

MAX

100

tc (MCLK) -100

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 4)

MIN

MAX

UNIT

td(FSR)

Delay time, frame sync

100

tsu(PCMIN)

Setup time, receive data

th(PCMIN)

Hold time, receive data

tc (MCLK) -100

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode (see
Figure 3)
MIN

MAX

=0 to 100 pF

145

=0 to 100 pF

145

=0 pF

215

TEST CONDITION

PARAMETER
tpd1

Transmit clock! to bit 1 data valid at PCMOUT
(data enable time on time slot entry) (see Note 5)

tpd2

Transmit clock! bit n to bit n data valid at PCMOUT
(data valid time)

tpd3

Transmit clockJ. bit 8 to bit 8 hi-Z at PCMOUT
(data float time on time slot exit) (see Note 6)

NOTE 6: Timing parameters tpd1 , tpd3, and tpd5 are referenced to the high-impedance state.

~TEXAS

INSTRUMENTS
2-132

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

absolute and relative delay times over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER

TEST CONDITION

Transmit absolute delay time to PCMOUT

Transmit differential envelope delay time
relative to transmit absolute delay time

Receive absolute delay time to PWRO

Receive differential envelope delay time
relative to transmit absolute delay time

All typical values are at VDD

MIN

TYPt

Fixed data rate,
MCLK = 2.048 MHz,
Input to ANLGIN 1.02 kHz at 0 dBmO

500

f = 500 Hz - 600 Hz

170

f = 600 Hz - 1000 Hz

f = 1000 Hz - 2600 Hz

f = 2600 Hz - 2800 Hz

105

Fixed data rate,
MCLK = 2.048 MHz,
Digital input is DMW codes

190

f = 500 Hz - 600 Hz

f = 600 Hz - 1000 Hz

f = 1000 Hz - 2600 Hz

f = 2600 Hz - 2800 Hz

110

MAX

UNIT

IlS

Il S

=5 V, and TA =25°C

w
:>
w
a:
c.
t-

oa:
c.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-133

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

0.15 dB

0.15 dB
CI)

'iii

en
'C
CI)

'C
I::

co
C.
><

-1

Typical Filter
Transfer Function

200 Hz

I
N

J:
~

,..

"tJ 'jO~

:rJ

o
C
c::

-I
"tJ

-10

-20

:-30

-30

-40

-50

oS
CI)

~
0::
I::

'jO

Cl
I

:rJ

=::

-60~~--~--~~~~~~

__~~~__~__~~~~~~~____~__~~-u~-u~~-60

100

1k
f - Frequency - Hz

NOTE B: For this figure, gain (voltage amplification) is defined as gain relative to gain at 1 kHz-dB

Figure 1. Transmit-Filter Transfer Characteristics

~TEXAS

2-134

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

10k

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

PARAMETER MEASUREMENT INFORMATION

0.15 dB

0.15 dB
3000 HZ

0.15 dB

20 Hz
-1

-a
I

...

.:.::

'Iii
c

'iii
CJ

-10

-14dB

III

:;
Gi

-20

5>
w

-20

a:
c..

'iii
CJ
I

Typical Filter
Transfer Function

-30

::::»
C

-40

oa:

-40

c..

-50

~--~~~~~----~--~~~~~------~--~-L-U-W~~~-60

100

10 k

f - Frequency - Hz

NOTE A: For this figure, gain (voltage amplification) is defined as gain relative to gain at 1 kHz-dB

Figure 2. Receive-Filter Transfer Characteristics

~TEXAS

INSTRUMENTS
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2-135

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

MCLK

td(FSX)1 ~
FSJ~--"'"

tpd1
PCMOUT----------~

t Bit 1 =MSB =most significant bit and is clocked in first on the PCMIN terminal or is clocked out first on the PCMOUT terminal.
t

Bit 8 = LSB = least significant bit and is clocked in last on the PCMIN terminal or is clocked out last on the PCMOUT terminal.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V when the high level is indicated and 0.8 V if the low
level is indicated.

"'tJ

Figure 3. PCM Transmit Timing

o
C
C

MCLK

111
I

II I
t
......-_",,71 ,- td(FSR) r

o-I
"'tJ

tsu(PCMIN)

-m

1\
II
I

-+-.i 14I 1---.1 *-

I
~

tc(MCLK)

td(PCMIN)

I
I
I
I
I

-1+---+1

PCMIN

Bit It
Valid

Bit 2
Valid

Bit3
Valid

Bit4
Valid

Bit5
Valid

Bit6
Valid

Bit7
Valid

Bit 8*
Valid

t Bit 1 = MSB = most significant bit and is clocked in first on the PCMIN terminal or is clocked out first on the PCMOUT terminal.
t

Figure 4. PCM Receive Timing

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

PRINCIPALS OF OPERATION
system reliability and design considerations
TCM38C17 system reliability and design considerations are described in the following paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the QCombo is heavily protected against latch-up, it is still possible to cause latch-up under certain
conditions in which excess current is forced into or out of one or more terminals. Latch-up can occur when the
supply voltage drops momentarily below ground or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted
into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between
the power supply and GND (see Figure 5). If it is possible that a QCombo-equipped card that has an edge
connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground edge
connector traces are longer than the power and signal traces so that the card ground is always the first to make
contact.

w
:>
w

a::

device power-up sequence
Latch-up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another Signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended that the following
power-up sequence always be used:
1.

Ensure that no Signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply power.

Force a power down condition in the device.

Connect the master clock.

Release the power down condition.

Apply FS synchronization pulses.

Apply the signal inputs.

oa::

When powering down the device, this procedure should be followed in the reverse order.

~TEXAS

INSTRUMENTS
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2-137

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

PRINCIPLES OF OPERATION

Vee
GNe
Figure 5. Latch-Up Protection Diode Connection
Internal sequencing

On the transmit channel, digital output PCMOUT is held in the high-impedance state for approximately four
frames (500 J.1S) after power up or application of Voo. After this delay, PCMOUT is functional and occurs in the
proper timeslot. Valid digital information, such as for on/off hook detection, is available almost immediately.
To further enhance system reliability, PCMOUT is placed in a high-impedance state approximately 20 J.1S after
an interruption of MCLK. This interruption could possibly occur with some kind of fault condition elsewhere in
the system.

"tJ

power-down operation

To minimize power consumption, a power-down mode is provided for each channel. To power down a channel,
an external logic low Signal is applied to the corresponding PDN terminal. It is not sufficient to remove the logic
high to PDN; in the absence of a signal, the PDN terminal floats to logic high and the device remains active.
In the power-down mode, the average power consumption is reduced to an average of 1 mW/channel.

o
C

o-I

"m
:0

miscellaneous
TCM38C17 timing and voltage references are described in the following paragraphs.
data timing

The TCM38C17 operates at 2.048 MHz using fixed-data-rate timing. An 8-kHz clock signal should be applied
to the FS terminal to set the sampling frequency. Data is transmitted on the PCMOUT terminal on the first eight
positive transitions of MCLK following the rising edge of FS. Data is received on the PCMIN terminal on the first
eight falling edges of MCLK following FS.

:em

precision voltage references

It is recommended that an external capacitor of 1-J.LF value be connected between REFLTR1 and AVSS and
between REFLTR2 and AVSS to ensure clean voltage references. Voltage references that determine the gain
and dynamic range characteristics of the device are generated internally. A band-gap mechanism is used to
derive a temperature-independent and bias-stable reference voltage. These references are calibrated during
the manufacturing process. Separate references are supplied to the transmit and receive sections, and each
is calibrated independently. Each reference value is then further trimmed in the gain-setting operational
amplifiers to a final precision value. Manufacturing tolerances of typically ±0.04 dB in absolute gain (voltage
amplification) can be achieved for each half channel, providing the user a significant margin to compensate for
error in other board components.

~TEXAS

2-138

INSTRUMENTS
"POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

PRINCIPALS OF OPERATION

transmit operation
TCM38C17 transmit operation is described in the following paragraphs.

transmit input amplifier
The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational
amplifier. Gain for the amplifier is set using external input and feedback resistors as shown in Figure 6. This
allows maximum flexibility in presetting volume levels. Unity gain can be achieved by assigning RI and RF equal
values. The feedback impedance between GSX and ANLGIN- should be greater than 10 kn in parallel with
less than 50 pF. GSX also provides a means of sampling the amplified signal.
GSX

>-----.

Ace

->w
W

External

Internal

A=- -

a:
a.

Figure 6. Transmit Path Gain Setting Circuitry
transmit filter
The transmit section filters provide passband flatness and stopband attenuation that fulfills the AT&T 03/04
channel bank transmission specification and CCITT recommendation G.712. The device specifications meet
or exceed digital class 5 central office switching systems requirements.
A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power lines;
17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency noise.
Even with the high rejection at these frequencies, the sharpness of the band edge gives low attenuation at
200 Hz. This feature allows the use of low-cost transformer hybrids without external components .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-139

I(.)

::J
C

a:
a.

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

PRINCIPALS OF OPERATION

receive operation
TCM38C17 receive operation is described in the following paragraphs.

receive filter
The receive section filters provide pass-band flatness and stopband rejection that fulfills both the AT&T 03/04
specification and CCITT recommendation G.712. The filter contains the required compensation for the (sin x)/x
response of such decoders.

output amplifier
The QCombo incorporates a versatile analog output power amplifier than can drive transformer hybrids or
low-impedance loads directly in either a single-ended or differential configuration. The QCombo output stage
allows for volume control (in the differential mode) by connection of a resistor chain to the output terminals of
the device. The inverting operational amplifier can drive a 600 Q load in parallel with 100 pF. Figure 7 is a
representation of the internal structure of the output amplifier.

"tJ

DAe

o
o
c

-...-'V'\I\r-_______---I

RGSR1

-I

"tJ

RGSR2

m
S
m

Unity Gain
Inverter

External

Figure 7. Output Amplifier Architecture

~TEXAS

INSTRUMENTS
2-140

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

APPLICATIONS INFORMATION
Various TCM38C17 output configurations are detailed in the following paragraphs.

differential configuration
For connection to a transformer, the fully differential configuration is recommended to provide maximum
possible output, or voltage swing, to the primary of an attached transformer. Figure 8 shows the aCombo in a
fully differential mode.
PWRO+ :.
R1
GSR

.~
>

.~ RL

R2 :~
PWRO- :.

Figure 8. Fully Differential Gain-Setting Configuration

PWRO+ and PWRO- are low-impedance complementary outputs. The total output available for the output load
(Rd is then Vo = Vo+ - Vo-. R1 and R2 form a gain-setting resistor network with a center tap connected to
the GSR input.
R1 + R2 should be greater than 10 kQ and less than 100 kQ because the parallel combination R1 + R2 and Rl
sets the total loading. The total parasitiC capacitance of the GSR input, along with the parallel combination of
R1 and R2, define a time constant that must be minimized to avoid inaccuracies in the gain calculations.
The resistor gain control actually consists of attenuating the full differential output voltage. The equation to
determine the value of the attenuation constant is given in equation 1.

3:
w
:;
w
a.

a:
tO

A = 1 + (R 1 + R2)
4 + (R1 + R2)

(1)

which can also be expressed as shown in equation 2.
_
R1 + R2
A - 4(R2 + R1 + 4).

(2)

where A = attenuation constant
Depending on the values of gain setting resistors R1 and R2, the attenuation constant (A) can have a value of
0.25 to unity (1), or approximately 12 dB of voltage adjustment.

~TEXAS

INSTRUMENTS
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2-141

0
a:
a.

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040 - JUNE 1996

APPLICATIONS INFORMATION

differential configuration (continued)
Maximum output (A = 1) can be obtained by maximizing R1 and minimizing R2. This can be done by letting
R1 = infinity and R2 = 0 n (common GSR and PWRO-), as shown in Figure 9. Referring to the transmit and
receive gain and dynamic range specifications, a maximum output of approximately 8 Vpp can be expected in
this configuration. See the maximum analog output section for more detail on the digital input required for
maximum analog output.
PWRO+ :
>

GSR ....

PWRO-

VO-

Figure 9. Fully Differential Maximum Gain-Setting Configuration (A = 1)

\J
:D

Figure 10 illustrates the QCombo with the resistor gain-control setting for an attenuation of A = 0.625.

o
C
c

PWRO+ :

10 kn .>

-I
\J
:D

GSR

PWRO-

m
S
m

2.5 kn .>>

RL
VO-

Figure 10. Fully Differential Mid-Gain-Setting Configuration (A = 0.625)

Shown in Figure 11, a minimum output (A =0.25 dB) can be obtained by letting R1
PWRO+), and R2 = infinity.
PWRO+

GSR ....
"
PWRO-

=0 n (common GSR and

....

VO-

Figure 11. Fully Differential Minimum-Gain-Setting Configuration (A

2-142

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=0.25)

TCM38C17
QCombo™ FOUR-CHANNEL (QUAD) PCM COMBO
SLWS040-JUNE 1996

APPLICATIONS INFORMATION

single-ended configuration
Figure 12 illustrates the QCombo in a typical single-ended configuration. Either of the outputs can be connected
through the load to analog ground (AGND), achieving an output'voltage swing that is one half of the fully
differential output voltage swing. Gain is set by manipulating the resistor network in the same way as detailed
for the differential mode. The single-ended mode is most commonly used when interfacing to a succeeding
stage that is referenced to analog ground.
PWRO+

GSR ....

R2
PWRO

<<>

: RL

...

Figure 12. Single-Ended Configuration

3:
>
w

a:
c.
Io

oa:
c.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-143

2-144

TP3054A,TP3057A, TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

•

Complete PCM Codec and Filtering
Systems Include:
- Transmit High-Pass and Low-Pass
Filtering
- Receive Low-Pass Filter With {sin x)/x
Correction
- Active RC Noise Filters
- Il-Law or A-Law Compatible Coder and
Decoder
- Internal Precision Voltage Reference
- Serial 1/0 Interface
- Internal Autozero Circuitry

•

Il-Law ... TP3054A and TP13054A

•

A-Law ... TP3057 A and TP13057 A

•
o

±5-V Operation
Low Operating Power ... 50 mW Typ

Power-Down Standby Mode ... 3 mW Typ

•
•

Automatic Power Down
TTL- or CMOS-Compatible Digital Interface

•

Maximizes Line Interface Card Circuit
Density

•

Improved Versions of National
Semiconductor TP3054, TP3057, TP3054-X,
TP3057-X

description
The TP3054A, TP3057A, TP13054A, and
TP13057A are comprised of a single-chip PCM
codec (pulse code-modulated encoder and
decoder) and PCM line filter. These devices
provide all the functions required to interface a
full-duplex (2-wire) voice telephone circuit with a
TDM (time-division-multiplexed) system. These
devices are pin-for-pin compatible with the
National Semiconductor TP3054A and TP3057 A,
respectively. Primary applications include:
•

Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital voice-band data-storage systems

•

Digital signal processing

ow OR

N PACKAGE

(TOP VIEW)

VBB
ANLG GNO
VFRO
Vee
FSR
OR
BCLKR/CLKSEL
MCLKR/PON

1
2

3
4
5
6
7

16 ] VFXI+
VFXIGSX
TSX
FSX
OX
BCLKX
9 MCLKX

15
14
13
12
11
10

These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3054A, TP3057A, TP13054A, and TP13057A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3057 A and
TP13057 A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below -55 dBmO.
The TP3054A and TP3057 A are characterized for operation from O°C to 70°C. The TP13054A and TP13057 A
are characterized for operation from -40°C to 85°C.

~~0~~~t~~~~0~:1~ sl;!~rfrc~~i~~si~e~~~:~!r~~ g: Ie~~~~~~~~m~~fs

standard warranty. Production processing does not necessarily Include
testing of all parameters.

•
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2-145

TP3054A, TP3057A,TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

functional block diagram
14

.------------------------------------------------------GSX
R2

Analog
Input
15 R1
VFXI- --'\A~_ _-t

SwitchedCapacitor
Band-Pass Filter

VFXI +_16______- 1

Transmit
Regulator

SwitchedCapacitor
low-Pass Filter

3
VFRO

Receive
Regulator

Power
Amplifier

VBB

ANlG GNO

MClKX

MClKR! BClKX BClKRI FSR FSX
PON
ClKSEl

~TEXAS

2-146

ClK

Timing and Control

Vec

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13
I-----TSX

TP3054A, TP3057A,TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

ANlG GND

Analog ground. All signals are referenced to ANlG GND.

BClKR/CLKSEl

The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
BClKR/ClKSEl can be a logic input that selects either 1.536 MHzl1.544 MHz or 2.048 MHz for the master clock in
the synchronous mode. BClKX is used for both transmit and receive directions (see Table 1).

The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous with
MClKX.

BClKX
DR

Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that is enabled by FSX.

FSR

Receive-frame sync pulse input that enables BClKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

FSX

Transmit-frame sync pulse that enables BClKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

GSX

Analog output of the transmit input amplifier. GSX is used to externally set gain.

MClKR/PDN

MClKX
TSX

9
13

Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MClKX, but should
be synchronous with MClKX for best performance. When MClKR is connected continuously low, MClKX is selected
for all internal timing. When MClKR is connected continuously high, the device is powered down.
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MClKR
Open-drain output that pulses low during the encoder time slot

=-5 V ±5%
= 5 V ±5%

VBB

Negative power supply. VBB

VCC

Positive power supply. VCC

VFRO

Analog output of the receive filter

VFXI+

Noninverting input of the transmit input amplifier

VFXI-

Inverting input of the transmit input amplifier

•
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TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Supply voltage, Vss (see Note 1) ............................................................ -7 V
Voltage range at any analog input or output ............................... Vee +0.3 V to Vss -0.3 V
Voltage range at any digital input or output .......................... Vee +0.3 V to ANLG GND -0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: TP3054A, TP3057 A ............................... O°C to 70°C
TP13054A, TP13057A .......................... -40°C to 85°C
Storage temperature range ........................................................ -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE

DERATING FACTOR
ABOVE TA 25°C

1025 mW

8.2 mW/oC

656mW

533mW

1150mW

9.2 mW/oC

736mW

598mW

TA 70°C
POWER RATING

PACKAGE

TA S 25°C
POWER RATING

TA 85°C
POWER RATING

recommended operating conditions (see Note 2)
MIN

NOM

MAX

UNIT

Supply voltage, Vce

4.75

5.25

Supply voltage, VSB

-4.75

-5

-5.25

V
V

2.2

High-level input voltage, VIH

0.6

Low-level input voltage, VIL

±2.5

Common-mode input voltage range, VICR:j:

Load capacitance, GSX, CL

ITP3054A, TP3057A
ITP13054A, TP13057A

Operating free-air temperature, TA

V
kO

Load resistance, GSX, RL

-40

pF
°C

:j: Measured with CMRR > 60 dS.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.

electrical characteristics over recommended ranges of supply voltage operating free-air
temperature range (unless otherwise noted)
supply current
PARAMETER

TEST CONDITIONS
Power down

ICC

Supply current from VCC

ISS

Supply current from VSS

TP305xA
MIN

No load

Active
Power down
Active

No load

~TEXAS

INSTRUMENTS
2-148

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TYP*

TP1305xA
MAX

MIN

TYP*

MAX

0.5

1.2

0.5

1.2

UNIT

TP3054A, TP3057A,TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

electrical characteristics at Vee = 5 V ±5%, VBB = -5 V ±5%, GND at 0 V, TA = 25°C (unless
otherwise noted)
digital interface
PARAMETER
VOH

TEST CONDITIONS

High-level output voltage

IH = -3.2 mA

IL= 3.2 mA

TSX

IL= 3.2 mA,

MIN

MAX

2.4

UNIT
V

0.4

VOL

Low-level output voltage

IIH

High-level input current

VI = VIH to VCC

±10

IlL

Low-level input current

All digital inputs

VI = GND to VIL

±10

IOZ

Output current in high-impedance state

Vo = GND to VCC

±10

MAX

UNIT

Drain open

0.4

V
~A

analog interface with transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current

VFXI + or VFXI -

VI =-2.5 Vto 2.5 V

Input resistance

VFXI + or VFXI -

VI = -2.5 V to 2.5 V

Output resistance

MIN

±200
10

Closed loop, Unity gain

Output dynamic range

GSX

Open-loop voltage amplification

VFXI+toGSX

RL~

TYPt

nA
Mn

10 kn

±2.8

5000

Unity-gain bandwidth

GSX

VIO

Input offset voltage

VFXI + or VFXI -

CMRR

Common-mode rejection ratio

KSVR

Supply-voltage rejection ratio

MHz

2
±20

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
analog interface with receive filter
PARAMETER
Output resistance

TEST CONDITIONS

MIN

IVFRO

Load resistance

VFRO =±2.5 V

TYPt

MAX

600

UNIT
n
n

Load capacitance

I VFROto GND

500

Output dc offset voltage

IVFROto GND

±200

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

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2-149

TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

timing requirements
TEST CONDITIONS

PARAMETER

MIN

TYPt

MAX

1.S36
1.S44
2.048

fclock(M)

Frequency of master clock

MCLKX and
MCLKR

fclock(B)

Frequency of bit clock, transmit

BCLKX

tw1

Pulse duration, MCLKX and MCLKR high

160

tw2

Pulse duration, MCLKX and MCLKR low

160

tr1

MCLKX and
MCLKR

Rise time of master clock

Depends on the device used and
BCLKXlCLKSEL

UNIT

MHz
2048

kHz

Measured from 20% to 80%

tf1

Fall time of master clock

MCLKX and
MCLKR

tr2

Rise time of bit clock, transmit

BCLKX

tf2

Fall time of bit clock, transmit

BCLKX

tsu1

Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKXJ.

First bit clock after the leading
edge of FSX

tW3

Pulse duration, BCLKX and BCLKR high

VIH = 2.2 V

160

tw4

Pulse duration, BCLKX and BCLKR low

VIL = 0.6 V

160

th1

Hold time, frame sync low after bit clock low
(long frame only)

th2

Hold time, BCLKX high after frame synci
(short frame only)

tsu2

Setup time, frame sync high before bit clockJ.
(long frame only)

td1

Delay lime, BCLKX high to data valid

td2

Delay time, BCLKX high to TSX low

td3

Delay time, BCLKX (or 8 clock FSX in long frame only)
low to data output disabled

td4

Delay time, FSX or BCLKX high to data valid (long
frame only)

Measured from 20% to 80%

100

80
Load = 1S0 pF plus 2 LSTTL loads+

140

16S

165

Load = 150 pF plus 2 LSTTL loads+

CL = 0 pF to 1S0 pF

tsu3

Setup time, DR valid before BCLKRJ.

th3

Hold time, DR valid after BCLKR or BCLKXJ.

tsu4

Setup time, FSR or FSX high before BCLKR or
BCLKRJ.

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

th4

Hold time, FSX or FSR high after BCLKX or BCLKRJ.

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

100

thS

Hold time, frame sync high after bit clockJ.

Long-frame sync pulse
(from 3 to 8 bit clock periods long)

100

tws

Minimum pulse duration of the frame sync pulse
(low level)

64 kbps operating mode

160

All typical values are at VCC = S V, VBB = -S V, and TA = 2SoC.
+ Nominal input value for an LSTTL load is 18 kil.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high .

•
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TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

operating characteristics, over operating free-air temperature range, Vee =5 V ±5%,
Vee =-5 V ±5%, GND at 0 V, VJ =1.2276 V, f =1.02 kHz, transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)
filter gains and tracking errors
PARAMETER

Maximum peak transmit overload level

TEST CONDITIONS+

I TP3054A, TP13054A

ITP3057A,TP13057A

Transmit filter gain, absolute (at 0 dBmO)

MIN

TYPt

3.17 dBmO

2.501

3.14dBmO

20492
-0.15

TA = 25°C
f = 50 Hz

-30
-1.8

-0.1

f = 300 Hz to 3000 Hz

-0.15

0.15

f = 3300 Hz

-0.35

0.05

f = 3400 Hz

-0.8

0
-14

f = 4000 Hz
~

-26

f= 200 Hz

4600 Hz (measure response from

-32

o Hz to 4000 Hz)
Absolute transmit gain variation with temperature and supply
voltage

0.15
-40

UNIT

f= 16 Hz
f = 60 Hz

Transmit filter gain, relative to absolute

MAX

Relative to absolute transmit gain

-0.1

0.1

±0.2

Sinusoidal test method,
Reference level = -10 dBmO
3 dBmO

Transmit gain tracking error with level

input level

-40 dBmO

-40 dBmO > input level

-50 dBmO

±Oo4

-50 dBmO > input level

-55 dBmO

±O.8

Input is digital code sequence for
O-dBmO signal,
TA= 25°C

Receive filter gain, absolute (at 0 dBmO)

-0.15

0.15

-0.35

0.05

f = 3400 Hz

-0.8

TA = 25°c

-14

f = 4000 Hz
Absolute receive gain variation with temperature and supply
voltage

0.15

f = 3300 Hz

f = 0 Hz to 3000 Hz,
Receive filter gain, relative to absolute

-0.15

See Note 4

TA = full range,

-0.1

0.1

Sinusoidal test method; reference
input PCM code corresponds to an
ideally encoded -10 dBmO signal
Receive gain tracking error with level

3 dBmO ~ input level

Receive output drive voltage

-40 dBmO
~

-50 dBmO

±Oo4

-50 dBmO > input level

-55 dBmO

±0.8
±2.5

RL= 10 kQ

Transmit and receive gain tracking error with level (A-law,
CCITIC 712)

±0.2

-40 dBmO > input level

Pseudo-noise test method; reference
input PCM code corresponds to an
ideally encoded -10 dBmO signal
3 dBmO ~ input level

-40 dBmO

±0.25

-40 dBmO > input level

-50 dBmO

±0.3

-50 dBmO > input level

-55 dBmO

±Oo45

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

+Absolute rms signal levels are defined as follows: VI = 1.2276 V = 0 dBmO = 4 dBm at f = 1.02 kHz with RL = 600 Q.
NOTE 4: Full range for the TP3054A and TP3057 A is O°C to 70°C. Full range for the TP13054A and TP13057 A is -40°C to 85°C.

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TP3054A, TP3057A,TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

envelope delay distortion with frequency
PARAMETER

TEST CONDITIONS

= 1600 Hz
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz'
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz

Transmit delay, absolute (at 0 dBmO)

MIN

Transmit delay, relative to absolute

Receive delay, absolute (at 0 dBmO)

Receive delay, relative to absolute

TYPt

MAX

UNIT

290

315

Jls

195

220

120

145

105

Jls

130

155

180

200

Jls

-40

-25

-30

-20
70

100

125

140

175

TYPt

MAX

noise
PARAMETER

TEST CONDITIONS

MIN

UNIT

Transmit noise, C-message weighted

TP3054A,
TP13054A

VFXI

=0 V

dBrnCO

Transmit noise, psophometric weighted
(see Note 5)

TP3057A,
TP13057A

VFXI

=0 V

-78

-75

dBmOp

Receive noise, C-message weighted

TP3054A,
TP13054A

PCM code equals alternating positive
and negative zero

dBrnCO

Receive noise, psophometric weighted

TP3057A,
TP13057A

PCM code equals positive zero

-86

-83

dBmOp

-53

dBmO

f =0 kHz to 100 kHz,
VFXI+ =0 V,
Loop-around measurement

Noise, single frequency

t All typical values are at VCC = 5 V, VBB =-5 V, and TA =25°C.
NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite Signals on the transmit side are below -55 dBmO.

~TEXAS

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MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

power supply rejection
TEST CONDITIONS

PARAMETER

Positive power-supply rejection, transmit

Negative power-supply rejection, transmit

Positive power-supply rejection, receive

Negative power-supply rejection, receive

VCC = 5 V + 100 mVrms,
VFXI+ =-50 dBmO

f
f

VBB =-5 V + 100 mVrms,
VFXI+ =-50 dBmO

f
f

= 0 Hz to 4 kHz

=0 Hz to 4 kHz

f
f

PCM code equals positive zero,
VBB =-5 V + 100 mVrms

dBCt

lA-law

Ill-law

dBCt

lA-law

.11l-law

dBCt

lA-law

.11l-law

dBCt

. dB

=4 kHz to 50 kHz

f = 4 kHz to 50 kHz
o dBmO, 300-Hz to 3400-Hz input applied to DR (measure individual

-30

image signals at VFRO)
Spurious out-of-band signals at the
channel output (VFRO)

UNIT

Ill-law

=4 kHz to 50 kHz

=0 Hz to 4 kHz

MAX

=4 kHz to 50 kHz

f = 0 Hz to 4 kHz

PCM code equals positive zero,
VCC = 5 V + 100 mVrms

MIN

lA-law

=4600 Hz to 7600 Hz
=7600 Hz to 8400 Hz
f = 8400 Hz to 100 kHz

-33

-40

distortion
PARAMETER

TEST CONDITIONS

MIN

= 3 dBmO
Level = 0 dBmO to - 30 dBmO
Signal-to-distortion ratio, transmit or receive half-channert:

Level

=-40 dBmO

Level

=-55 dBmO

MAX

UNIT

Level

36
Transmit

Receive

Transmit

Receive

dBCt

Single-frequency distortion products, transmit

-46

Single-frequency distortion products, receive

-46

-41

Loop-around measurement,
VFXI + =-4 dBmO to -21 dBmO,
Two frequencies in the range of 300 Hz to 3400 Hz

Intermodulation distortion

=-3 dBmO
=-6 dBmO to -27 dBmO
Level =-34 dBmO
Level =-40 dBmO
Level =-55 dBmO
Level =-3 dBmO
Level =-6 dBmO to -27 dBmO
Level =-34 dBmO
Level =-40 dBmO
Level =-55 dBmO
Level

Level

Signal-to-distortion ratio, transmit half-channel (A-law)
(CCITT G.714)§

Signal-to-distortion ratio, receive half-channel (A-law)
(CCITT G.714)§

33
36
33.5

28.5
13.5
33
36
34.2

30
15

t The Unit dBC applies to C-message weighting.
:t: Sinusoidal test method (see Note 6)
§ Pseudo-noise test method
NOTE 6: The TP3054A and TP13054A are measured using a C-message weighted filter. The TP3057 A and TP13057 A are measured using a
psophometric weighted filter.

•
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TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

crosstalk
TYPt

MAX

UNIT

Crosstalk, transmit to receive

PARAMETER

f = 300 Hz to 3000 Hz,

TEST CONDITIONS
DR at steady PCM code

-90

-75

Crosstalk, receive to transmit (see Note 7)

VFXI=OV,

f = 300 Hz to 3000 Hz

-90

-75

MIN

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
NOTE 7:

Receive-to-transmit crosstalk is measured with a-50 dBmO activation signal applied at VFXI +.

PARAMETER MEASUREMENT INFORMATION
~ 14- td3
I -\--..;2;;;;.0;.;.yo_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ I fIJ 20"10

-+j j4- td2
TSX ------~I\1
tr1 ---+j 14-

MClKX
MClKR

II
II

--JIII.- tf1

I
I

fclock(M)

i4----J*_

I
I
I
I
I

BClKX

FSX

I
I
I
I
I

----...I

BClKR

th2 --.j

j4-11
II

II
II
II
II

I
I
I
I

--.: tt- tsu4
I

FSR

~th4

r:::-\~.--------------------------~Ii-----------~I------I:
I
80"10

_ _ _ _ _ _ 20"10

tsu3

____________ ___ _____ ___ _____ ____
~

Figure 1. Short-Frame Sync Timing

~TEXAS

INSTRUMENTS
2-154

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

I
I
I

I4--+t- th3
I
I

--+I*I

th3

~--~----J~--~------

TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
t
r1

----.II.-

tw1

~
I
I,_
I

~,I
r---rr

- - - + I - fclock(M)

1.
4.
-1

II
II ~ j+-

tl1l

-.! I+- tr2

tw2

MClKR
tsu1

BClKX

tsu1~ I+20% 89% 1
I

th1

---+I

FSX

800;.-tf

T----------r-\

td4

td1

-J ~

2
X 3
4
tW 3:::::r;..:;J
I
11.-.1- tw4

BClKR

th5

\~.----------~I----------·----~I--T~---

l---+l I+--J+-----+j i

-----ft

fclock(B)

j480% ~

tsu2

----~2=0%~lr~1
td4

td3

---l

1
1

G:I~::
td3

1 800;.

Figure 2. Long-Frame Sync Timing

"TEXAS
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TP3054A,TP3057A, TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
TP305xA, TP1305xA system reliability and design considerations are described in the following paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP305xA and TP1305xA are heavily protected against latch-up, it is still possible to cause
latch-up under certain conditions in which excess current is forced into or out of one or more terminals. Latch-up
can occurwhen the positive supply voltage drops momentarily below ground, when the negative supply voltage
rises momentarily above ground, or possibly if a signal is applied to a terminal after power has been applied
but before the ground is connected. This can happen if the device is hot-inserted into a card with the power
applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted into a
system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP305xA- or TP1305xA-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.

Ensure that no Signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply Vss (most negative voltage).

Apply Vee (most positive voltage).

Force a power down condition in the device.

Connect clocks.

Release the power down condition.

Apply FS synchronization pulses.

Apply the Signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

2-156

"TEXAS
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TP3054A, TP3057A,TP13054A,TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC
DGND

Vee
Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3054A, TP3057A, TP13054A, and TP13057A devices when power
is first applied, placing it into the power-down mode. OX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MClKR/PON powers up the device and
activates all circuits. OX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.

synchronous operation
For synchronous operation, a clock is applied to MClKX. MClKR/PON is used as a power-down control. A low
level on MClKR powers up the device and a high level powers it down. In either case, MClKX is selected as
the master clock for both receive and transmit direction. BClKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BClKRlClKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BClKR/ClKSEl selects BClKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BClKR/ClKSEL.
In the synchronous mode, BClKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
Table 1. Selection of Master-Clock Frequencies

eCLKRlCLKSEL

MASTER-CLOCK FREQUENCY SELECTED
TP13057A,TP3057A
TP13054A,TP3054A

Clock Input

1.536 MHz or 1.544 MHz

2.048 MHz

Logic Input L
(sync mode only)

2.048 MHz

1.536 MHz or 1.544 MHz

Logic Input H (open)
(sync mode only)

1.536 MHz or 1.544 MHz

2.048 MHz

The encoding cycle begins with each FSX pulse and the PCM data from the previous cycle is shifted out of the
enabled OX output on the rising edge of BClKX. After eight bit-clock periods, the 3-state OX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via OR on the falling edge of BClKX (or
BClKR, if running). FSX and FSR must be synchronous with MClKX and MClKR .

•
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TP3054A, TP3057A, TP13054A, TP13057A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3057 A and TP13057 A, 1.536 MHz or 1.544 MHz for the TP3054A and TP13054A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PON. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.

short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCLKX, the next rising edge of BCLKX
enables the 3-state output buffer, OX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables OX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.

long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, whichever occurs later, enables the OX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth riSing edge or FSX going low, whichever
occurs later, disables OX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at OR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.

transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per /l-Iaw (TP3054A and TP13054A) or A-law (TP3057 A
and TP13057A) coding conventions, the AOC is a companding type. A precision voltage reference provides a
nominal input overload (t[max]) of nominally 2.5 V peak. The sampling of the filter output is controlled by the FSX
frame-sync pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a
buffer and shifted out through OX at the next FSX pulse. The total encoding delay is approximately 290 /ls. Any
offset voltage due to the filters or comparator is cancelled by sign-bit integration.

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MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

PRINCIPLES OF OPERATION
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is J..l-Iaw (TP3054A and TP13054A) or A-law (TP3057A and TP13057A) and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post-filter/power amplifier capable of driving a 600-Q load to a level of 7.2 dBm. The
receive section is unity gain. At FSR, the data at DR is clocked in on the falling edge of the next eight BClKR
(BClKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10 J..ls later, the decoder
DAC output is updated. The decoder delay is about 10 J..ls (decoder update) plus 110 J..ls (filter delay) plus
62.5 J..ls (1/2 frame), or a total of approximately 180 J..ls .

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MONOLITHIC SERIAL INTERFACE
COMBINED PCM COOEC AND FILTER
SCTS026C - SEPTEMBER 1992 - REVISED JULY 1996

APPLICATION INFORMATION

power supplies
While the pins of the TP1305xA and TP305xA families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and Vss
supplies should be decoupled by connecting O.1-IlF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to Vee and Vss.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to Vee
and Vss with 10-IlF capacitors.
16

VBB

Fr om SLiC

VFXI+
15

0.1 IlF ::::::;:::
2

J-

VFXI
ANLG GND
14 R1

- 0.1IlF::::~

GSX
4
VCC

5V
To SLiC

VFRO

TP3054A
TP3057A
TP13054A
TP13057A

-1
Analog Interface

- - - - - - - - ------------- - - - - - - - 5

FSR

FSX

OX
Da ta In
5VorG NO

6
7
8

PDN

Digital
Interface

DR
BCLKR/CLKSEL

BCLKX

MCLKRlPDN

MCLKX

NOTE A: Transmit gain = 20 log

(R1:2 R2), (R1 + R2)

:2:

10 kQ

Figure 4. Typical Synchronous Application

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0 ut

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BC LKX (2.048 MHzl1.544 MHz)

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

•

Complete PCM Co dec and Filtering
Systems Includes:
- Transmit High-Pass and Low-Pass
Filtering
- Receive Low-Pass Filter With (sin x)/x
Correction
- Active RC Noise Filters
- Jl-Law or A-Law Compatible Coder and
Decoder
- Internal Precision Voltage Reference
- Serial I/O Interface
- Internal Autozero Circuitry

•

Jl-Law - TP30548 and TP130548

•

A-Law - TP30578 and TP130578

•
•

±5-V Operation
Low Operating Power ... 50 mW Typ

•

Power-Down Standby Mode ... 3 mW Typ

•
•

Automatic Power Down
TTL- or CMOS-Compatible Digital Interface

•

Maximizes Line Interface Card Circuit
Density

Improved Versions of National
Semiconductor TP3054, TP3057, TP3054-X,
TP3057-X

description

ow OR

The TP3054B, TP3057B, TP13054B, and
TP13057B are comprised of a single-chip PCM
codec (pulse-code-modulated encoder and decoder) and PCM line filter. These devices provide
all the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TOM
(time-division-multiplexed) system. These devices are pin-for-pin compatible with the National
Semiconductor TP3054B and TP3057B, respectively. Primary applications include:
•

N PACKAGE

(TOP VIEW)

VBB
ANLG GNO
VFRO
VCC
FSR
OR
BCLKR/CLKSEL
MCLKR/PON

1 U 16
2

5
6
7

12
11
10

VFXI+
VFXIGSX
TSX
FSX
OX
BCLKX
MCLKX

Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital voice-band data-storage systems

Digital signal processing

These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (DIA
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3054B, TP3057B, TP13054B, and TP13057B provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3054B and
TP13054B contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below -55 dBmO.
The TP3054B and TP3057B are characterized for operation from O°C to 70°C. The TP13054B and TP13057B
are characterized for operation from -40°C to 85°C.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

•
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2-161

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A- MAY 1990- REVISED JULY 1996

functional block diagram
14

r-----------------------------------------------------~GSX

Analog
Input
VFXI- 15

SwitchedCapacitor
Band-Pass Filter

VFXI + 1_6_ _ _ _ _-t

Transmit
Regulator

SwitchedCapacitor
Low-Pass Filter

3
VFRO - - - - - - <

Receive

~-----f Regulator

Power
Amplifier

CLK

Timing and Control

Vcc

VBB

ANLG GNO

MCLKX

MCLKRI BCLKX BCLKRI FSR FSX
PON
CLKSEL

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2-162

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TP3054B, TP3057B,TP13054B,TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A- MAY 1990- REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

ANlG GND

Analog ground. All signals are referenced to ANlG GND.

BClKRlClKSEl

The bit clock that shifts out the PCM data on DX. BClKX can vary from 64 kHz to 2.048 MHz, but must be synchronous
with MClKX.

BClKX
DR

FSR

Receive frame-sync pulse input that enables BClKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

FSX

Transmit frame-sync pulse that enables BClKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

GSX

Analog output of the transmit input amplifier. GSX is used to externally set gain.

MClKR/PDN

MClKX
TSX

9
13

Receive data input. PCM data is shifted into DR following the FSR leading edge.
The 3-state PCM data output that in enabled by FSX

Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MClKX, but should
be synchronous with MClKX for best performance. When MClKR is connected continuously low, MClKX is selected
for all internal timing. When MClKR is connected continuously high, the device is powered down.
Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MClKR.
Open-drain output that pulses low during the encoder time slot

=-5 V ±5%
=5 V ±5%

VBB

Negative power supply pin. VSS

VCC

Positive power supply pin. VCC

VFRO

Analog output of the receive filter

VFXI+

Noninverting input of the transmit input amplifier

VFXI-

Inverting input of the transmit input amplifier

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2-163

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A- MAY 1990 - REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Supply voltage, Vss (see Note 1) ............................................................ -7 V
Voltage range at any analog input or output ............................... Vee +0.3 V to Vas -0.3 V
Voltage range at any digital input or output .......................... Vee +0.3 V to ANLG GND -0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA: TP30548, TP30578 .......................... O°C to 70°C
TP130548, TP130578 ...................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GNO.
DISSIPATION RATING TABLE
PACKAGE

TA $ 25°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

1150mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

8.2 mW/oC

656mW

533mW

9.2 mW/oC

736mW

598mW

recommended operating conditions (see Note 2)
UNIT

MIN

NOM

MAX

Supply voltage, VCC

4.75

5.25

Supply voltage, VBB

-4.75

-5

-5.25

High-level input voltage, VIH

0.6

Common-mode input voltage range, VICR+

±2.5

Load resistance, GSX, RL

ITP3054B, TP3057B
ITP13054B,TP13057B

V
V

Load capacitance, GSX, CL
Operating free-air temperature, TA

2.2

Low-level input voltage, VIL

-40

pF
°C

+ Measured with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed .

•
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INSTRUMENTS
2-164

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current
PARAMETER

ICC

Supply current from Vec

ISS

Supply current from VBB

TEST CONDITIONS
Power down

TP305xB
MIN

TYP

No load

Active
Power down

No load

Active

TP1305xB
MAX

MIN

TYP

MAX

0.5

1.2

0.5

1.2

UNIT

electrical characteristics at Vee = 5 V ±5%, Vee = -5 V ±5%, GND at 0 V, TA = 25°C (unless otherwise
noted)
digital interface
PARAMETER
VOH
VOL

Low-level output voltage

MIN

TEST CONDITIONS

High-level output voltage

IH =-3.2 mA

IL = 3.2 mA

TSX

IL = 3.2 mA,

MAX

2.4

V
0.4

Drain open

UNIT

0.4

IIH

High-level input current

VI = VIH to Vce

±10

JlA

IlL

Low-level input current

All digital inputs

VI = GNO to VIL

±10

)lA

VOL

Output current in high-impedance state

Vo = GNO to Vee

±10

JlA

MAX

UNIT

analog interface with transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current

VFXI + or VFXI -

VI = -2.5 V to 2.5 V

Input resistance

VFXI + or VFXI -

VI = -2.5 V to 2.5 V

Output resistance

Closed loop,

Output dynamic range

GSX

Open-loop voltage amplification

VFXI+ to GSX

RL~

MIN

TYPt

±200

Unity gain

nA
MQ

10
1

10 kQ

±2.B

5000

Unity-gain bandwidth

GSX

VIO

Input offset voltage

VFXI + or VFXI -

CMRR

Common-mode rejection ratio

KSVR

Supply-voltage rejection ratio

MHz
±20

t All tYPical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

analog interface with receive filter
PARAMETER
Output resistance

TEST CONDITIONS

MIN

IVFRO

Load resistance

VFRO =±2.5 V

TYPt

MAX

UNIT
Q

600

Load capacitance

I VFROtoGND

500

Output dc offset voltage

IVFROto GNO

±200

t All typical values are at Vce = 5 V, VSB = -5 V, and TA = 25°C.

~TEXAS

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2-165

TP30548, TP30578, TP130548, TP130578
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

operating characteristics, over operating free-air temperature range, Vee 5 V ±5%,
Vee =-5 V ±5%, GND at 0 V, VI =1.2276 V, f =1.02 kHz; transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)
timing requirements
PARAMETER

TEST CONDITIONS

fclock(M)

Frequency of master clock

MCLKX and
MCLKR
BCLKX

MIN

TYPt

MAX

1.536
1.544
2.048

Depends on the device used and
BCLKXJCLKSEL
64

UNIT
MHz

fclock(B)

Frequency of bit clock, transmit

tw1

Pulse duration, MCLKX and MCLKR high

160

tw2

Pulse duration, MCLKX and MCLKR low

160

2.048

kHz

Rise time of master clock

MCLKX and
MCLKR

Measured from 20% to 80%

tf1

Fall time of master clock

MCLKX and
MCLKR

Measured from 20% to 80%

tr1

tr2

Rise time of bit clock, transmit

BCLKX

Measured from 20% to 80%

tf2

Fall time of bit clock, transmit

BCLKX

Measured from 20% to 80%

tsu1

Setup time, BCLKX high (and FSX in long-frame sync
mode) before MCLKXJ,

First bit clock after the leading edge
of FSX

=2.2 V
=0.6 V

100

160

tw3

Pulse duration, BCLKX and BCLKR high

VIH

tw4

Pulse duration, BCLKX and BCLKR low

VIL

th1

Hold time, frame sync low after bit clock low
(long frame only)

th2

Hold time, BCLKX high after frame synci
(short frame only)

tsu2

Setup time, frame sync high before bit clockJ,
(long frame only)

td1

Delay time, BCLKX high to data valid

Load

td2

Delay time, BCLKX high to TSX low

Load

td3

Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled

td4

Delay time, FSX or BCLKX high to data valid
(long frame only)

= 150 pF plus 2 LSTTL loads+
= 150 pF plus 2 LSTTL loads+

CL = 0 pF to 150 pF

140

165

tsu3

Setup time, DR valid before BCLKRJ,

th3

Hold time, DR valid after BCLKR or BCLKXJ,

tsu4

Setup time, FSR or FSX high before BCLKR or
BCLKRJ.-

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

th4

Hold time, FSX or FSR high after BCLKX or BCLKRJ,

Short-frame sync pulse (1 or 2 bit
clock periods long) (see Note 3)

100

th5

Hold time, frame sync high after bit clockJ,

Long-frame sync pulse (from 3 to
8 bit clock periods long)

100

tW5

Minimum pulse duration of the frame sync pulse
(low level)

64 kbps operating mode

160

t All typical values are at VCC = 5 V, VBB =-5 V, and TA =25°C.
+ Nominal input value for an LSTTL lead is 18 kn.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.

~TEXAS

INSTRUMENTS
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TP3054B,TP3057B, TP13054B,TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

filter gains and tracking errors
PARAMETER
Maximum peak transmit overload level

TEST CONDITIONS*

ITP3054B, TP13054B
ITP3057B, TP13057B

Transmit filter gain, absolute (at 0 dBmO)

MIN

2.501

3.14 dBmO

20492

-0.15

TA= 25°C

0.15

f = 50 Hz

-30

-0.1

f = 300 Hz to 3000 Hz

-0.15

0.15

-0.35

0.05

f = 3400 Hz

-0.8

0
-14

f = 4000 Hz
~

-26
-1.8

f = 3300 Hz

UNIT
V

-40

f = 200 Hz

4600 Hz (measure response from

-32

o Hz to 4000 Hz)

Absolute transmit gain variation with temperature.and supply
voltage

MAX

f= 16 Hz

f = 60 Hz

Transmit filter gain, relative to absolute

TYPt

3.17 dBmO

Relative to absolute transmit gain
See Note 4

-0.1

0.1

±0.2

Sinusoidal test method,
Reference level = -10 dBmO
3 dBmO

Transmit gain tracking error with level

Receive filter gain, absolute (at 0 dBmO)

Receive filter gain, relative to absolute

input level

-40 dBmO

-40 dBmO > input level

-50 dBmO

±Oo4

-50 dBmO > input level

-55 dBmO

±0.8

Input is digital code sequence for
o dBmO signal,
TA = 25°C

-0.15

0.15

f = 0 Hz to 3000 Hz,

-0.15

0.15

f = 3300 Hz

-0.35

0.05

=3400 Hz

-0.8

TA = 25°C

-14

f = 4000 Hz
Absolute receive gain variation with temperature and supply
voltage

TA = full range,

See Note 4

-0.1

0.1

±0.2

Sinusoidal test method; reference
input PCM code corresponds to an
ideally encoded -10 dBmO signal
Receive gain tracking error with level

3 dBmO ~ input level

Receive output drive voltage

-40 dBmO

-40 dBmO > input level

-50 dBmO

±Oo4

-50 dBmO > input level

-55 dBmO

±0.8

RL = 10 kQ

Transmit and receive gain tracking error with level (A-law,
CCIITC712)

±2.5

±0.25

PseudO noise test method; reference
input PCM code corresponds to an
ideally encoded -10 dBmO signal
3 dBmO ~ input level

~ -40

dBmO

-40 dBmO > input level

-50 dBmO

±0.3

-50 dBmO > input level

-55 dBmO

±Oo45

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
:j: Absolute rms signal levels are defined as follows: V, = 1.2276 V = 0 dBmO = 4 dBm at f = 1.02 kHz with RL = 600 Q.
NOTE 4: Full range for the TP3054B and TP3057B is O°C to 70°C. Full range for the TP13054B and TP13057B is -40°C to 85°C .

•
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2-167

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

envelope delay distortion with frequency
PARAMETER

TYPt

MAX

UNIT

f = 1600 Hz

290

315

Il s

= 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz

195

220

120

145

TEST CONDITIONS

Transmit delay, absolute (at 0 dBmO)

MIN

Transmit delay, relative to absolute

Receive delay, absolute (at 0 dBmO)

Receive delay, relative to absolute

105

130

155

180

200

-40

-25

-30

-20
70

100

125

140

175

TYPt

MAX

Il s

Ils

t All typical values are at VCC = 5 V, VBB =-5 V, and TA =25°C.
noise
PARAMETER

TEST CONDITIONS

MIN

UNIT

Transmit noise, C-message weighted+

TP3054B,
TP13054B

VFXI

=OV

dBrnCO

Transmit noise, psophometric weighted
(see Note 5)

TP3057B,
TP13057B

VFXI

=0 V

-74

-69

dBmOp

Receive noise, C-message weighted

TP3054B,
TP13054B

PCM code equals alternating positive
and negative zero

dBrnCO

Receive noise, psophometric weighted

TP3057B,
TP13057B

PCM code equals positive zero

-86

-83

dBmOp

-53

dBmO

Noise, single frequency

VFXI+ =OV,
f = 0 kHz to 100 kHz,
Loop-around measurement

t All typical values are at VCC = 5 V, VBB =-5 V, and TA = 25°C.
+This parameter is achieved through use of patented circuitry and is not recommended for applications in which the composite signals on the
transmit side are below -55 dBmO.
NOTE 5: Measured by extrapolation from the distortion test result.

~TEXAS

INSTRUMENTS
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TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

power supply rejection
PARAMETER

Positive power-supply rejection, transmit

TEST CONDITIONS

I = 0 Hz to 4 kHz

VCC = 5 V + 100 mVrms,
VFXI+ = -50 dBmO

MIN

I = 0 Hz to 4 kHz

VBB = -5 V + 100 mVrms,
VFXI+ = -50 dBmO

Ill-law

dBCt

lA-law

Ill-law

dBCt

I = 4 kHz to 50 kHz
Positive power-supply rejection, receive

I = 0 Hz to 4 kHz

PCM code equals positive zero,
VCC = 5 V + 100 mVrms

lA-law

Ill-law

dBCt

lA-law

Ill-law

dBCt

I = 4 kHz to 50 kHz
Negative power-supply rejection, receive

I = 0 Hz to 4 kHz

PCM code equals positive zero,
VBB = -5 V + 100 mVrms

I = 4 kHz to 50 kHz

o dBmO, 300-Hz to 3400-Hz input applied to DR (measure individual
Spurious out-ol-band signals at the
channel output (VFRO)

UNIT

I = 4 kHz to 50 kHz
Negative power-supply rejection, transmit

MAX

lA-law

-30

image signals at VFRO)
I = 4600 Hz to 7600 Hz

-33

1= 7600 Hz to 100 kHz

-40

dB
dB

t The Unit dBC applies to C-message weighting.

distortion
PARAMETER

TEST CONDITIONS

MIN

Level = 3 dBmO
Level = 0 dBmO to -30 dBmO
Signal-to-distortion ratio, transmit or receive hall-channel+

Level = -40 dBmO

Level = -55 dBmO

MAX

UNIT

33
36
Transmit

Receive

Transmit

Receive

dBCt

Single-Irequency distortion products, transmit

-46

Single-Irequency distortion products, receive

-46

-41

Loop-around measurement,
VFXI+ = -4 dBmO to -21 dBmO,
Two Irequencies in the range 01 300 Hz to 3400 Hz

Intermodulation distortion

Level = -3 dBmO
Level = -6 dBmO to -27 dBmO
Signal-to-distortion ratio, transmit hall-channel (A-law)
(CCITT G.714)§

Level = -34 dBmO

33.5

Level = -40 dBmO

28.5

Level = -55 dBmO

13.5

Level = -3 dBmO
Level = -6 dBmO to -27 dBmO
Signal-to-distortion ratio, receive hall-channel (A-law)
(CCITT G.714)§

33
dB

33
36

Level = -34 dBmO

34.2

Level = -40 dBmO

Level = -55 dBmO

t The Unit dBC applies to C-message weighting.
+ Sinusoidal test method (see Note 6)
§ Pseudo-noise test method
NOTE 6: The TP3054B and TP13054B are measured using a C-message lilter. The TP3057B and the TP13057B are measured using a
psophometric weighted lilter.

•
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TP3054B, TP3057B, TP13054B, TP130578
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

crosstalk
PARAMETER

TYPt

MAX

UNIT

DR at steady PCM code

-90

-75

f = 300 Hz to 3000 Hz

-90

-75

TEST CONDITIONS

Crosstalk, transmit-to-receive

f =300 Hz to 3000 Hz,

Crosstalk, receive-to-transmit (see Note 7)

VFXI

=0 V,

MIN

t All typical values are at VCC =5 V, VBB =-5 V, and TA =25°C.
NOTE 7: Receive-to-transmit crosstalk is measured with a-50 dBmO activation signal applied at VFXI +.

PARAMETER MEASUREMENT INFORMATION

-+I 14- td3

-+j /4- td2

------------~I~

1~~~20~%------------------------------------------~1

TSX

BClKX

I
I
I
I
I
I
I
I
I

FSX

I
I
I
I
I

tr1 -+j!4--

II
II

-JIIl.- tf1

I
I
I

~---I.r-

fclock(M)

MClKX
MClKR

20%

-.j ~ td3
DX ______________~----~~----~~----~r----~~----~~----~~----~~--~8~oo~~----

"-__. . I '-____

..I ' -_ _ _ _..I "-_ _ _ _..I ' -_ _ _ _..I ' -_ _ _ _..I ' -_ _ _ _..I ' -_ _~

BClKR

20%

th2~~11

FSR

~th4

~'-.________________________________*11------------.
Ii
I

______~_20%

1 -------

j++Il
I ~th3

I
I

I
---+II.-I

th3

--------------....I~----....I~----....I~----....I~----....I~----~----~----....I~--~------

Figure 1. Short-Frame Sync Timing

2-170

Ii
I

Ltsu4

tsu3

20%

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
tr1 ~ j4-

tw1~

I ~t+-tf11

MCLKX
MCLKA

~.----.t-- fclock(M)

I~ tw2

20%
I

th1

---+I

It-

11111

FSX

20%

td4

jf (
"l1-.1

j+-

--.j

tsu2

fclock(B)

thS

-_-_-_-_-_-_-_-_-_-...I.r_-_~+-20-%_

80% \'-_ _ _ _ _

1-+-1

14-

-f4---j :

td4

1,-- :

td1

OX -----(""-1--"X,-_2__X

X 4 X""-s--t

td3

~ I~

EI j}~~~o
II

td3~r

-JX'-_-JX

OA _ _ _ _

Figure 2. Long-Frame Sync Timing

•
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TP3054B,TP3057B, TP13054B,TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

PRINCIPLES OF OPERATION

system reliability and design considerations
TP305xB, TP1305xB system reliability and design considerations are described in the following paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP305xB and TP1305xB devices are heavily protected against latch-up, it is still possible to
cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals.
Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative
supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted
into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP305xB- or TP1305xB-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.

Ensure that no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply

Force a power down condition in the device.

Connect clocks.

Vee (most positive voltage).

Release the power down condition.

Apply FS synchronization pulses.

Apply the signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

"TEXAS
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TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC
DGND

VBB

Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3054B, TP3057B, TP13054B, and TP13057B devices when power
is first applied, placing it into the power-down mode. OX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MClKR/PON powers up the device and
activates all circuits. OX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.

synchronous operation
For synchronous operation, a clock is applied to MClKX. MClKR/PON is used as a power-down control. A low
level on MClKR powers up the device and a high level powers it down. In either case, MClKX is selected as
the master clock for both receive and transmit direction. BClKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BClKRlClKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BClKRlClKSEl selects BClKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BClKR/ClKSEL.
In the synchronous mode, BClKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MClKX.

Table 1. Selection of Master-Clock Frequencies
BCLKR/CLKSEL

MASTER-CLOCK FREQUENCY SELECTED
TP13057B,TP3057B
TP13054B,TP3054B

Clock Input

1.536 MHz or 1.544 MHz

2.048 MHz

Logic Input L
(sync mode only)

2.048 MHz

1.536 MHz or 1.544 MHz

Logic Input H (open)
(sync mode only)

1.536 MHz or 1.544 MHz

2.048 MHz

The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled OX output on the riSing edge of BClKX. After eight bit-clock periods, the 3-state OX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via OR on the falling edge of BClKX (or
BClKR, if running). FSX and FSR must be synchronous with MClKX and MClKR.

~TEXAS

INSTRUMENTS
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2-173

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MClKX and MClKR must
be 2.048 MHz for the TP3057B and TP13057B, 1.536 MHz or 1.544 MHz for the TP3054B and TP13054B and
need not be synchronous. However, for best performance, MClKR should be synchronous with MClKX. This
is easily achieved by applying only static logic levels to MClKR/PON. This connects MClKX to all internal
MClKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX and FSX must be synchronous with MClKX and BClKX. Each
decoding cycle is started with FSR and FSR must be synchronous with BClKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BClKX and BClKR can operate from 64 kHz to 2.048 MHz.

short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BClKX, the next riSing edge of BClKX
enables the 3-state output buffer, OX, which outputs the sign bits. The remaining seven bits are clocked out on
the following seven rising edges and the next falling edge disables OX. With FSR high during a falling edge of
BClKR (BClKX in synchronous mode), the next falling edge of BClKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.

long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BClKX, which ever occurs later, enables the OX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BClKX edges clock out the
remaining seven bits. The falling edge of BClKX following the eighth rising edge or FSX going low, whichever
occurs later, disables DX. A rising edge on FSR, the receive-frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BClKR (BClKX in synchronous mode). The long-frame sync
pulse can be utilized in either the synchronous or asynchronous mode.

transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eighth-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per fl.-law (TP3054B and TP13054B) or A-law (TP3057B
and TP13057B) coding conventions, the AOC is a companding type. A precision voltage reference provides a
nominal input overload of 2.5 V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse.
Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and shifted
out through OX at the next FSX pulse. The total encoding delay is approximately 290 fl.s. Any offset voltage due
to the filters or comparator is cancelled by sign-bit integration.

~TEXAS

INSTRUMENTS
2-174

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A- MAY 1990 - REVISED JULY 1996

PRINCIPLES OF OPERATION
receive section
The receive section consists of an expanding DAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is Il-Iaw (TP3054B and TP13054B) or A-law (TP3057B and TP13057B) and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post-filter/power amplifier capable of driving a 600-.0 load to a level of 7.2 dBm. The
receive section is unity gain. At FSR, the data at DR is clocked in on the falling edge of the next eight BClKR
(BClKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10 Ils later, the decoder
DAC output is updated. The decoder delay is about 10 IlS ( decoder update) plus 110 Ils (filter delay) plus
62.51ls (1/2 frame), or a total of approximately 180 Ils .

•
TEXAS
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2-175

TP3054B, TP3057B, TP13054B, TP13057B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS042A - MAY 1990 - REVISED JULY 1996

APPLICATION INFORMATION·

power supplies
While the pins of the TP1305xB and TP305xB families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed, ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and VBB
supplies should be decoupled by connecting O.1-JlF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to Vee and VBB.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation, rather than via a ground bus. This common ground point should be decoupled to Vee
and V BB with 10-JlF capacitors.
1

16
VBB

0.1 JlF :::::~
2

J- 0.1

VFXI
ANLG GND

15
14 R1

JlF:::::~

...A

GSX
4
VCC

5V
3
To SLiC

VFRO

Fr om SLiC

VFXI+

1
-

TP3054B
TP3057B
TP130548
TP13057B

J-Analog Interface

- - - - - - - - ------------- f - - - - - - - 5

FSR

FSX
DX

Da ta In

6
7

5 Vor GND
8
PDN

NOTE A: Transmit gain = 20 log

DR
BCLKR/CLKSEL

BCLKX

MCLKR/PDN

(R1:2 R2), (R1 + R2)

MCLKX

2!:

12
11

10 kQ

Figure 4. Typical Synchronous Application

•
TEXAS
INSTRUMENTS
2-176

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

----r--

Data
0 ut

Digital
Interface

B CLKX (2.048 MHzl1.544 MHz)

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

•

Complete PCM Co dec and Filtering
Systems Include:
- Transmit High-Pass and Low-Pass
Filtering
- Receive Low-Pass Filter With (sin x)/x
Correction
- Active RC Noise Filters
- Jl-Law or A-Law Compatible Coder and
Decoder
- Internal Precision Voltage Reference
- Serial 1/0 Interface
- Internal Autozero Circuitry

•

Jl-Law - TP3064B and TP13064B

•

A-Law - TP3067B and TP13067B

•
•

±5-V Operation
Low Operating Power ... 70 mW Typ

•

Power-Down Standby Mode ... 3 mW Typ

•
•

Automatic Power Down
TTL- or CMOS-Compatible Digital Interface

•

Maximizes Line Interface Card Circuit
Density
Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
TP3067-X

description

ow OR

The TP3064A, TP3067 A, TP13064A, and
TP13067A are comprised of a single-chip PCM
codec (pulse-code-modulated encoder and decoder) and PCM line filter. These devices provide
all the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TOM
(time-division-multiplexed) system. These devices are pin-for-pin compatible with the National
Semiconductor TP3064A and TP3067 A, respectively. Primary applications include:
•

Line interface for digital transmission and
switching of T1 carrier, PABX, and central
office telephone systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital voice-band data-storage systems

•

Digital signal processing

N PACKAGE
(TOP VIEW)

VPO+
ANLG GND
VPOVPI
VFRO
VCC
FSR
DR
BCLKR/CLKSEL
MCLKR/PDN [

1 U 20
2
3

4
5
6

7
8
9
10

VBB
VFXI+
VFXIGSX
ANLG LOOP
TSX
FSX
DX
BCLKX
11 P MCLKX

19
18
17
16
15
14
13
12

These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two t'ransmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064A, TP3067 A, TP13064A, and TP13067 A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and
TP13067 A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below -55 dBmO.
The TP3064A and TP3067 A are characterized for operation from ODC to 70 DC. The TP13064A and TP13067 A
are characterized for operation from _40DC to 85 DC.

PRODUCTION DATA Information is current as of publication date.
Products conform to speCifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily Include
testing of all parameters.

•
TEXAS
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2-177

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

functional block diagram
r-~RA2~~________________________________________________-1~____
17_ GSX
Analog
Input

, -________________________________________~~---1-6-ANLG
LOOP

VFXI- 1_BJ V V ,'v-1..-t
VFXI + 1_9_ _--1
SwitchedCapacitor
Band-Pass Filter
VPO+ ---=-1__~._<

Transmit
Regulator

OE
VPO-

---.:3-e~._<
SwitchedCapacitor
Low-Pass Filter

Receive
Regulatc...

CLK
R4

15 _
Timing and Control
5V

-5V

r r

VCC

VBB

ANLG GNO

MCLKX

MCLKRI BCLKX BCLKRI FSR FSX
PON
CLKSEL

~TEXAS

2-178

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TSX

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

ANLG GNO

ANlG lOOP

Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit
filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power
amplifier.

The bit clock that shifts data into OR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,
can be a logic input that selects either 1.536 MHzl1.544 MHz or 2.048 MHz for master clock in synchronous mode.
SClKX is used for both transmit and receive directions (see Table 1).

The bit clock that shifts out the PCM data on OX. SClKX can vary from 64 kHz to 2.048 MHz, but must be synchronous
with MClKX.

SClKRlClKSEl

SClKX
OR

Analog ground. All signals are referenced to ANlG GNO.

Receive data input. PCM data is shifted into OR following the FSR leading edge.
The 3-state PCM data output that is enabled by FSX.

FSR

Receive frame sync pulse input that enables BClKR to shift PCM data in OR. FSR is an 8-kHz pulse train (see Figures
1 and 2 for timing details).

FSX

Transmit frame sync pulse that enables BClKX to shift out the PCM data on OX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

GSX

Analog output of the transmit input amplifier. GSX is used to externally set gain.

MClKRlPON

Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MClKX, but should
be synchronous for best performance. When MClKR is connected continuously low, MClKX is selected for all internal
timing. When MClKR is connected continuously high, the device is powered down.

MClKX

Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MClKR

TSX

Open-drain output that pulses low during the encoder time slot

VBS

Negative power supply. VSS

VCC

Positive power supply. VCC

VFRO

Analog output of the receive filter

VFXI+

Noninverting input of the transmit input amplifier

VFXI-

Inverting input of the transmit input amplifier

=-5 V ± 5%
=5 V ± 5%

VPI

Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VSS

VPO+

The noninverted output of the receive power amplifier

VPO-

The inverted output of the receive power amplifier

~TEXAS

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2-179

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range {unless otherwise noted}t
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Supply voltage, VBB (see Note 1) ............................................................ - 7 V
Voltage range at any analog input or output ............................... Vee + 0.3 V to VBB - 0.3 V
Voltage range at any digital input or output ............................... Vee + 0.3 V to GND - 0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range, TA: TP3064A, TP3067 A .......................... O°C to 70°C
TP13064A, TP13067A ...................... -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package ............... 260°C

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation Qf the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
TA~25°C

POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

1150mW

PACKAGE

TA 70°C
POWER RATING

TA 85°C
POWER RATING

8.2 mWrC

656mW

533mW

9.2 mW/oC

736mW

598mW

recommended operating conditions (see Note 2)
MIN

NOM

MAX

Supply voltage, VCC

4.75

5.25

Supply voltage, VBB

-4.75

-5

-5.25

High-level input voltage, VIH

2.2
0.6

Low-level input voltage, VIL

±2.5

Common-mode input voltage range, VICR:j:
Load resistance at GSX, RL

ITP3064A, TP3067A

Operating free-air temperature, TA

I TP13064A, TP13067A

V
V

kf!

Load capacitance at GSX, CL

UNIT

-40

pF
°C

:j: Measure with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed.

~TEXAS

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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
supply current
TEST CONDITIONS

PARAMETER

ICC

Supply current from VCC

IBB

Supply current from VBB

Power down

TP306xA
MIN

TYpt

No load

Active
Power down

No load

Active

TP1306xA
MAX

MIN

TVPt

MAX

0.5

1.2

0.5

1.2

UNIT

mA
mA

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
electrical characteristics at Vee = 5 V ± 5%, VBB = -5 V ± 5%, GND at 0 V, TA = 25°C (unless otherwise
noted)
digital interface
PARAMETER
VOH

MIN

TEST CONDITIONS

High-level output voltage

IH =-3.2 mA

IL= 3.2 mA

TSX

IL = 3.2 mA,

MAX

2.4

UNIT
V

0.4

VOL

Low-level output voltage

IIH

High-level input current

VI = VIH to VCC

±10

IlL

Low-level input current

All digital inputs

VI = GND to VIL

±10

IOZ

Output current in high-impedance state

Vo = GND to VCC

±10

MAX

UNIT

0.4

Drain open

analog interface with transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current

VFXI+ or VFXI-

VI = -2.5 V to 2.5 V

Input resistance

VFXI+ or VFXI-

VI = -2.5 V to 2.5 V

Output resistance

Closed loop,

Output dynamic range

GSX

Open-loop voltage amplification

VFXI+to GSX

MIN

TVPt

±200
10
1

Unit gain

nA
Mn

RL~10kn

±2.8

5000
1

MHz

Unity-gain bandwidth

GSX

VIO

Input offset voltage

VFXI+ or VFXI-

CMRR

Common-mode rejection ratio

kSVR

Supply-voltage rejection ratio

±20

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

analog interface with receive filter
PARAMETER
Output resistance

TEST CONDITIONS

MIN

IVFRO

Load resistance

VFRO =±2.5 V

TVPt

MAX

600

UNIT
n
n

Load capacitance

I VFROtoGND

500

Output dc offset voltage

IVFROto GND

±200

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

analog Interface with power amplifiers
PARAMETER

TEST CONDITIONS

Input current

VPI =-1 Vto 1 V

Input resistance

VPI = -1 V to 1 V

Output resistance

VPO+or VPO-

Inverting unity gain

Voltage amplification

VPO-orVPO+

VPO- = 1.77 Vrms,

Unity-gain bandwidth

VPO-

Open loop

VIO

Input offset voltage

MAX

1
RL = 600 n

kHz
±25

I 4 kHz to 50 kHz

Load resistance

Connected from VPO+ to VPO-

Load capacitance

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

mV
dB

600
100

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C .

-1
400

10kHz to 4 kHz

UNIT

Mn
n

VPO- connected to VPI

2-182

TYpt

±100

Supply-voltage rejection ratio of VCC or VBB

kSVR

MIN

TP3064A, TP3067A,TP13064A,TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

operating characteristics, over operating free-air temperature range Vee 5 V ± 5%,
Vee -5 V ± 5%, GND at 0 V, VI 1.2276 V, f 1.02 kHz, transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)

timing requirements
PARAMETER

TEST CONDITIONS
MCLX
and
MCLKR

MIN

TYPt

MAX

1.536
1.544
2.048

Depends on the device used and
BCLKXJCLKSEL

UNIT

fclock(M)

Frequency of master clock

fclock(B)

Frequency of bit clock, transmit

BCLKX

tr1

Rise time of master clock

MCLKX
and
MCLKR

Measured from 20% to 80%

tf1

Fall time of master clock

MCLKX
and
MCLKR

Measured from 20% to 80%

MHz
2.048

MHz

tr2

Rise time of bit clock, transmit

BCLKX

Measured from 20% to 80%

BCLKX

Measured from 20% to 80%

tf2

Fall time of bit clock, transmit

tw1

Pulse duration, MCLKX and MCLKR high

160

tw2

Pulse duration, MCLKX and MCLKR low

160

tsu1

Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKXJ..

100

First bit clock after the leading edge
ofFSX

tW3

Pulse duration, BCLKX and BCLKR high

VIH = 2.2 V

160

tw4

Pulse duration, BCLKX and BCLKR low

VIL= 0.6 V

160

th1

Hold time, frame sync low after bit clock low (long
frame only)

th2

Hold time, BCLKX high after frame synci (short
frame only)

tsu2

Setup time, frame sync high before bit c1ockJ.. (long
frame only)

td1

Delay time, BCLKX high to data valid

Load = 150 pF plus 2 LSTTL loads+

td2

Delay time, BCLKX high to TSX low

Load = 150 pF plus 2 LSTTL loads+

td3

Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled

td4

Delay time, FSX or BCLKX high to data valid (long
frame only)

tsu3

Setup time, DR valid before BCLKRJ..

th3

Hold time, DR valid after BCLKR or BCLKXJ..

tsu4

Setup time, FSR or FSX high before BCLKR or
BCLKXJ..

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

th4

Hold time, FSX or FSR high after BCLKX or
BCLKRJ..

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

100

th5

Hold time, frame sync high after bit c1ockJ..

Long-frame sync pulse (from 3- to
8-bit clock periods long)

100

tw5

Pulse duration of the frame sync pulse (low level)

64 kbps operating mode

160

CL = 0 pF to 150 pF

140

165

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.

+Nominal input value for an LSTTL load is 18 kil.

NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high .

•
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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

filter gains and tracking errors
PARAMETER

Maximum peak transmit
overload level

TEST CONDITIONS:t

ITP3064A, TP13064A
ITP3067A, TP13067A

MIN

2.501

3.14 dBmO

2.492

TA = 25°C

Transmit filter gain, absolute (at 0 dBmO)

TYPt

3.17dBmO

-0.15

= 16 Hz
f = 50 Hz
f = 60 Hz
f = 200 Hz
f =300 Hz to 3000 Hz
f =3300 Hz
f =3400 Hz
f = 4000 Hz
f

Absolute transmit gain variation with
temperature and supply voltage

Transmit gain tracking error with level

-1.8

-0.1

-0.15

0.15

-0.35

0.05

-0.8

-32
-0.1

-50 dBmO > input level

±0.2
±0.4

-55 dBmO

Receive filter gain, absolute (at 0 dBmO)

Input is digital code sequence for 0 dBmO signal,
TA = 25°C
TA = 25°C

Receive filter gain, relative to absolute

=0 Hz to 3000 Hz,
=3300 Hz
f =3400 Hz
f =4000 Hz
TA =full range,

See Note 4

0.1

=-10 dBmO

-40 dBmO

-40 dBmO > input level 2: -50 dBmO

Absolute receive gain variation with temperature
and supply voltage

-14

Sinusoidal test method; Reference level
input level

0.15

-30

4600 Hz (measure response from 0 Hzt04000Hz)

-26

Relative to absolute transmit gain

3 dBmO

UNIT

-40

Transmit filter gain, relative to absolute

MAX

±0.8
-0.15

0.15

-0.15

0.15

-0.35

0.05

-0.8

-14
-0.1

0.1

±0.2

Sinusoidal test method; reference input PCM code
corresponds to an ideally encoded -10 dBmO signal
Receive gain tracking error with level

Receive output drive voltage

Transmit and receive gain tracking error with
level (A-law, CCITT C712)

3 dBmO 2: input level 2: -40 dBmO
-40 dBmO > input level

-50 dBmO

±0.4

-50 dBmO > input level

-55 dBmO

±0.8

RL = 10 kn

±2.5

±0.25

Pseudo-noise-test method; reference input PCM
code corresponds to an ideally encoded -10 dBmO
signal
3 dBmO

input level 2: -40 dBmO

-40 dBmO > input level

-50 dBmO

±0.3

-50 dBmO > input level 2: -55 dBmO

±0.45

t All typical values are at VCC = 5 V, VBB =-5 V, and TA =25°C.
+Absolute rms signal levels are defined as follows: VI = 1.2276 V =0 dBmO =4 dBm at f = 1.02 kHz with RL =600 n.
NOTE 4: Full range for the TP3064A and TP3067A is O°C to 70°C. Full range for the TP13064A and TP13067 A is -40°C to 85°C.

~TEXAS

INSTRUMENTS
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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

envelope delay distortion with frequency
PARAMETER

TEST CONDITIONS

= 1600 Hz
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
Transmit filier gain, relative to absolute
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
Receive delay, absolute (at 0 dBmO)
f = 1600 Hz
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
Receive delay, relative to absolute
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
t All typical values are at VCC =5 V, VBB =-5 V, and TA = 25°C.
Transmit delay, absolute (at 0 dBmO)

MIN

TYPt

MAX

UNIT

290

315

Il s

195

220

120

145

Il s

105

130

155

180

200

Ils

-40

-25

-30

-20
70

100

125

140

175

TYPt

MAX

noise
PARAMETER

TEST CONDITIONS

MIN

UNIT

Transmit noise, C-message weighted

TP3064A,
TP13064A

VFXI

=0 V

dBrnCO

Transmit noise, psophometric weighted
(see Note 5)

TP3067A,
TP13067A

VFXI

=0 V

-78

-75

dBmOp

Receive noise, C-message weighted

TP3064A,
TP13064A

PCM code equals alternating positive
and negative zero

dBrnCO

Receive noise, psophometric weighted

TP3067A,
TP13067A

PCM code equals positive zero

-86

-83

dBmOp

-53

dBmO

Noise, single frequency

f = 0 kHz to 100 kHz,
VFXI+ = 0 V,
Loop-around measurement

All typical values are at VCC = 5 V, VBB =-5 V, and TA = 25°C.
NOTE 5: Measured by extrapolation from the distortion test result. This parameter is achieved through use of patented circuitry and is not
recommended for applications in which the composite signals on the transmit side are below -55 dBmO.

~TEXAS

INSTRUMENTS
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2-185

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

power supply rejection
TEST CONDITIONS

PARAMETER

Positive power-supply rejection, transmit

Negative power-supply rejection, transmit

Positive power-supply rejection, receive

Negative power-supply rejection, receive

=0 Hz to 4 kHz

VCC = 5 V + 100 mVrms,
VFXI+ =-50 dBmO

MIN

f
f

PCM code equals positive zero,
VCC = 5 V + 100 mVrms

f
f

PCM code equals positive zero,
VBB -5 V + 100 mVrms

Ill-law

dBCt

lA-law

Ill-law

dBCt

= 4 kHz to 50 kHz
=0 Hz to 4 kHz

lA-law

Ill-law

dBCt

lA-law

Ill-law

dBCt

=4 kHz to 50 kHz

=0 Hz to 4 kHz

f = 4 kHz to 50 kHz

o dBmO, 300-Hz to 3400-Hz input applied to DR
Spurious out-of-band signals at the
channel output (V FRO)

UNIT

= 4 kHz to 50 kHz

f = 0 Hz to 4 kHz

VBB =-5 V + 100 mVrms,
VFXI+ =-50 dBmO

MAX

lA-law

dB
-30

(measure individual image signals at VFRO)

=4600 Hz to 7600 Hz
f =7600 Hz to 100 kHz

-33

-40

dB
dB

t The unit dBC applies to C-message weighting.

distortion
PARAMETER

TEST CONDITIONS

=3 dBmO
Level = 0 dBmO to -30 dBmO

Level

Signal-to-distortion ratio, transmit or receive half-channel+

Level

=-40 dBmO

Level = -55 dBmO

MIN

MAX

UNIT

33
36
Transmit

Receive

Transmit

Receive

dBCt

Single-frequency distortion products, transmit

-46

Single-frequency distortion products, receive

-46

-41

Loop-around measurement,
VFXI+ =-4 dBmO to -21 dBmO,
Two frequencies in the range of 300 Hz to 3400 Hz

Intermodulation distortion

Pseudo noise test method

=-3 dBmO
=-6 dBmO to -27 dBmO
Level =-34 dBmO
Level =-40 dBmO

28.5

Level = -55 dBmO

13.5

Level

Signal-to-distortion ratio, transmit half-channel (A-Law)
(CCID G.714)§

Level

=-3 dBmO

Level = -6 dBmO to -27 dBmO
Signal-to-distortion ratio, receive half-channel (A-law)
(CCIDG.714)§

=-34 dBmO
Level =-40 dBmO
Level =-55 dBmO
Level

33
36
33.5

33
36
34.2

30
15

t The unit dBC applies to C-message weighting.
+ Sinusoidal test method (see Note 6)
§ Pseudo-noise test method
NOTE 6: The TP13064A and TP3064A are measured using a C-message filter. The TP13067A and TP3067A are measured using a
psophometric weighted filter.

~TEXAS

INSTRUMENTS
2-186

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

crosstalk
TYPt

MAX

UNIT

Crosstalk, transmit to receive

f = 300 Hz to 3000 Hz,

DR at steady PCM code

-90

-75

Crosstalk, receive to transmit (see Note 7)

VFXI = 0 V,

f = 300 Hz to 3000 Hz

-90

-72

MIN

MAX

UNIT

PARAMETER

TEST CONDITIONS

MIN

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
NOTE 7:

Receive-to-transmit crosstalk is measured with a-50 dBmO activation signal applied to VFXI+.

power amplifiers
TEST CONDITIONS

PARAMETER
Balanced load,
Maximum 0 dBmO rms level for better than ±0.1 dB
linearity over the range if -10 dBmO to 3 dBmO

Signal/distortion

RL connected between VPO+ and VPO -

RL = 600 n

3.3

RL = 1200 n

3.5

RL = 30 kn

RL= 600 n

Vrms
dB

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-187

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

~~~

------------~I I

I I~----

I \- 20%
1120%
I ~~------------------------------------~
I
I

TSX
tr1 -+j I+--

II -JIIl.- tf1 I

14----+1-- fclock(M)

I
I
I
I
I
I
I

MCLKX
MCLKR

BCLKX

FSX

20%

------I

BCLKR

th2-.j

~II
II

--1I

II
I
II
I
II
I
~th4
II
I
80%
I
I
20%
~._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~II----------~I~-----

~tsu4

;r:::-\

FSR _________

tsu3

~I
I
I
I

DR _ _ _ _ _ _ _ _ _ _ _ _-J~_ __

Figure 1. Short-Frame Sync Timing

~TEXAS

INSTRUMENTS
2-188

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~th3

I
I

--.j I.- th3

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
tr1 ~ 14::

~
I'"

th1--.j

tw1 ~

~~tf1:

tw2

\80%

,I:

tSU2

thS

~%
I

-1- - - - - - - - f\ =\

---.l I+-

'2~~~~:o------~8~O%~o,i--1
------"

"
tsu3

-..I

I.f-

II I"
DR

20%

t d4

r-r-----r:
I

FSR

fclock(B)

~thS

tsu2

td4~1
II
ox - - - - - - - . . ;( 1

th1

,
,
,
,
,
-t---------r -\
I
, -f

I
I

4, ?H -

FSX

~I"- - - . t - - fclock(M)

:rl

I
t

---+I

th3

2 X 3 X 4 X S X 6 X 7 x = Q........_ _

Figure 2. Long-Frame Sync Timing

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-189

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
TP306xA, TP1306xA system reliability and design considerations are described in the following paragraphs.

latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP306xA and TP1306xA devices are heavily protected against latch-up, it is still possible to
cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals.
Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative
supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card that has an edge connector and the card is hot-inserted
into a system with the power on.
To help ensure that latch-up does not occur, it is considered good design practice to connect a reverse-biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) between the
power supply and GND (see Figure 3). If it is possible that a TP306xA- or TP1306xA-equipped card that has
an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the ground
edge connector traces are longer than the power and signal traces so that the card ground is always the first
to make contact.

Ensure that no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply

Force a power down condition in the device.

Vee (most positive voltage).

Connect clocks.

Release the power down condition.

Apply FS synchronization pulses.

Apply the signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

~TEXAS

2-190

INSTRUMENTS
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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C- SEPTEMBER 1992 -REVISED JULY 1996

PRINCIPLES OF OPERATION
VCC

DGND

Vee

Figure 3. Latch-Up Protection Diode Connection
internal sequencing
Power-on reset circuitry initializes the TP3064A, TP3067A, TP13064A, and TP13067A devices when power
is first applied, placing it into the power-down mode. OX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKRlPON powers up the device and
activates all circuits. OX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.

synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PON is used as a power-down control. A low
level on MCLKR powers up the device and a high level powers it down. In either case, MCLKX is selected as
the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done via BCLKRlCLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.

Table 1. Selection of Master-Clock Frequencies
eCLKR/CLKSEL

MASTER-CLOCK FREQUENCY SELECTED
TP3064A,TP13064A

TP3067A,TP13067A

Clock Input

1.536 MHz or 1.544 MHz

2.048 MHz

Logic Input L
(sync mode only)

2.048 MHz

1.536 MHz or 1.544 MHz

Logic Input H (open)
(sync mode only)

1.536 MHz or 1.544 MHz

2.048 MHz

~TEXAS

INSTRUMENTS
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2-191

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

PRINCIPLES OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3064A and TP13064A, 1.536 MHz or 1.544 MHz for the TP3067 A and TP13067 A and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKR/PON. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.

short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX
enables the 3-state output buffer, OX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables OX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the remaining bits. The short-frame sync pulse can be utilized in either the
synchronous or asynchronous mode.

long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships, as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the OX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables OX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at OR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse may be used in either the synchronous or asynchronous mode .

•
TEXAS
INSTRUMENTS '
2-192

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3064A,TP3067A, TP13064A,TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C- SEPTEMBER 1992 -REVISED JULY 1996

PRINCIPLES OF, OPERATION

transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. The low noise and wide bandwidth characteristics of these devices provide gains in excess of 20 dB
across the audio passband. The operational amplifier drives a unity-gain filter consisting of an RC active prefilter
followed by an eight-order switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter
directly drives the encoder sample-and-hold circuit. As per /l-Iaw (TP3064A and TP13064A) or A-law (TP3067 A
and TP13067 A) coding conventions, the AOC is a companding type. A precision voltage reference provides an
input overload of nominally 2.5-V peak. The sampling of the filter output is controlled by the FSX frame sync
pulse. Then the successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and
shifted out through OX at the next FSX pulse. The total encoding delay is approximately 290 /ls. Any offset
voltage due to the filters or comparator is cancelled by sign bit integration (see Table 2).

Table 2. Encoding Format at OX Output
TP3064A,TP13064A
Ii-Law

VI = + Full scale

VI =0

1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1

VI = - Full scale

000 0

TP3067A,TP13067A
A-Law
(INCLUDES EVEN-BIT INVERSION)

0 000

1 1
0 1

o
o

1 o 1 0 1
1 0 1 0 1

o
o

1 0

receive section
The receive section consists of an expanding OAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is /l-Iaw (TP3064A and TP13064A) or A-law (TP3067A and TP13067A), and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post filter with its output at VFRO. The receive section is unity gain, but gain can be
added by using the power amplifiers. At FSR, the data at DR is clocked in on the falling edge of the next eight
BClKR (BClKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10-/ls later the
decoder OAC output is updated. The decoder delay is about 10 /ls (decoder update) plus 110 /lS (filter delay)
plus 62.5 /ls (1/2 frame), or a total of approximately180 /ls.

receive power amplifiers
Two inverting-mode power amplifiers are provided for directly driving a match-line interface transformer. The
gain of the first power amplifier can be adjusted to boost the ±2.5-V peak output signal from the receive filter
up to the ± 3.3-V peak into an unbalanced 300-0 load, or±4 V into an unbalanced 15-kO load. The second power
amplifier is internally connected in the unity-gain inverting mode to give 6 dB of signal gain for balanced loads.
Maximum power transfer to a 600-0 subscriber line termination is obtained by differentially driving a balanced
transformer with "./2: 1 turns ratio, as shown in Figure 3. A total peak power of 15.6 dBm can be delivered to the
load plus termination.

•
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2-193

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

APPLICATION INFORMATION
power supplies
While the pins of the TP1306xA and TP306xA families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and VBB
supplies should be decoupled by connecting O.1-!J,F decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to Vee and VBB'
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to Vee
and VBB with 1O-!J,F capacitors.

~TEXAS

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TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS025C - SEPTEMBER 1992 -REVISED JULY 1996

APPLICATION INFORMATION

Hybrid

300n

ZBAl

300n

6
GND

VCC
VPO+
3

FSR
DR
BClKR
MClKR/PDN

NOTES: A. Transmit gain

VFXITP3064A
TP3067A
TP13064A
TP13067A

VPI

R4
5

VFXI+

VPO-

VBB
19
18
R1
GSX

17
16
15

VFRO

9
10

12
11

=20 Ylog (R1

ANlG lOOP
TSX
FSX
DX
BClKX
MClKX

+ R2), (R1 + R2) 2! 10 kn
R2

B. Receive gain =20 Ylog (2 x R3 ). R4 2! 10 kn
R4

Figure 4. Typical Synchronous Application

•
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2-195

2-196

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

•

Complete PCM Codec and Filtering
Systems Include:
- Transmit High-Pass and Low-Pass
Filtering
- Receive Low-Pass Filter With (sin xlIx
Correction
- Active RC Noise Filters
- Il-Law or A-Law Compatible Coder and
Decoder
- Internal Precision Voltage Reference
- Serial I/O Interface
- Internal Autozero Circuitry

•
•

Il-Law - TP13064B and TP30648
A-Law - TP130678 and TP30678

•
•
•
•
•
•

±5-V Operation
Low Operating Power ... 70 mW Typ
Power-Down Standby Mode ... 3 mW Typ
Automatic Power Down
TIL- or CMOS-Compatible Digital Interface
Maximizes Line Interface Card Circuit
Density

•

Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
and TP3067-X

description
The TP30648, TP30678, TP130648, and
TP130678 each comprise a single-chip pulsecode-modulation encoder and decoder (PCM
codec), and PCM line filter. They also provide
band-pass filtering of the analog signals prior to
the encoding, and low-pass filtering after the
decoding of voice signals and call-progress tones.
All the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a time-division-multiplexed (TOM) system are included
on-chip. These devices are pin-for-pin compatible
with the National Semiconductor TP3064 and
TP3067. Primary applications include:
•

Line interface for digital transmission and
switching of T1 carrier, PA8X (private
automated branch exchange), and central
office telephone systems

•

Subscriber line concentrators

•

Digital-encryption systems

•

Digital voice-band data-storage systems

•

Digital signal processing

OW OR N PACKAGE
(TOP VIEW)

1 U

VPO+
ANLG GNO
VPOVPI
VFRO
VCC
FSR
OR
BCLKRlCLKSEL
MCLKR/PON

[

2
3
4
5
6
7
8
9
10

VBB
19 VFXI+
18 VFXI17 GSX
16 ANLG LOOP
15 TSX
14 FSX
13 OX
12 BCLKX
11 P MCLKX

These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system, and are intended to be used
at the analog termination of a PCM line or trunk. They require a transmit master clock and a receive master clock
that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are
synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP30648 and TP130648 contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below -55 d8mO.

These devices have limited built-in ESD protection. The leads should be shorted together orthe device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.

PRODUCTION DATA information Is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily Include
testing of ail parameters.

~TEXAS

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2-197

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

The TP3064B and TP3067B are characterized for operation from O°C to 70°C. The TP13064B and TP13067B
are characterized for operation from -40°C to 85°C.

functional block diagram
R2

Analog
Input
VFXI-

GSX

r -________________________________________~~--_1~6_ANlG

lOOP

_18-'V'v'\r---<~

VFXI+ _19_ _- i
SwitchedCapacitor
Band-Pass Filter
VPO+ --.:..1---4t--<

Transmit
Regulator

OE
VPO -

----'3-411~a--<
SwitchedCapacitor
low-Pass Filter

Receive
Regulator

ClK
R4

5VFRO

Timing and Control
5V

6j
VCC

-5V

20j
VBB

2j
ANlG GNO

MClKX

MClKR! BClKX BClKR! FSR FSX
PON
ClKSEl

~TEXAS

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15 _
TSX

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

Analog ground. All signals are referenced to ANLG GNO.

ANLG GNO

ANLG LOOP

The bit clock that shifts data into OR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Altemately,
can be a logic input that selects either 1.536 MHzl1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).

The bit clock that shifts out the PCM data on OX. May vary from 64 kHz to 2.048 MHz, but must be synchronous
with MCLKX

BCLKA/CLKSEL

BCLKX

Receive data input. PCM data is shifted into OR following the FSR leading edge.

FSR

Receive frame-sync pulse input that enables BCLKR to shift PCM data in OR. FSR is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

FSX

Transmit frame-sync pulse that enables BCLKX to shift out the PCM data on OX. FSX is an 8-kHz pulse train (see
Figures 1 and 2 for timing details).

GSX

Analog output of the transmit input amplifier. GSX is used to externally set gain.

MCLKA/PON

Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but
should be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected
for all internal timing. When MCLKR is connected continuously high, the device is powered down.

The 3-state PCM data output that is enabled by FSX

MCLKX

Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR

TSX

Open-drain output that pulses low during the encoder time slot

VBS

Negative power supply. VBS

VCC

Positive power supply. VCC

VFRO

Analog output of the receive filter

VFXI+

Noninverting input of the transmit input amplifier

VFXI-

Inverting input of the transmit input amplifier

=-5 V ± 5%
=5 V ± 5%

VPI

Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBS.

VPO+

The noninverted output of the receive power amplifier

VPO-

The inverted output of the receive power amplifier

•
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TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage, Vee (see Note 1) ............................................................. 7 V
Supply voltage, VBB (see Note 1) ............................................................ -7 V
Voltage range at any analog input or output ............................... Vee + 0.3 V to VBB - 0.3 V
Voltage range at any digital input or output ............................... Vee + 0.3 V to GND - 0.3 V
Continuous total dissipation ........................................... See Dissipation Rating Table
Operating free-air temperature range: TP30648, TP30678 .............................. O°C to 70°C
TP130648, TP130678 .......................... -40°C to 85°C
Storage temperature range ........................................................ -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DWor N package ............... 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
DERATING FACTOR
ABOVE TA = 25°C

PACKAGE

TA !> 25°C
POWER RATING

1025 mW

8.2 mW/oC

656mW

533mW

1150mW

9.2 mW/oC

736mW

598mW

TA= 70°C
POWER RATING

TA = 85°C
POWER RATING

recommended operating conditions (see Note 2)
MIN

NOM

MAX

UNIT

Supply voltage, Vec

4.75

5.25

Supply voltage, VSB

-4.75

-5

-5.25

0.6

High-level input voltage, VIH

2.2

Low-level input voltage, VIL
Common-mode input voltage range, VICR t

±2.5

Load resistance at GSX, RL

ITP3064B, TP3067B
ITP13064B, TP13067B

k!1

Load capacitance at GSX, CL
Operating free-air temperature, TA

-40

pF
°c

t Measure with CMRR > 60 dB.
NOTE 2: To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device
power-up sequence paragraphs later in this document should be followed .

•
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TP3064B,TP3067B, TP13064B,TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D- MAY 1990 -REVISED JULY 1996

electrical characteristics over power supply variations and recommended free-air temperature
range (unless otherwise noted)
supply current
PARAMETER

ICC

Supply current from VCC

IBB

Supply current from VBB

TEST CONDITIONS
Power down

TP306xB
MIN

TYPt

No load

Active
Power down

No load

Active

TP1306xB
MAX

MIN

TYPt

MAX

O.S

1.2

O.S

1.2

UNIT

t All typical values are at VCC = S V, VBB = -S V, and TA = 2SoC.

electrical characteristics at Vee 5 V ± 5%, VBB -5 V ± 5%, GND at 0 V, TA 25°C (unless otherwise
noted)
digital interface
PARAMETER
VOH

MIN

TEST CONDITIONS

High-level output voltage

IH =-3.2 mA

IL= 3.2 mA

TSX

IL = 3.2 rnA,

MAX

2.4

UNIT
V

0.4

VOL

Low-level output voltage

IIH

High-level input current

VI = VIH to VCC

±10

JlA

IlL

Low-level input current

All digital inputs

VI = GND to VIL

±10

JlA

IOZ

Output current in high-impedance state

Vo = GND to VCC

±10

JlA

MAX

UNIT

Drain open

0.4

analog interface with transmit amplifier input
PARAMETER

TEST CONDITIONS

Input current

VFXI+ or VFXI-

VI = -2.S V to 2.S V

Input resistance

VFXI+ or VFXI-

VI = -2.S V to 2.S V

Output resistance

Closed loop,

Output dynamic range

GSX

Open-loop voltage amplification

VFXI+to GSX

MIN

TYPt

±200

Unit gain

nA
Mn

RL ~ 10 kn

±2.8

SOOO
1

MHz

Unity-gain bandwidth

GSX

VIO

Input offset voltage

VFXI+ or VFXI-

CMRR

Common-mode rejection ratio

kSVR

Supply-voltage rejection ratio

±20

t All typical values are at VCC = S V, VBB = -S V, and TA = 2SoC.

analog interface with receive filter
PARAMETER
Output resistance

TEST CONDITIONS

MIN

IVFRO
VFRO =±2.S V

Load resistance

TYPt

MAX

600

UNIT
n
n

Load capacitance

I VFROto GND

SOO

Output dc offset voltage

I VFROto GND

±200

t All typical values are at VCC = S V, VBB = -S V, and TA = 2SoC .

•
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TP3064B, TP3067B,TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

analog interface with power amplifiers
PARAMETER
II

Input current

Input resistance

TEST CONDITIONS

=-1
VPI =-1
VPI

Output resistance

VPO+orVPO-

Inverting unity gain

Voltage amplification

VPO-orVPO+

VPO-

Unity-gain bandwidth

VPO-

Open loop

VIO

Input offset voltage

MAX

=1.77 Vrms,

=600 n

kHz
±25

I4 kHz to 50 kHz

VPO- connected to VPI

Load resistance

Connected from VPO+ to VPO-

Load capacitance

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

mV
dB

600
100

t All typical values are at VCC =5 V, VBB =-5 V, and TA =25°C.

-1
400

10kHz to 4 kHz

UNIT

Mn
n

Supply-voltage rejection ratio of VCC or VBB

2-202

TYPt

±100

V to 1 V

kSVR

MIN

V to 1 V

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D- MAY 1990 -REVISED JULY 1996

timing requirements
PARAMETER

TEST CONDITIONS
MCLX
and
MCLKR

MIN

TYPt

MAX

1.536
1.544
2.048

Depends on the device used and
BCLKx/CLKSEL

UNIT
MHz

fclock(M)

Frequency of master clock

fclock(B)

Frequency of bit clock, transmit

BCLKX

tr1

Rise time of master clock

MCLKX
and
MCLKR

Measured from 20% to 80%

tf1

Fall time of master clock

MCLKX
and
MCLKR

Measured from 20% to 80%

2.048

MHz

tr2

Rise time of bit clock, transmit

BCLKX

Measured from 20% to 80%

tl2

Fall time of bit clock, transmit

BCLKX

Measured from 20% to 80%

tw1

Pulse duration, MCLKX and MCLKR high

160

tw2

Pulse duration, MCLKX and MCLKR low

160

tsu1

Setup time, BCLKX high (and FSX in long-frame
sync mode) before MCLKXJ..

100

First bit clock after the leading edge
of FSX

tW3

Pulse duration, BCLKX and BCLKR high

VIH = 2.2 V

160

tw4

Pulse duration, BCLKX and BCLKR low

VIL = 0.6 V

160

th1

Hold time, frame sync low after bit clock low (long
frame only)

th2

Hold time, BCLKX high after frame synci (short
frame only)

tsu2

Setup time, frame sync high before bit clockJ.. (long
frame only)

ns
140

140

165

td1

Delay time, BCLKX high to data valid

Load = 150 pF plus 2 LSTIL loads:f:

td2

Delay time, BCLKX high to TSX low

Load = 150 pF plus 2 LSTIL loads:f:

td3

Delay time, BCLKX (or 8 clock FSX in long frame
only) low to data output disabled

td4

Delay time, FSX or BCLKX high to data valid (long
frame only)

tsu3

Setup time, DR valid before BCLKR..l.

th3

Hold time, DR valid after BCLKR or BCLKX..l.

tsu4

Setup time, FSR or FSX high before BCLKR or
BCLKX..l.

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

th4

Hold time, FSX or FSR high after BCLKX or
BCLKR..l.

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

100

th5

Hold time, frame sync high after bit clock..l.

Long-frame sync pulse (from 3- to
8-bit clock periods long)

100

tW5

Pulse duration of the frame sync pulse (low level)

64 kbps operating mode

160

CL = 0 pF to 150 pF

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
:j: Nominal input value for an LSTIL load is 18 kil.
NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.

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MONOLITHIC SERIAL INTERFACE
COMBINED PCM CO DEC AND FILTER
SCTS031D - MAY 1990-REVISED JULY 1996

operating characteristics over operating free-air temperature range, Vee 5 V ± 5%,
Vee -5 V ± 5%, GND at 0 V, VI 1.2276 V, f 1.02 kHz, transmit input amplifier connected for unity
gain, noninverting (unless otherwise noted)

filter gains and tracking errors
PARAMETER
Maximum peak transmit
overload level

TEST CONDITIONS*

ITP3064B, TP13064B
ITP3067B, TP13067B

Transmit filter gain, absolute .(al 0 dBmO)

MIN

2.501

3.14 dBmO

2.492
-0.15

TA = 25°G

UNIT
V

0.15
-40

f = 50 Hz

-30

-26

f = 200 Hz

Absolute transmit gain variation with
temperature and supply voltage

MAX

f= 16 Hz

f = 60 Hz

Transmit filter gain, relative to absolute

TYP*

3.17 dBmO

-1.8

-0.1

f = 300 Hz to 3000 Hz

-0.15

0.15

f = 3300 Hz

-0.35

0.05

f = 3400 Hz

-0.8

f = 4000 Hz

-14

f;::: 4600 Hz (measure response from 0 Hzt04000Hz)

-32

Relative to absolute transmit gain

-0.1

0.1

Sinusoidal test method; Reference level = -10 dBmO
Transmit gain tracking error with level

Receive filter gain, absolute (at 0 dBmO)

Receive filter gain, relative to absolute

3 dBmO ;::: input level;::: -40 dBmO

±0.2

-40 dBmO > input level;::: -50 dBmO

±0.4

-50 dBmO > input level;::: -55 dBmO

±0.8

Input is digital code sequence for 0 dBmO signal,
TA = 25°G

-0.15

0.15

f = 0 Hz to 3000 Hz,

-0.15

0.15

f = 3300 Hz

-0.35

0.05

f = 3400 Hz

-0.8

TA = 25°G

TA = full range,

-14

f = 4000 Hz
Absolute receive gain variation with temperature
and supply voltage

See Note 4

-0.1

0.1

Sinusoidal test method; reference input PGM code
corresponds to an ideally encoded -10 dBmO signal
Receive gain tracking error with level

Receive output drive voltage

Transmit and receive gain tracking error with
level (A-law, GGID G712)

3 dBmO ;::: input level;::: -40 dBmO

±0.2

-40 dBmO > input level;::: -50 dBmO

±0.4

-50 dBmO > input level;::: -55 dBmO

±0.8

RL = 10 kn

±2.5

3 dBmO ;::: input level;::: -40 dBmO

±0.25

-40 dBmO > input level;::: -50 dBmO

±0.3

-50 dBmO > input level;::: -55 dBmO

±0.45

All typical values are at V GG == 5 V, VBB = -5 V, and TA == 25°G.
:j: Absolute rms signal levels are defined as follows: VI == 1.2276 V == 0 dBmO == 4 dBm at f == 1.02 kHz with RL == 600 n.
NOTE 4: Full range for the TP3064B and TP3067B is OOG to 70oG. Full range for the TP13064B and TP13067B is -40oG to 85°G.

~TEXAS

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Pseudo-noise test method; reference input PGM
code corresponds to an ideally encoded -10 dBmO
Signal

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TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM COOEC AND FILTER
SCTS031D - MAY 1990 -REVISED JULY 1996

envelope delay distortion with frequency
PARAMETER

TEST CONDITIONS

= 1600 Hz
f = 500 Hz to 600 Hz
f = 600 Hz to 800 Hz
f = 800 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz
f = 1600 Hz
f = 500 Hz to 1000 Hz
f = 1000 Hz to 1600 Hz
f = 1600 Hz to 2600 Hz
f = 2600 Hz to 2800 Hz
f = 2800 Hz to 3000 Hz

Transmit delay, absolute (at 0 dBmO)

MIN

Transmit filter gain, relative to absolute

Receive delay, absolute (at 0 dBmO)

Receive delay, relative to absolute

TYPt

MAX

UNIT

290

315

Il s

195

220

120

145

Il s

105

130

155

180

200

Ils

-40

-25

-30

-20
70

100

125

140

175

t All typical values are at VCC =5 V, VBB =-5 V, and TA =25°C.
noise
TYPt

MAX

Transmit noise, C-message weighted:t

PARAMETER
TP3064B,TP13064B

VFXI

=0 V

dBrnCa

Transmit noise, psophometric
weighted (see Note 5)

TP3067B,TP13067B

VFXI

=0 V

-74

-69

dBmOp

Receive noise, C-message weighted

TP3064B, TP13064B

PCM code equals alternating positive
and negative zero

dBrnCO

Receive noise, psophometric
weighted

TP3067B,TP13067B

PCM code equals positive zero

-86

-83

dBmOp

-53

dBmO

Noise, single frequency

TEST CONDITIONS

VFXI+ = av,
f = 0 kHz to 100 kHz,
Loop-around measurement

MIN

UNIT

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
:tThis parameter is achieved through use of patented circuitry and is not recommended for applications in which the composite signals on the
transmit side are below -55 dBmO.
NOTE 5: Measured by extrapolation from the distortion test result

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MONOLITHIC SERIAL INTERFACE
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SCTS031 D - MAY 1990 -REVISED JULY 1996

power supply rejection
PARAMETER

Positive power-supply rejection, transmit

Negative power-supply rejection, transmit

Positive power-supply rejection, receive

Negative power-supply rejection, receive

TEST CONDITIONS

VCC = 5 V + 100 mVrms,
VFXI+ =-50 dBmO
VBB =-5 V + 100 mVrms,
VFXI+ =-50 dBmO

PCM code equals positive zero,
VCC =5 V + 100 mVrms

=0 Hz to 4 kHz

=4 kHz to 50 kHz

=0 Hz to 4 kHz

= 4 kHz to 50 kHz

=0 Hz to 4 kHz

=4 kHz to 50 kHz

PCM code equals positive zero,
VBB =-5 V + 100 mVrms

=0 Hz to 4 kHz

MIN

UNIT

I~-Iaw

dBCt

lA-law

I~-Iaw

dBCt

lA-law

I~-Iaw

dBCt

lA-law

I~-Iaw

dBCt

f =4 kHz to 50 kHz
o dBmO, 300-Hz to 3400-Hz input applied to DR (measure individual

-30

image signals at VFRO)
Spurious out-of-band signals at the
channel output (VFRO)

MAX

lA-law

=4600 Hz to 7600 Hz
=7600 Hz to 8400 Hz
f =8400 Hz to 100kHz

-33

-40

t The unit dBC applies to C-message weighting.

distortion
PARAMETER

TEST CONDITIONS

MIN

=3 dBmO
Level =0 dBmO to -30 dBmO
Level

Signal-to-distortion ratio, transmit or receive half-channel+

Level

=-40 dBmO

Level

=-55 dBmO

MAX

UNIT

33
36
Transmit

Receive

Transmit

Receive

dBCt

Single-frequency distortion products, transmit

-46

Single-frequency distortion products, receive

-46

-41

Loop-around measurement,
VFXI+ =-4 dBmO to -21 dBmO,
Two frequencies in the range of 300 Hz to 3400 Hz

Intermodulation distortion

=-3 dBmO
=-6 dBmO to -27 dBmO
Level =-34 dBmO
Level =-40 dBmO
Level =-55 dBmO
Level =-3 dBmO
Level =-6 dBmO to -27 dBmO
Level =-34 dBmO
Level =-40 dBmO
Level =-55 dBmO
Level
Level

Signal-to-distortion ratio, transmit half-channel (A-law)
(CCITT G.714)§

Signal-to-distortion ratio, receive half-channel (A-law)
(CCITT G.714)§

33
36
33.5

28.5
13.5
33
36
34.2

30
15

t The Unit dBC applies to C-message weighting.
+ Sinusoidal test method (see Note 6).
§ Pseudo-noise test method
NOTE 6: The TP13064A and TP3064A are measured using a C-message filter. The TP13067A and TP3067A are measured using a
psophometric weighted filter.

"TEXAS
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TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

crosstalk
PARAMETER

TYPt

MAX

UNIT

Crosstalk, transmit to receive

f = 300 Hz to 3000 Hz,

TEST CONDITIONS
DR at steady PCM code

-90

-75

Crosstalk, receive to transmit (see Note 7)

VFXI = 0 V,

f = 300 Hz to 3000 Hz

-90

-72

MIN

MAX

UNIT

MIN

t All typical values are at VCC = 5 V, VBB = -5 V, and TA = 25°C.
NOTE 7: Receive-to-transmit crosstalk is measured with a-50 dBmO activation signal applied to VFXI+.

power amplifiers
PARAMETER

TEST CONDITIONS
Balanced load, RL, connected
between VPO+ and VPO-

Maximum 0 dBmO rms level for better than ±0.1 dB linearity over t~e range if
-10 dBmO to 3 dBmO

Signal/distortion

RL= 600n

3.3

RL = 1200 n

3.5

RL = 30 kn

RL= 600 n

VRMS
dB

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MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D - MAY 1990 -REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION

j4-

td2

------"T"\\I

1~~2~0~~-------------_ _- - - - - - - - - - - - - -_ _------+J

TSX

tr1 -+j j4--

II --J I.II
II

tf1

I
I

14-----...-

fclock(M)

MClKX
MClKR

BClKX
th2

I I
-+l
~ ~tsu4

r-II
I ~th4

i
I
I

FSX _ _ _ _80%!c----:\.
80%
-J!20%
______________
\~.

________________________

I ______

--+l j4- td3
r---"""\r----"\r----"r---~~----""\r----\,---~r___s..80%

DX----------~

~--

'---....I \,____.1 ' -_ _----J' '-----',""-----"-----1'----......I'-~20%

BClKR

20%

th2 ---+l

j4-11
I

/4-+!- th4

-r-+ll

80%
•.____________________________~'I----------_I~-----

tsu3

_ _ _ _ _ _ _ _ _ _ _ _- J _ _ _ _ _ , _ _ _ _

~,"-

_ _- J '_ _ _ _

Figure 1. Short-Frame Sync Timing

2-208

;r::::--\

FSR _________ 20%

III

-+j tr- tsu4

•
TEXAS
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~th3

I
I

I
- . j I.--- th3

~~----~---J--~'----

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D- MAY 1990-REVISED JULY 1996

PARAMETER MEASUREMENT INFORMATION
tr1 -.j!+-

tw1

+--+l

II
1
II ~ j4- tf1 1

MClKX
MClKR

BClKX

14-1"- - - + 1 - -

~,I

r--Tf

fclock(M)

tw2

20%

I
th1 -.j

It-

11111

tsu2

td4

-+!

I++t-

fclock(B)

j4- thS

80%

~I
~I

I..

80%4
~ ______
~
~o~1

I,~

::r,\ _ _ _-+-4--_--_-_--_--_---l--r_-~~
I
I
~

td4

td1

---..I ~

I
I

--------..;,;:~;.;.;.~{trr-2_.1X'___3_.1X'__4__xr--s~t
1 ~X'___

td3

6 X 7

~I
~II

x:::!I=j}:~~
II

td3~r

BClKR

I
th1 ---.I!+-

~tsU2

thS~

20%

I
I+I

II
II

I
I

80% f~------8""""'"OOi<-:o
~----------------T1~~
FSR _ _ _2:.;;:.;0°;'~o
\....-...,.I....
j _ _ _ _ _ _ _ _ _ _ _ _+-1........._-a....

,:i::-

tsu3

-.I
II

It1111

i
h3

--.j

r--

th3

________~X'_____X'__2__X 3X4XSX6X7(!J___
Figure 2. Long-Frame Sync Timing

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-209

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

PRINCIPLES OF OPERATION
system reliability and design considerations
TP306xB, TP1306xB system reliability and design considerations are detailed in the following paragraphs.
latch-up
Latch-up is possible in all CMOS devices. It is caused by the firing of a parasitic SCR that is present due to the
inherent nature of CMOS. When a latch-up occurs, the device draws excessive amounts of current and will
continue to draw heavy current until power is removed. Latch-up can result in permanent damage to the device
if supply current to the device is not limited.
Even though the TP306xB and TP1306xB devices are heavily protected against latch-up, it is still possible to
cause latch-up under certain conditions in which excess current is forced into or out of one or more terminals.
Latch-up can occur when the positive supply voltage drops momentarily below ground, when the negative
supply voltage rises momentarily above ground, or possibly if a signal is applied to a terminal after power has
been applied but before the ground is connected. This can happen if the device is hot-inserted into a card with
the power applied, or if the device is mounted on a card with an edge connector, and the card is hot-inserted
into a system with the power on.

To help ensure that latch-up does not occur, it is considered good design practice to connect a reversed biased
Schottky diode (with a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent), between
each power supply and GND (see Figure 3). If it is possible that a TP306xB- or TP1306xB-equipped card that
has an edge connector could be hot-inserted into a powered-up system, it is also important to ensure that the
ground edge connector traces are longer than the power and signal traces so that the card ground is always
the first to make contact.
device power-up sequence
Latch-Up can also occur if a signal source is connected without the device being properly grounded. A signal
applied to one terminal could then find a ground through another signal terminal on the device. To ensure proper
operation of the device and as a safeguard against this sort of latch-up, it is recommended the following
power-up sequence always be used:
1.

Ensure no signals are applied to the device before the power-up sequence is complete.

Connect GND.

Apply VBB (most negative voltage).

Apply

Vee (most positive voltage).

Force a power down condition in the device.

Connect clocks.

Release power down condition.

Apply FSX and/or FXR synchronization pulses.

Apply signal inputs.

When powering down the device, this procedure should be followed in the reverse order.

~TEXAS

2-210

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031 D - MAY 1990 -REVISED JULY 1996

PRINCIPALS OF OPERATION

Vee
DGND

Vee
Figure 3. Diode Configuration for Latch-Up Protection Circuitry
internal sequencing
Power-on reset circuitry initializes the TP3064B, TP3067B, TP13064B, and TP13067B devices when power
is first applied, placing it into the power-down mode. OX and VFRO outputs go into high-impedance states and
all nonessential circuitry is disabled. A low level or clock applied to MCLKR/PON powers up the device and
activates all circuits. OX, a 3-state PCM data output, remains in the high-impedance state until the arrival of the
second FSX pulse.

power supplies
All ground connections to each device should meet at a common point as close as possible to ANLG-GNO. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and VBB
supplies should be decoupled by connecting 0.1-J.lF decoupling capacitors between each power rail and this
common point. These bypass capacitors must be connected as close as possible to Vee and VBB.
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than through a ground bus. This common ground point should be decoupled to
Vee and VBB with 10-J.lF capacitors.

synchronous operation
For synchronous operation, a clock is applied to MCLKX. MCLKR/PON is used as a power-down control. A logic

o applied to MCLKR powers-up the device and a high level powers it down. In either case, MCLKX is selected
as the master clock for both receive and transmit direction. BCLKX must also have a bit clock applied to it. The
selection of the proper internal divider for a master-clock frequency of 1.536 MHz, 1.544 MHz, or 2.048 MHz
can be done using BCLKR/CLKSEL. The device automatically compensates for the 193rd clock pulse of each
frame.
A fixed level on BCLKR/CLKSEL selects BCLKX as the bit clock for both the transmit and receive directions.
Table 1 indicates the frequencies of operation that can be selected depending on the state of BCLKR/CLKSEL.
In the synchronous mode, BCLKX may be in the range from 64 kHz to 2.048 MHz but must be synchronous
with MCLKX.
The encoding cycle begins with each FSX pulse, and the PCM data from the previous cycle is shifted out of the
enabled OX output on the rising edge of BCLKX. After eight-bit clock periods, the 3-state OX output is returned
to the high-impedance state. With an FSR pulse, PCM data is latched via DR on the falling edge of BCLKX (or
BCLKR, if running). FSX and FSR must be synchronous with MCLKX and MCLKR.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2-211

TP3064B, TP3067B,TP13064B,TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D - MAY 1990 -REVISED JULY 1996

PRINCIPALS OF OPERATION
asynchronous operation
For asynchronous operation, separate transmit and receive clocks can be applied. MCLKX and MCLKR must
be 2.048 MHz for the TP3064B and TP13064B, 1.536 MHz or 1.544 MHz for the TP3067B and TP13067B and
need not be synchronous. However, for best performance, MCLKR should be synchronous with MCLKX. This
is easily achieved by applying only static logic levels to MCLKRlPON. This connects MCLKX to all internal
MCLKR functions. For 1.544-MHz operation, the device compensates for the 193rd clock pulse of each frame.
Each encoding cycle is started with FSX, and FSX must be synchronous with MCLKX and BCLKX. Each
decoding cycle is started with FSR, and FSR must be synchronous with BCLKR. The logic levels shown in
Table 1 are not valid in the asynchronous mode. BCLKX and BCLKR can operate from 64 kHz to 2.048 MHz.

short-frame sync operation
The device can operate with either a short- or a long-frame sync pulse. On power up, the device automatically
goes into the short-frame mode where both FSX and FSR must be one bit-clock period long, with timing
relationships specified in Figure 1. With FSX high during a falling edge of BCKLX, the next rising edge of BCLKX
enables the 3-state output buffer, OX, which outputs the sign bit. The remaining seven bits are clocked out on
the following seven rising edges, and the next falling edge disables OX. With FSR high during a falling edge
of BCLKR (BCLKX in synchronous mode), the next falling edge of BCLKR latches in the sign bit. The following
seven falling edges latch in the seven remaining bits. The short-frame sync pulse may be utilized in either the
synchronous or asynchronous mode.

Table 1. Selection of Master-Clock Frequencies
8CLKR/CLKSEL

MASTER-CLOCK FREQUENCY SELECTED
TP30648,TP130648

TP30678,TP130678

Clock Input

1.536 MHz or 1.544 MHz

2.048 MHz

Logic Input L
(sync mode only)

2.048 MHz

1.536 MHz or 1.544 MHz

Logic Input H (open)
(sync mode only)

1.536 MHz or 1.544 MHz

2.048 MHz

long-frame sync operation
Both FSX and FSR must be three or more bit-clock periods long to use the long-frame sync mode with timing
relationships as shown in Figure 2. Using the transmit frame sync (FSX), the device detects whether a shortor long-frame sync pulse is being used. For 64-kHz operation, the frame-sync pulse must be kept low for a
minimum of 160 ns. The rising edge of FSX or BCLKX, which ever occurs later, enables the OX 3-state output
buffer. The first bit clocked out is the sign bit. The next seven rising edges of BCLKX edges clock out the
remaining seven bits. The falling edge of BCLKX following the eighth rising edge or FSX going low, whichever
occurs later, disables OX. A rising edge on FSR, the receive frame sync pulse, causes the PCM data at DR to
be latched in on the next eight falling edges of BCLKR (BCLKX in synchronous mode). The long-frame sync
pulse can be used in either the synchronous or asynchronous mode.

~TEXAS

INSTRUMENTS
2-212

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D- MAY 1990-REVISEDJULY 1996

PRINCIPALS OF OPERATION

transmit section
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors. Gains in excess of 20 dB across the audio pass band are possible via low noise and wide bandwidth.
The operational amplifier drives a unity-gain filter consisting of an RC active prefilter followed by an eight-order
switched-capacitor band-pass filter clocked at 256 kHz. The output of this filter directly drives the encoder
sample-and-hold circuit. As per Jl-Iaw (TP3064B and TP13064B) or A-law (TP3067B and TP13067B) coding
conventions, the AOC is a companding type. A precision voltage reference provides a input overload of
nominally 2.5-V peak. The sampling of the filter output is controlled by the FSX frame-sync pulse. Then the
successive-approximation encoding cycle begins. The 8-bit code is loaded into a buffer and shifted out through
OX at the next FSX pulse. The total encoding delay is approximately 290 Jls. Any offset voltage due to the filters
or comparator is cancelled by sign bit integration (see Table 2).

Table 2. Encoding Format at OX Output
TP3064B,TP13064B
~-LAW

VI = + Full scale

VI =0

1 1 1 1 1 1 1 1
0 1 1 1 1 1 1 1

VI = - Full scale

0 0

TP3067B,TP13067B
A-LAW
(INCLUDES EVEN-BIT INVERSION)

0 000 0 0

1 0

1 1 0 1 o 1 0 1
o 1 o1 0 1 o 1
001

1 0

receive section
The receive section consists of an expanding OAC that drives a fifth-order low-pass filter clocked at 256 kHz.
The decoder is Jl-Iaw (TP3064B and TP13064B) or A-law (TP3067B and TP13067B) and the fifth-order
low-pass filter corrects for the (sin x)/x attenuation caused by the 8-kHz sample/hold. The filter is followed by
a second-order RC active post-filter with its output at VFRO. The receive section is unity-gain but gain can be
added by using the power amplifiers. At FSR, the data at DR is clocked in on the falling edge of the next eight
BCLKR (BCLKX) periods. At the end of the decoder time slot, the decoding cycle begins and 10 Jls later the
decoder OAC output is updated. The decoder delay is about 10 Jls (decoder update) plus 110 Jls (filter delay)
plus 62.5 J..ls (1/2 frame), or a total of approximately180 Jls.

receive power amplifiers
Two inverting-mode power amplifiers are provided for directly driving a match-line interface transformer. The
gain of the first power amplifier can be adjusted to boost the ±2.5-V peak output signal from the receive filter
up to the ±3.3-V peak into an unbalanced 300-Q load, or±4 V into an unbalanced 15-kQ load. The second power
amplifier is internally connected in unity-gain inverting mode to give 6-dB signal gain for balanced loads.
Maximum power transfer to a 600-Q subscriber line termination is obtained by differentially driving a balanced
transformer with -Y2:1 turns ratio, as shown in Figure 3. A total peak power of 15.6 dBm can be delivered to the
load plus termination.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-213

TP3064B, TP3067B,TP13064B,TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D - MAY 1990 -REVISED JULY 1996

APPLICATION INFORMATION
power supplies
While the pins of the TP1306xB and TP306xB families are well protected against electrical misuse, it is
recommended that the standard CMOS practice be followed ensuring that ground is connected to the device
before any other connections are made. In applications where the printed-circuit board can be plugged into a
hot socket with power and clocks already present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to ANLG GND. This
minimizes the interaction of ground return currents flowing through a common bus impedance. Vee and VBB
supplies should be decoupled by connecting O.1-JlF decoupling capacitors to this common point. These bypass
capacitors must be connected as close as possible to Vee and VBB'
For best performance, the ground point of each codec/filter on a card should be connected to a common card
ground in star formation rather than via a ground bus. This common ground point should be decoupled to Vee
and VBB with 1O-JlF capacitors.

~TEXAS

2-214

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D- MAY 1990-REVISED JULY 1996

APPLICATION INFORMATION

Hybrid

300n

ZBAL

-5V

5V
300n

6
VCC

GND

VPO+
3

VPO-

R3
4

VPI

VBB
VFXI+

TP3064B
TP3067B
TP13064B
TP13067B

VFXI-

19
18
R1

GSX

17
16

R4
5
FSR
DR
BCLKR
MCLKR/PDN

NOTES: A. Transmit gain

VFRO

=20 log

B. Receive gain = 20 log

(R1 + R2). (R1 + R2)
R2

ANLG LOOP
TSX
FSX

OX
BCLKX
MCLKX

~ 10 kn

(2 x R3 )- R4 ~ 10 kn
R4

Figure 4. Typical Synchronous Application

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-215

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER
SCTS031D - MAY 1990-REVISED JULY 1996

APPLICATION INFORMATION
17
GSX

______________________________________-+_____
16_ANLG
LOOP

18
VFXI19
R1

VFXI+
Analog
Input

SwitchedCapacitor
Band-Pass Filter

Transmit
Regulator

SwitchedCapacitor
Low-Pass Filter

Receive
Regulator

CLK
R4
VFRO
Timing and Control
5V

-5V
11

·1 2·1 21
VCC

2-216

VBB

ANLG GNO

MCLKX

MCLKRI BCLKX BCLKR! FSR FSX
PON
CLKSEL

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

15
TSX

1IDI

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io
__
n _______________
Telecommunications Circuits

1IDI

~C_e_n_tr_a_I_O_ff_ic_e_C__od_e_c_s_____________
Transient Voltage Suppressors

1IDI

~R_F_f_o_r_Te_l_e_m_e_tr_y_a_n_d_R_K_E__________
Wireless Communications Circuits

1IDI
~V_o_ic_e_-_B_a_n_d_A_u_d_i_o_p_r_o_c_e_s_s_o_rs______1B
~P_r_o_ce_s_s_o_r_s_f_o_r_A_n_a_lo_g__C_e_lI_u_la_r______

~R_F_f_o_r_P_e_r_s_o_n_a_1_c_o_m_m
__
u_n_ic_a_t_io_n_s______

~B...;,._a_s_e_b_a_n_d_ln_t_e_rf_a_c_e_C_i_rc_u_i_ts_________•

---:U

L...--D_iQ
__
ita_I_S_i_Q_n_a_l_p_ro_c_e_s_s_o_r_s_______
Mechanical Data

3-1

lEI
::;I
m
:::J
en
-CD
:::J

....
~
.-m
...

to
CD

s:::
-c

"'C
CD

en
en
o.,
en

3-2

TCM1030, TCM1060
DUAL TRANSIENT·VOLTAGE SUPPRESSORS
SCTS040A - JUNE 1989 - REVISED MAY 1996

•

Meet or Exceed Bell Standard LSSGR
Requirements

•

Externally-Controlled Negative Firing
Voltage ... -70 V Max

•

Accurately Controlled, Wide Negative
Firing Voltage Range ... -5 V to -65 V

Surge Current (see Note 1):
TCM1030
TCM1060
10/1000
16 A
30 A
10/160
25 A
45 A
2110
35 A
50 A

•

D OR P PACKAGE
(TOP VIEW)

TIP[]S TIP

Vs
NC
RING

GND
GND
RING

NC - No internal connection
The D package is available taped and
reeled. Add R suffix (i.e., TCM1030DR).

High Holding Current
- TCM1030 ... 100 rnA Min
- TCM1060 ... 150 rnA Min

description
The TCM1030 and TCM1060 dual transient-voltage suppressors are designed specifically for telephone
line-card protection against lightning and transients (voltage transients) induced by ac lines. One of the TIP
terminals (pin 1 or 8) and one of the RING terminals (pin 4 or 5) are connected to the tip and ring circuits of a
SLiC (subscriber-line interface circuit). The battery feed connections between the SLiC and the subscriber line
are from the remaining TIP (pin 1 or 8) and RING (pin 4 or 5) through the TCM1 030 or the TCM1 060 to the tip
and ring lines. Transients are suppressed between tip and ground, and ring and ground.
Positive transients are clamped by diodes 01 and 02. Negative transients that are more negative than VS cause
the SCRs, Q1 and Q2, to crowbar. The high holding current of the SCRs prevent dc latchup as the transient
subsides.
The TCM1030 and TCM1060 are characterized for operation from -40°C to 85°C.

functional block diagram
TIP

-------~

TIP

7
Vs

GND

2
6

GND

D2
RING _4_ _ _ _ _ _---"

RING

NOTE 1: The notation 10/1000 refers to a waveshape having tr =10 ~s and tw =1000 ~s ending at 50% of the peak value. The notation 10/160
is tr = 10 ~s and tw = 160 ~s. The notation 2/10 is tr = 2 ~s and tw = 10 ~s.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

.TEXAS .
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3-3

TCM1030, TCM1060
DUAL TRANSIENT-VOLTAGE SUPPRESSORS
SCTS040A - JUNE 1989 - REVISED MAY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
TCM1030 nonrepetitive peak surge current (see Note 1): 10/1000 .............................. ±16 A
10/160 ............................... ±25A
2/10 ................................. ±35A
TCM1060 nonrepetitive peak surge current (see Note 1): 10/1000 .............................. ±30 A
10/160 ............................... ±45 A
2/10 ................................. ±50 A
Nonrepetitive peak surge current, tw = 10 ms, half sinewave (see Note 2) .......................... 5 A
Continuous 60-Hz sinewave at 1 A ............................................................ 2 s
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... -40°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: D or P package ................. 260°C
t

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1 The notation 10/1000 refers to a waveshape having tr =10 Ils and tw =1000 Ils ending at 50% of the peak value. The notation 10/160
is tr 10 Ils and tw 160 Ils. The notation 2/10 is tr 2 Ils and tw 10 Ils.
2. This value applies when the case temperature is at or below 85°C. The surge current may be repeated after the device has returned
to thermal equilibrium.

DISSIPATION RATING TABLE
PACKAGE

TA:5 25°C
POWER RATING

TA 85°C
POWER RATING

725mW

5.8 mW/oC

377mW

1000mW

B.O mW/oC

520mW

~TEXAS

INSTRUMENTS
3-4

OPERATING FACTOR
ABOVE TA 25°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM1030, TCM1060
DUAL TRANSIENT-VOLTAGE SUPPRESSORS
SCTS040A - JUNE 1989 - REVISED MAY 1996

electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER

VCF

Forward clamping voltage
(diode forward voltage) (see
Note 3)

TEST CONDITIONS

TCM1030

TCM1060

TYPt

MAX

IFM = 1-A transient

1.2

IFM = 10-A transient

2.5

IFM = 16-A transient

TYPt

MAX

1.2

2.5

3.1

ITM = 1-A transient

1.2

MIN

IFM = 30-A transient

ITM = 10-A transient

2.5

VC(R)

Reverse clamping voltage
(SCR on-state voltage) (see
Note 3)

ITM = 16-A transient

l!(trip)

Trip current (see Note 4)

Vs =-50 V

-100

Holding current

Vs =-50 V

-100

4.8

ITM = 30-A transient

VI (trip)

Trip voltage

Il(stby)

Standby current

-325

-100

I = trip current

-50

-55

-50

-55

Vs =-65 V,

I = trip current

-65

-70

-65

-70

±5

Transient overshoot voltage

VS=-50V,

2.5

TIP and RING at -50 V

Coff

Off-state (high impedance)
capacitance

TIP and RING at GND

dv/dt

Critical rate of rise of off-state
voltage (see Note 5)

Vs open,

VS=-50V

-1

mA
mA

Vs =-50 V,

tr = 10 ns

7
-325

-150

TIP and RING at -85 V or GND,
VS= -85 V

UNIT

-1

V
IlA
V
pF
kV/IlS

t All typical values are at TA = 25°C.
NOTES: 3. The current flows through one TIP (or RING) terminal and one of the GND terminals. The voltage is measured between the other
TIP (or RING) terminal and the other GND terminal. Measurement time:::; 1 ms.
4. The negative value of trip current refers to the current flowing out of TIP or RING on the line side that is sufficient in magnitude to
trigger the SCRs. Measurement time:::; 1 ns.
5. The critical dv/dt is measured using a linear rate of rise with the maximum voltage limited to-50 V with Vs connected to TIP or RING
being measured.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-5

TCM1030, TCM1060
DUAL TRANSIENT-VOLTAGE SUPPRESSORS
SCTS040A - JUNE 1989 - REVISED MAY 1996

TYPICAL CHARACTERISTICS
TIP OR RING CURRENT

vs
TIP OR RING TO GND VOLTAGE
0.5
0.4

Vs = -48 V
TA = 25°C

0.3

ex:
I

0.2

0.1

<.!)

-0.1

:;
u
z

a.
i=

-0.2

,
L

- -~-

-0.3

-0.4
-0.5
- 50 - 40 - 30 - 20 - 10

Tip or Ring to GND Voltage - V

Figure 1

APPLICATION INFORMATION
The trip voltage represents the most negative level of stress applied to the system. Positive transients are
clamped by diodes 01 and 02. When a negative transient is applied, current flows from Vs to TIP or RING where
the transient voltage is applied. When the current through TIP or RING reaches the pulse-trip current, the SCR
turns on and shorts TIP or RING to GND. The majority of the transient energy is dissipated in the external resistor
(nominally 100 Q for the TCM1 030 and 50 Q for the TCM1 060). Current into Vs ceases when the SCR turns
on. When the energy of the transient has been dissipated so that the current into TIP or RING due to the transient
plus the battery feed supply is less than the holding current, the SCR turns off.
To help ensure reliability and consistency in the firing voltage, it is recommended that two capacitors be
connected between V Sand GNO, as close to the device terminals as possible. One capacitor should be a 0.1 ).tF,
100 V ceramic unit and the other, a 0.47 ).tF, 100 V stacked-film (not wound) metalized plastic capacitor. If
inductance is present in the line to VS, these capacitors help prevent overshoot in the firing voltage during fast
rise-time transients.
To avoid dc latchup after the SCR has fired, the current must be less than the holding current, IH. To prevent
this from happening, the line feed current must be limited to the following conditions:
V
R

TP
line

+ 2Rp < IH

where VTP and VRP are the voltages on TIP and RING, respectively, of the TCM1030 orTCM1060.lnduced ac
currents into TIP or RING (e.g., power-line inductive coupling) must be less than the trip current to prevent the
SCR from firing.

~TEXAS

INSTRUMENTS
3-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM1030, TCM1060
DUAL TRANSIENT-VOLTAGE SUPPRESSORS
SCTS040A - JUNE 1989 - REVISED MAY 1996

APPLICATION INFORMATION
Line short-circuits to external power sources can damage the suppressor due to excessive power dissipation.
Conventional protection techniques, such as fuses or PTC (positive temperature coefficient) thermistors, should
be used to eliminate or reduce the fault current.

Control

Rccicvc
Voice
Transmit
Voice

=>
-....-

T
1

Subscriber Line
Interface Circuit
(SLlC)

~~ Vs
4

-+-

4~11:
48V

TCM1030,
TCM1060

GND
GND

RING

_,- 0.47 JlF
(see Note B)

~""'

--L
T

TIP

Rp (see Note A)

GND

VBAT

TIP

Rp (see Note A)
A

RING

0.1 JlF
(see Note C)

NOTES: A. Rp is 100 n minimum for TCM1030 and 50 n minimum for TCM1060.
B. 0.47 JlF, 100 V stacked film metalized plastic capacitor
C. 0.1 JlF, 100 V ceramic capacitor

Figure 2. Typical Line-Card Application Circuit

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3-7

3-8

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io__
n______________~1IDI
Telecommunications Circuits
Central Office Codecs
Transient Voltage Suppressors
RF for Telemetry and RKE
Wireless Communications Circuits

Processors for Analog Cellular

Voice-Band Audio Processors

III

RF for Personal Communications

•

Baseband Interface Circuits

•

Digital Signal Processors

III

Mechanical Data

4-1

4-2

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

•

Wide VHF/UHF Frequency Range: 200 MHz
to 450 MHz for World-Wide Remote Control
Frequency Compatibility
High Receiver Sensitivity ... -103 dBm at
315 MHz

•

Accepts Baseband Data Rates from 500 Hz
to 10 kHz

•

Manchester Decoded and Raw Baseband
Outputs for Easy Interface to TI
MARCSTARTM or Other Serial Data
Decoders and Microcontrollers

•

TRF (Tuned Radio Frequency) Design
Eliminates Local Oscillator (No Emissions) ,
and Reduces Many Government
Type-Approvals (Including FCC)

•

No Mixing Products Result in No Image to
Reject

•

Adjustable Internal Sampling Clock Set By
External Components

•

Internal Amplifier and Comparator for
Amplification and Shaping of Low-Level
Input Signals with Average-Detecting
Autobias Adaptive Threshold Circuitry for
Improved Sensitivity

•

Minimum External Component Count and
Surface-Mount Packaging for Extremely
Small Circuit Footprint - Typically Replaces
more than 40 Components in an Equivalent
Discrete Solution

•

No Manual Alignment When Using SAW
Filters
Advanced Submicron BiCMOS Process
Technology for Minimum Power'
Consumption

•

description
The TRF1400 VHF/UHF RZASK Remote Control
Receiver is a member' of the MARCSTAR
(Multichannel Advanced Remote Control Signalling Transmitter and Receiver) family of remote
control serial data devices specifically designed
for RZ ASK (Return-to-Zero Amplitude-Shift
Keyed) communications systems operating in the
200 MHz - 450 MHz band. These devices are
targeted for use in automotive and home security
systems, garage door openers, remote utility
metering, and other low-power remote control and
telemetry systems.
A complete RZ ASK receiver solution on a chip,
the TRF1400 requires only a minimum of external
components for operation. This significantly
reduces the complexity and footprint of new
designs compared with current discrete receiver
designs. The TRF1400 requires no manual
alignment when using external SAW (surface
acoustic wave) filters. For a lower cost solution,
the device is also compatible with external LC
components.

!i:a:

OW PACKAGE
(TOP VIEW)

LPF
AGND
RFIN3
AVec
AGND
AVec
AGND
OFFSET
AGND
OSCR
OSCC
DVcc

10
2
3
4
5
6
7

8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

RFOUT2
LNA2T
RFIN2
AGND
RFOUT1
LNA1T
RFIN1
AGND
DOUT
TRIG
BBOUT
DGND

o
u.
z
w

z
~
C

o
m

-n

:xJ

o
z

NOM

MAX

UNIT

Supply voltage, Vee

4.5

5.5

Input frequency, fin

200

450

MHz

Operating free-air temperature, TA

-40

°e

Minimum permissible AM modulation of RF envelope, measured at -102 dBm at RFINPUT

25%

electrical characteristics as measured in the test circuit detailed in Figures 1 through 6 with
fin 315 MHz over recommended ranges of supply voltage and operating free-air temperature,
typical values are at Vee 5 V and TA 25°C (unless otherwise noted)

current consumption
PARAMETER
lee

TEST CONDITIONS

1/0 pins terminated with typical loads

Average supply current from Vee

digital interface
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

TEST CONDITIONS
: DOUT, TRIG, BBOUT

MIN

MAX

0.5

IOL=-3.2 mA

UNIT
V

Vee- 0 .5

10H =3.2 mA

VSWR (voltage standing-wave ratio), ripple rejection
PARAMETER
VSWR into 50

n (requires external Le matching network), RFIN1, RFOUT1, RFIN2, RFOUT2, RFIN3

Ripple rejection, 1 MHz (injected at AVee and DVee), measured at BBOUT while maintaining
BER = 3/100 with desired carrier at -50 dBm (see Note 2)
NOTE 2: BER (bit error rate -

TVP

MAX

2:1
6% Vee

errorslnumber of bits) is qualified by integration of logic-level pulses (>50% high = 1, <50% low = O).

~TEXAS

INSTRUMENTS
4-6

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
VN

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

RF sensitivity/overload
TEST CONDITIONS

PARAMETER
RF input (average) at test board RF input required for BER
3/100 (see Note 2) at 5 kHz baseband data rate,
2.5 kHz Manachester data rate
Overload signal at fc with BER 3/100 at 5 kHz
(see Note 2) baseband data rate,
2.5 kHz Manchester data rate
NOTES:

VCC= 5 V,

MIN

TYP

fin = 315 MHz,
external SAW preselector bandpass filter
(see Note 3)
VCC = 5 V,
fin = 315 MHz

MAX

UNIT

-103

dBm

TA = 25°C,

-20

TA = 25°C,

dBm

2. BER (bit error rate = errors/number of bits) is qualified by integration of logic-level pulses (> 50% high = 1, < 50% low = 0).
3. The SAW bandpass filter must have a rejection level greater than or equal to 50 dB at ±0.5 fc, insertion loss of less than or equal
to 3 dB, and a -3 dB passband width of 0.2% fc.

oscillator (internal clock)
PARAMETER
Sample clock frequency, SCLK (5x baseband data rate, 10x Manchester data rate)

MIN

MAX

2.5

UNIT
kHz

±5%

Frequency spread (process variation, temperature, VCC), not including external component tolerance

z
o

timing requirements
RF input data (see Figure 7)
MIN

MAX

UNIT

Rise time, RF input data

0.1 tc1

fls

Fall time, RF input data

0.1 tc1

fls

received data
Baseband data frequency AM RZ ASK

MIN

MAX

0.5

kHz

0.25

Manchester data frequency AM RZ ASK
Pulse period tolerance for synchronization, valid TRIG and DOUT data

UNIT

Dead time between wakeup time and frame start time (for synchronization valid, TRIG and
DOUT data) (see Figure 8)

tw3

Duration, modulated RF carrier (see Figure 9)

51%

38+SCLK

317 + SCLK

100

2000

fls

TYP

MAX

UNIT

switching characteristics
device latency, for BBOUT, TRIG, DOUT (see Figure 9)
PARAMETER

MIN

Demodulation delay time across device (RFINPUT to BBOUT)

td1

Delay time between BBOUT

td2

Delay time between DOUT

and TRIG

1.9+ SCLK

t and TRIG t

2.5+ SCLK

ms
fls
3.2 + SCLK

0.5+ SCLK

fls
fls

RF carrier (see Figure 9)
PARAMETER

MIN

TYP

MAX

UNIT

two

Duration, logic 0 data cell

2t w 3

fls

tw1

Duration, logic 1 data cell

2t w 3

fls

tw2

Duration, trigger pulse

0.5+SCLK

fls

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

49%

Delay time between power applied and output signal at BBOUT

a:
o
u.

±8%

Pulse duty cycle for synchronization, valid TRIG and DOUT data

4-7

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TRF1400 electrical characteristics were measured with the device connected in the circuit shown in Figure 1.
As with any RF design, the successful integration of the device into a circuit board relies heavily on the layout
of the board and the quality of the external components. Figure 2 through Figure 6 show layout artwork for the
production of the circuit board used to obtain the TRF1400 electrical characteristics. Table 1 lists the parts
required to complete the test circuit, which demonstrates TRF1400 performance at 315 MHz. Specified
component tolerances and where applicable, Q, should be observed during the selection of parts.
A complete set of Gerber photoplotter files for the circuit board can be obtained from any TI Field Sales Office.
R8

RF Input

Z
0

C20

-=-

R7
TRIG

h
L1

DOUT

-=C4

T-=

C19

'J'C2
-

R6
BBOUT

C18

-=-

-Z

L2
N

e
12

R4
DVCC

C15

C16

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

Figure 2. TRF1400 Test Circuit Board Layout - Top Side

:.:~:.;

'C:::=~~o

....... ~

• • •••••• ~

•

:_ • • °0

o
u.

~::

: •••

....

:.~~

•

.:: ••:":: .. ~
.. ::~:
°

••
••••
0

•

E:35

•••••••• ~••••• o.

Figure 3. TRF1400 Test Circuit Board Layout - Bottom Side

RFIN

o
m

10%

-z

I
tr

'TI

--.j
Rise Time

Figure 7. RFIN1 Rise and Fall Times

o
z

•
TEXAS
INSTRUMENTS
4-12

MANUFACTURER PIN

680n

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

G-12AP

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
Manchester data format and timing
The TRF1400 requires specific Manchester data formatting and timing to decode and output Manchester serial
data. For the TRF1400 to output meaningful function data at the TRIG and DOUT terminals, the incoming RF
signal must have the Manchester-encoded binary format and timing shown in Figure 8 (for 50 kHz SCLK). A
wakeup time and frame-start time is required for the device to synchronize with the incoming data. The wakeup
time is designated by a data-bit 0 and data-bit 1 data sequence repeated five times.
Figure 9 shows Manchester-encoded function data timing.

1
1

Data 1

RF
INPUT

1
1

Function Data Starts
(see Figure 9)

11011011101 1 1
1
1
1
I
1
I

1
1

10011s~

1
1

14-

~ tx

1 (0.76ms- .._ _ _ _ _-

~ 200l1s SCLK =50 kHz '
j4-- Wakeup Time =200 I1s x 10 =2 ms

1 6.34 ms)

~!4----

1.6ms

(DOUT, TRIG Active During This Time)

-.!

(BBOUT Active During This Time)

1
1
.1

--.I

1
1

Frame Start Time

=3.6 ms -----~~

o
~

o
LL

Figure 8. Manchester-Encoded RF Binary Data Format at RF Input

Data 0
RF
INPUT

BBOUT

H.1
1

I td1~

~l
rt- tw1 -t-fi

14-- two ---.I

. I

TRIG

Data 0

Data 1

DOUT

Data 1

td2~

~
c

HI H:::I

'__---1'"""--_.....

1
1
1

1+--1

I VOH
VOL

_-+ _____ ~

~t-. . ;.I__--,n. . .~_---,n

ro :::

t w2---+i ~

Figure 9. Manchester-Encoded Function Data Timing Diagram

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

4-13

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014-JUNE 1996

PRINCIPLES OF OPERATION
general
The TRF1400 VHF/UHF RZ ASK Remote Control Receiver demodulates AM RZ ASK modulated RF carriers
between 200 MHz and 450 MHz with a 500-Hz to 1O-kHz baseband data rate or a 250-Hz to 5-kHz Manchester
data rate.
signal reception
The RF signal is collected by an antenna and then passed through an LC matching network to bandpass-filter
the signal and compensate for various antenna loading impedances. The signal is then input to the RFIN1
terminal of the TRF1400.
signal path through device
The RF signal applied to the RFIN1 terminal is amplified by LNA 1 and LNA2. The combined gain ofthe two LNAs
is 40 dB, with a 1-dB compression point of -80 dBm, and a noise figure of 5 dB (nominal). The amplified signal
is output at RFOUT2 and enters an external preselector bandpass filter before being applied to the third stage
of amplification at terminal RFIN3.

»c

The third stage of amplification consists of a single-ended-input to differential-output amplifier followed by six
high-gain differential log-detecting amplifier stages with an equivalent gain of 60 dB (nominal). First, the signal
is converted to a differential signal for increased noise immunity. Next, the differential signal is passed through
the six high-gain differential log-detecting amplifiers, forming a detection circuit. Each log-detecting amplifier
is biased such that when an RF signal is present, an imbalance is caused in its bias circuit. The imbalance in
each of the six stages is converted to a voltage and then summed into a baseband envelope representation of
the RF signal. This signal then passes through an autoleveling circuit before being applied to a comparator to
produce the TTL-level baseband signal output that appears at BBOUT. An external low-pass filter connected
to BBOUT attenuates high-frequency transients in the output signal.

~
z(")

The demodulated signal is also applied to the Manchester decoding and timing recovery logic section of the
TRF1400. The Manchester decoding section has two outputs, TRIG and DOUT, which should be externally
low-pass filtered to attenuate high frequency transients. The signals appearing at these outputs are meaningful
only when the received Manchester-encoded data is formatted and timed as shown in Figure 9.

When Manchester-encoded data is received and demodulated, Manchester serial data is output at DOUT and
a trigger pulse is output at TRIG. The TRIG pulse rises at the start of each decoded data bit appearing at DOUT.
The DOUT and TRIG outputs are not required in an application incorporating a TI MARCSTAR TRC1300/1315
Remote Control Transmitter/Receiver due to the autosynchronization available on that decoder.

frequency adjustment
The TRF1400 requires no manual alignment. The receive frequency is dependent only on the choice of external
matching networks and preselecting filters used. In that respect, the user has only to stock a different set of
external components for each frequency, and no manual alignment or end-of-line frequency programming need
be performed.
decoder interface
For baseband operation, the TRC1300/1315 4-function, 40-bit rolling-code decoder can be interfaced directly
to the TRF1400 using the baseband-data output (BBOUT) of the device. The TRC1300/1315 decodes the
received data into instructions that it then executes.
For Manchester operation, a standard microcontroller decoder must know when to poll its input for data. The
TRF1400 provides an output terminal (TRIG) for this purpose that pulses on each valid received data cell. In
this system configuration, Manchester-encoded binary data must be used in the format described below to allow
the TRF1400 to synchronize properly and produce the TRIG and DOUT outputs.

~TEXAS

4-14

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014-JUNE 1996

PRINCIPLES OF OPERATION
external components and device performance
While the TRF1400 uses a minimum of external components in the typical application, the choice of those
components greatly affects the performance of the device. When a SAW preselector is used, the selectivity
(out-of-band rejection) and sensitivity of the TRF1400 are optimized as a result of the high Q of the SAW devices.
If an LC preselector is used, these parameters change and the overall performance of the TRF1400 is reduced,
but can still meet the requirements of many end-equipment applications.
An external resistor connected between OFFSET and ground adjusts the internal offset voltage of the receiver
decoding section to maximize the noise rejection of the device. While a 1-MQ resistor is suggested, this value
can be changed to minimize toggling of outputs DOUT, TRIG, and BBOUT during periods of nonvalid received
code.
internal clock/synchronization
An internal clock (SCLK) is used by the TRF1400 for processing the demodulated incoming data stream and
for controlling the Manchester-decoding and timing-recovery logic sections of the device. The frequency of
SCLK is set by an external resistor connected between the OSCR and OSCC terminals and an external
capacitor connected between OSCC and GND, and is adjustable between 2.5 kHz and 50 kHz.
For baseband output, SCLK is set to 5x the received baseband data rate (500 Hz to 10kHz). Incoming baseband
data is then sampled at 5x its transmitted data rate. TTL-level baseband data is output at BBOUT whenever
the TRF1400 receives ASK-modulated data in any format. This provides compatibility with systems that use
other code formatting, and whose serial data decoders do not require the DOUT or TRIG outputs from the
receiver.
For Manchester data output, SCLK must be set to 1Ox the received Manchester-encoded data rate (250 Hz to
5 kHz), for the output signals at TRIG and DOUT to be meaningful. The high sampling rate (10x) ensures
accurate correlation of the received signal.
The received Manchester data rate (set by a clock on the transmitter/encoder end) can vary as much as ± 8%
and TRF1400 synchronization still results. This allows for frequency drift due to external component tolerances
and temperature changes on the transmitter end. At the TRF1400 end, a ±8% frequency variation is also
allowed. Thus, the total permissible frequency variation from transmitter clock to receiver clock can be as much
as ±16%. For example, if a serial Manchester data rate of 1.5 kHz is used at the encoder/transmitter end, then
the TRF1400 sample clock oscillator (SCLK) must be set to 1Ox the transmitted data rate, or 15 kHz. SCLK is
allowed to vary ±8% in frequency, from 13.8 kHz to 16.2 kHz in this case, and the TRF1400 synchronizes
successfully to the incoming data. The data rate of the incoming data itself can also vary the same amount. It
is left to the user to design the system such that the transmitter/encoder data rate drifts ±8% or less. The
TRF1400 can introduce as much as a ±5% frequency variation due to its internal tolerances and semiconductor
process variations, so the external resistor and capacitor values used with the TRF1400 can have up to a ±3%
value tolerance.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-15

z
o

~
~

o
Ll.
Z

o
Z

~
C

<3:

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014-JUNE 1996

PRINCIPLES OF OPERATION
internal clock/synchronization (continued)
The internal clock speed is set by connecting a resistor between OSCR and OSCC and a capacitor between
OSCC and GND. The following equation defines the sample clock (SCLK) speed as a function of the external
resistor and capacitor:

Fosc = _ _ _-:--_ _....!1~-_:__-----:1.386
Where:

(Rext

Rs)

(C ext

+ C p)

Rext is the external resistor connected between OSCR and OSCC.
Rs is the internal series resistance, typically 100 or less.
Cext is the external capacitor connected between OSCC and GND.
C p is parasitic capacitance and is dependant on board layout - typical value is 5 pF.

For minimum current draw, large values (in the thousands of ohms) for Rext should be used. Typical Rext values
and the resulting SCLK frequency when C ext = 100 pF are shown in Figure 10.

100

>u
t:

-Z

I
=100 pF

o
m

Cext

:I
C"

-n

o
:c

..I

"'"'"

()
CJ)

~ t----

o
z

300

600

900

1200

1500

---

1800

R - Resistance -

r---

2100

2400

2700

Figure 10. External Resistance Versus Sample Clock Frequency

~TEXAS

INSTRUMENTS
4-16

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3000

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

APPLICABLE REGULATIONS
Receiver design, as well as transmitter design, is regulated throughout the world. Since the TRF1400 is targeted for
world-wide sales, the applicable standard for each region must be considered when the device is to be used in
systems to be successfully marketed in that region. Forthis reason, the TRF1400 conforms to all requirements shown
in Figure 11 and Table 2. The primary specifications of most of the standards address carrier frequency and spurious
emissions.
CANADA
Dept. of Communications (DoC),
Telecom Regulatory Service,
Radio Standard Specifications
(RSS), RSS-210, 260-470 MHz
and 902-928 MHz

~APA"

Ministry of Posts &
Telecommunications
~T)<322MHZ

o
~

USA
Federal Communications
Commission (FCC) Code of
Federal Regulations 47
(CFR 47) Parts 15.35,15.205,
15.209, and 15.231, 260-470 MHz,
and Part 15.249, 902-928 MHz
(see Note 6)

:a:

SOUTH AFRICA
403.916 MHz and
411.6 MHz

ou.

Dept. of Transportation and
Telecommunications (DTC),
and ECR60, 303.825 MHz
and 318 MHz

o
Z

GERMANY
Femmeldetechnisches
Zentralamt (FTZ), FTZ
17 TR 2100, 433.92 MHz

UNITED KINGDOM
Dept. of Trade and Industry
(DTI), MPT 1340, 418 MHz,
and for automotive only:
433.92 MHz

~
Z

:JJ

REGULATION

FREQUENCY

USA

Federal Communications Commission (FCC) Code of
Federal Regulations 47 (CFR 47) Parts 15.35, 15.205,
15.209, 15.231, and 15.249 (see Note 4)

Germany

Femmeldetechnisches Zentralamt (FTZ), FTZ 17 TR21 00

433.92 MHz

France

Centre National d'Etudes des T'el'ecommunications
(National Telecom Research Center, CNET), Groupement
Terminaux Procedures et Applications (Terminals,
Procedures and Applications Group, TPA), Specification
Technique (ST), ST/PAAlTPNAGH/1542

233.5-225 MHz (automotive only)

United Kingdom

Dept. of Trade and Industry (DTI), MPT 1340

418 MHz
433.92 MHz (automotive only)

260-470 MHz (Part 15.35,15.205,15.209)
902-928 MHz (Part 15.249, see Note 4)

Japan

Ministry of Posts and Telecommunications (MPT)

< 322 MHz

Canada

Dept. of Communications (DoC), Telecom Regulatory
Service, Radio Standard Specifications (RSS), RSS-210

260-470 MHz (RSS-21 0)
902-928 MHz

Hong Kong

Post Office, Telecom Branch, Telecom Order 1989,
Sec 39, Cap. 106

314 MHz

Australia

Dept. of Transportation and Telecommunications (DTC),
and ECR60

303.825 MHz and 318 MHz

Israel

Ministry of Communications, Engineering & Licensing Div.

South Africa

325 MHz
403.916 MHz and 411.6 MHz

NOTE 4: Although the FCC Part 15.231 allows low-power unlicensed radios in the range of 260 MHz to 470 MHz, not all frequencies in this range
are desirable. This is due to emission restrictions applying to fundamentals and harmonics in various forbidden bands as defined in Parts
15.205 and 15.209. USA frequencies shown above conform to these additional restrictions and are commonly used in the USA. Under
Part 15.249, transmitters may continuously radiate 50 000 IlV/m at 3 meters with simple modulation. Part 15.247 permits still higher
power, but must use true spread-spectrum modulation. See FCC CFR 47, Part 47, Part 15 for details.

~TEXAS

INSTRUMENTS
4-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

APPLICATION INFORMATION
typical receiver/decoder application
The application example shown in Figure 12 uses the TRF1400 VHF/UHF RZ ASK Remote Control Receiver
interfaced with the TI MARCSTAR TRC1300/1315 Decoder, which illustrates the receive side of an RF-linked remote
control system. This configuration is typically used in automotive and home security systems as well as in telemetry
applications such as utility meter remote monitoring.
U1 is a TRF1400 and is supported by the external components shown. A parallel LC circuit can be substituted for
the SAW preselector filter. Because the receiver is interfaced to the TI MARCSTAR decoder that self-synchronizes
to baseband information, only the baseband output BBOUT is used.
U2 is a MARCSTAR 4-function, 40-bit rolling-code encoder/decoder device (TRC1315) configured as a serial data
decoder (CONF low). The TRC1315 can be powered by a 12-V supply and provides a regulated 5 V forthe TRF1400
receiver. PROG is held low to disable the program mode. Both the encoder (at the transmitting end, not shown) and
decoder are set to a 1-kHz data clock frequency using an external RC network at OSCC and OSCR. When U2
receives valid function code, the corresponding output(s) on U2 go low and LED 1 - LED 4 light for the length of time
valid code frames are received. The RX LED also lights during valid received code. In an actual system, the
VCRITX1 - VCRITX4 outputs of the TRC1315 are connected to various functions, such as an auto alarm, door locks,
or trunk lock activation.
Both devices require power supply bypassing. A 1-IlF electrolytic capacitor in parallel with a O.1-IlF ceramic capacitor
(low ESR, high-frequency capacitor, such as CK-05 type recommended) should be connected from the positive
supply to ground. These capacitors should be placed as close as possible to the device Vee and GND terminals.

o
~

a:
a:
o
LL
Z

o
Z

~
c

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-19

TRF1400
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS014 - JUNE 1996

APPLICATION INFORMATION

-=-=-=23

24
N

<
z
..J

SAW or LJC
Preselector

22
l-

l::l

20 19
~
::l
0

u::

(!J

I-

;(

::l

m
m

..J

U1 (TRF1400 MARCSTAR Remote Control Receiver)

Z
(!J

o
m

(J
(J

~ C

(!J

..J

c
z

C
LL

zi1
o

:xl

12Vdc

0.11lF

o
z

TO. 1 IlF

LED1-LED4
R1-R4
1600n

+
1 F
1l

c..
c(

R5 1600 n

11
"2'

I-

(J)

W
I-

CO)

I:::I

U2 (TRC1315 MARCSTAR Decoder)

u..

0
0

C!l
0

a:
c..
3

>
0

LEDRX

12
0
0

0
0

..J

(J)

C!l

Figure 12. MARCSTAR Receiver/Decoder Using Baseband Data Output

~TEXAS

INSTRUMENTS
4-20

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043 - JUNE 1996

Wide VHF/UHF Frequency Range .•. 200
MHz to 450 MHz for World-Wide Remote
Control Frequency Compatibility
High Receiver Sensitivity ... -102 dBm at
315 MHz

•

Accepts Baseband Data Rates from 500 Hz
to 10 kHz

•

TRF (Tuned Radio Frequency) Design
Eliminates Local Oscillator (No Emissions)
and Reduces Many Government
Type-Approvals (Including FCC)

•

No Mixing Products Result in No Image to
Reject

•

Internal Amplifier and Comparator for
Amplification and Shaping of Low-Level
Input Signals with Average-Detecting
Autobias Adaptive Threshold Circuitry for
Improved Sensitivity
Minimum External Component Count and
Surface-Mount Packaging for Extremely
Small Circuit Footprint - Typically Replaces
more than 40 Components in an Equivalent
Discrete Solution
No Manual Alignment When Using SAW
Filters
Advanced Submicron BiCMOS Process
Technology for Minimum Power
Consumption

description
The TRF141 0 VHF/UHF RZ ASK Remote Control
Receiver is a member of the MARCSTAR
(Multichannel Advanced Remote Control Signalling Transmitter and Receiver) family of remote
control serial data devices specifically designed
for RZ ASK (Return-to-Zero Amplitude-Shift
Keyed) communications systems operating in the
200 MHz-450 MHz band. This device is targeted
for use in automotive and home security systems,
garage door openers, remote utility metering, and
other low-power remote control and telemetry
systems.
A complete RZ ASK receiver solution on a chip,
the TRF141 0 requires only a minimum of external
components for operation. This significantly
reduces the complexity and footprint of new
designs compared with current discrete receiver
designs. The TRF1410 requires no manual
alignment when using external SAW (surface
acoustic wave) filters. For a lower cost solution,
the device is also compatible with external LC
components.

3=
->W
W

OW PACKAGE
(TOP VIEW)

RFOUT2
AGND
RFIN3
AGND
AVcc
AGND
AGND
AVcc
BBOUT
AGND

2
3
4
5

19
18

15
14
13
12
11

7
8
9

17
16

LNA2T
RFIN2
AGND
AGND
RFOUT1
LNA1T
RFIN1
OFFSET
LPF
AVcc

a:
a.

....

::l
C

a:
a.

The TRF141 0 also includes several on-chip features that would normally require additional circuitry in a receiver
system design. These include two low-noise front-end amplifiers, an RF amplifier/comparator for detection and
shaping of input signals, and a demodulated RZ ASK baseband TTL-level output that readily interfaces to
self-synchronizing devices such as the TI rolling-code MARCSTAR decoder (TRC1300ITRC1315).

MARCSTAR is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW Information concerns products in the formative or
design phase of development Characteristic data and other

~~:~~~~~~~:c~~ti~~~l~e~~a~~o~~~~ ~~~~u~~~Wc~serves the right to

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-21

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043 - JUNE 1996

description (continued)
The TRF141 0 VHF/UHF RZ ASK remote control receiver is available in a 20-pin SOIC (DW) package, and is
characterized for operation over the temperature range of -40°C to 85°C. The DW package is available taped
and reeled. Add R suffix to device type (e.g., TRF1410R).

functional block diagram
RFOUT2

AGND

RFIN3

AGND

-4---'-1--------,

LNA2T

RFIN2

RF LNA 2

AGND

""C

AVec

c:
0

AGND

-I
""C

AGND

m
S
m

AVec

RF LNA 1

LNA1T

RFIN1

8
13

Autolevel

RFOUT1

OFFSET

+-BBOUT

LPF

T
AGND

~TEXAS

4-22

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AVCC

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043-JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

AGND

2,4,
6,7,
10,17,
18

AVCC

5,8,
11

1/0

DESCRIPTION
Analog ground for all internal analog circuits. All analog signals are referenced to these terminals.

Positive power supply voltage for all analog circuits -

4.5 V to 5.5 V.

BBOUT

Baseband data output. This is the demodulated envelope of the recovered RF signal. BBOUT is active with any
received ASK signal coding format.

LNA1T

Low-noise amplifier (LNA) #1 ground termination. LNA 1T should be connected to AGND through a parallel
resistor-capacitor bias network. If left unconnected, the LNA is disabled.

LNA2T

Low-noise amplifier (LNA) #2 ground termination. LNA2T should be connected to AGND through a parallel
resistor-capacitor bias network. If left unconnected, the LNA is disabled.

LPF

External low-pass capacitor used in the average-detecting adaptive threshold circuitry.

OFFSET

Connection to external offset resistor. This resistor (1 MQ suggested) sets the internal threshold detector offset
voltage. Lowering the value of this resistor decreases device sensitivity.

RFIN1

RF input to first low-noise, high-gain amplifier stage.

RFIN2

RF input to second low-noise, high-gain amplifier stage.

RFIN3

RF input to the detecting RF amplifier stages. Filtered RF in the form of AM RZ ASK data at frequencies between
200 MHz and 450 MHz, at a baud rate between 500 Hz and 10kHz can be applied to this terminal for detection
and decoding.

RFOUT1

RF output of the first low-noise, high-gain amplifier.

RFOUT2

RF output of the second low-noise, high-gain amplifier. Typically, the input of an external SAW or LC filter is
connected to this terminal.

:;:
w

a:
c..
I-

a:
c..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-23

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043 - JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, AVCC, DVCC (see Note 1) .......................................... -0.6 to 6
Input voltage range, VI ................................................................. -0.6 to 6
Continuous total power dissipation ........................................................ 180 mW
Operating free-air temperature range, TA ............................................ -55°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
ESD protection, all terminals: human body model ............................................. 2 kV
machine model ................................................ 200 V
JEDEC latchup .................................................................. 150 mA or 11 V

recommended operating conditions
MIN

""C

o----I
m
S
m

MAX

UNIT

4.5

5.5

Input frequency, fin

200

450

MHz

Operating free-air temperature, TA

-40

Minimum permissible AM modulation of RF envelope, measured at -102 dBm at RFINPUT

°C

25%

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature, typical values are at fin = 315 MHz, Vee = 5 V, and TA = 25°C (unless otherwise noted)
current consumption

""C

NOM

Supply voltage, Vee

PARAMETER
lee

TEST CONDITIONS
I/O pins terminated with typical loads

Average supply current from Vee

digital interface
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

TEST CONDITIONS

MIN

:BBOUT

MAX

Vee- 0 .5

10H =3.2 mA

V
0.5

IOL=-3.2 mA

UNIT

VSWR (voltage standing-wave ratio), ripple rejection
PARAMETER
VSWR into 50

n (requires external Le matching network), RFIN1, RFOUT1, RFIN2, RFOUT2, RFIN3

Ripple rejection, 1 MHz (injected at AVee and DVee),
measured at BBOUT while maintaining BER = 3/100 with desired carrier at -50 dBm (see Note 2)
NOTE 2:

BER (bit error rate -

TYP

MAX

2:1
6% Vee

errors/number of bits) is qualified by integration of logic-level pulses (> 50% high = 1, < 50% low = 0).

~TEXAS

INSTRUMENTS
4-24

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT
VN

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043-JUNE 1996

RF sensitivity/overload
PARAMETER

TEST CONDITIONS

RF input (average) at test board RF input required for BER
3/100 (see Note 2) at 5 kHz baseband data rate

fin = 315 MHz,
external SAW preselector bandpass filter
(see Note 3)

Overload signal at fc with BER 3/100 at 5 kHz
(see Note 2) baseband data rate

Vee= 5V,
fin = 315 MHz

NOTES:

MIN

TYP

MAX

UNIT

-102

dBm

TA = 25°e,

Vee =5V,

-20

TA = 25°e,

dBm

2. BER (bit error rate = errors/number of bits) is qualified by integration of logic-level pulses (> 50% high = 1, < 50% low = 0).
3. The SAW bandpass filter must have a rejection level greater than or equal to 50 dB at ±O.5 fc, insertion loss of less than or equal
to 3 dB, and a -3 dB passband width of 0.2% fc.

timing requirements
RF input data (see Figure 1)t
MIN

MAX

UNIT

Rise time, RF input data

0.1 tc1

Fall time, RF input data

0.1 tc1

t tc1

is the duration of the modulated RF carrier.

received data
Baseband data frequency AM RZ ASK

MIN

MAX

0.5

:>
W
a:

a.
t-

90%

::J
C

RFIN

a:
a.

10%

tr~

j4-tf

Rise Time

Figure 1. RFIN1 Rise and Fall Times

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-25

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043 - JUNE 1996

PRINCIPLES OF OPERATION
general
The TRF141 a VHF/UHF RZ ASK Remote Control Receiver demodulates AM RZ ASK modulated RF carriers
between 200 MHz and 450 MHz with a 500-Hz to 1a-kHz baseband data rate.

signal reception
The RF signal is collected by an antenna and then passed through an LC matching network to band-pass filter
the signal and compensate for various antenna loading impedances. The signal is then input to the RFIN1
terminal of the TRF141 O.

signal path through device
The RF signal applied tothe RFIN1 terminal is amplified by LNA1 and LNA2. The combined gain of the two LNAs
is 40 dB, with a 1-dB compression point of -80 dBm, and a noise figure of 5 dB (nominal). The amplified signal
is output at RFOUT2 and enters an external preselector band-pass filter before being applied to the third stage
of amplification at terminal RFIN3.
The third stage of amplification consists of a single-ended-input to differential-output amplifier followed by six
high-gain differential log-detecting amplifier stages with an equivalent gain of 60 dB (nominal). First, the signal
is converted to a differential signal for increased noise immunity. Next, the differential signal is passed through
the six high-gain differential log-detecting amplifiers, forming a detection circuit. Each log-detecting amplifier
is biased such that when an RF signal is present, an imbalance is caused in its bias circuit. The imbalance in
each of the six stages is converted to a voltage and then summed into a baseband envelope representation of
the RF signal. This signal then passes through an autoleveling circuit before being applied to a comparator to
produce the TTL-level baseband signal output that appears at BBOUT. An external low-pass filter connected
to BBOUT attenuates high-frequency transients in the output signal.

'"1J

::c
o
o
c:
(")

-I
'"1J

frequency adjustment

:c
m
<
-

The TRF141 a requires no manual alignment. The receive frequency is dependent only on the choice of external
matching networks and preselecting filters used. In that respect, the user has only to stock a different set of
external components for each frequency, and no manual alignment or end-of-line frequency programming need
be performed.

decoder interface
The TRC1300/1315 four-function, 40-bit rolling-code decoder can be interfaced directly to the TRF141 a using
the baseband-data output (BBOUT) of the device. The TRC1300/1315 decodes the received data into
instructions that it then executes.

external components and device performance
While the TRF141 a uses a minimum of external components in the typical application, the choice of those
components greatly affects the performance of the device. When a SAW preselector is used, the selectivity
(out-of-band rejection) and sensitivity of the TRF141 a are optimized as a result of the high Q of the SAW devices.
If an LC preselector is used, these parameters change and the overall performance of the TRF141 a is reduced,
but can still meet the requirements of many end-equipment applications.
An external resistor connected between OFFSET and ground adjusts the internal offset voltage of the receiver
decoding section to maximize the noise rejection of the device. While a 1-Mn resistor is suggested, this value
can be changed to minimize toggling of output SBOUT during periods of nonvalid received code.

~TEXAS

4-26

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043 - JUNE 1996

APPLICABLE REGULATIONS
Receiver design, as well as transmitter design, is regulated throughout the world. Since the TRF141 0 is targeted
for world-wide sales, the applicable standard for each region must be considered when the device is to be used
in systems to be successfully marketed in that region. For this reason, the TRF1410 conforms to all
requirements shown in Figure 2 and Table 1. The primary specifications of most of the standards address carrier
frequency and spurious emissions.
CANADA
Dept. of Communications (DoC),
Telecom Regulatory Service,
Radio Standard Specifications
(RSS), RSS-210, 260-470 MHz
and 902-928 MHz

USA
Federal Communications
Commission (FCC) Code of
Federal Regulations 47
(CFR 47) Parts 15.35, 15.205,
15.209, and 15.231, 260-470 MHz,
and Part 15.249, 902-928 MHz
(see Note 6)

APAN
Ministry of Posts &
Telecommunications
;T)<322MHZ

>
w

SOUTH AFRICA
403.916 MHz and
411.6 MHz

Dept. of Transportation and
Telecommunications (DTC),
and ECR60, 303.825 MHz
and 318 MHz

a..

::l

GERMANY
Femmeldetechnisches
Zentralamt (FTZ), FTZ
17TR 2100, 433.92 MHz

c..

UNITED KINGDOM
Dept. of Trade and Industry
(DTI), MPT 1340, 418 MHz,
and for automotive only:
433.92 MHz

The Interim European
Telecommunications Standard, I-ETS 300
220 (433.92 MHz) is proposed by the
European Telecommunications
Standards Institute (ETSI) for all
European Community (EC) countries.
Most European countries not shown
currently use 433.92 MHz according to
CEPT recommendations and are likely to
adopt rules similar to ETSII-ETS 300 220.

FRANCE
Centre National d'Etudes des
T'el'ecommunications
(National Telecom Research Center, CNET),
Groupement Terminaux Procedures et
Applications (Terminals, Procedures, and
Applications Group, TPA), Specification
Technique (ST), ST/PAAlTPAlAGH/1542,
223.5-225 MHz and for automotive only:
433.92 MHz

Figure 2. World-Wide Receiver Regulations

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4-27

TRF1410
MARCSTARTM RF
VHF/UHF RZ ASK REMOTE CONTROL RECEIVER
SLWS043-JUNE 1996

APPLICABLE REGULATIONS
Table 1. World-Wide Regulations
REGION
USA

FREQUENCY

REGULATION
Federal Communications Commission (FCC) Code of
Federal Regulations 47 (CFR 47) Parts 15.35,15.205,
15.209, 15.231, and 15.249 (see Note 4)

260-470 MHz (Part 15.35, 15.205, 15.209)
902-928 MHz (Part 15.249, see Note 4)

Germany

Femmeldetechnisches Zentralamt (FTZ), FTZ 17 TR2100

433.92 MHz

France

233.5-225 MHz (automotive only)

United Kingdom

Dept. of Trade and Industry (DTI), MPT 1340

418 MHz
433.92 MHz (automotive only)

Japan

Ministry of Posts and Telecommunications (MPT)

< 322 MHz

Canada

Dept. of Communications (DoC), Telecom Regulatory
Service, Radio Standard Specifications (RSS), RSS-210

260-470 MHz (RSS-21 0)
902-928 MHz

""C

Hong Kong

Post Office, Telecom Branch, Telecom Order 1989,
Sec 39, Cap. 106

314 MHz

Australia

Dept. of Transportation and Telecommunications (DTC),
and ECR60

303.825 MHz and 318 MHz

Israel

Ministry of Communications, Engineering & Licensing Div.

325 MHz

:IJ
C

c:
o
-I
""C

m
S

South Africa

403.916 MHz and 411.6 MHz

NOTE 4: Although the FCC Part 15.231 allows low-power unlicensed radios in the range of 260 MHz to 470 MHz, not all frequencies in this range
are desirable. This is due to emission restrictions applying to fundamentals and harmonics in various forbidden bands as defined in Parts
15.205 and 15.209. USA frequencies shown above conform to these additional restrictions and are commonly used in the USA. Under
Part 15.249, transmitters may continuously radiate 50000 JlV/m at 3 meters with simple modulation. Part 15.247 permits still higher
power, but must use true spread-spectrum modulation. See FCC CFR 47, Part 47, Part 15 for details.

~TEXAS

INSTRUMENTS
4-28

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MARCSTARTM RF
Application Report

Gerald Coles
Mixed Signal and RF New Product Development

SLWAOO5

"TEXAS
INSTRUMENTS

4-29

IMPORTANT NOTICE

Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by go.vernment requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage ("Critical Applications").
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer's applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.

4-30

Contents
Title

Page

Introduction .................................................................................... 4-33
External components .............................................................................. 4-33
Antenna issues ................................................................................... 4-33
Proximity to local noise sources ..................................................................... 4-33
Sensitivity/Out-of-band rejection .................................................................... 4-34
Improvements ................................................................................... 4-34

List of Illustrations
Figure

Title

Page

1. Average Sensitivity and Out-of-Band Rejection ....................................................... 4-34
2. TRF1400 Receiver Test Circuit ..................................... '.............................. 4-35
3. TRF1400 Receiver Test Circuit, Board Layout - Top Side ............................................. 4-35
4. TRF1400 Receiver Test Circuit, Board Layout - Bottom Side .......................................... 4-36
5. TRF1400 Receiver Test Circuit, Board Solder Mask - Top Side ......................................... 4-36
6. TRF1400 Receiver Test Circuit, Board Solder Mask - Bottom Side ...................................... 4-36
7. TRF1400 Receiver Test Circuit, Board Silk Screen .................................................... 4-37

List of Tables
Table

Title

Page

1. TRF1400 315-MHz Receiver Test Circuit Parts List ................................................... 4-38

4-31

4-32

Introduction
The TRF1400 receiver was designed as an almost completely integrated VHFIUHF receiver. However, the interface to each
working environment requires some attention to the external components and board layout to take full advantage of the device
abilities. In addition, system design issues such as antenna design and proximity oflocal noise sources (microprocessors, motors,
etc.) should be considered.

External components
As with any RF design, the successful integration of the device into a circuit board relies on the layout of the board and the quality
of the external components. Component tolerances and, where applicable, Q should be noted and followed. Included in this report
is a depiction of artwork for the production of an evaluation circuit board that can be employed to demonstrate TRF1400
performance at 315 MHz. A list of required external parts and tolerances is also provided. To obtain a complete set of Gerber
photoplotter files, contact any TI Field Sales Office.

Antenna issues
The coupling of the signal into the device is of paramount importance in order to realize the maximum system sensitivity. The
input network provided in the evaluation circuit is designed to match the receiver input to a nominal 50-Q load. Also included
in this network is a trap to reduce interference from lOS-MHz broadcast signals.
Optimally, the antenna that is used with this receiver should not only be matched to the input impedance, but should be of an
efficient design. A quarter wave monopole, for example, is a good choice. Loop antennas may also be used, but their performance
may vary widely given the available area and proximity to the circuit board. Also, loop antennas, even those shorter than one
wavelength, tend to exhibit distinct nulls in the antenna pattern. If possible, the antenna should be mounted away from the receiver
circuit board. Unfortunately, in many instances system requirements prohibit this and impose conflicting requirements of space,
ease of matching, and efficiency.
If requirements dictate that the antenna be included into a receiver module or other space-restricted areas, try to select an antenna
that is close to an ideal form, and then look to see how it might be integrated into the mechanical confines. If this is not possible
or not possible without folding the element over the circuit board, sweep the antenna with a network analyzer to determine the
effects of the proximity to the ground plane and other devices. Where ever possible, trim the antenna to achieve matching or to
approach a region on the Smith Chart® where a l-one-element match to 50 Q may be achieved. If possible, keep a folded antenna
at least 0.5 inch from the ground plane to avoid extreme sensitivity to mechanical vibration. As is often the case in nonideal
situations, design of an integrated antenna can be very empirical.

Proximity to local noise sources
Any receiver should be shielded from noise sources that may interfere with the reception of the intended signal, and the TRF1400
is no different. Care should be taken when integrating the device onto a board with microprocessors. Regulate and filter power
supply lines, paying particular attention to filter the supply lines again at the receiver power supply terminals to ensure clean lines.
Use both low-frequency and high-frequency filter sections. Due to their high harmonic content, digital signals produce broadband
noise of sufficient power to interfere with receiver operation both through the front end and by coupling to board traces. Where
possible, route digital lines around and away from the receiver and on mutilayer boards, consider running separate planes for these
signals.
Care should also be taken to suppress transient noise from relays or broadband noise from motors and other sources.
Smith Chart® is a registered trademark of the Analog Instruments Company.

4-33

Sensitivity/Out-of-band rejection
Out-of-band rejection (rejection of signals outside the intended passband of the receiver), depends to a large extent on the SAW
(surface acoustic wave) filter. In the layout depicted, the pad for the SAW filter has been carefully designed to maximize the
isolation between the input and output pins by including a ground "island" with low impedance paths (vias) between top and
bottom ground planes. Figure I shows average sensitivity and out-of-band rejection.

o
~

-20

I\~

~ ~~-

I~
-40
E

"
I

~
·iii

-60

CI.l

CJ)

-80

v\ IV

-100

-120

\
300

305

310

315

320

325

330

f - Frequency - MHz
NOTE A: RFM RF1211 SAW Filter

Figure 1. Average Sensitivity and Out-of-Band Rejection
Improvements
As a result of work accomplished with the use of the receiver test circuit (Figure 2) and board (Figure 3), several improvements
can be suggested.
Do not use plate-through holes on the input and output pins of the SAW filter. Do use plate-through holes for all the ground vias,
especially in the "island" area.
Figure 2 shows the schematic for the TRF1400 receiver test circuit. Components listed in Table 1 have been selected for 315 MHz.

4-34

RF Input

~
~
<
z

I-

SAW
Filter

u..
a:

..J

u::

,.......J\1\I\r---..

1
L1

R6
.---'\1\I\r-e-.

u..
a:

..J

I-

a:I-

BBOUT

C18

TRIG

C19

T-::-

i
u::

~
z

"
e

m
m

TRF1400

u..

D..
..J

(")

0
0

u::

0
0

"<
7

rn
u..
u..

~
6

C17
l-

9
R3

lC6

C20

':J;C2
-

T-::-

DOUT

-::Rl

.---'\1\I\r"'-!~

C10

C12 -::-

Cll

0
0

IX:

(,)

0
0

(/)

>
e

-::-

DVCC

-::-

C16
T

AVCC
C13T

C15

C14
T

Figure 2. TRF1400 Receiver Test Circuit

Figure 3. TRF1400 Receiver Test Circuit, Board Layout - Top Side

4-35

:.: .....
"w
••••••••
. :: :'.,
:...:.. t :~~
........

~ :.~

~==::~~o

~::

....: ... ~
...::.:
...... .. ..... " .
••••,

Figure 4. TRF1400 Receiver Test Circuit, Board Layout - Bottom Side

0
0

D
0
08

00
o 0

Figure 5. TRF1400 Receiver Test Circuit, Board Solder Mask - Top Side

o
o

00
00

Figure 6. TRF1400 Receiver Test Circuit, Board Solder Mask -

4-36

Bottom Side

~TEXAS

INSTRUMENTS

Figure 7. TRF1400 Receiver Test Circuit, Board Silk Screen

4-37

Table 1. TRF1400 31S-MHz Receiver Test Circuit Parts List
DESIGNATORS

SIZE I VALUE I @ FREQ.

MANUFACTURER

MANUFACTURER PIN

Capacitor

4 pF

Murata

GRM40COG040COSOV

Capacitor

22 pF

Murata

GRM40COG220J050BD

Capacitor

22 pF

Murata

GRM40COG220JOSOBD

Capacitor

100 pF

Murata

GRM40COG 101 JOSOBD

Capacitor

S pF

Murata

GRM40COGOSODOSOBD

Capacitor

1.S pF

Murata

GRM40COG1 R5COSOBD

Capacitor

100 pF

Murata

GRM40COG101JOSOBD

Capacitor

3pF

Murata

GRM40COG030COSOBD

Capacitor

18 pF

Murata

GRM40COG180JOSOBD

C10

Capacitor

0.047 ).IF

Murata

GRM40X7R473KOSO

C11

Capacitor

2200 pF

Murata

GRM40X7R222KOSOBD

C12

Capacitor

2200 pF

Murata

GRM40X7R222KOSOBD

C13

Capacitor

0.022 ).IF

Murata

GRM40X7R223KOSOBL

C14

Capacitor Tantalum t

Sprague

293D475X90S0D2T

Murata

G RM40COG221 JOSOBD

4.7 ).IF

C15

Capacitor

C16

Capacitor Tantalumt

C17

Capacitor

2200 pF

C18

Capacitor

C19

Capacitor

C20

Capacitor

220 pF, S%
4.7 ).IF

Sprague

293D475X90S0D2T

Murata

GRM40X7R222KOSOBD

0.022 ).IF

Murata

GRM40X7R223KOSOBL

2200 pF

Murata

GRM40X7R222K050BD

0.022 ).IF

Murata

GRM40X7R223K050BL

2-Pin Connector

2340-6111-TN

2-Pin Connector

2340-6111-TN

6-Pin Connector

2340-6111-TN

Header shunts

9299S2-10

S1-S2
F1

SAW filter

Inductor

L2
L3
L4

RF1211

RFM

RF1211

47nH

Coilcraft

0805HS470TMBC

Inductor

82 nH

Coilcraft

0805HS820TKBC

Inductor

120 nH

Coilcraft

0805HS 121TKBC

Inductor

39 nH

Coilcraft

0805HS390TMBC

Johnson

142-0701-201

NKK

G-12AP

RF SMA Connector

Resistor

1200il

Resistor

1200il

Resistor

1Mil

Resistor

130 Kil, 1%

Resistor

Oil

Resistor

1Kil

Resistor

100il

Resistor

1Kil

Resistor

680il

R10

Resistor

short

R11

Resistor

330il

4-38

DESCRIPTION

Switch

Table 2: TRF1400 31S-MHz Receiver Test Circuit Parts List
DESIGNATORS
Vcc1

DESCRIPTION

SIZE I VALUE I

FREQ.

Batttery Clip

B1X

Battery, Lithium

Receiver

MANUFACTURER
Keystone

3.3-V Coin Cell (2 ea.)
TRF1400

MANUFACTURER PIN
1061

Panasonic

CR2016

TRF1400

t Tantalum capacitors are rated at 6.3 Vdc minimum.

4-39

4-40

1IDI

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io__
n _______________
Telecommunications Circuits

Central Office Codecs

Transient Voltage Suppressors

lEI

RF for Telemetry and RKE

•

Wireless Communications Circuits
Processors for Analog Cellular
Voice-Band Audio Processors
RF for Personal Communications
Baseband Interface Circuits
Digital Signal Processors

Mechanical Data

5-1

»
::J
oQ)

o
CD

s::

"""t

5-2

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWSOOBC - SEPTEMBER 1994 - REVISED JUNE 1996

•

Single Chip for AMPSfTACS Data and SAT
Processing

•

Independent Watchdog Timer

•

3.3-V or 5-V Operation

•

RXfTX Automatic Mute Functions

•

Simple Serial Interface

•

Arbitration Processing

•

User-Configurable Interrupt Structure

20 Programmable Expansion 1/0 Ports

•

TX and RX Data Buffers

•

44-Pin Mini-QFP FR Package

•

Programmable Timer

description
The TCM8002 provides the data transceiving, data processing, and SAT (supervisory audio tone) functions for
the AMPS (advanced mobile phone service) and TACS (total access communications system) cellular
telephone standards. A highly integrated device, the TCM8002 includes a number of additional functions that
are helpful in the implementation of the typical cellular telephone. These extra functions include a watchdog
timer, which is normally external to the telephone microcontroller, and two 8-bit- and one 4-bit-wide
user-programmable general-purpose input/output ports. These can be used to provide port expansion for the
microcontroller. An 8-bit counter/timer for user-defined purposes is also included.
To facilitate the application of the TCM8002 and to minimize the number of connections, a single serial interface
to the microcontroller is used for controlling, receiving, and transmitting data. There is also a dedicated interface,
including a compatible clock signal, to the companion TCM8010 audio processor that performs most of the
audio processing required in a cellular telephone. Additional outputs are also provided for interfacing to other
audio processors.
The TCM8002 is built using a low-power CMOS process and operates with a 5-V or 3.3-V power supply. When
used in conjunction with the TCM8010, a unique and very compact low-power solution for AMPSITACS
baseband processing in 5-V and 3-V systems is realized.

44434241 40393837363534

HDATAlP04(O)
CLKOUT/P04(1 )
HCS/P04(2)
HCLKlP04(3)
SATOUT
TXOUT
SATIN
RXIN
PI01(O)
PI01(1)
PI01(2)

33
32
31
30
29
28
27
26
25
24
23

~TEXAS

CS
RCCBUSY/P04(4)
WDOUT
RFEN
PI03(3)
PI03(2)
PI03(1)
PI03(O)
PI02(7)
PI02(6)
PI02(5)

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-3

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWSOOBC - SEPTEMBER 1994 - REVISED JUNE 1996

functional block diagram
CLKOUT/P04(1)

XTAL 1

RESET

XTAL2

t40

From Microprocessor
Interface

----"1--__

---'3'--'1 WDOUT

HCS/P04(2)
TCM8010
Interface

HCLKlP04(3)
HDATAlP04(0)
SATOUT
SATIN

RXIN

RAEN/P04(6)

______+-+-__________~-+~4-__~3~2RCCBUSYI

2!43~1------------L~~~J----II""~-=--1

P04(4)
DATAIN
DATAOUT

RFEN~30~~----------------~

-+-+-+_____3~7

L -_ _ _ _ _ _

TAEN/P04(7) ..:.,.44.:.........__- - - - - - - - - 1
TXOUT-6~__- - - - - - - - - I

INTRPT

...---====-----===~
1-____________---.:3=.8 TMZEROI
L-._ _- - I

9-16
PI01 (0-7)

18-25
PI02(0-7)

26-29
PI03(0-3)

()=bit count

~TEXAS

INSTRUMENTS
5-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

P04(5)

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLwsooac - SEPTEMBER 1994 - REVISED JUNE 1996

Terminal Functionst
TERMINAL*
NAME

NO.

DESCRIPTION

CLKOUT/P04(1 )

Clock output/programmable output #4, bit 1. A 2.56-MHz clock signal is output on this terminal or the
device can be set so that it is bit 1 of P04.

Chip select (active low). This is the chip select input from the microcontroller.

DATAIN

Data input. Serial data from the microcontroller is input on this terminal.

DATAOUT

Data output. This is the serial data output to the microcontroller (3-state).

DCLK

Data clock. This is the serial microcontroller interface clock input.

HCLKlP04(3)

TCM8010 interface clock/programmable output #4, bit 3. A clock signal to the TCM8010 or bit 3 of
programmable output 4 is output on this terminal.

HDATNP04(0)

I/O

TCM8010 interface data line/programmable output #4, bit O. This terminal is used for data to and from
the TCM801 0, or is bit 3 of programmable output 4.

HCS/P04(2)

TCM8010 interface chip select output (active-Iow)/programmable output #4, bit 2. This terminal
selects the TCM8010, or is bit 2 of programmable output 4.

Interrupt output. This is the interrupt line to the microprocessor.

PI01(0-7)

INTRPT

9-16

I/O

Programmable I/O port #1, bits 0 - 7. This 8-bit port can be configured as either inputs or outputs
(microcontroller port expansion).

PI02(0-7)

18-25

I/O

Programmable I/O port #2, bits 0 - 7. This 8-bit port can be configured as either inputs or outputs
(microcontroller port expansion).

PI03(0-3)

26-29

I/O

Programmable I/O port #3, bits 0 - 3. This 4-bit port can be configured as either inputs or outputs
(microcontroller port expansion).

RAEN/P04(6)

Receive audio enable output/programmable output #4, bit 6. This terminal is used to enable the
receive audio section of the phone, or is bit 6 of programmable output 4 (open drain).

RCCBUSY/P04(4)

RECC busy status/programmable output #4, bit 4. This terminal outputs the status result of the
majority vote of the three most recent busy/idle bits, or is bit 4 of programmable output 4.

RESET

Reset input, active low. A low applied to this terminal resets the TCM8002 and loads the default values
listed in the write map.

RFEN

RF enable. This terminal is used to enable the transmitter section of the phone (open drain).

RXIN

Baseband Manchester data input. Manchester-encoded data from control or voice channel is input
on this terminal.

SATIN

SAT input. Square-wave SAT data from the TCM801 0 audio processor is input on this terminal.

SATOUT

Regenerated SAT output. Regenerated SAT data is output to the TCM801 0 audio processor on this
terminal.

TAEN/P04(7)

Transmit audio enable/programmable output #4, bit 7. The logic level on this terminal changes state
during RVC message or ST transmission, or is bit 7 of programmable output 4 (open drain).

TMZERO/P04(5)

Timer zero/programmable output #4, bit 5. The logic level on this terminal changes state when the
counter/timer passes or reaches zero, or is bit 5 of programmable output 4.

TXOUT

Transmit data output. Encoded transmit data is output to the TMC8010 audio processor on this
terminal.
Positive supply voltage. Input is 3.3-V or 5-V.

VDD

VSS

WDOUT

Watchdog timer output. A logic-low pulse is output on this terminal when the watchdog timer times
out.

XTAl1

Crystal terminal 1/external clock source input. An external crystal is connected to this terminal for the
internal clock oscillator. An external clock signal can also be input on this terminal.

XTAL2

Crystal terminal 2. An external crystal is connected to this terminal for the internal clock oscillator.

Ground supply voltage.

t All inputs feature Schmitt triggers. All of the PIO terminals also feature optional
:I: ( ) =bit count when in the terminal column

10-IlA pullups.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-5

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

detailed description
Data communication between the mobile station and the land station in AMPS and TACS systems is achieved
over forward and reverse control channels when a call is not in progress, or in short bursts over the forward and
reverse voice channels when a call is in progress. The TCM8002 device has a receive path that recovers data
from the FOCC (forward control-channel) and FVC (forward voice-channel) formats. The transmit path encodes
and formats data for the RECC (reverse control channel) and RVC (reverse voice channel).
For voice-channel communications, the received SAT is detected and regenerated for transmission.
Communication with the microcontroller/microprocessor in the telephone is through a serial interface. The
TCM8002 also provides interrupts to alert the processor to the occurrence of specific events. The receiver is
made up of the Data Recovery, Majority Voting, BCH (Bose-Chaudhuri-Hocquenghem) Decoder, RX Buffer,
Arbitration Logic, and RX Control blocks. The SAT Detector/Regenerator is used during FVC reception and RVC
transmission.
The transmit path consists of the TX Buffer and TX Encoder blocks. A serial microprocessor interface and the
interrupt logic are also provided. Four ancillary functions are included:
•

TCM8010 interface

•

Watchdog Timer

•

Counter/Timer

•

twenty programmable digital bidirectional 110 lines (eight of the output terminals can be reconfigured as
processor output ports)

clock divider
The clock signal for the TCM8002 is supplied in two ways:
•
•

A crystal can be connected to XTAL 1 and XTAL2.
A clock Signal from another source can be connected to XTAL 1.

When a crystal is used, a resistor (typical value 1 MQ) should be connected between XTAL 1 and XTAL2 to
provide a bias for the oscillator. The crystal frequency must be 2.56 MHz, 5.12 MHz, 7.68 MHz, or 10.24 MHz.
If an external clock signal is connected, it must be at one of these crystal frequencies or one of two additional
frequencies: 15.36 MHz or 20.48 MHz .
.The clock frequency defaults to 2.56 MHz when the TCM8002 is reset. The clock-divider circuit provides a
2.56-MHz clock for internal use and must be configured according to the selected crystal or external clock
frequency. Control word 2, bits 5 and 6, and control word 4, bit 1, are used to configure the clock divider. The
output from the clock-divider circuit is provided at CLKOUT and is always 2.56 MHz. This can be used to clock
the TCM801 0 advanced audio processor.
The bit rate of the transmitted Manchester-encoded data, the signaling-tone frequency, and the accuracy of the
SAT measurement are all determined by the crystal or external clock. The AMPS and TACS system
requirements both specify a maximum transmitted bit frequency error of ± 100 ppm; therefore, over the
operating temperature range of the phone, the crystal or clock frequency error must be no more than ± 100 ppm.

~TEXAS

INSTRUMENTS
5-6

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

absolute maximum ratings over operating temperature ranget
Supply voltage range, Voo, Vss (see Note 1) ......................................... -0.5 V to 6 V
Input voltage range, VI ...................................................... -0.5 V to Voo + 0.5 V
Output voltage range (includes open-drain outputs), Va ......................... -0.5 V to Voo + 0.5 V
Operating ambient temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage Values are with respect to GND.

recommended operating conditions

IVDD = 3 V

Supply voltage, VDD

I VDD =5 V

MIN

NOM

MAX

2.7

3.3

3.6

4.5

5.5

UNIT
V

Input voltage, VI

VDD

Output voltage, Vo

VDD

High-level input voltage, VIH

0.7 VDD

IVDD = 3 V
IVDD = 5 V

Low-level input voltage, VIL

0.3 VDD

-40

Operating ambient temperature range, TA

0.2 VDD
25

electrical characteristics over recommended operating conditions, Voo = 3.3 V (unless otherwise
noted)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH =-0.9 mA
10L = 1.6 mA

MIN

TYP

MAX

VOL

Low-level output voltage

0.5

VIT+

Positive-going input threshold voltage

VIT-

Negative-going input threshold voltage

0.3 VDD

Vhys

Hysteresis (V IT + - VIT-)

0.1 VDD

10Z

High-impedance output current

VI = VDD or VSS

IlL

Low-level input current

VI = VSS

IIH

High-level input current

VI =VDD

Pullup output current

VI =VSS

IDD

Supply current with 2.56-MHz crystal

Low-power mode

1.1

Low-power mode, SAT off

0.9

0.7 VDD

Default mode

V
V
V

0.3 VDD
±10
-1
1

-2.12

UNIT
V

VDD-0.55

-5.32

-10.18

IlA
IlA
IlA
IlA

1.4
mA

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-7

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

electrical characteristics over recommended operating conditions, Voo
noted)
PARAMETER

TEST CONDITIONS

=5 V (unless otherwise

MIN

VOH

High-level output voltage

10H =-2 mA

VOL

Low-level output voltage

IOL=2 mA

VIT+

Positive-going input threshold voltage

VIT-

Negative-going input threshold voltage

0.2 VDD

Vhys

Hysteresis (VIT + - VIT -)

0.1 VDD

10Z

High-impedance output current

VI = VDD or VSS

IlL

Low-level input current

IIH

High-level input current

Pullup output current

VI = VSS

IDD

TYP

MAX

0.5
0.7 VDD

Supply current with 2.56-MHz crystal

UNIT
V

VDD-0.8

V
V
V

0.3 VDD

±10

JlA

VI =VSS

-1

JlA

VI =VDD

JlA

-24.47

JlA

-7.2

-14.84

Default mode

3.6

Low-power mode

2.8

Low-power mode, SAT off

2.5

timing requirements over recommended ranges of operating conditions (see Figure 1)
MIN

MAX

UNIT
ns

tsu1

Setup time, CS low before DCLKi

300

th1

Hold time, CS low after DCLKt

300

tsu2

Setup time, DATAIN before DCLKi

300

th2

Hold time, DATAIN after DCLKi

300

DCLK clock period (nominal)

Jls

tc(er)

DCLK clock period, Read start bit - Event Register

Jls

tc(or)

DCLK clock period, Read start bit - Other Register

Jls

100

Period that CS must be high between read or write operations

~TEXAS

INSTRUMENTS
5-8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
Figure 1 shows the timing for processor read and write operations. DATAOUT has a 3-state driver and normally
presents the high-impedance state as shown in Figure 1. This allows DATAIN and DATAOUT be be tied together to
a bidirectional microprocessor pin.

cSI~
1

______________~1
I

~ 14- tsu1
1 1

th1 ~

DCLK
Write

Write Address

---~

1 4 - - - - - Write Data - - - - - - - .

DCLK

Read

DATAI~ 0

Bit

~t~(

I
~14

I .......-r---------4;jl-j- - - - - - - - .1
I

Read Address

DATAOUT

~
I
~
Q11

Q10

~~
tl

(from event regIster)
tc(er)

DATAOUT---------------~

(from any other register)
tc(or)

I
I

Read Data

--i.--.!I...
!.. _ _ __

Read Data - - - - - - - .

Read Start Bit ~

Figure 1. Microprocessor-Interface Timing

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-9

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
receive path
The following paragraphs detail the TCM8002 receive path, which includes the function blocks as given in the
functional block diagram.

Data Recovery
The input to the Data Recovery block is RXIN and the signal applied to this terminal should be a digital version
of the output from the FM demodulator/discriminator in the phone. Data recovery is performed by a digital
phase-lock circuit with its center frequency at the designated bit rate (Le., 10 kbps for AMPS and 8 kbps for
TACS).
The dotting preamble produces a square wave with a frequency one-half of the bit rate and transitions at the
center of each bit period. This is used by the data recovery circuit to acquire bit synchronization with the
acquisition coefficient (DATAREC coef 1). After synchronization is achieved, the lock coefficient is used
(DATAREC coef 2) to allow phase adjustment during subsequent occurrences of dotting.

RX Control
The receiver control circuit detects the dotting sequence and the frame synchronization code (11100010010).
Once frame synchonization has been achieved, the received data stream is separated. The FOCe stream is
separated into busy/idle bits, bits of word A, and bits of word B. Recovered FVC bits are separated into bits of
the received word, dotting bits, and word sync bits. For both FOCC and FVC, a word repeat count is also
maintained. For the FOCC, a count is maintained of the number of consecutive sync words matched and the
number not matched. Two matches are required to acquire and confirm frame synchronizatidn. Five
consecutive mismatches indicate loss-of-frame synchronization.
During FOCC reception, the busy/idle bits are fed directly to the Arbitration Logic block. A majority vote of the
most recent three busy/idle bits is made available at RCCBUSY and at status word 1, bit 4.
During FVe message reception, the receive audio enable output (RAEN) changes state. The output changes
on frame synchronization and returns to the initial state 928 bit periods later. Status word 2, bit 1 is set for this
period.
The receive audio circuit in a connected TCM8010 can be automatically controlled through the TCM8010
interface (see control word 2). During FVC wide band data reception, a copy of the previous TCM801 0 control
word 1 is resent with bits 0 and 1 set to 0, muting the received audio path. After the end of data reception, the
original TCM801 0 control word 1 is resent.

Majority Voting
The Majority Voting function performs a bit-wise majority vote on the repeated FOCC or FVC words. All five
repeats of the (A or B) FOCC word are used and up to 11 repeats of the FVC word are used. The result is to
recognize each of the 40 bits as a logic 0 or logic 1.

BCH Decoder
The error-correction circuit corrects the received BCH code. This is a 40-bit code word consisting of 28 data
bits and 12 parity bits. The circuit is able to correct errors in the received majority-voted 40-bit word from the
12 parity bits. Up to two errors in either the data or parity can be detected. The corrected 28 data bits together
with 4 correction status bits may be read from the RX data word 0 to RX data word 3 locations. In low-power
mode, this block is turned on only when there is data to be corrected and is selected by control word 4, bit o.

~TEXAS

INSTRUMENTS
5-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
RX Buffer
The 28-bit output from the BCH Decoder is fed into the RX Buffer, which can then be read by the microprocessor.
Every time new data is available, an interrupt is generated and a status bit is set. The interrupt may be masked.
The data is read in four 8-bit bytes, and when the last byte (least significant bit) is read, the status bit is reset.

Arbitration Logic
During FOCC reception, the arbitration logic uses the busy/idle bits to determine the status of the RECC. The
arbitration logic monitors the busy/idle status of the FaCe at the start of each RECC transmission. A collision
is detected when the status becomes busy within the first 56 bit periods or when it remains idle after 104 bit
periods. When a collision is detected, the arbitration-failure flag in the event register is set and an interrupt can
be generated (depending on interrupt control word 1). RFEN changes state and the transmission of data to
TXOUT is also aborted if bit 5 of control word 1 is set. To reset the state of RFEN and allow the transmission
of data to TXOUT after an arbitration failure, it is necessary to reset the arbitration-fail latch by writing to address
26 (reset arbitration).

SAT Detector/Regenerator
The SAT detection and regeneration circuit takes the square wave at SATIN as its input. The detection and
regeneration functions are performed by a digital phase-locked loop. The regenerated SAT is output at SATOUT.
SAT determination is performed using this circuit and the result is updated every 0.2 seconds and then output
to the microcontroller interface. The SAT color code (SCC) is determined from the frequency measurement and
the result is available from status word 1, bit 6 and bit 7. If the SAT output frequency is outside of the SAT
frequency range, the SAT is considered invalid and zeros are loaded into word 1, bit 6 and bit 7. In low-power
mode (selected by control word 4, bit 0), this functional block can be turned off by control word 1, bit 7.

transmit path
The TCM8002 transmit path includes the following function blocks as given in the functional block diagram:

TX Buffer
The TX Buffer is a 36-bit buffer that is written to by the processor in five write operations. After the fifth write (the
least significant bit), the TX buffer-available status bit is reset. The status bit is set when the transmit data is read
by the TX Encoder.

TX Encoder
The TX Encoder reads the contents of the TX Buffer and then performs BCH encoding, Manchester encoding,
and RECC or RVC frame formatting. The result is output at TXOUT. The encoding and transmit cycle is initiated
by one of the following conditions:
o

With the TX Encoder function not active, transmission is initiated by a processor write to the
Commence-TX address.

•

With data to be read from the TX Buffer and the TX Encoder active, transmission of the next frame
follows directly after completion of an active frame and the seizure precursor is omitted.

Under processor control, the TX Encoder generates a signaling tone (ST), which is 10kHz for AMPS and
8 kHz for TACS.
During RVe message transmission or ST transmission, the transmit audio enable output (TAEN) changes state.
The transmit audio circuit in a connected TCM801 0 can be automatically controlled via the TCM801 0 interface
(see control word 2). During RVC wide-band data transmission, a copy of the previous TCM801 0 control word 1
is resent with bit 5 cleared to 0 and bit 6 set to 1. This mutes the transmit audio path and enables the transmit
data path. At the end of data reception, the original TCM801 0 control word 1 is resent.

~TEXAS

INSTRUMENTS'
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-11

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWSOOBC - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION

miscellaneous functions
The following paragraphs detail TCM8010 miscellaneous functions shown in the functional block diagram.
TCM8010 Interface
The TCM801 0 Interface provides a serial communication channel to the TCM801 0 advanced audio processor
using terminals HCS, HCLK, and HDATA. .
Write operation:

The TCM801 0 address bits and data bits are written in two write operations to the TCM801 0
interface with word 1 first and then word O. On completion of the write to the TCM8010
interface word 0, the data is clocked out to the TCM801 0 chip overthe 3-wire serial interface.
The TCM801 0 interface status bit (status word 2, bit 0) indicates when the interface is active.

Read operation:

The TCM801 0 address bits and HCLK speed are written to the TCM801 0 interface word O.
This initiates an AID conversion and results in retrieval using the 3-bit serial interface. The
status bit (status word 2, bit 0) is set for the duration of the interaction. On completion, the
8-bit result can be read from the TCM801 0 result location. The HCLK speed is detailed in
Table 1.
Table 1. TCM8010 HCLK Speed Control Bits (Interface Word 0)
7

TCM8010 Read
Address

HCLKSPEED
CONTROL BITS

HCLKSPEED
IN kHz

80
160

CounterlTimer
The Countermmer is an 8-bit down counter that counts at the bit rate (Le., 10kHz for AMPS, 8 kHz for TACS).
This circuit can be configured to repeatedly count down from the programmed coefficient or to count down once
only and stop at zero. A countdown is initiated by a write to the coefficient location. TMZERO can be used to
detect when the counter passes/reaches zero. When the counter/timer is configured to cycle continuously,
TMZERO changes state for one bit period. An interrupt can also be generated.
Watchdog Timer
The watchdog timer provides a timeout of a minimum of 1 second to a maximum of 1.2 seconds. The timer is
initially started by the first write to address 21 (start/restart watchdog). After this first write, timeout is prevented
by writing to the watchdog timer address at intervals not exceeding 1 second.
When timeout occurs, WDOUT pulses low for 100 Jls (AMPS operation) or 125 Jls (TACS operation) and RFEN
changes state, but the data in the control registers remain unchanged. It is then necessary to reset the TCM8002
to return the RFEN output to its original state.
WDOUT is also held low for the duration of a low input at RESET. WDOUT remains high in its normal (high) state
during a software reset (write to location reset).

~TEXAS

INSTRUMENTS
5-12

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Programmable 1/0 Extension
The Programmable I/O Extension provides processor port expansion. PI01 (0-7), PI02(O-7), and PI03(O-3)
can be configured as either inputs or outputs. For those pins configured as outputs, the output values are set
through the microprocessor interface. The values at all of the ports can be read through the microprocessor
interface.
Eight output terminals can also be configured as programmable outputs instead of the named functions. The
programmable outputs are the terminals with the IP04( . .. ) in their names. All inputs feature Schmitt triggers
and all the PIO terminals feature optional 10-!lA pullups.

RESET
A low logic level at RESET performs a chip reset. The default values listed in the write address map are loaded.

microcontroller interface
The TCM8002 microcontroller interface is descriped in subsequent paragraphs.

write
For a write operation, CS is taken low and data on DATAIN is clocked into the TCM8002 on each rising edge
of DCLK. It is important that CS is taken low when DCLK is low for the correct operation of the read/write
selection logic in the microprocessor interface. The input sequence is start bit (logic 1), 7-bit address, then 8 bits
of data. The operation is completed by CS returning to a high logic level with DCLK low. If DCLK is not low, an
extra clock pulse is required. The address and data to be written to control the TCM8002 and to transmit
Manchester-encoded signals are detailed in the write address map (Table 2). Eight bits of data are always
written to the interface and data is right-justified. When writing to addresses 20 - 26, it is necessary to supply
clock cycles to write dummy data to the microprocessor interface to start the actions. The state of DATAIN during
these write-data clock cycles is not important.

read
For a read operation, the start bit is cleared to O. Following the seven address bits, DATAOUT is enabled and
the output data is updated on each falling edge of DCLK. DCLK must be low when CS is taken low for correct
operation of the read/write selection logic in the microprocessor interface. The operation is completed by CS
returning to a high logic level with DCLK low. When DCLK is not low, an extra clock pulse is required.
When reading from the event register only, DCLK must be changed from its nominal period of 1 !ls to a period
of 2 !ls so that the start bit is 2 !ls long. This can be accomplished by skipping a clock pulse while the start bit
is low. Reading from all other registers requires no adjustment to the DCLK nominal period of 1 !ls.
DATAOUT returns to the high-impedance state when CS returns high. During the read operation, eight bits of
data are output on DATAOUT in the order of bit 7 to bit O. During a read from the event register, however,
12 bits of data appear in the order of bit 11 to bit 0; i.e., 12 DCLK cycles should be made before CS returns high.
The data is right-justified.

Interrupt Circuit
Interrupt-control words 1 and 2 are used to program which events cause an interrupt. When any of the events
occur, the associated bit of the event register is set. INTRPT is set whenever an enabled interrupt occurs.
When the event register is read, its contents are first transferred to a buffer and the register is cleared. The bits
are then read out in series. At the end of the read sequence, INTRPT is reset. When an interrupt event occurs
during the read operation, INTRPT remains low for approximately 1 !ls and then returns high.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-13

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION

write address map
Table 2 shows the write address map. Table 3 through Table 12 explain control words listed in Table 2; the other
addresses are described in subsequent paragraphs.

Table 2. Write Address Map
ADDRESS
(7 BITS) HEX

FUNCTION

NAME

DEFAULT
VALUE

Control Word 1

Operational control word

Control Word 2

Operational control word

Control Word 3

Signal polarity selection

Interrupt Control Word 1

Interrupt enables

Interrupt Control Word 2

Interrupt enables

PI01 Control Word

PI01 direction selection

PI01 Output Word

PI01 values for outputs

PI02 Control Word

PI02 direction selection

PI02 Output Word

PI02 values for outputs

PI03 Control Word

PI03 direction selection

PI03 Output Word

PI03 values for outputs

P04 Control Word

P04 configuration selection

P04 Output Word

P04 values for selected terminals

CommenceTX

Commence TX command

Start Watchdog

StarVrestart watchdog

AbortTX

Abort TX command

Clear TX Buffer

Clear TX buffer command

Restart Frame Sync

Restarted frame-sync command

Reset

Reset chip command

Reset Arbitration

Reset arbitration circuit

TX Data Word 0

TX data bits 35-32

TX Data Word 1

TX data bits 31-24

TX Data Word 2

TX data bits 23 -16

TX Data Word 3

TX data bits 15-8

TX Data Word 4

TX data bits 7 -0 (LSBs)

TCM8010 Interface Word 0

Read/write bit, address and 09 - 06

TCM8010 Interface Word 1

TCM8010 data bits 05 - DO

Countermmer Coef

Coef and start command

SAT Coef

SAT circuit-time constant coefficient

DATAREC Coef 1

Acquisition coefficient

DATAREC Coef 2

Lock coefficient

Control Word 4

Operational control word

Mismatch

Frame mismatch coefficient

FOCC Dotting

Detect coefficient

FVC Dotting

Detect coefficient

"TEXAS
INSTRUMENTS
5-14

NO. OF
SIGNIFICANT
BITS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWSOOBC - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 3. Address 00 - Control Word 1
BIT
0

FUNCTION (WHEN BIT IS SET)
Enable SATOUT output

Signalling tone (ST) select (to TXOUT)

Voice-channel operation (RVC) (not control channel RECC)

Digital color code first bit (DCC) (see Table 4)

Digital color code second bit (DCC) (see Table 4)

Enable RFEN and TOUT; disable on detection of an arbitration fail

Timer/counter continuously cycles

Disable SAT detector and regenerator (only in low-power mode)

The translation between the 2-bit DCC code and the transmitted data is shown in Table 4.

Table 4. Two-Bit DCC Code Translation
CONTROL WORD 1

TRANSMITTED CODE

BIT4

BIT3

0000000

0011111

1100011

1111100

Table 5. Address 01 - Control Word 2
BIT

FUNCTION (WHEN BIT IS SET)

AMPS (not TACS)

FOCC B word (not A word)

Enable automatic control of TCM801 0 receive audio circuit through the TCM801 0 interface

Enable automatic control of TCM8010 transmit audio circuit through the TCM8010 interface

Disable all 10-11 A pullups of PI01, PI02, and PI03

Clock selection (along with bit 1 of control word 4)

TCM8010 interface write-speed selection

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-15

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 6. Clock-Selection Bits
CONTROL
WORD 4

CONTROL WORD 2

SELECTED CLOCK
FREQUENCY

TCM8010
INTERFACE CLOCK

2.56 MHz

320 kHz

5.12 MHz

320 kHz

7.68 MHz

320 kHz

10.24 MHz

320 kHz

2.56 MHz

1.28 MHz

BIT 1

BIT7

BIT6

BITS

5.12 MHz

1.28 MHz

7.68 MHz

1.28 MHz
1.28 MHz

10.24 MHz

Not used

15.36 MHz

320 kHz

20.48 MHz

320 kHz

Not used

15.36 MHz

1.28 MHz

20.48 MHz

1.28 MHz

Table 7. Address 02 - Control Word 3 Functions
BIT

FUNCTION (WHEN BIT IS SET)

Invert polarity of RXIN

Invert polarity of TXOUT

Invert polarity of RFENt

Invert polarity of INTRPT, active low

RAEN active lowt

TAEN active lowt

TMZERO active low

RCCBUSY active low

t RFEN, RAEN, and TAEN have open-drain output drivers. These
drivers have active pulldowns and require provision of external
pullups.

•
TEXAS
INSTRUMENTS
5-16

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 8. Address 03 - Interrupt-Control Word 1
INTERRUPT ENABLED
(WHEN BIT IS SET)

BIT
0

RX data available

TX buffer available

Arbitration failure

TX sequence completed

Change of RECC bus/idle status

Counter/timer reaches zero state

SAT measurement decision changes

Table 9. Address 04 - Interrupt-Control Word 2
INTERRUPT ENABLED
(WHEN BIT IS SET)

BIT

TCM8010 interface activity completed

0
1

FVC dotting detected

FVC frame sync achieved

Change of FOCC frame-sync status

SAT measurement update (every 0.2 seconds)

Table 10. Address 05 - PI01 Control Word
BIT (0-7)

CORRESPONDING TERMINAL FUNCTION
(0-7)

Input

Output

The eight terminals of the port are configured as inputs by default. The terminals have programmable 10-JlA
pull ups that can be disabled using bit 4 of control word 2.
address 06 - PI01 output word
This sets the state of the PI01 terminals when configured as outputs.
address 07 - PI02 control word
This selects whether the individual port 2 terminals are configured as inputs or outputs.
address 08 - PI02 output word
This sets the state of the PI02 terminals when configured as outputs.
address 09 - PI03 control word
This selects whether the individual port 3 terminals are configured as inputs or outputs.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-17

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
address OA - PI03 output word
This sets the state of the PI03 terminals when configured as outputs.
address 08 - P04 control word
The eight output terminals HDATA, CLKOUT, HCS, HCLK, RCCBUSY, TMZERO, RAEN, and TAEN can be
independently reconfigured as outputs. Control bits set the terminals as programmable outputs.
address OC - P04 output word
This sets the value of the P04 terminals configured as outputs. RAEN and TAEN remain open-drain outputs
when configured as programmable outputs.
address 20 - commence TX
Writing to address 20 transfers data from the TX Buffer to the TX Encoder and starts the encoding and
transmission of the data.
address 21 - start watchdog
Writing to address 21 starts one cycle of the Watchdog Timer.
address 22 - abort TX
Writing to address 22 immediately stops a transmission sequence that is in progress.
address 23 - clear TX buffer
Writing to address 23 clears the contents of the TX Buffer. This command can be used to stop the automatic
transmission of a second word written to the TX Buffer when the TX Encoder is active. This command does not
stop the complete transmission of the first word.
address 24 - restart frame sync
Writing to address 24 resets the data-recovery circuit, which then uses the acquisition coefficient initially to
achieve bit synchronization to the received data. It can be used when the phone switches to a new FOCC
(forward control channel) to reduce the time taken to acquire bit synchronization. The data-recovery circuit does
not have to wait until it has detected loss of bit synchronization to change from using the lock coefficient to using
the acquisition coefficient.
address 25 - reset
Writing to address 25 performs a device reset. Its function is identical to that of RESET except that it does not
affect WDOUT. The default values listed in the write address map are then loaded.
address 26 - reset arbitration
Writing to address 26 resets the arbitration-failure circuit.
addresses 40 to 44 - TX data words 0 to 4
The data to be transmitted is written to these five addresses, thereby loading the TX Buffer.

~TEXAS

INSTRUMENTS
5-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
address 48 - TCM801 0 interface word 0
Table 11. Interface Word 0
BIT
7

FUNCTION
Value = 0 for TCM801 0 read operation, 1 for write operation

6-4

TCM8010 address

3-0

TCM8010 write data bits 09-06

Writing to the TCM801 0 interface word 0 initiates a TCM801 0 interaction. The result of any read operation (Le.,
an AOC conversion result) can be accessed by a subsequent read from the TCM801 0 result location.

address 49 - TCM801 0 interface word 1
These are the TCM801 0 data bits 05 to DO.

address 40 - counter/timer coefficient
Writing to address 40 sets the count length and starts a down count from the value written.

address 50 - SAT coef
This coefficient controls the SAT detector digital phase-locked loop time constant.

address 51 - OATAREC coef 1
This controls the data-recovery circuit acquisition performance before bit synchronization is achieved.

address 52 - OATAREC coef 2
This controls the data-recovery circuit lock performance after bit synchronization is achieved.

address 53 - control word 4
Table 12. Control Word 4
BIT

FUNCTION (WHEN BIT IS SET)

Low-power mode select

Clock selection (with control word 2)

With low-power mode selected, the BCH decoder circuit is turned on only when there is data to be
error-corrected. The SAT detector and regenerator can be turned off when not required (control word 1).
I

address 57 - mismatch
This relates to the number of successive frames that are not recognized during data recovery before bit
synchronization is searched again.

address 59 - FOCC dotting
This is a coefficient forthe data-recovery circuit and is related to how much of the dotting preamble of the forward
control channel data is required before it is accepted that bit synchronization has been achieved.

address SA - FVC dotting
This is a coefficient forthe data-recovery circuit and is related to how much of the dotting preamble of the forward
voice channel data is required before it is accepted that bit synchronization has been achieved .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-19

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION

read address map
Table 13 shows the read address map. This is followed by an explanation of all the bits contained in this address
map including detailed information in Table 14 through Table 19.

Table 13. Read Address Map
ADDRESS
(7 BITS) HEX

FUNCTION

NAME

00.

Status Word 1

Status word 1

Status Word 2

Status word 2

Event Register

Event register

PI01 Status Word

State of PI01 terminals

PI02 Status Word

State of PI02 terminals

PI03 Status Word

State of PI03 terminals

RX Data Word 0

RX bits 27-20

RX Data Word 1

RX bits 19-12

RX Data Word 2

RX bits 11-4

RX Data Word 3 (bits 7-4)

RX bits 3-0 and error-correction status

Uncorrected RX Data Word 0

Uncorrected received data bits 39-32

Uncorrected RX Data Word 1

Uncorrected received data bits 31-24

Uncorrected RX Data Word 2

Uncorrected received data bits 23-16

Uncorrected RX Data Word 3

Uncorrected received data bits 15-8

Uncorrected RX Data Word 4

Uncorrected received data bits 7-0

RX Repeat Count

Number of word repeats used for the majority voting

TCM8010 Result

8-bit result of TCM801 0 ND conversion

SAT (supervisory audio tone)

SAT frequency measurement

Table 14. Address 00 - Status Word 1
BIT

STATUS (WHEN BIT IS SET)

RX data available

TX buffer available

Most recent TX aborted or arbitration failure

TX encoder active

RECC busy (not idle)

Counter/timer at zero state

SAT frequency band as detailed in Table 13

•
TEXAS
INSTRUMENTS
5-20

NO. OF
SIGNIFICANT
BITS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWSOOBC - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 15. SAT Frequency Band
STATUS WORD 1

MEASURED FREQUENCY

BIT7

BIT6

5957 Hz < f < 5987 Hz

5987 Hz < f < 6017 Hz

6017 Hz < f < 6047 Hz

6047 Hz < f < 5957 Hzt

t This indicates an invalid SAT.

Table 16. Address 01 - Status Word 2
BIT

STATUS (WHEN BIT IS SET)
TCM8010 interface active

0
1

FVC message being received

In FOCC frame sync

Table 17. Address 02 - Event Register
BIT

OCCURRENCES SINCE PREVIOUS READ OF THIS WORD
(WHEN BIT IS SET)

RX data available

TX buffer available

Arbitration failure

TX sequence completed

Change of FOCC busy/idle status

Counter/timer reaches zero state

SAT result changed value

TCM8010 interface activity completed

FVC dotting detected

FVC frame sync achieved

Change of FOCC frame-sync status

SAT measurement update (every 0.2 seconds)

These flags indicate which event(s) have occurred since the previous read, regardless of their associated
interrupt control bits.

addresses 04, OS, and 06 - PI01, PI02, and PI03 status words
These registers contain the states of the PI01, PI02, and PI03 terminals.

address 10 - RX data word 0 .
This register contains the corrected received data bits 27 -20.

address 11 - RX data word 1
This register contains the corrected received data bits 19-12.

address 12 - RX data word 2
This register contains the corrected received data bits 11-4.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-21

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
address 13 - RX data word 3
This register contains the corrected received data bits 3-0 and the error-correction status detailed in Table 17.
Table 18. Received Data Word 3
BIT

FUNCTION

RX data bit 3

RX data bit 2

RX data bit 1

RX data bit 0

3-0

Received-data decode status

Table 19. Error-Correction Status
RECEIVED DATA WORD 3

DECODE STATUS

BIT3

BIT2

BIT 1

BITO

No errors detected

One error detected in parity bits

Two errors detected in parity bits

Not used

One error corrected in data

One error corrected in data, one error detected in parity bits

Not used

Two errors corrected in data

Not used

More than two erasures occurred (see Note 2). Up to two data bits
are corrected.

More than two erasures occurred (see Note 2). One error detected
in parity bits. Up to one data bit are corrected.

More than two erasures occurred (see Note 2). Two errors in parity
bits are detected.

More than two errors detected. Data is not corrected.

NOTE 2: A bit erasure occurs when the bit is detected an equal number of times as a 1 and as a 0 over the
valid repeats.

•
TEXAS
INSTRUMENTS
5-22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
addresses 18 to 1C - uncorrected received data
The uncorrected received data can be read from the five uncorrected received data words. The 12 LSBs are
the received parity bits, and the remaining 28 bits are the received data.
address 1D - received repeat count
The received repeat count gives the number of repeats of the received word that were used by the bit-wise
majority voting circuit to generate the uncorrected received data.
address 20 - TCM801 0 read result
Address 20 contains the ADC result retrieved from the TCM801 0 audio processor. This data is valid once the
TCM8010 interface has completed the read operation.
address 30 - SAT (supervisory audio tone)
The SAT tone provides the SAT frequency measurement in 2's-complement format with a resolution of 1 Hz and
with respect to the frequency of 6 kHz, as shown in Table 20.
Table 20. SAT Frequency Measurements

FREQUENCY IN kHz

MEASUREMENT
CODE

6.004

00000011

6.000

11111111

5.996

11111011

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-23

TCM8002
DATA PROCESSOR FOR CELLULAR TELEPHONE
SLWS008C - SEPTEMBER 1994 - REVISED JUNE 1996

APPLICATION INFORMATION
Figure 2 shows a typical complete baseband solution using a TCM8002 data processor and a TCM8010 audio
processor.

Receive Audio Input {RXAUDIO

----7f-------~

TCM8010
RXIN
SP1
TXVO
SP2

\ - - Speak.. 1 }

Recelve
.
Voice Output

t--

Speaker 2

t--

TXAUDlO} Tran.smit
Audio Out

CIN
RXO
M10
Transmit Voice Inputs {MIC1
MIC2

----7
----7

M1N
f---'\/\I\r-___f\N\r--!

M20
M2N

EXIN
TXO
ETC
EXO

CTC

RXVI

CVE

M1P

M2P

CMPR

REF

TXVI

VMID

POUT

cs - DCLK - -

CIl

.a!

0C/l

DATAIN

CIl

DATAOUT

C/l

e
eu
Q.

INTERRUPT

RESET

WATCH·DOG

DATAIN

RESET

----+- WDOUT

~~
_

DCLK

----+- DATAOUT
----+- INTRPT

TIMER

c::::J

TMZERO

XTAL1

SATIN

RXSO

SATOUT

TXSA

RXIN

RXDO

ADC1

ADCIN1

TXOUT

TXDA

ADC2

ADCIN2

DAC1

DAC10UT

HCLK

DCLK

DAC2

DAC20UT

HDATA

DATA

DAC3

DAC30UT

HCS

CLKOUT

Analog I/O

XTI

RFEN

PI01 (0-7)

PI02 (0-7)

PI03(0-3)

RCCBUSY/P04(4)
XTAL2
RAEN/P04(6)
TAEN/P04(7)

Transmitter Enable

RCCBUSY/P04(4)
RAEN/P04(6)

1------------

Figure 2. Complete Baseband Solution

•
TEXAS
INSTRUMENTS
5-24

LIMIN

TCM8002
u
I'CI
't:

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TAEN/P04(7)

I/O Expansion

TCM8010-37
AMPSfTACS AUDIO PROCESSOR
SLWS034-JUNE 1996

•
•
•
•
•
•

TACS and AMPS Operation
Integrated RX and TX Voice Filters
Integrated RX and TX Data Filters
RX and TX Narrow-Band SAT Filters
RX Data Recovery Comparator
Pre-emphasis and De-emphasis Filtering

•
•

Adjustable TX Limiter
Microphone Preamplifiers
Digitally Controlled Gains and Signal
Selection or Muting

•
•

Three a-Bit DACs With Output Buffers
a-Bit ADC With Input Multiplexer

•
•
•
•
•
•
o

DTMF Generator
On-Chip Compandor
Flexible Clock or Oscillator Operation
Simple 3-Wire Digital Interface
Low-Power ... 2-mA Standby Current
44-Pin Mini QFP (FR) Package
Advanced LinBiCMOS Technology

FR PACKAGE
(TOP VIEW)

o
M2P
M2N
M20
POUT
LlMIN
TXO

44 43 42 41 40 39 38 37 36 35 34

VMIO
ANLG VOO

7
8

REF

RXIN
RXO

XTO
XTI
DGTL Voo
DAC3
DAC2
DAC1
CS
DCLK
TXSA
TXDA
ADC2

12 13 14 15 16 17 18 19 20 21 22

description
The TCM8010-37 is a complete AMPSrrACS (advanced mobile telephone service/total access
communications system) audio processor built using the Texas Instruments Advanced LinBiCMOSTM
technology and packaged in a 44-pin mini QFP (FR) package. This device provides a highly integrated solution
for analog-signal processing in mobile and hand-held FM cellular telephones while conserving circuit board area
and vertical height within the finished product. All necessary voice and data filters, and all appropriate
antialiasing and smoothing filters are incorporated in the device. Continuous-time filters are used for the
antialiasing and smoothing functions while switched-capacitor techniques are used only where appropriate.
Ancillary functions such as microphone preamplifiers, differential loudspeaker outputs, CCITT-compatible
compander, DTMF (dual-tone multi-frequency) generator, three 8-bit DACs (digital-to-analog converters), and
an 8-bit ADC (analog-to-digital converter) with input multiplexer are also included in the device. A simple 3-wire
serial interface provides digital control of Signal-path switching, muting and gain adjustment, the 8-bit DACs,
transmit limit level, DTMF code and amplitude, and ADC multiplexer input select, and also allows the ADC output
to be read.
In active mode, the TCM801 0-37 consumes less than 12 mA of supply current. When the DTMF generator or
the ADC are not in operation, the power consumption is even less. The device can be put into a standby mode
in which only the receive (RX) data path is active, reducing the supply current to a typical value of 2 mA or less.
Either the integrated-clock oscillator or an external clock signal (with several frequency options) can be used.

Advanced LinBiCMOS is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA Information Is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily Include
testing of all parameters.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-25

functional block diagram

'('

I\)

.
en
o

O'l

RXO
11

ETC
13

I RXTRIM
±4dB

ANLG

~~~;--:':]

c....

RECEIVE PATH

RXIN 10

RXVI
15
CTI

EXIN
12

De-emphasis
-6dB

17 SP1

Volume
Control
±15 dB

Expander

18 SP2

»-1

:5: 0
"'tJ:5:

~~
)::c;

c
c
o

"'tJ

Data
Comparator

20 RXDO

en
en

-0

ADC1 _ _ _- . I

~z'"
;~~~

ADC2

ffi~~
~ t:

irnG;
s;z

RXSAT
Filter

SAT
Comparator

RXSO

lJ.J

w~><

_2",,-3_ _- . I

DATA

'--

3~ ~

DCLK 26

To Control Registers

TXSAT
Filter
±2dB

SATSW

DTMF
Generator

~ DAC1
3

~(J)

(fl

-.J

'"'"
01

r-------il

TXSA 25
TXDA 24

TX Data
Filter
TRANSMIT PATH

M10

Pre-emphasis
+ 6dB

M2P j
M2N ~
M20

M1P~
M1N ~4

Limiter

•

41
TXVO

POUT

LlMIN

a-Bit
DACS

~ DAC2
30 DAC3

en~

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

AOC1-AOC2

22,23

ANLG VOO

I/O

DESCRIPTION

AOC input 1 and 2. Various voltages can be applied to these terminals for selective conversion and
measurement by the internal NO converter (analog).
Analog positive power supply. VDD

= 3.7 V -

CIN

Compressor input. The signal from TXVO is ac coupled to CIN through an external capacitor (analog).

CMPR

Compressor rectifier input. The Compressor output signal at CO is ac coupled to CMPR and TXVI through
an external capacitor (analog).

Compressor output. The Compressor output signal at CO is ac coupled to CMPR and TXVI through an
external capacitor (analog).

Chip select of serial interface, active low. When pulled low, the TCM801 0-37 is selected (digital).

CTC

Compressor time constant. An external capacitor connected from CTC to G N 0 (V SS) sets the compressor
attack and recovery times (analog).

CTI

Call tone input to RXSW. An external call tone signal can be applied to the receive channel at RXSW
through CTI (analog and digital).

CVE

Compressor virtual ground. An external capacitor should be connected between CVE and CO to improve
the compressor high-frequency stability (analog).

28,29,30

DAC outputs. The result of D/A conversions appear at these terminals (analog).

DATA

I/O

Data line of serial interface. Serial data passes into and out of the TCM801 0-37 through this terminal
(digital).

DCLK

Clock input of serial interface. An external clock signal applied to this terminal clocks the serial interface
and is also used to drive the NO converter (digital).

Expander time constant. An external capacitor connected from ETC to GND (VSS) sets the compressor
attack and recovery times (analog).

DAC1-DAC3

= 3.7 V -

DGTL VDD

ETC

EXIN

Expander input. The signal from RXO is ac coupled to EXIN through an external capacitor (analog).

EXO

Expander output. The Expander output signal at EXO is ac coupled to RXVI through an external capacitor
(analog).

Digital positive power supply. VDD

LlMIN

Limiter input. The signal from POUT is ac coupled to LlMIN through an external capacitor (analog).

MlO

Microphone amplifer 1 output. The output signal at this terminal can be applied to the transmit path or used
for an external accessory. It is also used for setting the gain of Microphone amplifer 1 (analog).

M1P,M1N
M20
M2P, M2N
POUT
REF

43,44

Microphone amplifier 1 differential inputs. Voice signals are input on these terminals (analog).

Microphone amplifer 2 output. The output signal at this terminal can be applied to the transmit path or used
for an external accessory. It is also used for setting the gain of Microphone amplifer 2 (analog).

1,2

Microphone amplifier 2 differential inputs. Voice signals are input on these terminals (analog).

Pre-emphasis output. The output signal at POUT is ac coupled to LlMIN through an external capacitor
(analog).
Midrail reference. REF should be decoupled to Vss with an external capacitor.

RXDO

Receive section data output. The Data Comparator output signal is available at RXDO (digital).

RXIN

Receive section input. The demodulated signal from the RF receiver is input through RXIN (analog).

RXO

Receive section deemphasis voice filter output. The signal at RXO is ac coupled to EXIN through an
external capacitor (analog).

RXSO

Receive section supervisory audio tone output. Recovered SAT signals or the output of the RX SAT Filter
block is available at this terminal (digital or analog).

RXVI

Voice input to Volume Control stage. The Expander output signal at EXO is ac coupled to RXVI through
an external capacitor (analog).

17,18

Speaker outputs 1 and 2. These outputs can be configured as differential drive (both terminals), one or the
other as a single-ended (one terminal active), or both terminals muted (analog).

Transmit data filter input. An external Manchester-encoded digital Signal is applied to this terminal (digital).

SP1, SP2
TXDA

l./}TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-27

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

Terminal Functions
6

TXSA

Transmit SAT input. External SAT data is input at TXSA.

TXVI

Voice input to transrnit output stages. The Compressor output signal at CO is ac coupled to TXVI through
an external capacitor (analog).

TXVO

Transmit voice input stage output. The voice output signal at TXVO is ac coupled to CIN through an external
capacitor (analog).

TXO

Transmit section output. Voice, SAT, and data signals, summed together in any combination, are output at
TXO to be routed to the RF transmitter.

VMID

VSS

Negative power supply. VSS

XTI

Crystal/external clock input. A crystal is connected between XTI and XTO for internal oscillator operation
or an external clock signal (2': 0.5 V peak sinusoidal) is applied to XTI.

XTO

32,33

Buffered midrail voltage. VMID should be decoupled to Vss with an external capacitor.

=0 V.

Crystal inputs. A crystal is connected between XTO and XTI for internal oscillator operation.

•
TEXAS
INSTRUMENTS
5-28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range, Voo (see Note'1) .............................................. -0.3 V to 7 V
Input voltage, VI (any pin) ............................................... VSS - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA ............................................ -30°C to 70 D C
Continuous total power dissipation at (or below) TA = 25°C ................................... 893 mW
Storage temperature range, Tstg ................................................... -65°C to 150D C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to VSS.

recommended operating conditions
MIN

NOM

MAX

3.7

Supply voltage, DGTL VDD and ANLG VDD
High-level input voltage, VIH

V
V

0.8VDD

Low-level input voltage, VIL
-30

Operating free-air temperature range, TA

UNIT

0.8

electrical characteristics over recommended operating virtual junction temperature range,
Voo = 4 V, fxtal = 2.56 MHz
MIN

PARAMETER
Standby mode, DACs off
IDD(A)

Analog supply current

1.3

1.88

9.5

14.82

10.1

Operating mode

UNIT

1.52

Standby mode, DACs on

Including DTMF generator

Digital supply current

MAX

Operating mode

Standby mode
IDD(D)

TYP

0.9

15.82
85

882

0.41

1.29

ADC operating
REF

Mid-supply voltage at REF terminal

Operating mode

1.92

2.08

VMID

Buffered mid-supply reference voltage

Operating mode

1.92

2.08

MIN

TYP

MAX

analog inputs
PARAMETER
II
Zi

IInput impedance at RXIN, RXVI, L1MIN, TXSA, TXDA

100

I Input impedance at EXIN, CIN, CMPR, TXVI

UNIT
~A

Input current at M1 P, M1 N, M2P, M2N, ADC1, ADC2, CTI

digital interface
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

IIH

High-level input current

VI =5V

IlL

Low-level input current

VI=OV

1
1

fCLK

Serial clock frequency, DCLK input

VOH

High-level output voltage

IOH = 500 ~A

VOL

Low-level output voltage

IOL = 500 ~A

0.9VDD
0.1 VDD

UNIT
~A

MHz
V

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-29

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034-JUNE 1996

transmit path electrical characteristics (see the functional block diagram)
input stage gain M10/M20 to TXVO, VOO

=4 V
MIN

MAX

Gain

MICTRIM = < 1000>

-0.5

0.5

MICTRIM positive range

MICTRIM = <1111 >

3.3

4.3

MICTRIM negative range

MICTRIM = < 0000>

-4.8

-3.8

0.38

0.68

TEST CONDITIONSt

PARAMETER

MICTRIM step size

Preamp CMRR
Distortion

VI = 0.8 V,

f= 1 kHz

MICSW isolation

VI = 80mV,

f = 1 kHz

UNIT
dB

dB
0.5%

t The control bits associated with a block or function are shown in < > (see Table 1).

compressor CIN to CO, Voo = 4 V
TEST CONDITIONS

MIN

TYP

MAX

UNIT

60.7

102.3

VI = Vref + 2 dB to Vref -18 dB

-0.01

±0.5

VI = Vref -18 dB to Vref -48 dB

-0.16

±1

PARAMETER
Unity gain levelt
EL

Relative linearity error

RCOMP

Compressor resistance

:j: This parameter becomes Vref for the relative-linearity-error test conditions.

output stage TXVI to TXO, Voo = 4 V
TEST CONDITIONSt

PARAMETER
TXTRIM step size

MIN

MAX

UNIT

0.16

0.36

TXTRIM positive range

TXTRIM = <11111 >

3.5

4.5

TXTRIM negative range

TXTRIM = <00000>

-4.8

-3.8

MIN

MAX

UNIT

1520

mVpp

TXATTEN step size
TXATTEN range

t The control bits associated with a block or function are shown in < > (see Table 1).
output stage limiter TXVI to TXO, Voo

=4 V
TEST CONDITIONSt

PARAMETER

Maximum output signal

TXVI = 253 mY,
f = 300 Hz to 25000 Hz,
L1M=<110>

Distortion

f= 1 kHz,
Level at TXO = 2/3 x level measured in
previous test,
LIM = <110>

Trim step size, analog test mode A, output at RXDO

TXVI = 253 mV

0.8

1.2

Trim positive range, analog test mode A, output at RXDO

L1M=<111>

2.5

3.5

Trim negative range, analog test mode A, output at RXDO

LIM = <000>

-4.5

-3.5

The control bits associated with a block or function are shown in < > (see Table 1).

~TEXAS

INSTRUMENTS

5-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

output stage frequency response TXVI to TXO, Voo
PARAMETER

=4 V
TEST CONDITIONS

MIN

f < 200 Hz

O-dB reference at f = 1 kHz,
TXVI = 20.8 mV

Frequency response

UNIT

-20

f = 300 Hz

-13.46

-9.46

f = 500 Hz

-9.02

-5.02

f = 2000 Hz

3.02

7.02

f = 2500 Hz

4.96

8.96

f = 3000 Hz

4.96

10.54

f = 5900 Hz

-35

f = 6000 Hz

-35

overall transmit path electrical characteristics M10/M20 to TXO, TXATT

=<00>, VDD =4 V

TEST CONDITIONSt

MIN

TYP

MAX

UNIT

Compressor bypass gain

MICT = < 1000>, TXT = < 10000>

10.8

13.0

Output noise, compressor enabled,
M10/M20 = VMID psophometric weighting

RXIN = 320 mV,

f = 1 kHz

2.3

6.47

mVrms

Voice mute attenuation

MlO/M20 = 80 mV,

f = 1 kHz

PARAMETER

MAX

-80

The control bits associated with a block or function are shown in < > (see Table 1).

DATA output levels TXDA to TXO, VOO

=4 V

PARAMETER
Output level

Frequency response

MIN

MAX

UNIT

AMPS

fl = 1O-kHz square wave, amplitude 0 V to 4 V

TEST CONDITIONS

856

950

mVpp

TACS

fl = 8-kHz square wave, amplitude 0 V to 4 V

856

950

mVpp

kHz

14.4

17.6

kHz

AMPS
TACS

3 dB relative to 1 kHz,

Analog test mode B

Transmit data mute attenuation

SAT output levels TXSA to TXO, Voo = 4 V
PARAMETER
Output level

TEST CONDITIONSt
fl = 6-kHz square wave, amplitude 0 V to 4 V

ISAT = <0>,

SAT trim positive range
SAT trim negative range
SAT trim step size

MAX

UNIT

93.1

1.9

2.4

-2.8

-2.2

0.4

f < 3 kHz

0.2

-35

f = 4.8 kHz

-25

f=5.1 kHz

-20

-5

0.5

f = 5.94 kHz

-0.5

0.5

f = 6.06 kHz

-0.5

0.5

-5

0.5

f=7.2kHz

-20

f> 9 kHz

-35

f = 5.8 kHz
Frequency response

MIN
76.2

O-dB reference at f = 6 kHz,

ISAT= <0>

f = 6.2 kHz

Transmit SAT mute attenuation

t The control bits associated with a block or function are shown in < > (see Table 1).

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-31

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

SAT output level RXIN to TXO, RXT

=<1000>, SAT =<1000>, TXT =<10000>, Voo =4 V

PARAMETER

TEST CONDITIONSt

SAT output level

ISAT = <1 >,

MIN

Input to RXIN = 6-kHz sine wave, amplitude 480 mV

TYP

MAX

320

t The control bits associated with a block or function are shown in < > (see Table 1).
receive path electrical characteristics (see the functional block diagram)
input stage RXIN to RXO, Voo = 4 V
PARAMETER

TEST CONDITIONSt

MIN

MAX

UNIT

Gain

RXTRIM = < 1000>

-6.4

-5.2

RXTRIM positive range

RXTRIM = < 1111 >

3.2

4.2

RXTRIM negative range

RXTRIM = <0000>

-4.5

-3.8

0.39

0.69

RXTRIM step size

O-dB reference at f = 1 kHz,
RXIN = 320 mV

Frequency response

f <100 Hz

-28

f = 240 Hz

12.9

f = 300 Hz

f =400 Hz

7.5

8.6

f = 2400 Hz

-8.2

-7.1

f = 3000 Hz

-12

-9

-40

f> 5900 Hz

t The control bits associated with a block or function are shown in < > (see Table 1).
Expander EXIN to EXO, Voo

=4 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

64.1

100

104.1

EXIN = Vref +9.5 dB to Vref -2.8 dB

-0.3

±1

EXIN = Vref -2.8 dB to Vref -23.8 dB

-0.8

±2

71.6

UNIT

Unity gain level = Vref+
Relative linearity error
Internal Expander resistance (REXP)

37.5

:j: This parameter becomes Vref for the relative-linearity-error test conditions.

output stage
PARAMETER

Volume control

TEST CONDITIONSt

MIN

MAX

Gain RXVI to SP1/SP2

VOL= <1000>

0.5

1.5

Positive range

VOL = <1111 >

Negative range

VOL= <0000>

-16.5

-15.5

1.75

2.25

VOL=<1000>

VOL= <1000>

-5.5

-4

Step size
CTI input
Expander bypass gain from RXIN to SP1/SP2

Gain to SP1/SP2

Output load at SP1/SP2
Output voltage at SP1/SP2

RL= 500 n

Distortion at SP1/SP2, expander enabled

RXIN = 400 mV,

Noise at SP1/SP2, expander bypassed

RXIN = VMID, psophometric weighting

Voice mute attenuation

RXIN = 400 mV,

t The control bits associated with a block or function are shown in < > (see Table 1).

~TEXAS

INSTRUMENTS
5-32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f = 1 kHz,
f = 1 kHz

500

1.96

Vpp

No load

2%
3
50

mV
dB

TCM8010-37
AMPSfTACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

RX DATA comparator RXIN to RXDO, Voo = 4 V
PARAMETER

TEST CONDITIONS

MIN

Must-detect level

MAX

168.2
f = 4 kHz, 5 kHz,
8 kHz, and 10kHz

Must-nat-detect level
Output duty cycle

35.4
47.5%

RXIN = 900 mV peak to peak

RX SAT frequency response RXIN to RXSO, SATDIG
PARAMETER

mVpp

52.5%

=< 1 >, Voo =4 V
TEST CONDITIONS

MAX

UNIT

f < 3 kHz

MIN

-35

f = 4.8 kHz

-25

f=5.1 kHz

-19

-5

0.5

f = 5.94 kHz

-0.5

0.5

f = 6.06 kHz

-0.5

0.5

f = 5.8 kHz
Frequency response

UNIT

O-dB reference at f = 6 kHz

-5

0.5

f = 7.2 kHz

-20

1> 9 kHz

-35

f = 6.2 kHz

RX SAT comparator RXIN to RXSO, SATDIG = <0>, Voo = 4 V
PARAMETER'

TEST CONDITIONS

MIN

TYP

f = 6 kHz

Must-detect level

MAX

miscellaneous block electrical characteristics
digital-to-analog converters DAC1, DAC2, and DAC3
TEST CONDITIONSt

MIN

Output voltage at code 255

PARAMETER

DACX2 = <1 >

VDD-130

Output voltage at code 255

DACX2 = <0>

VDD/2-100

Zero code offset

TYP

MAX

UNIT
mV

VDD/2 + 100

40.3

Differential nonlinearity (codes 5 - 250)

0.3

LSB

Integral nonlinearity (codes 5 - 250)

0.3

LSB

t The control bits associated with a block or function are shown in < > (see Table 1).
analog-to-digital converters, DCLK

=160 kHz, Voo =4 V

PARAMETER

TEST CONDITIONS

Full scale for inputs ADC1, ADC2, and VMID

MIN

TYP

2.3

2.6

Differential nonlinearity

0.5

Integral nonlinearity

0.5

Clock rate (DCLK)

MAX

UNIT
V

LSB

200

kHz

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-33

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

DTMF generator transmit levels at TXO, TXTRIM
PARAMETER

DTTRt

=<10000>, Voo =4 V
TEST CONDITIONS

697·Hz tone, low tone

AMPS mode

1477-Hz tone, high tone

TYP

MAX

UNIT

117

129.6

238.8

264

296.5

48.6

71.5

110.6

137

153.5

<0100>

697-Hz tone, low tone

TACS mode

1477-Hz tone, high tone

DTMF trim steps

MIN
86.8

<0000> - <0001 >

0.4

<0001> - <0010>

0.4

<0010> - <0011 >

0.4

<0011> - <0100>

0.5

<0100> - <0101 >

0.5

<0101> - <0110>

0.6

<0110> - <0111 >

0.6

<0111> - < 1000>

0.7

< 1000> - < 1001 >

0.7

<1001> - <1010>

0.8

<1010>-<1011>

0.9

< 1011> - < 1100>

1.0

< 1100> - < 1101 >

1.1

<1101> - <1110>

1.3

<1110> - <1111 >

1.5

Positive range

<0100>-<1111>

7.63

9.8

11.75

Negative range

<0100> - <0000>

-2.58

-1.39

-1.29

1.3

1.85

2.2

Skew, change in level of high tone

<0100>

Distortion products

<0100>

Relative to low tone

-30

The control bits associated with a block or function are shown in < > (see Table 1).

DTMF generator receive levels at SP1 and SP2, DTTR = <0100>, VOL = <1000>, Voo = 4 V
PARAMETER
All tones
Distortion products

TEST CONDITIONS

MIN

MAX

UNIT

AMPS mode

45.6

54.6

TACS mode

22.5

29.1

-40

Relative to low tone

~TEXAS

INSTRUMENTS
5-34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

TYPICAL CHARACTERISTICS
TRANSMIT PASS-BAND DETAIL

TRANSMIT VOICE FREQUENCY RESPONSE

VOO~4 J

III
'C

c
.2
iii

IAI'

-20

CI)

-30

1\,

Limit
'C

«
CI)

;g
Lower
Limit

-50

«>

I I II

-60

-70

Limi~
-5

-10

-15
-20
100

10000

1000

100

/.~

I
-

IIIII
11111

10
'C

Figure 2

0
-10

-20

E
ii
«
CI)

-30

-40

;g
«>

I-- -

Vi 0

=4 Vi

10
III

I '~

c
0

Actual

E
ii

«
CI)

-5

\~
,

Lower
Limit

;g
I

-10

\
1000

10000

If"~~~
,I
II
II
If
II

-20
100

I I II

VO[ ='4 V'

Upper
Limit

Lower
Limit
I

«>
-15

-50
-60
100

RECEIVE PASS-BAND DETAIL

... ~

.2
iii

Upper
Limit
~

10000

f - Frequency - Hz

RECEIVE VOICE FREQUENCY RESPONSE

III

Actual

Figure 1

,.......

Lower
Limit

1000

f - Frequency - Hz

Upper

-40

«>

.2
iii
u
E
ii
E

Actual __

III

Voo ~ 4 \i

Upper

\
\

~;:::::::

-10

I I IIII

io\

I I

Actual

~
1000

10000

f - Frequency - Hz

f - Frcqucncy - Hz

Figure 4

Figure 3

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-35

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034

JUNE 1996

TYPICAL CHARACTERISTICS
TRANSMIT SAT FREQUENCY RESPONSE
10

TRANSMIT

VOp=4 V

s::

-10

ca
~
a.
E
«CII

-20
-30

>- Upper

;g
I

-40

«>
-50

Limit

h~
! ~,\
Vi~
I~,

-2
-3

-4

CII
Cl

-5

-6

......

I I

4000

6000

8000

5700

5500

f - Frequency - Hz

6100

6300

\
6500

Figure 6
RECEIVE PASS-BAND DETAIL

VOO=4 V

V0 0=1 V

-1

s::

-2

-3

-4

CII
Cl

-5

-6

«
S

«>

/
/

-7

-8
-60L-~~~--~--~--~--~--~~

8000

10000

-9

"\ \

J /

I
-50~~~-4---+--1a

V r

Actual/

:Ea.

6000

f - Frequency - Hz

RECEIVE SAT FREQUENCY RESPONSE

4000

\
\

5900

Figure 5

2000

I I

)

-9

10000

Lower
Limit

-8

/
/

Lower
Limit

Upper
Limit

«> -7

j/1

s::

~ -.....

V r h ""\
II \ '\
ActU~1 I
1

-1

ca
~
a.

Vo p=4 V

ttu~~
2000

Upper Limit

Lower
Limit

5700

5900

6100

f - Frequency - Hz

Figure 7

Figure 8

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

\
1\
\

)

5500

f - Frequency - Hz

5-36

P~SS-BAND DETAIL

6300

6500

TCM8010-37
AMPSfTACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

TYPICAL CHARACTERISTICS
TRANSMIT DATA FREQUENCY RESPONSE - TACS

TRANSMIT DATA FREQUENCY RESPONSE - AMPS
5
I
I I I II

In
I

I:
0

-5

i5..

-10

-20

-15

-25

"""

-25
1000

-20

>
. In standby mode < STBY >,
the receive data path from RXIN to RXDO is on and the DACs can be on or off as required. All other parts of
the device, including the crystal oscillator, are off. When in the active mode, the receive and transmit paths and
the DAC blocks are continuously on, and theDTMF generators and ADCs are turned on as required.
Control bits < MD1 - MDo> set the TCM801 0-37 for the desired system (AMPS or TACS).

transmit path
The transmit path on the TCM801 0-37 consists of a number of functional blocks, which are described in the
following paragraphs.
MIC INPUTS
Voice signals are input on M1 P, M1 N, M2P, and M2N to a pair of microphone preamplifiers, which are stable
for gains between 0 dB and 20 dB. All voice-path specifications are given with the preamplifiers configured as
unity-gain inverting amplifiers. In standby mode, the bias to the microphone preamplifiers is turned off and the
outputs M1 0 and M20 are in the high-impedance state.

MICSW
The MICSW block is a 2-input switch that selects either of the preamplifier outputs, and is under control of the
digital control interface through the control word < MICSEL>.

MICTRIM
The MICTRIM block provides gain adjustment to compensate for differing microphone sensitivities
< MICT3 - MICT0 >. A second-order Sallen-Key low-pass filter is incorporated in this block to provide antialiasing
for the transmit voice signal.

COMPRESSOR
The compressor provides a 1-dB change in output signal level for a 2-dB change in input level over an operating
input range of 50 dB. The unity-gain point, Vref, is proportional to the value of VDD (see the compressor table
in the transmit path electrical charactistics). Attack time is measured by increasing the input-signal amplitude
by a 12-dB step relative to 13 mV rms and is defined as the time required for the output envelope to reach 1.5
times the final steady-state level. Recovery time is measured by reducing the input signal amplitude by a 12-dB
step to 13 mV rms and is defined as the time required for the output envelope to settle to 0.75 times the final
steady-state level.
The attack and recovery times are determined by an internal resistor (RCOMP) and the external capacitor, CCTC,
connected between CTC and VSS (0 V).
Attack time = 0.151 x CCTC x RCOMP
Recovery time = 0.693 x CCTC x RCOMP

TXSW
This functional block is a 3-input switch that selects either the compressor output, compressor bypass (for
testing), or the output of the DTMF generator. TXSW is controlled by .

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8010-37
AMPSrrACS AUDIO PROCESSOR
SLWS034-JUNE 1996

PRINCIPLES OF OPERATION
TXATTEN

The output of TXSW passes through the TXATTEN block, which provides four levels of attenuation.
PRE·EMPHASIS

The output from TXATTEN is connected to the Pre-emphasis block, which provides the necessary 6 dB per
octave increase in gain with frequency by using a second-order filter. Also included in this block is an
eighth-order band-pass filter function with a 300-Hz to 3-kHz passband. The nominal gain of this stage is 6 dB
at 1 kHz and its output is routed to the POUT terminal.
LIMITER

The Limiter block limits the maximum output under overload signal conditions, and the limit level is adjustable
under control serial interface bits < L1M2 - LIMa>. The limiter range is designed to allow the transmit path
distortion and maximum signal output specifications to be achieved at a single limiter-adjustment code. The
output of the Pre-emphasis block is ac coupled (through an external capacitor) into the L1MIN terminal to ensure
symmetrical limiting.
LOW·PASS FILTER

The limiter output is processed by the Low-Pass Filter block, which is a fourth-order low-pass filter plus
second-order equalizer, to remove excessive harmonics produced by the limiting process.
TXSUM

This block can sum together or mute any of its three inputs (SAT, data, and voice) under the control of the
bits respectively.
TXTRIM

The TXTRIM gain-adjust block can compensate for different modulator sensitivities using bits .
A continuous-time output low-pass smoothing filter is included with a typical cutoff frequency of 30 kHz.
TX DATA FILTER

Transmit data is input to terminal TXDA and is routed to the TX Data Filter block where the data is first
conditioned by a second-order antialiasing filter before going on to the transmit data filter.
The transmit data is a Manchester-encoded digital Signal at 10k biVs for AMPS or 8k bits/s for TAGS. The
transmit data filter for these two modes is a fourth-order Butterworth low-pass filter, with its - 3-dB point
switch able between AMPS and TAGS modes.
The filtered AMPS or TAGS wide-band data signal is summed into the transmit Signal path in the TXSUM block.
TXSAT FILTER PATH - TXSA to TXO

The input to the transmit SAT signal path is determined by the SATSW block, which selects between the TXSA
terminal and the output of the receive SAT filter (RXSAT). The signal is processed by the TXSAT filter block,
which includes an antialiasing filter, a fourth-order narrow-band band-pass filter centered at 6 kHz, and a
gain-adjust stage < SAT3 - SATa>. The output of this block is then applied to an input of TXSUM to be summed
into the voice path when selected.

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5-39

TCM8010-37
AMPSrrACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION
receive path - voice
The demodulated signal from the receiver is input to the TCM8010-37 at the RXIN terminal. A pair of
loudspeaker drivers are provided, producing output signals on terminals SP1 and SP2, and are capable of
driving 500-0 loads.

RXTRIM
A gain-adjust block, RXTRIM, is provided to allow variations in the receiver FM demodulator/discriminator
characteristics to be accommodated . This block is enabled in both active and standby modes.
A second-order continuous-time filter with a typical cutoff frequency of 30 kHz provides an antialiasing function
for the receive signal path.

DE-EMPHASIS
The De-emphasis filter block exhibits a 6-dB/octave decrease in gain versus frequency characteristic. It also
includes an eighth-order band-pass filter (passband =300 Hz to 3 kHz) to separate the received voice signal
from the data and SAT signals. A continuous-time smoothing filter is incorporated at the output, and the output
signal appears at terminal RXO.

EXPANDER
The Expander block provides a 2-dB change in output signal level for a 1-dB change in input level over an
operating input range of 33 dB. The unity-gain level, Vref, is proportional to VDD (see the expander table in the
receiver path electrical charactistics). Attack time is measured by increasing the input signal amplitude by a 6-dB
step relative to 72.5 mV and is defined as the time required for the output envelope to reach 0.57 times the final
steady-state level. Recovery time is measured by reducing the input signal amplitude by a 6-dB step to 72.5
mV and is defined as the time required for the output envelope to settle to 1.5 times the final steady-state level.
The attack and recovery times are determined by an internal resistor, REXP, and the external capacitor, CEXP,
connected to ETC and 0 V, Vss.
Attack time = 0.173 x CETC x REXP
Recovery time

=0.693 x CETC x REXP

RXSW
RXSW is a 4-input switch block that provides a selection between the call-tone input terminal (CTI), the
expander output (externally capacitively coupled to terminal RXVI), the expander-bypass path (for testing), and
the output from the DTMF generator as the input to the volume-control block. The control bits are < RXSW1 and
RXSWo>·
To simplify the connection of a digital signal for a user alert tone (typically between 200 Hz and 400 Hz), no
internal bias is provided forthe CTI input. If an ac-coupled signal is applied to CTI, an external bias resistor with
a typical value of 100 kn is required and should be connected between CTI and VMID.

VOLUME CONTROL
The Volume Control block provides output level adjustment to implement a user-adjustable level control using
control bits .

LSSW
The loudspeaker control switch block (LSSW) allows selection between either SP1 or SP2 outputs, muting, or
differential drive of both terminals through the control bits < LS1 - LSo>.

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INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION
receive path - data/SAT
The demodulated signal from the receiver is input to the TCM8010-37 at the RXIN terminal. This signal,
containing voice, data, and SAT components, is processed and antialias-filtered by the RXTRIM block.
receive data path - DATA COMPARATOR
The signal from RXTRIM is applied to the data comparator block, which has defined threshold levels. The data
signal is Manchester-encoded at 10 kbiUs for AMPS mode and at 8 kbiUs for TACS mode. Detected data
appears at RXDO. This signal path is enabled in the standby mode.
receive SAT path - RX SAT FILTER
The RX SAT Filter block uses a fourth-order Butterworth band-pass filter centered at 6 kHz to separate received
SAT signals from the voice signal. The output of the band-pass filter is routed to an input of the SATSW block
and to the SAT Comparator block.
receive SAT path - SATSW
SATSW is a 2-input switch block that selects between the output of the RX SAT filter and an external SAT source
(applied to terminal TXSA) using control bit .
receive SAT path - SAT COMPARATOR
The SAT Comparator block recovers the SAT signal and has defined hysteresis levels for improved noise
immunity. The output is routed to terminal RXSO. An internal switch, controlled by bit , bypasses the
SAT comparator and applies the output from the RX SAT Filter block directly to terminal RXSO.

digital interface
The TCM801 0-37 is controlled by a 3-wire digital interface, consisting of a clock signal (DCLK), a chip select
(CS), and a bidirectional data line (DATA). The logic signal present on DATA is written into the device on the
rising edge of DCLK when CS is low. Serial messages to and from the device contain a read/write bit, an address
field, and a data word. Results from the ADC are read back using the serial interface, and the DCLK signal is
used to drive the converter. Test access to analog and digital sections of the device are provided using the serial
interface.
write operations
A timing diagram for a write operation to the device is shown in Figure 13. In this case, the read/write bit is set
to 1, followed by a 3-bit address word (A2-AO), and a 10-bit data word (09-00). Data shifts into the device on
the rising edge of DCLK and is transferred to internal registers on the falling edge of the fourteenth clock pulse
after CS goes low. If CS returns high before this tiTe, no transfer takes place and the input interface is reset.
cs

1'---_ _ _ _ _ _ _ _-""1

OCLK

DATA

Figure 13. Write-Operation Timing

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5-41

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION

control words
Table 1 shows control-word and configuration assignments for the device. Table 2 shows control-word
descriptions, Table 3 shows test modes, and Table 4 details DTMF control words.

Table 1. Control-Word and Configuration Assignments
Address Bits

CONTROL DATA BITS

Word 0

STBY

MD1

MDO

ISAT

SATDIG

DACX2

CKSEL

CKRT2

CKRT1

CKRTO

Word 1

TXSW1

TXSWO

TXSAT

TXDAT

TXVOX

TXATI1

TXATIO

DACON

LS1

LSO

Word 2

MICSEL

MICT3

MICT2

MICT1

MICTO

TXT4

TXT3

TXT2

TXT1

TXTO

Word 3

LlM2

LlM1

LIMO

SAT3

SAT2

SAT1

SATO

Word 4

RXT3

RXT2

RXT1

RXTO

RXSW1

RXSWO

VOL3

VOL2

VOL1

YOLO

WordS

DTSK

DTIR3

DTIR2

DTIR1

DTIRO

TEST1

TESTO

Word 6

DACAD1

DACADO

DAC7

DAC6

DAC5

DAC4

DAC3

DAC2

DAC1

DACO

Word 7

DTMF3

DTMF2

DTMF1

DTMFO

Table 2. Control-Word Descriptions
DESCRIPTION
Word 0

STBY = Standby select: 0 = Standby, 1 = Active
MD1 - MDO = Mode select: 00 = AMPS, 01 = Undefined, 10 = TACS, 11 = Undefined
ISAT = SAT select: 0 = External, 1 = Internal
SATDIG =Digital/Analog RX SAT: 0 = Digital, 1 = Analog
DACX2 = DAC range select: 0 = 0 - VDD/2, 1 = 0 - VDD
CKSEL = Clock source select: 0 = Oscillator, 1 = Sinusoidal input
CKRT2 -CKRTO = Clock rate select: 000 = 3.58 MHz, 001 = 7.16 MHz, 010 = 10.74 MHz, 011 = 14.32 MHz, 100 = 2.56 MHz,
101 = 10.24 MHz, 110 = 12.80 MHz, 111 = 15.36 MHz

Word 1

TXSW1 - TXSWO = TX Voice select: 00 = Mute, 01 = Compressor O/P, 10= Compressor bypass, 11 = DTMF
TXSAT = Transmit SAT enable: 0 = Mute, 1 = Enable
TXDAT = Transmit Wide-band data enable: 0 = Mute, 1 = Enable
TXVOX = Transmit Voice enable: 0 = Mute, 1 = Enable
TXATI 1 - TXATI0 = TX attenuation: 00 = 0 dB, 01 = 8 dB, 10 = dB, 11 = 24 dB
DACON =DACS on select in standby: 0 = Off, 1 = On
LS1 - LSO = Loudspeaker configuration: 00 = Mute, 01 = SP2 enable, 10= SP1 enable, 11 = Differential

Word 2

MICSEL =Microphone select: 0 = M1, 1 = M2
MICT3 - MICTO = Microphone trim: 0000 = minimum gain, 1111 = maximum gain
TXT4 - TXT0 = TX Deviation trim: 00000 = minimum gain, 11111 = maximum gain

Word 3

L1M2 - LIMO = Deviation limiter adjust: 000 = minimum deviation, 111 = maximum deviation
SAT3 - SATO = TXSAT adjust: 0000 = minimum, 1111 = maximum
DO - D1 =0, D2 = 1

Word 4

RXT3 - RXTO = RX input adjust: 0000 = minimum, 1111 = maximum
RXSW1 - RXSWO = RX switch control: 00 = CT input, 01 = Expander O/P,.1 0 = Expander bypass, 11 = DTMF
VOL3 - YOLO = RX path audio volume control: 0000 = minimum, 1111 = maximum

Word 5

DTSK = DTMF Skew enable: 0 = disabled, 1 = enabled
DTIR3 - DTIRO = DTMF adjust: 0000 = minimum, 1111 = maximum
TEST 1 - TEST 0 = Test mode: (see Table 3)
D2- D4 =0

Word 6

DACAD1 - DACADO = DAC address: 00 = DAC 1, 01 = DAC 2,10 = DAC 3,11 = a" DACs

Word 7

DTMF3 - DTMFO = DTMF control: (see Table 4)

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION
Table 3. Test Modes (Word 5)
CONTROL BITS

TEST OUTPUTS

MODE

SATDIG

TEST1

TESTO

AT RXDO

AT RXSO

Digital Test

Digital DTMF High Tone

Digital DTMF Low Tone

Analog Test A

Receive Data (analog)

Analog Test B

Limiter Output (dc)

Bandgap Output

Transmit Data (analog)

Other States

Recieve Data (digital)

Receive SAT (digital)

Other States

Digital DTMF High Tone

Digital DTMF Low Tone

Other States

Digital DTMF High Tone

RXSAT (analog)

Normal

Table 4. DTMF Control (Word 7)
CONTROL BITS

DTMF GENERATOR OUTPUT

DTMF3

DTMF2

DTMF1

DTMFO

KEY

LOW TONE (Hz)

HIGH TONE (Hz)

697

1209

770

1209

852

1209

941

1209

697

1336

770

1336

852

1336

941

1336

697

1477

770

1477

852

1477

941

1477

697

Off

1209

Off

1477

Off

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5-43

TCM8010-37
AMPSrrACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION
read operations
A timing diagram of a read operation, which outputs ADC results from the device, is shown in
Figure 14. The first bit driven into the device is a logic 0, followed by a 3-bit address word. The device then
assumes control of the DATA line on the falling edge of the fifth clock pulse after CS goes low. The conversion
result is output MSB first, with the MSB being output on the falling edge of the seventh clock pulse after CS goes
low. Control of the DATA line is released (returned to input mode) when CS goes high.

I ~----------------~I

OCLK

DATA
IN

=xl

AO
MSB

I I I

DATA
OUT

LSB
05

AOC
Sample

Figure 14. Read-Operation Timing
Table 5 details the decoding of the three address bits.

Table 5. Address Bit Decoding
A2

REFERENCE

Band gap

MEASUREMENT
VMID
ADC1
ADC2

additional functions
The following paragraphs detail some additional functions of the TCM801 0-37.

digital-to-analog converters
Three 8-bit, voltage-output DACs are provided, with outputs on terminals DAC1, DAC2, and DAC3. The output
range of each converter is from 0 V to VOO/2 or 0 V to VOO with an LSB step size of VOO/256 or VOO/2 x 1/256
as selected by < DACX2 >. All DAC outputs can either go to 0 V in standby mode or be active depending on the
state of control bit . For correct operation of the TCM8010-37, < DACON > must be cleared to 0 in
active mode. Previously written values are restored to the DAC outputs on entry to active mode.
selects which DAC is being addressed, and sets the output voltage.

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TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

PRINCIPLES OF OPERATION
analog-to-digital converter

The TCM801 0-37 contains an 8-bit ADC with a 3-channel analog-input multiplexer. This allows conversion of
signals on ADC1, ADC2, and VMID. An internal band-gap voltage reference multiplied by two is used
when measuring ADC1, ADC2, and VMID.
Fifteen periods of DCLK are required to complete a conversion.
DTMF Generator

The DTMF generator produces the seven standard tones with a frequency accuracy of ± 1%. The desired DTMF
Signal is selected by . A switchable pre-emphasis or skew between the low and high tone
groups is provided for TACS operation and is selected by bit < DTSK>.
DTMF signal levels scale directly with supply voltage. A 4-bit trim is provided to allow adjustment of DTMF
amplitude to meet system specifications and allow flexibility for user-generated call-tone-type Signals
«DTTR3-DTTRo». When DTMF is selected in the transmit or receive paths, typical voice signals are
attenuated by 50 dB.

clock and supply
Power supply and clock considerations are covered in the following paragraphs.
supply voltage

Specifications are given for a supply voltage of 5 V. Signal levels such as SAT, DATA, and DTMF are derived
from this. Other parameters such as the compressor and expander unity-gain levels are also dependent on the
supply voltage.
supply current

The TCM801 0-37 has two basic operating modes: standby and active. In the standby mode, only the receive
data path is enabled and current consumption is less than 2 rnA. There is also the option of keeping the DACs
powered up in the standby mode, depending on the setting of . In the active mode, all functional
blocks are powered up and the current consumption is less than 12 rnA.
crystal oscillator and clock interface

The clock signal for the device can be generated by the internal Oscillator block using an external crystal
connected to the XTO and XTI terminals. Or, an external 0.5-V (minimum) peak sinusoidal clock signal can be
applied to XTI. The external clock signal or the crystal can be one of eight frequencies, selected by control bits
< CKRT2-CKRTa>. Crystal or external clock operation is selected by < CKSEL>.

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5-45

TCM8010-37
AMPSrrACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

APPLICATION INFORMATION

analog cellular telephone baseband solution
The TCM8002 and TCM801 0-37 chip set provides a complete solution to the audio and data filtering, decoding,
and encoding required in a cellular telephone forthe AMPS orTACS systems. The applications circuit schematic
is shown in Figure 15 and demonstrates that a minimum of external components is required.
The following extra functions are included in the TCM801 0-37 and TCM8002:
•
o
•
•

Three digital-to-analog converters
An analog-to-digital converter
Two timers
110 expansion

overall description
The following paragraphs detail the various function of the TCM801 0-37 and TCM8002 chip set when used in
this application.
TCM8010-37 transmit path
The inputs to the microphone amplifiers are MIC1 and MIC2. MIC1 could be used for the internal microphone
and MIC2 for accessories (a hands-free unit, for example). the TCM8010-37 is designed for single-supply
operation. REF is provided to bias the noninverting inputs of the microphone amplifiers, M1 P and M2P. The
wide-band data to be transmitted is input as a digital signal to TXDA. The TCM801 0-37 then filters the signal
and provides a level trim for it.
The TCM8002 produces a digitally-filtered signal, phase locked to the received SAT. This is then connected to
the input TXSA of the TCM801 0-37, which filters and provides level adjustment for the digital signal. The output
from the TCM8010-37 is at TXO and should be connected to the modulator in the RF sectiQn. The voice,
wide-band data, and SAT signal levels are programmable, eliminating the need for external adjustments.
TCM8010-37 receive path
The output from the FM demodulator/discriminator should be connected to the receive audio input (RXIN) of
the TCM8010-37. Two audio outputs are provided at SP1 and SP2. These outputs can be configured to be two
separate outputs, with one driving the telephone earpiece and the other for test or accessories, a hands-free
unit for example, or optionally the outputs can be configured to provide a differential output to increase the
maximum level.
The TCM801 0-37 filters and converts the received wide-band data to a digital signal and outputs this at RXDO
for connection to the TCM8002. The received SAT signal is filtered and converted to a digital signal. It is then
made available at RXSO for transmission to the TCM8002.
TCM8010-37 digital-to-analog converters
Three uncommitted 8-bit DACs are included in the TCM801 0-37 (DAC1 OUT, DAC20UT, and DAC30UT). One
can be used for power control of the RF transmit amplifier. The other two could be used to provide adjustment
voltages for the RF stage such as calibrating the temperature-compensated crystal oscillator (TCXO) and
trimming the first intermediate frequency (IF) stage.
TCM8010-37 analog-to-digital converter
Two multiplexed inputs to an ADC included in the TCM801 0-37 are provided (ADCIN 1 and ADCIN 2). Possible
uses are to measure battery voltage (using a potential divider) or received-signal-strength indicator (RSSI)
voltage.

•
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TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

APPLICATION INFORMATION
TCM8002 transmit path
The data encoder includes all the necessary formatting for transmission on the control and voice channels. This
digital signal is output at TXOUT. The received SAT digital signal is connected to TCM8002 SATIN and then the
signal is recovered from the noise before being measured and regenerated. The digital output signal appears
at TCM8002 SATOUT.
TCM8002 receive path
The received digital data Signal is connected to RXIN for the control-and-voice channel data-recovery circuit.
The data is then majority-voted and error-corrected. Finally, an interrupt is generated to signal the
microcontroller that there is received data available.
TCM8002 timers
A watchdog timer is provided that can reset the microcontroller in the telephone if a fault occurs. This is a
requirement of both the AMPS and TACS systems.
An uncommitted programmable 8-bit timer is also available with an output labeled TMZERO that pulses low
when the count reaches zero.
TCM8002 110 expansion
Twenty programmable I/O lines are provided for the telephone microcontroller. These are individually
bit-programmable as outputs or inputs with optional current source pullups.
An intelligent interface to the TCM801 0-37 audio processor provides an automatic audio-mute function when
wide-band data is being transmitted or received.
TCM8002 and TCM8010-37 clock and control
Both the TCM8002 and TCM8010-37 are connected to the microcontroller through the serial interface (CS,
DCLK, DATAIN, DATAOUT, INTERRUPT). The TCM8002 can be programmed to generate interrupts when
events such as received data available or the counter/timer reaching zero state occurs.
A low-power crystal oscillator is integrated into the TCM8002, and the CLKOUT output is provided for
connection to the TCM801 0-37.

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5-47

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

APPLICATION INFORMATION

Receive Audio Input {RXAUDIO

--1

TCM8010
RXIN

SPl
TXVO
SP2

C6
CIN

Transmit Voice Inputs

rCl~

Ml0
M1N
R4

MIC2~

M20

CI)

CS
DCLK

DATAIN

:s...
UI
UI
CI)

DATAOUT

CS
DCLK
DATAIN
DATAOUT

INTERRUPT

INTRPT

RESET

WATCHDOG
TIMER

RESET

WDOUT
TMZERO

XTALl

RXVI

CVE

M1P

M2P

CMPR

REF

Cl0

VMID

POUT

SATOUT

TXSA

RXIN

RXDO

ADCl

ADCINl

TXOUT

TXDA

ADC2

ADCIN2

DACl

DAC10UT

HCLK

DCLK

DAC2

DAC20UT

HDATA

DATA

DAC3

DAC30UT

HCS

CLKOUT
RFEN

Analog I/O

XTI

1------------

RFEN }

PIOl (0-7)

PI02 (0-7)

PI03 (0-3)

Transmitter Enable

I/O Expansion

RCCBUSY/P04(4)
1----+-.---1 XTAL2
RAEN/P04(6)

1------------

TAEN/P04(7)

1------------

RCCBUSY/P04(4)
RAEN/P04(6)

Figure 15. Complete Baseband Solution

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INSTRUMENTS
5-48

RXSO

ETC

TXAUDIO} Transmit
Audio Out

SATIN

~
~

LIMIN

TCM8002
u

TXO

CTC

TXVI

~CI)

Cll
EXIN

EXO

RXO

M2N
R6

t-- speakerl} Receive
t-- Speaker2 Voice Output

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TAEN/P04(7)

TCM8010-37
AMPSITACS AUDIO PROCESSOR
SLWS034-JUNE 1996

APPLICATION INFORMATION
external component selection
COMPONENT
DESIGNATION

TYPICAL
VALUE

FUNCTION

47 kn

Recommended minimum value

47 kn

Sets microphone preamplifier number 2 gain ... R4/R3
Recommended minimum value

47 kn

100 kn

Sets microphone preamplifier number 1 gain ... R2/R1

Provides dc bias for the compressor

1 Mn

100 nF

AC couples the input to microphone preamplifier number 1 (MIC 1)

Biasing resistor for crystal oscillator

100 nF

AC couples the input to microphone preamplifier number 2 (MIC 2)

390 nF

10 nF

47pF

Sets the attack and recovery times of the compressor
AC couples the receive audio and data input from the FM demodulator/discriminator
Required for HF stability of the compressor

100 nF

AC couples the output of the selected microphone preamplifier to the compressor input. This is required
because any dc offset would cause linearity errors.

100 nF

AC couples the output of the preemphasis and band-pass filter to the limiter stage to ensure symmetrical
clipping

100 nF

AC couples the output of the compressor to the transmit switch (TXSW). Since this is also the compressor
rectifier input, any dc offset would cause linearity errors.

100 nF

AC decouples the compressor dc feedback

C10

100 nF

AC couples the output from the expander to the receive switch (RXSW)

C11

100 nF

AC couples the input to the expander to remove offsets that would otherwise cause linearity errors at low
signal levels

C12
C13

C14

470 nF

Decouples the resistor divider that produces REF, the input for the VMID generator

C15

100 nF

AC couples the output from the transmit voice, data, and SAT signals to the FM modulator in the RF section

Required when the earpiece drive is single ended (not differential)

C16

330 nF

Sets the attack and recovery times of the expander

C17

470 nF

Provides a low ac impedance reference for the transmit and receive paths

C18

33 pF

C19

33 pF

2.56 MHz

Provides X1 with the required capacitive loading
Provides X1 with the required capacitive loading
Crystal

printed circuit board layout precautions
Resistors R5 and R6 should be placed close to the TCM801 0-37 to minimize stray capacitance between CO
and CVE. Otherwise, compressor gain errors are caused at low signal levels and high frequencies.

suggested trim sequence
The TCM801 0-37 and TCM8002 are designed so that no manual trims are required. All levels can be adjusted
to meet the system requirements and compensate for production tolerances by writing to the digital interface.
The data required can then be stored in a nonvolatile memory by the microcontroller in the telephone. When
the telephone is turned on, an initialization routine can write this calibration data to the TCM801 0-37.
\

~TEXAS

INSTRUMENTS
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5-49

TCM8010·37
AMPSfTACS AUDIO PROCESSOR
SLWS034 - JUNE 1996

APPLICATION INFORMATION
suggested trim sequence (continued)
The suggested sequence of adjustments for trimming is detailed below.
To begin the transmission portion of the trim sequence:
Step 1.

TXTRIM
a.

Step 2.

Step 3.

Set the TCM8002 and TCM801 0-37 to transmit signaling tone.

Adjust to set the frequency deviation to that required by either the AMPS or TACS
system.

TXSAT
a.

Turn the signaling tone off and turn on the SAT path. Input a 6-kHz signal to RXIN.

Adjust < SAT3 - SAT0> to give the required frequency deviation.

MICTRIM
a.

Step 4.

Step 5.

Set the transmit data trim < DAT2 - DAT0> to nominal = < 100 >.

Mute the signaling tone and SAT.

Inject an audio signal at the desired level into the microphone preamplifier.

Adjust < MICT3 - MICT0> to set the frequency deviation.

LIMITER TRIM
a.

Increase the audio signal level by 20 dB typically.

Adjust < LlM2 - LIMo> to produce the required maximum deviation.

DTMF TRIM
a.

Mute the signaling tone, audio, and SAT.

For TACS, set bit < DTSK> to enable the skew of the levels between the low and high tones.

Turn on the DTMF generator and adjust to give the desired frequency deviation.

Continue with the receive portion of the trim sequence;
Step 6.

RXTRIM
Input a modulated signal to the telephone and adjust to produce the required level at
SP1 and SP2.

Ending with the RF stage:
Step 7.

DACs to trim RF section
Three 8-bit DACs can be used to trim sections of the RF stage using < DACCAD1 - DACADo> to select
the DAC and < DAC7 - DACo> to set the level. < DACX2> sets the range of all three DACs and
< DACON > enables all three outputs when the TCM801 0-37 is in standby.
Typical uses would be RF transmit power control, TCXO trim, and first IF section trim.

~TEXAS

5-50

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8010-37
AMPSfTACS AUDIO PROCESSOR
SLWS034-JUNE 1996

APPLICATION INFORMATION

transmit signal levels
The TCM801 0-37 is designed for signal levels detailed in the following tables for the AMPS and TACS systems.
These tables suggest levels for both the transmitted and received audio, SAT, and DATA signals.

AMPS mode
SIGNAL
Design level
Peak voice level
SAT

PEAK FREQUENCY DEVIATION
(kHz)

LEVEL AT TXO

UNIT

400

1697.1

mVrms
mVpp

100

mVrms

1131.4

mVpp

DTMF low tone, 697 Hz

3.1365

156.8

mVrms

DTMF high lone, 1477 Hz

6.6465

332.3

mVrms

LEVEL AT TXO

UNIT
mVrms

DATA

TACS mode
SIGNAL

PEAK FREQUENCY DEVIATION
(kHz)

Design level

5.7

356.3

Peak voice level

9.5

1697.6

mVpp

SAT

1.7

106.3

mVrms

DATA
DTMF low lone, 697 Hz
DTMF high lone, 1477 Hz

6.4

1131.5

mVpp

1.2 max

mVrms

3.19 max

199.4

mVrms

LEVEL AT RXIN

UNIT

receive signal levels
AMPS mode
SIGNAL
Design level

PEAK FREQUENCY DEVIATION
(kHz)
8

400

1697.1

mVpp

SAT

100

mVrms

DATA

1131.4

mVpp

LEVEL AT RXIN

UNIT
mVrms

Peak voice level

mVrms

TACS mode
SIGNAL

PEAK FREQUENCY DEVIATION
(kHz)

Design level

5.7

356.3

Peak voice level

9.5

1697.6

mVpp

SAT

1.7

106.3

mVrms

DATA

6.4

1131.5

mVpp

•
TEXAS
INSTRUMENTS
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5-51

5-52

TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

•
•
•
•
o

TACS and AMPS Operation
Integrated RX and TX Voice Filters
Integrated RX and TX Data Filters
RX and TX Narrow-Band SAT Filters
RX Data Recovery Comparator

FR PACKAGE
(TOP VIEW)

zo..oo

g:-:.

RXO
11

IIII EXIN ETC

/13

I
Cfl

I I
RXTRIM hi Deemphasis (-J
t1

RXIN 10

±4 dB

-6 dB

-u

--I

I I
Expander

~SP1

~ ~ '---

Volume
Control
± 15 dB

RXSW

18 SP2

REF
Data
Comparator

VMID
"U

a
~

o~ .....

~Z~-;-

ADC1 22
ADC2 23

~m(/)

RXSAT
Filter"

~(/)

DCLK

~ Control
Digital 1-/ Control Bits

CS 27

(fJ

....
01

SAT
Comparator

<.n

RXSO

DGTL VDD

r-I

'---

TXSAT
Filter
±2dB

SATSW

DTMF
Generator

~ DAC1
3

0>
01

TXSA ~
TXDA 24

...------II

TX Data
Filter
WB

Preemphasis
6dB

Limiter

TXVO

POUT

5
LlMIN

8-Bit
DACS

~ DAC2
30 DAC3

0
-0

en
en
0
:a

s:
OJ

ADC

:t>0
C
C

m
m

(")

20 RXDO

ene»

~~
O~
en en

0
0

DATA

-OS

m
<
Ui
m

~~
~~~
~C:><
~~;l>

~
+>

I LSSW'---J " "

ANLG VDD

VSS

»-1
sO

0
0
m

TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

Terminal Functions
TERMINAL
NAME

NO.

ADC1-ADC2

22,23

ANLG VDD

DESCRIPTION

VO
I

ADC input 1 and 2 (analog)
Analog positive supply

CIN

Compressor input (analog)

CMPR

Compressor rectifier input (analog)

Compressor output, ac coupled to CMPR and to TXVI (analog)

Serial interface chip select, active low (digital)

CTC

Compressor time constant (analog)

CTI

Call tone input (analog and digital)

CVE

Compressor virtual ground (analog)

DAC1-DAC3
DATA

28,29,30

DAC outputs (analog)

I/O

Serial interface data signal (digital)

Serial interface clock signal (digital)

DCLK

DGTLVDD

ETC

EXIN

Expander input (analog)

EXO

Expander output, ac coupled to RXVI (analog)

LlMIN

Limiter input (analog)

Microphone preamplifer 1 output (analog)

43,44

Microphone preamplifier 1 differential inputs (analog)

Microphone preamplifer 2 output (analog)

M2P/N

1,2

Microphone preamplifier 2 differential inputs (analog)

POUT

Preemphasis output, ac coupled to LlMIN (analog)

M10
M1P/N
M20

REF

Digital positive supply
Expander time constant (analog)

Midrail reference - decouple to V ss with external capacitor

RXDO

Receive section data output (digital)

RXIN

Receive section input (analog)

RXO

Receive section deemphasis voice filter output (analog)

RXSO

Receive section supervisory audio tone (SAT) output (digital or analog)

RXVI

Voice input to volume control stage (analog)

SP1/2

17,18

Speaker outputs 1 and 2 (analog)

TXDA

Transmit data filter input (digital or analog)
Transmit section output (analog)

TXSA

TXVI

Input to TX voice-path output stages (analog)

TXVO

Transmit voice input stage output, ac coupled to CIN (analog)

TXO

VMID

VSS

XTI/XTO

32,33

Transmit SAT input (digital or analog)

Buffered midrail voltage - decouple to V ss with external capacitor
Negative supply (0 V)
Crystal oscillator and clock recovery inputs

~TEXAS

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5-55

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

absolute maximum ratings over operating free-air temperature ranget
Supply voltage range, Voo (see Note 1) .............................................. -0.3 V to 7 V
Input voltage, VI (any pin) ............................................... VSS - 0.3 V to Voo + 0.3 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Continuous total power dissipation at (or below) TA = 25°C ................................... 893 mW
Storage temperature range, Tstg ................................................... -65°C to 150°C

recommended operating conditions
Supply voltage, OGTL VOO and ANLG VOO

MIN

NOM

MAX

4.5

5.5

Low-level input voltage, VIL
Operating virtual junction temperature, T J

V
V

0. 8V OO

High-level input voltage, VIH

UNIT

-30

0.8

°C

electrical characteristics over recommended operating virtual junction temperature range,
Voo =5 V, fxtal =2.56 MHz
TYP

MAX

Standby mode, OACs off

1.7

Standby mode, OACs on

1.4

MIN

PARAMETER

100(A)

Analog supply current

Operating mode

Standby mode

160

1000

Operating mode

0.5

1.7

Including OTMF generator

100(0)

Oigital supply current

AOC operating
REF

Midsupply reference voltage

Operating mode

2.4

2.5

2.6

VMIO

Buffered midsupply reference voltage

Operating mode

2.4

2.5

2.6

MIN

TYP

MAX

UNIT

IlA
mA

analog inputs
PARAMETER
II

Input current at M1 P, M1 N, M2P, M2N, AOC1, AOC2, CTI
/Input impedance at RXIN, RXVI, LlMIN, TXSA, TXOA

IlA

100

I Input impedance at EXIN, CIN, CMPR, TXVI

UNIT

kf!

digital interface
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

IIH

High-level input current

VI =5V

IlL

Low-level input current

VI= OV

1
1

fCLK

Serial clock frequency, OCLK input

VOH

High-level output voltage

IOH = 500 IlA

VOL

Low-level output voltage

IOL= 500 IlA

•
TEXAS
INSTRUMENTS
5-56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0. 9V OO
0. 1VOO

UNIT
IlA
MHz
V

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

transmit path electrical characteristics
input stage gain M10/M20 to TXVO, Voo

=5 V

PARAMETER

TEST CONDITIONS

MIN

MAX

-0.5

0.5

MICTRIM = <1111 >

3.3

4.3

MICTRIM = < 0000>

-4.8

-3.8

0.38

0.68

Gain

MICTRIM = < 1000> (see Note 2)

MICTRIM positive range
MICTRIM negative range
MICTRIM step size
PreampCMRR

Distortion

VI= 1 V,

f= 1 kHz

MICSW isolation

VI = 100mV,

f= 1 kHz

UNIT

dB
0.5%
dB

NOTE 2: The control bits associated with a block or function are shown in < >.

compressor CIN to CO, VOO

=5 V
TEST CONDITIONS

MIN

TYP

MAX

103

127

VI = Vref + 2 dB to Vref -18 dB

-0.Q1

±0.5

VI = Vref - 18 dB to Vref -48 dB

-0.16

±1

k11

PARAMETER

Unity gain levelt
Relative linearity error

RCOMP compressor resistance

UNIT

t This parameter becomes Vref for the relative-linearity-error test conditions.

output stage TXVI to TXO, Voo

=5 V
TEST CONDITIONS

PARAMETER

TXTRIM step size

MIN

MAX

UNIT

0.16

0.36

TXTRIM positive range

TXTRIM = <11111 >

3.5

4.5

TXTRIM negative range

TXTRIM = <00000>

-4.8

-3.8

TXATTEN step size
TXATTEN range

output stage limiter TXVI to TXO, Voo

MIN

MAX

UNIT

1900

mVp-p

=5 V

PARAMETER

TEST CONDITIONS

Maximum output signal

TXVI = 316 mV,
f = 300 Hz to 25000 Hz,

Distortion

f = 1 kHz, level at TXO = 2/3 x level
measured in previous test, LIM = < 110>

LIM =<110>

Trim step size, analog test mode A, output at RXDO

TXVI =316mV

0.8

1.2

Trim positive range, analog test mode A, output at RXDO

LIM = <111 >

2.5

3.5

Trim negative range, analog test mode A, output at RXDO

LIM = <000>

-4.5

-3.5

•
TEXAS
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5-57

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

output stage frequency response TXVI to TXO, Voo

=5 V

PARAMETER

TEST CONDITIONS

MIN

f < 200 Hz

O-dB reference at f = 1 kHz,
TXVI = 26 mV

Frequency response

MAX

UNIT

-20

f = 300 Hz

-13.46

-9.46

f = 500 Hz

-9.02

-5.02

f = 2000 Hz

3.02

7.02

f = 2500 Hz

4.96

8.96

f = 3000 Hz

4.96

10.54

f = 5900 Hz

-35

f = 6000 Hz

-35

overall transmit path electrical characteristics M10/M20 to TXO, TXATT

=<00>, VDD =5 V

TEST CONDITIONS

MIN

TYP

MAX

Compressor bypass gain

MICT = < 1000>, TXT = < 10000>

10.8

13.0

Output noise, compressor enabled,
M10/M20 = VMID psophometric weighting

RXIN = 400 mY,

f = 1 kHz

Voice mute attenuation

MlO/M20 = 100 mY,

f= 1 kHz

PARAMETER

UNIT
dB

2.3

mVrms

-80

DATA output levels TXDA to TXO, VOO = 5 V
MIN

MAX

UNIT

AMPS

fl = 1O-kHz square wave, amplitude 0 V to 5 V

TEST CONDITIONS

1070

1188

mVp-p

TACS

fl = 8-kHz square wave, amplitude 0 V to 5 V

1070

1188

mVp-p

kHz

14.4

17.6

kHz

PARAMETER
Output level

Frequency response

AMPS
TACS

3 dB relative to 1 kHz,

Analog test mode B

TX data mute attenuation

SAT output levels TXSA to TXO, Voo

=5 V

PARAMETER
Output level

MAX

116

2.3

-2.7

-2.3

0.2

0.4

f < 3 kHz

-35

f = 4.8 kHz

-25

f = 5.1 kHz

-20

-5

0.5

f = 5.94 kHz

-0.5

0.5

f = 6.06 kHz

-0.5

0.5

-5

0.5

f = 7.2 kHz

-20

f> 9 kHz

-35

fl = 6-kHz square wave, amplitude 0 V to 5 V

SAT trim negative range
SAT trim step size

f = 5.8 kHz
O-dB reference at f = 6 kHz,

ISAT= <0>

f = 6.2 kHz

TX SAT mute attenuation

~TEXAS

INSTRUMENTS
5-58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

MIN

TEST CONDITIONS
ISAT = <0>,

SAT trim positive range

Frequency response

TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

SAT output level RXIN to TXO, RXT

=<1000>, SAT =<1000>, TXT =<10000>, Vee =5 V

PARAMETER

TEST CONDITIONS

Output level

ISAT = <1 >,

MIN

Input to RXIN = 6-kHz sine wave, amplitude 600 mV

TYP

MAX

400

receive path electrical characteristics
input stage RXIN to RXO, Vee

=5 V

PARAMETER

MIN

MAX

UNIT

Gain

RXTRIM = < 1000>

TEST CONDITIONS

-6.3

-5.2

RXTRIM positive range

RXTRIM = <1111 >

3.2

4.2

RXTRIM negative range

RXTRIM = <0000>

-4.5

-3.8

0.39

0.69

f <100 Hz

-28

f = 240 Hz

12.9

RXTRIM step size

f = 300 Hz
O-dB reference at f = 1 kHz,
RXIN =400 mV

Frequency response

f = 400 Hz

7.5

8.5

f = 2400 Hz

-8.2

-7.1

f = 3000 Hz

-12

-9

-40

UNIT

f > 5900 Hz

expander EXIN to EXO, Vee

=5 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

100

130

EXIN = Vref + 9.5 dB to Vref -2.8 dB

-0.3

±1

EXIN = Vref -2.8 dB to Vref -23.8 dB

-0.8

±2

71.6

UNIT

Unity gain level = Vref t
Relative linearity error

37.5

REXP expander resistance

t This parameter becomes Vref for the relative-linearity-error test conditions.

output stage
PARAMETER

Volume control

MIN

MAX

Gain RXVI to SP1/SP2

VOL = <1000>

TEST CONDITIONS

0.5

1.5

Positive range

VOL= <1111 >

Negative range

VOL= <0000>

-16.5

-15.5

1.75

2.25

Step size
CTI input

Gain to SP1/SP2

Expander bypass gain from RXIN to SP1/SP2

VOL = <1000>

VOL= <1000>

-5.5

-4

Output load at SP1/SP2
Output voltage at SP1/SP2

RL= 500n

Distortion at SP1/SP2, expander enabled

RXIN = 400 mV,

Noise at SP1/SP2, expander bypassed

RXIN = VMID, psophometric weighting

Voice mute attenuation

RXIN = 400 mV,

f= 1 kHz,

500

2.5

Vp-p

No load

f = 1 kHz

2%
3

mV
dB

RX DATA comparator RXIN to RXDO, Vee = 5 V
PARAMETER

TEST CONDITIONS

Must-detect level
Must-not-detect level
Output duty cycle

MIN

MAX

210
f = 4 kHz, 5 kHz,
8 kHz, and 10kHz

40
RXIN = 900 mV peak to peak

47.5%

UNIT
mVp-p

52.5%

•
TEXAS
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5-59

TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

RX SAT frequency response RXIN to RXSO, SATDIG

=<1 >, Voo =5 V
MAX

UNIT

f < 3 kHz

-35

=4.8 kHz
f =5.1 kHz
f =5.8 kHz
f =5.94 kHz
f =6.06 kHz
f =6.2 kHz
f =7.2 kHz

-25

-19

-5

0.5

-0.5

0.5

-0.5

0.5

-5

0.5

-20

-35

TEST CONDITIONS

PARAMETER

MIN

O-dB reference at f

Frequency response

=6 kHz

1> 9 kHz

RX SAT comparator RXIN to RXSO, SATDIG

=<0>, Voo =5 V
TEST CONDITIONS

PARAMETER

Must-detect level

= 6 kHz

MIN

TYP

MAX

miscellaneous block electrical characteristics
digital-to-analog converters DAC1, DAC2, and DAC3
PARAMETER

Output voltage at code 255

TEST CONDITIONS

MIN

=<1 >
DACX2 =<0>

VDD-130

DACX2

Output voltage at code 255

TYP

UNIT

MAX

mV
VDD/2 + 100

VDD/2 -100

Differential nonlinearity (codes 5 - 250)

0.3

LSB

Integral nonlinearity (codes 5 - 250)

0.3

LSB

Zero code offset

analog-to-digital converter, DCLK =160 kHz, Voo

=5 V
TEST CONDITIONS

PARAMETER

nonlin~arity

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MAX

2.6

0.5

Clock rate (DCLK)

5-60

TYP

0.5

Differential nonlinearity
Integral

MIN

2.3

Full scale for inputs ADC1, ADC2, and VMID

UNIT

LSB

200

kHz

TCM8010-50
AMPSrrACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

DTMF generator transmit levels at TXO, TXTRIM
PARAMETER

=<10000>, Voo =5 V

DTTR

697-Hz tone, low tone

TEST CONDITIONS

AMPS mode

1477-Hz tone, high tone

<0100>

697-Hz tone, low tone

TACSmode

1477-Hz tone, high tone

DTMF trim steps

MIN

TYP

MAX

UNIT

108

153

164.9

300

340

348.6

140

175

190

<0000> - <0001 >

0.4

<0001> - <0010>

0.4

<0010> - <0011 >

0.4

<0011> - <0100>

0.5

<0100> - <0101 >

0.5

<0101> - <0110>

0.6

<0110> - <0111 >

0.6

dB
dB

<0111> - <1000>

0.7

< 1000> - <1001 >

0.7

< 1001> - < 1010>

0.8

<1010>-<1011>

0.9

<1011>-<1100>

1.0

<1100> - <1101 >

1.1

<1101> - < 1110>

1.3

<1110> - <1111 >

1.5

Positive range

<0100> -<1111 >

7.1

9.8

12.1

Negative range

<0100> - <0000>

-2.7

-1.9

-1

1.85

2.2

Skew, change in level of high tone

<0100>

Distortion products

<0100>

DTMF generator receive levels at SP1 and SP2, DTTR

1.3
Relative to low tone

-30

=<0100>, VOL =<1000>, Voo =5 V

PARAMETER

TEST CONDITIONS

All tones
Distortion products

MIN

MAX

AMPS mode

TACS mode

-40

Relative to low tone

UNIT

~TEXAS

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5-61

TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

TYPICAL CHARACTERISTICS
TX VOICE FREQUENCY RESPONSE

TX PASS-BAND DETAIL

I
I:

:EC.
E

-10
-10

-20

10000
f - Frequency - Hz

-25

-25
1000

-20

>
ct

-30
1000

100000

1"'1

10000

100000

f - Frequency - Hz

Figure 10

Figure 9
COMPRESSOR LINEARITY

EXPANDER LINEARITY

0.5
0.4

0.8

0.3

0.6

0.2

III
"0

0.1

:E
III
III
I:

::i

t.,.......- ~

0
-0.1 P' . /

III
"0

:E
III
III
I:

0.2
0
-0.2

::i

-0.2

-0.4

-0.3

-0.6

-0.4
-0.5
-50

0.4

r--

j....--"

-0.8
-40

-30

-20

-10

Input Step - dB

-1
-30

-25

-20

-15 -10
-5
Input Step - dB

Figure 12

Figure 11

~TEXAS

INSTRUMENTS
5-64

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

APPLICATION INFORMATION

analog cellular telephone baseband solution
The TCM8002 and TCM801 0-50 chip set provides a complete solution to the audio and data filtering, decoding,
and encoding required in a cellular telephone for the AMPS or TACS systems. The applications-circuit
schematic is shown in Figure 13 and demonstrates that a minimum of external components is required.
The following extra functions are included in the TCM801 0-50 and TCM8002:
•
o
o
•

Three digital-to-analog converters
Analog-to-digital converter
Two timers
I/O expansion

overall description
The following paragraphs detail the various function of the TCM801 0-50 and TCM8002 chip set when used in
this application.

TCM8010-50 transmit path
The inputs to the microphone amplifiers are MIC1 and MIC2. MIC1 could be used for the internal microphone
and MIC2 for accessories (a hands-free unit). The TCM801 0-50 is designed for single-supply operation. REF
is provided to bias the noninverting inputs of the microphone amplifiers, M1 P and M2P. The wide band data to
be transmitted is input as a digital signal to TXDA. The TCM801 0-50 then filters and provides a level trim for
the signal.
The TCM8002 produces a digitally-filtered signal, phase locked to the received SAT. This is then connected to
the input TXSA of the TCM801 0-50, which filters and provides level adjustment for the digital signal. The output
from the TCM8010-50 is at TXO and should be connected to the modulator in the RF section. The voice,
wideband data, and SAT signal levels are programmable, eliminating the need for external adjustments.

TCM8010-50 receive path
The output from the FM demodulator/discriminator should be connected to the receive audio input (RXIN) of
the TCM801 0-50. Two audio outputs are provided at SP1 and SP2. These can be configured to be two separate
outputs, with one driving the phone earpiece and the other for test or accessories (a hands-free unit) for
example, or optionally can be configured to provide a differential output to increase the maximum level.
The TCM801 0-50 filters and converts the received wideband data to a digital signal and outputs this at RXDO
for connection to the TCM8002. The received SAT signal is filtered and converted to a digital signal. It is then
made available at RXSO for transmission to the TCM8002.

TCM8010-50 digital-to-analog converters
Three uncommitted 8-bit DACs are included in the TCM801 0-50 (DAC1 OUT, DAC20UT, and DAC30UT). One
can be used for power control of the RF transmit amplifier. The other two could be used to provide adjustment
voltages for the RF stage such as calibrating the temperature-compensated crystal oscillator (TCXO) and
trimming the first intermediate frequency (IF) stage.

TCM8010-50 analog-to-digital converter
Two multiplexed inputs to an ADC included in the TCM801 0-50 are provided (ADCIN 1 and ADCIN 2). Possible
uses are to measure battery voltage (using a potential divider) or received-signal-strength indicator (RSSI)
voltage.

~TEXAS

INSTRUMENTS
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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

TCM8002 receive path
The received digital data signal is connected to RXIN for the control-and-voice channel data-recovery circuit.
The data is then majority voted and error corrected. Finally, an interrupt is generated to signal to the
microcontroller that there is received data available.

TCM8002 timers
A watchdog timer is provided that can reset the microcontroller in the telephone if a fault occurs. This is a
requirement of both the AMPS and TACS systems.
An uncommitted programmable 8-bit timer is also available with an output labelled TMZERO that pulses low
when the count reaches zero.

TCM8002 110 expansion
Twenty programmable I/O lines are provided for the telephone microcontroller. These are individually
bit-programmable as outputs or inputs with optional current source pullups.
An intelligent interface to the audio processor (TCM801 0-50) provides an automatic audio-mute function when
wideband data is being transmitted or received.

TCM8002 and TCM8010-50 clock and control
Both the TCM8002 and TCM8010-50 are connected to the microcontroller through the ::;erial interface (CS,
DCLK, DATAIN, DATAOUT, INTERRUPT). The TCM8002 can be programmed to generate interrupts when
events such as RX data available (data received) or the counter/timer reaching zero state occurs.
A low-power crystal oscillator is integrated into the TCM8002, and the CLKOUT output is provided for
connection to the TCM801 0-50.

~TEXAS

INSTRUMENTS
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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

APPLICATION INFORMATION

Receive Audio Input {RXAUDIO

--1

TCM8010
RXIN

SP1
TXVO
SP2

C6
CIN

Transmit Voice Inputs

EXIN

M1N

TXO

R4
M20

ETC

M2N

EXO

CTC

RXVI

CVE

M1P

M2P

CMPR

REF

TXVI

CII

CS
DCLK

()

DATAIN

CS
DCLK
DATAIN

CII

DATAOUT

C15
C16

r--

TXAUDIO} Tran.smit
Audio Out

VMID

POUT

C17

SATIN

RXSO

SATOUT

TXSA

RXIN

RXDO

ADC1

ADCIN1

TXOUT

TXDA

ADC2

ADCIN2
DAC10UT

I/)
I/)

Voice Output

LIMIN

TCM8002

~CII

Speaker2

C10

tC11

M10

MIC2~

t-- speak..' } Recelve
.

RXO

fC'~

C13
C12

INTERRUPT

INTRPT

HNCS

DAC1

RESET

HCLK

DCLK

DAC2

DAC20UT

HDATA

DATA

DAC3

DAC30UT

e
u

WATCHDOG
TIMER

WDOUT
TMZERO

XTAL1

CLKOUT

Analog 1/0

XT1

RFEN

RFEN} Transmitter Enable

PI01 (0:7)

PI02(0:7)

PI02 (0:7)

PI03(0:3)

PI03 (0:3)
1/0 Expansion

RCCBUSY/PO(4)

XTAL2
RAEN/P04(6)

RAEN/P04(6)

TAEN/P04(7)

Figure 13. Complete Baseband Solution

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-67

TCM8010-50
AMPSrrACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

APPLICATION INFORMATION
external component selection
COMPONENT
DESIGNATION

TYPICAL
VALUE

FUNCTION

47kn

Microphone preamplifier number 1 gain

47kn

Recommended minimum value

47kn

Microphone preamplifier number 2 gain

47kn

Recommended minimum value

100 kn

=R2IR1
=R4/R3

Provides dc bias for the compressor

1 Mn

100 nF

AC couples the input to microphone preamplifier number 1 (MIC 1)

Biasing resistor for crystal oscillator

100 nF

AC couples the input to microphone preamplifier number 2 (MIC 2)

390 nF

10nF

47pF

Determines the attack and recovery times of the compressor
AC couples the receive audio and data input from the FM demodulator/discriminator
Required for HF stability of the compressor

100 nF

AC couples the output of the selected microphone preamplifier to the compressor input. This is required
because any dc offset would cause linearity errors.

100 nF

AC couples the output of the preemphasis and bandpass filter to the limiter stage to ensure symmetrical
clipping

100nF

AC couples the output of the compressor to the transmit switch (TXSW). Since this is also the compressor
rectifier input, any dc offset would cause linearity errors.

100nF

AC decouples the compressor dc feedback

C10

100 nF

AC couples the output from the expander to the receive switch (RXSW)

C11

100nF

AC couples the input to the expander to remove offsets that would otherwise cause linearity errors at low
signal levels

C12

C13

C14

470nF

Decouples the resistor divider that produces REF, the input for the VMID generator

C15

100 nF

AC couples the output from the transmit voice, data, and SAT signals to the FM modulator in the RF section

Required when the earpiece drive is single ended (not differential)

C16

330 nF

Determines the attack and recovery times of the expander

C17

470nF

Provides a low ac impedance reference for the transmit and receive paths

C18

33pF

C19

33pF

2.56 MHz

Provides X1 with the required capacitive loading
Provides X1 with the required capacitive loading
Crystal

printed circuit board layout precautions
Resistors R5 and R6 should be placed close to the TCM801 0-50 to minimize stray capacitance between CO
and CVE. Otherwise, compressor gain errors are caused at low Signal levels and high frequencies.

suggested trim sequence
The TCM801 0-50 and TCM8002 are designed so that no manual trims are required. All levels can be adjusted
to meet the system requirements and compensate for production tolerances by writing to the digital interface.
The data required can then be stored in a nonvolatile memory by the microcontroller in the telephone. When
the telephone is turned on, an initialization routine can write this calibration data to the TCM801 0-50 .

•
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TCM8010-50
AMPSrrACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

APPLICATION INFORMATION
suggested trim sequence (continued)
The suggested sequence of adjustments for trimming is detailed below.

transmit
Step 1.

TXTRIM
d.

Step 2.

Step 3.

Set the TCM8002 and TCM801 0-50 to transmit signaling tone.

Adjust to set the frequency deviation to that required by the system, AMPS orTACS.

TXSAT
a.

Turn the signaling tone off and turn on the SAT path. Input a 6-kHz signal to RXIN.

Adjust to give the required frequency deviation.

MICTRIM
a.

Step 4.

Step 5.

Set the TX data trim < DAT2 - DAT0> to nominal = < 100 >.

Mute the Signaling tone and SAT.

Inject an audio signal at the desired level into the microphone preamplifier.

Adjust to set the frequency deviation.

LIMITER TRIM
a.

Increase the audio signal level by 20 dB typically.

Adjust < L1M2 - LIMo> to produce the required maximum deviation.

DTMF TRIM
a.

Mute the Signaling tone, audio, and SAT.

For TACS, set bit < DTSK> to enable the skew of the levels between the low and high tones.

Turn on the DTMF generator and adjust to give the desired frequency deviation.

receive
Step 6.

RXTRIM
Input a modulated signal to the telephone and adjust < RXT3 - RXT0> to produce the required level at
SP1 and SP2.

RF stage
Step 7.

DACs to trim RF section
Three 8-bit DACs can be used to trim sections ofthe RF stage using to select
the DAC and to set the level. sets the range of all three DACs and
< DACON > enables all three outputs when the TCM801 0-50 is in standby.
Typical uses would be RF transmit power control, TCXO trim, and first IF section trim.

The TCM801 0-50 is designed for signal levels detailed in the following tables for AMPS and TACS systems.
These tables suggest levels for both the transmitted and received audio, SAT, and DATA signals .

•
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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

APPLICATION INFORMATION

transmit signal levels
AMPS mode
SIGNAL
Design level
Peak voice level

PEAK FREQUENCY DEVIATION
(kHz)

LEVELATTXO

400

1697.1

UNIT
mVrms
mV peak to peak
mVrms

SAT

100

DATA

1131.4

mV peak to peak

DTMF low tone, 697 Hz

3.1365

156.8

mVrms

DTMF high tone, 1477 Hz

6.6465

332.3

mVrms

LEVELATTXO

UNIT

TACS mode
SIGNAL

PEAK FREQUENCY DEVIATION
(kHz)

Design level

5.7

356.3

mVrms

Peak voice level

9.5

1697.6

mV peak to peak

SAT

1.7

106.3

mVrms

DATA

6.4

1131.5

mV peak to peak

DTMF low tone, 697 Hz
DTMF high tone, 1477 Hz

1.2 max

mVrms

3.19 max

199.4

mVrms

LEVEL AT RXIN

UNIT

receive signal levels
AMPS mode
SIGNAL
Design level
Peak voice level

PEAK FREQUENCY DEVIATION
(kHz)
8

400

1697.1

mVrms
mV peak to peak

SAT

100

DATA

1131.4

mV peak to peak

LEVEL AT RXIN

UNIT

mVrms

TACS mode
SIGNAL

PEAK FREQUENCY DEVIATION
(kHz)

Design level

5.7

356.3

mVrms

Peak voice level

9.5

1697.6

mV peak to peak

SAT

1.7

106.3

mVrms

DATA

6.4

1131.5

mV peak to peak

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8010-50
AMPSrrACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
general
The TCM801 0-50 consists of a number of functional blocks and is controlled by the digital interface. The control
bits associated with each block are shown in the angled brackets symbol < >. In standby mode , the
receive data path from RXIN to RXDO is on and the DACs can be on or off as required. All other parts of the
device, including the crystal oscillator, are off. When in the active mode, the receive and transmit paths and the
OAC blocks are continuously on, and the DTMF and AOC blocks are turned on as required.
Control bits set the TCM8010-50 for the desired system (AMPS or TACS).

transmit path
The transmit path on the TCM8010-50 consists of a number of functional blocks, which are described in the
following paragraphs.

mic inputs
Voice signals are input via a pair of microphone preamplifiers, which are stable for gains between 0 dB and
20 dB. All voice-path specifications are given with the preamplifiers configured as unity-gain inverting amplifiers.
In standby mode, the bias to the microphone preamplifiers is turned off and the outputs M1 and M20 are in
the high-impedance state.

MICSW
The MICSW block is a 2-input switch that selects either of the preamplifier outputs, and is under control of the
digital interface «MICSEL».

MICTRIM
The MICTRIM block provides gain adjustment to compensate for differing microphone sensitivities
«MICT3 - MICTO»' A second-order Sallen-Key low-pass filter is incorporated in this block to provide
anti aliasing for the TX voice signal.

compressor
The compressor provides a 1-dB change in output signal level for a 2-dB change in input level over an operating
input range of 50 dB. The unity-gain point, Vref, is proportional to the value of Voo (see the compressor table
in the transmit path electrical charactistics). Attack time is measured by increasing the input-signal amplitude
by a 12-dB step relative to 13 mV rms and is defined as the time required for the output envelope to reach 1.5
times the final steady-state level. Recovery time is measured by reducing the input signal amplitude by a 12-dB
step to 13 mV rms and is defined as the time required for the output envelope to settle to 0.75 times the final
steady-state level.
The attack and recovery times are determined by an internal resistor (RCOMP) and the external capacitor, CCTC,
connected betw!3en CTC and 0 V, VSS'
Attack time

= 0.151

x CCTC x RCOMP

Recovery time = 0.693 x CCTC x RCOMP

TXSW
This block is a 3-input switch that selects either the compressor output, compressor bypass (for testing), or the
output of the DTMF generator. TXSW is controlled by .

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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
TXATTEN
The output of TXSW passes through the TXATTEN block, which provides four levels of attenuation.

preemphasis
The output from TXATTEN is connected to the preemphasis block, which provides the necessary 6 dB per
octave increase in gain with frequency by using a second-order filter. Also included in this block is an
eighth-order band-pass filter function with a 300-Hz to 3-kHz passband. The nominal gain of this stage is 6 dB
at 1 kHz and its output is routed to the POUT terminal.

limiter
The limiter block limits the maximum output under overload Signal conditions, and the limit level is adjustable
under control of the serial interface < LlM2 - LIMo >. The limiter range is designed to allow the TX path distortion
and maximum signal output specifications to be achieved at a single limiter-adjustment code. The output of the
preemphasis block is ac coupled (via an external capacitor) into the LlMIN terminal to ensure symmetrical
limiting.

low-pass filter
The limiter output is processed by the low-pass filter block, which is a fourth-order low-pass filter plus
second-order equalizer, to remove excessive harmonics produced by the limiting process.

TXSUM
This block can sum together or mute any of its three inputs (SAT, data, and voice) under the control of the
< TXSAT, TXDAT, TXVOX> bits, respectively.

TXTRIM
The TXTRIM gain-adjust block can be used to compensate for different modulator sensitivities using bits
. A continuous-time output low-pass smoothing filter is included with a typical cutoff frequency
of 30 kHz.

TX data filter
Transmit data is input to terminal TXDA and is routed to the TX data filter block where the data is first conditioned
by a second-order antialiasing filter before going on to the transmit data filter.
In the AMPS and TAGS modes, the transmit data is a Manchester-encoded digital signal at 10k bitls for AMPS
or 8k bits/s for TAGS. The transmit data filter for these two modes is a fourth-order Butterworth low-pass filter,
with its - 3-dB point switchable between AMPS and TAGS modes.
The filtered AMPS or TAGS wideband-data signal is summed into the transmit signal path in the TXSUM block.

TXSAT filter path - TXSA to TXO
The input to the transmit SAT signal path is determined by the SATSW block, which selects between the TXSA
terminal and the output of the receive SAT filter (RXSAT). The signal is processed by the TXSAT filter block,
which includes an antialiasing filter, a fourth-order narrow-band band-pass filter centered at 6 kHz, and a gain
adjust stage . The output of this block is then applied to an input of TXSUM to be summed into
the voice path when selected.

~TEXAS

INSTRUMENTS
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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION

receive path - voice
The demodulated signal from the receiver is input to the TCM8010-50 at the RXIN terminal. A pair of
loudspeaker drivers are provided, producing output signals on terminals SP1 and SP2, and are capable of
driving 500-Q loads.
RXTRIM
A gain-adjust block, RXTRIM, is provided to allow variations in the receiver FM demodulator/discriminator
characteristics to be accommodated < RXT3 - RXT0>. This block is enabled in both active and standby modes.
A second-order continuous-time filter with a typical cutoff frequency of 30 kHz provides an antialiasing function
for the receive signal path.

deemphasis
The deemphasis filter block exhibits a 6-dB/octave decrease in gain versus frequency characteristic. It also
includes an eighth-order band-pass filter (pass band = 300 Hz to 3 kHz) to separate the received voice signal
from the data and SAT signals. A continuous-time smoothing filter is incorporated at the output, and the output
signal appears at terminal RXO.

expander
I

The expander block provides a 2-dB change in output signal level for a 1-dB change in input level over an
operating input range of 33 dB. The unity-gain level, Vref, is proportional to Voo (see the expander table in the
receiver path electrical charactistics). Attack time is measured by increasing the input signal amplitude by a 6-dB
step relative to 72.5 mV and is defined as the time required for the output envelope to reach 0.57 times the final
steady-state level. Recovery time is measured by reducing the input signal amplitude by a 6-dB step to 72.5
mV and is defined as the time required for the output envelope to settle to 1.5 times the final steady-state level.
The attack and recovery times are determined by an internal resistor, REXP, and the external capacitor, CEXP,
connected to ETC and 0 V, VSS'
Attack time = 0.173 x CETC x REXP
Recovery time = 0.693 x CETC x REXP
RXSW
RXSW is a 4-input switch block that provides a selection between the call-tone input terminal (CTI), the
expander output (externally capacitively coupled to terminal RXVI), the expander-bypass path (for testing), and
the output from the DTMF generator as the input to the volume-control block. The control bits are < RXSW1 and
RXSWa>·
To simplify the connection of a digital signal for a User Alert tone (typically between 200 Hz and 400 Hz), no
internal bias is provided for the CTI input. If an ac-coupled signal is applied to CTI, an external bias resistor
(typical value is 100 kn) is required and should be connected between CTI and VMIO.

volume control
This block provides output level adjustment to implement a user-adjustable level control via control bits
.
LSSW
The loudspeaker control switch block (LSSW) allows selection between either SP1 or SP2 outputs, muting, or
differential drive of both terminals via control bits .

•
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TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
receive path - data/SAT
The demodulated signal from the receiver is input to the TCM8010-50 at the RXIN terminal. This Signal,
containing voice, data, and SAT components, is processed and antialias filtered by the RXTRIM block.
receive data path - data comparator
The signal from RXTRIM is applied to the data comparator block, which has defined threshold levels. The data
signal is Manchester encoded at 10 kbitls for AMPS mode and at 8 kbitls for TACS mode. Detected data appears
at RXDO. This signal path is enabled in the standby mode.
receive SAT path - RX SAT filter
The RX SAT filter block uses a fourth-order Butterworth bandpass filter centered at 6 kHz to separate received
SAT signals from the voice signal. The output of the bandpass filter is routed to an input of the SATSW block
and to the SAT comparator block.
receive SAT path - SATSW
SATSW is a 2-input switch block that selects between the output of the RX SAT filter and an external SAT source
(applied to terminal TXSA) via control bit < ISAT>.
receive SAT path - SAT comparator
The SAT comparator block recovers the SAT signal and has defined hysteresis levels for improved noise
immunity. The output is routed to terminal RXSO. An internal switch, controlled by bit , bypasses the
SAT comparator, applying the output from the RX SAT filter block directly to terminal RXSO.

digital interface
The TCM801 0-50 is controlled by a 3-wire digital interface, consisting of a clock signal (DCLK), a chip select
(CS), and a bidirectional data line (DATA). The logic signal present on DATA is written into the device on the
rising edge of DCLK when CS is low. Serial messages to and from the device contain a read/write bit, an address
field, and a data word. Results from the ADC are read back using the serial interface, and the DCLK signal is
used to drive the converter. Test access to analog and digital sections of the device are provided using the serial
interface.
write operations
A timing diagram for a write operation to the device is shown in Figure 14. In this case, the read/write bit is set
to 1, followed by a 3-bit address word, (A2-AO), and a 1O-bit data word (09-00). Data shifts into the device
on the rising edge of DCLK and is transferred to internal registers on the falling edge of the fourteenth clock pulse
after CS goes low. If CS returns high before this time, no transfer takes place and the input interface is reset.

OCLK

Figure 14. Write-Operation Timing

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INSTRUMENTS
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TCM8010-50
AMPSfTACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION

control words
Table 1 shows control-word and configuration assignments for the device. Table 2 shows control-word
descriptions, Table 3 shows test modes, and Table 4 details DTMF control words.
Table 1. Control-Word and Configuration Assignments
A2

Word 0

STBY

MD1

MOo

ISAT

SATDIG

DACX2

CKSEL

CKRT2

CKRT1

CKRTO

Word 1

TXSW1

TXSWO

TXSAT

TXDAT

TXVOX

TXATI1

TXATIO

DACON

LS1

LSO

Word 2

MICSEL

MICT3

MICT2

MICT1

MICTO

TXT4

TXT3

TXT2

TXT1

TXTO

Word 3

LlM2

LlM1

LIMO

SAT3

SAT2

SAT1

SATO

Word 4

RXT3

RXT2

RXT1

RXTO

RXSW1

RXSWO

VOL3

VOL2

VOL1

VOLO

WordS

DTSK

DTIR3

DTIR2

DTIR1

DTIRO

TEST1

TESTO

Word 6

DACAD1

DACADO

DAC7

DAC6

DACS

DAC4

DAC3

DAC2

DAC1

DACO

Word 7

DTMF3

DTMF2

DTMF1

DTMFO

Table 2. Control-Word Descriptions
DESCRIPTION
Word 0

STBY = Standby select: 0 = Standby, 1 = Active
MD1 - MOO = Mode select: 00 = AMPS, 01 = Undefined, 10 = TACS, 11 = Undefined
ISAT = SAT select: 0 = External, 1 = Internal
SATDIG = Digital/Analog RX SAT: 0 = Digital, 1 = Analog
DACX2 = DAC range select: 0 = 0 - VDD/2, 1 = 0 - VDD
CKSEL = Clock source select: 0 = Oscillator, 1 = Sinusoidal input
CKRT2 - CKRTO = Clock rate select: 000 = 3.S8 MHz, 001 = 7.16 MHz, 010 = 10.74 MHz, 011 = 14.32 MHz, 100 = 2.S6 MHz,
101 = 10.24 MHz, 110 = 12.80 MHz, 111 = 1S.36 MHz

Word 1

TXSW1 - TXSWO = TX Voice select: 00 = Mute, 01 = Compressor O/P, 10 = Compressor bypass, 11 = DTMF
TXSAT = TX SAT enable: 0 = Mute, 1 = Enable
TXDAT = TX Wide band data enable: 0 = Mute, 1 = Enable
TXVOX = TX Voice enable: 0 = Mute, 1 = Enable
TXATI 1 - TXATI0 = TX attenuation: 00 = 0 dB, 01 = 8 dB, 10= dB, 11 = 24 dB
DACON = DACS on select in standby: 0 = Off, 1 = On
LS1 - LSO = Loudspeaker configuration: 00 = Mute, 01 = SP2 enable, 10 = SP1 enable, 11 = Differential

Word 2

MICSEL = Microphone select: 0 = M1, 1 = M2
MICT3 - MICTO = Microphone trim: 0000 = minimum gain, 1111 = maximum gain
TXT4 - TXT0 = TX Deviation trim: 00000 = minimum gain, 11111 = maximum gain

Word 3

LlM2 - LIMO = Deviation limiter adjust: 000 = minimum deviation, 111 = maximum deviation
SAT3 - SATO = TXSAT adjust: 0000 = minimum, 1111 = maximum
DO - 01 = 0, D2 = 1

Word 4

RXT3 - RXTO = RX input adjust: 0000 = minimum, 1111 = maximum
RXSW1 - RXSWO = RX switch control: 00 = CT input, 01 = Expander O/P, 10 = Expander bypass, 11 = DTMF
VOL3 - VOLO = RX path audio volume control: 0000 = minimum, 1111 = maximum

WordS

DTSK = DTMF Skew enable: 0 = disabled, 1 = enabled
DTIR3 - DTIRO = DTMF adjust: 0000 = minimum, 1111 = maximum
TEST 1 - TEST0 = Test mode: (see Table 3)
02 - 04 = 0

Word 6

DACAD1 - DACADO = DAC address: 00 = DAC 1, 01 = DAC 2, 10 = DAC 3, 11 = all DACs

Word 7

DTMF3 - DTMFO = DTMF control: (see Table 4)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

S-7S

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
Table 3. Test Modes (to Word 5)
OUTPUT AT RXDO

OUTPUT AT RXSO

Digital Test

Digital DTMF High Tone

Digital DTMF Low Tone

Analog Test A

Rx Data (analog)

Limiter Output (de)

Analog Test B

Bandgap Output

Tx Data (analog)

Other States

Rx Data (digital)

Rx SAT (digital)

Other States

Digital DTMF High Tone

Digital DTMF Low Tone

Other States

Digital DTMF High Tone

RXSAT (analog)

SATDIG

TEST1

TESTO

MODE

Normal

0
1

Table 4. DTMF Control (to Word 7)
DTMF3

DTMF2

DTMF1

DTMFo

KEY

LOW TONE Hz

HIGH TONE Hz

697

1209

770

1209

852
941

1209

697

1336

770

1336

852

1336

941

1336

697

1477

770

1477

852

1477

941

1477

697

Off

1209

1477

Off

~TEXAS

INSTRUMENTS
5-76

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8010-50
AMPSITACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
read operations
A timing diagram of a read operation, which outputs ADC results from the device, is shown in
Figure 15. The first bit driven into the device is a logic 0, followed by a 3-bit address word. The device then
assumes control of the DATA line on the falling edge of the fifth clock pulse after CS goes low. The conversion
result is output MSB first, with the MSB being output on the falling edge of the seventh clock pulse after CS goes
low. Control of the DATA line is released (returned to input mode), when CS goes high.

I ~----------------~I

OCLK

DATA
IN

=;]

AO
MSB

I I I

DATA
OUT

LSB
05

r--

AOC
Sample

Figure 15. Read-Operation Timing
Table 5 details the decoding of the three address bits.
Table 5. Address Bit Decoding

REFERENCE

Band gap

VMID

Band gap

ADC1

Band gap

ADC2

MEASUREMENT

additional functions
The following paragraphs detail some additional functions of the TCM801 0-50.
digital-to-analog converters
Three a-bit, voltage-output DACs are provided, with outputs on terminals DAC1 , DAC2, and DAC3. The oulpul
range of each converter is from 0 V to Voo/2 or 0 V to VOD with an LSB step size of VOO/256 or Vool2 x 1/2!3G
as selected by < DACX2 >. All DAC outputs can either go to 0 V in standby mode or be active on dependinfJ on
the state of control bit < DACON >. For correct operation of all of the TCM801 0-50, < DACON > must be sol 10
o in active mode. Previously written values are restored to the DAC outputs on entry to active modo.
selects which DAC is being addressed, and sets the output vollano .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-77

TCM8010-50
AMPSrrACS AUDIO PROCESSOR
SLWS009A - SEPTEMBER 1994 - REVISED DECEMBER 1995

PRINCIPLES OF OPERATION
analog-to-digital converter
The TCM8010-S0 contains an 8-bit ADC with a 3-channel analog-input multiplexer. This allows conversion of
signals on ADC1, ADC2, and VMID. An internal band gap voltage reference multiplied by two is used when
measuring ADC1, ADC2, and VMID.
Fifteen periods of DCLK are required to complete a conversion.
DTMF generator
The DTMF generator produces the seven standard tones with a frequency accuracy of ± 1%. The desired DTMF
signal is selected by . A switchable preemphasis or skew between the low and high tone
groups is provided for TACS operation and is selected by bit < DTSK>.
DTMF signal levels scale directly with supply voltage. A 4-bit trim is provided to allow adjustment of DTMF
amplitude to meet system specifications and allow flexibility for user-generated call-tone type signals
«DTTR3-DTIRo». When DTMF is selected in the transmit or receive paths, typical voice signals are
attenuated by SO dB.

clock and supply
Power supply and clock considerations are covered in the following paragraphs.
supply voltage
Specifications are given for a supply voltage of S V. Signal levels such as SAT, DATA, and DTMF are derived
from this. Other parameters such as the compressor and expander unity-gain levels are also dependent on the
supply voltage.
supply current
The TCM8010-S0 has two basic operating modes: standby and active. In the standby mode, only the receive
data path is enabled and current consumption is less than 2 rnA. There is also the option of keeping the DACs
powered up in the standby mode, depending on the setting of < DACON >. In the active mode, all functional
blocks are powered up and the current consumption is less than 12 rnA.
crystal oscillator and clock interface
The clock signal for the device can be generated by the internal oscillator block using an external crystal
connected to the XTO and XT1 terminals. Or, an external O.S-V (minimum) peak sinusoidal clock signal can be
applied to XT1. The external clock signal or the crystal can be one of eight frequencies, selected by control bits
. Crystal or external clock operation is selected by .

~TEXAS

5-78

INSTRUMENTS
POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

•
•
•
•
•
Q

•
•
•

Single Chip Audio and Data Processor for
AMPS/EAMPS/NAMPSITACS/ETACS/JTACS
and NTACS

•
•
•

a-Bit Programmable Timer
Software-Selectable RXlTX Automute
Digitally-Controlled Gains and Signal
Selection or Muting

On-Chip Compander

•
o

Three a-Bit DACs with Output Buffers
DTMF Generator

Automatic Frequency Control
Microphone Preamplifiers

•
o

Arbitration Processing
Two a-bit Programmable Expansion 110
Ports

Operation From Internal Oscillator, External
Clock, or External TCXO

2.7-V to

s.s-v Operation

Multiple Power-Saving Modes

32-.0. Earpiece Driver
Simple Serial Interface
User-Configurable Interrupt Structure
Independent Watchdog Timer

description
The TCM8030 baseband processor for analog cellular telephones provides all the baseband signal processing
required for any of the following standards for mobile and hand-portable cellular telephones: AMPS (Advanced
Mobile telephone Service); EAMPS (Extended Advanced Mobile telephone Service); NAMPS (Narrow-Band
Advanced Mobile telephone Service); TACS (Total Access Communication System); ETACS (Extended Total
Access Communication System); JTACS (Japanese Total Access Communication System), and NTACS
(North-American Total Access Communication System).
The analog section of the TCM8030 performs all filtering required for the speech, data, SAT (supervisory audio
tone), and ST (signaling tone) paths. It has an integrated, CCITT (International Telegraph and Telephone
Consultative Committee)-compatible compander as well as microphone preamplifiers and a differential, 32-.0.
earpiece driver to complete the full integration of the baseband audio signal paths.
The digital section of the device implements the data transceiving, data processing, and SAT functions,
including data recovery, majority voting, BCH (Bose-Chaudhuri-Hocquenghem) decoding, BCH encoding, TX
(transmission) frame assembly, and SAT generation, detection, and regeneration. The TCM8030 supports both
narrow-band standards, NTACS and NAMPS, with full implementation of the narrowband data, and DSAT
(digital supervisory audio tone) and DST (digital signaling tone) filtering and processing functions. An on-chip,
AFC (automatic frequency control) circuit also facilitates narrow-band operation. Communication with the
microcontroller is achieved through a simple 4-wire serial interface.
In addition to these basic signal processing requirements, the TCM8030, integrates many of the ancillary
functions required in a typical FM cellular telephone. Included are three 8-bit DACs (digital-to-analog
converters), a DTMF (dual-tone multiple-frequency) generator, an 8-bit programmable counter/timer, an
independent watchdog timer, two 8-bit microcontroller expansion ports, and a 4-bit keyboard interrupt port.
Clock operation is through a pin-selectable on-chip crystal-referenced oscillator, an external clock source, or
an external TCXO (temperature-controlled crystal oscillator).

Caution. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in
conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-79

>
w
a:
a..

::J

o
a:

a..

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

description (continued)
The TCM8030 is designed for ultra low-power applications and is manufactured using a low-power CMOS
process. It operates from a single 2.7-V to 5.5-V supply and has five power-saving modes in addition to normal
operation. The TCM8030 also features a total power-down mode in which the TCM8030 waits for the user to
press the power-on key located on the telephone keyboard. Also implemented are two features that extend idle
mode operation time.
One feature enables a reduction in the duty cycle of the microcontroller, and the other feature periodically shuts
down the RF receiver. These features reduce the system power consumption to a minimum during idle mode
and Significantly increase the telephone standby time.
The gain and signal selection paths are software configurable so that all audio trimming functions can be
achieved without manual intervention during telephone calibration on the production line. This production-time
reduction feature, together with its high level of integration and low-power design, makes the TCM8030 an ideal
solution for FM analog cellular telephones.
QFP PACKAGE

(Top VIEW)

"'tJ

o
C

80 7978 77 76 7574 73 7271 70 69 68 67 6665 64 63 62 61

DVSSL1
INTRPT
RESET
NC
PIOO
PI01
PI02
PI03
PI04
PI05
PI06
PIO?
Ploa
PI09
PI010
PI011
PI012
PI013
PI014
PI015

-I
"'tJ

S
m

•

60
59

NC - No internal connection

~TEXAS

-INSTRUMENTS
5-80

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MIC2
MICGAIN2
MIC1
MICGAIN1
DTI
SUBVSS
DA1
DA2
DA3
TXVSS
NC
TXVMID
TXVDD
STO
AMPOUT
AMPINN
AMPINP
TXO
STI
CTI

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

functional block diagram
DTI
~ 56

STO
I 47

..
..

57
MICGAIN 1
1
MIC 58
MIC 2 60
MICGAIN 2 59

CLKOUT
CLKSEL
XOUT
XIN
TCXO
IF

67
66
68
69
72

Transmit Path

......

•

DTMF
Generator

Power
Control

L ...

28
70

....
Data and SAT

.......

Clocks

....'"
'"

.......

54
DA1
53
DA2
52
DA3

...

Data
Processor

....

'"
'"
'"

....'"

..'"

5-12
PIOO

...
r

PI07
13-20
PI08

.. ..

110

EXTRST
EXTPWR
WDOUT
RESET
DATAIN
DATAOUT
DCLK
CS
INTRPT
RXRFEN

.;=:

LS Driver

PI015
2 1-24
KEYO

••
•
KEY3

.. ..
'"

36
35

.......

39
38
34

Data and SAI
25

-,
I

Receive Path

.....
.....
~

..
..
..

• •

42-'STI

41.1 401371481511331311731711801301
CTI

c
>
~

a::

TXRFEN

TMOUT

I(J

••
•

REC2

DTO

••
•

REC1

74
3
76
77
78
79
2

TXO

RECP

a::

RECN

RECIN

SYNC
RXGAIN
RXIN

11291551 32+49+

en c en
en c en

> > >
~ ~ ~

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-81

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

AMPINN

Operational amplifier inverting input -

AMPINP

Operational amplifier non inverting input -

AMPOUT

Operational amplifier output -

CTI

Call tone input (analog)

CLKSEL

Clock source select (digital)

CLKOUT

Clock output (digital)

Chip select input, active low (digital)

DA1-DA3

Digital-to-analog converter output (analog)

Data input (digital)

DATAOUT

Data output (digital)

DCLK

Data clock input (digital)

DTI

Transmit DTMF input (analog)

DTMF generator output (analog)

"'C

80,30

DVSSL1,
DVSSL2

1,29

(")

-f

Digital power supply No.1 and No.2
Digital ground No.1 and No.2

EXTRST

EXTPWR

INTRPT

uncommitted (analog)

52-54

DVDDL1,
DVDDL2

uncommitted (analog)

DATAIN

DTO

DESCRIPTION

I/O

Reset output to the rest of the telephone (used in total power-down mode) (digital)
Power-on enable to the rest of the telephone (used in total-power-down mode) (digital)
Input from second IF to AFC circuit (analog)

Interrupt output (digital)

21-24

I/O

Keyboard interrupt inputs or programmable I/O ports (digital)

"'C

KEYO- KEY3

LSVDD

<
-

LSVSS

MIC1,
MIC2

58,60

Microphone amplifier No.1 and No.2 input (analog)

MICGAIN1
MICGAIN2

57,59

Microphone amplifier No.1 and 2 output (analog)

P100-P1015

5-20

I/O

Programmable input or output port 0 through 15 (digital)

REC1, REC2

35,36

Receive output No.1 and No.2 (analog)
Earpiece amplifier input (analog)

Loudspeaker power supply
Loudspeaker ground

RECIN

RECN

Earpiece amplifier differential outputs, negative (analog)

RECP

Earpiece amplifier differential outputs, positive (analog)

RESET

Reset input, active low (digital)

RXIN

Receive amplifier input (analog)

RXGAIN

Receive amplifier output gain (analog)

RXRFEN

RXRF enable output from RXRF idle mode logic (digital)

RXVDD

RXVMID

RXVSS

SYNC

STI

Sidetone input (analog)

STO

Sidetone output (analog)

SUBVSS

Receive-analog power supply
0

Receive-analog mid-supply voltage
Receive-analog ground
Frame sync (digital)

Substrate ground connection

~TEXAS

INSTRUMENTS
5-82

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

TCXO

TCXOVDD

TCXOVSS

TMOUT

1/0
I

DESCRIPTION
Input from TCXO to input buffer, AFC, and clock circuits (digital)
XTALOSC and TCXO input buffer power supply
XTALOSC and TCXO input buffer ground

Counter I timer output (digital)

TXO

Transmit output (analog)

TXRFEN

Transmit RF enable output from arbitration logic (digital)

TXVDD

TXVMID

TX analog mid-supply voltage

Transmit analog supply

TXVSS

WDOUT

XIN

Clock input or input connection for external crystal

XOUT

External crystal output connection

Transmit analog ground
Watchdog timer output (digital)

absolute maximum ratings over operating free-air temperat~Jre range (see Note 1)t
Supply voltage range, Voo, VSS .................................................... - 0.5V to 6.0V
Input voltage range, any input, VI ............................................... - 0.5 to VDO + 0.5V
Output voltage range (includes open drain outputs), any output, Va ................. - 0.5 to VDO + 0.5V
Operating free-air temperature range, TA ............................................. - 30°C to 70°C
Continuous total power dissipation at (or below) TA = 25°C ......................................... .
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 65°C to 150°C
t

recommended operating conditions
MIN

NOM

MAX

3.8

Supply voltage, VDD

2.7

Operating free-air temperature range, TA

-30

Operating junction temperature, TJ

-30
10

Output load resistance at MICGAIN1 and MICGAIN2

Output load capacitance at RXGAIN

Load capacitance, DACx

Output load resistance at AMPOUT

Output load capacitance at AMPOUT
500

Output load at REC1/REC2

pF
kQ

100

Output load to GND at DTO

pF
kQ

Load resistance, DACx

pF
kQ

Output load resistance at RXGAIN

DC
kQ

50
20

Output load capacitance at MICGAIN1 and MICGAIN2

UNIT

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-83

->W

w
a:
a..
I-

U
::J
C

o
a:
a..

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

electrical characteristics over recommended range of supply voltages and operating conditions
(unless otherwise noted)
supply current
PARAMETER

TEST CONDITIONS

Analog supply current

100(A)

MIN

TYP

Full operation

MAX

UNIT

rnA

100(0)

Oigital supply current

Full operation

0.5

100(PM1)

Power mode No.1

Total power-down mode

100(PM2)

Power mode No.2

Shut-down mode

340

JlA

100(PM3)

Power mode No.3

Idle mode

2.2

rnA

100(PM4)

Power mode No.4

Tone mode

rnA

100(PM5)

Power mode No.5

Full operation, OTMF off

rnA

100(PM6)

Power mode No.6

Full operation, OTMF on

rnA

rnA
JlA

digital I/Os
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

IOH = 1 rnA

VOL

Low-level output voltage

IOL= 1 rnA

:c
o
c
c

VIT+

Positive-going input threshold voltage

VIT-

Negative-going input threshold voltage

IlL

Low-level input current

-I

IIH

High-level input current

"'tJ

Vhvs

Hysteresis (V IT + - VIT _)

10Z

High-impedance output current

MIN

MAX

UNIT

VOO-O.4
VSS +0.4
0. 7V OO

V
V
V

0.3 VOO
0. 3V OO

0.1 VOO

±10

JlA

VI =VSS

-1

JlA

VI =VOO

JlA

TYP

MAX

UNIT

1.5

2.5

MHz

0.1

mVrms

VI = VOO or VSS

~ transmit path specifications (see Figure 14)

<
-

MIC1 and MIC2
PARAMETER

TEST CONDITIONS

MIN

Unity gain frequency

Input current at MIC1 and MIC2
Input noise, psophometric weighting

JlA

Rin = 50 kil
70

Open loop voltage amplification
Close loop voltage amplification

80
26

VOICE and OTMF (V/O) trim, MIC1 to TXO
PARAMETER

TEST CONDITIONS

Positive trim range

Code FH

Negative trim range

Code OH

MIN

MAX

3.75
-4.3

Step size

o dB tolerance

TYP

Code 8H

UNIT

dB
dB

0.5

COMPRESSOR, MIC1 to TXO
PARAMETER

TEST CONDITIONS

MIN

Unity gain level

TYP

Linearity
Attack time (see Note 2)
Recovery time (see Note 3)
NOTES:

2. Time taken for the output to settle to 1.5 times the final value with a 6-dB input step
3. Time taken for the output to settle to 0.75 times the final value with a -6-d8 input step

~TEXAS

INSTRUMENTS
5-84

MAX

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

UNIT

dBV

-24.43
±1

2.4

3.6

10.8

13.5

16.2

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

LIMITER, MIC1 to TXO
PARAMETER

TEST CONDITIONS

Maximum output signal, AMPSrrACS

MIN

Code Fh, max deviation

Positive trim range

Code Fh

Negative trim range

Code Oh

TYP

MAX

2.6
-4.6

Step size

o dB tolerance

Code Ah

Distortion, AMPS/NAMPSrrACS

2/3 of max output signal

UNIT
mVpp

740

dB
dB

0.43

dB
3%

TXTRIM, MIC1 to TXO
PARAMETER

TEST CONDITIONS

Positive trim range

Code 1Fh

Negative trim range

Code Oh

MIN

MAX

4.1

Code 10h

UNIT
dB

-4.4

Step size

o dB Tolerance

TYP

dB
0.2

transmit path, MIC1 to TXO
PARAMETER

TEST CONDITIONS

TXSUM mute attenuation

f = 1 kHz at MIC1

Distortion, AMPS/NAMPSrrACS

2/3 of max output signal

IAMPS and TACS

Noise, Compressor enabled,

INAMPS

MIN

TYP

MAX

UNIT
dB

MIC1/MIC2=VMID

2.3

mVrms

Crosstalk in TXSW

f= 1 kHz

Crosstalk RX and TX Path MIC1/REC1, RXIN grounded

f = 1 kHz at 100 mV

transmit data} at TXO
TEST CONDITIONS

PARAMETER

MIN

IAMPSrrACS

Output level

INAMPS/NTACS

TYP

MAX

UNIT

5S0

mVpp

3.3%

Harmonic distortion

PARAMETER

TEST CONDITIONS

Positive trim range

Code Fh

Negative trim range

Code Oh

MIN

o dB tolerance

TYP

MAX
1.S

-2.3

Step size
Code 4h

UNIT
dB
dB

0.6

0.5

transmit SAT at TXO
TEST CONDITIONS

PARAMETER

MIN

TYP

MAX

UNIT
mVrms

\AMPSrrACS

Harmonie distortion

transmit SAT TRIM at TXO
PARAMETER

TEST CONDITIONS

Positive trim range

Code 7h

Negative trim range

Code Oh

Step size

o dB tolerance

->w
a::

a.
Io

::J

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TX-OAT Trim at TXO

Output level

=:w

Code Sh

MIN

TYP

MAX
2.3

-2.4

UNIT
dB
dB

0.3

0.5

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-S5

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

receive path specifications (see Figure 14)
RXAMP
PARAMETER

TEST CONDITIONS

MIN

Unity gain frequency

TYP

MAX

1.5

Input current

MHz

Input noise psophometrically weighted

Rin = 50 kn

IlA
0.1

Open-loop voltage amplification

Closed-loop voltage amplification

UNIT

mVrms
dB

TYP

MAX

RXTRIM, RXGAIN to REC1
TEST CONDITIONS

PARAMETER
Positive trim range

Code Fh

Negative trim range

Code Oh

MIN

3.7
-4.3

Step size

a dB Tolerance

Code 8h

UNIT
dB
dB

0.5

Audio Expander, RXGAIN to REC1

""C

Unity gain level

C
C

Attack time (see Note 4)

Recovery time (see Note 5)

""C

receiver path, RXGAIN to REC1

MAX

UNIT
mVpp

±2

2.4

3.6

10.8

13.5

16.2

TYP

MAX

UNIT

4. Time taken for the output to settle to 0.57 times the final value with a 6-dB input step
5. Time taken for the output to settle to 1.5 times the final value with a -6-dB input step

<
-

TYP

Linearity

NOTES:

MIN

690

(")

--t

TEST CONDITIONS

PARAMETER

TEST CONDITIONS

MIN

REC1 SW mute attenuation

Crosstalk between REC1/REC2

Distortion at REC1/REC2 Expander enabled

0.01%

RXIN 400 mV, f=1 kHz, No load

Noise at REC1/REC2 Expander bypassed

RXIN = VMID, psophometric weighting

Voice mute attenuation

RXIN = 400 mV, 1kHz

Output voltage at REC1/REC2

RL=500n

1.5

0.02

mVrms
dB

Vpp

VOL CTRL, RXGAIN to REC1
PARAMETER

TEST CONDITIONS

Positive range

Code Fh

Negative range

Code Oh

MIN

TYP

MAX
16.5

-20

Code 8h

dB
dB

2.5

Step size

a dB Tolerance

UNIT

0.5

LS DRIVER at RECP and RECN
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Open loop voltage amplification

Unity gain frequency

1.5

MHz

0.8

Vp-p

Differential output level

VDD=3 V

Distortion

0.12%

Input load resistance

150

"TEXAS
INSTRUMENTS
5-86

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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

receive data detect
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

NAMPS

-27.68

dBV

NTACS

-25.65

dBV

TACS, JTACS

-6.53

dBV

AMPS

-6.43

dBV

Must not detect level

-25.51

dBV

Must detect level

-19.49

dBV

Level at RXGAIN

receive SAT detect
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ITACS, JTACS

-17.95

lAMPS

-18.56

dBV

Must not detect level

-37.43

dBV

Must detect level

-30.49

dBV

Level at RXGAIN

dBV

miscellaneous block specifications (see Figure 14)
digital-to-analog converters DAC1, DAC2, and DAC3
PARAMETER

TEST CONDITIONS

MIN

DACx output voltage

Code 255

DACx zero code DC offset

Code 0

Differential nonlinearity

Codes 5 -250

-1

Integral nonlinearity

Codes 5 -250

-1

TYP

MAX

0.05

VDD-0.05

Conversion time

UNIT

LSB

LSB
ms

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DTO output level low

270

mVrms

697 Hz

270

mVrms

270

mVrms

852 Hz

270

mVrms

941 Hz

270

mVrms

DTO output level high

270

mVrms

1150 Hz

270

mVrms

AMPS

1209 Hz

270

mVrms

270

mVrms

1477 Hz

270

mVrms

1633 Hz

270

mVrms

2048 Hz

270

mVrms

1336 Hz

a:
c..
t-

DTMFGEN

770 Hz

sw
>

AMPS

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-87

::l
C

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

AMP7
PARAMETER

TEST CONDITIONS

MIN

Unity gain frequency

TYP

MAX

1.5

Input current

MHz
~A

Input noise, psophometric weighting

0.1

Rin = 50 kn

Open-loop voltage amplification

83
15

Closed-loop voltage amplification
Harmonic Distortion

UNIT

mVrms
dB

0.01%

timing requirements over recommended ranges of operating conditions (see Figure 1)
MIN

NOM

MAX

UNIT

tsu1

Setup time, CS to DCLKi

~200

tsu2

Setup time, DATAIN before DCLKi

~200

Hold time, DATAIN after DCLKi

~200

Delay time, DCLKi to

cst (start of next cycle)

ns
$;1

DCLK

"'C

o
c

c:
o

-I

"'C
J]

<
-

~TEXAS

INSTRUMENTS

5-88

~1000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MHz

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
Figure 1 shows the write timing diagram for the microcontroiler interface. The read timing diagram for the
microcontroiler interface is shown in Figure 2. Refer to microcontroiler interface operation for a detailed
description.

1 - - - 1_

j4---+fI
DCLK - - - - - ,

14-- td

tsu1

~
~

WRITE

DATAIN
Start Bit

-f
w
t-

3:
w

o
a:

1 4 - - - - Read Data - - - - . t

Figure 2. Microcontroller Interface Read Timing Diagram

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

::l
C

5-89

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

TYPICAL CHARACTERISTICS
NBRXLPF FREQUENCY RESPONSE
10

0.01

I
I
I

-10

0.008

;:!

\ji
-30
~l)\ ~
-40

I1l

-50

I
CIl

'cOJ
::

-70

-90

(

en
I1l
..c:
c..
c..

--..

0.004

r----

0.003

. . . "-----I-

0.001
r-

0.6

0.8

f - Frequency - kHz

Figure 3

C
C

(")

NBRXLPF EYE PATTERN

-I
"'C

1.25

0.75

TXBPF FREQUENCY RESPONSE

.-------,_~~-----r-~:::IiI""'OIi:"T""--....,

0.005

0.002

0.4

0.2

::sm

~l.

-80

0.006

CIl

0.007

I1l

\ i:\
II

-60

"'C

0.009

II
II

II ~ !I
II

I
-20

>
I

-10

0.5

CIl

-20

m
'C

0.25

ii
E

0.125 l-------lr-ll---+--\-_._---+---t--tI

(l)

.!::!

iii
E
(;

-20

:¥

-25

'cCl

-0.125

l--~r\'It-------+---f-_W_-----t---_#__-tI

-0.25

r----I----ir.--~--#-~.__--_r__,..--H

-30

-0.375

~~---+--1I\.----+_I_-_+_ll_--+-_#__---fl

-35

\
\
\

-10

m
~ -15
"C

Or--~~-~--~---_r-~ffi

-5

~..---+-I--__+~--+-_I_--+-_+_--tI

0.25 1----\--j'-l----+--\----tJJ-----t--\----H

o
a::
a.

( r\

-40
-0.625 L-..-_---L_ _--I._ _--I..._ _
_ _- I
0.5
1.5
2
2.5
3
~

->w

TXLPF FREQUENCY RESPONSE

0.625...-------r-----,...-----,.-----r----,

a::

EYE PATTERN FOR TXDALPF AND TXSUMLPF
COMBINED (NARROWBAND)

100

Figure 7

Figure 6

0.375

31.62

f - Frequency - kHz

-45
0.1

If
0.3162

3.163

31.63

f - Frequency - kHz

Normalized Time - s

Figure 9

Figure 8

•
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-91

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

TYPICAL CHARACTERISTICS
TXLPF FEQUENCY RESPONSE

TXSATBPF RESPONSE PROFILE
5

0.8

0.6

-5

0.4

.."

-10

"tJ

~ -15

0.2

I
GI
"tJ

·c.a

co -0.2
::E

·c
W -25
-30

-0.6

-35

-0.8

-40

"'C

-1

............

0.3162

3.163

31.63

Figure 10

-2

·c.aCl
co
::E

I
I

-'"

7
f - Frequency - kHz

-6
-8

- r---

-0.1

-10
-12

GI
"tJ

·c.aCl
co
::E

---

-0.3
-0.4

-0.6

-16

-0.2

-0.5

-14

-0.7

-0.8

-18

3.162

31.63

100

316.3

f - Frequency - kHz

Figure 12

Figure 13

~TEXAS

INSTRUMENTS
5-92

0.1

.'\

-4

GI
"tJ

\.' ~\.

0.2

TXSUMLPF FREQUENCY RESPONSE

"tJ

Figure 11

I
4

f - Frequency - kHz

-I
"'C
::D

i i
i i

-45

0.1

::D

III \~\
//1 1\\
// i i\\
/f i I \ '
/'/ I ! \
............ ,
I

::E

-0.4

.......

~ -20

<
-

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

STO

MICG~~:

TRANSMIT AUDIO CHANNEL

AMPOUT

MIC2
MICGAIN2

DTO

o~ .....
Z~
_.

mrJ)

I~~
~m{J)

-~~

~(J)
>

(fl

AMPINN

! IPower-()ff I +

E::::~ :

AMPINP

TXO

CLKOUT

'~11 · i@+I'~~1 ~ ~
RXRFEN

I..

1 1

TXRFEN

I...

1 1

XIN

TCXO

IF
DAt
DA2
DA3
PIOO

·:
··

TMOUT -+1.
.. . - - - - - - ' - ,
LSVDD
RECP
RECN
RECIN

CLKSEL
XOUT

I"'! _

PI07
Ploa

LSVSS

··

SYNc-+I..
..-----~---------------------_1

PI015
KEYO

•

KEY3

REC1

I..

REC2

1111

RXGAIN
RXIN

»
Z
»m
I»
°en
G)m
om
m»
IZ
Ie
c:."
»:0
:0
0

CIl-iO
~mm

t;;

Q
Q

I--

C/)

(/)

>
x

I-

CJ)

>
x
a:

>
X

CI)

o
>

en
en
>

000

Figure 14. TCM8030 Detailed Functional Block Diagram

PRODUCT PREVIEW

~
U)
fJ)

>
0

0
~

~ ~

CIl I en
I§men-l

1"'00
E5:O
:s:

~Z""
--

a:
a.
I-

_ _ _-ITXSUMLPF

TXO

Sources

---0,

Data Source

:J
C

External

r - - - -,

I
I
I
I
I
I
I

...!:D'-!.T.!...I_ _ _ _ _ _---,

a:
a.

I~~KM~==~~--~

L-

I
-

MICGAIN2

oJ
DTO

-----.fDTMFl
L:::J
Figure 16. Transmit Audio-Path Block Diagram

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-95

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

overview (continued)
Miscellaneous functional blocks are shown in Figure 17. The LS DRIVER block provides the capability to drive
loudspeakers. Gain is set with the external resistor pair R1/R2. An uncommitted operational amplifier (AMP7)
is provided and a pair of gain-set resistors (R3/R4) are shown connected externally.
A separate mid-rail voltage source is provided for both the receive and transmit paths. Each is deselected when
its part of the circuit is powered down.
A programmable divide, PROG DIVID, can be programmed to divide the oscillator signal (or external clock) into
four separate internal clocking signals. The oscillator block requires only a crystal (XTAL) and a pair of
capacitors for operation. Alternatively, an external clock can be connected at XIN, or TCXO can be selected as
required. A triple DAC is also provided for oscillator trim functions. Used in conjunction with the AFC control in
the data processor block (see Figure 18), this permits lower stability oscillators to be used successfully, thus
saving system costs.

~
JV -

""C

r--------CLKOUl
.-----+--CLKSEL

ixVMID

::D

c:
o

TXVSS

-I

-c::.
J

LS DRIVER

""C

::D

m
S
m

External

AMP7

@J=
AC
1-3

DA1
DA2
DA3

DACs

+RXVMID

RXVSS

Figure 17. Miscellaneous Functional Block Diagrams

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

External

CLOCKS

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
overview (continued)
The data processor, Figure 18, provides a large number of functions for processing cellular data streams and
controlling the other functions of the TCM8030.
Power-off and idle-mode logic is provided, together with both standard and watchdog timers. Incoming (RX)
data is selected according to standard (for example, WB/NB) and processed through filters/comparators to
comply with the standard. After majority voting and BCH decoding, the data is buffered and applied to the
microcontroller .interface. On the transmit side, data is placed in the TX buffer after selecting the appropriate
encoder. The encoded data goes through its attenuator/trim stage to the transmit data lowpass filter (TXDAT
LPF) and is switched into the transmit (TX) audio path.
SAT is recovered from the RX audio path through a filter and comparator and fed to the data processor
detector/regenerator. Regenerated TXSAT goes through programmable attenuator/trim stages to the
band-pass filter that feeds the TX path.
Digital supervisory audio tone (DSAT) is detected through the NB data recovery block. The regenerated signal
is sent through the normal NBDAT path to the transmit path.
The microprocessor interface is a simple serial shift register function, using DATAIN, DATAOUT, DATACLK, and
CS, and has an interrupt output (INTRPT). This interface allows the TCM8030 to communicate with the
microcontroller that is operating the telephone.
Data Processor

EXTRST _ _--/-.jrPo;;;;;:c)ij'JI~-""

EXTPWR - - - + - I
WDOUT

---+-I

::J
C

RESET - .
DATAIN
DATAOUT
DClK
CS

---t----r--:::::::-T:::::::::.::l

---1----1
---t----I
---1----1

INTERPT

--i-----t-,-L-...J

RXRFEN

---+-I

TXRFEN

---+-I

a:
a.

TMOUT

SYNC

w
:>
w
a:
a.

---+--------------1

Figure 18. Data Processor Block Diagram

"TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-97

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
audio processing functions -

receive path

The TCM8030 audio receive path is composed of the following circuits, as shown in Figure 14. A brief functional
description is given for each circuit listed.
RXAMP
The receive amplifier circuit (RXAMP) receives its input from terminal RXIN. A portion of the RXAMP output is
applied through terminal RXGAIN to a pair of external resistors that set the stage gain. The RXAMP noninverting
input is internally connected to the internal RXVMID reference signal.
RXTRIM
The receive trim (RXTRIM) stage is provided to compensate for FM discriminator variations. This block also
includes a switched-capacitor filter to perform antialiasing.
RXBPF
The receive band-pass-filter (RXBPF) is a switched-capacitor filter with a passband of 300 Hz to 3 kHz.
AUDIO DE-EMPHASIS

""CI

As the audio frequency increases, the audio deemphasis circuit decreases the signal gain at a rate of 6 dB per
octave across 300 Hz to 3 KHz.

:rJ

o
C

AUDIO EXPANDER

-f
"tJ

:rJ

The audio expander circuit provides an output level change of 2 dB for an input signal level change of 1 dB.
EBSW
The audio expander bypass switch (EBSW) permits the routing of the received audio around the audio expander
circuit during testing.
REC1SW

<
-

The receive 1 switch (REC1 SW) selects one of three inputs: the output from the audio expander (or bypassed
expander), the CTI (DTMF) input, or it selects RXVMID to mute the channel.
VOL CTRL
The volume control (VOL CTRL) circuit can be programmed to provide a nominal gain of -20 dB to +17.5 dB.
RECSUM
The receiver summing circuit and switch (RECSUM) provides the means for adding the sidetone input (STI) into
the receive audio path.
RECBUF
The receive buffer (RECBUF) switches in or mutes two output buffers independently, or connects these buffers
in differential mode so that a piezo speaker can be connected to REC1 and REC2 terminals. Independent
control of the two audio outputs allows one to be used for external handsfree operation.
LSDRIVER
The loud speaker driver (LS DRIVER) circuit is a selectable differential or single-ended output earpiece power
amplifier. It is used to drive a 32-Q dynamic earpiece (or a piezo earpiece).

~TEXAS

INSTRUMENTS
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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

audio processing functions - transmit path
The TCM8030 audio transmit path is composed of the following circuits as shown in Figure 14. A brief functional
description is given for each circuit listed.

MIC1, MIC2
A pair of single-ended microphone amplifiers accept two input signals (MIC1 and MIC2). Output from each
amplifier is fed back through terminals MICGAIN1 and MICGAIN2 and applied to an external resistor to set the
gain for each individual amplifier.

TXSW
The transmit switch (TXSW) permits selecting one of four transmit audio sources. TXSW can select either the
voice signal from MICAMP1 or MICAMP2, or the input from the DTI terminal (which has been connected
externally to the DTMF generator). The path can also be muted by connecting the switch to the internal
reference TXVMID signal.

VlD TRIM
The voice and DTMF (V/D Trim) circuit contains an antialiasing filter to process the audio signal before it is
applied to the transmit band-pass filter. This circuit block also provides a means to trim the voice and DTMF
signal levels.

TXBPF
The transmit band-pass filter (TXBPF) circuit is a switched-capacitor band-pass filter that passes only the
transmit-audio frequencies from 300 Hz to 3 kHz.

COMPRESSOR
The compressor circuit compresses the audio signal and outputs a Signal that changes by1 dB for an input signal
change of 2 dB.

CBSW
The compressor bypass switch (CBSW) permits routing the audio signal around the compressor circuit when
testing the audio channel or for passing DTMF signals.

PRE-EMPHASIS
As audio frequency increases, the preemphasis circuit increases the signal gain at a rate of 6 dB per octave
across the 300Hz to 3KHz audio passband.

LIMITER
The LIMITER circuit limits the transmit signal deviation within an acceptable range.

TXLPF
This circuit is a transmission low-pass switched-capacitor filter (TXLPF). It removes harmonics caused by the
(deviation) limiter. Linear phase design prevents overshoots. This circuit is also used in the narrow-band mode
to filter switched-capacitor output noise from TXDATLPF.

TXSUMLPF
The transmit summing and low-pass filter circuit (TXSUMLPF) selectively sums voice, data, or SAT into the
audio output. It also includes a low-pass switched-capacitor filter to reduce spurious output emissions above
10 kHz.

•
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5-99

3r:
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a::

a..

I-

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o
a::

a..

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
TXTRIM
The transmit trim stage (TXTRIM) trims the FM deviation transmitting ST or wide-band data prior to its output
on the TXO terminal stage. This stage has a continuous second-order smoothing filter that removes noise.

data processing functions -

receive path

The TCM8030 data receive path is composed of the following circuits as shown in Figure 14. A brief functional
description is given for each circuit listed.

WB-RXCOMP
This wide-band receive comparator circuit (WB-RXCOMP) features built-in hysteresis to reject noise.

WB - RX RECOVERY
This circuit performs the wide-band receive data recovery function (WB-RX RECOVERY), including dotting.
WORD SYNC
This circuit performs frame synchronization (WORD SYNC) recovery for the wide-band data channel.

"tJ

NB-RXLPF

:xJ

The narrow-band receive-data and low-pass filter circuit (NB-RXLPF) contains a low-pass switched-capacitor
filter for filtering DSAT and audio signals. This circuit also includes a deCimating antialias stage at the input.

C
C

NB-RXCOMP

The narrow-band receive and DSAT comparator circuit (NB-RXCOMP) features built-in hysteresis to reject
noise.

-I
"'C

NB - RX RECOVERY

m
S
m
=E

The narrow band data and DSAT recovery circuit (NB-RX RECOVERY) recovers the narrow-band data and
DSAT components for application to the BCH decoder circuit.

SYNC WORD DET
The sync word detect circuit (Sync Word DET) detects the narrow-band data sync word.

DSATDET
The digital supervisory audio tone detector circuit (DSAT DET) monitors the narrow-band receive recovery data
for the DSAT signal.

MAJORITY VOTING
All 40 receive-data bits are individually majority voted in the wide-band and narrow-band data majority voting
circuit. The number of repeats used can be read using the microcontroller interface.

BCHDECODER
The wide-band and narrow-band BCH decoder stage can correct up to two errors in the received signal and
give a 4-bit-error-correction status report.

RXBUFFER
The receive buffer (RX BUFFER) stage provides a buffer for both wide-band and narrow-band received data.

RXCONTROL
The receive control (RX CONTROL) functional block controls the wide-band/narrow-band receive data
recovery and decoding stages and splits the time-multiplexed busy/idle bits, chooses word A or B, and starts
majority voting and error correction when required.

~TEXAS

INSTRUMENTS
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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
ARBITRAT LOGIC
The arbitration logic circuit (ARBITRAT LOGIC) arbitrates the wide-band data busy/idle bits majority voting and
outputs the result to the TXRFEN terminal.

IDLE-MODE LOGIC
The idle-mode logic circuit senses the microcontroller unit (MCU) idle mode and receive RF (RXRF) idle mode
functions and applies an enable signal to output terminal RXRFEN to control internal power mode.

data processing functions - transmit path
The data processing functions associated with the TCM8030 transmit path are performed by the following
circuits illustrated in Figure 14. A brief functional description is given for each circuit listed.

TXBUFFER
The transmit buffer (TXBUFFER) buffers both narrow-band and wide-band data that is loaded from the five
transmit dataword registers.

WB - TX Encoder
The wide-band transmit data encoder circuit (WB - TX Encoder) receives the data from the transmit buffer and
performs all the necessary operations for both the reverse control channel (RECC) and reverse voice channel
(RVC) data transmission. BCH parity bits are calculated and added to the data along with word sync and dotting.
The wide-band signaling tone, ST, is generated when required.

NB - TX Encoder
The narrow-band transmit data encoder circuit (NB - TX Encoder) calculates the BCH encoding parity bits from
the data in the transmit buffer and adds the 3~-bit sync word to synchronize the transmission of RVC data to
the DSAT.

DATSW
The digital audio tone switch (DATSW) selects either narrow-band data orthe output from the DSAT/DST GEN
stage for application to the NB - DAT ATTEN stage. Operation of the DATSW is controlled by the value in bits
5 and 6 of the operational control word C1. When bits 5 and 6 are 0, the switch connects to the NB - TX Encoder
input. See topic, address 00 - operational control word (C1) topic for detailed information about control word
C1.

WBINBSW-a, -b and -c
The (wide-band, narrow-band) switches WB/NBSW-a through -c are ganged together to select either
narrow-band (NAMPS) or wide-band (AMPS) transmission operation. The switch position is controlled by the
value in bit 1 of the operational control word. See topic, address 00 - operational control word (C1) for detailed
information about the control word C1.

DSATIDST GEN
The digital supervisory audio tone/digital sinaling tone generator (DSAT/DST GEN) circuit generates the
narrow-band DSAT and DST signals.

NB - OAT ATTEN AND WB - OAT ATTEN
These two circuits are fixed narrow-band and wide-band data attenuators (NB - DAT ATTEN AND WB - DAT
ATTEN that set the correct data Signal levels.

TXDATTRIM
The transmit data trim circuit (TXDAT TRIM) trims the DSAT, DST, and narrow-band data levels .

•
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5-101

->w
W

a:
a.

:::l
C

a:
a.

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
TX-DATLPF
The transmit data low-pass filter circuit (TX-DAT LPF) provides low-pass switched-capacitor filtering of the
SAT, DST, and transmitted narrow-band and wide-band data to minimize output harmonics and achieve
correct narrow-band transmitted data eye pattern.

SAT processing functions -

receive path

The processing of the supervisory audio tone (SAT) is the TCM8030 receive path is performed by the following
circuits shown in Figure 14. A brief functional description is given for each circuit listed.

RXSATBPF
The receive SAT band-pass filter (RXSAT BPF) is a switched-capacitor filter.

SATCOMP
The supervisory audio tone comparator (SAT COMP) circuit slices the received SAT signal before sending it
to the SAT GEN/DET circuit and contains built-in hysteresis to aid in noise rejection.

'"'C SAT processing functions - transmit path

The supervisory audio tone processing functions associated with the TCM8030 transmit path are performed
by the following circuits illustrated in Figure 14. A brief functional description is given for each circuit listed.

o
C

c:
o

SATGENIDET
The supervisory audio tone generator and detect (SAT GEN/DET) circuit is primarily a transponding digital
phase-locked loop (PLL) circuit. It is used in wide-band mode only. This circuit is an enhanced design that
improves SAT sensitivity. SAT outputs can also be programmed without a SAT input when testing the telephone.

-I
'"'C

SATATTEN

The supervisory audio tone attenuator (SAT ATTEN) circuit consists of a fixed attenuator and is used to set the
correct TX SAT signal level.

SATTRIM
The supervisory audio tone trim (SAT TRIM) circuit sets the wide-band SAT trim level. Output from this circuit
is applied to the TXSATBPF antialias filter.

TXSATBPF
The transmit band-pass filter (TXSAT BPF) circuit is a switched-capacitor band-pass filter that performs
antialiasing.

Clocks
The crystal oscillator and programmable dividers (OSC and PROG DlVID) circuits generate internal clocks and
also an external clock output on the CLKOUT terminal.

5-102

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
OSC and PROG DIVID

The TCM8030 can be clocked from one of three sources as selected by the CLKSEL terminal as follows:
1.

Internal crystal oscillator (XTALOSC), crystal connected between terminals XIN and XOUT. In this mode
the crystal used must be 5.12 MHz. (CLKSEL=LOW).

External square wave frequency with a standard CMOS logic level input applied to terminal XIN.
(CLKSEL=LOW).

External TCXO sine wave with an amplitude at least 0.5 V peak-to-peak applied to terminal TCXO
(CLKSEL=HIGH).

When the CLKSEL terminal is high in mode 3, an external TCXO is selected. When CLKSEL is low, then the
clock source is the internal crystal oscillator when a crystal is connected between terminals XIN and XOUT in
mode 1 or when an external squarewave frequency is applied to terminal XIN in mode 2.
In modes 2 and 3, any of the frequencies in Table 1 can be used.
When the device is being tested, mode 2 is used with a 10 MHz, full CMOS logic-level external clock.
The state of the CLKSEL terminal is also used to route either the TCXO frequency signal source (CLKSEL=1)
or the internal oscillator/external squarewave frequency signal source (CLKSEL=O) through a divide-by-two
counter to the CLKOUT terminal. Bit 3 of (CLKOUTSEL) is used to place the CLKOUT terminal in a Hi-Z state
when an external clock is not needed.
When modes 1 or 2 are used as the master clock for the TCM8030 using an internal crystal oscillator or external
square wave source, the AFC circuit functions with the TCXO operating at any frequency less than 20 MHz.
When mode 3 is used as the master clock for the TCM8030, the external TCXO frequency must be one of the
frequencies associated with CKRT(bits 0-2) as shown in Table 1.
Frequency divider circuits derive the internal clocks, 2.56 MHz to the data processor and 1.28 MHz, and
320 kHz, 160 kHz, and 10kHz to the audio processor.
The internal oscillator XTALOSC, TXCO input clock recovery circuit TCXOAMP, and internal dividers,
PROGDIV share their own dedicated power supply terminals so the amount of crosstalk from the rest of the
circuit (and hence the clock jitter) is minimized.
All the clock circuits are powered down in the TCM8030 total power-down mode, but in all other modes, the clock
output on CLKOUT is active when CLKOUTSEL is O.
The first 3 bits of the CLKSRC register specifiy the master clock input or crystal frequency, and bit 3 of CLKSRC
controls the output of a clock signal on CLKOUT, as shown in Table 1.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

5-103

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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
OSC and PROG DIVID (continued)

Table 1. Master Clock Input Frequency and CLKOUT Select
BIT 1
CKRT1

BITO
CKRTO

1
1

BIT2
CKRT2

"tJ

BIT3
CLKOUTSEL

FREQUENCY
SELECTED

TERMINAL
CLKOUT

5.12 MHzi

7.68 MHz

10.24 MHz

12.8 MHz

15.36 MHz

17.92 MHz

X
X

:j:

Active

Hi-Z

t When using the internal crystal oscillator, 5.12 MHz must be selected and a 5.12 MHz crystal must be

::D
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connected between terminals XIN and XOUT.
:j: CKRT(bits 0-2) = 110 and 111 not allowed.

The clocking scheme is summarized in Figure 19.

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~TEXAS

INSTRUMENTS
5-104

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

ose and PROG DIVID (continued)
IFAMP
1 - - - - - - - - - 4 - - IF

.....-----~4-

TCXO

TXCOAMP
PWDTCXO
PWDXTAL

--1------------+------'
--1------------+--------,
.------~----;~----~r

~-"""-+-----~I-

RESET
CLKSEL
CLKOUT

CKRTO

- - - f -........

CKRT1

---1---""

CKRT2

--+--....

CLKOUTSEL

Programmable
Divider

1-----/-----'

---+----+------,
Enz

XTALOSC
' -_ _ _- " " 1 - - - - - - + - - + - 4 1 -

XOUT} External Clock
XIN
or Crystal

a::
a..

2.56 MHz

1.28 MHz
--t---tH

Fixed
Divider

Internal Clocks

320 kHz

oa::

160 kHz
10 kHz
Internal Clocks

a..

_________________________ JI

Figure 19. TCM8030 Clocking Scheme Functional Block Diagram

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

:>
w

4
TCXOVDD
All Circuits { ..
4 - - - - - - TCXOVSS

PWDFIL

5-105

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
POWER MODES
The power off logic circuitry implements six modes in which various functions of the TCM8030 are powered off.
These modes are selected by control word 4. In power-down mode, all internal circuits, including the crystal
oscillator (XTALOSC) are disabled.

total power-down mode
In this mode, power is still applied to the TCM8030 but, the device is in total power-down mode. All circuits
including clock, bias circuits, PIOs, and the watchdog timer are powered down and the TCM8030 is stopped
so it draws only minimal-leakage current. The EXTPWR output terminal is low to disable the power supply to
the rest of the telephone (including the MCU). The EXTRST terminal also is active-low during total power-down
mode and the TCM8030 microcontroller interface is disabled.
It is intended that the TCM8030 be the only device in the telephone with its power supply enabled in this mode.
Static power-up logic implemented using one of the keyboard interrupt ports waits for the power-on key to be
pressed. After the power-on key is pressed, the TCM8030 exits total power-down mode, reactivates the
oscillator, enables the regulators to the rest of the telephone (using the EXTPWR enable signal), and holds
EXTRST terminal low for 0.1 to 0.2 seconds to allow the rest of the telephone to power up reset when the system
is stable.

"tJ

The TCM8030 is placed in total-power-down mode by writing 02 hexadecimal to C4(bits4:0). (Both of the bits
C4 (bits 1-0) must be toggled with this write). The security bit, C4.1, reduces the probability that the total
power-down mode is entered erroneously, for example, by RFI (radio frequency interference).

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The independent analog circuits IFAMP, AMP7, and DAC1-3 are also powered down in total power-down mode
independently of the status of their own power-down control bits in register AUXPE (write address 30).

-I
"tJ

The total power-down mode is used in the cellular telephone system from the first connection of the battery as
follows:

Power is applied for the first time when the battery is connected. Only the TCM8030 has its power supply
connected initially and powers up in shutdown mode, enabling its clock, such as XTALOSC, when selected
by CLKSEL terminal and immediately setting the EXTPWR high.

The powerup clear to TCM8030 (RESET input) is held low (active) during the operation of the external
power-on-reset (RC) circuit. This causes EXTRST to also be low (active).

When the external power-on-reset is complete, the TCM8030 MCU interface is enabled and the MCU starts
its boot routine. Because TCM8030 INTRPT terminal is not set to 1, the MCU knows that it was reset by
a powerup from a battery connect. (In this situation the telephone should appear to be OFF until the
power-on key is pressed.) The MCU then writes to the TCM8030 to:

:s:m

•

Enable a keypad interrupt on the appropriate key terminal. This requires four writes to TCM8030
registers:
PI31NT (write address 1C) to enable the terminal interrupt
-

PI3PULL (write address 1B) to enable or disable the pullup as required
PIOC3 (write address 19) to set direction as input
IE2 (write address 06) to enable interrupts from the PI03 and keypad port

•

Set the C4 (bits 4-0) to 01 h to enter total power down mode

•
TEXAS
INSTRUMENTS
5-106

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
total power-down mode (continued)
The MCU must first enable the keypad port terminal connected to the power-on key before entering total
power-down mode. If this is not done, only RESET to the TCM8030 reenables it.
4.

At this point the clock stops, EXTPWR goes low (inactive), EXTRST goes active low, and the MCU and other
parts of the system power off, waiting for the power-on key to be pressed.

The user presses the power-on key and this is sensed on one of the KEY inputs. Asynchronous logic, which
does not need the clock, reads the power-on key and forces the TCM8030 back into shutdown mode and
turns EXTPWR back on. The TCM8030 event register also records the fact that a keypad interrupt has been
received.

EXTPWR going high powers up the microcontroller and after a timed interval of between 0.1 second and
0.2 second plus the XTALOSC warm-up time, EXTRST is released, allowing the rest of the system to power
up reset when the system is stable. The MCU then executes its boot routine.

At this time the INTRPT terminal from the TCM8030 is active and the the microcontroller checks the
TCM8030 event register and finds that it has been awakened by a keypad event, such as the power-on key
was pressed. This means that the microcontroller starts initializing the entire system appropriately.
Figure 20 summarizes the TCM8030 power sequence.

.14
1

I
EXTPWR

EXTRST

1
1
1
14 .14

.14

.14
1

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1
1
1
.1
1

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NOTES: A. A battery is connected and power is applied the first time. (TCM8030 powers up in shutdown mode.)
B. The TCM8030 is waiting for power key to be pressed.
C. The microcontrolier powers up and EXTRST is released after 0.1 to 0.2 second delay (plus XTALOSC warmup time).
D. RESET low during the power up-reset mode.
E. Power-up reset cycle starts, and microcontroller enables keypad interrupts. TCM8030 enters the total power-down mode.
F. A keypad sense power-on event, such as the power-on key, is pressed. EXTPWR is re-enabled, after 0.1 to 0.2 seconds timer
times out (plus XTALOSC the warm up time).

Figure 20. Summary of TCM8030 Power-Up Events

shutdown mode
The microcontroller interface, all three PIOs, clock, bias circuits, and the watchdog timer blocks remain
operational in the shutdown mode. The shutdown mode can be used, when the telephone is switched on but
is not able to receive calls, for example, while the battery is being recharged. The microcontroller interface
may be used to access all internal registers during shutdown mode, but the microcontroller can not issue
commands for addresses 08h to OEh .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-107

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a.

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
idle mode
In addition to the circuits that are operational in shutdown mode, the wide-band receive data path is enabled
in this mode. This corresponds to the telephone being in idle mode, on a forward control channel (FOCG).
Two submodes are also implemented within the idle mode to further minimize power consumption within the
telephone. First, the MCU idle submode (see description for register E2 in read address map - read address
06, Table 39) enables the MCU to go to sleep when no new messages are received, and the RXRF idle
submode (see description for register RXRFTIM in write address map - write address 20, Table 2 in detailed
description - Write Address Map) allows the RF receiver to be powered down when it is not needed.

tone mode
In addition to the circuits in shutdown mode, the DTMF generator, and the section of the RX audio path
following the CTI input are powered up in this mode. This mode can be used when the telephone is powered
up and the user interface, such as the key pad and user memories, is enabled but the telephone is not in
communication with the base station.

full operation mode, (DTMF TX off)

'"C
:D

A" circuits except the DTMF generator are on. This mode corresponds to a telephone conversation in
progress.

full operation mode, (DTMF TX on)
A" circuits are on. This mode is enabled for a DTMF tone to be transmitted during a telephone conversation.

-I
'"C
:D

m
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m

miscellaneous functions
There are several circuits within the TCM8030 that perform specific functions given in Figure 14. These circuits
are listed below along with a brief functional description.

TXVMID and RXVMID
The TXVMID and RXVMID functional blocks are separate receive and transmit analog reference voltage
generators. The circuits contain resistive dividers fed from analog voltage supplies. The outputs are buffered
and then decoupled externally to provide an accurate, quiet, mid-rail reference for internal audio circuits.

AFC
The AFC (automatic frequency controller) circuit receives one input from an external TCXO
(temperature-compensated oscillator) and another input from the receiver second IF (intermediate frequency)
stage. The counters in this block then process the inputs and provide a count that can be read using the
microcontro"er interface.

DAC 1-3
The DACs 1 - 3 are each 8-bit linear digital-to-analog converters.

AMP7
AMP 7 is an uncommitted operational amplifier.

DTMFGEN
The dual-tone multifrequency generator (DTMF GEN) circuit generates the tones for pushbutton dialing and
provides the user-alert tone.

TIMER
The timer circuit is a programmable 8-bit count-down timer. The timer can either countdown once or cycle
continuously. When the count reaches zero, the output changes state.

~TEXAS

INSTRUMENTS
5-108

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
WATCHDOG TIMER
The watchdog timer circuit is started by a write to a location in the microcontroller interface. If the location is not
written to again within the timeout period, the watchdog timer times out and its output changes state. This
change in output resets the telephone microcontroller.
PIO PORT 1 AND PIO PORT 2
PIO port 1 and PIO port 2 are two 8-bit wide programmable ports. Each line of each port can be individually
programmed to be either an input or an output.
KEYBOARD SCAN
The KEYBOARD SCAN port is a 4-bit port that accepts inputs from a keyboard and generates interrupts to the
microcontroller. The port can also be reconfigured as a general purpose I/O (inpuVoutput) port. One 1/0
terminals connected to the telephone ONIOFF key supplies a wakeup signal that terminates the total
power-down mode.
MICRO CONTRL IfF and INTRPT LOGIC
All wide-band and narrow-band data communications are transmitted to and received from the telephone
microcontroller using the microcontroller interface (MICRO CONTRL IIF) circuitry. Internal data, command, and
interrupt registers are programmed using write operations. Other internal data, status, and interrupt registers
are monitored using read operations.

microcontroller interface operation
Sampling of input data occurs on the rising edge of DCLK, and changes in output data occur on the falling edge.
DCLK may begin and end in either the high or low state. Operation of the microcontroller interface may be
achieved in software using the microcontroller general purpose 1/0 terminals. Alternatively, it may be noted that
the timing diagram, shown in Figure 21, is compatible with a 2-byte transfer using a peripheral having an SPI
(serial peripheral interface) when operating in CPOL = 1 and CPHA = 1 modes. This timing is also compatible
with clock-synchronous transfers from the general-purpose 8-bit UART (universal asynchronous
receiver-transmitter), when an additional microcontroller 1/0 port is used to generate the CS signal. In the latter
case, the duration of the eighth clock pulse shown can be increased, so that two consecutive 8-bit writes can
be used for a TCM8030 write operation, or a consecutive 8-bit write and an 8-bit read can be used for a TCM8030
read operation.
The DATAOUT terminal has a 3-state driver and normally presents a high impedance, as indicated in Figure 2.
This allows the both the DATAIN and the DATAOUT pins to be connected to a bidirectional microcontroller pin .

•
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-109

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TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
write
For a write operation, the CS input is taken low and data on DATAIN is clocked into the TCM8030 on each rising
edge of DCLK, Figure 21. The input sequence is start bit (logic 1), 7-bit address, and then eight bits of data.
The address and data to be written to control the TCM8030 and to transmit Manchester-encoded signals are
detailed in the write address map given in Table 2. Eight bits of data are always written to the interface and the
data is right justified.
For those write operations to addresses that have less than eight significant data bits, it is necessary to supply
the full complement of eight data clock cycles on DCLK, although the state of DATAIN during these
nonsignificant write data clock cycles is not important.

L
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WRITE

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DATAIN

Start Bit

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~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-111

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Write Address Map (continued)
HEXADECIMAL
ADDRESS
(7 BITS)
1C
1O-1F

:a
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m

NO. OF
SIGNIFICANT
BITS

DEFAULT
VALUE
(HEX)

Enable event monitoring on P13, set
sense of input

NAME
PI03 interrupt control

PI31NT

FUNCTION

Not used

RXRF idle mode timer

RXRFTIM

RXRFTIM, RF power-saving duration

Counter / timer coef.

TIMER

Coefficient and start command

Mismatch

FRAMEMIS

Frame mismatch coefficient wide-band

FOCCdotting

FCCDOT

Detect coefficient -

wide-band

FVC dotting

FVCDOT

Detect coefficient - wide-band

Narrow band error coef.

N8COEF

Allowed narrow-band errors

SATcoef.

SATCOEF

SAT lock determination - wide-band

27-20

Not used

Dataprocessor test control 1

DTEST1

Dataprocessor test control

Auxiliary power enables

AUXPE

Power enables DACs, IFAMP, AMP7
and LSDRIVER

Clock source frequency select

CLKSRC

Frequency of external clock source,
and CLKOUT 3-state enable

Receive audio path config

RXCFG

Receive audio path switch settings

Transmit audio path config

TXCFG

Transmit audio path switch settings

Microphone and TX DTMF trim

VDTRIM

Voice and DTMF trim gain setting

Limiter trim

LIMITER

Limiter gain setting

Transmit SAT trim

SATTRIM

Transmit SAT trim gain setting

Transmit data trim

TXDATRIM

Transmit Data trim gain setting

Transmit trim

TXTRIM

Final TX trim gain setting

Receive trim

RXTRIM

Receive trim gain setting

Volume control

VOLCTRL

Loudspeaker volume control

DTMF control

DTMFCTRL

DTMF frequency setting

Analog test modes

ATEST

Analog test mode control

3D-3F

Not used

DAC range select

DACRANGE

DAC range setting

DAC1 data

DAC1DAT

DAC1 input data code

DAC2 data

DAC2DAT

DAC2 input data code

DAC3 data

DAC3DAT

DAC3 input data code

AFCcontrol

AFCCTRL

AFC control

~TEXAS

INSTRUMENTS
5-112

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION

detailed description - write address map (continued)
In the following description for write address registers, a bit position within a register is identified by prefixing
the bit number with its register name. For example, bit 6 of control word 1 in write address 00 is identified as
C1.6.
address 00 -

operational control word 1 (C1)

Control word C1 is composed of eight bits. When a C1 bit is set to 1, the functions shown in Table 3 are
performed (function performed when bit is reset to 0).
Table 3. Control Word 1 (C1) Definition
BIT

FUNCTION
AMPS/(TACS)

Narrow-band mode/(wide-band mode)

Voice channel operation (RVC)/(Control channel operation RECC)

Receive FOCC 8-word/(receive FOCC A-word)

Enable automatic arbitration logic. RXRFEN goes low, TXOUT is disabled on
arbitration fail.

Enable SATOUT output - wide-band
Enable DSAT/DST output - narrow-band

Enable Signaling Tone (ST) generation - wide-band
Enable Digital Signaling Tone (DST) generation - narrow-band

Timer continuously cycles/(stops when it reaches 00 count)

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transmit mode operation

Bits C1.1, C1.2, C1.S and C1.6 of operational control word 1 (C1) in write address 00, together with the control
word TXSUM control bits TXVEN, TXDEN, and TXSEN (write address 33), control the transmit mode of the
TCM8030 as shown in Table 4. No other combination of these control bits should be used.

TXCFG.3
(TXVEN)

TXCFG.4
(TXDEN)

TXCFG.5
(TXSEN)

C1.2'
(RVC

not

WB)

RECC)

C1.5
(SAT!
DSAT

C1.6
(ST!DST)

TRANSMITTED SIGNAL AT TXO TERMINAL

Wide-band data on RECC

Wide-band data on RVC

ST and voice on RVC mixed together at TXSUM

SAT and voice on RVC mixed together at TXSUM

ST and SAT and voice on RVC mixed together at
TXSUM

Narrow-band data and voice on RVC mixed together at
TXSUM

DST and voice on RVC mixed together at TXSUM

DSAT and voice on RVC mixed together at TXSUM

Transmitter muted at TXSUM

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

oa:

a..

Table 4. Transmit Signal Selection
C1.1
(NB

:J
C

5-113

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
arbitration
Table 5 defines how arbitration is controlled and how the RXRFEN terminal is used

Table 5. Operational Control Word 1, Bit 4 Definition C1.4
C1.4
(write addr 00)

RXRFEN TERMINAL

ARBITRATION

Software controlled
Arbitration failure indicated by event bit E1.2
(read address 05) and status bit S1.2 (read address 00)

Always inactive 02)

Hardware controlled
(RF amplifier directly switched off using TXRFEN terminal and
TXOUT disabled on arbitration failure. Also arbitration failure
still indicated by event bit E1 .2 (read address 05) and status bit
S1.2 (read address 00))

Used for arbitration circuit.
Terminal goes active on arbitration failure. Only returns
high after Reset Arbitration command - sense set by
C3.2 (write address 02)

sense set by C3.2 (write address

address 01 - DCC/SAT/DSAT Control Word (C2)

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:D

Control word C2 is seven bits wide. When a C2 bit is set to 1, the functions shown in Table 6 are performed.

Table 6. Control Word 2 (C2) Definition

BIT

C')

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FUNCTION
Digital color code 1st bit (DCC)

Digital color code 2nd bit (DCC)

SAT color code 1st bit (SCC) -

SAT color code 2nd bit (SCC) -

DSAT color code 1st bit (DSCC) -

DSAT color code 2nd bit (DSCC) -

narrow-band

DSAT color code 3rd bit (DSCC) -

narrow-band

Not used

wide-band
wide-band
narrow-band

digital color codes (DCC)
The DCC control bits result in the sequences shown in Table 7 being included in the transmitted RECC
message.

Table 7. Digital Color Codes CONTROL WORD 2

narrow-band

TRANSMITTED CODE

BIT1

BITO

0000000

001 1 1 11

1100011

11 1 1100

"TEXAS
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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
SAT and DSAT circuit operation
SAT reception - wide-band
A digital phase-locked loop locks onto the received SAT signal when it is in the frequency band corresponding
to the SAT color code (SCC) bits as shown in Table 8.

Table 8. SAT Color Codes - Wide-band
CONTROL WORD 2
BIT3

BIT2

SAT FREQUENCY BAND

5955 Hz < f < 5985 Hz

5985 Hz < f < 6015 Hz

6015 Hz < f < 6045 Hz

Transmit test

When the input frequency is not in the expected band, the invalid SAT status flag, S1.6 (read address 00) is set.
Note that the SAT status flag is high when the SAT circuit is initialized. Initialization occurs when entering
wide-band voice channel mode and also when control word 2 is rewritten; however, the phase of the
regenerated SAT is not disturbed.
The associated event flag E1.6 (read address 05) is set when the SAT status changes from valid to invalid, when
it changes from invalid to valid, and also on the first SAT evaluation after initialization. This event generates an
interrupt if the mask bit IE1.6 (write address 05) is set.
SAT lock status is evaluated over a 0.1 second interval to avoid the occurrence when the reference and input
signals are only temporarily in phase. A programmable coeffiCient, SATCOEF in write address 26, controls the
evaluation of lock status.

3=
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SAT transmission - wide-band
The SAT circuit always generates a valid SAT within the band defined by the written SCC, independently of the
received signal. The microcontroller must turn off the SAT by resetting bit = 0 of C1.5 (write address 00), after
a lost SAT event occurs. The exact SAT frequency transmitted depends on the state of the SAT comparator
output:
1.

When a SAT is received that is outside the the SCC band, the transmitted SAT is within ±15 Hz of the center
frequency of the band. It is not steady. Typically it alternates between + 15 Hz and -15 Hz.

When no SAT signal is received at all and the SAT comparator output is at logic 0, the transmitted SAT is
within the range ±1 Hz of the SCC center frequency. This situation is detected and the invalid SAT flag is
set high.

Because a valid SAT within the SCC band is always transmitted, all three SAT frequencies can be generated
during the production test of the telephone simply by writing the correct bits in C2.2+3 SCC as shown in Table 8.
When there is no received signal, the SAT output is within ±1 Hz of the SCC center frequency. In addition, when
SCC is set to 11, a 6-kHz test frequency is generated that is unaffected by any received signal and does not
attempt to lock onto it.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-115

a:
a.

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
DSAT reception - narrow-band
In narrow-band mode (C1.1 =1, write address 00) the received signal is continuously compared with the DSAT
word corresponding to the DSAT Color Code (DSCC) bits as shown in Table 9.

Table 9. DSAT Color Codes - Narrow-band
CONTROL WORD 2

"tJ

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-I
"tJ

BITS

BIT4

2556C8

255828

256A98

25AD4D

26A828

2682AD

2969A8

AAAAAA

A DSAT word is regarded as correctly detected and the receiver is locked onto the voice channel when the
number of errors is less than or equal to that written to the NBCOEF register (write address 25). When the DSAT
is not detected, the invalid DSAT status flag, S1.6 read address 00, is set to 1. The DSAT status flag is high when
the DSAT circuit is initialized. The DSAT circuit is initialized after entering narrow-band mode and also whenever
C2 is written. The associated event flag E1.6 (read address 05) is set whenever the status has changed from
valid to invalid or from invalid to valid, and also after the first evaluation, which takes place 0.12 seconds after
the circuit is initialized. This event generates an interrupt when the mask bit IE1.6 (write address 05) has been
set.

m
!:5
m

DSATWORD

BIT6

The base station stops DSAT transmission when data is transmitted. The effect of this on DSAT determination
is discussed in topic MRI (mobile-reported interference) operation and read address 25 narrow-band error rate
(NBERRS).

DSAT transmission - narrow-band
The DSAT circuit always generates the DSAT corresponding to the DSCC, independently of the received DSAT.
It is up to the microcontroller to turn the DSAT off by writing 0 to C1.5 (write address 00) after a lost DSAT event
occurs.
Control bit C1.6 (write address 00) determines whether DSAT or DST is output. When this bit is set high, DST
is generated instead of DSAT. DST is simply the inverted DSAT. The transition from DSAT to DST and vice-versa
only takes place at specific places in the code sequence, as defined by the NAMPS/NTACS specifications. The
switching point is handled automatically.
During the production test of the telephone, all DSATs can be transmitted even when no DSAT is received .

•
TEXAS
INSTRUMENTS
5-116

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION

address 02 - signal polarity selection (C3)
The signal polarity selection control word (C3) is four bits wide. The functions when bit positions are set high
or low are shown in Table 10.

Table 10. Signal Polarity Selection Control Word (C3) Definition
BIT

FUNCTION

When cleared 0, = normal logic: RXIN data zero = logic low, RXIN data one = logic high
When set to 1, = inverted logic: RXIN data zero = logic high, RXIN data one = logic low

When cleared 0, = normal logic: TXO data zero = logic low, TXO data one = logic high
When set to 1, = inverted logic: TXO data zero = logic high, TXO data one = logic low

When cleared 0, = TXRFEN and RXRFEN are active high (high = arbitration failure/RXRF idle mode active)t
When set to 1, = TXRFEN and RXRFEN are active low (low = arbitration failure/RXRF idle mode active)t

When cleared 0, = INTRPT is active high (high = interrupt valid)
When set to 1, = INTRPT is active low (low =interrupt valid)

4-7

Not used

t TXRFEN and RXRFEN have open-drain output drivers. These terminals have active pulldowns, and require external pullups.

address 03 -

master power enables (C4)

This register controls the operation of the different power modes as shown in Table 11. When a bit in this register
is set to 1, a section of the TCM8030 is powered up. After a RESET, only bit 0 is enabled so that the device is
initially in shutdown mode. To disable sections of the TCM8030, a 0 is written to the appropriate bit.

Table 11. Master Power Enables (C4) Definition
BIT

FUNCTION

Power up of CLOCK (TCXOAMP, XTALOSC and PROGDIV). When clock is powered down (0 in this bit), all circuits in the
data processor and PIO ports are also off. Only the keypad port remains active to receive an external power key-press.
Reset state is 1 so that the TCM8030 powers up in shutdown mode.

Security bit. Reset to O. It must always be the inverse of C4.0 and must be set to 1 at same time as C4.0 is reset to 0 to enter
total power-down mode.

FOCC data reception enabled. Reset to O.

DTMF generator and DTMF receive path enabled. Reset to O.

Transmission circuits for speech, data, SAT/DSAT, and ST/DST, and receive circuit for speech enabled, reset to O.

5-7

Not used

TCM8030 power modes
The following bits should be written to register C4 to specify one of the six TCM8030 power modes as shown
in Table 12.

Table 12. Power Modes (C4) Definition
POWER MODE

C4.4

C4.3

C4.2

C4.1

C4.0

Shutdown mode

Idle mode

Tone mode

Full operation mode, DTMF TX off

Full operation mode, DTMF TX on

Total power-down mode

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

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5-117

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a.

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
independent circuits
The IFAMP, DACs 1 - 3, and AMP? blocks can be individually powered down as described for the auxiliary
power enable (AUXPE) register (write address 30). These bits are overidden and all circuits powered down in
total power-down mode.

address 04 - FOCC/FVC optional controls (C5)
The FOCC/FVC operational control word C5 is four bits wide. The function of each bit depends on its value
(0 or 1) as shown in Table 13.

Table 13. Operational Control Word 5 (C5) Definition
BIT
0

-c

4-7

FUNCTION

o = One busy/idle bit examined to detect busy/idle status
1 =Two busy/idle bits examined to detect busy/idle status
o = Maximum of eleven FVC word repeats used - wide-band
1 = Maximum of five FVC word repeats used - wide-band
o =Auto muting is enabled when transmitting and receiving a message on voice channel - wide-band
1 = Auto muting is disabled when transmitting and receiving a message on voice channel- wide-band
o = RXRF idle mode disabled
1 = RXRF idle mode enabled
Not used

-I

address 05 - interrupt control word 1 (IE1)

-C

The interrupt control word 1 (IE1) is seven bits wide. The function of each bit when set to 1 is as shown in
Table 14.

::D

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Table 14. Interrupt Control Word 1 (IE1) Definition

BIT

FUNCTION

RX data available

TX buffer available

Arbitration failure

TX sequence completed

Change of RECC busy/idle status

Counter/timer reaches zero state

Wide-band SAT/narrow-band DSAT status changed

Not used

~TEXAS

INSTRUMENTS
5-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 06 -

interrupt control word 2 (IE2)

The interrupt control word 2 (IE2) is eight bits wide. The function of each bit when set to 1 is shown in Table 15.

Table 15. Interrupt Control Word 2 (IE2) Definition
BIT

FUNCTION

FOCC data changed, (different from previously received word)

FVC dotting detected - wide-band

FVC frame sync achieved (wide-band word sync/narrow-band sync word received)

Change of FOCC frame sync status

Change of RXRF idle mode power-saving status

NRZ error count register (NBERRS) updated -

PI03 input port signal sensed

AFC has reached terminal count

narrow-band

address 08 - commence TX (TXSTART)
A write operation (the data is not significant) to this address transfers data from the transmit buffer to the transmit
encoder and starts the encoding and transmission of the data.

address 09 - start watchdog (WDSTART)
A write operation (the data is not significant) to this address starts one cycle of the watchdog timer. Unless
restarted, the watchdog times out in 1.5 to 1.6 seconds. Timeout is indicated by the WDOUT output terminal
going low for 100 ms. The TXRFEN terminal is also disabled until the next chip reset or WDSTART command
occurs.

....(.)
~

address OA - abort TX (TXABORT)
A write operation (the data is not significant) to this address immediately stops a transmission sequence that
is in progress.

address OB - clear TX buffer (TXCLEAR)
A write operation (the data is not significant) to this address clears the contents of the transmit buffer. This
prevents the contents from being transmitted from the end of the transmission of a word that is currently in
progress (known as following on).

restart frame sync (FRAMESYNC)

A write operation (the data is not significant) resets the data recovery circuit to achieve bit synchronization to
the received data. It can be used when the telephone switches to a new forward control channel (FOCC) to
reduce the time taken to acquire bit synchronization. The data recovery circuit does not have to wait until it has
detected loss of bit synchronization to change to fast-lock mode .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The WDSTART command should be given at intervals of 1.4 seconds or less.

address OC -

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5-119

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a.

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address OD -

reset (RST)

A write operation (the data is not significant) to this address performs a chip reset. Its function is identical to that
of the RESET input terminal, except that it does not affect the WDOUT terminal. The default values listed in the
write address map are loaded.

address OE -

reset arbitration (ARBITRST)

A write operation (the data is not significant) to this address resets the arbitration circuit. After an arbitration
failure, this command must be sent to re-enable the transmission of data.

address 10 - TX data word 0 (TXDO)
This register contains the transmitted data bits 35 to 28 (bit 35 is the MSB).

address 11 - TX data word 1 (TXD1)
This register contains the transmitted data bits 27 to 20 (bit 27 is the MSB).

-c

o
c
c
o

address 12 - TX data word 2 (TXD2)
This register contains the transmitted data bits 19 to 12 (bit 19 is the MSB).

address 13 - TX data word 3 (TXD3)

-I

This register contains the transmitted data bits 11 to 4 (bit 11 is the MSB).

-C

address 14 - TX data word 4 (TXD4)
This register contains the transmitted transmit data word 4, bits 4-7 as shown in Table 16.

Table 16. Transmit Data Word 4 (TXD4) Definition

BIT
3-0

FUNCTION
Not used

TXdata bitO

TXdata bit 1

TXdata bit2

TX data bit 3

The data to be transmitted is written to 5 addresses (10 -14), and this loads the transmit buffer. Data word TXD4
is the least significant byte and should be written last.

~TEXAS

5-120

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 15,17,19 -

PIO control words (PIOC1, PIOC2, PIOC3)

These control words select whether the individual terminals of the port are configured as inputs or used as
outputs as shown in Table 17.

Table 17. PIO Control Words (PIO C1,2,3) Definition
VALUE

CORRESPONDING TERMINAL FUNCTION

Input

Output

The eight terminals (four for PI03) of the port are configured as inputs by default.

address 16,18,1 A -

PIO output words (P01, P02, P03)

This sets the state of the PIO terminals that are configured as outputs.

address 1B -

PI03 pullup enables (PI3PULL)

When set to 1, bits 0 to 3 of this register activate a small pullup transistor. The pullup allows the inputs to be driven
by open-drain drivers. After reset, the ports are configured as inputs and the PI03 pullups are enabled.

address 1C -

PI03 interrupt control (PI3INT)

c.
t-

FUNCTION

PI03 operates as normal port

Signal sensed on PI31NT causes interrupt when IE2.6 is
high. (Note: The port may still be read at address 20 in this
mode)

::l
C

Table 19. PI03 Interrupt Control (PI3INT bits 7-4) Definition

address 20 -

FUNCTION

PI31NT BIT(4-7)

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Table 18. PI03 Interrupt Control (PI3INT, bits 3-0) Definition
PI31NT BIT(o-3)

3:
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Active low interrupt

Active high interrupt

RXRF idle mode timer (RXRFTIM)

Writing to this 6-bit address sets the duration of RXRF idle (RF receiver powered down) mode. In RXRF idle
mode, the RF receiver may be powered down for part of the FOGG data frame using the RXRFEN terminal. This
should only be used in good signal conditions when multiple repeats of the word are not required.
The default value of 2Bh ensures that the receiver has five bit periods within which to power up before the start
of the dotting sequence of the next frame. For AMPS, a bit period is 0.1 ms; for TAGS, it is 0.125 ms. The timer
is clocked at the bit rate divided by 8. For example, RFRXTIM = 2 A allows the receiver up to 15 additional8-bit
periods in which to stabilize before the start of dotting .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-121

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

address 21 - counter I timer coef (TIMER)
Writing to this address sets the count length and starts the counter. The timer counts in units of 12.8 ms, giving
a maximum time interval of 3.264 seconds (255 counts). A TMZERO terminal and status bit 81.5 indicate the
timer status. When the timer is counting, TMZERO and 81.5 are low, but when the timer reaches zero, they go
high and stay high until TIMER is written again unless C1. 7 is high, to indicate recycling mode. In recycling mode,
the timer automatically reloads the count coefficient and starts the count again so TMZERO and 81.5 is only
low for 12.8 ms. In the recirculating mode, with timer set to 255, the output would be low for 255 counts and high
for 1 count, giving an overall period of 256 counts.
The timer can be stopped either by a chip reset or by writing 00 to TIMER. This causes TMZERO signal and
81.5 to stay low. (Note that after sending the start command there is a latency of 12.8 ms before the timer is
loaded.)
When IE1.5 (write address 05) is set, an interrupt is generated when the counter reaches zero.

address 22 - mismatch wide-band (FRAMEMIS)
This is the number of invalid wide-band word syncs that are allowed during data recovery on both FVC and
FOCC before bit synchronization with the dotting pattern is restarted.

"'C
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o
C

address 23 - FOCC dotting coefficient (FCC DOT) -

wide-band

This is a coefficient for the data recovery circuit and sets how much of the dotting preamble of the FOCC data
is required before it is accepted that bit synchronization has been achieved. It applies only to wide-band mode.

-I
"'C

address 24 - FVC dotting coefficient (FVCDOT) -

:rJ

This is a coefficient for the data recovery circuit and sets how much of the dotting preamble of the FVC data
is required before it is accepted that bit synchronization has been achieved. It applies only to wide-band mode.

::sm

wide-band

address 25 - allowed narrow-band errors (NBCOEF) -

narrow-band

This register defines how many errors are allowed in the detection of the D8AT and 8YNC words as shown in
Table 20. When errors are received in a D8AT word that exceed the error threshold, the D8AT is assumed to
be lost and the event bit E1.6 (change in D8AT status) is set. When a 8YNC word is transmitted, but the number
of errors exceeds the error threshold, then the 8YNC word and the data following it are not recognized. Even
when the SYNC word is correctly detected, a bad D8AT status is reported. This is cleared when 24 bits of D8AT
have been received following the data word (up to 1.6 seconds from the time the D8AT went bad).

Table 20. Narrow-Band Error Coefficient Setting
MAXIMUM BIT
ERRORS
ALLOWED

MAXIMUM BIT
ERRORS
RECOMMENDED

BITS

FUNCTION

0-3

DSATERRS

Not used

6-4

SYNCERRS

Not used

DEFAULT

The two error coefficients are initialized to a on reset. They may be set to any value up to and including 6. It is
recommended, however, that the D8AT and 8YNC word-error thresholds do not exceed 3 and 4, respectively,
as these values correspond to the maximum bit error rates documented in the NAMP8 specification.

~TEXAS

5-122

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 26 - SAT lock determination (SATCOEF) - wide-band
The SAT PLL attempts to lock onto the incoming signal when it is a coherent signal within ±15 Hz of the SCC
center frequency. SAT lock is determined over a 0.1-second interval, during which time there is approximately
600 cycles of the regenerated SAT. The input and output signals are compared, and when they are out-of-phase
an error counter is incremented. When the counter reaches the value defined by SATCOEF (Table 21), an
invalid SAT is indicated immediately on status bit S1.6 (read address 00). When the counter does not reach the
threshold by the end of the 0.1-second period, a valid SAT is indicated.
When the received SAT is different from the SCC, lock cannot not be obtained. The input and reference signals
beat in and out of phase. They are out of phase 50% of the time, so approximately 300 errors can be expected.
The absence of a signal is also detected. The number of times that the input is held high or low for a whole cycle
is counted, halved, and then added to the error counter.
To allow a safety margin, the error counter only goes up to the default error threshold of 255. It should not be
necessary to lower the threshold; however, some programmability has been provided. The lower nibble of error
threshold is hardwired to Fh and the upper nibble can be programmed using the SATCOEF register. It is also
possible to enable/disable the counting of the two error types that have been discussed.

Table 21. SAT Lock Control Definition
SATCOEF BIT

0-3

address 2E -

FUNCTION
Errors required to loose lock (ms nibble)

DEFAULT
Fh

Phase error counting enabled

5 .

No-signal error counting enabled

data processor test control 1 (DTEST1)

To facilitate production testing of the data processor, PIO ports 1 and 2 can be used to control and observe
internal blocks. Port directions must be set as input and output respectively by writing to the direction control
register PIO C1 and PIO C2 (write addresses 15 and 17).
To select a test mode, set the appropriate bit of the test register to 1 as defined in Table 22. When more than
one test mode is selected, then control using PI01 affects all test modes simultaneously, but data can be
observed from one test mode only. The selected test mode that is the least significant bit of DTEST1 is the one
that is observed on PI02.

Table 22. TCM8030 Data Processor Test Modes
DTEST1
BIT

TEST MODE

Reserved

Data Recovery Observation

3-7

Reserved

The detailed description of each test mode is shown in Table 23.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-123

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
Table 23. Data Recovery Observation (DTEST1.2
PI02
BIT

=1)

INFORMATION OBSERVED ON PI02 OUTPUTS
WHEN DTEST1.0 IS SET TO 1

NRZ narrow-band data and wide-band data before Manchester decoding.
(e.g., Manchester-encoded 1 is seen as 0 followed by 1)
200 Hz (narrow-band); 16 kHz (TACS); 20 kHz (AMPS).

NRZ clock -

Decoded Manchester data. (e.g., 01 or 10 input sequences output as 1 or 0)

Clock-100 Hz (narrow-band), 8 kHz (TACS), 10kHz (AMPS)

4-7

Reserved

address 30 - auxiliary power enables (AUXPE)
This register is used to independently enable (bit is set to 1) or power down (bit is set to 0) the DACs, AMP?
(uncommitted op amp), IFAMP, and LS DRIVER blocks as shown in Table 24.
Table 24. Auxiliary Power Enables (AUXPE) Definition

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BIT

NAME

FUNCTION

DAC1EN

DAC1 enable

DAC2EN

DAC2 enable

DAC3EN

DAC3enabie

AMP7EN

AMP7 (uncommitted op amp enable)

IFAMPEN

IFAMP enable

LSDRIVEREN

LSDRIVER enable. The LS driver is powered off
independently when both bits C4.3 and C4.4 are low
(see write address 3). Differential or single-ended
operation is selected by bit RXCFG.7, write address 32.

-I

""C
:IJ

:s:m

address 31 - clock source frequency select (CLKSRC)

The TCM8030 can be clocked from one of the following frequency sources selected by the first three bits in the
CLKSRC register as shown in Table 25 (refer to Table 1 also).
Table 25. External Clock and Crystal Frequency Select
BIT

NAME

CKRTO

CKRT1

CKRT2

CLKOUTSEL

FREQUENCY

CKRT (bits 2-D)
000: 5.12 MHz, 001: 7.68 MHz, 010: 10.24 MHz, 011: 12.80 MHz
100: 15.36 MHz, 101: 17.92 MHz, 110: not allowed, 111: not allowed
When cleared to 0 the CLKOUT terminal active; when set to 1: CLKOUT terminal

~TEXAS

INSTRUMENTS
5-124

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=hi-Z

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 32 -

receive-audio path configuration (RXCFG)

The RXCFG register configures the receive audio path switches. The receive audio path is automuted at
REC1 SW during the reception of wide-band data on FVC when automuting is enabled with a 0 to CS.2 (write
address 4) as shown in Table 26.

Table 26. Receive-Audio Path Configuration (RXCFG) Control
BIT

NAME

EBSW

FUNCTION

REC1SWO

REC1SW1

RECSUM

Side-tone switch and summing block (RECSUM) = 0: STI switched out
1: STI summed in

RECBUFO

REC1 and REC2 configuration (REC2SW) =

RECBUF1

Expander bypass switch. 0 = Expander connected, 1 = Expander bypassed
Receive path switch REC1 SW =

00: Mute
11 : forbidden
10: CTI input
01: Expander (or bypassed Expander) output

00: REC1 mute, REC2 mute
01: REC1 connected, REC2 mute
10: REC1 mute, REC2 connected

3:
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11: REC1 and REC2 differential

LSOPBIAS

DIFFSIGSEL

Independent loudspeaker VMID output bias control on RECN and RECP terminals.
1 = RECN and RECP outputs are biased to VMID internally,
o = RECN and RECP outputs must be biased externally.
Note that in power-off mode, the LS output biases are automatically
switched off.

a:
a.

LSDRIVER differential/single-ended control
0: single-ended output
(Only RECN output active, RECP output powered down),
1: RECN and RECP form differential outputs

:::J

address 33 - transmit-audio path configuration (TXCFG)
The TXCFG register is six bits wide and configures the transmit-audio path switches as shown in Table 27. The
audio transmit path is automuted at the TXSUM functional block during the transmission of wide-band data on
RVC, when automuting is enabled with a written to CS.2 (write address 4).

Refer to Table 2 at write address 00 to configure different transmit modes using the last three bits in this register
and the control bits in operational control word 1 (C1), write address o.

Table 27. Transmit-Audio Path Configuration (TXCFG) Control
BIT

NAME

TXSWO

TXSW1

FUNCTION
TX audio source. TXSW =

11: DTI
10: AMP2 Select
01: AMP1 Select
00: Mute

CBSW

Compressor bypass

0: Compressor connected
1: Compressor bypassed

TXVEN

TX voice enable at TXSUM,

TXDEN

TX data enable at TXSUM,

o = Mute, 1 = Enable
o = Mute, 1 = Enable

TXSEN

TX SAT enable at TXSUM,

0= Mute, 1 = Enable

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-125

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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 34 - microphone and TX DTMF trim (VDTRIM)
The VDTRIM register is four bits wide and sets the VDTRIM stage gain for microphone and/or TX DTMF level
trim as shown in Table 28.

Table 28. Microphone and TXDTMF Trim (VDTRIM) Adjust

"'C

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o
C
C

V03

V02

VOl

VOO

NOMINAL GAIN (dB)

-4.30

-3.74

-3.20

-2.65

-2.12

-1.58

-1.06

-0.53

0.53

1.05

1.58
2.12

o-I

2.65

3.14

"'C

3.74

:JJ

=:s

~TEXAS

INSTRUMENTS
5-126

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 35 -

limiter trim (LIMITER)

The LIMITER register is four bits wide and sets the limiter deviation as shown in Table 29.
Table 29. Limiter Trim Adjust
DIFFERENCE FROM
NOMINAL LIMIT
LEVEL (dB)

L1M3

LIM2

LIM1

LIMO

-5

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

3:
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0.5

1.5

I-

2.5

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oa:

•
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-127

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 36 - transmit SAT trim (SAT TRIM)
The SAT TRIM register is four bits wide and sets the SAT TRIM gain as shown in Table 30.

Table 30. Transmit SAT TRIM Adjust
SAT3

SAT2

SAT1

SATO

NOMINAL GAIN (dB)

-2.28

-1.97

-1.67

-1.36

-1.06

-0.76

-0.45

-0.15

0.15

"'tJ

0.45

0.76

1.06

1.36

o-I

1.67

1.97

2.29

"'tJ

address 37 - transmit data trim (TXDATRIM)

The TXDATRIM register is three bits wide and sets the TX data trim levels as shown in Table 31.

<
-m

Table 31. Transmit Data Trim (DXDATRIM) Adjust

DAT2

DAT1

DATO

NOMINAL GAIN (dB)

-2.28

-1.82

-1.21

-0.6

0.6

1.21

1.82

~TEXAS

INSTRUMENTS
5-128

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 38 - transmit trim (TXTRIM)
The TXTRIM register is five bits wide and sets the TXTRIM stage gain, the final stage in the TX path as shown
in Table 32.
Table 32. Transmit Trim (TXTRIM) Adjust
NOMINAL GAIN (dB)

TXT4

TXT3

TXT2

TXT1

TXTO

-4.37

-4.08

-3.8

-3.5

-3.24

-2.97

-2.7

-2.42

-2.15

-1.88

-1.61

-1.34
-1.07

-0.8

-0.54

-0.27

0.27

0.53

0.8

1.07

1.34

1.61

1.88

2.15

2.42

2.69

2.97

3.24

3.52

3.8

4.08

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TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-129

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 39 - receive trim (RXTRIM)
The RXTRIM register is four bits wide and sets the RX TRIM stage gain as shown in Table 33.

Table 33. Receive Trim (RXTRIM) Adjust

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RXT3

RXT2

RXT1

RXTO

-4.3

-3.74

-3.2

-2.65

-2.12

-1.58

-1.06

-0.53

0.53

1.05

1.58

2.12

2.65

3.14

3.74

NOMINAL GAIN (dB)

address 3A - loudspeaker volume control (VOL CTRL)
The VOL CTRL register is four bits wide and sets the loudspeaker volume as shown in Table 34.

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Table 34. Loud Speaker Volume Control (VOL CTRL) Adjust
VOL3

VOL2

VOL1

VOLO

-20

-17.5

-15

-12.5

NOMINAL GAIN (dB)

-10

-7.5

-5

-2.5

2.5

7.5

12.5

17.5

~TEXAS

INSTRUMENTS
5-130

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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 38 -

DTMF control (DTMFCTRL)

The DTMFCTRL register is six bits wide. Bits 0 through 4 select the DTMF generator output as shown in
Table 35.
Table 35. DTMF Tone Output Control
KEY

DTMF4

DTMF3

DTMF2

DTMF1

DTMFO

LOW TONE (Hz)

697

HIGH TONE (Hz)

1209

697

1336

697

1477

770

1209

770

1336

770

1477

852

1209

852

1336

852

1477

941

1209

941

1336

941

1477

697

1150

770

1150

852

1150

941

1150

Off
Off
Off
Off

697

770

852

941

Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off

II:

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1150
1209
1336
1477
1633
2048

Off
Off
Off
Off
Off
Off

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-131

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
Bit 5 of the DTMF, control word 1 bits 0 and 1, selects DTMF mode control. The levels of the DTMF tones and
a 2-dB level skew between the high tones and low tones is set according to the control bits as shown in Table 36.

Table 36. DTMF Mode Control
CONTROL
WORD 1
(WRITE ADDR 0)
BITO

CONTROL
WORD 1
(WRITE ADDR 0)
BIT1

DTMF
CONTROL WORD
(WRITE ADDR 3B)
BIT5
MODCTRL

SYSTEM

TAGS

Not allowed

1.734 Vpp .

AMPS

AMPS levels
(skew off)

1 Vpp

2Vpp

AMPS

Not allowed

1 Vpp

2Vpp

AMPS

NAMPS levels
(skew off)

AMPS

Not allowed

address 3C - analog test modes (ATEST)
To facilitate testing of the TCM8030, the REC1 and REC2 outputs can be reconfigured to observe internal
analog signals. This register is reset to 0000 and should not be written to during normal operation.

S
m

SIGNAL LEVEL AT
DTO (3 V SUPPLY)
PER TONE

address 40 - DAC range select (DACRANGE)
The DACRANGE register is three bits wide and sets the range of each DAC (address 41 - 43) as shown in
Table 37.

Each DAC can be independently set to full or half range. For full range, the step size is TXVDD/256 and for half
range the step size is TXVDD/512. Register AUXPE, at address 30, is used to independently power up or down
each DAC. Each DAC has its own address to which the conversion word is written as described in the following
paragraphs.

Table 37. DAC Range Select (DACRANGE) Definition
BIT

NAME

DAG1XO

DAC1 range select. 0 =TXVDD/2, 1 =TXVDD

FUNCTION

DAG2X1

DAC2 range select. 0 =TXVDD/2, 1 =TXVDD

DAC3X2

DAG3 range select. 0 =TXVDD/2, 1 = TXVDD

address 41 - DAC1 data (DAC1 DAT)
Input data register for the first DAC (DAC1).

address 42 - DAC2 data (DAC2DAT)
Input data register for the second DAC (DAC2) .

•
TEXAS
INSTRUMENTS
5-132

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 43 -

DAC3 data (DAC3DAT)

Input data register for the third DAC (DAC3).

address 44 - AFC control (AFCCTRL)
The AFCCTRL register is five bits wide. The first four bits set the AFC cycle and the fifth bit, AFCSTART, starts
an AFC measurement cycle as shown in Table 38.

Table 38. AFC Control
BIT

NAME

AFCTERMO

AFCTERM1

AFCTERM2

AFCTERM3

AFCSTART

FUNCTION

AFCTERM (bits 3-0)

=4 bits set terminal count of AFC cycle

AFC start/stop. When AFCST = 1: start AFC count,
when AFCST = 0: stop AFC count.

The AFC measurement cycle begins when the AFCSTART bit (bit 4) is set. When the TCXO count reaches the
terminal value set by the AFCTERM (bits 0-4) bits, the count is stopped, the AFC event bit E2.7 (read
address 06) is set, and when the AFC interrupt mask bit IE2.7 (write address 06) has been set, an interrupt is
generated. The microcontroller can then read the 20-bit terminal count of the IF-2 counter at AFCIF1, AFCIF2,
and AFCIF3 (read addresses 43 to 45).
The start bit AFCSTART is reset automatically when the terminal value is reached. When AFCSTART is low the
counter is stopped - not reset. Reading the terminal count when AFCSTART is low causes the counters to reset
after the read of AFCIF3. Reading the counters when AFCSTART is high does not cause a reset, but the serial
reading process means the data may not be reliable.
Note also that IFAMP must be powered-up with bit AUXPE.4 set (write address 30) before the AFC function can
start.

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-133

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
read
Figure 22 shows the microcontroller read timing diagram.
For a read operation, the start bit is bit O. Following the seven address bits, the DATAOUT terminal is enabled
and the output data is updated on each falling edge of DCLK. The DATAOUT terminal returns to a high
impedance state when CS goes high. During the read operation, 8 bits of data are output on DATAOUT in the
order bit 7 to bit o. The address and meaning of the data read from the TCM8030 using the microcontroller
interface is shown in the read address map (Table 39.) The data is right justified.

L
READ

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DATAIN

\ ,1 " " ' _ _ _ _ _ _ _ _ _ _ _ _ __
Start Bit

c::
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.1..

Read Address

D~O~------------------

14------ Read Data - - - - . t

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Figure 22. Microcontroller Interface Read Timing Diagram

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~TEXAS

5-134

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
Table 39. Read Address Map
HEXADECIMAL
ADDRESS
(7 BITS)

NAME

FUNCTION

NUMBER OF
SIGNIFICANT BITS

Status word 1

Status word 2

02-04

Not used

Event register 1

Event register 2

07-0F

Not used

RX data word 0

RXDO

RX bits 27 - 20

RX data word 1

RXD1

RX bits 19 -12

RX data word 2

RXD2

RX bits 11-4

RX data word 3 (Bits 7 - 4)

RXD3

RX bits 3 - 0 and error correction status

14-15

PI01 status word

PI1

State of PI01 terminals

PI02 status word

PI2

State of PI02 terminals

PI03 status word

PI3

State of PI03 terminals

RXRPT

Number of word repeats used for the
majority voting - wide-band

18-21
22
26-42

Not used

->W
W

Not used
RX repeat count

Not used

Narrow band error rate

NBERRS

Number of DSAT and SYNC bit errors in the
last 200 received bits - narrow-band

AFC term count most
significant nibble

AFCIF1

Termination count of IF-2.
most significant byte

AFC term count middle byte

AFCIF2

Termination count of IF-2. middle byte

AFC term count
least significant byte

AFCIF3

Termination count of IF-2.
least significant nibble

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-135

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

,
detailed description - read address map
In the following descriptions for the read address registers, a bit position within a register is identified by prefixing
the bit number with its register name. For example, bit 1 of event register 1 (read address 05) is identified
as: E1.1.

address 00 - status word 1 register (51)
The 81 register is seven bits wide and the status of each bit, when it is set to 1, is shown in Table 40.

Table 40. Status Word 1 (S1) Definition

BIT

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STATUS

RX data available

TX buffer available

Most recent TX aborted OR arbitration-wi de-band failure

TX encoder active

RECC busy (not idle)

Counter/timer at zero state

Received wide-band SAT {narrow-band DSAT does not match the value defined in register C2. This bit is initially high during the first evaluation.

address 01 - status word 2 register (52)

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The 82 register is eight bits wide and the status of each bit, when it is set to 1, is shown in Table 41.

Table 41. Status Word 2 (S2) Definition

m
S

BIT

STATUS

Last two FOCC words differ

Not Used

FVC message being received

In FOCC frame sync

RXRF idle mode power saving active

Not Used

~TEXAS

INSTRUMENTS
5-136

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION

address 05 - event register 1 (E1)
The E1 register is seven bits wide and the status of each bit, when it is set to 1, is shown in Table 42.
Table 42. Event Register 1 (E1) Definition
BIT

STATUS SINCE PREVIOUS READ OF THIS WORD

RX data available

TX buffer available

Arbitration failure

TX sequence completed

Change of FOCC busy/idle status

Counter/timer reaches zero state

Wide-band SAT/narrow-band DSAT status changed. This always changes after
the first evaluation.

These flags indicate which event(s) have occurred since the previous read, regardless of their associated
interrupt control bits. Event registers are cleared following a read. Since there are two registers, the following
protocol takes place:
1. The microcontroller addresses E1.
2.

The INTRPT terminal goes low, the contents of both interrupt registers are transferred to buffers and the
registers are cleared and are then ready to catch new events.

The serial microcontroller interface clocks out the buffered event information.

Any new events are caught in the main interrupt register; however, at this time INTRPT remains low.

The microcontroller addresses E2.

The buffered E2 information, caught in step 2, is clocked out.

Once the read is completed, INTRPT goes high if any interrupts occurred during steps 2 through 6. The
event register now contains all the events that occurred during the read process.

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NOTE

Always read both E1 and then E2 in order. Reading only E1 results in the events being queued until
E2 is eventually read.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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5-137

oa:

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TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 06 - event register 2 (E2)
The E2 register is eight bits wide and the status of each bit, when it is set to 1, is shown in Table 43.
Table 43. Event Register 2 (E2) Definition
BIT

FVC dotting detected -

FVC frame sync achieved (wide-band word sync/narrow-band sync word)

Change of FOCC frame sync status

Change of RXRF idle mode power-saving status

NRZ error count register (NBERRS) updated -

PI03 input port-sensed signal

AFC has reached terminal count

wide-band

narrow-band

Priorities for the events in registers E1 and E2, shown in Table 42 and Table 43, are handled inside the
TCM8030. Interrupt priorities are handled in software.

-I
"tJ

FOCC data changed value

These flags indicate which event(s) have occurred since the previous read, regardless of their associated
interrupt control bits. E2 can only be read after E1 because of the protocol for queuing and clearing events (see
the description for address 02).

"tJ

STATUS SINCE PREVIOUS READ OF THIS WORD

MCU idle mode processing
This idle mode processing feature is in addition to RXRF idle mode. It allows the use of microcontroller
power-saving modes.

m
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Operation is achieved by masking out the RX1 data available event, by writing 0 to IE1.0 (write address 05) and
writing a 1 to the FOCC data change event, IE2.0 (write address 06).
The TCM8030 generates an interrupt only when the received word changes from its previous value. This means
that no interrupt is generated (after the first word) during the reception of a stream of words that are the same.
This extended time between interrupts allows the microcontroller to spend more time in sleep mode.

This feature may be implemented after the reception of a CFM (control filler message). It is likely that several
more CFMs are received, so the microcontroller can enter idle mode processing and subsequently enter sleep
mode.
No interpretation of messages is done, however. The interrupt is generated based on a bit-for-bit comparison
of the current word and the previous one. Continuously repeated single words are handled, but repeated
multiword messages are not supported.

SYNC terminal
This terminal goes high in FVC mode (C1.2 = 1, write address 00) while a message is being received. It also
goes high in FOCC mode (C1.2 = 0, write address 00) while the data processor is in sync with the control
channel.

address 10 - RX data word 0 (RXDO)
This register contains the error-corrected received data bits 27 to 20 (bit 27 is MS8).

~TEXAS
5-138

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

PRINCIPLES OF OPERATION
address 11 -

RX data word 1 (RXD1)

This register contains the error-corrected received data bits 19 to 12 (bit .19 is MSB).

address 12 -

RX data word 2 (RXD2)

This register contains the error-corrected received data bits 11 to 4 (bit 11 is MSB).

address 13 -

RX data word 3 (RXD3)

This register contains the error-corrected received data bits 3 to 0 and the error correction status as shown in
Table 44.
Table 44. RX Data Word 3 (RXD3) Definition
BIT

STATUS

3-0

Received data decode status (see Table 45)

RXdata bitO

RXdata bit 1

RXdata bit2

RX data bit 3

The received data error correction status is contained in bits 0 - 3, with 16 possible status conditions as shown
in Table 45.
Table 45. RX Data Word 3 (RXD3) Error Correction Status Definition
RECEIVED DATA WORD 3

::J

DECODE STATUS

BIT3

BIT2

BIT 1

BITO

One error detected in parity bits

Two errors detailed in parity bits

Not used

One error corrected in data

One error corrected in data, one error detected in parity bits

Not used

Two errors corrected in data

Not used

More than two erasurest occurred -

up to two data bits corrected.
one error detected in parity bits and up to one data bit
two errors in parity bits detected.

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No errors detected

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More than two erasures t occurred corrected.

More than two erasurest occurred -

More than two errors detected -

data not corrected.

t A bit erasure occurs when, over valid repeats, the bit is detected an equal number of times as a 1 and as a O.

~TEXAS

INSTRUMENTS
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5-139

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
addresses 16,18, 1A - PIO status words (P11, P12, P13)
These addresses monitor the states of PI01, PI02, and PI03 terminals.

address 22 - RX repeat count - wide-band
The received repeat count gives the number of repeats of the received word that were actually used, using the
bit-wise majority voting circuit to generate the received data.

address 25 - narrow-band error rate (NBERRS)
This register is provided to assist in implementing the mobile reported interference function required by the
NAMPS specification.

MRI (mobile-reported interference) operation
The NBERRS register contains the total errors detected in the 200 NRZ bits of DSAT and sync word that were
received up until the latest update. The NBERRS register is updated once for each group of 100 received NRZ
bits. At the same time as this update, the event E2.S (read address 06) is triggered. When the interrupt bit IE2.S
(write address 06) has been set, then an interrupt is generated. The microcontroller can then read the NBERRS
register to determine the error rate over the last 200 NRZ bits.

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While the sync word is being received, the DSAT error checking reports a large number of errors. The errors
are eliminated automatically (subtracted out) once the whole word is successfully received, and the error
register is incremented by the number of sync-word errors. When a complete data word is received, the DSAT
continues as if it were never interrupted, that is, during data reception the reference DSAT generator phase is
advanced every NRZ clock cycle even when there is no DSAT output.

o-I
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:rJ

Error counting begins when 24 bits of NRZ data have been received. The total-error count contained in these
twenty-fourth bits determines the DSAT status. However, the NBERRS error counting mechanism only
considers the twenty-fourth bit. Afterthis initialization period, the error counting mechanism functions regardless
of DSAT status. For example, when bad DSAT status is indicated, the reference DSAT generator maintains its
original phase and continues to perform error accumulation on each bit as it is received. After only 1.6 seconds
(the time taken for a sync word, data word, and 24 bits of DSAT) the DSAT generator phase is rotated to find
a best fit with the received data. Having found the best fit, the received bit is tested against the reference bit to
see whether the error count needs to be incremented.

S
m

The rest of the MRI function is done in software. This consists of comparing the narrow-band error rate with the
threshold setting that has been communicated by a control message to the mobile unit. When this threshold
setting is exceeded, a MRI order is generated from the mobile to the base station over the RVC.
The microcontroller must:
1.

Read the NBERRS register after an NBERRS update interrupt.

Integrate as required, many NBERRS readings over time to get an averaged result.

Determine when the error rate has gone above the threshold.

Generate an MRI order, when threshold has been exceeded, on the RVC by sending a correct data word
to the TCM8030.

The MRI circuit always operates on FVC in narrow-band mode. MRI interrupts can be enabled or disabled by
setting or resetting the interrupt mask bit IE2.S (write address 06). Therefore, no MRI start/stop bit is provided.
The NBERRS count is reinitialized when the narrow-band mode (C1.1, write address OO) and FVC (C1.2, write
address OO) bits change from any other state to binary 11. Hence, no MRI clear bit is provided.

~TEXAS

INSTRUMENTS
5-140

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030

BASEBAND PROCESSOR FOR

ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

PRINCIPLES OF OPERATION
address 43 -

AFC terminal count MS byte (AFCIF1)

This register contains the most significant byte (bits 12 -19 stored in locations 0-7) of the IF-2 counter in the
AFC block.

address 44 -

AFC terminal count middle byte (AFCIF2)

This register contains the middle byte (bits 4-11 stored in locations 0 - 7) of the IF-2 counter in the AFC block.

address 45 -

AFC terminal count lower byte (AFCIF3)

This register contains the lower nibble (bits 0-3 stored in locations 4 -7 respectively) of the IF-2 counter in the
AFC block as shown in Table 46.
Table 46. AFC Terminal Count Lower Byte (AFCIF3) Definition
BIT

STATUS

AFC, IF-2 counter bit 0

AFC, IF-2 counter bit 1

AFC, IF-2 counter bit 2

AFC, IF-2 counter bit 3

s:w

The AFC terminal counter should be read MS byte first and LS nibble last. After a reading of the LS nibble has
occurred, both the TCXO counter and the AFC counter are automatically reset.

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-141

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033 - JUNE 1996

APPLICATIONS INFORMATION
suggested trim sequence
The TCM8030 is designed so that no manual trims are required. All levels can be adjusted to meet system
requirements and to compensate for production tolerances by writing to the digital interface. The data required
is stored in a nonvolatile memory by the microcontroller in the telephone. When the telephone is turned on, an
initialization routine writes this calibration data to the TCM8030.
The sequence of adjustments is detailed in the following procedure. Steps 1 - 6 adjust the transmit path and
step 7 adjusts the receive path.
1. TXTRIM

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Set the TX OAT TRIM to nominal = 100.

Set the TCM8030 to transmit signaling tone.

Adjust the TXTRIM register to set the frequency deviation to that required by the system.

TXSAT
a.

Turn the signaling tone off and turn on the SAT path.

Set the TCM8030 to generate its own SAT tone of 6000 Hz.

Adjust the SATTRIM register to give the required frequency deviation.

VDTRIM

(")

Mute the signaling tone and SAT.

-I

Inject an audio signal at the desired level into the microphone preamplifier, MICAMP2.

Adjust the VDTRIM register to set the frequency deviation. This also adjusts the TX DTMF level.

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:::;

LIMITER TRIM
a.

Increase the audio signal level by 20 dB, typically.

Adjust LIMITER register to produce the required maximum deviation.

DTMFTrim
The DTMF level is set by external resistors between the DTO output and the DTI input (TX side) and CTI
input (RX side). There is no independent DTMF trim register on the TCM8030.

TX NARROW BAND DATA (NTACS or NAMPS)
The narrow-band data transmission level can be adjusted using the TXDATRIM register.

RXTRIM
a.

Input a modulated signal to the telephone

Adjust the RXTRIM register to produce the required signal level at REC1 and REC2.

~TEXAS

INSTRUMENTS
5-142

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM8030
BASEBAND PROCESSOR FOR
ANALOG CELLULAR TELEPHONES
SLWS033-JUNE 1996

APPLICATIONS INFORMATION
muting the audio paths
Both the transmit path as well as the receive path can be muted at two locations within the TCM8030. Muting
is accomplished by writing DOh to the associated transmit receive configuration register.

transmit
Writing 00 (hex) to register TXCFG (address 33) mutes the TX path. The path is actually muted at TXSW and
TXSUM by connection to TXVMID.
receive
Writing 00 (hex) to register RXCFG (address 32) mutes the RX path. The path is actually muted at REC1 SW
and RECBUF by connection to RXVMID.

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5-143

5-144

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io_n______________~1IDI
Telecommunications Circuits

Central Office Codecs
Transient Voltage Suppressors
RF for Telemetry and RKE

lEI

III

Wireless Communications Circuits
Processors for Analog·Celiular
Voice-Band Audio Processors
RFfor Personal Communications
Baseband Interface Circuits

Digital. Signal Processors
Mechanical Data

6-1

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6-2

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

•

Single 5-V Operation

•

Low Power Consumption:
- Operating Mode . .. 40 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode . .. 3 mW Typ

Combined AID, DIA, and Filters

•

Extended Variable-Frequency Operation
- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 I< I-XO 0
~ -(f) I- z...J(f)
:J(Z Z
OLL
...J °LL :::>
0
00
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0
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Ne - No internal connection

•

VBAP is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA Information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of ali parameters.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-3

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

description
The TCM320AC36 and TCM320AC37 voice-band audio processor (VBAP) integrated circuits are designed to
perform the transmit encoding (AID conversion) and receive decoding (01A conversion) together with transmit
and receive filtering for voice-band communications systems. Cellular telephone systems are targeted in
particular; however, these integrated circuits can function in other systems including digital audio,
telecommunications, and data acquisition.
These devices are pin-selectable for either of two modes, companded and linear, providing data in two formats.
In the companded mode, data is transmitted and received in 8-bit words. In the linear mode, 13 bits of data, and
either three bits of gain-setting control data, or three zero bits of padding to create a 16-bit word, are sent and
received.
The transmit section is designed to interface directly with an electret microphone element. The microphone input
signal (MICIN) is buffered and amplified with provision for setting the amplifier gain to accommodate a range
of signal input levels. The amplified signal is passed through antialiasing and band-pass filters. The filtered
signal is then applied to the input of a compressing analog-to-digital converter (COAOC) when companded
mode is selected. Otherwise, the analog-to-digital converter performs a linear conversion. The resulting data
is then clocked out of OOUT as a serial data stream.
The receive section takes a frame of serial data on DIN and converts it to analog through an expanding
digital-to-analog converter (EXOAC) when the companded mode is selected; otherwise, a linear conversion is
performed. The analog signal then passes through switched capacitor filters, which provide out-of-band
rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The
earphone amplifier has a differential output with adjustable gain and is designed to minimize static power
dissipation.
A single on-chip high-precision band-gap circuit generates all voltage references, eliminating the need for
external reference voltages. An internal reference voltage equal to Vcc/2, VM I0, is used to develop the midlevel
virtual ground for all the amplifier circuits and the microphone bias circuit. Another reference voltage, MICBIAS,
can supply bias current for the microphone.
The TCM320AC3xC devices are characterized for operation from O°C to 70°C. The TCM320AC3xl devices are
characterized for operation from -40°C to 85°C.

~TEXAS

INSTRUMENTS
6-4

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

functional block diagram

MICMUTE
DOUT
MICIN
FSX

MICGS ~19=---4--+-_ _- l

VMID
MICSIAS

AID
Converter
Voltage
Reference

17
20

256 kHz

D/A

8 kHz

Converter
Voltage
Reference

9
EARA
EARS
EARGS
EARMUTE

FSR

3
4
10

Earphone
Amplifier

DIN

GND

VCC
Terminal numbers shown are for the OW and N packages.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-5

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0038 - MAY 1992 - REVISED JUNE 1996

Terminal Functions
TERMINAL
NAME

1/0

NO.
DW,N

DESCRIPTION

AGND

AVCC

ClK

Clock input. In the fixed-data-rate mode, ClK is the master clock input as well as the transmit and
receive data clock input. In the variable-data-rate mode, ClK is the master clock input only (digital).

Selection of fixed- or variable-data-rate operation. When DClKR is connected to VCC, the device
operates in the fixed-data-rate mode. When DClKR is not connected to VCC, the device operates in
the variable-data-rate mode and DClKR becomes the receive data clock (digital).

DClKR

DGND

DIN

Ground return for all internal analog circuits
5-V supply voltage for all internal analog circuits

Ground return for all internal digital circuits

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is ClK for a fixed data rate and DClKR for a variable data rate (digital).

DOUT

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is ClK for a fixed data rate and DClKX for a variable data rate (digital).

DVCC

5-V supply voltage for all internal digital circuits

EARA

EARS

EARGS

Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential
divider network connected across EARA and EARS adjusts the power amplifier gain. Maximum gain
occurs when EARGS is connected to EARS. Minimum gain occurs when EARGS is connected to
EARA. Earphone frequency response correction is performed using an RC approach (analog).

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).

FSR

Frame-synchronization clock input for the receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).

FSX

Frame synchronization clock input for the transmit channel. FSX operates independently of FSR, but
also in an analogous manner to FSR. The transmit channel enters the standby condition when FSX
is low for five frames or longer. The device enters a production test-mode condition when either FSX
or FSR is held high for five frames or longer (digital).

GND

LlNSEl

Linear selection input. When low, LlNSEl selects linearcoding/decoding. When high, LlNSEl selects
companded coding/decoding. Companding code on the' AC36 is Il-Iaw, and companding code on the
'AC37 is A-law (digital).

MICBIAS

Microphone bias. MICSIAS voltage for the electret microphone is equal to VMID.

MICGS

Output of the internal microphone amplifier. MICGS is used as the feedback to set the microphone
amplifier gain. If sidetone is required, it is accomplished by connecting a series network between
MICGS and EARGS (analog).

MICIN

Microphone input. Electret microphone input to the internal microphone amplifier (analog)

Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).

Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).

I/O

Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSXlDClKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DCLKX becomes the transmit data
clock input (digital).

EARMUTE

MICMUTE
PDN
TSXlDClKX

VCC

VMID

Earphone output. EARA forms a differential drive when used with the EARS signal (analog).
Earphone output. EARB forms a differential drive when used with the EAR A signal (analog).

Ground return for all internal circuits

5-V supply voltage for all internal circuits

VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors (1 IlF and
470 pF) should be connected between VMID and ground for filtering .

•
TEXAS
INSTRUMENTS
6-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0038 - MAY 1992 - REVISED JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.3 V to 7 V
Output voltage range at DOUT, Va ................................................... -0.3 V to 7 V
Input voltage range at DIN, VI ....................................................... -0.3 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: C suffix ......................................... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ........... . . . . . . . . . . . . . . . . . . .. 260°C

PACKAGE

TA :S;25°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

8.2 mW/oC

656mW

533mW

1150mW

9.2 mWfOC

736mW

598mW

1075 mW

7.1 mW/oC

756mW

649mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

recommended operating conditions (see Note 2)
MIN

MAX

Supply voltage, VCC (see Note 3)

4.5

5.5

High-level input voltage, VIH

2.2
0.8

113

Low-level input voltage, VIL
Load resistance between EARA and EARS, RL (see Note 4)

Operating free-air temperature, TA
NOTES:

600

Load capacitance between EARA and EARS, CL (see Note 4)

l TCM320AC36C, TCM320AC37C
1TCM320AC361, TCM320AC371

UNIT

-40

°C

2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up sequence detailed in the system
reliability features paragraph should be followed.
3. Voltages at analog inputs, outputs, and VCC are with respect to GND.
4. RL and CL should not be applied simultaneously.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-7

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, fOCLKR or fOCLKX

=2.048 MHz, outputs not loaded, VCC =5 V, TA =25°C

PARAMETER

TEST CONDITIONS
Operating

ICC

Supply current from VCC

MIN

PDN is high with ClK signal present

MAX

UNIT

9.9

Power down

PDN is low for 500 Jls

Standby-both

PDN is high with FSX and FSR held low

Standby - one

PDN is high with either FSX or FSR pulsing with the
other held low

0.85
mA

digital interface
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

VOL

low-level output voltage

IIH

High-level input current, any digital input

VI = 2.2 Vto VCC
VI = OtoO.8 V

IDOUT

IOH = -3.2 mA,

VCC=5V

IOl=3.2 mA,

VCC=5V

MIN

TYPt

2.4

4.6
0.2

MAX

UNIT
V

0.4

JlA

III

low-level input current, any digital input

Input capacitance

Output capacitance

t All tYPical values are at VCC = 5 V, TA = 25°C.
microphone interface
PARAMETER

TEST CONDITIONS

VIO

Input offset voltage at MICIN

liB

Input bias current at MICIN

Unity-gain bandwidth, open loop at MICIN

MIN

TYpt

MAX
±5

VI =Ot05 V

±200

Input capacitance at MICIN

large-signal voltage amplification at MICGS

lOmax

Maximum output current

lVMID
MICBIAS
(source only)

V/V

10000

MHz

UNIT

JlA

t All typical values are at VCC = 5 V, TA = 25°C.

speaker interface
TEST CONDITIONS

PARAMETER
VO(PP)

AC output voltage

VOO

Output offset voltage at EARA, EARB (single-ended)
Input leakage current at EARGS

VI = 0.5 V to (VCC - 0.5) V

lOmax

Maximum output current

Rl= 600

Output resistance at EARA, EARB

n
1

EARMUTE low, max level when muted

t All typical values are at VCC = 5 V, TA = 25°C.

~TEXAS

INSTRUMENTS
6-8

TYPt

Relative to GND

11(lkg)

Gain change

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-80

MAX

UNIT

Vpp

mVpk

±200

±5

n
dB

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B- MAY 1992 - REVISED JUNE 1996

transmit gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee
TA 25°C (unless otherwise noted) (see Notes 5 and 6)

PARAMETER

TEST CONDITIONS

Transmit reference-signal level (0 dB) (see Note 7)

Overload-signal level (MICIN at unity gain)

MIN

0.982

Companded mode selected, A-law (,AC37)

0.985

Linear mode selected ('AC36 and 'AC37)

1.001

Companded mode selected, fl-Iaw ('AC36)

Companded mode selected, A-law (' AC37)

Linear mode selected (,AC36 and 'AC37)

O-dB input signal

Absolute gain error

±1

MICIN to DOUT at 3 dBmO to -36 dBmO
Gain error with input level relative to gain at -10 dBmO

Gain variation
NOTES:

MAX

Companded mode selected, fl-Iaw ('AC36)

±0.5

=5 V,
UNIT

Vrms

Vpp

dB
dB

MICIN to DOUT at -37 dBmO to -40 dBmO

±1

MICIN to DOUT at -41 dBmO to -50 dBmO

±1.5

MICIN to DOUT at -51 dBmO to -55 dBmO

±2

±0.5

VCC±10%,

=O°C to 70°C

5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference point of the channel
under test.
6. The input amplifier is set for inverting unity gain.
7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.

transmit filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, ClK 2.048 MHz, FSX 8 kHz (see Note 6)

PARAMETER

TEST CONDITIONS

=50 Hz
fMICIN =200 Hz
fMICIN =300 Hz to 3 kHz
fMICIN =3.3 kHz
fMICIN =3.4 kHz
fMICIN =4 kHz
fMICIN

Gain relative to input signal gain at
1.02kHz

Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB

MIN

MAX

-10

-1.8

UNIT

0
±O.15

-0.35

0.04

-1

-0.1

-14

fMICIN ~4.6 kHz

-32

NOTE 6. The input amplifier is set for inverting unity gain.

transmit idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER

TEST CONDITIONS

Transmit noise, psophometrically weighted

MICIN connected to MICGS through a 10-k.Q resistor

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kil resistor
MICIN to DOUT at 0 dBmO to -17 dBmO

Transmit signal-to-distortion ratio with sine-wave input

Intermodulation distortion, 2-tone CCITT method,
composite power level-13 dBmO

MIN

MAX

UNIT

-71

dBOp

dBrnCO

MICIN to DOUT at -18 dBmO to -23 dBmO

MICIN to DOUT at -24 dBmO to -29 dBmO

MICIN to DOUT at -30 dBmO to -35 dBmO

MICIN to DOUT at -36 dBmO to -45 dBmO

CCITT G.712 (7.1), R2

CCITT G.712 (7.2), R3

NOTE 8: Transmit noise, linear mode: 200 flVrms is equivalent to -74 dB (referenced to device O-dB level) .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-9

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
TEST CONDITIONS

PARAMETER

MIN

MICIN connected to MICGS through a 10-kQ resistor

Transmit noise

MICIN to OOUT at 0 dBmO to -6 dBmO

MICIN to OOUT at-7 dBmO to-12 dBmO

MICIN to OOUT at -13 dBmO to -18 dBmO

MICIN to OOUT at -19 dBmO to -24 dBmO

MICIN to OOUT at -25 dBmO to -40 dBmO

MICIN to OOUT at -41 dBmO to -45 dBmO

MAX

UNIT

200

IlVrms

Transmit signal-to-distortion ratio with sine-wave input

NOTES:

6. The input amplifier is set for inverting unity gain.
8. Transmit noise, linear mode: 200 IlVrms is equivalent to -74 dB (referenced to device O-dB level).

receive gain and dynamic range, companded mode (/-l-Iaw or A-law) or linear mode selected,
TA 25°C (unless otherwise noted) (see Notes 9 and 10)

TEST CONDITIONS

PARAMETER
Receive reference-signal level (0 dB) (see Note 11)

Overload-signal level

MIN

Companded mode selected, A-law (' AC37)

0.739

Linear mode selected (' AC36 and' AC37)

0.751

Companded mode selected, Il-Iaw ('AC36)

Companded mode selected, A-law (,AC37)

Linear mode selected (,AC36 and 'AC37)

3
±1

OIN to EARA and EARB at -37 dBmO to -40 dBmO

±1

OIN to EARA and EARB at -41 dBmO to -50 dBmO

±1.5

VCC±10%,

=O°C to 70°C

UNIT
Vrms

Vpp
dB

±0.5

OIN to EARA and EARB at -51 dBmO to -55 dBmO
Gain variation

MAX
0.736

OIN to EARA and EARB at 3 dBmO to -36 dBmO
Gain error with output level relative to gain at -10 dBmO

Vee =5 V,

Companded mode selected, Il-Iaw ('AC36)

O-dB input signal

Absolute gain error

NOTES:

±2
±0.5

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
10. Unless otherwise noted, the digital input is a word stream generated by passing a O-dB sine wave at 1020 Hz through an ideal
encoder, where 0 dB is defined as the zero reference.
11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier
set to unity.

receive filter transfer, companded mode (/-l-Iaw or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR 8 kHz (see Note 9)

TEST CONDITIONS

PARAMETER

= < 200 Hz
fOIN = 200 Hz
fOIN = 300 Hz to 3 kHz
fOIN = 3.3 kHz
fOIN = 3.4 kHz
fOIN =4 kHz
fOIN => 4.6 kHz

MIN

Gain relative to gain at 1 .02 kHz

NOTE 9.

OIN

=0 dBmO

UNIT

-0.5

0.15
±0.15

-0.35

0.03

-1

-0.18

-14
-30

Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected .

•
TEXAS
INSTRUMENTS
6-10

MAX
0.15

fOIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0038 - MAY 1992 - REVISED JUNE 1996

receive idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over recommended
ranges of supply voltage and operating free-air temperature (see Note 9)
TEST CONDITIONS

PARAMETER

Receive noise, C-message weighted

Receive signal-to-distortion ratio with sine-wave input

NOTE 9.

MIN

= 11010101 (A-law)
DIN = 11111111 (Wlaw)
DIN

Receive noise, psophometrically weighted

MAX

UNIT

-75

dBOp

DIN to EARA and EARB at 0 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -30 dBmO

DIN to EARA and EARB at -31 dBmO to -38 dBmO

DIN to EARA and EARB at -39 dBmO to -45 dBmO

dBrncO

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
TEST CONDITIONS

PARAMETER
Receive noise

DIN

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCITT distortion method,
composite power level -13 dBmO
NOTES:

MIN

=00000000

DIN to EARA and EARB at 0 dBmO to -6 dBmO

DIN to EARA and EARB at -7 dBmO to -12 dBmO

DIN to EARA and EARB at -13 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -40 dBmO

DIN to EARA and EARB at -41 dBmO to -45 dBmO

CCITT G.712 (7.1), R2

CCITT G.712 (7.2), R3

MAX

UNIT

200

~Vrms

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 ~Vrms is equivalent to -71 dB (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

-30

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EARB)

-30

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB

Crosstalk attenuation, receive-to-transmit

DIN = 0 dBmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

t All typical values are at VCC =5 V, TA =25°C.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-11

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN
tt

NOMt

MAX

Transition time, ClK and DClKX/DClKR

Duty cycle, ClK

45%

50%

55%

Duty cycle, DClKX/DClKR

45%

50%

55%

UNIT
ns

t All typical values are at VCC =5 V, TA =25°C.
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before ClKJ..

468

th(FSX)

Hold time, FSX high after ClKJ..

468

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
MIN

MAX

tsu(FSR)

Setup time, FSR high before ClKJ..

468

UNIT
ns

th(FSR)

Hold time, FSR high after ClKJ..

468

tsu(DIN)

Setup time, DIN high or low before ClKJ..

th(DIN)

Hold time, DIN high or low after ClKJ..

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MAX

UNIT

tsu(FSX)

Setup time, FSX high before DClKXJ..

tc (DClKX)-40

th(FSX)

Hold time, FSX high after DClKXJ..

tc (DClKX)-35

MIN

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before DClKRJ..

th(FSR)

Hold time, FSR high after DClKRJ..

tsu(DIN)

Setup time, DIN high or low before DClKRJ..

th(DIN)

Hold time, DIN high or low after DClKRJ..

ns
tc (DClKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL =0 to 10 pF (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd1

From ClK bit 1 high to DOUT bit 1 valid

tpd2

From ClK high to DOUT valid, bits 2 to n

tpd3

From ClK bit n low to DOUT bit n Hi-Z

tpd4

From ClK bit 1 high to TSX active (low)

Rpull up = 1.24 kQ

tpd5

From ClK bit n low to TSX inactive (high)

Rpullup = 1.24 kQ

~TEXAS

INSTRUMENTS
6-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ns
40

ns
ns

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER

TEST CONDITIONS

MIN

UNIT

MAX

tpd6

FSX high to DOUT bit 1 valid

CL= Oto 10 pF

tpd7

DCLKX high to DOUT valid, bits 2 to n

CL= 0 to 10 pF

~d8

FSX low to DOUT bit n Hi-Z

PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL' Bit 1 = MSB (most significant bit) and is clocked in first on DIN
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.

I'"
o

I
I

---------I~

Receive Time Slot

N-2

N-1

DIN

I I
I+-

See Note C

NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

tsu(DIN)

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
TransmitTimeSlot---------~

I...

I-I

th(FSX)

N-2

N-1

N+1

20%

ClK
tsu(FSX)

----J+-.J

I...

FSX

,d;%'f\~~~Wli0..\. .\\
. . . . .\: . . . -__+--_ _ _ _{~/.,.j--------+I--1

I...

1 141...~~------t__----- See Note 8 _ _ _ _ _ _ _ _.1-1-------..

I+-

See rote A

tpd2

tpd3 ----.:

DOUT------------~I~

See Note C

tpd1

-+!

tpd5 ~

TSX------------~:~~~2~OO~~--------------------~~,.,.~---------------------J~~8-0-%--
-+!

~ tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-13

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0038 - MAY 1992 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

1 4 - - - - - - - - - - Receive Time Slot ---------~
DCLKR

FSR

DIN
See Note C
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram
1
Hil
41----------I 1
2
3

Transmit Time Slot ----------~.I
4
N-2
N-1
N
I N+1

DCLKX

20%

I4-¥---

FSX

----..::.o$~~ i
See Note A

tpd6 ~

DOUT
See Note C

tsu(FSX)

((

th(FSX) ~

See Note B

tpd8 ~

14-1

0-_4I>-------f-'----

VMID

EARA

EARB

r--------------------~
NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network
receive data format
In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).
In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dS steps, giving a maximum attenuation of 21 dS
when all bits are 1s. The volume control bits are not latched into the VSAP and must be present in each received
data word.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-19

TCM320AC36, TCM320AC37
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS003B - MAY 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.

COMPANDED MODE

LINEAR MODE

CD7

LD12

CD6

LD11

CD5

CD4

LD10
LOg

CD3

LDB

CD2

LD7

6
7

CD1

LD6

CDO

LD5

LD4

g
A

LD3
LD2

LOO

E
F

LD1

Volume control and other control bits always follow the PCM data in time:
Companded Mode:

MSB
(sign bit)

LSB
,CD7 CDS CDS CD4 CD3 C02 CD1 COOl
V
Companded Data

Linear Mode:

MSB
(sign bit)

LSB
LD12 LD11 LD10 LOg LOS LD7 LOS LOS LD4 LD3 LD2 LD1 LDO

~------------------~V

Linear Data
Time---.

where:
CD7 -CDO = Data word when in companded mode
LD12-LDO= Data word when in linear mode
V2, V1, VO = Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

~TEXAS

INSTRUMENTS
6-20

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

I~
Volume Control

TCM320AC36, TCM320AC37
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0038 - MAY 1992- REVISED JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARS are low-impedance complementary outputs. The voltages at the nodes are:
VO+at EARA
VO- at EARS
Voo = Vo+ - Vo- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kQ and less than 100 kn for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 0.751 Vrms).
Voo=AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

EARA

Digital mW Sequence
lAW CelTT G.712

-.- DIN

EARGS

........

Vo
> R2

EARB

~
<

: RL

.
r

Vo-

NOTE A: "T:erminal numbers shown are for the DW and N packages.

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VSAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK' to the frame sync frequency, fFSR/fFSX' This ratio for the VSAP is 2.048 MHzl8 kHz, or 256
master clocks per frame sync. For example, to operate the VSAP at a sampling rate of fFSR and fFSX equal to
16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the VSAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-21

6-22

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

•

Single 5-V Operation

•

Low Power Consumption:
Operating Mode . .. 40 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode . .. 3 mW Typ

Combined AID, DIA, and Filters

Extended Variable-Frequency Operation
- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 kHz

Electret Microphone Bias Reference
Voltage Available

•

Drive a Piezo Speaker Directly

•

Compatible With All Digital Signal
Processors (DSPs)

•

Selectable Between 8-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
- TCM320AC38 .. . Jl-Law and Linear
Modes
- TCM320AC39 ... A-Law and Linear
Modes

•

Programmable Volume Control in Linear
Mode

300 Hz - 3.6 I 4.6 kHz

MIN

Gain relative to gain at 1.02 kHz

OIN

=0 dBmO

MAX

UNIT

0.15

fOIN

-0.5

0.15
±0.15

-0.35

0.03

-1

-0.18

-14
-30

NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected .

•
TEXAS
INSTRUMENTS
6-30

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

receive idle channel noise and distortion, companded mode (Il-Iaw or A-law selected) over recommended
ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER

MIN

TEST CONDITIONS
DIN = 11010101 (A-law)

Receive noise, psophometrically weighted

DIN = 11111111 (Il-Iaw)

Receive noise, C-message weighted

UNIT

-75

dBOp

DIN to EARA and EARB at 0 dBmO to -18 dBmO

Receive signal-to-distortion ratio with sine-wave input

MAX

dBrncO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -30 dBmO

DIN to EARA and EARB at -31 dBmO to -38 dBmO

DIN to EARA and EARB at -39 dBmO to -45 dBmO

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER

MIN

TEST CONDITIONS

Receive noise

DIN

=00000000

DIN to EARA and EARB at 0 dBmO to -6 dBmO

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCITT distortion method,
composite power level -13 dBmO
NOTES:

MAX

UNIT

200

IlVrms

DIN to EARA and EARB at -7 dBmO to -12 dBmO

DIN to EARA and EARB at -13 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -40 dBmO

DIN to EARA and EARB at -41 dBmO to -45 dBmO

CCITT G.712 (7.1), R2

CCITT G.712 (7.2), R3

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 IlVrms is equivalent to -71 dB (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

-30

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EAR B)

-30

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB

Crosstalk attenuation, receive-to-transmit

DIN = 0 dBmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

All typical values are at VCC

=5 V, TA =25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-31

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN
tt

NOMt

MAX

Transition time, CLK and DCLKX/DCLKR

Duty cycle, CLK

45%

50%

55%

Duty cycle, DCLKX/DCLKR

45%

50%

55%

UNIT
ns

t All typical values are at VCC =5 V, TA =25°C.
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

tsu(FSX)

Setup time, FSX high before CLKJ..

468

UNIT
ns

th(FSX)

Hold time, FSX high after CLKJ..

468

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before CLKJ..

468

th{FSR)

Hold time, FSR high after CLKJ..

468

tsu(DIN)

Setup time, DIN high or low before CLKJ..

th(DIN)

Hold time, DIN high or low after CLKJ..

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MAX

UNIT

tsu(FSX)

Setup time, FSX high before DCLKXJ..

MIN
40

tc (DCLKX)-40

th(FSX)

Hold time, FSX high after DCLKXJ..

tc (DCLKX)-35

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

MAX

. UNIT

tsu(FSR)

Setup time, FSR high before DCLKRJ..

th(FSR)

Hold time, FSR high after DCLKRJ..

tsu(DIN)

Setup time, DIN high or low before DCLKRJ..

th(DIN)

Hold time, DIN high or low after DCLKRJ..

tc (DCLKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL =0 to 10 pF (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

tpd1

From CLK bit 1 high to DOUT bit 1 valid

tpd2

From CLK high to DOUT valid, bits 2 to n

tpd3

From CLK bit n low to DOUT bit n Hi-Z

tpd4

From CLK bit 1 high to TSX active (low)

Rpull up

tpd5

From CLK bit n low to TSX inactive (high)

Rpull up

"TEXAS
INSTRUMENTS
6-32

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

=1.24 kn
=1.24 kn

ns
ns
ns

40
30

UNIT

ns
ns

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER
tpd6

FSX high to DOUT bit 1 valid

tpd7

DClKX high to DOUT valid, bits 2 to n

tpd8

FSX low to DOUT bit n Hi-Z

TEST CONDITIONS

MIN

MAX

=0 to 10 pF
Cl =0 to 10 pF
Cl

UNIT

14
o

I
I

---------~

Receive Time Slot

N-2

N-1

DIN
See Note C

I I

NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

I+-

tsu(DIN)

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
1l<1li4 1 - - - - - - - - - - Transmit Time Slot - - - - - - - - - - - .

N-1

tsu(FSX)

N+1

---J+-.J
, 14

.1 th(FSX)
,
q~W:9\
\\d~\\\
,
,_,
'::1Y I ~
~h..:::l!_~~\Io,.;\Io,.;\~\lo....-_ _--+-_ _ _ _ _---'l('I-(_ _ _ _ _ _ _ _ _-+-_
_ __
I

•

I-

1414~1;--------+-------

I+-

See ,Note A

tpd1

See Note B _ _ _ _ _ _ _ _.l-_ _ _~.

tpd2

tpd3 --.:

DOUT-------------+I~

See Note C

20%

ClK

FSX

--+l

tpd54

;""8-0-%-: \

---+i

20%

((

j+- tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-33

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

DCLKR

FSR

DIN
See NoteC

NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram

I:~~--14
~I
I

tpd8

-+II+-

TCM320AC38, TCM320AC39
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS0048 - JUNE 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
general
system reliability features
The device should be powered up and initialized as follows:
1.

Apply GNO.

Apply Vee.

Connect all clocks.

Apply TTL high to PON.

Apply synchronizing pulses to FSX and/or FSR.

Even though the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain
improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode (with
a forward voltage drop of less than or equal to 0.4 V - 1 N5711 or equivalent) should be connected between
Vee (power supply) and GNO.
On the transmit channel, digital outputs OOUT and TSX are held in the high-impedance state for approximately
four frames (500 Ils) after power up or application of Vee. After this delay, DOUT, TSX, and signaling are
functional and occur in the correct time slot. The analog circuits on the transmit side require approximately
60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system
integrity, OOUT and TSX are placed in the high-impedance state after an interruption of ClK.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PON. In the absence of a signal, PON is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 3 mW.
Three standby modes give the user the option of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR
is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When
the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and
standby procedures.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-35

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS

Power on

Power down
Entire device on standby
mode
Only transmit channel in
standby mode
Only receive channel in
standby mode

PROCEDURE

=high,
=pulses,
=pulses
PDN =low,
FSX, FSR =xt
FSX =low,
FSR =low,
PDN =high
FSX = low,
FSR =pulses,
PDN =high
FSR =low,
FSX =pulses,
PDN =high
PDN
FSX
FSR

TYPICAL POWER
CONSUMPTION
40mW

DIGITAL OUTPUT STATUS

Digital outputs active but not loaded

3mW

TSX and DOUT in the high-impedance state

SmW

TSX and DOUT in the high-impedance state

20mW

TSX and DOUT in the high-impedance state within five
frames

20mW

Digital outputs active but not loaded

t X =don't care
fixed-data-rate timing
Fixed-data-rate timing is selected by connecting DClKR to Vee and uses the master clock (ClK), frame
synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling
frequency. Data is transmitted on DOUT on the positive transitions of ClK following the rising edge of FSX. Data
is received on DIN on the falling edges of ClK following FSR. A D/A conversion is performed on the received
digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred
to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode.

variable-data-rate timing
Variable-data-rate timing is selected by connecting DClKR to the receive data clock. In this mode, the master
clock (ClK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled
by DClKR and DClKX respectively. This allows the data to be transferred in and out of the device at any rate
up to the frequency of the master clock. DClKR and DClKX must be synchronous with ClK.
While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DClKX.
Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of
DClKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as
DClKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than
once per frame, is available only with variable-data-rate timing.

asynchronous operations
To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters,
filters, and voltage references on the transmit and receive sides to allow completely independent operation of
the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be synchronized
at the beginning of each frame.

precision voltage references
A precision band-gap reference voltage is generated internally and is used to supply all the references required
for operation of both the transmit and receive channels. The gain in each channel is trimmed during the
manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage
and device temperature.

~TEXAS

INSTRUMENTS
6-36

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
conversion laws
The TCM320AC38 provides Il-Iaw companding operation that approximates the CCITT G.711
recommendation. The TCM320AC39 provides A-law companding operation that approximates the CCITT
G.711 recommendation. The linear mode of operation uses a 13-bit two's-complement format and is the same
for both the TCM320AC38 and the TCM320AC39.
transmit operation
microphone input
The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as
shown in Figure 5. The VMID buffer circuit provides a voltage (MICBIAS) equal to 1/2 Vee as a reference for
the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output
(MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to
set the amplifier gain. In the companded mode, when the MICIN signal level decreases to a level near the noise
floor, the VBAP mutes the signal and outputs zero bits while continuing to monitor the signal level. When the
input level once again exceeds the noise threshold, the mute is released and normal operation resumes. Input
hysteresis is provided to ensure noiseless transitions in to and out of the muted condition. VMID appears at a
terminal to provide a place to filter the VMID voltage.

I--------------------~
r -_ _...._ _ _ _ _ _V_M_I':":"D~-------._- VMID Reference

171

2kQ
3.31lF
+

10 kQ
Electret
Microphone

10 kQ

For Amplifiers

1
1
1
1
MICBIASI
201
1
1
1
MICGSI
19
1
MICIN
18
1
1
MICMUTE 1
1
6

VDD

VMID

To Transmit Filters

TCM320AC38/39 VBAP

---------------------1

NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUr.
transmit filter
A low-pass antialiasing section is included on the device and achieves a 35-dB attenuation at the sampling
frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-37

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS0048 - JUNE 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal
sample-and-hold capacitor. The encoder performs an AID conversion on a switched-capacitor array. Digital
data representing the sample is transmitted on the first 8 or 16 data clock cycles of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder using the sign-bit averaging
technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the
encoder.
data word structure
The data word is eight bits long in the companded mode and all eight bits represent one audio data sample.
The sign bit is the first bit transmitted.
The data word is 16 bits long in the linear mode. The first 13 bits comprise the audio data sample, and the last
three bits form the volume control word in the receive direction (DIN) and are zero pad bits in the transmit
direction (DOUT). The sign bit is transmitted first.

receive operation
decoding
In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate
and on the last eight clock cycles in variable-data rate. In the linear mode, the serial data word is received at
DIN on the first 13 clock cycles. DID conversion is performed, and the corresponding analog sample is held on
an internal sample-and-hold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that approximates both
the AT&T 03/04 specification and CCITT recommendation G.712 when operated at the recommended
frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders.
receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone aUdio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around VCC/2.
The receive-channel output level can be adjusted between specified limits by connecting an external resistor
network to EARGS.

~TEXAS

INSTRUMENTS
6-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

PRINCIPLES OF OPERATION

r--------------------,
1
1

14
1--1--

EARGS

1
1
1

1 2

EARA

1
1

> - - - - - t l f - - - - - - - t - - EARB

VMID

r--------------------~
NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network
receive data format
In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).
In the linear mode, 16 bits of data are received. The first 13 bits are the OfA code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB
when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received
data word.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-39

TCM320AC38, TCM320AC39
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B-JUNE 1992- REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.

COMPANDED MODE

LINEAR MODE

CD7

LD12

CD6

LDll

CD5

LD10

CD4

LD9

CD3

LOB

CD2

LD7

CDl

LD6

CDO

LD5

B
9
A

LD4
LD2

LD3
LDl
LDO

Volume control and other control bits always follow the PCM data in time:
Companded Mode:

MSB
(sign bit)

LSB
,CD7 CDG CD5 CD4 CD3 CD2 CDl CDOI

v
Companded Data

Linear Mode:

MSB
(sign bit)

LSB
LD12 LDll LD10 LD9 LDB LD7 LDG LD5 LD4 LD3 LD2 LDl LDO

~------------------~v

Linear Data
Time-.

where:
C07-COO = Data word when in companded mode
. LD12-LDO= Data word when in linear mode
V2, V1, VO = Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

~TEXAS

INSTRUMENTS
6-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

/~
Volume Control

TCM320AC38, TCM320AC39
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS004B - JUNE 1992 - REVISED JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at EARA
Vo- at EARB
VOD = Vo+ - Vo- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kn and less than 100 kn for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 0.751 Vrms).
VOD=AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

EARA t-2--1~--It---_-..-_____. - VO+
R1
Digital mW Sequence
lAW CCITT G.712

DIN

EARGS

1---4---...

EARB

t-3--1~--It---__________..-

VO-

NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK' to the frame sync frequency, fFSR/fFSX. This ratio for the VBAP is 2.6 MHzl8 kHz, or 325 master
clocks per frame sync. For example, to operate the VBAP at a sampling rate of fFSR and fFSX equal to 16 kHz,
fCLK must be 325 times 16 kHz, or 5.2 MHz. If the VBAP is operated above an 8-kHz sample rate, however, it
is expected that the performance becomes somewhat degraded. Exact parametric specifications for rates up
to 16-kHz sample rate are not specified at this time.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-41

6-42

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

•
•

Single 5-V Operation
Low Power Consumption:
Operating Mode ... 40 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode ... 3 mW Typ

•

Combined AID, DIA, and Filters

•

o Extended Variable-Frequency Operation
~

•
•

- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 kHz
Electret Microphone Bias Reference
Voltage Available

o
•

Drive a Piezo Speaker Directly
Compatible With All Digital Signal
Processors (DSPs)

Selectable Between 8-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
- TCM320AC56 ... Il-Law and Linear
Modes
- TCM320AC57 ... A-Law and Linear
Modes
Programmable Volume Control in Linear
Mode
300 Hz - 3.6 kHz Passband with Specified
Master Clock
Designed for Standard 2.048-MHz Master
Clock for U.S. Analog, U.S. Digital, and
CT2, DECT, GSM, and PCS Standards for
Hand-Held Battery-Powered Telephones

description
ow OR N PACKAGE

PT PACKAGE
(TOP VIEW)

(TOP VIEW)
C/J

PDN
EARA
EARS
EARGS
Vee
MICMUTE
DClKR
DIN
FSR
EARMUTE

MICSIAS
MICGS
MICIN
VMID
GND
LlNSEl
TSXlDClKX
DOUT
FSX
ClK

C/J

Z
0: 0: 0: Z (()
W
a:

I-

::l

Terminal numbers shown are for the DW and N packages.

a:
c..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-45

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.
DW,N

AVCC
ClK

AGND

DClKR

DGND

Ground return for all internal analog circuits
5-V supply voltage for all internal analog circuits

Ground return for all internal digital circuits

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is ClK for a fixed data rate and DClKR for a variable data rate (digital).

DOUT

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is ClK for a fixed data rate and DClKX for a variable data rate (digital).

DVCC

DIN

"tJ

5-V supply voltage for all internal digital circuits

EARA

Earphone output. EARA forms a differential drive when used with the EARB signal (analog).

EARB

Earphone output. EARB forms a differential drive when used with the EARA signal (analog).

EARGS

Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential
divider network connected across EARA and EARB adjusts the power amplifier gain. Maximum gain
occurs when EARGS is connected to EARB. Minimum gain occurs when EARGS is connected to
EARA. Earphone frequency response correction is performed using an RC approach (analog).

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).

FSR

FSX

Linearselection input. When low, L1NSElselects linear coding/decoding. When high, L1NSEl selects
companded coding/decoding. Companding code on the 'AC56 is Jl-Iaw, and companding code on the
'AC57 is A-law (digital).

o-I

"tJ

EARMUTE

::sm
:e

DESCRIPTION

I/O
PT

GND

L1NSEl

Ground return for all internal circuits

MICBIAS

Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID.

MICGS

MICIN

Microphone input. Electret microphone input to the internal microphone amplifier (analog)

MICMUTE

Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).

PDN

Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).

I/O

Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSXlDClKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DClKX becomes the transmit data
clock input (digital).

TSXlDClKX

VCC

VMID

5-V supply voltage for all internal circuits

VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors (1 JlF and
470 pF) should be connected between VMID and ground for filtering.

~TEXAS

INSTRUMENTS
6-46

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) .............................................. -0.3 V to 7 V
Output voltage range at DOUT, Va ................................................... -0.3 V to 7 V
Input voltage range at DIN, VI ....................................................... -0.3 V to 7 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: C suffix ......................................... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ........... . . . . . . . . . . . . . . . . . . .. 260°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage value is with respect to GND.
DISSIPATION RATING TABLE
PACKAGE

TA:::;25°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

1150mW

1075 mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

8.2 mW/oC

656mW

533mW

9.2 mW/oC

736mW

598mW

7.1 mW/oC

756mW

649mW

recommended operating conditions (see Note 2)
MIN

MAX

Supply' voltage, VCC (see Note 3)

4.5

5.5

High-level input voltage, VIH

2.2
0.8

113

Low-level input voltage, VIL
Load resistance between EARA and EARB, RL (see Note 4)

Operating free-air temperature, TA
NOTES:

ITCM320AC56C, TCM320AC57C
I TCM320AC561, TCM320AC571

UNIT

600

Load capacitance between EARA and EARB, CL (see Note 4)
0

-40

°C

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3:
w
>
w

6-47

a:
a.
Io
~

c
o

a:
a.

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, fOCLKR or fOCLKX

=2.048 MHz, outputs not loaded, VCC =5 V, TA =25°C

PARAMETER

TEST CONDITIONS
Operating

ICC

Supply current from VCC

MIN

PDN is high with ClK signal present

MAX

UNIT

9.9

Power down

PDN is low for 500 Ils

Standby - both

PDN is high with FSX and FSR held low

Standby - one

PDN is high with either FSX or FSR pulsing with the
other held low

0.85
rnA

digital interface
PARAMETER

"tJ
JJ

o
C
C

-I
"tJ
JJ

<
m
=E

TEST CONDITIONS

MIN

TYPt

2.4

4.6

MAX

UNIT

VOH

High-level output voltage

VOL

low-level output voltage

IIH

High-level input current, any digital input

III

Low-level input current, any digital input

Input capacitance

Output capacitance

!DOUT

IOH = -3.2 rnA,

VCC= 5 V

IOl=3.2 rnA,

VCC= 5 V

0.2

V
0.4

VI = 2.2 V to VCC

IlA

VI = Oto 0.8 V

IlA

t All typical values are at VCC = 5 V, TA = 25°C.

microphone interface
PARAMETER

TEST CONDITIONS

VIO

Input offset voltage at MICIN

liB

Input bias current at MICIN

Unity-gain bandwidth, open loop at MICIN

MIN

TYpt

VI = 0 to 5 V

MAX
±5
±200

Input capacitance at MICIN
large-signal voltage amplification at MICGS

lOmax

Maximum output current

IVMID

MICBIAS
(source only)

mV
nA
MHz

UNIT

10000

VIV

IlA

t All typical values are at VCC = 5 V, TA = 25°C.
speaker interface
PARAMETER

TEST CONDITIONS

VO(PP)

AC output voltage

VOO

Output offset voltage at EARA, EARB (single-ended)

II(lkQ)

Input leakage current at EARGS

VI = 0.5 V to (VCC - 0.5) V

Maximum output current

Rl= 600n

Output resistance at EARA, EARB

1
EARMUTE low, max level when muted

t All typical values are at VCC = 5 V, TA = 25°C.

~·TEXAS

INSTRUMENTS
6-48

TYPt

Relative to GND

lomax

Gain change

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-80

MAX

UNIT

Vpp

mVpk

±200

±5

mA
n
dB

TCi'vi320AC56, TCi\t1320AC57
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

transmit gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee
TA =25°C (unless otherwise noted) (see Notes 5 and 6)
PARAMETER

TEST CONDITIONS
Companded mode selected,

Transmit reference-signal level (0 dB) (see Note 7)

~-Iaw

MIN

0.982

Companded mode selected, A-law (,AC57)

0.985

Linear mode selected (,AC56 and 'AC57)

1.001

Companded mode selected, ~-Iaw ('AC56)
Overload-signal level (MICIN at unity gain)

Linear mode selected (,AC56 and 'AC57)

4
±1

MICIN to DOUT at 3 dBmO to -36 dBmO
Gain error with input level relative to gain at -10 dBmO

Gain variation
NOTES:

UNIT

Vrms

Companded mode selected, A-law (,AC57)

O-dB input signal

Absolute gain error

MAX

('AC56)

=5 V,

±0.5

Vpp

dB
dB

MICIN to DOUT at -37 dBmO to -40 dBmO

±1

MICIN to DOUT at -41 dBmO to -50 dBmO

±1.5

MICIN to DOUT at -51 dBmO to -55 dBmO

±2

±0.5

VCC±10%,

=O°C to 70°C

5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined asthe zero-reference point ofthe channel
under test.
6. The input amplifier is set for inverting unity gain.
7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.

TEST CONDITIONS

PARAMETER

Gain relative to input signal gain at
1.02 kHz

Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB

= 50 Hz
= 200 Hz
fMICIN = 300 Hz to 3 kHz
fMICIN = 3.3 kHz
fMICIN = 3.4 kHz
fMICIN = 4 kHz

MIN

MAX

fMICIN

-10

fMICIN

-1.8

>
w

c..
Io

±0.15
-0.35

0.04

-1

-0.1

-32

NOTE 6. The input amplifier is set for inverting unity gain.

transmit idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER

TEST CONDITIONS

Transmit noise, psophometrically weighted

MICIN connected to MICGS through a 10-kil resistor

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kil resistor
MICIN to DOUT at 0 dBmO to -17 dBmO

Transmit signal-to-distortion ratio with sine-wave input

Intermodulation distortion, 2-tone CCITI method,
composite power level-13 dBmO

MIN

MAX

UNIT

-71

dSOp

dBrnCO

MICIN to DOUT at -18 dBmO to -23 dBmO

MICIN to DOUT at -24 dBmO to -29 dBmO

MICIN to DOUT at -30 dBmO to -35 dBmO

MICIN to DOUT at -36 dBmO to -45 dBmO

CCITI G.712 (7.1), R2

CCITI G.712 (7.2), R3

NOTE 8: Transmit noise, linear mode: 200 ~Vrms is equivalent to -74 dB (referenced to device O-dB level).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

::J

-14

fMICIN ~4.6 kHz

s:w

UNIT

transmit filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, ClK =2.048 MHz, FSX =8 kHz (see Note 6)

6-49

a:
c..

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
TEST CONDITIONS

PARAMETER

Transmit signal-to-distortion ratio with sine-wave input

NOTES:

MIN

MICIN connected to MICGS through a 10-kQ resistor

Transmit noise

MICIN to OOUT at 0 dBmO to -6 dBmO

MICIN to OOUT at -7 dBmO to -12 dBmO

MICIN to OOUT at -13 dBmO to -18 dBmO

MICIN to OOUT at -19 dBmO to -24 dBmO

MICIN to OOUT at -25 dBmO to -40 dBmO

MICIN to OOUT at -41 dBmO to -45 dBmO

MAX

UNIT

200

IlVrms

6. The input amplifier is set for inverting unity gain.
8. Transmit noise, linear mode: 200 IlVrms is equivalent to -74 dB (referenced to device O-dB level).

receive gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee
TA = 25°C (unless otherwise noted) (see Notes 9 and 10)
TEST CONDITIONS

PARAMETER
Receive reference-signal level (0 dB) (see Note 11)

"'tJ

Overload-signal level
Absolute gain error

(')

Gain error with output level relative to gain at -10 dBmO

"'C

::D

m
S

Companded mode selected, A-law (,AC57)

0.739

Linear mode selected (,AC56 and 'AC57)

0.751

Companded mode selected, Il-Iaw ('AC56)

Companded mode selected, A-law (,AC57)

Linear mode selected (,AC56 and 'AC57)

3
±1

DIN to EARA and EARB at 3 dBmO to -36 dBmO
DIN to EARA and EARB at -37 dBmO to -40 dBmO

±1

DIN to EARA and EARB at -41 dBmO to -50 dBmO

±1.5

NOTES:

VCC±10%,

UNIT
Vrms

Vpp
dB

±0.5

DIN to EARA and EARB at -51 dBmO to -55 dBmO
Gain variation

MAX
0.736

O-dB input signal

-t

MIN

Companded mode selected, Il-Iaw ('AC56)

= 5 V,

±2

= O°C to 70°C

±0.5

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin xlIx corrected.
10. Unless otherwise noted, the digital input is a word stream generated by passing a O-dB sine wave at 1020 Hz through an ideal
encoder, where 0 dB is defined as the zero reference.
11. This reference-signal level is measured at the speaker output of the receive channel with the gain of the output speaker amplifier
set to unity.

receive filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR =8 kHz (see Note 9)
PARAMETER

TEST CONDITIONS

MIN

fOIN = 200 Hz

-0.5

DIN = 0 dBmO

UNIT

0.15
iO.15

fOIN = 300 Hz to 3 kHz
Gain relative to gain at 1.02 kHz

MAX
0.15

fOIN = < 200 Hz

fOIN = 3.3 kHz

-0.35

0.03

fOIN = 3.4 kHz

-1

-0.18

fOIN = 4 kHz

-14

fOIN = > 4.6 kHz

-30

•
TEXAS
INSTRUMENTS
6-50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCiV1320AC56, TCiV1320AC57
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

receive idle channel noise and distortion, companded mode with /l-Iaw or A-law selected, over recommended
ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER

MIN

TEST CONDITIONS

= 11010101 (A-law)
DIN = 11111111 (Jl-Iaw)

Receive noise, psophometrically weighted

DIN

Receive noise, C-message weighted

UNIT

-75

dBOp

DIN to EARA and EARB at 0 dBmO to -18 dBmO

Receive signal-to-distortion ratio with sine-wave input

MAX

dBrncO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -30 dBmO

DIN to EARA and EARB at -31 dBmO to -38 dBmO

DIN to EAR A and EARB at -39 dBmO to -45 dBmO

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER

TEST CONDITIONS

Receive noise

DIN

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCITT distortion method,
composite power level -13 dBmO
NOTES:

MIN

=00000000

DIN to EARA and EARB at 0 dBmO to -6 dBmO

DIN to EARA and EARB at -7 dBmO to -12 dBmO

DIN to EARA and EARB at -13 dBmO to -18 dBmO

DIN to EARA and EARB at-19 dBmO to-24 dBmO

DIN to EARA and EARB at -25 dBmO to -40 dBmO

DIN to EARA and EARB at -41 dBmO to -45 dBmO

CCITT G.712 (7.1), R2

CCITT G.712 (7.2), R3

MAX

UNIT

200

JlVrms

s:w

>
w
a:

c..
t-

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 JlVrms is equivalent to -71 dB (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature

PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

-30

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EAR B)

-30

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB

Crosstalk attenuation, receive-to-transmit

DIN = 0 dBmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

All typical values are at VCC = 5 V, TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-51

:;:)

o
a.:

c..

TCM320AC56, TCM320AC57
VOICE·BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN

NOMt

MAX

Transition time, ClK and DClKX/DClKR

Duty cycle, ClK

45%

50%

55%

Duty cycle, DClKX/DClKR

45%

50%

55%

UNIT

t All typical values are at VCC =5 V, TA =25°C.
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before ClKt

468

th(FSX)

Hold time, FSX high after ClKt

468

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)

"tJ

o
C
c::

-I
"tJ

=::
m
=E

MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before ClKt

468

th(FSR)

Hold time, FSR high after ClKt

468

tsu(DIN)

Setup time, DIN high or low before ClKt

th(DIN)

Hold time, DIN high or low after ClKt

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before DClKXt

40 t c (DClKX)-40

th(FSX)

Hold time, FSX high after DClKXt

t c(DClKX)-35

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before DClKRt

th(FSR)

Hold time, FSR high after DClKRt

tsu(DIN)

Setup time, DIN high or low before DClKRt

th(DIN)

Hold time, DIN high or low after DClKRt

ns
tc (DClKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL = 0 to 10 pF (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

tpd1

From ClK bit 1 high to DOUT bit 1 valid

tpd2

From ClK high to DOUT valid, bits 2 to n

tpd3

From ClK bit n low to DOUT bit n Hi-Z

tpd4

From ClK bit 1 high to TSX active (low)

Rpull up = 1.24 kn

tpd5

From ClK bit n low to TSX inactive (high)

Rpull up

~TEXAS

INSTRUMENTS
6-52

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

= 1.24 kn

ns
ns
ns

40
30

UNIT

ns
ns

TCM320AC56, TCiv1320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER

TEST CONDITIONS

MIN

MAX

~d6

FSX high to DOUT bit 1 valid

CL = 0 to 10 pF

tpd7

DCLKX high to DOUT valid, bits 2 to n

CL= Oto 10 pF

tpd8

FSX low to DOUT bit n Hi-Z

UNIT
ns
ns
ns

PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL. Bit 1 = MSB (most significant bit) and is clocked in first on DIN
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUr. N = 8 for the companded mode, and N = 16 for the linear mode.

I
I

---------~

Receive Time Slot

N-2

N-1

ClK

->w
w
a:
a..
Io

DIN
See Note C

NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

~ tsu(DIN)

oa::

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram

a..

~I----------- Transmit Time Slot - - - - - - - - - - - . 1
2
4
N-2
N-1
N
N+1
3

1l<1li

o
ClK

20%

tsu(FSX)

~
1 I~

i .1

th(FSX)

~ ~~\~~~~~\~~~\~
1

____

~r~r

_______

_ __

See ~ote A

.L.I

tpd2

DOUT-------------+-<
See Note C

1 lte~--;I-------f------ Se~ 'Note B _ _ _ _ _ _ _ _ ---~.
tpd3 - . :

I
N

tpd1 ~

I
tpd54

i "~2~OO~~____________________~)~~---------------------J~~8~0~%---+j

I+-

tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th{FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-53

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
---------~

1 4 - - - - - - - - - - - Receive Time Slot
DCLKR

20%
1

th(FSR) ~

tsu(FSR)
FSR

((

\\\\\\\\~\\\ w
a:
c..

power-down and standby operations

INSTRUMENTS

6-55

O
::l
C

a:
c..

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS

"'C

::D

DIGITAL OUTPUT STATUS

Power on

PDN = high,
FSX = pulses,
FSR = pulses

40mW

Digital outputs active but not loaded

Power down

PDN = low,
FSX, FSR = xt

13mW

TSX and DOUT in the high-impedance state

Entire device on standby
mode

FSX = low,
FSR = low,
PDN = high

5mW

TSX and DOUT in the high-impedance state

Only transmit channel in
standby mode

FSX = low,
FSR = pulses,
PDN = high

20mW

TSX and DOUT in the high-impedance state within five
frames

Only receive channel in
standby mode

FSR = low,
FSX = pulses,
PDN = high

20mW

Digital outputs active but not loaded

X = don't care

Fixed-data-rate timing is selected by connecting DClKR to Vee and uses the master clock (ClK), frame
synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling
frequency. Data is transmitted on DOUT on the positive transitions of ClK following the rising edge of FSX. Data
is received on DIN on the falling edges of ClK following FSR. A D/A conversion is performed on the received
digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred
to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode.

o-f
"'C

TYPICAL POWER
CONSUMPTION

fixed-data-rate timing

::D

PROCEDURE

variable-data-rate timing

Variable-data-rate timing is selected by connecting DClKR to the receive data clock. In this mode, the master
clock (ClK) controls the switched-capacitor filters, while data transfer into DIN and out of DOUT is controlled
by DClKR and DClKX respectively. This allows the data to be transferred in and out of the device at any rate
up to the frequency of the master clock. DClKR and DClKX must be synchronous with ClK.

"!}TEXAS
INSTRUMENTS
6-56

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

iCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

PRINCIPLES OF OPERATION
conversion laws
The TCM320AC56 provides J..l-Iaw companding operation that approximates the CCITT G.711
recommendation. The TCM320AC57 provides A-law companding operation that approximates the CCITT
G.711 recommendation. The linear mode of operation uses a 13-bit two's-complement format and is the same
for both the TCM320AC56 and the TCM320AC57.

I--------------------~
.---_ _. . . _ - - - - - - V - M - : - : : I D : + - - - - - - - - e - VMID Reference
171
For Amplifiers
1
VMID
1
1
1
MICBIASI
20

VDD

->w
W

a:
a.
....o

I
10 kr.l

1
1
MICGSI
19
1
MICIN
18
1
1

::J
C

oa:

To Transmit Filters

MICMUTE 1
TCM320AC56/57 VBAP
1
6 --------------------~
NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.

transmit filter
A low-pass antialiasing section is included on the device and achieves a 35-dB attenuation at the sampling
frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-57

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

"'C

-I

receive filter

"'C

The receive section of the filter provides pass-band flatness and stop-band rejection that approximates both
the AT&T 03/04 specification and CCITT recommendation G.712 when operated at the recommended
frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders.

m
:::m

receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone aUdio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around VCC/2.
The receive-channel output level can be adjusted between spe,cified limits by connecting an external resistor
network to EARGS.

~TEXAS

INSTRUMENTS
6-58

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

PRINCIPLES OF OPERATION

r--------------------,
1
1

IN
~~----------;--

EARGS

EARA

1
1
1
1

1
1

>--9----------1-- EARB
1

VMID

r--------------------~

NOTE A: Terminal numbers shown are for the DW and N packages.

w
a::

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network

c..

receive data format

I-

In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).

(.)

In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB
when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received
data word.

::J
C

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-59

o
a::

c..

TCM320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016 - JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
SIT NO.

COMPANDED MODE

LINEAR MODE

CD7

LD12

CD6

LDll

CDS

LD10

CD4

LD9

CD3

LDB

CD2

LD7

CDl

LD6

CDO

LOS

LD4

9
A
B

C
D

""CJ
JJ

LD3
LD2
LDl
LDO
Vl

Volume control and other control bits always follow the PCM data in time:

C
C

Companded Mode:

-I
""CJ

MSB
(sign bit)

LSB

\CD7 CDG CDS CD4 CD3 CD2 CDl CDO/

V
Companded Data

:xJ

:$
m

Linear Mode:

MSB
(sign bit)

LSB
LD12 LDll LD10 LD9 LDS LD7 LDG LDS LD4 LD3 LD2 LD1 LDO

~------------------~v

Linear Data
Time---+

where:
CD7 -CDO = Data word when in companded mode
LD12-LDO= Data word when in linear mode
V2, V1, VO = Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

•
TEXAS
INSTRUMENTS
6-60

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

/~
Volume Control

TCiVl320AC56, TCM320AC57
VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS016-JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARS are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at EARA
Vo- at EARS
Voo = Vo+ - Vo- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kQ and less than 100 kQ for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 0.751 Vrms).
Voo =AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

EARA

->w

...

.?R1
Digital mW Sequence
~ DIN
lAW CCITT G.712

EARGS

.......

a::

<'
<

5 R2 VI
EARB

...

VO-

::l

NOTE A: Terminal numbers shown are for the DW and N packages.

a:
a.

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK' to the frame sync frequency, fFSR/fFSX' This ratio for the VSAP is 2.048 MHzl8 kHz, or 256
master clocks per frame sync. For example, to operate the VSAP at a sampling rate of fFSR and fFSX equal to
16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the VSAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric speCifications
for rates up to 16-kHz sample rate are not specified at this time.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-61

6-62

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

•

Selectable Between 8-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
TLV320AC36 ... !J,-Law and Linear Modes
- TLV320AC37 ... A-Law and Linear
Modes

Combined AID, DIA, and Filters

•

Extended Variable-Frequency Operation
- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 kHz

Programmable Volume Control in Linear
Mode

•

300 Hz - 3.6 kHz Passband with Specified
Master Clock

Electret Microphone Bias Reference
Voltage Available

Designed for Standard 2.048-MHz Master
Clock for U.S. Analog, U.S. Digital, CT2,
DECT, GSM, and PCS Standards for
Hand-Held Battery-Powered Telephones

•

Single 3-V Operation

•

Low Power Consumption:
Operating Mode . .. 20 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode . .. 2 mW Typ

•

Drive a Piezo Speaker Directly

•

Compatible With All Digital Signal
Processors (DSPs)
ow OR N PACKAGE

PTPACKAGE
(TOP VIEW)

(TOP VIEW)

Cf)

PDN
EARA
EARS
EARGS
Vee
MICMUTE
DClKR
DIN
FSR
EARMUTE

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11 ]

MICSIAS
MICGS
MICIN
VMID
GND
LlNSEl
TSXlDClKX
DOUT
FSX
ClK

~CJ«

::;!;(/)z

a: a: a: IZ en (!) zz wwwo..:2:2:2z zz

0 0 «««O~~~O 0 0

VMID
NC
AGND
NC
NC
NC
NC
NC
NC
DGND
LlNSEl
NC

NC
NC
NC
AVec
NC
NC
NC
NC
DVee
NC
MICMUTE
NC
~Xl-X
...J(/)::J~

OLLQ-l

Ne - No internal connection

...
~

VBAP is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-63

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

description
The TLV320AC36 and TLV320AC37 voice-band audio processor (VBAP) integrated circuits are designed to
perform the transmit encoding (AID conversion) and receive decoding (DIA conversion) together with transmit
and receive filtering for voice-band communications systems. Cellular telephone systems are targeted in
particular; however, these integrated circuits can function in other systems including digital audio,
telecommunications, and data acquisition.
These devices are pin-selectable for either of two modes, companded and linear, providing data in two formats.
In the companded mode, data is transmitted and received in 8-bit words. In the linear mode, 13 bits of data, and
either three bits of gain-setting control data, or three zero bits of padding to create a16-bit word, are sent and
received.
The transmit section is designed to interface directly with an electret microphone element. The microphone input
signal (MICIN) is buffered and amplified with provision for setting the amplifier gain to accommodate a range
of signal input levels. The amplified signal is passed through antialiasing and band-pass filters. The filtered
signal is then applied to the input of a compressing analog-to-digital converter (COADC) when companded
mode is selected. Otherwise, the analog-to-digital converter performs a linear conversion. The resulting data
is then clocked out of DOUT as a serial data stream.
The receive section takes a frame of serial data on DIN and converts it to analog through an expanding
digital-to-analog converter (EXDAC) when the companded mode is selected; otherwise, a linear conversion is
performed. The analog signal then passes through switched capacitor filters, which provide out-of-band
rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The
earphone amplifier has a differential output with adjustable gain and is designed to minimize static power
dissipation.
A single on-chip high-precision band-gap circuit generates all voltage references, eliminating the need for
external reference voltages. An internal reference voltage equal to Vcc/2, VMID, is used to develop the midlevel
virtual ground for all the amplifier circuits and the microphone bias circuit. Another reference voltage, MICBIAS,
can supply bias current for the microphone.
The TLV320AC3xC devices are characterized for operation from O°C to 70°C. The TLV320AC3xl devices are
characterized for operation from -40°C to 85°C .

6-64

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

functional block diagram

Transmit
Third-Order
Antialias

MICMUTE
MICIN

Transmit
Sixth-Order
Low Pass

Transmit
First-Order
High Pass

256 kHz

8 kHz

DOUT

FSX

MICGS .....:...:19=----+--+_ _---'
Band-Gap
Voltage
Reference
AID
Converter
Voltage
Reference

VMID _17~""'1+----1
MICBIAS _2:::.;0=-----+____---1
'-------'

256 kHz

D/A
Converter
Voltage
Reference

8 kHz

.--_--+_9:... FSR
2
EARA-- -........
EARB ...,;3=--_4-l Earphone
EARGS 4
Amplifier

1--_4--_8
=__

1--.......1 - 1

DIN

EARMUTE-1~0----1-_ _~

VCC

GND

PDN

NOTE A: Terminal numbers shown are for the OW and N packages .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-65

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.
DW,N

DESCRIPTION

1/0

AVCC
ClK

AGND

DClKR

DGND

DIN

Ground return for all internal analog circuits
3-V supply voltage for all internal analog circuits

Ground return for all internal digital circuits

27
8

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is elK for a fixed data rate and DClKR for a variable data rate (digital).

DOUT

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is ClK for a fixed data rate and DClKX for a variable data rate (digital).

DVCC

3-V supply voltage for all internal digital circuits

EARA

EARS

Earphone output. EARS forms a differential drive when used with the EARA signal (analog).

EARGS

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).

FSR

Frame-synchronization clock input forthe receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).

FSX

GND

LlNSEl

Linear selection input. When low, LlNSEl selects linearcoding/decoding. When high, LlNSEl selects
companded coding/decoding. Companding code on the' AC36 is ~-Iaw, and companding code on the
'AC37 is A-law (digital).

MICSIAS

Microphone bias. MICSIAS voltage for the electret microphone is equal to VMID.

MICGS

MICIN

EARMUTE

Earphone output. EARA forms a differential drive when used with the EARS signal (analog).

Ground return for all internal circuits

Microphone input. Electret microphone input to the internal microphone amplifier (analog)

MICMUTE

Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).

PDN

Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).

I/O

Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSXlDClKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DClKX becomes the transmit data
clock input (digital).

TSX/DClKX

VCC

VMID

3-V supply voltage for all internal circuits

VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors
(1 ~F and 470 pF) should be connected between VMID and ground for filtering.

~TEXAS

INSTRUMENTS
6-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 5.5 V
Output voltage range at DOUT, Va .................................................. -0.3 V to 5.5 V
Input voltage range at DIN, VI ...................................................... -0.3 V to 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: C suffix ......................................... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

PACKAGE

TA::;25°C
POWER RATING

1025 mW

8.2 mWrC

656mW

533mW

1150mW

9.2 mW/oC

736mW

598mW

1075 mW

7.1 mW/oC

756mW

649mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

recommended operating conditions (see Note 2)
MIN

MAX

Supply voltage, VCC (see Note 3)

2.7

3.3

High·level input voltage, VIH

2.2
0.8

Low-level input voltage, VIL
Load resistance between EARA and EARB, RL (see Note 4)

Operating free-air temperature, TA
NOTES:

600

Load capacitance between EARA and EARB, CL (see Note 4)

ITLV320AC36C, TLV320AC37C
I TLV320AC361, TLV320AC371

UNIT

-40

°C

2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up sequence detailed in the system
reliability features paragraph should be followed.
3. Voltages at analog inputs, outputs, and VCC are with respect to GNO.
4. RL and CL should not be applied simultaneously.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-67

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, fOCLKR or fOCLKX

=2.048 MHz, outputs not loaded, VCC =3 V, TA =25°C
TEST CONDITIONS

PARAMETER

ICC

Operating

PDN is high with ClK signal present

Supply current from VCC

Power down

PDN is low for 500 Ils

Standby-both

PDN is high with FSX and FSR held low

Standby - one

PDN is high with either FSX or FSR pulsing with the
other held low

MIN

MAX

UNIT

7.5
0.75
2

4.5

digital interface
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage

Val

low-level output voltage

IIH

High-level input current, any digital input

VI = 2.2 V to VCC
VI = Oto 0.8 V

!DOUT

IOH = -3.2 mA,

VCC=3 V

IOl= 3.2 mA,

VCC=3 V

MIN

TYPt

2.4

2.8
0.2

MAX

UNIT
V

0.4

IlA

III

low-level input current, any digital input

Input capacitance

Output capacitance

t All typical values are at VCC = 3 V, TA = 25°C.

microphone interface
PARAMETER

TEST CONDITIONS

Via

Input offset voltage at MICIN

liB

Input bias current at MICIN

Unity-gain bandwidth, open loop at MICIN:j:

Input capacitance at MICIN

large-signal voltage amplification at MICGS

lOmax

Maximum output current

MIN

TYpt

MAX
±5

VI = Oto 3 V

±200

UNIT
mV
nA
MHz

1.5
5

10000

VIV

VMID

IlA

MICBIAS
(source only)

t All typical values are at VCC = 3 V, TA = 25°C.
:j: The frequency of the first pole is 100 Hz.

speaker interface
TEST CONDITIONS

PARAMETER
VO(PP)

AC output voltage

VOO

Output offset voltage at EARA, EARB (single-ended)

Relative to GND

II(lkg)

Input leakage current at EARGS

VI = 0.5 V to (VCC - 0.5) V

lOmax

Maximum output current

Rl= 600

TYPt

Output resistance at EARA, EARB
Gain change

1
EARMUTE low, max level when muted

t All typical values are at VCC = 3 V, TA = 25°C.
§ 2.5 Vpp when Vec is 2.7 V.

•
TEXAS
INSTRUMENTS
6-68

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-60

MAX

UNIT

3§

Vpp

mVpk

±200

±2.5

n
dB

TLV320AC36, 'rLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

transmit gain and dynamic range, companded mode (Wlaw or A-law) or linear mode selected, Vee
TA = 25°C (unless otherwise noted) (see Notes 5 and 6)
TEST CONDITIONS

PARAMETER

Transmit reference-signal level (0 dB) (see Note 7)

Overload-signal level (MICIN at unity gain)

Gain error with input level relative to gain at -10 dBmO

Gain variation

MAX
0.614

Companded mode selected, A-law (,AC37)

0.616

Linear mode selected (,AC36 and 'AC37)

0.626

Companded mode selected, Jl-Iaw ('AC36)

2.5

Companded mode selected, A-law ('AC37)

2.5

Linear mode selected (,AC36 and 'AC37)

2.5

O-dB input signal

Absolute gain error

NOTES:

MIN

Companded mode selected, Jl-Iaw ('AC36)

=3 V,
UNIT

Vrms

Vpp

±1

MICIN to DOUT at 3 dBmO to -40 dBmO

±0.5

MICIN to DOUT at -41 dBmO to -50 dBmO

±1.5

MICIN to DOUT at -51 dBmO to -55 dBmO

±2

±0.5

VCC±10%,

=O°C to 70°C

5. Unless otherwise noted, the analog input is 0 dB, 1020-Hzsine wave, where 0 dB is defined as the zero-reference point of the channel
under test.
6. The input amplifier is set for inverting unity gain.
7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.

transmit filter transfer, companded mode (ll-Iaw or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, ClK =2.048 MHz, FSX =8 kHz (see Note 6)
PARAMETER

Gain relative to input signal gain at
1.02 kHz

TEST CONDITIONS

Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB

MIN

MAX

fMICIN = 50 Hz

-10

fMICIN = 200 Hz

-2.8

UNIT

0
±O.25

fMICIN = 300 Hz to 3 kHz
fMICIN = 3.3 kHz

-0.55

0.2

fMICIN = 3.4 kHz

-1

-0.1

fMICIN = 4 kHz

-14

fMICIN ~4.6 kHz

-32

NOTE 6. The input amplifier is set for inverting unity gain.

transmit idle channel noise and distortion, companded mode with ll-Iaw or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
TEST CONDITIONS

PARAMETER
Transmit noise, psophometrically weighted

MICIN connected to MICGS through a 10-kQ resistor

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kil resistor
MICIN to DOUT at 0 dBmO to -24 dBmO

Transmit signal-to-distortion ratio with sine-wave input

Intermodulation distortion, 2-tone CCITT method,
composite power level-13 dBmO

MIN

MAX

UNIT

-72

dBOp

dBrnCO

MICIN to DOUT at -25 dBmO to -30 dBmO

MICIN to DOUT at -31 dBmO to -38 dBmO

MICIN to DOUT at -39 dBmO to -40 dBmO

MICIN to DOUT at -41 dBmO to -45 dBmO

CCITTG.712 (7.1), R2

CCITT G.712 (7.2), R3

NOTE 8: Transmit noise, linear mode: 200 JlVrms is equivalent to -74 dB (referenced to device O-dB level).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-69

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
PARAMETER

TEST CONDITIONS

Transmit signal-to-distortion ratio with sine-wave input

NOTES:

MIN

MAX

UNIT

200

/lVrms

MICIN connected to MICGS through a 10-kn resistor

Transmit noise

MICIN to OOUT at 0 dBmO to -10 dBmO

MICIN to OOUT at -11 dBmO to -12 dBmO

MICIN to OOUT at -13 dBmO to -18 dBmO

MICIN to OOUT at -19 dBmO to -24 dBmO

MICIN to OOUT at -25 dBmO to -40 dBmO

MICIN to OOUT at -41 dBmO to -45 dBmO

6. The input amplifier is set for inverting unity gain.
8. Transmit noise, linear mode: 200 /lVrms is equivalent to -74 dB (referenced to device O-dB level).

receive gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected,
TA 25°C (unless otherwise noted) (see Notes 9 and 10)

TEST CONDITIONS

PARAMETER
Receive reference-signal level (0 dB) (see Note 11)

Overload-signal level

MIN

0.736

Companded mode selected, A-law CAC37)

0.739

Linear mode selected CAC36 and 'AC37)

0.751

Companded mode selected, /l-Iaw CAC36)

Companded mode selected, A-law CAC37)

Gain variation
NOTES:

±1

OIN to EARA and EARB at 3 dBmO to -38 dBmO

±0.5

OIN to EARA and EARB at -39 dBmO to -50 dBmO

±1.5

OIN to EARA and EARB at -51 dBmO to -55 dBmO

±2
±0.5

TA = O°C to 70°C

VCC±10%,

=3 V,
UNIT
Vrms

Vpp

O-dB input signal

Gain error with output level relative to gain at -10 dBmO

MAX

Companded mode selected, /l-Iaw CAC36)

Linear mode selected ('AC36 and 'AC37)
Absolute gain error

Vee

dB
dB
dB

receive filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR 8 kHz (see Note 9)

PARAMETER

MIN

TEST CONDITIONS

-0.5

fOIN = 200 Hz
OIN = 0 dBmO

0.25

fOIN = 3.3 kHz

-0.55

0.2

fOIN = 3.4 kHz

-1

-0.1

-14

fOIN =4 kHz
fOIN = > 4.6 kHz

UNIT

±0.25

fOIN = 300 Hz to 3 kHz
Gain relative to gain at 1.02 kHz

MAX
0.25

fOIN = < 200 Hz

-30

NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.

~TEXAS

INSTRUMENTS
6-70

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TlV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

receive idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over recommended
ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER

TEST CONDITIONS

MIN

= 11010101 (A-law)
DIN = 11111111 (Il-Iaw)

Receive noise, psophometrically weighted

DIN

Receive noise, C-message weighted

NOTE 9.

UNIT

-72

dSOp

DIN to EARA and EARS at 0 dSmO to -18 dSmO

Receive signal-to-distortion ratio with sine-wave input

MAX

dSrncO

DIN to EARA and EARS at -19 dSmO to -24 dBmO

DIN to EARA and EARS at -25 dSmO to -30 dBmO

DIN to EARA and EARS at -31 dSmO to -38 dBmO

DIN to EARA and EARS at -39 dSmO to -45 dBmO

Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS is
connected to EARS and the output is taken between EARA and EARS. All output levels are (sin x)/x corrected.

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER

TEST CONDITIONS

Receive noise

DIN

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCITT distortion method,
composite power level -13 dSmO
NOTES:

MIN

=00000000

DIN to EARA and EARS at 0 dSmO to -12 dSmO

DIN to EARA and EARS at -13 dSmO to -18 dBmO

DIN to EARA and EARS at -19 dSmO to -24 dBmO

DIN to EARA and EARS at -25 dSmO to -40 dBmO

DIN to EARA and EARS at -41 dSmO to -45 dBmO

CCITT G.712 (7.1), R2

CCITT G.712 (7.2), R3

MAX

UNIT

200

IlVrms

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARS and the output is taken between EARA and EARS. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 IlVrms is equivalent to -71 dS (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

-30

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARS,
f = 0 to 30 kHz (measured differentially between EARA
and EARS)

-30

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dS, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARS,
measured differentially between EARA and EARS

Crosstalk attenuation, receive-to-transmit

DIN = 0 dSmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

All typical values are at VCC

=3 V, TA = 25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-71

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN
tt

NOMt

MAX

Transition time, ClK and DClKX/DClKR

Duty cycle, ClK

45%

50%

55%

Duty cycle, DClKX/DClKR

45%

50%

55%

UNIT
ns

t All typical values are at VCC = 3 V, TA =25°C.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before ClK.!.

468

th(FSX)

Hold time, FSX high after ClK.!.

468

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)
MIN

MAX

tsu(FSR)

Setup time, FSR high before ClK.!.

468

UNIT
ns

th(FSR)

Hold time, FSR high after ClK.!.

468

tsu(DIN)

Setup time, DIN high or low before ClK.!.

th(DIN)

Hold time, DIN high or low after ClK.!.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before DClKX.!.

tc (DClKX)-40

th(FSX)

Hold time, FSX high after DClKX.!.

tc (DClKX)-35

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

UNIT

MAX

tsu(FSR)

Setup time, FSR high before DClKR.!.

th(FSR)

Hold time, FSR high after DClKR.!.

tsu(DIN)

Setup time, DIN high or low before DClKR.!.

th(DIN)

Hold time, DIN high or low after DClKR.!.

tc (DClKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL = 0 to 10 pF (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd1

From ClK bit 1 high to DOUT bit 1 valid

tpd2

From ClK high to DOUT valid, bits 2 to n

tpd3

From ClK bit n low to DOUT bit n Hi-Z

tpd4

From ClK bit 1 high to TSX active (low)

Rpull up = 1.24 kQ

tpd5

From ClK bit n low to TSX inactive (high)

Rpull up

~TEXAS

INSTRUMENTS
6-72

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

= 1.24 kQ

40
30

ns
ns

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
TEST CONDITIONS

PARAMETER

MAX

MIN

UNIT

tpd6

FSX high to DOUT bit 1 valid

Cl = 0 to 10 pF

tpd7

DClKX high to DOUT valid, bits 2 to n

Cl= Oto 10 pF

tr>_d8

FSX low to DOUT bit n Hi-Z

PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL. Bit 1 = MSB (most significant bit) and is clocked in first on DIN
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUT. N = 8 for the companded mode, and N = 16 for the linear mode.
Receive Time Slot

JIIII

I1
I

--------~~

N-2

N-1

DIN

I I
---+i I+-

See Note C
NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

tsu(DIN)

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram

1l1li
ClK

--1+.1
i .1
I 1l1li

th(FSX)

N-2

N-1

N+1

20%
tsu(FSX)

FSX

Transmit Time Slot ---------~I

~'\V!\
\\3~\\\
,_':1Y
1 D~\.::o_""'\j,.,\j,.,\"'\""'_ _--+-_ _ _ _ _

--i(\"'(_ _ _ _ _ _ _ _ _....;-_ _ __

1l1li

1 1411111~1c___------_I_----- Se~ JNote B - - - - - - - - " ' - - - - -.....
.1 See Note A
l+I

DOUT-------+I~

See Note C

tpd1 ~

I
tpd54

i \
~

1--8~0"lc~oI

20%

((

j4- tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-73

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

1 4 - - - - - - - - - - Receive Time Slot

----------~

N-2

N-1

DCLKR

FSR

DIN
See NoteC
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram

1
....,..1----------- Transmit Time Slot -----------.~I
1

N-2

N-1

DCLKX

20%

th(FSX) --.:
J}

FSX

\\\\~~

See Note B

~u.~...>.J'-",\~~--1l1li
I .1

tpd8 ---.j
DOUT ------~~
See NoteC
1....lO........._
NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.

Figure 4. Variable-Data Rate Mode, Transmit Side Timing Diagram

~TEXAS

6-74

N+1

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1.-

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
general
system reliability features
The device should be powered up and initialized as follows:
1.

Apply GND.

Apply Vee.

Connect all clocks.

Apply TTL high to PON.

Apply synchronizing pulses to FSX and/or FSR.

Even though the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain
improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode (with
a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) should be connected between
Vee (power supply) and GNO.
On the transmit channel, digital outputs OOUT and TSX are held in the high-impedance state for approximately
four frames (500 /ls) after power up or application of Vee. After this delay, OOUT, TSX, and signaling are
functional and occur in the correct time slot. The analog circuits on the transmit side require approximately
60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system
integrity, OOUT and TSX are placed in the high-impedance state after an interruption of ClK.

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PON. In the absence of a signal, PON is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 2 mW.
Three standby modes give the user the option of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR
is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When
the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and
standby procedures.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-75

TLV320AC36,TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS

PROCEDURE

TYPICAL POWER
CONSUMPTION

DIGITAL OUTPUT STATUS

Power on

PDN =high,
FSX =pulses,
FSR =pulses

Power down

rON = low,
FSX, FSR =xt

2mW

TSX and DOUT in the high-impedance state

Entire device on standby
mode

FSX =low,
FSR =low,
PDN =high

SmW

TSX and DOUT in the high-impedance state

Only transmit channel in
standby mode

FSX = low,
FSR =pulses,
PDN = high

10mW

TSX and DOUT in the high-impedance state within five
frames

Only receive channel in
standby mode

FSR =low,
FSX =pulses,
PDN =high

10mW

Digital outputs active but not loaded

20mW

Digital outputs active but not loaded

X = don't care

fixed-data-rate timing
Fixed-data-rate timing is selected by connecting DClKR to Vee and uses the master clock (ClK), frame
synchronization clocks (FSX and FSR), and the TSX output. FSX and FSR are inputs that set the sampling
frequency. Data is transmitted on DOUT on the positive transitions of ClK following the rising edge of FSX. Data
is received on DIN on the falling edges of ClK following FSR. A D/A conversion is performed on the received
digital word, and the resulting analog sample is held on an internal sample-and-hold capacitor until transferred
to the receive filter. The data word is eight bits long in the companded mode and 16 bits long in the linear mode.

~TEXAS

INSTRUMENTS
6-76

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
conversion laws
The TLV320AC36 provides Il-Iaw companding operation that approximates the CCITT G. 711 recommendation.
The TLV320AC37 provides A-law companding operation that approximates the CCITT G. 711 recommendation.
The linear mode of operation uses a 13-bit two's-complement format and is the same for both the TLV320AC36
and the TLV320AC37.
transmit operation
microphone input
The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as
shown in Figure 5. The VMID buffer circuit provides a voltage (MICBIAS) equal to 1/2 Vee as a reference for
the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output
(MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to
set the amplifier gain. In the companded mode, when the MICIN signal level decreases to a level near the noise
floor, the VBAP mutes the signal and outputs zero bits while continuing to monitor the signal level. When the
input level once again exceeds the noise threshold, the mute is released and normal operation resumes. Input
hysteresis is provided to ensure noiseless transitions in to and out of the muted condition. VMID appears at a
terminal to provide a place to filter the VMID voltage.

I--------------------~
.----_ _....._ _ _ _ _ _V--'M..;..I___
D : + - - - - - - - - - . . - - VMID Reference
171
For Amplifiers

I
I
I
I

VDD

VMID

MICBIASI
20 I

10kn

I
I
I
MICGSI
19
I
MICIN

To Transmit Filters

I
MICMUTE I
I
6

TLV320AC36/37 VBAP

-----------------------1

NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.
transmit filter
A low-pass anti aliasing section is included on the device and achieves a 35-dB attenuation at the sampling
frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-77

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

receive operation
decoding
In the companded mode, the serial data word is received at DIN on the first eight clock cycles in fixed-data rate
and on the last eight clock cycles in variable-data rate. In the linear mode, the serial data word is received at
DIN on the first 13 clock cycles. D/A conversion is performed, and the corresponding analog sample is held on
an internal sample-and-hold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that approximates both
the AT&T 03/04 specification and CCITT recommendation G.712 when operated at the recommended
frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders.
receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone aUdio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around VCC/2.
The receive-channel output level can be adjusted between specified limits by connecting an external resistor
network to EARGS.

~TEXAS

INSTRUMENTS
6-78

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION

r--------------------,
1
1

t---t-- EARGS

~~----------~-

EARA

1
1
1
1

>--.-----+-VMID

EARB

r--------------------~
NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network
receive data format
In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).
In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB
when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received
data word.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-79

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.

COMPANDED MODE

LINEAR MODE

CD7

LD12

CD6

LD11

CD5

LD10

CD4

LD9

CD3

LD8

CD2

LD7

CD1

LD6

CDO

LD5

LD4

9
A

B
C
D
E
F

LD3
LD2
LD1
LDO
V2
V1
VO

Volume control and other control bits always follow the PCM data in time:
Companded Mode:

MSB
(sign bit)

LSB
,CD7 CDS CDS CD4 CD3 C02 CD1 COOl
V
Companded Data

Linear Mode:

MSB
(sign bit)

LSB
LD12 LD11 LD10 LOg LOS LD7 LOS LOS LD4 LD3 LD2 LD1 LOa

~----------------~~V

Linear Data
Time--.

where:
CD7-CDO = Data word when in companded mode
LD12-LDO= Data word when in linear mode
V2, V1,
= Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

~TEXAS

INSTRUMENTS
6-80

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I~
Volume Control

TLV320AC36, TLV320AC37
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS006A - NOVEMBER 1994 - REVISED JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at EARA
VO- at EARB
VOD = VO+ - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kQ and less than 100 kQ for R1 + R2 is recommended because of the following:
The parallel combination R 1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 1.001 Vrms).
VOD=AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

EARA 1-2---1~---It--_--r-______""'- VO+
R1
Digital mW Sequence
lAW CCITT G.712

DIN

EARGS 1--4---"
R2

EARB r3~~---It--_~______. - VO-

NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK, to the frame sync frequency, fFSR/fFSX. This ratio for the VBAP is 2.048 MHz/8 kHz, or 256
master clocks per frame sync. For example, to operate the VBAP at a sampling rate of fFSR and fFSX equal to
16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the VBAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-81

6-82

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

•

Single 3-V Operation

•

Low Power Consumption:
Operating Mode . .. 20 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode . .. 2 mW Typ

Combined AID, DIA, and Filters

o Extended Variable-Frequency Operation
- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 kHz

o Electret Microphone Bias Reference
Voltage Available
•

Drive a Piezo Speaker Directly

•

Compatible With All Digital Signal
Processors (DSPs)

•

Selectable Between a-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
- TLV320AC40 . .. Jl-Law and Linear Modes
- TLV320AC41 ... A-Law and Linear
Modes

•

Programmable Volume Control in Linear
Mode

300 Hz 3.6 kHz Passband with Specified
Master Clock

Designed for Standard 1.152-MHz Master
Clock in DECT Standard for Hand-Held
Battery-Powered Telephones

ow OR N PACKAGE

PT PACKAGE
(TOP VIEW)

(TOP VIEW)

C/}

PDN
EARA
EARB
EARGS
Vee
MICMUTE
DClKR
DIN
FSR
EARMUTE[

1
2
3
4
5
6
7
8
9
10

MICBIAS
19 MICGS
18 MICIN
17 VMID
16 GND
15 LlNSEl
14 TSXlDClKX
13 DOUT
12 FSX
11] ClK

~co==W

oo
W
a:
a.

::)

0
a:
a.

NOTE A: Terminal numbers shown are for the DW and N packages.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-85

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.
DW,N

AVCC
ClK

AGND

DClKR

DGND

o
c

o-I
"'C

Ground return for all internal analog circuits

DIN

"'C

3-V supply voltage for all internal analog circuits

Ground return for all internal digital circuits

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is ClK for a fixed data rate and DClKR for a variable data rate (digital).

DOUT

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is ClK for a fixed data rate and DClKX for a variable data rate (digital).

DVCC

3-V supply voltage for all internal digital circuits

EARA

EARB

a
a

EARGS

Earphone gain set input of feedback signal for the earphone output. The ratio of an external potential
divider network connected across EAR A and EARB adjusts the power amplifier gain. Maximum gain
occurs when EARGS is connected to EARB. Minimum gain occurs when EARGS is connected to
EARA. Earphone frequency response correction is performed using an RC approach (analog).

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).

FSR

Frame-synchronization clock input forthe receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).

FSX

GND

LlNSEl

MICBIAS

MICGS

a
a

MICIN

EARMUTE

-m
<

DESCRIPTION

1/0

Earphone output. EARA forms a differential drive when used with the EARB signal (analog).
Earphone output. EARB forms a differential drive when used with the EARA signal (analog).

Ground return for all internal circuits
Linearselection input. When low, LlNSElselects linear coding/decoding. When high, LlNSEl selects
companded coding/decoding. Companding code on the' AC40 is Jl-Iaw, and companding code on the
'AC41 is A-law (digital).
Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID.
Output of the internal microphone amplifier. MICGS is used as the feedback to set the microphone
amplifier gain. If sidetone is required, it is accomplished by connecting a series network between
MICGS and EARGS (analog).

Microphone input. Electret microphone input to the internal microphone amplifier (analog)

MICMUTE

Microphone input mute control Signal. When MICMUTE is active (low), zero code is transmitted (dig.).

PDN

Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).

I/O

Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSXlDClKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DClKX becomes the transmit data
clock input (digital).

TSXlDClKX

VCC

VMID

3-V supply voltage for all internal circuits

VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors
(1 JlF and 470 pF) should be connected between VMID and ground for filtering.

~TEXAS

INSTRUMENTS
6-86

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

absolute maxir:num ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 5.5 V
Output voltage range at DOUT, Va .................................................. -0.3 V to 5.5 V
Input voltage range at DIN, VI ...................................................... -0.3 V to 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: C suffix ......................................... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

TA:525°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

1150mW

1075 mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

8.2 mW/oC

656mW

533mW

9.2 mW/oC

736mW

598mW

7.1 mW/oC

756mW

649mW

recommended operating conditions (see Note 2)
MIN

MAX

Supply voltage, VCC (see Note 3)

2.7

3.3

High-level input voltage, VIH

2.2
0.8

Low-level input voltage, VIL
Load resistance between EARA and EARS, RL (see Note 4)

ITLV320AC40C, TLV320AC41 C

Operating free-air temperature, TA
NOTES:

600

Load capacitance between EARA and EARS, CL (see Note 4)

I TLV320AC401, TLV320AC41I

UNIT

-40

°c

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-87

w
5>
w
a:
a.
Io
::)
c

oa:

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, fOCLKR or fOCLKX = 1.152 MHz, outputs not loaded, VCC = 3 V, TA = 25°C
TEST CONDITIONS

PARAMETER

ICC

Supply current from VCC

Operating

PDN is high with ClK signal present

MIN

MAX

UNIT

7.5

0.75

Power down

PDN is low for 500

Standby - both

PDN is high with FSX and FSR held low

Standby - one

PDN is high with either FSX or FSR pulsing with the
other held low

4.5

digital interface
PARAMETER

""0

::c
c

c:
o

TEST CONDITIONS

VOH

High-level output voltage

VOL

low-level output voltage

IIH

High-level input current, any digital input

VI = 2.2 V to VCC
VI = Oto 0.8 V

DOUT

2.8
0.2

MAX

UNIT
V

0.4

Input capacitance

Output capacitance

t All typical values are at VCC = 3 V, TA = 25°C.

microphone interface
PARAMETER

TEST CONDITIONS

-I

Input bias current at MICIN

Unity-gain bandwidth, open loop at MICIN+

""0

Input capacitance at MICIN

large-signal voltage amplification at MICGS

lomax

Maximum output current

VCC = 3V

TYPt

2.4

low-level input current, any digital input

liB

-m

IOl=3.2 mA,

MIN

III

Input offset voltage at MICIN

m
<

VCC= 3 V

VIO

::c

IOH = -3.2 mA,

MIN

TYPt

MAX
±5

VI = Oto 3 V

±200

IVMID

mV
nA
MHz

1.5

IMICBIAS
(source only)

UNIT

10000

VIV

t All typical values are at VCC =3 V, TA = 25°C.
+ The frequency of the first pole is 100 Hz.

speaker interface
PARAMETER

TEST CONDITIONS

VO(PP)

AC output voltage

VOO

Output offset voltage at EARA, EARB (single-ended)

Relative to GND

11(lkq)

Input leakage current at EARGS

VI = 0.5 V to (VCC - 0.5) V

lOmax

Maximum output current

Rl = 600 n

Output resistance at EARA, EARB

t All typical values are at VCC
§ 2.5 Vpp when VCC is 2.7 V.

TYPt

1
EARMUTE low, max level when muted

Gain change

= 3 V, TA = 25°C.

•
TEXAS
INSTRUMENTS
6-88

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-60

MAX

UNIT

3§

Vpp

mVpk

±200

±2.5

n
dB

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

transmit gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee = 3 V,
TA =25°C (unless otherwise noted) (see Notes 5 and 6)
TEST CONDITIONS

PARAMETER

Transmit reference-signal level (0 dB) (see Note 7)

Overload-signal level (MICIN at unity gain)

MIN

0.614

Companded mode selected, A-law (,AC41)

0.616

Linear mode selected (,AC40 and 'AC41)

0.626

Companded mode selected, Il-Iaw (,AC40)

2.5

Companded mode selected, A-law (,AC41)

2.5

Linear mode selected (,AC40 and 'AC41)

2.5

Gain error with input level relative to gain at -10 dBmO

Gain variation

UNIT

Vrms

Vpp

±1

MICIN to DOUT at 3 dl3rnO to -40 dBmO

±0.5

MICIN to DOUT at -41 dBmO to -50 dBmO

±1.5

MICIN to DOUT at -51 dBmO to -55 dBmO

±2

±0.5

O-dB input signal

Absolute gain error

MAX

Companded mode selected, Il-Iaw (,AC40)

TA = O°C to 70°C

VCC±10%,

NOTES: 5. Unless otherwise noted, the analog input is 0 dB, 1020-Hz sine wave, where 0 dB is defined as the zero-reference pomt ofthe channel
under test.
6. The input amplifier is set for inverting unity gain.
7. The reference-signal level, which is input to the transmit channel, is defined as a value 3 dB below the full-scale value of 2 V.

transmit filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, ClK = 1.152 MHz, FSX = 8 kHz (see Note 6)
PARAMETER

TEST CONDITIONS

=50 Hz
fMICIN =200 Hz
fMICIN =300 Hz to 3 kHz
fMICIN =3.3 kHz
fMICIN =3.4 kHz
fMICIN =4 kHz
fMICIN

Gain relative to input signal gain at
1.02 kHz

Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB

MIN

MAX

-10

-2.8

UNIT

0
0.2

-1

-0.1

-32

transmit idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
TEST CONDITIONS

PARAMETER

MICIN connected to MICGS through a 10-kQ resistor

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kQ resistor

Transmit signal-to-distortion ratio with sine-wave input

Intermodulation distortion, 2-tone CCITT method,
composite power level-13 dBmO

MIN

MAX

UNIT

-72

dBOp

MICIN to DOUT at 0 dBmO to -24 dBmO

MICIN to DOUT at -25 dBmO to -30 dBmO

MICIN to DOUT at -31 dBmO to -38 dBmO

MICIN to DOUT at -39 dBmO to -40 dBmO

MICIN to DOUT at -41 dBmO to -45 dBmO

CCITTG.712 (7.1), R2

CCITT G.712 (7.2), R3

dBrnCO

NOTE 8: Transmit noise, linear mode: 200 IlVrms IS equivalent to -74 dB (referenced to deVice O-dB level).

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTE 6. The input amplifier is set for inverting unity gain.

Transmit noise, psophometrically weighted

I:l
C

-14

fMICIN ~4.6 kHz

±0.25
-0.55

3:
w
>
w
a:

6-89

a:
a.

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
PARAMETER

TEST CONDITIONS

Transmit noise

MIN

MICIN connected to MICGS through a 10-kn resistor

Transmit signal-to-distortion ratio with sine-wave input

MICIN to DOUT at 0 dBmO to -10 dBmO

MICIN to DOUT at -11 dBmO to -12 dBmO

MICIN to DOUT at -13 dBmO to -18 dBmO

MICIN to DOUT at -19 dBmO to -24 dBmO

MICIN to DOUT at -25 dBmO to -40 dBmO

MICIN to DOUT at -41 dBmO to -45 dBmO

MAX

UNIT

200

IlVrm s

NOTES: 6. The Input amplifier IS set for Invertmg unity gain .
8. Transmit noise, linear mode: 200 IlVrms is equivalent to -74 dB (referenced to device O-dB level).

receive gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee
TA =25°C (unless otherwise noted) (see Notes 9 and 10)
PARAMETER

TEST CONDITIONS

Receive reference-signal level (0 dB) (see Note 11)

:tJ

o
C

c:
o

-I

:tJ

MIN

0.736

Companded mode selected, A-law (,AC41)

0.739

Linear mode selected (,AC40 and 'AC41)

0.751

Companded mode selected, Il-Iaw (,AC40)
Overload-signal level
Absolute gain error

Gain variation
NOTES:

<
-

Linear mode selected (,AC40 and 'AC41)

3
±1

DIN to EARA and EARB at 3 dBmO to -38 dBmO

±0.5

DIN to EARA and EARB at -39 dBmO to -50 dBmO

±1.5

DIN to EARA and EARB at -51 dBmO to -55 dBmO

±2

TA = O°C to 70°C

VCC±10%,

UNIT

Vrms

Companded mode selected, A-law (,AC41)
O-dB input signal

Gain error with output level relative to gain at -10 dBmO

MAX

Companded mode selected, Il-Iaw (,AC40)

=3 V,

±O.5

Vpp
dB
dB
dB

receive filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR = 8 kHz (see Note 9)
PARAMETER

TEST CONDITIONS

MIN

fDIN = 200 Hz

-0.5

DIN = 0 dBmO

UNIT

0.25
±0.25

fOIN = 300 Hz to 3 kHz
Gain relative to gain at 1.02 kHz

MAX

0.25

fOIN = < 200 Hz

fOIN = 3.3 kHz

-0.55

0.2

fDIN = 3.4 kHz

-1

-0.1

fOIN =4 kHz

-14

fDiN = > 4.6 kHz

-30

•
TEXAS
INSTRUMENTS
6-90

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

receive idle channel noise and distortion, companded mode with /.!-Iaw or A-law selected, over recommended
ranges of supply voltage and operating free-air ~emperature (see Note 9)
PARAMETER

TEST CONDITIONS

= 11010101

Receive noise, psophometrically weighted

DIN

Receive noise, C-message weighted

DIN = 11111111 (~-Iaw)

MIN

(A-law)

NOTE 9.

UNIT

-72

dBOp

DIN to EARA and EARB at 0 dBmO to -18 dBmO

Receive signal-to-distortion ratio with sine-wave input

MAX

dBrncO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -30 dBmO

DIN to EARA and EARB at -31 dBmO to -38 dBrnO

DIN to EARA and EARB at -39 dBmO to -45 dBmO

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER

TEST CONDITIONS

Receive noise

DIN

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCID distortion method,
composite power level -13 dBmO
NOTES:

MIN

=00000000

DIN to EARA and EARB at 0 dBmO to -12 dBmO

DIN to EARA and EARB at -13 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -40 dBmO

DIN to EARA and EARB at -41 dBmO to -45 dBmO

CCID G.712 (7.1), R2

CCID G.712 (7.2), R3

MAX

UNIT

200

~Vrms

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 ~Vrms is equivalent to -71 dB (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EARB)

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB

Crosstalk attenuation, receive-to-transmit

DIN = 0 dBmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

All typical values are at VCC = 3 V, TA

-30

D..

:::l

D..
-30

=25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-91

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN

NOMt

MAX

Transition time, ClK and DClKX/DClKR

Duty cycle, ClK

45%

50%

55%

Duty cycle, DClKX/DClKR

45%

50%

55%

UNIT

t All typical values are at VCC = 3 V, TA = 25°C.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

tsu(FSX)

Setup time, FSX high before ClKt

468

th(FSX)

Hold time, FSX high after ClKt

468

UNIT

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)

"'tI

o
C

Co
-I
"'tI

m
S

m
~

MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before ClKt

468

th(FSR)

Hold time, FSR high after ClKt

468

tsu(DIN)

Setup time, DIN high or low before ClKt

th(DIN)

Hold time, DIN high or low after ClKt

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MIN

MAX

UNIT

tsu(FSX)

Setup time, FSX high before DClKXt

40 tc (DClKX)-40

th(FSX)

Hold time, FSX high after DClKXt

tc (DClKX)-35

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

MAX

UNIT

tsu(FSR)

Setup time, FSR high before DClKRt

th(FSR)

Hold time, FSR high after DClKRt

tsu(DIN)

Setup time, DIN high or low before DClKRt

th(DlN)

Hold time, DIN high or low after DClKRt

tc (DClKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL =0 to 10 pF (see Figure 2)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd1

From ClK bit 1 high to DOUT bit 1 valid

tpd2

From ClK high to DOUT valid, bits 2 to n

tpd3

From ClK bit n low to DOUT bit n Hi-Z

tpd4

From ClK bit 1 high to TSX active (low)

Rpull up = 1.24 kn

tpd5

From ClK bit n low to TSX inactive (high)

Rpullup= 1.24 kn

~TEXAS

6-92

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

40
30

ns
ns

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

tpd6

FSX high to DOUT bit 1 valid

CL = 0 to 10 pF

tpd7

DCLKX high to DOUT valid, bits 2 to n

CL=Ot010pF

tpd8

FSX low to DOUT bit n Hi-Z

PARAMETER MEASUREMENT INFORMATION
All timing parameters are referenced to VIH and VIL. Bit 1 = MSB (most significant bit) and is clocked in first on DIN
or clocked out first on DOUT. Bit n = LSB (least significant bit) and is clocked in last on DIN or is clocked out last on
DOUr. N =8 for the companded mode, and N = 16 for the linear mode.

I
I

---------~

Receive Time Slot

N-2

N-1

3=
w
>
w
• a:
a.

DIN

I0
::l
C

I I

See Note C

NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

~ tSu(DIN)

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram
I..

a::

Transmit Time Slot - - - - - - - - - - - .

N-2

N-1

N+1

DOUT ..............................-+~
See Note C

tpdS

1~8~Oo/c~o-

20%

\4-

((

tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-93

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
1 4 - - - - - - - - - - Receive Time Slot

---------~

DCLKR

FSR

DIN
See Note C

NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram

"tJ
:IJ

l<1li141---------- Transmit Time Slot - - - - - - - - - -...1

o
C
c

FSX

"tJ
:IJ

N-2

N-1

th(FSX) -.:

----""-loo$~~ i
See Note A

tpd6 ~

N+1

I+-

\\\\~~

((

~~~...>.j'~""'\...lop~---

See Note B

,.1

tpd8 -..j

14-1

DOUT -----~~F
See Note C
\..L'o....lol...;~--'

'-----'

' - - - - - - I '---""",,'r---'

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.

Figure 4. Variable-Data Rate Mode, Transmit Side Timing Diagram

"TEXAS
INSTRUMENTS
6-94

20%

~ tsu(FSX)

-I

m
<
m

DCLKX

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1..-

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

PRINCIPLES OF OPERATION
general
system reliability features
The device should be powered up and initialized as follows:
1.

Apply GND.

Apply Vee.

Connect all clocks.

Apply TTL high to PDN.

Apply synchronizing pulses to FSX and/or FSR.

Even though the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain
improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode (with
a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) should be connected between
Vee (power supply) and GND.
On the transmit channel, digital outputs DOUT and TSX are held in the high-impedance state for approximately
four frames (500 Jls) after power up or application of Vee. After this delay, DOUT, TSX, and signaling are
functional and occur in the correct time slot. The analog circuits on the transmit side require approximately
60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system
integrity, DOUT and TSX are placed in the high-impedance state after an interruption of ClK.

->w
W

power-down and standby operations

a..

To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external low signal is applied to PDN. In the absence of a signal, PDN is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 2 mW.
Three standby modes give the user the option of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR
is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When
the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and
standby procedures.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-95

....(.)
:::l
C

II:

a..

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS

Power on

Power down
Entire device on standby
mode
Only transmit channel in
standby mode
Only receive channel in
standby mode

"tJ

o
c
c

=high,
=pulses,
=pulses
PDN =low,
FSX, FSR =xt
FSX =low,
FSR =low,
PDN =high
FSX = low,
FSR =pulses,
PDN =high
FSR =low,
FSX =pulses,
PDN =high
PDN
FSX
FSR

TYPICAL POWER
CONSUMPTION
20mW

DIGITAL OUTPUT STATUS

Digital outputs active but not loaded

2mW

TSX and DOUT in the high-impedance state

5mW

TSX and DOUT in the high-impedance state

10mW

TSX and DOUT in the high-impedance state within five
frames

10mW

Digital outputs active but not loaded

-I
"tJ

:c
m
S
m

PROCEDURE

While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DClKX.
Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of
DClKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as
DClKX is pulsed and FSX is held high. This feature, which allows the data word to be transmitted more than
once per frame, is available only with variable-data-rate timing.
asynchronous operations
To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters,
filters, and voltage references on the transmit and receive sides to allow completely independent operation of
the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be synchronized
at the beginning of each frame.
precision voltage references
A precision band-gap reference voltage is generated internally and is used to supply all the references required
for operation of both the transmit and receive channels. The gain in each channel is trimmed during the
manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage
and device temperature.

~TEXAS

6-96

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

PRINCIPLES OF OPERATION
conversion laws
The TLV320AC40 provides J.l-Iaw companding operation that approximates the CCITT G.711 recommendation.
The TLV320AC41 provides A-law companding operation that approximates the CCITT G.711 recommendation.
The linear mode of operation uses a 13-bit two's-complement format and is the same for both the TLV320AC40
and the TLV320AC41.

transmit operation
microphone input
The microphone input amplifier is designed specifically to interface to electret-type microphone elements, as
shown in Figure 5. The VMID buffer circuit provides a voltage (MICBIAS) equal to 1/2 Vee as a reference for
the microphone amplifier and a bias voltage to the electret microphone. The microphone amplifier output
(MICGS) is used in conjunction with a feedback network and applied to the amplifier inverting input (MICIN) to
set the amplifier gain. In the companded mode, when the MICIN signal level decreases to a level near the noise
floor, the VBAP mutes the Signal and outputs zero bits while continuing to monitor the signal level. When the
input level once again exceeds the noise threshold, the mute is released and normal operation resumes. Input
hysteresis is provided to ensure noiseless transitions in to and out of the muted condition. VMID appears at a
terminal to provide a place to filter the VMID voltage.
.---_____------V.:....:M~I.::.D-I---------_e_- VMID Reference
171
For Amplifiers

I
I
I
I

VDD

a:
c.
Io

VMID

MICBIASI
20 I

2kO
3.3JlF

+
10 kO
Electret
Microphone

10 kO

c
o

I
I
I

a:
c.

MICGSI
19
I
MICIN
18

To Transmit Filters

I
MICMUTE I
I
6

->w==
W

I--------------------~

TLV320AC40/41 VBAP

----------------------'J

NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.

transmit filter
A low-pass antialiasing section is included on the device and achieves a 35-dB attenuation at the sampling
frequency. No external components are required to provide the necessary anti aliasing function for the
switched-capacitor section of the transmit filter.

·~TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-97

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

""C

-I
""C

receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that approximates both
the AT&T 03/04 specification and CCITT recommendation G.712 when operated at the recommended
frequencies. The filter contains the required compensation for the (sin x)/x response of such decoders.

<
-

receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone aUdio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around Vcc/2.
The receive-channel output level can be adjusted between specified limits by connecting an external resistor
network to EARGS.

~TEXAS

INSTRUMENTS
6-98

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC40, TLV320AC4'1
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045 - JUNE 1996

PRINCIPLES OF OPERATION

r--------------------j,
,

'4
IN

,
,

EARGS

EARA

,
,
,
,

'3
VMID

EARS

w
5>

r--------------------~

NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network

a..

receive data format
In the companded mode, eight bits of data are received. The sign bit is the first bit received (see Table 2).
In the linear mode, 16 bits of data are received. The first 13 bits are the D/A code, and the remaining three bits
form the volume control word (see Table 2). The volume control function is actually an attenuation control in
which the first bit received is the most significant. The maximum volume occurs when all three volume control
bits are zero. Eight levels of attenuation are selectable in 3-dB steps, giving a maximum attenuation of 21 dB
when all bits are 1s. The volume control bits are not latched into the VBAP and must be present in each received
data word.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-99

.-o

:J
C

II:

a..

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.

COMPANDED MODE

LINEAR MODE

CO?

lO12

C06

L011

C05

L010
L09

C04

C03

LOB

CO2

lO?

C01

lO6

COO

L05

B
9
A

L04

L03

lO2

L01

LOO

'"tJ
JJ

V2
V1

Volume control and other control bits always follow the PCM data in time:

Companded Mode:

MSB
(sign bit)

LSB
,CD7 COG CDS CD4 CD3 C02 CD1 CDO/
V
Companded Data

-t
'"tJ
JJ

m
S

Linear Mode:

MSB
(sign bit)

LSB
LD12 LD11 LD10 LOg LOS LD7 LOG LOS LD4 LD3 LD2 LD1 LDO

~------------------~v

Linear Data
Time----+

where:
CD? -COO = Data word when in companded mode
LD12-LDO= Data word when in linear mode
V2, V1, VO = Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

~TEXAS

INSTRUMENTS
6-100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

/~
Volume Control

TLV320AC40, TLV320AC41
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS045-JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARS are low-impedance complementary outputs. The voltages at the nodes are:
Vo+ at EARA
Vo- at EARS
Voo = Vo+ - Vo- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kQ and less than 100 kn for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 1.001 Vrms).
Voo=AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

EARA

...

3=
->w
w

R1
Digital mW Sequence

lAW CCITT G.712

----.- DIN

EARGS

.....
...

Vo
<

EARS

3 ..

a:
a..

--..

....
o

Vo-

::)

c
a:

NOTE A: Terminal numbers shown are for the DW and N packages.

a..

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK' to the frame sync frequency, fFSR/fFSX. This ratio for the VSAP is 1.152 MHz/8 kHz, or 144
master clocks per frame sync. For example, to operate the VSAP at a sampling rate of fFSR and fFSX equal to
16 kHz, fCLK must be 144 times 16 kHz, or 2.304 MHz. If the VBAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-101

6-102

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

•
e

Single 3-V Operation
Low Power Consumption:
Operating Mode . .. 20 mW Typ
- Standby Mode. .. 5 mW Typ
- Power-Down Mode . .. 2 mW Typ

•

Selectable Between 8-Bit Companded and
13-Bit (Dynamic Range) Linear Conversion:
- TLV320AC56 . .. /l-Law and Linear Modes
- TLV320AC57 ... A-Law and Linear
Modes

•

Combined AID, DIA, and Filters

•

Extended Variable-Frequency Operation
- Sample Rates up to 16 kHz
- Pass-Band up to 7.2 kHz

Programmable Volume Control in Linear
Mode

•

300 Hz - 3.6 kHz Passband with Specified
Master Clock

•

o Designed for Standard 2.048-MHz Master

Electret Microphone Bias Reference
Voltngc Avnilnblc

•

Drive a Piezo Speaker Directly

•

Compatible With All Digital Signal
Processors (DSPs)

Clock for U.S. Analog, U.S. Digital, and
CT2, DECT, GSM, and PCS Standards for
Hand-Held Battery-Powered Telephones

ow OR N PACKAGE

PT PACKAGE
(TOP VIEW)

(TOP VIEW)

Cf)

~Cf)

Cf)

PDN
EARA
EARS
EARGS
Vee
MICMUTE
DClKR
DIN
FSR
EARMUTE

MICSIAS
MICGS
MICIN
VMID
GND
LlNSEl
TSXlDClKX
DOUT
FSX
ClK

~ (2I Z III (!J
a: ««oQQ

(!J

«
UJ

UJUJa..:2::2:

s:w

000
~ ZZZ

VMID
NC
AGND
NC
NC
NC
NC
NC
NC
DGND
LlNSEl
NC

NC
NC
NC
AVec
NC
NC
NC
NC
DVee
NC
MICMUTE
NC
0

a: za:

O~X

I-X 0 0

I- Z...JCJ) ::J~ ZZ
~
Z ...J
o~ ::J
OLL O...J

0
0

Ne - No internal connection

...
~

:2:

«
UJ

0 0
0

VBAP is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without nolice.

•
TEXAS
INSTRUMENTS
POST OFFiCE BOX 655303 • DALLAS, TEXAS 75265

6-103

:>
w
a:
c.

I-

::l

a:
c.

TLV320AC56,TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

description
The TLV320AC56 and TLV320AC57 voice-band audio processor (VBAP) integrated circuits are designed to
perform the transmit encoding (AID conversion) and receive decoding (D/A conversion) together with transmit
and receive filtering for voice-band communications systems. Cellular telephone systems are targeted in
particular; however, these integrated circuits can function in other systems including digital audio,
telecommunications, and data acquisition.
These devices are pin-selectable for either of two modes, companded and linear, providing data in two formats.
In the companded mode, data is transmitted and received in 8-bit words. In the linear mode, 13 bits of data and
either three bits of gain-setting control data, or three zero bits of padding to create a16-bit word, are sent and
received.
The transmit section is designed to interface directly with an electret microphone element. The microphone input
signal (MICIN) is buffered and amplified with provision for setting the amplifier gain to accommodate a range
of signal input levels. The amplified signal is passed through antialiasing and band-pass filters. The filtered
signal is then applied to the input of a compressing analog-to-digital converter (COADC) when companded
mode is selected. Otherwise, the analog-to-digital converter performs a linear conversion. The resulting data
is then clocked out of DOUT as a serial data stream.
The receive section takes a frame of serial data on DIN and converts it to analog through an expanding
digital-to-analog converter (EXDAC) when the companded mode is selected; otherwise, a linear conversion is
performed. The analog signal then passes through switched capacitor filters, which provide out-of-band
rejection, (sin x)/x correction functions, and smoothing. The filtered signal is sent to the earphone amplifier. The
earphone amplifier has a differential output with adjustable gain and is designed to minimize static power
dissipation.

'"'C

o
C

A single on-chip high-precision band-gap circuit generates all voltage references, eliminating the need for
external reference voltages. An internal reference voltage equal to Vcc/2, VMID, is used to develop the midlevel
virtual ground for all the amplifier circuits and the microphone bias circuit. Another reference voltage, MICBIAS,
can supply bias current for the microphone.

-I
'"'C

The TLV320AC5xC devices are characterized for operation from O°C to 70°C. The TLV320AC5xl devices are
characterized for operation from -40°C to 85°C.

S
m

•
TEXAS
INSTRUMENTS
6-104

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC56,TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

functional block diagram

Transmit
Third-Order
Antialias

MICMUTE
MICIN

Transmit
Sixth-Order
Low Pass

Transmit
First-Order
High Pass

256 kHz

8 kHz

DOUT

FSX

MICGS ---=.;19=--.....-+-_ _---1

VMID
VMID
MICBIAS

Band-Gap
Voltage
Reference
AID
Converter
Voltage
Reference

17
20

256 kHz

D/A
Converter
Voltage
Reference

8 kHz

~
W

9
2
3
4
EARGS
10
EARMUTE
EARA
EARB

Earphone
Amplifier

/5
VCC

/16
GND

FSR

DIN

5>
W
a:
C.

::l
C

PDN

a:::

NOTE A: Terminal numbers shown are for the DW and N packages.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-105

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

Terminal Functions
TERMINAL
NAME

ClK

DClKR

DGND

o
c
c
(')
-I
"'tJ

Ground return for all internal analog circuits

3-V supply voltage for all internal analog circuits

Ground return for all internal digital circuits

Receive data input. Input data is clocked in on consecutive negative transitions of the receive data
clock, which is ClK for a fixed data rate and DClKR for a variable data rate (digital).

DOUT

Transmit data output. Transmit data is clocked out on consecutive positive transitions of the transmit
data clock, which is ClK for a fixed data rate and DClKX for a variable data rate (digital).

DVCC

DIN

3-V supply voltage for all internal digital circuits

EARA

EARB

Earphone output. EARB forms a differential drive when used with the EARA signal (analog).

EARGS

Earphone output mute control signal. When EARMUTE is low, the output amplifier is disabled and no
audio is sent to the earphone (digital).

FSR

Frame-synchronization ciock input for the receive channel. In the variable-data-rate mode, this signal
must remain high for the duration of the time slot. The receive channel enters the standby condition
when FSR is TTL-low for five frames or longer. The device enters a production test-mode condition
when either FSR or FSX is held high for five frames or longer (digital).

FSX

Frame synchronization ciock input for the transmit channel. FSX operates independently of FSR, but
also in an analogous manner to FSR. The transmit channel enters the standby condition when FSX
is low for five frames or longer. The device enters a production test-mode condition when either FSX
or FSR is held high for five frames or longer (digital).

Linear selection input. When low, LlNSEl selects linear coding/decoding. When high, LlNSEl selects
companded coding/decoding. Companding code on the 'AC56 is Il-Iaw, and companding code on the
'AC57 is A-law (digital).

EARMUTE

m
<

DESCRIPTION

AVCC

AGND

"'tJ

110

NO.
DW,N

GND

LlNSEl

Earphone output. EARA forms a differential drive when used with the EARB signal (analog).

Ground return for all internal circuits

MICBIAS

Microphone bias. MICBIAS voltage for the electret microphone is equal to VMID.

MICGS

MICIN

Microphone input. Electret microphone input to the internal microphone amplifier (analog)

MICMUTE

Microphone input mute control signal. When MICMUTE is active (low), zero code is transmitted (dig.).

PDN

Power-down input. When PDN is low, the device powers down to reduce power consumption (digital).

I/O

Transmit time slot strobe (active-low output) or data clock (input) for the transmit channel. In the
fixed-data-rate mode, TSXlDClKX is an open-drain output that pulls to ground and is used as an
enable signal for a 3-state buffer. In the variable-data-rate mode, DClKX becomes the transmit data
ciock input (digital).

TSXlDClKX

VCC

VMID

3-V supply voltage for all internal circuits

VCC/2 bias voltage reference. A pair of external, low-leakage, high-frequency capacitors
(1 IlF and 470 pF) should be connected between VMID and ground for filtering.

~TEXAS

INSTRUMENTS
6--106

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

iLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vee (see Note 1) ............................................. -0.3 V to 5.5 V
Output voltage range at DOUT, Va .................................................. -0.3 V to 5.5 V
Input voltage range at DIN, VI ...................................................... -0.3 V to 5.5 V
Continuous total power dissipation ..................................... See Dissipation Rating Table
Operating free-air temperature range: C suffix ......................................... O°C to 70°C
I suffix ........................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C

TA ~25°C
POWER RATING

DERATING FACTOR
ABOVE TA 25°C

1025 mW

1150mW

1075 mW

TA 70°C
POWER RATING

TA 85°C
POWER RATING

8.2 mW/oC

656mW

533mW

9.2 mW/oC

736mW

598mW

7.1 mW;oC

756mW

649mW

s:w

recommended operating conditions (see Note 2)
MIN

MAX

Supply voltage, VCC (see Note 3)

2.7

3.3

High-level input voltage, VIH

2.2

Low-level input voltage, VIL

Operating free-air temperature, TA
NOTES:

ITLV320AC56C, TLV320AC57C

1TLV320AC561, TLV320AC571

600

Load capacitance between EARA and EARS, CL (see Note 4)

V
V

0.8

Load resistance between EARA and EARS, RL (see Note 4)

UNIT

-40

nF
°c

2. To avoid possible damage to these CMOS devices and resulting reliability problems, the power-up sequence detailed in the system
reliability features paragraph should be followed.
3. Voltages at analog inputs, outputs, and VCC are with respect to GNO.
4. RL and CL should not be applied simultaneously.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-107

5>
w
a:
a.

I-

o
c

::>

a:
a.

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

electrical characteristics over recommended ranges of supply voltage and free-air temperature
(unless otherwise noted)
supply current, fOCLKR or fOCLKX

=2.048 MHz, outputs not loaded, VCC =3 V, TA =25°C

PARAMETER

TEST CONDITIONS

ICC

Supply current from VCC

MIN

PDN is high with ClK signal present

Operating

MAX

UNIT

7.5

Power down

PDN is low for 500 Ils

Standby - both

PDN is high with FSX and FSR held low

Standby - one

PDN is high with either FSX or FSR pulsing with the
other held low

0.75
2

4.5

digital interface
PARAMETER

"tJ

:c
o
c
c

High-level output voltage

VOL

low-level output voltage

TEST CONDITIONS
!DOUT

IOH = -3.2 mA,

VCC = 3V

IOl= 3.2 mA,

Vee= 3V

MIN

TYPt

2.4

2.8
0.2

MAX

UNIT
V

0.4

IIH

High-level input current, any digital input

VI = 2.2 V to VCC

IlA

III

low-level input current, any digital input

VI = 0 to 0.8 V

Il A

Input capacitance

Output capacitance

t All typical values are at VCC = 3 V, TA = 25°C.
microphone interface
PARAMETER

-I

"tJ

:c
m
<
-

VOH

TEST CONDITIONS

VIO

Input offset voltage at MICIN

liB

Input bias current at MICIN

Unity-gain bandwidth, open loop at MICIN+

MIN

TYPt

VI =Oto 3 V

MAX
±5
±200

1.5

Input capacitance at MICIN

large-signal voltage amplification at MICGS

lomax

Maximum output current

IVMID

MICSIAS
(source only)

UNIT
mV
nA
MHz

10000

V/V

IlA

t All typical values are at VCC = 3 V, TA = 25°C.
+The frequency of the first pole is 100 Hz.
speaker interface
PARAMETER

TEST CONDITIONS

VO(PP)

AC output voltage

VOO

Output offset voltage at EARA, EARS (single-ended)

Relative to GND

11(lkq)

Input leakage current at EARGS

VI = 0.5 V to (VCC - 0.5) V

lOmax

Maximum output current

Rl= 600

TYPt

Output resistance at EARA, EARS
Gain change

1
EARMUTE low, max level when muted

All typical values are at VCC = 3 V, TA = 25°C.
§ 2.5 Vpp when VCC is 2.7 V.

~TEXAS

INSTRUMENTS
6-108

MIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-60

MAX

UNIT

3§

Vpp

mVpk

±200

±2.5

n
dB

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

transmit gain and dynamic range, companded mode (/-l-Iaw or A-law) or linear mode selected, Vee
TA = 25°C (unless otherwise noted) (see Notes 5 and 6)
PARAMETER

TEST CONDITIONS

Transmit reference-signal level (0 dB) (see Note 7)

Overload-signal level (MICIN at unity gain)

Absolute gain error

Gain variation

MAX
0.614

Companded mode selected, A-law CAC57)

0.616

Linear mode selected CAC56 and 'AC57)

0.626

Companded mode selected, Il-Iaw CAC56)

2.5

Companded mode selected, A-law CAC57)

2.5

Linear mode selected CAC56 and 'AC57)

2.5

O-dB input signal

Gain error with input level relative to gain at -10 dBmO

NOTES:

MIN

Companded mode selected, Il-Iaw CAC56)

=3 V,
UNIT

Vrms

Vpp

±1

MICIN to DOUT <:It 3 dBmO to -40 dBmO

±0.5

MICIN to DOUT at -41 dBmO to -50 dBmO

±1.5

MICIN to DOUT at -51 dBmO to -55 dBmO

±2

±0.5

VCC ±10%,

=O°C to 70°C

transmit filter transfer, companded mode (/-l-Iaw or A-law) or linear mode selected, over recommended
ranges of supply voltage and free-air temperature, ClK = 2.048 MHz, FSX = 8 kHz (see Note 6)
PARAMETER

Gain relative to input signal gain at
1.02 kHz

TEST CONDITIONS

Input amplifier set for unity gain,
noninverting maximum gain output signal
at MICIN is 0 dB

MIN

MAX

fMICIN = 50 Hz

-10

fMICIN = 200 Hz

-2.8

0
±0.25

fMICIN = 300 Hz to 3 kHz
fMICIN = 3.3 kHz

-0.55

0.2

fMICIN = 3.4 kHz

-1

-0.1

fMICIN

UNIT

= 4 kHz

::l
C

-14
-32

fMICIN ;::4.6 kHz
NOTE 6. The input amplifier is set for inverting unity gain.

transmit idle channel noise and distortion, companded mode with /-l-Iaw or A-law selected, over
recommended ranges of supply voltage and operating free-air temperature (see Note 8)
PARAMETER

TEST CONDITIONS

MIN

MAX

Transmit noise, psophometrically weighted

MICIN connected to MICGS through a 10-kil resistor

-72

Transmit noise, C-message weighted

MICIN connected to MICGS through a 10-kil resistor

MICIN to DOUT at 0 dBmO to -24 dBmO

Transmit signal-to-distortion ratio with sine-wave input

Intermodulation distortion, 2-tone CCID method,
composite power level -13 dBmO

UNIT
dBOp
dBrnCO

MICIN to DOUT at -25 dBmO to -30 dBmO

MICIN to DOUT at -31 dBmO to -38 dBmO

MICIN to DOUT at -39 dBmO to -40 dBmO

MICIN to DOUT at -41 dBmO to -45 dBmO

CCIDG.712 (7.1), R2

CCID G.712 (7.2), R3

NOTE 8: Transmit nOise, linear mode: 200 IlVrms is eqUivalent to -74 dB (referenced to device O-dB level).

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

3f:
w
:>
w
a:
a.
Io

6-109

o
a:
a.

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

transmit idle channel noise and distortion, linear mode selected, over recommended ranges of supply
voltage and operating free-air temperature (see Notes 6 and 8)
TEST CONDITIONS

PARAMETER

MICIN to OOUT at 0 dBmO to -10 dBmO

Transmit signal-to-distortion ratio with sine-wave input

NOTES:

MIN

MICIN connected to MICGS through a 10-kil resistor

Transmit noise

MAX

UNIT

200

INrms

MICIN to OOUT at -11 dBmO to -12 dBmO

MICIN to OOUT at -13 dBmO to -18 dBmO

MICIN to OOUT at -19 dBmO to -24 dBmO

MICIN to OOUT at -25 dBmO to -40 dBmO

MICIN to OOUT at -41 dBmO to -45 dBmO

6. The input amplifier is set for inverting unity gain.
8. Transmit noise, linear mode: 200 I.Nrms is equivalent to -74 dB (referenced to device O-dB level).

receive gain and dynamic range, companded mode (Il-Iaw or A-law) or linear mode selected, Vee
TA 25°C (unless otherwise noted) (see Notes 9 and 10)

TEST CONDITIONS

PARAMETER
Receive reference-signal level (0 dB) (see Note 11)

""tJ

o
C

c:
o

-I

""tJ

Absolute gain error

Gain variation
NOTES:

m
~

Companded mode selected, A-law (' AC57)

0.739

Linear mode selected (,AC56 and 'AC57)

0.751

~-Iaw

('AC56)

Companded mode selected, A-law (,AC57)

Linear mode selected ('AC56 and 'AC57)

O-dB input signal

Gain error with output level relative to gain at -10 dBmO

MAX
0.736

Companded mode selected,
Overload-signal level

MIN

Companded mode selected, ~-Iaw ('AC56)

±1

OIN to EARA and EARB at 3 dBmO to -38 dBmO

±0.5

OIN to EARA and EARB at -39 dBmO to -50 dBmO

±1.5

OIN to EARA and EARB at -51 dBmO to -55 dBmO

±2
±0.5

TA = O°C to 70°C

VCC ±10%,

=3 V,
UNIT
Vrms

Vpp
dB
dB
dB

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
10. Unless otherwise noted, the digital input is a word stream generated by passing a O-dB sine wave at 1020 Hz through an ideal
encoder, where 0 dB is defined as the zero reference.
11. This reference-signal level is measured at the speaker output of the receive channel with the. gain of the output speaker amplifier
set to unity.

receive filter transfer, companded mode (Il-Iaw or A-law) or linear mode selected, over recommended ranges
of supply voltage and operating free-air temperature, FSR 8 kHz (see Note 9)

PARAMETER

TEST CONDITIONS

=< 200 Hz
fOIN =200 Hz
fOIN =300 Hz to 3 kHz
fOIN =3.3 kHz

MIN

Gain relative to gain at 1.02 kHz

OIN

=0 dBmO

fOIN = 3.4 kHz
fOIN
fOIN

=4 kHz
= 4.6 kHz
;>

MAX

UNIT

0.25

fOIN

-0.5

0.25
±0.25

-0.55

0.2

-1

-0.1

-14
-30

~TEXAS

INSTRUMENTS
6-110

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC56,TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

receive idle channel noise and distortion, companded mode with Il-Iaw or A-law selected, over recommended
ranges of supply voltage and operating free-air temperature (see Note 9)
PARAMETER

TEST CONDITIONS

MIN

=11010101 (A-law)
DIN =11111111 (II-law)

Receive noise, psophometrically weighted

DIN

Receive noise, C-message weighted

Receive signal-to-distortion ratio with sine-wave input

MAX

UNIT

-72

dBOp

DIN to EARA and EARB at 0 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to -24 dBmO

DIN to EARA and EARB at -25 dBmO to -30 dBmO

DIN to EARA and EARB at -31 dBmO to -38 dBmO

DIN to EARA and EARB at -39 dBmO to -45 dBmO

dBrncO

NOTE 9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS b
connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.

receive idle channel noise and distortion, linear mode selected, over recommended ranges of supply voltage
and operating free-air temperature (see Notes 9 and 12)
PARAMETER

TEST CONDITIONS

Receive noise

DIN

Receive signal-to-distortion ratio with sine-wave input

Intermodulation, 2-tone CCID distortion method,
composite power level -13 dBmO
NOTES:

MIN

=00000000

DIN to EAR A and EARB at 0 dBmO to -12 dBmO

DIN to EARA and EARB at -13 dBmO to -18 dBmO

DIN to EARA and EARB at -19 dBmO to - 24 dBmO

DIN to EARA and EARB at -25 dBmO to -40 dBmO

DIN to EARA and EARB at -41 dBmO to -45 dBmO

CCIDG.712 (7.1), R2

CCID G.712 (7.2), R3

MAX

UNIT

200

IlVrms

9. Receive output is measured differentially in the maximum gain configuration. To set the output amplifier for maximum gain, EARGS
is connected to EARB and the output is taken between EARA and EARB. All output levels are (sin x)/x corrected.
12. Receive noise, linear mode: 200 IlVrms is equivalent to -71 dB (referenced to device O-dB level).

power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

Supply voltage rejection, transmit channel

Idle channel, supply signal = 100 mVrms,
f = 0 to 30 kHz (measured at DOUT)

-30

Supply voltage rejection, receive channel

Idle channel, supply signal = 100 mVrms,
EARGS connected to EARB,
f = 0 to 30 kHz (measured differentially between EARA
and EARB)

-30

Crosstalk attenuation, transmit-to-receive
(differential)

MICIN = 0 dB, f = 1.02 kHz, unity transmit gain,
EARGS connected to EARB,
measured differentially between EARA and EARB

Crosstalk attenuation, receive-to-transmit

DIN = 0 dBmO, f = 1.02 kHz, unity transmit
gain, measured at DOUT

t All typical values are at VCC

5=
w
a:
c.

I-

:J
C

oa:

=3 V, TA =25°C.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3:
w

6-111

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1 through Figure 4)
MIN
tt

NOMt

MAX
10

Transition time, ClK and DClKX/DClKR
Duty cycle, ClK

45%

50%

55%

Duty cycle, DClKX/DClKR

45%

50%

55%

UNIT
ns

t All typical values are at VCC = 3 V, TA = 25°C.

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 2)
MIN

MAX

UNIT

tsu{FSX~

Setup time, FSX high before ClKJ.

468

th(FSX)

Hold time, FSX high after ClKJ.

468

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 1)

"'C

::D

o
C

Co
-f
"'C

::D

m
<
ffi

MIN

MAX

tsu{FSR)

Setup time, FSR high before ClKJ.

468

th(FSR)

Hold time, FSR high after ClKJ.

468

tsu(DIN)

Setup time, DIN high or low before ClKJ.

th(DIN)

Hold time, DIN high or low after ClKJ.

UNIT

transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 4)
MAX

UNIT

tsu(FSX)

Setup time, FSX high before DClKXJ.

t~lDClKX}-40

th(FSX)

Hold time, FSX high after DClKXJ.

tc (DClKX)-35

MIN

receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 3)
MIN

MAX'

UNIT

tsu(FSR)

Setup time, FSR high before DClKRJ.

th(FSR)

Hold time, FSR high after DClKRJ.

tsuJDIN)

Setup time, DIN high or low before DClKRJ.

th(DIN)

Hold time, DIN high or low after DClKRJ.

tc(DClKR)-35

switching characteristics
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode,
CL = 0 to 10 pF (see Figure 2)
TEST CONDITIONS

PARAMETER

MIN

MAX

UNIT

tpd1

From ClK bit 1 high to DOUT bit 1 valid

tpd2

From ClK high to DOUT valid, bits 2 to n

tp_d3

From ClK bit n low to DOUT bit n Hi-Z

tpd4

From ClK bit 1 high to TSX active (low)

Rpull up = 1.24 kn

t~d5

From ClK bit n low to TSX inactive (high)

Rpull up = 1.24 kn

~TEXAS

INSTRUMENTS
6-112

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

40
30

ns
ns

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

propagation delay times over recommended ranges of operating conditions, variable-data-rate mode (see
Figure 4)
TEST CONDITIONS

PARAMETER

MIN

MAX

UNIT

tpd6

FSX high to DOUT bit 1 valid

Cl = 0 to 10 pF

tpd7

DClKX high to DOUT valid, bits 2 to n

Cl = 0 to 10 pF

tpd8

FSX low to DOUT bit n Hi-Z

I
I

Receive Time Slot - - - - - - - - - - .

N-2

N-1

ClK

->w
a:

tsu(DIN)

a.
Io

Figure 1. Fixed-Data Rate Mode, Receive Side Timing Diagram

DIN
See Note C
NOTES: A. This window is allowed for FSR high.
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

:J
C

1<11'l1li1----------- Transmit Time Slot - - - - - - - - -...

o
ClK

N-l

N+l

20%

~ i
I I..
~I
th(FSX)
4f\w:9\ \\d",\\\
,_, ~ 1 ~1\1..:l_~'-\"'\"'\""\..l......_ _~_ _ _ _ _ _-'l(""(_ _ _ _ _ _ _ _ _-+____

tsu(FSX)
FSX

I..

1 1~1III---;1-------f----~I See Note A

Se~JNote B - - - - - - - - - ' - - - - - -....
~
~

DOUT------------~I~

See Note C

tpd1 ~

tpd5 ~

1~8~OOIc-:-o-

: \

20%

((

tpd4

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low (th(FSX) max determined by data collision considerations).
C. Transitions are measured at 50%.

Figure 2. Fixed-Data Rate Mode, Transmit Side Timing Diagram

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-113

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

PARAMETER MEASUREMENT INFORMATION

DCLKR

FSR

DIN
See Note C
NOTES: A. This window is allowed for FSR high (tsu(FSR) max determined by data collision considerations).
B. This window is allowed for FSR low.
C. Transitions are measured at 50%.

Figure 3. Variable-Data Rate Mode, Receive Side Timing Diagram

'tJ
:D

14
41---------- Transmit Time Slot -----------'~I

c:
FSX

-a

N-2

N-1

6rn~i

tpd6
DOUT
See Note C

ffi{~

~~~~-""'''.lop.~---

--'1 I+- tpd7
1

See Note B

NOTES: A. This window is allowed for FSX high.
B. This window is allowed for FSX low without data repetition.
C. Transitions are measured at 50%.

Figure 4. Variable-Data Rate Mode, Transmit Side Timing Diagram

~TEXAS

INSTRUMENTS
6-114

N+1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-+l 14-

\\\\~~

((

14 I ~I 1
--+I 1+-1

20%
th(FSX)

1
1

---~~~~II
See Note A

:xJ

3
1

-I

~ tsu(FSX)

m
<
-

DCLKX

tpd8

-+11.-

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

PRINCIPLES OF OPERATION
general
system reliability features
The device should be powered up and initialized as follows:
1.

Apply GNO.

Apply Vee.

Connect all clocks.

Apply TTL high to PON.

Apply synchronizing pulses to FSX and/or FSR.

Even though the VBAP is heavily protected against latch-up, it is still possible to cause it to latch up under certain
improper power conditions. To help ensure that latch-up does not occur, a reverse-biased Schottky diode (with
a forward voltage drop of less than or equal to 0.4 V - 1N5711 or equivalent) should be connected between
Vee (power supply) and GNO.
On the transmit channel, digital outputs OOUT and TSX are held in the high-impedance state for approximately
four frames (500 llS) after power up or application of Vee. After this delay, OOUT, TSX, and signaling are
functional and occur in the correct time slot. The analog circuits on the transmit side require approximately
60 ms to reach their equilibrium value due to the autozero circuit settling time. To further enhance system
integrity, OOUT and TSX are placed in the high-impedance state after an interruption of ClK.

->w
W

a::

power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.

For power down, an external low signal is applied to PON. In the absence of a signal, PON is internally pulled
up to a high logic level and the device remains active. In the power-down mode, the average power consumption
is reduced to 2 mW.

Three standby modes give the user the option of placing the entire device on standby, placing only the transmit
channel on standby, or placing only the receive channel on standby. To place the entire device on standby, both
FSX and FSR are held low. For transmit-only operation (receive channel on standby), FSX is pulsing and FSR
is held low. For receive-only operation (transmit section on standby), FSR is pulsing and FSX is held low. When
the entire device is in standby mode, power consumption is reduced to 5 mW. See Table 1 for power-down and
standby procedures.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-115

::l
C

o
a::

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

PRINCIPLES OF OPERATION
Table 1. Power-Down and Standby Procedures
DEVICE STATUS

:a
o
c
c

TYPICAL POWER
CONSUMPTION

DIGITAL OUTPUT STATUS

Power on

PDN =high,
FSX =pulses,
FSR =pulses

Power down

PDN = low,
FSX, FSR = xt

2mW

TSX and DOUT in the high-impedance state

Entire device on standby
mode

FSX = low,
FSR = low,
PDN = high

5mW

TSX and DOUT in the high-impedance state

Only transmit channel in
standby mode

FSX = low,
FSR = pulses,
PDN = high

10mW

TSX and DOUT in the high-impedance state within five
frames

Only receive channel in
standby mode

FSR = low,
FSX = pulses,
PDN = high

10mW

Digital outputs active but not loaded

20mW

Digital outputs active but not loaded

=don't care

-f
"'tJ

:a
m

PROCEDURE

m
===

While the FSX input is high, data is transmitted from DOUT on consecutive positive transitions of DClKX.
Similarly, while the FSR input is high, the data word is received at DIN on consecutive negative transitions of
DClKR. The transmitted data word at DOUT is repeated in all remaining time slots in the frame as long as
DClKX is pulsed and FSX is held high. This feature, which allows the data word to be. transmitted more than
once per frame, is available only with variable-data-rate timing.
asynchronous operations
To avoid crosstalk problems associated with special interrupt circuits, the design includes separate converters,
filters, and voltage references on the transmit and receive sides to allow completely independent operation of
the two channels. In either timing mode, the master clock, data clock, and time-slot strobe must be synchronized
at the beginning of each frame.
precision voltage references
A precision band-gap reference voltage is generated internally and is used to supply all the references required
for operation of both the transmit and receive channels. The gain in each channel is trimmed during the
manufacturing process. This ensures very accurate, stable gain performance over variations in supply voltage
and device temperature.

•
TEXAS
INSTRUMENTS
6-116

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

PRINCIPLES OF OPERATION
conversion laws
The TLV320AC56 provides Jl-Iaw companding operation that approximates the CCITT G. 711 recommendation.
The TLV320AC57 provides A-law companding operation that approximates the CCITT G. 711 recommendation.
The linear mode of operation uses a 13-bit two's-complement format and is the same for both the TLV320AC56
and the TLV320AC57.

I--------------------~
.--_ _...._ _ _ _ _ _V_M;...I_D+-_ _ _ _ _ _ _..._ VMID Reference
171
For Amplifiers
1

3:
w

VDD

->w

VMID

1
1

a:
a.

MICBIASI
201
1

I-

2kn
3.3~F

+
10 kn
Electret
Microphone

10 kn

MICGSI
19
MICIN

c
o
a:
a.

18 1

To Transmit Filters

MICMUTE 1
1

TLV320AC56/57 VBAP

--------------------~

NOTE A: Terminal numbers shown are for the OW and N packages.

Figure 5. Typical Microphone Interface
microphone mute function
The MICMUTE input causes the digital circuitry to transmit all zero code on DOUT.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-117

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

."
:0

-I
."

m
S
m

receive buffer
The receive buffer contains the volume control.
earphone amplifier
The earphone aUdio-output amplifier has a balanced output, as shown in Figure 6, to allow maximum flexibility
in output configuration. The output amplifier is designed to directly drive a piezo earphone in the differential
configuration without any additional external components. The output can also be used to drive a single-ended
load with the output signal voltage centered around VCC/2.
The receive-channel output level can be adjusted between specified limits by connecting an external resistor
network to EARGS.

~TEXAS

INSTRUMENTS
6-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TLV320AC56,TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044 - JUNE 1996

PRINCIPLES OF OPERATION

r--------------------j
1

EARGS

EARA
1
1
1

1
1
1

>-~~--------+_-

VMID

EARS

w
:>
w

r--------------------~
NOTE A: Terminal numbers shown are for the DW and N packages.

Figure 6. Earphone Audio-Output Amplifier Configuration and Internal Gain-Setting Network

c..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

6-119

::l
C

oa:

c..

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Receive-Data Bit Definitions
BIT NO.

COMPANDED MODE

LINEAR MODE

CO?

L012

C06

L011

C05

L010
L09

C04

C03

LOB

CO2

LO?

C01

L06

COO

L05

L04

L03

A
B

C
0

"tJ
::D

E
F

L02
L01
LOO
V2
V1
VO

Volume control and other control bits always follow the PCM data in time:

c:
o

Companded Mode:

MSB
(sign bit)

LSB
,CD7 COG COS CD4 CD3 C02 CD1 COOl
V
Companded Data

-I

"tJ
::D

Linear Mode:

MSB
(sign bit)

LSB
LD12 LD11 LD10 LD9 LOS LD7 LOG LOS LD4 LD3 LD2 LD1 LDO

~------------------~V

Linear Data
Time---+

where:
CD? -COO = Data word when in companded mode
LD12-LDO= Data word when in linear mode
V2, V1,
= Volume (attenuation control) 000 = maximum volume, 3 dBmO
111 = minimum volume, -18 dBmO

~TEXAS

INSTRUMENTS
6-120

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I~
Volume Control

TLV320AC56, TLV320AC57
3-V VOICE-BAND AUDIO PROCESSORS (VBAPTM)
SLWS044-JUNE 1996

APPLICATION INFORMATION

output gain set design considerations (see Figure 7)
EARA and EARB are low-impedance complementary outputs. The voltages at the nodes are:
VO+ at EARA
VO- at EARB
VOD = VO+ - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to EARGS.
A value greater than 10 kQ and less than 100 kQ for R1 + R2 is recommended because of the following:
The parallel combination R1 + R2 and RL sets the total loading. The total capacitance at EARGS and the
parallel combination of R1 and R2 define a time constant that has to be minimized to avoid inaccuracies.
VA represents the maximum available digital mW output response (VA = 1.001 Vrms).
VOD =AxVA
1 + (R1/R2)
where A = 4 + (R1/R2)

3:
w
:>
w
Digital mW Sequence
lAW CCITT G.712

DIN

EARGS

1 - - - 4 - -__

c..

I-

EARB 1-3-1~~J--__________""" Va-

::J
C

NOTE A: Terminal numbers shown are for the OW and N packages.

c..

Figure 7. Gain-Setting Configuration

higher clock frequencies and sample rates
The VBAP is designed to work with sample rates up to 16 kHz where the frequency of the frame sync determines
the sampling frequency. However, there is a fundamental requirement to maintain the ratio of the master clock
frequency, fCLK' to the frame sync frequency, fFSR/fFSX. This ratio for the VBAP is 2.048 MHz/8 kHz, or 256
master clocks per frame sync. For example, to operate the VBAP at a sampling rate of fFSR and fFSX equal to
16 kHz, fCLK must be 256 times 16 kHz, or 4.096 MHz. If the VBAP is operated above an 8-kHz sample rate,
however, it is expected that the performance becomes somewhat degraded. Exact parametric specifications
for rates up to 16-kHz sample rate are not specified at this time.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

6-121

6-122

~G_e_n_e_r_a_ll_n_fo_r_m__
at_io
__
n ______________~1IDI
Telecommunications Circuits

Central Office Codecs

•

Transient Voltage Suppressors

•

RF for Telemetry and RKE

•

Wireless Communications Circuits

Processors for Analog Cellular
Voice-Band Audio Processors

II
III

RF for Personal Communications

1II

L--B_a_s_e_b_a_"_d_I"_t_e_rf_8_c_e_C_i_rc_u_i_ts______

1II

L--D_i~g_it_81_S_i_g_"_a_l_p_ro_c_e_s_s_o_r_s___________
Mechanical Data

7-1

•

II
~

0
....,

-a
....,
en

(1)

0
::J
Q)

0
0

3
3

_.
Q)
.....
_.

::J
0

0
::J

7-2

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021-JUNE 1996

DB PACKAGE
(TOP VIEW)

•

Low-Noise Amplifier (LNA), Radio
Frequency (RF) Mixer, and
Voltage-Controlled Oscillator (VCO)

•
•
o

High 1-d8 Compression Mode
High Linearity Mode
Conversion From RF to Intermediate
Frequency (IF) on a Single Chip
Suitable for Portable gOO-MHz Cellular and
Cordless Telephones
Low Current Consumption

•
o
•
•

Operates From 3.5 V to 5.5 V
20-Pin Plastic Shrink Small Outline (SSOP)
Package

•

Application Selectable On-board or
External Oscillator

PD1
PD2
AUX LOAUX::::LO+
OSC2
VCO_GND
OSC1
VCO_VCC
VCO_BYP
LNA_GND

10
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

MIX_OUTMIX_OUT+
MIX_IN
MIX_GND
LNA_GND
LNA_IN
LNA_VCC
LNA_OUT
LNA_GND
LNA_GND

description
Texas Instruments (TITM) TRF1015 is a single-chip RF down-converter suitable for gOO-MHz receiver
applications. It combines a low-noise amplifier (LNA), a buffered VOltage-controlled oscillator (VeO), and an RF
mixer, into a 20-pin SSOP package with very few extern&1 components required.

;=:
W
:;

Three independently selectable modes of operation are provided for both the LNA and the mixer: low-current
mode, low-noise mode, and high 1-dB compression mode with low-noise and moderate current consumption.
The high compression mode is suitable for applications requiring full duplex capability. It is suitable for
maintaining receiver sensitivity in the presence of large interfering signals and also has a high bit error rate
(BER) mode for digital modulation.

c..

The LNA has a gain of 14 dB and noise figure of 2 dB. Input and output characteristic impedances of the LNA
are 50-.0. The single balanced RF mixer has a gain of 11 dB with single-sideband (SSB) noise figure of 10 dB.
The veo has a operational range from 650 MHz to 1150 MHz and a minimum tuning range of 25 MHz using
an external varactor. The veo gain and tuning range can be adjusted to meet the phase-locked loop (PLL)
design requirement with an external shunt and feedback capacitors in series with the resonator. A buffered
output of the veo signal is provided for phase locking capability and can be configured for single-ended or
differential operation. The veo with the RF mixer can convert an RF signal in the range of 800 MHz to 1000 MHz
to a first IF of 30 MHz to 100 MHz.
Power consumption is kept to a minimum and can be further reduced by placing only the required modules in
operate mode and the remaining modules in standby mode.
Typical Power Consumption at VCC
MODULE

=3.75 V

STANDBY

LNA(1,O)
RF mixer (1, 0)(0,1)

veo and buffer amplifiers
All modules

OPERATE

100llW

26mW

30mW

45mW

100llW

101 mW

The TRF1015 is offered in the 20-pin DB package and is characterized for operation from -40 o e
to 85°e free-air temperature.

TI is a trademark of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-3

w
a:

I-

::l
C

c..

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021 - JUNE 1996

functional block diagram

PD1

PD2

AUX_LO-

Power-Down
Logic

<:'

AUX_LO+

OSC2

VCO_GND

OSC1

.~
?

"tJ

vco_VCC

VCO_BYP

LNA_GND

r--....

::::;:::

~
I

0
-I
"tJ

::::
m

•
TEXAS
INSTRUMENTS
7-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

AUX_LO-

AUX_LO+

LNA_GND

LNA_IN

LNA_OUT

LNA_Vee

DESCRIPTION
PLL auxiliary local oscillator (LO) output (inverting)
PLL auxiliary LO output (non-inverting)
LNA ground
LNA ground
LNA RF input
LNA RF output
LNA voltage supply

LNA_GND

LNA ground

LNA_GND

LNA ground

MIX_GND

MIX_IN

Mixer RF input

MIX_OUT-

Mixer IF output (inverting)

MIX_OUT+

OSe2

OSe1

PD1

I
I

Mixer ground

Mixer IF output (non-inverting)
External oscillator input

3:
->w
W

VeOtank port
Powerdown LSB

PD2

VeO_BYPASS

veo bypass port (external capacitor)

VeO_GND

veo ground

veo_vee

veo voltage supply

Powerdown MSB

II:
C.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Vee .......................................................... -0.3 V to 6 V
Input voltage range, VI ...................................................... -0.3 V to Vee + 0.3 V
Power dissipation at or below TA = 25°C ................................................... 300 mW
Maximum operating virtual-junction temperature, TJ .......................................... 150°C
Operating free-air temperature range ................................................ -40°C to 85°C
Storage temperature range ........................................................ -65°C to 125°C

recommended operating conditions
MIN· NOM
Vee

Supply voltage

VIH

High-level input voltage

3.5

3.75

MAX

UNIT

5.5

Vee

VIL

Low-level input voltage

-0.3

0.8

Operating free-air temperature

-40

Virtual-junction temperature

-30

105

De
De

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-5

::)

II:

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021-JUNE 1996

electrical characteristics over recommended operating free-air temperature range and
Vee =3.75 V; measured in recommended application board
PARAMETER

TEST CONDITIONS

CASCADE (lNAlSAW:f:/MIXER)

MIN

TYPt

MAX

3.5

UNIT

IF= 45 MHz

Power conversion gain

SSB noise figure
Input 1 dB compression point
Input 3rd order intercept point, 2 f2 - f1
Input 2nd order intercept point, 2 flO - 2 fRF

flO = 914 MHz
fRF = 891.5 MHz

LO feedthrough to RF

880 MHz to 1070 MHz

dB
dB

-26

dBm

-14

-12

dBm

-45

-40

dBm

970

MHz

lNA

RF frequency range

850

Power gain

Noise figure

"'C

PD1 = 1,

PD2= 1

13.5

PD1 =0,

PD2= 1

PD1 = 1,

PD2= 1

1.8

PD1 =0,

PD2 = 1

Gain/temperature sensitivity

0.008

dB
dB/oC

:IJ

Gain/frequency sensitivity

Input return loss

ZI = 50n

-10

Output return loss

ZO= 50n

-12

-0.015

Reverse isolation

c::

o-I

-25

Input 1 dB compression

"'C

:IJ

Input 3rd-order intercept

PD1 = 1,

PD2= 1

-15

PD1 =0,

PD2= 1

-10

PD1 = 1,

PD2= 1

-6

PD1 =0,

PD2 = 1

-1

t Typical values are at TA = 25°C.
:j: Surface acoustic wave (SAW)

:.e

~TEXAS

INSTRUMENTS
7-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

dB/MHz
dB

dBm

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021-JUNE 1996

electrical characteristics over recommended operating free-air temperature range and
Vee =3.75 V; measured in recommended application board (continued)
PARAMETER

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

RFMIXER
RF frequency range

850

970

MHz

lO frequency range

880

1070

MHz

IF frequency range

100

MHz

Power conversion gain

SSB noise figure

RF input impedance

lO input impedance

External veo

IF output impedance

Open-collector output

RF input return loss

1000

ZI = 50 n

-10

lO input return loss

ZI = 50 n

-10

IF output return loss

ZO= 50n

-10

dBm

-1

dBm

Input 1 dB compression point
Input 3rd-order intercept point, 2 f2 - f1
Input 2nd-order intercept point, 2 flO - 2 fRF

flO = 914 MHz
fRF = 891.5 MHz

RF feedthrough to IF

850 MHz to 970 MHz

-20

lO feedthrough to IF

850 MHz to 1070 MHz

-25

lO feedthrough to RF

880 MHz to 1070 MHz

-15

Frequency range

Tuning range is 25 MHZ
min, 30 MHZ typ,
centered around the set
veo frequency.

Auxiliary LO output power

Into 50 n load

Phase noise

Offset = 60 kHz

Harmonics

1150

c..

MHz

....
o

::J

-11

dBm

-114

dBc/Hz

-20

dBc

c..

t TYPical values are at TA = 25°e.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

veo

650

3:
w
>
w

7-7

TRF1015
CELLULAR RECEIVER FRONT-END
SLWS021-JUNE 1996

current consumption over recommended operating free-air temperature range and Vee
(PD1 1, PD2 1)

TYPt

MAX

LNA

RF mixer

rnA

veo and buffer amplifiers

current consumption over recommended operating free-air temperature range and Vee
(PD1 0, PD2 1)

-I

MAX
8

rnA

RF mixer

rnA

m
=5

MAX
100

IlA

RF mixer

100

IlA

veo and buffer amplifiers

100

IlA

RF mixer

veo and buffer amplifiers
t

Typical values are at TA

=25°e.

~TEXAS

7-8

=3.75 V;

LNA

UNIT

TYPt

current consumption over recommended operating free-air temperature range and Vee
(PD1 = 1, PD2 = 0)

"'C

=3.75 V;

LNA

rnA

TYPt

current consumption over recommended operating free-air temperature range and Vee
(PD1 = 0, PD2 = 0)

UNIT

LNA

veo and buffer amplifiers

"'C

=3.75 V;

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

=3.75 V;

TYPt

MAX

100

JlA

rnA

UNIT
Il A

PD1
PD2

MIX-,OUTPower-Down
Logic

r - - - - - - t l - - - ' - - I2=0---,1

T-- t _.

=to _.

13.75 V

=t:

:;Qrr;i

13.75 V

(see Note B)

~~
z

"'C
"'C

o
~

o
z
Z

-n

o
:0
:s:

NOTES: A. Optional inductors to improve the LO input and AUX_LO return losses from -6 dB.
B. Optional capacitors to block this ICs dc components from entering the filters

m
r

c:
r

Figure 1. Recommended Application Circuit With External Oscillator

:c
:JJ

(J)

~
I

CD
CD
Ol

PRODUCT PREVIEW

:JJ
."

:JJ
0-1
Z:JJ
-I."
.......

Z ......
Cc.n

M31A31::1d .lOnaOl::ld
C/l

C/l

~
I

I 20 I

TC2! R1

=t C1

C
Z

13·75 V

0-1
m:D

....

. . "T1

::c
m
m

:D
"T1

o
z

"'tJ
"'tJ

-u

--I

o .... ~

~2~--;-

~~
m~~

(5
Z

§t::><

Z
"T1
o

~~;l>
~

lTHIl

:::c

:5:

_(f)~

~(Jl

~
(f)

....

'"'"

NOTES: A. Optional inductor to improve tlie LO input and AUX_LO return losses from -6 dB.
B. Optional capacitors to block this ICs dc components from entering the filters

Figure 2. Recommended Application Circuit With Internal Oscillator

(5
Z

l>CJ1

o(f)

z
c

TRFiOi5
CELLULAR RECEIVER FRONT-END
SLWS021-JUNE 1996

recommended component list
'-

RESISTORS:

CAPACITORS:

INDUCTORS:

Kamaya™ 1206

Murata™ 1206

Toko™ LL 1608 LL2012 32CS

Cl=100pF

Ll =220nH

= 1.S kn

R2 = 22

=S6 pF

C3 = 202 pF
C4

= 12 pF

CS = 100 pF

=8.2 nH

L3 = 8.2 nH
L4
LS

=8.2 nH
=8.2 nH

C6 = 100 pF
C7
C8

=2 pF
= 1 pF

C9 =2 pF

Others:

Cl0 = 100 pF

Pl = Coaxial Resonator - Trans-Tech™ SR8800LPQl OS08Y

Cll = 100 pF

Vl = Varactor - Siemens™ 88YS1-03W

C12 = 2 pF

Ul = TRF1015

C13 = 68 pF

U2 = Saw Filter - Murata SAFC881.5MA70N

:>
w
a:
a.

;::)

a
a:
a.

Kamaya is a trademark of Kamaya Electric Company, Ltd.
Murata is a trademark of Murata Manufacturing Co., Ltd.
Siemens is a trademark of Siemens Corporation.
Taka is a trademark of Taka, Inc.
Trans-Tech is a trademark of Trans-Tech, Inc.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-11

7-12

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

•

Fractional-N/lnteger-N High-Frequency
(O.7-2.2 GHz) Synthesizer for Radio
Frequency (RF) Channel

•

Dual Integer-N Low-Frequency
Synthesizers (70-250 MHz) for Transmit
and Receive Intermediate Frequency (IF)
Local Oscillators (LO)
Variable Denominator for Fractions 1:1
Through 1:13

o
•

Dual-Modulus Prescaler of 1:32, 33
Built-In Analog Switch and Timer to
Dynamically Change Filter Time Constants

•

Up to 20 MHz 3-Wire High-Speed Serial
Data Input Interface

•

Low Current Consumption and Standby
Mode

•

Suitable for Many Portable Cellular
Telephone Standards

PW PACKAGE
(TOP VIEW)
PDA1
VSSAUX1,2
lD
VCCAUX1,2
AUX2
SW2
PDA2
STROBE
ClK
DATA
VCCA
VSSA

10
2
3
4
5
6
7

8
9

10
11
12

24
23
22
21
20
19
18
17

16
15
14
13

AUX1
VCCCOM
REF
VSSCOM
VCcRF
VSSRF
RF
VCCP
REFC
REFM
PDM
S'v'v'1

description
Texas Instruments (TITM) TRF2040 is a triple-channel, fractional-N/integer-N frequency synthesizer component
for use in phase-locked loop (PLL) circuits. The high-frequency channel operates in fractional-N or integer-N
modes up to 2.2 GHz. The low-frequency channels operate in integer-N mode up to 250 MHz. The extreme
flexibility of this device and wide array of operating options furnish the user with reliable solutions to the
synthesizer needs of systems as diverse as advanced mobile phone service (AMPS), global system for mobile
(GSM), personal digital cellular (POC), personal communication service (PCS1900), and digital cellular
systems (OCS1800). A high-speed three-wire bus serial data structure provides broad control system design
compatibility. An 18-bit main counter provides division for input signals in two modes: a range of 700 MHz to
1,100 MHz and 1,100 MHz to 2,200 MHz. The auxiliary counters accept inputs between 70 MHz and 250 MHz.
The TRF2040 provides a channel selection local oscillator, a receiver auxiliary local oscillator, and transmitter
offset local oscillator control signals. These are charge pump output control currents for three separate loops.
The TRF2040 is offered in a 24-pin plastiC thin shrink PW small-outline package. The TRF2040 is characterized
for free-air operation from -40°C to 85°C.

is a trademark of Texas Instruments Incorporated.

PRODUCT PREVIEW Information concerns products In the formative or
design phase of development Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-13

3:
->w
w
a:
c.

o
a.::

TRF2040
FRACTIONAL·N/INTEGER·N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

functional block diagram
REFM

REF

"tJ

o
C

(')

-t

~----------------__~PDA1

AUX1

"tJ

~SW2

~----~~--------__~

AUX2

PDA2

STROBE~~--------~~----1.____- r__- r____~

U
Address Decoder

Lock Detect Control ~~----~-- LD
~______________

N, T

Control Register

PLL3 Control

Word-2

Control Register

PLL2 Control

Word-1

Control Register

PLL 1 Control

Device Control

CLK--------------__----------------~

~TEXAS

7-14

Test Mode Control

Word-3

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

1/0

AUX1

Auxiliary-1 PLL signal input

AUX2

Auxiliary-2 PLL signal input

CLK

Serial interface clock input

DATA

Serial interface data input

Lock detector output

PDA1

Auxiliary-1 PLL phase detector and charge pump output

PDA2

Auxiliary-2 PLL phase detector and charge pump output

PDM

Main RF PLL phase detector and charge pump output

REFC

External resistor connection to set fractional compensation charge pump output current

REFM

External resistor connection to set main charge pump output current

REF

External reference oscillator input

Main RF PLL signal input

STROBE

Serial interface load input

SW1

Analog switch 1 output

SW2

Analog switch 2 output

VCCRF

Main RF PLL supply voltage

VCCA

Analog supply voltage for main RF PLL charge pumps

VCCAUX1,2

Auxiliary-1, -2 PLL supply voltage

VCCCOM

Supply voltage for oscillator amplifier, control registers, and reference clock divider

VCCP

Main RF PLL prescaler supply voltage

VSSA

Analog ground for main RF charge pumps

VSSAUX1,2

Ground connection for auxiliary dividers and phase detectors

VSSCOM

Ground connection for oscillator amplifier, control registers, and reference clock divider

VSSRF

Ground connection for main RF dividers and phase detector

s:w

:>
w
a:

a..
I-

:l
C

a..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-15

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

control register bit assignment
FIRST IN MSB
23

LAST IN LSB
20

I 19 I 18 I 17 I 16 I 15 1

110

I9 I

8 1 7

I6 I5 I4

31 2

lalp lolR

Iu Iv Iw Ix

13 112 111
E

I F2 J

F1
L

1 1 1 0
C

M
S
y

1-bit data to control PLL 1. When 1, the PLL 1 is on. When 0, the PLL 1 is off.

S: 18-bit data for PLL 1 count~r.
C:
D:
E:
F1:
F2:

""tJ

o
C

4-bit fractional numerator data.
7-bit data to define main charge pump1 output factor.
1-bit data to control all TRF2040 circuits. When 1, all circuits are on. When 0, all circuits are off.
4-bit fractional denominator data.
1-bit data to control 13 denominator spreader function. When 1, spreader is on. May be used only in low range
input (H = 0).
G: 4-bit timer data to control low-pass filter switch and charge pump output current. When the reference clock of
PLL 1 counts to 16 times of this value, the mode is changed from fast lockup mode to locked mode.
H: 1-bit data to select input range of PLL 1. When 1, the input range is 2 GHz. When the range is 1 GHz.
I: 1-bit data to control charge pump1 output polarity. When I = 0, VCO frequency below reference frequency results
in source output current from charge pump.
J: 2-bit data to select the ratio of charge pump output current for PLL 1.
Output current ratio of fast lockup mode to locked mode is:

-I
""tJ

m
:5
m
c::=

c::::

K:
L:
M:
N:

0:
P:

Q:
R:

S:
T:
U:
V:
W:
X:
Y:

DATA

RATIO

00
01
10
11

9/1
9/2
9/3
9/4

7-bit data to define fractional compensation charge pump1 output factor.
S-bit data for reference post counter.
9-bit data for reference counter.
3-bit data for test mode.
1-bit data to select reference clock for PLL 1. When 1, the 3-bit post counter output is selected. When 0, the 11-bit
reference counter outputs is selected.
1-bit data to select reference clock for PLL2 and PLL3. When 1, the 3-bit post counter output is selected. When 0,
the 11-bit reference counter output is selected.
1-bit data to control the output charge pump polarity of PLL2. When I = 0, VCO frequency below reference
frequency results in source output current from charge pump.
1-bit data to control PLL2. When 1, the PLL2 is on. When 0, the PLL2 is off.
14-bit data for PLL2 counter.
3-bit data for test mode.
1-bit data to select clock for lock detection circuit. When 1, the reference clock for PLL2 and PLL3 is selected.
When 0, the reference clock for PLL 1 is selected.
1-bit data to control low-pass filter switch of PLL3. When 1, the switch is closed (on) and is in the lockup mode.
When 0, the switch is open (off) and is in the FM modulation mode.
1-bit data to control the output charge pump polarity of PLL3.
1-bit data to control PLL3. When 1, the PLL3 is on. When 0, the PLL3 is off.
14-bit data for PLL3 counter.

~TEXAS

INSTRUMENTS
7-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

main divider operation
The main RF divider in the TRF2040 divides by B for F1-C cycles and divides by B + 1 for C cycles resulting in
an average divide ratio of B+C/F1. The process is controlled by a modulo F1 accumulator which increments
in steps of C. B, C, and F1 are programmed using the serial interface.
B is the integer portion of the main divider ratio and can take on values ranging from 992 to 262143 (2 18 _1).
The lower range value is constrained by the type of dual-modulus prescaler implemented in the main divider.
Because the prescaler is a 32/33 prescaler, the minimum division ratio is determined by 32*31 =992.
The ratio of C to F1 provides the fractional portion of the main divider ratio. C can take on values ranging from
o to F1-1 , where F1 can take on ratios of 1 to 13. Because C can have a value of zero (0), the main divider can
operate in integer mode only, as opposed to integer plus fraction mode.

fractional compensation
Fractional-N division is used to achieve channel spacing frequencies that are much less than the phase detector
reference frequency. The benefits of fractional-N division are higher loop bandwidth and phase detector
reference frequency suppression. Unfortunately, fractional-N sidebands at, and factors of, the channel spacing
frequency will be present with non-zero fraction channels (C =/:- 0).
The TRF2040 design incorporates fractional sideband suppression methods. The scheme uses a
compensation charge pump to generate opposite polarity current pulses that are a function of the contents of
the fractional accumulator. These compensation pulses help to cancel the effects of the fractional error
component of the normal charge pump current. The pulse width of the compensation pulse is modulated by the
fractional accumulator in a manner so that the area (time x current) is proportional to the fractional error. The
magnitude of the compensation current is programmable (K).

sw
>
w
a:

0denominator spreading
A secondary method for reducing fractional sidebands is provided in the TRF2040. The user may selectively
(F2) activate a denominator spreading function which tends to spread the energy of the distinct fractional
sidebands over the system loop bandwidth. The denominator value is changed by -1, 0, + 1, or +2 every time
the fractional accumulator overflows. The frequency of the spreading is proportional to the numerator value.
This function is completely transparent to the user, and channel solutions need not be altered.

t:::>
O
C

a:
0-

speed-up mode operation
Additional charge pumps and an analog switch are provided in order to achieve faster tuning times. The loop
gain can be increased and the filter time constant can be reduced by incorporating the speed-up mode charge
pumps and the analog switch. The normal/speed-up mode current ratio is programmable (J) as well as the
speed-up mode duration (G). A 4-bit counter is referenced to the main loop reference clock; the counter is
decremented once for every 16 main divider reference counts. Speed-up mode will terminate when the 4-bit
counter reaches its terminal count of zero .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-17

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

main RF synthesizer charge pump current plan
The charge pumps for the main RF synthesizer are current outputs and are programmable with external scaling
resistors (REFM and REFC) and internal programmable DACs. The normal mode and speed-up mode main
and compensation charge pump currents are found as follows.
1.

Determine the reference voltages as a function of control fields D and K.
a.

Main charge pump reference voltage Vm as seen on terminal 15 (REFM),
V

i.e., If D
b.

::xJ

= (128

256

1 25 V

Calculate normal mode main charge pump current Inm,
Inm =

R~~M

x (J + 1) x 5,

where REFM is in kn and Inm is in rnA.

Calculate normal mode main charge pump current Inm,
Ism =

(")

-I

1 25 V

Determine normal mode and speed-up mode main charge pump currents as a function of Vm, REFM, and J.
a.

=0, Vm =0.625 V. If D = 127, Vm = 1.245 V.

""C

256

Compensation charge pump reference voltage Vc as seen on terminal 16 (REFC),
V

= (128

R~~M x

9 x 5,

where REFM is in kn and Ism is in mA.

i.e., REFM = 24 kn, D = 128, J = 0; Inm = 0.259 rnA peak; Ism

""C

::xJ

Determine normal mode and speed-up mode compensation charge pump currents as a function of Vc,
REFC, and J.
a.

<
m
=E

=2.33 rnA peak.

Calculate normal mode compensation charge pump current Inc,
Inc =

R~~C

x (J

1) + 60,

where REFC is in kn and Inc is in !lAo

Calculate speed-up mode compensation charge pump current Isc,

R~~C x 9 + 60, where REFC is in kn and Isc is in !lAo
i.e., REFC = 24 kn, K = 128, J = 0; Inc =0.856!lA peak; Isc = 7.78!lA peak.
Isc =

The average normal mode and speed-up mode main charge pump current is a function of the phase error by:
lavg _ main = Inm 2: Ism x Phase error.
The total average normal mode and speed-up mode charge pump current for the main RF synthesizer is the
sum of lavg-main and the compensation currents Inc and Isc by:
Itotal = lavg _ main

7-18

Inc

Isc .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

auxiliary divider operation
The auxiliary synthesizer loops operate in integer-only mode. The 8/9 prescalers used in the auxiliary dividers
(8 and Y) provide division ranging from 56 to 16384 (2 14_1). An additional analog switch is provided with the
auxiliary-2 charge pump output. This analog switch can be selected (V) on (low-impedance) or off
(high-impedance) in order to accommodate two loop filter frequency responses, one for normal locked mode
and another for frequency modulation (FM) mode.

auxiliary synthesizer charge pump current plan
The charge pumps for the auxiliary synthesizers are current outputs. The average auxiliary charge pump
currents will be a function of the phase error by:
Ph
A
Iavg - aux1 ,2 = 0.3
2lt x
ase error, m .

reference divider operation
The reference divider circuit consists of a main, 9-bit count (M) and a 5-bit post-counter (L). The main RF
synthesizer phase detector can be connected to output of the 9-bit counter directly or to the output of the 5-bit
post-counter directly using the programmable DP8T switch (O). The auxiliary synthesizer phase detectors can
be connected in a similar fashion (P).

lock detection
The unlocked state for an active channel is detected when the associated phase comparator output pulse width
becomes larger than one clock cycle of the selected reference frequency. A logic high on the LD pin indicates
a locked condition. A logic low on the LD pin indicates an unlocked condition.
The lock detect selection bit U in Word 3 selects the reference clock for the lock detection circuitry. If U = 0 and
the main RF PLL is activated by A =1, the locked or unlocked state of the main RF PLL will be indicated on LD.
If U = 1 and the auxiliary-1 PLL and/or the auxiliary-2 PLL is activated by R = 1 and/or X = 1, respectively, the
locked or unlocked state(s} of auxiliary-1, -2 PLL(s} will be indicated on LD.

powerdown control
Four control bits (A, E, R, X) are provided for power consumption control of the TRF2040. Bit E disables the
entire circuitry of the TRF2040 except the serial data interface. Bits A, R, and X disable the Main RF synthesizer,
the auxiliary-1 synthesizer and the auxiliary-2 synthesizer, respectively.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-19

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::l

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TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022-JUNE 1996

test mode operation
Various internal signals can be routed to the LD terminal for test purposes using Nand T fields as defined in
the following table:
N-BITS

T-BITSt

000

XOO

Lock detect pulse

ROUTING TO LD

001

XOO

Main prescaler output

000

X01

Main 5-bit sub counter output

001

X01

Main 13-bit main counter output

001

X10

Main phase detector down pulse output

000

X11

Main phase detector up pulse output

001

X11

Main phase detector VeO-side input

011

XOO

Reserved

010

X01

Reserved

011

X01

Fractional compensation pulse

011

X10

Auxiliary-1 prescaler output

010

X11

Auxiliary-1 3-bit sub counter output

"'tJ

011

X11

Auxiliary-1 11-bit main counter output

101

XOO

Auxiliary-1 phase detector down pulse output

100

X01

Auxiliary-1 phase detector up pulse output

101

X01

Auxiliary-1 phase detector VeO-side input

101

X10

Auxiliary-2 prescaler output

100

X11

Auxiliary-2 3-bit sub counter output

101

X11

Auxiliary-2 11-bit main counter output

111

XOO

Auxiliary-2 phase detector down pulse output

110

X01

Auxiliary-2 phase detector up pulse output

111

X01

Auxiliary-2 phase detector VeO-side input

111

X11

Lock detect clock pulse

-f
"'tJ

<
-

Bit 2 of the T-word is defined for an external clock pulse mode. In this mode, the internal counters of
all three synthesizers are fed clock pulses from an external clock source through SW1 as opposed to
being fed from the internal prescalers as in normal operation.

For normal device operation, zeros should be written to all bits of Nand T.

~TEXAS

INSTRUMENTS
7-20

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022-JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VeeRF, VeeAUX1,2, VeeCOM ................................. -0.3 V to 4.8 V
Input voltage range, VI ...................................................... -0.3 V to Vee + 0.3 V
Power dissipation at or below TA = 25°C ................................................... 300 mW
Maximum virtual-junction temperature, TJ ................................................... 150°C
Operating free-air temperature range TA ............................................ -55°C to 125°C
Storage temperature range, Tstg ................................................... -65°C to 150°C

recommended operating conditions
MIN

NOM

MAX

VCCRF

Main RF PLL supply voltage

2.7

3.6

UNIT

VCCAUX1,2

Auxiliary-1 and Auxiliary-2 supply voltage

2.7

3.6

VCCCOM

Common circuits supply voltage

2.7

3.6

2.7

VCCA

Analog supply voltage

VIH

High-level input voltage

VCC

VIL

Low-level input voltage

-0.3

0.8

1100

2200

MHz

fRF

=1)
RF input frequency in the 1 GHz mode (H =0)

700

1100

MHz

fAUX1

AUX1 input frequency

250

MHz

fAUX2

AUX2 input frequency

250

MHz

fREF

REF input frequency

MHz

Operating free-air temperature

-40

°C

Virtual-junction temperature

-30

105

°C

fRF

RF input frequency in the 2 GHz mode (H

3.6
V
V

3:
w

:>
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a.
t-

:::l
C

oa::

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-21

TRF2040
FRACTIONAL·N/INTEGER·N SYNTHESIZER CIRCUIT
SLWS022 - JUNE 1996

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER

TEST CONDITIONS

VOH

High-level
output
voltage

VCCAUX1,2 = 3 V,

IOH=-1 mA

VOL

Low-level
output
voltage

VCCAUX1 ,2 = 3 V,

IOL= 1 mA

Input
threshold
voltage

CLOCK

MIN

PDA1

VCCAUX1,2 = 3 V,

VO= 1.5 V

PDA2

VCCAUX1,2 = 3 V,

VO= 1.5 V

Analog
switch on
resistance

SW1

VCCRF=3 V,

VO=1.5V

SW2

VCCAUX1 ,2 = 3 V,

VO=1.5V

Fast lockup mode,

REFM = 24 kn,

Fast lockup mode,
PDM

REFM = 24 kn,

0= 0, J = 3
Locked mode,

REFM = 24 kn,

0=127

-I

REFM = 24 kn,

0=0

"tJ
lJ

Fast lockup mode,

REFC = 24 kn,

K = 127, J = 3
Compensation
charge
pump
output
current

Fast lockup mode,
PDM

REFC = 24 kn,

K = 0, J = 3
Locked mode,

REFC = 24 kn,

K= 127
Locked mode,

REFC =24 kn,

0=0
Auxiliary
charge
pump
output
currents

PDA1,2

ICCRF

PLL 1 supply current

VCCRF = 3 V

ICC AUX1 ,2

PLL2 and PLL3
supply current

VCCAUX1 ,2 = 3 V

ICCCOM

Common circuits
supply current

VCCCOM = 3V

ICCA

Analog supply current

VCCA=3 V

~TEXAS

INSTRUMENTS
7-22

0.4

VCCCOM/2

Locked mode,

m
<
-m

VCCAUX1,2-0.4

D=127,J=3

C
C

UNIT

DATA

Output
resistance

Main charge
pump
output
current

MAX

STROBE

"tJ
lJ

TYPt

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

4.67

2.34
mA
0.52
0.26

19.5

/lA

9.7

/lA

2.2

/lA

1.1

/lA

300

/lA

TRF2040
FRACTIONAL-N/INTEGER-N SYNTHESIZER CIRCUIT
SLWS022-JUNE 1996

serial interface timing requirements
PARAMETER

MIN

TEST CONDITIONS

TYP

MAX

UNIT

MHz

fclock

Clock frequency

tw H

Pulse duration

ClK high

tw l

Pulse duration

ClKlow

Data before ClK high

STROBE before ClK high

Data after ClK high

STROBE after ClK low

tsu

Setup time

Hold time

D:lt:l
Valid

D:lt:l
Change

DATA~~________________________

CLK~U
th

'11
~

STROBE 4

!IIII

1-\'
~
ww

0~! 1f\"L

Clock Enabled
Shift In Data

tsu

---.I

¥==
th

Clock Disabled

- I I~

Store Data

-+!

-VIH
-VIL
-VIH
-VIL

14-

-VIH
-VIL

:>
W

-I

Figure 1. Serial Input Timing Requirements

REFERENCE
CLOCK

;r?:

a:
a.

....

---_....

::l
C

DIVIDING NUMBER
N (VCO)

a:
a.

MAIN CHARGE
PUMP OUTPUT

COMPENSATION
CHARGE PUMP
OUTPUT - - - -....

NOTE: tw is proportional to the contents of the fractional accumulator.

Figure 2. Charge Pump Output Ripple Compensation

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-23

7-24

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

•
o

2.7 V - 5.1 V Operation
Low-Power Operation: 7 rnA at 3.6 V

•
•

1.1 GHz Operation
Two Operating Modes:
Philips SA7025 Emulation Mode
Pin-for-Pin and Programming
Compatible
Extended Performance Mode (EPM)
Programmable EPM Fractional
Modulus of 1-16
Dual RF - IF Phase-Locked Loops

o
o
•
•

PWPACKAGE
(TOP VIEW)

CLOCK
DATA
STROBE

VSS
RFIN
RFIN

Veep
REFIN
RA
AUXIN

10
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VDD
TEST
LOCK
RF
RN

VDDA
PHP
PHI

VSSA
PHA

Fractional-N or Integer-N Operation
Normal, Speed-Up, and Fractional
Compensation Charge Pumps

description
The TRF2050 is a low-voltage, 1.1-GHz, fractional-N/integer-N, dual-channel, low-power, PLL (phase-locked
loop) frequency synthesizer component for IS54 cellular applications. Fractional-N division and an integral
speed-up charge pump are used to achieve rapid channel switching. Two operating modes are available:
1) SA7025 emulation mode in which the part emulates the Philips SA7025 fractional-N synthesizer for a wide
range of main divider division ratios, and 2) EPM (extended performance mode) that provides additional
features including fractional accumulator modulos from 1 to 16 (compared to only five or eight for the SA7025)
and programmable control of the speed-up mode duration (compared to the SA7025 method of holding the
strobe line high).
Along with external loop filters, the TRF2050 provides all functions necessary for VCO control in a dual-PLL
frequency synthesizer system. A main channel is provided for RF (radio frequency) channels and an auxiliary
channel for IF channels. The current-output charge pumps directly drive passive RC filter networks to generate
VCO control voltages. Rapid main-channel frequency switching is achieved with a charge pump arrangement
that increases the current drive and alters the loop-filter frequency response during the speed-up mode portion
of the switching interval.

These devices have limited built-in ESD protection. The leads should be shorted together orthe device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-25

w
:>
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::J
C

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TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

functional block diagram
DATA~2~~-------------r-------------------------------.

CLOCK _1__.-______________- 4
STROBE --=3~~_ _ _ _ _ _ _--1

Serial Control Shift Registers

Common Registers

EPM Registers

7025 Registers

Conversion and Selection t

Control Lines

1-+4--.:.1-'...7 RF

L.-_ _ _ _......

~~~~~~~11!4 PHP

RFIN

I--t--~t-~

t -......1-'-1.;::...6

'"C

~---=:;~::::;--'

RFIN

:IJ

o
C

1--o....:.1.=..3 PHI

Lo-_ _ _ _......

REFIN _8'------1.-_ _1

1___________
.~1=8
LOCK

"1J

:JJ

r-~:=~1-~~9 RA

AUXIN -,1:...=0~____-I

Conversion and selection block provides emulation of SA7025 64/65/72 triple-modulus prescaler operation using the TRF2050 32/33
dual-modulus prescaler.

•
TEXAS
INSTRUMENTS
7-26

POST OFFICE BOX 055303 • DALLAS, TEXAS 75265

PHA

TRr-2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030-JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

1/0

DESCRIPTION

AUXIN

Auxiliary channel RF input

CLOCK

Serial interface clock signal

DATA

Serial interface data signal

LOCK

Lock detector output
Auxiliary charge pump output

PHA

PHI

Integral charge pump output

PHP

Proportional charge pump output

RFIN

Prescaler positive RF input

RFIN

Prescaler negative RF input

REFIN

Reference frequency input signal

Resistor to VSSA sets auxiliary charge pump reference current

Resistor to VSSA sets proportional and integral charge pump reference current

Resistor to VSSA sets compensation charge pump reference current

STROBE

Serial interface strobe signal

TEST

Test Terminal

VCCP

Prescaler positive supply voltage

VDD

Digital supply voltage
Analog supply voltage

VDDA

VSS

Digital ground

VSSA

Analog ground

3:
w
>
w

a..

I-

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, VCCP, Voo, VOOA (see Note 1) ...... '" .... '" ................. -0.6 V to 5.6 V
Input voltage range, logic signals .................................................... -0.6 V to 5.6 V
Operating ambient temperature range, TA ............................................ -55°C to 85°C
Storage temperature range, Tstg .................................................... -65°C to 150°C
t

recommended operating conditions
Supply voltage, VCCP. Vcc. VDD, VDDA
High-level input voltage, VIH

MIN

NOM

MAX

2.7

3.6

5.1

Low-level input voltage, VIL

0.05

0.5

1.6

GHz
MHz

Reference input frequency, f(REFIN)

Auxiliary input frequency, f(AUXIN)

200

Differential RF input power, VID(RFIN) (50-n characteristic impedance)

V
V

VCC -0.5

RF input frequency, f(RFIN)

UNIT

MHz

-20

dBm
Vpp

Reference input voltage, VI(REFIN)

0.2

Auxiliary input voltage, VI(AUXIN)

0.2

Operating free-air temperature, TA

-40

Vpp

°c

"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-27

o
:::;)
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o
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a..

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

electrical characteristics over recommended operating free-air temperature range, vee
TA 25°C (unless otherwise noted)

=3.6 V,

supply current
PARAMETER

MIN

MAX

Average operational supply current

digital interface
PARAMETER
VOH

High-level output voltage

VOL

Low-level output voltage

IIH

High-level input current

IlL

Low-level input current

TEST CONDITIONS
IOH = 3.2 mA

LOCK

MIN

TYP

MAX

0.5

IOL = -3.2 mA
DATA, CLOCK,
STROBE

UNIT
V

VCC-0.5

IJA

auxiliary pump currents
PARAMETER

TEST CONDITIONS

MIN

RA= 100 kil

"'tJ

c::

-I
"'tJ

<
-

MAX

proportional charge pump current

TYP
±0.25

PARAMETER
IPHP_N
IpHP _S

TEST CONDITIONS

Normal mode (locked)

CN = 128,

RN = 18 kil

Speed-up (channel-switching) mode

CN = 128,
RN = 18 kil

CL= 1,

MIN

TYP

MAX

UNIT

±0.5

±2.5

compensation charge pump current
PARAMETER

TEST CONDITIONS

IpHC_N

Normal mode (locked)

RN = 18 kil,

RF = 24 kil

IPHC_S

Speed-up (channel-switching) mode

CL= 1,
RF= 24 kil

RN = 18 kil,

MIN

TYP

MAX

UNIT

±1.3

±6.3

integral charge pump current
PARAMETER
IpHLN
IpHN_S

TEST CONDITIONS

MIN

Normal mode (locked)
CN = 128,
CK=4,

Speed-up (channel-switching) mode

CL= 1,
RN = 18 kil

TYP

MAX

UNIT

±8

main charge pumps current plan
OPERATION
MODE

TEST
CONDITION

UNIT

Peak proportional output (PHPPK-NM) = [(18.75/ (RN + 0.75)) x CN/256)]

Normal

(RN in kil)

Average proportional output (PHPAVG-NM) = (Phase Error 121t) x PHPPK-NM

Normal

PARAMETER

Peak proportional output (PHPPK-SM)=
{[(18.75 1 (RN + 0.75)) x (CN/256)] + [(18.751 (RN + 0.75)) x (CN/256) x 2CL+1]}

Speed-up

Average proportional output (PHPAVG-SM) = (Phase Error 121t) x (PHPPK-SM)

Speed-up

Peak integral output (PHlpK-SM) = [(18.751 (RN + 0.75)) x CK x (CN/256) x 2CL+1]

Speed-up

Average Integral output (PHIAVG-SM) = (Phase Error 121t) x PHlpK-SM)

Speed-up

Peak compensation output = 30/RFt

mA
(RN in kil)

mA
mA

(RN in kil)

mA
mA

(RF in kil)

IJA
t The average compensation output current is a pulse-width-modulated function of the contents of the fractional accumulator and the peak
compensation output current.

•
TEXAS
INSTRUMENTS
7-28

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

auxiliary charge-pump current plan
PARAMETER

=20 x 1.25/ RA
Average auxiliary output (PHAAVG) =(Phase Error / 2 n) x PHApK
Peak auxiliary output (PHApK)

TEST CONDITION

UNIT

(RAin kil)

rnA
rnA

timing requirements, serial data interface
TEST CONDITIONS

PARAMETER

MIN

MAX

UNIT

MHz

f(CLOCK)

Clock frequency

tw{CLKHI)

Clock high time pulse width, CLOCK high

tw(CLKLO)

Clock low time pulse width, CLOCK low

tsu(D)

Setup time, data valid before CLOCKi

n::;

th(D)

Hold time, data valid after CLOCKi

tsu(Strobe)

Setup time, STROBEi before CLOCKi

th(Strobe)

Hold time, STROBE,!. after CLOCK low

::w

PARAMETER MEASUREMENT INFORMATION

->w

Change

14 Valid

DATA

~~____________________~:I
I

tSU(D~14
~
th(D) 14 , tw(CLKHI)
1

~ I.-

-----.+--

,.1

tsu(Strobe)

--J~

STROBE ________________________________________

I-

o
~
c

_--;II~_ _....J:
4

a:
a.

CLOCK

th(Strobe)

I
I

oa:

~::

Figure 1. Serial-Data Interface Timing

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-29

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

PRINCIPLES OF OPERATION

serial control
Instruction word formats for the SA 7025 emulation mode are shown in Figure 2; Table 1 lists the corresponding
function table.
Instruction word formats for extended performance mode are shown in Figure 3; Table 2 lists the corresponding
function table.
MSB (Last In)
031

LSB (First In)

WORD ~
A1

"tJ

o
C

-I

"tJ

m
S

m
~

101 0
I

SM
I

EMO
SA AON

Figure 2. Serial Word Format for SA7025 Emulation Mode

•
TEXAS
INSTRUMENTS
7-30

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

PRINCIPLES OF OPERATION
Table 1. SA7025 Emulation Serial-Word-Format Function Listing
FUNCTION

SYMBOL

BITS

NM1

Number of main divider cycles when prescaler modulus

NM2

8 if PR = 01
4ifPR=10

Number of main divider cycles when prescaler modulus

=64
=65

NM3

4 if PR = 10

Number of main divider cycles when prescaler modulus

=72

Prescaler type:
PR = 01; modulus 2 pre5caler (64/65)
PR = 10; modulus 3 prescaler (64/65/72)

Fractional-N increment

FMOD

Fractional-N modulus selection:
0= modulo 5
1 = modulo 8

LONG

A word format selection:

o = 24-bit AO format

3:
w
>
w

1 = 32-bit A 1 format
Binary current-setting factor for main charge pumps

Binary acceleration factor for integral charge pump current

Binary acceleration factor for proportional charge pump current

Auxiliary divider enable flag:
0= disabled
1 = enabled

Auxiliary divider ratio

Auxiliary prescaler select:
o = divide by 4
1 = divide by 1

Reference divider ratio

Reference select for main phase detector

Main divider enable flag:
0= disabled
1 = enabled

Reference select for auxiliary phase detector

Test mode connection of internal signals to the LOCK terminal:
00 = LOCK
01 = Auxiliary divider
10= Main divider
11 = Reference divider

c..
Io

=»
c
o
a:

c..

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-31

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030-JUNE 1996

PRINCIPLES OF OPERATION
MSB (Last In)
031

WORD:, H:

LSB (First In)
DO

N~: 1 : : : :N: : : : : : : : : : : : : 101 : : :c~ :::1

023

0
1 1:

N~:

I : : : : N:

0
: : : : : : : : : : : : 11

~ :I:::~N: : : I:~K: I~L 1*1
I' :0: 0:'I :::::~A: : : : : I:1 :F~~D: I0:' I
D I' :0:' :0I:::::~R: : : : : I-~ I~I _+1 0: 01

B I' :0: 0: 0I:
-a

:a
o
c
c:

-I

-a
m

:sm

I~I

1':':':'1

Figure 3. Serial Word Format for Extended Performance Mode

~TEXAS

INSTRUMENTS
7-32

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

PRINCIPLES OF OPERATION
Table 2. Extended Performance Mode Function Table
Symbol

Bits

Same as
SA7025
Mode

Function

Fractional-N increment

Overall main divider integer division ratio (NM)

Yes

Binary current setting factor for main charge pumps

Speed-up mode duration (number of reference divider cycles)
Binary acceleration factor for integral charge pump current

Yes

MCP

Main charge pump polarity:
0= positive
1 = negative

ACP

Auxilliary charge polarity:
0= positive
1 = negative

Yes

Auxiliary divider ratio

Yes

Auxiliary prescaler select:
o = divide by 4
1 = divide by 1

Binary acceleration factor for proportional charge pump current
Auxiliary divider enable flag:
0= disabled
1 = enabled

FMOD

Fraction accumulator modulus

Yes

Reference divider ratio

Yes

Reference select for main phase detector

Yes

Main divider enable flag:
0= disabled
1 = enabled

Yes

Reference select for auxiliary phase detector

w
>
w
a:
c..

a:
c..

Test mode connection of internal signals to the LOCK terminal:
00= LOCK
01 = Auxiliary divider
10 = Main divider
11 = Reference divider

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-33

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030-JUNE 1996

PRINCIPLES OF OPERATION

main divider
The main divider in the TRF2050 divides by N for FMOD-NF cycles and by N+1 for NF cycles resulting in an
average divide ratio of N+NF/FMOD. The process is controlled by a modulo FMOD accumulator, which
increments in steps of NF. N, FMOD, and NF are programmable using the serial interface.
The main divider organization is shown in Figure 4. The 32133 prescaler uses a bipolar design to meet the
requirement of 1.6-GHz maximum RF input frequency. All remaining blocks are low-power CMOS designs.
13-Bit
B-Counter

RFIN - - - + 1

PV (to Phase Detector)

14
*A _ _ _ B--.I
N~

/5 Bits /

"'C

LSB

o
C

13 Bits

MSB

c:
o

N-----......,"'-------~
4
NF -....,....--I~

-I

5-Bit

FMOD _---."'"""""'I~ Fraction Accumulator 1 - 4 - - - - - - - - - '

"'C

Figure 4. Main Divider Organization

S
m
::E

~TEXAS

7-34

]

fPV
~RFIN I (N+NF/FMOD~

Structure of N-Word

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

PRINCIPLES OF OPERATION

fractional compensation
Fractional-N division is used to achieve channel spacing that is much smaller than the phase detector
comparison frequency. As an example of this application, Figure 5 shows a configuration for generating the RF
local oscillator for a TIA (Telecommunications Industry Association) Standard IS54 cellular telephone
application. A phase detector compares the reference divider frequencies (fCR) with the feedback signal (fcv)
from the VCO. Channel spacing is 30 kHz for a phase detector comparison frequency of 240 kHz.
fRF

=(N+NF/FMOD) x 240 kHz
(940.56 - 965.73 MHz
in 30 kHz steps)

fREF=
19.44 MHz
NR (81) - - - - - - - - '

NF (0-7) -------I~
Fraction
FMOD (8) - - - - - -..... Control
N (4023-3919) - - - - - - - - . . J___.....,_.......

Figure 5. IS54 Fractional-N Synthesizer Example
The fractional divide process causes variations in the period of the main divider output waveform because
dividing by N+1 requires one more input cycle than dividing by N. For example, in a 1-GHz application, the main
divider output period is 1 ns longer when dividing by N+ 1 than when dividing by N. This results in a periodic phase
error and corresponding sidebands (fractional spurs) in the VCO output spectrum. The TRF2050 design
includes a fractional compensation scheme for surpressing the fractional spurs. The scheme uses a
compensation charge pump to generate opposite polarity current pulses that cancel the effects of the fractional
error component of the normal charge pump current. The fractional accumulator contents are used to modulate
the width of the compensation current pulses so that the area (current x time) is proportional to the fractional
error. An offset is introduced so that the compensation pulses are always the same polarity. Figure 6 shows the
fractional compensation operation of the synthesizer for an output frequency of 953.25 MHz.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-35

w
==
:>
w
a:
c..

....

::l
C

a:
c..

TRF2050
LOW-VOLTAGE 1.1-GHz FRACTIONAL-N IINTEGER-N SYNTHESIZER
SLWS030 - JUNE 1996

PRINCIPLES OF OPERATION

Number of Main
Divider Pulses
RF Input

114
..,.
1

N+1
(3972)

1
.14
1

N+1
(3972)

1
.14
1

N+1
(3972)

1
.14
1

N+1
(3972)

1
.14
1

N+1
(3972)

1
.14
1

N+1
(3972)

1 (3971) 1
.14
.1
1
1

rtfl flfUlJl. nnnn. nnnn. nnnn. nnnn. nnnn. nnnn. nIL

Main Divider Out

I
I

REF Divider Out

-JL
_I I ---...."----",.---'"'L---:tr--,,,.---'"'L----'L-..___~
Phase Offset

Phase Error

Phase Offset

'"tJ
::D

Phase Offset Component

C
C

-I

LJl

Fractional Error Component

Main Charge
Pump Currents

'"tJ
::D

Total

m
<
m

Equal and Opposite Areas

Compensation
Charge Pump Current

Figure 6. IS54 Fractional-N Synthesizer
Operational at 953.25 MHz with N 3971, NF 7 and FMOD

•
TEXAS
INSTRUMENTS
7-36

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TRF3020
IIQ AND FM MODULATOR
SLWS019 - JUNE1996

•

Offset Voltage-Controlled Oscillator (VCO)
and Single-Sideband Suppressed Carrier
(SSBSC) Downconverter Generate TX
Carrier From External Receive Local
Oscillator (RXLO)
Direct 1/0 Modulator For Digital
rr/4-Differential Ouadrature Phase-Shift Key
(DOPSK) Gaussian Mean Shift Key (GMSK)
Transmission

•

Variable Gain Amplifier (VGA) With
-31 to 9 dBm Output Power Control

•
•

Operates From 3.5 V to 4.2 V
Suitable for Portable Digital Cellular
Telephones [(IS-54), Global System for
Mobile (GSM)]
Serial Data Interface

•

48-Pin Ouad Flatpack (LOFP)

Frequency Modulation (FM) of VCO or FM
Synthesis Using 1/0 Modulator for Analog
Transmission
PT PACKAGE
(TOP VIEW)

:J:JCIlW

000000

ooo~~

zzzzzzza::::2:xx>

0484746 45 4443 4241 40 393837
NC

TXEN
DATA
ClK

NC
GND
TXlO+
TXlOlOCK
PHSOUT
IPEAK
GND
TNK+

4
5

STROBE
GND

->w
w
a:
c.
t-

Vee

8
9

Q+

Q-

::l

13 14 1516 17 18 19 20 21 222324

c..

1000000+0100
~ozzzzz~z~zo
~> (!}
w
a::
a.
Io
::)

Q+

TNK+

Q-

'-----~~~:

TNK-

oa::

-!!1

TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-39

TRF3020
I/Q AND FM MODULATOR
SLWS019 - JUNE1996

Terminal Functions
PIN
NAME

NO.

DESCRIPTION

1/0

CLK

DATA

GND

5,11,15,16,17,
18,19,21,23,
30,

Clock input
Serial data input
Ground

Noninverting in-phase baseband input

Inverting in-phase baseband input
Peak charge pump current set

IPEAK

LOCK

Lock detect digital output signal

MCLK

Master clock output

1,2,3,4,32,36,
42, 43, 44, 45,
46,47,48

No connect

PHSOUT

"tJ

Q+

Noninverting quadrature baseband input

Q-

Inverting quadrature baseband input

RCLK

STROBE

Data strobe enable

TNK+

Offset VCO noninverting tank port

o-I
"tJ

<
-

Phase detector charge pump output

Reference clock output

TNK-

Offset VCO inverting tank port

TX+

Noninverting transmit output

TX-

Inverting transmit output

TXEN

Transmit enable

TXLO+

Noninverting transmit LO input

TXLO-

Inverting transmit LO input

XTLB

Crystal oscillator base

XTLE

Crystal oscillator emitter

VCC

14,24,29,37

Power supply

~TEXAS

INSTRUMENTS
7-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF3020
IIQ AND FM MODULATOR
SLWS019-JUNE1996

absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, Vee ......................................................... -0.3 V to 4.5 V
Power dissipation, TA = 25°C, 48-pin plastic LQFP .......................................... 450 mW
Maximum operating virtual-junction temperature, TJ .......................................... 150°C
Operating free-air temperature range ................................................ -40°C to 85°C
Storage temperature range ........................................................ -65°C to 150°C

recommended operating conditions
PARAMETER

MIN

NOM

MAX

UNIT

3.6

3.75

3.9

VCC

Supply voltage

VIH

High-level input voltage

0.7VCC

VCC+0.3

VIL

Low-level input voltage

-0.3

0.3VCC

VIC

Common mode voltage of baseband inputs

TXLO

Input power

-13

-10

dBm
MHz

0.5VCC

TXLO

Input frequency

900

1040

Operating free-air temperature

-40

°C

Operating virtual-junction temperature

-40

105

°C

electrical characteristics at

PARAMETER

ICC

Vee =3.75 V, TA =25°C (unless otherwise noted)

Supply current

VOL

Low-level output voltage, LOCK

VOH

High-level output voltage, LOCK

TEST CONDITIONS

MIN

TYP

Sleep

Receive

Transmit

130

MAX

IO(LOCK) = 2 mA

0.40

IO(LOCK) = 1 JlA

0.05

IO(LOCK) =-2 mA

VCC-0.40

IO(LOCK) = -1 IlA

VCC-0.05

UNIT

I-

w
c..

U
:::l
C

o
a::

c..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-41

TRF3020
1/0 AND FM MODULATOR
SLWS019 - JUNE1996

electrical characteristics at vee

=3.75 V, TA =25°C (unless otherwise noted)
TEST CONDITIONS

PARAMETER

MIN

ac coupled, 50 0 single-ended and

TXlO input VSWR

TYP

MAX

UNIT

MHz

2:1

100 0 differential

Offset VCO frequency

200

PHSOUT output level

0.5

VCC-0.5

PHSOUT peak current

Rset = 4.7 kO

XO frequency
XO external drive level

6.4
10

ClK duty cycle

50%

MClK duty cycle

50%

ClK1 duty cycle

V
mA
MHz
Vp _p

50%

ClK output level

5 kO 117 pF

Vp _p

MClK output level

5 kO 117 pF

ClK1 output level

5 kO 117 pF

V _
pp
Vp_p

TX+fTX- frequency

820

920

MHz

TX+fTX- impedance

Differential

200

TX+fTX- VSWR

ZO= 200 0

2:1

TX+fTX-level

Zo = 200 0, I/O quadrature

TX+fTX-level flatness

Zo = 200 0" I/O quadrature
824-849 MHz

TX+fTX- 3rd order modulation spurious

I/O in-phase

-42

-36

dBc

TX+fTX- 5th order modulation spurious

I/O in-phase

-55

-45

dBc

TX+fTX- 7th order modulation spurious

I/O in-phase

-65

-53

dBc

TX+fTX- carrier suppression

I/O quadrature

-45

TX+fTX- sideband suppression

I/O quadrature

-45

dBc

TX+fTX- broadband noise

869-894 MHz

-136

dBm/Hz

'"'C

C
C

-I
'"'C

<
-

TX+fTX- other spurious

dBc

dBc/Hz

-101

f = 60 kHZ
2-824 MHz

-45

dBc

824-849 MHz

-47

dBc

849-869 MHz

-45

dBc

869-894 MHz

-104

dBm

894-8490 MHz

-45

dBc

TXlO and harmonics

-21

dBc

MHz

Baseband frequency
Baseband level

Differential

0.6

Baseband impedance

Differential

Offset loop lock time

fo = ±200 Hz

~TEXAS

INSTRUMENTS
7-42

dBm

-95

f = 30 kHZ

TX+fTX- phase noise

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.8

Vp-p
kO

Il s

TRF3020
110 AND FM MODULATOR
SLWS019 - JUNE1996

serial control interface timing requirements
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

MHz

fclock

Clock frequency

tw H

Pulse duration

ClK high

tw l

Pulse duration

ClK low

DATA before ClK high

STROBE before ClK high

DATA after ClK high

STROBE after ClK low

Setup time

tsu

Hold time

serial control interface timing characteristics
Data
Valid

Data

IChangel

DATA

3=
->w
w
a:

CLK

I"
STROBE

-. .

-------------+-+---C-I-OC-k-E-n-a-b-le-d-~----Jf1
Shift in Data

Clock msabled
Store Data

c..
tO

::J

Figure 1. Serial Input Timing Sequence

Gword
D23

SPARE

data field description
Table 2 describes the data field assignments found in the 24-bit, serial data G word.
Table 2. G Word Data Field Functions
DATA
FIELD

BITS

Power control

FUNCTION

+N, N=6, 7, 8, 9

MODE

AMPS mode

Synthesizer on/off

SM1

Sleep mode 1

SM2

Sleep mode 2

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-43

c..

TRF3020
IfQ AND FM MODULATOR
SLWS019 - JUNE1996

PC - power control (VGA)
The power control circuit has a control range of 40 dB (0 dB to -40 dB) with a monotonically decreasing slope.
Power control decreases in steps of 0.2 dB from 0 dB to -12 dB and in steps of 2 dB from -12 dB to -40 dB.
The nominal power output of the VGA is 9 dBm.

N - variable modulus select
The offset veo modulus division ratio (+N) is determined by the values of bits N1 and NO as shown in Table 3.

Table 3. Offset VCO Modulus Select
N1

MODE - output driver mode select
The mode bits allows a reduction in current for the TX output driver while in AMPS mode. MODE = 1 for
non-AMPS, MODE = 0 for AMPS.

"tJ

SE - synthesizer enable

SM1 - sleep mode 1

The SE bit turns on and off the offset loop synthesizer circuits. SE

-I
"tJ

The SM1 bit is used to shut down the TXLO buffer. SM1

= 1, buffer on; SM1

= 0, buffer off.

SM2 - sleep mode 2

<
-

= 1, synthesizer on; SE = 0, synthesizer off.

The SM2 bit is used to shut down the RCLK buffer. SM2

= 1, buffer on; SM2 = 0, buffer off.

powerdown control
The powerdown control of TRF3020 internal functions is determined by the states of G word data bits SE, SM1,
SM2, and PC and by external control signal TXEN as shown in Table 4.

Table 4. Powerdown Control
FUNCTION
Crystal oscillator

SLEEP

MODE
RECEIVE

TRANSMIT

DATA BITI
CONTROL BIT

Phase detector

Offset divider

OffsetVCO

VCO buffer

SSBSC downconverter

MCLK buffer

RCLKbuffer

On
On

SM2

TXLO buffer

SM1

I/Q modulator

VGA

TXEN,PC

Control logic

Lock detect

•
TEXAS
INSTRUMENTS
7-44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF3020
1/0 AND FM MODULATOR
SLWS019 - JUNE1996

CLKt
CATAt

(2)

---..r-L

SYNENt

(3)

STROBEt

3:
w
:>
w

CLOCK, DATA, STROBE, and TXEN are device terminal connections. SYNEN is an internal signal.
SYNEN and TXEN Enable Control
SYNEN

TXEN

Phase detector
VCO

a..

VGA

+N variable modulus select

I-

SSB downconverter
I/Q modulator

::J
C

Figure 2. Transmit Offset Synthesizer Reset Circuit

transmit offset synthesizer reset circuit
The transmit offset synthesizer reset circuit, as shown in Figure 2, provides power control of the transmit offset
synthesizer, TXLO buffer, and the SSB downconverter during transmit frame sequences. The address decoder
for the G word ANDed together with the strobe signal is used to transfer the contents of the temporary holding
register into the working register. D-flip-flop (3) is used to prevent multiple strobe and address pulses in the event
the address decoder output toggles on garbage bits during the time the strobe remains in a high state.
With the falling edge of the strobe signal and SE = 1, the transmit offset synthesizer, TXLO buffer, modulator
and SSB downconverter are enabled with SYNEN = 1. After the synthesizer is locked and just before the
beginning of a transmit frame, the TXEN = 1 signal turns on the variable gain amplifier.
The rising edge of TXEN has no effect on SYNEN, butthe falling edge ofTXEN toggles the Q output of Dflip-flop
(2) to a 0 state. This, in turn, resets D flip-flop (1) which causes SYNEN to go to a 0 state thereby disabling the
synthesizer, modulator, and variable gain amplifier.
The G word must be reloaded and the above sequence repeated for every subsequent transmit frame event.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-45

a..

TRF3020
I/Q AND FM MODULATOR
SLWS019 - JUNE1996

Table 5. Typical Filter Network
VALUE

COMPONENT DESIGNATOR

DUAL MODE

AMPS MODE

560n

1 kn

5.6 kn

2.2 nF

2.7 JlF

No load

0.27 JlF

33 pF

6.8 nF

RSET

15kn

75 kn

I-----: II
I
R2

PHSOUT >>--I*-R-1-

T""C

C3 • VCTRl

Figure 3. Typical PLL Filter

i --f-f'Nv--

o
c

-I

TNK+

""C

IE:

m
<

-m

vcc

(Amps Modulation)

120 MHz

fVCO

~ ~
VR1

1
2n Jl1 C'
VCTRL

(1 1

+ C1 + C2 + CJR1

C1 = C2 = 33 pF
C3
12 pF

TNK-

= 82 nH

Figure 4. VCO Tank Configuration

CVAR

Figure 5. Crystal Oscillator Configuration

~TEXAS

INSTRUMENTS
7-46

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

)-1

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

• 3.6-V and 4.8-V Operating Voltage
for AMPS/NADC and GSM Cellular
Telephone Applications Respectively

• High Power Efficiency
- at 35 dBm Output Power,
53% PAE Typical
- at 29 dBm Output Power,
30% PAE Typical

• Wide UHF Frequency
Range: 800 to 2000 MHz,
Suitable for PCS Applications

• Extremely Reliable
• Suitable for GSM and Highly
Linear NADC Applications
o SOT-89 Plastic Power Package

• High Output Power
- at 4.8 V and 900 MHz,
35 dBm Typical (CW or pulsed)
- at 3.6 V and 836 MHz,
31 dBm Typical (CW or pulsed)
• High Gain
- at 4.8 V and 900 MHz,
14 dB Typical Gain at Po 35 dBm
- at 3.6 V and 836 MHz,
19 dB Typical Gain at Po = 29 dBm

PK PACKAGE
(TOP VIEW)

3:
w

:;:
G

w
a:
a.

I-

description
The TRF7000 is a gallium arsenide MESFET (metal Schottky field-effect transistor) housed in an SOT-89 (PK)
plastic power package. It is designed for high power applications in the 800 MHz to 2000 MHz frequency range
and is a low cost solution that is suitable for use in either GSM (Global System for Mobil Communications) or
highly linear dual-mode AMPS/NADC (Advanced Mobile Phone Service/North American Digital Cellular) mobile
telephone systems. A wide operational frequency range allows the TRF7000 to be used in PCS (personal
communications systems) applications.
A O.S-micron gate length and an interdigitated structure using airbridge interconnects between drain fingers
provide high gain, high frequency cut-off, and high power-efficiency (PAE). Gold metalization and silicon nitride
passivation assure a reliable device.

PRODUCT PREVIEW Information concerns products In the formative or
design phase of developmenl Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-47

o
~
c

a:
a.

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Drain-source voltage, VDS (see Note 1) ...................................................... 15 V
Gate-source voltage, VGS .................................................................. -5 V
Drain current, IDS (VG = 0 V) ................................................................ 6 A
Total power dissipation, PT at T C = 25°C ..................................................... 4 W
Storage temperature, Tstg ........................................................ -65°C to 150°C
Channel temperature, TCH ................................................................ 175°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only. and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltages are with respect to GND.

electrical characteristics at VOS as specified and TA = 25°C
DC characteristics
TEST CONDITION

PARAMETER

MIN

TYP

MAX

UNITS

Saturated drain current

VGS=O.
VDS swept between 0.5 V and 3.5 V.
searching for maximum IDS.
VDS at IDSS recorded as VDSP

Transconductance

IIDSS - IDS1 II VGS.
VDS swept between 0.5 V and VDSP.
searching for maximum IDS.
recorded as IDS1.VGS = -0.5 V

Pinch-off voltage (Vp)

VDS = 2 V.
VGS swept to bring IDS = 0.5 mNmm

-3.8

-2.9

-2

"tJ

V(BR)GD

Gate-drain breakdown voltage

Drain is grounded.
Source is floating.
1 mNmm drawn at the gate

-30

-14

-8

m
<

Thermal resistance

Channel to case

"tJ

::D

o
C
C

o-I
::D

3300

°C/W

NAOC RF characteristics
PARAMETER
Po

Output power

Power gain
Power-added efficiency. (PAE)

TEST CONDITION
Class NAB.
IDSQ = 900 mA,
f = 836 Mhz.

MIN

VDS = 4.8 V.
PI = 10 dBm.
Fixed test circuit

TVP

MAX

UNITS

dBm

30%

AMPS RF characteristics
PARAMETER
Po

Output power

Power gain
Power-added efficiency. (PAE)

TEST CONDITION
Class NAB.
IDSQ = 900 mA,
f = 836 Mhz.

MIN

VDS = 3.6 V.
PI = 17 dBm.
Fixed test circuit

TYP

MAX

UNITS

dBm

53%

GSM RF characteristics
PARAMETER
Po

Output power

Power gain
Power-added efficiency. (PAE)

TEST CONDITION
Class AB/B.
IDSQ = 900 mA,
f = 900 Mhz.

VDS =4.8 V.
P, = 21 dBm.
Fixed test circuit

~TEXAS

INSTRUMENTS
7-48

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

TYP

MAX

UNITS

dBm

53%

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

TYPICAL CHARACTERISTICS
POWER DERATING CURVE
5

roc.

'\~

'iii

...
CIl

0==

Il.

iii

;§
I

oJ-

"'"

150

100

200 '

250

TC - Case Temperature - DC

Figure 1

:>
w
a::

a..

DRAIN-SOURCE VOLTAGE

...

DRAIN CURRENT

vs
8

VGS= OV
7

u
r::
CI)

in
'C
CI)

Gain (dB)

20
15

'C
'C

D..
I
W

O~~~~--~--~--~--~--~--~--~--~--~~O

"tJ

PI-Input Power - dBm

Figure 3. Typical RF Performance for GSM

c
o

4o.---------------------------------------------,6o
1=836MHz
55
Vos 4.8 V
36

-t

"tJ
:D

~"":';""'---I

m
:S
m

50
45

CI)

'C
CI)

25
20

15
8

5
~~--~~--~~--~~--~~~~--~~--~~~o

PI-Input Power - dBm

Figure 4. Typical RF Performance for NADC

~TEXAS

7-50

>u
r::

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

'C
'C

1
CI)

:::o

D..
I
W

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

TYPICAL CHARACTERISTICS
40
36

60
f = 836 MHz

VOS =3.6 V

Ii
OJ

._
-::l
C. c
ca

(!J

.. 3:
~ 0

0..

(!J

50
45

eft.

0..

0
5

CIl

'C
CIl

'C
'C

"!
CIl

3:
0

0..

5
0
7

PI - Input Power - dBm

-w
>

Figure 5. Typical RF Performance for AMPS

a:
c..

:::::»
C

oa:

c..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-51

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

TYPICAL CHARACTERISTICS

VOS 3.6 V
lOS 1 ATyp

-1

"'C
::rJ

o
C
c

Frequency
(MHz)

S[1,1]
Mag

S[1,1]
Ang (deg)

S[2,1]
Mag

S[2,1]
Ang (deg)

S[1,2]
Mag

S[1,2]
Ang (deg)

S[2,2]
Mag

S[2,2]
Ang (deg)

700

0.971

-164.9

2.660

0.011

0.896

170.9

("')

800

0.971

-169.6

2.334

85.5

0.011

-1.1

0.897

169.4

-4
"'C
::rJ

900

0.971

-173.5

2.077

82.3

0.011

-3.8

0.898

167.9

1000

0.971

-177

1.869

79.4

0.011

-6.3

0.898

166.4

1100

0.971

179.9

1.696

76.7

0.011

-8.6

0.899

164.9

1200

0.971

177.1

1.552

74.1

0.011

-10.7

0.900

163.5

1300

0.971

174.4

1.428

71.6

0.011

-12.8

0.900

162

1400

0.971

172

1.321

69.2

0.011

-14.7

0.901

160.6

1500

0.971

169.6

1.228

66.9

0.011

-16.6

0.902

159.2

1600

0.971

167.4

1.146

64.6

0.011

-18.5

0.902

157.8

1700

0.971

165.3

1.074

62.4

0.011

-20.3

0.903

156.4

1800

0.971

163.3

1.009

60.2

0.011

-22

0.903

155

1900

0.972

161.3

0.950

58.1

0.010

-23.7

0.904

153.6

2000

0.972

159.4

0.897

0.010

-25.4

0.905

152.2

m
<

Figure 6. Typical Small Signal Scattering Parameters

~TEXAS

7-52

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

APPLICATION INFORMATION
VDS

I I

14-~--rI--i-I-;~1If- 12

w=40 mils
11 = 12 = 300 mils
Turns 2.25
Space = 5 mils

~
w = 20 mils
1=140mils

w =20 mils
1=230mils

5011 Line

5011 Line
w=20mils

RF out

3:
->w
w
a:
a.

....

Board Material Specifications:
Type FR4 j cr = 4.3 j h = 12 mils
COMPONENT
DESIGNATION
C1

TYPICAL VALUE
(GSM)
1000 pF

oa:

FUNCTION

DC blocking capacitor for RF input

1.6 pF

Matching capacitor

5.6 pF

Matching capacitor

24pF

Matching capacitor

7.5pF

Matching capacitor

2.7pF

Matching capacitor

1000 pF

DC blocking capacitor for RF output
Stability network capaCitor

100pF

Power supply decoupling capacitor

C10

1000 pF

Stability network capaCitor

C11

20pF

Power supply decoupling capacitor

12nH

RF choke

311

Stability network resistor (optional)

10011

Stability network resistor

Figure 7. Application/Demonstration Board Schematic for GSM

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

7-53

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

APPLICATION INFORMATION
VDS

-=-

II
II

-=12
w=40mils
11 = 12 = 300 mils
Turns = 2.25
Space=5 mils

w=20mils
1= 300 mils

w = 20 mils
I = 82 mils

50 Q Line

'"t:J
:D

RFin

-1
C1

c:
o

w=~20 mils
1= 800 mils

-I
'"t:J
:D

Board Material Specifications:
Type FR4 ; Er = 4.3 ; h = 12 mils
COMPONENT
DESIGNATION

TYPICAL VALUE
(NADC)

FUNCTION

1000 pF

DC blocking capacitor for RF input

4.7pF

Matching capacitor

30pF

Matching capacitor

7.5 pF

Matching capacitor

2.5 pF

Matching capacitor

1000 pF

DC blocking capacitor for RF output

100 pF

Stability network capacitor

100pF

Power supply decoupling capacitor

1000 pF

Stability network capacitor

Cl0

20pF

Power supply decoupling capacitor

12 nH

RF choke

Stability network resistor (optional)

lOOn

Stability network resistor

Figure 8. Application/Demonstration Board Schematic for NADC

~TEXAS

INSTRUMENTS
7-54

f- RFout

m
=:=
m

50 n Line
w = 20 mils

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF7000
POWER GaAs MESFET
SLWS027 - JULY 1996

APPLICATION INFORMATION
VDS

-=-

I I

-=12
w=40 mils
11 = 12 = 300 mils
Turn:: = 2.25
Space = 5 mils

w=20 mils
I =365 mils

500 Line
w=20mils

500 Line
RFin

--1

3:
w

C1
R2

w=20 mils
I =800 mils

II:

I-

Board Material Specifications:
Type FR4; Er = 4.3; h = 12 mils
COMPONENT
DESIGNATION

TYPICAL VALUE
(AMPS)

oII:

FUNCTION

1000 pF

DC blocking capacitor for RF input

3.3pF

Matching capacitor

30pF

Matching capacitor

7.5 pF

Matching capacitor

1000 pF

DC blocking capacitor for RF output

100 pF

Stability network capacitor

100 pF

Power supply decoupling capacitor

1000 pF

Stability network capacitor

20 pF

Power supply decoupling capacitor

12 nH

RF choke

Stability network resistor (optional)

1000

Stability network resistor

Figure 9. Application/Demonstration Board Schematic for AMPS

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-55

7-56

TRF80'IO
gOO-MHz RF TRANSMIT DRIVER
SLWS031-JULY 1996

• Operates from 3.6-V and 4.S-V Supplies for
AMPS/NADC and GSM Applications
Respectively
• Unconditionally Stable
• Wide UHF Frequency Range - SOO MHz to
1000 MHz
8 21 dBm and 22 dBm Power Outputs in
AMPS/NADC and GSM Applications
Respectively
• Linear Ramp Control
o Transmit Enable/Disable Control

PWP PACKAGE
(TOP VIEW)

GND
GND
RFIN
GND
GND

VPC
GND
GND

VBB
GND

2
3
4
5
6
7

20
19
18

9
10

17
16
15
14
13
12
11

GND
GND
RFOUT
GND
GND
TXEN
GND

Vee
Vee
GND

• Advanced BiCMOS Processing Technology
for Low-Power Consumption, High
Efficiency, and Highly Linear Operation
• Minimum of External Components
Required for Operation
o Surface-Mount Thermally-Enhanced
Package for Extremely Small Circuit
Footprint

3:
w

description
The TRF8010 is an RF transmit driver amplifier designed for gOO-MHz digital, analog, and dual-mode
communication applications. It consists of a 2-stage driver amplifier and a linear ramp controller for burst control
in TDMA (time division multiple access) applications. Very few external components are required for operation.
The TRF801 0 amplifies the RF signal from the preceding modulator and upconverter stages in an RF section
of a transmitter to a level sufficient to drive a final RF power output device. The output impedance of RFOUT
is approximately 50 n. But, since this terminal is connected to an open-collector output device, minimal external
matching is required.
The device is enabled when the TXEN input is held high. A power-control signal applied to the VPC input can
be used to ramp the RF output power up or down to meet ramp and spurious emission specifications in TDMA
systems. The power control signal causes a linear change in output power as the voltage applied to VPC varies
between 0 V and 3 V. With the RF input power applied to RFIN at 0 dBm and TXEN high, adjusting VPC from
o V to 3 V linearly increases the output power from a maximum of -1 0 dBm at VPC = 0 V to the output power
appropriate for the application (21 dBm for AMPS/NADC [Advanced Mobile Phone Service/North American
Digital Cellular] operation or 22 dBm for GSM [Global Systems for Mobile Communications] operation). Forward
isolation with the RF input power applied to RFIN at 0 dBm, VPC =0 V, and TXEN low is a minimum of 47 dB.

These devices have limited built-in ESD protection. The leads should be shorted together orthe device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

PRODUCT PREVIEW information concerns products In the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-57

:>
w
a:
a..

I-

:::l
C

o0:
a..

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031-JULY 1996

description (continued)
The TRF801 0 is available in a small, surface-mount, thermally-enhanced TSSOP 20-pin (PWP) package, and
is characterized for operation from -25°C to 85°C. The PWP package has a solderable thermal pad that can
be used to improve the package thermal performance by bonding the pad to an external thermal plane. The pad
also acts as a low-inductance electrical path to ground, and for the TRF801 0, should be electrically connected
to the PCB ground plane as a continuation of the regular package pins that are designated GND.

functional block diagram
18

3
RFIN - - - - - - - - - 1

RFOUT

15
TXEN------------;

"'C

6
VPC----I

::c
o
c
c:
o

Bias/Band Gap
Reference

Linear Ramp
Control

12,13

vcc VBB

Terminal Functions

-f
""C

TERMINAL
NAME

:c
m
!5
m
=E

GND

NO.

DESCRIPTION

I/O

Analog ground for all internal analog circuits. All Signals are referenced to this terminal.

1,2,4,5, 7, 8,
10,11,14,16,
17,19,20

RFIN

RF input. This terminal accepts signals between 800 MHz and 1000 MHz.

RFOUT

RF output. This is an open-collector output and requires a decoupled connection to VCC for
operation.

TXEN

Transmit enable input (digital). A logic high applied to TXEN enables the device output.

VSS

VCC

12, 13

VPC

Control section supply voltage
First stage bias
I

Output-power control input (analog). A signal between a v and 3 V applied to VPC adjusts
output power between -10 dSm and the maximum output power appropriate for the application.

~TEXAS

INSTRUMENTS
7-58

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031 - JULY 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, Vcc (see Note 1) .............................................. -0.6 V to 5.6 V
Input voltage range at TXEN, VPC .................................................. -0.6 V to 5.6 V
Input power at RFIN ..................................................................... 10 dBm
Continuous total power dissipation at TA = 25°C ............................ , ................... 1 W
Operating junction temperature, T J ......................................................... 150°C
Operating free-air temperature range, TA ............................................. -25°C to 85°C
Storage temperature range, Tstg .................................................... -30°C to 100°C

recommended operating conditions
MIN
Supply voltage, VCC (see Note 2)

NOM

MAX

High-level input voltage at TXEN, VIH

V
V

VCC -0.8

Low-level input voltage, TXEN, VIL
Operating free-air temperature, TA

UNIT

-25

0.8

°c

->w

electrical characteristics over full range of operating conditions
supply current, Vee

=3.6 V and Vee =4.8 V

PARAMETER

ICC

Supply current from VCC

TEST CONDITIONS

MIN

TYPt

MAX

UNIT

I-

Operating at
maximum power out

TXEN high, VPC = 3 V

170

Operating at minimum
power out

TXEN high, VPC = 0 V

Power down

TXEN low, VPC = 0 V

0.05

t Typical values are at TA = 25°C.

AMPS/NADC operation, Vee

PARAMETER

TEST CONDITIONS

Operating frequency range
PI = 0 dBm

Gain (small signal)

PI = -20 dBm

Power added efficiency (PAE)

PI = 0 dBm

Input return loss (internally matched)

Harmonics (2fO, 3fO)

849

Padj (60 kHz)

TXEN low

MHz
dBm

dB
dB

45 MHz offset at 21 dBm Po

-92

dBm

Po =21 dBm

-30

dBc

-30
PI =-2 dBm,
BW= 24.3 kHz

-55

dBc

-65

Padj (90 kHz)
TXEN high

UNIT

Padj (30 kHz)

tTypical values are at TA

MAX

Noise power in 30 kHz channel

Output power

TYPt

24%

Output return loss (externally matched, small signal)

PI = 0 dBm,

VPC = 0 V

-10
-47

dBm

=25°C.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

::l
C

824

Output power

MIN

=3.6 V, TXEN high, VPC =3 V (unless otherwise noted)

Adjacent channel leakage power

NOTE 2: Voltage values are with respect to GND.

7-59

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031 -JULY 1996

GSM operation, Vee

=4.8 V, TXEN high, VPC =3 V (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

Extended GSM operating frequency range
Po

TYP

870
22

dBm

Gain (small signal)

PI =-20 dBm,
pulsed with a pulse width of 577 Jls,
and 1:8 duty cycle

Power added efficiency (PAE)

PI = 0 dBm,
pulsed with a pulse width of 577 Jls,
and 1:8 duty cycle

25%

d Phase shift

d Po = 1dB for Po 21 to 22 dBm

Harmonics (2fO, 3fO)

Po = 22 dBm

Noise power in 30 kHz bandwidth

o
C

-I
-C

m
S

20 MHz above fO
10 MHz above fO
TXEN high

Output power

2.5

deg

TXEN low

Po = 22 dBm

-30

dBc

-89

dBm

-77
VPC = OV

PI = 0 dBm,

dBm
-10
-47

dBm

stability, AMPS/NADC and GSM operation
PARAMETER

MHz

Output power

Input return loss (internally matched)

UNIT

925

PI = 0 dBm,
pulsed with a pulse width of 577 Jls,
and 1:8 duty cycle

Output return loss
(externally matched, small signal)

-c

MAX

TEST CONDITIONS
Output VSWRt < 6: 1 all phases,
VCC < 7.5 V,
PI = 0 dBm,
PO:$ 22 dBm

Stability

MIN

TYP

MAX

UNIT

No parasitic oscillations
(all spurious < -70 dBc)

t VSWR = voltage standing wave ratio.

switching characteristics
AMPS/NADC and GSM operation, Vee' = 3.6 Vor 4.8 V, TA = 25°C
PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

ton

Switching time, RF output OFF to ON

TXEN = high, VPC step 0 V to 3 V

Jls

toff

Switching time, RF output ON to OFF

TXEN = high, VPC step 3 V to 0 V

Jls

~TEXAS

INSTRUMENTS
7-60

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031-JULY 1996

APPLICATION INFORMATION
A typical application example for AMPS/NADC cellular telephone systems is shown in Figure 1.
In all cases, a capacitor must be connected from the positive supply to ground as close to the IC pins as possible
for power supply bypassing. A dc-blocking capacitor is also required on the output RF terminal.
Board Material:
Type FR4, Er = 4.3, h = 12 mils

20
GND

GND
-::-

50 n line,
RFINPUT w=20 mils

19
GND

-::-

3
4

-::-

RFIN

RFOUT

GND

•

7
-::-

-::-

15
VPC

TXEN

GND

VCC

1= 220 mils,
W= 20 mils

VCC

VBB
10

GND

GND
c4D

-::-

GND
TRF8010

w=20mils

-::-

16 -::-

RFOUTPUT

GND
-::-

50 n line,
w=20 mils

GND

-::-

I-

-::-

:::l
C

+
VCC

Figure 1. Typical AMPS/NADC Cellular Telephone Application

external component selection
COMPONENT
DESIGNATION

TYPICAL VALUE
(AMPS/NADC)

3.3pF

Output impedance matching capacitor

100pF

DC-blocking capacitor for RF output

100pF

Matching capacitor

1000 pF

Power supply decoupling capacitor

5.7 nH

Output impedance-matching inductor

100nH

DC bias/RF choke

FUNCTION

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-61

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031 - JULY 1996

APPLICATION INFORMATION
typical RF performance curves
30~------------------------------------------------~

28
26p-------_______

24
22

20
18

~!g

.e-

·iii
~
~ ~

~ 0.:~

0.:

Po (dBm)

16
14
12
10
6
4

"'C

PAE (%)

14
12
10
8
6

f 836 MHz
TXEN 2.8 V
VCC = 3.6 V
. VPC=3 V

O~~--~--~~--~--~~~~--~--~~--~--~~--~

-10

-8

-6

-2

-4

PI - Input Power - dBm

Figure 2. Typical Po/Gain/PAE vs PI Curves for AMPS

-I

25~------------------------------------------------~

"'C

-:J

I
I:
Co ._
-:J ~
10

o.. ..Ql
Ql

o==

0.:

0
0.:
I

I~
0

0.:

f 836 MHz
TXEN =2.8 V
VCC=3.6 V
PI =OdBm

"I "
In

o
-5
-10

-15
-20

-25
-30~~

0.4

0.8

1.2

1.6

2.4

VPc-V

Figure 3. Typical Po/Gain vs VPC Curve for AMPS

~TEXAS

7-62

30
28
26
24
22
20
18
16

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2.8

4
2
0

I:
Ql

·0

E
w

"
"«"

0==
0.:

I
W

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031-JULY 1996

APPLICATION INFORMATION
A typical application example for GSM cellular telephone systems is shown in Figure 4.
In all cases, a capacitor must be connected from the positive supply to ground as close to the Ie pins as possible
for power supply bypassing. A dc-blocking capacitor is also required on the output RF terminal.
Board Material:
Type FR4, Er = 4.3, h = 12 mils

20
GND

GND

-=
50 n line,
RF INPUT w=20 mils

-=
3
4

-=
-=

19
GND

GND

RFIN

RFOUT

GND

•

-=
-=
R1

VPC

TXEN

GND

VCC

VBB

Vcc

3:
->W
W

14
13

9
10

GND

GND
c4D

w=20 mils

TRF8010
6

RFOUTPUT

GND

50 n line,
w=20 mils

-=
18

I =220 mils,
w=20mils

I-=

II:

c..

I-

::J
C

VCC

II:

Figure 4. Typical GSM Cellular Telephone Application

c..

external component selection
COMPONENT
DESIGNATION

TYPICAL VALUE
(GSM)

FUNCTION

3.3 pF

Output impedance matching capacitor

100pF

DC-blocking capacitor for RF output

100pF

Matching capacitor

1000 pF

Power supply decoupling capacitor

6.8 nH

Output impedance-matching inductor

100nH

DC bias/RF choke

180n

Bias supply resistor

•
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7-63

TRF8010
gOO-MHz RF TRANSMIT DRIVER
SLWS031-JULY 1996

APPLICATION INFORMATION
typical RF performance curves
30

30
28

28
26
24

m m
"C

..!.

cIU
.-

18
16

o ..

::o a..::0

12
10

14
12
10

CI)

22
20

20
18
14

a..

I
C)

a..0

8
6
4
2

"t'J

8
6

f=900MHz
TXEN =4V
VCC=4.8V
VPC=3V

-10

c
c:
o

-8

-6

-4

-2

4
2
0
2

PI - Input Power - dBm

Figure 5. Typical Po/Gain/PAE vs PI Curves for GSM

-I

30~------------------------------------------------~

"t'J

m
:S
m

f = 900 MHz
TXEN =4 V
VCC=4.8 V
PI=OdBm

!g m
I
-~

Co .-

-~ C)
IU

..
CI)

CI)
::

o a..
a.. I
IC)

a..0

-20
-25~~--~--~~--~--~~~~--~--~~--~--~~--~

0.4

0.8

1.2

1.6

2.4

VPC-V

Figure 6. Typical Po/Gain vs VPC Curve for GSM

•
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

2.8

'#.
I

cCI)

E
w
"C
CI)

"C
"C
c(
~

a..
I
W

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

•

Charge Pump Provides Negative Gate Bias
for Depletion-Mode GaAs Power Amplifiers

•

Buffered Clock Output to Drive Additional
External Charge Pump
135-mQ High-Side Switch Controls Supply
Voltage to the GaAs Power Amplifier
Power-Good Circuitry Prevents High-Side
Switch Turn-on Until Negative Gate Bias is
Present

•
o

•

Charge Pump Can Be Driven From the
Internal Oscillator or An External Clock

•
•

1O-~A Maximum Standby Current
Low-Profile (1.2-mm Max Height), 20-Pin
TSSOP Package

PW PACKAGE
(TOP VIEW)

GATE_BIAS
Vee

C1C1+
BATT_IN
BATT_IN
BATT_IN
PGP
PG
GND

10
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VDD

ClK
BClK
GND
BATT_OUT
BATT_OUT
BATT_OUT
SW_EN
OSC_EN
EN

description
The TPS91 03 is a highly integrated power supply for depletion-mode GaAs power amplifiers (PA) in cellular
handsets and other wireless communications equipment. Functional integration and low-profile packaging
combine to minimize circuit-board area and component height requirements. The device includes: a p-channel
MOSFET configured as a high-side switch to control the application of power to the PA; a driver for the high-side
switch with a logic-compatible input; a charge pump to provide negative gate-bias voltage; and logic to prevent
turn-on of the high-side switch until gate bias is present. The high-side switch has a typical on-state resistance
of 135 mQ.
The TPS91 03 is available in a 20-pin thin shrink small-outline package (TSSOP) or in chip form. Contact factory
for die sales. The device operates over a junction temperature range of -25°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICE
TA

TSSOP
(PW)

-25°e to 85°e

TPS9103PWLE

CHIP FORM
(Y)
TPS9103Y

The PW package is only available left-end taped and reeled
(indicated by the LE suffix on the device type).

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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

functional block diagram

.; .,l6'~7

BATT_IN ..,;5;.:."

"";"-/_-------------4IrTI?""'" :/

14, 15, 16

BATT_OUT

VCC
VCC

~2~__________________~

BCLK . . ,;.1. :. . 8_ _<

r-r-__~

VDD

~2~O'-__________

~1~1r.--________

OSC_EN

r-r-+-__________~

C1+
C1-

GND

~8~

Comparator

____________~. .__~

4
3

Inverting
Charge
Pump

O.6R

~TEXAS

INSTRUMENTS
7-66

__________~9 PG

e-1-________~~-------------------1=9 CLK
PG
R

PGP

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

TPS9103Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS91 03. Thermal compression or
ultrasonic bonding may be used on the doped-aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform. Contact factory for die sales.
BONDING PAD ASSIGNMENTS

VCC VDD

4
C1+
3
C1BATT_IN 5, 6, 7
PGP

9
11

EN
OSC_EN

GATE_BIAS
14,15,16
BATT_OUT
TPS9103Y

12
13

SW_EN
CLK

BCLK
10,17
GND

CHIP THICKNESS: 15 TYPICAL
BONDING PADS: 4 x 4 MINIMUM
TJ max

=150°C

TOLERANCES ARE ±10%.
ALL DIMENSIONS ARE IN MILS.

I..

111111111111111111111111111111111111111111111111111111111111111111111111111111111111

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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

Terminal Functions
TERMINAL
NAME

DESCRIPTION

NO.

GATE_BIAS

Negative gate-bias output voltage

VCC

logic supply voltage

C1-

External capacitor connection (inverting charge pump)

C1+

External capacitor connection (inverting charge pump)

BATT_IN

High-side switch input voltage

BATT_IN

High-side switch input voltage

BATT_IN

High-side switch input voltage

PGP

Program input for power-good threshold

Power-good output

GNO

Ground

Chip-enable input

OSC_EN

Oscillator-enable input

SW_EN

High-side switch enable input

BATT_OUT

High-side switch output voltage

BATT_OUT

High-side switch output voltage

BATT_OUT

High-side switch output voltage

GND

Ground

BClK

Buffered clock output

ClK

Clock (bidirectional)

VOO

Charge-pump supply voltage

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iPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

detailed description
high-side switch and driver (BATT_IN, BATT_OUT, SW_EN)
The high-side switch is a p-channel MOSFET with a maximum on-state resistance of 180 mQ
(VI(BATT_IN) = 6 V and Vee = 3.3 V). The driver pulls the gate of the high-side switch to GATE_BIAS instead of
ground to reduce the MOSFET on-state resistance. Gate breakdown considerations limit the voltage between
BATT_IN and GATE_BIAS to 15 V. Extremely fast switching times are not required in this application, and the
high-side switch/driver is designed to provide 21ls maximum switching times with minimum power consumption.
The GaAs depletion-mode MOSFETs in the PA are protected from damage at power-up by internal logic that
inhibits the driver until negative gate bias is available. The control input SW_EN is compatible with 3-V and 5-V
CMOS logic; a logic-high input turns the high-side switch on.

oscillator (OSC_EN, ClK)
The internal oscillator drives the charge pump at 50 kHz with a nominal duty cycle of 50% when both the EN
and OSC EN inputs are logic lows. ClK outputs the internal oscillator signal (no buffer). A logic-high input to
OSC_EN disables the internal oscillator and allows the charge pump to operate from an external clock
connected to ClK. When an external clock with negative overshoot is applied, a Schottky diode must be added
to limit the amplitude of the overshoot.

charge pump (GATE_BIAS, C1+, C1-)
The inverting charge pump generates the negative gate-bias voltage output at GATE_BIAS.

chip enable (EN)
A logic high on EN shuts down the internal functions of the TPS91 03 and turns the bias system off, reducing
the supply current to less than 10 1lA. A low input on EN causes normal operation to resume.

power good (PG, PGP)
PG output is logic high when GATE_BIAS is in regulation. PG output is logic low when GATE_BIAS is not in
regulation. The high-side switch is disabled and PG is forced to logic low whenever the magnitude of
GATE_BIAS is less than 0.6 x Voo. A modified threshold for the power-good function can be achieved by
programming PGP with an external resistor.

undervoltage lockout for Vee and Voo (UVLO and UVDlO)
Undervoltage lockout prevents operation at supply voltages too low for proper operation. When UVlO or
UVDlO is active, all power-switch drives are forced to the off state and bias is removed from unneeded
functions. Hysteresis is provided to minimize cycling on and off because of source impedance loading when the
supply voltage is close to the threshold.

buffered clock output (BClK)
The buffered clock output is a driver for an external charge pump. When the optional external charge pump is
not needed, BClK should be left unconnected. For more details, see the application section.

supply input for inverting charge pump (Voo)
Voo is the supply voltage for the inverting charge pump. In normal operation, Voo is connected to Vee. If the
negative gate-bias needs to be larger than Vee (Le., more negative), then a higher voltage supply needs to be
connected to Voo. This can be supplied from an external charge pump driven from BClK.

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7-69

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

DISSIPATION RATING TABLE
PACKAGE
PW

DERATING FACTOR
ABOVE TA 25°C

TA:>25°C
POWER RATING

TA 85°C
POWER RATING

353mW

255mW

6.5 mW/oC

645mW

Maximum values are calculated using a derating factor based on RSJA
mounted on an FR4 board with no special thermal considerations.

TA 70°C
POWER RATING

= 154°CIW for the package. These devices are

700

E
I

.2
iii

'iii

"'-

600

PW Package
RSJA 154°CIW

500

If)

C
~

400

::J

300

~ i""-...
...........

(.J

E
~

.;c

200

111

100

o
25

TA - Free-Air Temperature - °C

Figure 1. Dissipation vs Free-Air Temperature

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
High-side switch input voltage range, BATT_IN (see Note 1) ............................ -0.3 V to 15 V
Supply voltage range, Vee, VDD ..................................................... -0.3 V to 7 V
Differential voltage, IBATT_INI-IGATE_BIASI .................................................. 15 V
Input voltage range, SW_EN, EN, ClK, OSC_EN, PG .......................... -0.3 V to Vee + 0.3 V
GATE_BIAS ............................................................................. -5.5 V
Output current, PG ........................................................................ 5 rnA
Output current, BClK ..................................................................... 50 rnA
Output current, GATE_BIAS ............................................................... 10 rnA
Output current, BATT_OUT .................................................................. 2 A
Peak output current, BATT_OUT .............................................................. 4 A
Maximum external clock frequency, ClK ................................................... 100 kHz
Continuous total power dissipation ..................................... See Dissipation Rating Table
Junction temperature range, T J .................................................... -25°C to 150°C
Storage temperature range, Tstg ................................................... -65°C to 150°C

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to device GND.
2. Differential voltage calculated: IVlmaxl + IGATE_BIASI

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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

recommended operating conditions
MIN

Input voltage, BATT_IN

NOM

MAX

UNIT

Supply voltage, VCC, VDD

2.7

5.5

Output voltage, GATE_BIAS, Vo

-2

-5

Continuous output current, GATE_BIAS

Continuous output current, BATT_OUT

Charge-pump capacitor value at C 1+/C 1-

2
0.33

External clock frequency, ClK

High-level input voltage, VIH

----

SW_EN,EN,OSC_EN,ClK

0.8

Input current, II
Operating junction temperature, T J

kHz
V

low-level input voltage, Vil

A
JlF

-1

JlA

-25

125

°c

electrical characteristics over recommended operating junction temperature range,
BATT_IN =6 V, VCC =VOO =3.3 V, IO(BATT_OUT) =0.5 A, IO(GATE_BIAS) =2 rnA,
EN =OSC_EN =0 V, SW_EN =Vcc, C1 =0.331lF (unless otherwise noted)
charge pump
PARAMETER

TEST CONDITIONS

MIN

Output voltage

-3

Output resistance

TYP

-3.10

MAX

-3.3

UNIT

V
a

high-side switch
PARAMETER

TEST CONDITIONS

MIN

Dran-to-source on-state resistance

leakage current

TYP

135

TA = 25°C

MAX

UNIT

180
210

TA = -25°C to 85°C

TA = 25°C,

160

VI(BATT IN) = 3 V

220

TA = -25°C to 85°C,

BATT_IN = 3 V

TA = 25°C,

VI(BATT IN) = 9 V,

SW_EN = 0 V

TA = 85°C,

VI(BATT IN) = 9 V,

SW_EN =0 V

260
JlA

Delay to high-level output

SW_EN from 0 to VCC

0.2

Jls

Delay to low-level output

SW_EN from VCC to 0

0.9

JlS

oscillator
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

Frequency

VCC=2.7Vt05.5V

Duty cycle

VCC=2.7Vt05.5V

40%

50%

60%

UNIT

kHz

buffered clock output (BCLK)
PARAMETER

TEST CONDITIONS

MIN

Output resistance

TYP

MAX

High-level output voltage

I(BClK) = 30 mA

Low-level output voltage

I(BCLK) = 30 mA

UNIT

a
V

VCC -0.3
0.3

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7-71

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

power good (PG)
PARAMETER

TEST CONDITIONS

Threshold voltage

VOO = 2.7 Vto 5.5 V

On-state voltage

IO(PG) = 500 !-lA,

Vee = 2.7 V to 5.5 V

Off-state voltage

IO(PG) =-500 !-lA,

Vee = 2.7 V to 5.5 V

MIN

TYP

MAX

0. 6OxVOO

UNIT
V

0.3
Vee- 0 .3

V
V

Hysteresis

130

power good (PGP)
PARAMETER

TEST CONDITIONS

Input impedance

MIN

TYP

MAX

TYP

MAX

undervoltage lockout (UVLO + UVDLO)
PARAMETER
Start threshold voltage

TEST CONDITIONS
Vee increasing

MIN
2.4

Hysteresis

2.7
130

UNIT
V
mV

supply current (Icc and 100)
PARAMETER

TEST CONDITIONS

Standby mode

EN = Vee'

Undervoltage lockout

Vee = VOO < 2.3 V

Operating mode

No load

~TEXAS

INSTRUMENTS
7-72

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

MIN

TYP

MAX

UNIT

IlA

300

500

IlA

TPS9'I03
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

PARAMETER MEASUREMENT INFORMATION

-=-

Vee

---Q>----Q-~...----1

BATT_IN

BATT_OUT

BATT_IN

BATT_OUT

BATT_IN

BATT_OUT

Vee
Voo

GATE_BIAS

e1+

.....Vee

>
I

III
CI

.l!!

"SCo
"S

r::

III

-1

-2

-3

lrT

t-Time-ms

Figure 3. GATE_BIAS Output Voltage Rise Time

•
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7-73

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A - JULY 1996

PARAMETER MEASUREMENT INFORMATION

10 - GATE_BIAS =5 rnA
Voo =Vee =5 V

. . . . . . . . . . . . . . . . . . . . . . . . . . ···4·········.··

. . . . . . . . . . . . ...

. . . . . . +1..........................
. . . . ..
..........................
•.1..

....

••••

••••••••••••

0.00.0

:t.....

••••••••

'f'

;

.... ; ...
5

•

••

01.
I

••••

I ..

20 niV/dlv

•..

••••

t-Tirne-Ils

Figure 4. Ripple on GATE_BIAS

~TEXAS

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.0

••••

:
•••

....

f ••••

TPS9'I03
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
FIGURE
rOS(on)

Static drain-source on-state resistance

Fosc

Oscillator frequency

Output voltage

VIT

Threshold voltage
Supply current (ICC + 100)

STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs Gate-source voltage, dc

vs Temperature

vs Supply voltage

vs Temperature

vs Output current

vs ClK frequency

vs Temperature

vs Supply voltage

vs Temperature

HIGH-SIDE SWITCH
STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs
GATE-SOURCE VOLTAGE,
E
I

de (VO(GATE_BIAS) -VI(BATI_IN»

190

r:::

180

CI)

'iii
170

160

150

CIl

140

(/)

C::

130

:;u
en

110

100

'2
o
~

L..---

120

C::

160

CIl

ca
en

.....,..,

C'CI

'lii

'iii

180

CIl

CIl
C'CI

TEMPERATURE

-12

.-""

CIl

ca
en

140

C::

CIl

120

(/)

C::

100

ca
en

'2
-11

-10

-9

-8

-7

-6

enco

...

60
-50

-25

V GS - Gate-Source Voltage,
dc (VO(GATE_BIAS) -VI(BATI_IN»

Figure 5

100

125

T - Temperature _oC

Figure 6

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TPS9"103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

TYPICAL CHARACTERISTICS

OSCillATOR FREQUENCY

SUPPLY VOLTAGE

TEMPERATURE

49.5

..lI::

>c
CIl
::s

>u
c
CIl
::s

.........

f!
u.

'uUI
0

..lI::

46
2.5

3.5

48.5

f!
u.

4.5

0
~
'uUI

0
I

47.5

5.5

75
0
25
50
T - Temperature - °e

-25

Vee - Supply Voltage - V

GATE BIAS
OUTPUT VOLTAGE

OUTPUT CURRENT

ClK FREQUENCY

-3

-1

-3.05

>
I

Vice = 2.7V -

-2

+-:::::

.--

'SCo
'S

-3

-4

I -f--

Vee = 3.3 V

I--- +--

-?
L---

-5 ....-

-6

>
~ -3.1
Cl

'S - 3.15

i'-.

I I I

o
I

Vee= 5 V

'"r--.....l""'-t--

t--

-3.2

-?
-3.25

-3.3
2

3
4
5
6
7
8
10 - Output Current - mA

~TEXAS

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f - eLK Frequency - kHz

Figure 10

Figure 9

7-76

125

Figure 8

Figure 7

CIl
Cl

100

TPS9'I03
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

TYPICAL CHARACTERISTICS

UNDERVOLTAGE LOCKOUT (Vee. Voo)
THRESHOLD VOLTAGE

SUPPLY CURRENT (lee + 100)

TEMPERATURE

SUPPLY VOLTAGE

2.65

450

2.63

-.........

(1)

2.61

...........

350

,,/

"0
I/)

"E
~
:l

2.59

300

!::

C
E
+

..c

400

::1.
I

..c

2.57

2,55
-50

Co
:l
CJ)

-25

0
25
50
T - Temperature -

100

250

200
2.7

125

3.2

3.7
4.2
4.7
Supply Voltage - V

°e

Figure 11

5.2

5.7

Figure 12
SUPPLY CURRENT (lee + 100)

vs
TEMPERATURE
500

ii
Co

250

200
-50

-25

25
50
T - Temperature -

100

125

°e

Figure 13

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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

THERMAL INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch packages requires special attention to power
dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection
surfaces, and the presence of other heat-generating components affect the power-dissipation limits of a given
component.
Three basic approaches for enhancing thermal performance are listed below:
e

Improving the power-dissipation capability of the PWB design

•

Improving the thermal coupling of the component to the PWB

•

Introducing airflow in to the system

Using the given ROJA for this IC, the maximum power dissipation can be calculated with the equation:
TJmax - T A
P Omax = ----"--:R=-----'-'

OJA
For the TPS91 03, the power dissipation is in the PMOSFET. To calculate the power, use: 12 x R where I is the
current through the device and R is the internal resistance as shown in the electrical characteristics table.
For a VI of 6 V, the resistance at 85°C is 0.210 Q. At a current of 2 A, the peak power dissipation is:
Po = 22

x 0.210

= 0.84 W

Assuming a duty cycle of 1/8 or 0.125, the average power is:
0.84 W x 0.125

= 0.105 W

The change in temperature is:
~T

= 0.105 W x 154°CIW = 16.2°C

and the junction temperature is:
T J = 85°C + 16.2°C =1 01.2°C

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TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

APPLICATION INFORMATION
introduction
Traditionally the RF power amplifier (PA) is powered directly from the battery, with a switching arrangement for
powering down when not in use. GaAs FET PAs require a negative bias voltage that must be present before
the supply is connected, or there is risk of destroying the FET. logic must be provided to ensure the presence
of the negative bias voltage.
A secondary charge pump is necessary for systems in which the supply voltage is insufficiently high - the
negative bias produced from the charge pump is inadequate. In mobile telephony a second charge pump
(regulated or unregulated) may also be needed, e.g. for varicap diodesNCOs and some preamplifiers. The
need for larger dynamic range or control-voltage range can become critical in certain applications.

the TPS91 03 approach
The TPS91 03 integrates a P-channel MOSFET high-side switch together with a selectable oscillator and charge
pump for the GaAs FET power-amplifier gate bias, which is monitored.
Complete precautions are taken to ensure that the PA supply is not enabled unless the gate bias is present while

Vee and Voo are also good. This protects the PA from inadvertent damage-without a major system size/cost
increase.
The bias regulation monitor is flexible, accommodating both fixed and programmable approaches. The fixed
resistors, provided internally, set the trip voltage to -0.6 x Voo. If Voo is 5 V, then the trip voltage is -3 V. Should
another value be preferred, it can be set by applying voltage divider to PGP. See the section "dimensioning the
external voltage divider" for more details.
The charge pump clock is also flexible. The on-chip oscillator runs at a nominal 50 kHz, or alternatively an
external oscillator can be connected to ClK. When an external clock is used, OSC_EN should be taken high
to disable the oscillator. When OSC_EN is low and the on-chip oscillator is used, ClK provides an unbuffered
clock output.
The circuit provides for a secondary charge pump driver. The buffered BClK output can be used (with four
external components) to provide a higher supply, both for those system functions that require it and for those
GaAs PAs that need a more negative bias than is made possible by inverting the existing supply. This is
facilitated by use of single-cell Li-ion batteries.
Figure 14 shows the TPS9103 in a typical application.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303. DALLAS, TEXAS 75265

7-79

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

APPLICATION INFORMATION
5

Battery
4 V to 8 V

XMIT

4
C2
0.33JlF

3
2

VCC
3.3V

+
C3

~.7 JlF

T-=-

C4
0.1 JlF

T-=11
12

BATT_IN

BATT_OUT

BATT_IN

BATT_OUT

BATT_IN

BATT_OUT

14
15

1--___- - - - - -

SW_EN
GATE_BIAS

Cl+

TSP9103
ClVCC

VDD

PGP

ClK

OSC_EN

BClK

9
8
19
18

GND

-=
Figure 14. Typical Application

~TEXAS

INSTRUMENTS
7-80

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PA Drain

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

APPLICATION INFORMATION

capacitors of the internal inverting charge pump (see Figure 15)
This charge pump inverts the voltage at Voo and provides a negative output voltage at GATE_BIAS.
TPS9103

Charge
Pump

T+

C-

Figure 15. Internal Inverting Charge Pump
The output capacitor C6 limits the voltage ripple at GATE_BIAS:
V

_ 'O(GATE_B'AS)
Ripple C6 x f

With a capacitor C6 of 4.7 JlF and an output current of 10 mA, the voltage ripple at GATE_BIAS is 42 mV.
The capacitor C2 can be calculated using an equivalent resistance method:
1
Requivalent = C2 x f

Using 0.33 JlF for C2, the equivalent resistance is:
Requivalent

1
0.33 [IF x 50 kHz

= 60.6

Add the internal resistance of the switches (35 Q) to get a total resistance seen by the current:
RTOTAL

+ 35 =

95 Q

With a total resistance of 95 nand 10 mA flowing through it, a voltage drop of 0.95 V occurs. With 5 V on Voo,
the output is -4.05 V with a 42 mV ripple.
The capacitors should have a low equivalent series resistance (ESR) to maintain low ripple and low noise.
Careful layout is required. In most instances it is advisable to add a small decoupling capacitor C5 close to the
GATE_BIAS. An additional 0.1-JlF capacitor at other locations may be necessary if the power amplifier is located
away from the TPS91 03.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-81

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

APPLICATION INFORMATION
dimensioning of the external charge pump
For systems in which the bias voltage requirement is not met by inverting the power rail, the BCLK output can
be used (with four passive components) to generate a higher Voo. The higher voltage is then inverted as before
to produce the bias voltage. This voltage is also available for other parts of the main circuitry (see Figure 16).
With the TPS91 03, an external charge pump could be used to increase the voltage at Voo, thereby deriving a
higher negative voltage at GATE_BIAS than would otherwise be available.

vce
01

Figure 16. External Charge Pump
When BCLK is low, node 1 charges up to Vee - Vdiode. When BCLK goes high, node 1 is 2 Vee - Vdiode. The
capacitor C8 charges up to 2 Vee - 2 Vdiode' This voltage can then be connected to Voo.
The magnitude of Vripple of Voo is determined by the value of C8. Capacitor value must be large enough that
the discharge during one period is not as great as the maximum voltage variation allowable. The discharge of
C8 depends on the load current.
C8 = IO(GATE_BIAS)
V ripple xf
With a supply voltage of Vee = 3.3 V, a maximum voltage variation (Vripple) of 2%
lec = 10 mA, the value of C8 is 3 1lF. A 4.7 IlF meets this requirement.

= 66 mV and a load of

The capacitance of C7 can be calculated using an equivalent resistance method:
1
Requivalent = C7 x f
Using 0.221lF for C7, the equivalent resistance is:
Requivalent

1
0.22 IlF x 50 kHz

90Q

Add the equivalent resistance to the internal resistance of the switch (10 Q):
RTOTAL =90 + 10 = 100 n
With a total resistance of 100 Q and with 10 mA flowing through it, a voltage drop of 1 V occurs. Thus with 3.3
Von Vee the output is 4.2 V with a 42-mV ripple.
Care must be taken that the maximum voltages are not exceeded when using BCLK as a charge pump (see
Figure 17).

~TEXAS

INSTRUMENTS
7-82

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
. SLVS131A-JULY1996

APPLICATION INFORMATION
5

Battery
4 Vtc 8 V

XMIT

4
C2
0.33 JlF

BATLIN

BATT_OUT

BATT_IN

BATT_OUT

BATT_IN

BATT_OUT

16
PA Gate-3 V

C1+

-=-

TSP9103
C1PGP

VCC

ClK
11

PA Drain

GATE_BIAS

SW_EN

PG
VCC
3.3 V

14
15

EN
OSC_EN

VDD

9
8
19
20

BClK
C7
0.22JlF
10

C8
4.7JlF

Figure 17. TPS9103 Configured With External Charge Pump

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7-83

TPS9103
POWER SUPPLY FOR GaAs POWER AMPLIFIERS
SLVS131A-JULY 1996

dimensioning the external voltage divider
Drain voitage should only be applied to the power amplifier when the complete negative voltage from the
GATE_BIAS output is provided to the gate of the GaAs power amplifier. For that reason there is an internal
voltage divider R/O.6R and a PG comparator in the TPS91 03 (see Figure 15). When the voltage at the inverting
input of the comparator reaches zero, the output goes high and the high-side MOSFET switches on, provided
a SW_EN high signal is applied. For example, when the supply voltage at Voo is 5 V, the high-side switch is
switched on when the voltage at GATE_BIAS reaches -3 V.
This trip point can be changed to another value by using an external voltage divider connected between Voo,
GATE_BIAS, and PGP. The resistor values should be low enough to minimize the error that is present when
the internal resistor values (typ R = 100 kQ ± 30%) are taken into consideration. Therefore, the external resistor
values, R1 and R2, are chosen within the 10-kQ range.

Vee

TPS9103

GATE_BIAS " -_ _ _ _ _ _ _ _.....

Figure 18. External Voltage Divider for Setting the Trip Point
R1

= 10 kQ. The value of R2 can then be calculated using:
- 0.6 x R x R1 x V
R2 =

where VDO

trip

-=-:,----:-:---==-:--==--:-:--~----::~

0.6 x V

x [R1 + R] + Vtrip x R1
DD

=supply voltage, and Vtrip =chosen value to trip PG comparator.

The values of the internal resistor can vary about 30%, and can move the trip point. In a worst-case condition,
with a resistor variation of 30%, the shifting of the trip point can be calculated to:

~Vtrip_point

= V DD

x (

1.3 x R
0.6 x R2
R1 + R
0.6 x R2 )
R1
x R2 + 0.78 x R - ~ x R2 + 0.6 x R

~TEXAS

INSTRUMENTS
7-84

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

General Information

III

'---------

Telecommunications Circuits

Central Office Codecs

•

Transient Voltage Suppressors

lEI

RF for Telemetry and RKE

•

Wireless Communications Circuits
Processors for Analog Cellular
Voice-Band Audio Processors
RF for Personal Communications
Baseband Interface Circuits
Digital Signal Processors
Mechanical Data

8-1

....
CD
~

-t

-h

o
-.
....
(J)

8-2

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

•
•

•

Compliance With TIA IS-54B Dual-Mode
Cellular Standard
Baseband Transmit Digital-to-Analog (D/A)
Conversion and Receive Analog-to-Digital
(AID) Conversion in Analog Transmit Mode
Using Dual 1O-Bit Sigma-Delta Converters
Square Root Raised Cosine (SQRC)
Filtering in the Digital Mode Using Dual
10-Bit Sigma-Delta Converters

•

Power Control Supervision for Radio
Frequency (RF) Power Amplifier, Automatic
Frequency Control (AFC), Automatic Gain
Control (AGC), and Synthesizer

•

Received Signal Strength Indicator (RSSI)
and Battery-Level AID Conversion Circuitry
Internal Clock Generation

rrl4-Differential Quadrature Phase-Shift Key
(DQPSK) Modulation Encoder in Digital
Transmit Mode

o
•

•
•

Wide-Band Data Clock Recovery and
Manchester Decoding
General-Purpose Digital Signal Processor
(DSP) and iviicroconlroller Inleriace
3.3-V and 5-V Operation
Low Power Consumption

description
Texas Instruments (TITM) TCM4300 18-54B advanced RF cellular telephone interface circuit (ARCTIC) provides
a baseband interface between digital signal processor (D8P), microcontroller, and RF modulator/demodulator
in a dual-mode 18-54B cellular telephone.
In the analog mode, the TCM4300 provides all required baseband filtering as well as transmit D/A conversion
and receive AID conversion using dual 10-bit sigma-delta converters. In addition, a WBD (wide-band data)
-10 kb/s Manchester frequency shift key (F8K) demodulator is provided to allow reduced D8P processing load
during subscriber standby mode.
In the digital mode, the TCM4300 accepts I and Q baseband data and performs AID and D/A conversion and
square root raised cosine filtering using dual 10-bit sigma-delta converters. The TCM4300 also has a
1t/4-DQP8K modulation encoder for dibit-to-symbol conversion in the digital transmit mode.
The microcontroller interface is compatible with a wide range of microcontrollers. A microcontroller can be used
to communicate with the user interface (keyboard, display, etc.) and to program up to three frequency
synthesizers by using the on-chip synthesizer interface circuit.
The TCM4300 provides advanced power control to minimize the power consumption of many dual-mode
telephone functional blocks such as the speech codec, FM receiver, I and Q demodulator, transmitter signal
processor, and RF power amplifier. In addition, the TCM4300 is designed to reduce system power consumption
through low-voltage operation and standby mode (see Table 1).
The TCM4300 is offered in the 100-pin PZ package and is characterized for free-air operation from -40°C
to 85°C.

NOTE: The data provided in this Product Preview is for the prototype version of the TCM4300.

ARCTIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW Information concerns products In the formative or
desl~n phase of developmenl Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-3

s:
W
:;:

a:
c..

I-

::J
C

a:
c..

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

description (continued)
Table 1. Typical Power Consumption
OPERATING MODE

5.5 V

75mW

275mW

Digital receiving

60mW

250mW

Digital transmitting

85mW

300mW

45mW

190mW

Analog transmitting and receiving

I MCLKOUT enabled
I MCLKOUT disabled

Idle mode
Digital mode, 1/3 transmitting

+1/3 receiving +1/3 standby

17mW

96mW

60mW

220mW

PZ PACKAGE
(TOP VIEW)

c...
~
OC
oC/) C/)

u..::;

~w
~~
mro~m~~~N~OXZ..J..J C/)ClClClClClClClClClClCl
Cl
C/)
C/)C/)~OCWOO c/)Clc...c...c...c...c...c...c...c...c...c...~~~ C/)

~~~~Q~~~~66~~~~~~~~~~~~u6

"tJ
:II

BAT
RSSI
AVDDREF
FM
RXQN
RXQP
AVDDRX
RXIN
RXIP
AGC
AFC
AVSSRX
VSS
VHR
VCM
PWRCONT
TXIP
TXIN
AVDDTX
TXQP
TXQN
AVSSTX
TXEN
TXONIND
PAEN

o
C

-I
"tJ

:II

m
m

:$
~

DVDD
DSPAO
DSPA1
DSPA2
DSPA3
DSPCSL
DSPRW
DSPSTRBL
MCLKOUT
XTAL
DVSS
MCLKIN
DVDD
MCCLK
RSOUTL
RSOUTH
RSINL
MCD7
MCD6
MCD5
MCD4
MCD3
MCD2
MCD1
MCDO

~TEXAS

INSTRUMENTS
8-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

functional block diagram
TXIP

J - 4 - - - - - - - - - t l - - l TXI (04b)

TXIN

TX Data
Registers

TXQP

TXQN

DSP
Interface
RXIP - - - - - - - I.......
RXIN

CONTROL

-----I.,

4
RXQN - - - - - - - I.......

DATA
ADDRESS

RXQP
RSINL
FM

---4.------I~

RSOUTH
RSOUTL
SINT
MCCLK
CSCLK
CMCLK
XTAL
MCLKIN
MCLKOUT

AGC

-+1

AFC

Common

T~ode Input

J-.-

~~~____~__________-+.J~I~

PWRCONT

PAEN
OUT1
FMRXEN
IQRXEN
TXEN
SCEN
SYNOL -----~
TXONIND --------11..-1

Gen

VCM

SYNLE

VHR

REFCAP
MWBDFINT

Synthesizer
Interface
03h-09h

-----I.,

CONTROL
DATA

ADDRESS

LCDCONTR

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

a.
t-

[2:0]

BAT

DWBDINT
CINT
DINT

R S S I - - -......-I

>
w
:J

RBIAS

SYNCLK
SYNDTA

8-5

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

Terminal Functions
RF interface analog signals
TERMINAL
NAME

NO.

1/0

DESCRIPTION
RECEIVE CHANNEL

Input from FM discriminator analog mode voice and wide-band data

RXIN

In-phase differential negative baseband received signal

RXIP

In-phase differential positive baseband received signal

RXQN

Quadrature differential negative baseband received signal

RXQP

Quadrature differential positive baseband received signal

In-phase differential negative baseband transmit signal

TXIP

In-phase differential positive baseband transmit signal

TXQN

Quadrature differential negative baseband transmit signal

TXQP

Quadrature differential positive baseband transmit signal

BAT

Battery strength monitor

RSSI

Received signal strength indicator. Used for signal strength measurements

c::

AGC

Automatic gain control digital-to-analog converter (DAC) output

AFC

Automatic frequency control DAC output

LCDCONTR

Liquid-crystal display (LCD) contrast control DAC output

"tJ

PWRCONT

Power amplifier (PA) power control DAC output

RBIAS

Input for bias current-setting resistor. A 100 kQ, 1% tolerance resistor to AVSS is recommended.

100

Input for reference decoupling capacitor. 3.31lF in parallel with 470 pF is recommended.

TRANSMIT CHANNEL
TXIN

"tJ

:xJ
C

o-I
:xJ

m
::E

MONITORS

CONTROLS

BIAS SETTING

REFCAP

RF interface digital signals
TERMINAL
NAME

NO.

DESCRIPTION

I/O

POWER AMPLIFIER, SYNTHESIZER, AND TRANSMIT CONTROLS
PAEN

Power enable for the transmit power amplifier, active high

OUT1

User-defined general purpose data or control signal

SYNCLK

Synthesizer serial-data clock

SYNDTA

Synthesizer serial-data bit

SYNLEO

Synthesizer 0, 1, and 2 latch enables. An active high indicates the latch is enabled.

SYNLE1

SYNLE2

SYNOL

TXEN

Power enable signal. Enables transmit signal processing, active high

TXONIND

Transmit on indicator. Signal indicating power is applied to the power amplifier.

Synthesizer out-of-Iock indicator. Active high indicates out of lock.

~TEXAS

INSTRUMENTS
8-6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

Terminal Functions (Continued)
miscellaneous digital signals
TERMINAL
NAME

NO.

DESCRIPTION

I/O
Reset input, active low

RSINL

RSOUTH

RSOUTL

0
0

CMCLK

CSCLK

0
0

MCCLK

Microcontroller clock. Adjustable frequency with 1.215 MHz at powerup.

MCLKIN

Master clock input. Frequency 38.88 MHz ± 100 ppm. A crystal can be connected between MCLKIN and XTAL to
provide an oscillator circuit. Alternately, XTAL can be left open and an external TTLICMOS-Ievel clock signal can
be connected to MCLKIN.

MCLKOUT

Buffered version of MCLKIN

XTAL

Use with MCLKIN to form an oscillator circuit.

Power on reset output, active high. At powerup, RSOUTH goes high for 10 ms.
Power on reset output, active low. At powerup, RSOUTL goes low for 10 ms causing an internal reset of the
TCM4300.
CLOCKS
Codec master clock. 2.048-MHz clock is provided as master clock and bit clock for speech codec.
Codec sample clock. 8-kHz frame synchronization pulse for speech codec. Connected to DSP for speech sample
interrupts.

POWER ENABLES
FMRXEN

10RXEN

SCEN

0
0
0

:>
w

Power enable for receiver FM path, active high
Power enable for receiver I/O path, active high

a:
a..

Power enable for speech codec, active high

DSP interface
TERMINAL
NAME

NO.

I1/01Z

DESCRIPTION

o
c

CINT

Controller data interrupt. Microcontroller data interrupt (active low) sent to DSP. Caused by the microcontroller
writing into the Send-C Int register location

DSPAO

DSP 4-bit parallel address bus. DSPA3 is the MSB, and DSPAO is the LSB.

DSPA1

DSPA2

DSPA3

DSPCSL

DSPDO

I/O/Z

DSPD1

DSPD2

DSPD3

oa:
a..

DSP interface chip select signal, active low
DSP 1O-bit parallel data bus. DSPD9 is the MSB, and DSPDO is the LSB.

DSPD4

DSPD5

DSPD6

DSPD7

DSPD8

DSPD9

DSPRW

DSPSTRBL

DSP strobe signal, active low

DWBDINT

DSP wide-band data interrupt. Wide-band data-ready interrupt (active low) caused byWBD demodulation circuits.

SINT

0
0

DSP read/write signal. DSPRW is active high for read cycles and active low for write cycles.

Sample interrupt (active low). Operates at 40 kHz in the analog mode and 48.6 kHz in the digital mode.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-7

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

Terminal Functions (Continued)
microcontroller interface
TERMINAL
NAME

NO.

1/0

DESCRIPTION
Microcontroller interrupt request signal. DSP data-ready interrupt sent to controller. Caused by DSP writing to
SEND DINT register location. DINT can be active high or low according to the levels of the microcontroller type
select (MTS) (1 :0) signals.

DINT

Microcontroller 5-bit parallel address bus. MCA4 is the MSB, and MCAO is the LSB.

Microcontroller interface chip-select signal, active high. Chip select occurs if MCCSH is high and MCCSL is
low.
Microcontroller interface chip-select signal, active low. Chip select occurs if MCCSH is high and MCCSL is low.

MCAO

MCA1

MCA2

MCA3
MCA4

43
/

MCCSH

MCCSL

MCDO

I/OIZ

MCD1

MCD2

MCD3

MCD4

MCD5

o
C

Microcontroller 8-bit parallel data bus. MCD7 is the MSB, and MCDO is the LSB.

MCD6

-I

MCD7

"tJ

MCDS

Microcontroller data strobe. Operational characteristics are selected by MTS (1 :0).

MCRW

Microcontroller read/write. Operational characteristics are selected by MTS (1 :0).

MTSO

MTS1

Microcontroller type select configuration control inputs. The interface is controlled by MTS (1 :0) as follows:
00 - Intel™ microcontroller interface characteristics
10 - Mitsubishi™ microcontroller and Motorola microcontroller 16-bit bus interface characteristics
01 - Motorola™ microcontroller 8-bit bus characteristics
11 - Reserved

MWBDFINT

Microcontrollerinterrupt request signal. Wide-band data-ready interrupt caused by WBD demodulator in analog
mode or frame interrupt sent by the DSP in digital mode. MWDBFINT can be active high or low, according to
the levels of the MTS (1 :0) signals.

Intel is a trademark of Intel Systems, Inc.
Mitsubishi is a trademark of Mitsubishi Inc.
Motorola is a trademark of Motorola Inc.

~TEXAS

INSTRUMENTS
8-8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS010E - DECEMBER 1994 - REVISED JUNE 1996

Terminal Functions (Continued)
supply and reference voltages
TERMINAL
NAME

NO.

AVDDRX

AVDDREF

AVDDTX

AVSSREF

AVSSRX

AVSSTX

DVDD

35,45,63,
75,90

DVSS

34,46,65,
76,91

110

DESCRIPTION
Analog supply voltage for RX receive path
Analog supply voltage for RX FM receive path
Analog supply voltage for TX transmit path
Analog ground for REFCAP
Analog ground for RX receive path
Analog ground for TX transmit path
Digital power supply. All supply pins must be connected.

Digital ground. All supply pins must be connected.

VCM

Voltage common mode. VCM is used to establish dc operating point for TX outputs and can be tied to VHR.

VHR

Half-rail reference voltage (VHR), approximately 0.5 x AVDD. VHR is used to establish dc operating pOint for
RX inputs.

VSS

13,97

Substrate ground

->==
W

detailed description
data transfer
The interface to both the system digital signal processor and microcontrolier is in the form of 2s complement.

W
£t
C.

I-

receive section
The mode of operation is determined by the state of the MODE, FMVOX, IQRXEN, and FMRXEN bits of the
DStatCtrl register, as shown in Table 2. The specifications for the receive section are included in Table 3.
Table 2. TCM4300 Receive Channel Control Signals
CONTROL SIGNAL

ANALOG MODE

MODE

IQRXEN

FMRXEN

In the digital mode (MODE=1), the receive section accepts RXIP, RXIN, RXQP, and RXON analog inputs. These
inputs are passed to continuous-time antialiasing filters (AAF), baseband filtering, and AID conversion blocks,
and then to sample registers where 10-bit registers can be read. The sample rate is 48.6 ksps.
In the analog mode (MODE = 0), the FMVOX bit of the DStatCtrl register enables or disables the Q side of the
receiver channel, and the FMRXEN bit controls the external functions. In the digital mode, IQRXEN enables
both the I and Q receive channels and external functions as well.
To save power, the receive I and Q channels are enabled separately. This operation occurs because in the
analog mode, only the Q channel is used. When the FMVOX bit is set to 1, it controls the input multiplexer,
connects the FM input to the receiver RXQP Signal, and connects the RXQN signal to VHR. When the MODE
control bit and the IQRXEN control bit are set to 1, both sides of the receive channel are enabled for use in the
digital mode.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

£t
C.

DIGITAL MODE

FMVOX

:::l
C

8-9

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

receive section (continued)
The input signals RXIP, RXIN and RXQP, RXQN are differential pair signals. Differential signals are used to
minimize the pickup of interference, ground, and supply noise, while maintaining a larger signal level. In
single-ended applications, the unused RXIN and RXQN terminals must be connected to VHR orto an externally
supplied bias voltage, and the input signal level must be adjusted in the RF circuitry to provide a higher level
signal so that the digital output codes are properly calibrated (0.5 V peak-to-peak corresponds to full-scale
digital output). In the analog mode, the RXQN input is internally referenced to VHR. Alternatively, the unused
inputs can be connected to VHR and the used inputs can be capacitively coupled. Note that when the RX and
FM inputs are capacitively coupled, the input pins to the TCM4300 are self-biased to VHR; no external bias is
needed at the input pins.
The single-ended output of an external FM discriminator is connected to the FM pin for analog mode voice and
WBD reception. The signal at this pin is conveyed to the Q side of the receiver via the multiplexer, and the other
Q input is connected internally to the VHR reference voltage. The I input of the RX circuitry is disabled in the
analog mode. The FM signal passes through the antialiasing filter, as specified in Table 4, before passing
through the NO converter. The signal at the FM pin is also routed directly to the WBD demodulator through a
·Iow-pass filter (LPF) with the -3 dB point at 270 kHz.
The VHR can provide a bias voltage for the received inputs when capacitively coupled from the RF section. To
meet noise requirements, the VHR output should have an external decoupling capacitor connected to ground.
The VHR output buffer is enabled by the OR of TXEN, FMVOX, and IQRXEN. The VHR output is high
impedance. otherwise.

"'C

In the digital mode, both the I and Q receive sides are enabled. Table 5 lists the receive channel frequency
response.

(')

When the I and Q sample conversion is complete and the data is placed in the RXI and RXQ sample registers,
the SINT interrupt line is asserted to indicate the presence of that data. This occurs at 48.6-kHz rate in the digital
mode and at 40-kHz rate in the analog mode. In the analog mode, only the RXQ conversion path is used, and
the RXI path is powered down.

-I
"'C

Table 3. RXIP, RXIN, RXQP, and RXQN Inputs (AVoo

m
m
===

PARAMETER

TEST CONDITIONS

Common-mode input voltage range

MIN

TYP

0.3

Differential

0.5

Single-ended

0.5

Nominal operating
level

Differential

0.125

Single-ended

0.125

I/O sample timing skew

6%
Input signal 0 - 15 kHz

A/D resolution
Signal to noise-pius distortion

Input at full scale - 1 dB

Integral nonlinearity

o dB to -60 dB input

Digital/Analog kHz
7%

Bits

dB
LSB

a channel)

Gain mismatch between I and

Vp-p. Provides 12 dB headroom for
AGC fading conditions.

48.6/40

Receive error vector magnitude (EVM)

UNIT
V
Vp-p

Sampling frequency, SINT

Gain error (lor

MAX
AVDD-0.3

Input voltage for fullscale digital output

Input CMRR (RXI, RXO)

=3 V, 4.5 V, 5 V)

±10%

Differential dc offset voltage
FM input sensitivity

±0.3

±30

mV
Vp-p for full scale (± 14 kHz deviation)

2.5

FM input dc offset (wrt VHR)

±90

FM input idle channel noise

-45

dB below full scale input

FM gain error
Power supply rejection

±7%
f

=0 kHz to 15 kHz

•
TEXAS
INSTRUMENTS
8-10

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

receive section (continued)
Table 4. RX Channel Frequency Response (FM Input in Analog Mode)
PARAMETER

Frequency response

TEST CONDITIONS

o kHz to 6 kHz (see Note 1)

2.5 V peak-to-peak,

20 kHz to 30 kHz (see Note 2)

-18

2.5 V peak-to-peak,

34 kHz to 46 kHz (see Note 3)

-48

Peak-to-peak group delay distortion

2.5 V peak-to-peak,

o kHz to 6 kHz

Absolute channel delay

2.5 V peak-to-peak,

o kHz to 6 kHz

NOTES:

MIN

2.5 V peak-to-peak,

TYP

MAX

UNIT

±0.5
dB

2
400

I-1s

1. Ripple magnitude
2. Stopband
3. Stopband and multiples of stopband

Table 5. RX Channel Frequency Response (RXI, RXQ Input in Digital Mode)
PARAMETER

Frequency response

TEST CONDITIONS

o kHz to 8 kHz (see Note 4)

0.125 V peak-to-peak,

8 kHz to 15 kHz (see Note 4)

0.125 V peak-to-peak,

16.2 kHz to 18 kHz (see Note 5)

-26

0.125 V peak-to-peak,

18 kHz to 45 kHz (see Note 5)

-30

0.125 V peak-to-peak,

45 kHz to 75 kHz (see Note 5)

-46
-60

0.125 V peak-to-peak,

> 75 kHz

Peak-to-peak group delay distortion

0.125 V peak-to-peak,

o kHz to 15 kHz

Absolute channel delay, RXI, Q IN to
digital OUT

0.125 V peak-to-peak,

o kHz to 15 kHz

NOTES:

MIN

0.125 V peak-to-peak,

TYP

MAX

±0.5

±0.75

UNIT

±1
dB

2
325

I-1S
I-1s

4. Deviation from ideal 0.35 SQRe response

3:
w

5>
w
a:
c..
tO

5. Stopband

transmit section

:::J

The transmit section operates in two distinct modes, digital or analog. The mode of operation is determined by
the MODE bit of the DStatCtrl register. In the digital mode, data is input to the transmit section by writing to the
TXI register. The resulting output is a 1tf4 DQPSK-modulated time division multiplexed (TDM) burst. In the
analog mode, the data is in the form of direct I and Q samples which are written to both the TXI and TXQ
registers, then DfA converted, filtered, and output through TXIP, TXIN, TXOP, and TXON. The I and 0 outputs
are zero-IF FM signals; that is, no baseband connection is necessary for FM transmission.
In the digital mode (MODE=1), the data is written to the TXI register using the SINT interrupt to synchronize the
data transfer. The TCM4300 performs parallel-to-serial conversion of the bits in the TXI register and encodes
the resulting bit stream as 1tf4 DQPSK data samples. These samples are then filtered by a digital square root
raised cosine (SORC) shaping filter with a roll-off rate of ex = 0.35 and converted to sampled analog form by two
9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by a continuous-time
resistance-capacitance (RC) filter.
The TCM4300 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the PA.
The start and stop times of the TDM burst are controlled by writing to a single bit, TXGO, in the DSP DStatCtrl
register.
In the analog mode (MODE = 0), the DSP writes 8-bit I and Q samples into the TXI and TXO data registers at
a 40-ksps rate. These writes are timed by the SINT interrupt signal. The samples are fed to a low-pass filter
before Df A conversion. In the transmit analog mode, the PAEN signal is always set to 1.
The transmitter section provides differential I and 0 outputs for both analog and digital modes. The differential
dc offset for the TXI and TXQ outputs can be independently adjusted using the TX offset registers.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-11

a
a:

c..

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

transmit section (continued)
Table 6. Transmit I and Q Channel Outputs
PARAMETER

TEST CONDITIONS

Peak output voltage full scale, centered at VCM

Nominal output-level (constellation radius) centered at VCM

MIN

TYP

Differential

2.24

Single-ended

1.12

Differential

Resolution

±10%

Zero code error differential

±90

Zero code error, each output, with respect to VCM

±90

±10

Zero code error, I to Q, with respect to other channel
(differential or single-ended)
Load impedance, between P and N pins

VCM input voltage range

1.3

Transmit offset DACs I and Q resolution

AVDD-1.3

Transmit offset DACs I and Q full-scale positive output

Transmit offset DACs I and Q full-scale negative output

3.4

pF
V
bits

Transmit offset DACs I and Q average step size

<
-

• Load capacitance

""C

-I

:XJ

dB
±15%
±0.3

Gain sampling mismatch between I and Q

bits

Gain mismatch between I and Q

8
40

Gain error (lor Q channel)

PPM/oC

±200

S/(N+D) ratio at differential outputs

:XJ

0.75

Low-level drift

UNIT
Vp

1.5

Single-ended

Transmit error vector magnitude (EVM)

""C

MAX

3.9

105.4

mV
mV

-108.8

Transmit offset DACs differential nonlinearity

±1.1

LSB

Transmit offset DACs integral nonlinearity

±1.1

LSB

Modulation Error: In the digital mode, during the transmit burst, the complex output of the transmitter circuits
consists of an ideal output s =I ideal + jQideal + error e =ei + je q. In Table 6, the modulation error (EVM) is defined
as the peak value of the magnitude of e relative to the ideal output:

.
lei
Mo duIatlon error percentage = 100 1ST %

~TEXAS

INSTRUMENTS
8-12

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

transmit section (continued)
Table 7 and Table 8 show the frequency response of the transmit section for digital and analog mode,
respectively.
Table 7. Transmit Channel Frequency Response (Digital Mode)
PARAMETER

TEST CONDITIONS

MIN

TYP

o kHz to 8 kHz (see Note 4)

Peak-to-peak group delay distortion
Absolute channel delay
NOTES:

UNIT

±0.3

8 kHz to 15 kHz (see Note 4)
Frequency response

MAX

±0.5

20 kHz to 45 kHz (see Note 5)

-29

45 kHz to 75 kHz (see Note 5)

-55

> 75 kHz (see Note 5)

-60

Any 30 kHz band centered at > 90 kHz (see Note 5)

-60

o kHz to 15 kHz
o kHz to 15 kHz

3
320

Ils
Ils

4. Deviation from ideal 0.35 SQRe response
5. Stopband

Table 8. Transmit Channel Frequency Response (Analog Mode)
PARAMETER

Frequency response

Peak-to-peak group delay distortion
Absolute channel delay
NOTES:

TEST CONDITIONS

MIN

TYP

MAX

o kHz to 8 kHz (see Note 1)

±0.5

8 kHz to 15 kHz (see Note 1)

±0.5

20 kHz to 45 kHz (see Note 5)

-31

45 kHz to 75 kHz (see Note 5)

-70

> 75 kHz (see Note 5)

-70

Any 30 kHz band centered at > 90 kHz (see Note 5)

-70

o kHz to 15 kHz
o kHz to 15 kHz

UNIT

:>
w
dB

a::

t::::»

O
3
540

Ils
Ils

1. Ripple magnitude
5. Stopband

o
a::
a.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-13

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

transmit burst operation (digital mode)
In the digital mode, the TCM4300 performs all encoding, signal processing, and power ramping for the burst.
Start and stop timing of the variable length bursts are set by means of the TXGO bit in the DStatCtrl register.
The SINT interrupt output interrupts the DSP at 48.6 kHz which is T/2 interval (T = 1 symbol period = 1/24.3 kHz).
The burst'is initiated by the DSP writing 1 to 5 dibits to the TXI register, a small positive delay offset value d to
the base station (SST) register, and a 1 to the TXGO bit in the DStatCtrl register.
The TXGO bit is sampled on the falling edge of SINT. The TX outputs are held at zero differential voltage (each
output pin is held at the voltage supplied to the VCM input pin) for 9.5 SINT periods (195.5 ~s) plus SST offset
delay after SINT has detected TXGO high; then the TX outputs begin to ramp to the initial rr/4 DOPSK
constellation value. The shape of the ramp is the transient resulting from the internal SORC filtering. At the same
time that the TX outputs are beginning to ramp, the PAEN digital output goes high. This output can be used to
enable the power amplifier of a cellular radio transmitter. The TCM4300 TX outputs reach the first rr/4 DOPSK
constellation value (maximum effect point, MEP) 6 SINT periods (3 symbol periods) after the start of the ramp.
The bit stream to be encoded as rr/4 DOPSK symbols is generated by right shifts on each SINT of the TXI
register with bit 0 (LSS) used first.
Previously written data continues to propagate through the TCM4300 internal filters until the last rr/4 DOPSK
constellation value (last MEP) occurs at the TX outputs 15.5 SINT periods (318.9I1S) plus SST offset delay after
the last symbol occurs (2 SINT periods before TXGO goes low); then the TX outputs decay to zero differential
voltage (each output at the voltage supplied to the VCM input pin). The shape of the decay is the transient
resulting from the internal SORC filtering. The TX outputs are held at zero differential voltage 6 SINT periods
(3 symbol periods) after the start of the decay. At this time the PAEN digital output is set low (see Figure 1 and
Figure 2).

::D

o
C

c:
o

Non-zero values of the SST 'Offset register increase the delays of both the TX waveforms and PAEN relative
to the edges of TXGO after it is internally sampled by SINT. The delays are increased in increments of 1/4 SINT
(1/8 symbol period).

-I
\J
::D

For delays of 1.SINT or greater, the fractional part of the delay can be achieved using the SST offset register
with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI.

m
S
m

The relative timing of PAEN and the TX waveforms is not affected by the SST offset register.
The IS-54 standard describes shortened bursts and normal bursts. The two types differ in duration and number
of transmitted bursts, burst length being determined by the TXGO bit.

14
1

~:~.---

N+3 SINT Periods
(N

= Total number of bits sent)

!4I
I

19.5 SINT Periods +d(T/8)

/4--#--

6 SINT Periods

---~~

15.5 SINT Perlods+d(T/8)

I
I
I

n"~~ =+:!::-h=~="" "T-r-=~=~=~=+-!;.~=~=~=~=.,..,!=~=~=~=~=~=-'<=4'l}r-r=i::~i~i-tr!=i:~~=:~=~=:~=~=~:j::i+r-i'~~~;il===~=~
>~
l b

TXVQOU:~~~:~7t~
Dibiltransmission

[] [] D D o t

»> c

c »>

»>

First MEP

t Total delay =d (SINT/4 or T/8) where d =integer value (0,1,2,3) written to the SST offset register.
Figure 1. Power Ramp-Up/Ramp-Down Timing Diagram

~TEXAS

INSTRUMENTS
8-14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Last MEP

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

transmit burst operation (digital mode) (continued)

r----------------------------------------------,
D

elK
Delay

L ___ _

r----

I
I
I
I
I
I

I
I
I
I
I
I
I
I

Channel Delay
(15.5 SINT Periods)

=0, 1/4, 1/2,314

Transmit Channel Delay + d(T/S)
Occurs from last symbol (2 SINT periods)
before TXGO goes low

--------------------------~

------------ --------------------------,
Q

SINT - - - a

I
I
I
I
I
I
I
I
I
I
I

PAEN Delay

9.5 - '

ClK

19.5 - .

PAEN Delay + d(T/B)
TXGO high: 9.5 SINT periods + d(T/S): PAEN high
low:
19.5
d(T/S):
low
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TXGO
___
__
_ SINT
_ _periods
_ _ _+_
_ _ PAEN
___
__

I
I Dibit In
I
I
I
I TXGO
I
I

Figure 2. TX Power Ramp-Up/Ramp-Down Functional Diagram

D..
I-

transmit I and Q output level
In the digital mode, the output level at TXI and TXQ is controlled by the TCM4300. During the burst, but not
including ramp-up or ramp-down periods, the average output level (1 2 + Q2) 112 should approximate the specified
value. There is no variable level control for TXI and TXQ within the TCM4300 other than the fixed ramping. In
the analog mode, the output of the TCM4300 depends only on the sample values written to the TXI and TXQ
registers.
There are small differences in the average output power levels between the digital and the analog modes. These
differences require compensation at the system level by a small attenuation in the sample values of the analog
output.
,/
When a change in transmit power is necessary, the microcontroller can change the value sent to the PWRCONT
DAC, the output of which can be connected to a voltage-controlled attenuator in the transmit path of the RF
section.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3:
w
>
w

8-15

:::l
C

D..

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

wide-band data demodulator
The wide-band data demodulator (WBDD) module demodulates the FM signal and outputs a
Manchester-decoded data stream. The WBDD is used for receiving the analog control channels of forward
control channel (FOCC) and forward voice channel (FVC). The bit error rate (BER) performance requirements
are listed in Table 9.

Table 9. Typical Bit Error Rate Performance (WBD_BW

=000)

TEST CONDITIONS

PARAMETER

MEAN CNR (dB)

MIN

-5

Bit error rate

-C

MAX

UNIT

0.4

0.279

0.143

0.056

0.0192

0.00623

0.00199

The WBDD is controlled by the bits in the control register WBDCtrl (see Table 10).

Table 10. Bits in Control Register WBDCtrl

NAME

WBD_LCKD

-t

WBD_BW

(")

WBD_ON

-C

m
m
===

BIT CODE

FUNCTION
Indicates whether edge detector is locked (1) or unlocked (0)
Turns the WBDD module on/off (1/0)
Sets the appropriate PLL bandwidth

000

20 Hz

001

39 Hz

010

78 Hz

011

156 Hz

100

313 Hz

101

625 Hz

110

1250 Hz

WBD_LCKD: This bit can be used to reduce the effects of signal dropouts due to fading. In the
Manchester-coded signal, there are two types of data edges. One type occurs at the midpoint of each data bit,
and the other occurs randomly, depending on the transmitted data sequence. Inside the WBDD, an edge
detector rapidly synchronizes itself to the midpoint edges when the WBD_LCKD bit is set to O. However, if a
signal dropout occurs, the edge detector may momentarily lock to the wrong edge because it cannot distinguish
the midpoint edges from the data edges. A sma" number of additional bits may be lost in this instance.
When the WBD_LCKD bit is set to 1, the edge detector uses the WBDD internal PLL output to distinguish the
correct edge. Once acquisition of data has occurred, if this bit is set to 1, the loss of bits due to signal dropouts
is restricted to the fade duration only.
When the WBDD PLL is not synchronized, as at powerup, the WBD_LCKD bit must be cleared to 0 to allow edge
synchronization to the data.
WBD_BW: The variable bandwidth is required for fast acquisition in the beginning using a wide b,;mdwidth for
the PLL, and a narrower bandwidth is used afterwards to reduce the likelihood of noise-causing loss of
synchronization.
The WBDCtrl register is accessible by both the DSP and the microcontro"er.

"TEXAS
INSTRUMENTS
8-16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCiV14300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

wide-band data interrupts
The WBDD operates whenever WBD_ON is high, and it does not require the receive channels to be enabled.
While WBD_ON is high, every 800 fls, 8 bits are placed in the WBD register, which is accessible by both the
DSP and the microcontroller ports. This value should be written at the same time as WBD_ON is initially set
high.
At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 fls
(8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by the corresponding
processor. They can also be cleared by their respective processor by writing a 1 to the corresponding clearWBD
bit.
There is one WBD control register. It can be written to by either processor port.

wide-band data demodulator: general information
The WBDD recovers the transmitter clock from the data stream, which is Manchester encoded, and decodes
the data bits. Consideration at the system level is required to ensure data integrity.
The WBD stream carries with it a 1a-kHz clock. The Manchester-coded data format contains a transition at the
middle of every bit-clock period, which aids in clock recovery. The polarity of the transition is data-dependent.
In a typical Manchester-coded WBD stream, a positive voltage for the first half of the data sequence bit time
followed by a negative voltage for the second half of the data sequence bit time represents the value a in the
data sequence. Likewise, a negative voltage followed by a transition to a positive voltage represents the value
1 in the data sequence. This is illustrated in Figure 3. The WBD stream can also be seen as the exClusive-OR
of the clock and data sequence. The data sequence is in nonreturn to zero (NRZ) format.

Data
0
Sequence 1-----01

w
a:
a.
....o
::l

weD

Stream

0::

a.
Recovered Clock
10 kHz

Figure 3. WeD Manchester-Coded Data Stream

auxiliary digital-to-analog converters (DACs), LCD contrast converter
Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three DIA converters
are updated when the corresponding data is received from the DSP. In fewer than 5 fls after the corresponding
registers are written to, the output has settled to within 1/2 LSB of its new value (see Table 11).
The LCDCONTR output is used by the microcontroller to adjust the contrast of the liquid-crystal display (LCD).
This converter is a separate 4-bit DAC.

~TEXAS

INSTRUMENTS
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8-17

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

auxiliary digital-to-analog converters (DACs), LCD contrast converter (continued)
Table 11. Auxiliary D/A Converters
PARAMETER

MIN

TEST CONDITIONS

vt,
AVDD > 4.5 vt,
AVDD > 5 vt,

AVDD > 3
Output range

=00
AUXFS [1 :0] =10
AUXFS [1 :0] =11
AUXFS [1 :0]

TYP

MAX

0.2

UNIT

2.5

0.2

4.5

Resolution AGC, AFC, PWRCONT DACs

bits

Resolution LCDCONTR DAC

bits

Gain + offset error (full scale) AGC, AFC, PWRCONT DAC

±5%

Gain + offset error (full scale) LCDCONTR DAC

±8%

Differential nonlinearity

±1.3

±2

LSB

Integral nonlinearity

±1.3

±2

LSB

Load resistance

Load capacitance

t Range settings depends only on AUXFS [1 :0]. The supply voltage is not detected.

"tJ

c:
o

The auxiliary DACs can be powered down. The AGC and AFC DACs have dedicated bits in the MlntCtrl register
to enable the DACs. The PWRCONT DAC is enabled by the TXEN bit in the DStatCtrl register. The LCDCONTR
DAC is enabled when the LCDEN bit of the LCD D/A register is set to 0, the four data bits being left justified.
The AFC, AGC, and PWRCONT DACs are disabled after powerup or after a reset of the TCM4300. After
powerup or reset, the default AUXFS[1 :0] is 00. When the DACs are powered down, their output pins go to a
high-impedance state and can tolerate any voltage present on the pin that falls within the supply range.

-I

The slope and the corresponding output values for the auxiliary DACs are listed in Table 12 and Table 13.

Table 12. Auxiliary D/A Converters Slope (AGC, AFC, PWRCONT)

S
m

AUXFS[1:0]
SETTING

SLOPE

NOMINAL LSB
VALUE
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 128
(MIDRANGE)
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 25S:t:
(MAX VALUE)
(V)

2.5/256

0.0098

1.25

2.5

Do not use

4/256

0.0156

4.5/256

0.0176

2.25

4.5

:j: The maximum input code is 255. The value shown for 256 is extrapolated.

Table 13. Auxiliary D/A Converters Slope (LCDCONTR)
AUXFS[1:0]
SETTING

SLOPE

NOMINAL LSB
VALUE
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 8
(MIDRANGE)
(V)

2.5/16

0.1563

1.25

2.5

Do not use

4/16

0.2500

4.5/16

0.2813

2.25

4.5

§ The maximum input code is 15. The value shown for 16 is extrapolated.

~TEXAS

INSTRUMENTS
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NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 1S§
(MAX VALUE)
(V)

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

RSSI, battery monitor
The received signal strength indicator (RSSI) and battery (BAT) strength monitor share a common register. The
input source is determined by writing any value to the mapped register location for that analog-to-digital
converter (see Table 14), and the result of the conversion is stored in both register locations. The conversion
process is initiated when the register is written to. The CVRDY bit in the MStatCtrl register is set to 1 to show
completion of the conversion process. Reading from either of the register locations causes the CVRDY bit to
change to O. The received signal strength indicator allows the mobile unit to choose the proper control channels
and to report signal levels to the base stations.
When CVRDY in the MStatCtrl register goes to 1, this indicates that the latest RSSI or battery voltage AID
conversion has been completed and can be read from the RSSI or BAT register location. CVRDY goes to 0 when
the microcontroller reads either of these locations.

Table 14. RSSIiBattery AID Converter
PARAMETER
Input range

TEST CONDITIONS
AVDD

=3 V, 4.5 V, 5 V

MIN

Resolution
Conversion time

TYP

0.2

MAX

2
8

AVDD

=3 V, 4.5 V, 5 V

±4%

Differential nonlinearity
Integral nonlinearity
Input resistance

V
bits

Gain + offset error (full scale)

UNIT

Jls
±5%
±1.5

LSB

±1.5

LSB

Mil

In order to save power, the entire RSSl/battery converter circuit is powered down when no AID conversions are
requested for 40 ~s. The microcontroller writes to RSSI or BAT registers, causing power to be applied to the
converter circuit. Power is applied to the converter circuit until the data value has been latched into the
corresponding register, at which time power to the converter is removed. Data remains in the result registers
after the converter is powered down.

timing and clock generation
The digital timing generation system uses a 38.88-MHz master clock, as shown in Figure 6. The upper half of
the figure shows the clock generation for clocks that must be phase adjusted in order to synchronize the mobile
unit with the received symbol stream in the digital mode. In the analog mode, these clocks operate without phase
adjustments. The lower half of Figure 6 shows the clocks that are directly derived from the master clock.

clock generation
There are three options for generating the master clock. A fundamental crystal or a third-overtone crystal with
a frequency of 8 MHz can be connected between the MCLKIN and the XTAL terminals or an external clock
source can be connected directly to the MCLKIN terminal. The MCLKOUT is a buffered master clock output at
the same frequency as MCLKIN. MCLKOUT can be used as the source clock for other devices in the system.
Setting the MCLKEN bit in the MStatCtrl register enables or disables this output. The MCLKOUT enable is
synchronous to eliminate abnormal cycles of the clock output.
All output clocks are derived from the master clock (MCLKIN). The sample clocks for the digital and analog
modes, the 8-kHz speech codec sample clock, and the clocks for the AID and D/A functions are also derived
from the master clock.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-19

w
>
w

a::

I-

=>
c
oa::
~

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS010E - DECEMBER 1994 - REVISED JUNE 1996

speech codec clock generation
The TCM4300 generates two clock outputs for use with speech codecs: the 2.048-MHz CMCLK and the 8-kHz
CSCLK. These clocks are generated so that each CSCLK period contains exactly 256 cycles of CMCLK. Since
2.048 MHz is not an integer division of the 38.88-MHz MCLKIN, one out of every 64 CMCLK cycles is 18
MCLKIN periods long, and the remaining 63 out of 64 are 19 MCLKIN periods long. The average frequency of
MCLKIN is therefore
MCLKIN x

( 63

+
64

= 2.048092 MHz

CSCLK is exactly CMCLK divided by 256. See Figure 4.
CMCLK
Co dec Master Clock 2.048 MHz
CSCLK

--------'

Co dec Sample Clock 8 kHz

Figure 4. Codec Master and Sample Clock Timing

-a

To save power, the codec clocks are only generated by TCM4300 when the SCEN bit of the DStatCtrl register
is set high. When SCEN is low, both outputs, CSCLK and CMCLK, are held low. SCEN is also available as an
output.

o
C

(")

microcontro"er clock

-I

A variable modulus divider provides a selection of frequencies for use as a microcontroller clock. The master
clock is divided by an integer from 32 to 2, giving a wide range of frequencies available to the microcontroller
(1.215 MHz to 19.88 MHz). The modulus can be changed by writing to the microcontroller clock register. The
output duty cycle is within the requirements of most microcontrollers, that is, from 40% to 60%. At power-on
reset, the clock divider defaults to 1.215 MHz.

-a

\~----

sample interrupt SINT

The SINT interrupt signal is the primary timing signal for the TCM4300 interface. The primary function of the
SINT is to indicate the ready condition to receive or transmit data. It also conveys timing marks to allow for the
synchronization of system DSP functions. In the digital mode, SINT is used in conjunction with the received sync
word to track cellular system timing. The SINT can be disabled by writing a 1 to the SOlS bit of the DlntCtrl
register. When enabled, the SINT operates continuously at 48.6 kHz in the digital mode and at 40 kHz in the
analog mode. The SINT signal does not require an interrupt acknowledge. The SINT is active low for 5.5 MCLK
cycles (141.5 ns) in the analog mode and 6.5 MCLK cycles (167.2 ns) in the digital mode.

phase-adjustment strategy
In the digital mode IS-54 system, receiver sample timing must be phase adjusted to synchronize the AID
conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit timing to
the base station timing. This is done by temporarily increasing or decreasing the periods of the clocks to be
adjusted. To avoid undesirable transients, each cycle of the clock being adjusted is altered by only one period
of MCLKIN. A total adjustment equivalent to multiple MCLKIN periods is accomplished by altering multiple
cycles of the clock being adjusted. The number of cycles altered is controlled by internal counters.
In the TCM4300 there are two clocks which must be adjusted: CMCLK and an internal 9.72-MHz clock from
which SINT is derived. Each of these clocks has an associated counter that counts the number of cycles that
have been lengthened or shortened by one MCLKIN period each and thus detects when the total adjustment
is complete. These counters are shown in Figure 6 as Adjust Counter A and Adjust Counter B .

8-20

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

phase-adjustment strategy (continued)
The magnitude of the 2s complement value written to the timing adjustment register determines the number of
cycles of the clocks to be lengthened or shortened by one MCLKIN period each to achieve the total desired
timing adjustment in units of MCLKIN periods. If a negative number is written, the clock periods are lengthened
for the duration of the timing adjustment, resulting in a timing delay. If a positive number is written, the clock
periods are shortened for the duration of the timing adjustment, resulting in a timing advance.
The divider used to generate CMCLK normally divides MCLKIN by either 19 or 18. When the CMCLK period
is being lengthened during a timing adjustment, MCLKIN is divided by either 20 or 19. When the CMCLK period
is being shortened, MCLKIN is divided by either 18 or 17 (see the section on speech codec clock generation).
The divider used to generate a 9.72-MHz clock divides by 4 during normal operation, by 5 when its period is
being lengthened during timing adjustments, and by 3 when its period is being shortened during timing
adjustments.
Because CMCLK and the 9.72-MHz internal clock have different periods, and the timing adjustments are limited
to one period of MCLKIN per period of the clock, these clocks take different times to complete the entire timing
adjustment. Because the total adjustment is the same number of MCLKIN periods for both clocks, the relative
phases of the two clocks are the same after the adjustment as they were before.
Both adjust counters reach zero when the adjustment is complete, so there is no need to write to the timing
adjustment register until another timing adjustment is required. For each write to the timing adjustment register,
a single timing adjustment of the direction and magnitude requested is performed.
2.048-MHz Co dec Master Clock CMCLK

s:w

->w
a:
a.

8-kHz Codec Sample Clock CSCLK

From DSP -+--.0<;....-.-.......

::::l

Phase-Adjusted
9.72-MHz Clock

a
a:
a.

Analog/Digital
40.0/48.6-kHz AID Sample Clock (SINT)

38.88 MHz
MCLKIN

Frequency Synth. Clock 303.75 kHz
Clock

WeD Demod. 6.48 MHz

Divider
ADC Clocks
Chain I----------------------.:.D...:.:.A=-C=-C.::-I-OC-k-S

From
Microcontroller -,..,.--..,

, Microcontroller Clock MCCLK
N

=(2, 3, ..• 32)
Sync.
Enable I -_ _ _ _ _ _ _ _-=E:.::.xt.:..::ec:..!rn.:..::a"--IC::.:Ic=:.o:::.:ck-,-,O=u=t~u::..:t,-"M:.:..:C=-=Lo:..:K,-=O:..:::U,-,-T

MCLKEN

Logic

Figure 5. Timing and Clock Generation for 3S.SS-MHz Clock
The output of each adjustment counter is fed to a variable modulus divider. For counter A, there are three
possible moduli, 3, 4, and 5. For counter B there are four possible moduli, 17, 18, 19, and 20.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-21

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

frequency synthesizer interface
The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side outputs
are a data line, a clock line, and three latch enable lines that separately strobe data into each synthesizer. The
control inputs are registers mapped into the microcontroller address space. The status of the interface can be
monitored to determine when the programming operation has been completed.
The synthesizer interface is designed to be general purpose. Most of the currently available synthesizers can
be accommodated by programming the interface according to the required synthesizer data and logic level
formats.
The output of the synthesizer interface consists of five signals. SYNCLK is the common data clock for all
attached synthesizer chips. The clock rate is MCLK/128 (",,304 kHz). The clock pulse has a 50% duty factor.
The serial data output SYNDTA is common to all synthesizers. Three strobe signals, SYNLE[2:0], are provided.
There is one for each synthesizer chip. The attributes of this interface are controlled by means of the synthesizer
control registers, SynCtrl[2,1 ,0]. These attributes determine:
•

"tJ

:xJ

o
C

The polarity of the clock (rising or falling edge)

•

Whether data is shifted left or right

•

The number of bits sent to the synthesizer

•

The timing and polarity of the latch enable bits

•

The selection of which synthesizer to program

Programming of the synthesizers is accomplished by writing to four microcontroller-mapped data registers.
These registers are chained to form a 32-bit data shift register that can be operated in either shift left or shift
right mode. This register set can accommodate various formats of synthesizer control data. When fewer than
32 bits of data are to be transmitted, the significant data bits must be justified such that the first bit to be
transferred is either the LSB or the MSB of the register set, as defined by the control register for LSB or MSB
first operation. All 32 bits of the data register are transmitted each time. See Table 17 for register location. See
Figure 6 for a representative block diagram of the frequency synthesizer interface.

-I
"tJ

m
<

•
TEXAS
INSTRUMENTS
8-22

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

frequency synthesizer interface (continued)
CLKPOL
NUMCLKS
Control
Registers

LOWVAL
HIGHVAL
Ready
and
Tim ing Log ic

SEL[2:0]
MSB/LSB FIRST

~s~v;:rNCiRDrvyVT.TO::M;:'«;St;:a;rtC~tr~1ilRe~g~is~t::er~--L----.J

SYNDTA 4 - - - - - - - - - - - - - ,

D 1-4------,

SYNLEO

SYNLE1

SVNLE2

flC
Bus

MSB/LSB FIRST

3:
w
>
w
a:
a.

SYNCLK 4 - - - - - - 1
t1------411~

:::l
C

303.75 KHz

oa:
a.

Figure 6. Synthesizer Interface Circuit Block Diagram
The SynDataO register contains the least significant bits of the 32-bit data register. SynData3 contains the most
significant bits. The bits in the SynCtrlO, SynCtrl1, and SynCtrl2 registers are allocated as shown in Figure 8.

SynCtrlO

7-5

4-0

SEL[2:0]

LOWVAL

7-6

4-0

SynCtrl1

Reserved

MSB/LSB
FIRST

HIGHVAL

7-6

4-0

SynCtrl2

Reserved

CLKPOL

NUMCLKS

Figure 7. Contents of SynData Registers
Table 15 identifies the meaning of each of the bit fields in SynCtrl[2:0] .

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-23

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

frequency synthesizer interface (continued)
In the status register MStatCtrl, two bits, SYNOL and SYNRDY, are dedicated to the synthesizers. The first is
an out-ot-Iock indicator that comes trom the SYNOL input terminal. If the SYNOL input terminal is connected
to the OR of the out-of-Iock signals trom the external synthesizers, the lock condition of the synthesizers can
be monitored by reading the MStatCtrl register. A high on SYNOL also prevents the PAEN output from being
asserted and forces the TXI and TXQ outputs to zero. The SYNRDY bit, active high, indicates when the
synthesizer interface is idle and ready for programming. When SYNRDY is low, the synthesizer interface is busy.
Controlling the synthesizer interface is straightforward. The microcontroller checks to see if the SYNRDY bit
is low. When it is low, the synthesizer interface is not ready. When SYNRDY goes high, the microcontroller
programs the desired information into the four registers. When the microcontroller write to the SynCtrl2 register
is complete, the synthesizer interface sets the SYNRDY bit low and begins to send data, clock, and latch enable
according to the format established in the registers. SYNRDY returns high when the entire operation is
.
complete.
Table 15. Synthesizer Control Fields
DESCRIPTION

NAME

=1, the SYNCLK signal is a positive-going, 50% duty cycle pulse. CLKPOL =0 reverses the polarity

CLKPOL

1 Bit. When CLKPOL
of SYNCLK.

NUMCLKS

HIGHVAL

This 5-bit field defines when the strobe signal for the selected synthesizer is driven high. This number is the bit number at
which the signal changes state. Bits being transferred on SYNDTA are sequentially designated 0, 1, ... 31, independent
of any MSB/LSB selection.

-I

LOWVAL

The value written into this 5-bit field affects the strobe signal for the selected synthesizer. This number is the bit number at
which the strobe signal is driven low. The first bit transferred out of the serial interface is defined to occur at bit-time 0,
independent of any MSB/LSB selection.

MSB/LSB FIRST

Writing a 0 to this bit causes the LSB (SynDataO[O]) to be the first bit sent to the SYNDTA terminal of the serial synthesizer
interface. Writing a 1 to this bit programs the block for MSB first operation (SynData3[7]).

SEL[2:0]

3 Bits. Select which synthesizer strobe line is active. A 1 in any of these bits activates the corresponding latch enable.

"tJ

o
C

"tJ

<
-

Up to 31 data bits plus a latch enable (SYNLEO,1 ,2) can be programmed in one programming cycle. If greater
than or equal to 32 bits of data must be programmed, TI recommends using two or more programming cycles
with data in each cycle and a latch enable in the final programming cycle. Two or more programming cycles are
recommended because all programming cycles must contain at least one SYNCLK pulse, whereas the latch
enable can be suppressed in any programming cycle .

•
TEXAS
INSTRUMENTS
8-24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

frequency synthesizer interface (continued)
Figure 9 shows an example of the synthesizer output signals. In this case, an 18-bit pattern, Ox10664, was
chosen to write into synthesizer 1 with a positive-going latch enable pulse at the eighteenth bit. In order to do
so, the microcontroller writes the values OOh into SynDataO, OOh into SynData 1, 99h into SynData2, 41 h into
SynData3, 52h into SynCtrlO, 31 h into SynCtrl1, and 32h into SynCtrl2.
SYNCLK

SYNDTA

~__________________~
o

SYNLE1

______________~nL

SYNLEO,2 ____________________________________________________________________________

SYNRDY

L . . . . . - - ._

_- - - ' ,

Figure 8. Example Synthesizer Output

power control port
For systems requiring minimum system current consumption, power can be provided to each functional part
of the TCM4300 only when that function is required for proper system operation. To accomplish this, the
TCM4300 provides six external power control signals accessible through the DStatCtrl and MStatCtrl registers.
These signals can be used to minimize the on time of the functional units. These power control signals are
SCEN, FMRXEN, IQRXEN, TXEN, PAEN, and OUT1 (see Table 16). The polarity of each of these signals is
high enable, low disable.
Table 16. External Power Control Signals
NAME

SUGGESTED EXTERNAL APPLICATION

RESET
VALUE

SCEN

Speech codec (microphone/speaker interface circuit) enable

FMRXEN

FM demodulator enable

IQRXEN

I and Q receive enable. Enables QPSK demodulator and AGC amplifier

TXEN

Transmit enable. Enables power to the transmitter signal processing
circuits: QPSK modulator, voltage-controlled amplifier, driver amplifier,
PA negative bias. This signal can be used to enable these subsystems
only during the TX burst in digital mode.

OUT1

User defined

PAEN

Power amplifier enable. Enables power to PA.

In addition to allowing control of power to external functional modules, these power control bits combined with
other control bits are used to control internal TCM4300 functions. This control system is shown in Figure 12.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-25

s:w

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w
a::

c.
o

I:J

o
a::

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

power control port (continued)
WBD_ON

I---=-----~..----~

WBD Demodulator Circuit

~----+------------------------------------

OUT1

FMRXEN
SC Clock Generation
SCEN
r-----~~~--~~~~--~~------------------------FMRXEN
FMVOX
DStatCtrl

SCEN

~--------------------------- FMRXEN
,...----_e_.

Q-Side Input MUX
Q-Side RX Enable

OUT1

I-Side RX Enable

VHR High Drive Enable
(Hi-Z when disabled)

IQRXEN

~~~--------------~----------------~-----------IQRXEN

TXEN

~~~--------------~----------------~-----------TXEN

MODE

J--!!.=-=--~..-----e----+-~

TXGO

"tJ
:IJ

TX and RX Filter Select
TX Signal Processing
PWRCONT, Enable (Hi-z When Disabled)

~-+--~~-4--------~~---------------------------SYNOL

-I
"tJ
:IJ

MStatCtrl

Transmitter
Control
Circuits

~-------------------

PAEN

~--------------------~---------------------------TXONIND

m
:S

MPAEN

Figure 9. Internal and External Power Control Logic

To allow for further system power savings, the TCM4300 receive I and a channels are enabled separately
because only the a side is used in analog mode. The FMVOX bit controls the a-side input multiplexer. When
FMVOX is high, the ap side of the receiver is connected to the FM input terminal, the ON input is connected
to the VHR reference voltage, and the a side of the receiver is powered up. The MODE bit controls the a-side
filter characteristics for digital or analog mode. The IORXEN bit enables both the I and 0 receiver sides. The
bit IORXEN can be set high while still in analog mode (FMVOX high or MODE low) to allow sufficient power-up
settling time for the external receiver I and a circuits.
Setting the MODE bit low connects RXOP to the FM input and RXON to VHR.
In the digital mode (MODE bit set high), setting IORXEN high turns on both sides of the receiver. The TXEN
enables the internal TX functions. When the TXEN bit is set low, the PWRCONT output goes to a
high-impedance state and the PAEN output is set low. The TXEN signal can be used to power down most of
the external transmit circuits between transmit bursts.
In the analog mode, (MODE bit set low), PAEN is high wheneverTXEN is active and SYNOL is low. The SYNOL
input can be used as an indication to the TCM4300 that the external synthesizers are out of lock. The PAEN
signal is gated by SYNOL to prevent off-channel transmissions.
The TXEN, IORXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the
DStatCtrl register with the internal SINT. The effect of a write to the DStatCtrl register on these signals does not
appear until the next SINT after the write.

~TEXAS

INSTRUMENTS
8-26

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

microcontroller-DSP communications
The microcontroller and the DSP communicate by means of two separate 32-byte first-in first-out (FIFO) buffers.
Figure 13 illustrates this scheme. The microcontroller writes to FIFO A, but data read from the same address
comes from FIFO B. On the DSP side, the situation is reversed.
To send data to the DSP, the microcontroller writes data to FIFO A. To indicate to the DSP that FIFO A is ready
to be read, the microcontroller writes a 1 to the Send-C bit of the microcontroller interrupt control register
MlntCtrl. When this happens, the DSP interrupt line CINT goes active, signaling to the DSP that data is waiting.
At the same time, the value that can be read from the Clear-C bit in the DlntCtrl register goes from 0 to 1,
indicating that the interrupt is pending. When the DSP writes a 1 to the Clear-C bit, the CINT line returns to the
inactive state and the value that can be read from Clear-C is O. The microcontroller cannot deassert the CINT
line.
The microcontroller-DSP communications interface is symmetric. Data sent from the DSP to the microcontroller
is handled as described above, with the roles of A and B FIFOs and C and D bits and interrupts reversed. If the
number of reads exceeds the number of writes from the other side, the values read are undefined.
Send CINT,
CINT Status,
Clear DINT

FIFO A

:>
w
a:
a..

FIFO B

I-

Send DINT,
DINT Status,
Clear CINT

::J
C

oa:

Figure 10. Microcontroller-DSP Data Buffers

a..

~TEXAS

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-27

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

microcontroller register map
The microcontroller can access 17 locations within the TC[v14300. The register locations are 8 bits wide, as
shown in Table 17 and Table 18.

Table 17. Microcontroller Register Map

"tJ

WBDCtrl

WBD_LCKD

OOh

WBD

MSB

01h

FIFO

MSB

02h

MlntCtrl

ClearWBD

03h

SynDataO

MSB

LSB

04h

SynData1

MSB

LSB

OSh

SynData2

MSB

LSB

06h

SynData3

MSB

07h

SynCtrlO

08h

SynCtrl1

Reserved

MSB/LSB FIRST

HIGHVAL

09h

SynCtrl2

Reserved

CLKPOL

NUMCLKS

Reserved

MSB

OCh

BAT AID

MSB

ODh

LCD D/A

MSB

OEh

MStatCtrl

SYNOL

OFh

TXIOffset

10h

TXQ Offset

Clear-F

Clear-D

Send-C

AGCEN

AFCEN

LSB

I FMRXEN I Reserved

LOWVAL

LSB
LSB
LSB
LSD

I TXONIND

I
I

Reserved

=:s

MCLKEN

Reserved

Sign

MSB

LSB

Reserved

Sign

MSB

LSB

AOOR

NAME

OOh

WBDCtrl

CVRDY

AuxFS1

OOh

WBD

01h

FIFO

CATEGORY
Wide-band data

AuxFSO

RIW
W
R

FIFO A(B) microcontroller to DSP (DSP to microcontroller)

W/(R)

02h

MlntCtrl

03h

SynDataO

04h

SynData1

05h

SynData2

06h

SynData3

07h

SynCtrlO

08h

SynCtrl1

09h

SynCtrl2

OAh

MCClock

Microcontroller clock speed

OBh

RSSI AID

RSSllevel

OCh

BAT AID

Battery level monitor

ODh

LCD D/A

LCD contrast control

OEh

MStatCtrl

Miscellaneous status/control

OFh

TXIOffset

10h

TXQOffset

Interrupt/control status

RIW

W
Synthesizer interface

Transmit dc offset compensation

RIW
W
W

•
TEXAS
INSTRUMENTS
8-28

LCDEN

SYNRDY

Table 18. Microcontroller Register Definitions

LSB

MSB

SEL[2:0]

MCClock

01
Reserved

LSB

RSSI AID

"tJ

WBD_BW

FIFO A(B) Microcontroller to DSP (DSP to Microcontroller)

OBh

OOh

I WBD_ON

OAh

o-I

NAME

AOOR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MPAEN

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

wide-band data/control register
This register is used for two functions, depending on whether it is being read from or written to. When read from,
the register provides the latest 8 bits of received and demodulated data to the microcontroller. When it is written
to, the bits are placed into the WBDCtrl register (see Table 17) as shown here:
7

2-0

5-3

Reserved

WBDCtrl

When the WBDCtrl register is read, bit 7 (MSB) is the last received data bit.
The definition of the WBDCtrl register, according to the DSP register map, is shown in Table 19.

Table 19. WBDCtrl Register
BIT

R/W

FUNCTION

RESET VALUE

R/W

WBD_LCKD

Wide-band data lock data. Determines whether edge detector is locked (1) or unlocked (0).

R/W

WBD_ON

Wide-band data on. Turns the WBDD module on/off (1/0).

7-5

R/W

WBD_BW[2:0]

Wide-band data bandwidth. Sets the appropriate PLL bandwidth.
20 Hz
000 :
001 :
39 Hz
78 Hz
010 :
156 Hz
011 :
313 Hz
100 :
101 :
625 Hz
110 : 1250 Hz

110

Reserved

4-0

NAME

->w
W

a:
a.
Jo

microcontroller status and control registers

MCClock: This location is used by the microcontrollerto change the speed of its own clock. The division modulus
is equal to a binary coded value written into this register. Only bits [5:0] are significant. After reset, MCClock is
equal to MCLKIN/32. Division modulus 2-32 are valid (0,1 are prohibited). The clock speed change occurs after
the write is complete.
MlntCtrl Bits [7:4]: These bit names in this field indicate the resulting action when the bit is set to 1. When these
bits are being read, a 1 indicates that the corresponding interrupt is pending. A 0 indicates that the interrupt is
clear. Writing a 0 into any bit location has no effect.
MlntCtrl Bits [3:1]: These bits enable power to the AGC and AFC DACs and their corresponding outputs.
FMRXEN can be used to assert (set to 1) the FMRXEN external function. The reset value is 0 (off).

MlntCtrl

ClearWBD

Clear-F

Clear-D

Send-C

AGCEN

AFCEN

FMRXEN

R/W

RIW

R/W

RIW

Reserved

MStatCtrl: This register contains various signals needed for system monitoring and control (see Table 20).

MStatCtrl

SYNOL

TXONIND

SYNRDY

MCLKEN

CVRDY

AuxFS1

AuxFSO

MPAEN

R/W

RIW

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-29

c
o

II:

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

microcontroller status and control registers (continued)
Table 20. MStatCtrl Register Bits
R/W

BIT

"tJ

::rJ

NAME

FUNCTION

RESET VALUE

Ext. pin

SYNOL

Synthesizer out of lock. Equal to level applied to SYNOL input pin. Can be used as an input for
an externally generated status signal to prevent transmission when external synthesizers are out
of lock. In digital mode, when SYNOL is high, PAEN will not be asserted and no signal can be
transmitted from TXIP, TXIN, TXQP, and TXQN.

TXONIND

Transmitter on indicator. Equal to level applied to TXONIND input pin. Can be used to indicate
power is applied to power amplifier.

Ext. pin

SYNRDY

Synthesizer interface ready to be programmed by the microcontroller. When a 1, the
microcontroller can program the frequency synthesizer interface. A 0 indicates the interface
circuit is busy.

R/W

MCLKEN

MCLKOUT enable. When set to 1 by the microcontroller, the 38.88-MHz master clock is sent out
via MCLKOUT. Writing 0 to this bit disables MCLKOUT signal.

CVRDY

Conversion ready. A 1 indicates that the latest RSSI or battery voltage AID conversion is complete
and can be read from the RSSI or battery register location. Goes to 0 when microcontroller reads
from either of these locations.

r---

AuxFS[1]

R/W

1
0

AuxFS[O]

R/W

MPAEN

Auxiliary DACs full-scale select. The auxiliary DACs are AGC, AFC, PWRCONT and also LCD
CONTR DAC. The microcontroller selects the full-scale output ranges with these bits. See
Table 12 and Table 13 for bit-to-output range mapping.
Microcontroller PA enable. A 0 indicates the external PA enable line PAEN is prevented from going
active. See Figure 12.

0
0
0

TXI Offset and TXQ Offset: These registers allow the differential offset voltages TXIP - TXIN and TXQP - TXQN
to be adjusted to compensate for internal and/or external offsets. The magnitude of adjustment is 0 x step size,
where 0 is a 6-bit, 2s complement integer written into bits 5-0 of these registers (see Table 6).

o-I

"tJ

::rJ

m
<
-

TXI(Q) Offset

7-6

5-0

Reserved

TXI(Q) Offset Value

LCD contrast
The LCD contrast register allows for 16 levels of control of terminal LCD contrast. The register is input to the
LCD contrast O/A allowing control of the level of intensity of the LCD display.

LDC D/A

7-4

3-1

LCD Contrast

Reserved

~'TEXAS

INSTRUMENTS
8-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

DSP register map
The register map accessible to the DSP port is shown in Table 21 and Table 22. There are 14 system
addressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A.
Figure 14 details the connection of TCM4300 to an example DSP.

Table 21. DSP Register Map

NAME

DOh

WBO

MSB

01h

WBOClrl

WBD_LCKD

WBD_ON

02h

RXI

Sign

MSB

LSB

03h

RXQ

Sign

MSB

LSB

04h

TXI

Sign

MSB

LSB

OSh

TXQ

Sign

MSB

LSB

AOOR

LSB

WBD_BW

Reserved

06h

FIFO

MSB

07h

DlnlClrl

ClearWBD

FIFO A(B) microconlroller 10 DSP (DSP 10 microconlroller)

08h

TimingAdj

MSB

09h

AGCDAC

MSB

LSB

Reserved

OAh

AFC DAC

MSB

LSB

Reserved

OBh

PWR DAC

MSB

LSB

Reserved

OCh

DSlalClrl

TXGO

ODh

BSTOffsel

SOlS

I Clear-C I Send-D I

Send-F

LSB

Reserved

Reserved
LSB

MODE

SCEN

I FMVOX I FMRXEN I IQRXEN I

TXEN

OUT1

Reserved

RXOF

ALB

MSB

LSB

a..

Table 22. DSP Register Definitions
AD DR

NAME

OOh

WBD

01h

WBDCtrl

02h

RXI

03h

RXQ

CATEGORY
Wide-band data

OSh

TXI

TXQ

:::l

RX channel NO results

a
a::

Digital mode: 1t/4 DQPSK modulator input data
Analog mode: TXQ D/A data
Digital mode: Not used
FIFO A(8) microcontroller to DSP (DSP to microcontroller)

FIFO
DlntCtrl

08h

Timing Adj

Symbol timing adjust

09h

AGC DAC

AGC

OAh

AFC DAC

AFC

OBh

PWR DAC

Power control

DStatCtrl
8STOffset

Interrupt control/status

Miscellaneous status/control
TOM burst offset

a..

07h

OCh

o
c

R/W

06h

ODh

I-

RIW

Wide-band data control

Analog mode: TXI D/A data
04h

w
5=
w
a::

R/(W)

R/W

RIW
W

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-31

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

wide-band data registers
Bit 9 of the wide-band data register is the most recently received bit.

WBD

9-2

1-0

WB Data

Reserved

7-5

4-0
Reserved

RNJ

base station offset register
BST offset values are 00, 01, 10, and 11, which correspond to an offset value d of 0, 1, 2, and 3, respectively.
BST

"'C

9-2

1-0

Reserved

Offset[1:0]

Offset

The delay in the TCM4300 TX channels is increased by the amount

-I

T SINT

DSP status and control registers

OlntCtrl, Clear and Send Bits: The bit names in the OlntCtrl register indicate the action to be taken when a 1
is written to the respective bit. When these bits are being read, a 1 indicates that the corresponding interrupt
is pending. A 0 indicates that the interrupt is not pending. Writing a 0 to any bit has no effect. Writing a 1 to the
clear bits clears the corresponding interrupt, and the interrupt terminal returns to its inactive level. Writing a 1
to the send bits causes the corresponding interrupt to go active.

<
-m
:E

OlntCtrl, SOlS: When a 1 is written to the SOlS bit, the SINT interrupt going to the OSP is disabled. The disabling
and re-enabling function is buffered to prevent the SINT signal from having shortened periods of output active.
The SOlS bit is active (1) upon reset.
7

4-0

DlntCtrl

Reserved
RNJ

DStatCtrl

TXGO

MODE

SCEN

FMVOX

I FMRXEN

IIQRXEN

RNJ

~TEXAS

INSTRUMENTS
8-32

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TXEN

OUT1

RXOF

ALB

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

DSP status and control registers (continued)
The DStatCtrl register contains various signals needed for system monitoring and control. These are described
in Table 23.

Table 23. DStatCtrl Register Bits
BIT

R/W

NAME

FUNCTION

RESET VALUE

TXGO

Transmitter go. Used in digital mode to initiate (1) and terminate (0) a transmit burst.

0
0

R/W

MODE

Digital (1) - Analog (0) mode select. Affects the clock dividers and the transmitter modes of
operation and the Q side filter.

R/W

SCEN

Speech codec enable. (microphone/speaker interface chip.) The SCEN output pin is connected
to this bit. Also enables (1) or disables (0) the intemal speech codec clock generation circuits.
(2.048 MHz - 8 kHz outputs)

R/W

FMVOX

FM voice enable. FMVOX = 1 enables the Q side of the intemal receiver circuits and connects the
receivers Q channel input to FM input pin (see Figure 12).

R/W

FMRXEN

FM receiver enable. The FMRXEN output pin is connected to this bit (see Figure 12).

R/W

IQRXEN

I and Q receiver enable. The IQRXEN output pin is connected to this bit. Enables (1), disables (0)
power to the I and Q sides of the internal receiver circuits (see Figure 12).

R/W

TXEN

Transmitter enable. The TXEN output pin is connected to this bit. Enables (1), disables (0) power
to the internal transmitter circuits (see Figure 12).

OUT1

Output 1. User-defined general purpose data or control signal.

R/W

RXOF

Receive channel offset. RXOF=1 disconnects the RXIP, RXIN, RXQP, and RXQN pins from
receive channel, and shorts internal RXIP to RXIN and RXQP to RXQN. It provides the capability
of measuring the dc offset of the receive channel.

ALB

Analog loop-back. ALB=1 disconnects the RXIP, RXIN, RXQP, and RXQN pins from the internal
receive channels and connects the corresponding internal signals to attenuated copies of the
TXIP, TXIN, TXQP, and TXQN signals. The attenuated factor is 8.

R/W

DSPD[9:0]

DSPA[3:0]
DSPCSL
TCM43 00

DSPRW
DSPSTRBL
SINT

....

:;:
w

a::

0..
I-

o
c

D[15:6]

:::J

A[3:0]

a
a::

....

R/W

...""

3:
w

0..

DSP

STRB
INT1

CINT

INT3

BDINT

INT4

Figure 11. DSP Interface

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-33

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS010E - DECEMBER 1994 - REVISED JUNE 1996

reset
internal reset
A low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on reset circuit
also causes internal reset. However, the logic level at RSINL has no effect on reset outputs RSOUTH and
RSOUTL.

power-on reset
The power-on reset (POR) is digitally implemented and provides a timed POR signal at RSOUTL and RSOUTH.
The POR pulse duration is equal to 388,800 cycles of MCLKIN (10 ms). There are two outputs to provide a high
reset and a low reset in order to accommodate the reset polarity requirements of any external device. The
TCM4300 internal registers are reset when the POR outputs are activated. See Figure 12.

oVoo

I
14---

RSOUTH

-a

/190%

_ _ _ _ ~_ _ _ J

RSOUTL

-I

90%

i\
I

~----

:IJ

c:
o

tw
10 ms Minimum {

10%Y

;--\l10%

Figure 12. Power-On Reset Timing
internal reset state

"tI
:IJ

After power-on reset, the TCM4300 register bits are initialized to the values shown in Table 25. The synthesizer
control pins SYNCLK, SYNLE[0:2], and SYNDTA are high after reset, and the synthesizer interface circuit is
in the stable idle state with no SYNCLK outputs.

m
<
-

Table 24. Power-On Reset Register Initialization
BIT9

DlntCtrl

DStatCtrl

ext

MlntCtrl
MStatCtrl
MCClock
r: reserved
ext: bit value from external pin

~TEXAS

INSTRUMENTS
8-34

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

microcontroller interface
The microcontroller interface of the TCM4300 is a general purpose bus interface which ensures compatibility
with a wide range of microcontrollers, including the Mitsubshi M37700 series and most Intel and Motorola series.
The interface consists of a pair of microcontroller type select (MTS[1 :0]) inputs, address and data buses, as well
as several input and output control signals that are designed to operate in a manner compatible with the
microcontroller selected by the user.
Table 25. Microcontroller Interface Confirguration
POLARITY

MTS1

MTSO

Intel

Motorola 16-bit and Mitsubishi

Low

Motorola a-bit

High

Low

Reserved

N/A

MODE

DATA STROBE (OS) ACTIVE

INTERRUPT/OUTPUT ACTIVE

Low (separate read and write)

High

The microcontroller interface of the TCM4300 is designed to allow direct connection to many microcontrollers.
Except for the interrupt pins, it is designed to connect to microcontrollers in the same manner as a memory
device.
The internal chip select is asserted when MCCSH = 1 and MCCSL = O.

Intel microcontroller mode of operation
When the microcontroller type select (MTS[1 :0]) inputs are both held low, the TCM4300 microcontroller
interface is configured into Intel mode (see Table 25). In this mode, the interface uses separate read and write
control strobes and active-high interrupt signals. The processor RD and WR strobe signals should be connected
to the TCM4300 MCDS signal and MCRW signal, respectively. The multiplexed address and data buses of the
microcontroller must be demultiplexed by external hardware. Table 27 lists the microcontroller interface
connections for Intel mode.

Tie to logic levels: low and low, respectively

MCCSH

Not on microcontrolier; can be used for address decoding

MCCSL

Not on microcontrolier; can be used for address decoding

MCD[7:0]

AD[7:0] data bus on microcontroller

MCA[4:0]

Demultiplexed address bits not on microcontrolier

MCRW

WR (Active-low write data strobe)

MCDS

RD (Active-low read data strobe) MCDS configured to active-low operation by MTS[1 :0].
The microcontrolier bus must be demultiplexed by external hardware.

MWBDFINT

One of INT[3:0] as appropriate

DINT

One of INT[3:0] as appropriate

D..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

::l
C

MICROCONTROLLER PIN

MTS[1:0]

D..
I-

Table 26. Microcontroller Interface Connections for Intel Mode
TCM4300 PIN

w
5>
w
a:

8-35

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 DE - DECEMBER 1994 - REVISED JUNE 1996

Mitsubishi microcontroller mode of operation
When the microcontroller type select (MTS[1 :0]) inputs are held high and low, respectively, the TCM4300
microcontroller interface is configured into Mitsubishi mode. In this mode, the interface has a single read/write
control (R/W) signal, an active-low data strobe (MCDS) signal, and active-low interrupt request signals. The
processor E and R/(W) signals should be connected to the TCM4300 MCDS signal and the MCRW signal,
respectively. Table 28 lists the microcontroller interface connections for Mitsubishi mode.

Table 27. Microcontroller Interface Connections for Mitsubishi Mode
TCM4300 PIN
MTS[1:0]

"tJ

MICROCONTROLLER PIN
Tie to logic levels: high and low, respectively

MCCSH

Not on microcontroller; can be used for address decoding

MCCSL

Not on microcontroller; can be used for address decoding

MCD[7:0]

D[7:0] data bus on microcontroller

MCA[4:0]

A[4:0]

MCRW

RIW

MCDS

E (Active-low read data strobe) MCDS configured to active-low operation by MTS[1 :0].

MWBDFINT

One of INT[3:0] as appropriate

DINT

One of INT[3:0] as appropriate

-I
"tJ

::D

:$
m
~

~TEXAS

INSTRUMENTS
8-36

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

Motorola microcontroller mode of operation
When the microcontroller type select MTSO = high and MTS1 = low, the TCM4300 microcontroller interface is
configured for 8-bit family (6800 family derivatives, e.g., 68HC11 03 and 68HC11 G5) bus characteristics, and
when the microcontroller type select MTSO = low and MTS1 = high, the microcontroller interface is configured
for 16-bit family (680 x 0 family derivatives, e.g., 68008 and 68302) characteristics. The Motorola mode makes
use of a single read/write control (R/W) signal and active-low interrupt request signals. The processor E (8 bit)
or OS (16 bit) and (R/W) control signals should be connected to the TCM4300 MCOS signal and the MCRW
signal, respectively. Table 29 illustrates the connections between the TCM4300 and an 8-bit Motorola
processor. Table 30 illustrates the connections between the TCM4300 and a 16-bit Motorola processor.

Table 28. Microcontroller Interface Connections for Motorola Mode (8 bit)
TCM4300 PIN

MICROCONTROLLER PIN

MTS[1:0]

Tie to logic levels: low and high, respectively

MCCSH

Not on microcontroller; can be used for address decoding

MCCSL

Not on microcontroller; can be used for address decoding

MCD[7:0]

PC[7:0] data bus on microcontroller

MCA[4:0]

Demultiplexed address output. PF[4:0] on microcontroller for non multiplexed machines
(e.g., 68CH11G5) and not on micro for multiplexed bus machines (e.g., 68HC11D3).

MCRW

RIW

MCDS

E (Active-high data strobe) MCDS configured to active-high operation by MTS[1 :0].

MWBDFINT

IRQ and/or NMI as appropriate

DINT

IRQ and/or NMI as appropriate

:s:w

:>
w
a:
a..

Table 29. Microcontroller Interface Connections for Motorola Mode (16 bit)
TCM4300 PIN

MICROCONTROLLER PIN

MTS[1:0]

Tie to logic levels: high and low, respectively

MCCSH

Not on microcontroller; can be used for address decoding

MCCSL

Not on mici-ocontroller (68000, 68008) CS1, CS2, or CS3 (68302)

MCD[7:0]

D[7:0] data bus on microcontroller

MCA[4:0]

A[4:0] (68008)

O
::l
C

a:
a..

A[5:1] (68000, 68302)
MCRW

RIW

MCDS

DS (active-low data strobe) (68008)
LDS (active-low data strobe) (68000, 68302) MCDS configured to active-low operation
by MTS[1:0]

MWBDFINT

IACK7, IACK6, or IACK1 (68302)
Not on microcontroller (68000, 68008)

DINT

One of INT[3:0] as appropriate

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-37

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: DVoo (see Notes 6 and 7): Condition 1 ...................... Vss -0.3 to +6 V
Condition 2 ............... Vss -0.3 to AVOD +0.3 V
AVOD (see Notes 7 and 8): Condition 1 ...................... VSS -0.3 to +6 V
Condition 2 .............. Vss -0.3 to DVoo +0.3 V
Input voltage range, VI: Digital signals .................................... Vss -0.3 to DVoo +0.3 V
Analog signals .................................... Vss -0.3 to AVOD +0.3 V
Output voltage range, Yo: Digital signals ............................................. VSS to DVoo
Analog signals ............ '" .............................. VSS to AVOD
Continuous total power dissipation ........................................... See Dissipation Table
Operating free-air temperature range, TA ........................................... -40°C to 85°C
Storage temperature range, Tstg .................................................. -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ............................... 260°C
NOTES:

6. Voltage values are with respect DVSS.
7. Maximum voltage is the minimum of the two conditions.
8. Voltage values are with respect to AVSS.
DISSIPATION RATING TABLE

""CJ

o
c
c:

PACKAGE

TA ~ 25°C
POWER RATING

DERATING FACTOR (TJA)
ABOVE TA 25°C

TA 85°C
POWER RATING

2222 mW

45°CNJ

889mW

recommended operating conditions

MIN

MAX

UNIT

5.5

-I

DVDD

Supply voltage

""CJ

VIH

High-level input voltage

Digital

VIL

Low-level input voltage

Digital

VOH

High-level output voltage

Digital

VOL

Low-level output voltage

Digital

IOH

High-level output current at 3 V

Digital

rnA

IOL

Low-level output current at 3 V

Digital

rnA

IOH

High-level output current at 5 V

Digital

rnA

IOL

Low-level output current at 5 V

Digital

Operating free-air temperature

::D

0
0.7 DVDD

-40

~TEXAS

INSTRUMENTS
8-38

0.7 DVDD

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DVDD+0.3

0.3 DVDD

DVDD

0.5

rnA
85

°C

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

electrical characteristics power consumption over full range of operating conditions (unless
otherwise noted)
PARAMETER
Analog transmitting and receiving

Oigital receiving

Oigital transmitting

Idle mode

AVOO= 3 V

OVOO = 5.5 V,

AVOO = 5.5 V

OVOO = 3 V,

AVOO= 3 V

OVOO = 5.5 V,

AVOO = 5.5 V

OVOO = 3 V,

AVOO = 3 V

OVOO = 5.5 V,

AVOO = 5.5 V

TYPt

AVOO =3 V
AVOO =3 V

MCLKOUT enabled

OVOO = 5.5 V,

AVOO = 5.5 V

190
96

Oigital mode, 1/3 transmitting +1/3 receiving + 113 standby

AVOO= 3 V

OVOO = 5.5 V,

AVOO = 5.5 V

300

OVOO = 3 V,

AVOO = 5.5 V

250

OVOO= 3 V,

OVOO = 5.5 V,

UNIT
mW

275

MCLKOUT enabled

OVOO=3 V,

MAX

MCLKOUT disabled

MIN

TEST CONDITIONS
OVOO =3 V,

17
mW

220

All typical values are at TA = 25°C

reference characteristics
PARAMETER
VOH(VHR)
rO

TEST CONDITIONS

MIN

High-level output voltage

0.5 AVOO-O.2
FMVOX or IQRXEN or TXEN = high

Output resistance

+All typical values are at OVOO= 5 V,

TYPt:

FMVOX or IQRXEN or TXEN = low

80
15

MAX

UNIT

0.5 AVOO+0.2

100

n
kn

AVOO = 5 V, and TA = 25°C

a::

I-

terminal impedance
FUNCTION

TERMINAL NAME

MIN

TYP§

Receive channel input impedance (single-ended)

RXIP/N and RXQP/N

Transmit channel output impedance (single-ended)

TXIP/N and TXQP/N

FM input impedance

WBO

200

MCLKOUT impedance

->w
W

MCLKOUT

3.3 V

240

MCLKOUT

180

MAX

100

UNIT

::)

kn
n
kn

a
a::

§ All typical values are at OVOO = 5 V, AVOO = 5 V, and TA = 25°C, unless otherwise specified .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-39

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

MCLKOUT timing requirements
MIN

NOM

MAX

IWH

Pulse duration high

IwL

Pulse duration low

Rise lime

Fail lime

NOTE: Tested with 15 pF loading on MCLKOUT

PARAMETER MEASUREMENT INFORMATION

14-

MCLKOUT ---.....11-.

"'tJ
JJ

tw H

J,. ~ 'wL ~ ~-- VOH
i~
¥ --- VOL

--.f

~ tr

-'1 14-

Figure 13. MCLKOUT Timing Diagram

o
C

-I
"'tJ
JJ

~TEXAS

INSTRUMENTS
8-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4300 to microcontroller interface timing requirements (Mitsubishi write cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCDS)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

tsu(CS)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before
falling edge of strobe (MCDS)

TCS(SU)

tsu(R/w)

NOTE: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

I..

90% \. :
:
90%
\1..1;.;;0;.;.%;....._ _ _ _ _ _ _.......;1...;;.oo..;.;yo~/1

MCDS

tsu(R/W) -.j

-r;1 1 114-

1 I
----- 1 I

10~

MCRW

!4------¥-

MCA[4:0]

_----IX:

MCD [7:0]

MCCSH

1I 1

~ tsu(W) ---.I

_ _----I.

tsu(WA)

th(CS)~

tsu(CS) ~1"-----et~1

theW)

O
%

110...·- - - j4-

'\L

X'---_
~:
. X"--____
1

MCCSL

r----

-------"T.-------'X
901t

th(R/W)

I y,0%

1 I..

(WA)

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 14. Microcontroller Interface Timing Requirements
(Mitsubishi Configuration Write Cycle, MTS[1 :0] 10)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5>
w

a:
a..
....o
::)
c
oa:
a..

tw(WSTB)

==
w

8-41

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS010E- DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4300 to microcontroller interface timing requirements (Mitsubishi read cycle)
ALTERNATE
SYMBOL

PARAMETER

'tJ
:rJ

o
C

-I
'tJ

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

TRW(SU)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(RA)

Setup time, read address

Read address (MCS) stable before falling edge of
strobe (MCDS)

TRA(SU)

th(RA)

Hold time, read address

Read address (MCA) stable after rising edge of
strobe (MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4300 driving
data bus (MCD)

TRD(EN)

tv(R)

Read data valid time

Falling edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe
(MCDS)

TRD(INV)

tdis(RD)

Disable time, read data

TCM4300 releases data bus after rising edge of
strobe (MCDS)

TRD(DIS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before
falling edge of strobe (MCDS)

TCS(SU)

th(CS)
tsu(CS)

NOTE: Timings are based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

\ . 90%
MCDS

:rJ

m
S
m

tsu(R/W)

~
I

90~o

100/1 i

10%
I"-----------J~I

I4t

1"1 14-I

I I

MCRW

th(R/W)

~D%

MCD [7:0]

MCCSH

----'if
tsu(CS)

MCCSL

90%

i90%~,,-_ _ _ __

~~t----.!.I

th(CS)

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 15. Microcontroller Interface Timing Requirements
(Mitsubishi Configuration Read Cycle, MTS[1 :0] 10)

•
TEXAS
INSTRUMENTS
8-42

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4300 to microcontroller interface timing requirements (Intel read cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read address

Read address (MCA) stable before falling edge of
strobe (MCDS)

TRA(SU)

Hold time, read address

Read address (MCA) stable after rising edge of
strobe (MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4300 driving
data bus (MCD)

TRD(EN)

tv(RD)

Valid time, read data

Falling edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe
(MCDS)

TRD(INV)

tdis(RD)

Disable time, read data

TCM4300 releases data bus after rising edge of
strobe (MCDS)

TRD(DIS)

tsu(CS)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

tsu(RA)
th(RA)

:>
w

NOTE: Timings are based upon Intel80C186 (16 MHz).

MCDS

~ 90%

1\
I

10%

90~/f

a:
c..

1I Ii

100/

3:
w

I-

MCRW

:J
C

a:
c..

MCCSL

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 16. Microcontroller Interface Timing Requirements
(Intel Configuration Read Cycle, MTS[1 :0] =00)

"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-43

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4300 to microcontroller interface timing requirements (Intel write cycle)
ALTERNATE
SYMBOL

PARAMETER

"'tI

MIN

MAX

UNIT

tsu{WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCRW)

TWA{SU)

th{WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCRW)

TWA{HO)

tsu{W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCRW)

TWD{SU)

th{W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCRW)

TWD{HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

tsu{CS)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCRW)

TCS{SU)

th{CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCRW)

TCS{HO)

NOTE: Timings are based upon Intel8C186 (16 MHz).

:IJ

MCDS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

c:
o

~~-------tw(WSTB)------~.~1

90% "\
1

"'tI

!4------¥-

:IJ

m
<
m

MCA [4:0]

_~X

MCRW

-I

¥III

10%

90%

10% _

~-----------------t

su(WA)

1 I~

~ tsu(W) - '

--JX

MCD [7:0] ______________..,..__________

th(WA)

X'---_

' - -I: theW)

. X'-____

:
MCCSH

901f
_ _ _ _----I.

I 1

tsu(CS) ---l4-1~-~.1

th(CS) ~

MCCSL

t\0%
1 . . . . .- - - - - - - -

~
1

10%'y

10%

NOTE: Chip selection is defined as both MCCS and MCRW active.

Figure 17. Microcontroller Interface Timing Requirements
(Intel Configuration Write Cycle, MTS[1 :0] 00)

~TEXAS

INSTRUMENTS
8-44

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 DE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4300 to microcontroller interface timing requirements (Motorola 16-bit read cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(RIW)

Setup time, read/write

Read/write (MCRW) stable before falling edge of strobe
(MCDS)

TRW(SU)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after rising edge of strobe
(MCDS)

TRW(HO)

tsu(RA)

Setup time, read address

Read address (MCA) stable before falling edge of
strobe (MCDS)

TRA(SU)

th(RA)

Hold time, read address

Read address (MCA) stable after rising edge of strobe
(MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4300 driving data
bus (MCD)

TRD(EN)

tv(RD)

Valid time, read data

Falling edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe (MCDS)

TRD(lNV)

Disable time, read data

TCM4300 releases data bus after rising edge of strobe
(MCDS)

TRD(DIS)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before falling
edge of strobe (MCDS)

TCS(HO)

tsu(CS)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before rising
edge of strobe (MCDS)

TCS(SU)

tdis(RD)

NOTE: Timings are based upon Motorola 68HCOOO (16.67 MHz) and Motorola 68302 (16 MHz).
MCDS
tsu(R/W)

MCRW

~O%
I • 10%
I
--.I
I I I

lOll

I I
1·1

MCD [7:0]

;f
tsu(CS)

MCCSL

90%

r~
I
I
I
I

::J
C

~O%
~

141

~ th(R/W)

tsu(RA) .

o
a:
a.

th(RA)

tdis(RD)

t;nVT~
I
:90%,

th(CS)~

141

I I
I I
I I

:I :~tV(RD)

ten(RD)

MCCSH

90°7

10%1

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 18. Microcontroller Interface Timing Requirements
(Motorola 16-Bit Read Cycle, MTS[1 :0] =10)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I-

-HI I

i+I

MCA [4:0]

90/1
10%~

3:
w
>
w
a:
a.

8-45

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS01 OE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4300 to microcontroller interface timing requirements (Motorola 16-bit write cycle)
ALTERNATE
SYMBOL

PARAMETER

"'C

MIN

MAX

UNIT

tsu(RIW)

Setup time, read/write

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

TRW(SU)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCDS)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(HO)

tsu(CS)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(SU)

NOTE: Timings are based upon Motorola 68HCOOO (16.67 MHz) and Motorola 68302 (16 MHz).

tw(WSTB)

'II1II

-t
"'C

MCDS

tsu(R/W) ---.j

----~

MCRW

1
1

10%

\.i
10% \;I.....t-I

1 1
1 I

l I i/

(WA)

th(R/W)

~----

1 1II1II

-----IX :
----"X

901f

IX,-----

t\0%
1
1

th(CS)~

1'-·---I11III-

I
10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 19. Microcontroller Interface Timing Requirements
(Motorola 16-Bit Write Cycle, MTS[1 :0] 10)

~TEXAS

INSTRUMENTS
8-46

th(WA)

: 'X~-

-----'. I
I
tsu(CS) ---Je11llll-----.t.1
I

'x-

~ tsu(W) -.I ~ theW)

MCD[7:0] - - - - ' - - :

MCCSL

1
1

-----------"""1'""". I. ....¥ 10%

MCCSH

90%

~ ~

I
I

MCA [4:0]

I ITo

90% "\

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4300 to microcontroller interface timing requirements (Motorola 8-bit read cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(RIW)

Setup time, read/write

Read/write (MCRW) stable before rising edge of
strobe (MCDS)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after falling edge of
strobe (MCDS)

TRW(HO)

tsu(RA)

Setup time, read address

Read address (MCA) stable before rising edge of
strobe (MCDS)

TRA(SU)

th(RA)

Hold time, read address

Read address (MCA) stable after falling edge of
strobe (MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Rising edge of strobe (MCDS) to TCM4300 driving
data bus (MCD)

TRD(EN)

tv(HD~

Valid time, read data

Rising edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after falling edge of strobe
(MCDS)

TRD(INV)

tdis(RD)

Disable time, read data

TCM4300 releases data bus after falling edge of
strobe (MCDS)

TRD(DIS)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(SU)

tsu(CS)

TRW(SU)

3:
w
>
w

a::

a.
t-

NOTE: Timings are based upon Motorola 68HC11 D3 (3 MHz) and Motorola 68HC11 G5 (2.1 MHz).
MCDS

O
::l
C

MCRW

a::

MCCSH

---...,,;1
th(CS)

MCCSL

90%

190%~,-_ _ _ __

----+14----~~

tsu(CS)

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 20. Microcontroller Interface Timing Requirements
(Motorola 8-Bit Read Cycle, MTS[1 :0] = 01)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-47

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4300 to microcontro"er interface timing requirements (Motorola a-bit write cycle)
ALTERNATE
SYMBOL

PARAMETER

"'C

o
c

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (MCRW) stable before rising edge of
strobe (MCDS)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (MCRW) stable after falling edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before rising edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after falling edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before falling edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after falling edge of strobe
(MCDS)

TWD(HO)

t\\i(WSTBl

Pulse duration, write strobe

Write strobe pulse width

TWR(STB).

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(SU)

th(CS)
tsu(CS)

NOTE: Timings are based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

141
41----

-I

90%~:

90%
10% /_ _ _ . . ; . 1 0 . ; . . , ° 1 < _ 0_ _ _ _ __

MCDS

"'C

tw(WSTB)

- - - - - -..... 1

tsu(R/W)

-.j ~I

~ 141- th(R/W)
I

, I

MCRW

Oo~~·--------------------~I~I
I
I I ¥10%
i4--.l-

MCA [4:0]

___X
I

I 141

(WA)

~,~

X"--_

: :

su(w)

MCD [7:0] _ _ _ _ _ _ _-,.._ _ _ _ _ _

~:
I 'h(W1

. X'--____

MCCSH

90/1
-----'.

tsu(CS)

MCCSL

----,4I-----.t.,
,

th(CS)-.j

' { 10%

~O%
,
~

10%Y

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 21. Microcontroller Interface Timing Requirements
(Motorola 8-Bit Write Cycle, MTS[1 :0] = 01)

~TEXAS

INSTRUMENTS
8-48

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

th(WA)

TCiv14300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWS010E - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
switching characteristics, TCM4300 to DSP Interface (write cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

Setup time, read/write

Read/write (DSPRW) stable before falling edge of
strobe (DSPSTRBL)

TRW(SU)

th(RIW)

Hold time, read/write

Read/write (DSPR W) stable after rising edge of
strobe (DSPSTRBL)

TRW(HO)

tsu(CS)

Setup time, chip select

Chip select stable (DSPCSL) before falling edge of
strobe (DSPSTRBL)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (DSPCSL) stable after rising edge of
strobe (DSPSTRBL)

TCS(HO)

tsu(WA)

Setup time, write address

Address (DSPA) stable before falling edge of strobe
(DSPSTRBL)

TWA(SU)

th(WA)

Hold time, write address

Address (DSPA) stable after rising edge of strobe
(DSPSTRBL)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (DSPD) before rising edge of strobe
(DSPSTRBL)

TWD(SU)

th(W)

Hold time, write data

Data stable (DSPD) after rising edge of strobe
(DSPSTRBL)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

tsu(RIW)

DSPCSL

\10%
tsu(CS)

~ :.l4-- tw(WSTB) - - - . J . I I

'
N

------DSPSTRBL

190%

tsu(R/W) - . :

____

DSPD

10%

..J~

th(CS)

1'-

fi
1

c
a

th(R/VI)

i: J;r------

0:::

1 1

~~I I _ -~~-

IIII_._I_ts_U_(W_A_)
.....
_ _ _ _ _ _...
:

-_-_-_-_

--.--..JX~i--r-:

'h(WA)

«"'----

r------I:

tsu(W)

~f----~e.1 I
I
I I..
4

1: .... -

I
..I

.......t---1-

theW)

Figure 22. TCM4300 to DSP Interface (Write Cycle)

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

::J

90%i } - - - - - - - - 10%

\l i

DSPRW

DSPA

10%/

~ 14-

3:
w
>
w
a:
a.
fo

8-49

TCM4300
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICTM)
SLWSD1 DE - DECEMBER 1994 - REVISED JUNE 1996

PARAMETER MEASUREMENT INFORMATION
switching characteristics, TCM4300 to DSP Interface (read cycle)
ALTERNATE
SYMBOL

PARAMETER

"'tJ

:xJ

C
C

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (DSPRW) stable before falling edge of
strobe (DSPSTRBL)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (DSPRW) stable after rising edge of
strobe (DSPSTRBL)

TRW(HO)

tsu(CS)

Setup time, chip select

Chip select stable (DSPCSL) before falling edge of
strobe (DSPSTRBL)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (DSPCSL) stable after rising edge of
strobe (DSPSTRBL)

TCS(HO)

tsu(RA)

Setup time, read address

Read address (DSPA) stable before strobe
(DSPSTRBL) goes low

TWA(SU)

th(RA)

Hold time, read address

Read address (DSPA) stable after strobe
(DSPSTRBL) goes high

TWA(HO)

ten(R)

Enable time, read data

Falling edge of strobe (DSPSTRBL) to TCM4300
driving data bus (DSPD)

TRD(EN)

td(DV)

Delay read data valid time

Falling edge of strobe (DSPSTRBL) to valid data
(DSPD)

TRD(DV)

th(R)

Hold time, read data

Data (DSPD) invalid after rising edge of strobe
(DSPSTRBL)

TRD(INV)

Disable time, read data

TCM4300 releases data bus after rising edge of
strobe (DSPSTRBL)

TRD(DIS)

tdis(R)

-f
"'tJ

:xJ

DSPCSL

\'0%

10%/

--.I :.- th(CS)

tsu(CS)~ ~

<
-

1';0%

DSPSTRBL

10%

tSU(R/W)~
DSPRW

14
DSPA

10%

11
,

~th(R/W)

.',

\0%

I ,

tsu(RA)

th(RA)

,
,~
,I I

DSPD

ten(R)

~ ~

~
:

th(R)

--.!

~td(DV)

,
,III

tdis(R)

Figure 23. TCM4300 to DSP Interface (Read Cycle)

•
TEXAS
INSTRUMENTS
8-50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

50
5

ns
ns

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

•

Compliance With TIA IS-136 Dual-Mode
Cellular Standard

•

Received Signal Strength Indicator (RSSI)
and Battery-Level AID Conversion Circuitry

•

Baseband Transmit Digital-to-Analog (D/A)
Conversion and Receive Analog-to-Digital
(AID) Conversion in Analog Mode Using
Dual 1O-Bit Sigma-Delta Converters

•
•

Internal Clock Generation
Wide-Band Data Clock Recovery and
Manchester Decoding

General-Purpose Digital Signal Processing
(DSP) and Microcontroller Interface

•

3.3-V and 5-V Operation

•

Low Power Consumption

o Square Root Raised Cosine (SQRC)
Filtering in the Digital Mode Using Dual
10-Bit Sigma-Delta Converters
•

•

7tl4-Differential Quadrature Phase-Shift Key
(DQPSK) Modulation Encoder in Digital
Transmit Mode

o Backward Compatible With TCM4300
ARCTIC

Power Control Supervision for Radio
Frequency (RF) Power Amplifier, Automatic
Frequency Control (AFC), Automatic Gain
Control (AGC), and Synthesizer

description
Texas Instruments (TITM) TCM4301 18-136 advanced RF cellular telephone interface circuit (ARCTICTM136)
provides a baseband interface between digital signal processor (D8P), microcontroller, and RF
modulator/demodulator in a dual-mode 18-136 cellular telephone.
In the analog mode, the TCM4301 provides all required baseband filtering as well as transmit D/A conversion
and receive AID conversion using dual 10-bit sigma-delta converters. In addition, a WBD (wide-band data)
-10 kb/s Manchester frequency shift key (F8K) demodulator is provided to allow reduced D8P processing load
during subscriber standby mode.
In the digital mode, the TCM4301 accepts I and Q baseband data and performs AID and D/A conversion and
square root raised cosine filtering using dual 10-bit sigma-delta converters. The TCM4301 also has a
7tl4-DQP8K modulation encoder for dibit-to-symbol conversion in the digital transmit mode.
The microcontroller interface is compatible with a wide range of microcontrollers. A microcontroller can be used
to communicate with the user interface (keyboard, display, etc.) and to program up to three frequency
synthesizers by using the on-Chip synthesizer interface circuit.
The TCM4301 provides advanced power control to minimize power consumption of many dual-mode telephone
functional blocks such as the speech codec, FM receiver, I and Q demodulator, transmitter signal processor,
and RF power amplifier. In addition, the TCM4301 is designed to reduce system power consumption through
low-voltage operation and standby mode (see Table 1).
The TCM4301 is offered in the 100-pin PZ package and is characterized for free-air operation from -40°C
to 85°C.

ARCTIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW Information concerns products in the formative or
design phase of development Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

•
TEXAS
INSTRUMENTS
POST OFFiCE BOX 655303 • DALLAS. TEXAS 75265

8-51

w
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~

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

description (continued)
Table 1. Typical Power Consumption
OPERATING MODE

Analog transmitting and receiving

S.SV

75mW

275mW

Digital receiving

60mW

250mW

Digital transmitting

85mW

300mW

45mW

190mW

17mW

96mW

I MCLKOUT enabled

Idle mode

I MCLKOUT disabled

IS-136 standby (sleep mode)

15mW

85mW

Digital mode, 1/3 transmitting + 1/3 receiving +1/3 standby

60mW

220mW

PZ PACKAGE
(TOP VIEW)

a.
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wXZ....J....JC/)OOOOOOOOOOO
0
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~~~~Q~~~()66~~~~~~~~~~~oo6

:IJ

BAT
RSSI
AVDDREF
FM
RXON
RXOP
AVDDRX
RXIN
RXIP
AGC
AFC
AVSSRX
VSS
VHR
VCM
PWRCONT
TXIP
TXIN
AVDDTX
TXOP
TXON
AVSSTX
TXEN
TXONIND
PAEN

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:IJ

::sm
:e

DVDD
DSPAO
DSPA1
DSPA2
DSPA3
DSPCSL
DSPRW
DSPSTRBL
MCLKOUT
XTAL
DVSS
MCLKIN
DVDD
MCCLK
RSOUTL
RSOUTH
RSINL
MCD7
MCD6
MCD5
MCD4
MCD3
MCD2
MCD1
MCDO

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

functional block diagram
TXIP

TXI (04b)

TXIN
TX Data
Registers

TXOP
TXON

TXO(05b)

DSP
Interface
RXIP - - - - - - - - 1......
RXIN

RXI
Analog
Mode (LPF)

-----j~

02h

CONTROL
10

Data

Sample 10
Register . -.........'110..

RXON - - - - - - - - 1......
RXOP

RXO 03h
RSINL

WBD
8
Register OOh

FM ---4t-------1H

RSOUTH
RSOUTL
SINT
MCCLK
CSCLK
CMCLK
XTAL
MCLKIN
MCLKOUT

WBD
Control
AUX

Internal
Clocks

•••

AGC

AFC

Clock
Generation
and
Timing
Adjustment
Logic

--.-1

PWRCONT

Input~

Control

... Vref

PAEN

CommonT;ode

~
Gen

oun

FMRXEN
IORXEN
TXEN
SCEN
SYNOL
TXONIND

DATA
ADDRESS

--------1~

VCM

SYNLE
[2:0]

VHR
REF CAP
MWBDFINT

Synthesizer
Interface
03h -09h

RSSI----.--t

CONTROL

BAT----.--t

DATA
ADDRESS

LCDCONTR

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

:J
C

RBIAS

SYNCLK
SYNDTA

I-

DWBDINT
CINT
DINT

- - - - - j.......

3:
->W
W

8-53

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

Terminal Functions
RF interface analog signals
TERMINAL
NAME

NO.

DESCRIPTION

I/O

RECEIVE CHANNEL
FM

Input from FM discriminator analog mode voice and wide-band data

RXIN

In-phase differential negative baseband received signal

RXIP

In-phase differential positive baseband received signal

RXQN

Quadrature differential negative baseband received signal

RXQP

Quadrature differential positive baseband received signal

In-phase differential negative baseband transmit signal

TXIP

In-phase differential positive baseband transmit signal

TXQN

Quadrature differential negative baseband transmit signal

TXQP

Quadrature differential positive baseband transmit signal

BAT

Battery strength monitor

RSSI

Received signal strength indicator. Used for signal strength measurements

AGC

Automatic gain control digital-to-analog converter (DAC) output
Automatic frequency control DAC output

TRANSMIT CHANNEL
TXIN

"tJ

MONITORS

CONTROLS

(")

AFC

LCDCONTR

Liquid-crystal display (LCD) contrast control DAC output

"tJ

PWRCONT

Power amplifier (PA) power control DAC output

RBIAS

Input for bias current-setting resistor. A 100 kQ, 1% tolerance resistor to AVSS is recommended.

100

Input for reference decoupling capacitor. 3.3 IlF in parallel with 470 pF is recommended.

m
<
m
::e

BIAS SETTING

REFCAP

RF interface digital signals
TERMINAL
NAME

NO.

DESCRIPTION

I/O

POWER AMPLIFIER, SYNTHESIZER, AND TRANSMIT CONTROLS
PAEN

Power enable for the transmit power amplifier, active high

OUT1

User-defined general purpose data or control signal

SYNCLK

Synthesizer serial-data clock

SYNDTA

Synthesizer serial-data bit

SYNLEO

Synthesizer 0, 1, and 2 latch enables. An active high indicates the latch is enabled.

SYNLE1

SYNLE2

SYNOL

Synthesizer out-of-Iock indicator. Active high indicates out of lock.

TXEN

Power enable signal. Enables transmit signal processing, active high.

TXONIND

Transmit on indicator. Signal indicating power is applied to the power amplifier.

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

Terminal Functions (Continued)
miscellaneous digital signals
TERMINAL
NAME

NO.

1/0

RSINL

RSOUTH

RSOUTL

0
0

CMCLK

CSCLK

DESCRIPTION
Reset input, active low
Power on reset output, active high. On power up, RSOUTH goes high for 10 ms.
Power on reset output, active low. On power up, RSOUTL goes low for 10 ms causing an internal reset of the
TCM4301.
CLOCKS
Codec master clock. 2.048-MHz clock provided as master clock and bit clock for speech codec.

0
0

MCCLK

Microcontroller clock. Adjustable frequency with 1.215 MHz on powerup.

MCLKIN

Master clock input. Frequency 38.88 MHz ±100 ppm. A crystal can be connected between MCLKIN and XTAL to
provide an oscillator circuit. Alternately, XTAL can be left open and an external TIL/CMOS-level clock signal can
be connected to MCLKIN.

MCLKOUT

Buffered version of MCLKIN

XTAL

Use with MCLKIN to form an oscillator circuit

Codec sample clock. 8-kHz frame synchronization pulse for speech codec. Connected to DSP for speech sample
interrupts.

3:
w
>
w

POWER ENABLES
FMRXEN

10RXEN

0
0

Power enable for receiver I/O path, active high

SCEN

Power enable for speech codec, active high

Power enable for receiver FM path, active high

a..
o

DSP interface
TERMINAL
NAME

NO.

I1I01Z

DESCRIPTION

CINT

Controller data interrupt. Microcontroller data interrupt (active low) sent to DSP. Caused by the microcontroller
writing into the Send-C Int register location.

DSPAO

DSP 4-bit parallel address bus. DSPA3 is the MSB, and DSPAO is the LSB.

DSPA1

DSPA2

:J
C

a..

DSPA3

DSPCSL

DSPDO

I/O/Z

DSPD1

DSPD2

DSPD3

DSPD4

DSPD5

DSPD6

DSPD7

DSPD8

DSPD9

DSPRW

DSP read/write signal. DSPRW is active high for read cycles and active low for write cycles.

DSPSTRBL

DSP strobe signal, active low

DWBDINT

SINT

0
0

DSP interface chip select, active low
DSP 1O-bit parallel data bus. DSPD9 is the MSB, and DSPDO is the LSB.

DSP wide-band data interrupt. Wide-band data-ready interrupt (active low) caused by WBD demodulation circuits.
Sample interrupt (active low). Operates at 40 kHz in the analog mode and 48.6 kHz in the digital mode and as sleep
interrupt in the sleep mode .

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-55

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

Terminal Functions (Continued)
microcontroller interface
TERMINAL
NAME

NO.

1/0

DESCRIPTION

DINT

Microcontroller interrupt request signal. DSP data-ready interrupt sent to controller. Caused by DSP writing into
SEND DINT register location. DINT can be active high or low according to the levels of the MTS (1 :0) signals.

Microcontroller 5-bit parallel address bus. MCA4 is the MSB, and MCAO is the LSB.

MCAO

MCA1

MCA2

MCA3

MCA4

MCCSH

MCCSL

MCDO

I/OIZ

MCD1

MCD2

MCD3

MCD4

MCD5

o-I

MCD6

MCD7

MCDS

Microcontroller data strobe. Operational characteristics are selected by MTS (1 :0).

""C

MCRW

Microcontroller read/write. Operational characteristics are selected by MTS (1 :0).

:IJ

MTSO

<
-

MTS1

Microcontroller type select configuration control inputs. The interface is controlled by MTS (1 :0) as follows:
00 - Intel™ microcontroller interface characteristics
10- Mitsubishi™ microcontroller and Motorola microcontroller 16-bit bus interface characteristics
01 - Motorola™ microcontroller 8-bit bus characteristics
11 - Reserved
!

MWBDFINT

""C

:IJ

o
C

m
m
~

Microcontroller 8-bit parallel data bus. MCD7 is the MSB, and MCDO is the LSB.

Microcontrollerinterrupt request signal. Wide-band data-ready interrupt caused byWBD demodulator in analog
mode or frame interrupt sent by the DSP in digital mode. MWDBFINT can be active high or low, according to
the levels of the MTS (1 :0) signals.

Intel is a trademark of Intel Systems, Inc.
Mitsubishi is a trademark of Mitsubishi Inc.
Motorola is a trademark of Motorola Inc.

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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

Terminal Functions (Continued)
supply and reference voltages
TERMINAL

1/0

DESCRIPTION

NAME

NO.

AVDDRX

Analog supply voltage for RX receive path

AVDDREF

Analog supply voltage for RX FM receive path

AVDDTX

Analog supply voltage for TX transmit path

AVSSREF

Analog ground for REFCAP

AVSSRX

AVSSTX

Analog ground for RX receive path
Analog ground for TX transmit path

DVDD

35,45,63,
75,90

Digital power supply. All supply pins must be connected.

DVSS

34,46,65,
76,91

Digital ground. All supply pins must be connected.

VCM

Voltage common mode. VCM is used to establish dc operating point for TX outputs and can be tied to VHR.

VHR

Half-rail reference voltage (VHR), approximately 0.5 x AVDD. VHR is used to establish dc operating point for
RX inputs.

VSS

13,97

Substrate ground

3:
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detailed description
data transfer
The interface to both the system digital signal processor and microcontroller is in the form of 2s complement.
receive section
The mode of operation is determined by the state of the MODE, FMVOX, IORXEN, and FMRXEN bits of the
DStatCtrl register, as shown in Table 2. The specifications for the receive section are included in Table 3.
Table 2. TCM4301 Receive Channel Control Signals
CONTROL SIGNAL

ANALOG MODE

MODE

IQRXEN

FMRXEN

In the digital mode (MODE=1), the receive section accepts RXIP, RXIN, RXOP, and RXON analog inputs. These
inputs are passed to continuous-time antialiasing filters (AAF), baseband filtering, and AID conversion blocks,
and then to sample registers where 10-bit registers can be read. The sample rate is 48.6 ksps.
In the analog mode (MODE = 0), the FMVOX bit of the DStatCtrl register enables or disables the 0 side of the
receiver channel, and the FMRXEN bit controls the external functions. In the digital mode, IORXEN enables
both the I and 0 receive channels and external functions as well.
To save power, the receive I and Q channels are enabled separately. This operation occurs because in the
analog mode, only the Q channel is used. When the FMVOX bit is set to 1, it controls the input multiplexer,
connects the FM input to the receiver RXQP signal, and connects the RXQN to VHR. When the MODE control
bit and the IQRXEN control bit are set to 1, both sides of the receive channel are enabled for use in the digital
mode.

"TEXAS
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DIGITAL MODE

FMVOX

8-57

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

receive section (continued)
The input signals RXIP, RXIN, and RXOP, RXON are differential pair signals. Differential signals are used to
minimize the pickup of interference and ground and supply noise, while maintaining a larger signal level. In
single-ended applications, the unused RXIN and RXON terminals must be connected to VHR orto an externally
supplied bias voltage, and the input signal level must be adjusted in the RF circuitry to provide a higher level
signal so that the digital output codes are properly calibrated (0.5 V peak-to-peak corresponds to full-scale
digital output). In the analog mode, the RXON input is internally referenced to VHR. Alternatively, the unused
inputs can be connected to VHR and the used inputs can be capacitively coupled. Note that when the RX and
FM inputs are capacitively coupled, the input pins to the TCM4301 are self-biased to VHR; no external bias is
needed at the input pins.
The single-ended output of an external FM discriminator is connected to the FM pin for analog mode voice and
WBD reception. The signal at this pin is conveyed to the 0 side of the receiver via the multiplexer, and the other
input is connected internally to the VHR reference voltage. The I input of the RX Circuitry is disabled in the
analog mode. The FM signal passes through the antialiasing filter, as specified in Table 4, before passing
through the AID converter. The signal at the FM pin is also routed directly to the WBD demodulator through a
low-pass filter (LPF) with the -3 dB point at 270 kHz.

""0

The VHR can provide a bias voltage for the received inputs when capacitively coupled from the RF section. To
meet noise requirements, the VHR output should have an external decoupling capacitor connected to ground.
The VHR output buffer is enabled by the OR of TXEN, FMVOX, and IORXEN. The VHR output is high
impedance otherwise.

In the digital mode, both the I and 0 receive sides are enabled. Table 5 lists the receive channel frequency
response.

c::

When the I and 0 sample conversion is complete and the data is placed in the RXI and RXO sample registers,
the SINT interrupt line is asserted to indicate the presence of that data. This occurs at 48.6-kHz rate in the digital
mode and at 40-kHz rate in the analog mode. In the analog mode, only the RXO conversion path is used, and
the RXI path is powered down.

-I
""0

Table 3. RXIP, RXIN, RXQP, and RXQN Inputs (AVoo

m
<
m

PARAMETER

TEST CONDITIONS

Common-mode input voltage range
Input voltage for fullscale digital output
Nominal operating
level

MIN
0.3

0.5

Single-ended

0.5

Differential

0.125

Single-ended

0.125

Input CMRR (RXI, RXO)

Vp-p. Provides 12 dB headroom for
AGC fading conditions.
dB

48.6/40

I/O sample timing skew

6%
Input signal 0 - 15 kHz

AID resolution
Signal to noise-pius distortion

Input at full scale - 1 dB

Integral nonlinearity

o dB to -60 dB input

UNIT
V
Vp-p

Receive error vector magnitude (EVM)

Digital/Analog kHz
7%

Bits

a channel)

Gain mismatch between I and

=3 V, 4.5 V, 5 V)

MAX
AVDD-0.3

Differential

Sampling frequency, SINT

Gain error (lor

TVP

LSB
±10%

±0.3

Differential dc offset voltage

±30

FM input sensitivity

2.5

dB
mV
Vp-p for full scale (± 14 kHz deviation)

FM input dc offset (wrt VHR)

±90

FM input idle channel noise

-45

dB below full scale input

FM gain error
Power supply rejection

±7"10
f

=0 kHz to 15 kHz

~TEXAS

INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

receive section (continued)
Table 4. RX Channel Frequency Response (FM Input in Analog Mode)
PARAMETER

TEST CONDITIONS

2.5 V peak-to-peak,

MIN

20 kHz to 30 kHz (see Note 2)

-18

2.5 V peak-to-peak,

34 kHz to 46 kHz (see Note 3)

-48

Peak-to-peak group delay distortion

2.5 V peak-to-peak,

Absolute channel delay

2.5 V peak-to-peak,

o kHz to 6 kHz
o kHz to 6 kHz

NOTES:

MAX

UNIT

±0.5

2.5 V peak-to-peak,

Frequency response

TVP

o kHz to 6 kHz (see Note 1)

2
400

Jls
Jls

1. Ripple magnitude
2. Stopband
3. Stopband and multiples of stopband

Table 5. RX Channel Frequency Response (RXI, RXQ Input in Digital Mode)
TEST CONDITIONS

PARAMETER

Frequency response

o kHz to 8 kHz (see Note 4)

0.125 V peak-to-peak,

8 kHz to 15 kHz (see Note 4)

0.125 V peak-to-peak,

16.2 kHz to 18 kHz (see Note 5)

-26

0.125 V peak-to-peak,

18 kHz to 45 kHz (see Note 5)

-30

0.125 V peak-to-peak,

45 kHz to 75 kHz (see Note 5)

-46
-60

0.125 V peak-to-peak,

> 75 kHz

Peak-to-peak group delay distortion

0.125 V peak-to-peak,

o kHz to 15 kHz

Absolute channel delay, RXI, Q IN to
digital OUT

0.125 V peak-to-peak,

o kHz to 15 kHz

NOTES:

MIN

0.125 V peak-to-peak,

TYP

MAX

±0.5

±0.75

UNIT

±1
dB

2
325

Jls
Jls

4. Deviation from Ideal 0.35 SQRe response
5. Stopband

transmit section
The transmit section operates in two distinct modes, digital or analog. The mode of operation is determined by
the MODE bit of the OStatCtrl register. In the digital mode, data is input to the transmit section by writing to the
TXI register. The resulting output is a 1tf4 OOPSK-modulated time division multiplexed (TOM) burst. In the
analog mode, the data is in the form of direct I and Q samples which are written into both the TXI and TXQ
registers, then OfA converted, filtered, and output through TXIP, TXIN, TXOP, and TXON. The I and Q outputs
are zero-IF FM signals; that is, no baseband connection is necessary for FM transmission.
In the digital mode (MOOE=1), the data is written into the TXI register using the SINT interrupt to synchronize
the data transfer. The TCM4301 performs parallel-to-serial conversion of the bits in the TXI register and encodes
the resulting bit stream as 1tf4 OOPSK data samples. These samples are then filtered by a digital square root
raised cosine (SORC) shaping filter with a roll-off rate of ex = 0.35 and converted to sampled analog form by two
9-bit digital-to-analog converters (OACs). The output of the OAC is then filtered by a continuous-time
resistance-capacitance (RC) filter.
The TCM4301 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the PA.
The start and stop times of the TOM burst are controlled by writing to a single bit, TXGO in the OSP OStatCtrl
register.
In the analog mode (MODE = 0), the OSP writes 8-bit I and 0 samples into the TXI and TXO data registers at
a 40-ksps rate. These writes are timed by the SINT interrupt signal. The samples are fed to a low-pass filter
before Of A conversion. In the transmit analog mode, the PAEN signal is always set to 1.
The transmitter section provides differential I and 0 outputs for both analog and digital modes. The differential
dc offset for the TXI and TXO outputs can be independently adjusted using the TX offset registers .

•
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-59

3:
->w
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a:
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Io
=>
c

oa:
a.

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042-JUNE 1996

transmit section (continued)
Table 6. Transmit I and Q Channel Outputs
TEST CONDITIONS

PARAMETER
Peak output voltage full scale, centered at VCM
Nominal output-level (constellation radius) centered at VCM

MIN

TYP

Differential

2.24

Single-ended

1.12

Differential
Single-ended

3%
40

Gain error (lor Q channel)
Gain mismatch between I and Q

±0.3

Zero code error differential

±90

Zero code error, each output, with respect to VCM

±90

±10

Zero code error, I to Q, with respect to other channel
(differential or single-ended)
Load impedance, between P and N pins

VCM input voltage range

1.3

Transmit offset DACs I and Q full-scale positive output

m
S
m

Load capacitance

::D

Transmit offset DACs I and Q resolution

-I

dB
±15%

"tJ

bits

48
±10%

Gain sampling mismatch between I and Q

S/(N+D) ratio at differential outputs

PPM/DC

±200

Resolution

::D

0.75

Low-level drift

UNIT
Vp

1.5

Transmit error vector magnitude (EVM)

"tJ

MAX

AVDD-1.3

3.4

3.9

105.4

Transmit offset DACs I and Q full-scale negative output

V
bits

Transmit offset DACs I and Q average step size

mV
mV

-108.8

Transmit offset DACs differential nonlinearity

±1.1

LSB

Transmit offset DACs integral nonlinearity

±1.1

LSB

:::

Modulation error percentage = 100 ::: %

~·TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

transmit section (continued)
Table 7 and Table 8 shows the frequency response of the transmit section for digital and analog mode,
respectively.
Table 7. Transmit Channel Frequency Response (Digital Mode)
PARAMETER

TEST CONDITIONS

MIN

TYP

o kHz to 8 kHz (see Note 4)

Peak-to-peak group delay distortion
Absolute channel delay
NOTES:

UNIT

±0.3

8 kHz to 15 kHz (see Note 4)
Frequency response

MAX

±0.5

20 kHz to 45 kHz (see Note 5)

-29

45 kHz to 75 kHz (see Note 5)

-55

> 75 kHz (see Note 5)

-60

Any 30 kHz band centered at > 90 kHz (see Note 5)

-60

o kHz to 15 kHz
o kHz to 15 kHz

Il s
Il s

320

4. Deviation from ideal 0.35 SQRe response
5. Stopband

Table 8. Transmit Channel Frequency Response (Analog Mode)
PARAMETER

TEST CONDITIONS

MIN

TYP

o kHz to 8 kHz (see Note 1)

Peak-to-peak group delay distortion
Absolute channel delay
NOTES:

±0.5

20 kHz to 45 kHz (see Note 5)

-31

45 kHz to 75 kHz (see Note 5)

-70

> 75 kHz (see Note 5)

-70

Any 30 kHz band centered at > 90 kHz (see Note 5)

-70

o kHz to 15 kHz
o kHz to 15 kHz

UNIT

±0.5

8 kHz to 15 kHz (see Note 1)
Frequency response

MAX

->W

w
a.
t-

a:
O

3
540

Il s

1. Ripple magnitude
5. Stopband

:::;)

a:
a.

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-61

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

transmit burst operation (digital mode)
In the digital mode, the TCM4301 performs all encoding, signal processing, and power ramping for the burst.
Start and stop timing of the variable length bursts are set by (Tleans of the TXGO bit in the DStatCtrl register.
The SINT interrupt output interrupts the OSP at 48.6 kHz which is T/2 interval (T =1 symbol period =1/24.3 kHz).
The burst is initiated by the OSP writing from 1 to 5 dibits to the TXI register, a small positive delay offset value d
to the base station (SST) register, and a 1 to the TXGO bit in the DStatCtrl register.
The TXGO bit is sampled on the falling edge of SINT. The TX outputs are held at zero differential voltage (each
output pin is held at the voltage supplied to the VCM input pin) for 9.5 SINT periods (195.5/1s) plus SST offset
delay after SINT has detected TXGO high; then the TX outputs begin to ramp to the initial 1t/4 OOPSK
constellation value. The shape of the ramp is the transient resulting from the internal SORC filtering. At the same
time that the TX outputs are beginning to ramp, the PAEN digital output goes high. This output can be used to
enable the power amplifier of a cellular radio transmitter. The TCM4301 TX outputs reach the first 1t/4 OOPSK
constellation value (maximum effect point, MEP) 6 SINT periods (3 symbol periods) after the start of the ramp.
The bit stream to be encoded as 1t/4 OOPSK symbols is generated by right shifts on each SINT of the TXI
register with bit 0 (LSS) used first.
Previously written data continues to propagate through the TCM4301 internal filters until the last 1t/4 OOPSK
constellation value (last MEP) occurs at the TX outputs 15.5 SINT periods (318.9/1s) plus SST offset delay after
the last symbol occurs (2 SINT periods before TXGO goes low); then the TX outputs decay to zero differential
voltage (each output at the voltage supplied to the VCM input pin). The shape of the decay is the transient
resulting from the internal SORC filtering. The TX outputs are held at zero differential voltage 6 SINT periods
(3 symbol periods) after the start of the decay. At this time the PAEN digital output is set low (see Figure 1 and
Figure 2).

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Non-zero values of the SST offset register increase the delays of both the TX waveforms and PAEN relative
to the edges ofTXGO after it is internally sampled by SINT. The delays are increased in increments of 1/4 SINT
(1/8 symbol period).

-I
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For delays of 1 SINT or greater, the fractional part of the delay can be achieved using the SST offset register
with the remaining integer SINT delay implemented externally by delaying the writing to TXGO and TXI.
The relative timing of PAEN and the TX waveforms is not affected by the SST offset register.
The IS-136 standard describes shortened bursts and normal bursts. The two types differ in duration and number
of transmitted bursts, burst length being determined by means of the TXGO bit.
N+3 SINT Periods
(N

=Total number of bits sent)

j4-

Total delay = d (SINT/4 or T/8) where d

6 SINT Periods

=integer value (0,1,2,3) written to the BST offset register.

Figure 1. Power Ramp-Up/Ramp-Down Timing Diagram

8-62

•
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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042 - JUNE 1996

transmit burst operation (digital mode) (continued)

r----------------------------------------------,
I

I Dibit In
I
I
I
I TXGO
I
I

I
I
I
I
I
I
I

Channel Delay
(15.5 SINT Periods)

ClK
Delay

=0, 1/4, 1/2,3/4

Transmit Channel Delay + d(T/8)
Occurs from last symbol (2 SINT periods)
before TXGO goes low

L ___ _

--------------------------~

r----

--------------------------,

I
I
I
I
I

L----j----.-t D

SINT

--__e

PAEN Delay
9.5

ClK

-.f

19.5 - .

PAEN Delay + d(T/8)
TXGO high: 9.5 SINT periods + d(T/8): PAEN high
low:
19.5
d(T/8):
low
L _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ TXGO
___
__
_ SINT
_ _periods
_ _ _+_
_ _ PAEN
___
__

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Figure 2. TX Power Ramp-Up/Ramp-Down Functional Diagram

I-

transmit I and Q output level
In the digital mode, the output level at TXI and TXQ is controlled by the TCM4301. During the burst, but not
including ramp-up or ramp-down periods, the average output level (1 2 + Q2) 1/2 should approximate the specified
value. There is no variable level control for TXI and TXQ within the TCM4301 other than the fixed ramping. In
the analog mode, the output of the TCM4301 depends only on the sample values written to the TXI and TXQ
registers.
There are small differences in the average output power levels between the digital and the analog modes. These
differences require compensation at the system level by a small attenuation in the sample values of the analog
output.
When a change in transmit power is necessary, the microcontroller can change the value sent to the PWRCONT
DAC, the output of which can be connected to a voltage-controlled attenuator in the transmit path of the RF
section.

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8-63

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTICT~136)
SLWS042 - JUNE 1996

wide-band data demodulator
The wide-band data demodulator (WBDD) module demodulates the FM signal and outputs a
Manchester-decoded data stream. The WBDD is used for receiving the analog control channels of forward
control channel (FOCC) and forward voice control (FVC). The bit error rate (BER) performance requirements
are listed in Table 9.
Table 9. Typical Bit Error Rate Performance (WBD_BW

=000)

TEST CONDITIONS

PARAMETER

MEAN CNR (dB)

MIN

-5

Bit error rate

"'tJ

MAX

UNIT

0.4

0.279

0.143

0.056

0.0192

0.00623

0.00199

The WBDD is controlled by the bits in the control register WBDCtrl (see Table 10).

Table 10. Bits in Control Register WBDCtrl

C
C

WBD_LCKD

-I

WBD_BW

NAME

WBD_ON

"tJ
:D

Indicates whether edge detector is locked (1) or unlocked (0)
Turns the WBDD module on/off (1/0)
Sets the appropriate PLL bandwidth

000

FUNCTION

BIT CODE

20Hz

001

39Hz

010

78 Hz

011

156Hz

100

313 Hz

101

625 Hz

110

1250 Hz

WBD_LCKD: This bit can be used to reduce the effects of signal dropouts due to fading. In the
Manchester-coded signal, there are two types of data edges. One type occurs at the midpoint of each data bit,
and the other occurs randomly, depending on the transmitted data sequence. Inside the WBDD, an edge
detector rapidly synchronizes itself to the midpoint edges when the WBD_LCKD bit is set to o. However, if a
signal dropout occurs, the edge detector may momentarily lock to the wrong edge because it cannot distinguish
the midpoint edges from the data edges. A small number of additional bits may be lost in this instance.
When the WBD_LCKD bit is set to 1, the edge detector uses the WBDD internal PLL output to distinguish the
correct edge. Once acquisition of data has occurred, if this bit is set to 1, the loss of bits due to signal dropouts
is restricted to the fade duration only.
When the WBDD PLL is not synchronized, as at powerup, the WBD_LCKD bit must be cleared to 0 to allow edge
synchronization to the data.
WBD_BW: The variable bandwidth is required for fast acquisition in the beginning using a wide bandwidth for
the PLL, and a narrower bandwidth is used afterwards to reduce the likelihood of noise-causing loss of
synchronization.
The WBDCtrl register is accessible by both the DSP and the microcontroller.

~TEXAS

INSTRUMENTS
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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

wide-band data interrupts
The WBOO operates whenever WBO_ON is high, and it does not require the receive channels to be enabled.
While WBO_ON is high, every 800 Ils, 8 bits are placed in the WBO register, which is accessible by both the
OSP and the microcontroller ports. This value should be written at the same time as WBO_ON is initially set
high.
At the same time, the interrupts OWBOINT and MWBOFINT are asserted. The interrupt rate is 800 Ils
(8 bits/1 0 kHz). These interrupts are individually cleared when the WBO register is read by the corresponding
processor. They can also be cleared by their respective processor by writing a 1 to the corresponding clear WBO
bit.
There is one WBO control register. It can be written to by either processor port.

wide-band data demodulator: general information
The WBOO recovers the transmitter clock from the data stream, which is Manchester encoded, and decodes
the data bits. Consideration at the system level is required to ensure data integrity.
The WBO stream carries with it a 1O-kHz clock. The Manchester-coded data format contains a transition at the
middle of every bit-clock period, which aids in clock recovery. The polarity of the transition is data-dependent.
In a typical Manchester-coded WBO stream, a positive voltage for the first half of the data sequence bit time
followed by a negative voltage for the second half of the data sequence bit time represents the value in the
data sequence. Likewise, a negative voltage followed by a transition to a positive voltage represents the value
1 in the data sequence. This is illustrated in Figure 3. The WBO stream can also be seen as the exclusive-OR
of the clock and data sequence. The data sequence is in nonreturn to zero (NRZ) format.

Data
0
Sequence 1------1

3:
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Stream

c..

Recovered Clock
10 kHz

Figure 3. WeD Manchester-Coded Data Stream

auxiliary digital-to-analog converters (DACs), LCD contrast converter
Auxiliary OACs generate AFC, AGC, and power control signals for the RF system. These three OIA converters
are updated when the corresponding data is received from the OSP. In fewer than 51ls after the corresponding
registers are written to, the output has settled to within 1/2 LSB of its new value (see Table 11).
The LCOCONTR output is used by the microcontroller to adjust the contrast of the liquid-crystal display (LCD).
This converter is a separate 4-bit OAC .

•
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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136}
SLWS042 - JUNE 1996

auxiliary digital-to-analog converters (DACs), LCD contrast converter (continued)
Table 11. Auxiliary DIA Converters
PARAMETER

TEST CONDITIONS

vt,
AVDD> 4.5 vt,
AVDD > 5 vt,
AVDD > 3

Output range

MIN

=00
AUXFS [1 :0] = 10
AUXFS [1 :0] = 11
AUXFS [1 :0]

TYP

MAX

0.2
0.2

0.2

4.5

Resolution AGC, AFC, PWRCONT DACs

Resolution LCDCONTR DAC

Gain + offset error (full scale) AGC, AFC, PWRCONT DAC

bits
bits
±5%

Gain + offset error (full scale) LCDCONTR DAC

±8%

Differential nonlinearity

±1.3

±2

LSB

Integral nonlinearity

±1.3

±2

LSB

Load resistance

Load capacitance

UNIT

2.5

Range settings depends only on AUXFS [1 :0]. The supply voltage is not detected.

The auxiliary DACs can be powered down. The AGC and AFC DACs have dedicated bits in the MlntCtrl register
to enable the DACs. The PWRCONT DAC is enabled by the TXEN bit in the DStatCtrl register. The LCDCONTR
DAC is enabled when the LCDEN bit of the LCD D/A register is set to 0, the four data bits being left justified.
The AFC, AGC, and PWRCONT DACs are disabled after powerup or after a reset of the TCM4301. After
powerup or reset, the default AUXFS[1 :0] is 00. When the DACs are powered down, their output pins go to a
high-impedance state and can tolerate any voltage present on the pin that falls within the supply range.

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The slope and the corresponding output values for the auxiliary DACs are listed in Table 12 and Table 13.

--I
""CI

Table 12. Auxiliary DIp.. Converters Slope (AGC, AFC, PWRCONT)

m
m
===

AUXFS[1:0]
SETTING

SLOPE

NOMINAL LSB
VALUE
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 128
(MIDRANGE)
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 256+
(MAX VALUE)

2.5/256

0.0098

1.25

2.5

Do not use

4/256

0.0156

4.5/256

0.0176

2.25

4.5

(V)

+ The maximum input code is 255. The value shown for 256 is extrapolated.

Table 13. Auxiliary D/A Converters Slope (LCDCONTR)
AUXFS[1:0]
SETTING

SLOPE

NOMINAL LSB
VALUE
(V)

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 8
(MIDRANGE)
(V)

2.5/16

0.1563

1.25

2.5

Do not use

4/16

0.2500

4.5/16

0.2813

2.25

4.5

§ The maximum input code is 15. The value shown for 16

extrapolated.

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INSTRUMENTS
8-66

NOMINAL OUTPUT VOLTAGE
FOR DIGITAL CODE 16§
(MAX VALUE)
(V)

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

RSSI, battery monitor
The receive signal strength indicator (RSSI) and battery (BAT) strength monitor share a common register. The
input source is determined by writing any value to the mapped register location for that analog-to-digital
converter (see Table 14), and the result of the conversion is stored in both register locations. The conversion
process is initiated when the register is written to. The CVRDY bit in the MStatCtrl register is set to 1 to show
completion of the conversion process. Reading from either of the register locations causes the CVRDY bit to
change to O. The received signal strength indicator allows the mobile unit to choose the proper control channels,
and to report signal levels to the base stations.
When CVRDY in the MStatCtrl register goes to 1, this indicates that the latest RSSI or battery voltage AID
conversion has been completed and can be read from the RSSI or BAT register location. CVRDY goes to 0 when
the microcontroller reads either of these locations.

Table 14. RSSl/Battery AID Converter
PARAMETER
Input range

TEST CONDITIONS
AVDD

=3 V, 4.5 V, 5 V

MIN

Resolution
Conversion time

TYP

0.2

MAX

2
8

AVDD

=3 V, 4.5 V, 5 V

±4%

Differential nonlinearity
Integral nonlinearity
Input resistance

V
bits

Gain + offset error (full scale)

UNIT

liS
±5%
±1.5

LSB

±1.5

LSB

In order to save power, the entire RSSlfbattery converter circuit is powered down when no AID conversions are
requested for 40 J.ls. The microcontroller writes to RSSI or BAT registers, causing power to be applied to the
converter circuit. Power is applied to the converter circuit until the data value has been latched into the
corresponding register, at which time power to the converter is removed. Data remains in the result registers
after the converter is powered down.

timing and clock generation
The digital timing generation system uses a 3a.aa-MHz master clock, as shown in Figure 6. The upper half of
the figure shows the clock generation for clocks that must be phase adjusted in order to synchronize the mobile
unit with the received symbol stream in the digital mode. In the analog mode, these clocks operate without phase
adjustments. The lower half of Figure 6 shows the clocks that are directly derived from the master clock.

clock generation
There are three options for generating the master clock. A fundamental crystal or third-overtone crystal with a
frequency of a MHz can be connected between the MCLKIN and the XTAL terminals or an external clock source
can be connected directly to the MCLKIN terminal. The MCLKOUT is a buffered master clock output at the same
frequency as MCLKIN. MCLKOUT can be used as the source clock for other devices in the system. Setting the
MCLKEN bit in the MStatCtrl register enables or disables this output. The MCLKOUT enable is synchronous
to eliminate abnormal cycles of the clock output.
All output clocks are derived from the master clock (MCLKIN). The sample clocks for the digital and analog
modes, the a-kHz speech codec sample clock, and the clocks for the AID and DfA functions are also derived
from the master clock.

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042-JUNE 1996

speech codec generation
The TCM4301 generates two clock outputs for use with speech codecs: the 2.048-MHz CMCLK and the 8-kHz
CSCLK. These clocks are generated so that each CSCLK period contains exactly 256 cycles of CMCLK. Since
2.048 MHz is not an integer division of the 38.88-MHz MCLKIN, one out of every 64 CMCLK cycles is 18
MCLKIN periods long, and the remaining 63 out of 64 are 19 MCLKIN periods long. The average frequency of
MCLKIN is therefore
MCLKIN x

( 63

+ 1)
64

= 2.048092 MHz

CSCLK is exactly CMCLK divided by 256. See Figure 4.
CMCLK
Codec Master Clock 2.048 MHz
CSCLK

-----"

Codec Sample Clock 8 kHz

Figure 4. Codec Master and Sample Clock Timing

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To save power, the codec clocks are only generated by TCM4301 when the SCEN bit of the DStatCtrl register
is set high. When SCEN is low, both outputs, CSCLK and CMCLK, are held low. SCEN is also available as an
output.

microcontroller clock

-I

\'-------

sample interrupt SINT
The SINT interrupt signal is the primary timing signal for the TCM4301 interface. The primary function of the
SINT is to indicate the ready condition to receive or transmit data. It also conveys timing marks to allow for the
synchronization of system DSP functions. In the digital mode, SINT is used in conjunction with the received sync
word to track cellular system timing. The SINT can be disabled by writing a 1 to the SOlS bit of the OlntCtrl
register. When enabled, the SINT operates continuously at 48.6 kHz in the digital mode and at 40 kHz in the
analog mode. The SINT signal does not require an interrupt acknowledge. The SINT is active low for
seven MCLKOUT cycles in both the analog mode and digital mode to guarantee capture by the OSP. The SINT
signal is the sleep timer interrupt when operating in sleep mode and is the normal sample interrupt when not
in sleep mode.

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

sleep mode timer
DSP and microcontroller registers
The sleep mode function is controlled in four TCM4301 registers. The relevant DSP registers are the sleep
control register (Slp_Ctrl), the sleep compare register (Slp_Cmp), and the sleep counter register (Slp_Cntr).
Address OEh in the DSP register map space is the [9:0] Slp_Cmp register on a write and is the [9:0] Slp_Cntr
on a read. Address OFh is the Slp_Ctrl register. The three least significant bits, [2:0], are Slp_Cntr [12:10] on
a read and Slp_Cmp [12: 10] on a write. The relevant microcontroller register is the microcontroller interrupt
control register (MlntCtrl), which is assigned address OEh in microcontroller register map space. The sleep
mode bit, SM, is bit [0] in MlntCtrl. See Figure 5.

sleep counter data
The sleep counter data is 13 bits wide. The three most significant sleep counter data bits [12:10] are read via
the internal DSP bus at the three least significant bits [2:0] in the sleep mode control register (Slp_Ctrl) at
address OFh. The ten least significant sleep counter data bits [9:0] are read from the sleep counter (Slp_Cntr)
at address OEh via the DSP bus. Two reads are needed to read the sleep counter data. The count value of the
three most significant bits in address OFh are latched when a read is performed at address OEh. This feature
allows the DSP to read the correct values of the three most significant bits at a later time.

sleep compare data
The sleep compare data is 13 bits wide. The three most significant sleep compare data bits [12: 10] are loaded
via the DSP bus by writing to the three least significant bits [2:0] of the sleep mode control register (Slp_Ctrl)
at address OFh. The ten least significant sleep compare data bits [9:0] are written via the DSP bus to the sleep
compare register (Slp_Cmp) at address OEh. Thus, two writes are needed to load the sleep compare data. The
three most significant data bits are set to zero upon a write to the ten least significant bits.

sleep mode control register (Slp_Ctrl)
The sleep control register is 10 bits wide. The three least significant bits [2:0] are Slp_Cntr [12:10] on a read
and Slp_Cmp [12:10] on a write. The remaining bits are defined as follows:
Bit [3], on Read: TMR_STS, Timer Status Bit: This bit indicates the mode status of the timer circuit. When
high, the 50 Hz counter is enabled and the circuit is in sleep mode. When low, the counter is disabled. This bit
is cleared during initialization.
on Write: STR_TMR, Start Timer Bit: Active high, cleared during initialization. This bit is set high by the
DSP (not latched) to initiate the sleep timer and disable MCLKOUT.
NOTE: The counter is to count beginning at the edge of a 48.6-kHz clock. Thus, the 50-Hz sleep counter clock is synchronous with
the 48.6-kHz clock.

Bit [4], on Read: MCSM, microcontroller sleep mode status bit. When read, this bit is the micro sleep mode
bit [MlntCtrl register bit [0], sleep mode bit (SM)], echoed back to the DSP. On read, this bit can be used by
the DSP to determine the cause of an SINT wakeup interrupt. When the DSP wakes up and reads the bit as
set (=1), then the SINT was caused by the timer expiring (A=B). If the DSP reads the bit as reset (=0), then
the SINT was caused by the microcontroller changing its sleep mode bit, SM, = O. This bit is cleared during
initialization.
on Write: STP_ TMR: This bit is active high (not latched). When high, the sleep counter is stopped and
reset. The DSP can then read TMR_STS to investigate the mode of the timer.
Bit [5], TEST, Test Bit. When a 1 is written to this bit, the contents of the Slp_Cmp and Slp_Ctrl registers can
be read by the DSP.

"TEXAS
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8-69

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

microcontroller interrupt control register (MlntCtrl)
The MlntCtrl register bit [0], sleep mode bit (8M), enables the sleep mode on the microcontroller side. The reset
value is 0, disabled. This bit is echoed back to the D8P and latched in bit [4] (MCSM) in the sleep control register
on a read by the DSP. This microcontroller sleep mode bit is set high by the microcontroller to enable sleep
mode. During sleep mode, the microcontroller can initiate an 81NT wakeup interrupt to the D8P by clearing this
bit. The counter continues to run until 8TP _ TMR is set high.
38.88MHz
MCLKIN

MCLKOUT

MCLKEN
Timer Status
Register
S

MCSM
STR_TMR

STP_TMR

MCLK
Delay

TMR_STS

48.6 kHz

"tJ

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c:
0

-I
"tJ

Disable Clock
Register

m
S
m

A
10

COMPA=B

NCLK
Delay
1024

Q 1----------1

SOlS

Internal DSP Bus

48.6 KHz

To DSP MCSM

Figure 5. Sleep Mode Timer Block Diagram

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SINT

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

microcontroller interrupt control register (MlntCtrl) (continued)
MCLKOUT is disabled under the following conditions:
•

D8P 8TR_TMR bit is written to with a 1, and the microcontroller sleep mode bit has been set (8M = 1).
The disable function is delayed by a minimum of 50 MCLKIN clock cycles.

MCLKOUT is enabled under the following conditions:
o

Microcontroller sleep mode signal is reset, 8M = O.

Compare output is active (A

•

TCM4301 is reset.

= B = 0).

phase-adjustment strategy
In the digital mode 18-136 system, receiver sample timing must be phase adjusted to synchronize the AID
conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit timing to
the base station timing. This is done by temporarily increasing or decreasing the periods of the clocks to be
adjusted. To avoid undesirable transients, each cycle of the clock being adjusted is altered by only one period
of MCLKIN. A total adjustment equivalent to multiple MCLKIN periods is accomplished by altering multiple
cycles of the clock being adjusted. The number of cycles altered is controlled by internal counters.
In the TCM4301 there are two clocks which must be adjusted: CMCLK and an internal 9.72-MHz clock from
which 81NT is derived. Each of these clocks has an associated counter that counts the number of cycles that
have been lengthened or shortened by one MCLKIN period each and thus detects when the total adjustment
is complete. These counters are shown in Figure 6 as Adjust Counter A and Adjust Counter B.
The magnitude of the 2s complement value written to the timing adjustment register determines the number of
cycles of the clocks to be lengthened or shortened by one MCLKIN period each to achieve the total desired
timing adjustment in units of MCLKIN periods. If a negative number is written, the clock periods are lengthened
for the duration of the timing adjustment, resulting in a timing delay. If a positive number is written, the clock
periods are shortened for the duration of the timing adjustment, resulting in a timing advance.
The divider used to generate CMCLK normally divides MCLKIN by either 19 or 18. When its period is being
lengthened during a timing adjustment, MCLKIN is divided by either 20 or 19. When the CMCLK period is being
shortened, MCLKIN is divided by either 18 or 17 (see the section on speech codec clock generation). The divider
used to generate a 9.72-MHz divides by 4 during normal operation, by 5 when its period is being lengthened
during timing adjustments, and by 3 when its period is being shortened during timing adjustments.
Because CMCLK and the 9.72-MHz internal clock have different periods, and the timing adjustments are limited
to one period of MCLKIN per period of the clock, these clocks take different times to complete the entire timing
adjustment. Because the total adjustment is the same number of MCLKIN periods for both clocks, the relative
phases of the two clocks are the same after the adjustment as they were before.
Both adjust counters reach zero when the adjustment is complete, so there is no need to write to the timing
adjustment register until another timing adjustment is required. For each write to the timing adjustment register,
a single timing adjustment of the direction and magnitude requested is performed.

~TEXAS

INSTRUMENTS
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8-71

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

2.048-MHz Codec Master Clock CMCLK

8-kHz Codec Sam Ie Clock CSCLK

From DSP -+--,..::.....--......
Phase-Adjusted
9.72-MHz Clock

Analog/Digital
40.0/48.6-kHz AID Sample Clock (SINT)

38.88 MHz
MCLKIN

Frequency Synth. Clock 303.75-kHz

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WBD Demod. 6.48 MHz

Clock
Divider
Chain

5
From
Microcontroller -~'-..

ADC Clocks
DAC Clocks
Microcontroller Clock MCCLK

=(1, 2, 3, ••• 32)

Sync.
Enable

-I

MCLKEN

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1--_ _ _ _ _ _ _ _-=E=xt=e..:..:rn=a:.:...1C=I;,;:;.o.;:.:ck..:...O;:;.;u=t.<:,.u=t...:.:Mc.:...:C=L:..:..:K=O-=U-=--T

Logic

Figure 6. Timing and Clock Generation for 3S.SS-MHz Clock

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The output of each adjustment counter is fed to a variable modulus divider. For counter A, there are three
possible moduli, 3, 4, and 5. For counter B, there are four possible moduli, 17, 18, 19, and 20.

~TEXAS

INSTRUMENTS
8-72

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface
The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side outputs
are a data line, a clock line, and three latch enable lines that separately strobe data into each synthesizer. The
control-side inputs are registers mapped into the microcontroller address space. The status of the interface can
be monitored to determine when the programming operation has been completed.
The synthesizer interface is designed to be general purpose. Most of the currently available synthesizers can
be accommodated by programming the interface according to the required synthesizer data and logic level
formats.
The output of the synthesizer interface consists of five signals. SYNCLK is the common data clock for all
attached synthesizer chips. Two control bits, CLKDIV, in SynCtrl2 control the frequency for the SYNCLK. These'
bits are initialized to 00, which results in MCLKIN/128 (",304 kHz). The clock pulse has a 50% duty factor. When
CLKDIV = 01, the rate is MCLKIN/64; when CLKDIV =10, the rate is MCLKIN/32; and when CLKDIV = 11, the
rate is MCLKIN/16. The serial data output SYNDTA is common to all synthesizers. Three strobe signals,
SYNLE[2:0], are provided. There is one for each synthesizer chip. The attributes of this interface are controlled
by means of the synthesizer control registers, SynCtrl[2,1 ,0]. These attributes determine:
•

The polarity of the clock (rising or falling edge)

•

Whether data is shifted left or right

•

The number of bits sent to the synthesizer

•

The timing and polarity of the latch enable bits

•

The selection of which synthesizer to program

;::

->W

Programming of the synthesizers is accomplished by writing to four microcontroller-mapped data registers.
These registers are chained to form a 32-bit data shift register that can be operated in either shift left or shift
right mode. This register set can accommodate various formats of synthesizer control data. When fewer than
32 bits of data are to be transmitted, the significant data bits must be justified such that the first bit to be
transferred is either the LSB or the MSB of the register set, as defined by the control register for LSB or MSB
first operation. All 32 bits of the data register are transmitted each time. See Table 17 for register location. See
Figure 7 for a respresentative block diagram of the frequency synthesizer interface.

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a:
a..
I-

::::l
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oa:
a..

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-73

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
CLKDIV
CLKDIS
CLKPOL
NUMCLKS
LOWVAL

Control
Registers

HIGHVAL
SEL[2:0]
Ready
and

MSB/LSB FIRST
IDLPOL

Timing Logic tSYiNRriY1rc;NiShrtCtrlR~rte;:---'L
SYNRDY To MStatCtrl Register

__---I

SYNDTA4-------------------~

0 ......-------,
SYNLEO

SELO

SEL1

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SYNLE1

c:
o

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LEINT
SYNLE2

SEL2

m
S
m

MCLK

SYNCLK 4 - - - - - - 1

Clock
Circuit

==
Figure 7. Synthesizer Interface Circuit Block Diagram

~TEXAS

INSTRUMENTS
8-74

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
The SynDataO register contains the least significant bits of the 32-bit data register. SynData3 contains the most
significant bits. The bits in the SynCtrlO, SynCtrl1, and SynCtrl2 registers are allocated as shown in Figure 8.

SynCtrlO

SynCtrl1

4-0
LOWVAL

7-6

4-0

CLKDIV[1 :0]

MSB/LSB
FIRST

HIGHVAL

SynCtrl2

7-5
SEL[2:0]

CLKDIV1

CLKDIVO

SYNCLK RATEt

MCLKIN/128

MCLKIN/64

MCLKIN/32

MCLKIN/16

MCLKIN is 38.88 MHz.

4-0

CLKDIS

IDLPOL

CLKPOL

NUMCLKS

->w==
W

Figure 8. Contents of SynData Registers

I-

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a:
c.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-75

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
Table 15 identifies the meaning of each of the bit fields in SynCtrl[2:0].
In the status register MStatCtrl, two bits, SYNOL and SYNRDY, are dedicated to the synthesizers. The first is
an out-of-Iock indicator that comes from the SYNOL input terminal. If the SYNOL input terminal is connected
to the OR of the out-of-Iock signals from the external synthesizers, the lock condition of the synthesizers can
be monitored by reading the MStatCtrl register. A high on SYNOL also prevents the PAEN output from being
asserted and forces the TXI and TXQ outputs to O. The SYNRDY bit, active high, indicates when the synthesizer
interface is idle and ready for programming. SYNRDY will indicate that the interface is idle following a
programming cycle after all SYNCLK, and SYNLE events are complete. All events are complete when BIT CNT
is equal to the greater of NUMCLKS, HIGHVAL, and LOWVAL; a value of 0 in NUMCLKS is the maximum value
possible. When SYNRDY is low, the synthesizer interface is busy.
Controlling the synthesizer interface is straightforward. The microcontroller checks to see if the SYNRDY bit
is low. When it is low, the synthesizer interface is not ready. When SYNRDY goes high, the microcontroller
programs the desired information into the four registers. When the microcontroller write to the SynCtrl2 register
is complete, the synthesizer interface sets the SYNRDY bit low and begins to send data, clock, and latch enable
according to the format established in the registers. SYNRDY returns high when the entire operation is
complete. The SynCtrl registers must be programmed in order of SynCtrlO, then SynCtrl1 , and finally SynCtrl2
to assure proper synthesizer programming.

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Table 15. Synthesizer Control Fields

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CLKPOL

-I

m
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m

2 Bits. Selects rate for SYNCLK: 00=MCLKl128, 01=MCLKl64, 10=MCLKl32, 11=MCLKl16
Defines the significant edge of SYNCLK that occurs in the middle of the SYNDTA bit.
0: Requires a falling edge
1: Requires a rising edge

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DESCRIPTION

NAME
CLKDIV(1 :0)

NUMCLKS

CLKDIS

This 5-bit field defines the total number of clock pulses that are to be produced on the SYNCLK terminal. The value written
into this field is the desired number of output clock pulses, with one exception: When 32 clock pulses are desired, all zeroes
are written into NUMCLKS.
Defines whether the SYNCLK signal will be active during a programming cycle.
0: Requires that the SYNCLK signal is active as defined by NUMCLKS, IDLPOL, and CLKPOL.

1: Requires that the SYNCLK signal remain in the idle state as defined by IDLPOL, and CLKPOL.
HIGHVALt

LOWVALt

MSB/LSB FIRST

SEL[2:0]

3 Bits. Select which synthesizer strobe line is active. A 1 in any of these bits activates the corresponding latch enable.

IDLPOL

Defines the idle state polarity of the SYNCLK signal.
0: Requires that the idle state of the SYNCLK signal to be the same as the CLKPOL control bit.
1: Requires that the idle state of the SYNCLK signal to be the complement of the CLKPOL control bit.

t LOWVAL and HIGHVAL should never be assigned the same value. A particular SYNLE signal can be made to transition from a low state on the
crossing of a cycle boundary to a high state as early as BIT CNT count one (1). If LOWVAL is given a value less than HIGHVAL, the selected
SYNLE signal(s) will exit the programming cycle in a high state. If HIGHVAL is given a value less than LOWVAL, the selected SYNLE signal(s)
will exit the programming cycle in a low state.

~TEXAS

INSTRUMENTS
8-76

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
Example 1: Single Cycle, SYNCLK Activity
Example 1 depicts a single programming cycle. Of particular interest is the activity of SYNCLK. The SYNCLK
signal begins the programming cycle in either a high or low logic state and completes the programming cycle
in a low logic state; the idle state of SYNCLK is a logic low.
The control bit CLKDIS is set to 0, which enables the output of SYNCLK. When SYNCLK is enabled by
CLKDIS = 0, SYNCLK will be enabled from a count of 0 to NUMCLKS of the BIT CNT counter. A value of 0 in
NUMCLKS provides for 32 SYNCLK periods.
The significant edge polarity is controlled by CLKPOL. With CLKPOL set to 1, the significant edge of SYNCLK
will be rising from a logic low to a high state and will do so in the middle of the associated SYNDTA bit.
Because the idle state polarity control bit IDLPOL is set to 1, the idle state of SYNCLK is the complement of the
CLKPOL bit, which is set to 1 in Example 1. Therefore, when the BIT CNT counter reaches a value equal to
NUMCLKS, SYNCLK returns to a low, idle state.

BITCNT

SYNCLK
____________________________

SYNDTA

SYNLEO __________________________________________

SYNLE1,2--------------------------------------------------------------------SYNRDY-,~______________________________________________________________~r__

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a:
a.

....

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CLKDIS = 0
CLKPOL = 1
IDLPOL = 1
NUMCLKS = 10
HIGHVAL = 12
LOWVAL= 18
SEL [2:0] = 001

a:
a.

Figure 9. Example 1: Single Cycle SYNCLK Activity

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-77

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
Example 2: Single Cycle, SYNCLK Activity
Example 2 is similar to Example 1 with the exception of the state of control bit IDLPOL. In Example 2, CLKPOL
is set to 1 and IDLPOL is set to O. With CLKPOL = 1, the significant edge of SYNCLK will be rising from a logic
low to a logic high state and will do so in the middle of the associated SYNDTA bit.
Because the idle state polarity control bit IDLPOL is set to 0, the idle state of SYNCLK is the same as the
CLKPOL bit, which is set to 1 in Example 2. Therefore, when the BIT CNT counter reaches a value equal to
NUMCLKS, SYNCLK remains at a high idle state.

BITCNT
SYNCLK
S Y N D T A " " " " -_ _ _ _ _ _ _ _ _ _ __
SYNLEO_-='~

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____________________________________~

SYNLE1,2--='~---------------------------------------------------------------SYNRDY-,~

____________________________________________________________~r__

CLKDIS=O
CLKPOL = 1
IDLPOL= 0
NUMCLKS = 10
HIGHVAL 12
LOWVAL= 18
SEL [2:0] = 001

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Figure 9. Example 2: Single Cycle, SYNCLK Activity (Continued)

-m
=e

~TEXAS

INSTRUMENTS
8-78

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

frequency synthesizer interface (continued)
Example 3: Single Cycle, SYNCLK Activity
Example 3 is similar to Example 1. In Example 3, CLKPOL and IDLPOL are both set to O. With CLKPOL = 0,
the significant edge of SYNCLK will be falling from a logic high to a logic low state and will do so in the middle
of the associated SYNDTA bit.
Because the idle state polarity control bit IDLPOL is set to 0, the idle state of SYNCLK is the same as the
CLKPOL bit, which is set to 0 in Example 3. Therefore, when the BIT CNT counter reaches a value equal to
NUMCLKS, SYNCLK returns to a low idle state.

BITCNT
SYNCLK
SYNDTA

____________________________

SYNLEO __________________________________________

SYNLE1,2--------------------------------------------------------------------SYNRDY-,~____________________________________________________________~r__

CLKDIS = 0
CLKPOL= 0
IDLPOL = 0
NUMCLKS = 10
HIGHVAL = 12
LOWVAL= 18
SEL [2:0] = 001

3:
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a:

I-

c
o

Figure 9. Example 3: Single Cycle, SYNCLK Activity (Continued)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-79

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
Example 4: Single Cycle, SYNCLK Activity
Example 4 is similar to Example 1. In Example 4, CLKPOL is set to 0 and IDLPOL is set to 1. With CLKPOL = 0,
the significant edge of SYNCLK will be falling from a logic high to a logic low state and will do so in the middle
of the associated SYNDTA bit.
Because the idle state polarity control bit IDLPOL is set to 1, the idle state of SYNCLK is the complement of the
CLKPOL bit, which is set to 0 in Example 4. Therefore, when the BIT CNT counter reaches a value equal to
NUMCLKS, SYNCLK remains in a high idle state.

BITCNT
SYNCLK
S Y N D T A ' ' " ' " ' __ _ _ _ _ _ _ _ _ _ _ __
SYNLEO-='_~""'"'_

SYNLE1,2_-='~""'"'_

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ___

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SYNRDY-,~

r__

_____________________________________________________________

CLKDIS = 0
CLKPOL = 0
IDLPOL = 1
NUMCLKS= 10
HIGHVAL = 12
LOWVAL= 18
SEL [2:0] = 001

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Figure 9. Example 4: Single Cycle, SYNCLK Activity (Continued)

•
TEXAS
INSTRUMENTS
8-80

POST OFFICE BOX 655303. DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

frequency synthesizer interface (continued)
Example 5: 32-Bit Data Transfer with SYNLE Activity Cycles
Example 5 depicts a 32-bit data transfer occurring in a single programming cycle followed by four cycles during
which the states of SYNLE signals are manipulated.

Programming Cycle 1
Transferring 32 bits of data requires the same number of SYNCLK periods. The NUMCLKS control field is set
to 0, which calls for 32 SYNCLKs during the data transfer programming cycle. The states of CLKPOL and
IDLPOL call for a rising edge SYNCLK which returns to a low idle state.
During the data transfer cycle, the SYNLE signals are assumed to have been previously made low by a
preceding initialization programming cycle. Because SEL [2:0] are all low, the SYNLE signals will not transition
during this cycle regardless of the values of HIGHVAL and LOWVAL.

Programming Cycle 2
SEL [2:0] is set to 001, which enables a state change in the SYNLEO signal alone. When the BIT CNT counter
reaches a value equal to that of the HIGHVAL control field, SYNLEO goes to the high state. The LOWVAL control
field is set to O. Because SYNLEO is already at a low state when the BIT CNT counter has a counter value of
o and LOWVAL is given a value less than HIGHVAL, the LOWVAL field has no effect on SYNLEO during this
programming cycle, and SYNLE remains in a high state at the termination of this programming cycle.
Note also the SYNCLK signal is suppressed to its idle low state by CLKDlS being set to 1 regardless of the value
in the NUMCLKS field. NUMCLKS is given a value of 0, which will ensure that the 32 BIT CNT counts occur
during the programming cycle.

Programming Cycle 3
SEL [2:0] is set to 001, which enables a change in the SYNLEO signal. HIGHVAL is given a value of 1 and
LOWVAL is given a value of O. Therefore, SYNLEO is forced low at a BIT CNT count of 0 and then returns high
at a BIT CNT count of 1.
Note also that the SYNCLK signal is still suppressed to its idle low state by CLKDIS being set to 1 regardless
of the value in the NUMCLKS field.

Programming Cycle 4
SEL [2:0] is set to 001, which enables a change in the SYNLEO signal. HIGHVAL is given a value of 0 and
LOWVAL is given a value of 30. Therefore, SYNLEO is forced to a low state at a BIT CNT count of 30.
Program Cycle 1
CLKDIS= 0
CLKPOL= 1
IDLPOL= 1
NUMCLKS = 0
HIGHVAL = 1
LOWVAL = 0
SEL [2:0] = 000

1 -

- 30 31

Program Cycle 2
CLKDIS = 1
CLKPOL = 1
IDLPOL = 1
NUMCLKS=O
HIGHVAL 1
LOWVAL=O
SEL [2:0] 001

=
=

1 -

- 30 31

Program Cycle 4
CLKDIS = 1
CLKPOL= 1
IDLPOL = 1
NUMCLKS =0
HIGHVAL= 0
LOWVAL= 30
SEL [2:0] = 001

Program Cycle 3
CLKDIS = 1
CLKPOL= 1
IDLPOL= 1
NUMCLKS=O
HIGHVAL= 1
LOWVAL=O
SEL [2:0] = 001

1 -

- 30 31

1 -

- 30 31

BITCNT
SYNCLK
SYNDTA
SYNLEO
SYNLE1,2

Figure 10. Example 5: 32-Bit Data Transfer with SYNLE Activity Cycles

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-81

3=
->w
a::

w
c..

I-

(.)
~

o
a::
c..

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

frequency synthesizer interface (continued)
Example 6: 32-Bit Data Transfer with SYNLE Boundary Crossing
Example 6 involves four programming cycles of which the first is used to transfer 32-bit data and the remaining
three contain boundary crossing of the SYNLE signals.

Programming Cycle 1
Program cycle 1 is identical to the one in Example 5. Thirty-two bits of data are transferred with the SYNLE
signals being forced to a low state at the beginning of the cycle.

Programming Cycle 2
Program cycle 2 is identical to the one in Example 5. SYNLEO is enabled by SEL [2:0]=001 and moves from
a low state to a high state when the BIT CNT counter reaches a value equal to the HIGHVAL (1) control field.
Note that the LOWVAL control field is set to a value of 0 and is less than the value in the HIGHVAL control field.
By this means, the SYNLEO signal will cross the program cycle boundary in a high state.

Programming Cycle 3
SEL [2:0] is set to 110, which enables a state change in the SYNLE1 and SYNLE2 signals. Because SYNLE1
and SYNLE2 are initially in a low state and LOWVAL is less than HIGHVAL, LOWVAL has no effect on SYNLE1
and SYNLE2. However, because HIGHVAL is given a value of 1, SYNLE1 and SYNLE2 transition from a low
to a high state on BIT CNT count of 1.

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Programming Cycle 4

SEL [2:0] is set to 111, which enables a state change in the all SYNLE Signals. Because all SYNLE signals are
initially in a high state and HIGHVAL is less than LOWVAL, HIGHVAL has no effect on the SYNLE signals.
However, because LOWVAL is given a value of 30, all the SYNLE signals transition from a high to a low state
on BIT CNT count of 30.

-I
"tJ

Note also that the SYNCLK signal is still suppressed to its idle low state throughout program cycles 2 through
4 by CLKDIS being set to 1.

m
<
-

Program Cycle 1
CLKDIS = 0
CLKPOL= 1
IDLPOL = 1
NUMCLKS=O
HIGHVAL = 1
LOWVAL=O
SEL [2:0] = 000

m
~

1 -

- 30 31

Program Cycle 2
CLKDIS = 1
CLKPOL = 1
IDLPOL = 1
NUMCLKS=O
HIGHVAL = 1
LOWVAL=O
SEL [2:0] = 001

1 -

- 3031

Program Cycle 3
CLKDIS = 1
CLKPOL= 1
IDLPOL = 1
NUMCLKS=O
HIGHVAL = 1
LOWVAL=O
SEL [2:0] = 110

1 -

- 30 31

Program Cycle 4
CLKDIS = 1
CLKPOL= 1
IDLPOL = 1
NUMCLKS=O
HIGHVAL= 0
LOWVAL=30
SEL [2:0] = 111

1 -

BITCNT
SYNCLK
SYNDTA
SYNLEO
SYNLE1,2

Figure,11. Example 6: 32-Bit Data Transfer with SYNLE Boundary Crossing

•
TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

- 3031

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

power control port
For systems requiring minimum system current consumption, power can be provided to each functional part
of the TCM4301 only when that function is required for proper system operation. To accomplish this, the
TCM4301 provides six external power control signals accessible through the DStatCtrl and MStatCtrl registers.
These signals can be used to minimize the ON time of the functional units. These power control signals are
SCEN, FMRXEN, IQRXEN, TXEN, PAEN, and OUT1 (see Table 16). The polarity of each of these signals is
high enable, low disable.

Table 16. External Power Control Signals
SUGGESTED EXTERNAL APPLICATION

NAME

RESET
VALUE

SCEN

Speech codec (microphone/speaker interface circuit) enable

FMRXEN

FM demodulator enable

IORXEN

I and 0 receive enable. Enables OPSK demodulator and AGC amplifier

TXEN

Transmit enable. Enables power to the transmitter signal processing
circuits: OPSK modulator, voltage-controlled amplifier, driver amplifier,
PA negative bias. This signal can be used to enable these subsystems
only during the TX burst in digital mode.

OUT1

User defined

PAEN

Power amplifier enable. Enables power to PA.

==
w

In addition to allowing control of power to external functional modules, these power control bits combined with
other control bits are used to control internal TCM4301 functions. This control system is shown in Figure 12.

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oa:

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-83

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

power control port (continued)
WBD_ON

t---------_e__-----.

WBD Demodulator Circuit

.---~--------------------

OUT1

FMRXEN

MCSCEN

SC Clock Generation

SCEN

~--------------- SCEN

FMRXEN

~--------------

FMRXEN

, - - - - - . . Q-Side Input MUX
VHR_ON
FMVOX
DStatCtrl

-c

Q-Side RX Enable

OUT1

I-Side RX Enable
IQRXEN

~==~~---~t-----'~--------r-~------

VHR High Drive Enable
(Hi-Z when disabled)
IQRXEN

TXEN
~==~-------~~-------~.--------TXEN

MODE
1----"-=-=-==--__
- __----1--.

-C

~~--+--+-----I~~--------------

o-I

TXGO

TX and RX Filter Select
TX Signal Processing
PWRCONT, Enable (Hi-z When Disabled)
SYNOL

MStatCtrl

Transmitter
Control
Circuits

~-----------

~------------+----------------

PAEN

TXONIND

MPAEN
~------------------------~.AGCEN
t---------------------------~~AFCEN

Figure 12. Internal and External Power Control Logic

"TEXAS
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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

power control port (continued)
To allow for further system power savings, the TCM4301 receive I and 0 channels are enabled separately
because only the 0 side is used in analog mode. The FMVOX bit controls the Q-side input multiplexer. When
FMVOX is high, the OP side of the receiver is connected to the FM input terminal, the ON input is connected
to the VHR reference voltage, and the side of the receiver is powered up. The MODE bit controls the O-side
filter characteristics for digital or analog mode. The IORXEN bit enables both the I and 0 receiver sides. The
bit IORXEN can be set high while still in analog mode (FMVOX high or MODE low) to allow sufficient power-up
settling time for the external receiver I and 0 circuits.

Setting the MODE bit low connects the RXOP to the FM input and RXON to VHR. VHR can be enabled at any
time by setting VHR_ON high.
In the digital mode (MODE bit set high), setting IORXEN high turns on both sides of the receiver. The TXEN
enables the internal TX functions. When the TXEN bit is set low, the PWRCONT output goes to a
high-impedance state and the PAEN output is set low. The TXEN signal can be used to power down most of
the external transmit circuits between transmit bursts.
In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The SYNOL
input can be used as an indication to the TCM4301 that the external synthesizers are out of lock. The PAEN
signal is gated by SYNOL to prevent off-channel transmissions.
The TXEN, IORXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the
DStatCtrl register with the internal SINT. The effect of a write to the DStatCtrl register on these signals does not
appear until the next SINT after the write.

3:
->w
w
a:
a..
t-

::l
C

a:
a..

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-85

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

microcontroller-DSP communications
The microcontroller and the DSP communicate by means of two separate 32-byte first-in first-out (FI FO) buffers.
Figure 13 illustrates this scheme. The microcontroller writes to FIFO A, but data read from the same address
comes from FIFO B. On the DSP side, the situation is reversed.
To send data to the DSP, the microcontroller writes data to FIFO A. To indicate to the DSP that FIFO A is ready
to be read, the microcontroller writes a 1 to the Send-C bit of the microcontroller interrupt control register
MlntCtrl. When this happens, the DSP interrupt line CINT goes active, signaling to the DSP that data is waiting.
At the same time, the value that can be read from the Clear-C bit in the DlntCtrl register goes from 0 to 1,
indicating that the interrupt is pending. When the DSP writes a 1 to the Clear-C bit, the CINT line returns to the
inactive state and the value that can be read from Clear-C is O. The microcontroller cannot deassert the CINT
line.
The microcontroller-DSP communications interface is symmetric. Data sent from the DSP to the microcontroller
is handled as described above, with the roles of A and B FIFOs and C and D bits and interrupts reversed. If the
'
number of reads exceeds the number of writes from the other side, the values read are undefined.
FPREN (accessible by both the DSP and microcontroller) in the WBDCtrl register can be used to enable (active
high) FIFO pointer resets. When this bit is set, the central processing unit (CPU) write pointer and the DSP read
pointer are cleared whenever the CINT interrupt is cleared; and the CPU read pointer and the DSP write pointer
are cleared whenever the DINT interrupt is cleared. The interrupts do not have to be active for the pointer clear
to occur. In addition, these pointers are cleared whenever there is a powerup or reset.

o
c
o

Send CINT,
CINT Status,
Clear DINT

c:
-I
."

FIFO A

:::m
=E

Send DINT,
DINT Status,
Clear CINT

Figure 13. Microcontroller-DSP Data Buffers

•
TEXAS
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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

microcontroller register map
The microcontroller can access 17 locations within the TCM4301. The register locations are 8 bits wide, as
shown in Table 17 and Table 18.
Table 17. Microcontro"er Register Map
AOOR

NAME

OOh

WBDCtrl

WBD_LCKD

I 06
I WBD_ON

1 02 I 01 I
-r VHR_ON I M_INT_POL I

WBD_BW

DO
FPREN
LSB

OOh

WBD

MSB

01h

FIFO

MSB

02h

MlntCtrl

ClearWBD

03h

SynDataO

MSB

LSB

04h

SynData1

MSB

LSB

OSh

SynData2

MSB

LSB

06h

SynData3

MSB

07h

SynCtrlO

08h

SynCtrl1

09h

SynCtrl2

LSB

FIFO A(B) Microcontrolier to DSP (DSP to Microcontrolier)

Clear-F

Clear-D

Send-C

AGCEN

AFCEN

FMRXEN

LSB
LOWVAL

SEL[2:0]
CLKDIV[1 :0]
CLKDIS

IDLPOL

MSB/LSB FIRST

HIGHVAL

CLKPOL

NUMCLKS

;::

MC_CLK_DIV[5:0]

OAh

MCClock

DSP_CLK_DIV[1 :0]

OBh

RSSI AiD

MSB

LSB

OCh

BAT AiD

MSB

LSB
LSD

ODh

LCD D/A

MSB

OEh

MStatCtrl

SYNOL

I TXONIND

SYNRDY

MCLKEN

Reserved
CVRDY

AuxFS1

I
I

MCSCEN
AuxFSO

I
I

LCDEN
MPAEN

OFh

TXIOffset

Reserved

Sign

MSB

LSB

10h

TXQ Offset

Reserved

Sign

MSB

LSB

NAME

OOh

WBDCtrl

OOh

WBD

CATEGORY
Wide-band data

FIFO A(B) microcontroller to DSP (DSP to microcontroller)

::l
C

RIW

o
a:

W
R

D..

W/(R)

01h

FIFO

02h

MlntCtrl

03h

SynDataO

04h

SynData1

05h

SynData2

06h

SynData3

07h

SynCtrlO

08h

SynCtrl1

09h

SynCtrl2

OAh

MCClock

Microcontroller clock speed

OBh

RSSI AiD

RSSllevel

OCh

BAT AiD

Battery level monitor

ODh

LCD D/A

LCD contrast control

OEh

MStatCtrl

Miscellaneous status!control

OFh

TXIOffset

10h

TXQ Offset

Interrupt/control status

RIW

W
Synthesizer interface

Transmit dc offset compensation

RIW

W
W

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

w
a:

D..
I-

Table 18. Microcontro"er Register Definitions
ADDR

->W

8-87

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136}
SLWS042 - JUNE 1996

WBDCtrl

5-3

WBD_BW[2:0]

RNI

R/W

RNI

FPREN

When reading the WBDCtrl register, bit 7 (MSB) is the last received data bit.
The definition of the WBDCtrl register, according to the DSP register map, is shown in Table 19.

Table 19. WSOCtrl Register

"tJ

BIT

R/W

NAME

FUNCTION

RESET VALUE

R/W

WBD_LCKD

Wide·band data lock data. Determines whether edge detector is locked (1) or unlocked (0).

R/W

WBD_ON

Wide·band data on. Turns the WBDD module on/off (1/0).

7-5

R/W

WBD_BW[2:0]

Wide·band data bandwidth. Sets the appropriate PLL bandwidth.
000 :
20 Hz
001 :
39 Hz
010 :
78 Hz
011 :
156 Hz
100 :
313 Hz
101 :
625 Hz
110 : 1250 Hz

VHR_ON

Half-rail reference voltage is turned on/off (1/0)

C
C

-I

"tJ

m
<

-m

=as defined by MTS(0:1), 1 =inverted as defined by

0
110

M_INT_POL

Microcontroller Interrupt polarity bit: 0
MTS(1:0)

FPREN

FIFO pointer reset enable. When set(1). the read painter in the FIFO is reset when the
interrupt (CINT or DINT) is cleared. When reset(O). the read painter in the FIFO is not acted
on when the interrupt is cleared.

Reserved

1-0

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

microcontroller status and control registers
MCClock:
7-6

5-0

MCClock

This location is used by the microcontrollerto change the speed of its own clock and the DSP clock. The division
modulus is equal to a binary coded value written into MC_CLK_DIV[S:O]. Writing a 0 is prohibited. The reset
value is divide by 32. The clock speed change occurs after the write completes writing to DSP_CLK_DIV[1 :0]
and sets the speed of MCLKOUT as follows:
DSP_CLK_DIV(1 :0)

MCLKOUT CLOCK
FREQUENCY

38.88 MHz

19.44 Mhz

9.72 MHz

4.86 MHz

MlntCtrl Bits [7:4]: These bit names in this field indicate the resulting action when the bit is set to 1. When these
bits are being read, a 1 indicates that the corresponding interrupt is pending. A 0 indicates that the interrupt is
clear. Writing a 0 into any bit location has no effect.
MlntCtrl Bits [3:1]: These bits enable power to the AGC and AFC DACs and their corresponding outputs.
FMRXEN can be used to assert (set to 1) the FMRXEN external function. The reset value is 0 (off).

MlntCtrl

ClearWBD

Clear-F

Clear-D

8end-C

AGCEN

AFCEN

RNI

::J

MStatCtrl: This register contains various signals needed for system monitoring and control (see Table 20).

M8tatCtri

>
w
a.
t-

o
FMRXEN

s:w

8YNOL

TXONIND

8YNRDY

MCLKEN

CVRDY

AuxF81

AuxF80

MPAEN

RIW

RNI

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8-89

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

microcontroller status and control registers
Table 20. MStatCtrl Register Bits
BIT

"tJ

:IJ

R/W

NAME

RESET VALUE

Ext. pin

SYNOL

TXONIND

Transmitter on indicator. Equal to level applied to TXONIND input pin. Can be used to indicate
power is applied to power amplifier.

Ext. pin

SYNRDY

Synthesizer interface ready to be programmed by the microcontroller. When a 1, the
microcontroller can program the frequency synthesizer interface. A 0 indicates the interface
circuit is busy.

R/W

MCLKEN

MCLKOUT enable. When set to 1 by the microcontroller, the 38.88-MHz master clock is sent out
via MCLKOUT. Writing 0 to this bit disables MCLKOUT signal.

CVADY

Conversion ready. A 1 indicates that the latest RSSI or battery voltage ND conversion is complete
and can be read from the ASSI or battery register location. Goes to 0 when microcontroller reads
from either of these locations.

AuxFS[1]
R/W
AuxFS[O]

1
0

R/W

MPAEN

Auxiliary DACs full-scale select. The auxiliary DACs are AGC, AFC, PWACONT and also LCD
CONTR DAC. The microcontroller selects the full-scale output ranges with these bits. See
Table 12 and Table 13 for bit-to-output range mapping.
Microcontroller PA enable. A 0 indicates the external PA enable line PAEN is prevented from going
active. See Figure 12.

-I
"tJ

:IJ

TXI(Q) Offset

7-6

5-0

Reserved

TXI(Q) Offset Value

=:s

0
0
0

TXI Offset and TXQ Offset: These registers allow the differential offset voltages TXIP - TXIN and TXQP - TXQN
to be adjusted to compensate for internal and/or external offsets. The magnitude of adjustment is D x step size,
where D is a 6-bit, 2s complement integer written into bits 5-0 of these registers (see Table 6).

FUNCTION
Synthesizer out of lock. Equal to level applied to SYNOL input pin. Can be used as an input for
an externally generated status signal to prevent transmission when external synthesizers are out
of lock. In digital mode, when SYNOL is high, PAEN will not be asserted and no signal can be
transmitted from TXIP, TXIN, TXQP, and TXQN.

LCD contrast
LCD contrast register allows for 16 levels of control of terminal LCD contrast. The register is input to the LCD
contrast D/A allowing control of the level of intensity of the LCD display.

LCD D/A

7-4

3-2

LCD Contrast

Reserved

~TEXAS

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TCM430'1
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

NAME

OOh

WBD

MSB

02
LSB

I FPREN

Reserved

01h

WBDCtrl

WBD_LCKD

WBD_ON

02h

RXI

Sign

MSB

LSB

03h

RXQ

Sign

MSB

LSB

04h

TXI

Sign

MSB

LSB

OSh

TXQ

Sign

MSB

06h

FIFO

MSB

07h

DlntCtrl

ClearWBD

08h

Timing Adj

MSB

09h

AGC DAC

MSB

WBD_BW

VHR_ON

MJNT_POL

LSB
FIFO A(B) microcontroller to DSP (DSP to microcontroller)

SDIS

Reserved

I Clear-C I Send-D I

Send-F

LSB

Reserved

LSB

Reserved

Reserved
LSB

OAh

AFC DAC

MSB

LSB

Reserved

OBh

PWR DAC

MSB

LSB

Reserved

OCh

DStatCtrl

TXGO

ODh

BSTOffset

OEh

Slp_Cmp

MSB

OEh

Slp_Cntr

MSB

OFh

MODE

I SCEN I FMVOX I FMRXEN I

IQRXEN

TXEN

I OUT1

Reserved

Slp_Ctrl

RXOF
MSB

I ALB
I LSB
LSB

Reserved

TEST
(RIW)

STP3MR(W)
MCSM(R)

STR3MR(W)
TMR_STS(R)

LSB

Slp_Cntr[12: 1O](R)
Slp_Cmp[12:10](W)

NAME

OOh

WBD

01h

WBDCtrl

02h

RXI

03h

RXQ

04h

TXI

05h

TXQ

...

:::)

Table 22. DSP Register Definitions
ADDR

w
:>
w
a:
c.

CATEGORY
Wide-band data

RIW

RX channel AID results

Digital mode: 7t/4 DQPSK modulator input data

oa:

RIW

Wide-band data control

Analog mode: TXI D/A data

Analog mode: TXQ D/A data
Digital mode: Not used

06h

FIFO

07h

DlntCtrl

08h

Timing Adj

Symbol timing adjust

09h

AGC DAC

AGC

OAh

AFC DAC

AFC

OBh

PWR DAC

Power control

OCh

DStatCtrl

ODh

BSTOffset

TDM burst offset

OEh

Slp_Cmp

Sleep compare data

OEh

Slp_Cntr

Sleep counter data

OFh

Slp_Ctrl

Sleep mode control

RIW

FIFO A(8) microcontroller to DSP (DSP to microcontroller)
Interrupt control/status

Miscellaneous status/control

R/(W)
RIW

W
RIW

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8-91

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

wide-band data registers
Bit 9 of the wide-band data register is the most recently received bit.

WBD

9-2

1-0

WB Data

Reserved

R
9

WBDCtrl

7-5

I WBD_LCKD I WBD_ON
RIW

432

WBD_BW[2:0]

RIW

1-0
Reserved

RIW

base station offset register
BST offset values are 00, 01, 10, and 11 corresponding to an offset value d of 0, 1, 2, and 3 respectively.
BST

9-2

1-0

Reserved

Offset[1:0]

Offset

"'C

The delay in the TCM4301 TX channels is increased by the amount

d x T SINT
4

o
C

-I

DSP status and control registers
OlntCtrl, Clear and Send Bits: The bit names in the OlntCtrl register indicate the action to be taken when a 1
is written to the bit. When reading these bits, a 1 indicates that the corresponding interrupt is pending. A 0
indicates that the interrupt is not pending. Writing a 0 to any bit has no effect. Writing a 1 to the clear bits clears
the corresponding interrupt, and the interrupt terminal returns to its inactive level. Writing a 1 to the send bits
causes the corresponding interrupt to go active.

"'C

OlntCtrl, SOlS: When a 1 is written to SOlS, the SINT interrupt going to the OSP is disabled. The disabling and
re-enabling function is buffered to prevent the SINT signal from having shortened periods of output active. The
SDIS bit is active (1) upon reset.
8

4-0

DlntCtrl

Reserved
RIW

DStatCtrl

TXGO

MODE

SCEN

FMVOX

I FMRXEN I IQRXEN
RIW

•
TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TXEN

OUT1

RXOF

ALB

TCiV14301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

DSP status and control registers (continued)
The DStatCtrl register contains various signals needed for system monitoring and control. These are described
in Table 23.
Table 23. DStatCtrl Register Bits
BIT

R/W

NAME

RESET VALUE

FUNCTION

TXGO

Transmitter go. Used in digital mode, to initiate (1) and terminate (0) a transmit burst.

MODE

Digital (1) - Analog (0) mode select. Affects the clock dividers and the transmitter modes of
operation and the 0 side filter.

R/W

SCEN

Speech codec enable. (microphone/speaker interface chip.) The SCEN output pin is connected
to this bit. Also enables (1) or disables (0) the internal speech codec clock generation circuits.
(2.048 MHz - 8 kHz outputs)

R/W

FMVOX

FM voice enable. FMVOX = 1 enables the 0 side of the internal receiver circuits and connects the
receivers 0 channel input to FM input pin (see Figure 12).

R/W

FMRXEN

FM receiver enable. The FMRXEN output pin is connected to this bit (see Figure 12).

IORXEN

I and 0 receiver enable. The IORXEN output pin is connected to this bit. Enables (1), disables (0)
power to the I and 0 sides of the internal receiver circuits (see Figure 12).

0
0

R/W

TXEN

Transmitter enable. The TXEN output pin is connected to this bit. Enables (1), disables (0) power
to the internal transmitter circuits (see Figure 12).

OUT1

Output 1. User defined general purpose data or control signal.

0
0

R/W

RXOF

Receive channel offset. RXOF = 1 disconnects the RXIP, RXIN, RXOP, and RXON pins from
receive channel,. and shorts internal RXIP to RXIN and RXOP to RXON. It provides the capability
of measuring dc offset of the receive channel.

R/W

ALB

Analog loop-back. ALB = 1 disconnects the RXIP, RXIN, RXOP, and RXON pins from the internal
receive channels and connects the corresponding internal signals to attenuated copies of the
TXIP, TXIN, TXOP, and TXON signals. The attenuated factor is 8.

>
w

a..

I-

DSPD[9:0]

DSPA[3:0]

DSPRW
DSPSTRBL

;:)

A[3:0]

DSPCSL
TCM43 01

D[15:6]

...
...

SINT

BDINT

DSP

..
..
.....
P'

CINT

a..

RIW
STRB

INT1
INT3
INT4

Figure 14. DSP Interface

~TEXAS

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8-93

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042 - JUNE 1996

DSP sleep registers
Address OFh is decoded to be the sleep mode register (Slp_Ctrl). Bit 5 (active high) is the TEST bit and is used
to allow write-only registers to be read for test purposes. Bit 4 is the stop timer bit (STP_ TMR) which is written
and latched. When read, this bit is the microcontrolier sleep mode bit. Bit 3 is the start timer bit (STR_TMR).
When a 1 is written to this bit, the MCLK delay starts. These control signals are active high and are cleared during
initialization. When bit 3 is read, it is the timer status bit (TMR_STS). It indicates the mode status of the timer
circuit. Bits 2, 1, and 0 are the three most significant bits of the sleep counter for reads from address OFh and
the three most significant bits of the sleep compare register during writes to address OFh.
Address OEh is decoded to be a write-only and a read-only 1O-bit register. The write-only register is the 10 least
significant bits of the sleep compare register (Slp_Cmp). The read-only register is the 10 least significant bits
of the sleep counter (Slp_Cntr).
When TEST = 1, reading address OEh returns the value of the 10 least significant bits of the sleep compare
register. When address OFh is being read, bit 5 is the TEST bit, bit 4 is the MCSM bit, bit 3 is the TMR_STS bit,
and bits 2:0 are the three most significant bits of the sleep compare register.
9-0
Slp_Cmp

~ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

OEh

"tJ
:Jl

MSB

LSB

o
C

9-0
Slp_Cntr L--_M_S_B_______________________________________________________________L_S_B----J
OEh

-I
"tJ

R
9-6
Reserved

2-0

STP_TMR(W)
MCSM(R)

STR_TMR(W)
TMR_STS(R)

Slp_Cntr[12: 1O](R)
Slp_Cmp[12:10](W)

RIW

<
-

Table 24. Slp_Ctrl Register Bits

BIT

RIW

NAME

9-6

N/A

Reserved

RIW

TEST

Enables write-only sleep registers to be read

MCSM

Microcontroller sleep mode status bit

STP_TMR

Stop timer

TMR_STS

Timer status bit. 1

FUNCTION

0
0
N/A
0

=running, 0 =not running

N/A

STR_TMR

2-0

Slp_Cntr[12:101

Three most significant bits of the sleep counter

2-0

Slp_Cmp[12: 101

Three most significant bits of the sleep compare register

Start timer

•
TEXAS
INSTRUMENTS
8-94

RESET VALUE

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

N/A

rCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042 - JUNE 1996

reset
internal reset
A low on RSINL causes the TCM4301 internal registers to assume their reset values. The power-on reset circuit
also causes internal reset. However, the logic level at RSINL has no effect on reset outputs RSOUTH and
RSOUTL.

power-on reset
The power-on reset (POR) is digitally implemented and provides a timed POR signal at RSOUTL and RSOUTH.
The POR pulse duration is equal to 388,800 cycles of MCLKIN (10 ms). There are two outputs to provide a high
reset and a low reset in order to accommodate the reset polarity requirements of any external device. The
TCM4301 internal registers are reset when the POR outputs are activated. See Figure 15.
DVDD

I+--

RSOUTH

/ If

----~----

RSOUTL

tw
,0 ms M;n;mum

90%

I
I

1\
I
I

~10%

~----

3:
w

10%Y

:>
w
a:

Figure 15. Power-On Reset Timing

a..

internal reset state
After power-on reset, the TCM4301 register bits are initialized to the values shown in Table 25. The synthesizer
control pins SYNCLK, SYNLE[0:2], and SYNDTA are high after reset, and the synthesizer interface circuit is
in stable idle state with no SYNCLK outputs.

81T9

DStatCtrl

ext

MlntCtrl
MStatCtri
MCClock

~TEXAS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

::l
C

a..

r: reserved
ext: bit value from external pin

INSTRUMENTS

(.)

o
a:

Table 25. Power-On Reset Register Initialization
DlntCtrl

I-

8-95

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

microcontroller interface
The microcontroller interface of the TCM4301 is a general-purpose bus interface, which ensures compatibility
with a wide range of microcontrollers, including the Mitsubshi M37700 series and most Intel and Motorola series.
The interface consists of a pair of microcontroller type select (MTS[1 :0]) inputs, address and data buses, as well
as several input and output control signals that are designed to operate in a manner compatible with the
microcontroller selected by the user.

Table 26. Microcontroller Interface Configuration
MTSO

Intel

0
1

::D

DSACTIVE

INTERRUPT/OUTPUT ACTIVE

Low (separate Read and Write)

High

Motorola 16-bit and Mitsubishi

Low

Motorola 8-bit

High

Low

Reserved

N/A

The microcontroller interface of the TCM4301 is designed to allow direct connection to many microcontrollers.
Except for the interrupt pins, it is designed to connect to microcontrollers in the same manner as a memory
device.

POLARITY

MODE

MTS1

The internal chip select is asserted when MCCSH

= 1 and MCCSL = O.

Intel microcontroller mode of operation

When the microcontroller type select (MTS[1 :0]) inputs are both held low, the TCM4301 microcontroller
interface is configured into Intel mode (see Table 26). In this mode, the interface uses separate read and write
control strobes and active-high interrupt signals. The processor RD and WR strobe signals should be connected
to the TCM4301 MCDS signal and MCRW signal, respectively. The multiplexed address and data buses of the
microcontroller must be demultiplexed by external hardware. Table 27 lists the microcontroller interface
connections for Intel mode.

-I
-C

::D

m
<
-

Table 27. Microcontroller Interface Connections for Intel Mode
TCM4301 PIN

MICROCONTROLLER PIN

MTS[1:0]

Tie to logic levels: low and low, respectively

MCCSH

Not on microcontroller; can be used for address decoding

MCCSL

Not on microcontroller; can be used for address decoding

MCD[7:0]

AD[7:0] data bus on microcontroller

MCA[4:0]

Demultiplexed address bits not on microcontroller

MCRW

WR (Active-low write data strobe)

MCDS

RD (Active-low read data strobe) MCDS configured to active-low operation by MTS[1 :0].
The microcontroller bus must be demultiplexed by external hardware.

MWBDFINT

One of INT[3:0] as appropriate

DINT

One of INT[3:0] as appropriate

~TEXAS

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TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

Mitsubishi microcontroller mode of operation
When the microcontroller type select (MTS[1 :0]) inputs are held high and low, respectively, the TCM4301
microcontroller interface is configured into Mitsubishi mode. In this mode, the interface has a single read/write
control (R/W) signal, an active-low data strobe (MCDS) signal, and active-low interrupt request signals. The
processor E and R/(W) signals should be connected to the TCM4301 MCDS signal and MCRW signal,
respectively. Table 28 lists the microcontroller interface connections for Mitsubishi mode.

Table 28. Microcontroller Interface Connections for Mitsubishi Mode
MICROCONTROLLER PIN

TCM4301 PIN
MTS[1:0]

Tie to logic levels: high and low, respectively

MCCSH

Not on microcontroller; can be used for address decoding

MCCSL

Not on microcontroller; can be used for address decoding

MCD[7:0]

D[7:0] data bus on microcontroller

MCA[4:0]

A[4:0]

MCRW

RIW

MCDS

E (Active-low read data strobe) MCDS configured to active-low operation by MTS[1 :0].

MWBDFINT

One of INT[3:0] as appropriate

DINT

One of INT[3:0] as appropriate

:=w

:>
w
a:
a..

I-

oa:
a..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-97

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

Motorola microcontroller mode of operation
When the microcontroller type select MTSO = high and MTS1 =low, the TCM4301 microcontroller interface is
configured for 8-bit family (6800 family derivatives, e.g., 68HC11 03 and 68HC11 G5) bus characteristics, and
when the microcontroller type select MTSO = low and MTS1 =high, the microcontroller interface is configured
for 16-bit family (680 x 0 family derivatives, e.g., 68008 and 68302) characteristics. The Motorola mode makes
use of a single read/write control (R/W) signal and active-low interrupt request signals. The processor E (8 bit)
or OS (16 bit) and (R/W) control signals should be connected to the TCM4301 MCOS signal and the MCRW
signal, respectively. Table 29 illustrates the connections between the TCM4301 and an 8-bit Motorola
processor. Table 30 illustrates the connections between the TCM4301 and a 16-bit Motorola processor.
Table 29. Microcontroller Interface Connections for Motorola Mode (8 Bit)
TCM4301 PIN

lie to logic levels: low and high, respectively

MCCSH

Not on microcontrolier; can be used for address decoding

MCCSL

Not on microcontrolier; can be used for address decoding

MCD[7:0]

PC[7:0] data bus on microcontrolier

MCA[4:0]

Demultiplexed address output. PF[4:0] on microcontrolier for non multiplexed machines
(e.g., 68CH11G5) and not on micro for multiplexed bus machines (e.g., 68HC11D3).

MCRW

RIW

"tJ

MICROCONTROLLER PIN

MTS[1:0]

MCDS

E (Active-high data strobe) MCDS configured to active-high operation by MTS[1 :0].

MWBDFINT

IRQ and/or NMI as appropriate

DINT

IRQ and/or NMI as appropriate

-f
."
:D

Table 30. Microcontroller Interface Connections for Motorola Mode (16 Bit)
TCM4301 PIN

m
S

MICROCONTROLLER PIN

MTS[1:0]

lie to logic levels: high and low, respectively

MCCSH

Not on microcontrolier; can be used for address decoding

MCCSL

Not on microcontrolier (68000, 68008) CS1, CS2, or CS3 (68302)

MCD[7:0]

D[7:0] data bus on microcontrolier

MCA[4:0]

A[4:0] (68008)
A[5:1] (68000, 68302)

MCRW

RIW

MCDS

DS (active-low data strobe) (68008)
LDS (active-low data strobe) (68000, 68302) MCDS configured to active-low operation
by MTS[1:0]

MWBDFINT

IACK7, IACK6, or IACK1 (68302)

DINT

One of INT[3:0] as appropriate

Not on microcontrolier (68000, 68008)

•
TEXAS
.
INSTRUMENTS
8-98

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range: DVDD (see Notes 6 and 7): Condition 1 ....................... Vss -0.3 to +6 V
Condition 2 ............... VSS -0.3 to AVDD +0.3 V
AVDD (see Notes 7 and 8): Condition 1 ....................... VSS -0.3 to +6 V
Condition 2 ............... Vss -0.3 to DVDD +0.3 V
Input voltage range, VI: Digital signals ..................................... VSS -0.3 to DVDD +0.3 V
Analog signals .................................... Vss -0.3 to AVDD +0.3 V
Output voltage range, Va: Digital signals ............................................. Vss to DVDD
Analog signals ............................................. Vss to AVDD
Continuous total power dissipation ..................................... '." ..... See Dissipation Table
Operating free-air temperature range, TA ............................................ -40°C to 85°C
Storage temperature range, Tstg ................................................... -65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ........... . . . . . . . . . . . . . . . . . . .. 260°C
NOTES:

6. Voltage values are with respect DVSS.
7. Maximum voltage is the minimum of the two conditions.
8. Voltage values are with respect to AVSS.
DISSIPATION RATING TABLE

PACKAGE

TA S25°C
POWER RATING

DERATING FACTOR (TJA)
ABOVE TA 25°C

TA 85°C
POWER RATING

2222mW

45°CIW

889mW

==
W

s:w

recommended operating conditions
DVDD

Supply voltage

MIN

MAX

UNIT

5.5

DVDD+0.3

0.3 DVDD

VIH

High-level input voltage

Digital

Vil

Low-level input voltage

Digital

VOH

High-level output voltage

Digital

VOL

low-level output voltage

Digital

tOH

High-level output current at 3 V

Digital

rnA

IOl

low-level output current at 3 V

Digital

rnA

IOH

High-level output current at 5 V

Digital

rnA

tOl

low-level output current at 5 V

Digital

Operating free-air temperature

0.7 DVDD
0
0.7 DVDD

DVDD

0.5

rnA

2
-40

°C

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-99

D..
I-

:J
C

D..

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

electrical characteristics power consumption over full range of operating conditions (unless
otherwise noted)
PARAMETER

TEST CONDITIONS
AVDD = 3 V

DVDD = 5.5 V,

AVDD = 5.5 V

DVDD= 3 V,

AVDD= 3 V

DVDD = 5.5 V,

AVDD = 5.5 V

DVDD = 3 V,

AVDD= 3 V

DVDD = 5.5 V,

AVDD = 5.5 V

MCLKOUT enabled

DVDD= 3V,

AVDD=3 V

MCLKOUT disabled

DVDD= 3 V,

AVDD=3 V

Analog transmitting and receiving

Digital receiving

Digital transmitting

Idle mode

MCLKOUT enabled
MCLKOUT disabled
18-136 standby (sleep mode)

Digital mode, 1/3 transmitting + 1/3 receiving + 1/3 standby

"tJ

t All typical values are at TA = 25°C

reference characteristics

:D
C

c:
o
~

"tJ

m
S
m

PARAMETER

VO~(VHR)
rO

MIN

DVDD = 3 V,

45
17

DVDD = 5.5 V,

AVDD = 5.5 V
AVDD=3 V

DVDD = 5.5 V,

AVDD = 5.5 V

DVDD = 3 V,

AVDD=3 V

DVDD = 5.5 V,

AVDD = 5.5 V

TYP*

80
15

220

0.5 AVDD-0.2

FMVOX or IQRXEN or TXEN = low

300

DVDD = 3 V,

FMVOX or IQRXEN or TXEN = high

250

AVDD = 5.5 V

MIN

UNIT
mW

275

DVDD = 5.5 V,

TEST CONDITIONS

MAX

190

High-level output voltage
Output resistance

TYPt

MAX

UNIT

0.5 AVDD+0.2

100

n
kn

:j: All typical values are at DVDD = 5 V, AVDD = 5 V, and TA = 25°C

terminal impedance
MIN

TYP§

Receive channel input impedance (single-ended)

RXIP/N and RXQP/N

Transmit channel output impedance (single-ended)

TXIP/N and TXQP/N

FM input

WBD

200

FUNCTION

MCLKOUT

TERMINAL NAME

MCLKOUT @ 3.3 V

240

MCLKOUT

180

§ All typical values are at DVDD = 5 V, AVDD = 5 V, and TA = 25°C, unless otherwise specified.

~TEXAS

INSTRUMENTS
8-100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MAX

100

UNIT

kn
n
kn
n

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

MCLKOUT timing requirements
MIN

NOM

MAX

twH

Pulse duration high

UNIT

twL

Pulse duration low

Rise time

Fall time

NOTE: Tested with 15 pF loading on MCLKOUT.

PARAMETER MEASUREMENT INFORMATION

\
I:
14-

MCLKOUT ---....JI-.

tw H

---tf

~ 'w L ~ ~-- VOH
iX
.y --- VOL
, I

~ tr

-"!4-

Figure 16. MCLKOUT Timing Diagram

:>
w
a:
a..
t-

::J

a:
a..

~TEXAS

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POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-101

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4301 to microcontroller interface timing requirements (Mitsubishi write cycle)
ALTERNATE
SYMBOL

PARAMETER

UNIT

tsu(R/w)

Setup time, read/write

th(R/w)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCDS)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

TCS(HO)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

tsu(CS)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before
falling edge of strobe (MCDS)

C
C

MAX

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

MIN

TRW(SU)

NOTE: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

~14---- tw(WSTB) ----I.~I

-I

i~10%

tsu(R/W) -.j

I." 90%

90% "\
:

MCDS

10%~ i

f+iI I 14I

I I
----- I I

<
-

I I I ~----

100~,-+-:-----------~il'""""'-:...;Y,O%

MCRW

MCA[4:0]

I ~

tsu(WA)

:
:

90/1
_ _- - I .

--JX

I 1\0%
I I

th{CS)~

tsu{CS) ~14--.t.1

I
MCCSL

14I

' { 10%

10%1

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 17. Microcontroller Interface Timing Requirements
(Mitsubishi Configuration Write Cycle, MTS[1 :0] = 10)

•
TEXAS
INSTRUMENTS
8-102

tsu(WA)

X,---. X'-____

14-- tsu(W) ----.l ~ t
I
:
I h(W)

MCD[7:0] _ _ _ _ _ _ _.,._ _ _ _ _

MCCSH

th(R/W)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCiv14301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT {ARCTIC™136)
SLWS042-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4301 to microcontroller interface timing requirements (Mitsubishi read cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(RIW)

Setup time, read/write

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

TRW(SU)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(RA)

Setup time, read address

Read address (MCS) stable before falling edge of
strobe (MCDS)

TRA(SU)

th(RA)

Hold time, read address

Read address (MCA) stable after rising edge of
strobe (MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4301 driving
data bus (MCD)

TRD(EN)

tv(R)

Read data valid time

Falling edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe
(MCDS)

TRD(INV)

tdis(RD)

Disable time, read data

TCM4301 releases data bus after rising edge of
strobe (MCDS)

TRD(DIS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before
falling edge of strobe (MCDS)

TCS(SU)

th(CS)
tsu(CS)

NOTE: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

~O%

MCDS
tsu(R/W)

-.I

I
MCRW

1 1
1.1

MCA [4:0]

MCD [7:0]

~90%
tsu(CS)

MCCSL

1 1
1 I
1 1
I 1
~I

tsu(RA)

141

th(R/W)

oa:

\90%

:1 ~tV(R)

'en(RO)

MCCSH

1 I

90;

-H

I4t

th(RA)

';nv~~

tdis(RD)

1
1
1
1
~

%1\

th(CS)~

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 18. Microcontroller Interface Timing Requirements
(Mitsubishi Configuration Read Cycle, MTS[1 :0] = 10)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I-

90;tf
10o~

1 • 10%
1

w
>
w
a:
c.

8-103

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4301 to microcontroller interface timing requirements (Intel read cycle)
ALTERNATE
SYMBOL

PARAMETER

UNIT

Read address (MCA) stable before falling edge of
strobe (MCDS)

TRA(SU)

Hold time, read address

Read address (MCA) stable after rising edge of
strobe (MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4301 driving
data bus (MCD)

TRD(EN)

tv(RD)

Valid time, read data

Falling edge of strobe (MCDS) to valid data (MCD)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe
(MCDS)

tdis(RD)

Disable time, read data

tsu(CS)
th(CS)

th(RA)

MAX

Setup time, read address

tsu(RA)

-c

MIN

TRD(DV)

TRD(INV)

TCM4301 releases data bus after rising edge of
strobe (MCDS)

TRD(DIS)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(SU)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

NOTE: Timings based upon Intel 80C186 (16 MHz)

C
C

t\0%
1 10%

MCDS

-I

141

MCA[4:0]

ten(RD)
MCD[7:0]

;190%

MCCSH
tsu(CS)
MCCSL

97f

10~

I.tl

tsu(RA)

:1 :~tV(RD)

r~
1
1
1
1

141

I 1
I 1
1 1

1 :
1 I
1 I

MCRW

-C

~ th(RA)

::
1411

t;nv~~

tdis(RD)

1
1

:90%~

th(CS)~

10%Y

' { 10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 19. Microcontroller Interface Timing Requirements
(Intel Configuration Read Cycle, MTS[1 :0] 00)

•
TEXAS
INSTRUMENTS
8-104

ns
50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4301 to microcontroller interface timing requirements (Intel write cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCRW)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCRW)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCRW)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCRW)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

tsu(CS)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCRW)

TCS(SU)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCRW)

TCS(HO)

th(CS)

~
w
5>
w
a::
a.

NOTE: Timings based upon Intel8C186 (16 MHz).

MCDS - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

~14--- tw(WSTB)

90%

MCRW

\.1!'\

I
~

___x
1

MCA[4:0]

¥III

10%

90%

10% _

I i4

(WA)

X,--_

I-

th(WA)

::l
C

oa::

~ tsu(W) ~ :~ th(W)

.--JX

MCD [7:0] ______________..,..__________

X'-_____

MCCSH

-----'. I

I I -.- - - - - -

tsu(CS)

----14-----.t.1

th(CS) ----.j

MCCSL

~O%

901f

14I

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCRW active.

Figure 20. Microcontroller Interface Timing Requirements
(Intel Configuration Write Cycle, MTS[1 :0] 00)

~TEXAS

INSTRUMENTS
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8-105

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4301 to microcontroller interface timing requirements (Motorola 16-bit read cycle)
ALTERNATE
SYMBOL

PARAMETER

"tJ

::D

MAX

UNIT

tsu(R/W)

Setup lime, read/write

Read/write (MCRW) stable before falling edge of strobe
(MCDS)

th(RIW)

Hold time, read/write

Read/write (MCRW) stable after rising edge of strobe
(MCDS)

TRW(HO)

tsu(RA)

Setup time, read address

Read address (MCA) stable before falling edge of
strobe (MCDS)

TRA(SU)

th(RA)

Hold time, read address

Read address (MCA) stable after rising edge of strobe
(MCDS)

TRA(HO)

ten(RD)

Enable time, read data

Falling edge of strobe (MCDS) to TCM4301 driving data
bus (MCD)

TRD(EN)

tv(RD)

Valid time, read data

Falling edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after rising edge of strobe (MCDS)

TRD(lNV)

Disable time, read data

TCM4301 releases data bus after rising edge of strobe
(MCDS)

TRD(DIS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before falling
edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select stable (MCCSH and MCCSL) before rising
edge of strobe (MCDS)

TCS(SU)

tdis(RD)

th(CS)

c:
o

tsu(CS)

MIN

TRW(SU)

NOTE: Timings based upon Motorola 68HCOOO (16.67 MHz) and Motorola 68302 (16 MHz).

-I
"tJ

"\ 90%
90%*
i~~·1~0_%______________
10_%~~i

MCDS

::D

tsu(R/W) ----:

m
S
m

MCRW

MCA[~~

-----___

-H

4
i:I I

14I I I

I I

~~~~ ~~·~~_~_U_~_A_)
__

: \-' - - - - - - -

I I

_____

~tV(RD)

t_e_n(_R_D)_~T_!-~s~

MCD [7:0] _ _ _ _ _ _

MCCSH

/!-%1 90%

_ _ _ _ _..I

tsu(CS)
MCCSL

I
I
I

iIIIII

th(R/W)

~~~:~_~~~:_~_~

"'JIII-t-I-..~~tdis(RD)

'inv

T~~-----1

th(CS)

~ ~----

10%Y

10%

-NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 21. Microcontroller Interface Timing Requirements
(Motorola 16-Bit Read Cycle, MTS[1 :0] = 10)

~TEXAS

INSTRUMENTS
8-106

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

TCM4301 to microcontroller interface timing requirements (Motorola 16-bit write cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (MCRW) stable before falling edge of
strobe (MCDS)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (MCRW) stable after rising edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before falling edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after rising edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before rising edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after rising edge of strobe
(MCDS)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

th(CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(SU)

tsu(CS)

NOTE: Timings based upon Motorola 68HCOOO (16.67 MHz) and Motorola 68302 (16 MHz).

1411111f-------- tw(WSTB)

---~~I

90% "\ :

MCDS

i \. 10%

tsu(R/W) ---.j

10%

I I
II

-----IX :
'

MCD [7:0]

(WA)

:J
C

th(R/W)

901f

o
a::

. X'-____
I t\0%
I I

th(CS)~

tsu(CS) -1~1III-~~1

'\L

c..

th(WA)

~ 'su(W) ---->I ~:
I 'h(W)

1l1li

-------"T.-----~X
_ _---J.

MCCSL

-r.;I I I!IIII-

III~_ _ __

MCCSH

90%

10~~i____________________~'~:~~0%

MCRW

MCA [4:0]

-I i

14I

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 22. Microcontroller Interface Timing Requirements
(Motorola 16-Bit Write Cycle, MTS[1 :0] = 10)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

->w
w
a::
c..
Io

8-107

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4301 to microcontroller interface timing requirements (Motorola a-bit read cycle)
ALTERNATE
SYMBOL

PARAMETER

:c
o
c

o-I

MIN

MAX

UNIT

tsu{RJW)

Setup time, read/write

Read/write (MCRW) stable before rising edge of
strobe (MCDS)

TRW{SU)

th{RJW)

Hold time, read/write

Read/write (MCRW) stable after falling edge of
strobe (MCDS)

TRW{HO)

tsu{RA)

Setup time, read address

Read address (MCA) stable before rising edge of
strobe (MCDS)

TRA{SU)

th{RA)

Hold time, read address

Read address (MCA) stable after falling edge of
strobe (MCDS)

TRA{HO)

ten{RD)

Enable time, read data

Rising edge of strobe (MCDS) to TCM4301 driving
data bus (MCD)

TRD{EN)

tv(RD)

Valid time, read data

Rising edge of strobe (MCDS) to valid data (MCD)

TRD(DV)

tinv

Data invalid time

Data (MCD) invalid after falling edge of strobe
(MCDS)

TRD{INV)

tdis{RD)

Disable time, read data

TCM4301 releases data bus after falling edge of
strobe (MCDS)

TRD{DIS)

th{CS)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS{HO)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS{SU)

tsu{CS)

NOTE: Timings based upon Motorola 68HC11 D3 (3 MHz) and Motorola 68HC11 G5 (2.1 MHz).

MCDS

10%
tsu{R/W)

~
I

9O
1

H-

90%~
1

I
I 1
I ~I

MCA[4:0]

ten~D)

MCD[7:0]

1 1
1 I..

tsu(RA)

: :~tV(RD)

T~
1

II1II1

th(CS)
MCCSL

II1II

~ tdis(RD)

:90%~

tsu(CS)~

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 23. Microcontroller Interface Timing Requirements
(Motorola 8-Bit Read Cycle, MTS[1 :0] =01)

~TEXAS

INSTRUMENTS
8-108

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

th(RA)

I
1

1
1

tlnv~~

,,90%

th(R/W)

i i \-

MCCSH

10%

~~
1 1 I

I 1

MCRW

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042-JUNE 1996

PARAMETER MEASUREMENT INFORMATION
TCM4301 to microcontroller interface timing requirements (Motorola a-bit write cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (MCRW) stable before rising edge of
strobe (MCDS)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (MCRW) stable after falling edge of
strobe (MCDS)

TRW(HO)

tsu(WA)

Setup time, write address

Address (MCA) stable before rising edge of strobe
(MCDS)

TWA(SU)

th(WA)

Hold time, write address

Address (MCA) stable after falling edge of strobe
(MCDS)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (MCD) before falling edge of strobe
(MCDS)

TWD(SU)

th(W)

Hold time, write data

Data stable (MCD) after falling edge of strobe
(MCDS)

TWD(HO)

twJWSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

Hold time, chip select

Chip select (MCCSH and MCCSL) stable before
rising edge of strobe (MCDS)

TCS(HO)

Setup time, chip select

Chip select (MCCSH and MCCSL) stable before
falling edge of strobe (MCDS)

TCS(SU)

th(CS)
tsu(CS)

NOTE: Timings based upon Mitsubishi 37732S4 (16 MHz) and Mitsubishi 3772S4L (8 MHz).

1e11lll---- tw(WSTB)
MCDS

_ _ _ _ _10%
_...J,/_
tsu(R/W)

10%

___X

"i/

I-

14I th(R/W)

, }

(WA
su

"1111

)

t
su(W)

10%

~·------------------------~'-+I~

~
MCA[4:0]

++I
, ,

,:'
~

MCRW

c..

90%~i"',___
--. 1;..;.0..;,;%;......_ _ _ __

~ ,I+-

c..

th(WA)

X""---_

* - - :

th(W)

. X"'--____

MCD [7:0] _____________.....,....__________
:
MCCSH

90/1
_ _---J.

I 1\0%
I
th(CS) -----1>/
14-

tsu(CS) ____
~--oo!~

MCCSL

·
..... - - - -

10%Y

10%

NOTE: Chip selection is defined as both MCCS and MCDS active.

Figure 24. Microcontroller Interface Timing Requirements
(Motorola a-Bit Write Cycle, MTS[1 :0] 01)

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

:>
w
a:

90%

::w

8-109

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
switching characteristics, TCM4301 to DSP Interface (write cycle)
ALTERNATE
SYMBOL

PARAMETER

o
c
c

UNIT

Read/write (DSPRW) stable before falling edge of
strobe (DSPSTRBL)

TRW(SU)

Hold time, read/write

Read/write (DSPR W) stable after rising edge of
strobe (DSPSTRBL)

TRW(HO)

tsu(CS)

Setup time, chip select

Chip select stable (DSPCSL) before falling edge of
strobe (DSPSTRBL)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (DSPCSL) stable after rising edge of
strobe (DSPSTRBL)

TCS(HO)

tsu(WA)

Setup time, write address

Address (DSPA) stable before falling edge of strobe
(DSPSTRBL)

TWA(SU)

th(WA)

Hold time, write address

Address (DSPA) stable after rising edge of strobe
(DSPSTRBL)

TWA(HO)

tsu(W)

Setup time, write data

Data stable (DSPD) before rising edge of strobe
(DSPSTRBL)

TWD(SU)

th(W)

Hold time, write data

Data stable (DSPD) after rising edge of strobe
(DSPSTRBL)

TWD(HO)

tw(WSTB)

Pulse duration, write strobe

Write strobe pulse width

TWR(STB)

th(R/w)

MAX

Setup time, read/write

tsu(R/w)

'1:J

MIN

(')

DSPCSL

-I

\10%
10%/
-+! l4-.I :.l4-- tw(WSTB) ---.J.I I
- - - - - - - 190%
90%i
tsu(CS)

'1:J

:c
m

DSPSTRBL

tsu(R/W)

m
~

DSPRW

'
N
~ I.-

10%

th(CS)

}iI---------

10%

fi
I

'J. !

I I

y,......---th(R/W)

DSPA

DSPD

Figure 25. TCM4301 to DSP Interface (Write Cycle)

•
TEXAS
INSTRUMENTS
8-110

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4301
ADVANCED RF CELLULAR TELEPHONE INTERFACE CIRCUIT (ARCTIC™136)
SLWS042 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION
switching characteristics, TCM4301 to DSP Interface (read cycle)
ALTERNATE
SYMBOL

PARAMETER

MIN

MAX

UNIT

tsu(R/w)

Setup time, read/write

Read/write (DSPRW) stable before falling edge of
strobe (DSPSTRBL)

TRW(SU)

th(R/w)

Hold time, read/write

Read/write (DSPRW) stable after rising edge of
strobe (DSPSTRBL)

TRW(HO)

tsu(CS)

Setup time, chip select

Chip select stable (DSPCSL) before falling edge of
strobe (DSPSTRBL)

TCS(SU)

th(CS)

Hold time, chip select

Chip select (DSPCSL) stable after rising edge of
strobe (DSPSTRBL)

TCS(HO)

tsu(RA)

Setup time, read address

Read address (DSPA) stable before strobe
(DSPSTRBL) goes low

TWA(SU)

th(RA)

Hold time, read address

Read address (DSPA) stable after strobe
(DSPSTRBL) goes high

TWA(HO)

ten(R)

Enable time, read data

Falling edge of strobe (DSPSTRBL) to TCM4301
driving data bus (DSPD)

TRD(EN)

td(DV)

Delay read data valid time

Falling edge of strobe (DSPSTRBL) to valid data
(DSPD)

TRD(DV)

th(R)

Hold time, read data

Data (DSPD) invalid after rising edge of strobe
(DSPSTRBL)

TRD(INV)

tdis(R)

Disable time, read data

TCM4301 releases data bus after rising edge of
strobe (DSPSTRBL)

TRD(DIS)

50
5

ns
ns

w
>
w
a:

I-

tsu(CS) ~

tsu(R/W)
DSPRW

1)0%
,10%
--H

9°1
10lIl

DSPA

10%9°11

~th(R/W)

:: \0%

c
o

--.I :.- th(CS)

l41

DSPSTRBL

10%/

\10%

DSPCSL

1 1

tsu(RA)

th(RA)

1
1

DSPD

ten(R)

-1

th(R)

~
, ,

I4--t,

--.I

~td(DV)

10lIl

tdis(R)

Figure 26. TCM4301 to DSP Interface (Read Cycle)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-111

8-112

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

•
•
•
•
o
e
o
•

Applications Include GSM 900 and DCS
1800 Cellular Telephones
80-Pin TQFP Package
Single 3-V Supply Voltage
Internal Voltage Reference
Extended RF Control Voltages
Advanced Power Management
GSM-DAI Interface
MCU and DSP Serial Interface

•
•
•
•

Five Ports Auxiliary AID
Meets JTAG Testability Standard (IEEE
Std 1131.1-1990)
Baseband Codec-GMSK Modulator with
On-Chip Burst Buffer
Voice Codec Features: Microphone
Amplifier and Bias Source,
Programmable Gain Amplifiers, Volume
Control and Side-Tone Control

description
The TCM4400 Global System for Mobile Communication (GSM) baseband RF interface circuit is designed for
GSM 900 and DCS 1800 European digital cellular telecommunication systems. It includes a complete set of
functions to perform the interface and processing of voice signals, generate baseband in-phase (I) and
quadrature (0) signals, and control the signals between a digital signal processor (DSP) and associated RF
circuits.
The TCM4400 includes a second serial interface intended for use with a microcontroller. Through this interface,
a microcontroller can access all the internal registers that can be accessed through the DSP digital serial
interface. This option is intended for applications in which part of the L 1 software is implemented in the
microcontroller.
A 4-pin parallel port is dedicated to the full control of the digital audio interface (DAI) to the GSM system simulator
that consists of system simulator reset (SSRST) control, clock generation, and rate adaptation with the DSP.
The voice processing portion of the device includes microphone and earphone amplifiers, analog-to-digital
(AID) and digital-to-analog (DJA) converters,speech digital filtering, and a serial port.
The baseband processing portion of the device includes a 2-channel uplink path, a 2-channel downlink path,
a serial port, and a parallel port. The uplink path performs Gaussian minimum shift keying (GMSK) modulation,
DJA conversion, and has smoothing filters to provide the external RF circuit with I and Q baseband signals. The
downlink path performs antialiasing, AID conversion, and channel separation filtering of the baseband I and Q
signals. The serial port allows baseband data exchange with the DSP, and the parallel port controls precise
timing signals.
Auxiliary RF functions such as automatic frequency control (AFC), automatic gain control (AGC), power control,
and analog monitoring are also implemented in the TCM4400. Internal functional blocks of the device can be
separately and automatically powered down with GSM RF windows.

PRODUCT PREVIEW Information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-113

==
w

:>
w
a:
c.
t-

;:)

oa:
c.

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

aO-Pln TQFP PACKAGE
(TOP VIEW)

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

"tJ
:D

o
C

c:
o
-I

"tJ
:D

BFSX
BClKX
BOX
BOR
BClKR
BFSR

2
3
4
5
6

•

AVDD1
VREF
IBIAS
VGAP

7
8
9
10

AVSS1
RESET
VFS
VOX
VOR
VClK
SSRST
SSOX
SSOR
SSClK

11
12
13
14
15
16
17
18
19
20

BULIP
BULIN
BUlQP
BUlQN

56
55
54
53
52
51
50

AVDD2
AVSS 2
BOLIN
BOLIP
BOlQN
BOlQP
VMIO

49
47
46
45
44

OVSS 3
AVSS3
APC
AFC
AGC
AOCMIO

43
42
41

AVDD3/5
OVDD3
AVDD3

m
m

8-114

60
59
58
57

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

functional block diagram
~

II)

:s a: c C

CO)

III)
~
0 w w w
l- I- l- I- l- I- l- I-

..J

c:(

..J

w
m

~1~l~I~I~I$I~I~1 ~I ~I

Main Clock
Generator

c:(

I-

:::D.

II)

:::)

..J

r!1

w
a:

GSMWindows
Timing
Interface

JTAG
Interface

..J

AuxiliaryDAC
AnalogAGC

Power
Management

APC(D/A)
RFTX Ramp

I-----------~-------+
USEl 1!..
UClK 1!..
UDX 1!..
UDR IL
BFSX ....!...

BDX ....!..
2
BClKX ~
BFSR
BDR
BClKR

MCU
Serial
Interface

DSP
Serial
Interface

-L

VFS .!L
VDX 1.L
VDR .!L

Voiceband
Serial
Interface

SSDR

..1L

I
I
I
I

..,

DAI
Interface

....
I
I
I

53
BULIP
54
~ BULIN
BULaN
r-- BUlap

r-s:!

Bu.
Controller

r-~

Baseband Downlink va Path
Automatic Offset Compensation
1D-Bit ADC and Antialiasing Filter

I
I
I

~ APC

r--

Baseband Uplink GMSK Modulator
Internal Burst RAM
Automatic Offset Compensation
a-Bit DAC and Antialiasing Filter

I I
1

1
1
1
1
L ____

Voice Uplink 13 Bit ADC
Two Analog Inputs
Programmable Gain
Bandpass Digital Filter

AGC

t---,- - - - - - - - - - - - 1

1
SSClK ~
SSRST .!Z....
SSDX 11L

.-+

I
I

VClK .!!..

r--

~
~

AGC,AFC
APC Output
Swing Control

BDLIP
BDLIN
BDLaN
BDLap

~I ~I ~I

l:il

---t
1
1

I REF-VREF
VMID
Bias

~I ~I ~I
D.

a:
c:(

w w

enl

AFC(D/A)
VTCXO Control

46
r--

a..
AFC

I-

~I ~I

"'r

~.-

:::l
C

Auxiliary
10Bits
5 Inputs ADC

ADIN1
~ ADIN2
~
~ ADIN3
~ ADIN4
40
ADIN5
r--

col

><
:::)
c:(

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

:>
W
~

I
Voice Downlink 13 Bit DAC
Auxiliary Earphone Output
Programmable Volume
Smoothing Filter
Bandpass Digital Filter

r-- AVDD3/5

8-115

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

Terminal Functions
TERMINAL
NAME

"o:c

NO.

110

ADCMID

I/O

ADIN1

DESCRIPTION
Reference voltage of auxiliary ND converters; decoupling only (analog)
Auxiliary 1O-bit ADC input 1 (analog)

ADIN2

Auxiliary 1O-bit ADC input 2 (analog)

ADIN5

Auxiliary 1O-bit ADC input 3 (analog)

ADIN4

Auxiliary 1O-bit ADC input 4 (analog)

ADIN3

Auxiliary 1O-bit ADC input 5 (analog)

AFC

Automatic frequency control DAC output (analog)

AGC

Automatic gain control DAC output (analog)

APC

AUXI

Auxiliary (high-level) speech signal input (analog)

AUXO

Auxiliary downlink (voice codec) amplifier output -

AVDD1

Analog positive power supply (bandgap, internal common-mode generator, bias current generator).

AVDD2

Analog positive power supply (baseband CODEC)

AVDD3

Analog positive power supply (auxiliary RF functions)

AVDD3/5

Analog positive power supply (auxiliary RF functions) -

AVDD4

Analog positive power supply (voice codec)

Automatic power control DAC output (analog)

single-ended (analog)

can be in the 3-V to 5-V range

AVSS1

Analog negative power supply (bandgap, internal common-mode generator, bias current generator).

AVSS2

Analog negative power supply (baseband CODEC)

AVSS3

Analog negative power supply (auxiliary RF functions)

-I

AVSS4

BCAL

:c
m

BCLKR

1/0

DSP serial interface clock input - this clock signal is provided by the DSP or the TCM4400 (digital).

BCLKX

DSP serial interface clock output. The frequency is the same as MCLK (digital).

BDR

BDX

DSP serial interface serial data output (digital)

BENA

Burst transmit or receive enable (depends on status of BULON and BDLON) (digital)

BDLON

Power on of baseband downlink (timing interface)

DSP serial interface receive frame synchronization input (digital)

BFSX

DSP serial interface transmit frame synchronization output (digital)

BDLIN

In-phase baseband input (-) -

downlink path (analog)

BDLIP

In-phase baseband input (+) -

downlink path (analog)

BDLQN

Quadrature baseband input (-) -

BDLQP

Quadrature baseband input (+) - downlink path (analog)

BULIN

In-phase baseband output (-) -

uplink path (analog)

BULIP

In-phase baseband output (+) -

uplink path (analog)

BULON

Serial clock input (serial interface) (digital)

BULQN

Quadrature baseband output (-) -

uplink path (analog)

BULQP

Quadrature baseband output (+) -

uplink path (analog)

DVDD1

Digital positive power supply (baseband and timing serial interfaces)

DVDD2

Digital positive power supply (baseband CODEC)

DVDD3

Digital positive power supply (auxiliary RF functions)

DVDD4

Digital positive power supply (voiceband codec and serial interface)

DVSS1

Digital negative power supply (baseband and timing serial interfaces)

BFSR

Analog negative power supply (voice codec)
Baseband uplink or downlink offset calibration enable (timing interface)

DSP serial interface serial data input (digital)

downlink path (analog)

~TEXAS

INSTRUMENTS
8-116

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

Terminal Functions
TERMINAL
NAME

NO.

DESCRIPTION

I/O

Digital negative power supply (baseband CODEC)

DVSS2

DVSS3

Digital negative power supply (auxiliary RF functions)

DVSS4

Digital negative power supply (voiceband codec and serial interface)

EARN

Earphone amplifier output H (analog)

EARP

Earphone amplifier output (+) (analog)

GNDA1

Analog signal ground for the microphone amplifier and auxiliary input

GNDA2

Signal return (ground) for AUXO output

IBIAS

1/0

MCLK

Internal bias reference current adjust -

adjust with external resistor (analog)

Master system clock input (13 MHz) (digital)

MICBIAS

Microphone bias supply output -

MICIP

Microphone amplifier input (+) (analog)

also used to decouple bias supply with external capacitor (analog)

MICIN

Microphone amplifier input (-) (analog)

PWRDN

Powerdown mode control input (digital)

RESET

Device global hardware reset -

SSCLK

DAI interface external 104 kHz clock output (digital)

SSDR

DAI interface data transfer input -

SSDX

DAI interface data transfer output -

pull to ground to reset (digital)

->w
W

connect to GSM-SS TDAI (digital)
connect to GSM-SS RDAI (digital)

SSRST

DAI interface reset input (digital)

TCK

Scan test clock (digital)

TDI

Scan path input (for testing purposes) (digital)

c..

Scan path output (for testing purposes) (digital)

I-

TDO

TEST1

1/0

Test 1/0 (digital)

TEST2

1/0

Test 1/0 (digital)

TEST3

Test output (digital)

TMS

JTAG test mode select (digital)

TRST

JTAG serial interface reset -

UCLK

MCU interface clock input (digital)

::J
C

c..

pull to ground to reset (digital)

UDR

MCU interface data transfer input (digital)

UDX

MCU interface data transfer output (digital)

USEL

MCU serial interface select (digital)

VCLK

Voiceband serial interface clock output (digital)

VDR

Voiceband serial interface receive data input (digital)

VDX

Voiceband serial interface transmit data output (digital)

VFS

Voiceband serial interface transmit frame synchronization output (digital)

VGAP

1/0

Bandgap reference voltage -

VMID

Midrail voltage output (analog)

VREF

1/0

Reference voltage -

decouple with external capacitor (analog)

serves as reference common-mode voltage for RF device when directly dc coupled

decouple with external capacitor (analog)

"TEXAS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-117

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t
Supply voltage range, AVDD, DVDD (see Note 1) ......................................... -0.3 to 6 V
Maximum voltage on any input, VI max ..................................... VDD +0.3 V / Vss -0.3 V
Storage temperature, Tstg ......................................................... -65 D C to 150D C
Maximum junction temperature, TJ ........................................................ + 150D C
t

Stresses beyond those listed under "absolute maximurT\ ratings" may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maxi mum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage measurements with respect to GNO.

recommended operating conditions
MIN

Vdc

Supply extended voltage range for RF blocks (AVOO3/5)

2.7

5.25

Vdc

-25

+85

Oigitall/O voltage with respect to OVSS

-0.3

OVOO+0.3

Vdc

Analog 1/0 voltage with respect to AVSS

-0.3

AVOO + 0.3

Oifference between any AVOO or OVOO

0.3

Typical high-level output current with digital pad higher than VOO-0.1 V (CMOS)

-I

Maximum low level input voltage, VIL

-C

High impedance state output current (pullup)

c:
o
:D

UNIT

3.3

Typical low-level output current with digital pad lower than 0.1 V (CMOS)

MAX

2.7

Operating temperature range

-c

NOM

Supply voltage range (AVOO, OVOO)

°C

500

/J A

Typical low-level output current with digital pad lower than 004 V (TIL)

-700

/J A

Typical high-level output current with digital pad higher than VOO-Oo4 V (TIL)

-3

Minimum high-level input voltage, VIH

0.8

V
0.3
15

Load resistance

k!1

Load capacitance

Maximum external load capacitance
Current capability at MICBIAS nominal audio level of 2.5 V

voltage references
REFERENCE
VGAP

VOLTAGE

DEFINITION

1.22V

Band gap used for all other references

VREF

1.75 V

Voltage reference of GMSK internal ADC and DAC

VMID

AVDD2 /2

MICBIAS

2 V I 2.5 V

ACDMID

1.75 V

Common-mode reference for uplink/downlink GMSK
Microphone-driving voltage
Voltage reference of the auxiliary ADCs

•
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INSTRUMENTS
8-118

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

/J A
pF

Oto
0.5

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
baseband uplink path
PARAMETER

TEST CONDITIONS

MIN

TYP

I and 0 D/A converters resolution

MAX

Dynamic range on each output

Centered on internal reference

Differential output dynamic range

BULOP-BULON or
BULIP-BULIN

Output load resistance, differential

Output load capacitance, differential

Output common-mode voltage

Programmable by bit SELVMID

UNIT
bit

8
VVREF

Vpp

2 x VVREF

Vpp
kn
pF

VDD/2
or 1.35 ±0.1

dc accuracy - uplink path
MIN

PARAMETER
Offset error before calibration
Offset error after calibration
Offset correction range

TYP

MAX

UNIT

±50

±5

±100

dynamic parameters - uplink path
PARAMETER

Maximum output modulation spectrum

Absolute gain relative to VREF

MIN

TYP

MAX

UNIT

±400 kHz

-65

±600 kHz

-70

±800 kHz

-70

±1

VREF

smoothing filters characteristics - uplink path
PARAMETER

MIN

o Hz to 100 kHz

Group delay

TYP

MIN

TYP

Gain matching between channels

10Hz to 96 kHz

±0.15

Phase matching between channels

10Hz to 96 kHz

0.5 0

MAX

UNIT
dB

0
0.25
I and 0 gain unbalance

Programmable

dB
0.50
0.75

"'TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

a
a::

1.5

TEST CONDITIONS

:J
C

MAX

I and Q channels gain and phase matching - uplink path
PARAMETER

w
>
w
a::
c..

8-119

c..

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

baseband uplink path global characteristics
PARAMETER

TEST CONDITIONS

MIN

GMSK phase error

TYP

MAX

UNIT

6°

Ipeak

1.5°

I rms

Power supply rejection
I active

Supply current for uplink path

I power-down

Maximum value

JlA

timing requirements of baseband uplink path
programmable delays - uplink path (see Figure 1)
MAX

UNITt

tsu1

Setup time, BENAi before APci

Bits DELU of register BUlRUDEl

1/4-bit

th1

Hold time, ramp-down from BENA low

Bits DELD of register BUlRUDEl

MIN

tt1

"'C

=0
Bit APCSPD = 1
Bit APCSPD

Transition time, APC

1/4-bit
1/16-bit
1/8-bit

Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted.

fixed delays - uplink path (see Figure 1)
MIN

o
c
c

Setup time, BUlONi to BCAli

tw1

Pulse duration, BCAl high

tsu3

Setup time, BCAl low before BENAi

-I

tw2

Pulse duration, BENA high

"'C

th2

Hold time, modulation low after BENA low

th3

Hold time, BUlONJ, after APC low

(')

MAX

N effective duration of burst
Controlled by BENA

Jls
Jls

N-32

1/4-bit

bit

I (Digital delay of modulator)

UNITt
Jls

132

Input-to-output modulator delay

NOM

tsu2

NOM

bit
1.5

bit

Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted.

timing requirements of baseband downlink path (see Figure 2)
MIN
tsu4

Setup time, BDlONi to BCAli

tW3

Pulse duraton, BCAl

tsu5

Setup time BCAl low before BENA i

tw4

NOM

MAX

Jls
60

N effective duration of burst
controlled by BENA

Pulse duration, BENA high

UNITt

Jls
Jls
1/4-bit

tsu6

Setup time, BENAi before DATAOUT VALID

Jls

th4

Hold time, DATAOUT VALID after BENAJ,

3.7

Jls

th5

Hold time, BOLON low after BENA low

t Bit is relative to GSM bit = 1/270 kHz. Units can be a fractional part of the GSM bit as noted.

~TEXAS

INSTRUMENTS
8-120

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Jls

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

baseband downlink path
PARAMETER

TEST CONDITIONS

TYP

MIN

MAX

UNIT

Dynamic range on each input

Centered on Internal Reference

VVREF

Vpp

Differential input dynamic range

BDLQP-BDLQN or DLiP-DLIN

2VVREF

Vpp

200

Input resistance at BDLQP-BDLQN or BDLIP-BDLIN
Input capacitance at BDLQP-BDLQN or BDLIP-BDLIN

pF
-10%

Common-mode input voltage

VDD/2

MAX

UNIT

±21060

Maximum digital code value

Range of digital output data

+10%

dc accuracy - downlink path
MIN

PARAMETER

TYP

Offset error before calibration

LSB

Offset error after calibration

±1

LSB

full scale

Offset correction range

dynamic parameters - downlink path
PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Dynamic range

Signal to noise plus distortion, whole downlink path

Absolute gain relative to VVREF

±1

channel characteristics
frequency response - downlink path
TEST CONDITIONS

PARAMETER

Frequency response of the total chain with
values referenced to 67.708 kHz

MIN

TYP

MAX

UNIT

o Hz

-0.2

67.5 kHz

-0.2

0.2

-4

0.3

96 kHz

0.2

135 kHz

-40

200 kHz

-40

400 kHz

-40

group delay - downlink path
PARAMETER

TEST CONDITIONS

MIN

o Hz to 100 kHz

Group delay

TYP

MAX

I and Q channels matching - downlink path
PARAMETER

Gain matching between channels
Delay matching between channels

TEST CONDITIONS

MIN

TYP

MAX

UNIT

. 10HZ to 96 kHz

±0.5

10Hz to 96 kHz

baseband downlink path global characteristics
PARAMETER

TEST CONDITIONS

MIN

TYP

Supply current for downlink path

MAX

'UNIT

Power supply rejection, 0 Hz -100 kHz band

I active
I power-down

IlA

•
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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-121

w
>
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a.

::)

o
a:

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

automatic power control

power DIA converter
PARAMETER

MIN

TEST CONDITIONS

Integral nonlinearity
Best fitting of linearity with the shaper
at full scale maximum

Differential nonlinearity
Settling time

TYP

MAX

UNIT

+/-2

LSB

+/-1

LSB

Jls

shaper DAC
PARAMETER

MIN

TEST CONDITIONS

Integral nonlinearity

Best fitting of linearity

=3 V)
Minimum voltage swing (AVDDsl5 =5 V)

Jls

APCSWG_config bit =1

Load capacitance

=3 V)
Power consumption active (AVODsl5 =5 V)

2.1

7.1

0.01

JlW

Maximum power consumption, power-down, 3-V and 5-V

auxiliary ADC

mOnltormg

LSB

APCSWG_config bit =0

Power consumption active (AVDDsl5

UNIT

Load resistance

"tJ

MAX

+/-1

Settling time
Minimum voltage swing (AVDDsl5

TYP

MAX

UNIT

Integral nonlinearity (best fitting)

Input signal range <0.95 VVREF

±4

LSB

-t

Differential nonlinearity

Input signal range < 0.95 VVREF

±2

LSB

"tJ

Integral nonlinearity (best fitting)

Input signal range> 0.95 VVREF

Differential nonlinearity

Input signal range >0.95 VVREF

PARAMETER

TEST CONDITIONS

Full-scale accuracy
Conversion time
Input range
Input leakage current
Input capacitance
Supply current for AOC

I active
I power-down

~TEXAS

INSTRUMENTS
8-122

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MIN

TYP

LSB
LSB
5

LSB

Jls

Oto VVREF

JlA

500

JlA

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

AGC characteristics
PARAMETER

TEST CONDITIONS

Integral nonlinearity

MIN

Best fitting line

Differential nonlinearity
Settling time

From AUXAGC load

Output swing (AVDD3/5

=3 V ± 10%)

MAX

LSB

±2

LSB

100

Ils
V

0.2

= 5 V ± 5%)

Offset voltage with code 000 (5 V ± 5%)

UNIT

±2

Offset voltage with code 000 (3 V ± 10%)
Output swing (AVDD3/5

TYP

V
0.4

AFC characteristics
PARAMETER

TEST CONDITIONS

MIN

TYP
2

Sampling frequency, fs

Minimum resolution

Depending on quartz characteristics

Integral nonlinearity from 0 to 80% output range

Best fitting line

Differential nonlinearity from 0 to 80% output range

MHz
MHz

0.5

MHz

0.25

MHz

bit

±D.5

LSB

±0.5

LSB
Ils

TBD

25 or 50

AFCSWG_config bit = 0

AFCSWG_config bit = 1

DC power-supply sensitivity

Over power supply range

Internal output resistance

Programmable value

Minimum voltage swing (AVDD = 3 V)
Minimum voltage swing (AVDD = 5 V)

Power consumption when device is active (typical)

UNIT

Settling time

MAX

fs = 2 MHz (VDD = 3 V)

0.7

fs = 1 MHz

0.6

fs = 0.5 MHz
fs = 0.25 MHz

0.54

mW
mW

:>
w
a:
c..
t-

::J
C

c..

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-123

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

voice uplink path
TEST CONDITIONS

PARAMETER

MIN

MAX

UNIT

Inputs 3 dBmO (maximum digital
sample amplitude)

32.5

mVrms

Nominal reference level (MICP - MICN)

from maximum value

-10

dBmO

100

Input resistance (MICP - MICN)
DC level at MICBIAS

+/- 10% precision value

2or2.5

Maximum input range at AUXI
Nominal reference level at AUXI

From maximum value

Minimum input resistance at AUXI

100

PGA gain range

With 1-dB steps

"'C

o
C

c:
o

mVrms

-10

dBmO

300

kn
16.6

-37.4

150 Hz

-25.9

200 Hz

-16.5

300Hz

-1.46

2000 Hz

-0.58

3000 Hz

-0.77

3400 Hz

-1

3600 Hz

-12.4

3800 Hz

-23.3

4000 Hz

-35

>-52

Reference point is 1000 Hz

1000 Hz
Frequency response

320

-7.4

Value obtained at nominal level

100 Hz

-f

TYP

Maximum input range (MICP - MICN)

>4600 Hz

psophometric SNR vs signal level uplink path

"'C

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

3dBmO

OdBmO

-5 dBmO

-10 dBmO

-20dBmO

-30dBmO

-40dBmO

-45 dBmO

Signal level

Over the range +3 dBmO to - 45
dBmO at 1 kHz with reference -10
dBmO

Gain tracking error

Maximum idle channel noise

300 HZ-3 kHz

Maximum group delay distortion

300 Hz -3 kHz

Crosstalk with the downlink path

-72

dBmO
ms

-66

Downlink path loaded with 30 n

global characteristicsfor voice uplink path
TEST CONDITIONS

PARAMETER

MIN

TYP

Supply current for voice uplink

Iactive
I power-down

•
TEXAS
INSTRUMENTS
8-124

MAX

UNIT
dB

Power supply rejection. 0 Hz -100 kHz band

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

IlA

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

voice downlink path
PARAMETER

Maximum output swing
(EARP - EARN)

TEST CONDITIONS

MIN

with 5% distortion and with 150 il
with 5% distortion and with 30 il

Minimum output resistive load

Depending on the output swing

150

Maximum output capacitive load
Earpiece mute switch attenuation
Maximum volume control

Typical audio level

Programmable volume control

Mute
Maximum output swing (AUXO), 5% distortion, maximum

Load = 1 kil

Minimum output resistive load

ac coupled

Total signal to noise ratio (AUXO)
Idle noise (AUXO)

300 Hz - 3 kHz

100

-6

-12

-18

-24

dB
dB
Vpeak

kil

100

-77

<-40

100 Hz

-5.8

150 Hz

-3.6

200 Hz

-2.5

300 Hz

-1.4

2000 Hz

-0.6

3000 Hz

-0.15

3400 Hz

-0.35

3600 Hz

-9.0

1000 Hz

Reference point

3800 Hz

-21.0

4000 Hz

-32.0

>4600 Hz

-60.0

VIN = 0.1 Vrms
Maximum distortion at 1 kHz with 30 il

Programmable gain amplifier

Gain tracking error

VIN = 1 Vrms

VIN = 1.5 Vrms

By 1-dB steps

-6

Over the range +3 dBmO to -30 dBmO
at 1 kHz with reference -10 dBmO

±0.25

Over the range -31 dBmO to -45 dBmO
at 1 kHz with reference -10 dBmO

±0.50

Idle channel noise, 0 Hz -30 KHz
Power supply rejection, 0 Hz -100 kHz

Side-tone gaip range

Vpp
Vpp

Mute switch attenuation (AUXO)

Supply current for voice
downlink

UNIT

1.5

1.96

Audio delay (AUXO)

Frequency response

MAX

3.92

<-40

Maximum output capacitive load
Maximum at 1 kHz over
300 Hz - 3 kHz

TYP

-71

dBm

7.4

In the band

active
power-down

2
With 3 dB steps

Side-tone mute

-17

/lA
1

-60

dB
dB

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-125

s:w

II:

C.
I-

:::l
C

II:

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

psophometric SNR vs signal level downlink path
PARAMETER

Signal level

TEST CONDITIONS

MIN

TYP

MAX

UNIT

-45 dBmO

-40dBmO

-30dBmO

-20dBmO

-10 dBmO

-3 dBmO

OdBmO

supply current
PARAMETER
Deep power down

13 MHz clock applied;
PWRDN active;
Band-gap voltage reference off

Power down with AFC

AFC programmed with internal 50 kn and 1 MHz clock

MIN

o
c

o-I

MAX

UNIT
IlA

AFC + GMSK - Rx

"'C

NOM

rnA

Audio + GMSK - Tx + APC + AFC

transmit burst

rnA

Audio + GMSK - Rx + AFC

receive burst

rnA

voice timing requirements (see Figure 5)
PARAMETER
VCLK

VCLK signal frequency

VCLK

VCLK duty cycle (±10%)

MIN

NOM

MAX

UNIT
kHz

520
50%

th6

Hold time, VFS.1. after VCLK low

100

"'C

th7

Hold time, VDR.1. after VCLK low

100

th8

Hold time, VDX high after VCLK high

100

tsu7

Setup time, VFsi before VCLK low

100

tsu8

Setup time, VDX.1. before VCLK low

100

tsu9

Setup time, VDR high before VCLK low

100

MCU serial interface timing requirements (see Figure 3)
PARAMETER

MIN

NOM

MAX

UNIT

tsu10

Setup time, UCLK.1. before USEU

tv1

Hold time, UDX valid after USEU

tv2

Hold time, UDX valid after UCLKi

th9

Sequential transfer delay between 16-bit word acquisition tw pulsduration, USEL high

th10

Hold time, UCLKi after USEU

th11

Hold time, UCLKi after USELi

tsu11

Setup time, data valid before UCLK.1.

th12

Hold time, data valid after UCLK.1.

tc max

Cycle time, ULCK

~TEXAS

INSTRUMENTS
8-126

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ns
3000

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

master clock timing requirements
MIN

PARAMETER

NOM

MAX

Master clock signal frequency

MHz

40%

Master clock duty cycle

60%

1.3

Maximum peak-to-peak amplitude
Minimum peak-to-peak amplitude

0.5

Common-mode input voltage

UNIT

V
V

VDD-0.5

VSS +0.5

PARAMETER MEASUREMENT INFORMATION

uplink timing considerations
Figure 1 shows the timing diagram for the uplink operation.
Timing for power-up, offset calibration, data transmission, and power ramp-up are driven by control bits applied
to BUlaN (base uplink on), BCAl (calibration) and BENA (enable). The burst content including guard bits, tail
bits, and data bits is sent by the DSP by way of the DSP interface and then stored by the TCM4400 in a burst
buffer. Transmission start is indicated by the control bit ENA when the BULON is active. The transmission,
sequencing, and power ramp-up are then controlled by an on-chip burst sequencer with a one-quarter-bit timing
accuracy. For a detailed description of the baseband in length path, see the functional description of the
baseband uplink path in the Principles of Operation section.
BULON

--I
~

SCAl

j+- t su2

l1"""---f\
----~ ~twl ~ :~--------------------------------~---------I

~th2

tSU3~

SENA

MODULATION

tw2

..I.!_y~

APC _ _ _ _ _ _ _ _ _ _ _ _

:'\

th1~

- - - - - - - - - - - - - - - - - - -_ _ _1

I I
tsul~

ttl

~ ~~------

~"-----+----------

--.!I

~
I

~th3

Figure 1. Uplink Timing Diagram

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

:>
w
a:
c..

I-

:::l

a:
c..

----------------------J!'r:i4-~--- ---~N

3:
w

8-127

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

downlink timing considerations
Figure 2 shows the timing diagram for downlink operation.
Timing control of the baseband downlink path is controlled by bits OlON (downlink on), BCAl (calibration) and
BENA (enable) when BOLON is active (see the topic, timing control and interface). BOLON controls the
power up of the baseband downlink path, BCAl controls the start and duration of the autocalibration sequence,
and BENA controls the beginning and the duration of data transmission to the OSP, using the OSP serial
interface.
The power-down sequence is controlled with two bits, the first bit (BBOlW of PWONWIN register) determines
whether the baseband downlink path can be powered down with external GSM receive window activation
(BOLON); the second bit (BBOlPO of PWONWIN register) controls the activation of the baseband downlink
path. See the topic, power-down functional description, for more details about power-down control.

BOLON

---I'f
~

"'C

BCAL ____

~J;f-1-------rt------------------------------~i----------~tw3~

BENA

-I
"tJ

\]1"-------

tsu4

~ th5

I+--+!-- tsu5

c:
JJ

14-

}1I

-------------------~I

Nil

~~----------tw4----------...1
I
I

~------------

:~JI"------~:{>-----I

OATAOUT

<
-

tsu6~

Figure 2. Downlink Timing Sequence

~TEXAS

INSTRUMENTS
8-128

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~th4

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

microcontroller serial interface timing considerations
Figure 3 shows the timing diagram for the microcontroller serial interface.
The microcontroller serial interface is designed to be compliant with a-bit standard synchronous serial ports.
The microcontroller operates on 16-bit words; this interface consists of four pins.
UCLK:

A clock provided by the microcontroller to the GSM baseband and voice AID and DfA conversion.

UDR:

An input terminal of the GSM baseband and voice AID and DfA components intended for reception
of data.

UDX:

An output terminal of the GSM baseband and voice AID and DfA'components intended for
transmission of data.

USEL:

An input terminal of the GSM baseband and voice AID and DfA components intended for
activation of the serial interface.

i+-----+I-- th 10

USEL

----~I
--~i--------~\~
~I!.-'
"

t su12 ~

I,I'

UCLK

..-- tc(max) ~

~~"-+:_.......

i -.I i+~4~~
,

th10

UDR

tv1--.!

UDX

th11

----+1,

->w

1 i mi

~
~

s:w

tv2

I
~
th9 -+I

::J

~'
~~

_Hi_-Z_ _--(I ....._ _ _ _ _ _

a:
c.
Io

)

a:
c.

th12
Hi-Z

Figure 3. Microcontrolle,r Serial Interface Timing Waveforms

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-129

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

DSP Serial port timing considerations
Figure 4 shows the timing diagram for OSP serial port operation.
Six pins are used for the serial port interface, see Figure 14. The terminal BCLKR is an 1/0 port for the serial
clock used to control the reception of the data BOR. At reset BCLKR is configured as an output and the clock
frequency is set to MCLKl3 (4.333 MHz with MCLK = 13 MHz), the clock signal is running permanently. The port
BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is provided
by the OSP and can run in burst mode to reduce power consumption. The receive frame synchronization (BFSR)
is used to identify the beginning of a data packet transfer on port BOR.
The transmitted serial data (BOX) is the serial data input; the transmit frame synchronization (BFSX) is used
to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice
NO and O/A converters with a frequency of MCLK. The downlink data bus (BFSX, BCLKX, BOX) can be driven
to VSS or placed in high-impedance when no data is to be transferred to the OSP. The bit BCLKOIR of the
register BCTLREG controls the direction of the BCLKR clock.
As with the voice serial interface, an extra clock cycle must be generated since the last 16-bit word received
on the OSP serial interface is latched on the next two falling BCLKR edge, following the least significant bit
(LSB). As for the voice serial interface, one extra clock period is generated on the BCLKX before the first
synchronization BFSX of downlink data sequence.

"'tJ

oC
C

-t

BCLKX
BFSX

-+--~

',';

m
S

BOX

--+---+--+<

(a) Burst-Mode Serial Port Transmit Operation

BCLKR
BFSR

--!---I

BOR-~--+--H

(b) Burst-Mode Serial Port Receive Operation

Figure 4. DSP Serial Port Timings

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PARAMETER MEASUREMENT INFORMATION

voiceband serial interface timing considerations
Figure 5 shows the timing diagram for both transmit and receive voiceband serial interface operation.
The signal VCLK is the output serial clock used to control the transmission or reception of the data (see
Figure 9). The transmitted serial data (VDX) is the serial data output; the frame synchronization (VFS) is used
to initiate the transfer of transmit and receive data. The received data (VDR) is the serial data input.
Each serial port includes four registers that include the data transmit register (DXR), the data receive register
(DRR), the transmit shift register (XSR) and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface; one extra cycle is
generated before VFS and two extra cycles are generated after the LSB.
VCLK

tsu7

VFS

I
I

i.--J-.

tsu8 --j4---.I
th6
I4----*- th8

~r--I\

--------~~

I
I

\~.--~I----_I---------------------------------------

VDX--------------~

MSB

LSB

XLOAD __________-J~~___________________________________________________ _

DXR
Loaded

XSR
Loaded

a. Audio-Serial-Port Transmit Operation

o
a::

tsu9--je1~

r--\.

------_I

I ...-----.,I
I
I
I

th7

____~I--~I----------------------------------------

VDR--------------~

MSB
RLOAD

a::

I-

VCLK

VFS

->w
w

LSB

-------

DDR
Loaded

b. Audio-Serial-Port Receive Operation

Figure 5. Voiceband Serial Interface Timing Waveforms

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INSTRUMENTS
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8-131

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLE OF OPERATION

baseband uplink path
Instead of the traditional transmit and receive terms, which can be confusing when describing a cellular
telephone 2-way communication, the terms uplink meaning from a user device to a remote station and downlink
meaning from a remote station, whether earthbound or satellite, are used to indicate the signal-flow direction.
The modulator circuit in the baseband uplink path performs the Gaussian minimum shift keying (GMSK) in
accordance with the GSM specification 5.04. The data to be modulated flows from the DSP through the serial
interface, it is differentially encoded, and it is applied to the input of the GMSK modulator. The GMSK modulator
is implemented with digital logic and a sin/cos look-up table in ROM, and it generates the I and Q components
(words) with an interpolation ratio of 16.
These digital I and Q words are sampled at a 4.33 MHz rate and applied to the inputs of a pair of high-speed
a-bit DACs. The analog outputs are then processed by second-order Bessel filters to reduce image frequencies
due to sampling and to obtain a spectrum consistent with GSM specification 05.05 (see Figure 6).
MAGNITUDE

vs
FREQUENCY

-c

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-20

-I
-C
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-40

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m

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-60

a:
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oa:
c..

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION

baseband downlink path

The baseband downlink path includes two identical circuits f6f processing the baseband I and components
generated by the RF circuits. The first stage of the downlink path is a continuous-time second-order antialiasing
filter (see Figure 8) that prevents aliasing due to sampling in the AlO converter. This filter also serves as an
adaptation stage (input impedance and common-mode level) between external world and on-chip circuitry.
TYPICAL FREQUENCY RESPONSE OF THE
ANTIALIASING FILTER
10
0

.............

-10
III

1'\

-20

I
CIl
'C

-c
:c

-30

'cCI
co

:::

o
c
c

-40

-50

-60

-C

-70
100

-I

m
<

-m

1000

10000
100000
f - Frequency - Hz

1e+06

\
1e+07

Figure 8. Antialiasing Filter
The antialiasing filter is followed by a third-order sigma-delta modulator that performs AlO conversion at a
sampling rate of 6.5 MHz. The AlO converter provides 3-bit words that are fed to a digital filter (see Figure 9)
that performs the decimation by a ratio of 24 to lower the sampling rate down to 270.8 KHz and the channel
separation by providing enough rejection of the adjacent channels to allow the demodulation performances
required by the GSM specification. Figure 10 shows the frequency response curve for the downlink digital filter
and Figure 11 shows the in-band response curve for the same digital filter.

The baseband downlink path includes an offset register in which the value representing the channel dc offset
is stored; this value is subtracted from the output of the digital filter before transmitting the digital samples to
the OSP using the serial interface. Upon reset, the offset register is loaded with 0 and updated with the BeAl
calibrating signal (see Figure 2).
The content of the offset register results from a calibration sequence. The input BOLIP is shorted with the input
BOLIN, and the input BOlQP is shorted with the input BOlaN. The digital outputs are evaluated and the values
are stored in the corresponding offset registers in accordance with the dc offset of the GSM baseband and voice
AlO and O/A downlink path. When the external autocalibration sequence is selected, the inputs BOLIP and
BOLIN and the inputs BOlOP and BOlaN remain connected to the external circuitry. The digital outputs are
evaluated and the values stored into the corresponding offset registers take in to account the dc offset of the
external circuitry.

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INSTRUMENTS
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TCi'v14400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
baseband downlink path (continued)
Timing control of the baseband downlink path is controlled by bits OlON (downlink on), BCAl (calibration) and
BENA (enable) when BOLON is active (see topic, timing control and interface). BOLON controls the power
up of the baseband downlink path, BCAl controls the start and duration of the autocalibration sequence, and
BENA controls the beginning and the duration of data transmission to the OSP by using the OSP serial interface.
The power-down sequence is controlled with two bits, the first bit (BBOlW of PWONWIN register) determines
whether the baseband downlink path can be powered down with external GSM receive window activation
(BOLON); the second bit, BBOlPO of register PWONWIN, controls the activation of the baseband downlink
path. See the topic, power-down functional description, for more details about power-down control.

BOLIP
BOLIN

To Baseband
Serial Interface

BOLQP
BOLQN

Figure 9. Functional Structure of the Baseband Downlink Path

c
a:
a.

10
0

--..........

-10
-20
!Xl
"C

"'"~

-30

CIl

'cC'I
III
::

-40

-50
-60

'"\1

-70

-80

3:
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w
a:
a.
Io
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100

150

200

f - Frequency - kHz

Figure 10. Downlink Digital Filter Frequency Response

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-135

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION

0.4

0.2
m
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'ctn
III

-0.2

-0.4

"'C

'"""

f - Frequency - kHz

Figure 11. Downlink Digital Filter In-band Response

(')

---.......

auxiliary RF functions

-I

The auxiliary RF functions include the following:

"'C

•

Automatic frequency control

•

Automatic gain control

•

RF power control

•

Monitoring

::D

::::
m

Each of these functions is discussed in the following paragraphs.

automatic frequency control (A Fe)
The automatic frequency control function consists in a DAC converter optimized for high resolution dc
conversion. The AFC digital interface includes two registers that can be written using the serial interfaces. The
content of these registers control a 13-bit DAC whose purpose is to correct frequency shifts of the oscillator
maintaining the master clock frequency in a 0.1 ppm range.
To optimize the AFC function depends on the type of oscillator used and whether its sampling frequency is
programmable. This means that the lower the selected frequency the lower the resolution and power
consumption. Using a high-quality resonance oscillator filter permits the AFC circuit to operate at low frequency.
Thus, a low-cost oscillator permits operation at a higher internal frequency to ensure 13-bit resolution.
The AFC value is programmed with registers AUXAFC1 and AUXAFC2. The internal resistance and output
voltage swing selection is controlled with bit AFZ of AUXCTL2 register. Power down is controlled with two bits:
the first bit, AFCPN of AUXCTL 1 register, determines whether the AFC can be powered down from the external
PWRDN terminal; the second bit, AFCPD of AUXCTL 1 register, controls the activation of the the AFC function.
See the topic, power-down functional description for more details about power-down control.

•
TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A,RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
automatic frequency control (continued)
The auxiliary analog functions of the GSM baseband AID and OfA conversions are independently powered from
the AV003/5 external terminal. The AFC output voltage swing is programmable to provide the largest possible
voltage range. This configuration is programmed with bit AFCZ of AUXCTRL2 register.

auxiliary analog converter (automatic gain control (AGe»
The auxiliary analog converter control function includes a register which can be written to using the serial
interfaces and a 10-bit DfA converter that provides a control signal to set the gain of the RF section receive
amplifier. The 10-bit DfA converter is accessed through the internal register AUXAGC.
Power down is controlled with two bits, the first bit (AAGCW of AUXCTL2 register) determines whether the
AAGC can be powered down with the external GSM receive window activation (BOLON), the second bit
(AGCPD of AUXCTL2 register) controls the activation of AGC function. See the topic, power-down functional
description for more details about power-down control.
The auxiliary analog functions of the GSM baseband AID and DfA conversions are independently powered from
the AV003/5 external terminal. The AGC output-voltage swing is programmable to provide the largest possible
voltage range. This configuration is programmed with bit AGCSWG of AUXCTL2 register.

RF power control
The RF power control section includes a register that is written to using the serial interfaces. The content of this
register is processed using an 8-bit DfA converter and determines the gain of the RF section power amplifier.
The reference of the 8-bit DfA converter (accessed by register AUXAPC) is provided by the ramp-up-shaper
OfA converter which is as-bit DfA converter controlled by the APCRAM registers located in random access
memory (RAM). This area of RAM contains sixty-four 1a-bit words which are read from address 0 through
address 62 during the ramp-up sequence and from 63 through 1 during the ramp-down sequence at a rate of
4 MHz when bit APCSPD is at zero or at a rate of 2 MHz when bit APCSPD is at 1. The ramp-up parameters
are obtained from the five least significant bits of the RAM words. The ramp-down parameters are obtained from
the most, significant bits of the RAM words. Content of address a must be identical with the content of address 1.
Content of address 62 must be identical with content of address 63.
This RAM is loaded once and its content determines the shape of the ramp-up and ramp-down control signal,
which means these control signals can be adapted to the response of the power amplifier used in the RF section.
The shape and timing of ramp-up and ramp-down waveforms are independent.
Timing of the ramp-up and ramp-down sequences is controlled internally; however, programming of the delay
register allows adjusting the power-control start time in a 4-bit range in 1f4-bit steps. The contents of the delay
register are referenced to the BENA Signal, which determines the beginning of the burst-signal modulation. This
feature allows adjusting the timing of the control signal versus the I and Q components within 1/4-bit accuracy
as defined in the specification GSM 05.05.
When APC is in power-down mode, the analog output is driven to VSS. During inactivity periods, the APC output
is switched to Vss to give low-current consumption to the power amplifier (drain cutoff current of the RF
amplifier); during activity periods, the binary value 00000 of the pulse shaper locks the APC driver.
Power down is controlled with two bits, the first bit (APCW of AUXCTL2 register) determines whether the APC
can be powered down by activating external GSM transmit window activation (BULaN); the second bit (APCPD
of AUXCTL2 register) controls the activation of APC function. See the topic, power-down functional description,
for more details about power-down control. The auxiliary analog functions of the GSM baseband AID and OfA
conversions are independently powered from the AV003/5 terminal. The APC output-voltage swing is
programmable to provide the largest voltage range. This configuration is programmed with bit APCSWG of the
AUXCTRL2 register.

~TEXAS

INSTRUMENTS
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8-137

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w
>
w

I(.)

:::l
C

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
monitoring
The monitoring section includes a 1O-bit AID converter and one result-register which allows monitoring of five
external analog values such as the temperature and the battery voltage. The selection of the input and reading
of the control registers is done using the serial interfaces.
The selection of the input channel is done with the bits ADCCHO - ADCCH2 of the AUXCTL 1 register; the data
is read from the AUXADC register. Power down is controlled with two bits, the first bit (ADCPN of AUXCTL 1
register) determines whether the AID converter can be powered down from the external PWRDN terminal; the
second bit (ADCPD of AUXCTL 1 register) controls the activation of the AID conversion function. See the topic,
power down functional description, for more details about power-down control.
Conversion is started with a write access to the AUXCTL 1 register. During the conversion, the ADCEOC bit of
BSTATUS register stays at 1 and resets to 0 when the converted data is loaded in to the AUXADC register. This
way the power consumption of the main parts of the converter is limited to the useful part of the conversion time.

voice codec
The voice coder/decoder (codec) circuitry processes analog audio components in the uplink path and applies
this signal to the voice signal interface for eventual baseband modulation. In the downlink path, the codec
circuitry changes voice-component data received from the voice serial interface into analog audio. The following
paragraphs describe these uplink/downlink functions in more detail.

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voice uplink path
The voice uplink path includes two input stages, refer to Figure 12. The first one is a microphone amplifier,
compatible with an electret microphone containing a F.ET-buffer with open-drain output, has a gain of typically
27 dB, and provides an external voltage of 2 V to 2.5 V to bias the microphone. The auxiliary audio input can
be used as an alternative source for a higher level speech signal. This stage performs single-ended to
differential conversion and provides a gain of 6 dB. When auxiliary audio input is used, the microphone input
is disabled and powered down.

-I

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The resulting fully differential signal is fed to a programmable gain amplifier that allows adjustment of the level
of the speech signal to the dynamic range of the AID converter, which is determined by the value of the internal
voltage reference. Programmable gain can be set from -12 dB to +12 dB in 1-dB steps and is programmed with
bits VULPG to VULPG4 of VBCTL 1 register.

Analog to digital conversion is made with a third-order sigma-delta modulator whose sampling rate is 1 MHz.
Output of the AID converter is fed to a speech digital filter which performs the decimation down to 8 KHz and
band limits the signal with both a low-pass and high-pass transfer functions. The speech samples are then
transmitted to the DSP using the voice serial interface at a rate of 8 kHz.
Programmable functions of the voice uplink path, power-up, input selection and gain are controlled by the DSP
or the MCU using the serial interfaces. The uplink voice path can be powered down with the bit VULON of the
VBCTL 1 internal register.

•
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INSTRUMENTS
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TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
MICBIAS

MICIP

PGA
+16.6-7.4 dB

MICIN

Sigma_Delta
Modulator ~
fs1 = 1 MHz

AUXI

Bandpass
Filter

Filter
fs2 = 40 KHz

To Voice
Serial Interface

fs3 = 8 KHz

Auxiliary
Amplifier
6dB

Figure 12. Uplink Path Block Diagram
voice downlink path
The voice downlink path receives speech samples at an 8-kHz rate from the voice serial interface and converts
them to analog signals to drive the external speech transducer.
The digital speech coming from the voice serial interface is first fed to a speech-digital finite-duration impulse
response (FIR) filter, which has two functions (see Figure 13). The first function is to interpolate the input signal
and increase the sampling rate form 8 kHz up to 1 MHz to permit D/A conversion by an oversampling digital
modulator. The second function is to band limit the speech signal using both low-pass and high-pass transfer
functions.
The interpolated and band-limited signal is fed to a second-order sigma-delta modulator and sampled at 1 MHz
to generate a 1-bit oversampled signal that drives a 1-bit 0/A converter.
Due to the oversampling conversion, the analog signal obtained at the output of the one-bit D/A converter is
mixed with high frequency noise. This noise is filtered by a switched-capacitor third-order low-pass filter and
the remaining signal is fed to a programmable gain amplifier (PGA) to adjust the volume control. Volume control
is done in 6-dB steps from 0 dB through -24 dB; in the mute state, attenuation is higher than 40 dB. A fine
adjustment of gain is possible from -6 to +6 dB in 1-dB steps to calibrate the system, depending on the earphone
characteristics. This configuration is programmed using the VBCTL2 register.
The PGA output is fed to two output stages: The earphone amplifier that provides a full differential signal on the
terminals EARP/EARN and an auxiliary output amplifier that provides a single-ended signal on terminal AUXO.
The downlink voice path can be powered down with bit VDLON of the VBCTL2 internal register.
A side-tone path is connected between the output of the voice uplink PGA and the input of the voice downlink
PGA. This path provides seven programmable gains (+ 1 dB, -2dB, -5 dB, -8 dB, -11 dB, -14 dB, -17 dB) and
one mute position. Side-tone path gain can be selected by programming bit at register address 23.
From Voice Uplink PGA

AUXO

EARP
EARN

Smoothing
Filter
Volume Count
and PGA
0+24 dB and
-6 +6 dB

One-Bit DAC
Low-Pass Filter
+3 dB

Sigma_Delta

SINC

M~~"~~O' ~ '""~~:~'O"~
fs1 = 1 MHz

fs2

= 40 KHz

FIR
Bandpass

Fill"

fS3

From Voice
Serial Interface

= 8 KHz

Figure 13. Downlink Path Block Diagram

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-139

->w==
W

a.
Io
::)
c

oa:
a.

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
DAI interface
This digital audio interface (DAI) consists of four terminals: SSRST, SSCLK, SSDR, and SSDX. It is compatible
with the digital audio interface described in the GSM Recommendatioin 11.10. This interface is designed to offer
minimum CPU overhead during audio tests and speech transcoding tests, and to minimize the extra hardware
and the number of external terminals of the mobile system (MS). With this interface the DSP does not have to
deal with rate adaptation. In normal operation the DSP works with a 8-kHz sampling rate with a 16-bit word
format and frame synchronization, but the DAI interface works with an 8-kHz sampling rate with a 13-bit word
format without frame synchronization. The DSP (or the MCU) does not have real time constraints with SSRST
since the reset of the internal transmitters is done automatically.

power-down functional description
During periods of time it is possible to disable some functions in order to lower the TCM4400 power
consumption. For example, it is possible to disable the internal functions dedicated to radio transmission during
GSM-idle mode. It is also possible to disable the internal demodulator path during transmit window.
There are three ways to control the power consumption of the internal blocks as described in following
paragraphs.

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direct control with internal register
With this method these internal blocks are power down:

o-I
"tJ

•

DAI GSM tests: bit DAION of register VBCTL3

•

Transmit and receive voice path: bit VULON of register VBCTL 1 and bit VDLON of register VBCTL2

radio window activation control

::XJ

With this method these internal blocks are powered up with the control of two bits. The first bit enables the
window control of the block activity, the second bit enables the power down.

=:s
m

First bit:

If cleared to 0, the function is powered down with the control of the corresponding GSM window
(BDLON/BULON terminal) and with the control of the second bit. If this first bit is set to 1, the power
down is only controlled by the second bit.

Second bit:

This bit is functionally associated with the first one. When this bit is loaded with 0, the function is
in power-down mode.

During transmit windows designated with the activity of the BULaN terminal:
-

Automatic power control (APC): bits APCW and APCPD of register AUXCTL2 are paired.
Baseband uplink path: bits BBULW and BBULPD of register PWDNRG1 are paired.
External reference voltage buffers VMID: bits VMIDW and VMIDPD are paired.

During receive windows designated with activity of the BDLON terminal:
-

Analog automatic gain control (AAGC): bits AAGCW and AAGCPD of register AUXCTL2 are paired.
Baseband downlink path: bits BBDLW and BBDLPD of register PWDNRG1 are paired.

~TEXAS

INSTRUMENTS
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iCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
external terminal PWRDN control
With this method these internal blocks are powered up with the control of two bits. The first bit enables the
external terminal PWRDN control of the block activity, the second bit enables the power down.
First bit:

If cleared to 0, the function is powered down with the control of PWRDN terminal and with the
control of the second bit. If this first bit is set to 1, the power down is only controlled by the second
bit.

Second bit:

This bit is functionally associated with the first one. When this bit is loaded with 0, the function is
in power-down mode.

For the digital serial interface to the DSP: bits BBSIPN and BBSIPD of register PWDNRG2 are paired.
For the timing interface: bits TIMGPN and TIMGPD of register PWDNRG2 are paired.
For the auxiliary AID converters: bits ADCPN and ADCPD of register AUXCTL 1 are paired.
For the automatic frequency control (AFC) block: bits AFCPN and AFCPD of register AUXCTL 1 are
paired.
Forthe external reference voltage buffers MICBIAS: bits VREFPN and VREFPD of register PWDNR~·~2
are paired.
For the internal reference band-gap buffers: bit VGAPPN determines whether or not that the bandgap
power down is under control of the PWRDN bit.

a:
a.

DSP voiceband serial interface
Voiceband serial digital interface consists in a bidirectional serial port. Both receive and transmit operations are
double buffered, thus allowing a continuous communication stream. The serial port is fully static and, thus,
functions with any arbitrary low clocking frequency.

520 kHz

I-

The transfer mode available on this port is:
Clock frequency

3:
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16-bit data packet

frame synchronization

VCLK is the output serial clock used to control the transmission or reception of the data, (see Figure 5). VCLK
can run in burst mode or continuous mode, depending on the VCLKMODE bit. The transmitted serial data (VOX)
is the serial data output; the frame synchronization (VFS) is used to initiate the transfer of transmit and receive
data. The received data (VDR) is the serial data input
Each serial port includes four registers, which are the data transmit register (DXR), the data receive register
(ORR), the transmit shift register (XSR), and the receive shift register (RSR).
The voice serial interface has the same structure and timing diagram as the serial interface. One extra cycle
is generated before VFS and two extra cycles are generated after the least significant bit (see Figure 5).

"TEXAS
INSTRUMENTS
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a.

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND DIA RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION

voltage references
Voltage and current generators are integrated inside the GSM converter. Some additional components are
required for the decoupling and regulation of the internal references. In addition, the internal buffers are
automatically shut down with the corresponding functions being powered down.
There are five terminals reserved for voltage references decoupling and use: VGAP, IBIAS, VREF, MICBIAS
and VMID (refer to Table 1):
VGAP:

This terminal is connected to the internal band gap reference voltage. It must be externally
connected to a 0.1-IlF capacitor. The band gap drives the current generator and the voltage
reference. This bandgap may be down powered by PWRDN pin depending on bit VGAPPN of
register PWDNRG2.

IBIAS:

This terminal is connected to the current reference. It must be externally connected to a 100 kQ
resistor. As this block is connected to the AFC function, the power down is controlled with similar
means. The current generator is shut down with the same bits of the band gap: one bit for the
power down selection of a hardware solution (with the external PWRDN terminal).

VREF:

This terminal is connected to the internal reference voltage. It must be externally connected to a
0.1-IlF capacitor. This band gap may be down powered with the control of the bits VREFPN and
VREFPD of the register PWDNRG2. This voltage reference is internally connected to three
buffers corresponding to the blocks of speech downlink, speech uplink and GMSK downlink. The
two first blocks are down powered with the inactivity of the corresponding speech blocks. This last
block is shut down outside the radio downlink activations.

-I
""C

MICBIAS:

This buffer is destined to drive an electret-type microphone. The output voltage can be chosen
by software (bit MICBIAS of VBCTL 1 register) between the value 2 V to 2.5 V.

m
:S
m

VMID:

This buffer gives the VDD/2 or 1.35 V common-mode output voltage of the baseband uplink path.
This voltage value is selected with the SELVMID bit.

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Table 1. Voltage References

REFERENCE

VOLTAGE

DEFINITION

VGAP

1.22 V

Band gap used for all other references

VREF

1.75V

Voltage reference of GMSK internal ADC and DAC

VMID

AVDD2/2

MICBIAS

2 V 12.5 V

ACDMID

1.75 V

Common-mode reference for uplink/downlink GMSK
Microphone-driving voltage
Voltage reference of the auxiliary ADCs

MCU serial baseband digital interface
The GSM baseband and voice AID and D/A conversion provide two digital serial 16-bit interfaces intended for
use with the DSP and a microcontroller device. Through this interface a microcontroller can access all the
internal registers that can be accessed through the DSP digital serial interface.
This option is intended for application in which part of layer-1 software is implemented into the microcontroller
and needs access to some functions implemented into the GSM baseband and voice AID and D/A conversion
circuitry.

~TEXAS

INSTRUMENTS
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TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
serial interface
The microcontroller serial interface is designed to be compliant with 8-bit standard synchronous serial ports.
This interface consists of four terminals (see Figure 3 for timing diagram).
UCLK:
UDR:
UDX:
USEL:

A clock provided by the microcontroller to GSM baseband and voice AID and DfA conversion.
An input terminal of the GSM baseband and voice AID and DfA components intended for reception
of data.
An output terminal of the GSM baseband and voice AID and DfA components intended for
transmission of data.
An input terminal of GSM baseband and voice AID and DfA components intended for activation
of the serial interface.

When USEL = Voo, the serial interface is deactivated and UDX is placed in a high-impedance state. A high level
on USEL resets the internal serial interface, the 16-bit transfers must be completed with
USEL= Vss.
The external MCU initiates data transfer by driving the selection terminal and sending a clock signal. For both
the GSM baseband and voice AID and DfA components, the MCU data is shifted out of the shift registers on
one edge of the clock and latched into the shift registers on the opposite clock edge.
As a result, both controllers send and receive data simultaneously. For the MCU portion, the software
determines whether the data is meaningful or dummy data. On the GSM Baseband and voice AID and DfA
conversion portion, dummy data is that data with all zeroes.
The 16-bit word data format is identical to the BSP data format. After a read-register command, there is a
sequential transfer delay between two 16-bit word acquisitions to let the internal sequencer extract the data
going from internal registers to the serial shift register.

UDIR determines whether data is transferred with MSB or LSB first.

•

UPOL determines the polarity of the clock

UPHA determines the insertion of a half-clock period in the data serial flow.

•
g

•

Table 2. Microcontroller Clocking Schemes
UPHA

Falling edge without delay

MCU Clocking Scheme

Falling edge with delay

Rising edge without delay

RiSing edge with delay

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Falling edge without delay - The MCU serial interface transmits data on the falling edge of the UCLK
and receives data on the rising edge of the UCLK
Falling edge with delay - The MCU serial interface transmits data one half-cycle ahead of the falling
edge of the UCLK and receive data on the falling edge of the UCLK
RiSing edge without delay - The MCU serial interface transmits data on the rising edge of the UCLK
and receive data on the falling edge of the UCLK
Rising edge with delay - The MCU serial interface transmits data one half-cycle ahead of the rising
edge of the UCLK and receive data on the rising edge of the UCLK

UPOL

a:
a.

o
a:

With UPOL and UPHA there are four clock schemes (see Table 2):
•

O
::l
C

Three internal bits control the data serial flow as follows:
•

3:
>
w

8-143

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
DSP/MCU serial interface
The DSP/MCU serial interface is used not only to configure the GSM baseboard and voice AID and D/A
conversion but also to transmit data to the DSP during downlink burst reactions. The following paragraphs
describe the operation of the serial interface in more detail.

DSP serial digital interface
The DSP serial digital interface (Figure 14) is used to transfer the baseband transmit and receive data, and is
also used to access all internal programming registers of the device (baseband codec, voice codec and auxiliary
RF functions). The format for the serial interface is 16 bits.
The baseband serial digital interface is a bidirectional (transmiVreceive) serial port. Both receive and transmit
operations are double buffered and permit a continuous communication stream (16-bit data packets). The serial
port is fully static and functions with any arbitrary, low-clocking frequency.
Six terminals are used for the serial port interface (see Figure 4 for timing diagram). BCLKR is an 1/0 port for
the serial clock used to control the reception of the data BDR. At reset BCLKR is configured as an output and
the clock frequency is set to MCLKl3 (4.333 MHz with MCLK = 13 MHz), the clock signal is running permanently.
The port BCLKR can be reconfigured as an input by programming an internal register. In this case BCLKR is
provided by the DSP and can run in burst mode to reduce power consumption. The receive frame
synchronization (BFSR) is used to identify the beginning of a data packet transfer on port BDA.

"'C

:c
o
c

The transmitted serial data (BDX) is the serial data input; the transmit frame synchronization (BFSX) is used
to initiate the transmission of data. The transmit clock (BCLKX) is provided by the GSM baseband and voice
AID and O/A converters with a MCLK frequency. The clock signal BCLKX can run in burst mode or continuous
mode, depending on the BCLKMOOE bit. The downlink data bus (BFSX, BCLKX, BOX) can be driven to VSS
or placed in a high-impedance state when no data is to be transferred to the OSP. The bit BCLKDIR of the
register BCTLREG controls the direction of the BCLKR clock.

(")

-I
"'C

As with the voice serial interface, on extra clock cycle must be generated because the last 16-bit word received
on the DSP serial interface is latched on the next two falling BCLKR edges following the LSB. As for the voice
serial interface, one extra clock period is generated on the BCLKX before the first synchronization BFSX of the
downlink data sequence.

m
~

Data Bus

load

16
- - - -

Rint on
RSR-DDR - - - Transfer

Xint on
DXR-SXR
Transfer

Clear
Clock

BDR

BFSR BClKR BClKX BFSX

Figure 14. DSP Serial Port

•
TEXAS
INSTRUMENTS
8-144

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

BDX

iCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
DSPIMCU serial interface operation and format
The DSPfMCU serial interface is used to both configure the GSM baseband and voice AID and DfA converters
(read and write operation in internal registers) and transmist RF data to the DSP during reception of a burst by
the downlink path of the GSM baseband and voice AID and DfA circuitry.
During reception of a burst (bit DLR of the status register is 1) and DSP serial interface and associated internal
bus are dedicated to the transfer of RF data from the GSM baseband AID and DfA converters to the DSP. During
this period only a write operation of internal registers can be done through the DSP serial interface. However,
all registers can be accessed by the serial MCU interface.
During transmission of a burst (bit ULX of the status register is 1) no read or write operation can be done in the
registers of the baseband uplink part of the GSM baseband, APC RAM, and APC shape register.
Writing or reading registers using the serial interface is done by transferring 16-bit words to the serial interface.
Each word is split into three fields as shown in Table 3.
Table 3. Read/Write Data Word

->w

When writing to internal registers observe the following convention:
Bit 0

: It indicates a write operation at zero .

Bits 1 to 5

: This field contains the address of the register to be accessed.

Bits 6 to 15

: This field contains the data to be written into the internal register.

a:
a..

I-

When reading from internal registers observe the following convention:
Bit 0
Bits 1 to 5
Bits 6 to 15

: At 1 it indicates a read operation.
: This field contains the address of the register to be accessed.
: This field is an irrelevant status in a read request operation.

Read operation from the downlink baseband codec is done using the TX part of the DSPfMCU serial interface
in the following 16-bit word format given in Table 4.
Table 4. 16-Bit Word Format
DATA

15
09

I
I

14
08

I
I

13
07

I
I

12
06

ADDRESS

I
I

9
03

I
I

8
02

I
I

7
01

4
A3

I
I

3
A2

I
I

2
A1

During reception of a burst, transfer of RF data from the downlink baseband codec is done using the transmit
part of the DSP serial interface in the following 16-bit word format: As the I and Q samples are coded with 16-bit
words, the data rate is 270833 x 16 x 2 which equals 8.66 Mbps. Since the digital clock MCLK is 13 MHz, transfer
is done at 13 Mbps in burst mode. During burst reception the DSP serial interface is idled about 33% of the time.
Table 5. Format of 16-Bit Word Transfer
DATA

15
015

I
I

14
014

I
I

13
013

I
I

12
012

I
I

11
011

I
I

10
010

I
I

9
09

I
I

8
08

IfQ

L7 J

L5 J
I

4
04

J
I

3
03

1
I

2
02

1
I

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-145

a:
a..

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND DIA RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
DSP/MCU serial interface registers
The following internal register buffers are accessed using the DSP/MCU serial interface during manual
operation of the TCM4400.

baseband uplink ramp delay register
Each bit position of the baseband uplink ramp-delay register is given in Table 6.

Table 6. Uplink Ramp-Delay Register
IBUFPTR

DELD3

DELD2

DELDl

DELDO

DELU3

DELU2

DELUl

DELUO

R=O

RIW

RNI

ANI

RNI

ANI

< - ACCESS TYPE

<-VALUE AT RESET

"'tJ

o
C

DELUO to DELU3

: Value of the delay of ramp-up start versus the rising edge of BENA.

DELDO to DELD3

: Value of the delay of ramp-down start versus the falling edge of BENA.

IBUFPTR

: Writing a 1 in this bit initializes the pointer of the burst buffer to the base
address.

RESERVD

: Reserved bits for testing purposes

RIW

: A 1 indicates a read operation; a 0 indicates a write operation.

The baseband uplink data buffer is used to transmit the uplink burst data. The uplink data buffer contents are
shown in Table 7.

Table 7. Uplink Data Buffer

01010101111/0

baseband uplink data buffer

-I
"'tJ

m
::sm

I RIW

ADDRESS :1

BULRUDEL: BASEBAND UPLINK RAMP DELAY REG.
RESERVD

ADDRESS: 2 (16 WORDS)

BIT29

BIT38

BIT39

BIT47

BIT48

BIT49

BIT56

BIT57

BIT58

BIT59

BIT66

BIT67

BIT68

BIT69

BIT75

BIT76

BIT77

BIT78

BIT79

BULDATA: BASEBAND UPLINK DATA BUFFER
BITO

BITl

BIT2

BIT3

BIT4

BIT5

BIT6

BIT7

BIT8

BIT9

BIT10

BITll

BIT12

BIT13

BIT14

BIT15

BIT16

BIT17

BIT18

BIT19

BIT20

BIT21

BIT22

BIT23

BIT24

BIT25

BIT26

BIT27

BIT28

BIT30

BIT31

BIT32

BIT33

BIT34

BIT35

BIT36

BIT37

BIT40

BIT41

BIT42

BIT43

BIT44

BIT45

BIT46

BIT50

BIT51

BIT52

BIT53

BIT54

BIT55

BIT60

BIT61

BIT62

BIT63

BIT64

BIT65

BIT70

BIT71

BIT72

BIT73

BIT74

BIT80

BIT81

BIT82

BIT83

BIT84

BIT85

BIT86

BIT87

BIT88

BIT89

BIT90

BIT91

BIT92

BIT93

BIT94

BIT95

BIT96

BIT97

BIT98

BIT99

BIT100

BIT10l

BIT102

BIT103

BIT104

BIT105

BIT106

BIT107

BIT108

BIT109

BITll0

BIT111

BITl12

BITl13

BITl14

BITl15

BITl16

BITl17

BITl18

BITl19

BIT120

BIT121

BIT122

BIT123

BIT124

BIT125

BIT126

BIT127

BIT128

BIT129

BIT130

BIT131

BIT132

BIT133

BIT134

BIT135

BIT136

BIT137

BIT138

BIT139

BIT140

BIT141

BIT142

BIT143

BIT144

BIT145

BIT146

BIT147

BIT148

BIT149

BIT150

BIT151

BIT152

BIT153

BIT154

BIT155

BIT156

BIT157

BIT158

BIT159

<-ACCESS TYPE

<-VALUE AT RESET

~TEXAS

INSTRUMENTS
8-146

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
baseband uplink data buffer (continued)
Bit 0 - Bit 159 are the bits composing the sequence of the transmitted burst, bit 0 is transmitted first. For a normal
burst, the uplink data buffer is loaded as follows:
BitO to Bit3

: 4 guard bits

Bit4 to Bit6

: 3 tail bits

Bit7 to Bit66

: 58 data bits

Bit67 to Bit92

: 26 training sequence bits

Bit93 to Bit92

: 58 training sequence bits

Bit151 to Bit153

: 3 tail bits

Bit154 to Bit159

: 6 guard bits

At reset and after each transmission, the burst buffer is reinitialized with guard bits (all bits = 1).

baseband uplink I and Q offset registers
The baseband uplink I and Q offset register contain the offset values for the I and Q components, respectively,
as shown in Tables 8 and 9.

Table 8. Uplink I Offset Register
BULIOFF: BASEBAND UPLINK I OFFSET REGISTER

ADDRESS: 3

o 10 10 11

I RIW 5>
w

RESERVD

ULlOFF8

ULlOFF7

ULlOFF6

ULlOFF5

ULlOFF4

ULlOFF3

ULlOFF2

ULlOFF1

ULiOFF

RIW

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

ULiOFFO to ULlOFF1

: Integration bits during calibration (to minimize sensitivity to noise)

ULlOFF2 to ULlOFF8

: Value of the offset on I channel

RESERVD

: Reserved bits for testing purposes

RIW

: A 1 indicates a read operation; a 0 indicates a write operation

11 1 1/0

I RIW

RESERVD

ULOOFF8

ULOOFF7

ULOOFF6

ULOOFF5

ULOOFF4

ULOOFF3

ULOOFF2

ULOOFF1

ULOOFFO

RIW

<-ACCESS TYPE

<-VALUE AT RESET

1 0 11 1 0 1 0 1 1/0

ULQOFFO to ULQOFF1

: Integration bits during calibration (to minimize sensitivity to noise)

ULQOFF2 to ULQOFF8

: Value of the offset on Q channel

RESERVD

: Reserved bits for testing purposes

RIW

: A 1 indicates a read operation; a 0 indicates a write operation

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I-

c
oa:
a..

ADDRESS: 4

a:
a..

Table 9. Uplink Q Offset Register
BULQOFF: BASEBAND UPLINK Q OFFSET REGISTER

w
==

8-147

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
baseband uplink I and Q DIA conversion registers
The I and Q component values generated by the I and Q uplink DfA converter during the conversion of analog
data are written to and read from the uplink I and Q DfA converter registers as shown in Tables 10 and 11.

Table 10. Uplink I DAC Register
BULIDAC: BASEBAND UPLINK I DAC REGISTER

ADDRESS: 6

o 10

I RfW

RESERVD

ULlDAC7

ULlDAC6

ULlDAC5

ULlDAC4

ULlDAC3

ULlDAC2

ULlDAC1

ULiDACO

RIW

<-ACCEOS TYPE

<-VALUE AT RESET

11 11 101

1/0

Data applies to DfA converter of I channel

ULiDACO to ULlDAC7:
RESERVD:

Reserved bits for testing

RIW:

A 1 indicates a read operation; a 0 indicates a write operation

Table 11. Uplink Q DAC Register

-c
:c

o
c

BULQDAC: BASEBAND UPLINK Q DAC REGISTER

ADDRESS: 5

o 10

I RfW

11 1 0 11 1 1/0

RESERVD

ULODAC7

ULODAC6

ULODAC5

ULODAC4

ULODAC3

ULODAC2

ULODAC1

ULODACO

RIW

<-ACCESS TYPE

<-VALUE AT RESET

(")

ULiDACO TO ULlDAC7:

-I

RESERVD:

Reserved bits for testing

-C

RIW:

A 1 indicates a read operation; a 0 indicates a write operation

Data is applied to the DfA converter of the Q channel

~TEXAS

INSTRUMENTS
8-148

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
power down register No.2
The values in each bit position of power-down register No.2 have the meaning outlined in Table 12.
Table 12. PWDNGR2 Register
PWDNRG2: REGISTER FOR POWERING DOWN

ADDRESS: 8

o 11

I RIW

RESERVD

TIMGPN

TIMGPD

BBSIPN

BBSIPD

VGAPPN

CHGUP

VREFPN

VREFPD

R=O

RIW

R/W

RIW

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

1 0 1 0 1 0 1 1/0

VREFPN:

If cleared to 0, the internal reference voltage is powered down under the control of terminal
PWRDN and bit VREFPD. If bit VREFPD is set to 1, the power down is only controlled by bit
VREFPD.

VREFPD:

This bit is functionally associated with bit VREFPD.

VGAPPN:

If cleared to 0, the intenal reference VGAP is powered down under the control of terminal
PWRDN. If this bit is set to 1, the VGAP is not placed in power-down mode.

TIMGPN:

If cleared to 0, the timing interface is powered down under the control of terminal PWRDN.

TIMGPD:

If this bit is set to 1, the power down is only controlled by bit TIMGPD. This bit is functionally
associated with bitTIMGPN. When this bit is 1, timing interface is active and in the power-down
mode.

BBSIPN:

If cleared to 0, the baseband serial interface is powered down under the control of terminal
PWRDN. If this bit is set to 1, the power down is only controlled by bit BBSIPD.

BBSIPD:

This bit is functionally associated with bit BBSIPN. When this bit is set to 1, baseband serial
interface is in power-down mode.

a:
a.

CHGUP:

This bit is used for testing purposes to accelerate the band-gap settling time.

I-

RESRVD:

Reserved bits for testing purpose.

s:w

>
w

(.)

::J

a::

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

8-149

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
power down register No. 1
The values in each bit position of power down register No.1 have the meaning outlined in Table 13.
Table 13. PWDNRG1 Register
PWDNRG1: REGISTER FOR POWERING DOWN

ADDRESS: 7 1 RIW

o 10

SELVMID

BALOOP

VMIDW

VMIDPD

BBULW

BBULPD

BBDLW

BBDLPD

EXTCAL

BBRST

R=O

RIW

R/W

RIW

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

BBRST:

This is the digital reset of the baseband codec, the RAM is set to 1 and the
memory of the digital filter is cleared to 0.

EXTCAL:

Downlink autocalibration mode (at 0: autocalibration; at 1: external calibration)

BBULW:

If cleared to 0, the baseband uplink path is powered down under the control of
the GSM transmit window (BULaN terminal). If this bit is set to 1, the power
down in only controlled by bit BBULPD.

BBULPD:

This bit is functionally associated with bit BBULW. When this bit is set to 1, the
baseband uplink path is in power-down mode.

BBDLW:

If cleared to 0, the baseband downlink path is powered down under the control
of GSM receive window (BDLON terminal). If this bit is set to 1, the power down
is only controlled by bit BBDLPD.

BBDLPD:

This bit is functionally associated with bit BBDLW. When this bit is set to 1, the
baseband downlink path is in power-down mode.

-I

VMIDW:

If cleared to 0, the VMID output driver is powered down under the control of
GSM transmit window (BULaN terminal). If this bit is set to 1, the power down
is only controlled by bit VMIDPD.

VMIDPD:

This bit is functionally associated and paired with bit VMIDW. When VMIDW bit
is set to 1, the VMID output driver is active. When VMIDPD bit is set to 1, the
VMID output driver is in power-down mode.

BALOOP:

When set to 1, the internal analog loop of I and Q uplink terminals are connected
to I and Q downlink terminals.

SELVMID:

When cleared to 0, this sets the common-mode voltage of the baseband uplink
and VMID at VDD/2; when set to 1, these voltages are set to 1.35 V.

"'C

0
0

"'C

m
:$
m
=E

8-150

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11 11 11 1 1/0

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SlWS029-JUNE 1996

PRINCIPLES OF OPERATION
baseband control register (see Table 14)
The values in the baseband control register bit positions determine whether the data is shifted left or right. Note
that the microcontroller unit (MCU) clocking scheme determines on which edge of the clock that data is received
or transmitted using the serial interface.

Table 14. Baseband Control Register
BCTLREG: BASEBAND CONTROL REGISTER

ADDRESS: 9 1 RIW

o /1

RESERVD

MClKBP

BClKMODE

BIZBUS

BClKDIR

UDIR

UPHA

UPOl

R=O

RIW

<-ACCESS TYPE

<-VALUE AT RESET

10 1 0 111

1/0

UDIR:

This bit determines whether the data is shifted in from right (see serial
register description) to left, LSB first (bit value 0), or from left to right, MSB
first (bit value 1).

BCLKMODE:

When cleared to 0, BLCKX runs in the burst mode; when set to 1, BCLKX
is continuous

MCLKBP:

When cleared to 0, UCLK signal passes through the clock slicer; when set
to 1, the clock slicer is bypassed (in this case, the signal at the MCLK
terminal must be digital).

MCU clocking schemes
Falling edge without delay:

The MCU seriel interface transmits data on the falling edge of the UCLK and
receives data on the rising edge of UCLK.

Falling edge with delay:

The MCU serial interface transmits data one half-cycle ahead of the falling
edge of the UCLK and receives data on the falling edge of the UCLK.

Rising edge without delay:

The MCU serial interface transmits data on the rising edge of the UCLK and
receives data on the falling edge of the UCLK.

Rising edge with delay:

The MCU serial interface transmits data one half-cycle ahead of the rising
edge of the UCLK and receives data on the riSing edge of UCLK.

UPHA

MCU clocking scheme

Falling edge without delay

Falling edge with delay

Rising edge without delay

Rising edge with delay

BCLKDIR:

Direction of the BCLKR port.

BIZBUS:

When set to 1, BOX, BCLKX, BFSX are in hi-Z when there is nothing to
transfer to the DSP; when cleared to 0, DBX, BCLKX, BFSX are set to V ss
when there is nothing to transfer to the DSP.

RESRVD:

Reserved bits for testing purpose

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

:>
w
a:

a.
Io

::J
C

oa:
a.

Table 15. MCU Clocking Schemes
UPOL

8-151

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
voiceband uplink control register
The values in the voiceband uplink control reigister bit positions control not only the power level of the audio
in the uplink path but also set the gain of the PGA from -12 dB to 12 dB in 1 dB steps. Bit MICBIAS and VULMIC
and VULAUX are shifted by one position to the left. This is shown in Table 16.
Table 16. Voiceband Uplink Control Register
VBCTL1: VOICEBAND UPLINK CONTROL REGISTER

ADDRESS: 10 1 RIW

o 11

RESERVD

MICBIAS

VULMIC

VULAUX

VULPG4

VULPG3

VULPG2

VULPG1

VULPGO

R=O

RIW

. RIW

<-ACCESS TYPE

<-VALUE AT RESET

VULON:

Power on the uplink path of the audio codec

VULAUX:

Enables the auxiliary input amplifier if bit VULON is 1

VULON

1 0 11 1 0 1 1/0

VULMIC:

Enables the microphone input amplifier if bit VULON is 1

MICBIAS:

When MICBIAS = 0, the analog bias for the electret microphone and external
decoupling is driven to 2 V; when the value is 1, the bias is 2.5 V.

"tJ

RESERVD:

Reserved for testing

VULPG (0 to 4):

Gain of the voice-uplink programmable gain amplifier (-6 dB to 6 dB in 1 dB step),
see Table 17.

C
C

Table 17. Uplink PGA Gain

VULPG 4

VULPG 3

VULPG 2

VULPG 1

VULPG 0

ABS GAIN

4.6dB

-11 dB

4.6dB

-10dB

4.6dB

-9 dB

<
-

4.6dB

-8 dB

4.6dB

-7 dB

4.6dB

-6 dB

4.6dB

-5 dB

4.6dB

-4 dB

4.6dB

-3 dB

0
0

4.6dB

-2 dB

4.6dB

-1 dB

4.6dB

OdB

4.6dB

1 dB

4.6dB

2 dB

4.6dB

3dB

0
0

4.6dB

4dB

4.6dB

5dB

-I
"tJ

-12dB

4.6dB

6dB

4.6dB

7dB

4.6dB

8dB

4.6dB

9dB

4.6dB

10dB

4.6dB

11 dB

4.6dB

12dB

•
TEXAS
INSTRUMENTS
8-152

PGA RELATIVE GAIN

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

rCM4400
GSM/DCS BASEBAND AND VOICE AID AND DIA RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
voiceband downlink control register
The values in the voiceband downlink control register bit positions control the audio power level in the downlink
path. Earphone volume is set (three bits VOLCTLO -VOLCTL2) and PGA gain is set from -6 dB to 6 dB in 1
dB steps. This is shown in Table 18.

Table 18. Voiceband Downlinlc Control Register
VBCTL2: VOICEBAND DOWNLINK CONTROL REGISTER

ADDRESS: 11

I RIW

VDLAUX

VDLEAR

VOLCTL2

VOLCTL1

VOLCTLO

VDLG3

VDLG2

VDLG1

VDLGO

VDLON

RIW

R/W

RIW

R!W

RIW

R!W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

VDLON:
VDLEAR:
VDLAUX:
VDLG (0 to 3) 1dB:

11 1 0 11 11 1 1/0

Power on of the downlink path of the audio codec
Enables the earphone amplifier if the bit VDLON is 1
Enables the auxiliary output amplifier if the bit VDLON is 1
Gain of the voice-downlink programmable gain amplifier (-6 dB to 6 dB in 1-dB
steps), see Table 19.

3:
w
>
w

Table 19. Downlink PGA Gain

VOLCTL (0 to 2):

VDLG3

VDLG2

VDLG1

VDLGO

-6 dB

-5 dB

RELATIVE GAIN

-4 dB

-3 dB

-2 dB

-1 dB
OdB

1 dB

2 dB

3dB

4 dB

5 dB

6dB

-6 dB

-6dB

a:
a..

::>

o
a:
a..

Volume control (0, -6,-12,18, -24, Mute), see Table 20.

Table 20. Volume Control Gain Settings
VOLCTL2

VOLCTL1

VOLCTLO

OdB

-6dB

RELATIVE GAIN

-12dB

-18dB

-24 dB

Mute

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-153

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND DIA RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
voiceband control register
The values in the voiceband control register have the meaning shown in Table 21.
Table 21. Voiceband Control Register
VBCTL3: VOICEBAND CONTROL REGISTER

ADDRESS: 12

o 11

I RIW
I 110

RESERVD

VCLKMODE

DAIMD1

DAIMDO

VDAI

DAION

VALOOP

VIZBUS

VRST

R=O

RIW

<-ACCESS TYPE

<-VALUE AT RESET

11 10 10

VALOOP:

When set to 1, the internal analog loop of output samples are sent to the audio input
terminal; standard audio paths are connected together, and auxiliary audio paths are
connected together.

VIZBUS:

When set to 1, VFS, VCLK, VDX are put in a hi-Z state when there is nothing to
transfer to the DSP, when cleared to 0, VFS and VCLK are put in VSS when there is
nothing to transfer to the DSP, and the VDX bus drives an undefined value (value
depends on the previous serial data transfers).

-c

VRST:

Resets the digital parts of the audio codec (digital filter and modulator).

::D

DAION:

When cleared to 0, the DAI block is in power down; when set to 1, the DAI block is
active.

VDAI:

Writing a 1 to this bit starts the SSCLK (104 kHz DAI clock) on reception of the first
sample. This bit is automatically reset to 0 by SSRST after reception of the last
sample.

RESERVD:

Reserved bits for testing

o
-t
-c
::D
m
S
m

DAIMD (0-1):

DAI mode selection as given in Table 22.

VCLKMODE

When cleared to 0, allows selection of VCLK in burst mode. When set to 1, allowsselection of VCLK in continuous mode.
Table 22. DAI Mode Selection

8-154

DAIMD1

DAIMDO

Normal operation (no tested device using DAI)

Test of speech decoder I DTX functions (downlink)

Test of speech encoder I DTX functions (uplink)

Test of acoustic devices and NO and D/A (voice path)

DAI MODE

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TCiVl4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
auxiliary functions control register No. 1
The bit values in the auxiliary functions control register No.1 resets the APC generator or the AFC modulator,
selects the AID counter input, and selects the AFC sampling frequency. This is shown in Table 23.

Table 23. AUX Functions Control Register No.1
UXCTL1: AUXILIARY FUNCTIONS CONTROL REGISTER

ADDRESS: 13

I RIW

11 11 1 0 11 1 1/0

AFCPN

AFCPD

ADCPN

ADCPD

AFCCK1

AFCCKO

ADCCH2

ADCCH1

ADCCHO

ARST

RIW

<-ACCESS TYPE

<-VALUE AT RESET

ARST:

Reset of the digital parts of the auxiliary functions (APC generator and AFC modulator).

ADCCH(O to 2):

Selection of the input of the AID converter, see Table 24.

Table 24. AID Converter Selection
ADCCH2

ADCCH1

ADCCH 0

AID conversion of ADIN1

AID conversion of ADIN2

AID conversion of ADIN3

AID conversion of ADIN4

AID conversion of ADIN5

AFCCK(O To 1):

AID CONVERTER INPUT SELECTION

s:w

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a:
a.

....

::J
C

Selection of the sampling frequency of the AFC, see Table 25.

oa:

Table 25. AFC Selection
AFCINTERNALFREQUENCY

AFCCK 1

AFCCKO

0.25 MHz

0.50 MHz

1 MHz

2 MHz

AFCPN:

If cleared to 0, the AFC block is powered down under the control of the PWRDN
terminal. If this bit is set to 1, the power down is only controlled by bit AFCPD.

AFCPD:

This bit is functionally associated and paired with bit AFCPN. When the AFCPN bit is
1, the AFC block is active. When the AFCPD bit is set to 1, the AFCPD block is in
power-down mode.

ADCPN:

If cleared to 0, the auxiliary ADC block is powered down when under the control of
PWRDN.
If this bit is set to 1, the power down is only controlled by bit ADCPD.

ADCPD:

This bit is functionally associated and paired with bit ADCPN. When the ADCPN bit is
set to 1, an auxiliary ADC is active. When the ADCPD bit is set to 1, the auxiliary
ADCPD is in power-down mode.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-155

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
automatic frequency control register (No. 1 and No.2)
There are two AFC control registers; each is 10 bits wide. AFC control register No.1 contains the least significant
bit of the AFC D/A converter output. AFC control register No.2 contains the most significant bit of the AFC D/A
converter input. See Table 26 and 27. The AFC value is loaded after successive writes of AFC MSB and AFC
LSB.
Table 26. AFC Control Register 1
AUXAFC1: AUTOMATIC FREQUENCY CONTROL REG1

ADDRESS: 14

o 11

I RIW

BIT9

BIT8

BIT?

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

R/W

RIW

R/W

<-ACCESS TYPE

<-VALUE AT RESET

11 11 10 1 1/0

LSB input of the 13-bit AFC D/A converter in 2's complement.

BIT9 to BITO:

Table 27. AFC Control Register 2

"tJ

AUXAFC2: AUTOMATIC FREQUENCY CONTROL REG2

ADDRESS: 15

o 11

I RIW

RESREVD

BIT12

BITll

BIT10

R=O

RIW

R/W

<-ACCESS TYPE

<-VALUE AT RESET

c:
o
-I
"tJ
:tJ

BIT12 to BIT10:

MSB Input of the 13-bit AFC D/A converter in 2's complement.

automatic power control register
The values in the automatic power control (APC) register set the operating conditions for the APC circuit, see
Table 28.

!S
m
=E

11 11 11 1 1/0

Table 28. APC Register
AUXAPC: AUTOMATIC POWER CONTROL REGISTER

ADDRESS: 16 1 RIW

RESERVD

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BITl

BITO

R=O

RIW

R/W

RIW

R/W

<-ACCESS TYPE

<-VALUE AT RESET

BIT7 to BITO:

Input of the 8-bit level APC DAC.

RESERVD:

Reserved bits for testing

~TEXAS

INSTRUMENTS
8-156

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1 10 1 0 1 0 10 1 1/0

TCfII14400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
automatic frequency control register (No. 1 and No.2) (continued)
The content of the APC RAM describes the shape of the ramp-up and ramp-down control, see Table 29.
Table 29. APC Ramp Control
APCRAM: AUTOMATIC POWER CONTROL RAM

RUP WORDO ( S BIT)

RDWNWORD1 (5BIT)

RUP WORD 21 (5 BIT)

111//11

///111111

IIIIII

IIIIIII

IIIIII

///11111

111111///1

//11111

IIIIII

IIIIIII

IIIIIIII

IIIIII

RDWNWORD62 (SBIT)

RUP WORD 62 (S BIT)

RDWNWORD63 (SBIT)

RUP WORD 63(S BIT)

I
I

ADDRESS: 17 (64 Words)

RDWN WORDO (S BIT)

Iw I
I X I

I
I

Iw I
I X I

<-ACCESS TYPE

<-VALUE AT RESET

Actual shape values (5 bits long) are contained in the shape D/A converter input register as shown in Table 30.

Table 30. Shape DAC Input Register
APCSHAP: SHAPE DAC INPUT REGISTER

ADDRESS: 18 1 RIW

RESERVD

BIT4

BIT3

BIT2

BIT1

BITO

R=O

RIW

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

BIT4 to BITO:

Input of the 5-bit APC DAC.

RESERVD:

Reserved bits for testing

1 1 0 10 11 1 0 1 1/0

analog AGe control register
The AGC control register is 1O-bits wide and controls operations of the analog AGC circuit as shown in Table 31 .

Table 31. Analog AGC Gain Control Register
AUXAAGC: ANALOG AUTOMATIC GAIN CONTROL REGISTER

ADDRESS: 19

I RIW

BIT9

BIT8

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

RIW

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

BIT9 to BITO:

Input of the 10-bit AAGC DAC.

RESERVD:

Reserved bits testing

1 1 0 10 1 1 11 1 1/0

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-157

:>
w

a:
a..
Io

::l

a:
a..

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
auxiliary functions control register No.2 (see Table 32)
The values in the auxiliary function control register No.2 set the operation parameters as decribed below:

"oJJ
C
C

AFCZ:

Selection of internal resistance of AFC driver. When AFCZ is 1, the resistance is 50 kn.
When AFZ is 0, the resistance is 25 kOhm. The largest swing is obtained with 50 kQ.

APCSCD:

When cleared to 0, the APC clock is at 4 MHz; when set to 1, the APC clock is at 2 MHz.

AGCSWG:

Selection of the swing of the AAGC output: 0 corresponds to a 0 V to 1.1 V swing;
1 corresponds to 0 V to 3.3 V swing

APCSWG:.

Selection of the swing of the APC output: 0 corresponds to a O-V to 3-V swing;
1 corresponds to O-V to 5-V swing

IAPCPTR:

Setting to 1 initializes the pointer of the APC RAM to the base address.

AAGCW:

If cleared to 0, the automatic gain control path is powered down with the control of GSM
receive window (BDLON terminal) and AAGCPD bit. If the AAGCPD bit is set to 1, the
power down is controlled by AAGCPD bit.

AAGCPD:

This bit is functionally associated with AAGCW bit. When this bit is set to 1, the automatic
gain control path is in power-down mode.

APCW:

If 0, the RF Power Control path is down powered with the control of GSM transmit
window (BULaN) and with the control of APCPD bit. If the APCPD bit is set to 1, power
down is only controlled by APCPD bit.

APCPD:

This bit is functionally associated with BBULW bit. When this bit is set to 1, the RF power
control path is in power-down mode.

-t

"mJJ

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m
=E

Table 32. AUX Functions Control Register No.2
AUXCTL2: AUXILIARY FUNCTIONS CONTROL REGISTER

ADDRESS: 20

I RIW

AGCW

AGCPD

APCW

APCPD3

IAPCTR

RESERVD

APCSWG

AGCSWG

APCSPD

AFCZ

RIW

<-ACCESS TYPE

<-VALUE AT RESET

~TEXAS

INSTRUMENTS
8-158

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1 / 0 / 1 / 0 / 0 /1/0

TCivl4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029-JUNE 1996

PRINCIPLES OF OPERATION
auxiliary AID converter output register
This register is read-only, but when there is an attempt to write into it, AID conversion starts see Table 33. When
the AID conversion is finished, the AUXADC register is loaded and the AID converter is automatically down
powered. During the conversion process the ADCEOC bit of the BSTATUS register is set. This bit is reset
automatically after AUXADC is loaded.

Table 33. AUX AID Converter Output Register
AUXADC: AUXILIARY AlD CONVERTER OUTPUT REGISTER

ADDRESS: 21

BIT9

BIT8

BIT7

BIT6

BITS

BIT4

BIT3

BIT2

BIT1

BITO

RIW

<-ACCESS TYPE

<-VALUE AT RESET

BIT9 to BITO:

1 10 /1 10 /1 1 1/0

Output of the 10-bit monitoring ADC.

baseband status register
The baseband status register stores the baseband status as decribed in Table 34.

:s:w

Table 34. Baseband Status Register
BSTATUS: BASEBAND STATUS REGISTER

1 10 11 11 1 0 1

ADDRESS: 22

RESERVD

ADCEOC

RAMPTR

BUFPTR

ULON

ULCAL

ULX

DLON

DLCAL

DLR

R=O

<-ACCESS TYPE

<-VALUE AT RESET

DLR:

This bit is set to 1 during conversion of a burst in the downlink path.

DLCAL:

This bit is set to 1 during offset calibration of the downlink path.

DLON:

When is set to 1, it indicates that the downlink path is in powered on.

ULX:

This bit is set to 1 during transmission of the burst in the uplink path.

ULCAL:

This bit is set to 1 during offset calibration of the uplink path.

ULON:

When set to 1, it indicates that the uplink path is in powered on.

BUFPTR:

When set to 1, it indicates that the pointer of the burst buffer is at address zero.

RAMPTR:

When set to 1, it indicates that the pointer of the APC RAM is at address zero.

ADCEOC:

(ADC-end of conversion) when this bit is set to 1, an ADC conversion is in process .

::l
C

a:
0-

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

>
w
a:

8-159

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
voiceband control register 4 (address 23)
Voiceband control register4 (VBCTL4) is a read/write register (see Table 35) and contains the four programming
bits of of VDLST as shown in Table 36.
Table 35. Voiceband Control Register 4
VBCTL4: VOICEBAND CONTROL REGISTER 4

ADDRESS: 23

1 RIW

1 1 0 11 11 11 1 1/0

RESERVD

VDLST3

VDLST2

VDLST1

VDLSTO

R=O

RIW

<-ACCESS TYPE

<-VALUE AT RESET

Table 36. VDLST Status
VDLST3

VDLST2

VDLST1

VDLSTO

Mute

-17 dB

-14 dB

-11 dB

-8 dB

-5 dB (nominal)

""C

:xJ

SIDE TONE GAIN

-2 dB

+1 dB

c:
-I

baseband uplink register (address 24)

"'tJ

The baseband uplink register (BULCTL) is a 3-bit register (see Table 37) that permits mismatch compensation
in the RF transmit mixer. Gain mismatches of 0 dB, -0.25 dB, -0.5 dB, and -0.25 dB are permitted between
the I and Q channel as shown in Table 38.

:xJ

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-

Table 37. Uplink Register BULCTL
ADDRESS: 24 1 RIW

BULCTL: BASEBAND UPLINK CONTROL REGISTER

RESERVD

IQSEL

R=O

R/W

RIW

<-ACCESS TYPE

<-VALUE AT RESET

Table 38. BLKCTL Register
BIT2

BIT1

BITO

IQSEL

GAIN I

GAINQ

OdB

-0.25 dB

OdB

-0.50 dB

OdB
OdB

-0.75 dB

OdB

- 0.25 dB

OdB

-0.50 dB

OdB

-0.75 dB

"TEXAS
INSTRUMENTS
8-160

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

1 11 1 0 1 0 10 1 1/0

TCM4400
GSM/DCS BASEBAND AND VOICE AID AND D/A RF INTERFACE CIRCUIT
SLWS029 - JUNE 1996

PRINCIPLES OF OPERATION
timing and interface
Accurate timing control of baseband uplink and downlink paths is performed using the timing serial interface.
The timing interface is a parallel asynchronous port with four control signals, refer to Figure 15. The BOLON
bit controls power on the downlink path of the baseband codec; the BULaN bit controls power on the uplink path
of the baseband codec, and the BCAL bit controls the calibration of the active parts of the baseband codec
selected by BULaN or BOLON.
The BENA bit controls the transmission of the reception of burst depending on which part of the baseband codec
is selected by the signals BULaN or BOLON. These asynchronous inputs are internally synchronized with the
uplink and downlink internal clocks and stored in timing register TR. The timing register, TR, is a 6-bit register
containing the bits defined in Table 39.

Table 39. 6-Bit TR Register

TR bit signification

3:
w

ULaN:

If set to 1, this bit turns on the uplink path of the baseband codec; if cleared to 0, the uplink
path is in power-down mode.

ULCAL:

When this bit is set to 1, the uplink offset autocalibration is active.

ULSENO:

A transition from 0 to 1 of ULSENO initiates the emission of a burst. The burst informations
data, burst length, and power level need to be loaded in the corresponding registers using
the serial interface.

OLON:

If set at 1, this bit turns on the downlink path of the baseband codec; if cleared to 0, the
downlink path is in power-down mode.

(.)

OLCAL:

When this bit is set at 1, the downlink offset autocalibration is active.·

OLREC:

A transition from 0 to 1 of OLREC initiates the transmission of data from the baseband codec
to the OSP using the serial interface.
BOLON

BCAL

BENA

BULON

CKOL

CKUL

OLON

OLCAL OLREC

ULON

ULCAL ULSENO

Figure 15. Timing Interface

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8-161

:>
w
a:

I--

::J
C

8-162

General Information

•

" - - - -_ _ _ _- - - - - 1

Telecommunications Circuits

Central Office Codecs

•

Transient Voltage Suppressors

•

RF for Telemetry and RKE

•

Wireless Communications Circuits
Processors for Analog C.ellular
Voice~Band

Audio Processors

RF for.· Personal Communications
Baseband .Interface Circuits
Digital Signal Processors

Mechanical· Data

9-1

c_.

_.
....

-_.
en
Q)

::::J

--a
Q)

....

CD
UJ
UJ

....UJ0

9-2

Ti'v1S320C203, Ti'v1S320C209, TiV1S320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

• High-Performance Static CMOS Technology

• 32-Bit ALU/ Accumulator

• Includes the T320C2xLP Core CPU

• 16 x 16-Bit Multiplier With a 32-Bit Product

• 16-Bit Timer
• Instruction Cycle
'C203
50 ns @ 5 V
35 ns @ 5 V
25 ns @ 5 V
35 ns @ 3 V
50 ns @ 3 V

• Block Moves for Data, Program, I/O Port
Space

Time
'C209
50 ns @ 5 V
35 ns @ 5 V

• Source Compatible With TMS320C25
• Upwardly Compatible to TMS320C5x
Devices
• TMS320C203 100-Pin PZ Package
• TMS320C209 BO-Pin PN Package

• TMS320C2xx Peripherals:
- On-Chip 16-Bit Timer
- 1 Wait State Software Programmable to
Each Space (,C209 Only)
- 0 - 7 Wait States Software Programmable
to Each Space ('C203 Only)
- On-Chip Oscillator
- One Synchronous Serial Port With Four
Level Deep FIFOs (,C203 Only)
- Full-Duplex Asynchronous Serial Port
(UART) (,C203 Only)
• Input Clock Options:
- x1, x2, x4, -;.-2 (,C203)
- x2 -;.-2 (,C209)

• Three external Interrupts
• Boot-Loader Option (,C203 Only)
• TMS320C2xx Integrated Memory:
- 544 x 16 Words of On-Chip Dual Access
Data RAM ('C2xx)
- 4K x 16 Words of On-Chip Single Access
Program/Data RAM (,C209 Only)
- 4K x 16 Words of On-Chip Program ROM
(,C209 Only)

o
~
a:
a:
ou.

• Support of Hardware Wait States
• Power Down IDLE Mode
• Scan-Based Emulation
• 1.1 rnA/MIPS at 3 V

• 224K x 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K I/O, and 32K Global)

U
Z

description
The TMS320C2xx generation of Texas Instruments TMS320 digital signal processors (DSPs) is fabricated with
static CMOS integrated circuit technology, and their architectural design is based upon that of the TMS320C5x
series, optimized for low power operation (see Table 1).The combination of advanced Harvard architecture,
on-chip peripherals, on-chip memory, and a highly specialized instruction set is the basis of the operational
flexibility and speed of the 'C2xx devices.
The TMS320C203 is packaged in a 100-pin PZ package while the TMS320C209 is packaged in an 80-pin PN
package.
The 'C2xx generation offers these advantages:
•
•
•
•

Enhanced TMS320 architectural design for increased performance and versatility
Advanced integrated-circuit processing technology for increased performance
Source code for the 'C2xx DSPs is software-compatible with the 'C1x and 'C2x DSPs and is upwardly
compatible with fifth-generation DSPs ('C5x)
New static-design techniques for minimizing power consumption and increasing radiation tolerance

ADVANCE INFORMA1l0N concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-3

~
C

:s xu>
10 13: >

f-10<:

EMUO
EMU1/0Ff'
TCK
TRST
TOI
TMS
TOO

VDD
READY
VSS
R/W

STIm

I'm
WE
BR

Vss
CLKR
FSR
DR
CLKX
Vss
FSX
DX
VDD
TOUT
TX
Vss
RX

100

NO
liS

~
o

NO
MP/MC
D15
Vss
D14
D13
VDD
D12
D11
Dl0
D9
D8

Vss
D6
D5
D4
D3

101
XF

READY
TCK

Vss
D11
VDD
Dl0
D9
D8
D7

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

5
6
7
8
9
10
11
12
13
14
15
16

Vss
D15
D14
D13
D12

g~~~~~~~~~~ffi~~$~~~~~

0
VDD
EMUO
EMUl
RS
TOI

17
18
19
20

A15
A14
A13
A12
Vss
All
Al0
A9
A8
VDD
VDD
A7
A6
Vss
A5

A4
A3
A2
Al
Vss

~NM~~m~romo~NM~~~~romo

NNNNNNNNNMMMMMMMMMM~

rJ) (/)f'o..

CD LOv ("') N

(/) enO 0 0 0 0

(f) ......

en 0

ocnl
...
0::;; f- f- f-

1C\J1C"')1~ z

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.....

en
~

-z

description (continued)

Table 2 provides a comparison of the devices in the 'C2xx generation. It shows the capacity of on-chip RAM
and ROM memories, number of serial and parallel 110 ports, execution time of one machine cycle, and type of
package with total pin count.

s:
~

Table 1. Low Power Dissipation

o
z

POWER

TMS320C203

1.1 rna/MIPS

TMS320C209

N/A

1.9 rna/MIPS

Table 2. Characteristics of the TMS320C2xx Processors
ON-CHIP MEMORY

1/0 PORTS

DATA

DATAl
PROG

PROG

SERIAL

PARALLEL

POWER
SUPPLY
(V)

TMS320C203

288

256

64K

3/5

50/35/25

PZ 100-PIN

TMS320C209

288

4K+ 256

64K

50/35

PN 80-PIN

TMS320C2XX
DEVICES

RAM

ROM

•
TEXAS
INSTRUMENTS
9-4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CYCLE
TIME
(NS)

PACKAGE
TYPE
PIN COUNT

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

TMS320C203 Interface Signals
PIN
NAME

NO.

I/OlZt

DESCRIPTION
DATA AND ADDRESS BUSES

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
DO

41
40
39
38
36
34
33
32
31
29
28
27
26
24
23
22

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5

74
73
72
71
69
68
67
66
64
62
61
60
58
57
56
55

A4
A3
A2
A1

Parallel data bus D15(MSB) through DO (LSB). Multiplexed to transfer data between the TMS320C2xx
and external data/program memory or 1/0 devices. Placed in the high-impedance state when not
outputting (R IW high) or RS when asserted. They go into the high-impedance state when OFF is active
low.

1/0lZ

Parallel data bus A15(MSB) through AO (LSB). Multiplexed to address external datal program memory
or 1/0 devices. These signals go into the high-impedance state when OFF is active low.

o
Z

OIZ

Program select signal. PS is always high unless low level asserted for communicating to off-chip program
space. PS goes into the high-impedance state when OFF is active low.

OIZ

Data select signal. DS is always high unless low level asserted for communicating to off-chip program
space. DS goes into the high-impedance state when OFF is active low.

OIZ

1/0 space select signal. IS is always high unless low level asserted for communicating to input/output
ports. is goes into the high-impedance state when OFF is active low.

READY

Data ready input. READY indicates that an external device is prepared for the bus transaction to be
completed.lfthe device is not ready (READY low), the TMS320C203 waits one cycle and checks READY
again. If READY is not used it should be pulled high.

R/W

OIZ

Readlwrite signal. RIW indicates transfer direction when communicating to an external device. Normally
in read mode (high), unless low level is asserted for performing a write operation. R/W goes into the
high-impedance state when OFF is active low.

OIZ

Read select indicates an active, external read cycle and can connect directly to the output enable (OE)
of external devices. RD is active on all external program, data, and 1/0 reads. RD goes into the
high-impedance state when OFF is active low.

OIZ

Write enable. The falling edge of WE indicates that the device is driving the external data bus (D15-DO).
Data can be latched by an external device on the rising edge of WE. WE is active on all external program,
data, and 1/0 writes. WE goes into the high-irnpedance state when OFF is active low.

!i:a:
o
u.

OIZ

MEMORY CONTROL SIGNALS
PS

z
o

I = input, 0 = output, Z =high impedance

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-5

~
C

Branch control input. When polled by BIOZ instruction, if BIO is low, the TMS320C203 executes a branch.
If BIO is not used it should be pulled high.
Software controlled Input/output pins via the asynchronous serial port register (ASPCA). At reset these pins
are configured as inputs. These can be used as general purpose input/output pins or as handshake control
for the UAAT. 100-103 go into the high-impedance state when OFF is active low.
INITIALIZATION, INTERRUPTS, AND RESET OPERATIONS

o
m

-z

"o::xJ

100

TEST

Aeserved input pin. Do not connect to this pin.

BOOT

Microprocessor mode select pin. When BOOT is high the device accesses off-chip memory. If BOOT is low,
the on-chip bootloader transfers data from external global data space to external AAM program space.

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked via the INTM or the IMR. When
NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should be pulled
high.

External user interrupts. Prioritized and maskable by the interrupt mask register (IMA) and the interrupt mode
bit (INTM). Can be polled and reset via the interruptflag register (IFA).lfthese signals are not used, they should
be pulled high. INT1 IHOLD can select a hold mode where the address, data, and control lines are 3-stated.
HOLD has priority over INT1 at reset.

NMI

~
oz

Aeset input. AS causes the TMS320C203 to terminate execution and forces the program counter to zero.
When AS is brought high, execution begins at location 0 of program memory after 16 cycles. AS affects
various registers and status bits.

HOLDIINT1
INT2
INT3

18
19
20

OSCILLATOR, PLL, AND TIMER SIGNALS

TOUT

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a CLKOUT1
cycle wide. TOUT goes into the high-impedance state when OFF is active low.

CLKOUT1

O/Z

Master clock ouput signal. The CLKOUT1 high pulse signifies the logic phase while the low pulse signifies the
latch phase.

CLKIN/X2
X1

12
13

I
0

Input clock. CLKIN/X2 is the input clock to the device. X1 is either multiplied and phase-locked using the PLL
operation or can bypass the PLL and operate in a divide-by-two mode. As X2, the pin operates as the oscillator
input with X1 being the oscillator output.

DIV1
DIV2

3
5

DIV1 and DIV2 provide clock mode inputs.
DIV1-DIV2 should not be changed unless the AS signal is active.

I = Input, 0 = output, Z =high impedance

•
TEXAS
INSTRUMENTS
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C203, TMS320C209, TiViS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

TMS320C203 Interface Signals (Continued)
PIN
NAME

NO.

I/OlZt

DESCRIPTION

PLL operating at 5 V. When the device is operated at 5 V, PLL5V should be strapped high. When operating
at 3 V, PLL5V should be strapped low.

OSCILLATOR, PLL, AND TIMER SIGNALS (CONTINUED)
PLL5V

SERIAL PORT AND UART SIGNALS

CLKX

1/0

Transmit clock. CLKX is a clock signal for clocking data from the OX (data receive register) to the OX pin data
transmit pin. The CLKX can be an input if the MCM bit in the SSPCR is set to o. CLKX can also be driven by
the device at one-half of the CLKOUT1 frequency when MCM = 1. If the serial port is not being used, CLKX
can be sampled as an 1/0 pin via the IN1 bit of the SSPCR register. CLKX goes into the high-impedance state
when OFF is active low. Value at reset is as an input.

CLKR

Receive clock input. External clock signal for clocking data from the DR (data receive) pin into the RSR (serial
port shift register). CLKR must be present during serial port transfers. If the serial port is not being used, CLKR
can be sampled as an input via the INO bit of the SSPCR.

FSR

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data receive
process beginning the clocking of the RSR. FSR goes into the high-impedance state when OFF is active low.
Frame synchronization pulse for transmit inputlouput. The falling edge of the FSR pulse initiates the
data-transmit process beginning the clocking of the RSR. Following reset, FSX is an input. FSX can be selected
by software to be an output when the TXM bit in the serial control registers, SSPCR is set to 1. FSX goes into
the high-impedance state when OFF is active low.

FSX

1/0

Serial data receive input. Serial data is received in the receive shift register (RSR) via DR.

Serial port transmit output. Serial data transmitted from the transmit shift register (XSR) via OX. Placed in the
high-impedance state when not transmitting and also when OFF is active low.

Asynchronous transmit pin.

Asynchronous receive pin.

JTAG test reset. TRST, when active high, gives the JTAG-scan system control of the operations of the device.
If TRST is not connected or driven low, the device operates in its functional mode, and the JTAG signals are
ignored.

TCK

JTAG test clock. TCK is normally a free-running clock signal with a 50% duty cycle. The changes on TAP (test
access port) input signals (TMS and TOI) are clOCked i'nto the TAP controller, instruction register, or selected
test data register on the rising edge of TCK. Changes at the TAP output signal (TOO) occur on the falling edge
of TCK.

TMS

JTAG test mode select. TMS is clocked into the TAP controller on the rising edge of TCK.

TOI

JTAG test data input. TOI is clocked into the selected register (instruction or data) on a rising edge of TCK.

TOO

Oil

EMUO

I/0Il

Emulator pin o. When TRST is driven low, this pin must be high for activation of the OFF condition. When TRST
is driven high, this pin is used as an interrupt to or from the emulator system and is defined an input/output
via JTAG scan.

I/0Il

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1 IOFF is used as an
interrupt to or from the emulator system and is defined as inputloutput via JTAG scan. When TRST is driven
low, this pin is configured as OFF. EMU1 10FF, when active low, puts all output drivers in the high-impedance
state. Note that OFF is used exclusively for testing and emulation purposes (not for multiprocessing
applications). Thus, for OFF condition, the following apply:
TRST = 0
EMUO = 1
EMU/OFF =0

I = input, 0 = output, l =high impedance

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

o
Z

~
C

JTAG test data output. The contents of the selected register (instruction or data) are shifted out of TOO on the
falling edge of TCK. TOO is in the high-impedance state except when scanning of data is in progress.

EMU1/0FF

oLL

TEST SIGNALS
TRST

o
~

9-7

VSS

~
Z

-Z

11
16
35
50
63
75
91
14
21
25
30
37
42
48
54
59
65
70
83
88
94

PWR

Power.

GND

Ground.

I = input. 0 = output. Z =high impedance

~
oz

~TEXAS

INSTRUMENTS
9-8

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C203, TruiS320C209, TruiS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

TMS320C209 Pin Functions
PIN
NAME

NO.

DESCRIPTION

I/O/zt

ADDRESS AND DATA BUSES
015
014
013
012
011
010
D9
08
07
D6
D5
04
03
02
D1
DO

11
13
14
16
17
18
19
20
23
24
25
26
27
28
30
31

A15
A14
A13
A12
A11
A10

60
59
58
57
55
54
53
52
49
48
46
45
44
43
42
39

A9
A8
A7
A6
A5
A4
A3
A2
A1
AD

Parallel data bus 015 (MSB) through DO (LSB). 015-00 are multiplexed to transfer data between the
core CPU and external datalprogram memory or 1/0 devices. 015-00 are placed in the
high-impedance state when not outputting or when RS is asserted. They also go into the high-impedance
state when OFF is active low. 015-00 are also used in external DMA access of the on-chip
single-access RAM.

I/OIZ

Parallel address bus A15 (MSB) through AO (LSB). A15-AO are multiplexed to address external
datalprogram memory or 1/0. A15-AO go into the high-impedance state when OFF is active low.
A15-AO are used as inputs for external OMA access of the on-chip single-access RAM.

~
~

o11.

OIZ

o
Z

MEMORY CONTROL SIGNALS
DS

OIZ

Data select signal. DS is always high unless low level asserted for communicating to off-chip program
space. DS goes into the high-impedance state when OFF is active low.

OIZ

Program select signal. PS is always high unless low-level asserted for communicating to off-chip
program space. PS goes into the high-impedance state when OFF is active low.

OIZ

1/0 space select signal. IS is always high unless low level asserted for communicating to 1/0 ports. IS
goes into the high-impedance state when OFF is active low.

READY

Data-ready input. READY indicates that an external device is prepared for the bus transaction to be
completed. If READY is not (READY low), the TMS320C209 waits one cycle and checks READY again.
If READY is not used it should be pulled high.

R/W

OIZ

Read/write signal. R/W indicates transfer direction when communicating to an external device.
Normally in read mode (high), unless low-level is asserted for performing a write operation. R/W goes
into the high-impedance state when OFF is active low.

STRB

OIZ

Strobe signal. STRB is always high unless asserted low to indicate an external bus cycle. STRB goes
into the high-impedance state when OFF is active low.

OIZ

Read select. RD indicates an active, external read cycle and can connect directly to the output enable
(0 E) of external devices. RO is active on all external program, data, and 1/0 reads. RD goes into the
high-impedance state when OFF is active low.

z
o

t I = input, a = output, Z =high impedance

•
TEXAS
INSTRUMENTS
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9-9

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

TMS320C209 Pin Functions (Continued)
PIN
NAME

NO.

I/O/zt

DESCRIPTION

Write enable. The falling edge of WE indicates that the device is driving the external data bus (015 - ~O).
Data can be latched by an external device on the rising edge of WE. WE is active on all external program,
data, and I/O writes. WE goes into the high-impedance state when OFF is active low.

MEMORY CONTROL SIGNALS (CONTINUED)
WE

O/Z

RAMEN

RAM enable. RAMEN enables the 4K x 16 words of on-chip RAM.
MULTIPROCESSING SIGNALS

O/Z

Bus request signal. BR is asserted during access of external global data memory space. BR can be used
to extend the data memory address space by up to 32K words. BR goes into the high-impedance state
when OFF is active low.

BIO

Branch control input. BIO is polled by BIOZ instruction. If BIO is low, the TMS320C209 executes a
branch. If BIO is not used, it should be pulled high.

O/Z

External flag output (latched software-programmable signal). XF is used for signaling other processors
in multiprocessing configurations or a general-purpose output pin.

lACK

O/Z

Interrupt acknowledge signal. lACK indicates receipt of an interrupt and that the program counter is
fetching the interrupt vector location designated by A 15-AO. lACK also goes into the high-impedance
state when OFF is active low.

INT1
INT2
INT3

33
34
35

External-user interrupts. INT1 -I NT3 are prioritized and maskable by the interrupt-mask register and the
interrupt-mode bit. If INT1-INT3 are not used they should be pulled high.

NMI

Nonmaskable interrupt. NMI is an external interrupt that cannot be masked via the INTM or the IMR.
When NMI is activated, the processor traps to the appropriate vector location. If NMI is not used, it should
be pulled high.

RS
RS

4
6

Reset input. RS and RS cause the TMS320C209 to terminate execution and force the program counter
to O. When RS is brought high, execution begins at location 0 of program memory after 16 cycles. RS
affects various registers and status bits.

MP/MC

Microprocessor/microcontroller mode-select pin. If MP/MC is low, the on-chip ROM is mapped into
program space. When MP/MC is high, the device accesses off-chip memory.

INITIALIZATION, INTERRUPT, AND RESET OPERATIONS

o
m

:rJ

OSCILLATOR/TIMER SIGNALS CLKIN1/2

o
z

CLKOUT1

O/Z

Masterclock output signal. CLKOUT1 cycles atthe machine-cycle rate ofthe CPU. The internal machine
cycle is bounded by the rising edges of CLKOUT1 . CLKOUT1 goes into the high-impedance state when
OFF is active low.

CLKMOO

Clock input mode. CLKMOD (when high) enables the clock doubler and phase lock loop on the clock
input signal. If the internal oscillator is not used, X1 should be left unconnected.

CLKIN/X2
X1

69
70

Clock input. The clock input to CLKIN/X2 operates at half of the internal machine rate if the phase lock
loop (PLL) is enabled (CLKMOD high), or twice the internal machine rate if the PLL is disabled. As X2,
the pin operates as the oscillator input with X1 being the oscillator output.

TOUT

Timer output. TOUT signals a pulse when the on-chip timer counts down past zero. The pulse is a
CLKOUT1 cycle wide.

PLL5V

PLL operating at 5 V. When PLL5V is operated at 5 V, PLL5V should be strapped high.

RES1

Reserved input pin. Do not connect to RES1.

I = input, 0 = output, Z =high impedance

•
TEXAS
INSTRUMENTS
9-10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiVlS320C203, TMS320C209, TiViS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

TMS320C209 Pin Functions (Continued)
PIN
NAME

NO.

I/O/zt

DESCRIPTION
TEST SIGNALS

TCK

JTAG test clock. TCK is normally a free-running clock signal with a50% duty cycle. The changes on TAP
(test access port) input signals (TMS and TOI) are clocked into the TAP controller, instruction register,
or selected test-data register on the rising edge of TCK. Changes at the TAP output signal (TOO) occur
on the falling edge of TCK.

TOI

JTAG test data input. TDI is clocked into the selected register (instruction or data) on a rising edge of
TCK.

TOO

OIZ

JTAG test data output. The contents of the selected register (instruction or data) are shifted out of TOO
on the falling edge of TCK. TOO is in the high-impedance state except when scanning of data is in
progress. TOO goes into the high-impedance state when OFF is active low.

TMS

JTAG test mode select. TMS is clocked into the TAP controller on the rising edge of TCK.

TRST

JTAG test reset. TRST, when active high, gives the JTAG scan system control of the operations of the
device. If TRST is not connected or driven low, the device operates in its functional mode, and the JTAG
signals are ignored.
Emulator pin O. When TRST is driven low, this pin must be high for activation of the OFF condition. When
TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined an
input/output via JTAG scan.

EMUO
EMU1

2
3

I/OIZ

Emulator pin 1. Emulator pin 1 disables all outputs. When TRST is driven high, EMU1 10FF is used as
an interrupt to or from the emulator system and is defined as input/output via JTAG scan. When TRST
is driven low, this pin is configured as OFF. EMU1 10FF, when active low, puts all output drivers in the
high-impedance state

VOO

VSS

12
21
22
29
41
47
56
61
73

PWR

o
LL

SUPPLY PINS
1
15
50
51
76

z
o

Power.

o
Z

PWR

Ground.

~
Z

o
m

-z

"oJJ
S

~
o
z

~TEXAS

INSTRUMENTS
9-12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C203, Ti'viS320C209, TivlS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

Table 3. Legend for C2xx Block Diagram
SYMBOL

DESCRIPTION

NAME

A Input

A input of the two operand CALU. A feeds ACC back to the CALU operations.

AOB

CALU Operation

Identifies the operation of A to B in the CALU. The 0 can be an arithmetic or logical operation as defined by
the operator selection for the current instruction.

ACC

Accumulator

32-bit register that stores the results and provides input for subsequent CALU operations. Also includes shift
and rotate capabilities.

ARAU

Auxiliary Register
Arithmetic Unit

An unsigned, 16-bit arithmetic unit used to calculate indirect addresses using the auxiliary registers as inputs
and outputs.

AUX
REGS

Auxiliary Register
0-7

These 16-bit registers are used as pOinters to anywhere within the data space address range. They are
operated upon by the ARAU and are selected by the ARP, auxiliary register pointer. ARO can also be used
as an index value for AR updates of more than one and as a compare value to AR(ARP).

B Input

B input of the two operand CALU. B feeds the 32-bit input (from ISCALE or PSCALE) to the CALU operations.

Bus Register
Signal

SR is asserted during access of the external global data memory space. READY is asserted to the device
when the global data memory is available forthe bus transaction. BR can be used to extend the data memory
address space by up to 32K words.

Carry

Register carry output from CALU. C is feed back into the CALU for extended arithmetic operation. The C bit
resides in ST1, status register 1 and can be tested in conditional instructions. C is also used in accumulator
shifts and rotates.

CALU

Central Arithmetic
Logic Unit

32-bit wide main arithmetic logic unit for the TMS320C2xx core. The CALU executes 32-bit operations in a
single machine cycle. CALU operates on data coming from ISCALE or PSCALE with data from ACC and
provides status results to PCTRL.

CNF

On-Chip RAM
Configuration
Control Bit

If set to 0, the reconfigurable data dual-access RAM blocks are mapped to data space; otherwise, they are
mapped to program space.

DRAB

Data Read
Address Bus

16-bit bus that provides the address for data read operations. DRAB is driven by the TMS320C2xx core.

a:
o
LL.

DRDB

Data-Read Bus

16-bit bus for data-space read data. DRDB is driven by memories or the logic interface.

DWAB

Data-Write Bus

16-bit bus that provides the address for data-write operations. DWAB is driven by the TMS320C2xx core.

DWEB

Data-Write Bus

16-bit bus for data-space write data. DWEB is driven by the TMS320C2xx core.

GREG

Global Memory
Allocation
Register

GREG specifies the size of the global data memory space.

IMR

Interrupt Mask
Register

IMR individually masks or enables the seven interrupts.

IFR

Interrupt Flag
Register

The 7-bit IFR indicates that the TMS320C2xx has latched an interrupt from one of the seven maskable
interrupts.

INTM

Interrupt Mode Bit

When set to 0, all unmasked interrupts are enabled. When set to 1, all maskable interrupts are disabled.

INT#

Interrupt Traps

A total of 32 interrupts via hardware and/or software are available.

ISCALE

Input Data-Scaling
Shifter

16 to 32-bit barrel left shifter. ISCALE shifts incoming 16-bit data t016 positions left relative to the 32-bit
output within the fetch cycle therefore not cycle overhead required for input scaling operations.

MPY

Multiplier

16 x 16-bit Multiplierto a 32-bit product. MPY executes multiplication in a single cycle. Operates either signed
or unsigned 2s complement arithmetic multiply.

MSTACK

Micro Stack

MSTACK provides temporary storage for the address of the next instruction to be fetched when program
address-generation logic is used to generate sequential addresses in data space.

MUX

Multiplexer

Multiplexes buses to a common input.

NPAR

Next Program
Address

NPAR holds the program address to be driven out PAB on the next cycle.

o
Z

~
C

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-13

OSCALE

32 to 16-bit barrel left shifter. OSCALE shifts the 32-bit accumulator output 0 to 7 bits left for quantization
management and outputs either the 16-bit high or low half of the shifted 32-bit data to DWEB.

PAB

Program Address
Bus

16-bit bus that provides the address for program space reads and writes. PAB is driven by the TMS320C2xx
core.

PAR

Program Address

PAR holds the address currently being driven on PAB for as many cycles as it takes to complete all memory
operations scheduled for the current machine cycle.

Program Counter

Increments the value from NPAR to provide sequential addresses for instruction fetching and sequential data
transfer operations.

PCTRL

Program
Controller

PCTRL decodes instruction, manages the pipeline, stores status, and decodes conditional operations.

Product Register
Shift Mode Bit

These two bits identify which of the four shift modes (0, 1,4, -6) will be used by PSCALE. PM resides in ST1.

PRDB

Program Read
Data Bus

16-bit bus for program space read data. PRDB is driven by the memories or the logic interface.

PREG

Product Register

32-bit register holds results of 16 x 16 multiply.

PSCALE

Product-Scaling
Shifter

0, 1 or 4-bit left shift or 6-bit right shift of multiplier product. The left shift options are used to manage the
additional sign bits resulting from the 2s complement multiply. The right shift option is used to scale down
the number to manage overflow of product accumulation in the CALU. PSCALE resides in tne path from the
32-bit product shifter and either the CALU or the DWEB and requires no cycle overhead.

TREG

Temporary
Register

16-bit register holds one of the operands for the multiply operations. TREG holds dynamic shift count for
LACT, ADDT, and SUBT instructions. TREG holds dynamic bit position for BITT instruction.

SSPCR

Synchronous
Serial Port Control
Register

Control register for selecting the mode of operation of the serial port.

SDTR

Synchronous
Serial Port
Transmit and
Receive Register

Data transmit and receive register.

TCR

Timer-Control
Register

TCR contains the control bits that define the divide-down ratio, start/stop the timer, and reload the period.
Also contained in TCR is the current count in the prescaler. Reset initializes the timer-divide-down ratio to
o and starts the timer.

PRD

Timer-Period
Register

PRD contains the 16-bit period that is loaded into the timer counter when the counter borrows or when the
reload bit is activated. Reset initializes the PRD to OxFFFF.

TIM

Timer-Counter
Register

TIM contains the current 16-bit count of the timer. Reset initializes the TIM to OxFFFF.

UART

Universal
Asynchronous
Receive Transmit

Asynchronous serial port.

ASPCR

Asynchronous
Serial Port Control
Register

ASPCR controls the asynchronous serial port operation.

10SR

I/O Status
Register

10SR detects current levels (and changes with inputs) on pins 100-103 and status of UART.

BRD

Baud Rate Divisor

Used to set the baud rate of the UART.

(")

-z

o
:xJ
s:

o
z

DESCRIPTION

NAME
Output
Data-Scaling
Shifter

•
TEXAS
INSTRUMENTS
9-14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiV1S320C203, TN1S320C209, TNiS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

Table 3. Legend for C2xx Block Diagram (Continued)
SYMBOL

NAME

DESCRIPTION

STO
ST1

Status Register

Contain the status of various conditions and modes. These registers can be stored into and loaded from data
memory, thus allowing the status of the machine to be saved and restored.

IMR

Interrupt Mask
Registers

IMR individually masks or enables the seven interrupts.

IFR

Interrupt Flag
Register

IFR indicates that the T320C2xLP core has latched an interrupt pulse from one of the maskable interrupts.

STACK

Stack

A block of memory used for storing return addresses for subroutines and interrupt service routines, or for
storing data. The 'C2xx stack is 16-bits wide and eight levels deep.

o
~
~

oIJ..
Z

o
Z

•

16-bit temporary register (TREG) that holds one of the operands for the multiplier, and

•

32-bit product register (PREG) that holds the product.

Four product shift modes (PM) are available at the PREG's output (PSCALE). These shift modes are useful for
performing multiply/accumulate operations, performing fractional arithmetic, or justifying fractional products.
The PM field of status register ST1 specifies the PM shift mode, as shown in Table 5.

Table 5. PSCALE Product Shift Modes

-z

"oJJ
S

SHIFT

no shift

DESCRIPTION
Product feed to CALU or data bus with no shift.

left 1

Removes the extra sign bit generated in a 2s-complement multiply to produce a 031 product.

left 4

Removes the extra 4 sign bits generated in a 16x13 2s-complement multiply to a produce a 031 product
when using the multiply by a 13-bit constant.

right 6

Scales the product to allow up to 128 product accumulation without the possibility of accumulator overflow.

The product can be shifted one bit to compensate for the extra sign bit gained in multiplying two 16-bit
2s-complement numbers (MPY). A four-bit shift is used in conjunction with the MPY instruction with a short
immediate value (13 bits or less) to eliminate the four extra sign bits gained in multiplying a 16-bit number by
a 13-bit number. Finally, the output of PREG can be right-shifted 6 bits to enable the execution of up to 128
consecutive multiply/accumulates without the possibility of overflow.

o
z

The LT (load TREG) instruction normally loads TREG to provide one operand (from the data bus), and the MPY
(multiply) instruction provides the section operand (also from the data bus). A multiplication can also be
performed with a 13-bit immediate operand when using the MPY instruction. A product is then obtained every
two cycles. When the code is executing multiple multiplies and product sums, the CPU supports the pipelining
of the TREG load operations with CALU operations using the previous product. These pipeline operations run
in parallel with loading the TREG include: load ACC with PREG (LTP); add PREG to ACC (LTA); add PREG to
ACC and shift TREG input data (DMOV) to next address in data memory (LTD); and subtract PREG from ACC
(LTS).
Two multiply/accumulate instructions (MAC and MAC D) fully utilize the computational bandwidth of the
multiplier, allowing both operands to be processed simultaneously. The data for these operations can be
transferred to the multiplier each cycle via the program and data buses. This facilitates single-cycle
multiply/accumulates when used with repeat (RPT) instruction. In these instructions, the coefficient addresses
are generated by program address generation (PAGEN), while the data addresses are generated by data
address generation (DAGEN). This allows the repeated instruction to sequentially access the values from the
coefficient table and step through the data in any of the indirect addressing modes.

"TEXAS
INSTRUMENTS
9-18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

multiplier (continued)
The MACD instruction, when repeated, supports filter constructs (weighted running averages) so that as the
sum-of-products is executed, the sample data is shifted in memory to make room for the next sample and to
throwaway the oldest sample.
The MPYU instruction performs an unsigned multiplication, which greatly facilitates extended-precision
arithmetic operations. The unsigned contents of TREG are multiplied by the unsigned contents of the addressed
data memory location, with the result placed in PREG. This allows the operands of greater than 16 bits to be
broken down into 16-bit words and processed separately to generate products of greater then 32-bits. The
SORA (square/add) and SORS (square/subtract) instructions pass the same value to both inputs of the
multiplier for squaring a data memory value.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into the 32-bit product register
(PREG). The product from PREG may be transferred to the CALU or to data memory via the SPH (store product
high) and SPL (store product low). Note: the transfer of PREG to either the CALU or data bus passes through
the PSCALE shifter and is therefore affected by product shift mode defined by PM. This is important when saving
PREG in an interrupt service routine context save as the PSCALE shift effects cannot be modeled in the restore
operation. PREG can be cleared by executing the MPY #0 instruction. The product register can be restored by
loading the saved low half into TREG and executing a MPY #1. The high half is then loaded using the LPH
instruction.
central arithmetic logic unit
The TMS320C2xx central arithmetic logic unit (CALU) implements a wide range of arithmetic and logical
functions, the majority of which execute in a single clock cycle. This ALU is referred to as central to differentiate
it from a second ALU used for indirect address generation called the ARAU. Once an operation is performed
in the CALU, the result is transferred to the accumulator (ACC) where additional operations, such as shifting,
may occur. Data that is input to the CALU may be scaled by ISCALE when coming from one of the data buses
(DRDB or PRDB) or scaled by PSCALE when coming from the multiplier.
The CALU is a general-purpose arithmetic/logic unit that operates on 16-bit words taken from data memory or
derived from immediate instructions. In addition to the usual arithmetic instructions, the CALU can perform
Boolean operations, facilitating the bit manipulation ability required for a high-speed controller. One input to the
CALU is always provided from the accumulator, and the other input may be provided from the Product Register
(PREG) of the multiplier or the output of the scaling shifter (that has been read from data memory or from the
ACC). After the CALU has performed the arithmetic or logical operation, the result is stored in the accumulator.
The TMS320C2xx supports floating-point operations for applications requiring a large dynamic range. The
NORM (normalization) instruction is used to normalize fixed-point numbers contained in the accumulator by
performing left shifts. The four bits of the TREG define a variable shift through the scaling shifter for the
LACT/ADDT/SUBT (load/add to /subtract from accumulator with shift specified by TREG) instructions. These
instructions are useful in floating-point arithmetic where a number needs to be de normalized, i.e., floating-point
to fixed-point conversion. They are also useful in execution of an automatic gain control (AGC) going into a filter.
The BITT (bit test) instruction provides testing of a single bit of a word in data memory based on the value
contained in the four LSB's of TREG.
The CALU overflow saturation mode may be enabled/disabled by setting/resetting the OVM bit of STO. When
the CALU is in the overflow saturation mode and an overflow occurs, the overflow flag is set and the accumulator
is loaded with either the most positive or the most negative value representable in the accumulator, depending
upon the direction of the overflow. The value of the accumulator upon saturation is 07FFFFFFFh (positive) or
080000000h (negative). If the OVM (overflow mode) status register bit is reset and an overflow occurs, the
overflowed results are loaded into the accumulator with modification. (Note that logical operations cannot result
in overflow.)

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

9-19

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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

central arithmetic logic unit (continued)
The CALU can execute a variety of branch instructions that depend on the status of the CALU and accumulator.
These instructions can be conditionally executed based on any meaningful combination of these status bits.
For overflow management these conditions include the OV (branch on overflow) and EQ (branch on
accumulator equal to zero). In addition, the BACC (branch to address in accumulator) instruction provides the
ability to branch to an address specified by the accumulator (computed goto). Bit test instructions (BIT and
BITT), which do not affect the accumulator, allow the testing of a specified bit of a word in data memory.
The CALU also has an associated carry bit that is set or reset depending on various operations within the device.
The carry bit allows more efficient computation of extended-precision products and additions or subtractions.
It is also useful in overflow management. The carry bit is affected by most arithmetic instructions as well as the
single-bit shift and rotate instructions. It is not affected by loading the accumulator, logical operations, or other
such non-arithmetic or control instructions.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumulator with borrow) instructions
provided use the previous value of carry in their addition/subtraction operation.
The one exception to operation of the carry bit is in the use of ADD with a shift count of 16 (add to high
accumulator) and SUB with a shift count of 16 (subtract from high accumulator) instructions. This case of the
ADD instruction can set the carry bit only if a carry is generated, and this case of the SUB instruction can reset
the carry bit only if a borrow is generated; otherwise, neither instruction affects it.

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-z

Two conditional operands, C and NC, are provided for branching, calling, returning, and conditionally executing
based upon the status of the carry bit. The SETC, CLRC, and LST #1 instructions also can be used to load the
carry bit. The carry bit is set to one on a hardware reset.

accumulator
The 32-bit accumulator is the registered output of the CALU. It can be split into two 16-bit segments for storage
in data memory. Shifters at the output of the accumulator provide a left-shift of 0 to 7 places. This shift is
performed while the data is being transferred to the data bus for storage. The contents of the accumulator
remain unchanged. When the post-scaling shifter is used on the high word of the accumulator (bits 16-31), the
MSB's are lost and the LSB's are filled with bits shifted in from the low word (bits 0-15). When the post-scaling
shifter is used on the low word, the LSB's are zero filled.

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s:
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The SFL and SFR (in-place one-bit shift to the left/right) instructions and the ROL and ROR (rotate to the
left/right) instructions implement shifting or rotating of the contents of the accumulator through the carry bit. The
SXM bit affects the definition of the SFR (shift accumulator right) instruction. When SXM=1 , SFR performs an
arithmetic right shift, maintaining the sign of the accumulator data. When SXM=O, SFR performs a logical shift,
shifting out the LSBs and shifting in a zero forthe MSB. The SFL (shift accumulator left) instruction is not affected
by the SXM bit and behaves the same in both cases, shifting out the MSB and shifting in a zero. Repeat (RPT)
instructions may be used with the shift and rotate instructions fm multiple-bit shifts.

o
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auxiliary registers and auxiliary-register arithmetic unit (ARAU)
The 'C2xx provides a register file containing eight auxiliary registers (ARO-AR7). The auxiliary registers are
used for indirect addressing of the data memory or for temporary data storage. Indirect auxiliary-register
addressing allows placement of the data memory address of an instruction operand into one of the auxiliary
registers. These registers are referenced with a 3-bit auxiliary register pointer (ARP) that is loaded with a value
from 0 through 7, designating ARO through AR7, respectively. The auxiliary registers and the ARP can be loaded
from data memory, the ACC, the product register, or by an immediate operand defined in the instruction. The
contents of these registers can also be stored in data memory or used as inputs to the central arithmetic logic
unit (CALU).

~TEXAS

9-20

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiVlS320C203, TiVlS320C209, TiVlS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

auxiliary registers and auxiliary-register arithmetic unit (ARAU) (continued)
The auxiliary register file (ARO-AR7) is connected to the auxiliary register arithmetic unit (ARAU). The ARAU
can autoindex the current auxiliary register while the data memory location is being addressed. Indexing either
by ±1 or by the contents of the ARO register can be performed. As a result, accessing tables of information does
not require the CALU for address manipulation; thus, the CALU is free for other operations in parallel.

memory
The 'C2xx implements three separate address spaces for program memory, data memory, and 1/0. Each space
accommodates a total of 64K 16-bit words. Within the 64K words of data space, the 256 to 32K words at the
top of the address range can be defined to be external global memory in increments of powers of two, as
specified by the contents of the global memory allocation register (GREG). Access to global memory is
arbitrated using the global memory bus request (BR) signal.
On the 'C2xx, the first 96 (0-5Fh) data memory locations are allocated for memory-mapped registers or
reseNed. This memory-mapped register space contains various control and status registers including those for
the CPU.
TMS320C209 (only)
The mask-programmable ROM is located in program memory space. Customers can arrange to have this ROM
programmed with contents unique to to any particular application. The ROM is enabled or disabled by the state
of the MP/MC control input upon resetting the device. The ROM occupies the lowest block of program memory
when enabled. When disabled, these addresses are located in the device's external program memory space.
The 'C209 devices provide two types of RAM: single-access RAM (SARAM) and dual-access RAM (DARAM).
The single-access RAM requires a full machine cycle to perform a read or a write. However, this is not one large
RAM block in which only one access per cycle is allowed. It is made up of 2K-word size-independent RAM blocks
and each one allows one CPU access per cycle. The CPU can read or write one block while accessing another
block at the same time. The 'C209 processor supports multiple accesses to its SARAM in one cycle as long as
they go to different RAM blocks. With an understanding of this structure, code and data can be appropriately
arranged to improve code performance.
The 'C2xx dual-access RAM (DARAM) allows writes to and reads from the RAM in the same cycle without the
address restrictions of the SARAM. The dual-access RAM is configured in three blocks: block 0 (BO), block 1
(B1), and block 2 (B2). Block 1 is 256 words in data memory and block 2 is 32 words in data memory. Block 0
is a 256-word block which can be configured as data or program memory. The SETC CNF (Configure BO as
data memory) and CLRC CNF (Configure BO as program memory) instructions allow dynamic configuration of
the memory maps through software. When using Block 0 as program memory, instructions can be downloaded
from external program memory into on-chip RAM and then executed.
TMS320C203 (only)
When using on-chip RAM, or high-speed external memory, the 'C2xx runs at full speed with no wait states. The
ability of the DARAM to allow two accesses to be performed in one cycle coupled with the parallel nature of the
'C2xx architecture enables the device to perform three concurrent memory accesses in any given machine
cycle. Externally, the READY line can be used to interface the 'C2xx to slower, less expensive external memory.
Downloading programs from slow off-chip memory to on-chip RAM can speed processing while cutting system
costs.

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-21

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NAME

DESCRIPTION

PSWS

External program-space wait state on. When active, PSWS = 1 applies one wait state to all reads to off-chip
program space (writes always take at least two cycles regardless of PSWS or READY). The memory cycle can
be further extended using the READY signal. However, the READY signal does not override the wait state
generated by PSWS. This bit is set to 1 (active) by reset (RS or RS).

DSWS

External data-space wait state on. When active, DSWS = 1 applies one wait state to all reads to off-chip data
space (writes always take at least two cycles regardless of DSWS or READY). The memory cycle can be further
extended using the READY signal. However, the READY signal does not override the wait state generated by
DSWS. This bit is set to 1 (active) by reset (RS or RS).

ISWS

AVIS

External input-/output-space wait state on. When active, ISWS = 1 applies one wait state to all reads to off-chip
110 space (write always takes at least two cycles regardless of ISWS or READY). The memory cycle can be further extended using the READY signal. However, the READY signal does not override the wait state generated
by ISWS. This bit is set to 1 (active) by reset (RS or RS).
Address visibility. When active high, AVIS presents the internal program address out of the logic-interface
address bus if the bus is not currently used in an external memory operation. The internal address is presented
to provide a trace mechanism of internal code operation. Therefore, the memory-control signals are not active.
AVIS is set to 1 (active) by reset (RS or RS). AVIS should be deactivated in production systems to reduce system
power and noise.

TMS320C203

The software wait-state generator can be programmed to generate between 0 and seven wait states for a given
space. The WSGR has 12 bits: three DATA, six PROGRAM, and three 1/0. The wait state generator inserts a
wait state(s) to a given memory space based on the value of the three bits, regardless of the condition of the
READY signal. The READY signal can be used to extend wait state further. All bits are set to 1 at reset so that
the device can operate from slow memory from reset. The WSGR register (shown in Figure 5 and
Table 13 and Table 14) resides at I/O port OxFFFF.

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15-12

:s::

Reserved

ISWS

DSWS

PSUWS

PSLWS

Figure 5. TMS320C203 Wait-State Generator Control Register (WSGR)

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Table 13. TMS320C203 Wait-State(s) Programming
BITS 11, 8, 5, 2

BITS 10, 7, 4,1

BITS 9, 6, 3, 0

WAIT-STATES FOR PROGRAM, DATA, AND 110

2
3

~TEXAS

INSTRUMENTS
9-30

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiViS320C203, TiV1S320C209, TiViS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

TMS320C203 (continued)
Table 14. 'C203 Wait-State Generator Control Register (WSGR)
NAME

DESCRIPTION

2-0

PSLWS

External program-space wait states (lower). PSLWS determines that between 0, ... ,7 wait states are applied to
all reads and writes to off-chip lower program space address (Oh-7FFFh). The memory cycle can be further
extended using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset, (RS).

5-3

PSUWS

External program-space wait states (upper). PSUWS determines that between 0, ... ,7 wait states are applied
to all reads and writes to off-chip upper program space address (8000h-OFFFFh). The memory cycle can be further extended using the READY signal. The READY signal does not override the wait states generated by PSWS.
These bits are set to 1 (active) by reset, (RS).

8-6

DSWS

External data space wait states. DSWS determines that between 0, ... ,7 wait states are applied to all reads and
writes to off-chip data space. The memory cycle can be further extended using the READY signal. The READY
signal does not override the wait states generated by DSWS. These bits are set to 1 (active) by reset, (RS).

11-9

ISWS

External input loutput-space wait state. DSWS determines that between 0,. .. ,7 wait states are applied to all
reads to all reads and writes to off-chip liD space. The memory cycle can be further extended using the READY
signal. The READY signal does not override the wait states generated by ISWS. These bits are set to 1 (active)
by reset, (RS).

15-12

BITS

Don't care.

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timer
The 'C2xx features a 16-bit timing circuit with a 4-bit prescaler. This timer clocks between one-half and one
thirty-second the machine rate of the device itself, depending upon the programmable timer's divide-down ratio.
This timer can be stopped, restarted, reset, or disabled by specific status bits.
The timer can be used to generate CPU interrupts periodically. The timer is decremented by one at every
CLKOUT1 cycle. A timer interrupt (TINT) and a pulse equal to the duration of a CLKOUT1 cycle on the external
TOUT pin are generated each time the counter decrements to zero. The timer thus provides a convenient means
of performing periodic 1/0 or other functions.

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TMS320C209 input clock options
The TMS320C209 includes two clock options. The first option (+2) operates the CPU at half the input clock rate.
The second option (x2) doubles the input clock and phase locks the output clock with the input clock. The +2
mode is enabled by tying the CLKMOD pin low. The x2 mode is enabled by tying the CLKMOD pin high.
The clock doubler option of the 'C209 uses an internal phase lock loop (PLL). The PLL requires approximately
1000 cycles to lock. The rising edge of RS (or falling edge of RS) must be delayed until at least three cycles
after the PLL has stabilized. Likewise, the modes cannot be dynamically switched because the internal clock
generator can generate minimal clock pulse with violations. The RS or RS signals should be in their active state
if the CLKMOD pin is changed.

TMS320C203 input clock options
The TMS320C203 provides multiple clock modes of: +2, x 1, x2, x4. The clock mode configuration cannot be
dynamically changed without executing another reset. The operation of the PLL circuit is affected by the
operating voltage of the device. If the device is operating at 5 V then the PLL5V signal should be tied high. For
3 V operation, PLL5V should be tied low.

"TEXAS
INSTRUMENTS
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9-31

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

synchronous serial port (TMS320C203 only)
A full duplex (bidirectional 16 bit on-chip synchronous serial port provides direct communication with serial
devices such as codecs, serial A/D (analog to digital) converters, and other serial systems. The interface signals
are compatible with codecs and many other serial devices. The serial port can also be used for
intercommunication between processors in multiprocessing applications.
Both receive and transmit operations have a four deep first in first out (FIFO). The advantage of having a FIFO
is a to alleviate the CPU from being loaded with the task of servicing a transmit or receive data on every interrupt,
allowing a continuous communications stream of 16-bit data packets. The continuous mode provides operation
that once initiated requires no further frame synchronization pulses when transmitting at maximum packet
frequency. The maximum transmission rate for both transmit and receive operations is CPU divided by two or
'CLKOUT1 (frequency)/2. Therefore, the maximum rate at 25 ns is 20 Mbitls and 14.28 Mbitls at 35 ns. The serial
port is fully static and functions arbitrarily at low clocking frequencies. When the serial ports are in reset the
device can be configured to shut off the serial port internal clocks, allowing the device to run in a lower power
mode of operation.
Three signals are necessary to connect the transmit pins of the transmitting device with the receive pins of the
receiving device for data transmission. The transmitted serial data signal (OX) sends the actual data. The
transmit frame synchronization signal (FSX) initiates the transfer (at the beginning of the packet), and the
transmit clock signal (CU
C

The repeat counter (RPTC) is loaded with the addressed data memory location if direct or indirect addressing
is used, an a-bit immediate value if short immediate addressing is used. The RPTC register is loaded by the
RPT instruction. This results in a maximum of N + 1 executions of a given instruction. RPTC is cleared by reset.
Once a repeat instruction (RPT) is decoded, all interrupts including NMI (except reset) are masked until the
completion of the repeat loop. However, the device responds to the HOLD signal while executing an RPT loop.

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instruction set summary
This section summarizes the opcodes of the instruction set for the 'C2xx digital signal processors. This
instruction set is a superset of the 'C1 x and 'C2x instruction sets. The instructions are arranged according to
function and are alphabetized by mnemonic within each category. The symbols in Table a are used in the
instruction set opcode table (Table 16). T he Texas Instruments 'C2xx assembler accepts 'C2x instructions.

:IJ

The number of words that an instruction occupies in program memory is specified in column 3 of Table 16.
Several instructions specify two values separated by a slash mark (I) for the number of words. In these cases,
different forms of the instruction occupy a different number of words. For example, the ADD instruction occupies
one word when the operand is a short immediate value or two words if the operand is a long immediate value.

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The number of cycles that an instruction requires to execute is in column 3 of Table 16. All instructions are
assumed to be executed from internal program memory (RAM) and internal data dual-access memory. The
cycle timings are for single-instruction execution, not for repeat mode.

~TEXAS

9-34

INSTRUMENTS
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

Table 15. Opcode Symbols
SYMBOL

DESCRIPTION

Address

ACC

Accumulator

ACCB

Accumulator buffer

ARX

Auxiliary register value (0-7)

BITX

4-bit field specifies which bit to test for the BIT instruction

BMAR

Block-move address register

DBMR

Dynamic bit-manipulation register

Addressing-mode bit

11 ... 11

Immediate operand value

INTM

Interrupt-mode flag bit

INTR#

Interrupt vector number

Field for the XC instruction, indicating the number of instructions (one or two) to execute conditionally

PREG

Product register

PROG

Program memory

RPTC

Repeat counter

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SHF, SHFT

3/4 bit shift value

Test-control bit

Two bits used by the conditional execution instructions to represent the conditions TC, NTC, and BIO.
TP
Meaning
BIOlow
00
01
TC=1
10
TC=O
11
None of the above conditions

TREGn

Temporary register n (n = 0, 1, or 2)

ZLVC

4-bit field representing the following conditions:
Z:
ACC=O
L:
ACC 0

2/4/2

Branch on I/O status low

2/4/3

Branch if accumulator ~ 0

2/4/2

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MSB

ADDC

~
Z
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Absolute value of accumulator

OPCODE

WORDS!
CYCLES

ADD

:t:-

DESCRIPTION

BCND

1011

1111
1011
SHFT
16-Bit Constant

1011

1110
1000
16-Bit Constant

1011

1110

0000

0001
0100

0111

1001
IADD RESS
Branch Address

1011

1110
0010
Branch Address

0111

1011
IADD RESS
Branch Address

1110

0001
0000
Branch Address

0000

1110

0010
0000
Branch Address

0000

1110

0011
0001
Branch Address

0001

1110

0011
1000
Branch Address

1100

1110

0011
0000
Branch Address

0100

1110

0000
0000
Branch Address

0000

1110

0011
1100
Branch Address

1100

0000

BIT

Test bit

1/1

0100

BITx

IADD

RESS

BITT

Test bit specified by TREG

1/1

0110

1111

IADD

RESS

Block move from data memory to data memory source immediate

2/3

Block move from data memory to data memory destination immediate

2/3

Block move from program memory to data memory

2/3

1010

1000 IADD RESS
Branch Address

1010

1001
IADD RESS
Branch Address

111

0011
IADD RESS
Branch Address

BLDD

BLPD

~TEXAS

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DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

Table 16. TMS320C2xx Instruction Set Summary (Continued)
C2xx
MNEMONIC

DESCRIPTION

WORDSI
CYCLES

Branch if accumulator < 0

2/4/2

Branch on no carry

2/4/2

Branch if no overflow

2/4/2

Branch if accumulator 7c- 0

2/4/2

Branch on overflow

2/4/2

Branch if accumulator = 0

2/4/2

OPCODE
MSB

LSB

1110

0011
0100
Branch Address

0100

1100

0011
0000
Branch Address

0001

1110

0011
0000
Branch Address

0010

1110

0011
0000
Branch Address

1000

1110

0011
0010
Branch Address

0010

1110

0011
1000
Branch Address

1000

BCND

CALA

Call subroutine indirect

1/4

CALL

Call subroutine

2/4

Conditional call subroutine

2/4/2

CMPL

Complement accumulator

1/1

1011

1110

0000

0001

CMPR

Compare auxiliary register with auxiliary register ARO

1/1

1011

1111

0100

01CM

CLRC

Configure block as data memory

1 11

1011

1110

0100

Configure block as program memory

1 11

1011

1110

0100

0101

Disable interrupt

1 11

1011

1110

0100

0001

SETC

1011

1110

0011

0000

0111

1010 1ADD RESS
Routine Address

1110

10TP ZLVC ZLVC
Routine Address

DMOV

Data move in data memory

1 11

0111

IADD

RESS

CLRC

Enable interrupt

1 11

1011

1110

0100

0000

IDLE

Idle until interrupt

111

Input data from port

2/2

1011

1110

0010

1010

1111

IADD

RESS

16BIT

1/0

PORT

ADR
S

INTR

Software interrupt

1/4

1011

1110

0111

LACC

Load accumulator with shift

1 11

0001

SHFT

1ADD

RESS

LACL

Load accumulator immediate short

1/1

1011

1001

8BIT

CNST

LACT

Load accumulator with shift specified by T register

1/1

0110

1011

IADD

RESS

LACC

Load accumulator long immediate with shift

LAR

2/2

1011

1111
1000 SHFT
16-Bit Constant

Load auxiliary register

1/2

0000

OARx

IADD

RESS

Load auxiliary register short immediate

1/2

1011

OARx

8BIT

CNST

MAR

Load auxiliary register pOinter

1 11

1000

1011

1000

1ARx

LDP

Load data-memory page pOinter

1/2

0000

1101

IADD

RESS

LDP

Load data-memory page pointer immediate

1/2

1011

110P

LPH

Load high-P register

1 11

0111

0101

LAR
LST

1011

AGE

P
IADD

1111
0000
16-Bit Constant

OINT
RESS
1ARx

Load auxiliary register long immediate

2/2

Load status register STO

1/2

0000

1110

IADD

RESS

Load status register ST1

1/2

0000

1111

IADD

RESS

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-37

o
~
~

o
LL
Z

(.)

o
m
z

o
:IJ
s:

~
oz

CLRC

RPT

~TEXAS

INSTRUMENTS
9-38

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

RESS
ADRS

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

Table 16. TMS320C2xx Instruction Set Summary (Continued)
C2xx
MNEMONIC

OPCODE

WORDSI
CYCLES

MSB

Store low accumulator with shift

1/1

1001

OSHF

IADD

SAR

Store auxiliary register

1/1

1000

OARx

IADD

RESS

SBRK

Subtract from auxiliary register short immediate

1/1

0111

1100

8BIT

CNST

SETC

Set carry bit

1/1

1011

1110

0100

1111

SFL

Shift accumulator left

1/1

1011

1110

0000

1001

SFR

Shift accumulator right

1/1

1011

1110

0000

1010

SETC

Set overflow mode

1/1

1011

1110

0100

0011

SPAC

Subtract P register from accumulator

1/1

1011

1110

0000

0101

SPH

Store high-P register

1/1

1000

1101

IADD

RESS

SPL

Store low-P register

1/1

1000

1100

IADD

RESS

SPM

Set P register output shift mode

1/1

1011

1111

IADD

RESS

SORA

Square and accumulate

1/1

0101

0010

IADD

RESS

SACL

DESCRIPTION

LSB
RESS

SORS

Square and subtract previous product from accumulator

1/1

0101

0011

IADD

RESS

SST

Store status register STO

1/1

1000

1110

IADD

RESS

SST

Store status register ST1

1/1

1111

IADD

RESS

1000
1010

1110
IADD
16-Bit Constant

RESS

SPLK

Store long immediate to data memory

2/2

SSXM

Set sign-extension mode

1/1

1011

1110

0100

0111

SETC

Set test! control flag

1/1

1011

1110

0100

1011

Subtract from accumulator long immediate with shift

2/2

Subtract from accumulator with shift

SUB

1011

1111
1010
16-Bit Constant

SHFT

1/1

0011

SHFT

IADD

RESS

Subtract from high accumulator

1/1

0110

0101

IADD

RESS

Subtract from accumulator short immediate

1/1

1011

1010

8BIT

CNST

SUBB

Subtract from accumulator with borrow

1/1

0110

0100

IADD

RESS

SUBC

Conditional subtract

1/1

0000

1010

IADD

RESS

SUBS

Subtract from low accumulator with sign extension suppressed

1/1

0110

IADD

RESS

SUBT

Subtract from accumulator with shift specified by TREG

1/1

0110

0111

IADD

RESS

SETC

Set external flag

1/1

1010

0110

IADD

RESS

TBLR

Table read

1/3

1010

0111

IADD

RESS

TBLW

Table write

1/3

1011

1110

0101

0001

TRAP

Software interrupt

1/4

1011

1110

0101

0001

Exclusive-OR with accumulator

1/1

0110

1100

IADD

RESS

Exclusive-OR immediate with accumulator with shift

2/2

Exclusive-OR immediate with accumulator with shift of 16

2/2

XOR

LACL

ZALR

1011

1111
1101
16-Bit Constant

SHFT

1011

1110
1000
16-Bit Constant

0011

Zero accumulator

1/1

1011

1001

0000

Zero low accumulator and load high accumulator

1/1

0110

1010

IADD

RESS

Zero low accumulator and load low accumulator with no sign extension

1/1

0110

1001

IADD

RESS

Zero low accumulator and load high accumulator with rounding

1/1

0110

1000

IADD

RESS

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-39

z
o

o
LL
Z
W

o
Z

~
Z

o
m

. See Table 17 for complete listings of development support tools for the 'C2xx. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.

-z

Table 17. TMS320C2xx Development Support Tools

'"T1

DEVELOPMENT TOOL

o
z

PLATFORM

PART NUMBER

Software
Compiler/Assembler/Linker

SPARC

TMDS3242555-08

Compiler/Assembler/Linker

PC-DOSTM

TMDS3242855-02

PC-DOS, OS/2TM

TMDS3242850-02

Assembler/Linker
Simulator

PC-DOS, WIN

TMDS3245851-02

Simulator

SPARC

TMDS3245551-01
DFDP

Digital Filter Design Package

PC-DOS

Debugger/Emulation Software

PC-DOS, OS/2, WIN

TMDS3240120

SPARCTM

TMDS3240620

Debugger/Emulation Software

Hardware
XDS-510 XL Emulator

PC-DOS, OS/2

XDS-510 WS Emulator

SPARC

SPARC is a trademark of SPARC International, Inc.
PC-DOS and OS/2 are trademarks of International Business Machines Corp.
XDS is a trademark of Texas Instruments Incorporated.

~TEXAS

INSTRUMENTS
9-40

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMDS00510
TMDS00510WS

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

device and development support tool nomenclature

To designate the stages in the product development cycle, Texas Instruments assigns prefixes to the part
numbers of all TMS320 devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP,
and TMS. Texas Instruments recommends two of three possible prefix designators for its support tools: TMDX
and TMDS. These prefixes represent evolutionary stages of product development from engineering prototypes
(TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). This development flow is defined
below.
Device Development Evolutionary Flow:
TMX

Experimental device that is not necessarily representative of the final device's electrical
specifications.

TMP

Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.

TMS

Fully-qualified production device

z
o

Support Tool Development Evolutionary Flow:
TMDX

Development support product that has not yet completed Texas Instruments internal qualification
testing.

TMDS

Fully qualified development support product

TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:

!i:E
a:
o
u.
Z

"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development support tools have been fully characterized, and the quality and reliability
of the device has been fully demonstrated. Texas Instruments standard warranty applies.
Predictions show that prototype devices (TMX or TMP) will have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate is still undefined. Only qualified production devices are to be used.

o
Z

~
c

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-41

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

device and development support tool nomenclature (continued)

TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, N, FN, or GB) and temperature range (for example, L). The following figures provide a legend for
reading the complete device name for any TMS320 family member.
TMS 320 (B) C 52 PJ
PREFIX
TMX =
TMP=
TMS=
SMJ =
SM =

I
experimental device
prototype device
qualified device
MIL-STD-883C
High Rei (non-883C)

DEVICE FAMILY
320 = TMS320 Family

BOOT LOADER OPTION

--------I

TECHNOLOGY'------------~

C
E
LC
VC

CMOS
CMOS EPROM
Low-Voltage CMOS (3.3 V)
Low Voltage CMOS (3 V)

(L)

TEMPERATURE RANGE (DEFAULT: 0 TO 70°C)
H = 0 to 50°C
L = 0 to 70°C
S = -55 to 100°C
.
M = -55 to 125°C
A = -40 to 85°C

PACKAGE TYPE
N
plastic DIP
J
ceramic CER-DIP
JD
ceramic DIP side-brazed
GB
ceramic PGA
FZ
ceramic CER-OUAD
FN
plastic leaded CC
FD
ceramic leadless CC
PJ
100-pin plastic EIAJ OFP
PO
132-pin plastic bumpered OFP
PZ
1OO-pin plastic TOFP
PN
80-pin TOFP
DEVICE
'C1x DSP:
10
14
15
16
17
'C2x DSP:
25

o
m

-z

":xJ
o

'C2xx DSP
209
203
'C3x DSP:
30
31
32
'C4x DSP:
40
44
'C5x DSP:
50
51
52
53

s.:
~

o
z

56
57

Figure 6. TMS320 Device Nomenclature

•
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ti'V1S320C203, TMS320C209, TiVlS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025-JUNE 1995

device and development support tool nomenclature (continued)
TMDS 32 4 28 1

TMDX
TMDS =

32 =

-0 2
MEDIUMt

prototype
qualified

DEVICE FAMILY

QUALIFICATION STATUSJ

2 = 5.25-inch floppy disk
8 = 1600 BPI magnetic tape

-----I

SIWFORMATt

o =
1 =

TMS320 family

PRODUCT T Y P E - - - - - - - I
4
6
8

SEQUENCE NUMBERI:

software
hardware
upgrade

MODEL*----------------~
11 = XDS/11
22 = XDS/22
88 = upgrade kits

OPERATING SYSTEMt - - - - - - - - - I

08
25 =
28 =
38
48 =
55
58 =

=
=

object code
source code

GENERATION*
1
'C1x

3
4
5
1....-_ _ _

'C1x IBM MS/PC-DOS
'C2x1'C2xxl'C5x SPARC
'C2x or 'C1x1'C2x1'C2xxl'C5x IBM MS/PC-DOS
'C3x IBM MS/PC-DOS
'C4x IBM MS/PC-DOS
'C5x or 'C2xxl'C5x SPARC
'C5x or 'C2xxl'C5x IBM MS/PC-DOS

'C2x or 'C2xx
'C3x
'C4x
'C5x or 'C5xl C2xx

FORMATt
1
5

=
=

TI-tagged
COFF

11.

Software only

+Hardware only

Figure 7. TMS320 Development Tool Nomenclature

()

documentation support
Extensive documentation supports all of the TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include data sheets, such as this
document, with design specifications, complete user's guides for all devices and development support tools,
and three volumes of the publication Digital Signal Processing Applications with the TMS320 Family.
The application book series describes hardware and software applications, including algorithms, for fixed and
floating point TMS320 family devices. The TMS320C2xx User's Guide, which describes in detail the
2xx-generation TMS320 products, is also currently available.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board
service (BBS) provides access to a wealth of information pertaining to the TMS320 family, including
documentation and source and object code for many DSP algorithms and utilities. The BBS can be reached
at 713/274-2323.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-43

-z

MIN

NOM

MAX

4.5

5.5

ClKIN

RS,ClKR,ClKX,RX,DR
(203 only)

All others

2
-0.3

RS,ClKR,ClKX,RX,DR
(203 only)

UNIT
V
V

ClKIN

o
m

TEST CONDITIONS

VDD + 0.3
V
VDD + 0.3

0.7
0.8

Vil

low-level input voltage

IOH

High-level output current

-300

J.lA

IOl

low-level output current

rnA

Case temperature

°C

All others

o
z

~TEXAS

9-44

-0.3

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.8

Tiv1S320C203, TivlS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSORS
SPRS025 - JUNE 1995

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
('320~C2xx only)t
Supply voltage range, VDD (see Note 2) ............................................. - 0.3 V to 5 V
Input voltage range ............................................................... - 0.3 V to 5 V
Output voltage range .............................................................. - 0.3 V to 5 V
Operating free-air temperature range, TA .............................................. O°C to 70°C
Storage temperature range, Tstg ................................................. - 55°C to 150°C

TMS320VC2xx recommended operating conditions
PARAMETER
VDD

Supply voltage

VSS

Supply voltage

TEST CONDITIONS

High-level input voltage

RS,ClKR,ClKX,RX,DR
(203 only)
All others
ClKIN

Vil

low-level input voltage

NOM

MAX

2.7

3.3

1.8

RS,ClKR,ClKX, RX,DR
(203 only)
All others

V
VDD + 0.3

0.5
0.2 VDD

-0.3

VDD +0.3

0.7 VDD

-0.3

UNIT

0
ClKIN

VIH

MIN

0.6

IOH

High-level output current

-300

Il A

IOl

low-level output current

rnA

Case temperature

°c

!i:2:
a:

o
L1.
Z
W

o
Z

--"VV\rO---;-----() Under

Test

Where:

IOL
IOH
VLOAD
CT

2 rnA (all outputs)
400 JlA (all outputs)
1.5V
60-pF typical load-circuit capacitance

Figure 8. Test Load Circuit

signal-transition levels
The data in this section is shown for both the 5-V version ('C2xx) and the 3.0-V version ('VC2xx). In each case,
the 5-V data is shown followed by the 3-V data in parentheses. TTL-output levels are driven to a minimum
logic-high level of 2.4 V (2 V) and to a maximum logic-low level of 0.6 V (0.4 V). Figure 9 shows the TTL-level
outputs.

o
~
~

[[

o
L1.
Z

()

Figure 9. TTL-Level Outputs

TTL-output transition times are specified as follows:
•

For a high-to-Iow transition, the level at which the output is said to be no longer high is 2 V (1.8 V) and the
level at which the output is said to be low is 1 V (0.8 V).

•

For a low-to-high transition, the level at which the output is said to be no longer low is 1 V (0.8 V) and the
level at which the output is said to be high is 2 V (1.6 V).

Figure 10 shows the TTL-level inputs.
r-------------------------------------~

==~-l~~----C------------~--~~~ :.~~9(:::.)
Figure 10. TTL-Level Inputs
TTL-compatible input transition times are specified as follows:
•

For a high-to-Iow transition on an input signal, the level at which the input is said to be no longer high is
2 V (1.8 V) and the level at which the input is said to be low is 0.8 V (0.4 V).

•

For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V (0.4 V) and the level at which the input is said to be high is 2 V (1.8 V) .

•
TEXAS
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9-47

internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-halfthe crystal's oscillating frequency. The crystal should be in either fundamental or overtone operation
and parallel resonant, with an effective series resistance of 30 ohms and a power dissipation of 1 mW; it should
be specified at a load capacitance of 20 pF. Note that overtone crystals require an additional tuned-LC circuit.
Figure 11 shows an external crystal (fundamental frequency) connected to the on-chip oscillator.

o
m
-z

TMS320C2xx timing at Vpp

=5 V with the PLL circuit disabled, divide-by-two mode
TEST CONDITIONS

MIN

NOM

o
s:

:IJ

~
oz

MAX

UNIT

80
fx

Input clock frequency

=0° C to 85° C

57.14

MHz

40.96
C1, C2 Load capacitance

t This device utilizes a fully static design and, therefore,

can operate with input clock cycle time (tc(CI)) approaching infinity. The device is
characterized at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements.

X2/CLKIN
Crystal

----101---....
Figure 11. Internal Clock Option

~TEXAS

.
INSTRUMENTS
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TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025-JUNE 1995

TMS320C2xx timing at Voo

=5 V with the PLL circuit disabled, divide-by-two mode (continued)

TMS320C2xx switching characteristics over recommended operating conditions [H
PARAMETER

'320C2XX-40
MIN

TYP

48.8

2tc (CI)

'320C2XX-S7
MAX

MIN

TYP

MAX

MIN

TYP

tc(CO)

Cycle time, ClKOUT1

td(CIH-CO)

Delay time, ClKIN high to
ClKOUT1 high/low

tf(CO)

Fall time, ClKOUT1

tr(CO)

Rise time, ClKOUT1

tw(COl)

Pulse duration, ClKOUT1 low

H-2

H+2

H-2

tw(COH)

Pulse duration, ClKOUT1 high

H-2

H+2

H-2

2tc (CI)
11

t This device is implemented in static logic and therefore can operate with tc(CI) approaching
approaching 0 Hz, but is tested at tc(CI) =300 ns to meet device test time requirements.

00.

=0.5 tc(co)l

'320C2XX-80

2tc (CI)

MAX

UNIT

ns
ns
ns

H+2

H-2

H+2

H +2

H-2

H+2

The device is characterized at frequencies

TMS320C2xx timing requirements over recommended operating conditions
'320C2XX-40

'320C2XX-S7

'320C2XX-80

MIN

MAX

MIN

MAX

MIN

17.5

12.5

MAX

UNIT

tc(CI)

Cycle time, ClKIN

tf(CI)

Fall time, ClKIN

tr(CI)

Rise time, ClKIN

tw(Cll)

Pulse duration, ClKIN low

tw(CIH)

Pulse duration, ClKIN high

t
t

t This device is implemented in static logic and therefore can operate with tc(CI) approaching
approaching 0 Hz, but is tested at tc(CI) = 150 ns to meet device test time requirements.

t
t
00.

8
8

t
t

5
5

The device is characterized at frequencies

z
o

~
~

oLL
Z
W

TYP

MIN

'320VCXX-57

MAX

MIN

:I:

tf{CO)

Fall time, ClKOUT1

tr(CO)

Rise time, ClKOUT1

tw(COl)

Pulse duration, ClKOUT1 low

H-3

H +2

H-2

H+2

tw(COH)

Pulse duration, ClKOUT1 high

H-3

H+2

H-2

H+2

2c {CI)
11

in static logic and therefore can operate with tc(CI) approaching
approaching 0 Hz, but is tested at tc(CI) = 300 ns to meet device test time reqUirements.

o
m

td(CIH-CO)

TMS320VC2xx timing requirements over recommended operating conditions

:I:
20

Delay time, ClKIN high to ClKOUT1 highllow

"oJl

UNIT

Cycle time, ClKOUT1

-z

MAX

tc{CO)

..
:I: This device IS Implemented

TYP

00.

2tc(CI)
11

The device,is characterized at frequencies
'

'320VC2XX-57

'320VC2XX-40
MIN

MAX

MIN

MAX

:I:

17.5

UNIT

tc{CI)

Cycle time, ClKIN

:I:

tf(C))

Fall time, ClKIN

tr{CI)

Rise time, ClKIN

tw(Cll)

Pulse duration, ClKIN low

tw(CIH)

Pulse duration, ClKIN high

:I:
:I:

:I: This

device IS Implemented In static logic and therefore can operate with tc(CI) approaching
approaching 0 Hz, but is tested at tc(CI) = 150 ns to meet device test time reqUirements.

o
z

~ tc(CI)

ClKIN

--AI

~I"_-~~II---.I

~-J>j-

td(CIH-CO)

tw(CIH)

I I..

N
I

tf(CI)-.j

1"-

tw(CIL)

I
-+I I+- tr(CI)
1

I~"-'------- tc(CO)

CLKOUT1

i+--

\l.

00.

8
8

\,--~I

'-----'

~I
W

--.I

~ tw(COH) ~

t (COL).0'
-.j

I+- tr(CO)

"1\,.,.-___~1
I I

--.j ~ tHCO)

Figure 12. CLKIN-to-CLKOUT Timing Without PLL (using +2 clock option)

~TEXAS

INSTRUMENTS
9-50

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The device is characterized at frequencies

:I:
:I:

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

timing with the PLL circuit enabled x2 mode
NAME

PARAMETER

Input clock frequency

TEST CONDITIONS

MIN

MAX

UNIT

TC = O°C to 85°C, 3 V

14.25

MHz

TC = O°C to 85°C, 5 V

MHz

=O.5tc(co)1

switching characteristics over recommended operating conditions @ 5 V [H
'320C2XX-40

PARAMETER

MIN

TYP

'320C2XX-57

MAX

MIN

100

TYP

'320C2XX-80

MAX

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, ClKOUT1

td(CIH-CO)

Delay time, ClKIN high to ClKOUTl
highllow

tt{GO)

Fall time, ClKOUTl

tr(CO)

Rise time, ClKOUT1

tw(COl)

Pulse duration, ClKOUT1 low

H-2

H+2

H-2

H +2

H-2

H+2

tw{COHt

Pulse duration, ClKOUT1 high

H-2

H+2

H-2

H+2

H-2

H +2

Transition time, Pll synchronized after
ClKIN supplied

1000

cycles

50
3

1000

timing requirements over recommended operating conditions

ns
ns
ns
ns

'320C2XX-80

MAX

MIN

MAX

MIN

MAX

100

200

UNIT

150

tf(CI)

Fall time, ClKIN

tr(CI)

Rise time, ClKIN

tw(Cll)

Pulse duration, ClKIN low

twlCIH)

Pulse duration, ClKIN high

switching characteristics over recommended operating conditions

TYP

'320C2XX-57
MAX

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, ClKOUTl

td(GIH-CO~

Delay time, ClKIN high to ClKOUTl high/low

tf(CO)

Fall time, ClKOUT1

tr(CO)

Rise time, ClKOUT1

tw(COl)

Pulse duration, ClKOUT low

H-2

H +2

H-2

H +2

tw(COH)

Pulse duration, ClKOUT high

H-2

H +2

H -2

H +2

Transition time, Pll synchronized after ClKIN supplied

1000

cycles

50
3

2tc (Clt
8

1000

2tc (CI)
8

118

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

a:
o
L1.
Z

o
Z

'320C2XX-40
MIN

z
o

'320C2XX-57

MIN

ICycle time, ClKIN multiply by one
ICycle time, ClKIN multiply by two

'320C2XX-40

tc(CI)

9-51

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used are created in accordance with JEDEC Standard 100-A. To shorten the
symbols, some of the pin names and other related terminology have been abbreviated as follows:
A

A[15:0]

Memory strobe pins IS, OS or PS

CLKIN/X2

READY

CLKOUT1

Read cycle or RD

0[15:0]

RESET pins RS or RS

INT[3:1] or INTx

Write cycle or WE

Lowercase subscripts and their meanings are:

The following letters and symbols and their meanings are:

access time

cycle time (period)

Low

delay time

Valid

full time

High impedance

hold time

Unknown, changing, or don't care level

setup time

High

rise time
transition time
v

valid time

pulse duration (width)

:aE

o
LL

general notes on timing parameters

All output signals from the TMS320C2xx devices (including CLKOUT1) are derived from an internal clock such
that all output transitions for a given half cycle occur with a minimum of skewing relative to each other.
The signal combinations shown in the following timing diagrams may not necessarily represent actual cycles.
For actual cycle examples, refer to the appropriate cycle description section of this data sheet.

o
Z

~
Z

o
m

-z

MAX

MIN

MAX

UNIT

H-7

H-6

H-10

H-8

tsu(A)CO

Setup time, address valid before CLKOUT1 low

H-9

H-8

th(A)COw

Hold time, address valid after CLKOUT1 low

H-3

H-2

tw(NSN)

Pulse duration, IS, DS, PS inactive hight

H-9

H-8

tw(WL)

Pulse duration, WE low (no wait states)

2H-2
2H-2

Setup time, address valid before WE low

th(A)W

Hold time, address valid after WE high

tw(WH)

Pulse duration, WE high

td(CO-W)

Delay time, CLKOUT1 low to WE low/high

td(WRD)

Delay time, WE high to RD low

3H -10

tsu(D)W

Setup time, write data valid before WE high

2H-15

th(D)W

Hold time, write data valid after WE high

tsu(DCOL)W

Setup time, write data valid before CLKOUT1 low

th(DCOL)W

Hold time, write data valid after CLKOUT1 low

Enable time, WE to data bus driven t
teniD)W
t Values derived from characterization data and not tested.

o
z

'320C2XX-80

H-10

tsu(A)W

5 V [H = O.5tc(co)1
MAX

MIN

2H +2

2H-20
H-4

2H+2

2H-2

H-4

2H-2

6
2Ht
2Ht
H + 11t

-4

PARAMETER

2Ht

H-4

H +7t
2Ht

2H-20

H + 11t

2H-14
H-3
2H-20
H-5

Setup time, address valid before WE low

th(A)W

Hold time, address valid after WE high

tsu(A)CO

ns
ns

2Ht

H +7t

2Ht

H+ 11t

-3

-4

3 V [H = O.5t c(co)1
'320VC2XX-40
'320VC2XX-57
MIN

tsu(A)W

ns
2H +2

3H-8

2H-15

H-4

3H-8
H +7t

2H-2

." switching characteristics over recommended operating conditions

'320C2XX-57

UNIT

MAX

H-5

H-10

Setup time, address valid before CLKOUT1 low

H-9

th(A)COw

Hold time, address valid after CLKOUT1 low

H-3

twlNSN)

Pulse duration, IS, DS, PS inactive hight

H -9

tw(WL)

Pulse duration, WE low (no wait states)

2H-2

tw(WH)

Pulse duration, WE high

2H-2

td{CO-W)

Delay time, GLKOUT1 low to WE low/high

td(WRD)

Delay time, WE high to RD low

tsu(D)W

Setup time, write data valid before WE high

th(D)W

Hold time, write data valid after WE high

tsu(DCOL)W

Setup time, write data valid before CLKOUT1 low

thfDCOL)W

Hold time, write data valid after CLKOUT1 low

ten(D)W

Enable time, WE to data bus drivent

2H-15
H-4
2H-20
H-4
-4

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

ns
ns

3H-8

t Values derived from characterization data and not tested.

9-56

ns
2H +2

2Ht

H +7t

2Ht

H + 11

ns
ns

TiviS320C203, Ti'vlS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025-JUNE 1995

PARAMETER MEASUREMENT INFORMATION
CLKOUT1

=x
-.l

AO-A15

I+- td(CO-A) -+l
I
I

th(A)CO

X\-_______---'X
1---------

j4-- td(CO-RO)

~I tsu(A)RO

--~~__
RO

I
,
I ta(RO) ---.! ~
ta(A)

I
010-0115

R/W

I
I
I

tw(ROL) 14

14-14--IIlI-tw(ROH)

I
I

~
.1 I

114

th(O)RO

=:!

--;-.1I -®(
--+j

STRB

14
tsu(O)RO

I~
th(A)RO ~ ~

.r---------------~I.

--rJ

r-r-

I
I

th(OCOL)R

tsu(OCOL)R

o
~

}>-------~

)@2X

~-~

oL1.

~ td(CO-S)

--J/

'{IIO......'_ _ _ _

\'----

Figure 14. Memory Interface Read Timing

o
Z

CX
I
~~l------~i----------~!~;I
~

r--\.
i --: ~ 'su(AleC I I }---{~~_____________
-1
\~______~I____~I__________:~I_/

tsu(A)W

"T1

~~--~l~~-----------

~
z
(')

\J\J

I I : + - td(WRO) ---+1

th(A)CO

»c

I
:I
1

ROJ

TiVlS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

READY timing

t'Immg
.

requlremen 5 over recommen d e d opera t'mg con dT
I Ions

=05teCCO).
'320C2XX-40,
'320C2XX57,
3/5 vt
MIN

MAX

'320C2XX-80
5V
MIN

UNIT

MAX

tsu(R-CO)

Setup time, READY before CLKOUT1 rises

th(CO-R)

Hold time, READY low after CLKOUT1 rises

tsu(R)RD

Setup time, READY before RD falls

thJH1RD

Hold time, READY after RD falls

tv(R)W

Valid time, READY after WE falls

4
H-13

4
H-10

ns
ns

th(R)W

Hold time, READY after WE falls

H +4

H+3

tvlA)Ar

Valid time, READY after address valid on read

H-17

H-15

tv(R)Aw

Valid time, READY after address valid on write

2H-18

2H-16

t 3-V operation, 'C203 only

CLKOUT1

I
I

RD~________

~:J
r-rr-

\~
tsu(R-CO)

I I 14
~I
I ,4
~I
-41 i+ tsu(R-RD) I

READY

AO-A15

:::x

______________I

,..-- th(R)W
~ tv(R)W

-+j

I
I

I,.---------------~

tv(R)Ar

==
a::

, .
th(R)CO
th(R)RD

u..

I~------------

~ tv(R)Aw ---.:

X,.---------------X\-______x: z
Figure

~
c

16. READY Timing

II(

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

9-59

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

RS, INT1-INT3, NMI, 810, TOUT, and XF timing
INTN refers to BIO, INT1-INT3, and NMI.

switching characteristics over recommended operating conditions [H = O.5tc(co)1
'320C2XX-40,
'320C2XX57,
3/5 vt
PARAMETER

'320C2XX-80
5V

UNIT

MIN

MAX

MIN

MAX

td(XFl

Delay time, XF valid after ClKOUT1

td(TOUT)

Delay time, TOUT high/low after ClKOUT1

tw(TOUT)

Pulse duration, TOUT high

2H -12

2H-9

UNIT

t 3-V operation, 'C203 only
+ Values derived from characterization data and not tested.

=O.5tc(co)1

timing requirements over recommended operating conditions [H

»
c
~
z

-z

::IJ

o
z

'320C2XX-40,
'320C2XX57,
3/5 vt
MIN

MAX

'320C2XX-80
5V
MIN

MAX

UNIT
UNIT

tsu(RS)CI

Setup time, RS no longer high before ClKIN low

tsu(RS)CO

Setup time, RS no longer low before ClKOUT1 low

tw(RSl)

Pulse duration, RS low

12H

td(EXl

Delay time, RS high to reset-vector fetch

34H

tsu(IN)CO

Setup time, INTx before ClKOUT1 low (synchronous)

th(IN)CO

Hold time, INTx after ClKOUT1 low (synchronous)

twONl

Pulse duration, INTx low/high

td(IN)

Delay time, INTx low to interrupt-vector fetch

2H + 18

2H + 16

12H

t 3-V operation, 'C203 only

I
I
I

ClKIN

CLKOUTl

~
14

tsu(RS)CI

/
I

tw(RSl)

114.. --~~I- tsu(RS)CO

--------+t~1

RS,

Figure 17. Reset Timing

~TEXAS

INSTRUMENTS
9-60

\ ____

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C203, TiV1S320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025-JUNE 1995

CLKOUT

~'-_-.....JI

)~_----II

INTN

~'-_-.....JI
I

I
I

tsu(IN)CO
j+_ _ _ _ _ _....1114141----

14- th(IN)CO
I

tW(IN)---'.-I~_ _ _ _ __

\'--_____~I

Figure 18. Interrupt and 810 Timing

CLKOUT1

I
I

~td(XF)
-~X

__--.,..._ _ __
:

~ td(TOUT)
1

14
TOUT

tw(TOUT)

------------~-------

:a:
a:
o
u..

Figure 19. XF and TOUT Timing

o
Z

0000000<___----'

o
z

_______x_________
7/15

8/16

Figure 22. Serial-Port Receive Timing

serial port transmit, external clocks, and external frames
switching characteristics over recommended operating conditions
PARAMETER

MIN

MAX

UNIT

td(DX)

Delay time, OX valid after CLKX high

tdis(DX)

Disable time, OX after CLKX high

th(DX)

Hold time, valid after CLKX high

-5

•
TEXAS
INSTRUMENTS
9-64

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ti'viS320C203, Ti'viS320C209, TwiS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

serial port transmit, external clocks, and external frames (continued)
timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H o.5tc(co)1

'320C2XX-40,
'320C2XX57,

'320C2XX-80
5V

3/5Vt
MAX

MIN

UNIT
UNIT

MAX

tc(SCK)

Cycle time, serial port clock

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

td(FS}

Delay time, FSX after CLKX rising edge high

th(FS)

Hold time, FSX after CLKX falling edge low

th(FS)H

Hold time, FSX after CLKX rising edge high

2H -8

2H-8

ns
ns

10
2H-8

2H-8

3-V operation, 'C203 only

tf(SCK)
CLKX

td(FS) ~

LJ
th(FS) --,.-,
I

)
FSX

--'

I
I

td(OX)
OX

I
I

\~~---+I-------ilr---'l!.,...! _ _ _ _ _ _....J!

'{'-\
......

-.III

tw(SCK) ......--al~

th(FS)H

--J++j

th(OX)

-+j 14-

tdis(OX)

l,q,-~_~X,--_ _X

>OOOOOOOOO<'-------JX
2

o
~

7/15

8/16

a::

oLL

I
I
I
I
I
~

j- o
Z

~
c

Figure 23. Serial-Port Transmit Timing of External Clocks and External Frames

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-65

TMS320C203, TMS320C209, TMS320VC203
DIGITAL SIGNAL PROCESSOR
SPRS025 - JUNE 1995

serial port transmit, internal clocks, and internal frames
switching characteristics over recommended operating conditions, H
PARAMETER

MIN

=O.5tc(CO)

'320C2XX-40,
'320C2XX57,
3/5 vt
TYP

'320C2XX-80
5V
MAX

MIN

-4

TYP

UNIT
MAX

td(FS)

Delay time, CLKX rising to FSX

td(DX)

Delay time, CLKX to DX

tdis(DX)

Disable time, CLKX rising to DX

tc(SCK)

Cycle time, serial port clock

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

th(DX)

Hold time, DX valid after CLKX rising high

-5

2H-20

2H-16

-5

-4

t 3-V operation, 'C203 only

--.I 1.- tf(SCK)
I

-z

o
J]
s

~
o
z

7/15

Figure 24. Serial Port Transmit Timing of Internal Clocks and Internal Frames

•
TEXAS
INSTRUMENTS
9-66

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Tfv1S320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

•
•

Powerful 16-Bit TMS320C5x CPU
20-, 25-, 35-, and 50-ns Single-Cycle
Instruction Execution Time for 5-V
Operation

•

25-, 40-, and 50-ns Single-Cycle Instruction
Execution Time for 3-V Operation
Single-Cycle 16 x 16-Bit Multiply/Add

o
•

224K x 16-Bit Maximum Addressable
External Memory Space (64K Program, 64K
Data, 64K 110, and 32K Global)

•

2K, 4K, 8K, 16K, 32K x 16-Bit Single-Access
On-Chip Program ROM

•

1K, 3K, 6K, 9K x 16-Bit Single-Access
On-Chip Program/Data RAM (SARAM)

•

1K Dual-Access On-Chip Program/Data
RAM (DARAM)

•

Full-Duplex Synchronous Serial Port for
Coder/Decoder Interface
Time-Division-Multiplexed (TDM) Serial Port

•

Hardware or Software Wait-State
Generation Capability

•
•

On-Chip Timer for Control Operations
Repeat Instructions for Efficient Use of
Program Space

•
•

Buffered Serial Port
Host Port Interface

•

Multiple Phase-Locked Loop (PLL)
Clocking Options (x1, x2, x3, x4, x5, x9
Depending on Device)

•

Block Moves for Data/Program
Management

•

On-Chip Scan-Based Emulation Logic

o Boundary Scan
•

Five Packaging Options
- 100-Pin Quad Flat Package (PJ Suffix)
- 100-Pin Thin Quad Flat Package
(PZ Suffix)
- 128-Pin Thin Quad Flat Package
(PBK Suffix)
- 132-Pin Quad Flat Package (PQ Suffix)
- 144-Pin Thin Quad Flat Package
(PGE Suffix)

•

Low Power Dissipation and Power-Down
Modes:
- 47 rnA (2.35 mA/MIP) at 5 V, 40-MHz
Clock (Average)
- 23 rnA (1.15 mA/MIP) at 3 V, 40-MHz
Clock (Average)
- 10 rnA at 5 V, 40-MHz Clock (IDLE1 Mode)
- 3 rnA at 5 V, 40-MHz Clock (IDLE2 Mode)
- 5 IlA at 5 V, Clocks Off (IDLE2 Mode)
High-Performance Static CMOS Technology
IEEE Standard 1149.1t Test-Access Port
(JTAG)

•
•

description
The TMS320C5x generation of the Texas Instruments (TFM) TMS320 digital signal processors (DSPs) is
fabricated with static CMOS integrated circuit technology; the architectural design is based upon that of an
earlier TI DSP, the TMS320C25. The combination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
the 'C5xt devices. They execute up to 50 million instructions per second (MIPS).
The 'C5x devices offer these advantages:
•
•
•
•
•
•

Enhanced TMS320 architectural design for increased performance and versatility
Modular architectural design for fast development of spin-off devices
Advanced integrated-circuit processing technology for increased performance
Upward-compatible source code (source code for 'C1 x and 'C2x DSPs is upward compatible with 'C5x DSPs.)
Enhanced TMS320 instruction set for faster algorithms and for optimized high-level language operation
New static-design techniques for minimizing power consumption and maximizing radiation tolerance

TI is a trademark of Texas Instruments Incorporated.
t IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture
References to 'C5x in this document include both TMS320C5x and TMS320LC5x devices unless specified otherwise.

PRODUCllON DATA Information Is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily Include
testing of ali parameters.

•
TEXAS
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9-67

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

description (continued)
Table 1 provides a comparison of the devices in the 'C5x generation. It shows the capacity of on-chip RAM and
ROM memories, number of serial and parallel I/O ports, execution time of one machine cycle, and type of
package with total pin count.

Table 1. Characteristics of the 'C5x Processors
ON-CHIP MEMORY (16-BIT WORDS)
TMS320
DEVICES

DARAM

SARAM

ROM

I/O PORTS

POWER
SUPPLY
(V)

CYCLE
TIME
(ns)

PACKAGE
TYPE
QFP:j:
132 pin

DATA

DATA +
PROG

PROG

SERIAL

PARALLELt

TMS320C50

544

512

2K§

64K

50/35/25

TMS320LC50

544

512

2K§

64K

3.3

50/40/25

132 pin

TMS320C51

544

512

8K§

64K

50/35/25/20

100/132 pin

TMS320LC51

544

512

8K§

64K

3.3

50/40/25

100/132 pin

TMS320C52

544

512

4K§

64K

50/35/25/20

100 pin

TMS320LC52

544

512

4K§

64K

3.3

50/40/25

100 pin

TMS320C53

544

512

16K§

64K

50/35/25

132 pin

TMS320LC53

544

512

16K§

64K

3.3

50/40/25

132 pin

TMS320C53S

544

512

16K§

64K

50/35/25

100 pin

TMS320LC53S

544

512

16K§

64K

3.3

50/40/25

100 pin

TMS320LC56

544

512

32K

64K

3.3

35/25

100 pin

TMS320LC57

544

512

32K

64K+ HPIII

3.3

35/25

128 pin

TMS320C57S

544

512

2K§

64K + HPIII

50/35/25

144 pin

TMS320LC57S

544

512

2K§

64K + HPIII

3.3

50/35

144 pin

t Sixteen of the 64K parallel I/O ports are memory mapped.
:j: QFP = Quad flatpack
§ ROM boot loader available
~ TDM serial port not available
# Includes auto-buffered serial port (SSP) but TDM serial port not available
II HPI = Host port interface

Pinouts for each package are device-specific.

~TEXAS

INSTRUMENTS
9-68

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

TMS320C50, TMS320LC50, TMS320C51, TMS320LC51, TMS320C53, TMS320LC53
PO PACKAGE
(TOP VIEW)

NC
NC

18
19

116
115

NC
NC

VSSO

114

VSSO
NC

113

112

VODI
lACK
NC

VOOI

111

D6
D5

110

CLKOUT1

109

108

HOLDA

107

TOX

106

105

TFSX/TFRM

DO
TMS

104

FSX

103

CLKMD2

VDDD

102

VSSI

VDOO
TCK

101

100

VSSI
TOO

VSSD

VDOC

VSSD
NC

VOOC
X1

INT1

X2/CLKIN

INT2

CLKIN2

INT3

INT4

STAB

NMI
OR

RlW

TOR

FSR

CLKR

VDDA

VSSC

VODA
NC
NC

VSSC
NC

50
51 52 53 54 55 56 57 58 59 60 61 62 63 84 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

NOTE: NC

= No connect (These pins are reserved.)

•
TEXAS
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9-69

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A- APRIL 1995 - REVISED APRIL 1996

Pin Functions for Devices in the PQ Package
SIGNAL

DESCRIPTION

TYPE

PARALLEL INTERFACE BUS
AO-A15

I/0Il,

DO-D15

I/0Il

PS, DS, IS

OIl

16-bit external address bus (MSB: A 15, LSB: AO)
16-bit external data bus (MSB: D15, LSB: DO)
Program, data, and 1/0 space select outputs, respectively

STRB

I/0Il

R/W

I/0Il

Read/write select for external cycles and external DMA

OIl

Read and write strobes, respectively, for external cycles

RD,WE
READY

liming strobe for external cycles and external DMA

External bus ready/wait-state control input

I/Oll

MP/MC

Microprocessorlmicrocomputer mode select. Enables internal ROM

HOLD

Puts parallell/F bus in high-impedance state after current cycle

Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero

HOLDA

OIl

External flag output. Setlcleared through software

BIO

I/O branch input. Implements conditional branches

Hold acknowledge. Indicates external bus in hold state

TOUT

OIl

lAO

OIl

Instruction acquisition signal

lACK

OIl

Interrupt acknowledge Signal

limer output signal. Indicates output of internal timer

INT1-INT4

External interrupt inputs

NMI

Nonmaskable external interrupt

Serial receive-data input

OIl

SERIAL PORT INTERFACE (SPI)

CLKR

CLKX

I/Oll

FSR

FSX

I/Oll

TDR

TDX

OIl

Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data ciock input
Serial transmit-data ciock. Internal or external source
Serial receive-frame-synchronization input
Serial transmit-frame-synchronization signal. Internal or external source
TOM SERIAL·PORT INTERFACE
TDM serial receive-data input
TDM serial transmit-data output. In high-impedance state when not transmitting
TDM serial receive-data ciock input

TCLKR

TCLKX

I/Oll

TDM serial transmit-data clock. Internal or external source

TFSRITADD

I/Oll

TDM serial receive-frame-synchrpnization input. In the TDM mode, TFSR/TADD is used to output!
input the address of the port.

TFSX/TFRM

TDM serial transmit-frame-synchronization signal. Internal or external source. In the TDM mode,
TFSX/TFRM becomes TFRM, the TDM frame synchronization.

LEGEND:
I
Input
0= Output
l
High impedance

=
=

~TEXAS

INSTRUMENTS
9-70

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for Devices in the PQ Package (Continued)
EMULATIONIIEEE STANDARD 1149.1 TEST ACCESS PORT (TAP)

TDI

TDO

OIl

TAP scan data input
TAP scan data output

TMS

TAP mode select input

TCK

TAP clock input

TRST

TAP reset (with pulldown resistor). Disables TAP when low

EMUO

I/OIl

Emulation control O. Reserved for emulation use

EMU1/0FF

I/Oll

Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL

Oscillator output

X2/CLKIN

Clock/oscillator input

CLKIN2

Clock input

CLKMD1, CLKMD2

Clock-mode select inputs

CLKOUT1

OIl

Device system-clock output
POWER SUPPLY CONNECTIONS

VDDA

Supply connection, address-bus output

VDDD

Supply connection, data-bus output

VDDC

Supply connection, control output

VDDI

Supply connection, internal logic

VSSA

Supply connection, address-bus output

VSSD

Supply connection, data-bus output

VSSC

Supply connection, control output

VSSI

Supply connection, internal logic

LEGEND:
I = Input
0= Output
S = Supply
l = High impedance

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-71

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRil 1995 - REVISED APRil 1996

TMS320LC57
PBK PACKAGE
(TOP VIEW)

HINT

EMUO
EMU1/0FF
VSSC
VSSC
TOUT
BClKX
ClKX
VOOC
BFSR
BClKR
RS
READY
HOLD
BIO
VDDC

94
93
92
91
90
89
88
87

All
Al0

ClKMOl

VSSA
VSSA
TOI
HOSl
HOS2

IAQ
TRST

VSSI
VSSI

MP/MC
015
014
013
012
011
010
09
08

VOOI
VOOI
A9
A8
A7
AS
A5
A4
A3
A2
Al

VSSA
HCS

65
~M~~~~$~~Ga«~~Q~~~~~~~$66~6666M~~8384

@@15~13~8~Ei8

»en en

9-72

VODA
A15
A14
A13
A12

VODC

VODD
VOOD

WE
H01
RO
HOO
HROY

Ii=

Ii!

9 en ::::i 0 0 ~ 0 0 I~ I~ I~ :::! I~ a: a: a: a: c( c( len
~~~§§~~~~~~~~~zog~d§§~
u u»
»I
»
I
I

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for the TMS320LC57 in the PBK Package
SIGNAL

TYPE

DESCRIPTION
PARALLEL INTERFACE BUS

AO-A15

1/0Il

DO-D15

1/0Il

PS, DS, IS

Oil

16-bit external address bus (MSB: A 15, LSB: AO)
16-bit external data bus (MSB: D15, LSB: DO)
Program, data, and 1/0 space select outputs, respectively

STRB

1/0Il

Timing strobe for external cycles and external DMA

RIW

1/0Il

Readlwrite select for external cycles and external DMA

RD,WE

Oil

READY

Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input

1/0Il

MP/MC

Microprocessor/microcomputer mode select. Enables internal ROM

HOLD

Puts parallell/F bus in high-impedance state after current cycle

Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACE/CONTROL SIGNALS
Reset. Initializes device and sets PC to zero

HOLDA

Oil

External flag output. Set/cleared through software

BIO

1/0 branch input. Implements conditional branches

Hold acknowledge. Indicates external bus in hold state

TOUT

Oil

Timer output signal. Indicates output of internal timer

IAQ

Oil

Instruction acquisition signal

INT1-INT4

External interrupt inputs

NMI

Nonmaskable external interrupt

Serial receive-data input

Oil

SERIAL PORT INTERFACE

CLKR

CLKX

1/0Il

FSR

FSX

1/0Il

Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
Serial transmit-data clock. Internal or external source
Serial receive-frame-synchronization input
Serial transmit-frame-synchronization signal. Internal or external source
HOST PORT INTERFACE (HPI)

HCNTLO
HCNTL1

HPI mode control 1

HPI mode control 2

HINT

Oil

HDS1

HPI data strobe 1

HDS2

HPI data strobe 2

HR/W

HPI readlwrite strobe

HAS

HRDY

Oil

Host interrupt

HPI address strobe
HPI ready signal

HCS

HPI chip select

HBIL

HPI byte identification input

HDO-HD7

1/0Il

HPI data bus

LEGEND:
I = Input
0= Output
l = High impedance

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-73

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for the TMS320LC57 in the PBK Package (Continued)
SIGNAL

DESCRIPTION

TYPE

BUFFERED SERIAL PORT
BDR

BDX

OIZ

BClKR

BCLKX

I/OIZ

BFSR

BFSX

I/OIZ

BSP receive data input
BSP transmit data output; in high-impedance state when not transmitting
BSP receive-data clock input
BSP transmit-data clock; internal or external source
SSP receive frame-synchronization input
SSP transmit frame-synchronization signal; internal or external source
EMULATION/JTAG INTERFACE

TDI

JTAG-test-port scan data input

TDO

OIZ

JTAG-test-port scan data output

TMS

JTAG-test-port mode select input

TCK

JTAG-port clock input

TRST

JTAG-port reset (with pull-down resistor). Disables JTAG when low

EMUO

I/OIZ

Emulation control O. Reserved for emulation use

EMU1/0FF

I/OIZ

Emulation control 1. Puts outputs in high-impedance state when low
CLOCK GENERATION AND CONTROL

Oscillator output

X2/CLKIN

Clock input

CLKMD1, CLKMD2,
CLKMD3

Clock-mode select inputs

CLKOUT1

OIZ

Device system-clock output
POWER SUPPLY CONNECTIONS

VDDA

Supply connection, address-bus output

VDDD

Supply connection, data-bus output

VDDC

Supply connection, control output

VDDI

Supply connection, internal logic

VSSA

Supply connection, address-bus output

VSSD

Supply connection, data-bus output

VSSC

Supply connection, control output

Supply connection, internal logic

VSSI
LEGEND:
I = Input
0= Output
S = Supply
Z = High impedance

~TEXAS

9-74

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

TMS320C51, TMS320LC51, TMS320C52, TMS320LC52, TMS320C53S, TMS320LC53S, TMS320LC56
PZPACKAGE
(TOP VIEW)

EMUO

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

EMU1/0FF
VSSC
TOUT

t
t
t

t
RS
READY
HOLD
810
TRST
VSSI
VSSI
MP/MC
D15
D14
D13
D12
Dll
Dl0
D9
D8
VDDD

10
11
12
13
14
15
16

17
18
19
20
21
22
23
24
25

WE
RD
VDDA
A15
A14
A13
A12
All
Al0
CLKMDl
VSSA
VSSA
TOI
VDDI
A9
A8
A7
A6
A5
A4
A3
A2
Al

AD
VSSA

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Cl Cl ~

CD It) "<:t (')
~ 0 rJ) Cl ~ Cl Cl I~
1(') l"<:t I~ +- +- +- +~~ClClClClClClClCl~8~~~~~~~Z

NOTE:
NC = No connect (These pins are reserved.)
t See Table 2 for device-specific pinouts.

Table 2. Device-Specific Pinouts for the PZ Package
PIN

'C51, 'LC51
TCLKX

. 'C52, 'LC52

'C53S, 'LC53S

'LC56*

CLKX2

BCLKX

CLKX

VSSI
CLKX

CLKX1

CLKX

TFSRITADD

VSSI

FSR2

BFSR

TCLKR

VSSI
DR

CLKR2

BCLKR

DR1

46~

TDR

BDR

FSR

VSSI
FSR

DR2

48§

FSR1

FSR

49§

CLKR

CLKR1

CLKR

CLKIN2

CLKMD3

91§

FSX

FSX1

FSX

TFSX/TFRM

FSX2

BFSX

DX1

DX2

BDX

93§

VSSI
DX

TDX

+Pin names beginning with "B" indicate signals on the buffered serial port (BSP).
§ No functional change

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-75

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for Devices in the PZ Package
SIGNAL

TYPE

DESCRIPTION
PARALLEL INTERFACE BUS

AO-A15

I/O/Z

00-015

I/O/Z

PS, OS, IS

O/Z

16-bit external address bus (MSB: A15, LSB: AO)
16-bit external data bus (MSB: 015, LSB: DO)
Program, data, and I/O space select outputs, respectively

STRB

I/O/Z

Timing strobe for external cycles and external DMA

R/W

I/O/Z

Read/write select for external cycles and external DMA

RD,WE

O/Z

READY

Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input

I/O/Z

Bus request. Arbitrates global memory and external DMA

Reset. Initializes device and sets PC to zero

MP/MC

Microprocessor/microcomputer mode select. Enables internal ROM

HOLD

SYSTEM INTERFACE/CONTROL SIGNALS

Puts parallel 1/ F bus in high-impedance state after current cycle
Hold acknowledge. Indicates external bus in hold state

HOLDA

O/Z

External flag output. Set/cleared through software

BIO

I/O branch input. Implements conditional branches

TOUT

O/Z

Timer output signal. Indicates output of internal timer

INT1-INT4

External interrupt inputs

NMI

Nonmaskable external interrupt

DR, DR1, DR2

Serial receive-data input

OX, DX1, DX2

O/Z

SERIAL PORT INTERFACE

CLKR,CLKR1,CLKR2

CLKX,CLKX1,CLKX2

I/O/Z

FSR, FSR1, FSR2

FSX,FSX1,FSX2

I/O/Z

BDR

BOX

O/Z

BCLKR

BCLKX

I/O/Z

BFSR

BFSX

I/O/Z

BSP receive data input
BSP transmit data output; in high-impedance state when not transmitting
BSP receive-data clock input
BSP transmit-data clock; internal or external source
BSP receive frame-synchronization input
BSP transmit frame-synchronization signal; internal or external source

LEGEND:
I = Input
0= Output
Z = High impedance
NOTE 1: 'LC56 devices only

~TEXAS

9-76

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for Devices in the PZ Package (Continued)
SIGNAL

DESCRIPTION

TYPE

TOM SERIAL PORT INTERFACE
TOR

TOX

Oil

TOM serial receive-data input
TOM serial transmit-data output. In high-impedance state when not transmitting

TCLKR

TCLKX

I/Oll

TOM serial transmit-data clock. Internal or external source

TOM serial receive-data clock input

TFSR/TAOO

I/Oll

TOM serial receive-frame-synchronization input. In the TOM mode, TFSR/TAOO is used to output!
input the address of the port

TFSXITFRM

TOM serial transmit-frame-synchronization signal. Internal or external source. In the TOM mode,
TFSXITFRM becomes TFRM, the TOM frame sync.

TOI

JTAG-test-port scan data input

TOO

Oil

JTAG-test-port scan data output

TMS

JTAG-test-port mode select input

TCK

JTAG-port clock input

TRST

JTAG-port reset (with pull-down resistor). Disables JTAG when low

EMUO

I/Oll

Emulation control

EMU1/0FF

I/O/Z

Emulation control 1. Puts outputs in high-impedance state when low

EMULATION/JTAG INTERFACE

o. Reserved for emulation use

CLOCK GENERATION AND CONTROL (SEE NOTE 2)
X1

Oscillator output

X2/CLKIN

Clock/oscillator input (PLL clock input for 'C56)

CLKIN2

Clock input (PLL clock input for 'C50, 'C51, "C52, 'C53, 'C53S)

CLKM01, CLKM02,
CLKM03

Clock-mode select inputs

CLKOUT1

Oil

Device system-clock output
POWER SUPPLY CONNECTIONS

VOOA

Supply connection, address-bus output

VOOO

Supply connection, data-bus output

VOOC

Supply connection, control output

VOOI

Supply connection, internal logic

VSSA

Supply connection, address-bus output

VSSO

Supply connection, data-bus output

VSSC

Supply connection, control output

Supply connection, internal logic
S
VSSI
LEGEND:
I = Input
0= Output
S = Supply
l = High impedance
NOTE 2: CLKIN2 pin is replaced by CLKM03 pin on 'LC56 devices.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-77

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISEO APRIL 1996

TMS320C52, TMS320LC52
PJ PACKAGE
(TOP VIEW)

EMU1/0FF

VOOO

EMUO

VSSO

VOOC

VSSO

VOOC

VOOI

06
05

VOOI
CLKOUT1

HOLOA

VSSI
FSX

TMS
VOOO

CLKM02

VOOO
TCK

VSSI

VSSO

VSSI
TOO

VSSO
INT1

VOOC
X1

INT2

X2/CLKIN

INT3

CLKIN2

INT4
NMI

RlW
PS
is

OR
VSSI
FSR
CLKR

VOOA

VSSC
WE

VSSA

NOTE:

=No connect (These pins are reserved.)

~TEXAS

9-78

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package
SIGNAL

TYPE

DESCRIPTION
PARALLEL INTERFACE BUS

AO-A15

I/0Il

DO-D15

I/0Il

PS, DS, IS

OIl

16-bit external address bus (MSB: A 15, LSB: AO)
16-bit external data bus (MSB: D15, LSB: DO)
Program, data, and 1/0 space select outputs, respectively

STRB

I/Oll

Timing strobe for external cycles and external DMA

RIW

I/Oll

Readlwrite select for external cycles and external DMA

RD, WE

OIl

READY

Read and write strobes, respectively, for external cycles
External bus ready/wait-state control input

I/0Il

MP/MC

Microprocessor/microcomputer mode select. Enables internal ROM

HOLD

Puts parallel II F bus in high-impedance state after current cycle

Bus request. Arbitrates global memory and external DMA
SYSTEM INTERFACEICONTROL SIGNALS
Reset. Initializes device and sets PC to zero

HOLDA

OIl

External flag output. Set/cleared through software

BIO

1/0 branch input. Implements conditional branches

TOUT

OIl

Hold acknowledge. Indicates external bus in hold state

Timer output signal. Indicates output of internal timer

INT1-INT4

External interrupt inputs

NMI

Nonmaskable external interrupt

Serial receive-data input

OIl

SERIAL PORT INTERFACE

CLKR

CLKX

I/0Il

Serial transmit-data output. In high-impedance state when not transmitting
Serial receive-data clock input
Serial transmit-data clock. Internal or external source

FSR

FSX

I/0Il

Serial receive-frame-synchronization input

TDI

TDO

OIl

TMS

JTAG-test-port mode select input

TCK

JTAG-port clock input

TRST

JTAG-port reset (with pulldown resistor). Disables JTAG when low

EMUO

I/0Il

Emulation control O. Reserved for emulation use

EMU1/0FF

I/0Il

Emulation control 1. Puts outputs in high-impedance state when low

Serial transmit-frame-synchronization signal. Internal or external source
EMULATION/JTAG INTERFACE
JTAG-test-port scan data input
JTAG-test-port scan data output

LEGEND:
I = Input
0= Output
l = High impedance

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-79

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A-APRIL 1995 - REVISED APRIL 1996

Pin Functions for the TMS320C52, TMS320LC52 in the PJ Package (Continued)
SIGNAL

DESCRIPTION

TYPE

CLOCK GENERATION AND CONTROL
X1

Oscillator output

X2/CLKIN

Clock/oscillator input

CLKIN2

Clock input (PLL clock input for 'C52, 'LC52)

CLKMD1, CLKMD2

Clock-mode select inputs

CLKOUT1

O/Z

Device system-clock output
POWER SUPPLY CONNECTIONS

VDDA

Supply connection, address-bus output

VDDD

Supply connection, data-bus output

VDDC

Supply connection, control output

VDDI

Supply connection, internal logic

VSSA

Supply connection, address-bus output

VSSD

Supply connection, data-bus output

VSSC

Supply connection, control output

Supply connection, internal logic

VSSI
LEGEND:
I = Input
0= Output
S = Supply

•
TEXAS
INSTRUMENTS
9-80

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRil 1995 - REVISED APRil 1996

TMS320C57S, TMS320LC57S
PGE PACKAGE
(TOP VIEW)

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~
HINT
EMUO
NC
EMU1/0FF
VSSC
VSSC
TOUT
BClKX
ClKX
VODC
BFSR
BClKR
RS
READY
HOLD
NC
BIO
VODC
VODC
IAQ
TRST
VSSI
VSSI
MP/MC
D15
D14
D13
NC
D12
D11
010
D9
NC
08

a ~ ~ § ~ ~ ~ ~ ~ ~ a ~ ~ ~ ~ ~ ~ ~ ~ ~ E~ ~ ~ ~
108
107

10
2

106

3
4

105
104
103
102
101
100

9
10

11
12

95
. 94

15
16

19
20

88
87
86

85
84
83
82
81
80
30

79
78

75
74

VDDD
VDDD

~ ~ ~ ~

orJ)rJ)
0

;

~ ~ ~ ~ ~ ~ ~ ~

b ~ ()Z ~

~ ~ ~ ~ ~ ~ ~ ~ ~

~ ~ ~ ~ ~

If:

If!

m~ ~ mR ~

VDDA
A15
NC
A14
A13
A12
NC
A11
A10
ClKMD1
VSSA
VSSA
TOI
HDS1
HDS2

0:
==

VDDI
VDDI
A9
A8
A7
NC
A6
A5
A4
A3
NC
A2
A1
AO

VSSA
HCS

ACCB
Store ACC in ACCB if ACC< ACCB
Exchange ACCB with ACC
Load ACC with ACCB
Load ACC with shift
Load ACC long immediate with shift
Load ACC with shift of 16
Load low word of ACC with immediate
Load low word of ACC
Load ACC with shift specified by TREG1 [3-0]
Load ACCL with memory-mapped register
Negate ACC
Normalize ACC
OR ACC with data value
OR with ACC long immediate with shift
OR with ACC long immediate with shift of 16
OR ACCB with ACC
Rotate ACC 1 bit left
Rotate ACCB and ACC left
Rotate ACC 1 bit right
Rotate ACCB and ACC right
Store ACC in ACCB
Store high ACC with shift
Store low ACC with shift
Store ACCL to memory-mapped register
Shift ACC 16 bits right if TREG1 [4] = 0
Shift ACCo-ACC15 right as specified by TREG1 [3-0]
Subtract ACCB from ACC
Subtract ACCB from ACC with borrow
Shift ACC 1 bit left
Shift ACCB and ACC left
Shift ACC 1 bit right
Shift ACCB and ACC right
Subtract from ACC with shift
Subtract from ACC with shift of 16
Subtract from ACC short immediate
Subtract from ACC long immediate with shift

ABS
ADCB
ADD
ADD
ADD
ADD
ADDB
ADDC
ADDS
ADDT
AND
AND
AND
ANDB
BSAR
CMPL
CRGT
CRLT
EXAR
LACB
LACC
LACC
LACC
LACL
LACL
LACT
LAMM
NEG
NORM
OR
OR
OR
ORB
ROL
ROLB
ROR
RORB
SACB
SACH
SACL
SAMM
SATH
SATL
SBB
SBBB
SFL
SFLB
SFR
SFRB
SUB
SUB
SUB
SUB

1011
1011
0010
1011
1011
0110
1011
0110
0110
0110
0110
1011
1011
1011
1011
1011
1011
1011
1011
1011
0001
1011
0110
1011
0110
0110
0000
1011
1010
0110
1011
1011
1011
1011
1011
1011
1011
1011
1001
1001
1000
1011
1011
1011
1011
1011
1011
1011
1011
0011
0110
1011
1011

1110
1110
SHFT
1000
1111
0001
1110
0000
0010
0011
1110
1111
1110
1110
1111
1110
1110
1110
1110
1110
SHFT
1111
1010
1001
1001
1011
1000
1110
0000
1101
1111
1110
1110
1110
1110
1110
1110
1110
lSHF
OSHF
1000
1110
1110
1110
1110
1110
1110
1110
1110
SHFT
0101
1010
1111

~TEXAS

INSTRUMENTS
9-104

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0000 0000
0001 0001
IAAA AAAA
IIlI IlIl

1001 SHFT
IAAA AAAA

0001 0000
IAAA
IAAA
IAAA
lAAA

AAAA
AAAA
AAAA
AAAA

1011
1000
0001
1110
0000
0001
0001
0001
0001

SHFT
0001
0010
SHFT
0001
1011
1100
1101
1111

IAAA AAAA

1000 SHFT
lAAA
IIII
lAAA
IAAA
IAAA

AAAA
IIII
AAAA
AAAA
AAAA

0000 0010
lAAA AAAA
lAAA AAAA

1100
1000
0001
0000
0001
0000
0001
0001

SHFT
0010
0011
1100
0100
1101
0101
1110

IAAA AAAA
IAAA AAAA
lAAA AAAA

0101
0101
0001
0001
0000
0001
0000
0001

1010
1011
1000
1001
1001
0110
1010
0111

lAAA AAAA
IAAA AAAA
1111 1111

1010 SHFT

WORDS

CYCLES

1
1
1
1
2
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2

1
1
1
1

2
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
2
1
1
1
1
1 or 2
1
1
1
2
2
1
1
1
1
1
1
1
1
1 or 2
1
1
1
1
1
1
1
1
1
1
1
2

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
ACCUMULATOR MEMORY REFERENCE INSTRUCTIONS (CONTINUED)
INSTRUCTION

MNEMONIC

Subtract from ACC with borrow
Conditional subtract
Subtract from ACC with sign extension suppressed
Subtract from ACC, shift specified by TREG1 [3-0]
XOR ACC with data value
XOR with ACC long immediate with shift
XOR with ACC long immediate with shift of 16
XOR ACCB with ACC
Zero ACC, load high ACC with rounding
Zero ACC and product register

SUBB
SUBC
SUBS
SUBT
XOR
XOR
XOR
XORB
ZALR
ZAP

OPCODE
0110
0000
0110
0110
0110
1011
1011
1011
0110
1011

0100
1010
0110
0111
1100
1111
1110
1110
1000
1110

IAAA
IAAA
IAAA
IAAA
IAAA
1101
1000
0001
IAAA
0101

AAAA
AAAA
AAAA
AAAA
AAAA
SHFT
0011
1010
AAAA
1001

WORDS

CYCLES

1
1
1
1
1
2
2
1
1
1

WORDS

CYCLES

1
1
1
1
2
1
1
1
1
1

1
1
1
1
2
2
2
1
1
1

WORDS

CYCLES

2
1
1
2
2
2
2
2
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1

4
4
2
20r4
2
20r4
2
2
4
2
4
2
20r4
2
4
4
4
20r4
2
2
4
4
4
1

AUXILIARY REGISTERS AND DATA PAGE POINTER INSTRUCTIONS
INSTRUCTION
Add to AR short immediate
Compare AR with CMPR
Load AR from addressed data
Load AR short immediate
Load A~ long immediate
Load data page pointer with addressed data
Load data page immediate
Modify auxiliary register
Store AR to addressed data
Subtract from AR short immediate

MNEMONIC
AORK
CMPR
LAR
LAR
LAR
LOP
LOP
MAR
SAR
SBRK

OPCODE
0111
1011
0000
1011
1011
0000
1011
1000
1000
0111

1000
1111
OARX
OARX
1111
1101
1101
1011
OARX
1100

IIII
0100
lAAA
IIII
0000
lAAA
IIII
lAAA
lAAA
IIII

IIII
01eM
AAAA
IIII
1ARX
AAAA
IIII
AAAA
AAAA
IIII

BRANCH INSTRUCTIONS
INSTRUCTION
Branch unconditional with AR update
Branch addressed by ACC
Branch addressed by ACC delayed
Branch AR "* 0 with AR update
Branch AR "* 0 with AR update delayed
Branch conditional
Branch conditional delayed
Branch unconditional with AR update delayed
Call subroutine addressed by ACC
Call subroutine addressed by ACC delayed
Call unconditional with AR update
Call unconditional with AR update delayed
Call conditional
Call conditional delayed
Software interrupt
Nonmaskable interrupt
Return
Return conditional
Return conditionally, delayed
Return, delayed
Return from interrupt with enable
Return from interrupt
Trap
Execute next one or two INST on condition

MNEMONIC
B
BACC
BACCO
BANZ
BANZD
BCNO
BCNOO
BO
CALA
CALAO
CALL
CALLO
CC
CCO
INTR
NMI
RET
RETC
RETCO
RETO
RETE
RETI
TRAP
XC

OPCODE
0111
1011
1011
0111
0111
1110
1111
0111
1011
1011
0111
0111
1110
1111
1011
1011
1110
1110
1111
1111
1011
1011
1011
111N

1001
1110
1110
1011
1111
OOTP
OOTP
1101
1110
1110
1010
1110
10TP
10TP
1110
1110
1111
11TP
11TP
1111
1110
1110
1110
01TP

1AAA
0010
0010
1AAA
1AAA
ZLve
ZLve
1AAA
0011
0011
1AAA
1AAA
ZLve
ZLve
0111
0101
0000
ZLve
ZLve
0000
0011
0011
0101
ZLve

AAAA
0000
0001
AAAA
AAAA
ZLve
ZLve
AAAA
0000
llOl
AAAA
AAAA
ZLve
ZLve
NTR#
0010
0000
ZLve
ZLve
0000
1010
1000
0001
ZLve

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-105

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
1/0 AND DATA MEMORY OPERATIONS
INSTRUCTION

MNEMONIC

Block move from data to data memory
Block move data to data DEST long immediate
Block move data to data with source in BMAR
Block move data to data with DEST in BMAR
Block move data to PROG with DEST in BMAR
Block move from program to data memory
Block move PROG to data with source in BMAR
Data move in data memory
Input external access
Load memory-mapped register
Out external access
Store memory-mapped register
Table read
Table write

BLDD
BLDD
BLDD
BLDD
BLDP
BLPD
BLPD
DMOV
IN
LMMR
OUT
SMMR
TBLR
TBLW

OPCODE
1010
1010
1010
1010
0101
1010
1010
0111
1010
1000
0000
0000
1010
1010

1000
1001
1100
1101
0111
0101
0100
0111
1111
1001
1100
1001
0110
0111

IAAA AAAA
IAAA AAAA
lAAA AAAA
IAAA AAAA
IAAA AAAA
lAAA AAAA
lAAA AAAA
lAAA AAAA
IAAA AAAA
lAAA AAAA
lAAA AAAA
IAAA AAAA
IAAA AAAA
lAAA AAAA

WORDS

CYCLES

2
2
1
1
1
2
1
1
2
2
2
2
1
1

3
3
2
2
2
3
2
1
2
2or3
3
2or3
3
3

WORDS

CYCLES

1
2
1
2
1
2
2
1
2

WORDS

CYCLES

1
1
1
1
1
1
1
1
2
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1

1
1
1
1
1
1
1
1
3
3
3
3
1
1
2
1
1
1
1
1
1
1
1
1
1
1

PARALLEL LOGIC UNIT INSTRUCTIONS
INSTRUCTION

MNEMONIC

AND DBMR with data value
AND long immediate with data value
Compare DBMR to data value
Compare data with long immediate
OR DBMR to data value
OR long immediate with data value
Store long immediate to data
XOR DBMR to data value
XOR long immediate with data value

APL
APL
CPL
CPL
OPL
OPL
SPLK
XPL
XPL

OPCODE
0101
0101
0101
0101
0101
0101
1010
0101
0101

1010
1110
1011
1111
1001
1101
1110
1000
1100

IAAA AAAA
lAAA AAAA
lAAA AAAA
IAAA AAAA
IAAA AAAA
lAAA AAAA
IAAA AAAA
lAAA AAAA
lAAA AAAA

T REGISTER, P REGISTER, AND MULTIPLY INSTRUCTIONS
INSTRUCTION

OPCODE

MNEMONIC

Add PREG to ACC
Load high PREG
Load TREGO
Load TREGO and accumulate previous product
Load TREGO, accumulate previous product, and move
data
Load TREGO and load ACC with PREG
Load TREGO and subtract previous product
Multiply/accumulate
Multiply/accumulate with data shift
MulVACC w/source ADRS in BMAR and DMOV
MulVACC with source address in BMAR
Multiply data value times TREGO
Multiply TREGO by 13-bit immediate
Multiply TREGO by long immediate
Multiply TREGO by data, add previous product
Multiply TREGO by data, ACC - PREG
Multiply unsigned data value times TREGO
Load ACC with product register
Subtract product from ACC
Store high product register
Store low product register
Set PREG shift count
Data to TREGO, square it, add PREG to ACC
Data to TREGO, square it, ACC - PREG
Zero product register

APAC
LPH
LT
LTA
LTD

1011
0111
0111
0111
0111

1110
0101
0011
0000
0010

LTP
LTS
MAC
MACD
MADD
MADS
MPY
MPY
MPY
MPYA
MPYS
MPYU
PAC
SPAC
SPH
SPL
SPM
SORA
SORS
ZPR

0111
0111
1010
1010
1010
1010
0101
1101
1011
0101
0101
0101
1011
1011
1000
1000
1011
0101
0101
1011

0001
0100
0010
0011
1011
1010
0100

IAAA AAAA
IAAA AAAA
IAAA AAAA
IAAA AAAA
IAAA AAAA
IAAA AAAA
lAAA AAAA
lAAA AAAA
lAAA AAAA
IAAA AAAA
lAAA AAAA

IIII IIII IIII

1110
0000
0001
0101
1110
1110
1101
1100
1111
0010
0011
1110

~TEXAS

INSTRUMENTS
9-106

0000 0100

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1000 0000
IAAA AAAA
IAAA AAAA
lAAA AAAA

0000 0011
0000 0101
lAAA AAAA
lAAA AAAA

0000 OOPM
IAAA AAAA
IAAA AAAA

0101 1000

TiViS320C5x, TiV1S320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

instruction set summary (continued)
Table 7. TMS320C5x Instruction Set Opcodes (Continued)
CONTROL INSTRUCTIONS
INSTRUCTION

MNEMONIC

Test bit specified immediate
Test bit in data value as specified by TREG2 [3-0]
Reset overflow mode
Reset sign extension mode
Reset hold mode
ResetTC bit
Reset carry
Reset CNF bit
Reset INTM bit
Reset XF pin
Idle
Idle until interrupt - low-power mode
Load status register 0
Load status register 1
No operation
Pop PC stack to low ACC
Pop stack to data memory
Push data memory value onto PC stack
Push low ACC to PC stack
Repeat instruction as specified by data
Repeat next INST specified by long immediate
Repeat INST specified by short immediate
Block repeat
Clear ACC/PREG and repeat next INST long immediate
Set overflow mode
Set sign extension mode
Set hold mode
SetTC bit
Set carry
Set XF pin high
Set CNF bit
Set INTM bit
Store status register 0
Store status register 1

BIT
BITT
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
CLRC
IDLE
IDLE2
LST
LST
NOP
POP
POPD
PSHD
PUSH
RPT
RPT
RPT
RPTB
RPTZ
SETC
SETC
SETC
SETC
SETC
SETC
SETC
SETC
SST
SST

WORDS

OPCODE
0100
0110
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
0000
0000
1000
1011
1000
0111
1011
0000
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1011
1000
1000

BITX IAAA AAAA
1111 IAAA AAAA

1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111
1011
1110
1010
0110
1110
1011
1110
1011
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1110
1111

0100
0100
0100
0100
0100
0100
0100
0100
0010
0010
lAM
lAAA
0000
0011
lAAA
lAAA
0011
lAAA
1100
1111
1100
1100
0100
0100
0100
0100
0100
0100
0100
0100
lAM
lAAA

0010
0110
1000
1010
1110
0100
0000
1100
0010
0011
AAAA
AAM
0000
0010
MM
AAAA
1100
AAM
0100
1111
0110
0101
0011
0111
1001
1011
1111
1101
0101
0001
AAAA
AAAA

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
1
1
1
1
1
1
1
1
1
1

CYCLES
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1

development support
Texas Instruments offers an extensive line of development tools for the 'C5x generation of DSPs, including tools
to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully
integrate and debug software and hardware modules.
The following products support development of 'C5x-based applications:

Software Development Tools:
Assembler/Linker
Simulator
Optimizing ANSI C compiler
Application algorithms
C/Assembly debugger and code profiler

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-107

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

development support (continued)
Hardware Development Tools:
Extended development set (XDSTM) emulator (supports 'C5x multiprocessor system debug)
'C5x EVM (Evaluation Module)
'C5x DSK (DSP Starter Kit)
The TMS320 Family Development Support Reference Guide (SPRU011) contains information about
development support products for all TMS320 family member devices, including documentation. Refer to this
document for further information about TMS320 documentation or any other TMS320 support products from
Texas Instruments. There is an additional document, the TMS320 Third Party Support Reference Guide
(SPRU052), which contains information about TMS320-related products from other companies in the industry.
To receive copies of TMS320 literature, contact the Literature Response Center at 800/477-8924.
See Table 8 for complete listings of development support tools for the 'C5x. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.

Table 8. TMS320C5x, TMS320LC5x Development Support Tools
DEVELOPMENT TOOL

PLATFORM

PART NUMBER

Software
Compiler/Assembler/Linker

PC-DOSTM, OS/2TM

TMDS3242855-02

Compiler/Assembler/Linker

SPARCTM, HpTM

TMDS3242555-08

Assembler/Linker

PC-DOS, OS/2TM

TMDS3242850-02

Simulator

PC-DOS, WINTM

TMDS3245851-02

Simulator

SPARC

TMDS3245551-09

Digital Filter Design Package

PC-DOS

Debugger/Emulation Software

PC-DOS, OS/2, WIN

TMDS3240150

SPARCTM

TMDS3240650

Debugger/Emulation Software

DFDP

Hardware
XDS-510 XL Emulator

PC-DOS, OS/2

XDS-510 WS Emulator

SPARC

EVM Evaluation Module

PC-DOS, WIN

TMDS3260050

PC-DOS

TMDS3200051

DSK DSP Starter Kit

TMDOO0510
TMDSOO0510WS

device and development support tool nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all TMS320
devices and support tools. Each TMS320 member has one of three prefixes: TMX, TMP, or TMS. Texas
Instruments recommends two of three possible prefix designators for its support tools: TMDX and TMDS. These
prefixes represent evolutionary stages of product development from engineering prototypes (TMX/TMDX)
through fully qualified production devices/tools (TMS/TMDS). This development flow is defined below.
Device development evolutionary flow:

TMX

Experimental device that is not necessarily representative of the final device's electrical
specifications

TMP

Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification

PC-DOS and OS/2 are trademarks of International Business Machines Corp.
SPARC is a trademark of SPARC International, Inc.
WIN is a trademark of Microsoft Corporation.
HP is a trademark of Hewlett-Packard Company.
XDS is a trademark of Texas Instruments Incorporated.

~TEXAS

INSTRUMENTS
9-108

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

device and development support tool nomenclature (continued)
TMS

Fully-qualified production device

Support tool development evolutionary flow:
TMDX

Development support product that has not yet completed Texas Instruments internal qualification
testing.

TMDS

Fully qualified development support product

TMX and TMP devices and TMDX development support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development support tools have been characterized fully, and the quality and reliability
of the device has been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system because their
expected end-use failure rate still is undefined. Only qualified production devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type
(for example, N, FN, or GB) and temperature range (for example, L). Figure 8 provides a legend for reading the
complete device name for any TMS320 family member.
TMS 320

(B)

TMX =
TMP =
TMS =
SMJ =
SM =

(L)

PREFIX _ _ _ _ _......1

experimental device
prototype device
qualified device
MIL-STD-883C
High Rei (non-883C)

DEVICE FAMILY - - - - - - - '
320 = TMS320 Family
LOW VOLTAGE OPTION (3.3V)
BOOT LOADER OPTION

--------1

TECHNOLOG¥------------~

C
CMOS
E = CMOS EPROM

TEMPERATURE RANGE (DEFAULT: 0 TO 70 D C)
H = 0 to 50 D C
L == 0 to 70 D C
S == -55 to 100 D C
M == -55to 125°C
A = -40 to 85°C
PACKAGE TYPE
N
plastic DIP
J
ceramic CER-DIP
JD
ceramic DIP side-brazed
GB
ceramic PGA
FZ
ceramic CER-OUAD
FN
plastic leaded CC
FD
ceramic leadless CC
PJ
100-pin plastic EIAJ OFP
PO
132-pin plastic bumpered OFP
PZ
100-pin plastic TOFP
PBK == 128-pin plastic TOFP
PG E == 144-pin plastic TQFP
DEVICE
'C1x DSP:

'C3x DSP:
10
14
15
16
17

30
31
32
'C4x DSP:
40
44

'C2x DSP:
25
26
'C2xx DSP:
203
209

'C5x DSP:
50
51
52
53
56
57

Figure 8. TMS320 Device Nomenclature

•
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INSTRUMENTS
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9-109

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

documentation support
Extensive documentation supports all TMS320 family generations of devices from product announcement
through applications development. The types of documentation available include data sheets, such as this
document, with design specifications, complete user's guides for all devices, development support tools, and
three volumes of the publication Digital Signal Processing Applications with the TMS320 Family (literature
numbers SPRA012, SPRA016, and SPRA017).
The application book series describes hardware and software applications, including algorithms, for fixed and
floating point TMS320 family devices. The TMS320C5x User's Guide (literature number SPRU056), which
describes in detail the fifth-generation TMS320 products, is currently available.
A series of DSP textbooks is published by Prentice-Hall and John Wiley & Sons to support digital signal
processing research and education. The TMS320 newsletter, Details on Signal Processing, is published
quarterly and distributed to update TMS320 customers on product information. The TMS320 DSP bulletin board
service (BBS) provides access to information pertaining to the TMS320 family, including documentation, source
code and object code for many DSP algorithms and utilities. The BBS can be reached at 713/274-2323.
Information regarding TI DSP products is also available on the Worldwide Web at http:/www.tLcom uniform
resource locator (URL).

•
TEXAS
INSTRUMENTS
9-110

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

absolute maximum ratings over operating ambient-air temperature range (unless otherwise noted)
(,320C5x only)t
Supply voltage range, Voo (see Note 3) ............................................. - 0.3 V to 7 V
Input voltage range, VI .............................................................. - 0.3 V to 7 V
Output voltage range, Va ........................................................... - 0.3 V to 7 V
Operating ambient temperature range, TA ............................................ -40°C to 85°C
Operating case temperature, T C ...................................................... O°C to 85°C
Storage temperature range, Tstg .................................................. - 55°C to 150°C

recommended operating conditions (,320C5x only)
VOO

Supply voltage

VSS

Supply voltage

High-level input voltage

Low-level input voltage

IOH

High-level output current (see Note 4)

IOL

Low-level output current

Operating case temperature

Operating ambient temperature

MAX

UNIT

5.25

V
V

VOO+0.3

2.5

VOO+0.3

X2/CLKIN, CLKIN2, CLKX, CLKR, TCLKX, TCLKR

-0.3

0.7

All other inputs

-0.3

0.8

CLKX,CLKR,TCLKX,TCLKR
All other inputs

VIL

NOM

0
X2/CLKIN, CLKIN2

VIH

MIN
4.75

-300+

Il A

-40

+ This IOH can be exceeded when using a 1-kQ pulldown resistor on the TOM serial port TAOO output; however, this output still meets VOH
specifications under these conditions.
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.

~TEXAS

INSTRUMENTS
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9-111

TMS320C5x, TMS320LC5x
. DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

electrical characteristics over recommended ranges of supply voltage and operating ambient-air
temperature (unless otherwise noted) (,320C5x only)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage (see Note 4)

10H = 300 JlA

VOL

Low-level output voltage (see Note 4)

IOL=2 mA

10Z

High-impedance output current (VOO = 5.25 V)

Input current (VI = VSS to VOO)

IOO(pins)

Supply current, core CPU

Supply current, pins

IOO(standby) Supply current, standby

MAX

-500

All other 3-state outputs

-20

-10

800

TMS, TCK, TOI (with internal pull ups)

-500

-50

X2/CLKIN

-10

V
JlA

JlA

fx =40 MHz,

VOO = 5.25 V

fx = 57 MHz,

VOO = 5.25 V

fx = 80 MHz,

VOO = 5.25 V

fx = 100 MHz,

VOO = 5.25 V

110

fx = 40 MHz,

VOO = 5.25 V

fx = 57 MHz,

VOO = 5.25 V

fx = 80 MHz,

VOO = 5.25 V

fx = 100 MHz,

VOO = 5.25 V

IOLE2, divide-by-two clock mode, clocks
shut off

UNIT
V

0.6

SR (with internal pull up)

All other inputs

IOO(core)

TYP:j:

2.4

0.3

TRST (with internal pulldown)
II

MIN

JlA

Input capacitance

Output capacitance

tTypical values are at VOO = 5 V, TA = 25°C, unless otherwise specified.
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels.

~TEXAS

INSTRUMENTS
9-112

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

absolute maximum ratings over specified temperature range (unless otherwise noted) (,320LC5x
only)t
Supply voltage range, Voo (see Note 3) ............................................... -0.3 V to 5 V
Input voltage range, VI .............................................................. -0.3 V to 5 V
Output voltage range, Va ............................................................ -0.3 V to 5 V
Operating ambient temperature range, TA . .'........................................... -40° to 85°C
Operating case temperature, T C ...................................................... O°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55° to 150°C

recommended operating conditions (,320LC5x only)
Voo

Supply voltage

Vss

Supply voltage

VIH

High-level input voltage

VIL

Low-level input voltage

IOH

High-level output current

IOL

Low-level output current

Operating case temperature

MIN

NOM

3.13

3.3

MAX

UNIT

3.47

X2/CLKIN, CLKIN2

2.5

VOO + 0.3

CLKX,CLKR,TCLKX,TCLKR

2.0

VOO + 0.3

All other inputs

1.8

VOO + 0.3

X2/CLKIN, CLKIN2, CLKX,
CLKR,TCLKX,TCLKR

-0.3

0.5

All other inputs

-0.3

Operating ambient temperature

V
V

0.6

V
V

-300+

°C

-40

°C

+ ThiS IOH may be exceeded when using a 1-kn pulldown resistor on the TOM serial port TAOO output; however, this output still meets VOH
specifications under these conditions.

•
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9-113

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) ('320LC5x only)
PARAMETER

TEST CONDITIONS

VOH

High-level output voltage
(see Note 4)

IOH = 300 JlA

VOL

Low-level output voltage
(see Note 4)

IOL= 2 mA

IOZ

High-impedance output current
(VOO = 3.47 V)

0.4
0.3+

IOL = 20 JlA
BR (with internal pull up)

-500

All other 3-state outputs

-20

-10

800

TMS, TCK, TOI pins (with internal pullups)

100(core)

100(pins)

Supply current, core CPU

Supply current, pins

-500

X2/CLKIN (oscillator enabled)

-50

X2/CLKIN (oscillator disabled)

-10

All other inputs

-10

JlA

fx = 40 MHz,

VOO = 3.47 V

fx = 50 MHz,

VOO = 3.47 V

fx = 80 MHz,

VOO = 3.47 V

fx = 40 MHz,

VOO = 3.47 V

fx = 50 MHz,

VOO = 3.47 V

fx = 80 MHz,

VOO = 3.47 V

IOLE2, divide-by-two clock mode, clocks
shutoff

100(standby) Supply current, standby

UNIT
V

VOO-0.3+

IOH =20 JlA

Input current (VI = VSS to VOO)

MAX

2.0

TRST(with internal pulldown)

TYPt

MIN

JlA

Input capacitance

Output capacitance

t All typical values are at VOO = 3.3 V, TA = 25°C.
+ Values derived from characterization data and not tested
NOTE 4: Figure 9 shows the test load circuit and Figure 10 and Figure 11 show the voltage reference levels .

•
TEXAS
INSTRUMENTS
9-114

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

PARAMETER MEASUREMENT INFORMATION
-1

Tester Pin
Electronics

I
I
I
I
I
I
CTI
I
I
-=I

VLoad

Output
Under
Test

Where:

IOL
IOH
VLOAD
CT

2 mA (all outputs) minimum
300 /lA (all outputs) minimum
1.5 V
80-pF typical load circuit capacitance

Figure 9. Test Load Circuit

signal transition levels
The data in this section is shown for both the 5-V version ('C5x) and the 3.3-V version ('LC5x). In each case,
the 5-V data is shown followed by the 3.3-V data in parentheses. TIL-output levels are driven to a minimum
logic-high level of 2.4 V (2 V) and to a maximum logic-low level of 0.6 V (0.4 V). Figure 10 shows the TTL-level
outputs.
2.4 V (2 V)
2 V (1.6 V)

1 V (0.8 V)
0.6 V (0.4 V)

Figure 10. TIL-Level Outputs
TIL-output transition times are specified as follows:
•

For a high-to-Iow transition, the level at which the output is said to be no longer high is 2 V (1.6 V), and the
level at which the output is said to be low is 1 V (0.8 V).

•

For a low-to-high transition, the level at which the output is said to be no longer low is 1 V (0.8 V), and the
level at which the output is said to be high is 2 V (1.6 V).

Figure 11 shows the TIL-level inputs.

2V(l.8V)

0.8 V (0.6 V)

Figure 11. TTL-Level Inputs
TIL-compatible input transition times are specified as follows:
•

For a high-to-Iow transition on an input signal, the level at which the input is said to be no longer high is
2 V (1.8 V), and the level at which the input is said to be low is 0.8 V (0.6 V).

•

For a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V (0.6 V), and the level at which the input is said to be high is 2 V (1.8 V) .

•
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

Letters and symbols and their meanings:

access time

cycle time (period)

Low

delay time

Valid

dis

disable time

High impedance

enable time

High

fail time
h

hold time

setup time

rise time
transition time
v

valid time

pulse duration (width)

Unknown, changing, or don't care level

~TEXAS

INSTRUMENTS

9-116

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

CLOCK CHARACTERISTICS AND TIMING
The 'CSx can use either its internal oscillator or an external frequency source for a clock. The clock mode is
determined by the clock mode pins (CLKMD1, CLKMD2, and CLKMD3). Table 9 shows the standard clock
options available on the 'csa, 'LCSa, 'CS1, 'LCS1, 'CS2, 'LCS2, 'CS3, 'LCS3, 'CS3S, and 'LCS3S. For these
devices, the CLKIN2 pin functions as the external frequency input when using the PLL options. An expanded
set of clock options is shown in Table 1a and is available on the 'LCS6, 'CS7S, and 'LCS7 devices. For these
devices, X2/CLKIN functions as the external frequency input when using the PLL options.

Table 9. Standard Clock Options
CLKMD1

CLKMD2

PLL clock generator optiont

Reserved for test purposes

External divide-by-two option or internal divide-by-two clock option
with an external crystal

External divide-by-two option with the internal oscillator disabled

CLOCK SOURCE

t PLL multiply-by-one option on 'C5a, 'C51, 'C53, 'C53S devices, PLL multiply-by-two option on
'C52 device

Table 10. PLL Clock Option for 'LC56, 'C57S, and 'LC57
CLKMD1

CLKMD2

CLKMD3

CLOCK SOURCE
PLL multiply-by-three

PLL multiply-by-four

PLL multiply-by-five

PLL multiply-by-nine

External divide-by-two option with oscillator disabled

PLL multiply-by-two

PLL multiply-by-one

External/Internal divide-by-two with oscillator enabled

.T~XAS

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9-117

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A- APRIL 1995 - REVISED APRIL 1996

internal divide-by-two clock option with external crystal
The internal oscillator is enabled by connecting a crystal across X1 and X2/CLKIN. The frequency of CLKOUT1
is one-half of the crystal's oscillating frequency. The crystal should be in either fundamental or overtone
operation and parallel resonant, with an effective series resistance of 30 n and a power dissipation of 1 mW;
it should be specified at a load capacitance of 20 pF. Overtone crystals require an additional tuned-LC circuit.
Figure 12 shows an external crystal (fundamental frequency) connected to the on-chip oscillator.

recommended operating conditions for internal divide-by-two clock option
MIN
TMS320CSx-40
TMS320CSx-S7
TMS320CSx-80
fclk

Input clock frequency

TMS320CSx-100+
TMS320LCSx-40
TMS320LCSx-SO
TMS320LCSx-80

C1, C2 Load capacitance
at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements.
+ '320CS1, '320CS2 currently available at this clock speed

X2/CLKIN

Crystal

-----101--....
Figure 12. Internal Clock Option

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

00.

MAX

UNIT

40.96
S7.14
80

MHz

100
40
SO

MHz

80
10

t This device utilizes a fully static design and, therefore, can operate with input clock cycle time (tc(CI)) approaching

9-118

NOM

ot
ot
ot
ot
ot
ot
ot

The device is characterized

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

external divide-by-two clock option
An external frequency source can be used by injecting the frequency directly into X2/CLKIN with X1 left
unconnected. Refer to Table 9 and Table 10 for appropriate configuration of the CLKMD1, CLKMD2 and
CLKMD3 pins to generate the external divide-by-2 clock option. The external frequency injected must conform
to the specifications listed in the timing requirements table.

switching characteristics over recommended operating conditions [H = 0.5 tc(co)l (,320C5x only)
(see Figure 13)
'320C5x-40

PARAMETER
tciCO}

Cycle time, CLKOUT1

td(CIH-COH/L)

Delay time, X2ICLKIN high to CLKOUT1 highllow

'320C5x-57

TYP

MAX

MIN

TYP

48.8

2tc (CI)
11

2tc (CI)

MAX

UNIT

MIN

tf(CO)

Fall time, CLKOUT1

tr(CO)

Rise time, CLKOUT1

tw(COL)

Pulse duration, CLKOUT110w

H-3

H +2

H-3

H+2

tw(COH)

Pulse duration, CLKOUT1 high

H-3

H +2

H-3

H+2

'320C5x-80

PARAMETER

'320C5x-100

. MIN

TYP

MAX

MIN

TYP

2tc (CI)
9

2tc (CI)

MAX

UNIT
ns

tc(CO)

Cycle time, CLKOUT1

td(CIH-COH/L)

Delay time, X2/CLKIN high to CLKOUT1 high/low

tf(CO)

Fall time, CLKOUT1

tr(CO)

Rise time, CLKOUT1

tw(COL)

Pulse duration, CLKOUT1 low

H-3

H+2

H-3

H+2

tw(COH)

Pulse duration, CLKOUT1 high

H-3

H +2

H-3

H +2

switching characteristics over recommended operating conditions [H
(see Figure 13)
'320LC5x-40

PARAMETER
tc(CO)

Cycle time, CLKOUT1

td(CIH-COH/L)

Delay time, X2/CLKIN high to
CLKOUT1 high/low

ns
ns
ns

=0.5 tc(CO)l (,320LC5x only)

'320LC5x-50

UNIT

'320LC5x-80

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

MAX

2tc (CI)

2tc (CIl

2tciCI)

UNIT

tliCO)

Fall time, CLKOUT1

tr(CO)

Rise time, CLKOUT1

tw(COL)

Pulse duration, CLKOUT1 low

H-3

H +2

H-3

H +2

H-3

H +2

tw(COH)

Pulse duration, CLKOUT1 high

H-3

H +2

H-3

H +2

H-3

H+2

t This device utilizes a fully static design and, therefore, can operate with tc(CI) approaching infinity. The device is characterized at frequencies
approaching 0 Hz but is tested at tc(CO) = 300 ns to meet device test time requirements .

•
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9-119

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (,320C5x only) (see Figure 13)
'320C5x-4O
MIN

'320C5x-57

'320C5x-80

MAX

MIN

MAX

MIN

MAX

MIN

MAX

17.5

12.5

24.4

'320C5x-100

UNIT

tc(CI)

Cycle time, X2/CLKIN

tt(CI)

Fall time, X2/CLKIN+

tr(CI)

Rise time, X2/CLKIN+

tw(CIL)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

t
t

tw(CIH)

t
t

8
8

5
5

t
t

5
5

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (,320LC5x only) (see Figure 13)
'320LC5x-40
MIN

MIN

'320lC5x-80

'320lC5x-50

MAX

MIN

12.5

UNIT

MAX

tc(CI)

Cycle time, X2/CLKIN

tf(CI)

Fall time, X2/CLKIN+

tr(CI)

Rise time, X2/CLKIN+

tw(CIL)

Pulse duration, X2/CLKIN low

Pulse duration, X2/CLKIN high

t
t

tw(CIH)

t
t

9
9

t
t

5
5

t This device utilizes a fully static design and, therefore, can operate with tc(CI) approaching The device is characterized at frequencies
approaching 0 Hz, but is tested at a minimum of tc(CI) = 150 ns to meet device test time requirements.
00.

+ Values derived from characterization data and not tested

~tw(Cll)

MtW(CIH)

ClKIN
!+--tc(CO) ----+I
I
tw(COH)
!+- td(CIH-COH/l)
1

I..

ClKOUT1J

-+I
~I

~ tf(CI)
1
1

~ tr(CO)
1 I
~I I tw(COl)

-+l

Figure 13. External Divide-by-Two Clock Timing

~TEXAS

INSTRUMENTS
9-120

~ tf(CO)
1
I..

-+I I+- tr(CI)
II

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Ti\liS320C5x, TiViS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

PLL clock generator option
An external frequency source can be used by injecting the frequency directly into CLKIN2+ with X1 left
unconnected and X2 connected to VDD. This external frequency is multiplied by the factors shown in Table 9
and Table 1a to generate the internal machine cycle. The multiply-by-one option is available on the 'C5a, 'LC5a,
'C51, 'LC51, 'C53, 'LC53, 'C53S and 'LC53S. The multiply-by-two option is available on the 'C52 and 'LC52.
Multiplication factors of 1,2,3,4,5, and 9 are available on the 'LC56, 'LC57, 'C57S and 'LC57S. Referto Table 9
and Table 1a for appropriate configuration of the CLKMD1 , CLKMD2 and CLKMD3 pins to generate the desired
PLL multiplication factor. The external frequency injected must conform to the specifications listed in the timing
requirements table.

switching characteristics over recommended operating conditions [H = 0.5 tc(co)l (,320C5x only)
(see Figure 14)
'320C5x-40

PARAMETER

MIN

TYP

'320C5x-57
MAX

MIN

MAX

TYP

UNIT
ns

tc(CO)

Cycle time, CLKOUT1

tf(CO)

Fall time, CLKOUT1

tr(CO)

Rise time, CLKOUT1

tw(COL)

Pulse duration, CLKOUT1 low

H-3t

H +2t

H-3t

H +2t

tw(COH)

Pulse duration, CLKOUT1 high

H-3t

H +2t

H-3t

H +2t

td(C2H-COH)

Delay time, CLKIN2 high to CLKOUT1
high

td(TP)

Delay time, transitory phase-PLL
synchronized after CLKIN2 suppliedt

1OOOtc(C2)+

48.8

1OOOtc(C2)+

MIN

TYP

'320C5x-100

'320C5x-80

PARAMETER

MAX

MIN

TYP

MAX
45

UNIT
ns

tciGO)

Cycle time, CLKOUT1

tf(CO)

Fall time, CLKOUT1

tr(CO)

Rise time, CLKOUT1

tw(COL)

Pulse duration, CLKOUT1 low

H-3t

H +2t

H-3t

H +2t

tw(COH)

Pulse duration, CLKOUT1 high

H-3t

H +2t

H-3t

H +2t

td(C2H-COH)

Delay time, CLKIN2 high to CLKOUT1
high

td(TP)

Delay time, transitory phase-PLL
synchronized after CLKIN2 suppliedt

100OtC(C2):j:

1000tC(C2):j:

t Values assured by design and not tested
+ On the TMS320C57S devices, CLKIN2 functions as the PLL clock input.

•
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

switching characteristics over recommended operating conditions [H =0.5 tc(co)l (,320LC5x only)
(see Figure 14)
PARAMETER

'320LC5x-40
MIN

TYP

'320LC5x-50
MAX

MIN

75t

TYP

'320LC5x-80
MAX

MIN

75t

TYP

MAX

UNIT

tc(CO)

Cycle time,
CLKOUT1

td(C2H-COH)

Delay time,
CLKIN2 high to
CLKOUT1 high

tf(CO)

Fail time,
CLKOUT1

tr(CO)

Rise time,
CLKOUT1

tw(COL)

Pulse duration,
CLKOUT11ow

H-3+

H +2+

H-3+

H +2+

H-3+

H +2+

tw(COH)

Pulse duration,
CLKOUT1 high

H-3+

H +2+

H-3+

H +2+

H-3+

H + 2+

td(TP)

Delay time,
transitory
phase-PLL
synchronized
afterCLKIN2
supplied

100otc (C2)

t Clocks can only be stopped while executing IDLE2 when using the PLL clock generator option.
+ Values assured by design and not tested
§ On the 'LC56, 'LC57, and 'LC57S devices, CLKIN2 functions as the PLL clock input.

"TEXAS
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9-122

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55t

TMS320C5x, TiVlS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (,320C5x only) (see Figure 14)
'320C5x-40

tc(C2)

Cycle time, CLKlN2

tf(C2)

Fall time, CLKIN2~

IMultiply-by-onet
IMultiply-by-two§

'320C5x-S7

MAX

MIN

MAX

UNIT

48.8

.75:1:

75:1:

97.6

150:1:

t r(C2)

Rise time, CLKIN2~

tw(C2L)

Pulse duration, CLKlN2 low

tc (C2)-15

t c (C2)-11

tw(C2H)

Pulse duration, CLKlN2 high

t c (C2)-15

tc (C2)-11

'320C5x-80

IMultiply-by-onet
IMultiply-by-two§

'320CSx-100

MAX

MIN

MAX

UNIT

75:1:

150:1:

110:1:

tc(C2)

Cycle time, CLKIN2

tlfC2)

Fall time, CLKIN2~

tr (C2)

Rise time, CLKIN2~

tw(C2L)

Pulse duration, CLKlN2 low

tc(C2)-B

tc (C2)-7

tw(C2H)

Pulse duration, CLKlN2 high

t c (C21- 8

tclC2)-7

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (,320LC5x only) (see Figure 14)
'320LC5x-40

I Multiply-by-onet

'320LC5x-80

'320LC5x-50

MAX

MIN

MAX

MIN

MAX

UNIT

75:1:

37.5:1:

100

150:1:

110:1:

tc(C2)

Cycle time, CLKIN2

tf(C2)

Fall time, CLKIN2~

t r(C2)

Rise time, CLKIN2~

t w (C2L)

Pulse duration, CLKIN2 low

t c (C2) -15

tc (C2)-13

t c (C2) - 8

t w(C2H)

Pulse duration, CLKIN2 high

tcJC2t- 15

t c (C2)-13

t c (C2)-8

IMultiply-by-two§

5
5

t Not available on 'C52, 'LC52
:I: Clocks can be stopped only while executing IDLE2 when using the PLL clock generator option. The td(TP) (the transitory phase) occurs when
restarting clock from IDLE2 in this mode.
§ Available on 'C52, 'LC52, 'LC56, 'C57S, 'LC57, and 'LC57S
~ Values derived from characterization data and not tested
tw(C2L) ~

CLKIN2~~

~ i.-

td(C2H-COH)
te(CO)
14

1
1l1li
CLKOUT1

td(TP)

~(j~
~

--~.I

1 .1

Iii

14-

1 1 tr(C2)~

14-

1 1

-+I I+- tw(COH)
1 1

1 1
1 1

tf(C2)

-+I
1
1

tf(CO)~
1
1

II
Figure 14. PLL Clock Generator Timing

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9-123

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

MEMORY AND PARALLEL I/O INTERFACE READ

switching characteristics over recommended operating conditions [H
(see Figure 15)
'320C5x-40

PARAMETER

MIN

'320C5x-57

MAX

MIN

=O.5tc(co)1 (,320C5x only)

'320C5x-80

MAX

MIN

'320C5x-100

MAX

MIN

UNIT

tsu(AV-RDL)

Setup time, address valid before
RD lowt

H-10+

H-7+

H-6+

th(RDH-AV)

Hold time, address valid after RD
hight

tw(RDL)

Pulse duration, RD low§'Il#

H-2

tw(RDH)

Pulse duration, RD high§'Il#

H-2

td(CO-ST)

Delay time, CLKOUT1 to STRB
rising or falling edge§'Il

-1

td(CO-RD)

Delay time, CLKOUT1 to RD rising
or falling edge§'Il

-3

td(RDH-WELl

Delay time, RD high to WE low

H+2

H-2

H+2

H-2

H+2

H-2

-2

-3

2H-5

H-2

2H-4

switching characteristics over recommended operating conditions [H = O.5tc(co)1 (,320LC5x only)
(see Figure 15)
'320LC5x-40
'320LC5x-50

PARAMETER

MIN

'320LC5x-80
UNIT
MAX

MIN

tsu(AV-RDL)

Setup time, address valid before RD lowt

th(RDH-AV)

Hold time, address valid after RD hight

H-1O+

H-7+

tw(RDL)

Pulse duration, RD low§'Il#

H-2

tw(RDH)

Pulse duration, RD high§'Il#

H-2

td(RDH-WEL)

Delay time, RD high to WE low

2H-5

2H-4

td(CO-RD)

Delay time, CLKOUT1 to RD rising or falling edge§'Il

tdLCO-STl

Delay time, CLKOUT1 to STRB rising or falling edge§'Il

H+2

ns
ns

H+2

ns
ns
ns

-2

-3

-2

t AO-A15, PS, DS, IS, RIW, and BR timings all are included in timings referenced as address.
+ See Figure 16 for address bus timing variation with load capacitance.
§ These timings are for the cycles following the first cycle after reset, which is always seven wait states.
'11 Values are derived from characterization data and not tested.
# Timings are valid for zero wait-state cycles only.

~TEXAS

INSTRUMENTS
9-124

H-2

MAX

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

'CIVlS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H =O.5t c(co)1 (,320C5x only) (see Figure 15)
'320CSx-40
MIN

MAX

'320CSx-S7

'320CSx-80

MAX

MIN

MAX

MIN

'320CSx-100
MIN

MAX

UNIT

ta(RDAV)

Access time, read data from
address valid

2H-1St

2H -15t

2H -lOt

ta(RDL-RD)

Access time, read data after RD
low

H-10

H-7

H-6

tsu(RD-RDH)

Setup time, read data before RD
high

th(RDH-RD)

Hold time, read data after RD high

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = O.5tc(co)1 (,320LC5x only) (see Figure 15)
'320LCSx-40
'320LCSx-SO
MIN
ta(RDAV)

Access time, read data from address valid

tsu(RD-RDH)

Setup time, read data before RD high

th(RDH-RD)

Hold time, read data after RD high

ta(RDL-RD)

Access time, read data after RD low

MAX

'320LCSx-80
UNIT
MIN

2H -17t

MAX
2H-lOt

H-10

H-7

t See Figure 16 for address bus timing variation with load capacitance .

•
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9-125

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

MEMORY AND PARALLEL 1/0 INTERFACE WRITE
switching characteristics over recommended operating conditions [H
(see Figure 15)
'320C5x-40

PARAMETER

MIN

'320C5x-57

MAX

MIN

=O.5tc(co)1 (,320C5x only)

'320C5x-80

MAX

MIN

'320C5x-100

MAX

MIN

MAX

UNIT

tsu(AV-WEL)

Setup time, address valid
before WE lowt

H-5+

tsu(WDV-WEH)

Setup time, write data
valid before WE high

2H-20

th(WEH-AV)

Hold time, address valid
after WE high t

H-lO+

th(WEH-WDV)

Hold time, write data valid
after WE high

H-5

H + 10§

H-5

H + 10§

H-4

H + 7§

H-4

H +7§

tw(WEL)

Pulse duration, WElow§~

2H-2

2H + 2§

2H-2

2H +2§

2H-2

2H +2

2H-2

2H+2

twJWEH)

Pulse duration, WE high§

2H-2

td(CO-ST)

Delay time, CLKOUT1 to
STRB rising or falling
edge§

-1

-2

td(CO-WE)

Delay time, CLKOUT1 to
WE rising or falling edge§

-1

td(WEH-RDL)

Delay time, WE high to
RDlow

3H-10

3H-7

ten(WEL-BUd)

Enable time, WE low to
data bus driven

-5§

-4§

H-5+
2H§~

2H-20

H-4+
2H§~

2H-14

H -10+

H-3+
2H§~

H-7+

2H-2

ns
2H§~

2H-14
H -7+

2H-2

ns
ns

2H-2

switching characteristics over recommended operating conditions [H =O.5tc(co)1 (,320LC5x only)
(see Figure 15)
'320LC5x-40
'320LC5x-50

PARAMETER

MIN

'320LC5x-80
UNIT
MAX

MIN

2H§~

2H-14

MAX

tsu(AV-WEL)

Setup time, address valid before WE lowt

tsu(WDV-WEH)

Setup time, write data valid before WE high#

2H-20

th(WEH-AV)

Hold time, address valid after WE hight

H-10+

th(WEH-WDV)

Hold time, write data valid after WE high

H-5

H + 10§

H-4

H +7§

tw(WEL)

Pulse duration, WE low~§

2H-4

2H +2

2H-4

2H + 2

tw(WEH)

Pulse duration, WE high~

td(WEH-RDL)

Delay time, WE high to RD low

td{CO-ST)

Delay time, CLKOUT1 to STRB rising or falling edge~

-2

td(CO-WE)

Delay time, CLKOUT1 to WE rising or falling edge~

-1

H-7+

H-4+

ns
2H§'Il

H-7+

2H-2

3H-10

3H-7

ns
ns

-5§
-4§
Enable time, WE to data bus driven
ns
ten(WE-BUdl
t AO-A15, PS, DS, IS, R/W, and BR timings are all included in timings referenced as address.
+ See Figure 16 for address bus timing variation with load capacitance.
§ Values derived from characterization data and not tested
~ This value holds true for zero wait states or one software wait state only.
# STRB and WE edges are 0-4 ns from CLKOUT1 edges on writes. Rising and falling edges of these signals track each other; tolerance of resulting
pulsewidths is ±2 ns, not ±4 ns.

•
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INSTRUMENTS
9-126

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

MEMORY AND PARALLEL 1/0 INTERFACE WRITE (CONTINUED)

AO-A15 - {

~
I
I

ta(RDAV)

DATA

&>j

tsu(R6-RDH)
1

I...

i@9<
.1

II...

th(RDH-RD)1

tsu(AV-RDL)

tsu(AV-WEL)

-+I i+VALID

~rj

i
~I !I
1

ta(RDL-RD)
I

th(RDH-AV)

RIW

:X~

VALID

tw(WEL)

---+i

tw(WEH)

~:.- )t~(CO-RD) ~!IO-I--------------.;;I/Y:
STRB

_______ I

td(CO-WE~
CLKOUT1

\\.----J1

1--

td(WEH-RDL) ...,

~I"----'I

td(CO-S~

I+-

NOTES: A. All timings are for 0 wait states. However, external writes always require two cycles to prevent external bus conflicts. The diagram
illustrates a one-cycle read and a two-cycle write and is not drawn to scale. All external writes immediately preceded by an external
read or immediately followed by an external read require three machine cycles.
B. Refer to Appendix B of TMS320C5x User's Guide (literature number SPRU056) for logical timings of external interface.

Figure 15. Memory and Parallel I/O Interface Read and Write Timing

•
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9-127

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

MEMORY AND PARALLEL 1/0 INTERFACE WRITE (CONTINUED)
I/)

2.00

J"c:

1.75

j::

1.50

gj 1.25

m
~

.!:
C!)

0.75

0.50

.:g
()

0.25

..."

,.,Vi-""'"

,..,..V

1.00

.t;

.,- -"

..,..,.. V
10

Change in Load Capacitance - pF

Figure 16. Address Bus Timing Variation With Load Capacitance

9-128

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100

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

READY TIMING FOR EXTERNALLY-GENERATED WAIT STATES

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (see Note 5) (see Figure 17 and Figure 18)
'320C5x·-40
'320C5x-57
'320LC5x-40
'320LC5x-50
MIN

MAX

'320C5x-80
'320LC5x-80
MIN

MAX

'320C5x-100
UNIT
MIN

MAX

tsu(RY-COH)

Setup time, READY before CLKOUT1 rising edge

tsu(RY-RDL)

Setup time, READY before RD falling edge

th(COH-RYH)

Hold time, READY after CLKOUT1 rising edge

th(RDL-RYj

Hold time, READY after RD falling edge

th(WEL-RY)

Hold time, READY after WE falling edge

H+5

H +4

H +3

tvJWEL-RY~

Valid time, READY after WE falling edge

H-10

H-15

H-8

NOTE 5: The external READY input is sampled only after the internal software wait states are completed.

CLKOUT1

1. . __. . 1.

tsu(RY-COH)

~
:

AO-At5

)(

;

: - tSU(R:-COH)

I
READY

r- th(~OH-RYH)

I -+!

~~~"""I--or~~~_I

tsu(RY-RDL)

1
1

k=
1

!.- Generated
Wait State

I
Wait State
I~ Generated ~

~
"I

by READY

Internally
th(RDL-RY)

Figure 17. Ready Timing for Externally-Generated Wait States During an External Read Cycle
CLKOUT1

~
th(COH-RYH) ~

AO-A15

tsu(RY-COH)

READY
tv(WEL-RY)

-.I

:::
'li+- Xi
~

x'----_

i
I

\~
~~___th_(W_E_L_-R_y_)_I• __~II____________~/1T
I
Wait State Generated by READY

1
1

Figure 18. Ready Timing for Externally-Generated Wait States During an External Write Cycle

•
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9-129

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

RESET, INTERRUPT, AND 810
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H =O.5tc(co)1 (see Figure 19)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50
MIN

MAX

'320C5x-80
'320C5x-100
'320LC5x-80
MIN

UNIT

MAX

tsu(lN-COL)

Setup time, INT1-INT4, NMI before CLKOUT1 lowt

tsu(RS-COL)

Setup time, RS before CLKOUT1 low

tsu(RS-CIL)

Setup time, RS before X2/CLKIN low

tsu(BI-COL)

Setup time, BIO before CLKOUT1 low

th(COL-IN)

Hold time, INT1-INT4, NMI after CLKOUT1 lowt

th(COL-BI}

Hold time, BIO after CLKOUT1 low

tw(lNL)SYN

Pulse duration, INT1-INT4, NMllow, synchronous

4H + 15§

4H + 10§

tw(INH}SYN

Pulse duration, INT1-INT4, NMI high, synchronous

2H + 15§

2H + 10§

tw(lNL)ASY

Pulse duration, INT1-INT4, NMllow, asynchronous:t:

6H + 15§

6H + 10§

tw(lNH)ASY

Pulse duration, INT1-INT4, NMI high, asynchronous;

4H + 15§

4H + 10§

tw(RSL}

Pulse duration, RS low

12H

tw{BIL1SYN

Pulse duration, BIO low, synchronous

tw(BIL)ASY

Pulse duration, BIO low, asynchronous;

H+ 15

H + 10

tdlRSH)

Delay time, RS high to reset vector fetch

34H

2H-5:t:

ns
2H -5:t:

t These parameters must be met to use the synchronous timings. Both reset and the interrupts can operate asynchronously. The pulse durations
require an extra half-cycle to ensure internal synchronization.
:t: Values derived from characterization data and not tested
§ If in IDLE2, add 4H to these timings.

X2ICLKIN

-+\ I.-

RS~"
CLKOUT1

tsu{RS-CIL)

14-- td{RSH) -.I

tw{RSL) -----i~~!j

tsu{BI-COL)~

:::J

14--- tsu{RS-COL)
I~
I
14-

14- tw{BIL)SYN ~

BIO - - - - - - - - - - " " ' \ \

I )rIr-1- - - 1 1 - - - - - - - - - - - + - - - - -

::;I ..- th(COL-BI)1

AO-A15_~
~ I

INT4-INT1

-.I I
I

I
I

su(IN-COL)
~ tw(INH)SYN ~

-+l

,041

I ,,......---

Figure 19. Reset, Interrupt, and BID Timings

•
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INSTRUMENTS
9-130

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

r--

tsu{IN-COL)
th(COL-IN)-+i
tw(INL)SYN ----+t~,

TMS320C5x,TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (lACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6)
switching characteristics over recommended operating conditions [H

=O.Ste(CO)] (see Figure 20)

'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50

PARAMETER

MIN

'320C5x-80
'320C5x-100
'320LC5x-80

MAX

MIN

UNIT

MAX

tsu(AV-IOL)

Setup time, address valid before lAO lowt

H-12=1=

H-9=1=

th(lOL-AV)

Hold time, address valid after lAO low

H-1O=I=

H-7=1=

tw(lOL)

Pulse duration, lAO low

H-10=l=

H-7=1=

td(CO-TU)

Delay time, CLKOUT1 falling edge to TOUT

-6

tsu(AV-IKL)

Setup time, address valid before lACK low§

H-12+

H-9=1=

th(IKL-AV)

Hold time, address valid after lACK low

H-10=l=

H-7=1=

tw(lKL)

Pulse duration, lACK low

H-1o=1=

H-7=1=

tw(TUH)

Pulse duration, TOUT high

2H-12

2H-9

td(CO-XFV)

Delay time, XF valid after CLKOUT1

-6

t lAO goes low during an instruction acquisition. It goes low only on the first cycle of the read when wait states are used. The falling edge should
be used to latch the valid address. The AVIS bit in the PMST register must be set to zero for the address to be valid when the instruction being
addressed resides in on-chip memory.
=1= Valid only if the external address reflects the current instruction activity (that is, code is executing on chip with no external bus cycles and AVIS
is on or code is executing off chip)
§ lACK goes low during the fetch of the first word of the interrupt vector. It goes low only on the first cycle of the read when wait states are used.
Address pins A 1-A4 can be decoded at the falling edge to identify the interrupt being acknowledged. The AVIS bit in the PMST register must
be set to zero for the address to be valid when the vectors reside in on-chip memory.
NOTE 6: lAO pin is not present on 100-pin packages.
lACK pin is not present on 100-pin and 128-pin packages .

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9-131

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A- APRIL 1995 - REVISED APRIL 1996

INSTRUCTION ACQUISITION (IAQ), INTERRUPT ACKNOWLEDGE (lACK),
EXTERNAL FLAG (XF), AND TOUT (SEE NOTE 6) (CONTINUED)
14

th(IQL-AV)

tsu(AV-IQL)

1
1l1li

IAQt

tw(IQL)

14
~I

IACKt
tW(IKL)

tsu(AV-IKL)

'X14
I

--JI

STRB~~________________________________________

CLKOUT1 '

'-.-----/

td(CO-TU)

,~----/

i
~:

'
td(CO-TU)

~~----~/IT

~ ~

'~
......____

114-4---.r~I- td(CO-XFV)

--'---"'1

1
1

XF-----------~.-------·;-----X--------I

TOUT __________________~h~1-------~~I

__________________

~ tw(TUH)~

t IAQ and lACK are not affected by wait states.
Figure 20. IAQ, lACK, and XF Timings Example With Two External Wait States

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

EXTERNAL DMA

switching characteristics over recommended operating conditions [H
(see Figure 21)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50

PARAMETER

=O.5tc(co)1 (see Note 7)

'320C5x-80
'320LC5x-80

'320C5x-100
UNIT

MIN

MAX

MIN

MAX

MIN

MAX

td(HOL-HAL)

Delay time, HOLD low to HOLDA low

td(HOH-HAH)

Delay time, HOLD high before HOLDA high

th(AZ-HAL)

Address high-impedance before HOLDA low:j:

H-15§

ten(HAH-Ad)

Enable time, HOLDA high to address driven

H-5§

td(XBL-IOL)

Delay time, XBR low to lAO low

4H§

6H§

4H§

6H§

4H§

6H§

td(XBH-IOH)

Delay time, XBR high to lAO high

2H§

4H§

2H§

4H§

2H§

4H§

td(XSL-RDV)

Delay time, read data valid after XSTRB low

th(XSH-RD)

Hold time, read data valid after XSTRB high

ten(IOL-RDd)

Enable time, lAO low to read data driven~

o§

2H§

o§

2H§

o§

2H§

th(XRL-DZ)

Hold time, XR/W low to data high impedance

O§

15§

o§

10§

o§

th(IOH-DZ)

Hold time, lAO high to data high impedance

H§

ten(D-XRH)

Enable time, data from XR/W going high

4§

3§

2§

H-10§

H-8§

H -4§

H-3§

HOLD is not acknowledged until current external access request is complete.
:j: This parameter includes all memory control lines.
§ Values derived from characterization data and not tested
~ This parameter refers to the delay between the time the condition (lAO = 0 and XR/W = 1) is satisfied and the time that the 'C5x data lines become
valid.
NOTE 7: X preceding a name refers to external drive of the signal.

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature (see Note 7) (see Figure 21)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50
MIN

MAX

'320C5x-80
'320LC5x-80
MIN

MAX

'320C5x-100
UNIT
MIN

MAX

td(HAL-XBL)

Delay time, HOLDA low to XBR low#

o§

td(IOL-XSL)

Delay time, lAO low to XSTRB low#

o§

tsu(AV-XSL)

Setup time, Xaddress valid before XSTRB low

tsu(DV-XSL)

Setup time, Xdata valid before XSTRB low

th(XSL-D)

Hold time, Xdata hold after XSTRB low

th(XSL-WA)

Hold time, write Xaddress hold after XSTRB low

tw(XSL)

Pulse duration, XSTRB low

tw(XSH)

Pulse duration, XSTRB high

tsu(RW-XSL)

Setup time, R/W valid before XSTRB low

th(XSH-RA)

Hold time, read Xaddress after XSTRB high

§ Values derived from characterization data and not tested
# XBR, XR/W, and XSTRB lines must be pulled up with a 1O-kQ resistor to be certain that they are in an inactive high state during the transition
period between the 'C5x driving them and the external circuit driving them.
NOTE 7: X preceding a name refers to external drive of the signal.

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A-APRIL 1995 - REVISED APRIL 1996

EXTERNAL DMA (CONTINUED)
~~

____________________________

~Ii

td(HOH-HAH~

td(HOL-HAL)

------~
ADDRESS
BUSI
CONTROL
SIGNALS

r-t

-----~

A~i---ten(HAH-Ad) ~

th(AZ-HAL)

t==

~--t- td(HAL-XBL)

'----

I
----~1.+ td(XBL-IQL)~~----------~
I
-+Ill:-

. \-------------I(

=====/~--~~I

I+-./-

td(XBH-IQH)

I
I
I
I

td(IQL-XSL)

I
I
____}---J----+j----,'t-/i

XADDRESS

I
I

---~:
I
I

I
I
I

d(XSL-,RDV)

t--i :
I
l.11.
I _,
I rrr

I
I

I
I
th(XSH-RD)
I
I
I
I
I
-+I J4-+

I
I
I
I

ten(IQL-RDd)

'----

I-

I -I I
I, II I
th(XSL-WA) I- I
I

Figure 21. External DMA Timing

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INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I
I
I J+--t-

th(IQH-DZ)

I§-

---4-.i

tSU(DV-XSL)--t---I
XDATA(WR)

I
I
-I

I I
I ~
-r---+I
I

'--

I
I
I
I
I

?>---;-:'----

:::

th(XSL-D)

9-134

th(XRL-DZ)

I~~I~j-------Ii

_II

tsu(AV-XSL)

I\!'--___ I

tsu(RW-XSL)

;--.!

__________----lo..l_
ten(IQL-RDd)

tw(XSH)

I
I

I
! !, I
th(XSH-RA)
II
I
I
I
I ~ I.I
I
I
t (AV XSL) -+--l+---.:
su
I i I
I

DATA(RD)

I+--

!--.W- tw(XSL)

I
XRIW

I
I
I

}

-+I

I
I+- ten(D-XRH)

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

SERIAL-PORT RECEIVE TIMING

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = O.Stc(eo)] (see Figure 22)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50
MIN
5.2Ht

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

MAX
:j:

'320C5x-80
'320LC5x-80
MIN
5.2Ht

'320C5x-100
UNIT
MIN

MAX
:j:

5.2Ht

6§
6§

a§
a§

6§
6§

ns
ns
ns

2.1Ht

tsu(FS-CK)

Setup time, FSR before CLKR falling edge

tsu(DR-CK)

Setup time, DR before CLKR falling edge

th(CK-FS)

Hold time, FSR after CLKR falling edge

thiCK-DR)

Hold time, DR valid after CLKR falling edge

6
6
6
6

ns
ns
ns

Values ensured by design but not tested
:j: The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 00. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§ Values derived from characterization data and not tested

I+-

tf(SCK)

1
1

CLKR
1

1
1111
1

FSR

I.- th(CK-FS)

1
1111

1
1

tsu(FS-CK)

-.I

tr(SCK)

tw(SCK)

tsu(DR-CK)

'/,

1
1

1
1111

1111

DR
Bit

I
I

X
2

thICK-DR)

'e:

X
7/15

8/16

Figure 22. Serial-Port Receive Timing

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9-135

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

SERIAL-PORT TRANSMIT TIMING, EXTERNAL CLOCKS, AND EXTERNAL FRAMES

switching characteristics over recommended operating conditions (see Note 8) (see Figure 23)
PARAMETER
td(CXH-DXV)

Delay time, DX valid after CLKX high

tdis(CXH-DX)

Disable time, DX invalid after CLKX high

th(CXH-DXV)

Hold time, DX valid after CLKX high

MIN

MAX

UNIT

40t

-5

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = O.Stc(CO)] (see Note 8) (see Figure 23)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50

'320C5x-80
'320LC5x-80

'320C5x-l00
UNIT

MIN

MAX

MIN

MAX

MIN

5.2Ht:

5.2H::j:

MAX

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

td(CXH-FXH)

Delay time, FSX high after CLKX high

th(CXL-FXL)

Hold time, FSX low after CLKX low

th(CXH-FXL)

Hold time, FSX low after CLKX high

2.1H::j:

2.1H::j:
2H-8

2.1H::j:

2H-8

2H-5

2H-8~

2H-5~

t Values derived from characterization data and not tested
::j: Values ensured by design but not tested
§ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 00. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
~ If the FSX pulse does not meet this specification, the first bit of serial data is driven on the DX pin until the falling edge of FSX. After the falling
edge of FSX, data is shifted out on the DX pin. The transmit buffer empty interrupt is generated when theth(CXL-FXL) and th(CXH-FXL) specification
is met.
NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is
independent of the source of CLKX.

I+CLKX

I+- td(CXH-FXH)i

FSX

I
I

j+--+I-

I
I

tf(SCK)

I
I

I
I
I
I
I
I
I

I I

th(CXH-FXL)
I

~I !I

tw(SCK)

\~\~\~~------~i--------~i~\~\--------------I

1"'--'- th(CXL-FXL)

-+i ~ td(CXH-DXV)

~~ ~,-----){

-+II+-

tdis(CXH-DX) ~

th(CXH-DXV)

X::,.....;

X
7/15

Figure 23. Serial-Port Transmit Timing of External Clocks and External Frames

•
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_----J

8/16

TiVlS320C5x, TiVlS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRSD3DA - APRIL 1995 - REVISED APRIL 1996

SERIAL-PORT TRANSMIT TIMING, INTERNAL CLOCKS, AND INTERNAL FRAMES
(SEE NOTE 8)
switching characteristics over recommended operating conditions [H

=O.Stc(CO)] (see Figure 24)

'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50

PARAMETER

MIN

td(CX-FX)

Delay time, CLKX rising edge to FSX

td(CX-DX)

Delay time, CLKX rising edge to OX

TYP

-5

'320C5x-80
'320C5x-l00
'320LC5x-80
MAX

MIN

-4

TYP

25
40t

tdis(CX-DX)

Disable time, CLKX rising edge to OX

tcLSCK)

Cycle time, serial-port clock

tf(SCK)
tr(SCK)
tw(SCK)

Pulse duration, serial-port clock low/high

tlllCXH-DXV)

Hold time, OX valid after CLKX high

UNIT
MAX

29t

Fall time, serial-port clock

Rise time, serial-port clock

4H-20

4H-14

-5

-4

t Values derived from characterization data and not tested
NOTE 8: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent on the source of CLKX. Specifically, the relationship of FSX to CLKX is
independent of the source of CLKX.

I+- tf(SCK)

I
CLKX

j+- td(CX-FX)

FSX

OX
Bit

I
I

I
I
I

I
I

td(CX-FX)

I
-.I 14I
I
I
I

td(CX-OX)

-+j

I
I
I
I
I
I

-J *- tr(SCK)

tw(SCK) ~

-+l I+-

fJfJ

I+-

tdis(CX-OX)

-+j l+-

I
I

th(CXH-OXV)

X
7/15

8/16

Figure 24. Serial-Port Transmit Timing of Internal Clocks and Internal Frames

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9-137

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

SERIAL-PORT RECEIVE TIMING IN TDM MODE

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H = a.Stc(eo)] (see Figure 25)
'320C5x-40
'320C5x-57
'320LC5x-40
'320LC5x-50
MIN

MAX
:j:

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(TO-TCH)

Setup time, TOAT before TCLK rising edge

th(TCH-TO)

Hold time, TOAT after TCLK rising edge

tsu(TA-TCH)

Setup time, TAOO before TCLK rising edge#

th(TCH-TA)

Hold time, TAOO after TCLK rising edge#

tsu(TF-TCH)
th(TCH-TF)

5.2Ht

'320C5x-80
'320LC5x-80
MIN
5.2Ht

'320C5x-100
UNIT

MAX
:j:

MIN

MAX
:j:

5.2H§

2.1Ht

-3

-2

-3

-2

Setup time, TFRM before TCLK rising edge§

Hold time, TFRM after TCLK rising edge§

t Values ensured by design and are not tested
:j: The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 00. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§ TFRM timing and waveforms shown in Figure 25 are for external TFRM. TFRM also can be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 26.
~ Values derived from characterization data and not tested
# These parameters apply only to the first bits in the serial bit string.
tf(SCK)..t

tW(SCK)H

TCLK

".I._ _ _.,.a.-

,..1

TDAT:?<

th(TCH-TA)
1

TADD

--.j14--

~II

1 1l1li

tc(SCK)
815--01

h
\

tsu(TD-TCH)

--.1II1II- th(TCH-TD)
B14

B13

~ tsu(TA-TCH)
1 ~11111- th(TCH-TA)

tw(SCK)

~~~ 8_1_..,j~
__

~~A7_,_

X,-_A_2__

~ ~ tsu(TF-TCH)

:~ th(TCH-TF)

TFRM

~~________________________________________________________________

Figure 25. Serial-Port Receive Timing in TOM Mode

~TEXAS

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INSTRUMENTS
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TfV1S320C5x, TiVlS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

SERIAL-PORT TRANSMIT TIMING IN TOM MODE

switching characteristics over recommended operating conditions [H

PARAMETER

=O.5tc{co)1 (see Figure 26)

'320CSx-40
'320CSx-S7
'320LCSx-40
'320LCSx-SO

'320CSx-80
'320LC5x-80

'320CSx-100

MIN

MAX

th(TCH-TDV)

Hold time, TDATfTADD valid after TCLK rising edge

td(TCH-TFV)

Delay time, TFRM valid after TCLK rising edget

td(TC-TDV)

Delay time, TCLK to valid TDATfTADD

MAX

3H + 10

UNIT

3H + 7

3H +5

t TFRM timing and waveforms shown in Figure 28 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is
illustrated in the receive timing diagram in Figure 27.

timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H O.5t c{co)1 (see Figure 26)

'320CSx-40
'320CSx-S7
'320LCSx-40
'320LCSx-SO

'320CSx-80
'320LCSx-80

'320CSx-100
UNIT

MIN

TYP

MAX

MIN

TYP

MAX

MIN

TYP

5.2H+

8H§

5.2H+

8H§

5.2Ht:

8H§

MAX

tc(SCK)

Cycle time, serial-port clock

tf(SCKl

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock lowl
high

2.1H+

+ Values ensured by design and are not tested
§ When SCK is generated internally
~ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 00. It is characterized approaching an input frequency
of 0 Hz but tested as a much higher frequency to minimize test time.
# Values derived from characterization data and not tested

tw(SCK)~
I I

itf(SCK)

I
I

TCLK

TADD

-,-----f~
I
I
I

..!

th(TCH-TDV)

I
I

TFRM~

--I

I
I

l1li-

~j4~

-.Ii+"

n
I

~
I

~ td(T~H-TFV)
I

II
I

·1

tc(SCK)-11il
TDAT

~:-- tr(SCK)

tw(SCK)

.F\..,~

td(TC-TDV)
B14

B13

l@t~~

th(TCH-TDV)
td(TC-TDV)

'-------GX:

-A1

~ AO

X-~A2~~JY

td(TCH-TFV)

\~________________________________________________________~~________~\I:~_____________________

Figure 26. Serial-Port Transmit Timing in TOM Mode

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9-139

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

BUFFERED SERIAL-PORT RECEIVE TIMING
timing requirements over recommended ranges of supply voltage and operating ambient-air
temperature [H O.5t c(co)1 (see Figure 27)

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(FS-CK)

MIN

MAX

6+
6+

UNIT
ns
ns
ns

Setup time, FSR before CLKR falling edge

tsu(DR-CK)

Setup time, DR before CLKR falling edge

th(CK-FS)

Hold time, FSR after CLKR falling edge

th(CK-DR)

Hold time, DR after CLKR falling edge

t The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching

00.

ns
tc(SCK)§

ns
ns

It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.

+Values derived from characterization data and not tested

~ First bit is read when FSR is sampled low by CLKR clock.
~ tf(SCK}
1
1

CLKR
1

-+j
14
1

FSR

I.- th(CK-FS}

tsu(FS-CK}

-+I

tsu(DR-CK)

X
2

'/;
~I

th(CK-DR)

>c:

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Figure 27. Buffered Serial-Port Receive Timing

9-140

tr(SCK}

tw(SCK}

DR
Bit

I
I

7/15

8/16

TMS320C5x, Ti\ilS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

BUFFERED SERIAL-PORT TRANSMIT TIMING OF EXTERNAL FRAMES (SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions (see Figure 28)
MIN

MAX

td(CXH-DXV)

Delay time, DX valid after CLKX rising edge

tdis(CXH-DX)

Disable time, DX invalid after CLKX rising edge

PARAMETER

tdisLCXH-DX)PCM

Disable time in PCM mode, DX invalid after CLKX rising edge

ten(CXH-DX)PCM

Enable time in PCM mode, DX valid after CLKX rising edge

th(CXH-DXV)

Hold time, DX valid after CLKX rising edge

UNIT

21
5

ns
20

timing requirements over recommended operating conditions (see Figure 28)
MIN

MAX

Fall time, serial-port clock

4:j:

trLSCK~

Rise time, serial-port clock

4:j:

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(FX-CXL)

Setup time, FSX before CLKX falling edge

th(CXL-FX)

Hold time, FSX after CLKX falling edge

tcLSCK~

Cycle time, serial-port clock

tf(SCK)

8.5

t The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching

00.

UNIT

tc (SCK)-5§

It is characterized approaching an input frequency

of 0 Hz but tested at a much higher frequency to minimize test time.
:j: Values derived from characterization data and not tested
§ If the FSX pulse does not meet this specification, the first bit of the serial data is driven on the DX pin until FSX goes low (sampled on falling edge
of CLKX). After falling edge of the FSX, data is shifted out on the DX pin.
NOTE 9: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX. External FSX timings are obtained from the "timing requirements over recommended operating
conditions" table listed in the "Buffered Serial-Port Transmit Timing of External Frames" section and internal FSX timings are obtained
from the "switching characteristics over recommended operating conditions" table listed under the "Buffered Serial-Port Transmit Timing
of Internal Frame and Internal Clock" section. Internal CLKX timings are obtained from the "switching characteristics over recommended
operating conditions" table listed under the "Buffered Serial-Port Transmit Timing of Internal Frame and Internal Clock" section and
external CLKX timings are obtained from the "timing requirements over recommended operating conditions" table in the "Buffered
Serial-Port Transmit Timing of External Frames" section.
NOTE 10: Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0

CLKX

~ tsu(FX-CXL)

I
FSX - - - . /

I+---+j-- th(CXL-FX)

I
I
I
I

tf(SCK)

I
1
1I
-J I.- tr(SCK)
II
~I : tw(SCK)
- -I t I' " " " I - - - - - - - - - 1
I
-+I ~ th(CXH-DXV)

~,,--\..a...\
.
- . . .\...a..-_----iI---__
I
l+I

td(CXH-DXV)-+I

DXBlt

I+I
I

)

)e:

~'- _ _ _---I

I
I
I
I
1
I
I

tdis(CXH-DX) -+j

X
7/15

8/16

Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames

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9-141

TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

BUFFERED SERIAL-PORT TRANSMIT TIMING OF INTERNAL FRAME AND INTERNAL CLOCK
(SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions [H

=0.5tc{co)1 (see Figure 29)
MIN

PARAMETER

MAX

UNIT

td(CXH-FXH)

Delay time, FSX high after CLKX rising edge

td(CXH-FXL)

Delay time, FSX low after CLKX rising edge

tdlCXH-DXV)

Delay time, DX valid after CLKX rising edge

tdis(CXH-DX)

Disable time, DX invalid after CLKX rising edge

tdis(CXH-DX)PCM

Disable time in PCM mode, DX invalid after CLKX rising edge

ten(CXH-DX)PCM

Enable time in PCM mode, DX valid after CLKX rising edge

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

th(CXH-DXV)

Hold time, DX valid after CLKX rising edge

ns
62H

H-4
4

t Values derived from characterization data and not tested
NOTES: 9. Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending
on the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to
CLKX is independent of the source of CLKX. External FSX timings are obtained from the "timing requirements over recommended
operating conditions" table listed in the "Buffered Serial-Port Transmit Timing of External Frames" section and internal FSX timings
are obtained from the "switching characteristics over recommended operating conditions" table listed under the "Buffered Serial-Port
Transmit Timing of Internal Frame and Internal Clock" section. Internal CLKX timings are obtained from the "switching characteristics
over recommended operating conditions" table listed under the "Buffered Serial-Port Transmit Timing of Internal Frame and Internal
Clock" section and external CLKX timings are obtained from the "timing requirements over recommended operating conditions" table
in the "Buffered Serial-Port Transmit Timing of External Frames" section.
10. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to O.

J4-CLKX

FSX

I
I
I
I

I+-

td(CXH-FXH)

I
I
--+I I+-

Jr-----,.\l

I
I
tw(SCK)
td(CXH-FXL)

-.l

I
I
~ I
I
I

td(CXH-DXV)

I
I

I
I
I
I

i ';',

tr(SCK)

i
tdis(CXH-DX)-+J

-+J J4--

th(CXH-DXV)

7/15

Figure 29. Buffered Serial-Port Transmit Timing of Internal Clocks and Internal Frames

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INSTRUMENTS
9-142

14I

01~~~__~x~____~x~______~~

g~ ~________

I
I
~ 14-

tf(SCK)

I
I

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TlVlS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY)
switching characteristics over recommended operating conditions [H
and 12) (see Figure 30 through Figure 33)
.
PARAMETER

=0.5tc(eo)] (See Notes 11
MIN

td(DSL-HDV)

Delay time, OS low to HD valid

td(HEL-HDV1)

Delay time, HDS falling to HD valid for first byte of a subsequent read:
Case 1: Shared-access mode if tw(HDS)h < 7H t
Case 2: Shared-access mode~(HDS)h > 7H
Case 3: Host-only mode if tw(HDS)h < 7H
Case 4: Host-only mode if tw(HDS)h > 7H

MAX

UNIT
ns

7H+20-t w (DSH)
20
40-t w (DSH)
20
20

td(DSL-HDV2)

Delay time, OS low to HD valid, second byte

td(DSH-HYH)

Delay time, OS high to HRDY high

tsu(HDV-HYH)

Setup time, HD valid before HRDY rising edge

th(DSH-HDV)

Hold time, HD valid after OS rising edge

12§

td(COH-HYH)

Delay time, CLKOUT rising edge to HRDY high

td(DSH-HYL)

Delay time, HDS or HCS high to HRDY low

td(COH-HTX)

Delay time, CLKOUT rising edge to HINT change

ns
3H-10

Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
Shared-access mode timings are met automatically if HRDY is used.
§ HD release
NOTES: 11. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRLO, HCNTRL 1, and HR/W
HDS refers to either HDS1 or HDS2.
OS refers to the logical OR of HCS and HDS.
12. On host-read accesses to the HPI, the setup time of HD before OS rising edge depends on the host waveforms and cannot be
specified here.

timing requirements over recommended operating conditions [H = 0.5t c(eo)] (See Note 11)
(see Figure 30 through Figure 33)
MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HAD/HBIL valid before HAS or OS falling edge#

th(DSL-HBV)

Hold time, HAD/HBIL valid after HAS or OS falling edge#

tsu(HSL-DSL)

Setup time, HAS low before OS falling edge

tw(DSL)

Pulse duration, OS low

tw(DSH)

Pulse duration, OS high

tc(DSH-DSH)

Cycle time, OS rising edge to next OS rising edge:
Case 1: When using HRDY (see Figure 32)
Case 2a: SAM accesses and HOM active writes to DSPINT or HINT without using HRDY
(see Figure 30 and Figure 31)
Case 2b: When not using HRDY for other HOM accesses

50
10H~

tsu(HDV-DSH)

Setup time, HD valid before OS rising edge

th(DSH-HDV)

Hold time, HD valid after OS rising edge

50
10

~ A host not using HRDY must meet the 10 H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
# When HAS is tied to VDD, timing is referenced to OS.
NOTE 11: SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRLO, HCNTRL 1, and HR/W
HDS refers to either HDS1 or HDS2.
OS refers to the logical OR of HCS and HDS .

•
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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A-APRIL 1995 - REVISED APRIL 1996

HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE

HAD

-Y,
Y
--.J: r J \
:H

tw(DSH)

'I
14
~

-I

RE~g

m
1l1li

'w(DSL)

~ ~

Valid
1l1li

i
----(

tsu(HBV-DSL)

I '--

I
IiIII

th(DSH-HDV)

,j:

x;-

'w(DSL)

: I :

~
tsu(HDV-DSH)

HD
WRITE

tw(DSH)

'd(D~L-HDV) ~ ~

I :

tc(DSH-DSH)

td(HE~-HDV1) i4
:

~g~ ~
II1II;---

r: ~ t-~(DSL-HBV)
Valid

th(DSL-HBV)

tsu(HBV-DSL)

HBIL

~valid

Valid

SECOND BYTE

~i td(DSL-~DV2)
_I

Valid

tsu(HDV-DSH)

~ ~th(DSH-HDV)
valid):

- : ro-'h(DSH-HDV)

i
(

,}-

!+-th(DSH-HDV)

Valid ) -

Figure 30. Read/Write Access Timings Without HRDY or HAS

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Ti\ilS320C5x, TiV1S320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE

:
HAD

14- tsu(HSL-DSL)

~ V~ ~ !h(D:~;,:BV)
: 14

HBIL\

SECOND BYTE

tw(DSH)

Valid

tsu(HBV-DSL)

.1:
£\['
14"'I

7
14 :

14'

tw(DSL)

tc(DSH-DSH)

----.10'

HCS
I,
H D S ' ,

td(HE~-HDV1):4
,

td(DS~-HDV) ~

-c114-

td(DSL-HPV2)

th(DSH-HDV)

-.I ~ th(DSH-HDV)

_OOJ

h~tc(DSH-DSH) ~

HD
READ

--l41---"~

_
HD
WRITE

---------<\

'tsu(HDV-DSH)

~ ~ !h(DSH-HDV)

Valid

)>-:- - - - - - «

!h(DSH-HDV)

Valid ) - -

Figure 31. Read/Write Access Timings Using HAS Without HRDY

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TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A-APRIL 1995 - REVISED APRIL 1996

HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)
FIRST BYTE

tsu(HBV-DSL)

SECOND BYTE

14-- tsu(HSL-DSL)
1

f4- 'h(DSL-HBV)

=x .f'V
: 1 -./

HAD

'SU(HBV-DSL)t :

~g~

(

1,..'

X'---->C

~lt=o----....,......:....---_---

tw DSH

~j4- th(DSL-HBV)t

HBll

'
~:

'---

tc(DSH-DSH)

)~'W(DSL)--tI~

1, I

' I

td(HEl-HDV1)
:

1l1li

td(DSL-HDV) ~

td(DSH-HYL)

1 ,

It!!
d(DSL-HDV2)

II1II

--.114- th(DSH-HDV)

~ tsu(HDV-HYH)

I11III

I4+-- td(D,SH-HYH)'

---.!m
.

' I

I
HRDY

;;=
1

---.I

I I *- th(DSH HDV)

HD
READ
tsu(HDV-DSH)

1l1li

I'
.1'

I '

~
HD
WRITE

-----i--------<\

tsu(HDV-DSH)

41 r:'h(DSH-HDV)
Valid

;,>-:------«

I~ ~I th(DSH-HDV)

V~lId

f.l

'd(COH-HYH)

CLKOUT
td(COH-HTX)

t When HAS is tied to VDD
Figure 32. Read/Write Access Timing With HRDY

•
TEXAS
INSTRUMENTS
9-146

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C5x, "(MS320LC5x
DIGITAL SIGNAL PROCESSO.RS
SPRS030A - APRIL 1995 - REVISED APRIL 1996

HOST PORT INTERFACE (TMS320C57S, TMS320LC57 ONLY) (CONTINUED)

HCS

IO-~-~~- td(DSH-HYL)

HRDY

----~i--\t~--------------~11
-----01.1
te-I~---- td(DSH-HYH)

\'-------

Figure 33. HRDY Signal When HCS Is Always Low

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-147

9-148

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

• Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and
One Program Memory Bus
• 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two
Independent 40-Bit Accumulators
• 17- x 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined
Single-Cycle Multiply/Accumulate (MAC)
Operation
• Compare Select Store Unit (CSSU) for the
Add/Compare Selection of the Viterbi
Operator
• Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator
Value in a Single Cycle
• Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units
e Data Bus With a Bus Holder Feature
• 192K x 16-Bit Maximum Addressable
Memory Space (64K Words Program,
64K Words Data, and 64K Words I/O)
• On-Chip ROM with Some Configurable to
Program/Data Memory
o Dual-Access On-Chip RAM
• Single-Instruction Repeat and Block Repeat
Operations for Program Code
• Block Memory Move Instructions for Better
Program and Data Management
• Instructions With a 32-Bit Long Word
Operand
• Instructions With Two- or Three-Operand
Reads
• Arithmetic Instructions With Parallel Store
and Parallel Load
• Conditional Store Instructions
• Fast Return From Interrupt

• On-Chip Peripherals
- Software-Programmable Wait-State
Generator and Programmable Bank
Switching
- On-Chip Phase-Locked Loop (PLL) Clock
Generator With Internal Oscillator or
External Clock Source
- Full-Duplexed Serial Port to Support 8- or
16-Bit Transfers (,C541 , 'LC541, 'VC541,
'LC544, 'VC544, 'LC545, 'VC545, 'LC546,
and 'VC546 Only)
- Time-Division Multiplexed (TDM) Serial
Port (,C542, 'LC542, 'VC542, 'LC543 and
'VC543 Only)
- Buffered Serial Port (BSP) (,C542, 'LC542
'VC542, 'LC543, 'VC543, 'LC545, 'VC545,
'LC546, and 'VC546 Only)
- 8-Bit Parallel Host Port Interface (HPI)
(,C542, 'LC542, 'VC542, 'LC545, and
'VC545 Only)
- One 16-Bit Timer
- External-Input/Output (XIO) Off Control
to Disable the External Data Bus,
Address Bus and Control Signals
• Power Consumption Control With IDLE1,
IDLE2, and IDLE3 Instructions With
Power-Down Modes

a:
o

L1.

• CLKOUT Off Control to Disable the
CLKOUT

• On-Chip Scan-Based Emulation Logic,
IEEE Std 1149.1t (JTAG) Boundary Scan
Logic

• 25-ns Single-Cycle Fixed-Point Instruction
Execution Time [40 million instructions per
second (MIPS)] for 5-V Power Supply
(,C541 and 'C542 Only)
• 20-ns and 25-ns Single-Cycle Fixed-Point
Instruction Execution Time (50 MIPS and
40 MIPS) for 3-V Power Supply (,LC54x and
'VC54x)

"TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

:2:
Z

IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

ADVANCE INFORMATION concerns new products in the sampling or
preproduction phase of development. Characteristic data and other
specifications are subject to change without notice.

9-149

~
c

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

description
The TMS320C54x, TMS320LC54x and TMS320VC54x fixed-point, digital signal processor (DSP) families are
fabricated with a combination of an advanced modified Harvard architecture which has one program memory
bus and three data memory buses. These processors also provide a central arithmetic logic unit (CALU) which
has a high-degree of parallelism and application-specific hardware logic, on-chip memory, additional on-chip
peripherals. These DSP families also provide a highly specialized instruction set which is the basis of the
operational flexibility and speed of these DSPs.
Separate program and data spaces allow simultaneous access to program instructions and data, providing the
high degree of parallelism. Two reads and one write operation can be performed in a single cycle. Instructions
with parallel store and application-specific instructions can fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that all can be performed in a single machine cycle. In addition, the 'C54x,
'LC54x and 'VC54x versions include the control mechanisms to manage interrupts, repeated operations, and
function calling.
Table 1 provides an overview of the 'C54x1'LC54x1'VC54x generation of DSPs. The table shows the capacity
of on-chip RAM and ROM memories, the peripherals, the execution time of one machine cycle, and the type
of package with its total pin count. Use the information in Table 1 to select the best processor for each
application.

:t:O

~
Z

Table 1. Characteristics of the 'C54x1'LC54x1'VC54x Processors

o
m

-Z

-n

o
::D
s:

o
z

DSP TYPE

NOMINAL
VOLTAGE (V)

ON-CHIP
MEMORY

PERIPHERALS

RAMt

ROM

SERIAL
PORT

TIMER

HPI

CYCLE
TIME (n5)

PACKAGE TYPE

100 pin (TQFP)

TMS320C541

5.0

28K+

TMS320LC541

3.3

28K+

20/25

100 pin (TQFP)

TMS320VC541

3.0

28K+

20/25

100 pin (TQFP)

TMS320C542

5.0

10K

2§

Yes

144 pin (TQFP)

TMS320LC542

3.3

10K

2§

Yes

20/25

TMS320VC542

3.0

10K

2§

Yes

20/25

128 pin (TQFP)/144 pin (TQFP)

TMS320LC543

3.3

10K

2§

20/25

100 pin (TQFP)

TMS320VC543

3.0

10K

2§

20/25

100 pin (TQFP)

TMS320LC544

3.3

24K+

20/25

80 pin (TQFP)

128 pin (TQFP)/144 pin (TQFP)

TMS320VC544

3.0

24K+

20/25

80 pin (TQFP)

TMS320LC545

3.3

48K'1

Yes

20/25

128 pin (TQFP)

TMS320VC545

3.0

48K'II

Yes

20/25

128 pin (TQFP)

TMS320LC546

3.3

48K'II

20/25

100 pin (TQFP)

TMS320VC546

3.0

48K'1

20/25

100 pin (TQFP)

Legend:
TQFP = Thin Quad Flat Pack
t The dual-access RAM can be configured as data memory or program and data memory.
+ For 'C541I'LC541I'VC541I'LC544/'VC544, 8K words of ROM can be configured as program memory or program/data memory.
§ TDM and buffered serial ports
'fi For 'LC545I'VC54SI'LC546I'VC546, 16K words of ROM can be configured as program memory or program/data memory.
# Standard and buffered serial ports

~TEXAS

INSTRUMENTS
9-150

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

TMS320LC542, TMS320VC542

PBK PACKAGEt
(TOP VIEW)

128127126125124123122121120119118117116115114113112111110109108107106105104103102101100 99 98 97
96

CVSS
DVDD
Al0
HD7
All
A12
A13
A14
A15

94
93
92
91
90
89
88

CVDD
HAS

DVSS
CVSS
CVDD
HCS
HRW
READY

R/Vi

MSTRB
10STRB
MSC
XF
HOLDA
lAO
HOLD
BIO
MP/MC

DVDD
CVSS

DVSS
DVDD
D5
D4
D3
D2
Dl
DO
RS
X2/CLKIN
Xl
HD3
CLKOUT

DVSS
HPIENAIVDD
CVDD
CVSS
TMS
TCK
TRST
TDI
TOO
EMUlIOFF
EMUO
TOUT
HD2
CNT
CLKMD3
CLKMD2
CLKMDl

:a:
a:

0
Z

DVSS
DVDD

~M~~~~.~~Ga«~~Q~GW~~~~~W~WYM~UmM

tIo

(I)

f--

t DVSS and DVDD are power supplies for I/O pins while CVSS and CVDD are power supplies for core CPU.
The pin function table on the following pages lists each pin number, signal, function, and operating mode(s) for
the TMS320LC542PBK/'VC542PBK (128-pin) packages .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

9-151

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC542PBKI'VC542PBK (128-Pin TQFP Package)
PIN
NAME

Supply

OVOO

·2

Supply

O/Z

H07
A11-A15
CVOO

-z

"T1

o
:c

s:
~
o
z

DESCRIPTION

FUNCTIONt

CVSS
A10

:t>

I/O/Z

5-9

O/Z

Supply

Ground
+VOO
Parallel port address bus
Parallel bi-directional data bus (HPI)
Parallel port address bus
+VOO

HAS

OVSS

Supply

Ground

CVSS

Supply

Ground

CVOO

Supply

+VOO

HCS

Chip select input (HPI)

HRW

Read/write (HPI)

REAOY

External access ready to complete

O/Z

Program space select

O/Z

Oata space select

O/Z

I/O select

R/W

O/Z

Read/write

MSTRS

O/Z

External memory access strobe

10STRS

O/Z

External I/O access strobe

Address data strobe (HPI)

MSC

O/Z

Microstate complete

O/Z

External flag

HOLOA

O/Z

Hold acknowledge

IAQ

O/Z

Instruction acquisition

HOLO

Request access of local memory

SIO

Sit I/O pin

MP/MC

OVOO

Supply

+VOO

CVSS

Supply

Ground

HCNTLO

OVSS

Supply

Microprocessor/microcomputer

Control inputs (HPI)
Ground

SCLKR

Receive clock input (SSP)

TCLKR

Receive clock input (TOM)
Frame synchronization pulse for receive (SSP)

SFSR

TFSRfTAOO

I/O

SOR

Serial data receive input (SSP)

HCNTL1

Control inputs (HPI)

TOR

Serial data receive input (TOM)

SCLKX

I/O/Z

Serial port 0 transmit clock (SSP)

TCLKX

I/O/Z

Serial port 0 transmit clock (TOM)

Receive frame synchronization (TOM)

t I = Input, 0 =Output, Z = High impedance

~TEXAS

INSTRUMENTS
9-152

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiviS320C54x, TiviS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC542PBK/'VC542PBK (128-Pin TQFP Package) (Continued)
PIN
NAME

DESCRIPTION

FUNCTIONt

CVSS

Supply

HINT

all

CVOO

Supply

Ground
Interrupt output (HPI)
+VOO

BFSX

1/0Il

Frame synchronization pulse for transmit (BSP)

TFSXlTFRM

1/0Il

Transmit frame synchronization (TOM)

HROY

all

OVOO

Supply

+VOO
Ground

Ready output (HPI)

OVSS

Supply

HOO

1/0Il

BOX

all

Serial data transmit output (BSP)

TOX

all

Serial data transmit output (TOM)

lACK

all

HBIL

Byte indentification input (HPI)

NM1

Nonmaskable interrupt
Interrupt 0 through Interrupt 3

Parallel bi-directional data bus (HPI)

Interrupt acknowledge

58-61

CVOO

Supply

+VOO

H01

1/0Il

Parallel bi-directional data bus (HPI)

CVSS

Supply

Ground

OVOO

Supply

+VOO
Ground

INTO-INT3

OVSS

Supply

CLKM01

Clock mode pin 1

CLKM02

Clock mode pin 2

CLKM03

Clock mode pin 3

CNT

1/0 level select

H02

1/0Il

TOUT

all

EMUO

1/0Il

:a5

a::

o
u.
Z

o
Z

Timer output

Emulator interrupt 0

EMU1/0FF

1/0Il

all

TDI

Test data input (IEEE standard 1149.1)

TRST

Test reset (IEEE standard 1149.1)

TCK

Test clock (IEEE standard 1149.1)

TMS

Test mode select (IEEE standard 1149.1)

CVSS

Supply

Ground

CVOO

Supply

+VOO

HPIENAIVOO

OVSS

Supply

all

I = Input,

z
o

Parallel bi-directional data bus (HPI)

TOO

CLKOUT

Emulator interrupt 1/shutoff
Test data output (IEEE standard 1149.1)

HPI module select input
Ground
Machine clock output

a = Output, l =High impedance

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

9-153

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC542PBKI'VC542PBK (128-Pin TQFP Package) (Continued)
PIN
NAME

I/Oll

Oscillator output

X2/CLKIN

Oscillatorlexternal clock input

Device reset

DO-OS

89-94

I/Oll

Parallel data port

OVDO

Supply

+VOO
Ground

DVSS

Supply

Ground

OVDO

Supply

+VOO

99-105

I/Oll

Parallel data port

106

I/Oll

Parallel bi-directional data bus (HPI)

107-109

I/Oll

Parallel data port

HD5

110

I/Oll

Parallel bi-directional data bus (HPI)

CVOO

111

Supply

+VOD

CVSS

112

Supply

HDS1

113

013-015

o
m
z

o
::D
:s:
~

DVSS

114

Supply

115

OVDO

116

Supply

AO-A3

117-120

Oil

121

I/Oll

A4-A9

122-127

Oil

CVDO

128

Supply

I = Input, 0

Ground
Data strobe input (HPI)

HOS2

HD6

""T1

Parallel bi-directional data bus (HPI)

CVSS
D6-012

~
z

DESCRIPTION

FUNCTIONt

H03

HD4

»c

Ground
Data strobe input (HPI)
+VOO
Parallel port address bus
Parallel bi-directional data bus (HPI)
Parallel port address bus
+VOD

=Output, l = High impedance

o
z

~TEXAS

INSTRUMENTS
9-154

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54}{, TMS320LC54}{, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039-FEBRUARY1996
TMS320LC545, TMS320VC545
PBK PACKAGEt
(TOP VIEW)

128127126125124123122121120 119118117116115114113112 11111010910810710610510410310210110099 98 97

CVSS
DVDD
A10
HD7
A11
A12
A13
A14
A15
CVDD
HAS
DVSS
CVSS
CVDD
HCS
HRW
READY
PS
DS
IS
R/W
MSTRB
10STRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
DVDD
CVSS

96
95

94
93
92
91
90
89
88

DVSS
DVDD
D5
D4
D3
D2
D1
DO
RS
X2/CLKIN
X1
HD3
CLKOUT
DVSS
HPIENAIVDD
CVDD
CVSS
TMS
TCK
TRST
TOI
TDO
EMU1/0FF
EMUO
TOUT
HD2
CNT
CLKMD3
CLKMD2
CLKMD1
DVSS
DVDD

~
~

L1.

0
Z

33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

~ ~ X

OJ f-

0 X

~ I~

...J

10 I~ IN 1(')

CVSS

112

Supply

HDS1

113

Ground
Data strobe input (HPI)

DVSS

114

Supply

HDS2

115

DVDD

116

Supply

AO-A3

117-120

O/Z

121

I/O/Z

A4-A9

122-127

O/Z

CVDD

128

Supply

HD6

Parallel bi-directional data bus (HPI)

Ground
Data strobe input (HPI)
+VDD
Parallel port address bus
Parallel bi-directional data bus (HPI)
Parallel port address bus
+VDD

t I =Input, 0 =Output, Z =High impedance

~
oz

•
TEXAS
INSTRUMENTS
9-158

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

TMS320C542/TMS320LC542/TMS320VC542
PGE PACKAGEf:I:
(TOP VIEW)

CVss
NC
CVSS
OVOO
A10
A11
A12
A13
A14
A15
CVOO
HAS
OVSS
CVSS
CVOO
HCS
HRW
READY

OVSS
NC
OVSS
OVOO
05
04
03
02
01
DO
RS
X2/CLKIN
X1
H03
CLKOUT
OVSS
HPIENA/VOO
CVOO
CVSS
TMS
TCK
TRST
TOI
TOO
EMU1/0FF
EMUO
TOUT
H02
CNT
CLKM03
CLKM02
CLKM01
OVSS
OVOO
NC
CVSS

13
14

PS
58
IS
R/W
MSTRB
10STRB
MSC
XF
HOLDA
IAQ
HOLD
BIO
MP/MC
OVOO
CVSS
NC
OVSS

a:
a:

Z
W

~
C

«
t NC =No connection
:j: DVSS and DVDD are power supplies for liD pins while CVSS and CVDD are power supplies for core CPU.
The pin function table on the following pages lists each pin number, signal, function, and operating mode(s) for
the TMS320C542PGE/'LC542PGE/'VC542PGE (144-pin) packages.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-159

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320C542PGEI'LC542PGEI'VC542PGE (144-Pin TQFP Package)
PIN
NAME

z
o

-z

o
:rJ
s:

~
oz

DESCRIPTION

FUNCTIONt

CVSS

Supply

N/A

CVSS

Supply

Ground

DVDD

Supply

+VDD

Ground
No connection

A10

O/Z

HD7

I/O/Z

7-11

O/Z

CVDD

Supply

HAS

DVSS

Supply

CVSS

Supply

Ground

CVDD

Supply

+VDD

A11-A15

»c

Parallel port address bus
Parallel bi-directional data bus (HPI)
Parallel port address bus
+VDD
Address data strobe (HPI)
Ground

HCS

HRW

Read/write (HPI)

READY

External access ready to complete

Chip select input (HPI)

O/Z

Data space select

O/Z

I/O select

RIW

O/Z

Read/write

MSTRB

O/Z

External memory access strobe

10STRB

O/Z

External I/O access strobe

MSC

O/Z

Microstate complete

O/Z

External flag

HOLDA

O/Z

Hold acknowledge

IAQ

O/Z

HOLD

Request access of local memory

BIO

Bit I/O pin

MP/MC

DVDD

Supply

+VDD

CVSS

Supply

Ground

N/A

DVSS

Supply

Ground

CVSS

Supply

Ground

N/A

HCNTLO

DVSS

Supply

BCLKR

Receive clock input (BSP)

TCLKR

Receive clock input (TDM)

BFSR

TFSRITADD

I/O

t I = Input, 0

Program space select

Instruction acquisition

Microprocessor/microcomputer

No connection

No connection
Control inputs (HPI)
Ground

Frame synchronization pulse for receive (BSP)
Receive frame synchronization (TDM)

=Output, Z = High impedance

~TEXAS

INSTRUMENTS
9-160

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320C542PGEI'LC542PGEI'VC542PGE
(144-Pin TQFP Package) (Continued)
PIN
NAME

DESCRIPTION

FUNCTIONt

BOR

Serial data receive input (BSP)

HCNTL1

Control inputs (HPI)
Serial data receive input (TOM)

TOR

BCLKX

I/O/Z

Serial port transmit clock (BSP)

TCLKX

I/O/Z

Serial port transmit clock (TOM)

CVSS

Supply

Ground

HINT

01Z

CVOO

Supply

Interrupt output (HPI)
+VOO

BFSX

I/O/Z

Frame synchronization pulse for transmit (BSP)

TFSXlTFRM

I/O/Z

Transmit frame synchronization (TOM)

HROY

O/Z

OVOO

Supply

+VOO

OVSS

Supply

Ground

HOO

I/O/Z

Parallel bi-directional data bus (HPI)

BOX

O/Z

Serial data transmit output (BSP)

TOX

O/Z

Serial data transmit output (TOM)

lACK

O/Z

Interrupt acknowledge

HBIL

Byte identification input (HPI)

NMI

Nonmaskable interrupt

INTO-INT3

Ready output (HPI)

64-67

CVOO

Supply

H01

I/O/Z

CVSS

Supply

o
~

:a:
a::
o
LL
Z

Interrupt 0 through Interrupt 3
+VOO

Parallel bi-directional data bus (HPI)

Ground

N/A

OVSS

Supply

Ground

CVSS

Supply

Ground

OVOO

Supply

+VOO
Ground

No connection

OVSS

Supply

CLKM01

CLKM02

Clock mode pin 2

CLKM03

Clock mode pin 3

g ~

~ ~ ~ ~ ~ ~ ~ ~ I~ I~ I~ ~ ~ I~ § E >g ~
If)

If)

The pin function table on the following pages lists each pin number, signal, function, and operating mode(s) for
the TMS320LC544PN/TMS320VC544PN (80-pin) packages.

!CC>

•

TEXAS

INSTRUMENTS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-163

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC544PN/TMS320VC544PN
(SO-Pin TQFP Package)
PIN
NAME

Supply

OIl

VOO

Supply

+VOO

VSS

Supply

Ground

R/W

OIl

Read/Write

MSTRB

OIl

External memory access strobe
External 1/0 access strobe

A10-A14

~
z

DESCRIPTION

FUNCTIONt

2-6

VSS

»c

Ground
Parallel port address bus

10STRB

OIl

VOO

Supply

+VOO

VSS

Supply

Ground

BIO

Bit 1/0 pin

MP/MC

Microprocessor/microcomputer

FSRO

Serial port 0 receive frame synchronization

FSR1

Serial port 1 receive frame synchronization

ORO

Serial port 0 data receive

External flag

OR1

VOO

Supply

+VOO

VSS

Supply

Ground

SCLKO

I/0Il

Serial port 0 clock

"a:D

SCLK1

I/0Il

Serial port 1 clock

FSXO

I/0Il

Serial port 0 transmit frame synchronization

FSX1

I/0Il

Serial port 1 transmit frame synchronization

OXO

OIl

Serial port 0 transmit output

OX1

OIl

Serial port 1 transmit output

-z
s

I = Input, 0

Serial port 1 data receive

=Output, l = High impedance

~TEXAS

INSTRUMENTS
9-164

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039- FEBRUARY 1996

Pin Functions for the TMS320LC544PN/TMS320VC544PN
(SO-Pin TQFP Package) (Continued)
PIN
NAME

DESCRIPTION

FUNCTIONt

Voo

Supply

+Voo

VSS

Supply

Ground

31-33

Interrupt 0, 1, 3

Clock mode pin 1

INTO, INT1 ,INT3
CLKM01
EMUO

I/OIZ

Emulator interrupt 0

EMU1/0FF

I/OIZ

Emulator interrupt 1/shut off

TOO

OIZ

TOI

VOO

Supply

+VOO

VSS

Supply

Ground

TRST

Test reset (IEEE standard 1149.1)

TCK

Test clock (IEEE standard 1149.1)

TMS

Test mode select (IEEE standard 1149.1)

CLKOUT

OIZ

X2/CLKIN

External clock input

Oevice reset

VOO

Supply

+VOO

VSS

Supply

Ground

49-55

I/OIZ

Parallel data port

VOO

Supply

+VOO

VSS

Supply

Ground

00-06

07-015
VOO
VSS
AO-A6
VOO
VSS
A7-A9

Test data output (IEEE standard 1149.1)
Test data input (IEEE standard 1149.1)

Machine clock output

58-66

I/OIZ

Parallel data port

Supply

+VOO
Ground

Supply

69-75

OIZ

Supply

+VOO

Supply

Ground

78-80

OIZ

~
~

a::
o
u.
Z

(.)

~
c

Parallel port address bus

t I = Input, 0 = Output, Z = High impedance

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-165

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

TMS320C541, TMS320LC541, TMS320VC541
PZPACKAGEt
(TOP VIEW)

CVSS
Al0

All

A12
A13

A14

A15

CVOO

l>
C

X2ICLKIN

OVSS

CVSS
CVOO

CLKOUT
OVSS

READY

CVOO

PS
OS
is
RiW

CVSS
TMS
TCK
TRST

MSTRB

TOI

10STRB
MSC

TOO
EMU1/0FF

EMUO

TOUT

CNT

CLKM03
CLKM02

-z

MP/Mc

o
:IJ
s:
~
o

CLKMOl

11=

gJ ~ - ~ a: ~ a: 0 - gJ g ~ X g gJ ~ X 10 l:iii I~ I~ I~ g gJ
>~~~~CC~~»~~»CC
C

Interrupt 0 through Interrupt 3

Clock mode pin 1

CNT

TOUT

OIl

I/O level select
Timer output

EMUO

I/Oll

EMU1/0FF

I/Oll

TOO

OIl

TOI

TRST

Test reset (IEEE standard 1149.1)

TCK

Test clock (IEEE standard 1149.1)

TMS

Test mode select (IEEE standard 1149.1)

CVSS

Supply

Ground

CVOO

Supply

+VOO

OVSS

Supply

Ground

CLKOUT

OIl

Oscillator output

X2/CLKIN

Oscillatorlexternal clock input

70-75

I/Oll

Parallel data port
+VOO

00-05

Emulator interrupt 0
Emulator interrupt 1/shut off
Test data output (IEEE standard 1149.1)
Test data input (IEEE standard 1149.1)

Machine clock output

Oevice reset

Supply

77-86

I/Oll

Parallel data port

CVOO

Supply

+VOO

CVSS

Supply

Ground

OVSS

Supply

Ground

OVOO

Supply

+VOO

91-100

OIZ

OVOO
06-015

AO-A9

t I = Input, 0

Parallel port address bus

=Output, Z =High impedance

~TEXAS

INSTRUMENTS
9-168

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

Ti'viS320C54x, Ti'vlS320LC54x, TiV1S320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039- FEBRUARY 1996

TMS320LC543, TMS320VC543
PZ PACKAGEt
(TOP VIEW)

CVSS
A10

D4
D3

A11
A12
A13

A14

D1
DO

A15

As
X2ICLKIN

CVDD
DVSS

cVss

CLKOUT

CVDD

DVss

READY

CVDD

CVSS
TMS

z
o

TCK
TRST

MSTRB

TDI

10STRB

TDO
EMU1/0FF

EMUO

HOLDA

TOUT

IAQ

~
~

CNT

HOLD

CLKMD3

BIO

CLKMD2

MP/MC

CLKMD1

o11.
Z

1:= If:
~dd~~g~dd~£~~~~g~~z~~~~£~
CfJ

cr: cr: cr: cr: cr: cr:

al I-

alI-

CfJ 0

CfJ X

I~ I~

CfJ

OVSS and OVOO are power supplies for I/O pins while CVSS and CVOO are power supplies for core CPU.

The pin function table on the following pages lists each pin number, signal, function, and operating mode(s) for
the TMS320LC543PZ/TMS320VC543PZ (1 OO-pin) packages.
For the 'LC543 and 'VC543, the letter B in front of CLKR, FSR, DR, CLKX, FSX, and OX means buffered serial
port (BSP). The letterT in front of CLKR, FSR, DR, CLKX, FSX, and OX means time-division multiplexed (TOM) .

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-169

~
c

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC543PZ/TMS320VC543PZ (100-Pin TQFP Package)
PIN
NAME
CVSS
A10-A15
CVDD

»c

~
z

o
m

-z

DESCRIPTION

FUNCTIONt

Supply

2-7

O/Z

Ground

Supply

+VDD

Parallel port address bus

DVSS

Supply

Ground

CVSS

Supply

Ground

CVDD

Supply

+VDD

READY

O/Z

Program space select

O/Z

Data space select

External access ready to complete

O/Z

I/O space select

R/W

O/Z

Read/write

MSTRB

O/Z

External memory access strobe

10STRB

O/Z

External I/O access strobe

MSC

O/Z

Microstate complete

O/Z

External flag

HOLDA

O/Z

Hold acknowledge

lAO

O/Z

Instruction acquisition

HOLD

Request access of local memory

BIO

Bit I/O pin

MP/MC

DVSS

Supply

Microprocessor/microcomputer
Ground

BClKR

Buffered serial port receive clock

TClKR

TDM serial port receive clock

BFSR

Buffered serial port receive frame synchronization

TFSR

TDM serial port receive frarne synchronization

o
z

BDR

Buffered serial port data receive

TDR

TDM serial port data receive

BClKX

I/O/Z

Buffered serial port transmit clock

TClKX

I/O/Z

TDM serial port transmit clock

CVSS

Supply

Ground

CVDD

Supply

+VDD

BFSX

I/O/Z

Buffered serial port transmit frame synchronization

TFSX

I/O/Z

TDM serial port transmit frame synchronization

DVDD

Supply

+VDD

DVSS

Supply

Ground

BDX

O/Z

Buffered serial port transmit output

TDX

O/Z

TDM serial port transmit output

t I = Input, 0

=Output, Z = High impedance

~TEXAS

INSTRUMENTS
9-170

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC543PZ/TMS320VC543PZ (100-Pin TQFP Package) (Continued)
PIN
NAME

DESCRIPTION

FUNCTIONt

lACK

OIl

Interrupt acknowledge

NMI

Non-maskable interrupt

INTO-INT3

45-48

Supply

+VDD

CVSS

Supply

Ground

CLKMD1

Clock mode pin 1

CLKMD2

Clock mode pin 2

CLKMD3

Clock mode pin 3

CNT

TOUT

Oil

EMUO

I/0Il

Emulator interrupt 0

EMU1/0FF

I/0Il

Emulator interrupt 1/shut off

TDO

OIl

TDI

TRST

Test reset (IEEE standard 1149.1)

TCK

Test clock (IEEE standard 1149.1)

TMS

Test mode select (IEEE standard 1149.1)

CVSS

Supply

Ground

CVDD

Supply

+VDD

DVSS

Supply

Ground

CLKOUT

OIl

CVDD

Interrupt 0 through Interrupt 3

1/0 level select
Timer output

ou.
Z

Machine clock output

Oscillatorlexternal clock input

Device reset

70-75

I/Oll

Parallel data port

Supply

+VDD

77-86

I/0Il

Parallel data port

CVDD

Supply

+VDD

CVSS

Supply

Ground

DVSS

Supply

Ground

DVDD

Supply

+VDD

AO-A9

91-100

OIl

D6-D15

Oscillator output

DVDD

o
~

Test data input (IEEE standard 1149.1)

X2/CLKIN

DO-D5

Test data output (IEEE standard 1149.1)

o
Z

c:(

Parallel port address bus

t I = Input, 0 =Output, l = High impedance

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-171

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

TMS320LC546, TMS320VC546
PZ PACKAGEt
(TOP VIEW)

CVSS
A10
A11

A12
A13

D4
D3
D1
DO

A14
A15
CVDD

RS
X2ICLKIN

DVSS

cVss

CLKOUT

DVss

CVDD
READY

CVDD

»c

TCK

RiW

~
z

TRST

MSTRB

TOI

10STRB
MSC

TOO
EMU1/0FF

EMUO
TOUT

HOLDA

o
m

IAQ

CNT

HOLD

-z

a
:D
s:

CVSS
TMS

BIO

CLKMD3
CLKMD2

MP/Mc

CLKMD1

(f) cr ~ cr ~ cr ~ x ~ (f) Cl X ~

Cl (f) X ~ I~

1-1

IN I'"

Cl (f)

~~cr(f)crClcr~~(f)Cl(f)~Cl~Cl~O~~~~~Cl(f)

Clgd~~WCl~d~~~~~ClW

----~~

a
z

For the 'LC546 and 'VC546, the letter S in front of CLKR, FSR, DR, FSX, and OX means SSP.

~TEXAS

9-172

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TiV1S320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Pin Functions for the TMS320LC546PZ/TMS320VC546PZ (1 OO-Pin TQFP Package)
PIN
NAME
CVSS
A10-A15
CVOO

DESCRIPTION

FUNCTIONt

Supply

2-7

O/Z

Ground

Supply

+VOO

Parallel port address bus

OVSS

Supply

Ground

CVSS

Supply

Ground

CVOO

Supply

+VOO

READY

O/Z

Data space select

O/Z

I/O space select

R/W

O/Z

Read/write

MSTRB

O/Z

External memory access strobe

10STRB

O/Z

External I/O access strobe

MSC

O/Z

Microstate complete

O/Z

External flag

HOLDA

O/Z

Hold acknowledge
Instruction acqUisition

External access ready to cornplete
Program space select

lAO

O/Z

HOLD

Request access of local memory

BIO

Bit I/O pin

MP/MC

OVSS

Supply

BCLKR

Buffered serial port receive clock

CLKR1

Serial port 1 receive clock

BFSR

Buffered serial port receive frame synchronization

FSR1

Serial port 1 receive frame synchronization

BOR

Buffered serial port data receive

OR1

Serial port 1 data receive

BCLKX

I/O/Z

Buffered serial port transmit clock

CLKX1

I/O/Z

Serial port 1 transmit clock

CVSS

Supply

Ground

CVOO

Supply

+VOO

o
IJ..

Microprocessor/microcomputer

BFSX

I/O/Z

Buffered serial port transmit frame synchronization

I/O/Z

Serial port 1 transmit frame synchronization

OVOO

Supply

+VOO

OVSS

Supply

BOX

O/Z

Buffered serial port transmit output

O/Z

Serial port 1 transmit output

I = Input, 0

o
~
Z

Ground

FSX1

OX1

o
Z

TOO

O/l

TDI

Test data input (IEEE standard 1149.1)

TRST

Test reset (IEEE standard 1149.1)

TCK

Test clock (IEEE standard 1149.1)

TMS

Test mode select (IEEE standard 1149.1)

CVSS

Supply

Ground

CVOO

Supply

+VOO

OVSS

Supply

CLKOUT

O/l

Oscillator output

X2/CLKIN

Oscillator/external clock input

70-75

I/O/l

Parallel data port
+VOO

C
Z

(")

-z

o
z

00-05

Emulator interrupt 1/shut off
Test data output (IEEE standard 1149.1)

Ground
Machine clock output

Oevice reset

Supply

77-86

I/O/l

Parallel data port

CVOO

Supply

+VOO

CVSS

Supply

Ground

OVSS

Supply

Ground

OVOO

Supply

+VOO

AO-A9

91-100

O/l

OVOO
06-015

Parallel port address bus

t I = Input, 0 =Output, l = High impedance

~TEXAS

INSTRUMENTS
9-174

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TiVlS320C54x, TiV1S320LC54x, iiV1S320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

The following tables list each signal, function, and operating mode(s) grouped by function.

Signal Descriptions
PIN
NAME

DESCRIPTION

TYPEt
DATA SIGNALS

A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
AO

(MSB)

015
014
013
012
011
010
09
08
07
06
05
04
03
02
01
00

(MSB)

Parallel address bus A15 (MSB) through AO (LSB). A15-AO are multiplexed to address external data/program memory or I/O. A15-AO are placed in the high-impedance state in the hold mode. A15-AO also go
into the high-impedance state when OFF is low.

O/Z

z
o
(LSB)
Parallel data bus 015 (MSB) through 00 (LSB). 015-00 are multiplexed to transfer data between the core
CPU and external data/program memory or I/O devices. 015- 00 are placed in high-impedance state when
not output or when RS or HOLO is asserted. 015-00 also go into the high-impedance state when OFF is
low. The data bus has a feature called bus holder that eliminates passive components and power dissipation
associated with it. The bus holder keeps the data bus at the previous logic level when the bus goes into a
high-impedance state.

~
~

a:
o
LL
Z

I/O/Z

o
Z

~
C

(LSB)

MEMORY CONTROL SIGNALS
DS
PS

MSTRB

O/Z

Memory strobe signal. MSTRB is always high unless low-level asserted to indicate an external bus access to data
or program memory. Placed in high-impedance state in hold mode. MSTRB also goes into the high-impedance
state when OFF is low.

READY

Data ready input. READY indicates that an external device is prepared for a bus transaction to be completed. If
the device is not ready (READY is low), the processor waits one cycle and checks READY again. Note that the
processor performs ready detection if at least two software wait states are programmed. The READY signal is not
sampled until the completion of the software wait states.

Rfiij

O/Z

Read/write signal. R/W indicates transfer direction during communication to an external device and is normally
in read mode (high), unless asserted low when the DSP performs a write operation. Placed in the high-impedance
state in hold mode, R/IN also goes into the high-impedance state when OFF is low.

10STRB

O/Z

I/O strobe signal. 10STRB is always high unless low level asserted to indicate an external bus access to an I/O
device. Placed in high-impedance state in hold mode. 10STRB also goes into the high-impedance state when OFF
is low.

Hold input. HOLD is asserted to request control of the address, data, and control lines. When acknowledged by
the 'C54x, these lines go into high-impedance state.

HOLDA

O/Z

Hold acknowledge signal. HOLDA indicates to the external circuitry that the processor is in a hold state and that
the address, data, and control lines are in a high-impedance state allowing them to be available to the external
circuitry. HOLDA also goes into the high-impedance state when is OFF low.

MSC

01Z

Microstate complete signal. MSC goes low when the last wait state of two or more internal software wait states
programmed are executed. If connected to the READY line, it forces one external wait state after the last internal
wait state has been completed. MSC also goes into the high-impedance state when OFF is low.

lAO

O/Z

Instruction acquisition signal. lAO is asserted (active low) when there is an instruction address on the address bus
and goes into the high-impedance state when OFF is low.

"o::D
S

o
z

HOLD

t I = Input, 0 = Output, Z = High impedance

~TEXAS

INSTRUMENTS
9-176

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54J{, TMS320VC54J{
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Signal Descriptions (Continued)
PIN
NAME

DESCRIPTION

TYPEt

OSCILLATOR/TIMER SIGNALS
CLKOUT

O/Z

Master clock output signal. CLKOUT cycles at the machine-cycle rate of the CPU. The internal machine cycle
is bounded by the rising edges of this signal. CLKOUT also goes into the high-impedance state when OFF is low.

CLKM01
CLKM02
CLKM03

Clock mode external/internal input signals. They allow you to select and configure different clock modes such
as crystal, external clock, various PLL factors.

X2/CLKIN

Input pin to internal oscillator from the crystal. If the internal (crystal) oscillator is not being used, a clock can
become input to the device using this pin. The internal machine cycle time is determined by the clock operating
mode pins (CLKM01, CLKM02 and CLKM03).

Output pin from the internal oscillator for the crystal. If the internal oscillator is not used, X1 should be left
unconnected. X1 does not go into the high-impedance state when OFF is low.

TOUT

Timer output. TOUT signals a pulse when the on-Chip timer counts down past zero. The pulse is a CLKOUT cycle
wide. TOUT also goes into the high-impedance state when OFF is low.

BUFFERED SERIAL PORT (BSP) SIGNALS

BCLKR

Receive clock input. BCLKR serves as the serial shift clock for the buffered serial port receiver.

BOR

Serial data receive input.

BFSR

Frame synchronization pulse for receive input. The BFSR pulse initiates the receive data process over BOR.

BCLKX

I/O/Z

Transmit clock. BCLKX serves as the serial shift clock for the buffered serial port transmitter. If RS is asserted
when BCLKX is configured as output, then BCLKX is turned into input mode by reset operation. BCLKX goes into
the high-impedance state when OFF is low.

BOX

O/Z

Serial data transmit output. BOX is placed in the high-impedance state when not transmitting, when RS is
asserted or when OFF is low.

BFSX

I/O/Z

Frame synchronization pulse for transmit input! output. The BFSX pulse initiates the transmit data process over
BOX. If RS is asserted when BFSX is configured as output, then BFSX is turned into input mode by reset
operation. BFSX goes into the high-impedance state when OFF is low.

SERIAL PORT 0 AND SERIAL PORT 1 SIGNALS
CLKRO
CLKR1

CLKXO
CLKX1
ORO
OR1
OXO
OX1

Receive clocks. External clock signal for clocking data from the data receive (OR) pin into the serial port receive
shift registers (RSR). Must be present during serial port transfers. If the serial port is not being used, CLKRO and
CLKR1 can be sampled as an input via INO bit of the SPC register.

I/O/Z

Transmit clock. Clock signal for clocking data from the serial port transmit shift register (XSR) to the data transmit
(OX) pin. CLKX can be an input if MCM in the serial port control register is cleared to O. It also can be driven by
the device at 1/4 CLKOUT frequency when MCM is set to 1. If the serial port is not used, CLKX can be sampled
as an input via IN1 of the SPC register. CLKXO and CLKX1 go into the high-impedance state when OFF is low.

Serial-data-receive input. Serial data is received in the RSR by DR.

O/Z

Serial port transmit output. Serial data is transmitted from the XSR via OX. OXO and OX1 are placed in the
high-impedance state when not transmitting and when OFF is low.

FSRO
FSR1

Frame synchronization pulse for receive input. The falling edge of the FSR pulse initiates the data-receive
process, beginning the clocking of the RSA.

FSXO
FSX1

I/O/Z

Frame synchronization pulse for transmit input/output. The falling edge of the FSX pulse initiates the data
transmit process, beginning the clocking of the XSR. Following reset, the default operating condition of FSX is
an input. FSXO and FSX1 can be selected by software to be an output when TXM in the serial control register
is set to 1. This pin goes into the high-impedance state when OFF is low.

t I = Input, 0 =Output, Z = High impedance

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-177

o
~

:2E

o
L1.
Z

o
Z

~
c

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039- FEBRUARY 1996

Signal Descriptions (Continued)
PIN
NAME

DESCRIPTION

TYPEt

TDM SERIAL PORT SIGNAL
TCLKR
TDR
TFSR/TADD
TCLKX

Receive clock input

Serial data receive input

I/O

Receive frame synchronization or address

I/O/l

Transmit clock

TDX

O/l

Serial data transmit output

TFSX/TFRM

I/O/l

Transmit frame synchronization
MISCELLANEOUS PIN
No connection

HOST PORT INTERFACE SIGNALS
HDD-HD7

Parallel bi-directional data bus. HDD-HD7 are placed in high-impedance state when not outputting data. The
signals go into the high-impedance state when OFF is low.

I/O/l

HCNTLO
HCNTL1

Control inputs

HBIL

Byte identification input

HCS

Chip select input

HDS1
HDS2

Data strobe inputs

HAS

Address strobe input

HRW

Read/write input

HRDY

Oil

Ready output. This signal goes into the high-impedance state when OFF is low.

O/l

Interrupt output. When the DSP is in reset, this signal is driven high. The signal goes into the high-impedance
state when OFF is low.

HPI module select input. This signal must be tied to VDD to have HPI selected. If this input is left open or
connected to ground, HPI module will not be selected, internal pullup for HPI input pins are enabled and HPI
data bus has keepers set.

o
m

-z

o
:c
s::
~
o
z

HINT

HPIENAIVDD

SUPPLY PNS

Supply

Ground. CVSS is the dedicated power supply for the core CPU.

CVDD

Supply

+VDD. CVDD is the dedicated power supply for the core CPU.

DVSS

Supply

Ground. DVSS is the dedicated power supply for I/O pins.

DVDD

Supply

+VDD. DVDD is the dedicated power supply for I/O pins.

CVSS

TEST PINS

TCK

IEEE standard 1149.1 test clock. This is normally a free-running clock signal with a 50% duty cycle. The
changes on test access port (TAP) of input signals TMS and TDI are clocked into the TAP controller, instruction
register, or selected test data register on the rising edge of TCK. Changes at the TAP output signal (TDO) occur
on the falling edge of TCK.

IEEE standard 1149.1 test data input, pin with internal pullup device. TDI is clocked into the selected register
(instruction or data) on a rising edge of TCK.

Oil

IEEE standard 1149.1 test data output. The contents of the selected register (instruction or data) is shifted out
of TDO on the falling edge of TCK. TDO is in the high-impedance state except when scanning of data is in
progress. TDO also goes into the high-impedance state when OFF is low.

TDO
t I = Input, 0

=Output, l = High impedance

•
TEXAS
INSTRUMENTS
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Signal Descriptions (Continued)
PIN
NAME

DESCRIPTION

TYPEt

TEST PINS (CONTINUED)
TMS

IEEE standard 1149.1 test mode select. Pin with internal pullup device. This serial control input is clocked into
the test access port (TAP) controller on the rising edge of TCK.

TRST

IEEE standard 1149.1 test reset. TRST, when high, gives the IEEE standard 1149.1 scan system control of the
operations of the device. If TRST is not connected or driven low, the device operates in its functional mode, and
the IEEE standard 1149.1 signals are ignored. Pin with internal pullup device.

EMUO

I/OIl

Emulator 0 pin. When TRST is driven low, EMUO must be high for activation of the OFF condition. When TRST
is driven high, EMUO is used as an interrupt to or from the emulator system and is defined as input/output via
IEEE standard 1149.1 scan system.

I/OIl

Emulator 1 pin/disable all outputs. When TRST is driven high, EMU1 IOFF is used as an interrupt to or from the
emulator system and is defined as input/output via IEEE standard 1149.1 scan system. When TRST is driven
low, EMU1 IOFF is configured as OFF. The EMU1 IOFF signal, when active low, puts all output drivers into the
high-impedance state. Note that OFF is used exclusively for testing and emulation purposes (not for
multiprocessing applications). Thus, for OFF condition, the following conditions apply:
TRST= low,
EMUO = high
EMU1 IOFF = low

EMU1/0FF

t I = Input, 0 = Output, l = High impedance

architecture

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:2E

The 'C54x/'LC54x/'VC54x DSPs use an advanced, modified Harvard architecture that maximizes processing
power by maintaining three separate bus structures for data memory and one for program memory. Separate
program and data spaces allow simultaneous access to program instructions and data, providing a high degree
of parallelism. For example, two reads and one write operation can be performed in a single cycle. Instructions
with parallel store and application-specific instructions fully utilize this architecture. In addition, data can be
transferred between data and program spaces. Such parallelism supports a powerful set of arithmetic, logic,
and bit-manipulation operations that all can be performed in a single machine cycle. In addition, the
'C54x/'LC54x/'VC54x include the control mechanisms to manage interrupts, repeated operations, and function
calling.
The functional block diagram includes the principal blocks and bus structure in the 'C54x/'LC54x/'VC54x
devices.

~TEXAS

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

9-179

a::
o
11.
Z
W

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~
C

ARAUO, ARAU1

PC
BRC, RC, RSA, REA
IPTR

Peripheral
Interface

TREG
Register

EXP Encoder

A~
~

+WT~,

,~,

~,~

TTI

o
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Multiplier (17 x 17)

ACCA(40)

0
U~

I I

ACCB(40)

' +~~ ~A~L

~'~d""")~
ZERO

+I
SAT

, ,+

~,~

~h,

ROUND

COMP

TRN
TC

~TEXAS

9-180

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

,~,

ALU(40)

Barrel Shifter

MSW/LSW
Select

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

bus structure
The 'C54x/'LC54x/'VC54x device architecture is built around eight major 16-bit buses:
•

One program bus (P bus), which carries the instruction code and immediate operands from program
memory

Three data buses (CB, DB, and EB), which interconnect to various elements, such as the CPU,
data-address generation logic, program-address generation logic, on-chip peripherals, and data memory
The CB and DB carry the operands read from data memory.
The EB carries the data to be written to memory.

Four address buses (PAB, CAB, DAB, and EAB), which carry the addresses needed for instruction
execution

The 'C54x/'LC54x/'VC54x devices have the capability to generate up to two data memory addresses per cycle,
which are stored into two auxiliary register arithmetic units (ARAUO and ARAU1).
The program bus (PB) can carry data operands stored in program space (for instance, a coefficient table) to
the multiplier for multiply / accumulate operations or to a destination in data space for the data move instruction.
This capability allows implementation of single-cycle three-operand instructions such as FIRS.
The 'C54x/'LC54x/'VC54x devices also have an on-chip bi-directional bus for accessing on-chip peripherals;
this bus is connected to DB and EB through the bus exchanger in the CPU interface. Accesses using this bus
can require more than two cycles for reads and writes depending on the peripheral's structure.
The 'C54x/'LC54x/'VC54x devices can have bus keepers connected to the data bus. Bus keepers ensure that
the data bus does not float. When bus keepers are enabled, the data bus maintains its previous level. Setting
bit 1 of the bank switching control register (BSCR) enables bus keepers and clearing bit 1 disables the bus
keepers. Resets automatically disable the bus keepers.
Table 2 summarizes the buses used by various types of accesses.

PAB
-V

Program write

-V

CAB

DAB

Data long (32-bit) read

-V

-V(hw)

-v(lw)

-v(hw)

-V(lw)

-V
-V

Data read/data write
-V

-V

~
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-n

Guard bits (bits 32-39)
A high-order word (bits 16-31)
A low-order word (bits 0-15)

barrel shifter
The 'C54x/'LC54x/'VC54x's barrel shifter has a 40-bit input connected to the accumulator, or data memory (C,
D bus) and a 40-bit output connected to the ALU, or data memory (E bus). The barrel shifter produces a left shift
of 0 to 31 bits and a right shift of 0 to 16 bits on the input data. The shift requirements are defined in the shift
count field (ASM) of ST1 or defined in the temporary register (TREG), which is designated as a shift count
register. This shifter and the exponent detector normalize the values in an accumulator in a single cycle. The
LSBs of the output are filled with Os and the MSBs can be either zero-filled or sign-extended, depending on the
state of the sign-extended mode bit (SXM) of ST1. Additional shift capabilities enable the processor to perform
numerical scaling, bit extraction, extended arithmetic, and overflow prevention operations.

o
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multiplier/adder
The multiplier / adder performs 17 x 17-bit 2s-complement multiplication with a 40-bit accumulation in a single
instruction cycle. The multiplier / adder block consists of several elements: a multiplier, adder, signed / unsigned
input control, fractional control, a zero detector, a rounder (2s-complement), overflow / saturation logic, and
TREG. The multiplier has two inputs: one input is selected from either TREG, data memory operand, or an
accumulator; the other is selected from either program memory, data memory, an accumulator, or an immediate
value. The fast on-chip multiplier allows the 'C54x to efficiently perform operations such as convolution,
correlation, and filtering.
In addition, the multiplier and ALU together execute multiply/accumulate (MAC) computations and ALU
operations in parallel in a single instruction cycle. This function is used in determining the Euclid distance, and
implementing symmetrical and LMS filters, which are required for complex DSP algorithms .

•
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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

compare, select and store unit (CSSU)
The compare, select, and store unit (CSSU) performs maximum comparisons between the accumulator's high
and low word, allows test/control (TC) flag bit of status control register 0 (STO) and transition (TRN) register
to keep their transition histories, and selects larger word in accumulator to be stored into data memory. The
CSSU also accelerates Viterbi-type butterfly computation with optimized on-chip hardware.

program control
Program control is provided by several hardware and software mechanisms:
•

The program controller decodes instructions, manages the pipeline, stores the status of operations, and
decodes conditional operations. Some of the hardware elements included in the program controller are the
program counter, the status and control register, the stack, and the address-generation logic.

•

Some of the software mechanisms used for program control include branches, calls, conditional
instructions, a repeat instruction, reset, and interrupts.

power-down modes
There are three power-down modes, activated by the IDLE1, IDLE2, and IDLE3 instructions. In these modes,
the 'C54x1'LC54x1'VC54x enters a dormant state and dissipates considerably less power than in normal
operation. The IDLE1 instruction is used to shut down the CPU. The IDLE2 instruction is used to shut down the
CPU and on-chip peripherals. The IDLE3 instruction is used to completely shut down the 'C54x1'LC54x1'VC54x
processor. This instruction stops the PLL circuitry as well as the CPU and peripherals.

~
~

memory

The total memory address range of the 'C54x/'LC54x/'VC54x devices is 192K 16-bit words. The memory space
is divided into three specific memory segments: 64K word program, 64K-word data, and 64K-word 1/0. The
program memory space contains the instructions to be executed as well as tables used in execution. The data
memory space stores data used by the instructions. The 1/0 memory space interfaces to external
memory-mapped peripherals and can also serve as extra data storage space.
The parallel nature of the architecture of these DSPs allows them to perform four concurrent memory operations
in any given machine cycle: fetching an instruction, reading two operands, and writing an operand. The four
parallel buses are the program-read bus (PB), the write-data bus (EB) and two read-data buses (CB and DB).
Each bus accesses different memory spaces for' different aspects of the DSPs operation. Additionally, this
architecture allows dual-operand reads, 32-bit-long word accesses, and a single read with a parallel store.
The 'C54x/'LC54x/'VC54x DSPs include on-chip memory to aid in system performance and integration.

on-chip ROM
The 'C541 , 'LC541 and 'VC541 all feature a 28K-word x 16-bit on-chip maskable ROM. 8K words of the 'C541 ,
'LC541 and 'VC541 ROM can be mapped into program and data memory space if the data ROM (DRaM) bit
in the processor mode status (PMST) register is set. This allows an instruction to use data stored in the ROM
as an operand.
The 'LC544 and 'VC544 both feature a 24K-word x 16-bit on-Chip maskable ROM. 8K words of the 'LC544 and
'VC544 ROM can be mapped into program and data memory space if the DRaM bit in the PMST register is set.
The 'LC545/'VC545/'LC546I'VC546 all feature a 48K-word x 16-bit on-chip maskable ROM. 16K words of the
ROM on these devices can be mapped into program and data memory space if the DRaM bit in the PMST
register is set.
The 'C542/'LC542/'VC542I'LC543/'VC543 all feature 2K-word x 16-bit on-chip ROM.
Customers can arrange to have the ROM of the 'C54x1'LC54x1'VC54x programmed with contents unique to any
particular application.

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9-183

ou.
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(,)

The 'C541 , 'LC541 and 'VC541 devices have a 5K-word x 16-bit on-chip dual-access RAM (DARAM) (5 blocks
of 1K-word each).

The 'C542, 'LC542, 'VC542, 'LC543 and 'VC543 have a 10K-word x 16-bit on-chip DARAM (5 blocks of 2K-word
each).

(')

The 'LC544 and 'VC544 have a 4K-word x 16-bit on-chip DARAM (2 blocks of 2K-word each).

The 'LC545, 'VC545, 'LC546 and 'VC546 have a 6K-word x 16-bit on-chip DARAM (3 blocks of 2K-word each).

"'TI

Each of these RAM blocks can be accessed twice per machine cycle. This memory is intended primarily to store
data values; however, it can be used to store program as well. At reset, the DARAM is mapped into data memory
space. DARAM can be mapped into programl data memory space by setting the OVLY bit in the PMST register.

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on-Chip memory security
The 'C54x1'LC54x1'VC54x devices have a maskable option to protect the contents of on-chip memories. When
the related bit is set, no externally originating instruction can access the on-chip memory spaces.

~
oz

9-184

•
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Ti'vIS320C54x, TiV1S320LC54x, TiVlS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

on-chip memory security (continued)
Hex
0000

Program

Hex
0000

Program
Reserved
(OVLY=1)
External
(OVLY=O)

Reserved
(OVLY=1)
External
(OVLY=O)
007F
0080

007F
0080
On-Chip DARAM
(OVLY=1)
External (OVLY=O)

On-Chip DARAM
(OVLY=1)
External (OVLY=O)

13FF
1400

8FFF
9000

External

FFFF

FF7F
FF80

Interrupts and
Reserved
(External)

FFFF

MP/MC= 1
(Microprocessor Mode)

005F
0060

Data
Memory-Mapped
Registers
Scratch-Pad RAM

007F
0080
On-Chip DARAM
(5K Words)
13FF
1400
External

External

On-Chip ROM
(28K Words)
FF7F
FF80

Hex
0000

Interrupts and
Reserved
(On-Chip)

DFFF
EOOO

On-Chip ROM
(DROM=1)
External
(DROM=O)

FEFF
FFOO

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~

Reserved
(DROM=1)
External
(DROM= 0)

FFFF

MP/MC= 0
(Microcomputer Mode)

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Figure 1. Memory Map (,C541 , 'LC541, 'VC541)

Hex
0000

Program
Reserved
(OVLY=1)
External
(OVLY=O)

007F
0080
On-Chip DARAM
(OVLY=1)
External (OVLY=O)

Reserved
(OVLY=1)
External
(OVLY=O)

007F
0080

Interrupts and
Reserved
(External)

MP/MC= 1
(Microprocessor Mode)

Hex
0000
005F
0060

FF7F
FF80
FFFF

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~
c

007F
0080

On-Chip DARAM
(10K Words)

27FF
2800

F800

Data
Memory-Mapped
Registers
Scratch-Pad

On-Chip DARAM
(OVLY=1)
External (OVLY=O)

EFFF
FOOO
External

FFFF

ProQram

External

27FF
2800

FF7F
FF80

Hex
0000

27FF
2800

Reserved
External

On-Chip ROM
(2KWords)
Interrupts and
Reserved
(On-Chip)

FFFF

MP/MC= 0
(Microcomputer Mode)

Figure 2. Memory Map (,C542, 'LC542, 'VC542, 'LC543 and 'VC543)

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9-185

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

on-chip memory security (continued)
Hex
0000

Program

Hex
0000

Reserved
(OVLY=1)
External
(OVLY=O)

Reserved
(OVLY=1)
External
(OVLY=O)
007F
0080

007F
0080

17FF
1800

FF7F
FF80

FFFF

Z
0

Interrupts and
Reserved
(External)
MP/MC= 1
(Microprocessor Mode)

-mz

On-Chip DARAM
(6K Words)

3FFF
4000

FF7F
FF80
FFFF

Interrupts and
Reserved
(On-Chip)

BFFF
COOO

FEFF
FFOO
FFFF

MP/MC= 0
(Microcomputer Mode)

Figure 3. Memory Map (,LC545, 'VC545, 'LC546, and 'VC546)

"0JJ
S

~TEXAS

9-186

Scratch-Pad RAM

007F
0080

External
External
On-Chip ROM
(48K Words)

005F
0060

Data
Memory-Mapped
Registers

17FF
1800
17FF
1800

External

Hex
0000

On-Chip DARAM
(OVLY=1)
External (OVLY=O)

Program

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

On-Chip ROM
(DROM=1)
External
(DROM=O)
Reserved
(DROM=1)
External
(DROM= 0)

TMS320C54;{, TMS320LC54;{, TMS320VC54;{
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

'LC5441'VC544 memory maps

Internal
Address

External
Physical
Address
A[O:14]
Prog Space

OOOOh

007Fh
0080h

OOOOh~OVLY=O~
or NO OVLY=1

VLV
or NO OVLY=1
DD7F"r
=D!
0080h OVLY=O
or NO OVLY=1

OFFFh
1000h

OFFFh(OVLY=O)
or NO(OVLY=1)
1000h

1FFFh
2000h

7FFFh
8000h

9FFFh
AOOOh

7FFFh
OOOOh

1FFFh
NO (see Note A)

External (OVLY=O)
(see Note B)
or Reserved (OVLY=1)

External (OVLY=O)
(see Note B)
or On-Chip RAM (OVLY=1)
(4K words)
External
(see Note B)

z
o

External
(24K words)
Can be in same physical memory as
data values since PS and OS
signals are not present on '544
(see Note C)

[[

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11.

External
(8K words)

Can be in same physical memory as
data values since PS and OS
signals are not present on '544
(see Note C)

o
Z

On-Chip ROM
(24Kwords)

C
FF7Fh
FF80h

(see Note A)

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m

External
(32K words)

-z

Can be in same physical memory as
data values since PS and OS
signals are not present on '544
(see Note B)

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FF7Fh
FF80h

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7F7Fh
7F80h
Interru~t

Vector Table
xternal

FFFFh

7FFFh

NOTES: A. The space placed between OOOOh and 7FFFh (when OVLY is off) or between 1000h and 7FFFh (when OVLY is on) addresses
requires special attention. An access at this space is the same as an access at the image address in the 8000h-FFFFh (internal
address) space.
B. For example, access at 1000h the same as an access at internal 9000h (or, in other words, external 1000h).

Figure 5. Memory Map - Program Space With MP/MC=1 (,LC544 and 'VC544)

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iMS320C54x, Ti\;IS320LC54x, TiV1S320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

'LC5441'VC544 memory maps (continued)

Internal
Address

External
Physical
Address
A[O:14]

OOOOh
005Fh

NO (see Note D)
NO

0060h
007Fh
OOSOh

NO
NO
NO

OFFFh
1000h

NO
1000h

7FFFh

7FFFh
OOOOh

SOOOh

SFFFh
9000h

OFFFh
1000h

Data Space
Memory-Mapped
Registers
Scratch-Pad
On-Chip DARAM
(4Kwords)
External
(2SK words)
Can be in same physica.Lt!:!emor:Yils
program values since PS and OS
signals are not present on '544
(see Note 8)
External
(4Kwords)

z
o

Can be in same physical memory as
program values since PS and OS
signals are not present on '544
(see Note 8)

:2:

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L1.

External
(see Note C)
DFFFh
EOOOh
FEFFh
FFOOh

5FFFh
6000h(DROM=O)
or NO(DROM=1)
7FOOh(DROM=O)
or NO(DROM=1)

External (DROM=O)
(see Note D)
or On-Chip DROM (DROM=1)

(.)
External (DROM=O)
(see Note D)
or Reserved (DROM=1)

FFFFh
NOTES: A. This space is on-chip only. NO means no external access.
B. It is the user's responsibility to make sure that data and program do not overlay in the same external physical addresses.
C. The 20K words of space placed between 9000h and DFFFh internal addresses requires special attention. An access at this space
is the same as an access at the image address in the 1OOOh-SFFFh space. For example, access at BOOOh (internal address) is an
access at external 3000h.
D. When DROM=O, the 8K words of space placed between EOOOh and FFFFh internal addresses requires special attention. An access
at this space is the same as an access at the image address in the 6000h-7FFFh space.

Figure 6. Memory Map - Data Space (,LC544 and 'VC544)
The external memory space on the 'LC544 and 'VC544 device addresses up to 32K of 16-bit words through
its external 15 line address bus A[O:14]. Since A15 line still is present in internal address buses, the internal
address reach is 64K for both data and program spaces. Two types of addresses are defined in Figure 4,
Figure 5, and Figure 6.
-> internal address which appears on internal buses (PAB, CAB, DAB, EAB).
-> external physical address which appears on the external A[O: 14] bus.

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9-189

At device reset, the reset, interrupt, and trap vectors are mapped to address FF80h in program space. However,
these vectors can be remapped to the beginning of any 128-word page in program space after device reset.
This is done by loading the interrupt vector pointer (IPTR) bits in the PMST register with the appropriate
128-word page boundary address. After loading IPTR, any user interrupt or trap vector is mapped to the new
128-word page. For example:

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STM

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iRemapped vectors to start at 5800h.

This example moves the interrupt vectors to off-chip program space at address 05800h. Any subsequent
interrupt (except for a device reset) fetches its interrupt vector from that new location. For example, if, after
loading the IPTR, an INT2 occurs, the interrupt service routine vector is fetched from location 5848h in program
space as opposed to location FFC8h. This feature facilitates moving the desired vectors out of the boot ROM
and then removing the ROM from the memory map. Once the system code is booted into the system from the
boot-loader code resident in ROM, the application reloads the IPTR with a value pOinting to the new vectors.
In the previous example, the STM instruction is used to modify the PMST. Note that the STM instruction modifies
not only the IPTR but other status/control bits in the PMST register.

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:s:

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#05800h,PMST

NOTE: The hardware reset (RS) vector can not be remapped, because the hardware reset loads the IPTR with 1s. Therefore, the reset vector
is always fetched at location FF80h in program space. In addition, for the 'C54x/'LC54x/'VC54x, 128 words are reserved in the on-Chip
ROM for device-testing purposes. Application code written to be implemented in on-Chip ROM must reserve these 128 words at addresses
FFOOh-FF7Fh in program space.

data memory
The data memory space on the 'C54x/'LC54x/'VC54x device addresses contains up to 64K of 16-bit words.
The 'C54x/'LC54x/'VC54x devices automatically access the on-Chip RAM when addressing within its bounds.
When an address is generated outside the RAM bounds, the device automatically generates an external
access.
The advantages of operating from on-chip memory are as follows:
•
•
•
•

Higher performance because no wait states are required
Higher performance because of better flow within the pipeline of the CALU
Lower cost than external memory
Lower power than external memory

The advantage of operating from off-chip memory is the ability to access a larger address space .

•
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TiIIiS320C54x, TiviS320LC54x, TiviS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

on-chip peripherals
All the 'C54x/'LC54xI'VC54x devices have the same CPU structure; however, they have different on-chip
peripherals connected to their CPUs. The on-chip peripheral options provided are:
•
•
•
Q

•
•

Software-programmable wait-state generator
Programmable bank switching
Parallel I/O ports
Serial ports
A hardware timer
A clock generator

software-programmable wait-state generator
Software-programmable wait-state generators can be used to extend external bus cycles up to seven machine
cycles to interface with slower off-chip memory and I/O devices. The software wait-state generators are
incorporated without any external hardware. For off-chip memory access, a number of wait states can be
specified for every 32K-word block of program and data memory space, and for one 64K-word block of I/O
space within the software wait-state (SWWSR) register.

programmable bank switching
Programmable bank switching can be used to insert one cycle automatically when croSSing memory-bank
boundaries inside program memory or data memory space. One cycle also can be inserted when crossing from
program-memory space to data-memory space. This extra cycle allows memory devices to release the bus
before other devices start driving the bus; thus avoiding bus contention. The size of memory bank for the bank
switching is defined by the bank switching control register (BSCR).

parallel 110 ports
Each 'C54x/'LC54x/'VC54x device has a total of 64K-I/0 ports. These ports can be addressed by the PORTR
instruction or the PORTW instruction. The IS signal indicates a read/write operation through an I/O port. The
'C54xI'LC54x/'VC54x devices can interface easily with external devices through the I/O ports while requiring
minimal off-chip address decoding circuits.

~
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a:
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Z

()

host-port interface (,C542, 'LC542, 'VC542, 'LC545, and 'VC545 only)
The host-port interface is an a-bit parallel port used to interface a host processor to the DSP device. Information
is exchanged between the DSP device and the host processor through on-chip memory that is accessible by
both the host and the DSP device. The DSP devices have access to the HPI control (HPIC) register and the
host can address the HPI memory through the HPI address register (HPIA). HPI memory is a 2K 16-bit DARAM
block which can also be used as general-purpose on-chip data or program DARAM.
Data transfers of 16-bit words occur as two consecutive bytes with a dedicated pin (HBIL) indicating whether
the high or low byte is being transmitted. Two control pins, HCNTL 1 and HCNTLO, control host access to the
HPIA, HPI data (with an optional automatic address increment), or the HPIC. The host can interrupt the DSP
device by writing to HPIC. The DSP device can interrupt the host with a dedicated HINT pin that the host can
acknowledge and clear.
The HPI has two modes of operation, shared-access mode (SAM) and host-only mode (HOM). In SAM, the
normal mode of operation, both the DSP device and the host can access HPI memory. In this mode,
asynchronous host accesses are resynchronized internally and, in case of conflict, the host has access priority
and the DSP device waits one cycle. The HOM capability allows the host to access HPI memory while the DSP
device is in IDLE2 (all internal clocks stopped) or in reset mode. The host can therefore access the HPI RAM
while the DSP device is in its optimal configuration in terms of power consumption.

"TEXAS
INSTRUMENTS
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z
o

9-191

o
m

-z

The TOM port allows the device to communicate through time-division multiplexing with up to seven other
'C54x1'LC54x1'VC54x devices with TOM ports. Time-division multiplexing is the division of time intervals into
a number of subintervals with each subinterval representing a prespecified communications channel. The TDM
port serially transmits 16-bit words on a single data line (TOAT) and destination addresses on a single address
line (TADO). Each device can transmit data on a Single channel and receive data from one or more of the eight
channels providing a simple and efficient interface for multiprocessing applications. A frame synchronization
pulse occurs once every 128 clock cycles corresponding to transmission of one 16-bit word on each of the eight
channels. Like the general-purpose serial port, the TOM port is double buffered on both input and output data.
The TOM port can also be configured in software to operate as a general-purpose serial port as described
above. Both types of ports described above are capable of operating at up to one-fourth the machine cycle rate
(CLKOUT).

o
JJ
s:

~
o
z

The buffered-serial port (BSP) consists of a full-duplex double-buffered serial-port interface (SPI) and an
auto-buffering unit (ABU). The SPI block of the BSP is an enhanced version of the general-purpose serial port.
The auto-buffering unit allows the SPI to read/write directly to 'C54x1'LC54x1'VC54x internal memory using a
dedicated bus independently of the CPU. This results in minimal overhead for SPI transactions and faster data
rates.
When auto-buffering capability is disabled (standard mode), transfers with SPI are performed under software
control through interrupts. In this mode, the ABU is transparent and the word-based interrupts (WXINT and
WRINT) provided by the SPI are sent to the CPU as transmit interrupt (XINT) and receive interrupt (RINT).
When auto buffering is enabled, word transfers are done directly between the SPI and the 'C54x1'LC54x1'VC54x
internal memory using ABU-embedded address generators.

~TEXAS

INSTRUMENTS
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TiviS320C54x, TiviS320LC54x, TiViS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

serial ports (continued)
The ABU has its own set of circular-addressing registers with corresponding address-generation units. Memory
for the buffers resides in 2K words of 'C54x1'LC54x1'VC54x internal memory. The length and starting addresses
ofthe buffers are user programmable. A buffer-empty/-full interrupt can be posted tothe CPU. Buffering is easily
halted by an auto-disabling capability. Auto-buffering capability can be enabled separately for transmit and
receive sections. When auto buffering is disabled, operation is similar to the general-purpose serial port.
The SPI allows transfer of 8-, 10-, 12-, or 16-bit data packets. In burst mode, data packets are directed by a
frame synchronization pulse for every packet. In continuous mode, the frame synchronization pulse occurs
when the data transmission is initiated and no further pulses occur. The frame and clock strobes are frequency
and polarity programmable. The SPI is fully static and operates at arbitrarily low clock frequencies. The
maximum operating frequency is CLKOUT (40 Mb/s at 25 ns).
Table 3 provides a comparison of the serial ports available in the 'C54xI'LC54x/'VC54x generation.
Table 3. Serial Port Configurations for the 'CS4x/'LCS4x/'VCS4x
DEVICE

GENERAL-PURPOSE
SERIAL PORT

TMS320C541

TMS320LC541

TMS320VC541

BUFFERED SERIAL PORT

TOM SERIAL PORT

TMS320C542

TMS320LC542

TMS320VC542

TMS320LC543

TMS320VC543
TMS320LC544

TMS320VC544

TMS320LC545

~
~

o
LL
Z

TMS320VC545

TMS320LC546

TMS320VC546

(,)

~
c

hardware timer
The 'C54x/'LC54x/'VC54x devices feature a 16-bit timing circuit with a four-bit prescaler. The timer counter is
decremented by one at every CLKOUT cycle. Each time the counter decrements to zero, a timer interrupt is
generated. The timer can be stopped, restarted, reset, or disabled by specific status bits.
clock generator
The clock generator consists of an internal oscillator and a phase-locked loop (PLL) circuit. The clock generator
can be driven internally by connecting a crystal resonator circuit, or driven by an external clock source. The PLL
circuit can generate an internal CPU clock by multiplying the clock source frequency by a specific factor.
Therefore, you can use a clock source with a lower frequency than that of the CPU .

•
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9-193

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

memory-mapped registers
All 'C54x1'LC54x1'VC54x devices have 26 memory-mapped CPU registers, which are mapped in data memory
space address Oh to 1Fh. Each of these devices also has a set of memory-mapped registers associated with
peripherals. Table 4 gives a list of CPU memory-mapped registers (MMR) common to all 'C54x1'LC54x1'VC54x
devices. Table 5 shows additional peripheral MMRs associated with the 'C541I'LC541/'VC541I'LC544I'VC544
devices. Table 6 shows additional peripheral MMRs associated with the 'LC545/'VC545I'LC546j'VC546
devices. Table 7 shows additional peripheral MMRs associated with the 'C5421'LC542/'VC5421'LC543I'VC543
devices.

Table 4. Core Processor Memory-Mapped Registers
NAME

~
z

o
m

-z

"'T1

o
z

DESCRIPTION

Hex

IMR

Interrupt mask register

IFR

Interrupt flag register
Reserved for testing

»c

ADDRESS
Dec

2-5

STO

Status register 0

8T1

Status register 1

Accumulator A low word (15-0)

Accumulator A high word (31-16)

Accumulator A guard bits (39-32)

Accumulator B low word (15-0)

Accumulator B high word (31-16)

Accumulator B guard bits (39-32)

TREG

Temporary register

TRN

Transition register

ARO

Auxiliary register 0

AR1

Auxiliary register 1

AR2

Auxiliary register 2

AR3

Auxiliary register 3

AR4

Auxiliary register 4

AR5

Auxiliary register 5

AR6

Auxiliary register 6

AR7

Auxiliary register 7

Stack pointer register

Circular buffer size register

BRC

Block repeat Counter

RSA

Block repeat start address

REA

Block repeat end address

PMST

Processor mode status (PMST) register

30-31

1E-1F

Reserved

•
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TMS320C54x, arMS320LC54x, lMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

Table 5. Peripheral Memory-Mapped Registers (,C541 , 'LC541, 'VC541, 'LC544 and 'VC544 Only)
ADDRESS

NAME

DESCRIPTION

Dec

Hex

DRRO

DXRO

Serial port 0 data transmit register

SPCO

Serial port 0 control register

Reserved

TIM

Timer register

Serial port 0 data receive register

PRD

Timer period register

TCR

Timer control register

Reserved

SWWSR

S/W wait-state register

BSCR

Bank switching control register

42-47

2A-2F

DXR1

Serial port 1 transmit register

SPC1

Serial port 1 control register

Reserved

52-95

34-5F

Reserved

DRR1

Reserved
Serial port 1 data receive register

o
~

2
a:

Table 6. Peripheral Memory-Mapped Registers (,LC545, 'VC545, 'LC546 and 'VC546 Only)
NAME

ADDRESS
Dec

Hex

DESCRIPTION

DRR

Data receive register

BSP

DXR

Data transmit register

BSP

SPC

Serial port control register

BSP

SPCE

BSP control extension register

BSP

TIM

Timer register

Timer

PRD

Timer period counter

Timer

TCR

Timer control register

Timer

Reserved

SWWSR

S/W wait-state register

External bus

BSCR

Bank switching control register

External bus

42-43

2A-2B

HPIC

2C
2D-2F

DRR1

Data receive register

Serial port

DXR1

Transmit register

Serial port

SPC1

Serial port control register

Serial port

51-55

33-37

o
Z

DESCRIPTION

Reserved

t Host port interface (HPI) on 'LC545, 'VC545, only
t Auto-buffering unit (ABU) .

status register (STO, ST1)
The status registers, STO and ST1, contain the status of the various conditions and modes for the
'C54x/'LC54x/'VC54x devices. STO contains the flags (OV, C, and TC) produced by arithmetic operations and
bit manipulations in addition to the DP and the ARP fields. ST1 contains the various modes and instructions that
the processor operates on and executes.
accumulators (Al, AH, AG, and Bl, BH, BG)
The 'C54xI'LC54x/'VC54x devices have two 40-bit accumulators; accumulator A and accumulator B. Each
accumulator is memory-mapped and partitioned into accumulator low word (AL, BL), accumulator high word
(AH, BH), and accumulator guard bits (AG, BG).
39

AH (BH)

•
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9-196

16 15

32 31
AG(BG)

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AH(BL)

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

auxiliary registers (ARO-AR7)

The eight 16-bit auxiliary registers (ARO-AR7) can be accessed by the CALU and modified by the auxiliary
register arithmetic units (ARAUs). The primary function of the auxiliary registers is generating 16-bit addresses
for data space. However, these registers also can act as general-purpose registers or counters.
temporary register (TREG)

The TREG is used to hold one of the multiplicands for multiply and multiply / accumulate instructions. It can hold
a dynamic (execution-time programmable) shift count for instructions with shift operation such as ADD, LD, and
SUB instructions. It also can hold a dynamic bit address for the BITT instruction. The EXP instruction stores the
exponent value computed onto the TREG, while the NORM instruction uses the TREG value to normalize the
number. For ACS operation of Viterbi decoding, TREG holds branch metrics used by the DADST and DSADT
instructions.
transition register (TRN)

The TRN is a 16-bit register that is used to hold the transition decision for the path to new metrics to perform
the Viterbi algorithm. The CMPS (compare, select, max, and store) instruction updates the contents of the TRN
based on the comparison between the accumulator high word and the accumulator low word.
stack-pointer register (SP)

The SP is a 16-bit register that contains the address at the top of the system. The SP always points to the last
element pushed onto the stack. The stack is manipulated by interrupts, traps, calls, returns, and the PUSHD,
PSHM, POPD, and POPM instructions. Pushes and pops of the stack predecrement and postincrement,
respectively, all 16 bits of the SP.
circular-buffer-size register (BK)

The 16-bit BK is used by the ARAUs in circular addressing to specify the data block size.

z
o

:a:
a:
o
u.
Z

block repeat registers (BRe, RSA, REA)

The block-repeat counter (BRC) is a 16-bit register used to specify the number of times a block of code is to
be repeated when performing a block repeat. The block-repeat start address (RSA) is a 16-bit register
containing the starting address of the block of program memory to be repeated when operating in the repeat
mode. The 16-bit block repeat-end address (REA) contains the ending address if the block of program memory
is to be repeated when operating in the repeat mode.

U
Z

interrupt registers (IMR, IFR)

The interrupt-mask register (IMR) is used to mask off specific interrupts individually at required times. The
interrupt-flag register (IFR) indicates the current status of the interrupts.
processor mode status register (PMST)

The processor-mode status register (PMST) controls memory configurations of the 'C54x1'LC54x1'VC54x
devices.

~!}TEXAS

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9-197

VSS

Supply voltage

~
Z
o

VIH

-z

High-level input voltage

VIL

Low-level input voltage

IOH

High-level output current

IOL

Low-level output current

Operating case temperature

"'T1

MAX

UNIT

5.25

V
V

RS, INTn, NMI,CNT,CLKMOn
X2/CLKIN

VOO +0.3

All other inputs

VOO +0.3

-0.3

-40

o
z

~TEXAS

INSTRUMENTS
9-198

NOM

Refer to Figure 7 for 5-V device test load circuit values.

MIN
4.75

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.8

-300

IlA

100

°c

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

electrical characteristics and operating conditions (,C541 , 'C542} (continued)
electrical characteristics over recommended operating case temperature range (unless otherwise
noted)
PARAMETER

TEST CONDITIONS

VOL

+
Low-level output voltage +

IOL=2 mA

'iZ

Input current in high impedance

VOO = 5.25 V, Vo = VSS to VOD

VOH

High-level output voltage

TRST

With internal pulldown

TMS, TCK, TOI

With internal pull ups

(V, = VSS to VOO)

TYPt

0[15:0]

MAX

Bus holders enabled, VOO = Nom,
V, = V,H Min

V
V

-20

IlA

-10

800

-500

10
75

Supply current, core CPU

Voo = 5 V, fx = 40 MHz,§ TA = 25°C

lOOp

Supply current, pins

VOO = 5 V, fx = 40 MHz,§ TA = 25°C

100

Supply current, standby

Ci
Co

IlA

-75
-10

All other input-only pins
100C

UNIT

0.6

Bus holders enabled, VOO = Nom,
V, = V,L Max

Input current
"

MIN
2.4

IOH =-300 IlA

10
120~

mA
mA

IlA

Input capacitance

Output capacitance

IOLE2

PLL x 1 mode,

40 MHz input

IOLE3

t All typical values are at VOO = 5 V, TA = 25°C.

All input and output voltage levels except RS, INTO-INT3, NMI, CNT, X2/CLKIN, CLKMOO-CLKM03 are TTL-compatible.
§ Clock mode: PLLx1 with external source
~ This value was obtained with 50% usage of MAC and 50% usage of Nap instructions. Actual operating current varies with program being
executed.

!i
~

a:
o
LL
Z

(.)

~
C

4f\./V---1>---:-,-0 Under

reT!
-=-

Test

,
_J

= 2 mA (all outputs)
= 300 flA (all outputs)
VLoad = 1.5 V
Cr
= 40 pF typical load circuit capacitance.

Where: IOL
IOH

o
m

Figure 7. S-V Test Load Circuit

signal transition levels
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of
0.6 V. Output transition times are specified as follows.

-z

For a high-to-Iow transition on a TTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V and the level at which the output is said to be low is 1 V. For a low-to-high transition, the level
at which the output is said to be no longer low is 1 V and the level at which the output is said to be high is 2 V.

"'T1

o
:rJ
:s:

2.4 V
2V

o
z

0.6V

Figure 8. TTL-Level Outputs (S-V Devices)
Transition times for TTL-compatible inputs are specified as follows. For a high-to-Iow transition on an input
signal, the level at which the input is said to be no longer high is 1.88 V and the level at which the input is said
to be low is 0.92 V. For a low-to-high transition on an input signal, the level at which the input is said to be no
longer low is 0.92 V and the level at which the input is said to be high is 1.88 V.

---I
-----

---

-------------

----------------

---

Figure 9. TTL-Level Inputs (S-V Devices)

•
TEXAS
INSTRUMENTS
9-200

- - - - 1.88 V (90%)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0.92 V (10%)
0.8V

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

electrical characteristics and operating conditions (,LC54x and 'VC54x only)
absolute maximum ratings over specified temperature range (unless otherwise noted)t
Supply voltage range, Voo :I: ........................................................ -0.3 V to 4.6 V
Input voltage range ................................................................ -0.3 V to 4.6 V
Output voltage range .............................................................. -0.3 V to 4.6 V
Operating case temperature range, T C .............................................. -40 o e to 1000 e
Storage temperature range, Tstg .................................................... -55°e to 1500 e

t Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and
t

functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to VSS.

recommended operating conditions

VDD

Supply voltage

VSS

Supply voltage

VIH

High-level input voltage

MIN

NOM

MAX

'LC54x

3.3

3.6

'VC54x

2.7

3.0

3.3

V
V

0
RS,INTn,NMI,CNT, X2/CLKIN,
CLKMDn, VDD = 3.3±0.3 V

2.5

VDD +0.3

RS,INTn,NMI,CNT, X2/CLKIN,
CLKMDn, VDD = 2.7 V

2.2

VDD + 0.3

VDD +0.3

All other inputs

UNIT

Low-level input voltage

0.8

IOH

High-level output current

-300

IlA

IOL

Low-level output current

+1.5

Operating case temperature

100

°C

-40

~
~

VIL

-0.3

o
LL
Z

(,)

Refer to Figure 10 for 3.3-V and 2.7-V device test load circuit values.

High-level output voltage

TEST CONDITIONS
Voo = 3.3 ± 0.3 V, IOH = MAX

10
64~

mA
mA

(.1A

Input capacitance

Output capacitance

t All typical values are at VOO = 3.3 V, TA = 25°C.
:\: All input and output voltage levels except RS, INTO-INT3, NMI, CNT, X2/CLKIN, CLKMOO-CLKM03 are LVTTL-compatible.
§ Clock mode: PLLx1 with external source
~ This value was obtained with 50% usage of MAC and 50% usage of NOP instructions. Actual operating current varies with program being
executed.

o
z

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INSTRUMENTS
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TiViS320C54x, TiViS320LC54x, TiViS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

son
Tester Pin
Electronics

Where: IOL
IOH
VLoad
CT

VLoad

)---I\/\/'v~--:---O

Output
Under
Test

= 1.5 mA (all outputs)

= 300 JlA (all outputs)
= 1.5 V
= 40 pF typical load circuit capacitance.

z
o

Figure 10. 3.3-V/2.7-V Test Load Circuit

signal transition levels
LVTTL-Ievel outputs are driven to a minimum logic-high level of 2.4/2.2 V ('LC54x/'VC54x) and to a maximum
logic-low level of 0.4 V. Output transition times are specified as follows.
For a high-to-Iow transition on a LVTTL-compatible output signal, the level at which the output is said to be no
longer high is 2 V (,LC device) or 1.8 V ('VC device), and the level at which the output is said to be low is
0.8 V. For a low-to-high transition, the level at which the output is said to be no longer low is 0.8 V, and the level
at which the output is said to be high is 2 V (,LC device) or 1.8 V ('VC device).
2.4/2.2 v
2.0/1.8 V

-__

/~i"------

~ td(CLKH-RWL)

~I
I

PS,OS

tSU(D)MS~ ~

th(A)W

~ th(O)MSH

tSU(A)W~

1+-*

~ td(CLKL-O)W

__....,,)>-+1---+----;-:--«
I

----~::
I
I

01S-00

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TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

memory and parallel I/O interface timing (continued)
timing parameters for a parallel I/O port (IOSTRB

= 0) read [H = 0.5 tc(CO)]t:l: (see Figure 18)
'LC542-40
'VC54x-40
'LC543-40

'C54x-40
'LC54x-40

MIN

MAX

'LC54x-50
'VC54x-50

MAX

ta(A)IO

Access time, read data access from address valid

3H-12

3H-10

ta(ISTRBL)IO

Access time, read data access from IOSTRB low

3H-12

3H-10

tsu(D)IOR

Setup time, read data before CLKOUT high

MIN

UNIT

MAX
3H-10
3H-10

td(CLKL-A)

Delay time, address valid from CLKOUT low

O§

ld(CLKH-ISTRBL)

Delay time, IOSTRB low from CLKOUT high

ld(CLKH-ISTRBH)

Delay time, IOSTRB high from CLKOUT high

-2

th(A)IOR

Hold time, address after CLKOUT low

5§

th(D)IOR

Hold time, read data after CLKOUT high

th(ISTRBH-D)R

Hold time, read data after IOSTRB high

z
o

t A15-AO and IS timings are Included In timings referenced as address.

+See Figure 20 for address bus timing variation with load capacitance.

§ Values derived from characterization data and not tested

CLKOUT

~
\.

A15-AO

I
td(CLKL-A)

---J~1---1

'-----

\\10----,1

o
u.

---r--:-----"IX'----I4---+t- th(A)IOR

- r - - - :

1
1

~
015-00

___oJ)

14
.1
II1II14---1."1 tsu(O)IOR
la(AllO ---->I
:
I

"(ISTI1RBL)IO

~
1

14
.1
---------~~

R/W

td(CLKH-ISTRBL)

th(O)IOR

(.)

(>--t-h(-IS-T-R-B-H--O-)-R-----td(CLKH-ISTRBH)

I
I~--------------

td(CLKL-A)

Delay time, address valid from CLKOUT low+

tct(CLKH-ISTRBL)

Delay time, IOSTRB low from CLKOUT high

tct(CLKH-D)IOW

Delay time, write data valid from CLKOUT high

tct(CLKH-ISTRBH)

Delay time, IOSTRB high from CLKOUT high

td(CLKL-RWL)

Delay time, RIW low from CLKOUT low

td(CLKL-RWH)

Delay time, RIW high from CLKOUT low

th(A)IOW

Hold time, address valid from CLKOUT low+

th(D)IOW

Hold time, write data after IOSTRB high

'C54x-40
'LC54x-40!
'VC54x-40

'LC54x-50
'VC54x-50

MIN

MAX

MIN

MAX

o§

H-S§

H+10

H-S§

H+10

-2

S§

H-S

H+S§

H-S

H+S§

UNIT

t See Figure 20 for address bus timing variation with load capacitance.
+ A1S-AO, and IS timings are included in timings referenced as address.
§ Values derived from characterization data and not tested

~
Z

CLKOUT

-zm

\.~----,A
"I
I

I
~IX~-'---:

td(CLKL-A)
A15-AO

td(CLKH-O)IOW

s:
~
o
z

D15-DO

\~----'/
I

----I--:-----..j,{<'---_

14
I

i4-+I- th(A)IOW

i
I
~ t~I(O)IOW
--~I--------~:--------~<~----~--·------~~~------------------

rr
I

I
td(CLKH-ISTRBL)

--~I------~\

~I
R/W

'-----' I

K td(CLKH~ISTRBH)
I

td(CLKL-RWL)

iI
HiIII4r----~.1I

;-------------

/
Figure 19. Parallel I/O Port Write (IOSTRB = 0)

•
TEXAS
INSTRUMENTS
9-210

td(CLKL-RWH)

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FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

memory and parallel 110 interface timing (continued)
1/1

c:
c:

1/1

1/1
CI)

-c
'C

c:t

';
Cl
c:

(,)

Change in Load Capacitance on Address Bus - pF

z
o

Figure 20. Address Bus Timing Variation with Load Capacitance

!i
~

oLL
Z

o
Z

~
c

~TEXAS

INSTRUMENTS
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9-211

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

ready timing for externally generated wait states
timing parameters for externally generated wait states [H

=0.5 tc(CO)]t
'CS4x-40
'LCS4x-401
'VCS4x-40
MIN

tsu(RDY)

Setup time, READY before CLKOUT low

th(RDY)

Hold time, READY after CLKOUT low

tv(RDY)MSTRB

Valid time, READY after MSTRB low

th(RDY)MSTRB

Hold time, READY after MSTRB low

tv(RDY)IOSTRB

Valid time, READY after IOSTRB low

th(RDY)IOSTRB

Hold time, READY after IOSTRB low

tv(MSCL)

Valid time, MSC low after CLKOUT low

tv(MSCH)

Valid time, MSC high after CLKOUT low

'LCS4x-SO
'VCS4x-SO

MAX

MIN

0
4H-15

UNIT

MAX
ns
ns
4H-15

5H-15
5H

ns
ns

4H
5H-15

ns
ns

-2

t The hardware wait states can be used only in conjunction with the software wait states to extend the bus cycles. To generate wait states by
READY, at least two software wait states must be programmed. READY is not sampled until the completion of the software wait states.

CLKOUT

o
m

-z

A1S-AO

'"T1

~X~~

__~______X=

tsu(RDY)

READY

--------------~--~ I

tv(RDY)MSTRB

I+- th(RDY)
I

~-----------------------

I
I

---!ol.----+---~~:
.
I

o
z

~
I
--.I

1-----t------t-'~~:- th(RDY)MSTRB

1.
4
.1
.

----Jr

'{\--..--+--_--;.--_ _
I
--+i :.- tv(MSCH)
~tV(MSCL) I

------------~i~\{
I

Wait States

Wait State

by READY

~ Generated Internally ----~+IIII...1- Generated ~

Figure 21. Memory Read With Externally Generated Wait States

~TEXAS

INSTRUMENTS
9-212

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039- FEBRUARY 1996

ready timing for externally generated wait states (continued)
CLKOUT

A15-AO

==><"----------,------r----------~
1

015-00

----~(~~---~~------~)~--, !+- th(ROY)

1111

1
~'I tsU(ROY)

'L-JUI-~~-------------

READY
tv(ROY)MSTRB

--+----~~I1

---c,Ir..1II

, 1

I ~I

,..

1:1

z
o

th(ROY)MSTRB

~
a:
a:

J++t- tv(MSCH)

~tV(MSCL)i

------------~I~~
:.-I

Wait State
Generated Internally

+
1

Wait State
Generated
by READY

o
u.

---.1
I

Figure 22. Memory Write With Externally Generated Wait States

o
Z

~tV(MSCH)

_ _ _ _ _ _ _ _ _ _,..141_ ~I

tv(MSCL)

th(RDY)IOSTRB/,-------

14141-- Wait State

o
m

--n
Z

Generated
Internally

_--J~~I4I1I
I

Wait State
Generated
by READY

Figure 23. I/O Read With Externally Generated Wait States

:c
S

o
z

~TEXAS

INSTRUMENTS
9-214

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

-J

I
I

Ti'vjS320C54x, TiIIiS320LC54x, TiIIiS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

ready timing for externally generated wait states (continued)
CLKOUT

A15-AO

015-00

~____________~______~___________________~

------------~(~---~-------~~-------------~)~--
~
14
:I
Fth(RDY)

READY

tv(RDY)IOSTRB

tsu(RDY)

y~~-------

I:~II

o
~

th(RDY)IOSTRB

~~I------~----_I~--------~/
I

I..!-- tv(MSCH)

HtV(MSCL) :

:2:

o
L1.

-----------~I~~

Wait State
, . . . - - Generated
I
Internally

--M
...r-I-

Wait State
Generated ----..,
by READY
I

Figure 24. I/O Write With Externally Generated Wait States

o
Z

~
Z

o
m

-z

o
z

MAX

MIN

UNIT

MAX

5t
5t
5t

Enable time, CLKOUT low to address, PS, OS, IS

2H+5

ten(CLKL-RW)

Enable time, CLKOUT low to RIW enabled

2H+5

ten(CLKL-S)

Enable time, CLKOUT low to MSTRB, IOSTRB enabled

2H+5

tw(HOLD)

Pulse duration, HOLD low duration

4H+10

tw(HOLDA)

Pulse duration, HOLDA low duration

2H+10

tsu(HOLDt

Setup time, HOLD before CLKOUT low

tv(HOLDA)

Valid time, HOLDA after CLKOUT low

tdis(CLKL-A)

Disable time, CLKOUT low to address, PS, OS, IS

tdis(CLKL-RW)

Disable time, CLKOUT low to RIW

tdis(CLKL-S)

Disable time, CLKOUT low to MSTRB, IOSTRB

ten(CLKL-A)

10
-2

CLKOUT

~ ~ tsu(HOLO)
HOLD

\r'

tw(HOLO)

tsu(HOLO) -+I

I'!

1
1
1
1

IV~

t V(HOLOA)1

HtV(HOLOA)
HOLDA

1 I

tw(HOLOA)

-J ~ tdis(CLKL-A)

A15-AO
PS, OS, is

•

~I ten(CLKL-A)

(

1
1

015-00

1
1

tdis(CLKL-RW)

7 7 : \'

R/Iii

~ tdis(CLKL-S)

MSTRB

I~
1

-.!
IOSTRB

I.
1
1
1

tdis(CLKL-S)

Figure 25. HOLD and HOLDA Timing (HM

~TEXAS

INSTRUMENTS
9-216

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I.
1
1

= 1)

c=
c:
c:

ten(CLKL-RW)

ten(CLKL-S)

ns
ns

t Values derived from characterization data and not tested.

"T1

o
:c
s:

'LC54x-50
'VC54x-50

TMS320C54x, iMS320LC54x, TMS320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

reset, interrupt, BIO, and MP/MC timings
timing parameters for reset, interrupt, BIO, and MP/MC [H

=0.5 tc(CO)]
'CS4x-40
'lCS4x-40/
'VCS4x-40
MIN

MAX

'lCS4x-SO
'VCS4x-SO
MIN

UNIT

MAX

th(RS)

Hold time, RS after CLKOUT low

th(BIO)

Hold time, BIO after CLKOUT low

ns
ns

th(INT)

Hold time, INTn, NMI, after CLKOUT lowt

th(MPMq

Hold time, MP/MC after CLKOUT low:j::

tw(RSL)

Pulse duration, RS low§~

4H+10

tw(BIO)S

Pulse duration, BIO low, synchronous

2H+15

2H+12

tw(BIO)A

Pulse duration, BIO low, asynchronous~

tw(INTH)

Pulse duration, INTn, NMI high

tw(INTL)S

Pulse duration, INTn, NMIIow (synchronous)

2H+15

2H+12

tw(lNTL)A

Pulse duration, INTn, NMIIow (asynchronous)~

tw(lNTL)WKP

Pulse duration, INTn, NMIIow for IDLE2/1DLE3 wakeup:j::

tsuJRS)

Setup time, RS before X2/CLKIN low#

tsu(BIO)

Setup time, BIO before CLKOUT low

tsu(INT)

Setup time, INTn, NMI, RS before CLKOUT low

tsu(MPMC)

Setup time, MP/MC before CLKOUT low:j::

t The external interrupts (INTO-INT3, NMI) are synchnonized to the core CPU via a two flip-flop synchronizer which samples these inputs with
consecutive falling edges of CLKOUT. The input to the interrupt pins is required to represent a 1-0-0 sequence at the timing that is corresponding
to three CLKOUTs sampling sequence.
:j:: Values ensured by design but not tested.
§ If the PLL mode is selected, then at power-on sequence, or at wakeup from IDLE3, RS must be held low for at least 50 Jls to assure synchronization
and lock-in of the PLL.
~ Values derived from characterization data and not tested.
# Divide-by-two mode

:a:

a:
0

W
, '\
\t,J

ClKIN

o
m

--------------~I
tsu(MPMC)

-z

I
I
I

~tsu(MPMC)

--+11III___~~1

MP/MC

"oJJ

Figure 28. MP/MC Timing

o
z

~TEXAS

INSTRUMENTS
9-218

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TMS320C54x, iMS320LC54x, Ti'viS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

instruction acquisition (lAO), interrupt acknowledge (lACK), external flag (XF), and TOUT timing
timing parameters for lAO and lACK (H

=0.5 tc(CO»

(see Figure 29)
'CS4x-40
'LCS4x-401
'VCS4x-40

'LCS4x-SO
'VCS4x-SO

UNIT

MIN

MAX

MIN

tcl(CLKL-IAOL)

Delay time, lAO valid from CLKOUT low

MAX
5

tc!(CLKL-IAOH)

Delay time, lAO high from CLKOUT low

-2

td(A)IAO

Delay time, address valid after lAO low

IcliCLKL-IACKL)

Delay time, lACK valid from CLKOUT low

td(CLKL-IACKH)

Delay time, lACK high from CLKOUT low

-2

td(A)IACK

Delay time, address valid after lACK low

th(A)IAO

Hold time, address valid after lAO high

th(A)IACK

Hold time, address valid after lACK high

twJIAOL)

Pulse duration, lAO low

tw(IACKL)

Pulse duration, lACK low

2H-10

~
a:
a:

\----J/

CLKOUT

A1S-AO

-----,-.'1
I
td(CLKL-IAOL) -114"---tI-~~1
1
1
1
1
~

------11-:---+-1-..'t

~~-

tw(tAQL)

1 ~I td(CLKL-IACKL)
1
I
~ td(A)IACK

:...

"""''il-----

_ _ _ _ _ _ _ _.......
1

o
u.
Z

:
1CI1

2H-10

\,---,1

\~--JI
I
:i4-4-.. ~...-:
.

2H-10

\,---,1

td(XF)

o
m

--------~x~----Figure 30. External Flag (X F) Timing

-z

z
o

:E
CC

o
u.
z

o
:II
s:

CLKOUT

/
_--J

\~--'/

I
td(TOUT) I~

TOUT

o
z

td(TOUT)

I
I

- - - - - - - - - - ' ! 4 - tw(TOUT) ~

~-----------

Figure 31. TOUT Timing

•
TEXAS
INSTRUMENTS
9-220

\,---,1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

z
~
c

TiV1S320C54x, TivlS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

serial port timing
timing parameters for serial port receive [H

tc(SCK)

Cycle time, serial port clock

tf{SCK)

Fall time, serial port c1ockt:

=0.5 tc(co)l (see Figure 32)
'C54x-40
'LC54x-401
'VC54x-40

'LC54x-50
'VC54x-50

MIN

MAX

MIN

tr(SCK)

Rise time, serial port c1ock:t:

tw(SCK)

Pulse duration, serial port clock low/high

th(FSR)
th(DR)

UNIT

MAX

Hold time, FSR after CLKR falling edge

Hold time, DR after CLKR falling edge

tsu(FSR}

Setup time, FSR before CLKR falling edge

tsu(DR)

Setup time, DR before CLKR falling edge

The senal port design is fully static and, therefore, can operate with tc(SCK) approaching 00, It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time,
:t: Values ensured by design but not tested

-+I I.I I

H
I..

FSR

I
I

tsu(FSR)

!'
,

>00000O<

a::
o
LL

')fJ

o
Z

th(OR)

)e:

tr(SCK)

tw(SCK)

tsu(OR)

,..

th(FSR)

,
OR
BIT

tf(SCK)

I
I

CLKR

X
7/15

C
OOOOOOOOOO<

tdis(OX)-+i

X
2

X
7/1S

Figure 33. Serial Port Transmit Timing With External Clocks and Frames

~TEXAS

INSTRUMENTS
9-222

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

J+-

j..
8/16

TlviS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

serial port timing (continued)
timing parameters for serial port transmit with internal clocks and frames [H = O.5t c(co)1
(see Figure 34)
'C54x-40
'LC54x-40I'VC54x-40
MIN

TYP

MAX

'LC54x-50
'VC54x-50
MIN

TYP

tc(SCK)

Cycle time, serial port clock

td(FSX)

Delay time, CLKX rising to FSX

td(DX)

Delay time, CLKX rising to DX
Disable time, CLKX rising to DX

tdis(DX)

UNIT
MAX

-5

th{DX)

Hold time, DX valid after CLKX rising edge

tf(SCK)

Fall time, serial port clock

tr(SCK)

Rise time, serial port clock

tw(SCK)

Pulse duration, serial port clock low/high

4H-8

t Values derived from characterization data and not tested

o
~

t--- tc(SCK) ~
~tw(SCK

CLKX

FSX

td(FSX)

' "

L
I

t~(SCK)

td(FSX)

I
,

~~ >OOOOOOO<~

-J I

-J \.- th(DX)

tdis(DX)

I~\

___...J){I

oLL

'i"'---____-+!~,o+-r-_t_d(_DX_)_'..-r,"'--------.J1
I
, II
I

~ ~ tr(SCK)

,rI

~\r,..\_ _...JX"-___. . .X"-___~)-

7/15

o
Z

8/16

Figure 34. Serial Port Transmit Timing With Internal Clocks and Frames

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-223

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

buffered serial port receive timing
timing requirements over recommended operating conditions (see Figure 35)
'C54x-40
'LC54x-401
'VC54x-40
MIN

UNIT

MAX

Cycle time, serial port clock

Fall time, serial port clock +

tr{SCIQ

Rise time, serial port clock +

tw(SCK)

Pulse duration, serial port clock low/high+

tsu(FSR)

Setup time, FSR before CLKR falling edge (see Note 2)

th(FSR)

Hold time, FSR after CLKR falling edge (see Note 2)

tsu(DR)

Setup time, DR before CLKR falling edge

th(DR)

Hold time, DR after CLKR falling edge

2
10

8.5

ns
ns

2
10

t c (SCK)-2§

The serial port design is fully static and therefore can operate with tc(SCK) approaching. It is characterized approaching an input frequency of
o Hz but tested at a much higher frequency to minimize test time.
+ Values ensured by design but not tested
§ First bit is read when FSR is sampled low by CLKR clock.
NOTE 2: Timings for CLKR and FSR are given with polarity bits (CLKP and FSP) set to O.

j4- tc(SCK) ~

I
I
CLKR

I
I
I

o
:a

MIN

t~(SCK)

o
m

MAX

tf(SCK)

-z

'LC54x-50
'VC54x-50

--.I
~

FSR

o
z

14- th(FSR)

I I
~ tsu(FSR)

-~---"'"'\'I

I
I

tw(SCK)

I
I
l+-

14- t'(SCK)

I
I

-+I

I~ tsU(DR)

~~------~I--~I-------------------------------I
I
I
I
I
I

XX>OOO<_---'X

-+i

I+- th(DR)
I
I

X'------JX'------JX'------JX

Figure 35. Serial Port Receive Timing

~TEXAS

INSTRUMENTS
9-224

I.- tw(SCK)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

8/10/12116

TiViS320C54x, TMS320LC54x, "rMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

buffered serial port transmit timing of external frames
switching characteristics over recommended operating conditions (see Figure 36)

PARAMETER

'CS4x-40
'LCS4x-401
'VCS4x-40

'LCS4x-SO
'VCS4x-SO

MIN

MAX

UNIT

MAX

td(DX)

Delay time, DX valid after CLKX rising

tdis(DX)

Disable time, OX after CLKX risingt

tdis(DX)pcm

Disable time, PCM mode,DX after CLKX risingt

ten(DX)pcm

Enable time, PCM mode,DX after CLKX risingt

th(DX)

Hold Time, OX valid after CLKX rising

6
6

t Values derived from characterization data but not tested.

timing requirements over recommended operating conditions (see Figure 36)
'CS4x-40
'LCS4x-401
'VCS4x-40
MIN

'LCS4x-SO
'VCS4x-SO

MAX

MIN

UNIT

MAX

tc(SCK)

Cycle time, serial port clock

tf(SCK)

Fall time, serial port clock §

tr(SCK)

Rise time, serial port cJock§

tw(SCK)

Pulse duration, serial port clock low/high§

8.5

th(FSX)

Hold time, FSX after CLKX falling edge (see Notes 1 and 3)

tsu(FSX)

Setup time, FSX before CLKX falling edge (see Notes 1 and 3)

tc(SCK)-6~

6
6

tc(SCK)-6~

ns
ns

o
~
~

oLL

+ The serial port design is fully static and therefore can operate with tc(SCK) approaching. It is characterized approaching an input frequency Z
of 0 Hz but tested at a much higher frequency to minimize test time.
W
§ Values ensured by design but not tested.
~ If FSX does not meet this specification, the first bit of the serial data is driven on DX until FSX goes low (sampled on falling edge of CLKX). After
falling edge of the FSX, data will be shifted out on the DX pin.
NOTES: 1. Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending
on the source of FSX, and CLKX timings always are dependant upon the source of CLKX. Specifically, the relationship of FSX to
CLKX is independant of the source of CLKX.
3. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to O.

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-225

o
Z

TMS320C54x, TMS320LC~4x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

buffered serial port transmit timing of external frames (continued)
~ tc(SCK)--.j

I
I
CLKR

I
I

-.:
~
FSR

I+- th(FSX)
I

~tSU(FSX)

~
td(DX)

>00000<

I
I
I
I
I
I
I
I
I
I

-+I I+- tf(SCK)
I I
I I
I
I
I
I
I I
I
-.I !.- tr(SCK)
I
I
I
I

I.- tw(SCK)

I I
I I

I
I
-.l

~tW(SCK)
I
I
I
I

tdis(OX)

-.I ~ th(OX)

-.I l+-

I
I

X X

)L8/10/12116

Figure 36. Serial Port Transmit Timing of External Clocks and External Frames

o
m

Z
-n

:rJ

?j
o
z

•
TEXAS
INSTRUMENTS
9-226

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

I
-+I l+I
I

·iiVlS320C54x, TiVlS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

buffered serial port transmit timing of internal frame and internal clock
switching characteristics over recommended operating conditions [H
PARAMETER

tc(SCK)

Cycle time, serial port clock

id(FSX)

Delay time, FSX after CLKX rising edge (see Notes 1 and 3)

td(DX)

Delay time, DX valid after CLKX rising edge

tdis(DXt

Disable time, DX after CLKX rising edge

=o.Stc(eO)] (see Figure 37)

'CS4x-40
'LCS4x-401
'VC54x-40

'LCS4x-SO
'VCS4x-SO

MIN

MAX

MIN

MAX

62H

ten(DX)pcm

t
Enable time, PCM mode, DX after CLKX rising edge t

th(DX)

Hold time, DX valid after CLKX rising edge

tf(SCK)

Fall time, serial port clock;

tr(SCK)

Rise time, serial port clock;

twJSCK)

Pulse duration, serial port clock low/high;

tdis(DX)pcm

Disable time, PCM mode, DX after CLKX rising edge

ns
ns
ns

4
4
H-4

UNIT

H-4

Values derived from characterization data but not tested.
; Values ensured by design but not tested.
NOTES: 1. Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending
on the source of FSX, and CLKX timings always are dependant upon the source of CLKX. Specifically, the relationship of FSX to
CLKX is independant of the source of CLKX.
3. Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to O.

14- tc(SCK) --.j
I
-.I
I
I
CLKX

I
I
I
td(FSX) -.! l+I
I

FSX

I
I
I

-.I

I
I
I
I

1+1I

--l

14- ~(FSX) I

i
I
I
td(DX)

>00000<

-.I

---..I 14I

(.)

I
I
I
I
I
I
I

o
m

-z

'LCS4x-SO
'VCS4x-SO

UNIT

MIN

MAxt

MIN

MAxt

:j:

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

trLSCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

tsu(TD-TCH)

Setup time, TDAT before TCLK rising edge

-6

6
6

th(TCH-TD)

Hold time, TDAT after TCLK rising edge

tsu(TA-TCH)

Setup time, TADD before TCLK rising edge§

th{TCH-TA)

Hold time, TADD after TCLK rising edge§

tsu(TF-TCH)

Setup time, TFRM before TCLK rising edge'll

th(TCH-TF)

Hold time, TFRM after TCLK rising edge'll

t Values ensured by design and are not tested.
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching infinity. It is characterized approaching an inputfrequency
of 0 Hz but tested at a much higher frequency to minimize test time.
§These parameters apply only to the first bits in the serial bit string.
'11 TFRM timing and waveforms shown in Figure 25 are for external TFRM. TFRM can also be configured as internal. The TFRM internal case is
illustrated in the transmit timing diagram in Figure 26.
:1=

tf(SCK)

TCLK

~ ~ ~ 1+ tr(SCK)
II
J.

.-------i'- tc(SCK)

I
I
I

I
I

~
II I

TFRM

tw(SCK)

~II

t su(TD-TCH)

-.I!4I

th(TCH-TD)

B14

Ith(TCH-TA) +114~j4" th(TCH-TA)
~t,"(TA-TCHl

TADD

r-rI

TDAT* 80 :~

~
oz

w(SCK)

X""-B-1-3--'~~~~_B_1_.......>C!!:

X~_A_2_......~:A7_

th(TCH-TF)

~~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
Figure 38. Serial-Port Receive Timing in TOM Mode

~TEXAS

9-228

INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

serial-port transmit timing in TOM mode (continued)
switching characteristics over recommended operating conditions [H

=O.5tc(co)1 (see Figure 26)

'CS4x-40
'LCS4x-401
'VCS4x-40

PARAMETER

MAX

MIN
th(TCH-TDV)

Hold time, external TDAT /TADD valid after TCLK rising edge

th(TCH-TDV)

Hold time, internal TDATITADD valid after TCLK rising edge

0
-5

t
Delay time, TFRM valid after TCLK rising edge, TCLK int t

td(TC-TDV)

MIN

-5

Delay time, TFRM valid after TCLK rising edge, TCLK ext
td(TCH-TFV)

'LCS4x-SO
'VCS4x-SO

UNIT

MAX
ns
ns

3H + 22

3H+22

3H + 12

3H+ 12

ns
ns

Delay time, TCLK to valid TDATITADD, TCLK ext

Delay time, TCLK to valid TDATITADD, TCLK int

TFRM timing and waveforms shown in Figure 26 are for internal TFRM. TFRM can also be configured as external. The TFRM external case is
illustrated in the receive timing diagram in Figure 25.

timing requirements over recommended ranges of supply voltage and operating free-air
temperature [H = O.5t c(Co)1 (see Figure 26)
'C54x-40
'LCS4x-40/
'VCS4x-40

'LCS4x-SO
'VCS4x-50

MIN

MAX

8H:t:

UNIT

MIN

MAX

8H:t:

tc(SCK)

Cycle time, serial-port clock

tf(SCK)

Fall time, serial-port clock

tr(SCK)

Rise time, serial-port clock

tw(SCK)

Pulse duration, serial-port clock low/high

4H:j:

4H:t:

:j: When SCK is generated internally this value is typical.

§ The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching 00. It is characterized approaching an input frequency
of 0 Hz but tested as a much higher frequency to minimize test time.
~ Values ensured by design but are not tested

TADD

B14

~J\........r\..

4- - - .

..,:X

o
LL

-:41

TDAT ...,..._ _ _

I n tw(SCK)
I

I
tc(SCK)

tw(SCK)~
TCLK

z
o

B13

X B12 :: BaX B7

:: B2X

x::E

I
-.!

TFRMJ

Figure 39. Serial-Port Transmit Timing in TOM Mode

•
TEXAS
INSTRUMENTS
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9-229

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

host port interface
switching characteristics over recommended operating conditions [H
and 12) (see Figure 30 through Figure 33)
PARAMETER

:t:O

o
m

-z

o
J]
s:

~
oz

td(DSL-HDV)

Delay time, DS low to HD valid

td(HEL-HDV1 )

Delay time, HDS falling to HD valid for first byte of a subsequent read:
Case 1: Shared-access mode if tw(HDS)h < 7H §11
Case 2: Shared-access mode if tw(HDS)h > 7H
Case 3: Host-only mode if tw(HDS)h < 7H
Case 4: Host-only mode if tw(HDS)h > 7H

td(DSL-HDV2)

Delay time, DS low to HD valid, second byte

td(DSH-HYH)

Delay time, DS high to HRDY high

=0.5tc(co)1 (See Notes 11
MIN

MAX

12t

UNIT
ns

t
t

7H+2o-tW (DSH
20
4o-tW (DSH
20
511

20
10(6)H+10t

tsu(HDV-HYH)

Setup time, HD valid before HRDY rising edge

th(DSH-HDV)

Hold time, HD valid after DS rising edge

td(COH-HYH)

3H-10t

ns
ns

12t#

Delay time, CLKOUT rising edge to HRDY high

10t

td(DSH-HYL)

Delay time, HDS or HCS high to HRDY low

12t

td(COH-HTX)

Delay time, CLKOUT rising edge to HINT change

t Values denved from characterization data and not tested.
t Values ensured by design but not tested.
§ Host-only mode timings apply for read accesses to HPIC or HPIA, write accesses to BOB, and resetting DSPINT or HINT to 0 in shared-access
mode. HRDY does not go low for these accesses.
11 Shared-access mode timings will be met automatically if HRDY is used.
#HD release
NOTES: 4. SAM = shared-access mode, HOM = host-only mode
HAD stands for HCNTRLO, HCNTRL1, and HR/w'
HDS refers to either HDS1 or HDS2 .
DS refers to the logical OR of HCS and HDS.
5. On host read accesses to the HPI, the setup time of HD before DS rising edge depends on the host waveforms and cannot be
specified here.

timing requirements over recommended operating conditions [H
(see Figure 30 through Figure 33)

= 0.5tc(co)1

(See Note 11)

MIN

MAX

UNIT

tsu(HBV-DSL)

Setup time, HAD/HBIL valid before DS falling edge

th(DSL-HBV)

Hold time, HAD/HBIL valid after DS falling edge

tsu(HSL-DSL)

Setup time, HAS low before DS falling edge

tw(DSL)

Pulse duration, DS low

30 11

50
10Ht

tw(DSH)

Pulse duration, DS high

tc(DSH-DSH) II

Cycle time, DS rising edge to next DS rising edge:
Case 1: When using HRDY (see Figure 39)
Case 2a: SAM accesses and HOM active writes to DSPINT or HINT without using HRDY
(see Figure 37 and Figure 38)
Case 2b: When not using HRDY for other HOM accesses

tsu(HDV-DSH)

Setup time, HD valid before DS rising edge

th(DSH-HDV)

Hold time, HD valid after DS rising edge

50
12

t Values ensured by design but not tested.
II A host not using HRDY should meet the 10H requirement all the time unless a software handshake is used to change the access rate according
to the HPI mode.
NOTE 11: SAM = shared-access mode, HOM host-only mode
HAD stands for HCNTRLO, HCNTRL1, and HR/w'
HDS refers to either HDS1 or HDS2.
DS refers to the logical OR of HCS and HDS.

~TEXAS

INSTRUMENTS
9-230

POST OFFICE BOX 655303 • DALLAS. TEXAS 75265

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

host port interface (continued)
FIRST BYTE

=t =4

HAD

HBIL]'\

t"'--~-:

'h(DSL-HBV)

'w(DSL)

~C(DSH-DSH)I ~

~ td(HE~-HDV1)

:..
td(DSL-HDV) ~

th(DSH HDV)

I-

tsu(HBV-DSL)

7: 'C
14

'w(DSH)

V'=l=
,"

~~AD

'h(DSL-HBV)

tSU(t"!BV-DSL)

II,

~g~

SECOND BYTE

1- - i

'w(DSH)

=4--1

'r'W(DSL)
1

t~DSL-HDV2)
14

0<) , (

tSU(HDV-DSH)~'
tsu(HDV-DSH)
1- ~ tsu(DSH-HDV)

o
~

th(DSH-HDV)

I"
1

~1..t.....J
~., tsu(DSH-HDV)

oLL

HD
WRITE

Figure 40. Read/Write Access Timings Without HRDY or HAS

o
Z

HBIL\

1/
1

14
1

td(HEL-HDV1):11111

td(DSL-HDV)~
HD
READ

I
1

C
~(DSH-DSH) ~
I

tf(DSH-DSH)
1

th(DSH-HDV)

td(DSL-HDV2

'\-------JC

-0-=1
.1

' - -_ _- . , . . - ' 1

I 1I

tSU.(DSH-HDV)

1
1

HD
WRITE

Figure 41. Read/Write Access Timings Using HAS Without HRDY

o
z

~TEXAS

INSTRUMENTS
9-232

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

~ th(DSH~HDV)
1
~I
J---~I

tsu(DSH-HDV)
tsu(HDV-DSH) I

"T1

o
:c
s:
~

tw(DSH)

-z

Q='W(OSLl-'{)
~

o
m

TMS320C54x, TMS320LC54x, TMS320VC54x
FIXED·POINT DIGITAL SIGNAL PROCESSORS
SPRS039 - FEBRUARY 1996

host port interface (continued)
FIRST BYTE

I
I
I

SECOND BYTE

~
I

tsu(HSL-DSL)

~ tsu(HBV-DSL)

I
I

HAD

1II1I

HBIL

Ith(DSL-HBV)t

4IW(OSL)
-,v
~
~
1II1I

tw(DSH)

II
I
I
td(HEL-HDV1)
td(DSL-HDV)

I
I
I
I

t~(DSH-DSH)

td(DSH-HYL)

tsu(HDV-DSH)

HD
WRITE

I
:

Rld(COH-HTX)

I
)(...----

II
IT\I
I I I I
1II1I
~ tsu(HDV-HYH)
I
~ td(DSL-HDV2),
I
th(DSH-HDV
~ th(DSH-HDV)
I
I

_ _ _ _ _ _ _ _--(Olh(OSH-HOV)

HI
I
I
I
I

HD
READ

CLKOUT

~DSH-DSH) 4
I

z
o

14-- td(DSH-HYH) ~

I
HRDY

~'--_>C
I
I

tsU(HBV-DSL) t

~:1
I
I

HCS
HOS

th(DSL-HBV)

I
I
I
I
I

th(DSH-HDV)

!Ctd(COH-HYH)

--'II

I
I

EXIF.tools

1996_TI_Wireless_and_Telecommunications_Products_Data_Book 1996 TI Wireless And Telecommunications Products Data Book

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