1996_Vitesse_Communications_Products_Data_Book 1996 Vitesse Communications Products Data Book
User Manual: 1996_Vitesse_Communications_Products_Data_Book
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Communications Products VITESSE SEMICONOUCfOR CORPORATION 1996 Communications Products Data Book Vitesse Semiconductor Corporation reserves the right to make changes in its products or specifications or other information at any time without prior notice. Thus, the reader is cautioned to confirm that data sheets and other information in this publication are current before placing orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Trademarks Vitesse, FURY, FX, GLX, VIPER and SCFX are trademarks of Vitesse Semiconductor Corporation Mentor is a trademark of Mentor Graphics Corporation LASAR is a trademark of Teradyne, Inc. SynopsyS® and Design Compiler@ are registered trademarks of Synopsys, Inc. Verilog and Valid are registered trademarks of Cadence Design Systems, Inc. The X Window System is a trademark of the Massachusetts Institute of Technology Postscript® is a trademark of Adobe Systems Macintosh is a trademark of Apple Computer, Inc. IBM is a trademark of International Business Machines Corp. Sun Workstation is a registered trandemark of Sun Microsystems, Inc. Apollo is a registered trademark of HP/Apollo Computer, Inc. Pentium™ is a trademark of Intel Corporation All other trademarks or registered trademarks mentioned herein remain the property of their respective companies. VlTESSE Semiconductor Corporation 741 Calle Plano Camarillo, CA 93012 Phone: (805) 388-3700 Fax: (805) 987-5896 Copyright ® Vitesse Semiconductor Corporation 1996 All rights reserved. Printed in U.S.A. G54010-0-0594 3M August 1996 ® VITESSE 1996 Communications Product Data Book v vi ® VITESSE Semiconductor Corporation Table of Contents GENERAL INFORMATION Introduction ................................................................................................................................. xxi Document Designations ............................................................................................................ xxiii Vitesse U.S. Sales Offices ..........................................................................................................xxv Vitesse European Sales Office .................................................................................................... xxv U.S. Representative Offices ...................................................................................................... xxvi International Representatives and Distributors ....................................................................... xxviii DATACOMMUNICATIONS Fibre Channel Product Summary ............................................................................................... 1 Fibre Channel Overview ................................................................................................................. 3 Transmitter/Receiver Overview ...................................................................................................... 7 VSC7105NSC7106 Features ........................................................................................................................................... 9 General Description ........................................................................................................................ 9 System Block Diagram ................................................................................................................... 9 VSC7105 Transmitter Functional Description ............................................................................. 10 VSC7106 Receiver Functional Description .................................................................................. 12 Absolute Maximum Ratings ..........................................................................................................24 Recommended Operating Conditions ........................................................................................... 24 Package Thermal Characteristics .................................................................................................. 31 Package Information .................................................................................................................... .33 Ordering Information ................................................................................................................... .34 VSC7107 Features ........................................................................................................................................ .35 System Block Diagram ................................................................................................................ .35 General Description ...................................................................................................................... .35 Functional Description ................................................................................................................. .36 Functional Block Diagram ........................................................................................................... .38 Fibre Channel Transmission Protocols ........................................................................................ .42 AC Timing Specifications ............................................................................................................. 57 Electrical Specifications ................................................................................................................ 62 Pin Description Tables ..................................................................................................................64 Package Information .....................................................................................................................66 Ordering Information ....................................................................................................................67 @ VITESSE 1996 Communications Product Data Book vii Table of Contents VSC711SNSC7116 Features .........................................................................................................................................69 General Description ......................................................................................................................69 Gigabaud Link Module Block Diagram .......................................................................................69 VSC7115 Transmitter Functional Description .............................................................................70 VSC7116 Receiver Functional Description ..................................................................................72 Absolute Maximum Ratings ..........................................................................................................78 Recommended Operating Conditions ............................................................................................78 Package Information ..................................................................................................................... 83 Ordering Information .......•............................................................................................................ 84 VSC7120 Features ......................................................................................................................................... 85 General Description ...................................................................................................................... 85 VSC7120 Block Diagram ............................................................................................................. 85 Functional Description .................................................................................................................. 86 Repeater Mode .............................................................................................................................. 86 Hub Mode .....................................................................................................................................89 Signal Detect Unit Behavior ...•......................................... 91 AC Characteristics ........................................................................................................................ 93 DC Characteristics ....................................................................................................................... 93 Absolute Maximum Ratings ................................................................................ ~ ....................... 94 Recommended Operating Conditions ........................................................................................... 94 Package Thermal Characteristics .................................................................................................. 97 Package Information ..................................................................................................................... 98 Ordering Information .................................................................................................................... 99 0; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSC7121 Features ....................................................................................................................................... 101 General Description ...........................................................'......................................................... 101 7121 BlockDiagram ................................................................................................................... 101 Absolute Maximum Ratings ........................................................................................................ 105 Recommended Operating Conditions .......................................................................................... 105 Input Structures ........................................................................................................................... 106 Package Thermal Characteristics ................................................................................................ 109 Package Information ................................................................................................................... 11 0 Ordering Information .................................................................................................................. 111 viii @ VITESSE Semiconductor Corporation Table of Contents VSC7125 Features ....................................................................................................................................... 113 General Description .................................................................................................................... 113 Block Diagram ............................................................................................................................ 113 Functional Description ................................................................................................................ 114 Absolute Maximum Ratings ....................................................................................................... 122 Recommended Operating Conditions ......................................................................................... 122 DC Characteristics ...................................................................................................................... 123 Thermal Considerations .............................................................................................................. 126 Package Information ................................................................................................................... 127. Ordering Information .................................................................................................................. 128 VSC7126 Features ....................................................................................................................................... 129 General Description .................................................................................................................... 129 VSC7126 Block Diagram ........................................................................................................... 129 VSC7135 Features ....................................................................................................................................... 131 General Description .................................................................................................................... 131 Functional Description ................................................................................................................ 132 Absolute Maximum Ratings ....................................................................................................... 140 Recommended Operating Conditions ......................................................................................... 140 DC Characteristics ..................................................................................................................... 141 Thermal Considerations .............................................................................................................. 144 Package Information .................................................................................................................... 145 Ordering Information .................................................................................................................. 146 VSC7181 Features ....................................................................................................................................... 147 Copper GLM Module ................................................................................................................. 147 General Description .................................................................................................................... 147 Functional Description ................................................................................................................ 149 Physical Description ................................................................................................................... 151 Electrical Interface ...................................................................................................................... 155 Absolute Maximum Ratings ....................................................................................................... 158 Recommended Operating Conditions .......................................................................................... 158 Ordering Information .................................................................................................................. 161 ® VITESSE 1996 Communications Product Data Book ix Table of Contents VSC7181EV Contents/Benefits ........................................................................................................................ 163 General Description .................................................................................................................... 163 CuGLM Evaluation Kit ............................................................................................................... 163 Order Information ....................................................................................................................... 164 VSC7201A Features ....................................................................................................................................... 165 Introduction ................................................................................................................................. 165 VSC7201A- Block DiagraJIl ...................................................................................................... 165 Terms and Conventions .............................................................................................................. 166 Quick Signal Pin Reference ........................................................................................................ 167 SCI Overview .............................................................................................................................. 169 Node Interface Bus (NIB us) ....................................................................................................... 194 SCI High Speed Link Signals .....................................................................................................228 Latency ........................................................................................................................................230 Performance Counters .................................................................................................................231 Test Access Port ..........................................................................................................................235 Internal Scan Test and Diagnostics .............................................................................................246 Electrical Specifications ..............................................................................................................247 Package Pin Description ............................................................................................................ 252 Signal Pin Description ................................................................................................................255 Mechanical Specifications ..........................................................................................................258 Thermal Specifications ...............................................................................................................259 Ordering Information ..................................................................................................................260 VSC7203 Features .......................................................................................................................................261 Introduction .................................................................................................................................261 VSC7203 Functional Block DiagraJIl ......................................................................................... 261 Functional Description ................................................................................................................262 JTAG ......................................................................................................................... ;.................264 AC Characteristics ......................................................................................................................268 AC Timing Waveforms ................................................................................ ,..............................269 DC Characteristics ......................................................... ,............................................................270 Absolute Maximum Ratings .......................................................................................................272 Recommended Operating Conditions ..........................................................................................272 Package Pin Description ., ...........................................................................................................273 Package Pinout [by Pin Number] ................................................................................................274 Package Pinout [by Signal NaJIle] ..............................................................................................277 ® VITESSE Semiconductor Corporation Table of Contents VSC7203 continued Package Information ...................................................................................................................280 Ordering Information ..................................................................................................................281 VSC7802 and VSC7805 Features .......................................................................................................................................283 General Description ....................................................................................................................283 VSC7802/7805 Block Diagram ..................................................................................................283 Electro-Optical Specifications ....................................................................................................284 Absolute Maximum Ratings .......................................................................................................285 Mechanical Package Specifications ............................................................................................289 Ordering Information ..................................................................................................................290 Notes on Measurement Conditions & Applications ...................................................................291 VSC7810 Features .......................................................................................................................................295 General Description ....................................................................................................................295 VSC7810 Block Diagram ...........................................................................................................295 Electro-Optical Specifications ....................................................................................................296 Absolute Maximum Ratings .......................................................................................................297 Mechanical Package Specifications ............................................................................................302 Ordering Information ................................................................................................................. .304 Notes on Measurement Conditions & Applications .................................................................. .305 TransmitterlReceiver Design Guide Introduction ................................................................................................................................ .309 System Interfacing ..................................................................................................................... .309 Clock Generation ....................................................................................................................... .309 High Speed Signal Termination ................................................................................................. .311 Single-Ended, 50 Ohm Termination .......................................................................................... .311 Single Ended, 75 Ohm Termination .......................................................................................... .312 Fiber Optic Module Termination ............................................................................................... .313 Preventing Oscillations .............................................................................................................. .314 Unused Inputs ............................................................................................................................ .315 Power Supply Considerations .................................................................................................... .315 Bypassing ................................................................................................................................... .316 Layout Considerations ................................................................................................................317 High Speed Serial 110 Layout Considerations ........................................................................... .318 Conclusion ................................................................................................................................. .319 Component Supplier List ........................................................................................................... .320 ® VITESSE 1996 Communications Product Data Book xi Table of Contents TELECOMMUNICATIONS Telecommunications Product Summary................................................................................. .321 VS8004IVS8005 Features ...................................................................................................................................... .325 Functional Description ................................................................................................................ 325 VS8004 ...................................................................................................................................... .325 VS8005 ...................................................................................................................................... .325 SKIP Signal ................................................................................................................................ .325 Applications ............................................................................................................................... .326 VS8004 AC Characteristics ....................................................................................................... .328 VS8005 AC Characteristics ................. :..................................................................................... .329 Absolute Maximum Ratings ....................................................................................................... 330 Recommended Operating Conditions ........................................................................................ .330 DC Characteristics ..................................................................................................................... .331 Package Information .................................................................................................................. .335 DUT Boards ................................................... ;........................................................................... .336 Ordering Information ................................................................................................................. .338 VS80211VS8022 Features ...................................................................................................................................... .339 Functional Description ............................................................................................................... .339 VS8021 ...................................................................................................................................... .339 VS8022 ...................................................................................................................................... .341 VS8021 Multiplexer AC Characteristics ................................................................................... .342 VS8022 Demultiplexer AC Characteristics ................................................................................ 344 VS8022 SONET Frame Recovery and Detection ...................................................................... .344 Absolute Maximum Ratings ................................................ ;...................................................... .346 Recommended Operating Conditions ........................................................................................ .346 DC Characteristics ..................................................................................................................... .347 Example Application: STS-48 SONET System Link ................................................................ .349 Package Information .................................................................................................................. .353 DUT Boards ............................................................................................................................... .354 DUT Test Setup ......... ;............................................................................................................... .357 Ordering Information ................................................................................................................. .358 xii @ VITESSE Semiconductor Corporation Table of Contents VSC8023NSC8024 Features ...................................................................................................................................... .359 System Block Diagram .............................................................................................................. .359 General Description ................................................................................................................... .359 VSC8023 Functional Description .............................................................................................. .360 VSC8024 Functional Description .............................................................................................. .364 VSC8023 AC Timing Characteristics ........................................................................................ .368 VSC8024 AC Timing Characteristics ........................................................................................ .372 Absolute Maximum Ratings ....................................................................................................... .377 Recommended Operating Conditions ........................................................................................ .377 ESD Ratings ............................................................................................................................... .377 DC Characteristics ..................................................................................................................... .378 Power Dissipation ................................................................................................................... ;.. .379 VSC8023 Package Pin Description ........................................................................................... .379 VSC8024 Package Pin Description ........................................................................................... .379 Application Notes ...................................................................................................................... .381 VS8061/VS8062 Features ...................................................................................................................................... .385 Functional Description ............................................................................................................... .385 VS8061 Multiplexer ................................................................................................................... .385 VS8062 Demultiplexer .............................................................................................................. .385 VS8061 Multiplexer AC Characteristics .................................................................................... 387 VS8061 Phase Detector Logic Diagram .................................................................................... .388 VS8062 Demultiplexer AC Characteristics ............................................................................... 389 Absolute Maximum Ratings ....................................................................................................... .390 Recommended Operating Conditions ........................................................................................ .390 ESD Ratings ............................................................................................................................... .390 DC Characteristics ..................................................................................................................... .391 Coupling for Inputs .................................................................................................................... .392 Package Information .................................................................................................................. .398 Thermal Considerations ............................................................................................................. .400 Ordering Information ................................................................................................................. .403 SRp •.••.•••• HMiiH .••••.MQX... .Unit.F¢timiitivR..FH 98 113 MHz -100 100 ppm Symmetry 40 60 % REFCLK rise and fall slew rate. 500 Random jitter mVIns 75 ps Tested on a sample basis Note 1 Duty cycle at 50% pt. Note 2 peak to peak Note 1) This value is based on typical system requirements (i.e.. Fibre Channel). The VSC7105 and VSC7J06 can tolerate REFCLK mismatching o/up to 0.5%. 2) This value assumes an AC-coupled REFCLK. Higher slew rates will minimize REFCLK's contribution to jitter due to edgetriggering ambiguity. G52079-0 Rev. 2.7 @ VlTESSE 1996 Communications Product Data Book Page 21 Data Sheet 1.0625 Gbitlsec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Figure 12: Parametric Measurement Information Serial Input Rise and Fall Time TTL Input and Output Rise and Fall Time 4t Jt =9t it Tr . 80% 90% SO% 20% SO% Tr Tr 10% Tr Receiver Input Eye Diagram Jitter Mask Bit Time a I 30% I Parametric Test Load Circuit Serial Output Load TTL A.C. Output Load -:[+-- -f:::])~--l-) 211=500 1 500 VDD -2.0V Serial Output Load -f) ) -.J..-=ZO=--=""60'"".""'900=-=--- 1t 750 VDD -2.0V Page 22 ® VITESSE Semiconductor Corporation G52079-o Rev. 2.7 Data Sheet 1.0625 Gbitlsec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Figure 13: Transmitter Jitter Measurement Method Random Jitter Measurement BERT Pattern Generator DATA t- DATA" Trigger 106.25MHz Digitizing Scope = = CLK 1.0625 GHz DATA 00000 11111 106.25MHz RJ --- VSC7105 TX REFCLKTX+ -K28.7 -K28.7 TX00111110000011111000 ---.-. Too:19 ~ r-- 1.0625 Gbitls Single·Ended Measurement NOTE: Random jitter (RJ) measurements performed according to Fibre Channel 4.1 Annex A, Test Methods, Section A.4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is.± 7 sigma of distribution. Deterministic Jitter Measurement BERT DATA I Pattern Generator PAT SYNC CLK = 1.0625 GHz DATh = 00000 11111 00000 11111 Trigger 53.125 Digitizing Scope 106.25MHz VSC7105 DJ --- REF~~KTX+ - ~ 1.0625 Gbitls Single-Ended Measurement TX- -K28.5 +K28.5 00111110101100000101---.-. TOO:19 TRIGGER DATA j 1 i ~ 20 ~it.time : i ~ 19bztnme .:. . ~ 18 bit time ::: i>t:;> CL Heat Spreader Up Top View .... 44 PQFP .... o>o::~.... .... gt2~5a~~~t:::~g >Z(J)CLCL>CLCLCLCL> VSS REFCLK SYNCEN rJNS VSSA VDDA LPEN RX+ RX· RLX+ RLX· VITESSE 0 VSC7106QF VDD R1S R14 R13 R12 VSST R11 R10 R09 ROS VDD 5go~ati~~~~~ CCLCLCLCL(J)CLCLCLCL> > > Note: The heat spreader is connected to Vss' G52079-0 Rev. 2.7 ® VITESSE 1996 Communications Product Data Book Page 27 Data Sheet 1.0625 Gbitlsec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Table 7: VSC7105 Pin Description ................... :PiJt#:: ................... 18-21,24-27 29-32,35-38 TOO:19 40-43 INPUT-TTL Parallel data on this bus is clocked in on the falling edge of TCLK in 20 bit mode, or on the falling edge of both TCLK and TCLKN in 10 bit mode. TOO is transmitted first in 20 bit mode and T1 0 first in 10 bit mode. INPUT - Multi-Level Static Input The level on this pin determines the serial encoding and the source of the bit clock to be used. The table below lists the effects caused by driving TEST to various levels. 16 TEST 15 DWS INPUT - Static: TTL This pin selects the parallel data bus width. When LOW, a 20 bit parallel bus width is selected and TOO:19 are active. WhenIflGH, a 10 bit parallel data bus is selected, TIO:19 are active and TOO :09 are ignored. INPUT-TTL Outputs enable inputs. Select serial ou1put state as shown in the Table below. 2, 1 > £iJi1< .tx+iixj ............................ ::: TLX+lTLX~.·:· LOW LOW active active LOW IflGH active IflGHlLOW HIGH LOW IflGHILOW active IflGH IflGH IflGHlLOW IflGHILOW 13 REFCLK CLOCK INPUT - Single-Ended (Biased at VDDI2, refer to Figure 14-A) A free running reference clock for the Pll clock multiplier. The frequency of REFCLK is O.lx the desired baud rate. 11,10 TCLK TCLKN OUTPUTS-COMPLRMENTARYTTL Half word rate clock true and complement (frequency REFCLKI2). In the 10 bit parallel data bus mode a new data word is clocked into the transmitter on the falling edge of both TCLK and TCLKN. In the 20 bit parallel data bus mode a new data word is clocked into the transmitter only on the falling edge ofTCLK. 5,4 Page 28 OBO OEI £i~~ TLX+, TLX- = OUTPUTS - DIFFERENTIAL Serial Output (Centered at VDD - 1.32V) These outputs are functionally equivalent to TX+ and TX-. ® VITESSE Semiconductor Corporation G52079-0 Rev. 2.7 Data Sheet 1.0625 Gbitlsec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links ................. ".:Pit;:#>" .................. 7,8 TX+ TX- 12 VSST TTL Ground 14 VDDT TTL Power Supply 3,9 VDDP Differential Output Power Supply 17,33,39 VDD Digital Power Supply 6,22,34,44 23 VSS VDDA Digital and Differential Output Ground Analog Power Supply 28 VSSA Analog Ground Table 8: VSC71 06 Pin Description 13-16,18-21, 24-27, 29-32,35-38 ROO:19 7 LPEN 4 DWS 41,40 RCLK, RCLKN OUTPUTS-CONWLEMENTARYTTL Recovered clock rate (frequency - REFCLKI2). The falling edge ofRCLK oulputs a new word on the 20 bit data bus in the 20 bit mode. The falling edge of RCLK and RCLKN outputs anew word on RI0:19 in the 10 bit mode. After a sync word is detected the period of the current RCLK and RCLKN is stretched to align with the half-word boundary. 2 REFCLK INPUT - Single-Ended Clock (Biased at VDDfl, refer to Figure 14-A) A free running reference clock for the PLL clock multiplier. The frequency of REFCLK is within ±1.00% of 0.1 x the desired baud rate. 42 SYNC 10,11 RLX+, RLX- 8,9 RX+,RX- G52079-0 Rev. 2.7 The width of the parallel data bus is selected by the state of the DWS pin. Parallel data on this bus is clocked out on the falling edge of RCLK in 20 bit mode and on the falling edges of both RCLK and RCLKN in 10 bit mode. ROO is the first bit received in 20 bit mode and RIO is the first bit received in 10 bit mode. In 10 bit mode, ROO:09 are driven high. INPUT-TTL When lllGH, LPEN selects the loopback differential serial inputs pins. When LOW, LPEN selects RX+ and RX- (normal operation). INPUT - Static: TTL The level on this pin selects the parallel data bus width. When LOW, a 20 bit parallel bus width is selected and ROO: 19 are active. When HIGH, a 10 bit parallel data bus is selected (RIO:19 are active) and ROO:I0 will go lllGH OUTPUT-TTL Upon detection of a valid sync symbol this output goes high for a RCLK period in 20 bit mode. In 10 bit mode, the SYNC output goes high for half an RCLK period. INPUT - DIFFERENTIAL Serial Input (Biased at VDDfl, refer to Figure 14-B) The serialloopback data inputs. Functionally equivalent to RX+ and RX-. refer to Figure 14-B) ® VlTESSE 1996 Communications Product Data Book Page 29 1.0625 Gbitlsec Transmitter/Receiver Chipset forFibre Channel or Proprietary Serial Links ' ... Data Sheet ,' Page 30 @ VITESSE Semiconductor Corporation G52079·0Rev.2.7 Data Sheet 1.0625 Gbitlsec Transmitter/Receiver Chipset for Fibre Channel or Proprietary Serial Links Package Thermal Characteristics The VSC7105 and VSC7106 are packaged into thermally enhanced plastic quad flatpacks. These packages use industry standard EIAJ footprints, but have been enhanced to improve thermal dissipation through low thermal resistance paths from the die to the exposed surface of the heat spreader and from the die to the leadframe through the heat spreader overlap of the leadfrarne. The construction of the package is as shown in Figure 16. Figure 16: Package Cross Section Copper Heat Spreader Wire Bond Die Plastic Molding Compound Table 9: 44 and 52 PQFP Thermal Resistance *Note: Includes conduction through the leads of the package for a non-thermally saturated board. The VSC7105 and VSC7106 are designed to operate with at a case temperature up to 90°C. The user must guarantee that the case temperature specification is not violated. Given the thermal resistance of the package in still air, the user can operate the VSC7106in still air if the ambient temperature does not exceed 36°C on a nonthermally saturated board. If the user's environment exceeds 36°C, then the user must either provide adequate airflow, attach a heat sink, or both. Below is an example to guide the user in determining these requirements with additional airflow and with adding a heatsink. G52079-0 Rev. 2.7 Limit LF2 LF2 LF2 LF2 LF2 @ OL2 diS ou iR LR2 LR2 LF2 LR3 LF2 OL2 OL2 LFl LFl LFl OL3 OL3 OL3 OL3 N/A •••• ••••••••• ou LR3 LR3 L» IDLES G520Bl-0 Rev. 1.3 ,mi. VITESSE 1996 Communications Product Data Book .0[,3 NoS. OL2 LFl Page 55 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links AC:LRL :'tRf "LR3 ....IDLE . :....... ~.,.: '.......~..... . ii)t$ .....,. Event Timeout (R_T_T OV) Link Reset N/A LF2 LRl LFL "Li2 .... oii ...'OU ....OM OIS .·iVijs ..OLS ......WQ~H ..iR LF2 LF2 LF2 Note 2 N/A OL3 Note 3 Note 4 OL3 NoteS N/A LRl LRl LRl LRl LRI Note 3 LRl LRl LEGEND L» means receiving from the Link. NIA means Not Applicable. A ** entry means no change in state. NOTES 1) A Primitive Sequence Protocol error is detected. 2) The timeout period starts timing when OIS is no longer recognized and none of the other events occur which cause a transition out of the state. 3) All events are ignored until the Port determines it is time to leave the OIS transmission state. 4) The timeout period starts timing when the Port is attempting to go online, transmits OIS, and none of the other events occur which cause a transition out of the state. 5) The timeout period starts timing when NOS is no longer recognized and none of the other events occur which cause a transition out of the state. 6) Depending on Laser safety requirements, the transmitter may enter a "pulse" transmission mode of operation when Loss of Signal is detected. The Link Control state machine is a Fibre Channel compliant state machine. For proprietary links, this state machine may be disabled by asserting the LCEN signal LOW. Generally, LCSM forces the encoder section to send primitive sequences and asserts REN high to disable reading from the FIFO when a link failure or reset is present. When disabled, LCSM will be disconnected from the encoder section and the encoder will transmit whatever is present on the encoder inputs irrespective of a link failure. Error reporting on the ERRBUS will not be affected and the LCSM(l :0) output will continue to report LCSM states. For a proprietary link in which LCSM is disabled, no primitive sequences except IDLEs will be transmitted except under user control. The LCSM will still detect and report link failures due to loss of synchronization greater than the time-out period and loss of signal when not in the offline state. The user will then need to respond appropriately to these conditions. Page 56 ® VITESSE Semiconductor Corporation G52081-Q Rev. 1.3 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links AC Timing Specifications Encoder Section Figure 6: AC Characteristic Wavefonns EFCLK EN_KCHAR EN_DATA(31 :0) EN_CMN 0(5:0) EFEF# HOLD# EREN# T19:00 ESYNC Nole 1 Use EFClK 10 clock system FIFO's or Oala Source in 32 bit mode. Use EN_ClK 10 clock syslem FIFO's or Data Source In 16 bit moda. Numbera in parenthesis shows clock period for 1.0626 Gbls operetion. G52081-0 Rev. 1.3 ® VITESSE 1996 Communications Product Data Book PageS7 Preliminary Data Sheet High Performance Encoder/Decoder for' Fibre Channel or Proprietary. Serial Links Encoder Section Table 7: Encoder ACTlmlngTable . . .. .. .... Hj>~~t~F:P#~#wi#i# TI Minimum Oock Period T2 EN_CLK to EFCLK Delay ........ •••• :.••.•.•..••• ·Mffl ... ... .. . M'tli •..(i~s 18.0 11.0 T3 Data Setup Time 5.0 1.0 T4 Data Hold Time 1.0 1.0 TS ENYAR Setnp Time 4.0 T6 ENYAR Hold Time 1.0 T7 EFEF# Setnp Time 2.0 TS EFEF# Hold Time 4.0 T9 HOLD# Setup Time 3.0 TlO HOLD# Hold Time 2.0 Tll EN_CLK to EFREN# Delay 11.0 TI2 EN_CLK to T19:00 Delay 11.0 T13 EN_CLK to PERR Delay 14.0 T14 EN_CLK Fall to ESYNC SetupTime 2.0 TIS EN_CLK Fall to ESYNC Hold Time . 1.0 ns ns ... .. ... .. ..... .. 30pFIoad ns 16 bit mode 32 bit mode ns 16 bit mode 32 bit mode ns ns ns ns ns ns ns ns ns ns . .¢~~i# 30pFIoad 20pFIoad 30pFIoad 30pFioad Figure 7: Data Row Waveforms EFCLK TOO:19 Data Is docked out 8 EN_CLK cycl•• latar HOLDil HOLDlIis assorted to prohibit , ..ding ~om FIFO's. Two EF_CLK dock cyd .. 01 IDLE'. in_ted to alow input pipelin. stag .. to lush data. HOLDA timing and number ot Idles required during a h04d cycle is TBO. Page 58 . . ® VlTESSE Semiconductor Corporation G520B 1-0 Rev. 1.3 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Decoder Section Figure 8: Data Flow Waveforms ROO:19 DFCLK The Data received Is docked out 6.6 DEC.CLK cycleolater and clocked ilto the FIFO on the DFCLK rising ""!put. Figure 9: Receiver Timing Waveforms ROO:19 lOSIG RESET, lRESET OFFLINE Numbers in parenthesis shows clock period for 1.0625 Gbls operation. G52081-0 Rev. 1.3 ® VITESSE 1996 Communications Product Data Book Page 59 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Decoder Section Figure 10: System Timing Waveforms (32 Bit Case) DFCLK DEC_KCHAR DEC_DATA{31 :16) DEC_CMND{5:0) DEC_PAR{3:0) DEC_DATA{15:0) Numbers In parentheslll shows clock period for 1.0625 GItI. operation. Figure 11: System Timing Waveforms (16 Bit Case) DEC_KCHAR DEC_DATA{31 :0) DEC_PAR{3:0) DEC_CMND{5:0) ERRBUS{6:0) DFWEND. DFWENDC. LCSM{1:0) Use of DEC_CLK for clocking system FIFO's Numbers in parenthesis showe clock period for 1.0625 Gble operation. Figure 12: Page 60 @ VITESSE Semiconductor Corporation G52081-0 Rev. 1.3 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Decoder Section Figure 13: AC Timing Characteristics Waveforms (32 Bit Case) DFCLK DEC_KCHAR DEC_DATA(31 :16) DEC_CMND(S:O) DEC_PAR(3:0) ERRBUS(6:0) DEC_DATA(1S:0) LCSM(1:0) Table 8: Decoder ACTlmingTabie T( Minimwn Clock Period T[ Duty Cycle 45 Tz RI9:00 Data Setup Time 1.0 ns T3 RI9:00 Data Hold Time 5.0 ns T4 Data Valid Setup to DFCLK Rise 8.0 ns Ts Data Valid Hold from DFCLK Rise 3.0 ns 30 pF load T6 Data Valid Setup to DEC_CLK (16 Bit) 4.0 ns 30pFIoad T7 Data Valid Hold from DEC_CLK (16 Bit) 2.0 ns 30 pF load Ts Control Signals Setup Time 2.0 ns 18.0 Tg Control Signals Hold Times 2.0 TIO DEC_CLK to Data Out Delay 2.0 ns 55 % 30 pF load ns 3OpFIoad 14.0 ns Tn DEC_CLK to DFCLK Delay 17.0 ns 30pFIoad T[Z DEC_CLK to LCSM(I:0) 14.0 ns 2OpFIoad G620B1-0 Rev. 1.3 ® VITESSE 1996 Communications Product Data Book Page 61 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Electrical Specifications Table 9: Absolute Maximum Ratings ··· ... ·.. ;;; .. Para""t~l¥/";;·· Vee lOUT lOUT Te TSTG ,,; ::::::;:: :::: +5V Power Supply Voltage TTL Input Voltage Applied TTL Oulput Current (Dc, outputIDgh) Cast Temperature under Bias Storage Temperature :::: ::; ::; -0.5V to +5.5V -0.5V to Vnn + 0.5V TBD TBD -55°C to +125°C TBD Table 10: Recommended Operating Conditions T Power Supply Voltage Operating Temperature Range ••• +5.0V+5% O°Cto +70°(;\"') Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Ambient temperature. Table 11: DC Characteristics ~atlliJt~rs:.Hn~c~~nH:Mi.1i ::~ji"Max ..V1Jit.fgo#4@1~i" ...................... VOH Output HIGH TTL Voltage VOL Oulput LOW TTL Voltage Vm VJL 1m Input HIGH TTL Voltage Input LOW TTL Voltage TTL Output HIGH Current TTL OulputHIGH Currentfor I/O wilh pull up or pull down macros TTL Output LOW Current TTL Oulput LOW Current for I/O with pull up or pull down macros Supply Voltage Supply Current Power Dissipation IJHP IJL In.p Vnn Inn Pn Page 62 @ 2.4 V 0.4 2.2 V IoH--4.0mA IoL=+4·OmA (for EFCLK. EFREN#. IoL = +8.OmA) V V -10 0.8 +10 IIA VIN=Vnn +10 +200 IIA VIN=Vnn -10 +10 IIA VIN=Vss -200 -10 IIA VIN=Vss 5.25 TBD TBD V mA W Freq. = 53 MHz 4.75 5.0 260 1.3 VlTESSE Semiconductor Corporation G52081-0 Rev. 1.3 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Figure 14: Pin Connection Diagram •••••• vdd Tll 1'02 T12 '1'03 ... Tn T04 T14 1'05 TIS "'" T06 TI6 Tal TI7 "" T08 TI8 T09 IDPVIEW TI9 eD_clk VI. ·:-:-:->X·:-:-l vdd dec clk ROO RIO ROI Rll R02 RI2 ROO ... RI3 R04 RI4 ROS RIS R06 RI6 RC17 RI7 R08 RI8 ROO v.. G52081-0 Rev. 1.3 @ VrrESSE 1996 Communications Product Data Book Page 63 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Pin Description Tables Table 12: Encoder Signals ~ilUrt Wll1l f1 .......... ,i)I# •••.•• EN.PATA(31:0) IN ENJ(CHAR IN H ••••••••••••••• ••• ••• • ••••••••••••••••••••••••• 32 hit Encoder Data Input Bus. "K" Otaracter Input which specifies to the VSC71 (J7 whether byteO is a special character or data character. "1" makes byteO a special character and "0" makes byteO a data character. ENYAR(3:0) IN Parity Inputs ENYAR(O) - Odd Parity Input for Byte 3, EN_DATA(7:0) ENYAR(I) - Odd Parity Input for Byte 2, EN_DATA(1S:8) ENYAR(2) - Odd Parity Input for Byte 1, EN_DATA(23: 16) EN_PAR(3) - Odd Parity Input for Byte 0, EN_DATA(31:24) EN_CMND(5:0) IN Six bit CMND bus for users to transmit Fibre Channel ordered sets. EFEF# IN Encoder FIFO Empty Flag Input. Informs VSC7107 that there are no valid data in FIFO and the VSC71(J7 will issue IDlEs. HOLD# IN Holds back the VSC71 (J7 from accepting data from the FIFO. The VSC71 (J7 will issue idles when the HOLD# is asserted low. EFREN# EN_CLK OUT EFCLK OUT ESYNC IN ENYERR OUT T19:00 OUT Encoder FIFO Read Enable signals the FIFO when VSC71 (J7 is ready for data. Encoder clock input. 53. 125MHz for maximum data rate. IN Encoder FIFO Oock. EN_CLK divided by 2 when configured in 32 bit mode and same as EN_CLK when configured in 16 bit mode. Encoder Sync. When in 16 bit mode, it informs VSC71 (J7 which half of the word is being transmitted. High specifies first half of word. In 32 bit mode, it forces the internal state machine to the upper byte. Parity error detection output. A HIGH indicates the parity circuit has detected a parity error. In 16 bit mode, ENYARO and ENYARI are ignored. Transmission Character output of the encoder section. The 20 hit, 2 encoded byte output. Table 13: Configuration Signals CRCEN IN 32116# IN LCEN IN LOSCONF IN POSIDLE DSYNC_EN IN IN Page 64 Enables CRC generation and checking when asserted high. When high configures the VSC71 (J7 to have a 32 bit system interface and when low configures VSC71 (J7 have a 16 hit interface. Link Control State Machine Enabled when high. Configures LOSS OF SYNCHRONIZATION state machine's invalid transmission word recognition.When high, all the Fibre Channel invalid word rules for loss of synchronization apply. When low only code violations are considered invalid words. Enables generation and recognition of 32 bit positive idle when high. Decoder Sync Enable. Enables word synchronization. ® V1TESSE Semiconductor Corporation G52081-0 Rev. 1.3 Preliminary Data Sheet High Performance Encoder/Decoder for Fibre Channel or Proprietary Serial Links Table 14: Decoder Signals NQ11Ie ··T:YPe DEC_PAR(3:0) our DEC_DXfA(31 :0) our our our our DEC_KCHAR DEC_CMND(S :0) IDLE ......... / .... •• :: VITESSE 1996 Communications Product Data Book Page 77 Data Sheet 1.0625 Gbitlsec Fibre Channel Transmitter/Receiver Chipset Absolute Maximum Ratings (1) Power Supply Voltage, (Voo) .............................................................................................................. O.5V to-t4V PECL DC Input Voltage, (VINP) ........................................................................ ~ .................... -O.SV to Voo +O.5V TTL DC Input Voltage, (VINT) .......................................................................................................... -O.SV to 6.0V DC Voltage Applied to Outputs for High Output State, (VIN'IT0 ........................................ -O.5V to Voo + O.SV TTL Output Current (lour), (DC, Output High) ........................................................................................... SOmA PECL Output Current, (lour), (DC, Output High) ...................................................................................... -SOmA Case Temperature Under Bias, (Tc) ............................................................................................... -Sso to + I2SoC Storage Temperature, (TsTG) ......................................................................................................... _65 0 to + IS00C Maximum Input ESD .................................................................................................................................. 1500 V Recommended Operating Conditions(2) Power Supply Voltage, (Voo) .............................................................................................................. +3.3V ± S% Operating Temperature Range, (T) (3) ............................................................................................ OOC to +110°C Notes: I) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied Exposure to these values for extended periods may affect device reliability. 2) Vitesse guarantees the functional and parametric operation of the part under "Recommended Operating Conditions" except where specifically noted in theAC and DC Parametric Tables. 3) Lower limit is ambient temperature and upper limit is case temperature. Page 78 ® VrrESSE Semiconductor Corporation G52093-0 Rev. 2.5 Data Sheet 1.0625 Gbitlsec Fibre Channel Transmitter/Receiver Chipset Table 18: VSC7115 DC Characteristics (Over recommended operating conditions). Vm(TIL) Input mGH voltage (TTL) 2.0 5.5 V VIL(TIL) Input LOW voltage (TTL) 0 0.8 V 1m(TIL) 11L(TIL) VDD Input mGH current (TTL) 50 J.IA. Input LOW current (TTL) -500 Supply voltage Supply current 3.14 -50 3.47 J.1A V 350 rnA 1.2 W 1DD PD Ll.V1N(DF) Ll.Vour 3.3 1.0 Power dissipation Serial data differential peak to peak input swing S1+/S1- 300 2600 mVpp TX+ITX-ITLX+ITLX-/SO+/SOSingle-ended ou1put differential peak to peak voltage swing 1200 2200 mVpp 1m :,; 6.6 rnA @Vm-5.5V VIN = 2.4V VIN = 0.5V ±5% ofVDD = 3.30V Outputs open, VDD = VDD max Outputs open, V DD = VDD max ACCoupled Internally biased at V DD/2 500 to VDD - 2.0V Table 19: VSC7116 DC Characteristics (Over recommended operating conditions). ..jim.al1iete~i . :::C::::::::::::: : :"': Mhi .. Typ - - - 0.6 2.0 - 5.5 V 0.8 V - 50 V IN =2.4V VIL(TIL) Input LOW voltage (TTL) 0 1m IlL VDD Input mGH current (TTL) - Input LOW current (TTL) -500 Supply voltage Supply current 3.14 Vm Ll.VINS1 G52093-o Rev. 2.5 -50 J.IA. J.IA. 3.47 520 V rnA 1.6 1.8 W 1.63 0 1.65 1.67 0 V 300 - 3200 mV - Input Bias Voltage for HS Differential Inputs Serial data differential peak to peak input (RXIRLX) swing V V .. ...... .:::: ........ : - Ou1put HIGH voltage (TTL) Ou1put LOW voltage (TTL) Input mGH voltage (TTL) Power dissipation Uii« 2.4 VOH(TIL) VOL(TIL) VIH(TIL) 1DD PD Max 3.3 - IoH=-1.2mA IoL=+1.2mA 1m:'; 6.6 rnA @Vm =5.5V VIN=0.5V ±5% ofVDD = 3.30v Outputs open, VDD = V DD max Outputs open, VDD = VDD max VDD = 3.30V, Measure open input voltage ACcoupled Internally biased at VD0f2 ® VITESSE 1996 Communications Product Data Book Page 79 Data Sheet 1.0625 Gbitlsec Fibre Channel Transmitter/Receiver Chipset Figure 23: VSC7115 Pin Diagram TLX+ VDDP TlXVSSD TXVDDP TX+ TEST VITESSE VDDP $0+ VSSD VSSD T07 Tl6 0 so- VSSD VDDA T06 TIS VSSA TOS Tl4 1'04 Tl3 VDDD VSSD Figure 24: VSC7116 Pin Diagram VSST EN_CDET RX+ RXTEST VDDA VDDA VSSA VSSD RLXVDDD RlX+ VSSD VDDD RlS ROS Rl4 R04 0 VDDr VSST VDDr Rl3 R03 Rl2 R02 VSST ~g~~~§~§~gg~~ Top View Page 80 !!l ~~ C"lljlj ® VITESSE Semiconductor Corporation G52093-O Rev. 2.5 Data Sheet 1.0625 Gbitlsec Fibre Channel Transmitter/Receiver Chipset Table 20: VSC7115 Pin Description 30,32,35,37, 43,49,19,21, 23,29,31,34, 36,42,44,50 45 TOO:19 TSELEXT INPUT-TTL Parallel data on the TOO:19 bus is clocked in on ilie rising edge ofTBC. Bit TOO corresponding to 8bll Ob bit a for the first character is transmitted first INPUT-TTL Transmit SELEct EXTernal control. When IDGH, data from ilie serial inputs SI+, SI- is multiplexed onto ilie primary outputs TX and TLX, and serialized data from TOO:19 is gated onto SO+, SO-. When LOW, SO+ is driven IDGH and SO- is driven LOW, and TX and TLX transmit ilie serialized data. INPUT-TTL When IDGH, iliis pin puts ilie transmitter in test mode for factory testing. In iliis mode, TBC is used to serialize 20 bit input data, and ilie internal PWVCO are bypassed. In normal mode iliis test pin is low. 8 TEST 11,9 SO+,SO- 14, 16 SI+, SI- 47,48 OEO,OEl 46 TBC TRANSMIT BYTE CLOCK INPUT - TTL Reference Clock for ilie PLL clock multiplier, nominally at 53.125 MHz. Parallel data on TOO: 19 is latched in on the rising edge ofTBC. The rising edge is also used to phase lock the internal VCO clock. 1,3 TLX+, TLX- OUTPUTS - DIFFERENTIAL (Biased at VDD-l Transmitter loop back ouq,uts, enabled when OEl is high, otherwise driven to a valid high logic leveL Logic high is TLX+ high and TLX- low. AC coupled is required when tying TX to TLX. G52093-0 Rev. 2.5 OUTPUTS - Differential (pECL Levels Referenced to 3.3V) High speed serial ouq,uts. When TSELEXT is high, these pins carry ilie serialized TOO:19 data. When TSELEXT is low, iliese pins are gated to a valid high logic level. AC coupling recommended. Output Enable inputs. When OED is high, it enables ilie primary ouq,uts TX+, TX-. In test mode, when OEO is low it is mapped to a reset for internal registers. When OEl is high it enables ilie loopback outputs ofTLX+, TLX-. = @ = VITESSE 1996 Communications Product Data Book Page 81 Data Sheet 1.0625 Gbitlsec Fibre Channel TransmitterlRec(!1iver Chipset Table 21: VSC7116 Pin Description HPhiI;: ......... , ....... HN~nw ... . .... . ..... ..... ..> . . . . / T •••• ••• .,.., .... 15.25.28. 30.35.37. 41.44.48. 50.16.26. 29.31.36. 38.42.45. 49.51 ROO:19 18 REFCLK 17 EWRAP 22 -RBC 14 COMDET 12.10 RLX+. RLX- 3,4 RX+.RX- 2 EN_CDEf 5 TEST 11.23,24.39 9,13.43 19,21.32. 34.46,47 1,20,27.33. 40,52 VDnD VSSD INPUT-TTL When high. this pin puts the 7116 in,testmode. REFCLK replaces the internal bitclk for factory testing. Normally LOW. Digital Power Suvply Digital Ground VDDT TTL Power Supply VSST TTL Ground 6.7 8 VDDA VSSA Analog Power Supply Analog Ground Page 82 OUTPUTS - TTL RO is the first bit received on the serial data stream. The data bus ROO:19 meets a setup and hold time specification with respect to the falling edge of the recovered clock -RBC. To minimize bounce, due to SSO noise. bits ROO:09 are clocked out 5 bit periods earlier. than bits RI0:19. INPUT-TTL REFerence ClOcK for the PLL clock multiplier. nominally at 53.125 MHz. The Pll will lock if the incoming serial baud rate is .f1.0% of 20X the REFCLK. For GLM applications this input will be tied to the system supplied TBC. INPUT,-TTL Loopback Enable. Electrical WRAP enable. When mGH this pin selects the loopback serial inputs RLX for serial to parallel conversion. When low. the RX inputs are selected. OUTPUT-TTL Recovered byte clock. nominally at S3 MHz. supplied to strobe the parallel output data. On recognizing a +comma sync character in the serial data stream. -RBC is stretched. if necessary. to re-sync, and outputs the sync character on bits ROO:06. The recovered clock is always extended. never truncated when resynchronization occurs OUTPlJr-TTL Upon detection of a positive comma (0011111) this output goes high for one -RBCperiod if EN_CDET is mGH. This output meets the same setup and hold time specified for the ROO: 19 parallel data oUtputs with respect to'the falling edge of -RBC. INPUT - DIFFERENTIAL (Biased at VDDf2) Serialloopback data inputs. AC coupling recommended INPUT - DIFFERENTIAL (Biased at VDDf2) Received serial data inputs. AC coupling recommended. ·INPUT-TTL ENable Comma DEfect. When pulled high. enables word synchronization. Word synchronization occurs \vhen the VSC7116 detects a positive comma (0011111) in the serial data stream. In systems where the word synchronization is undesired. a low on the EN_CDEf input disables the synchronization function and the data will be "un-framed". ®, VITESSE Semiconductor Corporation G52093-o Rev. 2.5 Data Sheet 1.0625 GbiVsec Fibre Channel Transmitter/Receiver Chipset Package Information 52 Pin PQFP Package Drawings F itfim A 39 8 H 13 27 14 ::::mm::: t SO+ ..,Af'----DSO>---~------------------_+~~o F1_ENI----------------------------I F2_ENI----------------------------I HFT-~------------------------~ G52120-o Rev. 2.1 PORT BYPASS CIRCUIT Signal Detect Unit I----FAILI \------- FAIL_LEDI ® VITESSE 1996 Communications Product Data Book Page 85 Data Sheet 1.0625 Gbitlsec Fibre Channel Repeater / Hub Circuit Functional Description I" The VSC7120 contains three functional blocks: a Clock Recovery Unit (CRU), a Signal Detect Unit (SDU), and a Port Bypass Circuit (PBC). These circuits operate at the full 1.0625 Gbls serial data rate and perform functions useful in Disk Arrays, Switches or Fibre Channel Arbitrated Loop (FC-AL) Hubs as repeaters and fault isolators. The CRU is a low jitter-peaking PLL which recovers a 1.0625 GHz clock from the RX serial data input, retimes the RX data then retransmits it through the embedded PBC to the SO outputs. The CRU retimes the incoming data in order to attenuate jitter and increase the amplitude of the signal at the SO outputs. This provides downstream users of this data with a signal of known amplitude and jitter.. The SDU performs two digital checks for valid data transmission to indicate whether the external node is functional. The first check, enabled by FeEN! being LOW, monitors the RX inputs for Fibre Channel 8BIl OB run length violations. All valid 8B/1OB codes have less than six consecutive identical bits so if incoming data has six or more consecutive identical bits, an error will be indicated on the FAlLIIFAlL_LEDI outputs. The second method, enabled by F2_ENI, monitors the RX inputs for a bit pattern ('1111010') found in Fibre Channel Ordered Sets which should be present at least once every 20 microseconds. The SDU provides the building blocks needed by Hubs to implement an extremely reliable and repeatable mechanism for determining when to isolate the external node from the Loop and when to reconnect it to the Loop. The PBC is a 2:1 Multiplexer which passes recovered data from the CRU to the SO outputs (ifPBC_ENI is HIGH) or passes SI data to the SO outputs (ifPBC_ENI is LOW). The Slinputs are always routed to the TX outputs which are gated by the TX_EN1 and TX_EN2 inputs. If both TX_ENI and TX_EN2 are LOW, then TX+ will be HIGH and TX- will be LOW. Otherwise, the TX outputs will be enabled. The VSC7120 has two modes of operation as follows: Repeater Mode Hub Mode Repeater Mode In Repeater Mode, the VSC7120 operates only to retime and buffer serial data from the RX inputs onto the SO output in order to attenuate jitter and amplify the signal. This mode is useful to remove high frequency jitter from the serial data and to amplify the signal to its full voltage swing. For FC-AL storage subsystems, the VSC7120 Repeater is useful in insulating the disk drive array subsystem (Le. JBOD - Just a Bunch Of Disks) from the node connected to it as shown in Figure 1. A more detailed application example is shown in Figure 2. Input data from the upstream node may be noisy and degraded due to long cabling but the VSC7120 Repeater cleans the incoming Fibre Channel serial data prior to its use by the first disk drive. Similarly, accumulated noise inside the array may be eliminated by using a VSC7120 between the array and the downstream FC-AL device. In very large disk arrays, repeaters may be required periodically within the array to remove serial data degradation as a result of data transported over connectors, board traces, and port bypass circuits. The Clock Recovery Unit in the VSC7120 uses an automatic lock-to-ref technique that eliminates the need for any external control logic to lock the CRU's PLL to REFCLK when data is not present on the RX input. When the RX inputs are removed, the PLL will drift away from the REFCLK frequency (Le. 106.25 MHz +1100 ppm). Internal circuitry halts this drift when the PLL reaches approximately +1- 1.5% of the REFCLK fre- Page 86 @ VlTESSE Semiconductor Corporation G52120-o Rev. 2.1 Data Sheet 1.0625 Gbitlsec Channel Repeater I Hub Circuit quency. When RX data is reapplied, the CRU is able to lock onto the new data very quickly since the PLL is quite near the frequency of the data. This automatic Lock-to-Reference feature is extremely important in repeater applications because an intelligent state machine or ruicrocontroller is usually not present to control this function. Figure 25: FC-AL JBOD Application for Repeaters JBOD Single Loop Example Figure 1 shows the VSC7120 being used in a repeater application. The PBC_ENI is set HIGH to pass the re-timed RX data to the SO outputs. The TX outputs would normally be disabled (TX_ENl=TX_EN2=LOW) to reduce power and noise. The SI inputs would be unused and should be terruinated in order to eliruinate oscillations. The SDU circuit can be powered down by disconnecting its supply pins (VSS_SDU, VSST, and VDDT) as shown in Figure 2. Two styles of output buffers are provided on the VSC7120 to allow the user to optimize their system design. The TX outputs are full powered buffers capable of driving long cables or other Fibre Channel devices. The SO outputs are half-powered buffers which are not optimized for driving long cables but can drive Fibre G52120-0 Rev. 2.1 ® VITESSE 1996 Communications Product Data Book Page 87 Data Sheet 1.0625 Gbitlsec Fibre Channel Repeater / Hub Circuit Channel devices such as DIE Modules, board traces and disk drives. In most repeater applications, SO would be adequate. However, in applications where the VSC7UO would drive long cables, the SO outputs should be connected to the SI inputs where the data will be routed to the TX outputs. This allows the user to optimize the design to reduce power and maximize signal quality. Rgure 26: VSC7120 In Repeater Mode Driving Another Device NIC +3.3V Terminate 51 Incoming Fibre'--_ _ _ _.. ~~IRX Channel data LOW LOW HIGH 106.25 MHz NIC NIC NlC TX NIC SOI-~-. TX_EN1 TX_EN2 PBC_EN! REFCLK FCEN! F2_EN! HFT ~ ~ FAIL! FAICLEOI To Fibre Channel Device NIC NIC :::> ,~ C/)I ~ C/) ~ C/)I ~ Nle =No Connect NIC GNO NIC Page 88 @ VITESSE Semiconductor Corporation G52120-0 Rev. 2.1 Data Sheet 1.0625 Gbitlsec Channel Repeater / Hub Circuit Hub Mode The VSC7120 can act as a single-chip Hub node as shown in Figure 3. In this figure, only three Fibre Channel Arbitrated Loop nodes are shown, with each connected to external devices using point-to-point links. This implements a "Virtual Loop" using a "Physical Star" configuration. The functions of a Hub node are: - Send data from the previous Hub node, N-1, to the external device, N (SI to TX) - Retime I Rebuffer incoming data from the external device (RX & CRU) - Monitor incoming data for valid Fibre Channel signals (SDU) - Pass recovered external data to next Hub node, N+ 1, if valid (CRU to SO) - Pass data from previous Hub node, N-1, to next Hub node, N+ 1, if external data is invalid (SI to SO) Figure 27: FC-AL Hub Application Device N-1 DeviceN Device N+1 HUB L ____________________________ ~ The VSC7120 implements most of the Hub node function but requires an external Hub Controller to use the SDU's outputs to control the PBC. The SDU and PBC provide the building blocks needed to isolate non-functioning external devices from the "Loop" but most customers wish to implement their own algorithms for determining when to isolate a device and when to reconnect a device. An FC-AL Hub should react only to catastrophic events such as open lines or shorts but should not respond to bit errors which are handled through standardized Fibre Channel protocols. This "Hub Controller" may be a rnicrocontroller, FPGA or even a simple PLD-based state machine. A more detailed view of the VSC7120 in Hub Mode is shown in Figure 4. In order to pass SI input data to TX, TX_EN1 is tied HIGH and TX_EN2 is left open. The CRU continuously locks onto RX data, retimes it and passes the recovered data to the PBC. The SDU monitors the incoming RX data under control of F1_ENI, F2_ENI and HFT (more about these signals later). The FAIL_LED! is intended to drive an Activity LED. The FAILI output is used by the Hub Controller to configure the PBC with the PBC_ENI input. IfFAILI is negated, G52120-0 Rev. 2.1 ® VITESSE 1996 Communications Product Data Book Page 89 Data Sheet 1.0625 Gbitlsec Fibre Channel Repeater / Hub Circuit then the Hub would normally pass recovered RX data to the next Hub Node via the SO outputs. If FAILI is asserted, then the previous Hub Node's data on SI would normally be passed to the next Hub Node via the SO outputs. The Hub Controller shoUld implement some sort of algorithm to qualify or filter FAILI before changing the state of PBC~ENI. . Figure 28: Fibre Channel Hub Port Duplex Line to FC Port Firom . ExtemaID eVlce Previous Hub Port (80) .. ~ L RX 81 NIC +3.3V I T IQ ~ HIGH- TX_EN1 NlC- TX_EN2 PBC_ENI 106.25 MHz- REFCLK --" FCENI F2_ENlIHFT C/) Q ~ TX 80 Next Hub Port (81) FAIL! FA/CLEDI I-- :::> Q ~ .~ :Jemal Device ~ ::,;; C1,) C1,)1 ~ Jc J-o Jc Hub Controller Page 90 @ VITESSE Semiconducto,.Corpor,ation G5212D-O Rev. 2.1 Data Sheet 1.0625 Gbitlsec Channel Repeater / Hub Circuit Signal Detect Unit Behavior The Signal Detect Unit indicates to the Hub Controller whether the RX input has valid Fibre Channel data. Two digital mechanisms exist to detect valid data. The first, called F1, is enabled when F1_ENI is LOW. This monitors incoming RX data for more than six consecutive ones or zeros. Valid 8BIlOB data will have no more than five consecutive ones or zeros. If more than six consecutive ones or zeros are encountered, then the SDU will assert the fail outputs (FAILI and FAIL_LEDI). The second method, called F2, is enabled when F2_ENI is LOW. Valid Fibre Channel data contains K28.5 characters at least every 20 microseconds. The F2 function within the SDU looks for a 7-bit pattern found in the K28.5 ('11111010') and asserts the fail outputs if this pattern is not encountered within the 20 microsecond period. A Fibre Channel active Hub should react only to catastrophic failure events, such as open lines, since the Fibre Channel protocol handles frame level error conditions. For this reason, the VSC7120's SDU fail outputs are designed to be asynchronously polled and processed by the Hub Controller to develop a high-level, intelligent Link Status in order to control the PBC. This allows the Hub controller, which could be a microprocessor, FPGA or even a PLD, to process all the nodes in the Hub with a common clock and simple control logic. The designer can "program" the sensitivity of the Hub Nodes to various error conditions and error rates. The HFT, High Frequency Timer, input to the SDU controls the F1 and F2 Registers (see the Block Diagram in Figure 6). HFT is debounced internally with a clock that is one eighth of the REFCLK frequency. The HFT input is considered asynchronous to the VSC7120 since the user cannot access this internal clock but HFT does have a minimum pulse width (250 nsec). The F1_ENI and F2_ENI gate the F1 and F2 register outputs to FAILI and FAIL_LEDI. When HFT goes low, the F1 and F2 registers are reset. The F1 detector output goes HIGH when a run length violation occurs. The F2 detector output goes LOW (indicating failure) until the K28.5 7-bit pattern is encountered within the prescribed period. F1 and F2 fault detection have different reaction times with F1 reacting quickly «0.5 microseconds) and F2 reacting slowly (20 microseconds). Moreover, F1 and F2 operate in an opposing manner. The rising edge of HFT is commonly used to sample the fail outputs in the Hub Controller. The user must sample at the lowest rate if both are simultaneously enabled or the user may alternately poll F1 and F2 to benefit from both fast reaction time and protection from oscillating signal failures. The VSC7120 allows flexibility for the system designer to tailor fault detection for their particular system environment, failure mechanisms, and reaction requirements. Figure 29: REFCLKTlming Waveforms REFCLK- - - -\- - - - - - - 'f- - - - - - -\ - - - - f\ - - - - - - - - - - - - - G5212D-O Rev. 2.1 @ - - - -Vlli(mjn) - - - -Vil(max) VITESSE 1996 Communications Product Data Book Page 91 Data Sheet 1.0625,Gbitlsec Fibre Channel Repeater / Hub Circuit Figure 30: Block Diagram: Signal Detect Unit .. .. i.. 31 - GI Recovered RXData FCENI 0 .t:! () GI a; c,.. GI LL. .. C 0 () S .GI C N LL. HFT----I Oebounce REFCLKIB'-----!> One-Shot .JL Figure 31: VSC7120 HFT Timing Waveforms r - Reset FI & F2 Registers on falling edge of HFr 1 HFr \ :... I ' HFrH---..·~I~HFrL n 1 ~----------~, 1 ~----- 1 ,.. Strobe FAIU into Hub Controller If only FI is enabled, High and Low times should be greater than 0.5 usee. If F2 is enabled, High and Low times should be greater than 20 usee. Page 92 @ VlTESSE Semiconductor Corporation G52120-0 Rev. 2.1 Data Sheet 1.0625 Gbitlsec Channel Repeater / Hub Circuit AC Characteristics Range over which both RX and Refloating be centered Difference between REFCLK and RX data frequency. DC Characteristics (Over recommended operating condftions) . ..................... ••PiiitUii~t~n ..................... VOH VOL Vru VIL 1m IlL VDD IDD(Hub) IDD(RPT) PD(HUB) PD(RPT) Il.VOUf(SO) Il.VOUf(TX) Il.V1N G52120-0 Rev. 2.1 •••• / ••••• ••• ....... Ou1put HIGH voltage (TIL) Ou1put LOW voltage (TIL) Input HIGH voltage (IlL) Input LOW voltage (TIL) Input HIGH current (IlL) Input LOW current (fTL) Supply voltage Supply Current (SOU Enabled) Supply Current (SOU not powered) Power dissipation (SDU Enabled) Power dissipation (SOU not powered) SO Ou1put differential peak-to-peak voltage swing TX Ou1put differential peak-to-peak voltage Swing Receiver differential peak-to-peak Input Sensitivity RX and SI @ Mm 7>'P M..h-H 2.4 0.5 2.0 0.8 50 ................. utilii ••••.••.•.•.. CqNdidOm;.·· .• ·•••••···· . . ............................ V V V V IOH--1.2mA IOL = +1.2 mA -50 3.47 450 350 1.56 1.22 J.LA J.LA VIN =2.4V VIN =0.5V V mA mA W W VDD = 3.30V±5% Ou1puts open, VDD = VDD max Ou1puts open, VDD = VDD max Ou1puts open, VDD = VDD max 1000 2200 mVp-p 500toVDD -2.0V 1200 2200 mVp-p 500toVDD -2.0V 300 2600 mVp-p VDD = 3.30V, direct coupled, single ended drive, other input open - 500 3.14 340 260 1.35 0.96 Ou1puts open, VDD=VDD max VITESSE 1996 Communications Product Data Book Page 93 1.0625 Gbitlsec Fibre Channel Repeater I Hub Circuit Data Sheet Abso/ute Maximum Ratings (1) Power Supply Voltage, (Voo) .................................................. ,......................................................... -O.SV to +4V PECL DC InputVoltage, (VINP) •••.•••••....•••..•...•..•.••....•.••.....•••••.••.•..••.•..••••.....••. ~ ••.•.••••••.•.••••• -O.5V to Voo +O.SV DC Input Voltage,· (VINT) ............................................................................................. -0.5\1 to \10D + 2.5V TTL Output Voltage, (Vourr) .............................................................................................. -O.SV to Voo + O.5V TTL Output Current (lour), (OV U~~;~ NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. Page 98 @ 25M4X . -- + t ( COPLANARITY 0.102 M4X. LEAD E VlTESSE Semiconductor Corporation G52120-0 Rev. 2.1 Data Sheet 1.0625 Gbitlsec Channel Repeater / Hub Circuit Ordering Information The order number for this product is formed by a combination of the device number and package type as shown below: VSC7120 OeviceType -----------', VSC7120 - 1.0625 Gbitsisec Repeater Package Type ----------~ OJ: 52 Pin Thermally Enhanced PQFP, 10mm Body Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time without prior notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent of the appropriate Vitesse officer is prohibited. G52120-0 Rev. 2.1 ® VITESSE 1996 Communications Product Data Book Page 99 1.0625 Gbitlsec Fibre Channel Repeater / Hub Circuit Page 10.0. 8 VlTESSE Semiconductor Corporation Data Sheet G52120-0 Rev. 2.1 VITESSE Data Sheet Quad Port Bypass Circuit for 1.0625 Gbitlsec Fibre Channel Arbitrated Loop Disk AITays Features • Supports ANSI X3Tll 1.0625 Gbit/sec FC-AL DiskAttach for Resiliency • TTL Bypass Select • Fully Differential for Minimum Jitter Accumulation. • 0.5W Typical Power Dissipation • Quad PBC's in Single Package • 44-Pin, 10mm PQFP • High Speed, PECL I/O's Referenced to Voo. • 3.3V Power Supply General Description The VSC7121 is a Quad Port Bypass Circuit (pBC). Four Fibre Channel PBC's are cascaded into a single part to minimize part count, cost, high frequency routing, and jitter accumulation. Port Bypass Circuits are used to provide resiliency in Fibre Channel Arbitrated Loop (FC-AL) architectures. PBC's are used within FC-AL disk arrays to allow for resiliency and hot swapping ofFC-AL drives. A Port Bypass Circuit is a 2:1 Multiplexer with two modes of operation: NORMAL and BYPASS. In NORMAL mode, the disk drive is connected to the loop. Data goes from the 7121's L_SOn pin to the Disk Drive RX input and data from the disk drive TX output goes to the 7121's L_SIn pin. Refer to Figure 35 for disk drive application. In BYPASS mode, the disk drive is either absent or non-functional and data bypasses to the next available disk drive. Normal mode is enabled with a HIGH on the SEL pin and BYPASS mode is enabled by a LOW on the SEL pin. Direct Attach Fibre Channel Disk Drives have an "LRC Interlock" signal defined to control the SEL function. Using a VSC7121 in a single loop of a disk array is illustrated in Figure 35: "Disk Array Application". FCAL drives are all expected to be dual loop. The VSC7121 is cascaded in a manner such that all the 7121's internal PBC's are used in the same loop. For dual loop implementations, two or more VSC7121 's should be used. Allocating each VSC7121 to only one of two loops preserves redundancy, prevents a single point of failure and lends itself to on-line maintainability. 7121 Block Diagram IN IN- PBC1 , .. _-----_ .... G52110-0 Rev. 2.1 ,, , I--I-I----j 0 PBC2 , ,--------, @ PBC3 ,, , oUf+ OUf- , _______ PBC4 L ,, VITESSE 1996 Communications Product Data Book Page 101 Quad Port Bypass Circuit for 1.0625 Gbitlsec Fibre Channel Arbitrated Loop Disk A"ays Data Sheet The VSC7121 can be cascaded through the IN and OUT pins for arrays of disk drives greater than 4. For disk arrays with a noninteger multiple of 4 disk drives, the unused PBC's can be hardwired to bypass with a external pulldown resistor. Table 24 is a truth table detailing the data flow through the VSC7121. Figure 1 shows a timing diagram of the data relationship in the VSC7121. There are no critical timing (setup, hold, or delay) parameters for the VSC7121 as this part routes the serial data encoded with the baud clock that is extracted by a Fibre Channel receiver. The primary AC parameter of importance is the jitter or data eye degradation inserted by the port bypass circuit. The design of the VSC7121 minimizes jitter accummulation by using fully differential circuits. This provides for symmetric rise and fall delays as well as noise rejection. Table 24: Truth Table Figure 34: Timing Waveforms IN+/LSI1+/LSI2+/LSI3+/LSI4+/- OUT+/LS01+/LS02+/LS03+/LS04+/- Page 102 ® VITESSE Semiconductor Corporation G52110-0 Rev. 2.1 Data Sheet Quad Port Bypass Circuit for 1.0625 Gbitlsec Fibre Channel Arbitrated Loop Disk Arrays Figure 35: Disk Array Application OualSC or OB-9 JBOD G52110-o Rev. 2.1 ® VITESSE 1996 Communications Product Data Book Page 103 Data Sheet Quad Port Bypass Circuit for 1.0625 Gbitlsec Fibre Channel Arbitrated Loop Disk Arrays Table 25: AC Characteristics (Over recommended operating conditions). Tl Tz TSDR" TSDF Tjittcr Flow-Through Propagation Delay Rising Edge to Rising Edge Flow through Propagation Delay Falling Edge to Falling Edge Serial data rise and fall time Data Jitter Accwnmulatioo. 7.0 DB 7.0 DB 300 ps. TBD ps Delay with all circuits bypassed. 75 Ohm Load Delay with all circuits bypassed. 75 Ohm load. 20% to SO%, tested on a sample basis RMS Output jitter accumulated with Valid SB/l0B code from IN to OUT all PBC stages bypassed. Tested on sample basis. Table 28: DC Characteristics (Over recommended operating conditions). :Pliiiimiiiiin::::: :: VIH(rIL) VlL(TIL) IIH(rIL) IlL(TIL) VDD IDD PD aVIN(DF) AVOlJ'I'(L_SO) AVOlJ'I'(OUI) Page 104 .. .. ::::::::::: p#.#.i#~i( .. ........ ............ Input moo voltage (SEL - TTL) Input LOW voltage (SEL - TTL) Input moo current (SEL- TTL) Input LOW current (SEL - TTL) Supply voltage Supply current Power Dissipation Receiver differential peak-to-peak Input Sensitivity, IN+I- &; L_SIn+lL..SOn+I- output differential peakto-peak voltage swing OUT+1- output differential peak-topeak voltage swing @ ::MiIi" : X:7bi: :::. 2.0 0 :CiiiJiliiiiii$ ::::::::::::: ... viihi: .. ::::::::::::::::: ..................................... V V IIH< 6.6mA@VIH -5.5V j.IA V1N =2.4V VIN =0.5V 5.5 O.S 50 -50 3.50 170 0.6 V mA W 300 2600 mVp-p 1000 2200 mVp-p 500toVDD -2.0V 1200 2200 mVp-p 500toVDD-2.0V -500 3.10 VlTESSE Semiconductor Corporation j.IA VDD = 3.30V ±5% Oulputs open, VDD = VDD max Oulputsopen, VDD=VDDmax ACCoupled. Internally biased at VDnf2 G5211Q-O Rev. 2.1 Data Sheet Quad Port Bypass Circuit for 1.0625 Gbitlsec Fibre Channel Arbitrated Loop Disk A"ays Absolute Maximum Ratings (1) TTL Power Supply Voltage, (VOD) ..................................................................................................... 0.5V to +4V PECL DC Input Voltage, (VINP) ............................................................................................. -O.SV to V DO +O.SV TTL DC Input Voltage, (VINT) .......................................................................................................... -O.SV to S.SV DC Voltage AppJied to Outputs for High Output State, (VINTfV ........................................ -O.SV to VOO + O.5V TTL Output Current (lOUT)' (DC, Output High) ........................................................................................... SOmA PEeL Output Current, (lOUT)' (DC, Output High) ...................................................................................... -SOmA Case Temperature Under Bias, (Tc) ............................................................................................... -Sso to + I2SoC Storage Temperature, (TSTO) ......................................................................................................... -6So to + IS00C Maximum Input ESD .................................................................................................................................. 1500 V Recommended Operating Conditions(2) Power Supply Voltage, (VOD) ...........................................................................................................+3.IV to 3.5V Ambient Operating Temperature Range, (T) ..................................................................................... O°C to + 70°C Notes: CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing per1) manent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. 2) Vitesse guarantees the functional and parametric operation of the part under "Recommended Operating Conditions: except where specifically noted in the AC and DC Parametric Tables G52110-o Rev. 2.1 ¢ii~cIjti~ 190 260 mA VIN=2.4V Outputs open, VDD=VODInaX Outputs open, VOO=VOOInaX Figure 48: Input Structures VDn +3.3V INPUT O-.......-i---+--I--, INPUT Ol-'---~ GND REFCLK and TTL Inputs A G52121-0 Rev. 3.1 High Speed Differential Input (RX+IRX-) B ® VITESSE 1996 Communications Product Data Book Page 123 Data Sheet 1.0625 Gbits/sec Fibre Channel Transceiver Figure 49: Pin Diagram N/C COMDET Vsso TO T1 T2 VSST RO Rl Vooo T3 T4 R2 VOOT R3 R4 RS TS Ts Vooo T7 R6 TS VOOT R7 RS R9 VSST T9 Vsso Vsso NlC (Top View) Table 32: Pin Description TO:9 lO-bit transmit character. Parallel data on this bus is clocked in on the rising edge of REFCLK. The data bit corresponding to TO is transmitted first. INPUT-TTL 22 REFCLK 62,61 TX+,TX- 45-43,4138,36-34 Page 124 This rising edge of this clock latches TO:9 into the input register. It also provides the reference clock, at one tenth the baud rate to the PLL OUTPUTS - Differential PEeL CAC Coupling recommended) These pins output the serialized transmit data when EWRAP is LOW. When EWRAP is HIGH, TX+ is HIGH and TX- is LOW. OUTPUTS-TTL RO:9· lO-bit received character. Parallel data on this bus is clocked out on the rising edges of RCLK and RCLKN. RO is the first bit received on RX+IRX-. Qj) VITESSE Semiconductor Corporation G52121-0 Rev. 3.1 Data Sheet 1.0625 Gbits/sec Fibre Channel Transceiver 19 EWRAP 54,52 RX+,RX- 31,30 Ra..K, Ra..KN INPUT-TTL LOW for Nonnal Operation. When HIGH, an internalloopback path from the transmitter to the receiver is enabled and the TX outputs are held HIGH. INPUTS - Differential PEeL (AC Coupling recommended) The serial receive data inputs selected when EWRAP is LOW. Internally biased tot VDD/2, with 3.3Kn resistors from each input pin to VDD and GND. OUTPUT - Complementary TTL Recovered clocks derived from one twentieth of the RX+/- data stream. Each rising transition of RCLK or RCLKN corresponds to a new word on RO:9. 24 INPUT-TTL Enables COMDET and word resyncbronization when HIGH. When LOW, keeps current word alignment and disables COMDET. 47 OUTPUT-TTL This output goes HIGH for half of an RCLK period to indicate that RO:9 contains a Comma Character ('OOl1111XXX'). COMDET will go HIGH only during a cycle when RCLKN is rising. COMDET is enabled by EN_CDET being HIGH.' COMDlIT TESTI 18,20,23 TEST2 TEST3 OUTPUT This signal is used for factoIY test. For nonnal operation, leave open. 26 16,17,27, 48,49,64 G52121-0 Rev. 3.1 INPUT These signals are used for factoIY test. For normal operation, tie to VDD. N/C No Connection. These pins are not internally connected. ® VITESSE 1996 Communications Product Data Book Page 125 Data Sheet 1.0625 Gbits/sec Fibre Channe/7i'ansceiver Thermal Considerations The VSC7125 is packaged in either a 10 mm PQFP or a 14 mm PQFP with internal heat spreaders. These packages use industry-standard EIAJ footprints, but have been enhanced to improve thermal dissipation. The construction of the packages is as shown in Figure 11. Figure 50: Package Cross Section Plastic Bond Wire Die Table 33: Thermal Resistance ::: Thermal resistance from junction to case Thennal resistance from case to ambient in still air including conduction through the leads. 53 32 °CIW Sea_l 00 Thennal resistance from case to ambient with 100 LFM airllow 44 28 °CIW Sea-200 Thennal resistance from case to ambient with200 LFM airllow 39 25 °CIW Sea-400 Thennal resistance from case to ambient with 400 LFM airllow 34 22 °CIW Thennal resistance from case to ambient with 600 LFM airllow 31 20 °CIW The VSC7125 is designed to operate with a junction temperature up to 110°C. The user must guarantee that the temperature specification is not violated. With the Thermal Resistances shown above, the lOxlOmm PQFP can operate in still air ambient temperatures of 53°C [53°C=11OoC-0.9W"'(10.5°c/w+53°CIW)] while the 14x14 PQFP can operate in still air ambient temperatures of 73°C [73°C=110oC-0.9W"'(10°c/w+32°C/W)]. If the ambient air temperature exceeds these limits then some form of cooling through a heatsink or an increase in airflow must be provided. Page 126 ~ VITESSE Semiconductor Corporation GS2121-0 Rev. 3.1 Data Sheet 1.0625 Gbits/sec Fibre Channel Transceiver Package Information 64-pin PQFP Package Drawing F Item A D 16 33 17 10 14 mm mm 2.45 2.45 MAX 2.00 2.00 +0.10 ±.05 Tol. E 0.30 0.35 F 13.20 17.20 ±.25 G 10.00 14.00 ±.10 H 13.20 17.20 ±.25 I 10.00 14.00 ±.10 J1 TBD TBD TBD J 0.88 0.80 ±.15 K 0.50 0.80 BASIC 32 10"TYP -1A A ~:=;'~'JIf'Jllf~_ STANDOFF rO.25MAX. -- i t l COPLANARITY 0.102 MAX. LEAD E NOTES: Drawing not to scale. All units in mm unless otherwise noted. GS2121-0 Rev. 3.1 ® VITESSE 1996 Communications Product Data Book Page 127 Data Sheet 1.0625 Gbits/sec Fibre Channel Transceiver Ordering Information The part number for this product is formed by a combination of the device number and the package style: VSC7125 cc: Device Type: VSC7125: 1.0625 Gbps Transceiver Package Style (64-pin) QN: 14x14mmPQFP QU: lOxlOmmPQFP Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products specifications or other information at any time Without prior notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life suppo~ appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 128 ® VITESSE Semiconductor Corporation G52121-0 Rev. 3.1 Product Preview 1.0625 Gbits/sec Fibre Channel Transceiver Features • ANSI X3T11 Fibre Channel Compatible 1.0625 Gbps Full-duplex Transceiver • 53.125 MHz TTL Reference Clock • GLM Compatible (FCSI-301-Rev 1.0) • Suitable for Both Coaxial and Optical Link Applications • 20 Bit TTL Interface for Transmit and Receive Data • Automatic Lock-to-Reference Function • Low Power Operation -750 mW • Monolithic Clock Synthesis and Clock Recovery No External Components • 80 Pin, 14x14 mm PQFP Package • Single +3.3V Power Supply General Description The VSC7126 is a full-speed Fibre Channel Transceiver optimized for Host Adapter and other space-constrained applications. It accepts two 10-bit 8B/lOB encoded transmit characters, latches them on the rising edge ofTBC and serializes the data onto the TX+/- PECL differential outputs at a baud rate which is twenty times the TBC frequency. It also samples serial receive data on the RX+/- PECL differential inputs, recovers the clock and data, deserializes it onto two lO-bit receive characters, outputs a recovered clocs at one twentieth of the incoming baud rate and detects Fibre Channel "Comma" characters. The VSC7126 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. VSC7126 Block Diagram EWRAP C>-------------------------------------, RX+ RXRBC(O) RBC(l) L_UNUSE CJ----j COM.J)Ef CJ----I EN_CDET D - - - - - . . J 1.0625 OHz 20 TO:19 ScrialDaia TX+ TX- Synthesized Oock 53.125 MHz TBC C>--..J....----t TXEN#C>--------------------------------------------~ G52148-o Rev. 1.3 @ VITESSE 1996 Communications Product Data Book Page 129 Product Preview 1.0625 Gbits/sec Fibre Channel Transceiver i· I Page 130 ® VlTESSE Semiconductor Corporation G52148-0 Rev. 1.3 Preliminary Data Sheet 1.25 Gbits/sec Gigabit Ethernet Transceiver Features • Gigabit Ethernet Transceiver @ 1.25 Gb/s • Low Power Operation - 700 mW • 10 Bit TTL Interface for Transmit and Receive Data • Suitable for Both Coaxial or Optical link Applications. • Monolithic Clock Synthesis and Clock Recovery - No External Components • 64 Pin, 14 mm Standard PQFP • Single +3.3V Supply • 125 MHz TIL Reference Clock General Description The VSC7135 is a 1.25 Gb/s Ethernet Transceiver optimized for Gigabit Ethernet or 1000Base-T applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency. The VSC7135 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data, deserializes it onto the 10-bi receive data bus, outputs two recovered clocks at one twentieth of the incoming baud rate and detect "Comma" characters. The VSC7135 contains on-chip PLL circuitry for synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no external components. This product is directly derived from the VSC7125 1.0625 Gbls Fibre Channel Transceiver aimed at full-speed Fibre Channel Disk Drives, HostAdaptors and RAID systems. Figure 1: Block Diagram EWRAP RO:9 ~"".---I RX+ RX- RCLK RCLKN 10 TX+ TO:9 Seria1Data TX- Synthelizod Oock REFCLK G52146-{) Rev. 1.2 @ VITESSE 1996 Communications Product Data Book Page 131 Preliminary Data Sheet 1.25 Gbits/sec Gigabit Ethemet Transceiver FuncuonalDescnpuon Clock Synthesizer The VSC7135 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to achieve a baud rate clock at nominally 1.25 GHz. The clock synthesizer contains a fully monolithic PLL which does not require any external components. Serializer The VSC7135 accepts TTL input data as a parallel 10 bit character on the TO:9 bus which is latched into the input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit TO transmitted first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel specification, or an equivalent, edge rich, DC-balanced code. Transmission Character Interface An encoded byte is 10 bits and is referred to as a transmission character. The 10 bit interface on the VSC7135 corresponds to a transmission character. This mapping is illustrated in Figure 2. Figure 2: Transmission Order and Mapping 01 an 88/108 Character Parallel Data Bits T9 T8 T7 T6 T5 T4 T3 T2 T1 TO 8BIlOB Bit Position j h g f i e d c b a Comma Character X X X 1 1 1 1 1 0 0 i Last Data Bit Transmitted i First Data Bit Transmitted Clock Recovery The VSC7135 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and retimes the data. The serial bit stream should be encoded so as to provide DC balance and limited run length by an 8BIlOB transmitter or equivalent. The VSC7135 clock recovery circuitry is completely monolithic and requires no external components. For proper operation, the baud rate of the data stream to be recovered should be within 0.01 % of ten times the REFCLK frequency. For example if the REFCLK used is 125MHz, then the incoming serial baud rate must be 1.25 gigabaud ±0.01 %. Deserializer The retimed serial bit stream is converted into a 10-bit paral1c~1 output character. The VSC7135 provides complementary TTL recovered clocks, RCLK and ~CLKN, which are at one twentieth of the serial baud rate. This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit halfword in the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. Page 132 ~ VlTESSE Semiconductor Corporation G52146-0 Rev. 1.2 Preliminary Data Sheet 1.25 Gbits/sec Gigabit Ethernet Transceiver The resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded into the output register at a point nominally midway between the transition edges of RCLK and RCLKN. If serial input data is not present, or does not meet the required baud rate, the VSC7135 will continue to produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output frequency under these circumstances may differ from their expected frequency by no more than ±1 %. Word Alignment The VSC7135 provides 7-bit comma character recognition and data word alignment. Word synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7135 constantly examines the serial data for the presence of the "Comma" character. This pattern is "OOIIIIIXXX", where the leading zero corresponds to the first bit received. The comma sequence is not contained in any normal SBIlOB coded data character or pair of adjacent characters. It occurs only within a special characters, known as K2S.1, K2S.5 and K2S.7, which is defined specifically for synchronization purposes. Improper alignment of the comma character is defined as any of the following conditions: 1) The comma is not aligned within a the lO-bit transmission character such that TO ...T6 "0011111" 2) The comma straddles the boundary between two lO-bit transmission characters. 3) The comma is properly aligned but occurs in the received character presented during the rising edge of RCLK rather than RCLKN. When EN_CDET is mGH and an improperly aligned comma is encountered, the internal data is shifted in such a manner that the comma character is aligned properly in RO:9. This results in proper character and halfword alignment. When the parallel data alignment changes in response to a improperly alligned comma pattern, some data which would have been presented on the parallel output port may be lost. However, the syncronization character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitiely, regardless of data pattern. On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the comma character and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that it can be captured by the adjoining protocol logic on the rising edge ofRCLKN. Functional waveforms for synchronization are given in Figure 3 and Figure 4. Figure 3 shows the case when a comma character is detected and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma character on RO:9. Figure 4 shows the case where the K2S.5 is detected, but it is out of phase and a change in the output data alignment is required. Note that up to three characters prior to the comma character may be corrupted by the realignment process. = G52146-0 Rev. 1.2 @ VITESSE 1996 Communications Product Data Book Page 133 Preliminary Data Sheet 1.25 Gbits/sec Gigabit Ethernet Transceiver Figure 3: Detection of a Properly Aligned Comma Character RCLK. RCLKN I COMLDET __________~~~________________________________ I + RO:9 TChar: 10 bit Transmission Character Figure 4: Detection and Resynchronizatoin of an Improperly Aligned Comma Receiving Two Consecutive K28.5+TChar TraDSDJ1ss1on Words R<;::LK. RCLKN COMLDET RO:9 I Page 134 Potentially Corrupted -=--" ~: I - -K28.7-K28.7 00""'00000""'000 I ::: :: ::: ::: ::: ::: ::: ::: ::: ::: ::: :: - VSC7135 TX TX+_ ---,. REFCLK TX TO:9 ~ , ..25GbIs Single-Ended Measurement I : OJ Oo,,;~~~o+W~O~OO'O' I :~ Random jitter (RJ) measurements performed according to Fibre Channel 4.3 AnnexA, Test Methods, Section A, 4.4. Measure standard deviation of all 50% crossing points. Peak to peak RJ is.± 7 sigma of distribution. Deterministic jitter (DJ) measurements performed according to Fibre Channel 4.3 Annex A. Test Methods, Section A.4.3. Measure time of all the 50% points of all ten transitions. DJ is the range of the timing variations. G5214S-Q Rev. 1.2 (!!) VITESSE 1996 Communications Product Data Book Page 139 Preliminary Data Sheet 1.25 Gbits/slilc Gigabit Ethernet Transceiver Absolute Maximum Ratings (1) Power, Supply Voltage, (VDD) ••••••.••••.••••..•.••••..•••.••••••••••.•••••••••.•••••••••..••••••••••••.••••••••••••••••••.•••..•••.••• -O.5V to +4V DC Input Voltage (pECI.. inputs) .......................................................................................... -O.5V to VDD +O.SV DC Input Voltage (TIL inputs) ...................................................................................................... -0.5V to S.SV DC Output Voltage (TIL Outputs) ......................................................................................-0.5V to VDD + O.SV Output Current (TTL Outputs) ............................................................................................................... +/-SOmA Output Current (pECL Outputs) ............................................................................................................. +/-SOmA Case Temperature Under Bias ...................................................................................................... -SSo to +12SoC Storage Temperature .................................................................................................................. -6SoC to + lS00C Maximum Input BSD (Human Body Model) ............................................................................................ lS00 V Recomm~nded Operating Conditions Power Supply Voltage, (VDD) .•.•..••....•••...•.•••..•...•••••••••••••••••••••••••••.•••••••••••••••••••••••••.••••••••••••••••.••••••••••+3.3V±S% Operating Temperature Range .......................................................... 00CAmbient to +9SoC Case Temperature Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at oT above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Page 140 ov --------MV - 2.0V TOO: 19 - O.8V Table 3: Transmit Timing ·.· . . ···.Mitt . . ~...UnU . . .raf,ll~tet.zje.se#.J1~~~ T2 / Data setup w.r.t. TBCrising edge 2.0 ns Measured from a Data valid HIGH (2.0V) or valid LOW (0.8V) level to TBC midpoint. Data hold w.r.t. TBC rising edge 3.3 ns Measured from TBC midpoint to a valid HIGH (2.0V) or valid LOW (0.8V) level Table 4: TBC Timing Characteristics ................................................................... ...................... Paran.etb#·. L.l}escriR~n , .. ·..... ·.·.MinHyQJ;UIiiiL .......... . .............................. . To TBC min clock pulsewidth HIGH 6.0 ns Measured 2.0V to 2.0V Tl TBC min clock period LOW 6.0 ns Measured 0.8V to 0.8V TBC Rise and Fall Time 1.0 3.2 ns 0.8Vto2.0V ±200 ppm 65 % TTCR,TTCF FT TBC Frequency Tolerance TDC TBC Duty Cycle G52098-0 Rev. 2.0 ......... . 35 @ TBC Frequency of the two oscillators in a link must meet this tolerance. Refer to GLM Duty Cycle Calculation V"ESSE 1996 Communications Product Data Book Page 155 Preliminary Data Sheet 1.0625 Gbitlsec Fibre Channel Copper Cable Gigabaud Link Module Figure 8: Receive Timing Wavefonns 18.58 nB min both tIuosholdB (while in frequency kick) - TRLOW --"11-TRlllGH-1 --------~--~ -RBe ------------ -------~V - - - - - - - O.8V -T1- - - - - - - - - - - 2.0V Data Valid - - - - - - - - - O.8V ROO: 19 Table 5: Receive Timing TJ Data valid setup prior to -RBC fall 2.50 DB Measured from -RBCmidpoint to a valid moo (2.0V) or valid LOW (0.8V). T2 Data valid hold after -RBC fall 6.0 ns Measured from -RBCmidpoint to a valid mGH(2.0V) or valid LOW (0.8V) Tp -RBC Period when in frequency lock 18.83 DB T oolp -RBC Period when out oflock 18.40 ns TRDC -RBC Duty Cycle when in frequency lock 40 T RH1GH -RBC Min Uock Pulse mGI! 7.0 ns Measured from Valid mGH to Valid mGH(2.0V) T RLOW -RBC Min Clock Pulse LOW 6.7 ns Measured from Valid LOW to Valid LOW (0.8V) -RBC rise and fall time 1.0 3.2 DB 0.6V to 2.2V, tested on a sample basis, 10pF1oad TRCR>TRCP 60 % TDR,TDF Data ou1put rise and fall time 4.0 ns 0.6V to 2.2Y, tested on a sample basis, 10pFIoad TLOCK Data acquisition lock time @ 1.0625Gb/s 2.4 /18 8B/I0B IDLE pattern sample basis Jnput Jitter Tolerance Page 156 Input data eye opening allocation at receiver input for BER ::; lE-12 30% bit time ® VITESSE Semiconductor Corporation As specified in Fibre Channel FC-PH standard eye diagram jitter mask. G52098-o Rev. 2.0 Preliminary Data Sheet 1.0625 Gbitlsec Fibre Channel Copper Cable Gigabaud Link Module Figure 9: Interface Equivalent Circuit for TTL I/O's TTL OUTPUTS TTL INPUTS Host Card Model VSC7181 Model -t'-')--75-0-hm------"'(~ r--tL)------~(~ 4pF±20% ~ 6O-900hm 150 - 190 pS/in <4in I 150 - 190 ps/in <2 in I Note: All output timing measurements made with IOpF load. Table 6: DC Characteristics (Over recommended operating conditions~ .......................... . .................................................... . ....................... .................. ........... ............. ... .......... PWl!let#,.,f . .p#"c,.ip@#Min .. Tyi! Max. Uniti . H¢(Iiidjt.i.Qn, H Vm-TIL TTL Valid Input HIGH voltage 2.0 5.5 V Vn.-TIL TTL Valid Input LOW voltage o 0.8 V VOH-TIL TTL Output HIGH Voltage 2.4 3.8 1 V VOL-TIL TTL Output LOW Voltage 0.6 V 1m-TIL Input HIGH current (TTL) 50 ~A VIN=2.4V In.-TIL Input LOW current (TTL) -50 ~A V1N =0.5V -500 1m:> 6.6mA @Vm = 5.5 V IOH=0.5mA IoL=-I.OmA ID Power Supply Current 0.80 0.95 A Outputs open, V cc = V cc max Po Power Dissipation 4.5 5.2 W Outputs open, V cc = V cc max ilVIN Serial data differential peak-topeak input swing SI+I- & RX+/- 300 3200 mVp-p ACCoupied Internally biased at Voof2 ilVOUTIX TX+/- differential peak-to-peak output voltage swing 1200 3200 mVp-p 750 to VDD - 2.0 V ilVOUTSO SO+/- differential peak-to-peak output voltage swing 1200 3200 mVp-p 500toVDD -2.0V Note: 1 Applies to ROO:19 only. G5209B-o Rev. 2.0 ® VITESSE 1996 Communications Product Data Book Page 157 1.0625 Gbitlsec Fibre Channel Copper Cable Gigabaud Link Module Preliminary Data Sheet Absolute Maximum Ratings (1) Power Supply Voltage, (+5V) ..........................................................................................................-0.5V to +7 .OV DC InputVoltage, (VlNT) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••.••••••••••••••••••••••.•• -0.5V to 5.5V DC Voltage Applied to Outputs for High Output State, (VouV .............................................. -O.5V to Vnn + 0.5V TIL Output Current (lour), (DC, Output High) ........................................................................................... 50mA PECL Output Current, (lour), (DC, Output High) ...................................................................................... -50mA Case Thmperature Under Bias, (Tc) ....................................................................... ,....................... _55° to + 125°C Storage Thmperature, (TSTG) ......................................................................................................... -65° to + 150°C Maximum Input ESD .................................................................................................................................. 1500 V Recommended Operating Conditions(2) Power supply Voltage, (Vnn) ................................................................................................................ .5V+/-10% Ambient Operating Temperature Range, (T) (3)..............................................................................O°C to + 110°C Notes: 1) CAur/ON: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at 0 r above the values listed is not implied Exposure to these values for extended periods may affect device reliability. 2) Vitesse guarantees the functional and parametric operation of the part under "Recommended Operating Conditions: except where specijicallynoted in the AC and DC Parametric Tables 3) Lowerlimit is ambient temperature. Upperlimit is case temperature on the VSC7115 and/or VSC7116. Page 158 @VlTESSE Semiconductor Corporation G52098-0 Rev. 2.0 Preliminary Data Sheet 1.0625 GbiVsec Fibre Channel Copper Cable Gigabaud Link Module Table 7: Input Pin Description ..................... •••• ••••• Piii# •• C03,D04, C04,D05, C05,D06, C06,D07, C07, C08, B03, B04, A04, B05, A05,B06, A06, B07, A07,B08 ...... ·.·.·.Name ••••••••••....•...•••••••••••.••••.••••••••••••••••••••• ·••• P"."~~~..,,.•••••••.• ·•· •••• · ...• ·• ·····•••· •••••••..•••.••••••••••••••• . .... INPUT-TIL Parallel data on the TOO:19 bus is clocked in on the rising edge ofTBC. Bit TOO corresponding to 8b11 Ob bit a. TOO is the first character transmitted. The bit ordering with respect to 8B/I0B code is shown below. TOO:19 TOO:09 - First Data Byte 00 01 02 03 04 OS 06 07 08 SBIl OB code character bit a b c d c i f g h j TIO:19 - Second Data Byte 8BIl OB code character bit 10 11 12 13 14 IS 16 17 18 19 a b c d c i f g h j 09 TBC INPUT-TIL Transmit Byte Clock. This is the 53.125 MHz reference clock provided by the system. The rising edge ofTBC is used to clock in the 20-bit parallel data and provides a reference clock for clock recovery on the receive side. EWRAP INPUT-TIL Enable WraplBnable Strobe ID. Applying a HIGH level to this pin will route serial data ou1put to the deserializer port of the VSC7181 by enabling the TLX ou1puts of the VSC7115 and enabling the RLX inputs of the VSC7116. This connection is internal to the daughter card. When a LOW level is applied, wrap mode is off, and the serial data is sent out the TX pins and received by the RX pins. TSELEXT INPUT-TTL Transmit SL This signal detennines the source of the TX data and the routing of the SI data. When LOW, TX will output the serialized data from TOO: 19 and SO will be static. When HIGH will ou1put the 1.0625 Gbitls serial data on the SI pins. and SO will ou1put the serialized data on TOO:19. C13 LRCPBE# INPUT-TIL Loop Redundancy Circuit Port Bypass Enable. This will disable the TX outputs to a static level when LOW. A lK pullup is applied to this signaI so that if a user does not drive this signal, the TX ou1puts are enabled D20 LC~REF# INPUT-TTL Lock to Reference. The receiver in the CuGLM does not require time spent in locking to reference. LCK_REF is used only to load data iuto the STRO_ID shift register. A20 EN_mET INPUT-TIL ENable Comma DETect. This signal provides control over the byte alignment function of the VSC7181. When LOW, the comma detect and resynchronization circuit is disabled. When HIGH, the VSC7181 will synchronize based on the detection of a comma character. When the link is not operational, EN_CDET is also used to clock data out of the STROB_ID shift register. DB9-5 DB9-9 RX+ RX- INPUT - High Speed, Differential, AC 'J1~ ~~fuzt :k~~F ............... , #:i'~~i. .:ri·':'':'::':'L.L.:' PSCISI, NSCISI In LVDS 2 SCI differential input strobe. PSCIFI,NSCIFI In LVDS 2 SCI differential input flag. PSCIDI[O:15), NSCIDI[O:15) In LVDS 32 SCI differential input data. PSCISO, NSCrsO Out LVDS 2 SCI differential oulput strobe. PSCIFO, NSCIFO Out LVDS 2 SCI differential oulput flag. PSCIDO[O:15), NSCIDO[O:15) Out LVDS 32 SCI differential oulput data. 3.3 Test Access Port and Internal Scan Test Signals :: ..... :... ::: :.:.::::: .:.~ ... ~ig#l . .. Levi-lI. ... #Ptw ............. ~". , PTDI In TTL 1 JTAG Test Access Port (TAP) Test Data In. PTMS In TTL 1 TAP Test Mode Select PTCK In TTL 1 TAP Test Clock. PTDO Out TTL 1 TAP Test Data Out. NTRST In TTL 1 TAP Test Reset PCKHSEL In TTL 1 CLKlllbypass select mux. When asserted CLKlll input will bypass the Pll. and drive the internal SCI clock directly. PTSTMD In TTL 1 Not used. Always assert low. PSTEP In TTL 1 Not used. Always assert low. PSTOP In GTL 1 Not used. Always assert low. TTL 2 PMAINTMDO toggles NlBus parity checking. PMAINTMDl modifies initialization sequence for test pmposes. PMAINTMD[O:l) In Out TTL 1 Internall GHz Pll. clock divided by lO test output IPNC In TTL Factory test scan input Tie to VCC. OPNC Out TTL 1 1 In TTL 1 Factory test enable. Tie to VCC. PDNlOOur TE Factory test scan oUlput. Do not connect. Total Signal Pins = 181 Page 168 ® VITESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 4.0 SCI Overview The objective of the Scalable Coherent Interface (SCI) standard is to provide a high performance interconnect system between processors and processor elements for tightly coupled, cache coherent data communication. SCI utilizes point-to-point links and passes data packets to avoid the problems of bus design such as shared resource bandwidth bottlenecks and design of multi-drop, high speed backplane transmission lines. The DataPurnp chip provides high speed SCI links, sends and receives packets, and manages the data transfer on the SCI physical layer. 4.1 SCI Node Model A complete SCI node consists of high speed SCI input and output links, queues for receiving and sending packets, a bypass FIFO for storage when the node is sending a packet, and upper level protocol management for transaction handling. Figure 4.1 shows a block diagram of an SCI node. Figure 4.1 : SCI Node Mode To System Node Interface Logic Link OUT Link IN G52141-o Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 169 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller The SCI function is broken into two distinct blocks. The physical link interface and queues for packets are handled on the DataPump chip, also known as a link controller. The higher level protoCol such as packet handling, cache coherence, CSR (control and status register) register support, and interface to the system is handled in node-specific interface logic. Therefore, the DataPump chip takes care of getting data packets on and off the high speed SCI link and transferring those packets to and from the node interface logic. 4.2 DatsPump Block Description The basic block diagram of the DataPump is shown in Figure 4.1. Data is received at the stripper block on the link inputs. The start of a data packet contains header information. The first 16-bit symbol in the header is the nodeId address of the target node to receive the packet. The stripper block checks this targetId to see if the packet is for this node. If so, the packet is stripped off the ringlet. If there is receive queue space available, the packet will be stored for later unloading by the node controller. If there is no queue space available the received packet will be discarded and a message will be sent to the sender to retry the packet again later. The receive queue block is split into storage for two types of packets, requests and responses. There is room for up to four packets of each type. Within receive request or response queues, slots are assigned on a first-in! first-out basis. If the packet is not intended for this node it is sent through the bypass FIFO. The bypass FIFO is required to store a packet as it is received if the DataPump is sending data at the same time. The send queue can only begin to transmit a packet if the bypass FIFO is empty. It is only allowed to transmit one packet at a time before it must again check the bypass FIFO. Therefore, the storage size of the bypass FIFO must be large enough to buffer the largest packet size which can be sent. The send queue is also split into two types, requests and responses, of which there are two queue slots for each type. The queue slots are loaded from the node interface logic and the slot loading order and transmission order is based on packet age. The DataPump also contains bus interface logic for communication with the node interface logic and onboard registers for node control and status register (CSR) support. However, on-chip registers are only provided to control the operation of the DataPump - full CSR support according to IEEE Std 1212-1991 must be provided by the node interface logic. 4.3 Physical Layer Connection The SCI physical layer connection consists of 18 differential input and output signals. The inputs consist of 16 data signals (PSCIDI[O:15]), a flag bit (pSCIFI) used to delimit packets, and a strobe signal (PSCISI) for latching incoming data. The outputs consist of 16 data (PSCIDO[O:15]), a flag (PSCIFO), and strobe (PSCISO). Each 16-bit data quantity transferred is called a symbol and is clocked on each rising and falling edge of the strobe signal. The 16 data plus flag signals transition in phase every 2ns (250 MHz) giving an effective data transfer rate of 1Gbyte/sec. Rgure 4.2 illustrates these signals using single-ended notation. Page 170 ® VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller Figure 4.2 : SCI Link Signals SCISI SCIDI[O:15] SCIFI The received strobe PSCISI is used for latching data and flag, but is not used for generating the output strobe PSCISO. The DataPump chip generates its own internal clock for clocking data through the high speed data path and driving out PSCIDO[O:15], PSCISO, and PSCIFO. The internally generated clock. is not guaranteed to be in phase with nor at precisely the same frequency as the incoming PSCISI. Therefore, all SCI link input signals are received on chip through the elastic buffer which re-times the signals to the internal high speed clock and inserts or deletes symbols with a logic state machine to account for small frequency differences between incoming symbols and the internal clock. The clocking boundaries and elastic buffer data re-timing function are shown in Figure 4.3. Symbols called idle symbols are transmitted between data packets or if no packets are being sent. The elastic buffer will only delete idle symbols, not symbols within a packet. Every packet must be followed by at least one idle symbol. This guarantees that there will always be enough idle symbols received which can be deleted in order to make up for the worst case clock frequency difference. Figure 4.3 : Elastic Buffer Data Re-tlmlng ..... PSCIDI [0:15] boundary clock re-timing /' "I t' received data PSCISI internal CLK DataPump Chip GS2141-0 Rev. 1.0 ® VrrESSE 1996 Communications Product Data Book Page 171 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller 4.4 Packet Formats SCI defines two groups of packet types; those packets involved in the logical protocol (send and echo packets), and other special link related packets. The VSC7201A does not support any of the special init packets except for the SYNC packet. 4.4.1 Basic Send and Echo Packets The packets involved in the logical protocol consist of four types; request-send, request-echo, responsesend, and response-echo. Logical protocol transactions are initiated with a requester and completed by a responder. Each transaction consists of two sub-actions; a request sub-action wherein command and possibly data are passed to the responder and a response sub-action where completion status and possibly data are returned to the requester. Each SUb-action involves two packet transfers. One is a send packet initiated at the output link of a producer node and the second is an echo packet returned by the consumer node and received on the input link of the producernode. Hence, normal SCI transactions are usually four-way transactions initiated with a send-request packet from a requester. The target of the request (the responder) sends an acknowledgment of receipt of the request packet by returning a request-echo packet. When the responder is ready with the requested data, it sends a responsesend packet and the original req~ester acknowledges with a response-echo packet. All packets are an integer multiple of four symbols in length. The DataPump supports all SCI packet types except 256-byte block sizes. Therefore, the largest packet size is 96-bytes, or 48 16-bit symbols. The DataPump also uses full 16-bit nodeIds for targetld and sourceId decoding. Figure 4.4 : Request Send Packet Format targetld «FFF016) command sourceID control addressOffset[OO .15] addressOffset[16.31] addressOffset[32.47] ext (0 or 16 bytes) data (0,16,32,48 or 64 bytes) cyclic-redwuiancy code (CRC) Page 172 ® VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller The basic request-send packet construction is shown in Figure 4.4. Each block in Figure 4.4 comprises a 16-bit symbol value. The targetld is the 16-bit nodeld of the target node. Node ID values above FFF0 16 are special reserved values. The command and control fields contain command and flow-control information. Some of the bits used for flow-control are modified by the DataPump chip. See sections 4.6 and 4.7. The sourceld is the 16-bit node ID of the sending node. The 48-bit address offset is interpreted by the responder. A packet may also contain a 16-byte extended header. The presence of extended header is indicated by a bit (com.eh) in the command field. The CRe (cyclic redundancy code) symbol at the end of the packet allows for error checking the entire data packet upon reception. When transmitting a packet from the send queue, the DataPump forms the eRe and appends it to the end of the packet. When receiving a packet into the receive queue, the DataPump forms the eRe as the packet is being received and checks the generated value against this transmitted value to ensure data correctness. Figure 4.5 : Request-Echo and Response-Echo Packet Format command sourceld cyclic-rechm.dancy code (CRC) The node interface logic external to the DataPump does not need to check or generate the CRe. Echo packets are 4 symbols long containing the source and target IDs exchanged, a command symbol which is a modified version of the send command, and the eRe. The DataPump automatically generates all required echo packets as a result of received packets. The node interface logic external to the DataPump cannot generate or receive echo packets. The basic echo packet is shown in Figure 4.5. G52141-o Rev. 1.0 ~ VrrESSE 1996 Communications Product Data Book Page 173 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Control/er Figure 4.6 : Rt\sponse-Send Packet Format targetId «FFF016) conunand sourceld control status forwld backId ext (0 or 16 bytes) data (0,16, 32, 48 or 64 bytes) cyclic-redundancy code (CRC) The basic response packet is shown in Figure 4.6. The response packet is similar to request packet except a status symbol and two nodeld pointers called forwld and backId are returned. These are used in the cache coherency scheme. The DataPump does not, however, handle any upper level cache coherency protocol management. Response packets are simply queued with a length of packet indicator. The DataPump also manages data How control information contained within packets and idle symbols. When no packet is being received, 16-bit idle symbols are received. The DataPump stores and transmits these idles, while checking and managing How control information contained in the idle symbol. For more detailed information about packet types and fields within packets, consult the IEEE Std 1596-1992. Page 174 8 VlTESSE Semiconductor Corporation GS2141-0 Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 4.4.2 Command and Control Symbols The DataPump uses cerUrln bits in the command and control fields for transaction and flow control. The format for these fields is defined in Figure 4.7. These fields are explained briefly in Table 4.1 Figure 4.7: .Command and Control Symbols send packet format: tgt com I sre I cont I ere • • send command symbol (com): I ropr I 8pr Iphase I old I ech 2 2 2 I eh emd 1 7 send control symbol (cont): tre todExp 5 todMant tpr 2 2 tranId 6 echo packet format: tgt com I sec ere echo command symbol (com): I ropr I spr Iphase I old I ech 22211 GS2141-0 Rev. 1.0 bsy 1 I res ItranIdl 6 ® VITESSE 1996 Communications Product Data Book Page 175 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller Table 4.1: Command and Control Bit Fields ...... •• •••••••••••••••••• .jjii FlI114 •••••••••••..... ......................... .~ ..• <. ) ..................... Maximum ringlet priority field. Passed but not used by DataPump. Send priority. Passed but not used by DataPump. com.mpr com.spr com.phase Used by queue control on DataPump. See 4.7 Queue Allocation. com.old Packet aging used by scrubber DataPump to remove old packets. Indicates echo packet; com.ech=O for send, com.ech=l for echo. Set by DataPump duriug transmission. Indicates use of extended header. If set to 1 a 16-byte extended header is present Specifies transaction command. com.ech com.eh com.cmd Used in echo packet to indicate no queue space available on target node. See 4.7 Queue Allocation. In echo packet indicates request or response echo; com.res=O for request, com.res=1 for response. com.bsy com.res Transaction Id set by requester in send-request packet This tranId value is used in all subaction packets related to the request Trace bit. Passed but not used by DataPump. Time-of-death; exponent Passed by but not used by DataPump. Time-of-death; exponent. Passed by but not used by DataPump. Transmit priority, set by node interface. Passed but not used by DataPump. com.tranId conttranId conttrc conttodExp conttodMant conttpr 4.4.3 Idle Symbols Idle symbols fill the spaces between packets. They contain bits associated with ringlet flow control which the DataPump uses to manage the SCI link. Figure 4.8 shows the bit fields and Table 4.2 defines these fields. The least significant byte is the complement of the most significant byte and is used for a simple parity check. Figure 4.8 : Idle Symbol Fields Idle Symbol: error checking bits 1-(8 control bits) 1 1 8 control bits / 1 ipr 2 Page 176 ac cc hg 19loldllt 1 1 1 ® VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller Table 4.2: Idle Symbol Field Descriptions .................... .................... .................... .................... ................... :::::::::::::::::::: ············· ....... BitiiieTd idle.ipr .......................................................... " .-".;;. ;· •••• •••••••• ·•••• OP_SENDQ..TAGO . sqfrzl -> OP_SENDQ..TAGI sqfrz2 -> OP_SENDQ..TAG2 sqfrz3 -> OP_SENDQ_TAG3 errors 18). bit 7 (sendQfull) -load attempted to full send Q bit 8 (dupTranId) - send req packet had a duplicate tranId bit 9 (sizeBlT) - send packet size eITOI bit 10 (NJregPar) - NIBus parity error on register read/write bit 11 (NIsendqPar) - NIDus parity error on send Q load bit 12 - not used bit 13 (rcvQempty) - read attempted from empty receive Q bit 14 (regAddrErr) - register access to bad address RC SCI input line stripper errors bit 18 (badldle) - idle symbol had a parity error bit 19 (badThruCrc) - bad CRC in bypassed packet bit 20 (badSIlpCrc) - bad CRC in stripped packet bit 21 (sIlpTooLong) - stripped packet greater than 48 symbols bit 22 (tossClkStb) - received extra clockStrobe packet bit 23 (reqAcTmo) - request Q reservation early ac timeout bit 24 (rspAcTmo) - response Q reservation early ac timeout RC errors - \VA'~l""~ bit 25 (noInSync) - elastic buffer lost synchronization bit 26 (tooLong) - bypassed packet greater than 48 symbols bit 27 (scrbLgTmr) - scrubber detected no low-go bits in ringlet bit 28 (reqRsvBlT) - bad retry phase on request Q bit 29 (rspRsvBlT) - bad retry phase on response Q bit 30 (acFail) - ac toggled more than once while output blocked echo doesn't match any in sendQ bit31 (echoUnkn)- ® VlTESSE Semiconductor Corporation G52141-Q Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller 4.8.5 DP_SENDQ_ TAG[O:3] Table 4.11: OP_SENOQ_TAG3 Register Offset 30016 (Request Queue Slot 0) LLJ ",~rhli H • .Bi# ............... , .. .. ... ·.· ................... ·.................... ·il~~~G~· ... ·· .. ·.... ·· .... ·..... ·.. ·· .. ···· .. ..... TA~~~$i not used 0 - reserved 1:4 reserved 5 echoNo 6 sndQpar 7 sndQto 8 validbit 9 RO RO RO RO RO RO not used 10:25 - tranid[O:5] 26:31 RO ··UJ (Test usage only: rqvld_s[3:0]) (Test usage only: sqvld_sO) target node for packet doesn't reply, packet scrubbed parity error occurred on packet transmission from send Q cc timeout on packet, no echo received in 4 cc times valid bit for send Q slot 3 transaction ID in send Q slot 3 (request slot 0) Table 4.12: OP_SENOQ_TAG2 Register Offset 30~6 (Request Queue Slot 1) .................. ..... .................... . not used TBfts •. ·..A~ce8F o reserved 1:4 RO (Test usage only: rqvld_s[7:4]) reserved 5 RO (Test usage only: sqvld_sl) echoNo 6 RO target node for packet doesn't reply, packet scrubbed sndQpar 7 RO parity error occurred on packet transmission from send Q sndQto 8 RO cc timeout on packet, no echo received in 4 cc times validbit 9 RO valid bit for send Q slot 2 not used 10:25 tranid[O:5] 26:31 RO transaction ID in send Q slot 2 (request slot 1) G52141-o Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 185 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Control/ef Table 4.13: DP_SENDQ_TAG1 Register Offset 30816 (Response Queue Slot 0) ::::: ::::::::::::::::::::: kiiS ••••• 4#~# not used 0:5 reServed 1:4 RO (Test usage only: rqvld_sf[3:0) reserved 5 RO (Test usage only: sqvld_s2) echoNo 6 RO target node for packet doesn't reply, packet scrubbed sndQpar 7 RO parity error occurred on packet transmission from send Q sndQto 8 RO cc timeout on packet, no echo received in 4 cc times validbit 9 RO valid bit for send Q slot 1 not used 10:25 tranid[0:5] 26:31 RO transaction ID in send Q slot 1 (response slot 0) Table 4.14: DP_SENDQ_TAGO Register Offset 30C16 (Response Queue Slot 1) .;, ....~~~¢ Page 186 ... ................. .................... ...... 'kiiL :··AttiitS . .................. • • :< . :.....,~~~.~~?'''~~~..:> not used 0:5 - reserved 1:4 RO (Test usage only: rqvld_f[7:4]) reserved 5 RO (Test usage Only: sqvld_s3) echoNo 6 RO target node for packet doesn't reply, packet scrubbed sndQpar 7 RO parity error occurred on packet transmission from send Q sndQto 8 RO cc timeout on packet, no echo received in 4 cc times validbit 9 RO valid bit for send Q slot 0 not used 10:25 - tranid[0:5] 26:31 RO • transaction ID in send Q slot 0 (response slot 1) ,® VITESSE Semiconductor CorporatiDn G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller v 4.8.6 DP_PC_ CONFIGO (offset 320u The detailed function of these register bits is described in Section 8.0 Performance Counters. Table 4.15: DP _PC_CONFIGO Register .............. .. IT~iil(t •• Bjh .. ... 4~t~# • IL____ .•. U____ ·•. ____ .•. ________; "~'''c.. ::,.;J .......................... ; ......... pcOmask[O:4] 0:4 RW Selector for the PPCO output pin. Assert only one at a time; bit 0 (pktSlotORs) - PPCO toggles when a packet is transmitted from the . send-response Q slot 0 and the packet matches the command maskl compare value. bit 1 (pktSlotORq) -PPCO toggles when a packet is transmitted from the send-request Q slot 0 and the packet matches the comand masklcompare value. bit 2 (pktRcv) - PPCO toggles when a packet is received and targeted to this node. bit 3 (pktByp) - PPCO toggles when a packet is bypassed. bit 4 (pktSent) - PPCO toggles when a packet is sent. rcvVldMask 5 RW Used to qualify the PPC1 output pin RcvPkt when Ii received packet is actually stripped and the packet is entered into the receive Q (as opposed to tossed for Q reservations or other reasons). extMask[O:4] 6:10 RW Masks the command symbol bits 4,5,7,8,9 from the extended comparison for PPC1 matching. These bits correspond to the command phase, echo bsy, and res bits as follows; bit 6 (extMaskO) -com.phaseO bit 7 (extMask1) - com.phase1 bit 8 (extMask2) - com,ech bit 9 (extMask3) - com.bsy (for echo packets) bit 10 (extMask4) - com.res (for echo packets) extCmp[O:4] 11:15 RW Compare values for command symbol bits 4,5,7,8,9 as described above. cmdSns 16 RW Command sense bit which, when asserted, inverts the cmd field match signal to allow qualifying PPC1 counters on mis-match instead of match. cmdMask[O:6] 17:23 RW Masks the command symbol bits 9: 15 from the command comparisonfor PPC1 matching. These bits correspond to the com.cmd field of send packets (not echos). cmdCmp[O:6] 24:30 RW refMask G52141-0 Rev. 1.0 Comparison value for the com.cmd bits. When asserted forces the PPCO pktRcv signal to be qualified with the ext mask/compare value. If the ext mask/compare is set to match echos, then refMask is used to cause pktRcv to count only echo packets or only send packets. 31 @ VITESSE 1996 Communications Product Data Book Page 187 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Control/er DP]C_CONFIGl is the selector for driving the PPCl pin. The following table lists the function of the PPCl pin when that bit of DP]C_CONFIG 1 is asserted. Only one bit of this register should be set at a time. Setting more than one bit will produce undefined results. See Section 8.0 Performance Counters for a more complete description of these bits. Table 4.16: DP_PC_CONFIG1 Register Page 188 PPC1 asserted while the receive-response reservation state machine state phase matches ext bits 0: 1 (extMask[0:4] set to 11 000 and extCmp[ 0: 1] set to the desired phase) PPC1 asserted while the receive-request reservation state machine state phase matches ext bits 0:1 PPCl asserted while a packet matching the cmdmasklcompare is entered in send-response queue slot O. rsRsvPhs 19 RW rqRsvPhs 20 RW rsSlotOTm 21 RW rqSlotarm 22 RW rRspDepth 25 RW rReqDepth 26 RW sRspDepth 27 RW at a rate proportional to the number of q entries in the send(see Section 8 Performance Counters) sReqDepth 28 RW PPCl toggles at a rate proportional to the nwnber of q entries in the sendresponse queue (see Section 8 Performance Counters) RcvPkt 29 RW PPC1 toggles each time a packet matching both ext and cmd maskI compare values is received and targeted to this node. BypPkt 30 RW SndPkt 31 RW PPCl asserted while a packet matching thecmd mask/compare is entered in send-request queue slot O. PPCl toggles each time a packet matching both ext and cmd maskl compare values is bypassed through this node. PPCl toggles each time a packet matching both ext and cmd maskI compare values is transmitted by this node. @VlTESSE Semiconductor Corporation G52141-O Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 4.9 Error Handling The DataPump checks and maintains an error log which records various error types. Errors fall into two categories; 1) SCI link related errors logged in the DP_ERRLOG fields notruup, flgerr, and strperr[O:6]; and 2) NIBus (node interface bus) transfer errors. SCI link related errors are logged in the DP_ERRLOG fields notruup, flgerr, strperr[O:6], and fatalerr[O:6]. NIB us errors are logged in the DP_ERRLOG.tcode[O:7] field. Multiple errors can occur and will all be logged unless the DP_STATE.sngerr bit is set. 4.9.1 SCI Link Related Errors Errors in the SCI link occur due to protocol or ringlet state errors. Some of these are fatal and cause the link to enter the "dead" state. Fatal errors are listed in Table 4.17. Going to "dead" on fatal errors can be prevented by setting the DP_STATE.stayrun bit. Others are not fatal and will be logged while the SCI link remains in the "running" state. Any SCI link error will assert the node interface logic interrupt pin NINTRNI. It remains asserted until the DP_ERRLOG register is cleared by a CSR write. Table 4.17: Fatal SCI Unk Errors Non-fatal SCI link related errors include errors detected at the input link and send queue related errors. Non-fatal input link errors are listed in Table 4.18. Multiple errors can occur and will be logged unless the DP_STATE.sngerr bit is set. G52141-Q Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 189 Preliminary Data Sheet 1GByteiSecSCI Compliant Link Controller Table 4.18: Non-fatal Input Link Errors Jlgerr 16 tooLong 26 badIdle badThruCrc 18 19 badStrpCic 20 strpTooLong 21 tossClkStb 22 rspAcTmo 23 reqAcTmo 24 Received packet was not properly framed. Bypassed packet greater than 48 symbols. Packet is truncated to 48 and correctly framed. Outgoing CRC is stomped. Received idle with bad parity. Replaced with last good idle symbol. Bypassed packet had bad CRC. Outgoing CRC is stomped. stripped packet for receive queue had bad CRC. Packet tossed and echo CRC stomped. stripped packet for receive queue greater than 48 symbols. Was tossed and echo CRC stomped. Received clockStrobe while still bypassing a clockStrobe. Packet tossed. Allocation counter timed out (acTmr=4) onrespon.se Q reservation before all outstanding reservations completed. Allocation counter timed out (acTmr=4) on request Q reservation before all outstanding reservations completed. The send queue releated errors are of three types listed in Table 4.19. These errors are non-fatal and are indicated by bits in the appropriate DP_SENDQ.TAG registers listed in 4.8.5. Also given in the tag register is the valid bit for the slot indicating whether the packet is actually valid, plus the packet's tranld value allowing identification of the packet with the error. If a send queue related error occurs on a packet in a queue slot, the packet will be held ("frozen") in the slot so that its DP _SENDQ_TAG register can be examined. This "freeze" indication is provided in the. DP_FRRLOG.sqfrz[O:3] field. These send queue errors also assert the NINTRNI pin. Table 4.19: Send Q Tag Error Flags· sndQto 8 sndQpar 7 echoNo 6 Send queue packet time out. Occurs when packet has waited 4 cc counts without receiving a matching echo. Send queue parity error. Upon transmission from send queue if a parity error is detected on the packet data. Echo NONE status returned. If packet receives echo with NONE status indicating targetId addressed no node. These errors are or'ed together to assert the NERRNI signal pin. This pin will remain asserted until all DP_FRRLOG tcode bits are cleared by a register write. Transfer errors are summarized in Table 4.20. Page 190 @VlTESSE Semiconduct()r Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Table 4.20: NI Transfer Errors I> It;;-u.;sendQfull . . . ·. iiii.· . · · · Tried to transfer to full send queue. 7 dupTranId 8 sizeErr 9 NJregPar NlsendqPar rcvQempty 10 11 13 regAddrErr G52141'() Rev. 1.0 14 ~ •••••••• Send req packet has duplicate tranId to packet already in the req queue. Node interface transfer length not multiple of 8 symbols or greater than max 48 symbols. Parity error detected on register write transfer to DataPump. Parity error detected on send queue transfer to DataPump. Tried to transfer from empty receive queue. Register offset address supplied from node interface on register read or write doesn't match any register. VrrESSE 1996 Communications Product Data Book Page 191 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 4.10 DataPump Reset and Initialization SCI auto-initialization as described in the IEEE SCI specification is not supported on this DataPump chip. a greatly simplified initialization scheme has been implemented which requires some software intelligence to start the line. The DataPUmp sequences through four valid chip states described below: RESETLINC - A hard reset of all registers in the DataPump is perfonned (NRESET asserted). DEADliNC - Internal chip clocks are nmning and the DataPump is waiting for the upstream strobe to start. In this state, the state-machines in the linc portion of the chip is frozen. Valid idles are sent from the linc. INITLINC - In this state, the upstream strobe has been received, and we are waiting for upstream synchronization. Tbebypass FIFO has now been re-synchronized but is locked so that no bypass traffic is let through. The output unit sends valid sync and idle packets to the downstream linc. Also, valid and freeze bits are cleared to free up used queue slots (i.e. for a wann restart). RUNLINC - DataPump initialization sequence complete, ready for normal chip operation. The initialization flow Diagram for the VSC7201A is shown in fig. 4.10. The "-" used in the figure indicates the false value of the signal. The "&" means the logical AND and the "+" means the logical OR of the listed signals. The only signals required to cycle through initialization are the NRESET pin and the DP_STATE register bits sigrst and gotodead. However, the following sequence is recommended for reliable synchronization. ~nstead, Figure 4.10 : Initialization Flow Diagram -NRFSEr -sigrst + gotodead Page 192 @VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 1. The NRESET pin should be asserted for at least 8 NICLK cycles then deasserted. The DataPump then proceeds to DEADLINC. 2. The DP_STATE.ruup bit is monitored which, when set, indicates that upstream clock is running. When ruup is detected, DP_STATE.sigrst is set. The DataPump state then advances from DEADLINC to INITLINC. Note that DP_STATE.gotodead was cleared by NRESET and should not be set or else the DataPump will remain in DEADLINC. 3. In the INITLINC state, software should monitor the DP_STATE.insync value which indicates that the upstream block is running and has detected a certain number of sync packets. Once DP_STATEjnsync reaches value "II" (it is a 2 bit field and indicates three sync packets received), then DP_STATE.sigrst is de-asserted and the DataPump enters the RUNLINC state. Setting of the NodeID values and scrubber selection should also be done during initialization. The DP_NODEID value can be set anytime after RESETLINC but MUST be done for all DataPumps in the ringlet before any packets are loaded into any send queues for transmission. The ringlet should also have one and ONLY one scrubber selected (by asserting the NSCRUB pin) before entering the RUNLINC state. The DP_STATE register contains many useful signals related to chip state, initialization, and error control (stayrun and gotodead). See 4.8.1 for a description of this register. G52141-0 Rev. 1.0 @ Va-ESSE 1996 Communications Product Data Book Page 193 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 5.0 Node Interface Sus (NISus) The DataPump communicates with the node controller via a bidirectional GTL interface called the NIBus. The DataPump informs the node controller when receive queues contain data or when send queues have available slots for transmission. The node controller can initiate various commands with the DataPump to read and write packets across this interface. Signal names are prepended with an N or P indicating negative true or positive true signals. 5.1 Interface Protocol and Signal Description The NIBus is a synchronous 64-bit data bus plus 8 bits of byte parity plus control signals. All signals are sampled or driven on the rising edge of CLKNI. The bus master is assumed to be the node interface logic. The DataPump chip is a slave on this bus controlled by asserting chip select, NDPSEL, and a 3-bit command on the PCMND pins. PCMND selected transfers of data can be from 2 to 12 sequential 64-bit data transfers for SCI packets and register reads and writes. 5.1.1 PDATA[O:63], PPARITY[O:7] PDATA is bidirectional data bus for use in transferring data to and from the DataPump. PPARITY indicates byte parity on PDATA. Good parity is odd (all ones give parity of one). PDATA and PPARITY are fioated at the end of the transfer or one cycle after NDPSEL goes false and remain fioated until NDPSEL is asserted. PDATA[O:63] are also fioated by the DataPump starting one cycle after PCMND is sampled, when it responds to a transfer command from the node interface to the DataPump (sendReq, sendResp, and regWrite). PDATA[32:63] are fioated similarly when the DataPump responds to a regRead transfer. 5.1.2 NDPSEL- Datapump Chip Select The NDPSEL input is used to chip select the DataPump and allow it to execute transfers and drive the data and control signals. The cycle in which NDPSEL is asserted, the DataPump will sample its PCMND inputs and begin executing commands. If NDPSEL goes false during any clock cycle of a DataPump command, the DataPump will abort the command cleanly without an error condition. This is an acceptable protocol for aborting DataPump command sequences. One cycle after NDPSEL goes false, all outputs will be fioated except PRCVREQ, PRCVRSP, PSNDREQ, PSNDRSP, PCLKSTB, NERRNI, and NINTRNI. 5.1.3 PCMND[O:2] - Transfer Command The PCMND inputs select the DataPump transfer command as listed in Table 5.1. The PCMND value is sampled in the cycle NDPSEL is asserted. If NDPSEL remains asserted after a transfer has completed, the DataPump will wait until NDPSEL is toggled before sampling a new PCMND. Therefore, NDPSEL acts as a strobe for latching a new PCMND value Page 194 @VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 Gayte/Sec SCI Compliant Link Controller Table 5.1: .PCMND Commands rcvReq rcvResp regRead 001 010 Transfer from the receive-response queue (5-15 cycles). Read contents of target register (4 cycles). reserved sendReq 011 100 sendResp regWrite reserved 101 110 Reserved for future use. Transfer to the send-request queue (5-15 cycles). Transfer to the send-response queue (5-15 cycles). Write contents of target CSR (4 clock cycles, 64 bits max.). 111 Reserved for future use. 5.1.4 NNIACK - Node Interface Acknowledge NNIACK is an input used to indicate valid end of transfer on send, receive, and register transfers. Transfers from the node interface to the DataPump are acknowledged valid by asserting NNIACK simultaneously with the last data transfer cycle. The packet size is determined by the DataPump based on receiving NNIACK with last data. The NNIRDY flow control can be used to delay NNIACK from the end of data if necessary. Aborting a transfer from the node interface to the DataPump should be done with NDPSEL, not NNIACK. Transfers from the DataPump to the node interface are acknowledged received as valid by asserting NNIACK one cycle after the last data transfer. If this acknowledge is provided, the DataPump will remove the packet from its queue after receiviilg NNIACK. NNIACK false one cycle after the last data transfer indicates invalid transfer and abort without error condition. In this case, the DataPump will not remove the transferred packet from the receive queue. 5.1.5 NDPACK - DataPump Acknowledge NDPACK is an output used to indicate valid end of transfer by the DataPump on send, receive, and register transfers. Transfers from the DataPump to the Node Interface are acknowledged valid by asserting NDPACK in the same cycle as the last data transfer. NDPACK false in this case indicates an error condition and the transfer should be disregarded. If the packet had a parity error, it will be discarded after the last cycle of the transfer (based on packet size). IfNDPSEL was deasserted aborting the transfer before the end, the packet will not be removed from the queue regardless of parity error. Data transfer length must be determined by the node interface by saving the "size" value from the header field in the packet and counting cycles. See Section 5.3.1 Condensed RequestlResponse Packets for more on the "size" value. Transfers to the DataPump from the node interface are a~knowledged valid by asserting NDPACK two cycles after the last data transfer cycle. The extra cycle is necessary for parity checking. NDPACK false in this case indicates an error condition and that the transferred packet cannot be accepted and was not queued. See Section 4.9 for interface error conditions. G52141-Q Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 195 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller NDPACK is floated at the end of the transfer or starting one cycle after NDPSEL goes false and remains floated until NDPSEL is asserted. 5.1.6 NNIRDY - Node Interlace Row Control NNIRDY is an input to the DataPump. Flow control is provided through NNIRDY. NNlRDY applies to data transfers and NNIACK acknowledge of transfers in either direction. A false NNIRDY will cause the DataPump to hold its state in the next cycle. It will continue to hold until NNIRDY goes true. The DataPump also qualifies PCMND sampling with NNIRDY. 5.1.7 PRCVREQ, PRCVRSP - Rcv Queue Flags These receive queue flags are outputs from the DataPump indicating the presence of a received packet from the SCI link. These queue flags will not be asserted until the entire packet has been received and the CRC has checked without error. The flags go false (queue empty) two cycles after receiving a receive queue transfer conunand if the packet being transferred is the last in the queue. If the transfer doesn't complete (aborted or error detected) and the packet is not freed from the receive queue, the queue flag will be asserted again at the end of the transfer. These receive flags are always driven and do not float when the DataPump is deselected. 5.1.8 PSNDREQ, PSNDRSP - Send Queue Flags The send queue flags are outputs from the DataPump indicating at least one available queue slot in each queue type (request or response) when asserted true. They will go false (indicating queue full) two cycles after receiving a send queue transfer conunand and if the queue will fill up as a result of the transfer. If the transfer doesn't complete and the packet isn't queued, the queue flag will go true again at the end of the transfer. They will go true indicating that a queue slot has freed up only after receiving a normal echo packet from the target SCI node of the send packet which was freed from the queue. The send queue flags are always driven and do not float when the DataPump is deselected. 5.1.9 NINTRNI-Inte"upt Node Interface NINTRNI is an output of the DataPump and is asserted whenever an error occurs synchronous to the SCI link. These errors are logged in the DP_ERRLOG register not including the tcode error field. NINTRNI remains asserted until the DP_ERRLOG is cleared. NINTRNI is always driven and is not floated when the DataPump is deselected. 5.1.10 NERRNI- NIBus Error Flag NERRNI is an output of the DataPump which is asserted whenever an NIBus transfer error occurs. These errors are listed in Section 4.9. NERRNI remains asserted until the DP_ERRLOG tcode field is cleared. 5.1.11 PCLKSTB - Clock strobe PCLKSTB is an output of the DataPump and is asserted in response to an eventOO packet and whether the DataPump is the clockStrobe master or slave. Page 196 4il VlTESSE Semiconductor Corporation G52141-o Rev. LO Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller The DataPump is the clockStrobe master when the eventOO packet is loaded into its send request queue for transmission. This packet should be targeted to the clock strobe master's DataPump targetId address so the eventOO makes a complete trip around the ringlet and is stripped and tossed by the clockStrobe master. Other DataPumps in the ringlet which pass the even tOO through are clockStrobe slaves. The clockStrobe master will assert PCLKSTB when the eventOO is transmitted on its output link and will deassert PCLKSTB when the packet is stripped at its input link. The clockStrobe slave will assert PCLKSTB for 13 CLKNI cycles when it receives and bypasses the eventOO packet. The slave will also start the DP_ CLKTHRU register to count 4ns SCI clock cycles when the eventOO is received and will stop the counter when the eventOO is transmitted on its output link. PCLKSTB is always driven and is not floated when the DataPump is deselected. 5.1.12NRESET NRESET is an input to the DataPump. Reset initialization of the DataPump occurs when the NRESET pin is driven from low to high. This rising edge transition must be synchronous to the NIB us clock, CLKNI. NRESET must be asserted for at least 8 CLKNI cycles. For a description of reset initialization see sections 4.10 DataPump Reset and 5.7 NIBus Reset and State Sync to the SCI Link. 5.1.13 NSYNCRQ - Send Sync Packet Request The NSYNCRQ pin is used to cause the DataPump to transmit a SYNC packet on its output. A SYNC packet will be scheduled for transmission if a one to zero transition is registered on the NSYNCRQ pin. Additional SYNC packets will only be scheduled after the first is transmitted and if, after that transmission, another one to zero transition is registered on the NSYNCRQ pin. Therefore, NSYNCRQ is intended to be asserted on the order of milliseconds in periodicity. Since the DataPump does not implement any pin-to-pin deskewing, no SYNC packets are required periodically and no NSYNCRQ assertions are required. 5.1.14 NSCRUB - Scrubber Selection The NSCRUB pin is used to select the DataPump as the scrubber in an SCI ringlet. For a description of scrubber selection and initialization see Section 4.10. For information on scrubber operation see the SCI standard Section 3.9.2 Scrubber maintenance. 5.1.15 PPC[O,1J - Performance Counters The PPC output pins provide performance counter signals for monitoring internal events in the DataPump. See Section 8.0 Performance Counters for details. These outputs are synchronous to the internal 250 MHz SCI clock (however, maximum toggle frequency is 66MHz). They are not synchronized in the DataPump to the NIBus clock, CLKNI. 5.1.16 CLKNI- Node Interface Clock CLKNI is the interface clock supplied by the node interface logic. All NIBus signals are synchronous with this clock. G52141-o Rev. 1.0 OJ) VITESSE 1996 Communications Product Data Book Page 197 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 5.1.17 CLKHI, PCKHSEL, PCLK250, PCKHMPY[O:1}, SCI Unk Clock and Control CLKHI (and NCLKHI) is the master differential clock input for generating the internal2S0Mhz SCI clock. It is not required to be phase or frequency related to the node interface clock, CLKNI. The DataPump has an onboard PLL for frequency multiplication to generate 2S0MHz. The CLKHI reference frequency for the PLL is lOOMHz. The internal SCI clock is intended to be 2S0MHz but can be programmed to different values using the PCKHSEL, PCLK2S0, and PCKHMPY[O:l] inputs for debug and diagnostic purposes. The values higher than 2S0MHz are not supported. PCKHSEL is a PLL bypass control input. When asserted the PLL is bypassed and the internal SCI clock is connected directly to the CL KHl input. Any frequency up to 2S0MHz can be provided in bypass mode. PCLK2S0 and PCKHMPY[O:l] provide divisions from the PLL generated SOOMHz value. The divide options and available internal SCI clock rates are given in Table S.2. The values higher than 2S0MHz are documented for completeness buf.are not supported. Table 5.2: SCI Clock Values : : !¢~5,i( .. :::::: . :.. :p:¢K.i:iA!~riii~~j... .mfi4~ ¥ai#~::: :~¢!~11C(~ii~J: .......... ........................................ . ..... 500 10 Page 198 00 2 250 01 4 125 ® VITESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller 5.2 Transfer Packet Formats The packet formats for transfers between the DataPump and node interface differ slightly from the sequential SCI packet format mainly for ease of data alignment to the 64-bit interface. These formats define the sequence of transfer data pertaining to a particular PCMND request from the node interface logic. 5.2.1 Condensed RequestIResponse Packets There are four condensed transfer packet formats corresponding to the PCMND[0:2] transfer command requests- rcvReq, rcvResp, sendReq, sendResp. These condensed packet formats are shown in figures 5.2 - 5.5. Send Queue transfer packets are always transferred from the node interface logic to the DataPump sequentially from header (octlet 0, figs. 5.2, 5.4) to last octlet. Receive-request queue packet transfers from the DataPump to the node interface logic are also always sequential from header to tail. The header information has been condensed to the lower 48-bits of the PDATA bus so that if the node interface logic is split into separate controller and datapath elements the controller need only connect to those 48bits. In both send packets, only the targetId of the destination node is required since the sourceId is provided by the DataPump and cannot be changed. In the receive packets, the targetId is provided in the most significant 16-bits as a matter of completeness, but this value will always be the nodeId of the DataPump. The control symbol contains the fields tranId, tpr, trc, todExp, and todMant. Only the tranId value is really required and used by the DataPump. The trace bit, trc, tpr, time of death count, todExp and todMant, are provided for completeness and are passed but not used by the DataPump. Finally, the packet size, "size", in pairs of octlets (16-bytes) is given in the header of the receive packets to allow the node interface to determine packet length for the transfer. This size value is not required on the send side since the DataPump computes packet length based on when the node interface finishes the send queue transfer with NNIACK asserted. 5.2.2 Register Read and Write Formats Registers on the DataPump are accessed using register read and write CMND transfer commands. On regRead commands, the most-significant 32-bits of the data bus, PDATA[0:31], are driven by the DataPump with the contents of the register specified by the 12-bit register address offset supplied on PDATA[36:47]. In this case, the DataPump ftoats its PDATA[32:63] pins to allow the node interface logic to drive register address offset on PDATA[36:47]. Of course PDATA[32:35], PDATA[48:63], and PPARITY[6:7] must be driven to ones by the node interface logic to give correct parity. On regWrite commands, PDATA[0:31] specify the write data and PDATA[36:47] specify the register address offset. Again PDATA[32:35], PDATA[48:63], and PPARITY[6:7] must be driven to ones by the node interface logic to give correct parity. The effects of the write vary depending on the register. See Section 4.8 Control and Status Support Registers. The data transfer formats for register commands are summarized in Figure 5.6. G52141-Q Rev. 1.0 @ VrrESSE 1996 Communications Product Data Book Page 199 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller FIgure 5.2 : Send-Request Condensed Transfer Packet Format =1:1: r- Q) 16 • FFFF16 8 1 7 16 FF16 lehl cmd 16 targetId addressOffset[OO: 15] :no o control addressOifset[16:31] addressOffset[32:47] 1 SQ) FFFF16 t) extended...hdr..byteO,l extended...hdr_byte2,3 extended...hdr_byte4,5 extended_hdr_byte6,7 2 0 extended...hdr_byte8,9 extended...hdr_byte10,11 extended...hdr_byte12,l extended_hdr_byte14,l 3 r- I/) Q) :n0 0 data_byteO,1 data_byte2,3 data_byte4,5 data_byte6,7 4 data_byte8,9 data_byte10,l1 data_byte12,13 data_byte14,15 5 data_byte16,17 ~byte18,19 data_byte20,21 data_byte22,23 6 data_byte24,25 data_byte26,27 data_byte28,29 data_byte30,31 7 data_byte32,33 data_byte34,35 data_byte36,37 data_byte38,39 8 dllta.-byte40,41 data_byte42,43 data_byte44,45 data_byte46,47 9 data_byte48,49 data_byte50,51 data_byte52,53 data_byte54,55 10 dllta.-byte56,57 data_byte58,59 data_byte60,61 data_byte62,63 1516 3132 4748 11 63 PDATA[O:63] Field Descriptions: targetId - target node ID; eh - extended header flag from control symbol; cmd - command field from control symbol; control- control symbol, tranld (required), tpr, trc, todExp, todMant (all optional); addressOffset[OO:47) - 48-bit address; extended...hdr - either 0 or 16 bytes depending on value of eh flag bit data_byteO-63 - data packet either 0, 16, 32, 48, or 64 bytes Fields set to ones (e.g. FFFF16) are specified to give known parity. These fields are reserved. Page 200 ~V1TESSE Semiconductor Corporation G52141-Q Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller Figure 5.3 : Receive Request Condensed Transfer Packet Fonnat ... CJ) r :tI: Qi 16 ~ CJ) 13 :c 0 1 F161 3 7 1 1 Isiz; eh I cmd 16 16 sourceld control 8 o addre8sOffset[OO: 15] addressOffset[16:31] addre8s0ffset[32:47] 1 extended_hdr_byteO, 1 extended_hdr_byte2,3 extended_hdr_byte4,5 extended..hdr_byte6,7 2 extended_hdr_byte8,9 extended_hdr_bytelO,11 extended_hdr_byteI2,1 extended_hdr_byteI4,1 PPPP16 I/) Qi 4 targetId i- I/) Qi t) 0 t data_byteO,1 data_byte2,3 data_byte4,5 data_byte6,7 3 4 data_byte8,9 data_bytelO, 11 data_bytel2,13 data_bytel4,15 5 data_byte16,17 data_bytel8,19 data_byte20,21 data_byte22,23 6 data_byte24,25 data_byte26,27 data_byte28,29 data_byte30,31 7 data_byte32,33 data_byte34,35 data_byte36,37 data_byte38,39 8 data_byte40,41 data_byte42,43 data_byte44,45 data..:.byte46,47 9 data_byte48,49 data_byte50,51 data_byte52,53 data_byte54,55 10 data_byte56,57 data_byte58,59 data_byte60,61 data_byte62,63 11 1516 3132 4748 63 PDATA[O:63] Field Descriptions: targetId - target node ID, i.e. this node; size - size of complete packet in pairs of oct1ets, from 1 to 6; eh - extended header flag from control symbol; cmd - command field from control symbol; sourceld - node ID of producer of this packet; control- control symbol, tranId (required), tpr, tre, todExp, todMant (all optional); addre8sOffset[OO:47] - 48-bit addre8S; extended_hdr - either 0 or 16 byte8 depending on value of eh flag bit data_byteO-63 - data packet either 0, 16, 32,48, or 64 byte8 Fields set to one8 (e.g. PPPP16) are specified to give known parity. The8e fields are re8erved. GS2141-0 Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 201 Preliminary Data Sheet 1 GByle/Sec SCI Compliant Link Controller Figure 5.4: Send-Response Condensed Transfer Packet Format "*'a> r-- r ... J1 ~ :u J: 0 16 8 FFFF16 FF16 7 16 8 16 targetId lehl cmd status FFFF16 Q) 1 o control forwld backld 1 extendedJl -: ~:>....>o...+:~: ,, ,,, -:- - / ,,, ,, NDPACK ,,, ,,, . -:- - - +-, - - , ,,, ,, ,,, , , NNIRDY ~~~~: :>....>.....>.""'--7-_-t-_-t--_~---:-_--!----'/(HPLD~ ,, ,, , Bus States +- - ,, ,,, , , (qreue wil be full~ PSNDREQ DataPump \'-..;..-_---.;...1___/ IDLE IDLE CMD CMD CMD CMD CHK ACK ACK IDLE (HOLD) This diagram illustrates how NDPSEL going high during ACK always aborts and sends the DataPump to IDLE. In the case of send queue transfers, however, there is no side effect of this abort. The send queue packet has already been validated in the queue by T8. NDPSEL going high after that only has the effect of overriding NNIRDY false (in T9) and sending the DataPump to IDLE. Page 218 ® VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller Figure 5.17 : SendReq Queue Transfer with DataPump Detected Transfer Error Tl T3 T2 T4 T5 T6 TI T8 TlO T9 CLKNI \~--~--~~--+--+~~~--~ , NDPSEL " I I I I PCMND[O:2] ~-j----~--' , , , ~----j---)--~ i i i i i PDATA[O:63] PPARITY[O:7]: NNIACK ~ NDPACK -r m +mLj NNIRDY ~ I I I i I "-L-- ,, ,, , \~+-(q_u_e_U~~_w_il_l_be-r~_"_)__+-__~:____-r__ PSNDREQ DataPump Bus States \~ I IDLE IDLE CMD CMD CMD CMD CHK ACK IDLE CMD This diagram shows a send packet transfer to the DataPump with a DataPump detected error in the transfer. The error could be due to bad parity in the transfer, trying to write a full queue (not in this case since the PSNDREQ queue flag shows room), packet size not a multiple of two octlets or greater than 12 octlets (this example shows a valid packet size and even number of octlets), or request packet has a duplicate tranId to a request packet already in the queue. The error is indicated by NDPACK false in cycle T8 when it should have been asserted true. The NDPACK signal always follows two cycles after NNIACK true (in theACK state) unless NNIRDY is used to add wait cycles. The packet is not entered into the queue and the DP_ERRLOG register records the transfer error and should be inspected by the node interface logic. This diagram illustrates minimum cycle timing of all signals with no hold cycles. G52141-0 Rev. 1.0 @ VrrESSE 1996 Communications Product Data Book Page 219 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Figure 5.18: RcvReq QueueTransfer Initiated by PRCVREQ Flag Tl T2 T3 T4 T6 T5 • T7 T8 TlO T9 CLKNI ·· · NDPSEL I I I t I I I I I I PCMNDI~21_ PDATA[O:63] ~ PPARITY[O:7]: ~- i - - -i- i : : : - ~ --- ~ -- :: i =~~ -r---!-----:-J \ /r-. . NNIRDY .. (queu~ will be ~mpty) PRCVREQ DataPump Bus States IDLE IDLE CMD CMD CMD CMD CHK ACK IDLE CMD This diagram shows a normal packet transfer from the DataPump to the node interface logic. In this case, the packet contains the required header information and 16 bytes of data. Larger data payloads simply extend the number of cycles. NDPACK is used to indicate the end of transfer. This diagram illustrates minimum cycle timing of all signals with no bold cycles. Page 220 @VlTESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller Figure 5.19 : RcvReq Queue Transfer with Hold for NNIACK Tl T2 T5 T4 T3 T8 T7 T6 TlO T9 CLKNI NDPSEL ,, PCMND[O:2] I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I PDATA[O:63] ~.:. - - - -:- PPARITY[O:7] : i i I I I I I I ~ -- - NNIACK NDPACK • I I I I I I I I I I -:- - - - : ' I I I I +-: I ~ ' I I I I I I u ui- u _ J u / : : \ _..; /_:-, . : ~+---~~---r-J ,, ,, NNIRDY ,, , (queu~, will be mpty) PRCVREQ DataPump BusSta1es IDLE IDLE CMD CMD CMD CMD CHK ACK ACK IDLE (HOLD) This diagmm shows the use of NNIRDY to hold off the assertion of NNIACK for one cycle at the end of a transfer to the node interface logic. This may occur if the node interface logic needs an extra clock cycle to verify the transfer and check parity before sending acknowledge, NNIACK. NNIRDY false in T9 causes the DataPump to hold in the ACK state and wait on sampling NNIACK until NNIRDY goes true again in TlO. Once the DataPump sees NNIACK in TIO, it goes into the IDLE state and removes the packet just transferred from the receive queue. If NNIACK had not been asserted in Tl 0, the DataPump would not remove the packet from its receive queue and the PRCVREQ flag would go true again in cycle Tll. G52141-0 Rev. 1.0 ® VrrESSE 1996 Communications Product Data Book Page 221 Preliminary Data Sheet 1G8yte/Sec SCI Compliant Link Controller Figure 5.20 : RcvReq Queue Transfer with Abort During ACK Hold • Tl T3 T2 T4 . T5 T6 no 1'9 T8 T7 CllCNI NDPSEL ~ __ __ __ __ ____ ~~ ~ ~ ~ ~(ar~ PCMND[~.2[~ PDATA[O'63] PPARITY[O:7] ~...:- : : I - -:.. - : ...: - - - -:.. - - -...:- : : : : : : : : =~ T---r-- / \ /-i---_.-~-,, ,, NNIRDY ,,, (queu~ will be ~mpty) PRCVREQ DataPump Bus States IDLE IDLE CMD CMD CMD CMD CHK i ACK IDLE IDLE This diagram shows how NDPSEL going high in the ACK state overrides NNIRDY false (as in T8). At the end of a receive queue transfer the DataPump checks for NNIRDY true and NNIACK true in the ACK cycle (beginning T9) in order to remove the just transferred receive packet from the receive queue. Since NDPSEL aborted the end of the transfer in T9 before the DataPump received NNIACK and NNIRDY true, the packet would not be removed from the queue. This is reflected by the PRCVREQ flag going true again in TlO indicating a packet still present in the queue. Page 222 e vtTESSE Semiconductor Corporation G52141-Q Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Control/er Figure 5.21 : RcvReq queue Transfer with DataPump Detected Transfer Error T1 T3 1'2 T4 T5 T7 T6 T8 CLKNI TIO T9 ,, ,,, \~--------~/\~~ NDPSEL , I I I I I PCMND[O:2]P~ I I I I I I I I I I I I I I I I I I ~~----~- PDATA[O:63] PPARITY[O:7]: i t---+-~ 1 : : : NNIACK NDPACK I I I I I I I I I I , I I • I I I I I I I I I I I I • I I I I I I I I I I I I I I " -:- - - - t- , I I I , , I I ~ ,, PRCVREQ I . -:- - - - t - - - -:- - / , NNlRDY t :, ,, ~ ,, ~-----+----~~ (queu~ will be ,ampty) DataPump BusSta1e8 IDLE IDLE CMD CMD CMD CMD CHK ACK IDLE CMD This diagram shows a packet transfer from the DataPump with a DataPump detected error in the transfer. The error could be due to bad parity in the packet in the receive queue or trying to read an empty queue (not in this case since the PRCVREQ queue Hag shows a packet to be read). The error is indicated by NDPACK false beginning in cycle T8 when it should have been asserted true. The NDPACK signal always occurs in the last data transfer cycle as indicated by counting octlets transferred up to the "size" value provided in the header octlet. If the error was due to a parity error in the packet, it is removed from the receive queue in the ACK cycle even if the bad parity were detected in cycle T4, first data. However, if NDPSEL goes false anytime before ACK the transfer will abort and the packet will be retained in the queue even if it had bad parity. This gives the same behavior due to abort if an error occurred or not. The DP_ERRLOG register records the transfer error and should be inspected by the node interface logic. G52141-o Rev. 1.0 OJ) VITESSE 1996 Communications Product Data Book Page 223 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller Figure 5.22 : RegWrlte Transfer Tl T2 T3 T6 T5 T4 CLKNI T8 T7 TI0 T9 ,, ,,, \Y~~--~~~--~--r-~--~ ,, NDPSEL PCMND10,2J _ ~~pPARrry[o:7]~ 1 PDATA[O:63] NNIACK - - < -1- - ad1' data>-~ - - - ~ - - - - ~ - ~ 1 ; 1 ~! I , I I I I I I i 1 I I I I ~ I I I I I I I I :::~::~~ NDPACK ·4----r-- n in . 1 I I NNIRDY . ... ,, , I DataPump ,, I I , I I I I I I I I I I I ' I I I I I I I I I I I I I t 1 I ,, ,, , 1 IDLE l ,, : u-/-ln~ I I I I I t ~"":""" rr:~ I Bus States I I ,, , IDLE 1 CMD I I I I I I ,, , CHK ACK IDLE 1 CMD CMD CMD CMD , ,, This diagram shows a normal register write transfer from the node interface logic to the DataPump. In this case, register address offset and data are provided in T4 along with NNIACK. NDPACK is used to acknowledge the end of transfer in T6. This diagram illustrates minimum cycle timing of all signals with no hold cycles. Page 224 @VlTESSE Semiconductor Corporation GS2141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Figure 5.23 : RegWrite Transfer with DataPump Detected Transfer Error T1 CLKNI T2 , T3 , T4 , T5 T7 T6 T9 T8 TIO ~~ ,,, ,,, ,, , I I , I \ i i i 1T\'-----7"---:----~__:_--:- NDPSEL PCMND[O:2] I ~ : : ~:i i: i: ~,,,,,,,,,":""""'"'''''<''' : : : : , , I , I , I I I I PDATA[O'63] ~..!----:...-~-:...---~----~- ~ PPARITY[O:7]: NNIACK ~i I I NDPACK iii ' ' I I I I +---+----:-_/ ' I I • I , I I I • "-~-~ NNIRDY • I I I DataPump Bus States I I I I • I I , I I : IDLE IDLE CMD CHK ACK IDLE: CMD • I I I ,, " " CMD CMD I I I I CMD This diagram shows a register write transfer from the node interface logic to the DataPump with a DataPump detected transfer error, Errors of this type could be bad parity in the transfer or bad register offset address. In either case, the error is indicated by NDPACK false in T5 when it should have been asserted true. No register is written and the DP_ERRLOG register records the transfer error and should be inspected by the node interface logic. This diagram illustrates minimum cycle timing of all signals with no hold cycles. G52141-0 Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 225 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Figure 5.24 : RegRead Transfer T1 T3 T2 TS T4 T6 TS T7 TIO T9 CLKNI NDPSEL ··, · I PCMND[O:2] I I I DATA[32:63] PARITY[4:7] DATA[O:3I] PARITY[O:3] I , I I I t 1 I I I I I I I I I I I I I I I I I I I I I I I I f I ~t----!--~eiaddr>-~---i----f-~ ~-j----t----i-~egt>-i--~ NNIACK NDPACK NNIRDY DataPump BusStale8 : : I I I I I f : : : : : : : : t I I I I I I I I I I I I I I I I I I I I -r---+---L-~l--~ I , I I I ~:: I I I I I I I I I I I · IDLE . IDLE I I I I I I I I I I I I ' I I I I I CMD· CHK . ACK . IDLE . CMD . CMD CMD· CMD . . This diagram shows a normal register read transfer from the node interface logic to the DataPump. In this case, register address offset is provided in T4. The DataPump provides register read data back in cycle T5 along with NDPACK. NNIACK is not required in this case since the DataPump would take no action based on a true or false NNIACK. This diagram illustrates minimum cycle timing of all signals with no hold cycles. Page 226 @VlTESSE· Semiconductor Corporation G52141-o Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller Figure 5.25 : RegRead transfer with DataPump detected error T2 TI TS T4 T3 CLKNI T7 T6 T8 TIO T9 ,,, ,, \~--~~~~~--~--~~--~ ,, NDPSEL PCMND[O:2] I I DATA[32:63] PARITY[4:7] DATA[O:31] PARITY[O:3] , I I I I I I I ~t-~e~addr>t- I I I ' I . ' I -1- --- ----l- --- t ----;-' 6 deDre -'-i- --- +--- -i- ---1- --- ~. I I I I I ' I I I I ' I I 1 I I I I I , I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I NNIACK I I I I ,, NDPACK I I ,, ~+-~ -1----r---~--/ , , ,, ,, I I I I I I • I I I I I I I I , I f I I I I I I I I I I I I I I I I I I I NNIRDY DataPump Bus States ,, ,, , ,, 'IDLE 'IDLE " ,, ,,,. 'CMD CHK I I I I I 'ACK 'IDLE 'CMD 'CMD 'CMD 'CMD ' This diagram shows a register read transfer with a DataPump detected transfer error. This type of error could only be a bad register offset address. The error is indicated by NDPACK false in T5 when it should have been asserted true. The data provided by the DataPump in T5 is undefined. The DP_ERRLOG register records the transfer error and should be inspected by the node interface logic. This diagram illustrates minimum cycle timing of all signals with no hold cycles. G52141-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 227 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller 6.0 SCI High Speed Link Signals The high speed interface on the DataPump chip complies with the Low Voltage Differential Signals proposed IEEE Std 1596.4. These are unidirectional, fully differential signals. The DC and AC electrical specifications are given in Section 11.0 Electrical Specifications. 6.1 PSCIDI[O:15} and PSCIDO[O:15} - Data These are the 16-bit parallel data in and data output signals. The outputs have 50 ohm output impedance in each differential output. The inputs are terminated between true and complement inputs with on-chip nominal 100 ohms as shown in Figure 6-1. Figure 6.1: PSCIDI and PSCIDO Terminations v... 6.2 PSCISI, PSCISO - SCI Strobe This is the input and output strobe signal. The strobe transitions at the same time as data and flag and is used to latch data and flag into the DataPump on both edges. The DataPump has internal delay between strobe and data, flag to generate a clock signal for the input registers. 6.3 PSCIF/, PSCIFO .. Flag Bit Encoding Flag is asserted at the beginning Of a packet to indicate packet start. Flag is de-asserted near the end of a packet to indicate packet end. The number of cycles flag remains asserted depends on packet type. If flag remains asserted at least 4 cycles, the packet must be a send packet (or an ABORT packet in which flag stays high 6 cycles and causes a nolnSync error). The minimum send packet is 8 symbols. Flag will be deasserted 4 symbols before the end of the packet (indicating when to begin creating an echo packet if necessary). Page 228 @VlTESSE Semiconductor Corporation G52141-o Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller An echo packet has a sequence of 3 cycles when flag is asserted. Flag goes false on the last cycle of the echo packet. Sync packets have 8 symbols and flag is asserted on the first symbol only. The ABORT packet (see Section 4.4.4 Special Packets and Flag Encoding) is 8 symbols long and the flag is asserted for the first 6 symbols. G52141-0 Rev. 1.0 @ VrrESSE 1996 Communications Product Data Book Page 229 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller 7.0 Latency (this section intentionally left blank) Page 230 e VlTESSE Semiconductor Corporation G52141-o Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller 8.0 Performance Counters Two output pins, PPCO and PPCl, are provided for monitoring certain internal events in the DataPump and which can be used along with external counters to monitor various performance aspects. There are two CSR registers which control the events which drive the PPCO and PPCl signals. Performance metrics are usually calculated by accumulating a reference count and dividing that into a qualified count with the ratio representing the performance metric. PPCO is the output pin used to generate the reference count and PPCl is used for the qualified count. For example, PPCO may be set up to count all packets sent by the DataPump and PPCl may be set to count all packets sent with a retry phase. The ratio of PPCl to PPCO is then the percentage of transmissions by this DataPump which were retrys. Another example would be to set PPCO to count all bypassed packets and PPCl to count bypassed packets which were coherent memory read requests. The ratio of PPCl to PPCO would then represent the percentage of those type packets out of all packets travelling to other nodes around the ringlet. 8.1 Command Field Mask/Compare There are three 7-bit mask/compare functions located in the DataPurnp for performing a match on a packet's command field value. There is one comparator in the SCI input block, one in the SCI transmission block, and one at the send queue. A match out of these comparators occurs according to the following logic; cmdMatch «packet.cmd[9:15] & cmdMask[0:6]) (cmdCmp[0:6] & cmdMask[0:6]» Thus, a bitwise equal comparison is made between the cmdCmp value in the DP_PC_CONFIGO register and the packet's command field cmd value (bits 9 through 15). The cmdMask value masks off the comparison on a bitwise basis if the corresponding cmdMask bit is set to one. "cmdMatch" then goes true if all bits of the packet's command.cmd value is equal to the cmdCmp value for the bits which are not masked off by cmdMask. A DP]C_CONFlGO register bit is also provided to invert the sense of "cmdMatch" called cmdSns. If cmdSns is set to one, "cmdMatch" will go true for mismatches instead of matches. These comparators located in the SCI input, SCI transmission block, and the send queue are used to qualify the counting of packets to match user specified command values. For example, the "cmdMatch" result will go true only for response packets if cmdCmp is set to 1111100 and cmdMask is set to 0000011 and cmdSns is 0 since response packets can have only the command field values of 1111100,111101,1111110, or 1111111. If cmdSns is set then to 1 then "cmdMatch" will go true for non-response packets (requests, moves, and events). In this way, the command comparator can be set up to match any type of packets. = == 8.2 Extended Command Field Mask/Compare In addition to the command field mask/compare functions there are two extended command field mask/ compare functions. One is located in the SCI input block and one in the SCI transmission block. The extended command field comparator is 5-bits wide and operates on the command symbol bits 4,5,7,8, and 9. Bits 4 and 5 are the com.phaseD and com.phasel bits which are used by the queue reservation protocol. Bit 7 indicates the packet is an echo when set. Bits 8 and 9 are the com.bsy and com. res bits respectively when the packet is an echo. Therefore, the extended command field mask/compare is useful for looking at the phase of packets to check for retry traffic and also for distinguishing echos from send packets. The logic for this mask/compare is as follows; G52141-0 Rev. 1.0 @ V"ESSE 1900 Communications Product Data Book Page 231 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller = = extMatch «packet.cmd[4,5,7-9] & extMask[0:4]) (extCmp[0:4] & extMask[0:4]) The values of extMask[0:4] and extCmp[0:4] are put into the DP_PC_CONFIGO register. The mask/compare functions exactly like the command field masklcompare except on different bits of the command field. 8.3 PPCO Functionality The reference counter PPCO can be set to monitor one of five events. The PPCO output will toggle every time one of these events occurs. A resetable extemal counter should be connected to the PPCO pin to accumulate a reference count over some time interval. These countable events are; 1. pktRcv - Packets received (i.e. target ID of packet matches this DataPump's nodeid) including echoes. Echoes can be excluded from this count by using the DP]C_CONFIGO refMask bit. This bit enables the extended command field masklcompare result to qualify the pktRcv PPCO signal. Therefore, to exclude echoes from the pktRcv count the refMask bit is set, the extMask value is set to 11011 and the extCmp value is set to 00000. This will cause pktRcv to toggle only on received send packets. 2. Packets bypassed, including echo packets. 3. Packets sent, not including generated echoes. 4. Number of packets transmitted from the send-request queue. 5. Number of packets transmitted from the send-response queue. Thus, the counter connected to PPCO can be used to count all packets received, sent, or bypassed by this DataPump over a particular time interval or can count the number of packets transmitted from either of the send queues over a time interval. This count value will be used as the refemce value to measure some other qualified count value against. The qualified count value is generated by the PPC1 signal. 8.4 PPC1 Functionality The qualified counter PPCl can be set to monitor one of 13 different events. These events are broken down into the following categories; 1. Toggle whenever a matching packet is received, bypassed, or sent. These are used to monitor the packet traffic and bandwidth utilization on the SCI links. 2. Toggle at a rate proportional to the current number of packets in one of the four queues. This can be used to measure average queue depth and utilization. 3. Toggle whenever cc or ac changes. These give a measure of time around the ringlet and allocation time around the ringlet. 4. Assert whenever a matching packet is entered into one of the send queues. This is used to measure latency of a packet in the send queue; that is, the amount of time a packet spends in the send queue from the time it is entered until it is finally accepted at the other end and removed from the queue. 5. Assert whenever the current reservation phase matches the extended mask/compare value in the phase bits. This is used to measure the amount of time the DataPump spends in each of the reservation phases. The DP]C_CONFIG1 register selects which of the 13 signals drives the PPCl output pin. A value of one in that register corresponding to a particular signal will selct that signal to drive PPCI. If more than one bit of DP_PC_CONFIGl is set to one the PPC1 output will be unpredictable. Page 232 e VlTESSE Semiconductor Corporation G52141-o Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Contro/Jer 8.4.1 Toggle on Matching Packet There are three signals which will toggle when detecting a matching packet. These are; t. RcvPkt - toggle when a matching packet is received at the SCI input link and the target ID matches this DataPump. This includes received echo packets but not generated echo packets. An additional qualifier bit in the DP_PC_CONFIGO registeris the rcvVldMask bit. When set to one, RcvPkt will toggle only on matching receive packets which in fact get entered into the receive queue. This would eliminate toggling on receive matching packets which are tossed because the receive queue is full or for other reasons such as bad CRC, etc. 2. BypPkt - toggle when a matching packet is bypassed from the input link to the bypass FIFO. This includes received echo packets but not generated echos. 3. SndPkt - toggle when a matching packet is transmitted from the send queue to the SCI output link, e.g. this does not include echos generated by the input link on retry echos. All three of these signals use both the cmdMatch and extMatch results to qualify the toggling of the signal. The result of these comparators is anded together to generate the qualifier. There is a cmdMatch and extMatch comparator in both the SCI input link (used to qualify RcvPkt and BypPkt) and the SCI output link (used to qualify SndPkt). 8.4.2 Average Queue Depth Measurement When PPCt is set to monitor one of the four queue depth signals (rRspDepth, rReqDepth, sRspDepth, sReqDepth) it will toggle at a rate proportional to the number of packets in that queue. If there are four packets in the queue PPCt will rise and fall 4 times during an S cycle CLKNI period. If there are three packets it will rise and fall 3 times in that same S cycle interval, for 2 packets it will rise and fall twice, and for t packet it will rise and fall only once. Therefore, a counter should be connected to PPCt and a seperate counter to CLKNI. Average queue depth could then be calculated by first resetting both counters, letting them run for an interval while normal SCI operation occurs, then stoping them and using the following formula; average queue depth = (pPCt count)/«CLKNI count)/S) In this way, the average queue depth can be determinoo for any queue under various loading conditions, etc. 8.4.3 CC and AC Ringlet Time Measurement PPCt can also be connected to signals monitoring the idle.cc and idle.ac bits going through the DataPump. When PPCt is connected to either of these signals, it will basically reflect the value of idle.cc or idle.ac in the DataPump. 8.4.4 Send Queue Latency Measurement The amount of time a send packet resides in the send queue can be monitored by connecting PPCt to one of the signals, rsSlotOTm or rqSlotOTm. These Signals are asserted as long as a packet is validated in either the request or response queue slot 0 location. Slot 0 is the first queue slot to be used after the queue starts from reset. By counting real time with one counter and elapsed time as qualified by PPCt with another counter, the average latency of slot 0 for request or response send queues can be measured. The cmdMatch comparator is also applied to the command field of the packet in slot 0 for this signal. If the cmdMatch is false, PPCt will not be asserted even if a packet is validated in slot o. This allows the user to only measure latency of certain types of packets in the send queue; for example, cmdMatch coul be set to only match cache coherent traffic, thus giving latency for only cache coherent traffic. GS2141-0 Rev. 1.0 @ VrrESSE 1996 Communications Product Data Book Page 233 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controllsr 8.4.5 Receive Queue Reservation State The amount of time spent in one of the queue reservation states (SERVE_NA, SERVE_A, SERVE_NB, SERVE_B) can be determined by using the rsRsvPhs and rqRsvPhs signals connected to PPCl. These signals will be asserted whenever the reservation state matches the phase in extCmp[O:l]. The extMask[O:l] will also mask. off either or both bits if desired. By using a real time counter and a second elapsed time counter connected to PPCl the user can measure average time spent in a particular reservation phase, or by using extMask the average time spent in a reservation phase (SERVE_A and SERVE_B) versus a non-reservation phase (SERVE_NA and SERVE_NB). Page 234 8 VITESSE Semiconductor Corporation G52141-o Rev. 1.0 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller 9.0 Test Access Port The DataPump conforms to the IEEE Std 1149.1 Standard Test Access Port and Boundary Scan Architecture. This allows access to all the inputs and outputs of the DataPump as well as on-line scan access to the CSR support registers using scan shadow registers. Also provided is access to internal RAMs. The Test Access Port uses the pins PTCK, PTMS, NTRST, PTDI, and PTDO to perform serial shifting of data and control for testing the DataPump. The internal DataPump clocks are all connected to PTCK to perform boundary scan or RAM testing. The clocks run normally for CSR shadow register access. The DataPump registers can be read and written through JTAG while the part is running normal operation. A block diagram of the various scan chains accessible through JTAG is shown in Figure 9.1. These registers operate like dual rank registers. That is, they have a shift register part and a parallel loading register part. In the case of boundary scan, the dual rank register is specified by the IEEE std. The CSR shadow register is a single rank parallel load and shift register. For shadow register read operations the shadow register parallel loads from a selected internal CSR register and the data is then shifted out. For write operations the shadow register is shifted into and the data parallel loaded into the selected internal register. The instruction register is a dual rank register made up of the shift register and a parallel load register. The outputs of the parallel load register actually provide the instruction data 9.0.1 Test-Loglc_Reset state Test logic is disabled in this state so normal operation of the DataPump can proceed unhindered. This state is entered asynchronously when NTRST is asserted or as long as PTMS is logic 1 for 5 consecutive PTCK rising edges. This state is unaffected by NRESET. 9.0.2 Run-Tesflldle State This is the idle state between scan operations. No scan activity takes place during this state. 9.0.3 Se/ect-DR-5can State This is the initial entry state for data register scan operations. No actual operations take place during this state, but it is necessary to go through this state to do data register scan operations. 9.0.4 Capture-DR state In this state, a specific instruction register selected data scan register parallel loads from a given source. In the case of the boundary scan EXTEST instruction the boundary scan register parallel loads from the input pins (and from chip internal signals on output pins). In the case of a CSR read the internal register selected for read parallel loads into the shadow register. No shifting of data takes place in this state. 9.0.5 Shift-DR state In this state, the data register currently connected between PTDI and PTDO as defined by the instruction register is shifted one stage toward PTDO on PTCK rising edge. If PTMS remains logic D, data will continue to shift with each PTCK rising edge. 9.0.6 Exitf-DR State This is a temporary state during which no scan operations take place and no registers change value. G52141·0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 235 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Figure 9.1 : Scan Test Access Port Block Diagram --l bypass FIFO register I rl recv queue RAM register TOI ~ TOO output mux r-----. send queue RAM register rl rl rl CSR shadow register Boundary Scan register Bypass register t clocks II- control signals I Y TCK TMS lRST# Page 236 Instruction decode I Instruction register ri'iux seleet I I control signals TAP Controller State Machine t t Ob V1TESSE Semiconductor Corporation G52141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Figure 9.2 : Test Access Port State Diagram 1 Test·Logic·Reset o o 0 Run.Testlldle 1 Seleet·DR-Sean 1 Seleet·IR·Sean o Note: The value (0 or 1) shown adjacent to each state transition represents the value of TMS sampled on the rising edge of TCK. G52141·0 Rev. 1.0 ® VrrESSE 1996 Communications Product Data Book Page 237 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller 9.1 TAP Controller State Machine The TAP controller state machine is clocked by PTCK and controlled by PTMS. It is asynchronously reset by NTRST. Figure 9.2 shows the TAP controller state diagram. The various states are described below. 9.1.1 Test-Loglc_Reset State Test logic is disabled in this state so normal operation of the DataPump can proceed unhindered. This state is entered asynchronously when NTRST is asserted or as long as PTMS is logic 1 for 5 consecutive PTCK rising edges. TIii~.state is unaffected by NRESET. 9.1.2 Run-Testlldle state This is the idle state between scan operations. No scan. activity takes place during this state. 9.1.3 Se/ect-DR-8can state This is the initial entry state for data register scan operations. No actual operations take place during this state, but it is necessary to go through this state to do data register scan operations. 9.1.4 Capture-DR State In this state, a specific instruction register selected data scan register parallel loads from a given source. In the case of the. boundary scan EXTEST instruction the boundary scan register parallel loads from the input pins (and from chip internal signals on output pins). In the case of a CSR read the internal register selected for read parallel loads into the shadow register. No shifting of data takes place in this state. 9.1.5 Shift-DR State In this state, the data register currently connected between PTDI and PTOO as defined by the instruction register is shifted one stage .toward PTDO on PTCK risiIlg edge. If PTMS remains logic 0, data will continue to shift with each PTCK rising edge. . 9.1.6 Exft1-DR state This Is a temporary state during which no scan operations take place and no registers change value. 9.1.7 Pause-DR state This state allows the TAP controller to temporarily halt the shifting of data through the data register connected between PTDI and PTOO. If PTMS remains logic 0, the TAP controller will remain paused in this state. This is a temporary state during which no scan operations take place and no registers change value. 9.1.8 Exlt2-DR state This is a temporary state during which no scan operations take place and no registers change value. 9.1.9 Update-DR State In this state a specific instruction register selected data register parallel loads. In the case of the boundary scan EXTEST instruction the output pin drivers parallel load from the boundary scan chain. In the case of a CSR write instruction, the selected internal register parallel loads from the shadow register. No shifting of data takes place during this state. Page 238 8 VlTESSE Semiconductor Corporation GS2141-0 Rev. 1.0 Preliminary Data Sheet 1 GBytelSec SCI Compliant Link Controller 9.1.10 Se/ect-lR-8can State This is the initial entry state for instruction register scan operations. No actual operations take place during this state, but it is necessary to go through this state to do instruction register scan operations. 9.1.11 Capture-IR State In this state, the shift register in the instruction register is loaded with the previous instruction value on the rising edge of PTCK. The instruction register retains its previous value. 9.1.12 Shlff-IR State In this state, the shift register in the instruction register is connected between PTDI and PTDO and is shifted one stage toward PTDO on PTCK rising edge. If PTMS remains logic 0, data will continue to shift with each PTCK rising edge. The current instruction register value retains its previous value. 9.1.13 Exlt1-lR State This is a temporary state during which no scan operations take place and no registers change value. 9.1.14 Pause-/R State This state allows the TAP controller to temporarily halt the shifting of data through the instruction shift register connected between PTDI and PTDO. If PTMS remains logic 0, the TAP controller will remain paused in this state. This is a temporary state during which no scan operations take place and no registers change value. 9.1.15 ExIt2-1R State This is a temporary state during which no scan operations take place and no registers change value. 9.1.16 Update-IR State The new instruction shifted into the instruction shift register is parallel loaded into the instruction register on the rising edge ofPTCKin this state. This value becomes the currentinstruction. 9.2 TAP Controller Instructions Instructions are shifted into the instruction register using the IR (instruction register) state machine operations. The instructions supported include TAP mandatory BYPASS, SAMPLFJPRELOAD, and EXTEST. DataPump specific instructions are also included. The instruction register is 8-bits long and each instruction code (inst[7:0)) is given in hex form in Table 9.1. The shift order for inst[O: 15] is inst7 to instO. The basic instructions are listed in Table 9.1. G52141-o Rev. 1.0 8 VITESSE 1996 Communications Product Data Book Page 239 Preliminary Data Sheet 1 GByle/Sec; SCI Compliant Link Controller Table 9.1: TAP Controller Instructions .......................... .......................... •• tmiti.iUiitl)ii ••• .......................... EXTEST SAMPLFJ PRELOAD RD_STATE WR_STATE RD.-NODEID WR_NODEID RD_CLKTHRU imi 0016 01 16 05 16 0616 15 16 1616 2516 RD...ERRLOG WR...ERRLOG RDYC_CONFIG 55 16 WRYC_CONFIG 5616 RD_SQTAGO 65 16 RD_SQTAGl 75 16 RD_SQTAG2 85 16 RD_SQTAG3 95 16 BYPASS FF16 45 16 4616 HH :::::::::::::::::: io.l!$j :::::::::'" ~."·.H • '". Provides external pin and board testing. Allows sampling inputs and preloading ou1pUts wifuout affecting normal operation. Read DP_STATE register Write DP_STATE register Read DP.-NODEID register Write DP_NODEID register Read DP_CLKTHRU Read DP...ERRLOG Write DP...ERRLOG Read DPYC_CONFIG Write DPYC_CONFIG Read DP_SENDQ.TAGO Read DP_SENDQ_TAGI Read DP_SENDQ.TAG2 Read DP_SENDQ5AG3 Connects TDI lobypass register lo TOO. 9.3 BYPASS Instruction The BYPASS instruction selects the single stage BYPASS shift register to be connected between PTDI and PTDO. This allows for a minimum delay shift path through the DataPump in the Shift-DR state. Capture-DR and Update-DR have no effect during this instruction. Execution of this instruction do not affect normal DataPump operation. 9.4 CSR Register Read/Write Instructions These instructions provide shadow register access to the CSR support registers. The CSR support registers are a maximum of 32-bits in size. A 40-bit shift register (called a shadow register) is provided which is connected to PTDI and PTDO when CSR read/write instructions are loaded into the instruction register. The register read instructions parallel load data from the selected CSR register into the shadow shift register on Capture-DR The CSR register data is paralle1loaded in with bit 0 corresponding to bit 0 of the shadow register. The data is then shifted out on Shift-DR starting with bit 39. Bits 33-39 are always O. Bit 32 is the Nlbusy bit and indicates that the Node Interface is currently reading a CSR register and using the register read multiplexers. If this bit is set, the read data loaded into the shadow reg- Page 240 ® VlTESSE Semiconductor Corporation GS2141-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller ister is undefined and the JTAG CSR read must be tried again until NIbusy is observed O. The remaining bit ordering shifted out (bits 31 to 0) is the same order as specified for each CSR register in Section 4.8. The register write instructions also parallel load data from the selected register on Capture-DR the same as a register read. During Shift-DR this read data is shifted out while the data to be written is shifted in. The write data is applied to the selected register on Update-DR. The write data should be shifted in starting with 8 zeros (shadow register bits 32-39) followed by the write data starting with bit 31. The write functionality applied on Update-DR is the same as if the data were written from the NIBus with a CSR write transaction. That is, if a bit of a register is read-only, the Update-DR won't change the bit. If a bit is clear-able, it will be cleared on Update-DR if the corresponding write data bit is set to one. Finally, if the bit is write-able, that bit will take the value of the corresponding bit in the write data on Update-DR. Full specification of each register bit and its access types are given in Section 4.8. 9.5 EXTEST Instruction The EXTEST instruction allows testing of off-chip connections to the I/O and PC-board interconnections. Data at the input pins is captured in the boundary scan shift register in the Capture-DR state. Data is shifted in the boundary scan shift register in the Shift-DR state. The boundary scan output registers are parallel loaded and the outputs of the DataPump driven on the rising edge ofPTCKin the Update-DR state. 9.6 SAMPLEIPRELOAD Instruction The SAMPLFlPRELOAD instruction operates identically to the EXTEST instruction in the DataPump. 9.7 Boundary Scan Register and Ordering The boundary scan register consists of a bit for each I/O plus three extra bits which control the tristate and bi-directional outputs. These three control bits are called QTRIDPACK, QTRI6332, and QTRI310. PDATA[O:63] and PPARlTY[0:7] are bidirectional I/O and NDPACKis a tri-stateable output. Table 9.2 gives the boundary scan ordering. Signal pin TSTMD must be grounded during boundary scan testing. Signal pin PTDI connects to the head of the boundary scan list. PTDI feeds Q_TRIDPACK. Signal pin PTDO is fed from the tail of the boundary scan list. Signal PSCID015 feeds PTDO. The boundary scan ordering is as follows: PTDI ~ QTRIDPACK ~ ..... ~ PSClOOI5-+ PTDO. I/O's not sampled in the boundary scan mode are the following: PTCLK, PTMS, PTDI, NTRST, CLKHI, NCLKHI, and PTDO. G52141-0 Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 241 Preliminary Data Sheet 1 GByte/Sec SCI Compliant Link Controller Table 9.2: Boundary Scan Chain Ordering -O.S to2.6V -O.S to 4.0 V -1.0 to Vm, + 1.0V -1.0 to VDD + 1.OV TBD TBD -SSCto +12SC -6SC to +ISOC Table 11.2: Recommended Operating Conditions S~»Ib#tp.i##~~teh .... ............~i#.yt,p .... ....... VTIL Tc Supply voltage +2.0 V Supply voltage +3.3 V Operating case temperature 1.9 3.1 · · · . · m. TemrlnatlDn ",,!sialic. = 25 (2/3)*Vrr -2% VREP +O.l 0.8 -10 V VREP -O.l mA V V V @i@g~~ N@#MH . .......................... ........................... ........................... ...Sig"al~",e ...... . ........................ r~g~riit N4t@~ ........................ ......................... ......................... a stCllar: ... N .... 11l8.. ....................... :;>:a~i@if!~ Niimtki: ....................... ........................... ......................... . ......................... . s,i~iiV4",e ............. PSCIDIl5 H02 NSCID08 N02 NSCID03 U21 H03 VCC N03 PSCID03 VOl VCC H04 VCC N04 NSCID04 V02 PCMND2 H18 VCC N18 NSCIDIl3 V03 NDPSEL H19 H2O vee N19 PSCIDIl2 V04 VCC NSCIFI mo NSCIDIl2 V05 VMM H21 NSCIDI6 N21 NSCIDIll VGREF JOl PSCISO POI PSCID02 V06 V(J7 J02 PSCIDOIO P02 PSCID04 vas PPCl NINTRNI J03 NSCIDOIO P03 VCC V09 PDATA4 J04 PSCID08 P04 VCC VIO VMM JI8 PSCIFI P18 VCC Vll VMM JI9 NSCIDI5 P19 VCC V12 VMM 120 PSCIDI5 P20 PSCIDIl3 V13 PDATA17 121 PSCIDI6 P21 PSCIDIll V14 PrDO KOI NSCID06 ROI NSCIDOO V15 PSTEP K02 K03 PSCIFO NSCIDOI V16 NTRST NSCIFO R02 R03 NSCRUB V17 VTTL K04 VCC R04 NNIACK V18 VCC K18 VCC R18 PSTOP V19 TE K19 NSCID17 R19 CLKHI V20 N/C K20 PSCID17 R20 NSCIDIl5 V21 VCC K21 NSCIDI8 R21 NSCIDIl4 WOl VCC L02 NSCID07 TOI PSCIDOO W02 lPNC L03 PSCID06 T02 NSYNCRQ W03 OPNC L04 VMM T03 PCMNDI W04 NDPACK 118 VMM T04 vee W05 PRCVRSP 119 NSCIDI9 T18 VCC W06 VMM L20 PSCID18 PCKHMPYI W07 vee MOl PSCID07 T19 T20 NCLKHI W08 VMM M02 NSCID05 T21 PSCIDIl4 W09 VMM M03 PSCID05 UOI PSCIDOI WIO VCC M04 VCC U02 NNIRDY Wll PDATAll M18 VCC U03 PCMNDO W12 vee M19 M20 PSCIDllO NSCIDIlO U04 VMM VMM Wl3 Ul8 Wl4 VMM VMM M21 PSCIDI9 Ul9 PCKHMPYO W15 VCC NOI NSCID02 U20 NRESET Wl6 VTTL G52141·0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 253 Preliminary Data Sheet 1 G8yte/Sec SCI Compliant Link Controller . :~~g~.~ . ~#i#,~Ii#:: .. .. .::N.~~~i+/ ....... ........ Wl? Wl8 Wl9 W20 W2l YOl Y02 Y03 Y04 Y05 Y06 YOO Y08 YfJ) YlO Yll Page 254 , ::::::::::':::::::::::"::: PTCK PMAINfMDl CLKNI N/C vee vee PRCVREQ PSNDREQ vee NERRNI PDATAO PDATAl PDATA3 PDATA6 PPARITYO PDATAIO :~ii~ ' !:) zt) 2:lVl ~:> Vl PLL LVDS STRB C'l "'-8 60 .... ~ ~t-- ·>,Z ZU Vl ill ..... :> r:l::~ VECL STRB G52143-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 261 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit FuncUonalDescnpUon The node bypass circuit is a switch that has two basic modes of operation: NORMAL and BYPASS mode. In NORMAL mode, SCI packets are transmitted from the SCI node to a node bypass circuit and from a node bypass circuit to the SCI node. In BYPASS mode, SCI packets are transmitted from node bypass circuit to node bypass circuit. While in BYPASS mode, SCI packets may be sent to an SCI node, to the node bypass circuit, and back to the same SCI node for diagnostic checking without interfering with ringlet operation. The node bypass circuit also has two modes which control clock generation through the PLL, HALFSPD and CLKSIlL. The HALFSPD bit, when set high, allows the node bypass circuit to be run at 500MB/s instead of 1GB/s. This operation allows the chip to be compatible with a broader range of SCI systems. Whether in full speed or half speed mode, the LVDS BUS is two bytes wide and the VECL BUS is four bytes wide. The CLKSIlL allows the user to bypass the intemally generated PLL clock and use an external clock, TSTCLK, to control the LVDS STRB output. When bypassing the PLL, the externally supplied clock should be set at 500MHz regardless of the speed mode chosen. It should be noted when the PLL output clock is being selected that, to ensure proper operation, the VECL STRB or LVDS STRB must be supplied to the node bypass circuit uninterrupted. Periodic interruption of the strobe signal to the PLL will cause the PLL to lose frequency lock and result in improper circuit operation. The truth table in Table 1 details the operation of the node bypass circuit. LDATA represents data that is coming from the SCI node, and VDATA represents data that is coming from another node bypass circuit. PLL OUT represents an LVDS STRB generated by the PLL, and TSTCLK represents an LVDS STRB generated by the externally supplied clock. Finally, LSTRB represents a strobe signal from the SCI node, and VSTRB represents a strobe signal from another node bypass circuit. Table 1: Truth Table ••••••••.•••·.·····g~JltT:#(rn.##t,f ••••.•••••••• :. . •.••••••••••••••• :.:.. •• • :••••••• :• • • •~t#·P#:~#~. ..................... .......................... ................ . 1iAili.F.SPD ~ :::::::;:;::;:;:::::::: <~~BypABS~ HiH ~Bif ::::::::::::::;:; :::::::::::::: o .. ::: ................ . ... o o o o o o o o o o o Page 262 ~ ................................................................................. ~YP¥lw.~..J;Vp.$ ......................... ~.... VDATA VDATA LDATA LDATA VDATA VDATA LDATA LDATA . H1ECiBUS . PII.OUT PII.OUT PII.OUT PII.OUT TSTCLK12 TSTCLKl4 TSTCLK12 TSTCLKI4 VlTESSE Semiconductor Corporation LDATA LDATA VDATA VDATA LDATA LDATA VDATA VDATA ::STRB:: r~(:?~: STRiF .................. spifiiij .................. LSTRB LSTRB VSTRB VSTRB LSTRB LSTRB VSTRB VSTRB 250MHz 125MHz 250MHz 125MHz 250MHz 125MHz 250MHz 125MHz G52143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit Figure 1: Vitesse SCI Chipset, Typical Four Node Application using VSC7201 A and VSC7203 ,------- -- - ------ -- - ----OJ. , . Node 0 ~ (":l PC Board VSC7203 LVDS I I tj .... ~ i> - VECL VSC7203 I I I L~ - ,• i L~DS : I I ~ (":l tj I II .LVDS .... ~ Node 3 i> ! VVECL VECL/ .II I Node 1 ~ 9 s: ~ I I L~S VSC7203 VSC7203 LVDS .. I I VECL ... I !L~S I I i / ... !L~S ~ ~ s: Node 2 I .--- ----- - -------- - --- - --!. Figure 1 illustrates a typical application using the YSC7203. A 4 node ringlet is shown interconnected using YSC7203 Node Bypass Circuits. For example, in a multi-processor application, if each node contains 4 processors this configuration results in a 16 processor system. Of course this approach can be extended to a larger number by inserting additional nodes in the VECL path. G52143-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 263 Preliminary Data Sheet 1 GByteisec SCI Compliant Switch Node Bypass Circuit JTAG The DataPump conforms to the IEEE Std 1149.1 Standard Test Access Port and Boundary Scan Architecture. This allows access to all the inputs and outputs of the YSC7203. The Test Access Port uses the pins TCK, TMS, TRST, TDI, and TDO to perform serial shifting of data and control for testing the YSC7203. A block diagram of the various scan chains accessible through JTAG is shown in Figure 2. These registers operate like dual rank registers. That is, they have a shift register part and a parallel loading register part. In the case of boundary scan, the dual rank register is specified by the IEEE std. The instruction register is a dual nmk register made up of the shift register and a parallel load register. The outputs of the parallel load register actually provide the instruction data. Figure 2: Scan Test Access Port Block Diagram TOO TOI Boundary Scan Register Output· Mux Bypass Register clocks control signals mux select TCK TMS TRST# Page 264 TAP Controller State Machine e VlTESSE Semiconductor Corporation G5~143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit TAP Controller State Machine The TAP controller state machine is clocked by TCK and controlled by TMS. It is asynchronously reset by TRST. Figure 3 shows the TAP controller state diagram. The TAP controller conforms to the specifications set forth in IEEE Std. 1149.1. Figure 3: Test Access Port State Diagram 1 Test·Logic·Reset )+------------------------.... o 1 Select·DR·Scan 1 Select·IRoScan 1 o Note: The value (0 or 1) shown adjacent to each state transition represents the value of 1MS sampled on the rising edge of TCK. GS2143-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 265 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit TAP Controller Instructions Instructions are shifted into the instruction register using the IR (instruction register) state machine operations. The instructions supported include TAP mandatory BYPASS, SAMPLFlPRELOAD, and EXTEST. The instruction register is 8-bits long and each instruction code (inst[O:7] is given in hex form in Table 2. The shift order for inst[O:7] is instO to inst7. The basic instructions are listed in Table 2. Table 2: TAP Controller Instructions :::::::::::::::::::: :::::::::::::::::::::::::::::::::::::::: :::::::: >:tt;~i.:~::::~:::: EXTEST SAMPLE! PRELOAD BYPASS OOh Provides external pin and board testing. Allows sampling inputs and preloading outputs without affecting normal operation. Connects TO! to bypass register to TOO. BYPASS Instruction The BYPASS instruction selects the single stage BYPASS shift register to be connected between TOI and TOO. This allows for a minimum delay shift path through the VSC7203 in the Shift-DR state. Capture-DR and Update-DR have no effect during this instruction. Execution of this instruction does not affect normal VSC7203 operation. EXTESTlnstruction The EXTEST instruction allows testing of off-chip connections to the I/O and PC-board interconnections. Data at the input pins is captured in the boundary scan shift register in the Capture-DR state. Data is shifted in the boundary scan shift register in the Shift-DR state. The boundary scan output registers are parallel loaded and the outputs of the DataPump driven on the rising edge ofTCKin the Update-DR state. Boundary Scan Register and Ordering The boundary scan register consists of a bit for each I/O plus an extra bit which controls the capturing of output data by the boundary scan shift register during SAMPLFJPRELOAD. This bit is called ORCAPT. Table 3 on the following page gives the boundary scan ordering. SAMPLE/PRELOAD Instruction During SAMPLFJPRELOAD, inputs are registered into the boundary scan shift register in the Capture-DR state. When the ORCAPT bit is high (enabled), the outputs are registered into the boundary scan shift register as well. Otherwise, the boundary scan shift register does not load the output values when ORCAPT is low. Data is shifted in the boundary scan shift register in the Shift-DR state. The boundary scan output registers are parallel loaded and the outputs of the VSC7203 are driven on the rising edge of TCK on the Update-DR state. Page 266 e VlTESSE Semiconductor Corporation G52143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit Table 3: Boundary Scan Chain Ordering •••••• •••••••••• ORCAPT G52143-0 Rev. 1.0 ...... ............................. t,P#> . ······ ................... H· !rIi¥itf~i~ :lf~~; .¢iU;~ internal 1 BYPASS input 2 PSCISO dill output 3 PSCIFO PSCIDO[15:0] dill output diff. output 4 5-20 PSCISI PSCIFI diff. input diff. input 21 22 PSCIDI[15:0] diff. input 23-38 POCLK diff. output 39 OFLAG[1:0] output 40-41 ODXl'A[31:0] output 42-73 PINCLK FLAG[I:0] diff. input 74 input 75,76 DXl'A[31:0] input 77-108 ® V"ESSE 1996 Communications Product Data Book •... Page 267 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit AC Characteristics Table 4: VECL Port SpeclflcaUons (Over recommended operating conditions). INCLK period - full speed INCLK period - half speed VECL input rise time VECL input fall time INCLK pulse width - full speed TPER, TPER, tR fp tpw INCLK pulse-width - half speed VECL input bus setup time VECL input bus h<.lld time VECL clock to VECL output delay LVDS clock to VECL ou1pnt delay· VECL oU1pnt rise time VECL oU1pnt fall time .fpw tsu tg tcK tcK ~ fp 4 8 TBD TBD 1.5 3 -0.40 1.75 TBD .95 TBD TBD 3.3 us ns ps ps ns ns us ns ns us Table 5: LVDS p'ort Specifications (Over recommended operating conditions). •.• • .•••. ·$YiIJiii1i· .••• ••••• •••••.••••.•.•••.••..••.••. .P#T:#nlkteh·· •••• • ..•.•••••••••••..••••••••••M:ln· •• ••• ••• •••••••••Mil¥· ••.•• •••.••••.••.• iinibi·.··.· . · . . tRil ft>4 tosKEWl tosKEW2 toSKEW3 ~ fps tIsKEWl tcK02 Page 268 .. LVDS oU1pnt rise time LVDS oU1pnt fail time LVDS output differential skew LVDS ou1pnt to ou1pnt skew LVDS ou1pnt pulse distortion LVDS input rise time LVDS input fall time LVDS input to input skew PSCISO to PSCIDO and PSCIFO delay @ 300 300 300 300 1800 VITESSE Semiconductor Corporation 500 500 50 100 200 800 800 500 2200 ps ps ps ps ps ps ps ps ps G52143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit AC Timing Waveforms Figure 4: Period, Pulse Width, Rise, and Fall Time Definitions TpER -- - - -mid ----"20% tF Figure 5: Setup and Hold Time Definitions -~----------~------------clock G52143-o Rev. 1.0 8 VITESSE 1996 Communications Product Data Book Page 269 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit DC Characteristics Table 6: Power Dissipation (Overreoomm....d ..,..,..'*'11 oondnlon•• VECL oulput open oIroun, LVDS oulpul. IMM Pd Power supply current from VMM Power supply current from VTIL Total Power Dissipation _"'.'ed 2.43 0.26 6.5 with tOO oh_.) A A w Table 7: TTL Input/Output (Over recommended operating condniollS.) L:iWylilb~( ·······:iiParameterHT HHMiB yy :yy~p ···::HMa ::::::l!~i#::> ................................. :::::.:::::.::::::::::.:::::::::::::::::::::::::: ...................... . 2.4 Output high, IOH -2.4mA VOH VOL Vm Vn, 1m In, = = Output low, IoL 8 mA Input high voltage [Not 5V tolerant] Input low voltage Input high current, VIN =2.4 V Input low current, VIN =0.4 V 0.4 VTIL + 1.0 0.8 50 2.0 -1.0 1000 V V V V uA uA Table 8: VECL Input/Output (Oller l8Commendsd operating conditions. Terminafion IUIstance =50 ohms.) ......................... .................................. ........ .... .............. ...... ... ...... .... :::::~,}iiM#(HiHH:::HOOm~~ :ii:::.HHLM~ Vrr VOL VOH Vm Vn, In, 1m Page 270 Termination voltage OulpUtlow OulpUthigh Input high voltage Input low voltage Input low leakage cw:rent Input high leakage current ~ ............................................................................ . .... :H:t)p::::·:::¥.#:.:::U~iU::: -0.1 0 0.98 0.9 0 -50 VlTESSE SemlconductClr Corporation 0 0.1 0.38 1.3 1.3 0.46 V V V V V 200 IIA IIA GS2143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypa$s Circuit Table 9: LVDS Output Driver (Over recommended operating conditions.) Rload =100 ohms 25 mV Table 10: LVDS Input Receiver (Over recommended operating conditions.) ................................................................................................................................................................................ $.Y.##l·Hf~m~~;': Vrn V IL +/- VID VICM RIN G52143-0 Rev. 1.0 Input voltage high Input voltage low Input differential voltage •••.•••••••• HH¢iiM.@j~FMt.t ·.HM#. ···ttiii~ Vm= l00mV 100 2200 mV Vm=l00mV 0 2100 mV 100 500 mV Input voltage common mode Vm=VIDMIN Vm=VIDMAX 50 2150 250 1950 Input impedance o $igit'~/lIial.ll~ ..•............................ PJllNumbe'··· ............................. . ................................... A03 AA02 AA03 BOI B20 CO2 COS D04 DOS D17 018 F03 G02 ROO R18 R19 T19 T20 T21 U19 U21 VOS V18 V19 V20 V21 WOS YOI Y02 Y06 Y16 E04 E18 U04 U18 019 B21 NSCIDIO NSCIDIl NSCIDIlO NSCIDI11 NSCIDI12 NSCIDI13 NSCIDI14 NSCIDI15 NSCIDI2 NSCIDI3 NSCIDI4 NSCIDI5 NSCIDI6 NSCIDI7 NSCIDI8 NSCIDI9 NSCIDOO NSCIDOI NSCIDOI0 NSCIDOll NSCID012 NSCID013 NSCID014 NSCIDOlS NSCID02 NSCID03 NSCID04 NSCIDOS NSCID06 NSCID07 NSCID08 NSCID09 NSCIFI NSClFO NSCISI NSCISO ODATAO VITESSE 1996 Communications Product Data Book R04 R03 K04 D02 H03 POI J02 DOl POl P04 POI NOI M03 MOl 104 F02 AA20 Y21 Y13 Y04 W09 W08 AA09 AA04 W15 AA19 W19 Y17 AA15 Y14 Wll AA06 L03 YI0 K02 AA12 A04 Page2n Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit :: Pin ................. NumIMr ::: L$/~~OI.a.JjJ~::: L: pi~ N:~@j"'< .::$ig~Uti~""~ : .: )i~iiJ N.lI/;j~~h • ::::~~~~~m.,:::: .......... , ODATAI ODATAIO ODATAII ODATAl2 ODATAl3 ODATAl4 ODATAls ODATA16 ODATAl7 ODATAl8 ODATAl9 ODATA2 ODATA20 ODATA21 ODATA22 ODATA23 ODATA24 ODATA25 ODATA26 ODATA27 ODATA28 ODATA29 ODATA3 ODATA30 ODATA31 ODATA4 ODATAS ODATA6 ODATA7 ODATA8 ODATA9 OFLAGO OFLAGI PINCLK POCLK PSCIDIO PSCIDIl PSCIDI10 PSCIDI11 Page 278 B04 BOO A09 AIO BIO Cll Bll A12 Bl2 Cl3 Bl3 BOs Al3 Bl4 Cl4 CIS Als A16 B16 Cl7 Bl7 Al8 A06 Bl8 C19 B06 PSCIDI12 PSCIDI13 PSCIDI14 PSCIDI1s PSCIDI2 PSCIDI3 PSCIDI4 PSCIDIS PSCIDI6 PSCIDI7 PSCIDI8 PSCIDI9 PSCIDOO PSCIDOI PSCIDOI0 PSCIDOll PSCID012 PSCID013 PSCID014 PSCIDOls PSCID02 PSCID03 PSCID04 PSCIDOs PSCID06 PSCID07 PSCID08 PSCID09 PSCIFI PSCIFO PSCISI PSCISO RESET TCK TbI C07 A07 BOS COS COO A19 A20 D20 CZO T02 TOI JOI roo TMS lRST TSTCLK D03' @ H04 G03 HOI BOO N04 P03 N02 M04 M02 L04 H02 G04 Y20 W20 W13 YOs Y09 Y08 AAIO WOO AA18 W17 V17 Yl8 AAl6 W14 Y12 AA07 KOI Yll K03 AA13 T03 UOI V02 W03 VOl U03 B02 VITESSE Semiconductor Corporation vee vee vee vee vee vee vee vee vee vee vee vee vee vee VCC vee vee vee vee vee vee VCC vee vee vee vee vee VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM VMM D06 D07 D08 D10 Dl2 D14 D1s D16 FOs P17 HOs H17 L02 L20 POS P17 TOS T17 uos V06 V07 V08 VIO V12 V14 VIS V16 AOs A08 All Al4 A17 A21 AAOI AAOs AAOS AAll AAl4 AA17 G52143-0 Rev. 1.0 Preliminary Data Sheet G52143-0 Rev. 1.0 1 GByle/sec SCI Compliant Switch Node Bypass Circuit @ VrrESSE 1996 Communications Product Data Book Page 279 Preliminary Data Sheet 1 G8yte/sec SCI Compliant Switch Node Bypass Circuit Package Information [IDQI TOP VlEW 1\ I I I I I ----- ----- ..I I I I I I I I I \ V-- ----- ~ ~ I I I I /' DIE CAVITY :::-... BALLA! / NOTCH ./ 16.01 " / SEATING PLANE SIDE VIEW 25.40 r::IEJ TYP 000000000 000000000 0000000000 000000000 000000 0 0000 0000 0000 00000 0000 1.93 :1:0.17 000000 000 0000000000 0000000000+----+ 0000000000+----+ o 000000 00000 00000 88888 00000 00000 0000 00000 00000 0000 00000 00000 00000 0000 00000 00000 0 o 000000 000000000 0000000000 0000000000 0000000000 000000000 0000000000 BOTI'OMVIEW All dimeMUms in millimeters Page 280 e VlTESSE Semiconductor Corporation G52143-0 Rev. 1.0 Preliminary Data Sheet 1 GByte/sec SCI Compliant Switch Node Bypass Circuit Ordering Information The order number for this product is formed by a combination of the device number and package type. VSC72XX T~ DeviceType _ _ _ _ _ _ _...JI VSC7203 - 1 GBls Node Bypass Circutt Package Type - - - - - - - - - - - - ' TN: 301 Pin BGA Package, 27mm Body Notice This document contains information on products that are in the preproduction phase of development. The information contained in this document is based on test results and initial product characterization. Characteristic data and other specifications are subject to change without notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing orders. Warning Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent of the appropriate Vitesse officer is prohibited. GS2143-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 281 1 GByte/sec SCI Compliant Switch Node Bypass Circuit Page 282 , @ VlTESSE Semiconductor Corporation Preliminary Data Sheet G52143-0 Rev. 1.0 VITESSE Preliminary Datasheet PhotodetectorlTransimpeciance Amplifier Family for Optical Communication Features • Integrated PhotodetectorlTransimpedance Amplifier Family Optimized for High Speed Optical Communications Applications • High Bandwidth • Integrated AGC • Large Optically Active Area • Fibre Channel Compatible Speed: [1/4 &112 Speed] • Single 5V Power Supply VSC7802 VSC7805 114 Speed: 266 Mb/s 112 Speed: 531 Mb/s • Low Input Noise Equivalent Power 300 650 500 100 0.75 1.0 General Description The VSC7802lVSC7805 series of integrated Photodetector/Transimpedance Amplifiers provide a highly integrated solution for converting light from a fiber optic communications channel into a differential output voltage. The benefits of Vitesse Semiconductor's Gallium Arsenide H-GaAs-llI process are fully utilized to provide very high bandwidth and low noise in a product with a large optically active area for easy alignment. The sensitivity, duty cycle distortion and jitter meet or exceed all Fibre Channel application requirements. Parts are available in either die form or in Hat-windowed packages. By using an integrated MSM (Metal-Semiconductor-Metal) photodetector with an integrated transimpedance amplifier, the input capacitance is lowered which allows for a larger optically active area than in discrete photodetectors. Integration also allows superior tracking over process, temperature and voltage between the photodetector and the amplifier, resulting in higher performance. These parts can easily be used in developing Fibre Channel Electro-Optic Receivers which exhibit very high performance and ease of use. VSC7S02l7S05 Block Diagram Photodetectorffransimpedance Amplifier +5V DO ,-----1+ 500. D1 500. Both DO and Dl have an internal 500. termination resistor to GND G52088-0 Rev. 1.5 ® VITESSE 1996 Communications Product Data Book Page 283 Preliminary Datasheet PhotodetectorlTransimpedance Amplifier Family for Optical.Communication Table 1: Electro-Optical Specifications ::$1",i1!1iT :: vee I.e PSRR A. Fe :::~~ ............ ...................... ::Piirl#. :HvttI : Ti6ip;: Supply Voltage Supply Current Power Supply Rejection Ratio Wavelength Low Frequency Cutoff BW Optical Modulation Bandwidth Dr Dynamic Range S Sensitivity 4.5 13 770 7802 7805 7802 7805 7802 7805 Rd Differential Responsivity 1.2 Output Bias Voltage Bias Offset Voltage 1.0 NEPo . Input Noise Equivalent Power Vno 0u1put Noise Voltage DCD Duty Cycle Distortion Tr •Tf lout PDJ Output Rise & Fall Time .e 40 7802 7805 7802 7805 7802 7805 V mA 850 1.8 300 650 f= 1 to 40 MHz (Jnclul1es External Filter) run MHz -3db.P=-17 dBm@50MHz MHz -3db. P=-17dBm@50MHz db dBm 25 60 n 0.25 0.8 V mV/lJ.V 2.5 150 0.75 1.0 0.6 1.2 8 1300 600 2.5 Optically Active Area Page 284 840 7802 7805 7802 7805 Output Drive Current Pattern Dependent Jitter 5.5 db 150 350 24.2 22.9 -22.8 -21.5 Vd Vdc AVdc :.... ·: .... ComiitiOmH:::········· TMI#.l .:UnttS ............... : ......................................... 35 Single Ended Ou1put Impedance Differential Output Voltage Ro 5.0 30 8 170 100 500 100 VrrESSE Semiconductor Corporation 266Mb1s 531 Mbls P= 1.4dBm. R = lOOn differential ~oacl=l00n P= -17 dBm@50MHz V mV IJ.Wrms BW=IGHz P=OmW mVrms BW=IGHz P=OmW % P= 1.4dBm psec. 20-80% P= l.4dBm mA Normal Test Conditions 500 psec. P = -5 dBm±-10% Voltage Window ~ Diameter G52088-0 Rev. 1.5 Preliminary Datasheet PhotodetectorlTransimpeciance Amplifier Family for Optical Communication Table 2: Absolute Maximum Ratings •· •••• sJl~#i •••••••• ·••••••••••••••• ···· • • f~~~r, •••..•••••.••••.••.••••••••••••. Vee T stg (1) Power Supply Storage Temperature -40·C to +85·C H.tg (1) Storage Humidity Top (1) Operating Temperature 5 to 95 %R.R (Including Condensation) 0°to70·C Operating Humidity 8 to 80%R.R (Excluding Condensation) H.,p (1) Pine S (1) 6V Incident Optical Power +3dBm Impact Shock 500 G. Half Sine Wave Pulse Duratiool +/-0.5 ms 3 Blows in each direction Vibratioo 20> 2000 > 20 Hz, 10 Minutes lOG. Peak Acceleration 4 Complete Cycles, 3 Perpendicular Axes (1) These specifications are for the 5.6mm package only. G5208S-o Rev. 1.5 @ VITESSE 1996 Communications Product Data Book Page 285 Preliminary Datasheet PhotodetectorlTransimpedance Amplifier Family for Optical Communication Figure 1: MSM Spectral Response Ii' 1 ~ .5- ,to :E l ! 750 700 900 850 800 Wavelenglh Inm) Figure 2: DIE IDD vs Temperature 29.5 29 1 A ,g 28.5 28 27.5 27 0 10 20 25 30 40 50 60 75 'emple) Page 286 e. VITESSE Semiconductor Corporation G52088-0 Rev. 1.5 Preliminary Datasheet PhotodetectorlTransimpedance Amplifier Family for Optical Communication Figure 3: Mechanical Specifications (Individual Die) (4X\ 0.355 (4X\ 0.055 +0.5 ~)0.11 (l) 0 d "- "" (l) Ol LO d C') C\I ~ Y\ d §: ~ §: 0 1,- ~ LO CX! ~ ~ ~ G~ ~L- \ (l) -.t LO d d ~ 00 x~ g rh 4J 0.055 DO Dlr1 4- 0.42 ~ q ~ 0 d §: §: 0.84 0.95 000.05 [ ~ 0 VSC7802DIE Note: All measurements in mm G52088-0 Rev. 1.5 ® VITESSE 1996 Communications Product Data Book Page 287 Preliminary Datasheet PhotodetectorlTransimpedance Amplifier Family for Optical Communication Figure 4: Mechanical SpecHications (Individual Die) (4X) 0.355 (4X) 0.055 «110.1 (4X) 0.11 &l 0 Ol .... C\I ~ 0 ... Ol ('I) ('I) ~ ci ci It) ('I) r: ,... ....C'! .... C\I ci ~ t! vL GND ~ ~ ~ 0 ci ,.... ,... ""'" ci ~ ~ r~ "'\ \.. / ,.... ('I) co 0 ~ C\I ci +5 t-' ci g g ci I-h H-J 0.055 :'- rh D14J DO 0.42 0.84 0.95 VSC7805D/E Note: AU measurements in mm Page 288 :to.05 ~ VrrESSE Semiconductor Corporation G520BB"() Rev. 1.5 Preliminary Datasheet PhotodetectorlTransimpedance Amplifier Family for Optical Communication Figure 5: Mechanical Package Specifications (5.6 mm Package) +sv DO 01 .s E SECTlONB-B SCALE NONE 0.es.,O.04 DETECTOR PLANE 8 2000 > 20 Hz, 10 Minutes 10 G. Peak Acceleration 4 Complete Cycles, 3 Petpendicular Axes Vibration (1) These specifications are for the 5.6mm package only. Figure 1: Amplitude vs. Frequency 10 6.795 ~14M ~ - '-.,. z 3 '" ""'" --...... ~ "'" 1 999.700 1 000.150 Frequency (MHz) Frequency response of VSC781 OMl upper 3db frequency is meaauerrl with re.pect to response at 50 MHz G52145·0. Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 297 Data Sheet Photodetector/Transimpedance Amplifier Family for Optical Communication Figure 2: MSM Spectral Response 'ii r---- 1 i2 0 a. ! 700 750 800 850 900 W_elenglh (nm) Figure 3: DIE IDD vs. Temperature 27·~--~--~---+--~----~--+---~--~ o 10 20 25 30 40 75 Temp IC) Figure 4: DIE Bandwidth vs. Temperature 1140 1130 i ~ 1120 ·······················__·········1 1110 1 1100 I: 1090 II .. 1080 1070 10110 +---I~-+---+---+----+---+---t----I Temp (C) Page 298 .§. 1.4 1.2 0.8 8. 0.6 0.4 02 J -..--~~-.....--+--~- 1.8 .~ :!c .....--l 1.8:--+--'" 0~--~10~--~~----~+---~30~--+~----~+---~~~~n Temple) Figure 6: DIE PRBS Jitter vs. Temperature ....................................................... ~~ :~ I-= ~ 50 40 ... J: 10 O~--~--~---+---~--~---+--~-~ W ~ ~ ~ ~ ~ ro ~ 00 Temple) Figure 7: DIE Duty Cycle D1stClrt!on vs. Temperature 1.6 ............................................................. :,a ......................:..a;.: ........ .. ...... 1.4~ 1.2 g CI l!: 0.8 0.6 0.4 0.2 10 ~ ~ Temple) G52145-o. Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 299 PhotodetectorlTransimpedance Amplifier Family for Optical Communication Data Sheet Figure 8: Eye Diagram Page 300 @ VITESSE Semiconductor Corporation G52145-0, Rev. 1.0 Data Sheet PhotodetectorlTransimpedance Amplifier Family for Optical Communication Figure 9: Mechanical SpecHlcaUons (Individual Die) (4X) 0365 (4X) 0.055 jlO.1 ~ (6X)0.11 0.42 La t') ~ ~ .... [ ~ ci 8P '\\ ..,. i!! ~ to -.t; .... ....~ to C'! .... DOH 01 [\ I': .... .... 0 ci X- X ~ -l- ~0GNott ~ ...I' GNO ct=rr 1~Ft=t ' - - .... La 0 ci 0 ci >.-C':! 0 X~ ..... '- I-' +5V La ci ~ 0 I (2X) 0.247 (2X) 0.~2~~ 2~ 0.18 0.05 0.05 0.84 0.94 1.04 .0.05 G52145-0. Rev. 1.0 n the board, male on the cable) with TX+ on pin I, TX- on pin 6, RX+ on pin 5 and RX- on pin 9. The shield of the cable is connected to chassis ground on both ends to provide a low impedance grounded shield. A cost effective duplex twinax cable which has an effective shielding scheme that reduces emissions to the point that systems pass FCC-Band CISPR EMI levels is available from W.L.Gore. The typical circuit for this application is shown below. Termination Example; 150 Ohm Differential 0B-9 OB-9 C3 Tx 150 Ohm Twinax R3 C4 Rx R1=R2=267 ohms, 1% R3=150 ohms, 1% C1=C2=C3=C4=0.01uF Fiber Optic Module Termination Many customers wish to use Fibre Channel over fiber optic cable for increased distance, reduced EMI or other reasons. In general, this is a 50 ohm application, however, each vendor of fiber optic transceivers may have slightly unique interfacing requirements so it is recommended that the user contact the vendor prior to design. For the purposes of this example, a circuit is described which interfaces to Finisar's FTR-8510 and Methode's MTR-8510 800nm transceiver module. No AC-coupling capacitors are required on the transmit side so only 182 ohm pull down resistors are provided. This application example assumes short traces (less than 2 inches) so that termination resistors are not required at the end of the traces on the transmit side. On the receive side, the normal 51.1 ohm and AC-coupling capacitor are provided. G52025-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 313 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips Termination Example: Fiber Optic Transceiver Rx 22 Tx OlE Module ..,....c;-----.--....::...-rrx- Rl=R2=182 ohms, 1% el=CZ=O.OluF R3,R4=51.1ohms, 1% Preventing Oscillations Since a link can be disconnected or a transmitter can be disabled, there are times when the receiver's inputs might not carry a valid signal. In the absence of a signal, both inputs of the receiver (RX+IRX-) will be at their internally determined bias points which are, by design, identical. When a differential input buffer's inputs are identical the buffer is susceptible to oscillations which could cause noise within the receiver. Vitesse's input buffers do not oscillate normally. however, in a noisy environment oscillations may occur. To prevent this problem, a Thevenin-equivalent resistor pair is used to both terminate the transmission line and to provide a small DC offset to the receiver. This offset is kept as low as possible so as not to introduce an offset under normal conditions which might add to the input jitter seen by the receiver. An example of this is shown below with values for both 50 ohm and 75 ohm impedance applications. Termination Example; Preventing Oscillation Rx+ ell Rx- CZI RI=R4=97.6 ohms, 1% R2=R3=I02 ohms, 1% for 50 ohm impedance, [72mV offset] RI=R4=147 ohms, 1% R2=R3=154 ohms, 1% for 75 ohm impedance, [76mV offset] el=CZ=O.OluF Page 314 8 VlTESSE Semiconductor Corporation G52025-0 Rev. 1.0 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips Unused Inputs In many applications the receiver inputs might not be used. In this situation, it is important to terminate the inputs so that they will not oscillate. In a single-ended application, the unused receiver input is AC-coupled to ground to reduce noise susceptibility but keep the input at the internal bias point. If the differential inputs are not used then the circuit shown below is recommended. A variety of useful circuits may be used for this purpose but the two considerations are: provide a DC-offset and provide a low-impedance noise attenuation path. In the circuit shown, 47 Kohm external resistors are added in parallel with the internal 3 Kohm pair. This results in a SO m V offset. The capacitor across the inputs provides a low-impedance path to reduce noise susceptibility. Termination Example: Unused Inputs Vdd Rl +sOmv q = ·sOmv Rx R2 Rl=R2=47K ohms, 5% Cl=O.OluF Power Supply Considerations Generating 3.3V - Linear Regulator All ofVitesse's Fibre Channel transmitters and receivers operate with a 3.3V +/- S% power supply. Although the migration to 3.3V logic power supplies is underway, many system do not have an available 3.3V supply for use in powering the transmitter/receivers. The easiest, smallest and cheapest way to convert from a SV power supply to a 3.3V level is through the use of a linear regulator. Converting from a + 12V supply to a 3.3V supply is more difficult due to the additional power dissipation in the regulator which must be handled correctly. At SV+/- 10%, the power dissipated in the regulator is calculated as (S.2SV - 3.3V)*I4d(max). One nice feature of a linear regulator is that it provides a very quiet output which is isolated from the noise on the SV supply. Since signal jitter is sensitive to power supply noise, the clean outputs of the linear regulator contribute to improved signal quality. A readily available, multiple-sourced linear regulator is the Linear Technology LTl086CM-3.3 which is a fixed, 3.3V output voltage regulator in a surface mounted, DD-Pak package that provides up to 1.S A output current. This is more than adequate to power a transmitter/receiver pair. A simple application circuit is shown below. Minimum values of input and output capacitance are required to provide stability to the regulator. Additional bypass capacitors must be added for additional power supply filtering at the pins of the chip. Similar linear regulators with different current limits are the LTll17CST-3.3 (800mA, SOT-223) and the LT1S86CM-3.3 (4A, TO-220) both from Linear Technology. G52025-0 Rev. 1.0 @ VlTESSE 1996 Communications Product Data Book Page 315 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips SV to 3.3V Conversion using a Linear Regulator LT1086 CM-3.3 IN 5V----r----11 10UFi ADJ OUT I I 10uFt l,( 3.3V ~O.1UF Generating 3.3V - DCIDC Converter The limitation of a linear regulator is that it is not efficient so heat is generated. In applications where excessive heat is not acceptable, a DC/DC Converter may be used to convert either the 5V or 12V supplies into a 3.3V supply. The DCIDC converters available for the current levels needed in this application have excellent efficiency, between 85% and 95% which reduces heat generation. However, the DC/DC converters are more expensive, require more real estate, need several components, are not trivial to use and add noise to the 3.3V supply. The noise is a concern since power supply noise will couple into the PLL circuits and buffers of the transmitter and receiver thereby increasing jitter generation in the transmitter and reducing jitter tolerance in the receiver. If a DCIDC converter is used, extra care should be taken to reduce output noise. An example of a DCIDC Converter which is appropriate for powering a transmitter/receiver is the Linear Technology, LT1256 1.5A part. For current levels under 450 mA, an LT 1574CS-3.3 is recommended. The DC! DC converter circuit is not shown here since these complicated parts have excellent application notes provided by the manufacturer. Bypassing The method in which bypass capacitors are used to filter the power supply to the transmitter and receiver has a significant impact upon signal quality. First, it is mandatory that the design include a power plane for V ss (Ground) which is at least 1 oz. copper. Secondly, a similar power plane for Vdd (3.3V) is strongly recommended. To reduce inductance, vias used to connect to these planes should not include thermal cut-outs similar to those found on VddlVss connections to thru-hole components. It is strongly suggested that each power and ground pin be supplied from their own vias. Bypass capacitors are more effective when located on the same side of the PCB as the transmitter/receiver. Of course, the capacitors MUST be located as closely as possible to the V dd and V ss pins of the chips. Furthermore, it is recommended that the capacitor be located between the pin and the via to the plane. A picture showing the preferred method for the layout of the bypassing capacitors is shown below. Since Vitesse's transmitters and receivers have roughly constant power supply current there is no need. for. exotic bypassing methods (i.e. two capacitors in parallel aimed at the Switching frequency of the internal circuit). It is also recommended that the power and ground planes remain intact rather than attempting to steer current paths through sculpted planes. Most customers who have tried to isolate the planes for the transmitters and receivers usually produce more noise rather than reduce noise. Page 316 @VITESSE Semiconductor Corporation G52025'O Rev. 1.0 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips Bypassing Layout Example TransmitterlReceiver Chip All of the transmitter/receivers have internal PLLs which are powered from separate supply pins usually called Vdda/Vssa where the "an denotes analog. These pins are particularly sensitive to noise so additional care must be taken to filter out noise. It is recommended thatVdd pass through a ferrite bead (i.e. TDK CB50-1206) to a bypass capacitor (at least one O.luF) and the power pin. The layout shown above indicates the preferred method for layout of this circuit. Layout Considerations When implementing a 1 Gb/s serial communications link the importance of the layout cannot be overstressed. However, following general, simple-to-use guidelines will ensure success and prove easier than most designers anticipate. The prioritization of signals is as follows: High Speed Serial I/O lines REFCLK traces Power Supplies & Bypass Capacitors Control Signals Data Busses Careful placement of components and the use of passives on both the top and bottom side will generally ensure optimal layout. As mentioned previously, a solid ground and power plane are quite useful in distributing clean power. G52025-0 Rev. 1.0 <10 VlTESSE 1996 Communications Product Data Book Page 317 1.0625 Gbits/sec Fibre Channel Physical Layer Chips Design Guide High Speed Serial VO Layout Considerations These signals contain digital data at frequencies between 106.25 to 531.125 MHz and require excellent frequency and phase response up to at least the 3rd harmonic, if not the 7th harmonic. Improved signal quality and longer practical transmission distances will result if the designer follows the general rules below: • Keep traces as short as possible. Initial component placement should be very carefully considered. • The impedance of the traces must match that of the termination resistors, connectors and cable in order to reduce reflections due to impedance mismatches. • Impedance matching termination resistors (i.e. 51.1, 75 or 150 ohm) should be located as close to the input pin of the receiver as possible in order to minimize stub length. Since an AC-coupling capacitor is often inserted between the pin and the termination resistor, this is sometimes difficult to optimize. • Differential impedance must be maintained in a 150 ohm differential application. Routing two 75 ohm traces is NOT adequate. The two traces must be separated by enough distance to maintain 150 ohm differential impedance. A good rule of thumb is that the trace separation should be at least 2.5 times the trace width. • When routing differential pairs, keep the trace length identical between the two traces. Differences in trace lengths translate directly into signal skew. When separations occur, the differential impedance may be affected so take care when this is done. • Keep differential pair traces on the same side of the PCB to minimize impedance discontinuities. • Place any impedance discontinuities close to the transmitter or receiver and locate them together. This will minimize their impact on signal quality. • Eliminate/reduce stub lengths. • Reduce, if not eliminate, vias to minimize impedance discontinuities. • Use rounded comers rather than 90 or 45 degree comers. • Keep signal traces far from other signals which might capacitively couple noise into the signals. This includes the other trace of a differential pair. • Do not route digital signals from other circuits across the area of the transmitter and receiver. • Do not cut up the power or ground planes in an effort to steer current paths. This usually produces more noise, not less. Page 318 e VlTES$E Semiconductor Corporation GS202S-0 Rev. 1.0 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips REFCLK Layout Considerations The most difficult issue with regard to the REFCLK is that the signal goes to multiple inputs which all require an extremely clean clock with fast edges. This becomes a clock distribution challenge. Of course from an emissions point of view, the goal is to eliminate the high frequency harmonics in order to reduce radiated emissions. So a system developer may have contradictory goals requiring some compromise position. One scheme used successfully in chipsets which require REFCLK only to the transmitter and receiver is to place the oscillator near the mid point between the two chips. Clock traces for each chip would then be routed from the oscillator outward to the chips with equal length traces. Daisy chaining bas also been used successfully however the signal quality at the chip in the middle of the trace is somewhat difficult to optimize. A 10 or 33 ohm series resistor located at the oscillator can help but not eliminate this problem. Power Supply Layout Considerations These issues have been discussed previously and will not be detailed here. VlaS used to connect the power planes to the Vdd and Vss pins of the chips should be at least 0.010 inches in diameter, preferably with no thermal relief, preferable plated closed with copper or solder. Also the via should be located on the opposite side of the bypass capacitor from the pin. Control Signal Layout Considerations There are no time-critical control signals on the transmitters/receivers. However it is important to route controllines to the chips in such a way as to avoid cross-talk and noise injection. Data Bus Layout Considerations The problem with the data busses is that there are a lot of signals in a small area. The only consideration here is to keep the traces roughly the same length as the clock used to latch them so that trace length differences do not reduce the setuplhold times of the Chips. Conclusion Following the general guidelines described in this design guide will help ensure that customers integrating Fibre Channel components experience first-time success. You are encouraged to contact your local Field Applications Engineer or the Application Engineering Department at Vitesse to discuss any questions and concerns you may have. Vitesse will be happy to work with customers in any way to promote the success of their designs including schematic and layout reviews. G52025-0 Rev. 1.0 4& V1TESSE 1996 Communications Product Data Book Page 319 Design Guide 1.0625 Gbits/sec Fibre Channel Physical Layer Chips ComponentSupplierLmt Below is a list of vendors who supplY components of interest to Fibre Channel customers. Where applicable, a part number and description has been provided for key components required for specific applications. Copper Cabl. Anembn •• AMP (800)52A·MPS2 High Frequency Coax, Twinx & Quad Cable Assemblies Berg (717.764-7200 Cable Assemblies 'frampeterBleetronics (818)707·2020 Coaxial Cable Assemblies W.L.Gore (302)368-2575 Quad Cable, PIN FCNl008·xx where xx is distance in meters Connectors AMP (8oo)52A·MP52 RF, Coax, DB·9 & Fibre Oumnel specific (HSSDC) connectors. B.F.Johnson (800)247·8256 RF, Coaxial COlUlectors Samtec (800)726-8329 "GLM" connector MOLC.120-01·P.Q-(LC) on the module FOLC·120·01·P·Q-(LC) on motherboard Fiber Optic ModulM AMPl4'tel (8oo)52A·MP52 GLM Modules and OlE Modules BCP (407)984-3671 51TThmsmitter & 51R Receiver Finisar (415)691-4000 ObIs OlE Modules at 800nm, FIR· SS 10 Ferce B1ectronics (703)382.0462 2684TThmsmitter and 2684RReceiver Fujikura Teclm.ology (408)748·6991 GIM Modules and OlE Modules Methode Electronics (708)867·9600 ObIs transceivers at 800nm. MTR·8510. Also GLM Modules Fiber Optic Cable 3M Fiber Optics (908)544-9119 AlcoaJFnjikura (800)866-3953 Methode Blectronics (800)323-6858 Magnetlce Collcraft (800)322-2654 Thmsfoouers fer Line interfacing 'Thclmitrol (215)426-9105 Active and Passive EqualizerlBuffers Osclllato.. Connot·Winfteld (708)851-4722 ICWorIcs (408)922-0202 W42C26 Clock Generator Motorola Seulicoo.ductor (800)441.2447 MC88915FN·loo I'lL Clock Doubler Pletrooics (206)776-1880 A variety of oscillators, T..t Equipment Anoot (415)322-5322 A Fibre Channel monitor!protocol analyzer, Finisar (415)691·4000 A family of Fibre Channel analyzer and monitors. Gadzoox Microsystems (408)866-9336 A serial data generator for receiver characterization. Hewlett Packard (408)435·7400 A variety of oscilloscopes, spectrum analyzers ... I·tecll (612)941·5905 A Fibre Oumnel emulator P_ Prctoco1lXyrate.x (714)476-1916 A Fibre Oumnel tester for Arbitrated Loop. 'Thlctronix (503)627·7111 A variety of oscilloscopes, spectrum analyzers... Wavetet (800)854-2708 Jitter analyzer. Page 320 . @VlTESSESemiconductorCorporation G52025-0 Rev. 1.0 Product Summary :0: ::: VSSOO4l800S 4:1 mux - :4 dcmux chipset with up to 2.5 Gb/s perfonnance. Ideal for high speed instrumentation and test equipment, fiber optic communication, LANs, computer-tocomputer interfaces. VSS02118022 SONEf Compatible 8:1 mux - I:S dcmux chipset with up to 2.5 Gbls performance. Incorporates SONET frame detection and recovery circuitry and is compatible with SONEf STS-3 through STS-48 applications. VSCS02318024 2.48 Gbls ATMiSONETISDH STM-16ISTS48 MuxlDemux and Section Terminator IC chipset Incorporates SONET/SDH frame generation, detection and recovery. Ideal for high performance ATM physical layers, SONEf/SDH lransmission systems, digitalvideo distribution and SONET/SDH test equipment. VSCS02318024EV (Data Sheet in Development) The VSCS023NSCS024 Evaluation Board provides users the ability to evaluate the VSCS023NSCS024 devices and perform interoperability testing with four PM5355 SI UNI-622 devices. The board is self contained and designed to allow 2.5 Gbls serial connections for interfacing to SONET or SDH test equipment allowing full compliance and error rate tests to be performed. VSS06118062 16:1 mux -1:16 demux chipset with up to 2.5 Gbls performance. Compatible with SONEf STS-3 through STS-48 applications. VSCS063 A 2.5 Gb/s, 16:1 multiplexer designed for STM-I6/STS-48 datarates atlow power dissipation. ® VlTESSE 1996 Communications Product Data Book Serial Data up to 2.S Gbls ECL lOOK Compatible Parallel Data I/O Single ECL Power Supply: VEE = -5.2 V I.S W Power Dissipation (fyp.) 28-pin Ceramic LDCC Package Serial Data up to 2.5 Gbls ECL lOOK Compatible Parallel Data I/O Standard ECL Power Supplies: VEE = -5.2 V, VTT=-2.0V 2.2 WPower Dissipation (fyp.) 52-pin Ceramic LDCC Package Byte Interleaves FourSTS-I21STM-4Data Slreamsto One STS-48/STM-16 Serial Slream Byte De-interleaves one STS-48/STM-16 Serial Slream into Four STS-I21STM-4 Data Slreams Supports OC48 and OC-48c Modes Performs Frame Synchronous Scrambling and Descrambling Provides Facilities and Equipment Loopbacks LOS Input and LOF Declaration Interfaces with PMCSierra's PM531215355 192 TBGA Package 2.5 Gbls Operation Includes Four PM5355 SIUNI-622 Devices for Inter ability Testing F1eX::y to Evaluate the VSCS02318024 in Various Operational Modes . . SMA Connections for High Speed Characterization Foo4prints Built in to Add Optic Modules Serial Connections for Interfacing to SONETISDH Test Equipment Serial Data up to 2.5 Gbls ECL lOOK Compatible Parallel Data I/O Standard ECL Power Supplies: VEE = -5.2 V. VTT=-2.0V 1.2 W Power Dissipation (fyp.) 52-pin Ceramic LDCC Package Serial Data Up to 2.5 Gbls Internal PLL for Uock Synthesis with 155.52 MHz Reference Uock Frequency ECL lOOK Compatible Parallel Data 110 Standard ECL Power Supplies: VEE = -5.2 V. VTT=-2.0V 2.SW (max) Power Dissipation 52-pin PQPP Package Page 321 Product Summary ::::: VSCS07118072 10 Obits/sec 16-bit MuxlDem.ux chipset for STS-192 and STM-64 applications. VSCSI0118102 Single channel (8101) and eight channel (8102) digital clock recoveryunit at 155 MbI s (STS-3). Combines the best ofPLL-based CRUs and run-length tolerant VOW-based CRUs. VSCSll0 ATMISONETISDH 1551622 Mbls tt'ansceiver. integrating high speed clock generation with 8 bit mwiJdem.uxing including frame detection and recovery. Ideal solution for ATM physica11ayers and SONET/SDH system. applications. The VSC8110 evaluatiOIl boafd provides VSCSll0EV VSCSlll Page 322 users the ability to evaluate the VSCSII 0 device and perform interoperability testing with the PM5312 STI'X device. The board is self contained and includes DIP switches to exercise the various modes on the VSCSII0 device. The board provides high speed serial connections for interfacing to SONET or SDH test equipment allowing full compliance and error rate tests to be performed. Low power. single power supply KfMl SONET/SDH 1551622 Mbls Transceiver MuxIDemux with integrated clock generation. Incorporates SONETISDH frame detectiOll and recovery. Ideal for KfM physica1layers and SONET/SDH systems. ::: Serial Data Up to 10 Gb/s ECL lOOK Compatible Parallel Data YO Standard ECL Power Supplies VEE = -5.2Y, VTT=-2.0V Single/Octal Otannel Clock Recovery Unit ECIJPECL YO Single 2V Power Supply 28 PinPLCC (8101). l00PQFP (8102) 400mW (8101). 3W(8102) Programmable Loop Bandwidth STS-3/STM-l or STS-l21STM-4 Data Rates Compatible with PMCSierra 531215355 Devices On Otip Clock Multiplication At Selectable Reference Frequencies Equipment and Facility Loopback Power - 1.98 Watts l00-Pin Thermally Enhanced PQFP Package 155Mb1s or 622 Mbls Operation Includes the PM5312.STI'X for Interoperability Testing . Completely Self Contained for Self Test Operation Flexibility to Evaluate the VSCSII 0 in All Modes of Operation . . SMA Connections for High Speed Otaracterization Allows Signals to be AC or Direct Coupled into theVSCSll0 ECL Buffered Interfaces Provided STS-3/STM-l or STS-I21STM-4 Data Rates Compatible with PMCSierra PM531215355 Devices On-chip Clock Multiplication Selectable Reference Frequencies Bellcore. ITU and ANSI Jitter Compliance Looptiming Facilities Enhanced Equipment and Facility Loopback Single 3.3V Power Supply Low Power - 1.2W max 100 Pin Thermally Enhanced PQFP Package 8 VITESSE Semiconductor Corporation Product Summary .....Pfo/!ii#i:~;i;iiy .... .......................... P#~i'iJiti1#··.··········· .... .." •••• .222l. The VSC8111 evaluation board provides users the ability to evaluate the VC8111 device and perform interoperability testing with the PM5355 S/UNI-622 device. The board is self contained and includes DIP switches to exercise the various modes on the VSC8111 device. The board provides high speed serial connections for interfacing to SONET or SDH test equipment allowing full compliance and error rate tests to be performed. 155 Mbls. 622 Mbls Operation Includes the PM5355 S/UNI-622 for Interopembility Testing . Completely Self Contained for SelfTe&t Operation Flexibility to Evaluate the VSC8111 in all Modes of Operation SMA Connections for High Speed OJ.aracterization Allows Signals to be AC or Direct Coupled into theVSC8111 ECL Buffered Interfaces Provided VSC8112 ATMISONETISDH 622 Mb/s muxldemux with integrated clock generation. Provides equipment and facilities loopback. Ideally suited for high speed data distribution in ATM and SONETISDH systems. Opemtes as a Bit-serial STS-3ISTM-l to STS-l21 STM-4 MuxlDemux On-chip 622 MHz Oock Generation from 155 MHz Reference Equipment and Facility Loopback Extended Temperature Range - O°C to 11 O°C Low Power - 1.5W Max 100 Pin Thermally Enhanced PQFP Package VSC864A-2 64 x 64 crosspoint switch with up to 200 Mb/s perfonnance and £10% duty cycle distortion. Ideal for high speed data distribution for telecommunications, computer network and multiprocessor switching, video switching, and test equipment. 200 Mbls Operation Duty Cycle Distortion SlO% ECL lOOK Compatible Parallel Data 1/0 Oocked Mode Output to Output Skew <1500 ps 9.4 W Power Dissipation (Typ.) Power Supply: -2.0 V ± 5% Cascadable for Larger System Requirements 344-pin Ceramic LDCC Package VSC8111EV (Data Sheet in Development) Q!) VITESSE 1996 Communications Product Data Book Page 323 Product Summary Page 324 8 VITESSE Semiconductor Corporation VITESSE Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset Features • Serial Data Rates up to 2.5 Gb/s • Differential or Single-Ended Inputs and Outputs • Parallel Data Rates up to 625 Mbls • Low Power Dissipation: 1.5 W (Typ. Per Chip) • EeL lOOK Compatible Parallel Data JlOs • Standard EeL Power Supply: VEE = -5.2 V • Divide-by-4 Clock for Synchronization of Parallel Data to Interfacing Chips • Available in Commercial (0° to +70°C) or Industrial (_40° to +85°C) Temperature Ranges • SKIP Input on Demux for Realignment of Output Word Boundaries • Proven BID Mode GaAs Technology • 28-pin Leaded Ceramic Chip Carrier FuncUonalDescnpUon The VS8004 and VS8005 are data conversion devices capable of serial data rates up to 2.5 Gb/s, transforming 4-bit wide parallel data to serial data and serial data to 4-bit wide parallel data. The VS8004NS8005 are fabricated in gallium arsenide using the Vitesse H-GaAs™ BID MESFET process which achieves high speed and low power dissipation. These products are packaged in a ceramic 28-pin leaded chip carrier. VSB004 The VS8004 is a high speed 4 bit parallel to serial data converter suitable for digital voice or data communications applications. All inputs and outputs can be used differentially or single-ended. The parallel inputs [D(0:3), ND(0:3)] accept data at rates up to 625 Mb/s. The differential serial data output (SDATA, NSDATA) presents the data sequentially from the parallel data inputs at rates up to 2.5 Gbls, synchronous with the differential high speed clock input (CLK, NCLK). An internal timing generator receives the high speed clock input and divides it by four to create a differential clock output (CLK4, NCLK4). This clock signal is provided so that incoming parallel signals can be synchronized to arrive at the input data registers simultaneously. An internal bias network. is provided at all inputs to simplify capacitive coupling. VSB005 The VS8005 is a high speed 4-bit serial to parallel data converter suitable for digital voice or data communications applications. All inputs and outputs can be used differentially or single-ended. The differential serial data inputs (SDATA, NSDATA) accept data at rates up to 2.5 Gb/s, synchronous with the differential high speed clock input (CLK, NCLK). The parallel outputs [D(0:3), ND(0:3)] present the data sequentially at rates up to 625 Mb/s. An internal timing generator receives the high speed clock input and divides it by four to create a differential clock output (CLK4, NCLK4) which is synchronous with the parallel data outputs. A control input (SKIP, NSKIP) is provided to allow realignment of the output parallel word boundaries. SKIP Signal The SKIP signal is provided to allow realignment of the output parallel4-bit word boundaries. Within the current CLK4, the rising edge of a SKIP causes an internal circuit in the VS8005 to hold the current 4-bit word output and drop the fifth output bit. The sixth output bit will become the MSB of the next 4-bit word output; and G52012-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book Page 325 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset· the falling edge of SKIP makes the next three parallel output words invalid (which is equal to three CLK4 or twelve CLK). After thlLt the outputs will be valid and will have the MSB of the output realigned by one bit. For Example, the user finds that the word boundary of the output is offby two bits, then he needs to perform two SKIPs. He needs to issue one SKIP, wait for three CLK4 cycles until the output is valid, then issue another SKIP, wait for another three CLK4 cycles. Then the outputs will have the bit positions in the right place as demonstrated in the following: Misaligned by 2 bits: 112 Byte Word Output C D G H K L 0 P S T C D E F I M N Q R A B E F J C H ----+ D I E F i J K L M P Q T A D E N 0 R S B C F G U SKIP INVAlID Misaligned by 1 bit: 112 Byte Word Output D E H I L M P Q T A D E D I ----+ E J M N Q R A B E F F G J K N 0 R S B C F G F G K L 0 P S T C D G H i U SKIP INVAlID Realignment Done. Applications • High Speed Instrumentation and Test Equipment • SeriaJization of Computer Backplanes • Fiber-optic Communication • Computer to Computer Interfaces • Local Area Networks • Serial Control Buses for Aerospace Environments Page 326 @ VlTESSE Semiconductor Corporation G52012-Q Rev. 2.0 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset Figure 1: VS8004 Block Diagram DB NOB 01 N01 02 ND2 4:1 SOATA Mux NSOATA 03 N03 CLK NCLK Timing Circuit ......~- CLK4 Vcc=f?JV ~ VEE = -5.2V:t O.26V ~ Figure 2: VS8005 Block Diagram DB SOATA NSOATA NOB 01 2:4 Demux CLK NCLK 02 ND2 SKIP NSKIP 03 N03 Vcc=0V o CLK4 > VEE = -5.2V:t O.26V o G52012-0 Rev. 2.0 .. ® VITESSE 1996 Communications Product Data Book Page 327 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset VS8004 AC Characteristics (Over recommended operating conditions) tax High Speed clock period 400 ps tsu \i D(0:3). ND(0:3). set-up time with respect to a.K4. Na.K4 900 ps D(0:3). ND(0:3). hold time with respect to CLK4. Na.K4 SDATA, NSDATA transitiOJl. time (LO to HI, ill to LO) while driving 500 to -2.0V -300 ps tnH(HS). tmL(HS) jitter(RMS) tnH·tnn, 150 ps a.K, Na.K to SDATA, NSDATA (max-min). (Hl to LO). same part, same pin at constant conditions <50 ps ECL output transitiOJl. time (LO to HI, HI to LO) while driving 50n (CLK4. Na.K4. D(0:3). ND(0:3» to -2.0V 500 ps Figure 3: VS8004 Waveforms CLK(1), NCLK CLK4(~ NCLK4 ~ ~lnH"1HL ==x_______A___..JX~---..;.M X~ ___...I) "'+~_-IH --"'''~I O(B:3), NO(B:3) ~LWDA~ \Vr--------~X....._ _ _ _- . . J "'"-_ _ _ _ _ _-J~ SOATA, NSOATA (1) Negative edge is .oIive edge Page 328 8 VlTESSE Semiconductor Corporation G52012-o Rev. 2.0 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset VSB005 AC Characteristics (Oller recommended operating conditions) tcLK High Speed clock period (CLK, NCLK) 400 CLK4, NCLK4 to D(O:3), ND(O:3) ps 400 ps SKIP, NSKIP pulse with (HIGH) 2 ns SKIP, NSKIP pulse with (LOW) 2 ns EeL output transition time (LOW to HIGH & HIGH to LOW) for D(O:3), ND(O:3) and CLK4, NCLK4 (Driving 5(0) 500 ps SDxrA, NSDxrA phase timing margin with respect to CLK, Na..K input: Phase Margin = (1 _ ts u + tH)360 0 tc Phase Margin 135 degrees where t , is minimum clock cycle. Figure 4: VS800S Wavefonns SOATA, NSOATA ~ j+tTLH. tTHL CLK4 N; 0(0:3), NO{O:3) ~ __ _' __ l:t040 ' X. VAUOOATA j+--tpWH S~~NS~P----~~ (1) Rising edg. _ _ _ da". G52012-0 Rev. 2.0 -,X NCLK4~____--JX"'---""'D ............................................................................................................ -6S· to + IS0·C Notes: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage, but are stress ratings only. Functionality at or exceeding the values listed is not implied Exposure to these values for extended periods may affect device reliability. (2) VBEmust be applied before any input signal voltage (VBCLIN)' Recommended Operating Conditions Power Supply Voltage (Vm;) ............................................................................................................. -S.2V ± 0.26V Operating Temperature Range* (T) ...................................... (Commercial) O· to 70·C, (Industrial) -40" to + 8S·C * Lower limit ofspecification is ambient temperature and upper limit is case temperature. Page 330 8 VlTESSE Semiconductor Corporation G52012-o Rev. 2.0 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset DC Characteristics Table 1: EeL Inputs and Outputs (Over recommended operating conditions with internal VREF, Vee =GND, Output load =50 ohms to -2.0V) . . .. H,i>4r~~~rjj~¥#ti##fi .Mi~ .. ... ~.....MdX .u~ii~.T¢~M.~.· Oulpllt LOW voltage -1020 -2000 -1620 mV mV Vm Input mGH voltage -1040 -600 mV Vn. Input LOW voltage -2000 -1600 mV 1000 JJA VIN=Vm(max) JJA VIN =Vn. (min) VOH 1m In. Oulpllt mGH voltage -700 Input mGH Current Input LOW Current 500 -1000 -500 VIN = Vm (max) orVn. (min) VIN = Vm (max) or Vn. (min) Guaranteed HIGH signal for ECLinputs Guaranteed LOW signal for Ea..inputs Note: 1) Differential ECL output pairs must be terminated identically. 2) Leakage currents exceed ECL specifications due to the internal bias network which is connected to all inputs Table 2: Power Dissipation (Over recommended operating conditions, Vcc =GND, outputs open circuit) ¥:s~OiH VS80iM YS#~VS8.00s .vS8.oosvsaiJiI.F (Mi,,!HH(ijl1jH(Mli;TFH(~F .·~).HH(~#)THunii8 • .. .. ':::: ::::::::::::::::: :::::::::::" ...................... . .... .. .............. .. . Power supply c\Il1'ent from VEE Power ctissipation 270 350 310 400 mA 1.5 1.9 1.6 2.2 W Table 3: High Speed Inputs (Over recommended operating conditions, Vcc =GND, Output load =50 n to -2.0V) Vn. Input mGH voltage -3.1 -3.0 -2.9 Input LOW voltage -4.1 0.8 -4.0 -3.9 V V GuaranteedmGHsignal Guaranteed LOW signal 1.0 1.2 V ACCoupled Input voltage swing Notes: 1) FSD protection is not providedfor the high speed input pins, therefore, proper procedures should be used when handling this product. 2) A reference generator is built in to each high speed input, and these inputs are intended to beAC coupled. 3) If a high speed input is used single-ended, a 150 pF capacitor must be connected between the unused high speed or complement input and the power supply (VtT). G52012-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book Page 331 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset Table 4: High Speed Outputs (Over recommended operating conditions, Vee =GND, output load =50n to -2.0V) !!Nom: Output mGH voltage -0.9 Output LOW voltage Output voltage swing -1.8 0.8 1.0 1.4 v v v Tenninated to -2.0V through 500 Terminated to -2.0V through 500 Output Load, 500 to -2V Notes: 1) ESD protection is not provided/or the high speed input pins, therefore, proper procedures should be used when handling Parallel Data, ClK, NClK, SKIP, NSKIP Inputs ECL inputs (clock or data) provide for AC coupled operation. Internal biasing will position the reference voltage of approximately -1.32 Volts on both the true and complement inputs. ChIp BoU'Idary r~--------------------------- VCC· GND ~'~F: f500 : Vrr r 0.1 ~F: Vrr High Speed Inputs High speed inputs (clock or data) provide for AC coupled operation. Internal biasing will position the reference voltage of approximately -3.5 Volts on both the true and complementary inputs. Single-ended, AC coupled operation is illustrated below .~;>.I!:<'!~!"Y ...•..•.•........... ~~PF; fSOG . I~pf r; Vrr Vrr VEE=·5.2V ............................. Page 332 ® VlTESSE Semiconductor Corporation = VTT Vee -2V G52012-0 Rev. 2.0 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer! Demultiplexer Chipset Rgure 5: VS8004 Pin Diagram N03 15 7 00 veCA 16 6 NC CLK4 17 VSBOO4 5 VEE 18 19 Heat Sink Side NCLK4 VEE 4 vee 3 VEE VCC vce NC NC Table 5: VS8004 Pin Description ••• ....P)~# ••••• .y~t#~ ................... ... IftL •• 23,24 CLK,NCLK I Differential high speed clock inputs 27,26 SDATA. NSDATA 0 Differential high speed serial data outputs ....... 17,18 CLK4,NCLK4 0 Differential divide by 4 clock outputs (ECL) 7-10,12-15 D( 0:3), ND(0:3) I Differential parallel data inputs (ECL) 3, 5, 19, 25(1) VEIl -S.2V supply voltage 2,4,11,20 Vee 16,28 VCCA o V ground connectioo. o V ouqrut ground connection (Normally c : ~ ~ DflJ VCCA VEE VCC VEE VCC NSKIP ~ C§ C§ ~ C/) ~ Table 6: VS8005 Pin Description .................pjh:#.:: ........•.... ..... :: .. :..... ~#~: .• :::.: •••••. •:··:::i(t?·.:.:.····::.·.·.:.::: .•. :·:::.;·:: .. ::::::~*ff#,tf##:: . . ::::::.:.:: • : .•••••••. ;.: . 24,23 CLK,NCLK 26,27 SDATA, NSDATA 17,18 CLK4,NCLK4 0 Differential divide by 4 clock outputs (BeL) 7-10, 12-15 D( 0:3), ND(0:3) 0 Differential parallel data outputs (BeL) 28,1 SKIP,NSKIP I Differential word boundary inputs (BeL) I Differential high speed clock inputs Differential high speed serial data outputs 3,5,19,25 Vo -5.2V supply voltage 2,4,11,20 Vee 6, 16 Vea.. o V ground CODDeCtion o V oulpUt ground counection 21,22 NC No COlIIleCtiOll Notes: 1) The heat sink is connected to VBB(pin 25). To prevent a short circuit between Vce; VcCA (0Vnormally) andVEE (-5.2Vnormally), do not connect this heat sink to ground. 2) The falling edge ofSKIP causes realignment of the parallel word boundary making parallel data invalidfor three CLK4, NCLK4 (12 CLK, NCLK) periods. Page 334 e VlTESSE Semiconductor Corporation G52012-0 Rev. 2.0 Data Sheet 2.5 Gbits/sec 4-Bit Multiplexer/ Demultiplexer Chipset Package Information 28·Pin Leaded Ceramic Package (LDCC) iB~ L B J Heat Sink Side j 28 1 1 45''''' N-II- A 11.176111.682 B 1.01611.524 8.128/8.636 1.143/1.397 0.40610.610 1.829/2.235 C E I J G52012-o Rev. 2.0 -10 0.440/0.460 0.040/0.060 0.33TYP 0.050TYP 0.01610.024 .0721.088 NOTES.. Drawing 7tOIlo ,eak. PacluJge.. Ceramic (alumina); Heat aInk.. Copper-twrptero; l.eatb .. Alloy 42 with gold plali1lg. K L M N 0 0.102/0.203 5.842/6.858 22.860125.398 0.00410.008 0.230/0.270 0.900/1.000 0.356/0.559 1.52512.287 0.01410.022 0.075TYP ® VITESSE 1996 Communications Product Data Book Page 335 Data Sheet 2.5 Gbits/sec4-Bit Multiplexer/ Demultiplexer Chipset DUTBoards The VS8004FDUTNS8005FDUT evaluation boards are special purpose circuit boards which provide a test bed suitable for evaluating the high performance characteristics of the VS8004 4:1 Multiplexer or the VS8005 1:4 Demultiplexer in the 28 pin leaded ceramic chip carrier. The figure below is a schematic representation of these circuit boards. These boards provide a controlled impedance transmission line for all signals, and suitable decoupling for the power supplies. The signal traces have a characteristic impedance of son. All EeL input lines are terminated with son (chip resistor) as close to the device package pin as possible. The high speed inputs are also provided with 150 pF blocking capacitors. Signals are launched onto the circuit board and removed by means of SMA coaxial connectors. While the input signals are terminated, the output signals are provided open circuit and are intended to be terminated in the measuring instrument. Normally, the VS8004 and VS8005 operate in an EeL environment with standard EeL power buses: 0V and -5.2Y. In order to simplify interface to standard ground referenced test equipment, however, the circuit board power buses are offset so that the shield connectors are at ground voltage. The figure below shows the arrangement of the power supply decoupling capacitors. There is a 33 J.lF electrolytic capacitor, as well as several 0.01 J.lF ceramic capacitors across each power bus. The device to be tested is held in place with a pressure retaining fixture. The figure on the following page indicates the physical dimensions and the connection labels for the evaluation boards. Figure 7: VsaOO4NSSOOS DUT Board Schematics +2V r r 1S0pF I i High ed SOD C/ooktu,.l or High Speed <:X:I5:!I • G5202S-o Rev. 4.0 8 VlTESSE 1996 Communications Product Data Book Page 343 Data Sheet 2.5 Gbitslsec SONET Compatible 8-bit MuxlDemux Chipset VSB022 Demultiplexer AC Characteristics (OVer recommended operating conditions) 3.2 12.8 Phase Margin speed clock: Ph/J8eMargin = (1- tsu + tH)360 0 . 135 us us 180 degrees te Note: If t. changes, all the remaining parameters change as indicated by the equations. VSB022 SONET Frame Recovery and Detection The SONET framing sequence is a string of Al bytes followed by a string of A2 bytes. (AI = 11110110 and A2 = 00101000) The first serial bit starts at the left of the byte. The table below shows the number of Al and A2 bytes in each SONET frame for different line rates. The VS8022 contains a frame recovery circuit and a frame detection circuit. .. Frame Recovery Circuit The frame recovery circuit is designed to scan the serial data stream, looking for the Al byte. When it finds the Al pattern, it adjusts internal timing so that the serial data is properly demultiplexed onto the eight parallel outputs. Subsequently, the MSB of the At byte will appear in the Dl position and LSB of the Al byte will appear in the D8 position. This word boundary alignment causes the BYCKO, BYCKON output to be resynchronized. While the frame aligner is hunting for the frame, BYCKO and parallel data are invalid. Frame recovery circuits are disabled by frame detection (resulting in FP) or by a falling edge on the OOFN input while FDIS is high. Page 344 @ VITESSE Semiconductor Corporation G52028-0 Rev. 4.0 Data Sheet 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset Frame Detection Circuit The frame detection circuit monitors the demultiplexed data, and senses the boundary between At and A2 bytes. This pulse on the FP output will reset the frame recovery circuit, so that no further resynchronization will occur until permission is given through OOFN. Circuit Operation The frame recovery circuits are initialized and enabled on the falling edge of the OOFN ECL input with FDIS held low. The OOFN must be at least one byte clock period wide. It must occur at least four byte clock periods before the AlIA2 boundary. The circuit requires at least three At bytes followed by 3 A2 bytes for successful alignment The first At byte is used by the frame recovery circuit to obtain initial word boundary alignment, while the following two Al and three A2 bytes are used to reset the frame recovery circuit and maintain alignment for the subsequent bit stream. Frame recognition will occur for each word boundary aligned AIAIA2A2A2 sequence in the data stream. Frame recognition is signaled by a one byte clock period high pulse on the FP ECL output pin. This FP pulse will appear one byte period after the firstA2 byte appears on the parallel data output pins. STS-3Frame STS-48 Frame ~ 3x3Byte.....,3 x 90 Byte'_----t 1251'S r-~3~A~1.~3~A=~~3~C~1.~ ______ j ~ 125 48 x 90 Byt ~ 3 x 48 Byte....., r- 48A1s 48A2s 48C1s lit DATA '" Ll----'---'---+-----! LTransport---l-sTS.3 Envelop~ OVerhead Capacity ~ II: DATA '" J L TranSPOW-ST8-48 EnvelO~ OVerhead Capacity Note: Al:r andA2:r: SONEI'framing sequence en: STS Frame ID G52028-0 Rev. 4.0 ~ VlTESSE 1996 Communications Product Data Book Page 345 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset Data Sheet Absolute Maximum Ratings(1) Power Supply Voltage (VTT ) ...........................................................................................................-3.OV to + O.SV Power Supply Voltage (Vm> .................................................................................:.................. V'IT + 0.7V to -6.0V EeL Input Voltage Applied (2) (VECLIN) ••••.•••••.•••.•••••••••••••••••••••••••••••••••••••••••••••••••.••••••.••••.••••••••••.••• -2.SV to + O.SV Higb Speed Input Voltage Applied ('2) (VHSIN) •••.••••••••••••••••••••••••.•••••••••••••••••••••.•..•••••••••••.••. VES-O.7V to Vcc + 0.7V Output Current (DC, output mGH) (lour) ..................... :............................................................................ -SO rnA Case Temperature Under Bias (Tc) ................................................................................................ -'5S· to + 12SoC Storage Temperature (3) (TSTcJ ...................................................................................•.................... -6S· to + lS0 C 0 Recommended Operating Conditions EeL Power Supply Voltage (4) (V'IT) ................................................................................................... -2.0V ± 0.1 V Power Supply Voltage (Vm> ..........................•.................................................................................. -S.2V ± 0.26V Operating Temperature Range (3) (T) .................................... (Commercial) o· to 700c, (Industrial) -400 to + 8S·C Notes: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) V7T must be applied before any input signal voltage magnitude ( IVBCt/N Iand IVHSIND can be greater than IV7T -0.5v.1 (3) Lower limit of specification is ambient temperature and upper limit is case temperature. (4) When using internal ECL lOOK reference level. Page 346 @ VrrESSE Semiconductor Corporation G52028-0 Rev. 4.0 Data Sheet 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset DC Characteristics Table 1: low Speed Eel Inputs and Outputs (Over recommended operating range with internal VREF, Vee =GND, Output load =50 a to -2.0V) ,r~h~~irir yp~~#i~# v OR ....... >Min. ••••••••• ~.. ..M.i#. .··:v.m .H¢~mJ~· Output mGH voltage -1020 Output LOW voltage Input mGH voltage -700 mV VIN - Vm (max) orVIL (min) -1620 mV VIN =Vm (max) orVIL (min) -600 mV Guaranteed HIGH signal for all inputs -1500 mV Guaranteed LOW signal for all inputs 1.4 V Output load 500 to VTr -1150 Input LOW voltage 0.8 Output voltage swing 1.0 Note: Differential EeL output pins must be terminated identically. Table 2: Power Dissipation (Over recommended operating conditions, Vcc =GND, outputs open circuit) .. ........................ ........................ . '" . / .··V$~Q~[ VS802[ VSBoii y$$oi~v$$o~i . :v$~~i .......... (tWM(TlP) '..(M'#,j n(Mi#it'?'ii '(M#i UnliS ........................ ........................ ........................ .. i!4r4~f·· Power supply current fromVEB Power supply current fromV'IT Power dissipation 400 600 450 600 mA 110 200 120 200 mA 2.3 3.75 2.6 3.75 W Table 3: High Speed Inputs and Outputs (Over recommended operating conditions, Vee =GND, Output load =50 a to -2.0V) IlVm V OH Input voltage swing VOL Output LOW voltage 0.8 Output mGH voltage 1.0 1.2 -0.9 V ACCoupied V Output load, 500 to -2.OV V Output load, 500 to -2.0V IlV0 1IT(dm) Output voltage swing for data 0.6 0.8 1.2 V Output load, 500 to -2.0V IlV01IT(elk) Output voltage swing forelock 0.6 0.7 1.2 V Output load, 500 to -2.0V -1.8 Notes: 1) A reference generator is builtin to each high speed input, and these inputs are designed to beAC coupled. 2) If a high speed input is used single-ended, a 150 pF capacitor must be connected between the unused high speed or complement input and the power supply (VIT)' 3) Differential high speed outputs must be terminated identically. 4) ESD protection is minimal/or the high speed input pins, therefore, proper procedures should be used when handling this product G52028-0 Rev. 4.0 @ VlTESSE 1996 Communications Product Data Book Page 347 Data Sheet 2.5 Gbitslsec BONET Compatible 8-bit MuxlDemux Chipset High Speed Inputs In the past, the high speed inputs, which are typically used for serial data and high speed clock inputs with frequencies greater than IGhz, were specified with absolute minimum and maximum voltage values. Since these inputs are intended for AC coupled applications, they have been re-specified in terms of a voltage swing (dVIN)· High speed clocks are intended for AC coupled operation. In most situations high speed serial data will have high transition density and contain no DC offsets, making them candidates for AC coupling as well. However, it is possible to employ DC coupling when the serial input data contains a DC component. The structure of the high speed input circuit is shown below. DC coupled circuits may be used to operate this input provided that the input swing is centered around the reference voltage. Since the internal resistor divider which forms the -3.5V reference presents an attenuation factor of only 0.6 to the VEl! power supply, it is recommended that, in single-ended DC coupling situations, the user provide an external reference which has better temperature and power supply rejection than the simple on chip resistive attenuator. This external reference should have a nominal value of -3.5 V and can be connected to the complimentary input. This complication can be avoided in DC coupled situations by using differential signals. . Chip Boundary '~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~------. Vee = GND GT-150PF : 50n Vrr 150p~ r Vrr Page 348 . @ VEE =-5.2V VrrESSE Semiconductor Corporation G52028-o Rev. 4.0 Data Sheet 2.5 Gbits/sec BONET Compatible 8-bit MuxlDemux Chipset Example Application: STS-48 SONET System Link The objective in this example is to multiplex/demultiplex 8 channels at the STS-48 line rate with SONET frame recovery capability. The system can be implemented using the VS8021 and VS8022 as follows: 8:1 Multiplexer Data at a line rate of 311.04 Mbyteslsec is registered at the inputs using the externally provided 311.04 MHz byte clock. ERR is gated into SYNC which is edge triggered for retiming of the input word. The 2488.32 MHz clock is used to generate timing signals for the mutiplexing function. The muxed output at 2488.32 Mbitsl sec is generated at the serial data output ofVS8021. 1:8 Demultiplexer The 1:8 demultiplexer receives serial data at 2488.32 Mbitslsec and generates parallel data at 311.04 Mbyteslsec along with a byte clock output of 311.04 MHz. The demux also has the SONET frame recovery and detection circuitry. During system start-up OOFN input receives a falling edge from the system control to permit recovery of the SONET frame and align on byte boundaries. Once the frame is aligned, the FP pulse is generated on every SONET frame. If for any reason the FP pulse disappears on frame boundaries then this signals the system that the frame synchronization is lost. The system then asserts the OOFN input (High to Low) to recover the SONET frame and align on byte boundaries, bringing the system back to a synchronized condition. After synchronization is achieved, the FP pulse starts again on every frame. ESD Protection Electrostatic discharge protection is provided for ECL JlO's and high speed clock and data JlO's to the following minimum limits: ECL JlO ............................................................................................................ lOOOV High Speed Clock and Data Inputs ..................................................................... 500V Figure 5: STS-48 SONET System Link .. ~ ................ ...... . OI/oIN} 4iI 02lD:2N ~g~ Ii D7JD7N O8/08N :: ., ::g: ~ Frwn. Enable (0011'1) Foam. PuI .. (FP) ~~--~--:-~~~~ G52028-Q Rev. 4.0 ® VlTESSE 1996 Communications Product Data Book Page 349 Data Sheet 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset Figure 6: Vsa021 Pin Diagram a~~~~Q~~~§~~~ D3N 40 D4 D4N vee BYCLK BYCLKN /Ie 41 26 25 42 43 44 24 23 22 DON 21 20 co 19 18 CLKIN 17 CLKI VEE (1) DO vrr 45 46 DB 47 D5N DB 48 49 50 16 /Ie D6N 51 15 /Ie 07 52 14 /Ie vee VSB021 Heat Sink Side ~ ~ ~ § Page 350 /Ie ~ ~ CON vee ~~~~~~~ C!D VlTESSE Semiconductor Corporation G52028-0 Rev. 4.0 Data Sheet 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset Table 4: VS8021 Pin Description. Note: 1) Pin #23 on both parts is connected to the heat sink. Connect to VEE or most negative chip voltage. G52028-0 Rev. 4.0 ® V1TESSE 1996 Communications Product Data Book Page 351 Data Sheet 2.5 Gbitslsec SONET Compatible 8-bit MuxlDemux Chipset Figure 7: Vsa022 Pin Diagram D5N N:: NO N:: os N:: vee VEE (7) BYlXON N:: VSB022 N:: VTT NO Heat Sink Side BYCKO N:: aKIN D4N vee vee CLKJ 04 DIN D5N 01 03 N:: Table 5: VS8022 Pin Description . .... ~~. ~ ~ ~~ ....... . .~~~: .~:.p#~#,P'~ ~ 3,5,6,8,31,32,34,35, 38-40, 42, 48, 50-52 D1-D8, DlN-D8N 0 ECL 17,19 CLKI,CLKIN I HS 47,44 BYCKO, BYCKON 0 ECL Divide by 8 clock ECL outputs 15,16 DI,DIN I HS High speed differential serial data inpnts Parallel EeL differential data ou1puts High speed differential clock inputs 11 FDIS I ECL Frame recovery disable input 12 OOFN I Ea. Frame recovery enable ECL input 4,10,18,30,36,43,49 Vex I Ground connection 7,46 Vrr -2.0V supply for internal reference generation & low power logic 23(1),33 V BB -5.2V supply for high speed logic I, 2, 13, 14,20-22,2429,37,41,45 NC Noconnectioo. Note: 1) Pin #23 on both parts is connected to the heat sink. Connect to VEE OT most negative chip voltage. Page 352 @ VITESSE Semiconductor Corporation G52028-0 Rev. 4.0 Data Sheet 2.5 Gbits/sec SONET Compatible 8-bit MuxlDemux Chipset Package Information 52·Pin LeaJed Ceramic Pacluzge (LDCC) B t • HEAT SINK SIDE o PACKAGE IS CAVITY DOWN 52 NOTES: Drawing not to .tcale. Pad",..: C.,andc (a/wnIIra); Heat..mJc.· Copplr-trmg.t.n; U4d8: AU0)I42 with gold plati1lg. A 18.54119. 56 0.730/0.770 0.016/0.024 1.0211.52 0.040/0.060 I J 0.41/0.61 B 2.0312.79 0.080/0.110 C* 15.49116.51 0.610/0.650 K* 0.09/0.24 0.003/0.009 D* E 15.24TYF O.600TYF 4.57/5.34 0.180/0.210 1.27TYP 0.050TYF 27.69/30.22 1.090/1.190 F 0.76/1.02 0.030/0.040 L M N 0.36/0.56 0.01410.022 G 16.94TYF 0.667TYF 0 1.75/1.90 0.069/0.075 H 1.9112.41 0.075/0.095 *At package body. G52028-0 Rev. 4.0 @ VlTESSE 1996 Communications Product Data Book Page 353 Data Sheet 2.5 Gbits/sec SONEr Compatible 8-bit MuxlDemux Chipset DUTBoards The VS8021NS8022 DUT boards are special purpose circuit boards which provide a test bed suitable for evaluating the performance characteristics of the VS8021 8:1 Multiplexer or the VS8022 1:8 Demultiplexer in the 52 pin LDCC package. The figure below is a schematic representation of these circuit boards. These boards provide a controlled impedance transmission line for all signals, and suitable decoupling for the power supplies. The signal traces , have a characteristic impedance of SOU All ECL input lines are terminated with son (chip resistor) as close to the device package pin as possible. The high speed inputs are also provided with 1S0pF blocking capacitors as shown. These capacitors are shorted in applications which require DC connection to these inputs. Signals are launched onto the circuit board and removed by means of SMA coaxial connectors. While the input signals are terminated, the output signals are provided open circuit and are intended to be terminated in the measuring instrument such as an oscilloscope. Normally, the VS8021 and VS8022 circuits operate in an ECL environment with standard ECL power buses: OV, -2V, -S.2V. In order to simplity interface to standard ground referenced test equipment, however, the circuit board power buses are offset so that the shield connectors are at ground voltage. The figure below shows the arrangement of the power supply decoupling capacitors. There is a 33 J.IF electrolytic capacitor, as well as several 0.01 J.IF ceramic capacitors across each power bus. The device to be tested is held in place with a pressure retaining fixture. The figures on the following two pages indicate the physical dimensions and the connections labels for the evaluation boards. Figure 8: VSS021NS8022 OUT Board Schematics +2V r /fg/lC C/ocIr nputs orHIgh ed 500 Data t;'uts € 1E 150pF ... INP I I Vcc Hlgh~ D.taorCl 150pF Oup/~ Device Under 500 ' 1'XIND<7:0> - TXINA<7:O> -+r--~ TXINB<7:O;. -+ -+ -+ REG ~ BITE ~ MUX INIRI. 1 ~ TXCLKIN r ~ TXCONIROL TXCLK+ TXCLK- t I RESET DISFPCHK SBTIOZO[1:0] SBLS'IS48C DISBIGBN SBLPCLK TXPCLKIN+ TXPCLKIN- - ... 8:1 SERIALIZER rt- 1\/\ ,I. y~J.PARlTY CALCULATION TXFPIN [3:0] DISSCRM .1 SCRAMBLER ~ TXPCLKOUT+ TXPCLKOUTTXSOUT+ TXSOUT- 4- f- TXSLBIN+ TXSLBINTXSLBCLK+ f- TXSLBCLKFACLOOP TXSCLKOUT+ TXSCLKOUTTXCLK12 RCLK155+ RCLK155SYNCRSTB TXOOF TXFPOUT NOFP The part is clocked by a 2.488 GHz clock, which has to be provided by an external PLL. The VSC8023 is equipped with a 155.52 MHz differential EeL output clock, RCLK155+ and RCLK155-, to facilitate the creation of the external PLL circuit. The block diagram in Figure 1 shows the major functional blocks associated with the VSC8023. Byte-wide data is presented to the TXINA<7:O>, TXINB<7:0>, TXINC<7:O>, and TXIND<7:0> input pins and is clocked into the part on the rising edge ofTXCLKIN, as depicted in Figure 3. The four PM5312s or the four PM5355s each output a frame pulse aligned to the first payload byte of every frame, as shown in the functional timing diagram, Figure 3. The byte-interleave mux will be reset on the occurrence of the first valid frame pulse on TXFPIN[3:0] (active high). A valid frame pulse will only be detected if all four TXFPIN[3:0] inputs Page 360 8 VrrESSE Semiconductor Corporation G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbitsisec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset are high at the same time. Therefore, if the four PM5312s or four PM5355s are not exactly byte aligned SYNCRSTB will be asserted low for sixteen 77.76 MHz (TXCLKI2) clock cycles. TXCLK12 will be held low during these sixteen cycles and for an additional sixteen cycles thereafter. TXOOF will be held high for sixteen TXCLK12 cycles after the TXCLK12 clock starts running again to indicate that the CPU needs to reload the registers in the four PM5312s or four PM5355s. The frame-pulse check circuitry can be disabled by asserting the DISFPCHK input high. When the asynchronous DISFPCHK input is high, the output NOFP will be held high while no valid frame pulse can be detected. Please refer to Figure 2 for the Synchronous Reset timing. In Co-directional mode TXCLK12 is not connected to TXCLKIN. Figure 2: Synchronous Reset Timing TX12CLK cycles cycles cycles ____ ~__________~________ J_:----~--________~________ o TXFPINO J~: 16 16 16 o TXFPINI TXFPIN2 : / 0 0 TXFPIN3 ~~--~----------~-------- SYNCRSTB 11--__---' TXOOF The output of the byte-interleave mux is scrambled with the SDHlSONET scrambling polynomial 1 + x 6 + x 7. The SDHlSONET scrambler can be disabled (on a frame wide basis only) by setting DISSCRM high. The value on the DISSCRM input is latched-in once every frame at the ~urrence of the frame pulse. A logic '1' latched-in during the current frame will result in a non-scrambled current frame, and the frames thereafter. The bit-interleaved parity byte B 1 is calculated over the entire scrambled frame and inserted into the B 1 location of the next frame before scrambling. This Bl generation can be disabled by setting the DISBIGEN input high. The value on this input is latched-in once every frame at the occurrence of the frame pulse. A logic '1' latched-in during the current frame will result in the B 1 byte in the current frame, and in the frames thereafter, being passed on transparently. The section-trace bytes (JO/ZO) can optionally be set to an increasing binary number from 01\hex to 30\hex by setting the SETJ9Z0[1:0] to '01 '. A non-zero value on the SETJOZO[I:0] bus latched-in during the current G52129-Q Rev. 2.0 ® VITESSE 1996 Communications Product Data Book Page 361 Preliminary Datasheet 2.488 Gbits/sec SDHISONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset frame will result in a change of the JOIZO bytes in the next frame and the frames thereafter if the value on the SETJOZO[l :0] bus is not changed. When SETJOZO[1:0] is held at '00', the JOrzo bytes will be passed on transparently. Since the first section-trace byte, JO, could carry a section-trace message it can be passed on transparently while the ZO bytes are set to an increasing binary number from 02\hex to 30\hex by setting SETJOZO[1 :01 to '10'. TXPOUT[7:0] is a parallel byte-wide STM-161STS-48 output which can be used for an Equipment Loopback (see Figure 19) or to feed a STM-64/STS-192 MUX circuit. TXFPOUT contains a frame pulse synchronized with the parallel STM-161STS-48 data rate. This frame pulse is aligned with the first payload byte in every STM-16ISTS-48 frame. Data on TXPOUT[7:0] and TXFPOUT is clocked out on the falling edge of TXPCLKOUT+ (rising TXPCLKOUT-). When the VSC8023 is used to feed a STM-64/STS-l92 MUX circuit (with byte wide data), the VSC8023 does not have to be supplied with a 2.488 GHz clock since the serial output mux is not used. Instead, a 311.04 MHz clock can be provided on the TXPCLKIN differential EeL input pins. The asynchronous SELPCLK input needs to be held high to select the TXPCLKIN. The serial STM-161STS-48 data stream is presented at the differential TXSOUT output on the rising edge ofTXSCLKOUT. To create a Facility Loopback, a high-speed clock (TXSLBCLK) and data (TXSLBIN) input have been provided. When the asynchronous FACLOOP input is held high, the data on TXSLBIN is clocked out through TXSOUT on the rising edge of the TXSLBCLK clock. Please refer to Figure 19 for a detailed Facility Loopback circuit diagram. In order to support STS-48c, where no byte-interleaving is required, the byte-interleaver will multiplex one byte (from every STM-41STS-12 data stream) at a time, instead of four bytes, by holding the SELSTS48C input high. Table 1: Section-trace Byte Select Settings . . . . . .. • "•• ~1t,r:J,i@J!1: ••••••••• "~1t,rlQ?i~r~' ••• '.' • "•••• '••••••••••••••••••• '••p#n~#(i#·.:":"""""""··· o o o Transparent 10 Transparent, ZO:02-301hex o 01-301hex Undefined Page 362 cP) V"ESSE Semiconductor Corporation. G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Figure 3: VSC8023 Functional Timing Diagram TXCLKIN TXINA<7:0> 7f) 7f) 7f) 7f) 7f) IDAI IDA2 TXINB<7:0> 7f) 7f) 7f) 7f) 7f) IDBl IDB2 IDA3 IDA4 IDB3 IDB4 TXINC<7:0> 7f) 7f) 7f) 7f) 7f) IDCI IDC2 IDC3 IDC4 IDC5 TXIND<7:0> 7f) 7f) 7f) 7f) 7,DDI IDD2 IDD3 IDD4 IDD5 starto/payload TXFPIN<3:0> -n IDA5 IDB5 TXSOUT (byte wide) Notes: (1) The correct latency between the TXlN data-stream inputs and the TXSOUI' data-stream output is NOT shown. (2) MSB leads on TXSOUI'; MSB is bit 7 on the TXINA. TXINB. TXlNC andTXIND data busses. G52129-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book Page 363 Preliminary Datasheet 2.488 Gbits/sec SDHISONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset VSCB024 FuncUonal DescnpUon The VSC8024 deseriaJizes a 2.488 Gbls data stream into a byte-wide data stream and recovers the SDHI SONET frame boundary. The SDHlSONET frame boundary is found by detecting the inner-most 24 bits of the last two Al bytes and the first twoA2 bytes in each frame or three Al bytes and threeA2 bytes, as shown in figure 4, when the SELFRDET[I:0] input signals are held low. The frame recovery is initiated when FRDETEN is held high. This control signal is level-sensitive and the VSC8024 will continually perform frame detection as long as FRDETEN is held high. Figure 4: Frame Boundary Detection Bits ~b~ 1 1~4------~------------------------------------------------------·~1 I 24~ 1 I '4 II, I I I 12~ I I ~I I I I 14 Al (F6) Al ~) I ' II !Inlnl~n n •• :••, :•••1 ..1 •• 1• r ~28) A2 28) A2 lilt !!n Al (F6) L .........., . . A2 (28) I lin: J :.................. : :...1 ..................., ... , l...........J. A frame detect based on these 24 bits will result in a SEF (Severely Errored Frame) detect at an average of no more than once every 6 minutes assuming a BER of 10.3 as specified by the SONET Bellcore spec. As an option, one can also base the frame-boundary detect on either the three innermost Al and the three innermost A2 bytes (48 bits) or on the last Al byte and the first four bits of the firstA2 byte (12 bits), based on the SELFRDET[1 :0] settings shown in Table 2. A frame detect based on 48 or 12 bits will result in a mean time between SEF detects of 0.43 and 103 minutes, respectively. The frame-detection and recovery circuit can be disabled by holding both asynchronous SELFRDET[l :0] inputs high. In this mode, data is muxed to the output (scrambling, B 1 insertion, B 1 calculation, and error detection functions are disabled). Table 2: Frame-detect Select Settings HFllncdonH HSELiiiiiiiiiii :sEuiIDETtF ................................................................................................... o 24 bits ~bits 12b~ o o o Frame detection disabled Page 364 ® VITESSE Semiconductor Corporation G52129-o Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SOH/SONET STM-16/STS-48 MuxlOemux and Section Terminator Ie. Chipset After the 1:8 Demux, the 8-bit parallel STM-161STS-48 data stream at 311.04 MHz is byte de-interleaved into four 8-bit parallel STM-4ISTS-12 data streams at 77.76 MHz (to four PM5312s or four PM5355s), consistent with the existing requirements for SDHlSONET intermediate level de-multiplexing. (In order to support STS-48c where no byte de-interleaving is required, the byte de-interleaver can be bypassed (straight forw~d demuxing will occur instead) by holding the asynchronous SELSTS48C input high). The part is clocked by a 2.488 GHz clock from the Clock and Data Recovery Unit (CRU). The block diagram in FtgUre 5 shows the major functional blocks associated with the VSC8024. Serial STM-16/STS-48 data is presented at the differential RXSIN input on the rising edge of RXSCLKIN+; refer to Figure 12. In order to create a Facility Loopback the registered RXSIN data and the RXSCLKIN are brought out of the chip (RXSLBOUT and RXSLBCLK). These two signals should be connected to the TXSLBIN and TXSLBCLK inputs on the VSC8023 in order to create a Facility Loopback. RXSLBOUT and RXSLBCLK outputs were added to minimize the loading on the high-speed clock and data lines coming from the RX optics module. In order to minimize the jitter on the RXSIN and RXSCLKIN inputs during normal operation, the RXSLBOUT and RXSLBCLK outputs can be disabled by holding the asynchronous input DISHSOUTS high. Please refer to Ftgure 19 for a detailed Facility Loopback circuit diagram. Figure 5: VSC8024 Functional Block Diagram DISLBOUTS PROPBIBRR SBLSTS4SC SDH RESET FRBRR DISDSCRM RXLOF RXFPOUT RXPPIN RXPCLKIN 1+ I I RXSEF RXCLKOur FRAMEPULSE RXCONrROL i FRDID'BN RXOUTA<7:0> +- r--V~ RXOUTB<7:0> +- r- J: II BYTE REG ~ DE·INTERLEAVE DEMUX ~ RXOUTC<7:0> +- r- RXOUTD<7:0> +- r-_~ 311.04 MHz I RXLBCLK+ RXLBCLK· +-- t--{l;'.~ - [ IDESCRAMBLBR SERIAUZER ~ DETEC£IOli i I Bl·PARlIY CALC 6I COMPARISION BIBRR r-RXeLKIN+ RXeLKIN· I- RXSIN+ RXSIN· f-t.~SLBOUf+ RXSLBOUf· SBLFRDB'Ill:O] LOS RXPlN(7: 0] EQULOOP G52129-o Rev. 2.0 (!j) VITESSE 1996 Communications Product Data Book Page 365 2.488 GbitS/sec SDH/SONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset Preliminary Datasheet The incoming data is optionally descrambled with the SDHlSONET scrambling polynomial and byte deinto four byte-wide parallel data streams and presented on the RXOUTA<7:O>, RXOUTB<7:0>, RXOUTC<7:0>, and RXOUTD<7:0> output pins at the rising edge ofRXCLKOUT; refer to Figure 6 for the functional timing of the receive circuit. The SDHlSONET de-scrambler is disabled (on a frame-wide basis only) by asserting DISDSCRM high. The value on the DISDSCRM input is latched-in once every frame at the occurrence.of the frame pulse. If DISDSCRM is set high and latched in during the current frame, the current frame and all subsequent frames will remain scrambled until DISDSCRM is set low. On system reset, the chip will start off in the severely errored frame (SEF) state; RXSEF will be high. The byte de-interleaver will be reset on the occurrence of the first frame pulse from the SDHlSONET frame-detection circuit. The SEF will be removed when two consecutive error-free frames have been received. When errored frames are being received, SEF will be set high after four consecutive errored frames. Again, the SEF will be removed when two consecutive errorfree frames have been received. The FRERR output will show a 25.72 ns wide pulse once every ftame if the 12, 24 or 48 bits in the Al and A2 frame ID bytes (used to recover the SDHlSONET frame boundary) contain one or more bit errors. LOF (loss-of-frame) is declared (RXLOF output) after the chip has been in the SEF state for 3 ms (24 frames), for both SDH and SONET. The LOF state is cleared 1ms after terminating SEF Detect when in the SONET mode, or after only two good consecutive frames, when in the SDH mode. SDH mode is set by asserting the SDH input high. For loss-of-signal (LOS) conditions, the VSC8024 is equipped with a LOS control input. Asserting this input high will result in the propagation of all zeroes down-stream. In this mode, the VSC8024 is clocked by RXPCLKIN. The bit-interleaved parity byte BI will be recalculated before descrambling and compared to its extracted value after descrambling. The BI bit errors will be presented on the B1ERR output as 25.72 ns wide pulses (up to 8 pulses per frame) and aligned at the start of the B I byte of the current frame. Besides calculating the B1 over the entire STM-16lSTS-48 frame, the VSC8024 optionally calculates the BI based on the first STM-41 STS-12 frame interleaved into the STM-16lSTS-48 frame when the PROPB 1ERR input is held high. The value on the PROPB 1ERR input is latched-in once every frame at the occurrence of the frame pulse. A logic' I' latched-in during the current frame will result in a non-modified B ISTS-l2#l in the current frame and in the ones thereafter if PROPB IERR remains high. This calculated B lSTS-12#1 is XORed with the error-mask derived from XORing the extracted BIsTS-48 with the calculated BIsTS-48 over the entire STM-16lSTS-48 frame. The result is inserted into the B1 byte position of the outgoing STM-4ISTS-12 data stream RXOUTA[7:0). This will make the B I error count on the B 1ERR output identical to the B I error count in the first PM53I2. The VSC8024 can also receive byte-wide STM-16lSTS-48 data from a'STM-64/STS-192 Demux Circuit (or for loopback purposes from the VSC8023 byte-wide STM-16lSTS-48 output) on the RXPIN[7:0) data bus. When SELPARIN is asserted high, the 1:8 Demux and the frame recovery circuit are bypassed. An external frame pulse aligned with the first payload byte in every frame has to be provided on the RXFPIN input. Data on RXPIN[7:0) and on RXFPIN is clocked into the VSC8024 on the rising edge of RXPCLKIN. inte~leaved Page ~66 @ VITESSE Semiconductor Corporation G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SOH/SONET STM-16/STS-48 MuxlOemux and Section Terminator IC Chipset Figure 6: VSca024 Functional Timing, Diagram I.. I.. I,. I,. I.. I., I,. I., Iml" 1+ I±H±I·±H+H+flDJffI++..HFE++++3 RXSIN (byte wide) n FRAME PULSE RXCLKOUT I Z1J Z1J Z1J Z1J Z1J DAI I DA21 RXOUTB<7:0> Z1J Z1J Z1J Z1J Z1J DBI I DB21 DB31 DB41 DBSI RXOUTC<7:0> Z1J Z1J Z1J Z1J Z1J DCII DC21 DC31 DC41 DCsl Z1J Z1J Z1J Z1J Z1J RXOUTA<7:0> RXOUTO<7:0> RXFPOUT I I DDlI DA31 DA41 DASI DD21 DD31 DD41 DDS I n .-----------. FRERR RXSEF RXLOF RXOUTA<7:0> BtERR ............... _--........, . .. ---- ...... --- ... ,, , ... _ ........................................ __ .... .-----------" Notes: (1) The correct latency between the KXSlN data-stream input and the KXOUT data-stream outputs is NOT shown. G52129-0 Rev. 2.0 TXSOUT- TXINA<7:O> TXSCLKOUT+ TXSCLKOUT- TXCLKIN TXCLK+ TXCLK- Note: TXlNB<7:0>. TXINC<7:0>. andTXIND<7:0> inputs have been omitted/or simplicity. Figure 8: VSCS023 Data and Clock Block Diagram (Parallel Transmit & Contra-dlrectlonal Mode) VSC8023 PMS3121PMS3SS TXFPOUT TXPOUT[7:0] TXPCLKOUT+/TXCLKIN TXPCLKIN+ TXPCLKIN - ~----------------~ Note: TXINB<7:0>. TXINC<7:0>. and TXlND<7:0> inputs have been omittedfor simplicity. Page 368 e VITESSE Semiconductor Corporation G52129-o Rev. 2.0 Preliminary Datasheet 2.488 Obits/sec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Figure 9: VSCS023 Data Input Timing Diagram TX12CLK TCLKIN V \ TXCLKIN TINAST,! TINAH TpPSU TTPPH TXINA<7:0> TXFPIN<3:0> Table 3: VSC8023 Data InputTimlng TTXCLK VSCS023 high-speed input clock period 401.9 ps TnD 12.86 50 ns DrxCLKIN Transmit data input byte clock period Transmit data input byte clock duty cycle TXINA<7:O> data setup time with respect to TXCLKIN TnD ns inD ns TED % TINAH TXINA<7:O> data hold time with respect to TXCLKIN T INBSU TXINB<7:O> data setup time with respect to TXCLKIN ns TINBH TXINB<7:O> data hold time with respect toTXCLKIN ns TINCSU TXINC<7:O> data setup time with respect to TXCLKlN TINCH TBD TBD ns TlNnsu TXINC<7:O> data hold time with respect to TXCLKIN TXIND<7:O> data setup time with respect to TXCLKIN TINDH TXIND<7:O> data hold time with respect to TXCLKIN TnD ns TXFPIN<3:0> data setup time with respect to TXCLKlN TBD ns TXFPIN<3:0> data hold time with respect to TXCLKIN TllD ns ns Maximum allowable propagation delay for connecting TX12CLK to TXCLKlN G52129-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book ns TED ns Page 369 Preliminary Datasheet 2.488 Gbits/sec SDHlSONET STM·161STS-48 MuxlDemux and Section Terminator IC Chipset Rgure 10: VSC8023 Serial and Parallel Data OutputTlmlng Diagram TXSCLKOUT+ TXSCLKOUT- lXSOUTAIB+ lXSOUTAIB- lXPCLKOUT+ lXPCLKOUT- TXPOUT[7:0]. TXFPOUT T~f M TPs~f M TTXsCLKOur X TTXPCLKOur X 1 1 Note: TX1ICLKOur and TXPCLKOur have not been drawn to scale. Table 4:VSC8023 Serial and Parallel Data Output Timing TTXSCLKOUT TSSKEW T'IXPCLKOUT TpSKEW Serial1i'ansmit clock period Skew between the falling edge ofTXSCLKOUT and valid data on TXSOUTAIB Parallel Transmit clock period Skew between the falling edge ofTXPCLKOUT and valid data on TXPFOUT[7:0] and on TXFPOUT 401.9 ps TIlD 3.215 ps DS TBD ps Note: Duty cycie/orTX1ICLKOUT andforTXPCLKOur is 50% +/- 5% worse case. Page 370 e VITESSE Semiconductor Corporation G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SDHISONET STM-16ISTS-48 MuxlDemux and Section Terminator IC Chipset Figure 11: VSC8023 Facility Loopback Input Timing Diagram TTXSLBCLK TXSLBIN + TXSLBIN - TTXLSU TTXUI. TXSLBCLK+ TXSLBCLK- Table 5: VSca023 Facility Loopback InputTlmlng TTXSLBCLK T1XLSU TTXLSH G52129-Q Rev. 2.0 Serialloopback clock period Serialloopback input data setup time with respect to rising edge ofTXSLBCLK+ Serialloopback input data hold time with respect to rising edge ofTXSLBCLK+ @ 401.9 ps TBD ps TED ps VITESSE 1996 Communications Product Data Book Page 371 Preliminary Datasheet 2.488 Gbits/sec SOH/SONET STM-161STS-48 MuxlDemux and Section Terminator Ie Chipset VSCB024 AC Timing Characteristics Figure 12: VSC8024 Data and Clock Block Diagram (Serial Receive Mode) VSCS024 2.488 Ghz CRU PM53121PM5355 RXSIN+ RXOUTA<7:0> D Q D Q RXSIN- eLK. eLK. RXFPOUT RXSCLKIN+ RXCLKOUT RXSCLKIN - Figure 13: VSC8024 Data and Clock Block Diagram (Parallel Receive Mode) VSC8024 RXPlN[7:0] RXFPIN PM53121PM5355 RXOUTA<7:0> D Q eLK RXFPOUT RXPCLKIN+ RXPCLKIN - Page 372 RXCIKOUT 8 VITESSE Semiconductor Corporation G52129-Q Rev. 2.0 Preliminary Datasheet 2.488 Gbitslsec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Figure 14: VSC8024 Serial and Parallel Data Input Timing Diagram TRXSCLKIN RXSCLKIN+ RXSCLKIN - TRXSSU TRXSH RXSIN+ RXSIN - TRXPCLKlN RXPCLKIN+ RXPCLKIN - TRXPSU TRXPlJ RXPIN[7:0]. RXFPIN Note: RXSCLKlN and RXPCLKlN have 1Iot bee1l draW1I to scale. Table 6: VSC8024 Serial........................ and Parallel...................... Data InputTlmlng ....... ................... ..... ....... ...... :~tW~~E::: TRXSCLKIN ... ........... :::::p#~#,P,~#y::LL . .. ......... LM~ Serial Receive clock period . . . . .. ....!!1!..#!!! : L:~ 401.9 :::(i~!#:: ps TRXSSU Serial Receive input data setup time with respect to rising edge ofRXSCLKIN+ TIlD ps TRXSH Serial Receive input data hold time with respect to rising edge ofRXSCLKIN+ TIm ps TRXPCLKIN Parallel Receive clock period 3.215 DB TRXPSU Parallel Receive input data setup time with respect to rising edge ofRXPCLKIN+ TIID DB TRXPH Parallel Receive input data hold time with respect to rising edge ofRXPCLKIN+ TIlD DB G52129-0 Rev. 2.0 ® VITESSE 1996 Communications Product Data Book Page 373 Preliminary Datasheet 2.488 Gbits/sec SDH/SONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset Figure 15: VSC8024 Data Output Timing Diagram TRXSCLKIN RXSCLKIN+ RXSCLKIN- TRXCLKOUT RXCLKOur<*) TRXCLKOUT RXCLKOUT RXOUTA<7:O> ZO RXFPOUT TSKEWI Note: RXSCLKlN and RXCLKOuP*)have not been drawn. to scale compared to the signals below them. Table 7: VSC8024 Data Output Timing TRXSCLKIN TRXCUCOur TSKBWl TRXVALID Serial Receive clock period Receive data output byte clock period Range in which the rising edge ofRXFPOUT will appear in relation to the falling edge of RXCLKOUT . Time data onRXOUTA<7:0>. RXOUTB<7:O>. RXOUTC<7:O> and RXOUTD<7:O> is valid before and after the rising edge ofRXCLKOUT Pulse width of frame detection pulse RXFPOUT Page 374 .8 VITESSE Semiconductor Corporation 401.9 ps 12.86 us .TIID TBD us us 12.86 us G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbitslsec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Figure 16: VSC8024 Error Data Output Timing Diagram RXCLKOUT RXFPOUT I ~~--~------------------ ,, ,, FRERR -~ TSAjEw2 , BIERR r TSKEW3 SeGond BIERR Pulse Note: The correct latency between RXFPOut and BIER'/{ has not been shown. Table 8: VSC8024 Error Data Output Timing . ... . >f~m~~r TSKEW2 Tpwz TLT TSKEW3 TPW3 G52129-0 Rev. 2.0 .::>HH:p~&~rw##~HHH •• Range in which the rising edge ofFRERR will appear in relation to the falling edge of RXa.KOUT Pulse width of frame error pulse FRERR Latency between the rising edge of RXFPOUT and the rising edge of a BIERR pulse Range in which the rising edge on BIERR will appear in relation to the falling edge ofRXa.KOUT Pulse width of B 1 error pulse BIERR H.M~ .. :. :L~HMit.tH.(i~.:: TB}) 25.72 13.82 25.72 8 VITESSE 1996 Communications Product Data Book DS DS 14.00 lIS TIlD DS DS Page 375 Preliminary Datasheet 2.488 Gbits/sec SDH/SONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset Figure 17: VSC8024 Facility Loopback OutputTlmlng Diagram RXSLBCLK.+ RXSLBCLK.- RXSLBOUT+ RXSLBOUT- TJ TRXSLBCLK X M Table 9: VSC8024 Facility Loopback Output Timing ........................... ........................... ............. ::1t~~~r< TRXSLBCLK Page 376 ~ .... .................. ....................... . ::::::::::::::< :::: ;:;: 4r4~E ..................... :••••..•• :••.•.•.•.•..• :•••••• ·P#~rw~# • .............................. :.......... ......(~#h ·.tiiiii~ ... lIT Power supply CUITCIlt from VIT THD mA ITIL Power supply CUITCIlt from V TIL Tlm mA 1')) Power dissipation THD W Note: Specified with outputs open circuit The combined maximum currents (In, 1m) fOT any part will not exceed '11-1D Watts. VSCB023 Package Pin Description Table 15: TBD VSCB024 Package Pin Description Table 16:TBD G52129-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book Page 379 Preliminary Datasheet 2.488 Gbits/sec SOH/SONET STM-161STS-48 MuxlOemux and Section Terminator IC Chipset Figure 18: 192TBGA Package Drawing (Bottom View) 19.05 1.27TYP 16 --I-~.::).. @@@@@®<:·eee,·::·@ @ @~f - I - - - - - - - r 15 '.' GHl~@@@®®®@@
0.~3 +/- 0.03 Notes: (1) Drawings not to scale. (2) AU unil8 in millimeters. Page 380 8 VITESSE Semiconductor Corporation G52129-0 Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SDH/SONEr STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Application Notes The byte clock (TXCLKI2 and TXCLKIN) on the VSC8023 has been brought off-chip to allow as much flexibility in system-level clocking schemes as possible. Refer to figures 7 & 8 for connection examples. Interconnecting the VSC8023 Byte Clocks (TXCLK12 andTXCLKIN) Contra-Directional Connection: In this mode, the byte clock (TXCLKI2) clocks both the VSC8023 and the PMC devices. It is important to pay close attention to the routing of this signal. The PMC devices are CMOS parts which can have very wide spreads in timing (1 ns-II ns clock in to parallel data out for the PM5355) which utilizes most of the 12.86 ns period (at 77.76 MHz), leaving little for the trace delays and set-up times required to interconnect the devices. The recommended way of routing this clock is to daisy chain it to the PMC device pins and then route it back to the VSC8023 along with the byte data. This eliminates the I-way trace delay that would otherwise be encountered between the data and clock and thus leaves 1.86 ns for the VSC8023 setup time and for variations in trace delays and rise times between clock and data. The trace delay must be kept under 2 ns (allowing an additional 1 ns for variations in rise times and skews) to ensure proper muxing of parallel input data into the VSC8023; reference Table 2. Co-Directional Connection: In the co-directional mode an internal data synchronizing circuit is used to optimize the phase relationship between a supplied TXCLKIN and internal clocks. The TXCLKIN signal needs only to meet setup and hold timing relative to the data stream and frame pulses. Equipment and Facility Loopbacks In order to create an Equipment Loopback, the EQULOOP VSC8024 input is held high. The byte-wide STM-I6ISTS-48 data on the VSC8023 TXPOUT[7:0] outputs is clocked into the VSC8024 RXPIN[7:0] inputs with the TXPCLKOUT clock. A frame pulse aligned with the first payload byte on the TXPOUT[7:0] databus is provided to assure proper alignment. Both the Facility and the Equipment Loopbacks can be enabled simultaneously. It is possible to disable (hold at a logic low) the serial high-speed outputs on the VSC8024 by holding the DISLBOUTS input high. G52129-0 Rev. 2.0 @ VITESSE 1996 Communications Product Data Book Page 381 Preliminary Datasheet 2.488 GbitS/sec SDH/SONET STM-161STS-48 MuxlDemux and Section Terminator IC Chipset Equipment and Facility Loopbacks The diagram below (F'tgure 19) shows how an Equipment and a Facility Loopback are created. When in Facility Loopback mode (FACLOOP is held high) the serial 2.488 Gbls data and clock from the RX optics module is first clocked into the VSC8024 and then fed back into the VSC8023 through TXSLBIN and TXSLBCLK. The FACLOOP input (held high) selects the data from the VSC8024 instead of the data from the 8:1 Mux. The result is a line loopback from the RX optics module back out to the TX optics module. Figure 19: Serial Loopback Mode Block Diagram 2.488 Gbls Dala and Clock to TX Optics Module 2.488 Gbls Data and Clock from RX Optics Module (CRU) VSC8023 - .... VSC8024 ..~ 8:1 MUX I I-Q ) 0 r---+0 Q rmour 0 RXSIN RXSCLKIN '--- TXSLBIN RXSLBOur TXSLBCLK RXSLBCLK TXPOUT[7:0] TXPCLKOur ~ - Q TXFPOur -FACLOOP 311 MHz RXPCLKIN ,---- '-- ..~ ~ r-0 Q RXPIN[7:0] -+,-- '--- 1:8 OEMUX& FR.OEICT. TXSCLKOur '--- 0 Q,....~ 0 RXFPIN .... FRAMBPULSB Q '--- BQULOOP NOlu: (1) All lignab tirawtlas lingle ended instead ofdi1ferential. (2) Oil/able High.speed VSC8024 Oulputa CM/roT Signol OlSLBOUTS NUl" shown. Page 382 e V"ESSE Semiconductor Corporation G52129-Q Rev. 2.0 Preliminary Datasheet 2.488 Gbits/sec SDH/SONET STM-16/STS-48 MuxlDemux and Section Terminator IC Chipset Notice This document contains information on products that are in the preproduction phase of development. The information contained in this document is based on test results and initial product characterization. Characteristic data and other specifications are subject to change without notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing orders. Warning Vitesse Semiconductor Corporntion's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52129-0 Rev. 2.0 ~ VITESSE 1996 Communications Product Data Book Page 383 2.488 GbitsisecSDHISONET STM-161STS-48 Preliminary Datasheet MuxIDemux and Section Terminator IC Chipset Page 384 @ VITESSE Semiconductor Corporation G52129-o Rev. 2.0 VITESSE Data Sheet 2.5 Gbits/sec 16-8it MuffipJexerl Demultiplexer Chipset Features • Serial Data Rate up to 2.5 Gb/s • 16-bit Wide ECL lOOK Compatible Parallel Data Interface • Differential High Speed Data Outputs • Differential or Single-ended High Speed Data and Clock Inputs • On-chip Phase Detector (VS8061 Multiplexer) • Power Dissipation: VS8061: 2.0W(max), VS8062: 1.7W(max) • Standard ECL Power Supplies: VBE = -5.2 volts, V'IT= -2.0 volts • Commercial (0· to 70· C) or Industrial (_40· C to 85· C) Temperature Range • Available in 52-pin Ceramic Leaded Chip Carrier Package or 52-pin Plastic Quad Flat Pack FuncHonalDescripHon The VS8061 and VS8062 are high speed interface devices capable of data rates up to 2.5 Gbls. These devices are fabricated in gallium arsenide using the Vitesse H-GaAs BID MESFET process to achieve high speed and low power dissipation. For ease of system design using these products, both devices use industry standard, -5.2V and -2V, power supplies, and have ECL compatible 110 for parallel data interfaces. Typical applications include telecommunication transmission and instrumentation. VSB061 Multiplexer The VS8061 consists of a 16:1 multiplexer circuit, a phase detector, and a timing circuit which generates a divide-by-16 clock from the high speed clock input. The 16:1 multiplexer accepts 16 parallel single-ended ECL compatible inputs (DO ..DI5) at data rates up to 156Mb1s and bitwise serializes them into a 2.5Gbls serial output (DO/DON). The internal timing of the VS8061 is referenced to the negative going edge of the high speed clock true input (CLK). This clock is divided by 16 and is provided as an output (CLKI6/CLKI6N). The setup and hold time of the parallel inputs (DO .. DI5) are specified with respect to the falling edge of CLK16, so that CLKI6/CLKI6N can be used to clock the data source of DO .. DI5. The on-chip phase detector monitors the phase relationship between the internally generated divide by 16 clock and an externally supplied low speed reference clock input (DCLKlDCLKN). Phase difference between these two clock signals generates an up or down output (U, D) for phase lock applications. The phase detector can be used as part of an external Phase Locked Loop (PLL) to implement a clock multiplication function. In applications where a 2.5 GHz system clock is provided, and the phase detector function is not required, it is recommended to connect one side of the DCLKlDCLKN input to V'IT through a 50 ohm resistor. The U and D output can be left open and unused. VSB062 Demultiplexer The VS8062 consists of a 1:16 demultiplexer and timing circuitry which generates a divide-by-16 clock from the high speed clock input. The demultiplexer accepts a serial data stream input (DIIDIN) at up to 2.5Gbls and deserializes it into 16 parallel single-ended EeL compatible outputs (DO ..DI5) at data rates up to 156 Mbls. The internal timing of the VS8062 is referenced to the negative going edge of the high speed clock true input (CLK). This clock is divided by 16 and provided as an output (CLKI61 CLKI6N). The timing parameters of the parallel data outputs (DO .. DI5) are specified with respect to the falling edge of CLK16, so that CLKI6/ CLK16N can be used to clock the destination of DO.. DI5. G52069-0 Rev. 3.0 @ VrrESSE 1996 Communications Product Data Book Page 385 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Figure 1: VS8061 Block Diagram Output DO r-----lRegisterl-----l/o-__ DON D15 Tuning Generator 1--41---+--.--------1 . . . ....--- CLK16 CLKl6N CLK CLKN Bit Rate Clock Phase Detector DCLK DCLKN >---u >---D Figure 2: VS8062 Block Diagram DI DIN Input D1 Register Parallel Data Outputs Output Registers CLK CLKN Page 386 Tuning 1 - -......- Generator e VITESSE Semiconductor Corporation _ _--I ..........- - CLK16 CLK16N G52069·0 Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset VSB061 Multiplexer AC Characteristics (Over recommended operating range) . . parometer ...................... ta.K ··HClock . . period· •••• ..'" • •••• to tosu tm CLK16, DCLK period ('a.K x 16) Parallel data set-up time (wrt CLK16 faIling edge) Data hold time (wrt CLK16 faIling edge) toe CLK16 duty cycle DCLK (DCLKN) rise and fall times (10%-90%) D(0.. 15) rise and faIl times (10%-90%) CLK16 (CLK16N) rise and fall times (10%-90%) DO (DON) rise and faIl times (20%-80%) ~tr ~tr t" t f ~tr HMlR .tyP. ..• Ma.Ji. .. ............. 400 6.4 2.0 0.5 thIii& . ................. ps 15.6 ns ns ns 40 60 1.5 2.0 0.5 150 % ns ns ns 165 ps "The parts are guaranteed to operate to a maximum frequency of 2.5GHz. Figure 3: Vsa061 Multiplexer Wavefonns High speed ~~ti~~k>~~~J CLK16 (CLK16N) Parallel data clock output 0(0 ... 15) Parallel data inputs DO (DON) High speed differential serial data output Serialized Data NOTE: G52069-0 Rev. 3.0 I56666d Don't care ~ ~----Io ----+1 VITESSE 1996 Communications Product Data Book Page 387 Data Sheet 2.5 Gbitslsec 16-Bit Multiplexer/ Demultiplexer Chipset VS8061 Phase Detector Logic Diagram The phase detector inside the VS8061 compares the phase difference between the internally generated divide-by-16 clock and the DCLK input. If both inputs (CLK16 and DCLK) to the phase detector are in phase, the U and D outputs will both below. If the rising edge ofCLK16 precedes DCLK, a series of pulses with pulse widths proportional to the phase difference will be present at the U output. Conversely, if DCLK precedes CLK16, then a series of pulses with widths proportional to the phase difference will be present at the D output. The other output will remain low. The Phase Detector ignores phase differences for falling edges. This circuitry is useful for implementing a Clock Multiplier Unit (CMU) function with the VS8061. For example, the DLCK can be the system reference clock at the parallel data rate. An external Voltage Controlled Oscillator (VCO) at 16X the frequency of the reference clock can be used as the CLK input for the VS8061. The phase detector outputs (U and D) can then be used by an external integrator to generate an output that controls the VCO. The generated 16X clock from the VCO will be phase-locked to the reference clock. Figure 4: VSS061 Phase Detector Logic Diagram u CLK16 DCLK D Figure 5: Phase Detector Input and Output Waveforms CLK16 DCLK u 0 Page 388 ~ll\ ~ll\ I I I \ \ I ~ll n n e VITESSE Semiconductor Corporation ~ G52069-o Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-8it Multiplexer/ Demultiplexer Chipset VSB062 Demultiplexer AC Characteristics (Over recommended operating range) ... ..... . . . ........ . .., . . . .. .......................................................... ............................... f.atti~iif>:H:l)e#'riPti#ti tax to ;m Oock period'" 400 BYTE CLK16 period AVRSOUT AVHS1N ........ .................................... , ............... ........... ... .............. . ........Mln ... ....1,Ji~....MaxU"lliL.¢pli4i@~F Output voltage swing 0.7 0.9 fuput voltage swing 0.6 0.7 Input voltage rise and fall time (high speed) 0.2 V 1.2 1.5 Output load, 50 Ohm to -2.0V V ACcoupled ns same for all data rates; no worse than sine wave at max speed Notes: 1) Built-in references generator, the high speed inputs are designed/or AC coupling 2) If a high speed input is driven single-ended, a capacitor should be connected between the unused high speed or complement input and Vrr(seejigures 7 and 8). G52069-0 Rev. 3.0 @ VITESSE 1996 Communications Product Data Book Page 391 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Coupling for Inputs Figure 7: AC-Coupllng for DCLI(, DCLKN Inputs • ___ ________________ • ~.!'l!p. ~9~!.l~~ry Vcc=GND -to) :·~f , Vrr : DCLKN ;~~---~--->~ Vn : Vrr =-2V = C1N TYP O.1IJ.F CSE TYP = O.1IJ.F for single ended applications. (Capacitor values are selected for DCLK 155 Mbls.) = DCLK, DCLKN Inputs Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 7 shows the configuration for a single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREP for EeL levels be used for the complementary input. High Speed Clock and Serial Data Inputs It is recommended that all high speed clock and serial data inputs (i.e. CLKlCLKN for the VSS061; DIIDIN and CLKlCLKN for the VSS062) be AC-coupled. Figure S shows the configuration for a single-ended AC-cou- pling operation. In most situations these inputs will have high transition density and little DC offset. However, in cases where this does not hold, direct DC connection is possible. The following is to assist in this application. All serial data and clock inputs have the same circuit topology, as shown in figure S. The reference voltage is created by a resistor divider as shown. If the input signal is driven differentially and DC-coupled to the part, the mid-point of the input signal swing should be centered about this reference voltage and not exceed the maximum allowable amplitude. For single-ended, DC-coupling operations, it is recommended that the user provides an external reference voltage which has better temperature and power supply noise rejection than the on-chip Page 392 8 VITESSE Semiconductor Corporation G52069-O Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-8it Multiplexer/ Demultiplexer Chipset resistor divider. The external reference should have a nominal value as indicated in the table and can be connected to either side of the differential gate. Table 4: High Speed Clock and Serial Data Inputs VS8061 VS8061, VS8062 VS8062 DCLK,DCLKN -1.32V 600mV 1.2V CLK,CLKN -3.5V 600mV 1.2V DI,DIN -3.5V 600mV 1.2V Figure 8: High Speed Clock and Serial Data Inputs Chip Boundary ....... ------ ... - ..... - ......... -- ...... -- .. --- ..... - ... -- - ... -., +) VEE =-5.2V , ...................... -- --_ ... -_ ... - _.. -- -_ ......... - ........ - ....... C 1N TYP = 100 pF CSE TYP =100 pF for single ended applications. (Capacitor values are selected for 01 = 2.5Gb/s.) G52069-o Rev. 3.0 @ VITESSE 1996 Communications Product Data Book Page 393 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Figure 9: Vsa06118062 F (52-Pin LDCC) Pin Diagrams NC NC NC VEE' NC NC NC DO VCC DON NC NC NC 02 03 04 VCC 05 06 VTT 07 08 VS8061 Heat Sink Side VCC De 010 NC -"''''8·It)~Z'''OO~l<: 0,.... ..... ,.....,.. (O'I"'"OZ -I 00>00 -:J> ~O 0 0 0 ::oo8~!2t::l;!~8ffiffio OZZ>OO>OO>I-I-Z 010 09 08 VCC 07 06 VTT 05 04 VS8062 Heat Sink Side VCC NC NC NC VEE" NC ClK CLKN DIN VCC 01 NC NC NC 03 02 NC OOEi08Z~"'OOOOO zz g ~ gzgzzz ~ 0 Heat Sink Up Top View 0 "Heat sink is electrically connected to pin 23 and should be biased to V-FB• Page 394 8 VrrESSE Semiconductor Corporation G52069-0 Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-8it Multiplexer/ Demultiplexer Chipset Figure 10: VS8061/8062 QH (52-Pin PQFP) Pin Diagrams f:J8otllootllo~tlltlloo »z>zz>oo»zz VCC vcc VTT ClK CLKN VEE TEST TEST 0 VTT NC U 0 OClK OClKN DO vcc VS8061QH VTT VTT CLK16 CLK16N 015 014 013 012 011 VCC &l8ottl:S~ttl~_ttlttloo »z>oo>oo»zz vee NC TEST VCC NC NC VEE VTT VTT VTT NC TEST 015 014 013 012 VCC NC NC NC ClK16 ClK16N 00 01 VCC VTT Heat Spreader Up Top View 'Heat spreader is electrically connected to pin 52 and should be biased to Vm . G52069-0 Rev. 3.0 @ VrrESSE 1996 Communications Product Data Book Page 395 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Table 5: VS8061 Pin Description '~~?'~~a~U ... ............ ..... ....... :!'i#:~¥o~!::: .::w.~~ ::110 ::.:P.i.~~ .::::.::::·::·::·:pk~et~#·:: ....................................................... . 38 13 CLK I HS High speed clock truei 37 12 a.KN I HS High speed clock complement 1 9 34 DCLK I ECL Data clock truei 10 35 Da..KN I ECL Data Clock complemenr 34 9 CLK16 0 ECL Clock divide-by-16 true 33 8 a..KI6N 0 ECL Clock divide-by-16 complement 11, 15-20,2225,28-32 1-3,5,6,3842,44,45,47, 48,50,51 D[0:15] I ECL Parallel data inputs 45 19 DO 0 HS 44 17 DON 0 HS Serial data output complement 7 31 U 0 ECL Phase detector output - up frequency 0 ECL Phase detector output - down frequency Serial data output true 8 32 D 1,12,27, 39,51 4,10,18,30, 36,43,49 Vee Most positive supply 2,5,13,14,21, 26,35 7,46 Vrr DCFL negative supply 36,42,43, 46, 49 33 VBB SCFL negative supply 6,40,41,47,48, 50 11,14-16,2022,2426,29,37,52 NC Do not connect, leave open 3,4 27,28 Test Test inputs. Used in factory for testing, connect to VTT through a resistor 52 23 VBB* Heat sink bias, counect to VBE , Can be used single-ended. Page 396 8 V"ESSE Semiconductor Corporation G52069-0 Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Table 6: VS8062 Pin Description l 48 21 CLK I HS High speed clock true 1 47 20 CLKN I HS IDgh speed clock complement 1 44 17 DI I HS Serial data flue 1 45 19 DIN I HS Serial data complement 1 31 8 CLK16 0 ECL Parallel data clock (high speed clock divide-by16) true 30 6 CLKI6N 0 ECL Parallel data clock (high speed clock divide-by16) complement 8-11,15-20,2225,28,29 3,5,31,32,34, 35,39-42, 44,45,47,48, 50,51 D[0:15) 0 ECL Parallel data outputs 1,12,27, 39,51 4,10,18,30, 36,43,49 Vex Most positive supply 2,5,13,14,21, 26,35 7,46 Vn DCFL negative supply 36,42,43, 46,49 33 V BB SCFL negative supply 3,6,32-34,37, 38,40,41,50 1,2,9,1116,22,2427,37,38,52 NC Do not ccmnect, leave open 4,7 28,29 Test Test inputs. Used in factory for testing, cooncet to VTT through a resistor 52 23 V BB• Heat sink bias, connect to VEB Can be wed Single-ended. G52069-0 Rev. 3.0 @ VITESSE 1996 Communications Product Data Book Page 397 Data Sheet 2.5 Gbitslsec .16-Bit Multiplexerl Demultiplexer Qhipset Package Information 52-Pin Ceramic LDCC (F) Package B l t t E 0- - . . . . ... . . . . .. ..... ... ..................... ... #~iiC ..........•. Hmiii(MiiiJM~F . . . .. . . ...... ............. H}li!(¥i#,iM#} .... ..... . . .. ............................. ijjjhi:i#~(¥i#/¥#}': .. ................................. . ..(#(¥WA!#J A 18.54119.56 0.730/0.770 0.41/0.61 0.016/0.024 B 1.0211.52 0.040/0.060 J 2.0312.79 0.080/0.11 0 C* 15.49/16.51 0.610/0.650 0.003/0.009 15.24TYP 0.600TYP K* L 0.0910.24 D* E 4.57/5.34 0.180/0.210 1.27TYP 0.050TYP M 27.69130.22 1.090/1.190 N 0.36/0.56 0.01410.022 0 1.7511.90 0.069/0.075 * At package body. Notes: 1) Drawings not to scale 2) Packages: Ceramic (alumina); Heat Sinks: Copper Tungsten; Leads: Alloy 42 with gold plating. @ VrrESSE Semiconductor Corporation G52069-0 Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset 52 Pin PQFP (QH) Package F G .iiemH 39 8 H 27 13 26 14 mm •• i Tot> A 2.35 MAX D 2.00 +.10/-.05 E 0.35 ±.05 F 17.20 ±.25 G 14.00 ±.10 H 17.20 ±.25 I 14.00 ±.10 J 0.88 +.15/-.10 J1 0.80 +.15/-.10 K 1.00 BASIC L 5.84 ±.50 DIA. A K A ~=t-~~I'lI'I'lI'I1II" STANDOFF rO.25 MAX. -t t [0.102 MAX. LEAD COPLANARITV NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. G52069-Q Rev. 3.0 E 8 VITESSE 1996 Communications Product Data Book Page 399 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Thermal Considerations The VS8061 and VS8062 are available in ceramic LDCC and thermally enhanced plastic quad flatpacks. These packages have been enhanced to improve thermal diSsipation through low thermal resistance paths from the die to the exposed surface of the heat spreader. The thermal resistance of the two packages is shown in the following table Table 7: Thermal Resistance Theanal resistance from junction to case. 1.3 2.1 Theanal resistance from case to ambient still air including conduction through the leads. 18.5 30.0 0C/W 0C/W Thermal Resistance with Airflow Shown in the table below is the thermal resistance with airflow. This thermal resistance value reflects all the thermal paths including through the leads in an environment where the leads are exposed. The temperature dif- ference between the ambient airflow temperature and the case temperature should be the worst case power of the device multiplied by the thermal resistance. Table 8: Thermal Resistance with Airflow :Y::(i.iife~~iiilI~t)y> ••..•••••.•••••• 24 °CIW 200lfpm 15.9 14.9 21 0C/W 300 Ifpm 14.2 500lfpm 13.3 19 15 OCIW 0C/W Thermal Resistance with Heat Sink The determination of appropriate heat sink to use is as shown below, using the VS8061 in QH package as an example. Figure 11: Vsa061 In QH Package Page 400 @ VITESSE Semiconductor Corporation G52069-0 Rev~ 3.0 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset The worst case temperature rise from case to ambient is given by the equation: where: eSA Theta sink to ambient e cs Theta case to sink TA(MAX)Air temperature, user supplied (typically 55° C) TC(MAXl Case temperature (85°C for Industrial range) ATTc-TA P(MAX) Power (2.0 W for VS8061) IfTA = 55° C and e cs (user supplied) is typically 0.6° CIW, 9 SA = (85 -2W 55)OC _ 060C/W . 9SA = 14.4°C/W Therefore, to maintain the proper case and junction temperature, a heat sink with a eSA of 14.4° CIW or less must be selected at the appropriate air flow. Note: the heat spreader is tied to VBEin both the VS8061 and VS8062. G52069-0 Rev. 3.0 @ Va-ESSE 1996 Communications Product Data Book Page 401 Data Sheet 2.5 Gbits/sec 16-Bit Multiplexer/ Demultiplexer Chipset Figure 12: Data Eye From Serial Output of VS8061 In QH Package (DOIDON) 1.~.· ........... :...... T. ·... :............ '" ........::::"::.... . .. ;. .... :........ !.... "........ :........ ; .... , ., ..:.: ... . A!' .... :. . ................... . .mL.-.. . . ). _. .L._..:..___~ ____~.. .-S~. ~'9ll-:' .__.... __ ................. ~..... ~'!JJ.~..ft\l.. J.. _.~~,_..~ 'l!i:..~.J~ Amplitude: 200mVldiv Time Scale: 50 psldiv Data Rate: 2.5 Gbls Figure 13: Measurement Setup 16 Channels at 155 Mbls 2.5 Gbls -1 PRB Data "- DO D1 1:16 De·serializer I I I D15 . I I . Bit Error Rate Tester DO D1 I I I DO VS8061 t DON I-D15 D TEKCSA803 Signal Analyzer t Page 402 ~ V"ESSE Semiconductor Corporation G52069'() Rev. 3.0 Data Sheet 2.5 Gbits/sec 16-8it Multiplexer/ Demultiplexer Chipset Ordering Information The order number for this product is formed by a combination of the device number, package type, and the operating temperature range. VS80XX -'1 OevlceType _ _ _ _ _ _ _ VSS061 - 2.5 Gbls 16-bil Multiplexer VSS062 - 2.5 Gbls 16-bil Demultiplexer Fe l_. . T.......... FC: 52 Pin Ceramic Leaded Chip Carrier (LOCC). O' C ambient to +70' C case FI: 52 Pin Ceramic Leaded Chip Carrier (LDCC). -40' C ambient to +S5' C case QH: 52 Pin Plastic Quad Flat Pack (PQFP). O' C ambient to +85' C case Notice Vitesse Semiconductor COlporation reserves the right to make changes in its products, specifications or other infonnation at any time without prior notice. Therefore the reader is cautioned to confinn that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitease product. Warning Vitease Semiconductor CotpOration's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52069-0 Rev. 3.0 ® VITESSE 1996 Communications Product Data Book Page 403 2.5 Gbitslsec 16-8it Multiplsxer/ Demultiplsxer Chipset Page 404 e vrrESSE Semir;onductor Corporation Data Sheet G52069-o Rev. 3.0 VITESSE Advanced Product Information STM-16ISTS-48 16: 1 Multiplexer with Integrated Clock Generation Features • 16:12.488 Gb/s Multiplexer • Differential High Speed Data Output • Integrated PIL for Clock Generation No External Components • Power Dissipation: 2.8 W(max) • Standard EeL Power Supplies: VEE = -5.2V Vu=-2.0V • 16-bitWide, Single-ended, EeL lOOK Compatible Parallel Data Interface • Commercial (0' to 85° C) Temperature Range • 155.52 MHz Reference Clock Frequency • Available In 52-pin Plastic Quad Flat Pack Functional Descrip#on The VSC8063 is a high speed multiplexer designed for STM-161STS-48 data rates at low power dissipation. For ease of system design, it uses industry standard, -5.2V and -2V, power supplies and has EeL-compatible I/O for parallel data interfaces. The VSC8063 provides an integrated solution for SDHlSONET transmission and instrumentation systems. The VSC8063 consists of a 16:1 multiplexer circuit and a clock multiplier unit. The 16:1 multiplexer accepts 16 parallel single-ended EeL compatible inputs (DO.. D15) at data rates of 155.52Mb1s then bitwise serializes the data word onto a 2.488Gbls serial output (DOIDON). The internal timing of the VSC8063 is referenced to the negative going edge of the 155.52 MHz clock true input (REFCLK). A divided-by-16 clock output is also provided (CLKl61CLKl6N). The setup and hold time of the parallel inputs (DO ..D15) are specified with respect to the falling edge of CLK16, so that CLKl61CLKl6N can be used to clock the data source of DO ..D15. VSCB063 Block Diagram Output Register ' - - - - DO A--DON > CLK16 CLK16""----..,, Clockl16 CMU x16 REFCLK REFCLKN G52134-0, Rev. 1.0 Timing GeneIll10r ~ Bit Rate Clock VITESSE 1996 Communications Product Data Book Page 405 STM-16/STS-4B 16:1 Multiplexer with Integrated Clock Generation Advanced Product Information Table 1: VSC8063 Multiplexer AC Characteristics (Over recommended operating rangriJ Figure 1: VSC8063 Multiplexer Waveforms CLK16 (CLK16N) Parallel data clock output 0(0 ... 15) Parallel data inputs REFCLK (REFCLKN) Reference clock input l~~(_J-- DO (DON) High speed differential serial data output Serialized Data NOTE: Page 406 4 mil@-Don't care 14-----10 - - - - + 1 ® VrrESSE Semiconductor Corporation G52134·0, Rev. 1.0 Advanced Product Information STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation Absolute Maximum Ratings(1) Power Supply Voltage (VTT) .............................................................................................................. -3.0V to O.5V Power Supply Voltage (VaJ .................................................................................................. VTT + 0.7V to -7.0V Input Voltage Applied (VECLIN) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -2.5V to 0.5V Output Current, lOUT (DC, output HI) ......................................................................................................... -50 rnA Case Temperature Under Bias (Tc) .................................................................................................... -55· to 125·C Storage Temperature (TSTO) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• _65· to 150·C Notes: (1) Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Vrrmust be applied before the magnitude of any input signal voltage (I~J, IVH.SIJ) can be greater than IV7T " O.5V1 Recommended Operating Conditions Power Supply Voltage (VTT) ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• -2.0V±5 % Power Supply Voltage (VaJ ................................................................................................................... -5.2V±5 % (n ................................................................................. (Commercial) O· to 85°C Operating Temperature Range* * Lower limit of specification is ambient temperature and upper limit is case temperature. G52134"O, Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 407 STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation Advanced Product Information DC Characteristics Table 2: ECl Inputs and Outputs (Over recommended operating conditions with internal VREF, Vcc =GND, Output load =50 ohms to -2.0V) Note: Differential EeL output pins must be terminated identically. Table 3: Power Dissipation (Over recommended operating conditions, VcC= GND, outputs open circuit) Power supply cummt from VEB Power supply cummt from Vrr Power dissipation 370 450 mA 140 170 mA 2.3 2.8 w Table 4: High Speed Output Specifications (Over recommended operating conditions, Vcc =GND, Output load =50 ohm to -2.0V) •HH. ............................... ••• ::HColUlitiDn'.·::. • ::········ ••....................................... HH.HHl)~~;H ••....... . Output load, 50 Ohm to -2.0V Output voltage swing Table 5: Clock Multiplier Unit Performance RCd OCd RCf MRC ~itter Page 408 Reference clock duty cycle CLK16 duty cycle Refereuce clock frequeru::y Refereuce clock frequency range RS. ou1putjitter (12 KHz to 20 MHz) 45 55 45 55 e VITESSE Semiconductor Corporation % MHz 155.52 -30 % +30 ppm 0.01 DI.tMS G52134-0, Rev. 1.0 Advanced Product Information STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation Coupling for Inputs Figure 2: AC-Coupllng for REFCLK, REFCLKN Inputs • ___ 9..h!R ~~~!:I~~I)'________________ • Vcc=GND -E) :RII = 1k.n (Approx.) , CIN TYP = 0.1J.tF CSE TYP 0.1 J.tF for single ended applications. (Capacitor values are selected for REFCLK = 155.52 MHz) = DCLK, DCLKN Inputs Internal biasing will position the reference voltage of approximately -1.32V on both the true and complement inputs. This input can either be DC-coupled or AC-coupled; it can also be driven single-ended or differentially. Figure 3 shows the configuration for single-ended, AC-coupling operation. In the case of direct coupling and single-ended input, it is recommended that a stable VREF for ECL levels be used for the complementary input. G52134-0, Rev. 1.0 Ql) VrrESSE 1996 Communications Product Data Book Page 409 STM-16ISTS-48 16:1 Muftiplexer with Integrated Clock Generation Advanced Product Information Figure 3: VSca063QH (52-Pin PQFP) Pin Diagrams fu8ottloottlo~ttlttloo »z>zz>oo»zz Top View Heal Spreader Up VCC VCC TEST TEST VEE VTT TEST TEST VTT VTT CLK16 CLK16N 015 014 013 012 011 VCC NC NC NC REFCLK REFCLKN DO VCC VTT "Heat spreader is electrically connected to pin 52 and should be biased to V"", Table 6: VSC8063 Pin Description 2,5,13,14,21, 26,35 Vrr 6,7,8,40,41, 47,48,50 NC 3,4 Test Page 410 ~ VrrESSE Semiconductor Corporation G52134-0, Rev. 1.0 Advanced Product Information STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation Package Information 52 Pin PQFP (QH) Package Drawings F ar.t~ .. A 39 8 H 27 13 26 14 mm :::··:·TdL:::···· 2.35 MAX D 2.00 +.10/-.05 E 0.35 ±.05 F 17.20 ±.25 G 14.00 ±.10 H 17.20 ±.25 I 14.00 ±.10 J 0.88 +.15/-.10 J1 0.80 +.15/-.10 K 1.00 BASIC L 5.84 ±.50DIA. - 1100TVP A 100lYP -l~ K ~=-IIIIIf"Jllf"Jllfllf"" NOTES: Drawing not to scale. Heat spreader up. All units in mm unless otherwise noted. G52134-0. Rev. 1.0 -It- STANDOFF t ( COPLANARITY 0.102 MAX. LEAD E 8 VrrESSE 1996 Communications Product Data Book Page 411 STM-16/STS-4B 16:1 Muftiplexer with Integrated Clock Generation Advanced Product Information Thermal Considerations The VSCS063 is available in a thermally enhanced plastic quad flatpack. This package has been enhanced to improve thermal dissipation through a low thermal resistance path from the die to the exposed surface of the heat spreader. The thermal resistance is shown in the following table: Table 7: Thermal Resistance Sea-lOO Thenna1 resistance from case to ambient with 600 Linear Feet per Minute of airflow 29 °CIW 26 °CIW 22 °CIW 20 °CIW Thermal Resistance with Heat Sink The determination of appropriate heat sink to use is as shown below, using the VSCS063 in QH package as an example. Figure 4: VSC8063 in QH Package The worst case temperature rise from case to ambient is given by the equation: where: BSA Theta sink to ambient Bcs Theta case to sink TA(MAX)Air temperature, user supplied (typically 55° C) TC(MAX) Case temperature (S5°C) ATTeTA P(MAX) Power (2.S W for VSCS063) Page 412 @ VITESSE Semiconductor Corporation G52134-0, Rev. 1.0 Advanced Product Information STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation IfTA = 55 C and 9cs (user supplied) is typically 0.6 CIW, 0 0 9 SA = (85 - 55)OC _ 0 60CIW 2.8W 9SA . = 10.1°CIW Therefore, to mllintain the proper case and junction temperature, a heat sink with a 9SA of 10.1° CIW or less must be selected at the appropriate air How. Note: the heat spreader is tied to VREin the VSC8063. G52134-0, Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 413 Advanced Product Information STM-16ISTS-48 16:1 Multiplexer with Integrated Clock Generation Ordering Information The order number for this product is formed by a combination of the device number, package type, and the operating temperature range. VSC80XX .QH DevlceType _ _ _ _ _ _ _....JI VSC8063 - 2.488 Gbls 16-bit MuHiplexer l. _.n'IT........... QH: 52 Pin Plastic Quad Flat Pack (PQFP), 00 C ambient to +85 0 C case Notice 1bis document contains information about a new product during its fabrication or early sampling phase of development. The infonnation in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confinn that this datasheet is current prior to design or order placement Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 414 @ VITESSE Semiconductor Corporation G52134-O, Rev. 1.0 VITESSE Advanced Product Information 10 Gbits/sec 16-8it MuxlDemux for STS-192 and STM-64 Applications Features • Performs 16:1, 1:16 MuxlDemux Between 10 Gb/s High Speed Signal and 16622 Mb/sec Low Speed Signals. • Intemal Input Terminations • Industry Standard -2.0V and -5.2V Power Supplies • VSC8071 is a 16:110 Gb/s Multiplexer with an Integrated Phase-frequency Detector • son Output Drive Capability and Impedance • High Performance Module • VSC8072 is a 1:16 10 Gb/s Demultiplexer Matched Outputs Typical System Block Diagram PU PO t t X16 " FRAME , PROCESSOR 1---__-+1 '------' CLKl16 ~j:l ~ ~ 8071 0 t X16 8072 I-: -:" \.~:-:-:-.I PRb~~~iOR ~~ CLKl16 10 GHzClk General Description The Vitesse 10 Gb/s multiplexer/demultiplexer chipset is intended to perform serialization and de-serialization between 622 Mb/s and 10 Gb/s rate bit streams. The devices are packaged in a custom multilayer connectorized module to provide an environment compatible with 10 GHz clock rates. VSC8071 Functional Description The VSC8071 10Gb/s multiplexer integrates a 16:1 multiplexer with synchronous timing control together with a phase detector. The phase detector can be used with an external loop filter and VCO to generate the bit rate clock. The ECL compatible parallel data inputs (DO•• DlS) and parallel data rate clocks (CLKI611CLKI6IN) are provided with on chip 50 ohm terminations to VIT. The bit rate clock (CLKI) input is internally terminated with a 50 ohm termination to Vcc. The serial data outputs (DO, DON) are back terminated with on-chip 100 ohm resistors. ECL compatible divided clock (CLKI60/CLKI60N) is provided and should be externally terminated with 50 ohm resistors to Vrr . VSC8072 Functional Description The VSC8072 IOGb/s demultiplexer integrates a 1:16 demultiplexer with synchronous timing control. Serial data inputs (DIIDIN) and bit rate clock input (CLK!) are internally terminated with 50 ohm termination to V cc. The deserialized data outputs (QO ••• QlS) and divided clock (CLKI60/CLKI60N) are ECL compatible outputs and should be terminated in 50 ohms to VTI' G52147-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 415 10 Gbits/sec 16-8it MuxlDemux Chipset for STS-192 and STM-64 Applications Advanced Product Information Figure 5: VSC8071 Functional Block Diagram DOO D01 DO DQ DON D16 ClK160 ClK160N ClKI PHASE DETECTOR ClK1S1 ClK161N Figure 6: VSCS072 Functional Block Diagram QOO Q01 DI{> DIN . Q16 ClK18 CLK18N ClKl Page 416 ® VITESSE Semiconductor Corporation G52147-o Rev. 1.0 Advanced Product Information 10 Gbits/sec 16-8it MuxIDemux for STS-192 and STM-64 Applications VSCB071 AC Characteristics (Over recommended operating conditions) tDQR, tooF Serial data rise and fall time 35 tcul6R., tcucl6F CLKl60 rise and fall times 200 300 pS See figure 5. pS See figure 5. tog Data setup to a.Kl60 TBD pS too Data hold from CLK160 TBD pS tpEI CLK161 to CLK160 delay TBD pS PUIPD =zero on-chip pn.se error fpm CLK161 to CLK160 delay TBD pS PUIPD =zero on-chip pn.se error CLKIperiod 100 pS a.K161 period 1.6 nS tcLKI tcLKt61 Single ended a.K161, differentially driven CLK161, Rgure 7: VSC8071 AC Timing Wave10nns tcua60 _ _ _ _~ CLK160 Low .peed clock output D(O... 15) ParaUel d8Ja input. CLK161 low .peed c/orX input DOIDON High .peed dlffer_l.erlal d8Ja output ---------~~--I=-=====SeriaJ~ I...--Data NaTE: I?QS(S(2Sa =Don'tcare G52147-0 Rev. 1.0 ~ tcuax16 V"ESSE 1996 Communications Product Data Book -[ • Page 417 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux Chipset for STS-192 and STM-64 Applications VSCB072 AC Characteristics (Over recommended operating conditions) See figure S. Rgure 8: VSC8072 AC Timing Waveforms TBD Page 418 8 VlTESSE Semiconductor Corporation G52147-0 Rev. 1.0 Advanced Product Information 10 Gbits/sec 16-8it MuxIDemux for STS-192 and STM-64 Applications Figure 9: Parametric Measurement Information Output Rise and Fall Time Parametric Test load Circuit Vee Serial Output load son Zo=son Zo=son G52147-0 Rev. 1.0 @ ECl Output load Vee son VITESSE 1996 Communications Product Data Book Page 419 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux Chipset forSTS-192 and STM-64 Applications DC Characteristics (Over recommended operating conditions) Table 2: ECl Inputs/Outputs. i#T:«~¥ ·.:P~i,fj'iR@#H:ii~i# ..ijpMQ.iHvni#. ./¢Q1.#liit.iP~ son to VIT Load son to V'IT Load V OH Output HIGH voltage -1100 -700 mV VOL Output LOW voltage Input HIGH voltage Input LOW voltage Input Swing Input HIGH current Input LOW current V IT -17S0 mV -1100 -700 mV VIT -lS40 mV 32 ·mA VIN 9 mA VIN Vm V IL AV1N 1m IlL 400 mV =-70OmV, VIT =-2.1 V =-17SOmV, V IT =-2.1 V Table 3: High-Speed Outputs (VSC8071) VOH VOL loL loH Output HIGH voltage Output LOW voltage Output Low Current Output High Current -130 -100 -70 mV ExternalSOO to VCC -1100 -900 -7S0 mV ExternalSOO to V CC 23 mA 3 mA Table 4: High-Speed Data Inputs (VSC8072) . . . . . , .................. ", . ......... , ................... .............................. , .... . .................................................. ,............ ............... :.f~i#jw~ji .P~$~#Pii##» Amplitude Input Voltage " Mi#~#.Miii -2.0 • Hp~itL¢~rt4!##~F 1.0 2.0 V -o.S 1.0 V Note: 1) Reference voltage in a single ended application must be±40mV from the mean input swing given AVIN = 750 mY. and ± 100mVfrom the mean input swing given AVIN =lV. Table 5: High-Speed Clock Inputs Input Swing - single ended VINDC Page 420 DCValueofCLKI @ 0.7S -1.8 V +1.8 VITESSE Semiconductor Corporation V G52147-o Rev. 1.0 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux for STS-192 and STM-64 Applications Table 6: Power DIssipation ECL Power Supply Voltage, (VEE> ................................................................................................ -7.0 V to +0.7 V v IT - Termination Voltage (ECL Inputs) ....................................................................................... -2.5 V to +0.5 V VTI _Termination Voltage (CLKI) ................................................................................................. -2.5 V to +0.5 V DC Input Voltage (Low-speed inputs) ................................................................................................. VIT - 2.5 V to +0.5 V DC Input Voltage, (CLK!) ...............................................................................................V c - 2.0 V to Vc + 2.0 V DC Input Voltage, (DI) .................................................................................................................. -2.5 V to +0.5 V Case Temperature Under Bias ........................................................................................................ -55 0 to +125 °C Storage Temperature ................................................................................................................... -65 °C to +150 °C Recommended Operating Conditions Power Supply Voltage, (VEB) ............................................................................................................... -5.2 V ±..5% Termination Supply Voltage, (VIT) ...................................................................................................... -2.0 V ±..5% Operating Temperature Range, (T) (2) ........................................................................................... 0 °C to + 70 °C Notes: (I) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Lower limit is ambient temperature and upper limit is case temperature. (3) CAUTION: Do not apply V1T prior to VEE G52147-Q Rev. 1.0 @ VrrESSE 1996 Communications Product Data Book Page 421 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux Chipset for STS-192 and STM-64 Applications ---- Figure 10: 10 Structures Vee r~~- -V~ - - - - - =~ ---1"0 vee I CP24mA 1. VEE MUX IDgb-8peed Output Buffer I I I I 50n elKI [:]_ _1 . . . - _ VEE • Appro:xinuIU Values I IDgb-8peed Clock Input Buffer Page 422 @ VITESSE Semiconductor Corporation G52147-O Rev. 1.0 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux for STS-192 and STM-64 Applications Figure 11: 10 Structures Cant ,------------------------------------, Ve Vee : I SOO 10pF 01 C I DIN DMUX mgh-8peed Data Input Buffer PU PO MUX Phase-Detector Output Circuit G52147-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 423 Advanced Product Information 10 Gbits/sec 16-8it MuxlDemux Chipset for STS-192 and STM-64 Applications Table 7: VSC8071 Pin Description •••.. •••..••••.••• y.....•.•• : / DOO:15 CLKI Vc CLKI6I, CLK16IN DO,DON, CLK160, CLK160N PU,PD Vee VEE Vrr Vbb ·.~K. ~ ........................................................... INPUT-ECL Parallel data presented to this port is clocked into the device. The timing of this data is relative to the CLKI60 oulput. INPUT - HIGH SPEED CLOCK Bit rate input clock. This clock is tenninated in 50 Ohms to Vc, and is AC coupled onchip. POWER SUPPLY (Common mode termination voltage for CLKI input) (Typically grounded) INPUf- DIFFERENTIAL EeL Parallel data rate clock. OUTPUT - DIFFERENTIAL HIGH SPEED Serial data output stream. DO and DON should be terminated with 50 Ohms to ground at the load. OUTPUT - DIFFERENTIAL ECL This is the bit rate clock divided by 16. OUTPUT - ANALOG Phase detector oulputs. GROUND POWER SUPPLY (-5.2 V NOM) POWER SUPPLY (-2.0 V NOM) Tennination supply for the single ended ECL inputs. ECL Reference Voltage (typ. -1.32V) Table 8: VSCB072 Pin Description ·. ··.·.·N~~. · · · · DI,DIN CLKI Vc QOO:15 CLKI6, CLK16N Vee VEE VD Page 424 ·n .... INPUT - HIGH SPEED DIFFERENTIAL (HS) Serial data input stream. These inputs are internally tenninated. If a single ended signal is used the other input should be capacitively de-coupled to VCO iNPUT - HIGH SPEED CLOCK (HS) Bit rate clock input. POWER SUPPLY (Termination voltage for CLKI input) (Typically grounded) OUTPUT-EeL De-serialized data outputs. The outputs are updated at 1/16 of the bit rate. OUTPUT - DIFFERENTIAL EeL This is the bit rate clock divided by 16. GROUND POWER SUPPLY (-5.2 V NOM) POWER SUPPLY (Common mode termination voltage for DI,DIN inputs) (Typically grounded) ~ VITESSE Semiconductor Corporation G52147-o Rev. 1.0 Advanced Product Information 10 Gbitslsec 16-8it MuxlDemux for STS-192 and STM-64 Applications Package Information VSC807118072 Module Heat Sink Side ,.800 I 1.000 Pin 42 I 0.330 0-IIOX.100D'EEP RFI (4PLCS) 0.100 REF 0 + RF2 RF3 0 RF4 0.330 Pin 1 Module Side View 0.380 0.189 G52147-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 425 Advanced Product Information 10 Gbits/sec 16-8it MuxlDemux Chipset for STS-192 and STM-64 Applications Table 9: Package Pin Table ..................... .. ....................... VSC8072 ............... ....VSC807.1 ..... ....... .... .............. ....... PiNtL PIN# ....................... .. ..................... VSC8071 .... ................. .. ..... .......... .·VSC8072 ....................... ifNi ·.VSC8071 .. ..................... .•HVSC80n .................. 1 Gnd Gnd 17 DlO Q05 33 000 Q15 2 Ve Ve 18 009 Q06 34 Vee Vee 3 Vd Vd 19 008 Q07 35 Clk16i NC 4 Gnd Gnd 20 Gnd Gnd 36 Vtt Vcca 5 Vbb NC 21 Vtt Vcca 37 Clk16in NC 6 CIkl60 CIk160n 22 Vee Vee 38 Pd Pd 7 Vtt Vcca 23 Gnd Gnd 39 Pu Pu 8 Clkl60n Clk16 24 007 Q08 40 Ve01· VeOl" 9 Vee Vee 25 006 Q09 41 Ve02" VC02* 10 015 QOO 26 005 QI0 42 Gnd Gnd 11 014 QOl 27 004 Q11 12 013 Q02 28 Gnd Gnd 13 D12 Q03 29 Vee Vee RFI NC NC 14 Vee Vee 30 003 Q12 RF2 CLK! CLKI 15 Gnd Gnd 31 002 Q13 RF3 DO DIN 16 D11 Q04 32 001 Q14 RF4 DON DI Note (1) .. Not Currently Implemented Page 426 @ VITESSE Semiconductor Corporation G52147-0 Rev. 1.0 Advanced Product Information 10 Gbits/sec 16-Bit MuxlDemux for STS-192 and STM-64 Applications Figure 12: Setup #1 Typical Test Configuration Error Deta,ctor -... Cf---!--t--;d;,----O DATA INPUT "1---0 CLOCK INPUT Generalor 1) Phase shifter need for testing DREF low speed interface should be >-+-------i--L...HmN 1SOOps conlnuous 2) All clld6's should be lermlnated because f1is yields a reaftslic ground environmenl '-----CJ DIRECT TRIGGER HIGH SPEED SCOPE TYPICAL TEST CONFIGURATION G52147-0 Rev. 1.0 @ VITESSE 1996 Communications Product Data Book Page 427 Advanced Product Information 10 Gbits/sec 16-8it MuxlDemux Chipset for STS-192 and STM-64 Applications Ordering Information The order number for this product is formed by a combination of the device number, and package type. VSC80XX DevieeType _ _ _ _ _ _ _--'1 VSCB071/B072 - 10 GbHs/sec 16-bit MuxlDemux Chipset xx lp_~ VSCB071/B072 Module Notice This document contains information about a new product during its fabrication or early sampling phase of development. The information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cantioned to confirm that this datasheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page.42B @ VITESSE Semiconductor Corporation G52147-o Rev. 1.0 VITESSE Preliminary Data Sheet 155.52 Mb/s Clock and Data Recovery Units Features • Recovers Clock and Data at STS-3 (155.52 Mb/s) Data Rate. • EeL or Psuedo ECL (PECL) Differential Inputs and Outputs. • No External Components Required. • Available in One-channel (VSC8l0l) or Eight-channel (VSC8l02) Versions. • Maximum Power Dissipation: VSC81Ol: 400mW, VSC8l02: 3W, • Recovers Data from NRZ or NRZI Data Streams. • Single 2V Power Supply • No Output Clock Drift in Absence of Data Transitions Once Lock is Acquired. • Available in 28PLCC (VSC8l0l) and 100PQFP (VSC8l02) Functional Description The VSC810l and VSC8l02 are clock and data recovery units for STS-3 (155.52 MbIs) applications. They implement the complete clock and data recovery functions and require no external components. The one-channel device, VSC8101, accepts serial data in NRZ or NRZI format and re-times the data using a sampling clock extracted from the input data stream. The recovered clock (RCLK+I-) and re-timed data (RDAT+I-) are presented at the serial output ports, aligned such that the falling edge of the recovered clock (RCLK+) coincides with the center of the data eye (see figure 4). The VSC8102 is an octal version of the VSC8101. A single reference clock input (REFCK+I-) at the STS-3 data rate (155.52MHz) is required for either device. The data and reference clock inputs, and the recovered data and clock outputs are differential ECL levels referenced to the Vee supply. Only one supply, +2V or -2V, is required for operation. Both the VSC8101 and VSC8102 employ a digital clock extraction technique, and do not contain a conventional PLL. As a result, the spectrum of the jitter in the recovered clock and data is non-Gaussian. Peak-to-peak jitter of RCLK+1- is ± 400 ps or less. The data input rate to the devices is required to be within ± 30 ppm from the reference clock frequency. The devices have data input jitter accommodation up to 3.2ns, half the data period. The VSC81 Oland VSC81 02 also provide an input which control the loop bandwidth of the clock extraction function. Tracking Frequency Bandwidth Control The tracking of the recovered clock and data to the frequency variation of the input data stream can be adjusted in the VSC8l01 and VSC8l02. In particular, the FILTERO input controls the degree to which the internal clock can track the input data frequency. The effect is equivalent to controlling the loop bandwidth of a conventional PLL-based clock recovery system. Equivalent bandwidths of 150 KHz and 10 KHz can be selected. The FILTERO input truth data is shown in the AC Characteristic Table. Jitter Tolerance The VSC8101 and VSC8102 are designed to meet the BellcoreGR-253-CORE, section 5.6.2.2.2 Jitter Tolerance specification. Figure 1: JitterTolerance Mask for STS-3 JilIef'Ampluda (UIP,~ ~ 1.5 0.15 ~~w~oo,-~~~I'-~a~~'~~!~~-~~~ G520B7-0 Rev. 1.3 @ V"ESSE 1996 Communications Product Data Book Page 429 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Figure 2: VSC8101 Block Diagram SDAT+ SDAT- REFCK+ REFCKFllTERO :::::::::::::;+=::::::::::~OD~~;a~r----------- r;:;J Rellmer r I Y Dci9101lckai F~ -------------'-- -------- RClK RClK- '-----' ---------------~ Figure 3: VSC8102 Block Diagram SDAT1 + SDAT1- ==========:;~======:;;f~~~==========RDM1+ I>RDAT11-_ _ _ _ _ _ RClKl + 1>------- RClKlSDAT2+ SDAT2- ::::::::=f~=;~::==:::::;~t;;-~------RDAT2+ 1>--..,..----- RDAT2- ~========= RClK2 + I>- RClK2- • =======!~~+=======:::::f~~===== I>- RDAT8 + RDAT8- 1-:::::::::::= RClK8 + I> RClK8- Page 430 8 VITESSE Semiconductor Corporation G52087-0 Rev. 1.3 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet VSC81 01181 02 AC Characteristics (Over recommended operating range .......................... Parameter •••••• ......................... tcLK tocYC •••• •••• .... Typ .•••••• ... REFCK+/- Input Clock periodV ) SDAT +/- Input data period tcLK - 6.43 Mitt .17iiUB - DB tCLK + 30 ppm - 30 ppm -30 - +30 ppm tcnc SDAT+/- Input Rate Difference with respect to REFCK+/REFCK+/- Duty Cycle 40 - 60 % tDH Recovered Data hold time from falling edge of Recovered Clock(2) 2.5 - 3.9 DB fog Recovered Data setup time to falling edge of Recovered Clock(2) 2.5 - 3.9 DB ,Hnc taCH RCLK+/- Recovered Oock Output High Pulse Width 2.6 - - DB ~CL RCLK+/- Recovered Clock Output Low Pulse Width 2.6 - DB RCLK+I- Recovered Clock Period SDAT+/- Input Jitter Accommodation (DC to 20 MHz) Peak-to-peak Lock Acquisitioo Time P) 6.0 - 6.S DB - - 3.2 DB - - 5.0 J.I.s - - 150 10 KHz 400 ps TBD ps 1.2 DB 1.2 DB ~CYC tDJA ft.A f BW Loop Bandwidth: a) at FIIl'ER0 = Lo b) atFIIl'ERO =Hi ~CJ RCLK+/- Recovered Oock Jitter fro PropagatiOn Delay from SDATA+/- Input to RDAT+/Output - tc~ let REFCK+/- Input rise and fall time, 20% to SO% - !so" tsDf SDATA+/- Input rise and fall time, 20% to SO% - - 300 - SOO ps 300 - SOO ps tRC~ tRCf tRD" tRDf RCLK+/- Recovered Clock Outputrise and fall time, 20% to SO% RDAT +/- Recovered Data Output rise and fall time, 20%toSO% -400 Notes: (1) The part is designed to operate at 155.52 MHz. A reference clock with frequency variation of +1- 50 ppm or better is recommended. Consult the factory for applications other than this frequency. (2) With minimum 50% Input Data Eye opening at 155.52 Mbls. (3) With a jitter-free data input and minimum transition density of 50%. G52087-o Rev. 1.3 @ VITESSE 1996 Communications Product Data Book Page 431 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Figure 4: VSC810118102 ACTimingWavefonn RBFCK+ I~') d- u 1+-_ _ - - ; ______ tDCYC 1-------'/ u u ___ \ -- - -- -_. ---+I DATA IN (2) VAUD DATA (2) Note: (1) Solid line indicates the true sense and dbtted line indicates the complementary sense of the signal. Absolute Maximum Ratings (1) Power Supply Voltage (Vcc -V1T) ..................................................................................................-0.5V to +3.0V Input Voltage (VIN) •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• Vee -2.5V to Vee + O.SV Output Current, lOUT (DC, Output HI) ....................................................................................................... -SOmA Case Temperature Under Bias, Tc ................................................................................................. _55° to +125°C Storage Temperature (TSTG) ........................................................................................................ -65°C to +135°C Recommended Operating Conditions The VSC8101 and VSC8102 can be powered by: a) connecting Vee to +2Vand V1T to GND, or b) connecting Vee to GND and V 1T to -2V. Power Supply Voltage (Vee -V1T) ........................................................................................................ 2.0V ± 5% Operating Temperature Range(2) ........................................................................................................ 0° to +70°C Notes: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing pe manent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. (2) Lower limit is ambient temperature and upper limit is cose temperature. Page 432 @ VITESSE Semiconductor Corporation G52087-o Rev. 1.3 155.52 Mbls Clock and Data Recovery Units Preliminary Data Sheet VSC81 01181 02 DC Characteristics (Over recommended operating conditions) Table 1: Inputs and Outputs ........ ............ .... ..... ... .......... ............... .......... .Mi~tYP if#fim~t~ .~~tl'ipti~# . ............................................... . .Md.tV~iii¢ii1lli'#W#{ Vm Input mGH voltage V cc 1150 V cc 600 mV Guaranteed mGH signal for all inputs V IL Input LOW voltage V'IT V cc1500 mV Guaranteed LOW signal for all inputs V OH Output mGH voltage V cc 1020 V cc 700 mV VIN =Vm (max) orVIL (min). Outputs terminated identically into V'IT with 50 ohms. VOL Output LOW voltage V'IT V CC 1620 mV VIN = Vm (max) orVIL (min). Outputs tenninated identically into V'IT with 50 ohms. (1) For AC-Coupliug: input swing VOCM at the pin. Input voltage swing for REFCK+/- and SDAT +/- 450 Output common mode voltage for RDAT +/- and RCLK+/- .5+ V'IT Output voltage swing for RDAT+/- and RCLK+/- 600 mV (2) For DC-Coupling: input swing referenced to the common mode voltage; Differential Outputs terminated identically into V'IT with 50 ohms. .8+ V'IT mV Differential Outputs terminated identically into V'IT with 50 ohms. Table 2: Power Dissipation PiliiiiiWter ..lie8CrtRtiQ~ ... ..... ... ... .... ·..... ·.MfnTy,i( .Mu ·unitfHHHC(};UiiiiQns Pn Power dissipation (VSC8101) 400 mW Pn Power dissipation (VSC8102) 3.0 W same as above Supply current (VSC8101) 190 rnA same as above Supply current (VSC81 02) 1430 rnA same as above Icc Icc G52087-0 Rev. 1.3 @ .. Outputs open, V cc = 2.1 V VITESSE 1996 Communications Product Data Book Page 433 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Generation of 2V Supply for the VSC8101NSC8102 In a EeL system, -2V will be one of the standard supplies and the VSC8101NSC8102 can be powered with GND and -2Y. However, for typical TTL systems, 2V is generally not available. In these applications, the 2V supply can be generated easily from a 5V or 3.3V supply. There are several manufacturers who supply complete single-chip linear regulators. Examples are: Table 3: Linear Regulators and Suppliers ......................... ••••••••••••••.•••M¥t~~rit .suPPly •.•••••• ·• ·~~~#~ff~~1t#!l#~ . . •. .•••••.••••••••..•.•(!~#ii# •••••••• .... ............ . Ma~ui~tW:er.;g !nfo~jjjiiii## ............................ VSC8101 REG1117 800mA Burr Brown. 800..548-6132 VSC8102 LTl086 1.5A Linear Tech. 408-432-1900 Note: (1) Complete data sheets for these ~gulators can be obtainedfrom the manufacturers. Page 434 @ VITESSE Semiconductor Corporation G520B7-Q Rev. 1.3 155.52 Mbls Clock and Data Recovery Units Preliminary Data Sheet Figure 5: Typical Applications (a) -2V Supply Vee ECl { Differential Input ECl -=3~~~.,---~ { Differential Input OF SOAT+ RDAT. VSC8101 SOAT· RDAT· or . REFCK+ RCLK. -=3~wi~"'w.I~ ~ REFCK· RCLK· .. (118) VSC8102 ~-EE==:::::l~1i* ME==:rrF -2V -2V - 2V +2V (b) +2V Supply ~~~ AC·Couple ...---.....JVee-.....JDFI...-----, SCAT + VSC8101 RDAT+ or RDAT· Differential { Input "'::::::::::B~ SOAT· Differential { Input ~K+~. (118) VSC8102 -==±7~ REFCK· V.,., RCLK· FlLTERI • T" HE==3;~.!lI!QI!lI!QI!lI!QI9~} l-(E==37-F r ~ Differential Output ~} Differential f-4E==~~f~H~rI~ Output F1LTllRO Vterm / / NUl'ES: (1) All reslsto,.. equal to 50 ohm unlus specified otherwise. (2) Shaded linM reprosenJ stu'" of tra",mia.i""liMIJ. They .hould have the com!4p01lding tracea on board be as 3Mrt as poasible to minimiz.e reflection. G52087-0 Rev. 1.3 @ User select 1 +2V VrrESSE 1996 Communications Product Data Book Page 435 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Table 4: VSC81 01 Pin Description :L~~~#i~ ....... b~eL: : REFCK+ 5 REFCKSDAT+ ,,!, U.'·':.·.:T·::: • :··.:.,.2UiliL12L • • .• • ECL Reference Clock input true 6 ECL Reference Clock input complement 9 EeL Data input true SDAT- 10 ECL Data input complement RCLK+ 25 ECL Recovered Clock true RCLK- 23 ECL Recovered Qock complement RDAT+ 21 ECL Recovered Data true RDAT- 19 ECL Recovered Data complement Flll'ER0 16 VcdVrr Selects the Loop Bandwidth: (1) FILTERO LO, Bandwidth 150 KHz (2) FILTERO HI, Bandwidth 10KHz FILTERI 17 VIT For normal operation, connect to VIT t1nu 50 ohm resistor DF 14 Vee For normal operation, connect to Vee t1nu 50 ohm resistor NC 1-3,7,11,13, 15,27,28 Do not connect, leave open vee 8,20,22,24 Positive supply, Vee VTT 4,12,18,26 Negative supply, Vrr = = = = Figure 6: VSC81 01 Pin Diagram ~ t) z t) z t) z t) z ~ REFCK+ 5 25 RCLK+ REFCK- 6 24 vce 23 RCLK- 22 VCC 9 21 RDAT+ SDAT- 10 20 VCC NC 11 19 RDAT- NC VSC8101 VCC 8 SDAT+ 28 PLCC ~ Page 436 t) z @ t) z u.. c t) z tf Ii: w w !::i !::i u: u: ~ VITESSE Semiconductor Corporation G52087-0 Rev. 1.3 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Table 5: VSC81 02 Pin Description SDAT+ ECL Data input true ECL Data input complement RCLK+ ECL Recovered Oock true RCLK- ECL Recovered Clock complement RDAT+ ECL Recovered Data true RDAT- ECL Recovered Data complement SDAT- FIU'ERO 30,27,21,18, 15.12,5,2 82 VccfVIT NC vee VIT G52087-0 Rev. 1.3 Selects the Loop Bandwidth: (1) FILTERO =LO, Bandwidth =150 KHz (2) FILTERO = Bandwidth =10KHz m. Do not connect, leave open 3,1",D',.lil,,":-,:''',:Jo, 62,68, 74,77 10.16,33,40, 48,52,59,65, 71,78,83,91, 98 @ Positive supply, Vee Negative supply, VIT VITESSE 1996 Communications Product Data Book Page 437 155.52 Mb/s Clock and Data Recovery Units Preliminary Data .Sheet Figure 7: VSC8102 Pin Diagram SOAT8+ OF SOAT&- NC VCC VTT SOAT7+ VCC SOAT7- RCLK6+ NC RCLK&- NC VCC NC ROAT6+ ROAT6- NC VTT VTT RCLK6+ SOAT6+ RCLK5- SOAT6- VCC VCC SOAT6+ sOATSVTT VSC8102 ROATS+ 100 PQFP VTT ROAT6RCLK4+ SOAT4+ RCLK4- SOAT4- VCC VCC ROAT4+ SOAT3+ ROAT4- SOAT3NC VTT NC RCLK3+ NC RCLK3- NC VCC ROAT3+ SOAT2+ ROAT3- SOAT2VCC VCC SOAT1+ VTT SOAT1- NC ~ 0 lAo w . ~ 0 lAo W t- I- + ~ ~ 0 0 . + • ;t ;t -I 00 0 -I 0 tt- + ~ ~ o 0 ~ lao: a: a: > a: a: z z a: a: > a: a: z z z ct lao: !il !il ~ -I 000 -I gz 0 DRAWING IS HEAT SINK UP Page.438 @ VITESSE Semiconductor Corporation G52087-oRev.l.3 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Package Information The VSC8101 is packaged in a 28-pin Plastic Leaded Chip Carrier (pLCC). 0.454 x 0.454 in. 2 body size. The VSC8I02is packaged in a lOO-pin Plastic Quad Flat Pack (PQFP). 20x 14 mm2 body size). Figure 8: VSC8101 Package Drawings (28PLCC-JEDEC) .. A .. B 1 28 5 25 C 0 .045 x4So CORNER CHAMFER 11 Item inch ToL A .490 ±.005 B .454 ±.002 ±.002 C .454 D .490 ±.OO5 E .010 ±.OOO3 F .420 ±.01O G .152 ±.O02 19 0.050± .002 0.023/0.029 x 30" + t NOTES: (1) Drowingl1lO11. scale. (2) AU unilJ in inch wtl....I"'rwile nol&l. GS20B7-0 Rev. 1.3 @ VITESSE 1996 Communications Product Data Book Page 439 155.52 Mb/s Clock and Data Recovery Units Preliminary Data Sheet Figure 9: VSC81 02 Package Drawings (100PQFP) ,:,mo;;", .;;.;;; .j~~ A 3.40 MAX Al 0.60 MAX A2 2.7 ±.10 D 17.20 ±.40 Dl 14.00 ±.10 E 23.20 ±.40 El 20.00 ±.10 L 0.80 ±.2 0.65 NOM b 0.30 ±.10 8 0-10' R .25 NOM R1 .2 NOM HEATSINK INTRUSION NIYI"ES: (1) Drawing. noll08ca1.. (2) 7\tIo .tylea and is clocked into the part on the rising edge of TXLSCKIN; refer to Figure 1. The data is serialized (MSB leading) and presented at the TxOUT+1- pins. The Clock Multiplier Unit (CMU) generates the high speed clock required for serialization and transmission. The high speed clock accompanying the transmitted data appears on the TxCLKOUT+1- pins. The reference clock is selectable using the control lines BO-B2; refer to Table 13. The data rate (155Mb/s or 622Mb/s) is selected using the STS12 control pin; refer to Table 13. The Facility Loopback mode is set by FACLOOP and is active high. A 51.84Mhz continuous clock (RX50MCK) is provided as a general board-level clock to drive other circuits such as the UTOPIA interface on the UNI devices. G51011-0, Rev. 1.5 ® VITESSE 1996 Communications Product Data Book Page 443 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation VSC8110 Block Diagram EQUIPMENr io\0PBACK RxDATAIN+ RxDATAIN- SERlALTO PARAUEL ~ ~ r--.V 1 ~ ~ FRAME DETECTION ~RECOVERY FACILlTY LOOPBACK (0 TxDATAOUT+ TxDATAOUT- PARAUEL TO SERIAL y~ RXOUT<7:O> T ~ r----- EQULOOP . REG ~ ~" FACLOOP REG . .... -r- - I .. OOF FP TXIN<7:0> 1XLSCKIN EQUIPMENI' io\0PBACK RxCLKIN+ RxCLKIN- o r- r--.V J I I fa RXLSCKOUT I G I H TXLSCKOUT I FACILlTY LOOPBACK TxCLKOUT+ TxCLKOUT- (0 +- .... y~ f 3/12 I ..... RESET RXSOMCK RBFCLK+ RBFCLK- CMU --r Page 444 pins; refer to Figure 4. The received high speed clock is divided by 8 and presented on the RXLSCKOUT pin. The receive circuit includes frame detection and recovery. The frame circuitry detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the AIA2 boundary. OOF is a level-sensitive signal, and the VSC8110 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three Al bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT<7 :0> will be byte aligned starting on the third A2 byte. When a frame is detected, a pulse is generated on FP. The pulse FP is synchronized with the byte-aligned third A2 byte on RXOUT<7 :0>. The FP pulse is one byte clock period long. The frame detector sends an FP pulse only if OOF is high or if a frame was detected while OOF was being pulled low. Facility Loopback The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RxDATAIN) is presented at the high speed transmit output (TxDATAOUT). In addition, the high speed receive clock input (RxCLKIN) is selected and presented at the high speed transmit clock output (TxCLKOUT). In Facility Loopback mode the high speed receive data (RxDATAIN) is also converted to parallel data and presented at the low speed receive data output pins (RXOUT<7:0». The receive clock (RxCLKIN) is also divided down and presented at the low speed clock output (RXLSCKOUT). The Facility and Equipment Loopbacks are not designed to be enabled at the same time. Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the parallel to serial conversion of the low speed data (TXIN<0:7» is selected and converted back to parallel data on the receiver circuit side and presented at the low speed parallel outputs (RXOUT<7:0». The internally generated 155Mhzl622Mhz clock is used to generate the low speed receive clock output (RXLSCKOUT), (Note that the clock presented at RXLSCKOUT can be changed to present the clock applied to the EXTCLKP/N pins if the EXTVCO control pin is set active high. In this mode EXTCLK is also presented at the TXCLKOUT and TXLSCKOUT pins.) In Equipment Loopback mode the transmit data (TXIN<7:0» is serialized and presented at the high speed output (TxDATAOUT) along with the high speed transmit clock (TxCLKOUT) which is generated by the on board clock multiplier unit. The facility and Equipment Loopbacks are not designed to be enabled at the same time. G51011-0, Rev. 1.5 @ VrrESSE 1996 Communications Product Data Book Page 445 Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation AC Timing Characteristics Figure 1: Receive Data and Clock Block Diagram . VSC8110 PMS3SS RxDATAIN+ RxDATAIN RxCLKIN + RxCLKIN - Q D eLK Figure 2: Receive High Speed Data Input Timing Diagram RxCLKIN + RxCLKIN - TRXSU TRXH RxDATAIN+ RxDATAIN - Page 446 @ VITESSE SemIconductor Corporation G51011-o, Rev. 1.5 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Table 1: Receive High Speed Data Input Timing Table (STS-12 Operation) Table 2: Receive High Speed Data Input Timing Table (STS-3 Operation) .•.... < TRXCLK Mbl·· •.•••. ~ ••.••• .••..1iiaX. 6.43 Receive clock period ...17"i# DB Serial data setup time with respect to RxCLKIN 1.5 DB Serial data hold time with respect to RxCLKIN 1.5 DB Figure 3: Transmit Data InputTlming Diagram TXLSCKouT Table 3: Transmit Data Input Timing Table (STS-12 Operation) ... :.. TCLKIN TPRop .... Transmit data input byte clock period 12.86 DB Transmit data setup time with respect to TXLSCKlN 1~ DB Transmit data hold time with respect to TXLSCKIN 1~ DB Maximum allowable propagation delay for COJDlecting TXLSCKOUT to TXLSCKIN 3 DB Note: Duty cycle for TXLSCKOUT is 50% +1- 5% worse case G51011-0, Rev. 1.5 ® VITESSE 1996 Communications Product Data Book Page 447 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Table 4: Transmit Data Input TIming Table (STS-3 Operation) TCLKIN TINSU 51.44 Transmit data input byte clock period DB Transmit data setup time with respect to TXLSCKlN 1.0 DB Transmit data hold time with respect to TXLSCKIN 1.0 DB Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN 3 DB Agure 4: Data and ClockTransmit Block Diagram VSC8110 RxDATA RXOUT<7:0> TxDATAOUT+ TxDATAOUTFP TxCLKOUT+ TxCLKOUTRxCLK RXLSCKOUT Figure 5: Receive Data Output TIming Diagram RxCLKlN+ RxCLKIN - RXLSCKOUT RXOUT<7:0> Al FP TSKEW Page 448 ~ VITESSE Semiconductor Corporation G51011-0, Rev. 1.5 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Table 5: Receive Data Output Timing Table (STS-12 Operation) TRXCLKIN Receive clock period 1.608 ns TRXLSCK Receive data oulput byte clock period 12.86 ns TSKEW Range in which the rising edge of FP will appear in relation to the falling edge of RXLSCKOur Time data onRXOur<7:O> is valid before and after the rising edge of RXLSCKOur TpW +/-1.5 4.9 ns ns 12.86 ns Receive clock period 6.43 ns Receive data oUlput byte clock period 51.44 ns Pulse width of frame detection pulse FP Table 6: Receive Data Output Timing Table (STS-3 Operation) TSKEW Range in which the rising edge of FP will appear in relation to the falling edge of RXLSCKOur Time data on RXOur<7:0> is valid before and after the rising edge of RXLSCKOur TpW Pulse width of frame detection pulse FP +/-1.5 24 ns ns 51.44 ns Figure 6: Transmit High Speed Data Timing Diagram TxCLKOUT+ TxCLKOUT- TxDATAOUT+ TxDATAOUT- G51011-0, Rev. 1.5 @ VrrESSE 1996 Communications Product Data Book Page 449 Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Table 7: Transmit High Speed Data Timing Table (STS-12 Operation) . ··Pammrilir ............................... 1.608 Transmit clock period TSKEW DB Skew between the falling edge ofTxCLKOur and valid data on TxDATAOur +/-200 ps Table 8: Transmit High Speed Data Timing Table (STS-3 Operation) TTXCLK Transmit clock period TSKEW Skew between the falling edge of TxCLKOur and valid data on TxDATAOur 6.43 DB +/-200 ps Data Latency The VSC8110 contains several operating modes, each of which exercise different logic paths through the part. Table 9 bounds the data latency through each path with an associated clock signal. Table 9: Data Latency ;:::::::;::::;:::::;: ClPlikH •i.leje,enc~. Receive Equipment Loopback Facilities Loopback Page 450 MSB atRxDATAINtodataonRXour<7:O:> Byte data TXIN<7:O:>to byte data onRXOur<7:0> MSB at RxDATAIN to MSB atTxDATAOur CJiJ:fli,tYi!~qJtit:k.~y4.~ H$t$~.tF H$:t$~~T TxCLKOur 2-11 2-11 RxCLKIN 18-25 15-22 TxCLKOur 19-33 17-31 RxCLKIN 10 10 8 VITESSE Semiconductor Corporation G51011-O, Rev. 1.5 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Absolute Maximum Ratings(1) Power Supply Voltage (VMM) Potential to GND ............................................................................-O.SV to +2.SV Power Supply Voltage (VT'TI.) Potential to GND ............................................................................ -O.5V to +S.5V TTL Input Voltage Applied ................................................................................................. -O.SV to V TIL + 1.0V VECL Input Voltage Applied .............................................................................................. -O.5V to VMM + 1.0V Output Current (lOUT) .................................................................................................................................. SOmA Case Temperature Under Bias (Tc) ................................................................................................ _55° to + 125°C Storage Temperature (TSTG) .......................................................................................................... _65° to + 150°C Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VMM) ...............................................................................................................+2.0V ±5 % Power Supply Voltage (VT'J'IJ ...............................................................................................................+5.0V±5 % Commercial Operating Temperature Range* (T) .................................................................................. 0° to 70°C * Lower limit of specification is ambient temperature and upper limit is case temperature. ESDRatings Proper ESD procedures should be used when handling this product. The VSC8110 is rated to the following ESD voltages based on the human body model: 1. All pi~s are rated at or above 1500V. G51011-0, Rev. loS @ VITESSE 1996 Communications Product Data Book Page 451 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation DC Characteristics Table 10: VECL Inputs and Outputs Page 452 Output HIGH voltage 2.4 VOL Output LOW voltage 0 0.5 mV VlH Input HIGH voltage 2.0 V1TL+1. 0 mV V IL Input LOW voltage 0 0.8 mV ® VITESSE Semiconductor Corporation mV VIN = VlH (max) orVIL (min) =8mA Guaranteed HIGH signal for all inputs G51011-0, Rev. 1.5 Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Power Dissipation Table 12: Power Supply Currents •••••• ITIL ....... .~' Power supply current from vMM 430 rnA Power supply current from vTIL 218 rnA Power dissipation 1.98 w Note: Specified with outputs open circuit. The combined maximum currents 0;..", lrrJ for any part will not exceed 1.98 Watts. Clock Multiplier Unit Table 13: Reference Frequency Selection and Output Frequency Control ..................... . . (jurput . . lffiIeri!n.c:ii ~q@;it:Y fMJIiF )?til4.4~i#* ••• JJf/J::J ••• 19.44 622.08 0 1 0 38.88 622.08 0 0 1 51.84 622.08 0 0 0 77.76 622.08 155.52 0 1 0 19.44 0 0 0 38.88 155.52 0 0 0 1 51.84 155.52 0 0 0 0 77.76 155.52 Table 14: Clock Multiplier Unit Performance Name Description RCd Reference clock duty cycle RCj Reference clock jitter (RMS) Min Typ 40 Max Units 60 % 5 ps Ocd Output clock duty cycle 60 % OCj Output clock jitter (RMS) @ 77.76 MHz ref 8 ps OCj Outputclockjitter(RMS)@51.84MHzref 10 ps OCj Output clock jitter (RMS) @ 38.88 MHz ref 13 ps OCj Output clock jitter (RMS) @ 19.44 MHz ref 15 ps OCfmiu Minimum output frequency 620 MHz OCfmax Maximum output frequency 624 MHz 40 Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter. G51011-O, Rev. 1.5 @ VITESSE 1996 Communications Product Data Book Page 453 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Package Pin Description Table 15: Pin Definitions ........................... .. .............. . ................. iili ... HLkkdH ...... ·.. $,t~~*( ..... ..• n# ....... .................. . ................. FACLOOP 1 I TTL • •••••••• ••••••••• ••• ••••• Facility loopback, active high VMM 2 +2V +2 volt supply _VSCTE 3 I TTL Test pin enable. Tie low for system operation RESET 4 I TTL Resets frame detection, dividers, controls, and tristates TTL outputs; active high EXTVCO 5 I TTL Test mode control; tie low for system operation BO 6 I TTL Reference clock select, refer to table 13 Bl 7 I TTL Reference clock select, refer to table 13 B2 8 I TTL Reference clock select, refer to table 13 VMM 9 TxDATAOUT+ 10 0 VECL Transmit output, high speed differential data + 0 VECL Transmit output, high speed differential data - TxDATAOUT- 11 VCC 12 TxCLKOUT+ 13 TxCLKOUT- 14 VMM 15 +2V +2 volt supply GND Ground 0 VECL Transmit high speed clock differential output+ 0 VECL Transmit high speed clock differential output- +2V +2 volt supply EXTCLKP 16 I VECL External clock input+, test mode only; tie to VMM for system operation EXTCLKN 17 I VECL External clock input-, test mode only; tie to ground for system operation vee 18 GND Ground RxCLKIN+ 19 I VECL Receive high speed differential clock input+ RxCLKIN- 20 I VECL Receive high speed differential clock input- VMM 21 OOF 22 NC 23 RxDATAIN+ +2V +2 volt supply I TTL Out Of Frame; Frame detection initiated with high level 24 I VECL Receive high speed differential data input+ RxDATAIN- 25 I VECL Receive high speed differential data input- NC 26 NC 27 VMM 28 NC 29 Page 454 No connection No connection No connection +2V +2 volt supply No connection @ VITESSE Semiconductor Corporation G51011-o, Rev. 1.5 Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation ............................. ...................... ................. iiii .··· .... ·Sigml.l .... ···· ........................ .... iflveL "" •••••••• I _VSCIPNC 30 VTTL 31 TTL Test mode input. Tie low for system operation +5.0V +5 volt supply 3SCOPNC 32 0 VECL Test mode output RXSOMCK 33 0 TTL vee 34 RXOUTO 35 0 0 RXOUTI 36 vee 37 RXOUT2 38 RXOUT3 39 vee 40 RXOUT4 41 0 0 GND Ground TTL Receive output data bitO TTL Receive output data bitt GND GrOlmd 0 TTL Receive output data bit2 0 TTL Receive output data bit3 GND Ground TTL Receive output data bit4 TTL Receive output data bit5 RXOUT5 42 43 RXOUT6 44 0 RXOUT7 45 0 vee 46 RXLSCKOUT 47 0 FP 48 0 VTTL 49 NC 50 No connection NC 51 No connection No connection GND Ground TTL Receive output data bit6 TTL Receive output data bit7 GND Ground TTL Receive byte clock output TTL Frame.detection pulse +5.0V +5 volt supply NC 52 NC 53 VMM 54 vee 55 REFCLK+ 56 I VECL Differential reference clock input+, refer to table 13 REFCLK- 57 I VECL Differential reference clock input-, refer to table 13 VTTL 58 +5.0V +5 volt supply (CMU) vee vee 59 GND GND Ground (eMU) No connection +2V GND +2 volt supply Ground Ground (eMU) NC 61 No connection NC 62 No connection G51011-O, Rev. 1.5 ••••••• Constant 51.84Mhz reference clock output, derived from the Uock Multiplier Unit vee 60 • ® VITESSE 1996 Communications Product Data Book Page 455 Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation ...... ·.. ~il("*l .. · ........................ ..... :HPiii ...... .1l0 ...... b;~d.: ................... ,,: . NC 63 No connection NC 64 No connection NC 65 No connection NC 66 VTIL 67 +5.0V +5 volt supply (CMU) VTfL 68 +5.0V +5 volt supply (CMU) VTIL 69 +5.0V +5 volt supply (CMU) VCC 70 Ground (CMU) vee vee 71 GND GND GND NC 73 No connection NC 74 No connection ': No connection 72 Ground (CMU) Ground (CMU) vee 75 GND VMM 76 +2V NC 77 No connection NC 78 No connection NC 79 No connection NC 80 VTIL 81 Ground +2 volt supply No connection 0 +5.0V +5 volt supply TXLSCKOUT 82 TIL Transmit byte clock out TXLSCKIN 83 TIL Transmit byte clock in vee 84 GND Ground TXIN7 85 TIL Transmit input data bit7 TXIN6 86 TIL Transmit input data bit6 vee 87 GND Ground TXIN5 88 TTL Transmit input data bitS TXIN4 89 TTL Transmit input data bit4 NC 90 TXIN3 91 TIL Transmit input data bit3 TXIN2 92 TIL Transmit input data bit2 vee 93 GND Ground TXINI 94 TIL Transmit input data bitt TXINO 95 TIL Transmit input data bitO NC 96 Page 456 ""... I No connection No connection @ VrrESSE Semiconductor Corporation G51011-0, Rev. 1.5 Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation ................... ....... ·.S{gMl .. ·.. ·.· STS12 o PILM 98 VECL PLL test output, leave unconnected in system operation VTTL 99 +5.0V +5 volt supply EQULOOP 100 TTL Equipment loopback, active high The VSC811 0 is manufactured in a 100PQFP package which is supplied by two different vendors. The critical dimensions in the drawing represent the superset of dimensions for both packages. The significant difference between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink. Package Thermal Characteristics The VSC811 0 is packaged in a thermally enhanced 100PQFP with an embedded heat sink. The heat sink surface configurations are shown in the package drawings. With natural convection, the case to air thermal resistance is estimated to be 27.SoCIW. The air flow versus thermal resistance relationship is shown in table 16. Table 16: Theta Case to Ambient versus Air Velocity Air velocitY (iWfMY G51011-o, Rev. 1.5 @ o 27.5 100 23.1 200 19.8 400 17.6 600 16 VITESSE 1996 Communications Product Data Book Page 457 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Package Information 100 PQFP Package Drawings :::~~ ••• IU~;; i_;;.;o, , A 3AO MAX Al 0.60 MAX A2 2.7 ±.10 D 17.20 ±AO DI 14.00 ±.IO E 23.20 ±.40 El 20.00 ±.10 L 0.80 ±.2 0.65 NOM b 0.30 ±.10 e 0-10· R .25 NOM RI .2 NOM 9.0X9.0--lii=$M-.! HEATSINK INTRUSION NOTES: (I) Drawlnp no//o _I.. (2)=~Z';.t=0":::t(3) Allunlll in mJ/JJma.... Page 458 e VITESSE Semiconductor Corporation G51011-0, Rev. 1.5 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Ordering Information The order numbers for this product are: Part Number VSC8110QB: VSC8110QB1: VSC8110QB2: Device Type 155Mb/s-622Mb1s Mux/Dmux with CMU in 100 Pin PQFP Commercial temperature, O°C ambient to 70° case 155Mb/s-622Mb/s MuxlDmux with CMU in 100 Pin PQFP Extended temperature, O°C ambient to 110° case 155Mb1s-622Mb/s Mux/Dmux with CMU in 100 Pin PQFP Industrial temperature, -40°C ambient to 85°C case Notice Vitesse Semiconductor Corporation reselVes the right to make changes in its products, specifications or other information at any time without prior notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G51011-0, Rev. 1.5 @ VITESSE 1996 Communications Product Data Book Page 459 ATMISONET/$DH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Data Sheet Application Notes 2 Volt Supply Generation From 5 Volts The 2 volt supply can be generated from the 5 volt supply using a linear regulator. There are many manufacturers who supply linear regulators. Refer to Table 17 for examples. Table 17: Recommended 2 Volt Voltage Regulator REGl117 800mA Burr Brown 800-548-6132 LT117A 800mA Linear Technology Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8110 has been brought off-chip to allow as much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both the VSC811 0 and the UNI devices, it is important to pay close attention to the routing of this signal. The UNI device in general is a CMOS part which can have very wide spreads in timing (l-llns clock in to parallel data out for the PM5355), which utilizes most of the 12.86ns period (at 78Mhz), leaving little for the trace delays and set-up times required to interconnect the 2 devices. The recommended way of routing this clock when used in a 622Mhz mode is to daisy chain it to the UNI device pin and then route it back to the VSC811 0 along with the byte data. This eliminates the I-way trace delay that would otherwise be encountered between the data and clock and thus leaves 1.86ns for the VSC8110 setup time and for variations in trace delays and rise times between clock and data. The trace delay must be kept under 2ns (allowing an additional Ins for variations in rise times and skews) to ensure proper muxing of parallel input data into the VSC811 0; reference Table 3 and 4. AC Coupling and Terminating High-speed 1I0s The high speed signals on the VSC8110 (RxDATAIN, RxCLKIN, TxDATAOUT, TxCLKOUT) use VEeL levels which are essentially EeL levels shifted positive by 2 volts. The VECL JlOs are referenced to the VMM supply and are terminated to ground. Since most optics modules use either EeL or PECL levels, the high speed ports need to be ac coupled to overcome the difference in dc levels. In addition, the inputs must be dc biased to hold the inputs at their threshold value with no signal applied. The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 8. The figure shows the appropriate termination values when interfacing PECL to VECL and VECL to PECL. This network provides the equivalent 50 ohm termination for the high speed JlOs and also provides the required dc biasing for both the drivers and receivers. Table 18 contains recommended values for each of the components. Layout of the 622 Signals The routing of the 622 signals should be done using good high speed design practices. This would include using controlled impedance lines and keeping the distance between components to an absolute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull Page 460 ® VITESSE Semiconductor Corporation G51011-0, Rev. 1.5 Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation down resistor should be placed as close to the VSC8110 pin as possible while the AC-coupling capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities. Ground Planes The ground plane for the components used in the 622 interface should be continuous and not sectioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with the ground return currents on the signal lines as well as in general. the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple etc. Sectioning of the positive supplies can provide some isolation benefits. Reference Clock Generation It has been noted that additional jitter may be generated on the reference clock if a TTL Oscillator is level shifted using a TTL to ECL converter. The best recommendation is to use an EeL oscillator which can be ACcoupled straight into the REF CLOCK inputs on the VSC8110 Figure 7: AC Coupled High Speed 110 PECL Output VSC8110 VECL Input/Output PECL Input + 5 Volt Supply VMM +2 Volt Supply + 5 Volt Supply R2 R3 Vcc Ground Vcc Ground Table 18: AC Coupling Component Values R1 270 ohms R2 147 ohms R3 76 ohms R4 50-100ohms 68 ohms R5 R6 190 ohms C1. C2, C3, C4 G5101H), Rev. 1.5 1% 1% 1% 1% 1% 1% .01ufHigh Frequency ® VITESSE 1996 Communications Product Data Book Page 461 ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation Page 462 @ VITESSE Semiconductor Corporation Data Sheet G51011-0, Rev. 1.5 VITESSE Preliminary Data Sheet ATM/SONET/SDH 622 Mb/s Transceiver Evaluation Board Operating Description Features • 622Mb/s at Speed Functional Operation • Includes the PMC 5312 STTX Device for Interoperability Testing • Completely Self Contained for Self Test Operations • Flexibility to Evaluate the VSC8110 in All Modes Of Operation • Mode Control Switches Included for Both the VSC8110 and PMC5312 Devices • SMA Connections Included for High Speed Bench Characterization • Allows Signals to be AC or Direct Coupled to the VSC8110 • ECL Buffered Interfaces are Included as an Option for High Speed Signals • On-board Mux to Simulate Loss of Signal • Socketed Board Option Available for the VSC8110 Device General Description The VSC8110 Evaluation Board provides users the ability to completely evaluate the VSC8110 device. The board contains both the VSC811 0 and PMC's PM5312 devices allowing users to verify interoperability between the parts. The board is self contained and includes a self test mode between the PM5312 and the VSC8110 requiring only an external +5 volt supply. In addition, there are multiple SMA connections (both direct and AC coupled) to the high speed serial ports which allow connecting the VSC811 0 to optical components for interoperability testing or to characterization equipment for jitter and waveform evaluations. LEDs are included which indicate functional status including loss of frame. VSC8110 Evaluation Board G56027-O Rev. 1.0 ® VrrESSE 1996 Communications Product Data Book Page 463 ATMISONET/SDH 155/622 Mb/s Transceiver Evaluation Board Operating Description Preliminary Data Sheet VSC8110 Evaluation Board Operation Functional Description The capability of the board can be divided into two areas. The first enables the evaluation of the VSC8110 device characteristics including output jitter, waveform integrity and basic functionality. The second allows interoperability testing with the PMC5312 as well as external optical interfaces. The board is designed to be as flexible as possible allowing direct coupled, AC coupled, single ended or differential signals and buffered high speed connections to the VSC811 O. The board utilizes standard SMA connectors for all the high speed ports as well as the reference clock inputs. The board is self contained allowing for a closed loop test between the VSC8110 and the PMC5312 device. All the required passive components are included for the translation from EeL or PEeL to the VSC8110 high speed 1I0s. The only requirements are: 1. Connect a 5 volt supply; 2. Connect the high speed transmit outputs back to the receiver inputs; 3. Provide a reference crystal oscillator module (socket provided) at 19.44, 38.88, 51.84 or 77.76Mhz or external clock reference source to the VSC8110. General Operation Power Supplies Operation of the board requires a 5 volt power supply connected to both +5 volt connectors on the power block along with a ground connection. The 5 volt supply is split to allow DC isolation of the VSC8110 from the other board components to allow measuring the supply currents. A 2 volt regulator is included on the board and no external 2 volt supply is required, however an external 2 volt connection is available on the power block as an option. To enable the use of the mode switches (SW1, SW2, SW3) shorting connectors must be applied to alllocations on CTR1, CTR2 and CTR6 pins. Device Operation Evaluation of the VSC811 0 device can be performed by applying a reference clock to the reference clock input SMA connectors (Ill and Il2) or by inserting a reference oscillator into the socket provided on the board and connecting it's output (J2, J4) to the reference clock inputs using SMA cables. The control pins (SW1 and SW2) must be set appropriately for the reference clock frequency and for the opeIlltion mode of the part; i.e. 622Mb/s or 155Mb/s along with theloopbackmodes. Note that the PMC5312 is not designed to work in a 155Mb/s mode and therefore a closed loop test at 155Mb/s is not possible on this evaluation board. With the exception of BO-B2 (BO, Bl and B2 set the reference frequency), most of the mode control switches should be set in the off position making them inactive. All of the controls on the VSC8110 are active high. This will insure the part is not in loopback mode or in reset mode and places the part in 622Mb/s mode. U4 is a differential receiver and is provided to insure clean edges are applied to the VSC8110 reference clock inputs. The inputto this device and to the VSC8110 areAC coupled with a Thevenin equivalent 50 ohm termination on the input side of each device. In addition T4A and T4B are used to tie either input to VBB in the Motorola device if a single ended reference clock signal is applied. Upon applying a reference clock to the part, the transmit data and clock outputs can be examined with or without applying data to the receive inputs. The high speed differential clock and data outputs go directly to the SMA connections J9 and IlO, and J5 and J6 respectively. Note that these outputs are referenced to the +2 volt supply. Page 464 @ VITESSE Semiconductor Corporation G56027-o Rev. 1.0 Preliminary Data Sheet ATM/SONET/SDH 622 Mb/s Transceiver Evaluation Board Operating Description Multiple SMA connections are provided for the high speed receive clock and data inputs. The standard configuration for the board is to apply clock and data signals at the 113, 117, 115 and 114 inputs respectively. In this configuration the input signals are AC coupled onto the board with a Thevenin equivalent 50 ohm termination and the inputs are buffered by the Motorola receiver circuits, U3 and U5. TIA, TlB, T3A and T3B are provided for single-ended signals, connecting one side of each input to the VBB ·reference on the Motorola part. The U2 device is a Mux and is provided to allow a simulated loss of signal using the buffered inputs. This is accomplished by the connection at TI. 17,118, J16 and J8 SMAs are provided as alternative inputs into the VSC8110. This is controlled by the connections at T5, T6, T7 and T8. These connections allow the receive clock and data to be connected directly to the VSC8110 using J8, J18 and 116 and J8 respectively. There is a Thevenin equivalent 50 ohm termination on these lines. At this same connection point it is possible to insert a capacitor for AC coupling into the inputs. Again note the input buffers on the VSC8110 are referenced to +2 volts. Connector T1 0 provides a convenient point to examine the 50Mhz free running output clock produced by the VSC8110. SMA connections 13,11 and 119 are used to exercise various test modes within the VSC8110 and not intended to be used by the customer. Interoperability Testing The VSC8110 parallel output bus and input bus are directly connected to the PMC5312 device. Test points are provided for each signal line via connectors CTR8 and CTR7 which can used to connect a high impedance scope probe. Status signals from the PMC5312 are accessible via CTRS. The control signals LOF, LAIS, LOS and PERF are connected to LEDs providing a visual indication of these signals. The data output bus on the PMC5312 is tied directly back to the input bus. This allows serial data received by the VSC8110 high speed inputs to be looped completely through the PMC5312 and fed back through the VSC8110 to the high speed transmit outputs, allowing for a closed loop evaluation using a SONET or BERT tester. This allows complete functional and at speed verification of the VSC8110 and PMC5312 to insure interoperability between the two components. Key control lines for the PMC5312 can be set using SW3. By resetting the RSTB line the PMC5312 will reset itself and thus force a re-framing sequence to occur. This can be used to verify that the VSC8110 and 5312 are correctly working together and that the frame detection and byte alignment circuits are functioning and can repeatedly and correctly perform frame alignment. T9 is a connector used to connect the low speed byte clock generated by the VSC811 0 to the PMC5312. This clock is used by the PMC5312 to clock the data out and into the VSC8110. This connection should have a shorting bar on it to insure operation of the PMC5312. G56027-0 Rev. 1.0 ® VITESSE 1996 Communications Product Data Book Page 465 ATM/SONET/SDH 155/622 Mb/s Transceiver Evaluation Board Operating Description Preliminary Data Sheet Self Test OperaUon A closed loop functional at speed test can be run on the board requiring only a 5 volt supply and a reference clock. This self test operation requires the use of SMA cables to connect the high speed transmit clock and data to the high speed receive clock and data. Note the differential clock signal needs to be inverted when connecting it to the receive side of the board. This is accomplished by connecting J5 to 114, J6 to 115 for the data, 113 to J9 and 117 to 110 for the clock. The reference clock is applied to the 112 and Jll inputs. The BO-B2 switches must be set for the correct reference frequency. The remaining switches should be set to the off position to disable the other modes of operation. When power is applied, random data will continuously loop through the VSC8110 and PMC5312 devices. A visual indication of operation can be obtained by removing the data cables while the devices are running. This will cause a LOF signal to be generated by the PMC5312 and the LOF LID will light. Replacing the cable will allow the devices to re-frame and the LED LOF indicator will turn off. Another test is to use the RSTB switch to reset the PMC5312 which will force the PMC5312 to request a re-frame from the VSC8110. This can be performed multiple times to demonstrate that the re-framing sequence conSistently occurs. The LED willilicker each time, but will go off once the device has re-framed. Page 466 ~ VrrESSE Semiconductor Corporation G56027-0 Rev. 1.0 VITESSE Preliminary Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Features • Operates at Either STS-3/STM-1 (155.52 Mb/s) or STS-l21STM-4 (622.08 Mb/s) Data Rates • Compatible with Industry ATM UNI Devices • On Chip Clock Generation of the 15552 Mhz or 622.08 Mhz High Speed Clock • Loss of Signal (LOS) Control • Provides Equipment, Facilities and Split Loopback Modes as well as Loop Timing Mode • Meets or Exceeds Bellcore, ITU and ANSI Specifications for Jitter Performance • Single 3.3V Supply Voltage • 8 Bit Parallel TTL Interface • Low Power - 1.2 Watts Maximum • SONET/SDH Frame Recovery • 100 PQFP Package General Description The VSC8111 is an ATMISONET/SDH compatible transceiver integrating high speed clock generation and clock recovery 8 bit serial-to-parallel and parallel-to-serial data conversion. The high speed clock is generated using an on-chip PLL which is selectable for 155.52 or 622.08 Mhz operation. The demultiplexer contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equipment loopback modes. The partis packaged in a 100PQFP with integrated heat spreader for optimum thermal performance and reduced cost. The VSC8111 provides an integrated solution for ATM physical layers and SONETI SDH systems applications. VSC8111 Block Diagram RXDATAIN+ RXDATAINLOSRXCLKIN+ RXCLKINEQULOOP OOF FACLOOP TXDATAOUT+ TXDATAOUT- TXCLKOUT+ TXCLKOUTRX50MCK LOOPTIM1 G52142-0, Rev. 1.1 @ VITESSE 1996 Communications Product Data Book Page 467 ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Preliminary Data Sheet Functional Description The VSC8111 is designed to provide a SONET/SDH compliant interface between the high speed optical networks and the lower speed User Network Interface devices such as the PM5355 S/uNI-622. The VSC8111 converts 8 bit parallel data at 77.76Mhz or 19.44Mhz to a serial bit stream at 622.0SMb/s or 155.52Mb/s respectively. The transmit section provides a Facility Loopback function which loops the received high speed data and clock directly to the transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from input reference frequencies of 19.44, 38.88, 51.84 or 77 .76 Mhz. The CMU can be bypassed with the receive clock in loop timing mode thus synchronizing the entire part to a single clock (RXCLKIN). The block diagram on page 1 shows the major functional blocks associated with the VSC8111. The receive circuit provides the serial-to-parallel conversion, converting 155Mb/s or 622Mb1s to an 8 bit parallel output at 19.44Mhz or 77.76Mhz respectively. The receive section provides an Equipment Loopback function which will loop the high speed transmit data and clock back through the demultiplexer to the 8 bit parallel outputs. Transmit Circuit Byte-wide dati is presented to TXIN<7:0> and is clocked into the part on the rising edge ofTXLSCKIN (refer to Figure 1). The data is then serialized (MSB leading) and presented at the TxOUT+/- pins. The serial output stream is synchronized to the CMU generated clock which is a phase aligned and frequency scaled version of the input reference clock. External control inputs BO-B2 and STS 12 select the multiply ratio of the CMU and either STS-3 (155Mb/s) or STS-12 (622Mb/s) transmission (see table 12). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit interface of the UNI device to the transmit receive registers on the VSC8111 (Figure 1) Figure 1: Receive Data and Clock Block Diagram VSC8111 PM5355 RxDATAIN+ RxDATAIN RxCLKIN+ RxCLKIN - Q D eLK LOSPECL LOSTTL Page 468 @ VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Receive Circuit High speed Non-Return to Zero (NRZ) serial data at 155Mb/s or 622Mb/s and corresponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. This data is converted to byte-wide parallel data and presented on RXOUT<7:0> pins (Figure 2). A divide-by-8 version of the received high-speed clock (RXLSCKOUT) should be used to synchronize the byte-serial RXOUT<7:0> data with the receive portion of the UNI device. The VSC8111 supports Loss of Signal (LOS) detection by providing two control inputs; LOSPECL (PECL) and LOSTTL (TTL). Two LOS inputs are provided to simplify interfacing to the chip by providing both PEeL and TTL level receivers. The PEeL and TTL receive data is XOR'd to generate the internal LOS control. Thus, the active level of the LOS input can be controlled by connecting the unused LOS input to either power or ground. For example, the CDX2622 optics module from Hewlett-Packard signals loss of optical power by asserting their PEeL LOS output low. To accommodate this signal, the VSC8111 part should have LOSPECL connected to the CDX2622 and the LOSTTL input should be tied to VDD (3.3V). Upon detecting LOS, the VSC8111 forces the receive data low which is an indication for any downstream equipment that an optical interface failure has occurred. The receive circuit also includes frame detection and recovery circuitry which detects the SONET/SDH frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock cycles before the AIA2 boundary. The OOF input control is a level-sensitive signal, and the VSC8111 will continually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been detected. Frame detection and recovery occurs when a series of three Al bytes followed by three A2 bytes has been detected. The parallel output data on RXOUT<7:0> will be byte aligned starting on the third A2 byte. When a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the byte-aligned third A2 byte on RXOUT<7:0>. The frame detector sends an FP pulse only if OOF is high orif a frame was detected while OOF was being pulled low. Figure 2: Data and Clock Transmit Block Diagram VSC8111 RXOUT<7:0> TxDATAOUT+ TxDATAOUTFP TxCLKOUT+ TxCLKOUTRXLSCKOUT G52142-0, Rev. 1.1 ® VITESSE 1996 Communications Product Data Book Page 469 ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Preliminary Data Sheet Facility Loopback The Facility Loopback function is controlled by the FACLOOP signal. When the FACLOOP signal is set high, the Facility Loopback mode is activated and the high speed serial receive data (RxDATAIN) is presented at the high speed transmit output (TxDATAOUT). In addition, the high speed receive clock input (RxCLKIN) is selected and presented at the high speed transmit clock output (TxCLKOUT). In Facility Loopback mode the high speed receive data (RxDATAIN) is also converted to parallel data and presented at the low speed receive data output pins (RXOUT<7:0». The receive clock (RxCLKIN) is also divided down and presented at the low speed clock output (RXLSCKOUT). Figure 3: Facility Loopback Data Path RXOUT<7:0> RXDATAIN TXDATAOUT +-1_-+ TXIN<7:0> Equipment Loopback The Equipment Loopback function is controlled by the EQULOOP signal. When the EQULOOP signal is set high, the Equipment Loopback mode is activated and the high speed transmit data generated from the parallel to serial conversion of the low speed data (TXIN<7 :0» is selected and converted back to parallel data on the receiver circuit side and presented at the low speed parallel outputs (RXOUT<7:0». The internally generated 155Mh:zJ622Mhz clock is used to generate the low speed receive clock output (RXLSCKOUT). In Equipment Loopback mode the transmit data (TXIN<7:0» is serialized and presented at the high speed output (TxDATAOUT) along with the high speed transmit clock (TxCLKOUT) which is generated by the on board clock multiplier unit. Page 470 @ VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Figure 4: Equipment Loopback Data Path RXDATAIN RXOUT<7:0> TXDATAOUT .~~~ TXIN<7:0> Split Loopback Equipment and facility loopback modes can be enabled simultaneously. In this case, high-speed serial data received (RXDATAIN) is mux'd through to the high-speed serial outputs (TXDATAOUT) and the low-speed transmit byte serial stream (TXIN) is mux'd into the low-speed byte serial receive output stream (RXOUT) Figure 5: Split Loopback Datapath RXDATAIN RXOUT<7:0> TXDATAOUT .~~~ TXIN<7:0> Loop Timing Two loop timing modes are supported by the VSCSlll. Loop timing mode bypassing the PLL is enabled by asserting the LOOPTIMO input high. In this mode, the CMU is bypassed with the receive clock (RXCLKIN). In this way, the entire part can be synchronously clocked from a single, external source. Loop timing mode NOT bypassing the PLL is enabled by asserting the LOOPTIMI input high. This control pin selects the divide-by-S version of the receive clock as the reference input to the eMU. Clock Synthesis The VSCS111 uses an integrated phase-locked loop (PLL) for clock synthesis of the 622Mb1s transmit data stream. The PLL is comprised of a phase-frequency detector (PFD), an integrating operation amplifier and a voltage controlled oscillator (VCO) configured in classic feedback system. The PFD compares the selected divided down version of the 622MHz VCO (select pins BO-B2 select divide-by ratios of S, 12, 16 and 32, see G52142-o, Rev. 1.1 @ VtTESSE 1996 Communications Product Data Book Page 471 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Table 13) and the reference clock. The integrator provides a transfer function between input phase error and output voltage control. The VCO portion of the PLL is a voltage controlled ring-oscillator with a center frequency of 622MHz. The reactive elements of the integrator are located Off-chip and are connected to the feedback loop of the amplifier through the CIP, C2P, CIN and C2N pins. The configuration of these external surface mounted capacitors is shown in Figure 6. Table 1 shows the recommended external capacitor values for the configurable reference frequencies. Good analog design practices should be applied to the board deSign for these external components. It is important that well matched capacitors are used and that tightly controlled analog ground and power planes are provided for the PLL portion of the circuitry. The dedicated PLL power (VDDANA) and ground (VSSANA) pins need to have quiet supply planes to minimize jitter generation within the clock synthesis unit. Figure 6: External Integrator capacitor CP=O.1uF CN=O.1uF Table 1: Recommended External Capacitor Values •• :••••••• ::.fJ!!4l:············ ............................ 19.44 38.88 51.84 TI,76 Page 472 8 ® Va-ESSE Semiconductor Corporation 0.1 0.1 G52142-0, Rev. 1. 1 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation AC Timing Characteristics Figure 7: Receive High Speed Data InputTlming Diagram TRXCLK RxCLKIN + RxCLKIN - . TRXH TRXSU RxDATAIN+ RxDATAIN - Table 2: Receive High Speed Data InputTiming Table (STS-12 Operation) TRXCLK 1.608 Receive clock period Serial data setup time with respect to RxCLKIN Serial data hold time with respect to RxCLKIN 500 500 TIS ps ps Table 3: Receive High Speed Data InputTlmlng Table (STS-3 Operation) ::0: :~: :::: :::::::::::::::::::::::: 6.43 Receive clock period TRXH TIS Serial data setup time with respect to RxCLKIN 1.5 TIS Serial data hold time with respect to RxCLKIN 1.5 TIS Figure 8: Transmit Data Input Timing Diagram TXLSCKouT G52142-0, Rev. 1.1 TINH .. / @ VITESSE 1996 Communications Product Data Book Page 473 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock· Generation Table 4: Transmit Data Input Timing Table (STS-12 Operation) TCLKIN TINSU TINH TPROP Transmit data input byte clock period Transmit data setup time with respect to TXLSCKIN 1.0 DB Transmit data hold time with respect to TXLSCKIN 1.0 DB 12.86 Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKIN DB 3 DB Note: Duty cycle for TXLSCKOUT is 50% +/- 5% worse case Table 5: Transmit Data Input Timing Table (STS-3 Operation) TCLKIN TINSU TINH Transmit data input byte clock period Transmit data setup time with respect to TXLSCKIN Transmit data hold time with respect to TXLSCKlN Maximum allowable propagation delay for connecting TXLSCKOUT to TXLSCKlN 51.44 DB 1.0 DB 1.0 DB 3 DB Figure 9: Receive Data Output Timing Diagram RxCLKIN+ RxCLKIN- RXLSCKOUT RXOUT<7:0> FP TSKEW Page 474 ® VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation Table 6: Receive Data Output Timing Table (STS-12 Operation) • ·.Pammehl,. • • TRXLSCK TSKEW TRXVALID TpW , Receive clock period 1.608 us Receive data output byte clock period 12.86 us Range in which the rising edge of FP will appear in relation to the falling edge of RXLSCKOUT +/-1.5 Time data on RXOUT <7:0> is valid before and after the rising edge of RXLSCKOUT 4.9 us us 12.86 us Receive clock period 6.43 us Receive data output byte clock period 51.44 us Pulse width of frame detection pulse FP Table 7: Receive Data Output Timing Table (STS-3 Operation) •••• Plli'i.imehl,.·" .......................... TRXLSCKT TSKEW Range in which the rising edge of FP will appear in relation to the falling edge of RXLSCKOUT +/-1.5 Time data on RXOUT <7:0> is valid before and after the rising edge of RXLSCKOUT 24 Pulse width of frame detection pulse FP us us 51.44 us Figure 10: Transmit High Speed Data Timing Diagram TxCLKOUT+ TxCLKOUT- TxDATAOUT+ TxDATAOUT- G52142-o, Rev. 1.1 Ts~3 M TTXCLK X ~ ® VITESSE 1996 Communications Product Data Book Page 475 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation Table 8: Transmit High Speed Data Timing Table (STS-12 Operation) TSKEW Skew between the falling edge ofTxU-KOUT and valid data on TxDXl'AOUT +/-200 ps Table 9: Transmit High Speed Data Timing Table (STS-3 Operation) ....:iji"H ···.MaX.. · ................ , ...................................................... . Min: TTXCLK Transmit clock period Skew between the falling edge ofTxU-KOUT and valid data on TxDXl'AOUT 6.43 ... llll~is ns +/-200 ps Data Latency The VSC8111 contains several operating modes, each of which exercise different logic paths through the part. Table 10 bounds the data latency through each path with an associated clock Signal. Table 10: Data Latency Byte data TXIN<7:O>to byte data on RXOUT<7:0> Facilities Loopback Page 476 MSB at RxDXl'AIN to MSB at TxDXl'AOUT TxCLKOUT 19-33 17-31 RxU-KIN 10 10 ® VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation Absolute Maximum Ratings(1) Power Supply Voltage (VOO) Potential to GND ................................................................................-0.5V to +4V DC Input Voltage (pECL inputs) ............................................................................................ -0.5V to VDD +O.5V DC Input Voltage (TIL inputs) ......................................................................................................... -0.5V to 5.5V DC Output Voltage (TIL Outputs) ........................................................................................ -O.5V to VDD + 0.5V Output Current (TIL Outputs) ................................................................................................................ +/-50mA Output Current (PECL Outputs) ............................................................................................................... +/-50mA Case Temperature Under Bias ......................................................................................................... _55° to +125°C Storage Temperature ..................................................................................................................... -65°C to +150oC Maximum Input ESD (Human Body Model) .............................................................................................. 1500 V Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VOO) ................................................................................................................ +3.3V±5 % Commercial Operating Temperature Range* (1) .................................................................................. 0° to 70°C * Lower limit ofspecification is ambient temperature and upper limit is case temperature. G52142-o, Rev. 1.1 @ VrrESSE 1996 Communications Product Data Book Page 477 Preliminary Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation DC Characteristics Table 11: PECl and TTL Inputs and Outputs '.PatlUllllten ,- ........................... ........ V OH ••••• •~~4ip~o~ ........ ....... Output HIGH voltage (TTL) VOL Output LOW voltage (TTL) AVOUI75 Serial Output voltage swing (TX+fTX-) AVOUTSO "'MiD." ...... •••••• Facility loopback, active high +3.3V Digital Logic Power Supply I TTL Test pin enable. Tie low for system operation 4 I TIL Resets frame detection, dividers, controls, and tristates TTL outputs; active high LOOPTIMO 5 I TIL Enable loop timing operation; active IllGH BO 6 I TIL Reference clock select, refer to table 12 Bl 7 I TTL Reference clock select, refer to table 12 B2 8 I TTL Reference clock select, refer to table 12 VDDP 9 +3.3V PECL JJO Power Supply TXDATAOUf+ 10 0 PECL Transmit output, high speed differential data + TXDATAOUf- 11 0 PECL Transmit output, high speed differential data - VSSD 12 TxCLKOUf+ 13 TxCLKOUf- 14 VDDP 15 LOSPECL 16 N/C 17 GND Digital Logic Ground 0 PECL Transmit high speed clock differential output+ 0 PECL Transmit high speed clock differential output- I +3.3V PECL JJO Power Supply PECL PECL Loss Of Signal control No Cmmection VSSD 18 GND Digital Logic Ground RxCLKIN+ 19 I PECL Receive high speed differential clock input+ RxCLKIN- 20 I PECL Receive high speed differential clock input- +3.3V Digital Logic Power Supply VDDD 21 OOF 22 I TTL Out Of Frame; Frame detection initiated with high level LOSTTL 23 I TTL TIL Loss Of Signal control RXDATAIN+ 24 I PECL Receive high speed differential data input+ RXDATAIN- 25 I PECL Receive high speed differential data input- NC 26 No connection NC 27 No connection VDDD 28 NC 29 3SCIPNC 30 Page 480 +3.3V Digital Logic Power Supply TTL Test mode input Tie low for system operation No connection I @ VITESSE Semiconductor Corporation G52142-o, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation .... ........................ .................... LeveL . . ·····signal·····.·· .................... .••...1'in.,,~•.~. ~~",•• TT /H VDDT 31 +3.3V TTL Output Power Supply _VSCOPNC 32 0 PECL Test mode output RX50MCK 33 0 TTL Constant 51.84Mhz reference clock output, derived from the Clock Multiplier Unit VSST 34 GND Ground RXOUTO 35 0 TTL Receive output data bitO RXOUT1 36 0 TTL Receive output data bitl VSST 37 GND TTL Output Ground RXOUT2 38 0 TTL Receive output data bit2 RXOUT3 39 0 VSST 40 RXOUT4 41 RXOUT5 42 TTL Receive output data bit3 GND TTL Output Ground 0 TTL Receive output data bit4 0 TTL Receive output data bitS VSST 43 GND TTL Output Ground RXOUT6 44 0 TTL Receive output data bit6 RXOUT7 45 0 TTL Receive output data bit7 VSST 46 GND TTL Output Ground RXLSCKOUT 47 0 TTL Receive byte clock output FP 48 0 TTL Frame detection pulse VDDT 49 +3.3V TTL Output Power Supply N/C 50 No Connection N/C 51 No Connection N/C 52 No Connection N/C 53 VDDD 54 +3.3V Digital Logic Power Supply VSSD 55 GND Digital Logic Ground No Connection REFCLK 56 I TTL Reference clock input, refer to table 13 LOOPTIMI 57 I TTL Enable loop timing operation; active ffiGH VDDT 58 +3.3V +3.3 volt supply (CMU) VSSANA 59 Analog Ground (CMU) VSSANA 60 GND GND N/C 61 No connection N/C 62 No connection G52142-G, Rev. 1.1 Analog Ground (eMU) ® VrrESSE 1996 Communications Product Data Book Page 481 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation /T~i8r1#:i ::ii::i~~:.·iiq ·i·i i i:i·.:~~ii! ..................................................................... i .•. ·:::~pe~~~~~: N/C 63 No connection N/C 64 No connection N/C 65 No connection No connection N/C 66 VDDANA 67 +3.3V Analog Power Supply (CMU) VDDANA 68 +3.3V Analog Power Supply (CMU) VDDANA 69 +3.3V Analog Power Supply (eMU) VSSANA 70 GND Analog Ground (CMU) VSSANA 71 GND Analog Ground (CMU) VSSD 72 GND Digital Logic Ground N/C 73 N/C 74 VSSD 75 No connection No connection GND Digital Logic Ground Digital Logic Power Supply VDDD 76 +3.3V C1P 77 Analog CMU external capacitor pin 1 positive terminal C2P 78 Analog CMU external capacitor pin 2 positive terminal C1N 79 Analog CMU external capacitor pin 1 negative tenninal C2N 80 Analog VDDT 81 +3.3V TTL Oulput Power Supply CMU external capacitor pin 2 negative tenninal TXLSCKOUT 82 0 TTL Transmit byte clock out I TXLSCKIN 83 TTL Transmit byte clock in VSST 84 GND TTL Oulput Ground TXIN7 85 TTL Transmit input data bit7 TXIN6 86 TTL Transmit input data bit6 VSSD 87 GND Digital Logic Ground TXIN5 88 TTL Transmit input data bit5 TXIN4 89 TTL Transmit iuput data bit4 TTL Transmit iuput data bit3 No connection N/C 90 TXIN3 91 TXIN2 92 TTL Transmit iuput data bit2 VSSD 93 GND Digital Logic Ground TXINl 94 TTL Transmit iuput data bitl TXINO 95 TTL Transmit input data bitO Page 482 @ VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet G52142-o. Rev. 1.1 ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation ® vrrESSE 1996 Communications Product Data Book Page 483 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Package Information 100 PQFP Package Drawings :::'fIliDi,:::: ;::::mm: .... :YOiOna;e:: A 3AO MAX Al 0.60 MAX A2 2.7 ±.IO D 17.20 ±AO DI 14.00 ±.IO H 23.20 ±.40 HI 20.00 ±.1O L 0.80 ±.2 0.65 NOM b 030 ±.IO e 0-10' R .25 NOM RI .2 NOM ~. 8.0 X 8.0 --I==$$=H-+I T HEATSINK INTRUSION NumS: (1) Drawl1lg. 710//0 _Ie. :-:o';"'o!:froado,. (2):; ~~:.% (3) AU lUll" band/lime,.,. Page 484 8 VITESSE Semiconductor Corporation G52142-0, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SOH 155/622 Mb/s Transceiver MuxlOemux with Integrated Clock Generation The VSC8111 is manufactured in a 100PQFP package which is supplied by two different vendors. The critical dimensions in the drawing represent the superset of dimensions for both packages. The significant difference between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink. Package Thermal Characteristics The VSC8111 is packaged in a thermally enhanced 100PQFP with an embedded heat sink. The heat sink surface configurations are shown in the package .drawings. With natural convection, the case to air thermal resistance is estimated to be 27.5°C/W. The air flow versus thermal resistance relationship is shown in Table 16. Table 16: Theta Case to Ambient versus Air Velocity AirV!ilQ~itY G52142-o. Rev. 1.1 •dQ,e IQalT iiJe;11f4irniitJm~e o .·.· · . . . ·. . ····.·~c.iW·· . . ··············· 27.5 ~fj>iIlF ......... , 100 23.1 200 19.8 400 17.6 600 16 ... ® VrrESSE 1996 Communications Product Data Book Page 485 ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Preliminary Data Sheet Ordering Information The order number for this product are: Part Number VSC8111QB: VSC8111QB1 Device Type 155Mb1s-622Mb1s Mux/Dmux with CMU in 100 Pin PQFP Commercial temperature, DoC ambient to 70° case 155Mb1s-622Mb1s Mux/Dmux with CMU in 100Pin PQFP 0° ambient to 1100 case Notice This document contains information on products that are in the preproduction phase of development The information contained in this document is based on test results and initial product characterization. Characteristic data and other specifications are subject to change without notice. Therefore, the reader is cautioned to confirm that this datasheet is current prior to placing orders. Warning ViteBse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 486 ~ VlTESSE Semiconductor Corporation G52142-o, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Application Notes Interconnecting the Byte Clocks (TXLSCKOUT and TXLSCKIN) The byte clock (TXLSCKOUT and TXLSCKIN) on the VSC8111 has been brought off-chip to allow as much flexibility in system-level clocking schemes as possible. Since the byte clock (TXLSCKOUT) clocks both the VSC8111 and the UN! devices, it is important to pay close attention to the routing of this signal. The UNI device in general is a CMOS part which can have very wide spreads in timing (l-11ns clock in to parallel data out for the PM5355), which utilizes most of the 12.86ns period (at 78Mhz), leaving little for the trace delays and set-up times required to interconnect the 2 devices. The recommended way of routing this clock when used in a 622Mhz mode is to daisy chain it to the UNI device pin and then route it back to the VSC8111 along with the byte data. This eliminates the I-way trace delay that would otherwise be encountered between the data and clock and thus leaves 1.86ns for the VSC8111 setup time and for variations in trace delays and rise times between clock and data. The trace delay must be kept under 2ns (allowing an additional Ins for variations in rise times and skews) to ensure proper muxing ofparallelinput data into the VSC8111; reference Table 4and 5. AC Coupling and Terminating High-speed II0s The high speed signals on the VSC8111 (RXDATAIN, RXCLKIN, TXDATAOUT, TXCLKOUT) use 3.3V PECL levels which are essentially ECL levels shifted positive by 3.3 volts. The PECL 1I0s are referenced to the V DD supply and are terminated to ground. Since most optics modules use either ECL or 5.0V PECL levels, the high speed ports need to be ac coupled to overcome the difference in dc levels. The PECL receiver inputs of the VSC8111 are internally biased at VDDI2. Therefore, AC-coupling to the VSC8111 inputs is accomplished by providing the pull-down resistor for the open-source PECL output and an AC-coupling capacitor used to eliminate the DC component of the output signal. This capacitor allows the PECL receivers of the VSC8111 to self-bias via its internal resistor divider network (see Figure 12). The PECL output drivers are capable of sourcing current but not sinking it. To establish a LOW output level, a pull-down resistor, traditionally connected to VDD-2.0V, is needed when the output FET is turned off. Since VDD-2.0V is usually not present in the system, the resistor should be terminated to ground for convenience. The VSC8111 output drivers should be AC-coupled to the 5.0V PECL inputs of the optics module. Appropriate biasing techniques for setting the DC-level of these inputs should be employed. The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 11. The figure shows the appropriate termination values when interfacing 3.3V PECL to 5.0V PECL. This network provides the equivalent 50 ohm termination for the high speed liDs and also provides the required dc biasing for the receivers of the optics module. Table 17 contains recommended values for each of the components. The TTL inputs of the VSC8111 are 3.3V TIL which can accept 5.0V TTL levels within a giving set of tolerances (see Table 11). These input structures shown in Figure 12 use a current limiter to avoid overdriving the inputFETs. G52142-0, Rev. 1.1 @ VrrESSE 1996 Communications Product Data Book Page 487 Preliminary Data Sheet ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Layout of the 622 Signals The routing of the 622 signals should be done using good high speed design practices. This would include using controlled impedance lines and keeping the distance between components to an absolute minimum. In addition, stubs should be kept at a minimum as well as any routing discontinuities. This will help minimize reflections and ringing on the high speed lines and insure the maximum eye opening. In addition the output pull down resistor should be placed as close to the VSC8111 pin as possible while the AC-coupling capacitor and the biasing resistors should be placed as close as possible to the optics input pin. The same is true on the receive circuit side. Using small outline components and minimum pad sizes also helps in reducing discontinuities. Ground Planes The ground plane for the components used in the 622 interface should be continuous and not sectioned in an attempt to provide isolation to various components. Sectioning of the ground planes tends to interfere with the ground return currents on the signal lines as well as in general, the smaller the ground planes the less effective they are in reducing ground bounce noise and the more difficult to decouple etc. Sectioning of the positive supplies can provide some isolation benefits. Figure 11: AC Coupled High Speed 110 VSC8111 PECL PECL PECL Output Input/Output Input + 5 Volt Supply VOO +3.3 Volt Supply + 5 Volt Supply ~Cl Vss Ground Vss Ground Table 17: AC Coupling Component Values Page 488 R1 182 ohms 1% R2 182 ohms 1% R3 680bms 1% R4 C1,C2,C3 190 ohms 1% .01ufHigh Frequency e V"ESSE Semiconductor Corporation G52142-D, Rev. 1.1 Preliminary Data Sheet ATM/SONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Figure 12: Input Structures VDD +3.3V INPUT Ol--.-t---.--t--, INPUT 01-+----+-1 GND REFCLK and TTL Inputs G52142-0. Rev. 1.1 @ High Speed Differential Input (RXDATAIN+lRXDATAIN-) (RXCLKIN+lRXCLKIN-) VITESSE 1996 Communications Product Data Book Page 489 ATMISONET/SDH 155/622 Mb/s Transceiver MuxlDemux with Integrated Clock Generation Page 490 ® VrrESSE Semiconductor Corporation Preliminary Data Sheet GS2142-0, Rev. 1.1 VITESSE Advanced Product Information SONET/SDH 622 Mb/s 4-bit Mux Demux with Integrated Clock Generation Features • Operates as a Bit-serial STS-3/STM-1 to STS-121STM-4 Mux/Dmux • On Chip Clock Generation of the 622.08 Mhz High Speed Clock, 155.52 Mhz Reference Clock • Fully Differential VECL Clock and Data 110 • Provides Equipment and Facilities Loopback • Low Power - 1.5 Watts Maximum • Dual Supply Operation- +2, +5 Volts ·100 PQFP Package • Extended Temperature Range O"C - 110·C case • Integrated PLL for Clock Generation No External Components General Description The VSC8112 is a SONET/SDH rate compatible 4-bit STS-3/STM-1 to STS-l21STM-4 Mux/Dmux with integrated high speed clock generation. The high speed clock is generated using an on-chip PLL with a 155.52 Mhz reference clock. To facilitate testing, the part has a test clock input which can be used in place of the internally generated 622 Mhz clock. In addition, the device provides both facility and equipment loopback modes. The part is packaged in a 100PQFP with integrated heat spreader for optimum thermal performance and reduced cost. Given the worst case maximum power consumption of 1.5 Watts, extended temperatUre range of + 11 0 ·C case, and no air flow, a corresponding +70 ·C ambient temperature can be achieved without a heat sink. VSC8112 Block Diagram RXOUI'<3:0>+ RXOUI'<3:O>- RXDATAIN+ RXDATAINEQULOOP RXCLKIN+ RXCLKIN- RXCLKOUT -+---+-t---t>I RESID' 1XCLKOUT+ 1XCLKOUTFACLOOP TXIN<3:0>+ TXIN<3:0>- 1XDATAOUI'+ 1XDATAOUTr- 1XCLKSBLO 1XCLKSELI G52136-O Rev. 1.2 _J~I::=:::--===-+ T.X'ISTCLK+ T.X'ISTCLKRBFCLK+ REFCLK- ® VITESSE 1996 Communications Product Data Book Page 491 SONET/SOH 622 Mb/s 4-bit MuxlOemux with Integrated Clock Generation Advanced Product Information FuncuonalDescnpuon The VSCS112 converts 4 parallel bits at 155.52Mhz to a serial bit stream at 622.0SMb/s. The transmit section provides It Facility Loopback function which loops the received high speed data and clock directly to the transmit outputs. A clock multiplier unit is integrated into the transmit circuit to generate the high speed clock for the serial output data stream from an input reference frequency of 155.52Mhz. The block diagram on page 1 shows the major functional blocks associated with the VSCSI12. The receive circuit provides the demux function, converting a 622Mb/s serial bit stream to a 4 bit parallel output at 155.52Mhz. The receive section provides an Equipment Loopback function which will loop the high speed transmit data and clock back through the demultiplexer to the 4 bit parallel outputs. Transmit Circuit Half-byte-wide data is presented to TXIN<3:0> and is clocked into the part on the rising edge of TXLSCKOUT. The data is serialized (MSB leading) and presented at the TXOUT+1- pins. The Clock Multiplier Unit (CMU) generates the high speed clock required for serialization and transmission. The high speed clock accompanying the transmitted data appears on the TXCLKOUT+I- pins. Two select lines, TXCLKSELO and TXCLKSELl, control the selection of the TXCLKOUT clock. One can chose from the PLL output (622.02Mhz), the PLL output divided by 12 (51.S4Mhz), a test clock input (TXTSTCLKIN) or the reference clock, which is 155.52Mhz. Please refer to table 9 for the definition of these 2 select lines. The Facility Loopback mode is set by FACLOOP and is active low. Receive Circuit 622Mb1s serial data and 622Mhz clock are input to RXIN+I- and RXCLKIN+I- pins respectively. This data is converted to half-byte-wide parallel data and presented on the RXOUT<3:0> pins. The received high speed clock is divided by 4 and presented on the RXCLKOUT pin. The Equipment Loopback mode is set by EQULOOP and is active low. Page 492 CIJ) VITESSE Semiconductor Corporation GS2136-0 Rev. 1.2 Advanced Product Information SONET/SDH 622 Mb/s 4-bit Mux Demux with Integrated Clock Generation AC Timing Characteristics Figure 1: Receive High Speed Data Input Timing Diagram TRXCLKIN RXCLKIN+ RXCLKIN - TRXSU TRXH ~ RXDATAIN+ RXDATAIN- Table 1: Receive High Speed Data InputTimlng Table T RXCLKIN TRJ{H Receive clock period Serial data setup time with respect to RXa..KIN Serial data hold time with respect to RXCLKIN 1.608 300 600 DB ps ps Figure 2: Transmit Data Input Timing Diagram TTXCLKIN TXLSCKOUT + TXIN<3:0>- Table 2: Transmit Data Input Timing Table TTXCLKIN TTXSU TTXH Transmit data input byte clock period Transmit data setup time with respect to TXLSCKOUT Transmit data hold time with respect to TXLSCKOUT 12.86 2150 -750 DB ps ps Note: Duty cycle for TXLSCKOUT is 50% +/- 5% WOT.S'e case G52136-0 Rev. 1.2 (!j) VITESSE 1996 Communications Product Data Book Page 493 SONEr/SOH 622 Mb/s 4-bit MuxlOemux with Integrated Clock Generation Advanced Product Information Figure 3: Receive Data Output Timing Diagram RXCLKOUT+ RXCLKOUT- RXOUT<3:0>+ RXOUT<3:0>- Table 3: Receive Data Output Timing Table TRXCLKOU Receive clock period 1.608 DB T TRXSKBW Skew between the falling edge ofRXCLKOUT and valid data on RXOUT<3;(» TBD ps Figure 4: Transmit. Data OutputTlmlng Diagram TXCLKOUT+ TXCLKOUT- TXDATAOUT+ TXDATAOUT- . Table 4: Transmit Data OutputTlmlng Table Transmit clock period Skew between the falling edge ofTXCLKOUT and valid data on TXDATAOUT Page 494 8 VITESSESemiconductor Corporation 1.608 DB TBD ps G521SS-o Rev. 1.2 Advanced Product Information SONET/SDH 622 Mb/s 4-bit Mux Demux with Integrated Clock Generation DC Characteristics Table 5: VECL Inputs and Outputs Note: Differential VECL ollipul pins must be terminated identically. Table 6: TTL Inputs and Outputs !(,fIl~ ............................................ •• ·.piikcr,iptJiJll .......... · . ·.... M.I~ •.. .ijp .M.~ ··lirl#s:.¢o.1i4~~ mV VIN = Vm (max) orVn.. (min) 1oIf'-2.4mA V OH Output mGH voltage 2.4 VOL Output LOW voltage ° 0.5 mV Vm Input HIGH voltage 2.0 VTIL+1. ° mV Vn.. Input LOW voltage ° 0.8 mV 1m Input mGH CUIl'ent 50 uA VnrVm(max) IlL Input LOW C\UTent uA VnrVn..(min) uA Vour=2.4V Vour=°.5V IoZH IoZL G52136-0 Rev. 1.2 -500 3-State Output OFF CUIl'ent mGH 3-State Output OFF CUIl'ent LOW 200 -200 uA e VITESSE 1996Communications Product Data Book VIN=Vm(max) orVn.. (min) IoL=8mA Guaranteed mGH signal for all inputs Guaranteed LOW signal for all inputs Page 495 Advanced Product.lnformation SONET/SDH 622 Mbls 4-bit MuxlDemux with Integrated Clock Generation Power Dissipation Table 7: Power Supply Currents :: IMM ::: Power supply current from VMM Power supply Current from VTJL Power dissipation 1m. Note: Specified with outputs open circuit. The combined maximum currents 286 mA 170 mA 1.50 w a... 1",) for any part wiU not exceed 1.50 Watts. Clock Multiplier Unit Table 8: TX Clock Selection .......................................... jjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjjj o o o o 622.08 155.52 TXTSTCLK TXTSTCLKl4 REFCLK REFCLKl4 51.84 12.96 Table 9: Clock Multiplier Unit Perfonnance :.. " . : : : : : . . . . H . . . . . . . ::::::::::::::::::::::::' .. : . : . . : : : p.fij~,:~tp~:l4iii RCd Reference clock duty cycle RCj Reference clock jitter (RMS) Ocd Output clock duty cycle OCj Output clock jitter (RMS) OCfmin OCfmax 40 40 @ . . . ... H. >::.H: ..Mi~.::/~j( . . .Md.tHP~@" 155.52 MHz ref Minimum output frequency Maximum output frequency 60 % 5 ps 60 % 10 ps 620 MHz MHz 624 Note: Jitter specification is defined utilizing a 12KHz - 5MHz LP-HP single pole filter. Page 496 @ VITESSE Semiconductor Corporation· GS2136-0 Rev. 1.2 Advanced Product Information SONET/SOH 622 Mb/s 4-bit Mux Oemux with Integrated Clock Generation Data Latency The VSC8l12 contains several operating modes, each of which exercise different logic paths through the part. Table 5 bounds the data latency through each path with an associated clock signal. Table 10: Data Latency ................................ ................................ ................................ ";::::;::::::;::::::,, H¢i)j¥ •• ::::LjiangeqiL ¢ir~u#MQil~ Transmit Receive .ll;e[~ .::.::F"l#~f*~~> MSB at RXDATAIN to data onRXOUT<3:0> Equipment Loopback Byte data TXIN<3:O> to byte data onRXOUT<3:O> Facilities Loopback MSB at RXDATAIN to MSB at TXDATAOUT TXCLKOUT TBD RXCLKIN TBD TXCLKOUT TBD RXCLKIN TBD Absolute Maximum Ratings(1) Power Supply Voltage (VMM) Potential to GND .............................................................................-O.5V to +2.5V Power Supply Voltage (V~ Potential to GND .............................................................................-0.5V to +5.5V TTL Input Voltage Applied ................................................................................................... -O.5V to VTIL + 1.0V VECL Input Voltage Applied ................................................................................................ -0.5V to V MM + 1.0V Output Current (lour) .................................................................................................................................... 50mA Case Temperature Under Bias (Tc) ................................................................................................ _55· to + l25·C Storage Temperature (TSTG) •••••.•••.••.••..•••••..•••.••.•••...••.••.•••••••••••••••••••••..•.••...••••.••••••••••.•...•.••..•••.••••• _65· to + l50·C Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltage (VMM) ................................................................................................................+ 2.0V ±5 % Power Supply Voltage (V~ ................................................................................................................+5.0V±5 % Extended Operating Temperature Range* (T) ...................................................................................... O· to 110·C * Lower limit of specification is ambient temperature and upper limit is case temperature. ESDRatings Proper ESD procedures should be used when handling this product. The VSC8ll2 is rated to the following ESD voltages based on the human body model: 1. All pins are rated at or above 1500V. G52136-0 Rev. 1.2 ® VITESSE 1996 Communications Product Data Book Page 497 Advanced Product Information SONET/SDH 622 Mbls 4-bit MuxlDemux with Integrated Clock Generation Package Pin Description Table 11: Pin Definitions NC No connection VMM 2 +2.0V +2 volt supply _vscrn 3 TIL Test pin enable. Tie low for system operation RESET 4 TTL Resets 1:4 Mux and 4:1 Dmux. and tristates TTL outputs; active high NC 5 No connection NC 6 No connection NC 7 No connection NC 8 VMM 9 TXDATAOUf+ 10 TXDATAOUf- 11 VCC 12 TXCLKOUf+ 13 TXCLKOUf- 14 VMM 15 NC 16 No connection NC 17 No connection I No connection o o o o +2.0V +2 volt supply VECL Transmit output, high speed differential data + VECL Transmit output, high speed differential data - GND GroWld VECL Transmit high speed clock differential output+ VECL Transmit high speed clock differential output- +2.0V +2 volt supply VCC 18 GND GroWld RXDATAIN+ 19 I VECL Receive high speed differential data input+ RXDATAIN- 20 I VECL Receive high speed differential data input- VMM 21 +2.0V +2 volt supply NC 22 NC 23 RXCLKIN+ 24 VECL Receive high speed differential clock input+ RXCLKIN- 25 VECL Receive high speed differential clock input- NC 26 No connection NC 27 No connection VMM 28 NC 29 _VSCIPNC No connection No connection +2.0V +2 volt supply 30 TIL Test mode input. Tie low for system operation VTIL 31 +5.0V +5 volt supply _VSCOPNC 32 VECL Test mode output Page 498 No connection o ~ VITESSE Semiconductor Corporation G5213S-o Rev. 1.2 Advanced Product Information , ~~ .............. ", ....... ",,',.................... .SigMi:.:"'~: SONET/SOH 622 Mb/s 4-bit Mux Oemux with Integrated Clock Generation L6j;(d :~ ~ ", ~ ~ II, ." NC 33 VMM 34 ~ ,Pi;'"ri "'_' 'c No connection +2.0V Ground RXOUTO+ 35 0 VECL Receive output data bitD+ RXOUTO- 36 0 VECL Receive output data bitO- vee 37 RXOUT1+ 38 RXOUT1- 39 VMM 40 RXOUT2+ 41 RXOUT2- 42 vee 43 RXOUT3+ 44 RXOUT3- 45 GND Ground 0 VECL Receive output data bitl + 0 VECL Receive output data bitl- +2.0V +2 volt supply 0 VECL Receive output data bit2+ 0 VECL Receive output data bit2- GND Ground 0 VECL Receive output data bit3+ 0 VECL Receive output data bit3- VMM 46 +2.0V +2 volt supply RXCLKOUT+ 47 0 VECL Receive output clock+ RXCLKOUT- 48 0 VECL Receive output clock- VTIL 49 NC 50 No connection NC 51 No connection NC 52 No connection +5.0V +5 volt supply NC 53 VMM 54 +2V vee 55 GND Ground REFCLK+ 56 I VECL Differential 155.52 Mhz reference clock input+ REFCLK- 57 I VECL Differential 155.52 Mhz reference clock input- VTIL 58 +5.0V +5 volt supply vee 59 Ground VCC 60 GND GND NC 61 No connection NC 62 No connection NC 63 No connection NC 64 No connection NC 65 No connection NC 66 No connection G52136-0 Rev. 1.2 ::: :~: .~:.:~,,~:~~ :~~,,!~: No connection @ +2 volt supply Ground VrrESSE 1996 Communications Product Data Book Page 499 Advanced Product Information SONETISDH 622 Mb/s 4-bit MuxlDemux with Integrated Clock Generation .. .. ... ......... .. ............. ....................... .. .......... ::::110:: : HiAvei HTPin ...... .................... H~I##l#:: ... :................ jji~:ri ::.! VTIL 67 +5.0V +5 volt supply VTIL 68 +5.0V +5 volt supply VTIL 69 +5.0V +5 volt supply vex vex vex 70 GND Ground 71 GND GND Ground TXTSTCLK+ 73 I VECL Test clock input+ TXTSTCLK- 74 I VECL Test clock input- vex 75 GND Ground VMM 76 +2.0V NC 77 No connection NC 78 No connection 72 79 I TIL Test clock select line 0 80 I TIL Test clock select line 1 VTIL 81 TXLSCKOUT+ 82 TXLSCKOUT- 83 VMM 84 FACLOOP 85 I I 86 87 TXlN3+ 88 TXlN3- 89 +5.0V +5 volt supply 0 VECL Transmit half-byte clock out+ 0 VECL Transmit half-byte clock out- +2.0V +2 volt supply TTL Facility loopback, active low TTL Equipment loopback, active low GND Ground I VECL Transmit input data bit3+ I VECL Transmit input data bit3- VMM 90 +2.0V +2 volt supply TXIN2+ 91 I VECL Transmit input data bit2+ TXIN2- 92 I VECL Transmit input data bit2- vex 93 GND Ground TXlNl+ 94 I VECL Transmit input data bitt + TXIN1- 95 I VECL Transmit input data bitl- VMM 96 +2.0V +2 volt supply TXINO+ 97 I VECL Transmit input data bitO+ TXlNO- 98 I VECL Transmit input data bitO- VTIL 99 NC 100 Page 500 +5.0V :"::,, ::.: : ........ +2 volt supply TXCLKSELO EQULOOP ;.:,c,,;.;~~ Ground TXCLKSELI vex "::,, +5 volt supply No connection @ VITESSE Semiconductor Corporation G52136-0 Rev. 1.2 Advanced Product Information SONET/SDH 622 Mb/s 4-bit Mux Demux with Integrated Clock Generation The VSC8112 is manufactured in a 100PQFP package which is supplied by two different vendors. The critical dimensions in the drawing represent the superset of dimensions for both packages. The significant difference between the two packages is in the shape and size of the heatspreader which needs to be considered when attaching a heatsink. Package Thermal Characteristics The VSC8112 is packaged in a thermally enhanced 100PQFP with an embedded heat sink. The heat sink surface configurations are shown in the package drawings. The air flow versus thermal resistance relationship is shown in table 12. With natural convection, the case to air thermal resistance is estimated to be 27.5°C/W. Therefore, at 70°C ambient with no air flow, no heat sink is required because of the extended operating temperature range of O°C to llO"C. Table 12: Theta Case to Ambient versus Air Velocity G52136-0 Rev. 1.2 @ VITESSE 1996 Communications Product Data Book Page 501 SONETISDH 622 Mbls 4-bit MuxlDemux with Integrated Clock Generation Advanced Product Information Package Information 1(}() PQFP Package Drawing' :~ :::::~ '., ;;~~: A 3.40 MAX AI 0.60 MAX A2 2.7 ±.IO D 17.20 ±.40 DI 14.00 ±.IO E 23.20 ±.40 EI 20.00 ±.IO L 0.80 ±.2 0.65 NOM 0.30 ±.IO b 0-10" R .25 NOM RI .2 NOM ~. 9.0X9.0-~~-.! T HEATSINK INTRUSION NarES: (1) Drawm,. 7I011o_1e. (2):; ~~:.1 :::O':::tT8lJtkrl (3) AU umla in millime"" Page 502 ® VrrESSE Semiconductor Corporation G52136-0 Rev. 1.2 Advanced Product Information SONET/SDH 622 Mb/s 4-bit Mux Demux with Integrated Clock Generation Ordering Information The order number for this product are: Part Number VSC8112QBl: Device Type 622Mb1s 4-bit MuxlDmux witJi CMU in 100 Pin PQFP Extended temperature Notice This document contains information about a new product during its fabrication or early sampling phase of development. The information in this document is based on design targets, simulation results or early prototype test results. Characteristic data and other specifications are subject to change without notice. Therefore the reader is cautioned to confirm that this datasheet is current prior to design or order placement. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52136-0 Rev. 1.2 @ VITESSE 1996 Communications Product Data Book Page 503 Advanced Product Information SONET/SDH 622 Mb/s 4-bit MuxlDemux with Integrated Clock Generation Application Notes 2 Volt Supply Generation From 5 Volts The 2 volt supply can be generated from the 5 volt supply using a linear regulator. There are many manufacturers who supply linear regulators. Refer to Table 13 for examples. Table 13: Recommended 2 Volt Voltage Regulator REG1lt7 800mA LTlt7A 800mA Burr Brown 800-548-6132 Linear Technology AC Coupling and Terminating VECL Dlfferentiall/Os All the clock and data signals on the VSC8112 use VECL levels which are essentially ECL levels shifted positive by 2 volts. The VECL 1I0s are referenced to the VMM supply and are terminated to ground Since most optics modules use either EeL or PECL levels, the high speed ports need to be ac coupled to overcome the difference in dc levels. In addition, the inputs must be dc biased to hold the inputs at their threshold value with no signal applied The dc biasing and 50 ohm termination requirements can easily be integrated together using a thevenin equivalent circuit as shown in Figure 5. The figure shows the appropriate termination values when intedacing PECL to VECL and VECL to PECL. This network provides the equivalent 50 ohm termination for the high speed 1I0s and also provides the required de biasing for both the drivers and receivers. Table 14 contains recommended values for each of the components. Figure 5: AC Coupled High Speed I/O PECL Output VECL Input/Output PECL Input + 5 Volt Supply VMM +2 Volt Supply + 5 Volt Supply ~I ~ R2 R3 VccGround Table 14: AC Coupling Component Values •••. H ....HjhkraneeH . . . . . ..... . .. . .... ... ......................... .¢~1RP.~~~¥ ............................. . R3 270 ohms 147 ohms 76 ohms R4 50 -100 olnns R5 R6 C1, C2, C3, C4 190 ohms R1 R2 Page 504 68 ohms . •••• 1% 1% 1% 1% 1% 1% .01ufHigh Frequency 8 VrrESSE Semiconductor Corporation G52136-0 Rev. 1.2 VITESSE Data Sheet 200 Mbls 64 x 64 Crosspoint Switch Features • 200 Mb/s Operation • Duty-cycle Distortion: • Power Dissipation: 9.4 Watts (Typ.) ~ 10% • Clocked or Flow-through Operation • EeL lOOK Compatible I/O • ~ 1500 ps Output to Output Skew (clocked mode) • 25.0 Output Drive • Single Power Supply: -2 V ± 5% • Commercial (0 0 to +70 0 C) or Industrial (_40 0 to +85 0 C) Temperature Ranges • Full Diagnostic Monitors • Cascadable for Larger System Requirements • Package: 344-pin Ceramic LDCC General Description The VSC864A-2 is a 64 x 64 crosspoint switch intended for high speed (up to 200 Mb/s) digital data communications applications. This product has 64 data inputs and 64 data outputs. Any input can be multiplexed to any, some, or all outputs. High speed digital data up to 200 Mbls can be switched with less than 20% pulse width distortion. In broadcast mode, any two outputs will exhibit less than 1500 ps of skew. All interfaces are fully compatible with EeL FlOOK logic levels. The VSC864A-2 requires only a single -2 V power supply. A separate Q bus is provided to allow observation of individual internal multiplexer address latches. Since the VSC864A-2 outputs are capable of driving 25.0 double-terminated buses with cutoff drivers, the device can be cascaded to form larger crosspoint switches. The VSC864A-2 Crosspoint Switch can be operated in either flow-through or synchronous mode by use of internal input and output data registers. In flow-through mode the data propagation delay is less than 5.8 ns. The individual address registers in the VSC864A-2 are double buffered. A local strobe signal is used to load an individual address for each output pin. A global strobe is used to simultaneously activate all 64 destination addresses. This product is ideal for high speed digital applications including data distribution for telecommunications, computer network and multiprocessor switching, and test equipment. In a telecommunications SONET application, for example, the VSC864A-2 can be used as an STS-3 protection switch, or in the fabric of a large switching system. The VSC864A-2 is packaged in a 344 pin ceramic LDCC package and typically dissipates less than 10 W. This product is fabricated using Vitesse's simple, high yielding, BID GaAs MESFET process which achieves high speed coupled with low power dissipation. Functional Description The VSC864A-2 may be used to connect anyone of 64 inputs to any combination of 64 output channels, according to a user defined bit pattern stored in each channel's control latch. During normal operation, signals flow from inputs (10 - 163) to output channels (ZO - Z63) through sixtyfour, 64: 1 multiplexers. The traffic pattern is controllable by data previously stored in sixty-four 7-bit control registers with each register corresponding to an output channel. The first 6 least significant bits in each control register are reserved for designating the MUX input which will be connected to its corresponding output, the most significant bit is used to tri-state this output if desired. The 6 LSBs are a binary numerical representation of the input channel selected (i.e.. , 000000 corresponds to 10,000001 corresponds to 11, etc.). G52132-O Rev. 2.0 @ V1TESSE 1996 Communications Product Data Book Page 505 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch The Write mode is used to alter anyone or all signal paths. During Write mode, inputs AO - A5 select which output channel's control register will be altered (also by a binary numerical representation). Inputs DO- D5 describe the new input signal to be selected for that channel. When a high pulse is applied to LOCAL STROBE, DO- D5 and the TRI bit is transferred into a holding latch. After some or all control registers are programmed, a high pulse is applied to GLOBAL S1R.oBE to transfer the information from the holding latch into all the control registers. In this way the entire crosspoint switch can be reconfigured simultaneously. The Read mode is a diagnostic feature used to examine the data stored in anyone control register and its corresponding 64:1 multiplexer output. The control register to be examined is selected by inputs SO- S5 (by a binary numerical representation). When a high pulse is applied to the TEST STROBE, the contents of the selected control register will be displayed at the QO- Q6 outputs and the corresponding 64:1 mux output will appear at the QD output. When TEST S1ROBE is "low" the Q bus has all low outputs (which is equivalent to being tri-stated). The VSC864A-2 can be configured to run in either synchronous clocked mode or asynchronous flowthrough mode. This feature is controlled by the CIFf input. When CIFf is high, the chip is in clocked mode and will require an input clock at its CK pin. In this mode all input and output data is registered. When CIFf is low the chip is in flow-through mode and will ignore the CK input. In clocked mode, the outputs on the monitor bus (QO- Q6, and QD), and input data (10 - 163) are registered by the master clock (CK). Figure 1: Block Diagram 10-163 CLK~~----------+-----~~------~ c~~------------+------;;-------;----T~ DO-D~ffi/------------~++~--~ Z1 AO-A5 GLOBAL STROBE -------------1 LOCAL SffiOBE ------------+4...... QD ~STSffiOBE::::::::::I==============l1========~~~ SO-S5 QO.Q6 Page 506 @ VlTESSE Semiconductor Corporation G52132-0 Rev. 2.0 200 Mb/s 64 x 64 Crosspoint Switch Data Sheet Absolute Maximum Ratings (1) Power Supply Voltage (ECL), VTT potential to GND ....................................................................-3.0V to +O.5V Input Voltage Applied, VB CLIN ....................................................................................................-2.5V to +0.5V Output Current, IOUT,(DC, output HI) ...................................................................................................... 100 rnA Case Temperature Under Bias, TC ................................................................................................. _55° to + 125°C Storage Temperature (ambient), TSTG ........................................................................................ -65°C to + 150°C Recommended Operating Conditions ECL Supply Voltage, VTT.................................................................................................................. -2.0V ± O.lV Commercial Operating Temperature Range, T(2) .................................................................................. 0° to 70°C Industrial Operating Temperature Range, T(2) ................................................................................... -40° to 85°C NOTES: (1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one ata time without causing permanent damage. Functionality at or above the values listed is not implied. EJeposure to these values for extendedperiods may affect device reliability. (2) Lower limit of specification is ambient temperature and upper limit is case temperature. G52132-0 Rev. 2.0 ® VlTESSE 1996 Communications Product Data Book Page 507 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch. AC Characteristics (Over recommended operating conditions Vee == VeeA = GND Output load 25(J to vrr.) Table 1: Flow-Through Mode. PW Minimwn data valid time 5 tDR Propagation delay (rising) Propagation delay (falling) 2800 foF 2800 Duty cycle distortion Output to output skew Bit Error Rate skew BER ~ 20% Duty Cycle Distortion; 50% input ns 10 5800 5800 20 ps ps % 2500 10-13 ps at 200 Mb/s(l) Ou a given part broadcast mode Note (2) (1) Duty cycle distortion =duty cycle out - duty cycle in / duty cycle in x 100% (2) Based on limited measurement time, not device performance limitations Table 2: Clocked Mode. Table 3: Write Mode. ..... ........ ....... ifiiii;@ii~# tRBCON tALSSU tALSH foISSU foLSH for.su tas,tu m ~ torn Page 508 . ...................... . •• .P~~f~~# . HiWiri ..r)'RiW~ Reconfiguration time A but to LOCAL STROBE set-up time a bus to LOCAL STROBE hold time D bus to LOCAL STROBE set-up time 650 D bus to LOCAL STROBE hold time GLOBAL STROBE to LOCAL STROBE set-up time GLOBAL STROBE and LOCAL STROBE pulse widths LOCAL STROBE low time TEST STROBE pulse width GLOBAL STROBE to LOCAL STROBE hold time @ 1300 ·t1jttiiH~Mi@~H ns 300 ps 0 ps 400 ps 2 ns 5 ns 5 ns 5 6.5 ns 0 ps VlTESSE Semiconductor Corporation Recommended local strobe frequency = 50MHz ns G52132-0 Rev. 2.0 200 Mb/s 64 x 64 Crosspoint Switch Data Sheet ......................... .•Paraftti!i~ ••• •• tcosu GLOBAL STROBE to valid output (llow-through mode) 2.7 a.K to GLOBAL STROBE set-up time (clocked mode) 200 ps Data being clocked in at this time is invalid GLOBAL STROBE to eLK hold time (clocked mode) 3.5 ns Data being clocked in at this time is invalid 5.6 ns TEST STROBE to valid Q output 7.1 ns S bus to valid output 7.1 ns TEST STROBE to tri-state condition onQ 6.5 ns AC Timing Waveforms Figure 2: Flow-through Mode Minimum Data Valid Time, PW Propagation Delay Zo -263 Figure 3: Clocked Mode Input Data Set-up & Hold Times 10 -163 ~ Clock to Output Delay _..II~ CK tcZF~ G52132-0 Rev. 2.0 ® VlTESSE 1996 Communications Product Data Book Page 509 Data Sheet 200 Mbls 64 x 64 Crosspoint Switch Figure 4: Write Mode --------lr------- Ao-As A address setup andholdrela- LOCAL --....Ir--~---~--',-------~- tiveto LOCAL STROBE. 'ALSH STROBE D data setup and hold relative to LOCAL STROBR Do-DS' TRI GLOBAL STROBE ~-- Z (output data) LOCAL STROBE to GLOBAL STROBE timing rela- ' - - - - - - tionship. a.K CLOCKED MODE - GLOBAL STROBE to CLK timing relationship. Figura 5: Read Mode So - Ss TEST STROBE --t~TSu-i ~tSTHl----- --+--t#--- Agura 6: Block Diagram of Internal Write Mode Circuits DBUS-----------------~ 1------ To 64:1 Mux Select Lines LOCAL STROBE - - - - - - - - - , A BUS--__'" G L O B A L - - - - - - - - - - - - - - - - - - - - -..... STROBE Page 510 8 VlTESSE Semiconductor Corporation G52132-o Rev. 2.0 200 Mb/s 64 x 64 Crosspoint Switch Data Sheet Table 4: Pin Description [H> I • -'1#. tlO IC••••••••••••••••••••• ·••••• •• • ·.H·.· :On ••• ••• <1V;~ 12-16,20-30, 35-45, 188, 192- 202, " •••••• IR<1. ."'. ·........... ·. ·.· ... ··· ..•............ ·····1 10 - 163 1 The 64 ECL signal inputs. 11 TRI 1 ECL input containing Tristate data to be loaded into a 64:1 Mux holding latch. (fristate HIGH) Combined with a control register's destination address. Used to tristate the corresponding output. 5-10 DO-D5 1 ECL inputs containing the destination address to be loaded into the 64:1 Mux holding latch. 178-183 Ao- A5 1 ECL inputs containing the address of the 64:1 Mux holding! controllatcb to be programmed. 177 LOCAL STROBE 1 Active mGH, ECL input used to load the DO-D5 and TRI data into the 64:1 Mux holding latch. 34 GLOBAL STROBE 1 Active HIGH, ECL input used to load destination addresses to all 64:1 S Mux control latches simultaneously from the data contained in their corresponding holding latches. 54-59 SO-S5 1 ECL inputs containing the address of the control latch to be observed at the QD output when the TEST STROBE is mGH. 60 TEST STROBE 1 Active mGH, ECL input used to enable Test Mode and observation of a selected 64:1 Mux control latch's destination address. 206 CIFf 203 = 1 ECL input used to enable Clocked or Flow-through Mode (Clocked mGHIFlow-Thru LOW). CK I ):IrT ~1~1.; 68,71,73,78,80,83,85,88, 92,95,97,100,102,107,109,112, 126,129,131,136,138,141,143, 148, 150, 153, 155,158, 162,165, 167,170,240,243,245,250,252, 255,257,260,264,267,269,272, 274,279,281,284,298,301,303, 308,310,313,315,320,322,325, 327,330,334,337,339,342 Zo- Z63 0 The 64 EeL signal outputs. 296 QD 0 EeL output used to observe the output of a selected 64:1 Mux in Test Mode. 114,117,121,124,286,289,293 QO-Q6 0 EeL outputs containing the selected 64:1 Muxcontrolregister's destination address and TRI bit in Test Mode G52132-0 Rev. 2.0 = = input for Clocked Mode. VlTESSE 1996 Communications Product Data Book Page 511 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch ::.:':::::::::::.::.:':~i~:~'::':::::: ::: •. .•.•. '.•. N!.:.::.I1IM ... :..... '.'. •. •. :... :.:.:. :. :::::::::::::::~~~~~~~~~~~~r~_~~~~~~~~_~~~~~~::::::::: ,.1JQ.: ... :.:.:.:.•. 3,17,32,47,61,76,90,104, 118,132,146,160,175,189,204, 219,233,248,262,276,290,304, 318,332 VCC 2,63,69,74,81,86,93,98, 103, 110, 115, 122, 127, 134, 139,144, lSI, 156, 163, 168, 174,235,241,246,253,258, 265,270,275,282,287,294, 299,306,311,316,323,328, 335,340 VCCA 4,18,33,48,62,77,91,105,119, 133,147,161,176,190,205,220, 234,249,263,277,305,319,333 VTT 291 VSUB I, 19,31,46,64-67,70,72, 75,79,82,84,87,89,94,96, 99,101,106,108,111,113, 116,120,123,125,128,130, 135, 137, 140, 142, 145, 149, 152, 154, 157, 159, 164, 166, 169,171-173, 191,218, 226-232, 236-239, 242, 244, 247,251, 254,256,259,261, 266,268,271,273,278,280, 283,285,288,292,295,297, 300,302,307,309,312,314, 317,321,324,326,329,331, 336,338,341,343,344 N/C Page 512 ~ •...•.•.•.•.•. :............. :::H::H>D.k~t.iP@#: .... ::::::::::::::::::::::;:::' . ::::::::::::.::::::.::::::.:.:::.:::::::::.::::::::::::::::: 0V ground coDllCCtion for intemallogic. 0V 'dirty' ground connection for outputs. -2V supply connection. -2V supply connection to subslrate (most negative supply). No Connection. These pins are not internally connected. VlTESSE Semiconductor Corporation G52132-0 Rev. 2.0 200 Mbls 64 x 64 Crosspoint Switch Data Sheet Table 5: Pin Identification N'oiii,~ PiJ.ii .N~~ .N~~ Niiiii~ Piji# N~ Z6 85 q8 162 Z50 303 Z7 88 q9 Z30 165 Z51 308 167 Z52 Z31 Z32 170 Z53 310 313 240 Z54 315 Z33 Z34 243 245 Z55 N~ 144 41 D2 7 D3 8 Z8 92 ~ 95 Z10 97 Piiiii .j'{ji# r.~# Piji# Ai~ i>bi# 10 12 122 26 11 225 123 211 45 196 12 13 13 124 27 43 42 D4 224 125 210 43 195 D5 9 10 14 126 28 43 43 Ao 183 127 209 43 194 Al 128 29 43 44 A2 182 181 Zl1 16 223 15 Z12 100 102 Z56 320 322 17 222 129 208 43 193 A3 180 Z13 107 Z35 250 Z57 325 18 16 130 30 43 45 ~ Z14 109 Z36 252 Z58 327 ~ 110 221 131 207 43 192 A5 179 178 Z15 112 Z37 255 Z59 330 20 132 35 43 49 So 54 Z16 126 Z38 257 ~01 334 111 217 133 202 43 188 SI 55 Z17 129 Z39 260 Z61 337 112 21 134 36 43 50 S2 56 Z18 131 Z40 264 Z62 339 113 216 135 201 43 187 S3 57 Z19 136 Z41 267 Z63 342 114 22 136 37 43 51 S4 58 qO 138 QO 114 215 137 200 43 186 S5 59 272 Ql 117 116 117 23 138 38 43 52 Zo 68 q1 Z22 141 Z42 Z4'3 269 115 143 Z44 274 Q2 121 214 139 199 q3 148 Z45 124 40 53 73 q4 150 Z46 279 281 Q3 39 ZI q 71 24 43 43 185 118 ~ 286 119 213 41 198 184 ZJ 78 qs 153 Z47 284 Q5 289 120 25 42 40 43 DO 5 ~ 80 q6 155 Z48 298 Q6 293 121 212 43 197 Dl 6 Z5 83 q7 158 ~9 301 4 15 GS2132-0 Rev. 2.0 @ VlTESSE 1996 Communications Product Data Book Page 513 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch Package Information Figure 7: 344 Pin Ceramic LDCC Package Heat Sink Side Package is Cavity Down K ~!'--------:--------'-!------~I i , rr::rr Table 6: 344 Pin Ceramic LDCCToIerance Table *At package body NOTES: 1) Drawing not to scale. 2) Packages: Ceramic (alumina); Heat sinks: Copper-tungsten; Leads: AUoy 42 with gold plating Page 514 @ VlTESSE Semiconductor Corporation G52132-0 Rev. 2.0 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch Expandabi/ity The VSC864A-2 can be expanded to larger crosspoint switches by configuring it so that any input can be multiplexed to any output. The figure below is an example of a 128 x 128 crosspoint switch. The top two VSC864A-2s (1&2) correspond to the first 64 outputs and the bottom two VSC864A-2s (3&4) correspond to the last 64 outputs. The VSC864A-2s on the left (1&3) correspond to the first 64 inputs, and the two VSC864A2s on the right (2&4) correspond to the last inputs. All like outputs are then joined to form a 128 bit Z output bus. The ability of the VSC864A-2 to tri-state its outputs will prevent contention on the Z bus. The TRI input is configured such that when it is active on the left hand chips (which are responsible for routing the first 64 inputs) it is inactive on the two right hand chips (which are responsible for routing the last 64 inputs). The TRI input thus functions as the MSB of a 7-bit channel address word (A-bus plus TRI). Chips can share A-bus information. The destination (D) bus can be shared among the four chips with the local strobe for each device being used to select which output address gets reconfigured. The layout and placement of the VSC864A-2 is such that inputs are on the top and bottom of the chip and outputs are to the right and left. In this way a PC board design for a large crosspoint is facilitated. In the read mode tri-stateability on the Q-bus can be controlled with the TEST STROBE input. A "low" level on this input will tri-state its corresponding Q-bus. In this way the Q-bus from all chips can be wire-OR'ed. Individual TEST STROBE signals to each chip, however, are required. r· . ·'. . Figure 8: 128 X 128 Crosspoint Switch Diagram rind 64 Inputs ZO-Z63 + + 1604·1127 10-163 ~~ AIJ-AS •• ~ VSC864 I 00- VSC864 TAl os ~ 18164 0 ulpuls .. 2n d64 0 ulpuls lJ)- TAl ~f- DO·D5 DO .0£ • AIJ-AS 1 2 ... •• 164-1127 , 10-16 6. L-- t r- ,,-'w ""-AS .... - -tr-" G52132-0 Rev. 2.0 @ ?27 •• VSC864 TAl r- ... . 1 164-1127 ",,- 1Z64ii127 VSC864 "'TAI 00·05 3 ~ 00-05 4 VlTESSE 1996 Communications Product Data Book Page 515 Data Sheet 200 Mb/s 64 x 64 Crosspoint Switch Ordering Information The part number for this product is formed by a combination of the device number and the package style: VSC864A-2xx Device Type: VSC864A-2: 64X64 Crosspoint Switch Package Type F: 344-pinLeaded Chip Carrier (LDCC) Notice Vitesse Semiconductor Corporation reserves the right to make changes in its products, specifications or other information at any time without prior notice. Therefore the reader IS cautioned to confirm that this datasheet is current prior to placing any orders. The company assumes no responsibility for any circuitry described other than circuitry entirely embodied in a Vitesse product. Warning Vitesse Semiconductor Corporation's product are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. Page 516 (Jj) VITESSE Semiconductor Corporation G52132-Q Rev. 2.0 Package Outlines Introduction This section contains outline drawings for all Vitesse Communications product packages. Table 1 lists each product, along with it's corresponding package and page number. Package outlines are also provided in the data sheets located in the telecommunications and datacommunications sections of this data book. Table 1: Vitesse Communications Product Packages H lProtl#.et, : <>Package H>H:p.ac~~:. fl'~~~c.t:· ~11k#~~ . :......... ~,e~ VSC7105 44 pin PQFP 521 VS8022 52pinLDCC 522 VSC7106 44 pin PQFP 521 VSCS023 192TBGA 527 VSC7107 184pinPQFP 526 VSC8024 VSC7115 52 pin PQFP 523 VSC7116 52pinPQFP 523 VSC7117 208pinPQFP 528 VSC7120 52pinPQFP 523 VSC7121 521 VSC7125 44pinPQFP 64pinPQFP,10mm VSC7125 192TBGA 527 52pinLDCC 522 52pinPQFP 523 52pinLDCC 522 52pinPQFP 523 VSC8063 52pinPQFP 523 524 VSCS071 Module 534 64pinPQFP,14mm 524 VSCS072 Module 534 VSC7201A 269pinTBGA 529 VSCSI0l 28PLCC 520 VSC7203 301 pinTBGA 530 VSCSI02 l00pinPQFP 525 VSC780217805, VSC7810 5.6 mm, TO-46 Ball Lens 532,533 VSCSll0 100 pin PQFP 525 525 VS8061 VS8062 VS8004 28pinLDCC 519 VSCS111 l00pinPQFP VS8005 28pinLDCC 519 VSCS112 100 pin PQFP 525 VS8021 52 pin LDCC 522 VSCS64A-2 344 pin LDCC 531 Trim and Form Equipment Faneort Industries otIers a variety of trim and form presses, ranging from smaller, economical, hand operated arbor presses, to more sophisticated trim and form presses for use in volume production and automated systems. Depending on the application, Fancort Industries will be able to recommend the most appropriate solution. Table 2 contains a list of all packages supported with Fancort lead trim and form equipment. For further information, contact Fancort Industries at 2011575-0610. Table 2: Fancort Forming Tools for Vltesse Standard Packages Note: Trim and form equipment may be available for additional Vitesse packages. @ VlTESSE 1996 Communications Product Data Book Page 517 Package Outlines Corfin Industries, Inc., utilizing Fancort Industries equipment, is the approved Vitesse vendor for trimming, forming and tinning. The following are brief descriptions of Corfin's SMT tooling and services for processing your Vitesse quadpacks. The level should be determined by taking into account your production requirements and specifications. Levell Corfin will form your components to specification using your universal systems, and if necessary, supply adjustable matrix trays for shipping the parts to you. Level 2 Fancort's universal tooling is designed for high mix and low production, R&D, training and repair. They process one side of the component at a time, and give you the flexibility to produce almost any footprint on packages up to 2.5" X 2.5" . A larger model is available for packages up to 4" X 4". PINV-F-1BIl-P Flxed Foot PIN V-F-1B/3A-P Adjustable Foot Level 3 Fancort's dedicated tooling with manual standoff control is designed for moderate production, and can be used in our hand or air press. These tools process all sides of the component at one time, and have a built-in micrometer for varying the standoff height. These tools hold the tightest, and most consistent tolerances. PINV-F-1N4 28 pins to 256 pins PIN V-F-IN4L 344 pins PIN 3300 Hand Press PIN 5000-1 Air Press Note: One dedicated die is necessary for each new pin count. Level 4 Fancort's Electronic Floating Anvil tooling is designed for production runs of very expensive parts, and where automatic standoff control is required. These tools will automatically control the finished standoff to within +/-.002" regardless of lead exit point and ceramic thickness. These tools automatically hold the tightest and most consistent tolerances. PIN V-F-1F/4 28 pins to 256 pins PIN V-F-1F/4L 344 pins PIN 5000-1 Special Air Press Note: One dedicated die is necessary for each new pin count. LevelS Corfin utilizes an electronic floating anvil press enabling customers to purchase a Level 4 tool for use in their integrated system. All you purchase is a dedicated Floating Anvil tool PIN F-IF series. Page 518. ~ V"ESSE Semiconductor Corporation Package Outlines Figure 1: 28 Pin Ceramic LDCC Package Dimensions 28·Pin Lstukd Ce1'Q1llic Package (WCC) r--_ _ _---,L....! CrL~~;JJ4 JJ Heat Sink Side l 28'--_ _ _- - ' 1 rlo ~. ~Tr~~~~~ 1 N A B C E I J -II- - I. M -----.~I f NUI'ES: Drawm, not 10 ICIlIL Package: Clramic (alJImi1Ia); Heal.brlc: Copper.Iung.ten; Leatb: Alloy 42 with gold p/alillg. 11.176111.682 1.01611.524 0.440/0.460 0.040/0.060 8.128/8.636 1.143/1.397 0.40610.610 1.829fl.235 0.33TYP 0.050TYP 0.01610.024 .0721.088 8 VlTESSE 1996 Communications Product Data Book K L M N 0 0.10210.203 5.84216.858 0.004/0.008 0.230/0.270 22.860/25.398 0.356/0.559 1.525fl.287 0.900/1.000 0.01410.022 0.075TYP Page 519 Package Outlines Rgure 2: 28 PLCC Package Dimensions (JEDEC Format) A .. B 1 ltenF mch 28 A B 5 25 C D E C D F .045 x 45° CORNER CHAMFER 11 G .490 .454 .454 .490 .010 .420 .152 ...................... ................. ::ToIO ±.OO5 ±.OO2 ±.OO2 ±.OO5 ±.OOO3 ±.01O ±.002 19 O.050±'OO2 .036 R TYP .020 MIN ~ -t 0.023/0.029 x 30' + t N(fJ'E8: Draw."", (1) /fJ . I T HEATSINK INTRUSION NIYI"ES: (1) Drawing. MIlo .cale. (2) 7Wo .tyt.. of expooed MaI.pTlJade" may be wed; 8quare or O1IaL (3) AU uni" in millime~T8 8 VITESSE 1996 Communications Product Data Book Page 525 Package Outlines Figure 8: 184 Pin PQFP Package Dimension :»'1",,;: ::mm: .......................... :::7W~::: A 0 A Al A2 0.25 MAX MIN 3.49 ±.10 D 31.20 ±.25 D1 28.00 ±.10 E El L e 31.20 ±.25 28.00 ±.10 0.88 +.15/-.10 0.50 BASIC b 0.22 ±.05 e 0-7· R Rl .30 4.07 .20 TYP TYP 139 184 e Page 526 b NOTE: Drawing not to scale. e VITESSE Semiconductor Corporation Package Outlines Figure 9: 192 Pin TBGA Package Dimensions (In millimeters) TOP VIEW .- - - -- ---- I I I I DIE CAVITY DIE SIZE .--- --I I -t;r. == ---- I I I I I I I I I I - 1[' r- ~~g ..§.~ ~ I \ I 5.80 BALLAI/ NOTCH 10.24 , BOTTOM VIEW -0- SEATING PLANE 19.06 SIDE VIEW c:!EJ TYP ~TYP 16 15 14 12 13 1011 8 6 9 7 3 OOOOOOOO~OO 000 00000000 0000000 0000000000000000 00000000 0000000 gggg+gggg 0000 0000 0888 o 0000 0000 0000 ~ ~ ~ ~ Q.QQQ 0000 0000 0000 oooo+------~ 00000000~0000000+------* ~ooooooooooooooo 00000000 0000000 00000000000000 R N L J G E C A ' BALL AI TPMKHFDB NOTCH 0.55 NOM 8 VlTESSE 1996 Communications Product Data Book Page 527 Package Outlines Figure 10: 208 Pin PQFP Package Dimensions \---0 ~I 0 2081 157 PIN1- NOTI!.Y: 1) All dime1llJUma in miJlinutm. 2) lJinu""iurLf ,hown are 1IOIPd1lll1 with totera.".. Q8 indicated. A A1 A2 D DO Dl Page 528 4.10 0.25 3.40 MAX MIN to.20 30.60 25.5 28.00 to.10 to.OS REF b 0.22 K 0.50 NOM LG to.16 e 0.60 0_10 0 R .25 R1 .2 NOM NOM @ VITESSE Semiconductor Corporation Package Outlines Figure 11: 269 Pin TBGA Package Dimensions (In millimeters) ~ ..TOP V lEW I I tl! - ---- ----I I I I ~ ~ 1--- ---I I I I I I I :~ \It / DIE SIZE /' DIECAvrrY V -- - -~-- --- I I I I I I I ~ ~ I I I I - ~ BALLA1/ .... NOTCH 11.55, 16.01 -C. SEATING PLANE SIDE VIEW -- BOTIOMVIEW ITill TYP 000000000 000000000 0000000000 000000000 0000 000 0000 000 0000 000 000000 000 0000000000 0000000000 0000000000 0000 0000 0000 8888 0000 0000 0000 0000 0000 0000 0000 0000000000 0000000000 0000000000 NOM @ VlTESSE 1996 Communications Product Data Book Page 529 Package Outlines Figure 12: 301 Pin TBGA Package Dimensions (In millimeters) ropvlEW I]LQQJ ;' ...... .... " , 'I' ----- I II' I I I I I I .., 0 cO --- ---- .. I I I I I I / DIE SIZE ~ --- -- !r -- --- - \11 /' DIECAVrrv ~ I I I I I I :)'1 \11 I I I I I ---I / ~ \11 BALLA! / 7.20 NOTCH " L_ ...... -cSIDE VIEW SEATING PLANE 11.66 " BOTTOM VIEW c:i£J TYP 000000000 000000000 0000000000 000000000 000000 0 0000 0000 0000 0000 0000 000000 000 0000000000 0000000000 0000000000 o 000000 00000 00000 88888 00000 00000 0000 00000 00000 0000 00000 0000 00000 0000 00000 00000 0 000000000 0080888888 0000000000 0000000000 000000000 0000000000 O. 5 Page 530 8 VrrESSE Semiconductor Corporation Package Outlines Figure 13: 344 Pin Ceramic LDCC Package Dimensions Heat Sink Side Package is Cavity Down K , ________ AB------------------~II t"~ "\, __ , o E, P.,. A 58.93/59.44 2.320/2.340 B 34.54TYP 1.36TYP C" 0.51 TYP 0.020TYP D 0.38/0.63 0.015/0.025 H 1* J* K E 2.16/2.92 0.085/0.115 F 0.09/0.216 0.0004/0.008 G 5.08n.62 0.200/0.300 f 0.15/0.25 0.00610.010 REF2.54TYP REF 0.100 TYP 32.00TYP 1.26TYP 39.46TYP 1.08TYP L 36.57/37.59 1.440/1.480 M* 54.36TYP 2.14OTYP *At package body NOTES: 1) Drawing not to scale. 2) Packages: Ceramic (alumina); Heat sinks: Copper-tungsten; Leads: Alloy 42 with gold plating ® V1TESSE 1996 Communications Product Data Book Page 531 Package Outlines Figure 14: Mechanical Package SpecHlcaUons (5.6 mm Package) DO .. .6 E lI) .. 0 ~ .. d d lI) ~ .... on i SECTlONB-B SCALE NONE 0.65:1:0.04 DETECTOR PLANE B~ SECTION A-A ROTATED CCW 90° SCALE NONE (4XJ 6.5 .os 3.3.0." REFERENCE ISOMETRIC SCALE NONE Page 532 Note: All measurements in mm ~ VITESSE Semiconductor Corporation Package Outlines Figure 15: Mechanical Package SpecHlcatlons (T0-46 Ball Lens Package) 2.54 4.7 +0.03100.1/-- ( .31.0.075 \'" --. L......-:;-:;-::~..../ L->- - I -*.---':=====~~:==~~- 7.00~O.5 ~ IlElEClon PWE ~ VlTESSE 1996 Communications Product Data Book Page 533 Package Outlines Figure 16: VSC807118072 Module Heat Sink Side 1------1---- 1.800 -------i 1.000 ----I 0.330 RFI 0 + RF2 RF3 0 RF4 0.330 Pinl Module Side View 0.380 0.189 Page 534 @ VITESSE Semiconductor Corporation Product Summary . . ~4I!t.l7##tr(y· . . ·............... ·......... p~i#riR~ ........... · . · . . ·. . 1.· •• ·..•• ·••. •.. ·",.;m;i~~. GIX Family Manufactured using latest generation H-GaAs N technology to achieve lowest powee solution. Ideal for cost sensitive applications in communications, A1BIinstrumentatian, and computers. Masterslice architecture acccunmodates embedded megacells. • 25,000-250,000 Gates (raw) • Sea-of-GatesArchilecture • Embedded SRAM, Register Files, PlL and Verniers • BeL, PEeL, 'I'TI., GIL, and HSIL Sigual Levels • 0.511 H-GaAs N MBSFBI' Process • Can Operate from Single 3.3V Power Supply • Full Speed and Half Power Macrocells • Power Managemenl Slashes Power in Low Frequency Blocks • 2-Jnput NOR Delay ('IYpical): '31 ps (Unloaded) @ 0.1 mW of Power FXFamily Highest integration and performance capable of 800 MHz in a sea of gates architecture. Ideal for applications requiring very high speed, low power digital logic al high levels of integration. Masterslice architecture makes FX ideal for applicatiaIB requiring embedded megacells. • 20,000-350,000 Gates (raw) • Sea-of-Gates Archilecture • Embedded SRAM, Register Files, PlL and Verniers • BCI.., PBCI.., and TIL • MIL-STD-883 Screening Available ·0.611 H-GaAs mMBSFBI' Frocess • 2-Jnput NOR Delay ('IYpical): 37 ps (Unloaded)@0.2mWofPower Viper Family Low cosl performance arrays. Ideal fa: 75 MHz to 700 MHz commercisl applications. ·7,000-20,000 Usable Gales • Sea-of-Gates Archilecture • Industty Siandard Plastic Packaging • BCI.., PBCI.., and TIL Signal Levels • 2-Jnput NOR Delay ('IYpical): 44 ps (Unloaded) @ 0.2 mW of Powee SCFXFamily High performance SCFIJDCFL combination arrays optimized for high speed designs up 10 3.0 GHz. Ideal for semi-costom telecommunications and data communications applications. Fury Family* Balanced speed and powee for performance rettee than BCL solutions at a fraction of tbc power. Ideal for low powee, perfa:mance logic applications. Highest YO to gale ratio. ·5,000-18,500 Usable Gales • Sea-of-Gates Archilcctw'e • Embedded SRAM, Register Files and PlLs • BCI.., PECI.., 'I'TI., CML. and LVDS • 0.6JL H-GaAs mMBSFBI'Process • DCFL 2-Jnput NOR Delay ('Iypical): 37 po Fury Family* *Not Recommended/or New Designs ~ VlTESSE 1996 Communications Product Data Book Page 535 Product Summary Page 536 ® VITESSE Semiconductor Corporation GLX, F)(, VIPER, SCFX, FURY Gate Arrays Application Specific Integrated Circuits Vitesse ASIC Design Kit Vitesse ASIC designs are supported on Mentor, Synopsys, Cadence, and Viewlogic platforms. Cadence includes support for Concept and Composer Schematic Capture. LASAR is the SunIHP-based "Golden Simulator" supplied with every Vitesse design kit to verify the functional and AC performance of the design by accounting for on-chip timing variations. Macrocelllibraries for the MOTIVErM timing verifier from Quad Design are also available. The Vitesse Design Kit allows a designer to perform schematic capture, functional simulation, front-annotated timing simulation, electrical rule checks, and back-annotated simulation after place and route. To facilitate ftoorplanning and block pre-placement, Vitesse has developed an interactive graphical pre-placement tool, VSCDP, that runs in the X Windows™ environment. Cadence place and route tools are used for physical implementation at Vitesse. CAElEDA Tools Vendor Tool Function Mentor Design Architect QuicksimII Schematic Capture Gate Level Simulation Cadence Composer Concept Verilog-XL Gate Ensemble Schematic Capture Schematic Capture Gate Level & Behavioral Simulation Place & Route ViewLogic ViewDraw ViewSim ViewTIme (Motive) Schematic Capture Gate Level Simulation TIming Verification Synopsys Design Compiler Logic Synthesis Teradyne LASAR Gate Level and Fault Grading Simulation QUAD Design Motive Static TIming Verification 8 VlTESSE 1996 Communications Product Data Book Page 537 Application Specific Integrated eifCL/its GLX, FX, VIPER, SCFX, FURY Gate Arrays Because our customers have varying needs and different levels of gate array design experience, Vitesse offers several implementation options. These options range from a completely customer designed chip to a tum-key implementation based on mutually agreed upon specifications. In all cases, Vitesse implementation engineers are assigned to answer questions and track the progress of the design from start to finish. In addition, the following steps are normally performed by Vitesse engineers for all designs: • Placement and routing of the design • Net-length extraction • Fan-out and metal delay calculation • Final design rule checking and layout versus schematic verification Through experience with many gate array designs, Vitesse has created a design automation framework and a well-defined flow for smooth implementation of customer designs. The flowchart at left summarizes the typical gate array project flow and breaks down the tasks as they are typically delegated to the customer or to Vitesse. ASIC Design Training Course Design classes are provided to help the customer understand the design methodology and tools utilized in the gate array design process. These classes ,are recommended for all customers planning to implement a design in a Vitesse gate array. Training can be provided at the Vitesse facility or at the customer's site. This introduction to semicustom digital high performance VLSI design prepares designers to implement circuits using high speed enhancement/depletion mode gallium arsenide technology. The intensive three-day course covers all phases of gate array design, including the design methodologies and tools specific to the design ofVLSI semicustom GaAs les. After completing the course, the attendee will be able to design high performance circuits with minimum consultation. In addition, a complete overview of related topics which impact circuit design, including wafer fabrication, test, assembly, and packaging will be presented. Schedule of Course Dates: • Monday - Wednesday, August 12-14,1996 • Monday - Wednesday, November 4-6, 1996 • Monday - Wednesday, FebrUary 3-5, 1997 • Monday - Wednesday, May 5-7,1997 • Monday - Wednesday, August 4-6, 1997 • Monday - Wednesday, November 3-5, 1997 Page 538 ® VrrESSE Semiconductor Corporation GLX, FX, VIPER, SCFX, FURY Gate Arrays Application Specific Integrated Circuits Implementing VitesseGate Arrays Figure 1: Gate Array Project Flow VITESSE , , 80TH CUSTOMER (26) ORe & lVS ..... (27)PG TAPE ., ......... ( (28) MASK MAKING J.: 1:.. ~~:;:.:;.:;:;..,..,!) , 1;;'2.1 FINALTEST ......... ......... . (33) SHIP @ ): ~.;-:_ _ _"\ VlTESSE 1996 Communications Product Data Book Page 539 Application Specific GLX, FX, VIPER, SCFX, FURY Gate Arrays Integrated Circuits Page 540 ~ VITESSE Semiconductor Corporation VITESSE GLX, FX, SCFX Masterslice Arrays Application Specific Integrated Circuits Features • Combines the Power of Megacells with the FX, SCFX or GLX Macrocell Library • 20,000-350,000 Raw Gates, Channeless Architecture • Sea-of-Gates Architecture and Four Layer Metal for High Density • Embedded Megacells Including:RAM, Register Files, Verniers, Counters, and PLLs • Data Sheets Available for all Megacells • RAM Compiler to Create Optimized RAM • EeL, PECL, and TTL Signal Levels • Optional Fixed Clock Distribution Scheme to Minimize Clock Skew • Commercial & Industrial Temperature Ranges Description FX, SCFX, and GLX gate arrays are available in Masterslice format with embedded full-custom megacells. Masterslice arrays combine the power of megacells with the flexibility of the FX, SCFX or GLX macrocell library. Depending upon the size of the megacell and the product, Masterslice arrays may incorporate in excess of 300,000 raw gates. As with all standard arrays, these products combine> 1 GHz performance with integration levels comparable to BiCMOS gate arrays. The masterslice approach provides simple integration of custom megafunclions onto the array, allowing the user to solve application specific requirements that cannot be effectively implemented in the sea-of-gates logic. Typical megacells include RAM, register file, and custom data path blocks. In addition, Vitesse has developed megacells specifically designed to solve difficult timing problems in applications such as telecommunication, data communication, and ATFJinstrumentation. These cells include PLLs, timing verniers, and very highspeed counters. Masterslice Array @ VlTESSE 1996 Communications Product Data Book Page 541 Page 542 8 VITESSE Semiconductor Corporation VITESSE GLX Family Gate Arrays Application Specific Integrated Circuits Features • Five Array Sizes: 15K,40K, 80K, 120K and 220K Raw Gates • Standard TTL, LVTI'L, ECL, LVPECL, GTL, HSTL and LVDS I/O Compatibility • Low-Power H-GaAs IV, 0.4fl, 4-Layer Metal, Technology • Compatible With Standard TIL or ECL System Power Supplies • Operates from either a single +3.3V Power Supply or Reduced Supply Voltages to Conserve Power • Superior SpeedlPower Performance: • - Typical gate delay: 130 ps @110J,l.W (unbujfered 2-in NOR, F.O. = 2,0.13 mm wire) - Typical gate delay: 140 ps @ 330J,l.W bujfered2-inNOR, F.O. = 2,0.S mm wire) • Industry Standard Plastic Molded Packages • Low-Power Macros Available Description The GLX series is a family of high performance, low power gate arrays based on the fourth generation, 0.4J.L, 4layer metal, HGaAs-IV process. GLX utilizes a sea-of-gates architecture and can be powered from 2.0V or 3.3V power supplies. The family consists of five members ranging from 15,000 raw gates to 220,000 raw gates with a utilization factor of up to 70%. GLX delivers both the lowest power per gate and the lowest price per gate of any high performance ASIC product family. All GLX macrocells are available in either full speed (110J,l.W per gate) or half power (65J,1.W per gate) versions. Power diSsipation is independent of operating frequency. By combining the cost benefits of a high yielding process, reduced die sizes, and low cost thermally enhanced plastic packaging, GLX provides a low cost solution for applications requiring performance beyond the capabilities of CMOS. Array Specific Features Array Name # of Internal Gates Us.ble Gal•• D Flip-Flops #of Input Cells #of VO Cells Total Signal Pins Package OptIons GLX15K 10K loOK 35 52 87 128 PQFP GLX40K 26K 2.6K 35 76 111 180 PQFP GLXBOK 48K 4.8K 31 104 135 208 PQFP GLX120K 72K 7.2K 31 120 151 240 PQFP GLX220K 110K 11.0K 31 156 187 XXXBGA @ VITESSE 1996 Communications Product Data Book Page 543 Page 544 (8 VlTESSE Semiconductor Corporation VITESSE FX Family Gate Arrays Application Specific Integrated Circuits Features • 10,000-350,000 Raw Gates, Channeless Architecture • MIL-S'ID-883 Screening Available • Commercial, Industrial, Extended and Military Temperature Ranges • Sea-of-Gates Architecture and Four Layer Metal for High Density • ECL, PECL, and TIL Signal • 0.6j.L H-GaAs III MESFET Process • Array Performance - Typical gate delay: 97 ps @ 0.19 mW (unbuffered 2-in NOR, F.O. = 1, 0.17 mm wire) - Typical gate delay: 95 ps @ 0.59 mW (buffered 2-in NOR, F. 3, 0.51 mm wire) • Multiple Buffering Options for Optimal SpeedPower Solution • Optional Fixed Clock Distribution Scheme to Minimize Clock Skew o. = Description The FX family consists of 8 products ranging from 10,000 to 350,000 raw gates. These arrays combine> 1 GHz performance with integration levels comparable to BiCMOS gate arrays. The FX family is manufactured in the production proven H-GaAs III process, and incorpomtes a channeless architecture allowing the first layer of metal to be routed over unused cells. This architecture eliminates the need for pre-defined channels, allowing much greater density and flexibility in design, resulting in superior performance. Because power dissipation is frequency-independent in H-GaAs technology, FX arrays have power dissipation levels comparable to or lower than similar density BiCMOS arrays at frequencies above 50 MHz. Custom masterslices are also available to incorporate functions such as SRAMs and multiport register files into FX arrays. FX arrays are ideal for mainframe computers, workstations, communications equipment and other systems requiring very high speed, low power digital logic at high levels of integration. Array Specific Features II of Internal Gates Array Name VGFX10K VGFX20K VGFX40K VGFX100K G51017_a Rev '91 Total Raw U•• bl. G.t•• D Ffip.Flop. 10K 7K 790 G.t •• 20K 10K II of Input Cells II of 110 Cells Total Signal Pins Package options 7 24 31 52POFP 31 40 71 100PQFP 13 24 37 52LDCC 132 PGA, 132 LOCC, 144PQFP 1K 39 52 91 42K 21K 2.1K 40 99 139 195PGA 3SK 19K 1.9K 36 99 135 208PQFP lOOK 50K 5K 73 100 173 211 PGA 91 100 191 256 LOCC VGFXI50K 188K 75K 8K 99 156 255 344LDCC VGFX200K 220K 110K 11K 83 172 255 415PPGA VGFX350K 350K 17SK 17.SK 107 218 325 557PPGA r-'GFX350KE 350K 175K 17.5K 127 250 377 557PPGA ® V"ESSE 1996 Communications Product Data Book Page 545 Page 546 e VlTESSE Semiconductor Corporation VITESSE VIPER Family Gate Arrays Application Specific Integrated Circuits Features • 7,000-13,000 Usable Gates, Channeless Array Architecture • Array Performance - 'IYpical gate delay: 118 ps @ 0.19 mW (unbuffered 2-in NOR, RO.= 1, 0.17 mm wire) - 'IYpical gate delay: 116 ps @ 0.59 mW (buffered 2-in NOR, RO.= 3, 0.51 mm wire) • Industry Standard Plastic Packaging • Superior Speed/Power Performance and Cost Comparable to BiCMOS • Robust Clock Distribution Scheme for Minimized Clock Skew • Production-Proven H-GaAs III Enhancement! Depletion MESFET Process • Multiple Buffering Options for Optimal Speed! Power Solution • ECL, PEeL, TIL, or Mixed Inputs/Outputs Description The VIPER family of gate arrays provides the best cost-per-function solution for system applications between 50 and 700 MHz. By combining the high performance of H-GaAs technology with the low cost of molded-plastic packages, VIPER delivers two to three times the performance of BiCMOS at comparable cost. This allows the designer to implement much simpler architectures to achieve performance targets. As with all Vitesse ASIC products, VIPER arrays are compatible with industry-standard TTL, EeL, and pseudo-ECL (PECL) signal levels, and utilize standard power supplies. The VIPER family is manufactured in the production proven H-GaAs III process, and incorporates a channeless architecture allowing the first layer of metal to be routed over unused cells. This architecture eliminates the need for pre-defined channels, allowing much greater density and flexibility in design, resulting in superior performance. VIPER arrays are ideal for applications at 50 MHz or higher. The performance advantage of VIPER over BiCMOS enables system designers to consider simpler architectural alternatives, such as serializing data streams and eliminating pipeline stages. Array Specific Features #of 110 Cells Total Signal Pins Package Options Usable Gates DFII~F/Ops #of Input Cells 7K 700 7 24 31 52 PQFP (1) 7K 700 31 40 71 100 PQFP (2) VGLC12K 10K 1K 39 52 91 144 PQFP (3) VGLC15K 13K 1.3K 36 99 135 208 PQFP (3) Array Name VGLC10K # of Internal Gates (1) EIA) footpring, 14 x 14 mm body size, thermally enhanced package. (2) EIA) footprint, 14 x 20 mm body size, thermally enhanced package. (3) EIA) footprint, 28 x 28 mm body size, thermally enhanced package. G52057_a Rev '92 ® VITESSE 1996 Communications Product Data Book Page 547 Page 548 8 VlTESSE Semiconductor Corporation G52057_a Rev '92 VITESSE SCFX Family Gate Arrays Application Specific Integrated Circuits Features • Tailored Specifically for High Perfonnance Telecommunications and Data Communications Applications. 2.5 GHz Perfonnance. • Phase-Locked Loop Megacells Available: - 155/622 MHz SONET STS-3/STS-12 - 1.0625 GHz Full Speed Fibre Channel • Ideal for SerializationlDeserialization • DCFL 2-Input NOR Delay (Typical): 37 ps (Unloaded) @ 0.2 mW of Power • 5,000-18,500 Usable Gates • DCFL D Flip Flop Toggle Rate: >1.6 GHz • Combination of High Speed SCFL and Low Power DCFL Cells • SCFL D Flip Flop Toggle Rate: >5.0 GHz • TTL, ECL, PECL, VECL, CML, SCFL, and LVDS Signal Levels • FlexibleAllocation of SCFL Resources • Embedded SRAM, Register Files and PLLs • Low Cost Industry Standard Plastic Molded Packages and TBGAs • 0.6J.l. H-GaAs IIIMESFET Process Description The SCFX family of gate arrays provides solutions for high speed designs ranging from 50 MHz to 2.5 GHz. SCFX arrays offer a unique capability by combining very high speed SCFL logic with low power DCFL logic, for an optimum speed-power solution. SCFX arrays are compatible with industry-standard TTL, ECL, and pseudo-ECL (PECL) signal levels, and utilize standard power supplies. SCFX arrays are available as masterslice arrays with embedded megacells such as RAMs, Register Files, and Phase-Locked-Loops, making SCFX ideally suited to telecommunications, data communications, signal processing, instrumentation, and clocking applications. Array Specific Features #OfSfgnals # Of Internal Gates Array Name SCFX10K SCFX40K G51085_a Rev 1.0 Total Usable SCFL 1# 01 Input II of VO SIgnal in Cent.r per quadrant PER quadl'/Jnt C.tt. C.tt. PIns Raw DCFL Usable DCFL 2600 876 2286 15748 @ Package Options 3 24 27 52 PQFP 27 40 67 100 PQFP 35 80 115 184PQFP 192TBGA 34 99 VITESSE 1996 Communications Product Data Book Page 549 Page 550 <8l VlTESSE Semiconductor Corporation G51085_a Rev 1.0 VITESSE FURY Family Gate Arrays Application Specific Integrated Circuits Features • Array Performance - D Flip-Hop Toggle Rates: >1 GHz ,::: -lYpical Gate Delay: 144 Ps @ 1.1 (2-input NOR, RO. = 3, 1.5 mm:~ifiX\:: - EeL Inputs/Outputs at 650 ~1::\":': - TTL Inputs/Outputs at lOQ~)' • Up To 30, 500 Equivalent Gates, Channeled Architecture I!IW\:::' • MIL-STD-883C, Level B Screening and Qualification Available • ECL and TTL Signal Levels • Commercial, Industrial, and Military Temperature Ranges "':"'" ::;:;.;:::':::; • Multiple Buffering a6~~~I~;Macroce11s " ;::" Description:':: 49.~,j~b6 The FURY family of gate arrays consists of five products ranging to 30,500 equivalent gates. These ASICs are ideally suited for systems which require high denii,~tY;,:~#ite..of-the-art performance while maintaining low power dissipation. These arrays interface with TTL, ari:ii:;ECL technologies without additional system requirements. The FURY family offers speed performan<;~:~ to or better than leading edge EeL gate arrays, while dissipating only 1/3 to 114 of the power. This Cal,,=~:;#pto substantial cost savings in overall cooling requirements. ", ,'"":::'::,"'" The FURY family of gate arrays can be used in su~"a:pp..lications as computers, communications, test, and general instrumentation. This family of high perf9r¢.~~Er~emi-custom products is ideally suited for systems requiring very high speed, low power digitallogi~lt:~h levels of integration. Array Specific Features::::>. # of Intema/d~iJ;:::' ECL Hi-Drive #of Output Only Cells 290 40 4 52 92 52 LOCC, 132LDCC, 132 PGA 6.4K 520 52 4 68 120 149 PGA, 164 LOCC 13.4K 1.lK 74 8 100 174 211 PGA 96 8 100 196 256 LOCC 74 8 100 174 211 PGA 96 8 100 196 256 LOCC 100 8 156 256 344LOCC ":;::" "::::' Array Name TTL, 13.4K VSC15K VSC30K G51013_a Rev '89 # of Input Cells 16.9K 30.5K 16.9K 30.5K 1.4K 2.5K Total Signal Pins 8 VITESSE 1996 Communications Product Data Book Package Options Page 551 Page 552 <1& VlTESSE Semiconductor Corporation G51013_a Rev '89 VITESSE Application Note 1 Printed Circuit Board Considerations Introduction Several important considerations must be taken into account when high speed GaAs (or ECL) ICs are interconnected on printed circuit boards. Chief among them is the need to properly terminate signal trace interconnections and the maintenance of low impedance ground and power supply connections. This application note reviews some of the popular design techniques which are utilized to insure the integrity of high frequency signals on a printed circuit board. While these techniques have been used in ECL systems for some time, they may not be familiar to designers accustomed to CMOS circnits. In general, signal traces on circuit boards should be treated as transmission lines if the propagation delay of the trace is more than one-tenth of the rise time of the signal. In the event that the propagation delay of the trace is short with respect to the rise time of the Signal, any reftections caused by unterminated transmission lines are masked during the relatively slow transition and are not seen as overshoot or ringing. Because most CMOS circnits have a high ratio of signal rise time to trace propagation delay, several inches of unterminated signal trace can be used without signal distortion. Since edge speeds in GaAs components are faster, the trace lengths must be considered as transmission lines and must be terminated properly to retain signal integrity. Figure 1: 200 MHz Signal 5 ns Why Are Properly Terminated Transmission Lines Needed? Rapidly changing signals require fast edge rates. A 200 MHz 50% duty cycle clock signal, for example, has a total period of 5ns. This period must accommodate a rise time, a fall time and some pulse width duration. As seen in Figure 1, this signal can result in rise and fall times of approximately Ins because of the desire to maintain the pulse signal integrity. Since GaAs circuits are designed to support signal rates beyond 200 MHz, both ECL compatible and'native' GaAs compatible output drivers are designed for sub-nanosecond rise and fall times. Such fast rise and fall time signals require that board Signal traces are terminated transmission lines. Anytime that the propagation delay of a signal trace is longer than one-tenth the rise or fall time of the signal, an unterminated trace will result in voltage reftections which can cause degradations in the signal integrity. Figure 2 shows the difference in signals observed in terminated and unterminated environments. As seen, unterminated signal lines can result in substantial overshoot and ringing which are caused by voltage reftections. ® VlTESSE 1996 Communications Product Data Book Page 553 Application Note 1 Printed Circuit Board Considerations These voltage reflections can cause a ringing signal which can be interpreted as several faster signals by the receiver. Terminated transmission lines eliminate voltage reflections and therefore produce clean waveforms. Generally, signals with sub-nanosecond rise and fall times must be terminated if the signal trace length is longer than 0.5 in. This is because the propagation velocity of a typical signal trace is approximately 2nslft. Figure 2: Signals at Terminated and Unterminated Signal Traces Terminated Unterminated Transmission Line Theory Transmission line theory is important to an understanding of the methods used to terminate GaAs signal lines. Figure 3 shows a signal trace with typical loads at both ends. Usually, the signal trace delay is long when compared with the signal rise or fall time and reflections will appear at their full amplitude. The output voltage swing at point A, (VA), is given by: VA= (V"') [R::ZoJ where Vint is the internal voltage swing, Ro is the chip output impedance and Zo is the line impedance. Since Ro is small compared to the line impedance. the output swing is nearly the same as the internal transition. The internal Swing is approximately 1.4 V and the typical output swing is 1.3 V. The signal propagates down the line and is seen at point B some time. Tpd ,later. The voltage reflection coefficient at the load end of the line, re, is a function of the line characteristic impedance and the load impedance and is given by: where RLis the termination load resistance and Zo is the line impedance (both in ohms). IfRL = Zoo there is no reflection. For any value ofRL close to Zoo the reflection is small. Page 554 ® VlTESSE Semiconductor Corporation Application Note 1 Printed Circuit Board Considerations Figure 3: Parallel Terminated Line Model Tpd ------1.~1 B ......- - -2 V Practical Transmission Lines The key to maintaining signal integrity in practical high frequency digital systems is the utilization of properly terminated, controlled impedance transmission lines. Controlled impedance transmission lines can be realized in several ways. For signal transmission over long distances, coaxial cables or twisted pairs are popular. Some common types of coaxial cable have characteristic impedances of 50, 75, 93 or 125 ohms. 1\visted pairs can be made from AWG 24-28 hook-up wire twisted about 30 turns per foot. Such twisted pairs have a characteristic impedance of about 110 ohms. For signal transmission within a circuit board, Striplines and Microstrip lines are usually used. A Microstrip line is shown in Figure 4. It is constructed with a strip conductor for the signal line separated from a ground plane by a dielectric. The signal line is made by etching away the unwanted copper using photoresist techniques. If the thickness, width of the line, and the distance from the ground plane are controlled, the line will exhibit a predictable characteristic impedance that can be controlled to within 5%. The characteristic impedance, Zo, of a Microstrip Line can be approximated by: z 0- 87 Je r+1.41 In[ 5.98h ] O.8w+t] where er is the relative dielectric constant of the board material (which is typically 5 for FR-4 fiber-glass epoxy boards), and w, h and t are the dimensions indicated in Figure 4 in inches. Figure 4: Mlcrostrip t T h Dielectric ® VITESSE 1996 Communications Product Data Book Page 555 Application Note 1 Printed Circuit Board Considerations Figure 5: Stripline The propagation delay of the line may be approximated by: Tpd= 1.017 J0.475 e,+ 0.S7 nslft Note that the propagation delay of the line is dependent only on the dielectric constant and is not a function of line width or spacing. For FR-4 fiber-glass epoxy boards, the propagation delay of the Microstrip line is approximately 1.8 ns/ft. A Stripline is shown in Figure 5. It corisists of a copper ribbon centered in a dielectric medium between two conducting planes. If the thickness and width of the line, the dielectric constant medium, and the distance between the ground planes are all controlled, the line will exhibit a characteristic impedance that can be held constant within 5%. The characteristic impedance of a Strip Line is given by: Zo= SO In[ ,j8, 4b ] 0.S71tw (0.8 + tlw) where er is the relative dielectric constant of the medium and b, t, and ware the dimensions shown in Figure 3. This equation proves accurate for: w (b _ t) < 0.35 and t b < 0.25 and the propagation delay of the line is: tpd= 1.017 ,j8,nslft For FR-4 fiber-glass epoxy, the propagation delay of the Stripline is about 2.27 ns/ft. Note that in both Striplines and Microstrip, the propagation delay is not a function of the width or spacing. Page 556 @VITESSE Semiconductor Corporation Application Note 1 Printed Circuit Board Considerations Parallel Terminated Lines Parallel terminated lines such as the one shown in Figure 3 are used for fastest circuit performance. Standard output drivers on Vitesse's GaAs products can drive 50 ohm lines. ASIC products also allow for up to 25 ohm drive capability. In each case the term "line" refers to a signal transmission line, terminated at the receiving end through a resistor of the characteristic line impedance to -2 Volts. With parallel terminated lines, the line termination supplies the output pull-down current for the open source-follower output PET. Thus, no other pull-down resistor is required at the output of the driving gate. Power Distribution Power distribution is an important factor in system design. The loss of noise margin dueto reduced power supply voltage or noise on the power supply lines means a reduction in the circuit tolerance to crosstalk and ringing. Points to consider for overall system operation include total circuit and termination power, voltage drops on the power busses, and noise induced on the power distribution lines by the circuits and by external sources. Vitesse GaAs circuits are designed to interface with each other over a power supply voltage range of ± 5% from the nominal-2 Volts without a loss of noise margin. However, if two chips are at different supply voltages or on the same power supply with a voltage offset between them, there will be a predictable loss of noise margin. The main causes of V IT power supply offsets between circuits are: • Inadequate power busses to handle the necessary current • Separate supplies with common positive terminals at slightly different potentials • Separate positive grounded supplies with an inadequate number of interconnection ground bus bars Power supply requirements for Vitesse GaAs circuits must take into account the fact that a 50 ohm ECL compatible output sources about 22 rnA in a logic mGH state and no current in a logic LOW state. The 22 rnA differential between the two states can produce a Significant power supply current fluctuation. Such an effect should be considered when specifying the power supply. Current fluctuations are by no means insurmountable. Brief current changes are smoothed by bypass capacitors at the power supplies. Also, the typical 50% distribution of output logic levels (e.g., mGH and LOW states) tends to minimize current changes. High frequency noise and ripple from the power supply should be avoided. These effects produce differences in voltage levels among sections of a system and lead to loss of noise margin. As a rule of thumb, noise can be considered "high frequency" whenever the mean wave length of the noise (in units of time) is not more than 2 times greater than the propagation delay of the longest power line. For implementations which use GaAs ICs, it is recommended that high frequency power supply noise be held to under 25 mV of total signal variation. When multiple power supplies are used, the positive terminals should be connected together with a large bus and the output voltages maintained as equal as possible. It is desirable to keep the power supply levels within 25 mV of one another. To achieve the requirements imposed by GaAs circuits on power supply distribution, printed circuit boards with large ground and power planes are commonly used. Power supply bypass capacitors are used on the circuit boards to handle the current transients required by the outputs. eviCe ... ·......................................... ptiVing ifCJj pe,vjCe···.············· i?¢JjJ()()l( ...... Hi?¢i:i~rql ......... LOW l00mV HOmV 105mV 90mV i?¢Jj~()(),K: ......i?¢i:!~ 145mV 145mV 150mV 140mV Table 3: ECl Noise Margins Using a Full External Reference :: ~:::::::: ~::::: ;; ~ ~: ~: ~:::::;:;;; ~ ~ (~~¢iLp.~~~~~~p.r~V~~g ~: ~ [ ~ [ [ ~ [ [ [~[ [ [ [ [ [ [ [ [ [ [ [ [ [ [ [Y#~~~~[P~~f~~[ [ ~ [ [ [ [ [ [ [ [ [ i~ ~: •••.•••••.••••.••••••••.. .................. .••••..•••..••.•••• ••••••••.... • • ·••• T 1 w.~~.i'~m,,~~ HIGH LOW 140mV 145mV pfii1ii~<8pt, p~~#~ 145mV 125mV 145mV 145mV 150mV 140mV Notes: (l )Worst case noise margins over nominal conditions. (2)Source/or ECL lOOK DC Characteristics: Fairchild FlOOK DC Family Specifications. (3)Source/or ECL 10KH DC Characteristics: Motorola MECLIOKH DC Family Specifications. 3. Full External Reference The user may provide an external reference voltage of -1.32V ± 25 mV to the external reference pin. (See table 3 for noise margins.) AN-8 discusses the creation of an external reference using the LM185. Different but equally important issues arise when interfacing Vitesse components' output (or any "non-bipolar" EeL output) with a silicon bi-polar EeL circuit input. Figures 3 & 4 illustrate this situation. In Figure 3, an EeL input is the base of an NPN bipolar transistor whose collector is connected to vee (0 Volts). In order not to degrade the switching characteristics of this input, it is essential that this input transistor be kept out of saturation, which means that the base collector diode must not become forward biased. This condition is assured when driving this input with a bipolar EeL output, since the emitter follower output cannot go more positive than one diode drop below vee. The situation is different when the output emitter follower is replaced with a FET such as in Figure 4. Vitesse's EeL output driver incorporates clamp circuitry to ensure that the output high level does not go more positive than -700mV. One major difference between Vitesse EeL compatible outputs and silicon EeL outputs is that Vitesse outputs are "cutoff' drivers which have an output low voltage equal to the VTT supply. In this way, a logic low is also a high impedance state and several outputs can be bussed together. @ VlTESSE 1996 Communications Product Data Book Page 561 Application Note 2 Interfacing GaAs Products to ECUITL I/O Figure 3: Bipolar Eel Outputs Driving an Eel Input Vcc=OV Vcc=OV VTT = -2.0 Figure 4: GaAs Eel Outputs Driving an Eel Input Vcc=OV Vcc=OV Vrr =-2.0V Page 562 ® VlTESSE Semiconductor Corporation Application Note 2 Interfacing GaAs Products to ECLffTL 110 TTL lID VitesseASICs support TTL inputs and outputs in addition to ECL I/O. The standard minimum input swing specification at a TTL input is ;?:1.2 V (0.8 - 2.0 V) compared to 310 mV for ECL. Figure 5 shows the guaranteed worst case TTL I/O levels in Vitesse components. The TTL inputs source a worst case current of -500 IJA. Figure 5: Worst Case TTL 1/0 Levels for Vltesse Products ±_.O_v______v~-Im =~.ov Voo +5.0 000 =av =a0 +5.0 NMH • = 400 mV f f \'IL NML =300mV TTL compatible outputs impose certain constraints on the user. Figure 6 is a schematic representation of the TTL output buffer with tri-state capability. Figure 6: TIL Output Buffer Schematic Vm =+5.0V OE IN @ VlTESSE 1996 Communications Product Data Book Page 563 Application Note 2 Interfacing GaAs Products to ECUTTLVO One difference between the Vitesse 'IT!.. totem-pole output and typical silicon TTL is that the high level (VOH) typically goes higher in the Vitesse output. The high level can be one diode drop below V'ITL (+5.0 V), whereas in standard 'IT!.., the output generally does not exceed 3.8 Volts. The low level (VOL) is similar to standard'IT!.. (:2: 0.4 Volts) with the rated sinking current (8 rnA). The TTL output tri-state current voltage characteristics are also different from typical silicon bipolar devices. Ftgure 7 shows the 'IT!.. output tri-state I-V curve. Note that the tri-state leakage current, IOZ, shows a sharp increase near 3.5 Volts. This voltage is low, but well beyond the 'IT!.. valid high level of 2.4 Volts. Figure 7: TTL Output Tri-State I-V Curve +2~------------~--------~--------~~--------~-,~, ·---r·. . . .r-·l. . . . · : +1 - 1 ~ : !!: 0 _ .. ·............ o t· ..·......·..·..·t....·····..·....t...··..·..·......!·....·..........· !!!! ::::: ....... ~ -1 - ~ ~ ~ ·f. . ·. . ·. . ·. t. . . . . ·. ·. l. . · ·. . ·. . I. ·. ·. · . . . · ....·.......... : E : :: :: :: : : : ~ ~ ~ iii i J J -2~--------~~--------+---------~--------~---------4 o ~ J 5 v'orce (Volts) In a typical system application, there may be many TTL outputs from the Vitesse component bussed together with either CMOS or 'IT!.. open collector outputs. The output high level on the bus equilibriates at an operating point (Q point) consistent with the I-V characteristics shown in Figure 7 and the current sourcing capability of the driving device. The output edge rates in the Vitesse TTL outputs are intrinsically fast (see Figure 8). With 30 pF capacitive load, the edge rates are about 3 ns. Handling very fast edge rates on TTL circuit boards is difficult due to the severe ringing that fast edges produce. To control the ringing on the circUit board, it is helpful to buffer the TTL outputs with a silicon bus interface chip such as the 74244. Page 564 ~ VlTESSE Semiconductor Corporation Application Note 2 Interfacing GaAs Products to ECUITL 110 Figure 8: Capacitive loading Effect on Vitesse TTL Output Buffers 5 4 Ci)' -S 3 .....0.. 2 1 0 0 10 20 30 40 50 CL (pF) DC Specifications The following tables (4-8) taken from the FURY Series Gate Array Design Manual are representative of all ofVitesse's GaAs devices. Tables 4, 5 and 6 give DC specifications for the EeL JlO cells using the internal reference, an external diode reference, or a full external reference, respectively. DC specifications for TTL JlOs are in Table 7. Following the tables are specified Recommended Operating Conditions and Absolute Maximum Ratings. Table 4: DC Characteristics for ECl I/O Cells Using Internal Reference ... .. ... ... . .. ... .. .. ........... .1jifti~ ....... ........ ......... i)~fi####~ ••.... ·• • VOH . .•••••• Mm ••••• •• ••• •• Mdi •••• • ••• UhlU ••• ••••••• .•••• $iil4#w~~ ........... . Output mGH voltage Output LOW voltage -1020 700 mV -2000 -1620 mV Input mGH voltage -1100 -700 mV Guaranteed mGH for all inputs Input LOW voltage -2000 -1540 mV Guaranteed LOW for all inputs V IN = Vm (max) orVn,(min) Notes: (1) Over recommended operating conditions, Vee = VeGA = GND, Output Load = 50C! to VTl' @ VlTESSE 1996 Communications Product Data Book Page 565 Application Note 2 Interfacing GaAs Products to ECUITL I/O Table 5: DC Characteristics for ECl 1/0 Cells Using External Diode Reference Notes: (1) Over recommended operating conditions, Vee =VCCA =GND, Output Load =500 to VT7' Table 6: DC Characteristics for ECl 110 Cells Using Full External Reference :HHit#4~/ :::::Li:>~feti~#:·· VOH VOL .>HM.i~: H.>M~ ::uitlU. ::Q~hli~~ Output LOW voltage -1025 -2000 700 -1620 mV mV VIN =Vm (max) orVIL(min) Input HIGH voltage -1165 -700 mV Guaranteed mGH for all inputs Input LOW voltage -2000 -1475 mV Guaranteed LOW for all inputs Output mGH voltage Notes: (1) Over Tecommended operating conditions, Vee =VeGA External Reference =1.32V± O.025v' =GND, Output Load =500 to VT7' Table 7: TTL Inputs/Outputs (Over recommended operating conditions, mGND = GND) Page 566 VOH Output HIGH voltage 2.4 VTIL V VOL Output LOW voltage 0 0.5 V IOL=8mA IOH =-2.4 mA Vm Input HIGH voltage 2.0 VTIL V Guaranteed HIGH for all inputs VIL Input LOW voltage 0 0.8 V Guaranteed LOW for all inputs 1m Input HIGH current 50 Input LOW current f.IA. f.IA. VIN=VTIL IlL IOZH 3-State Output OFF Current HIGH f.IA. VOUT= 2.4V IozL 3-State Output OFF Current LOW f.IA. VoUT =0.5V IOH Open collector output leakage current f.IA. VOUT=2.4V -500 100 -100 100 8 VlTESSE Semiconductor Corporation V IN =0.5V Application Note 2 Interfacing GaAs Products to ECUrTL I/O Absolute Maximum Ratings (1) Potential Pin to Ground, (V'IT ) .......................................................................................................-2.5V to +O.5V Potential Pin to Ground, (V'ITL) .....................................................................................................+6.OV to -O.5V ECL Input Voltage Applied (2), (VIN ECL) ...................................................................................... +0.5V to VTI Tn. Input Voltage Applied (2), (VIN'ITv ....................................................................................... -0.5V to VTTI.. ECL or Tn. Output Current, lour, (DC, output HIGH) ............................................................................ 50 rnA Case Temperature Under Bias, (Tc ) ............................................................................................. _55° to +125°C Storage Temperature(3), (TSTG) ..................................................................................................... _65° to +150°C NOTES: 1) CAUTION: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended periods may affect device reliability. 2) vrr. vrrL must be applied before any input signal voltage and VECUN input must be greater than vrr - O.5lf. 3) Lower limit of specification is ambient temperature and upper limit is case temperature. Recommended Operating Conditions ECL Supply Voltage (VCC ), (VTT ) ................................................................................................... -2.0V ± 5% Tn. Supply Voltage, (VTTI.. ) .......................................................................................................... +5.0V to +5% Operating Temperature (2), (T)(Commercial) 0° to 70°C, (Industrial) -40° to +85°C, (Military) -55° to + 125° C NOTES: 1) When using internal ECL lOOK reference level. 2) Lower limit ofspecification is ambient temperature and upper limit is case temperature. @ VITESSE 1996 Communications Product Data Book Page 567 Application Note 2 Interfacing GaAs Products to ECUITLVO Page 568 @VlTESSE Semiconductor Corporation VITESSE Generation of a -2 Volt Supply From a +5 Volt Supply· Application Note 4 Description Some Vitesse ASIC products need both -2V and +5V power supplies. This application note describes a method of generating a -2V supply from a +5V supply. It is possible to generate the -2V supply from a standard +5V supply, commonly found in TTL systems, by using a Switching regulator IC such as the LTI070 from Linear Technology Corp. (Milpitas, CA). The LTl070 is a monolithic high power switching regulator which can be configured with the aid of a few external components to create a positive input - negative output Flyback Converter. The schematic below depicts a Flyback Converter configuration capable of +5V to -2V conversion. In addition to the LTl070, the circuit includes a standard LMI24 op-amp from National Semiconductor Corp. (Santa Clara, CA) and a PE-65108 Transformer from Pulse Engineering (San Diego, CA). Such a circuit is capable of delivering up to 4 Amps of continuous current at -2 Volts and has line regulation of 0.05%N. Additional information on the LTI070 and the Output Flyback Converter configuration can be obtained from Linear Technology Corp. (408/432-1900) in their Application Note # 19. Figure 1: Flyback Converter Configuration +5V 0.47).1F 1KO PIn 1 112 T °1 (PE·65108) Pin 3 LT1070 1000).lF 1KO 2KO 0.01 ).IF Pin 6 (PE·65108) I. Pin 5 L..--I min -+-I /4- tH~ j4- ~/.----------~, r tsu,tH=?...I I ------/ t pD:5max ~ ~ Case Case Case 1 2 3 Metastable behavior can also be perceived in terms of its effect on flip-flop delay? As seen in Figure 2, the flip-flop has a normal propagation delay, tcQ' when the setup time specification is met. As the data input transition moves closer to the clock transition, however, the delay of the flip-flop increases - reaching its maximum value when the clock and data transitions occur simultaneously. As the data input transition moves past the hold time, no output transition occurs. ® VlTESSE 1996 Communications Product Data Book Page 571 Application Note 6 Metastable Behavior of GaAs DCFL Registers Figure 2: Metastable Delay OUtput Metastable Delay I teQ Register Delay No Transition I::::X: I Data \~ -I...--J'Clock \ I --...- AT ~ I Sstup& Hold Data Transition Time Relative to Clock (A1) Perhaps the most important concept in understanding metastable behavior is that the walk-out time is always a probabilistic phenomenon. A ''maximum'' walkout time for a given register does not exist. Rather, for a certain flip-flop there exists a relationship between a given walk-out time and the probability that this walk-out time will occur. Empirical studies have shown that the mean time between events where the synchronizer flipflop is still unresolved at time tw. MTBF(lW), is: 2,3 MTBF(lW) = exp(t.,/K2) (1) (Kl)(fcLKXfDATA) fortw >h where: lW is the time the flip-flop has been allowed to resolve after the clock transition. Kl, K2, and h are parameters associated with a particular register and are functions of the circuit design and construction. The total walk-out or indeterminate time can be viewed as two time periods: the amount of time taken for random noise to "push" the output just outside of the metastable state (TM)' and the recovery time (TR) from time TM until a valid logic state is achieved. Page 572 ~ VITESSE Semiconductor Corporation Application Note 6 Metastable Behavior of GaAs DCFL Registers Metastability Characterization Metastable beh..vior can be observed using many different methods. Analog circuit simulators such as SPICE cannot accurately characterize metastable behavior in a bistable element unless an accurate noise model is incorporated into the simulation. Given the random and often complex origins of noise in actual circuits, accurate noise models are quite difficult to create. Metastable behavior can also be observed in the lab using fine resolution delay lines to vary the relationship between clock and data until an indeterminate condition is observed using a triggered oscilloscope. Because metastability is a probabilistic phenomenon, however, it is impossible to obtain the Kl, K2, and h constants for a given register using either of the above methods. The most direct and accurate method of characterizing the metastable behavior of a llip-flop is to construct a synchronizer using that flip-flop and gather statistical data on that llip-flop's failure rate as a function of the settling time allowed. This characterization method readily yields the Kl, K2, and h constants necessary to predict synchronizer failure rates. To shorten the duration of the tests, random data transitions can be confined to a small window of time surrounding the active clock transition. Test Setup In order to characterize the metastable properties of GaAs DCFL registers, a synchronizer circuit was implemented on a FURY VSClOK gate array. The circuit schematic is shown in Figure 3. In order to simplify the testing, a latch (LLPIU) was used rather than a flip-flop. The LLPIU is an unbuffered DCFL latch. The clock and data signals are brought onto the chip through differential ECL compatible inputs. The clock (enable) signal was inverted to cause the circuit to latch on a positive clock, again to simplify the test. The output of the latch drives two DCFL inverters, U5 and U6. A difference in switching thresholds between the two inverters is created by using twice the standard D-mode FET width on inverter U5 and twice the E-mode FET width on inverter U6. This threshold window is approximately 130 mV in magnitude centered around the nominal inverter threshold. When the output of the latch is in the indeterminate region, therefore, the output of U5 will be high and the output of U6 will be low. The outputs of U5 and U6 are registered using flip-flops U7 and U8 and are driven off-chip through ECL outputs U9 and UIO. Figure 3: Metastability Circuit Schematic MDATA ~--''---_, MOUTl MDATAREF MCLK MOUll MCLKREF Ul0 U3 RCLK ® VlTESSE 1996 Communications Product Data Book Page 573 Application Note 6 Metastable Behavior of GaAs DCFL Registers Figure 4: Metastability Bench Setup Test Board MCLKIIEF 2KHz L...--:----:-....I 175mV pop t:':;;~~ 1IOUT1 IIOUT2 MCLK; IInATA Multi-Chann.1 Pul•• G.....m. (EH SP(2000) RCLK Clock 10 lhe Count. 10MHz The bench setup shown in Figure 4 was used to conduct the metastability testing. An EH SPG2000 4-channel pulse generator was used to provide the "raw" clock and data signals (MCLK and MDATA) to the latch as well as the RCLK signal to registers U7 and U8. In order to accurately control the relationship between the clock and data signals to the latch, the EeL differential input buffers, Ul and U2), were used as verniers. The MDATAREF signal Was set to a fixed voltage to adjust the clock and data signals so that metastable events per unit time were maximized. A triangie waveform was driven onto the MCLKREF pin in order to sweep the latch back and forth through its entire window of metastabi1ity. The size of the actual window was determined empirically to be about 15 ps. However, a 350 ps sweep window was chosen (by adjusting the amplitude of the triangle waveform) to ensure that the entire period where metastable events occurred was covered even if the MDATAREF input voltage drifted. Because the slew rate of the MCLK/MDATA Signal was set to 0.5 Vlns, a peak-to-peak voltage of 175 mV was used for The register output signals, MOUTI and MOUn, drive an offchip exclusive-OR which in tum drives a 16-bit EeL counter with over-How. For a given test the walkout time, tw, is controlled by setting the delay between the MCLK and RCLK signals. The time between trials (each trial being a latChing edge on MCLK) is set by varying the internal period on the SPG2000 plilse generator. For all of the tests summarized in this document, a period of 100 ns was used which corresponds to a clock rate of 10 MHz. For each part, errors were counted over a specific period of time for various values of walkout time. All of the testing was performed at room temperature with no air How applied to the part. A case temperature of 52± 2°C was measured for these conditions: A nominal supply voltage of -2.0 Volts was applied to the device under test. Prior to the actual MTBF testing, the output of the latch was observed directly using a sampling oscilloscope to ensure that metastable conditions could be induced by the test setup. Page 574 ~ VlTESSE Semiconductor Corporation Application Note 6 Metastable Behavior of GaAs DeFL Registers Test Results Figure 5 shows In(MTBF raw) versus the walkout time. This data is an average of testing done on two devices and is considered to be typical. For both parts, the data taken fit the theoretical model described in equation (1). The value of the experimental constant, h, which represents the minimum value of for which equation (1) holds, was not determined but appears to be less than 1 ns. Further testing is required to establish the worst case MTBF for a given walkout time. Vitesse recommends guardbanding the settling time allowed by at least 1 ns to meet the typical MTBF values specified. tw Figure 5: In(raw MTBF) as a Function of WalkoutTlme 10 Y= - 9.2725 + 5.482e+9x R =0.98 8 6 4 2 o -2 r-------~------~------~------~------~------~ 1.00e-9 2.00e-9 3.00e-9 4.00e-9 Average In (raw MTBF), Tease = 52 C The values for K1 and K2 are derived from the experimental data using the following relationships: K1 = exp(-ln«!cud(fDATA» - b) (2) K2 = 11m (3) where: ! CLK = clock frequency to the latch (to MHz) !DATA = effective data frequency (1.43 GHz) m,b = the slope and y-intercept of the linear fit of In(MTBF) vs. @ tw VlTESSE 1996 Communications Product Data Book Page 575 Application Note 6 Metastable Behavior of GaAs DeFL Registers The effective data rate of 1.43 GHz is achieved by limiting data transitions to the 350 ps sweep window around the clock. Because only a single rising edge occurs in this window, however, the effective data period is twice the sweep window. Using the slope and y-intercept from Figure 5, the values of KI and K2 are: KI = 7.44E-13/sec K2 = 1.82E-10 (dimensionless) Figure 6 charts the MTBF as a function of walkout time for a data frequency of 100 MHz and a clock frequency of 75 MHz. Data is given for both a GaAs DCFL circuit and a typical ECL register. Table 1 shows the typical MTBF for various combinations of feLK' fDATA' and 1w. The user should note that these MTBF values are for a single flip-flop. In order to calculate the MTBF for a dual-stage synchronizer, the MTBF of the first stage must be calculated first. This MTBF then becomes the data rate for the next stage when calculating the cumulative MTBF of the two registers in series. Synchronizer Applications Knowledge of the metastable behavior of registers in a given technology is crucial to the design of synchronizers. The VMEbus, for example, is an entirely asynchronous bUS? Because no timing is specified for bus arbitration signals, decision points such as the bus arbiter, the bus-grant daisy chain, and the interrupt-acknowledge daisy chain must contain synchronizers to resolve timing conflicts. Given that the system clock rate is a known value and the frequency of events to be synchronized can be estimated for the system, the MTBF for the synchronizer can be established based on the MTBF equation for that register. For example, a dual register synchronizer clocked at 100 MHz synchronizing data at 50 MHz will exhibit a mean time between failures of approximately 90 million years, allowing 1 ns for setup time and 1 ns for guardband. If the MTBF for a given amount of settling time is tolerable, a single DCFL register can be used to synchronize random events. For a single register, 100 MHz clock, and 50 MHz data, allowing an additional 5 ns of delay yields a typical MTBF of about 7 years. Figure 6: MTBF VS. WalkoutTime for GaAs and Eel 30.---------------------------------------, 20 ~ Ii:' c III § 10 I- .. is -Uo ~ ·10 ... In(MTBF) GIAe . . In(MTBF) ECl !--.....,r----,--...,.--...,.---r---..,...--.; 1.00.·9 2.008·9 3.008·9 4.008·9 5.008·9 6.00.·9 7.00..9 ·20 ·6.068·28 Walkout Time (sec) Page 576 ® VITESSE Semiconductor Corporation Application Note 6 Metastable Behavior of GaAs DCFL Registers Conclusions Compared with previously published results, initial testing indicates that GaAs DCFL registers are superior to ECL registers in terms of the mean time between failure due to metastable conditions. This result is likely attributable to the fast intrinsic delays of DCFL gates as well as the shorter feedback path inherent in DCFL latches. Past studies show that the trend is for the value of K2 to be lower for newer and faster technologies.2 Further testing will allow the variations in metastable behavior with respect to process to be determined. Testing over temperature and voltage variations is also scheduled although past research indicates that variations in Kl and K2 due to temperature and voltage are minimal compared to variations due to process? Table 1: MTBF as a Function of FDATA • FCLK and WalkoutTlme ....................................................................................................................................................... :: ::::::::::.::::::::::: :.•.::.•.>.:_.• :.e.• :.lk.:·.::.::.:r.:i1.:·.::.z.:.I .• :·:tiJdIk T/H .~r~r~s~~lD,:HH.: .fj~iita(lli) iii \" / •• : .: . :.:.•. i.,.:.~.·.~. .o .•.•. ·.,.•.,~.·. •.•. :. ~e~rI¢a .H!i.~U1:~: :··:Hpa,tiH .............................. L:.n~ \, . .fid 1.00E+07 2.50E+07 5.00E+07 1.00E+OS 3.30E+07 2.ooE+07 5.ooE+07 1.OOE+OS 4.00E-OS 1.S0E-OS S.OOE-09 2.00E+OS 6.60E+07 4.50E-09 l.42E-OS 1.15E+93 7.69E+39 2.99E+15 3.47E+06 3.04E+30 3. 1SE+89 2. 14E+36 S.31E+ll 1.33E+8S S.99E+35 3.46E+l 0 3.64E+85 2.44E+32 9.48E+07 9.65E+02 S.43E+26 4.02E+0l 3.51E+25 1.10E.Ol 9.63E+22 • References 1. Chaney, Thomas J., "Measured Flip-Flop Responses to Marginal Triggering", IEEE Transactions on Computers, Vol. C-32, No. 12, pp. 1207-1209, December 1983. 2. Beaston, John and R. Scott Tetrick "Designers Confront Metastability in Boards and Busses", Computer Design, pp 67-71, March 1, 1986. 3. Chaney, T.J. and F. U. Rosenberger, "Characterization and Scaling MOS flip-flop Performance in Synchronizer Applications", in Proc. Conf. Very Large Scale Integration Architecture, Design, Fabrication, California Instil. Technol., pp. 357-374,22-24 Jan 1979. @ VlTESSE 1996 Communications Product Data Book Page 577 Application Note 6 Metastable Behavior of GaAs DCFL Registers Page 578 ® VlTESSE Semiconductor Corporation VITESSE Application Note 7 GaAsDCFL ASIC Design Introduction For several years, Gallium Arsenide ICs have proven extremely useful in high-speed linear applications such as microwave amplifiers and fiber optic drivers. Within the past five years, however, improvements in processing technology coupled with the use of advanced design techniques have made the production of VLSI GaAs integrated circuits a reality. Vitesse Semiconductor Corporation has developed a tightly controlled GaAs enhancement/depletion mode (FlD) process. This process in conjunction with its direct-coupled FET logic (DCFL) design technique has enabled Vitesse to produce and ship ASIC circuits with complexities of over 100,000 gates. The performance of these circuits and the available EeL-compatible I/O structures allow GaAs DCFLASICs to serve as a viable alternative to ECL gate arrays or standard cells at the system level. This application note describes the similarities and differences in structure and implementation of GaAs DCFL and Bipolar ECUTTL ASIC devices. What is Direct-Coupled FET Logic? Direct-coupled FET logic (DCFL) is a technique used to design logic structures from enhancement and depletion mode FETs. DCFL has been in use since the mid-1970's to build nMOS circuits and is widely recognized for its density and simplicity in the creation of large integrated circuits. On paper, GaAs DCFL logic looks virtually identical to nMOS with the exception that nMOS uses MOSFETs while GaAs DCFL uses MESFETs. MOSFETs have an oxide insulated gate which prevents the flow of gate current, while MESFETs contain a Schottky barrier diode in the gate-source junction which allows the gate to source current supplied from the previous stage of logic. The gate diode also clamps the internal VOH level to about -1.3 V, or one diode drop above V1T Figure 1 shows a 2-input NOR driving an inverter. The depletion mode FETs (Ql & Q4 ) have their gates shorted to their drains and act like current sources. When both DO and Dl are low, Q2 and Q3 ate off, allowing ZNl to rise and turn on Q5. The current from Ql in this case will flow through the gate of Q5. If either DO or Dl are pulled high, the Ql current is shunted through Q2 and/or Q3, pullingZNllow. Figure 1: DCFL 2-lnput NOR and Inverter DO 2-input NOR Inverter DO ZN1 01 @ ZN2 VITEsSE 1996 Communications Product Data Book PageS79 Application Note 7 GaAsDCFL ASIC Design DCFl Features The key advantages of DCFL are circuit simplicity and the ability to switch very quickly using a small supply voltage. The 2-input NOR gate shown in Figure 1, uses only three transistors (resistors are not necessary). OaAs DCFL can operate reliably on a 1.1 V power supply, in contrast to bipolar ECL which requires either 4.5 or 5.2 V. Unlike ECL, no internal reference voltages are needed for OaAs DCFL circuits. All logic switches around the enhancement-mode PET threshold (about 250 m V above the source voltage, VIT). On the flip side, however, OaAs DCFL does not allow the use of series-gated structures, wire-ORs, or collector-dotting (all features of ECL). This is offset by the higher circuit density and corresponding shorter device interconnection lengths found in OaAs DCFL. Virtually all logic structures which have been created for Vitesse ASIC products are constructed from simple inverters or two to four input NOR gates. Figure 2 depicts a full adder macro implemented in OaAs DCFL. The logic portion of this macro is built from three 2-input NORs, five 3-input NORs, and one 4-input NOR. Vitesse incorporates a proprietary buffer on the outputs which effectively drive large capacitive loads with very little skew between the rising and falling edges. Table 1 is a comparison of the OaAs DCFL full adder macro with an equivalent version implemented in silicon bipolar ECL technology. Note that the OaAs DCFL version has a significantly shorter propagation delay, dissipates less than 30% of the power and uses only 70% of the space needed by its silicon counterpart. Figure 2: Full Adder Implemented in GaAs DCFl A~~--~--~~--~~------~--------~--------~--~ BCJ~--~------+---r-~------~----------~----------------~ qnCJ~--~----------~--------~--------------------------------~ Table 1: GaAs DCFl vs. Silicon ECl: Full Adder Macro Comparison AIB~SUM Page 580 560ps l125ps 340ps 1338ps Power (typ) 2.6mW 16.58mW Area 9144~ 31750 18112 @VITESSE Semiconductor Corporation Application Note 7 GaAsDCFL ASIC Design Buffering Tradeoffs Many ECLASIC products allow for a tradeoff between speed and power. This is generally accomplished by allowing the designer to select different switch and emitter follower current values by paralleling resistors using the metal personalization. Generally, the resistors necessary for at least two different speed/power versions of many functions are included in the basic cell. In GaAs DCFL, however, the trade-offs involved in buffering are somewhat different. In Vitesse's FURY and FX Series' of gate arrays, internal macrocells can have unbuffered, Ix drive, or 2x drive outputs. The trade-offs involved with this choice of buffering involve speed, power, and density. Moreover, the speed/power versus density tradeoffs will vary depending on the complexity of the macro function. In general, the presence (or absence) of buffering affects the intrinsic delay of the macro very little. Buffering will increase the driving ability of the macro output in terms of both DC drive limitations and AC performance. On the other hand, buffering requires additional depletion and enhancement mode devices which could otherwise be used for logic and also consumes additional power. The more complex the macro function, the less the price paid for the buffer in terms of percentage area and power. Figures 3 and 4 depict the buffering tradeoffs for a 4-input NOR and a D flip flop in the FX Series macrocelllibrary. Figure 3: FX Macro Buffering Options for a 2-input NOR Gate INTRINSIC DELAY (ps) (A,vg. rl • .nllll) DRIVE (pllhnm, tlslng) CELLI TYP. POWER (mW) Key, fa LN2US(2..JflPUlNORunbUffe,.d) o LN2 (2-i'lpUl NOR 1xbutfsr) • LN2B(2-/npUlNOR 2xbU",,, Figure 4: FX Macro Buffering Options for a D Flip-Flop ... 2.4' 717 27' 2.03 1.'3 u. ,. til INTfUNBle DELAY (pI) (AVI. rlulfal. CLK->Q) DRIVE Cpclmm, rlll"I) tU CELLa TYP. POWER (mWJ Key, C C LFP,U (lIIbUlfsrerJ Rlp-Aop) • LFP'B(FIp·RopllX""",,, LFP' (Rip-Rop '/XbU{fsr) ® VlTESSE 1996 Communications Product Data Book Page 581 Application Note 7 GaAsDCFL ASIC Design FURY Gate Array Architecture Like most third generation EeL gate arrays, the Vitesse FURY Series of gate arrays employ a channeled architecture. Metal! is used to route within macro cells and in the vertical channels between macrocell columns reserved for routing. Metal 2 channels run horizontally over the entire core area. A third layer of metalization is used for fixed power and ground distribution in the macrocell columns. Figure 5 shows the layout of the FURY VSC15K array. Figure 5: FURYVSC15K Array Architecture The YO ring contains 96 input-only buffers on the sides of the array and 100 input/output buffers on the top and bottom for a total of 196 YO pads. A D-latch or buffer can· be implemented in the input-only ce11s and a Dflip flop or a 2 or 3-input ORINOR gate may be placed in the output ce11 structure. In addition, each FURY array contains a small number of high-drive input ce11s which are used for distributing large fanout Signals, such as clocks, to local buffers in different areas of the core. Page 582 ~ VlTESSE Semiconductor Corporation Application Note 7 GaAsDCFL ASIC Design Each cell column in the core is composed of a large number of "slices" (192 in the case of the VSCI5K). A slice consists of four cells in a 2 by 2 configuration. A cell is equivalent to an unbuffered 2-input NOR (two enhancement-mode FETs and one depletion-mode FET). The minimum addressable unit (MAU) in a FURY array is two cells (six FETs). By contrast, the typical ECL gate array MAU contains 10 to 19 transistors and an equal number of resistors. The finer granularity of the FURY MAU minimizes the number of wasted transistors in a given macrocell implementation allowing for virtually 100% use of the core cells. To the IC designer, a Vitesse GaAs DCFL gate array appears much the same as its present ECL counterpart. Both have internal and JlO macrocells and both generally use channeled architectures with two layers of user metal and one layer of power/ground metal. FX Array Architecture The FX Series offers the integration level of BiCMOS gate arrays With speed performance exceeding that of ECL devices. Implemented using Vitesse's proprietary H-GaAs III process, the FX family of gate arrays is the first to combine ultra high integration with leading edge performance. The FX array family incorporates a channelless array architecture which allows metal routing on the first layer to be placed directly over unused cells. This approach avoids the need for pre-defined channels between columns of macros and therefore allows much greater density and flexibility than channelled gate array architectures. Due to an advanced four layer metal process, typical maximum array utilizations range from 50% to 67% of the total available gates. Capable of operating at well over 500 MHz, the FX Series arrays have been designed to provide the best speed - power performance of any gate array technology. The speed of leading edge ECL technology is achieved at a fraction ofECL's power. In addition, because of the frequency independent power consumption of H-GaAs technology, power dissipation levels comparable to, or lower than, similar ~ensity BiCMOS arrays can be achieved at frequencies above 50 MHz (see VitesseApplication Note 10,"Power Dissipation: BiCMOS vs. GaAs"). This power savings can add up to substantial cost savings to users in terms of overall cooling requirements. The FX Family includes support for the creation of custom masterslices. Functions such as SRAMs, multiport register files, and others can be merged with FX arrays resulting in unique architectures and optimum performance. As with all ofVitesse's ASIC products, the FX arrays interface with TTL and EeL devices directly. The FX array family uses standard power supplies and is supported on the ASIC industry's most popular CAE platforms for schematic capture, behavioral modeling and logic synthesis. The FX arrays contain three cell types: intemallogic cells, input only cells and input/output (1/0) cells. All input only and input/output cells contain undedicated logic which the user may personalize. There is enough configurable logic in these cells to implement moderately complex functions such as IDUX'es and flip flops, allowing the arrays to conform to the JTAG boundary scan standard. @ VlTESSE 1996 Communications Product Data Book Page 583 Application Note 7 GaAsDCFL ASIC Design FX arrays can be designed to implement full custom megacells such as SRAM and pre-defined core based megacel1s such as register files. In addition, a proprietary compiler is available to customers wishing to incorporate custom RAM configurations in their designs. A depiction of a VGFX350K with megacells incorporated is shown in Figure 6. Agure 6: FX Array Architecture f ·mpu/ c.-gI I I k¥W~\ E~ N:b: /K) cBIIs wrap around fils ~ and boftom d tho array and iti:Iuds aUldlitJIY grounds so no IIgnIllB need ID be sllCli_. RAMIROM Megacells As with ECL standard cell architectures, the FX gate arrays allow for the inclusion of custom, hand-packed ''megacell'' blocks. Unlike newer ECL standard cell technologies which use BieMOS for the implementation of dense RAM, the FX arrays use the same GaAs FJD process and design rules for RAM and ROM blocks that are used for standard DCFL logic. Page 584 8 VlTESSE Semiconductor Corporation Application Note 7 GaAsDCFL ASIC Design System Considerations At the system level (i.e., looking at a packaged part as a black box), Vitesse GaAs ASICs are virtually identical to ECL ASICs. ECL I/O buffers as well as TTL buffers are supported on all FURY and FX ASIC products. In implementing a board design which includes a Vitesse ASIC, however, the designer should be aware of ECL I/O differences and power supply requirements. ECLVO Vitesse ASICs support ECL lOOK input and output levels. Unlike standard ECL lOOK, however, the GaAs VOL min is always equal to V IT because the ECL outputs are cutoff in the low state. This is not a problem in digital applications, but may necessitate the use of a higher V IT (approximately -1.7 Volts) when driving a DAC because of potential analog feed-through problems associated with the larger input swings. Also, the -2.0 Volt supply must be controlled to ±5% to ensure that adequate noise margins are maintained using the internal V BB reference generator. If such regulation is not feasible, or if the design must receive 10m levels (which vary with temperature), then an external VBB reference should be supplied. Power Supply Considerations Nearly all VitesseASICs use -2Vas the primary supply voltage. In fact, for an ECL-only interface, -2V is the only supply required. Although the power dissipated by GaAs DCFL circuits is relatively small, the -2V regulator must be capable of supplying a large amount of current (up to 4 Amps in the case of a fully utilized VSC15K gate array). When TTL interfaces are needed, a +5V is required. Some gate arrays can be configured to a +5Y, +2V supply environment for TTL only operation. Conclusion Though the internal logic structures and raw materials used to construct GaAs DCFL ASICs are somewhat different from those used to build ECLASICs, the two technologies are virtually identical at the system level. The density and performance of GaAs DCFL ASICs make them attractive alternatives to ECL ASICs in many systems. With the advent of the FX family, the system designer now has the flexibility to more fully reap the benefits of GaAs DCFL technology. The major advantage of GaAs DCFL technology is the ability to produce ASIC devices which offer better density and performance than ECL while dissipating only 1/4 to 115 of the power. ® VlTESSE 1996 Communications Product Data Book Page 585 Application Note 7 GaAsDCFL ASIC Design Page 586 @VlTESSE Semiconductor Corporation VITESSE Application Note 8 Generating an Extemal EeL Reference Introduction The use of multiple ECL (or ECL-compatible GaAs) ASIC devices on a circuit board may require the addition of an externally generated ECL input reference voltage (VBB)' Providing this reference ensures that the input receivers of the EeL devices will all switch at the same threshold voltage independent of power supply or temperature variations. This application note describes a method for providing an external EeL input reference (-1.32 Volts) from a standard -2.0 Volt EeL supply using an adjustable micropower voltage reference and three resistors. Reference Circuit Description The reference circuit employs three resistors and an LM185, LM285, or LM385, which are 3-terminal adjustable band-gap voltage reference devices available from National Semiconductor Corporation. The LM185 is rated for operation over a -55°C to 125°C temperature range, while the LM285 is rated from -40°C to 85°C and the LM385, from O°C to 70°C. A block diagram of the LM185/285/385 is shown in Figure 1. The circuit shown in Figure 2 is used to create the voltage reference. Figure 1: Block Diagram of the LM18512851385 +r---~~----------------~ The reference circuit shown in Figure 2 uses VIT and Vee as external voltages to produce the reference voltage, VREP In order to create a reference which can be used with Vitesse EeL-compatible ASIC parts, the values for R}t R 2, andR3 must be chosen under the following operating conditions: • SupplyVoltage,(VIT) -2.0 Volts (± 10 %) • Current through LM1851285/385 from + to - , (ID ) 0.10 to 20 mA • ADJ Current through LM1851285/385, (IA ) ::; 10 nA (guaranteed by LM185/285/385 specs) • Current to each Vitesse EeL compatible input cell from VREP! (hnput) ::; 5 J.lA • Potential between Vee and ADJ, (~VR2 ) 1.24 Volts (reference voltage produced by the LM385) @ VlTESSE 1996 Communications Product Data Book Page 587 Application Note 8 Generating an External EeL Reference Figure 2: ECl Reference Circuit LM185/285/385 1--" ADJ ~ '----,-------' ~~ R• ... ...._ _ _ _ _....._-("") VREF = -1.32 V v {~ @i LOAD VTT =-2.0 Volts (± 10%) The values for R2 and R3 must satisfy the following condition: R3 [1] V REF= -1.24 (R 2 + 1) By equation [1], the following commonly available resistor values can be used for R2 and R3 to create a 1.32 Volt ± 10mV reference: R 2 = 16Kn R3 =lKn The stability of VREF depends on the tolerances of these two resistors. If k is the maximum normalized value and p is the minimum normalized value of the resistors R 2 and R 3 expressed as decimals, then the variation in V REF is given by the following equation: [2] Page 588 -1 i i ECl autdut i!::'/' i .'...6'........................................................................... . :!vefort. 'l : ~ l l ~ E ~ il l .. . . ........................................................ _........... . . ._............ .. . . . . . , . . . . .. . ,··········"["·········]"""·······r-····-I .. .. ········~. ·""r=..·=·..=.. ·...L· Time (ns) ASIC Device and Package Features to Alleviate ssa Problems All of Vitesse's high-performance packages are designed to minimize the electrical problems associated with simultaneously switching outputs. The power and ground pads on each device are fixed. These pads are bonded to separate planes in the multi-layer ceramic package. In order to isolate critical asynchronous inputs (such as clock and reset signals) from noise generated by output switching, outputs on Vitesse devices are confined to the top and bottom of the die (see Figure 4). Signals which are sensitive to noise can then be brought onto the device though input buffers on the left and right sides of the die. This not only isolates the inputs and outputs on the die itself but also minimizes mutual coupling (crosstalk) between output and input bond wires by placing them at 90° with respect to one another. Page 598 ® VlTESSE Semiconductor Corporation Application Note 11 The Effects of Simultaneously Switching Outputs in GaAs Devices SSO Test Chip Description output Registers In order to gain an empirical understanding of the effects of Switching large groups of outputs on a large device, Vitesse has designed and produced a test chip specifically designed to examine these effects. The schematic of the test chip is shown in Figure 3. The SSO test chip, or SSOTC, is implemented using a Vitesse FURY VSCI0K gate array in a 211 PGA package. The test circuitry consists of 80 shift registers grouped into four banks of 20 registers each. Each shift register contains four D flip-flops. The four Bank Scan signals allow data on the SDAT (scan data) bus to be clocked into the shift registers on a bank by bank basis. The input CLOCK serves as the system clock for both scanning and shifting operations. To reset all the registers at once, the RESET signal can be asserted~ The BZ bus signals allow the user to force the outputs of given bank to logic low without resetting the registers in the bank. Using the scan inputs, patterns which switch anywhere from one up to 80 outputs can be scanned in and clocked to the Z outputs. As with all FURY gate arrays, the power and ground pins are in fixed locations. In order to minimize the undesirable effects of simultaneous output switching, every four outputs typically share a ground, or VCCA, pad. The VCCA pads are in turn bonded to conductor planes in the 211 PGA package. Figure 3: Benchmark Circuit Upset Struchlr" UPOUT Upset Structures In order to mouitor the coupling of noise back into the SSO test chip, eight upset structures are interspersed around the periphery of the gate array as shown in Figure 4. Each upset structure consists of a D flip flop (FURY LFP3 macrocell) configured so that it will toggle on an active clock edge. The clock inputs of these structures (UPCLK bus) are driven by ECL input pins. The outputs of these structures are connected directly to ECL outputs (UPOUT bus). If the noise generated by the simultaneous output switching is sufficiently coupled to the upset structure input, the flip-flop will toggle, thus signifying an upset failure. ® VlTESSE 1996 Communications Product Data Book Page 599 Application Note 11 The Effects of Simultaneously Switching Outputs in GaAs Devices SSO Test Results Characterization of SSO effects was performed on a Teradyne 1953 VLSI tester. In order to execute a given test, all the shift registers are first reset and then logic highs are shifted into the registers whose outputs are to switch. The master clock is then used to shift the pattern to the outputs causing first a group of simultaneous rising edges and then a group of simultaneous falling edges. Simultaneous Switching Delay The effects of concurrent switching on output delay were measured by connecting both the CLK signal and one of the Z outputs, to a high speed oscilloscope while the test chip is in the Teradyne test fixture. The tester was then used to force various switching patterns on the part while the relative delay was monitored. During the initial testing, it was determined that most of the observed SSO delay was due to the device test fixture. The test fixture was re-worked to minimize the impedance to the VCCA pins. Subsequent testing showed a minimal delay degradation as increasing numbers of outputs sharing the same VCCA pin were switched. Analysis of the delay data showed the following typical delay per output switched: TpJsso) =15 ps/SSO for EeL outputs which share a common VCCA pad. A maximum total delay degradation of approximately 100 ps was observed when switching up to six EeL outputs sharing the same VCCA pad. Increasing the number of outputs switching beyond six, however, appeared to have a negligible effect on the output delay. Simultaneous Switching Noise A second phase of testing was performed to characterize the coupling of SSO noise to input pins. For these tests, various combinations of the Z outputs were switched and the states of the upset structure outputs (UPOUT bus) were monitored. No upset structure failures were observed when switching up to 40 outputs simultaneously. Results for more than 40 outputs switching were inconclusive due to the noise inherent in the VLSI test environment. Figure 4: SSO Test Chip Block Diagram I I I --,...- I I I I I~,~l~/] L/ I t I "".1 I .-~..,... I .'HFT~_ t Page 600 ~V1TESSE Semiconductor Corporation I I Application Note 11 The Effects of Simultaneously Switching Outputs in GaAs Devices As previously noted, however, SSO noise in the device appeared to be primarily a localized effect. The design of the pad ring on the FURY 10K as well as the design of the 211 PGA itself appears to accommodate the switching of all 100 ECL outputs on the device simultaneously with no effect on intemallogic states. System Design Recommendations for Minimizing SSO Effects To minimize the possibility of SSO related problems in a given system, precautions should be taken in the arrangement of the inputs and outputs on theASIC as well as in the construction of the board on which the integrated circuit(s) will reside. The following guidelines summarize these precautions. ASIC and Board Design Guidelines 1. Place all clock, set, or reset signals on the ASIC at least six pads away from any output. 2. When designing a custom pad ring,a) a VCCA pad should be allotted for each set offour ECL or GaAs outputs, and b) two VCCA pads and a VTTL (+5 V) pad should be allotted for each set of eight TTL outputs. 3. A large power plane should be used on the PC for distribution ofVCCA (Figure 5). 4. The peak switching current should be estimated for the worst case number of SSOs per device and adequate bypass capacitance should be added to satisfy the transient VCCA and VTTL current needs. Bypass CapaCitor Recommendations Bypass capacitors must be used in high frequency (> 100MHz) designs to filter out high frequency variations in the power supply voltages at the device power inputs and on the board. The following bypassing is recommended. 1. A 0.DlJ.tF high frequency capacitor should be placed between ground (VCCA) and each V IT (-2Volt) pin as close to the V IT pin as possible. 2. A 1 to 10 J.tF capacitor should be placed on the board at the power supply inputs to filter out variation in the power supply with longer time constants (e.g. power supply noise at the system clock frequency.) Figure 5: Recommended Ground Distribution ® VlTESSE 1996 Communications Product Data Book Page 601 The Effects of Simuftaneously Switching Outputs in GaAs Devices Page 602 e VlTESSE Semiconductor Corporation Application Note 11 VITESSE Application Note 13 Calculating Path Delays in FX Gate Arrays Introduction The following information is provided to aid in estimating AC path delays in the FX Series of gate arrays. A delay equation is a first order approximation of the actual delay and is a convenient way to estimate delays with manual calculations. The simulation tools Vitesse provides in its software suite use a delay equation that is far more sophisticated. For this reason, simulation delays will not match perfectly with hand calculations using this model. For most preliminary investigations, however, the follOwing delay equation is sufficient. Delay Equation The delay for each macro is expressed in terms of an equation which specifies the delay as a function of intrinsic delay, pin loading, metal length, pin drive, and derating based on a composite measure of process, temperature, and voltage. The standard form of the delay equation is shown below. ML] K* DELAY= [ Tp + I-NI -K1 + -K2 NO NO For output macros the following equation is used for the delay from A to PAD: DELAY (A to PAD) = [T P + k T P K 1{ C L)] K* For TTL output macros the following equation is used to determine the TRI to PAD delay: DELAY (TRI to PAD) = [rp]K* where: Tp = I-Nr = ML = No Kl K2 K* CL kTp = = = = = = The intrinsic delay of the macro for fan-out = 0, 0 mm of wire, and typical conditions (ps) Sum of the AC input loads being driven by the output (fan-out) Metal length being driven by the output (mm) Drive capability of output (dimensionless) Fan-out derating factor (pslfan-out) Metal load derating factor (pslmm) Composite derating factor (dimensionless) Load capacitance (pF) Load dependent delay (pslpF) ® VlTESSE 1996 Communications Product Data Book Page 603 Application Note 13 Calculating Path Delays in FX Gate Arrays The fan-out factor, K 1 , and metal load factor, K 2 • are parameters which have different values for low to high and high to low output signal transitions. They are used to convert the driven load drive strength ratios into time units. Their values are given in Table 1. Table 1: Fan-Out (K1) and Metal Load (K:z) Derating Factors ·.•.••.• :1Wimt#tJ~.: .:::. ::.: •••• trli~~t#tJ~.: ••• ··· HHtQ.WiQH.tgh •••• ·i:l;i#h~.~H 14 . 23 86 86 pshnm Notes: 1) Applies to propagation delays with an output signal transition from low to high. 2) Applies to propagation delays with an output signal transition from high to low. The composite derating factor, K*, given in Table 2, represents the extreme cases of process, temperature and voltage. Table 2: K* Composite Performance Derating Factors Notes: 1) Applies to propagation delays with an output signal transition from low to high. 2) Applies to propagation delays with an output signal transition from high to low. The information required to estimate path delays is found in the macro library contained in the FX Series GateArray Design Manual, version 2.0. Each dat~ sheet in this library contains the macro name, functional description, cell utilization, the macro's icon as it appears on the workstation screen, a logical truth table, intrinsic delay, power dissipation, and loading factors. The propagation delay (Tp) for every path through the macro is an intrinsic number based on a fan-out of 0, a wire load of 0 rom, and junction temperature of 25° C. They do not represent actual delay, but are used as the first entry in the delay equation. The loading factors give the fan-in load factor (AC and DC) for input pins (N[) and the output drive (No)(AC and DC) which each of the macro outputs provide. Page 604 8 VITESSE Semiconductor Corporation Application Note 13 Calculating Path Delays in FX Gate Anays Estimating Metal Lengths Before Place and Route The following formula should be used to predict the metal interconnect length on a critical path net when estimating timing using hand calculations. This formula assumes that all macros have been hand placed to optimize metal interconnect lengths or have been grouped into sections smaller than a few thousand gates each prior to automatic placement. ML= (N -1)O.17mm where: ML N = predicted metal interconnect length in mm number of connections on the net Figure 1: Sample Critical Path Calculation Sample Critical Path Calculation In the example at right, a critical path interconnect length of 0.17 mm of wire per driven inptA is assumed. To calculate the maximum clock frequency under worst case conditions through the path, the worst case delay must first be determined. A summary of this calculation is shown below. MIICI'O Signa' REG rise NOF12 BUF ... c'" '"' "". roNI ML Tp + --Kl + -K2 No No fall 180 290 rise fall 00 SO : ~ + + 52.7 42.3 + + 24.8 16.6 + + 28.3 17.4 + + 24.8 13.7 Poaible Delay Pat".: K* Delay 1.01 1.04 280.1 362.9 1.01 1.04 132.4 64.3 rise fall 00 40 + + 71.7 52.2 + + 22.5 13.7 1.01 1.04 155.7 110.1 XNOR2 rise f.1I 340 310 + + 8.8 7.4 + + 24.8 17.4 1.01 1.04 377.3 348.2 MUX41 rise fall rise fall rise fall 210 270 + + + 00 + + 59.8 44.4 28.3 17.4 28.1 17.4 24.8 13.7 1.01 1.04 1.01 1.04 1.01 1.04 300.9 345.1 132.4 64.3 104 104 NOR2 REG t",(set-up) SO 100 100 + + -- + + + + + -- 1. T.... (REG1)+ T , .....(NOR2) + T..",(BUF) + T,....(XNOR2) + T,.... (MUX41) + T....(NOFl2) + T...(REG)= 1429.8 ps 2. T,.....(REG1)+T....(NOR2)+ T,....(BUF) + T.... (XNOFl2) + T.... (MUX41)+ T , .....(NOFl2)+ T...(REG)= 1471.9ps Tota, WoNt ea.e Path Delay: 1471.9ps MlVClmum Clock Rate: 111471.9 p.. =679 MHz NOTE: WOlSt cast derated setup time is used irrespective of signal trandion. TSKEW Where: TCQ TD TRC THOW TSKEW Signal propagation delay from clock input to data output for register Ul Signal propagation delay due to combinatorial logic Signal propagation delay due to metal interconnect RC effects Data valid hold time requirement for register U2 Maximum skew between clock signals CLKl & CLK2 This issue becomes important in circuits such as shift registers or scan chains. If the clock skew is negative (the clock arrives at the second register before it arrives at the first), the logic delay must be decreased or the system clock period must be increased to satisfy setup times. To avoid setup violations, the following equation must be met: TcQ(max) + TD(max) + TRc(max) +TsET-up(max) + TSKEw< t Where: TSET-UP t Data valid set-up time requirement for register U2 TIme for one period of the clock Two categories of clock skew are defined for ASICs: on-chip skew and chip-to-chip skew. On-chip skew is determined by RC delay, loading variations, and transistor drive variations. This skew can be minimized with the fixed architectures described in Section III, "Clock Tree Architectures" . Chip-to-chip skew is determined by board level clock loading and drive variations, and on-chip clock latency variations from die to die. Special clock drivers and board layout techniques can minimize board level clock skew, and clock delay variations from one chip to another can be minimized by using one or more of the following methods: l) By using special board level clock driver chips with multiple outputs, clock edges can be adjusted to cancel the clock delay on the die. 2) Ceramic delay lines are included in series with each cloCk line to each chip on the board. Delay lines of various lengths can be added to the board to tailor the clock edge to each part. 3) A variable tap delay line (vernier) can be included on each chip. This delay line will add extra clock delay to faster parts for clock edge alignment with slower parts. 4) APhase-Lock-Loop (PLL) can be included on each chip to lock the edge of the internal clock to a lightly loaded global reference clock edge. Page 614 ® VlTESSE Semiconductor Corporation Application Note 17 Implementing the Fixed Clock "ee in FX Gate Arrays Items 1, 2, and 3 require a clock monitor output signal on each chip. Item 3 requires several input signals to adjust the clock edge. Item 4 requires a reference clock input signal. The clock duty cycle can become distorted as the clock signal travels through several levels of buffering. Flip-Hops have minimum clock pulse width specs that must be satisfied. In addition, latch based designs must maintain close to 50% duty cycle in order to achieve high clock frequencies. Clock edge rate can affect both skew and pulse width. The input switching thresholds of clock buffers and Hip-Hops vary due to process, temperature, and power supply variations. This variation translates into clock skew. The amount of skew is defined by the following equation: skew = (Vsw mismatch)/(edge rate V/ns) For very slow edge rates, a small threshold mismatch can cause race conditions even within latches and HipHops. Also, if slow edge rates keep the clock signal from reaching full voltage swing. Minimum pulse width violations can result To avoid these violations, it is desirable to maintain edge rates that are less than 20% of the clock period and a maximum of 1 ns for high speed designs. Clock Tree Architectures Clock tree architecture and layout are key elements affecting skew and edge rate. When considering clock tree architectures, the main objectives are to minimize overall clock tree propagation delay while maintaining good edge rates (chip-to-chip skew), and to minimize differences in the clock tree branches (on-chip skew). Secondary objectives include minimizing the place-and-route blockages created by the clock tree and providing standard 110 interface levels (ECL, TTL). The input capacitance on the clock input buffer must be minimized so that it does not represent a large capacitive stub to the PC board clock transmission line. Typical ASIC clock trees have to drive a total capacitance in the 100s of pF range. To drive this capacitance, current is typically amplified through several stages of buffers while maintaining minimum capacitance to the input pin. The goal is to minimize the number of buffer stages while maintaining good edge rates and low duty cycle distortion. Minimum and maximum clock tree delays can be established by multiplying the total clock tree delay by the composite ASIC derating factors. The difference between these delays is the device's contribution to chip-to-chip skew. Therefore, minimizing total clock tree delay will also minimize chip-to-chip clock skew. On-chip skew can be minimized by carefully balancing the clock tree. The traditional approach is to use a hierarchy of 'H' patterns as shown in Rgure 2. Typically, additional buffers are used at the four ends of the 'H'. This approach provides a very well balanced RC delay to any local driver on the die. It also minimizes RC delay by having several buffer stages along the RC path. However, the 'H' pattern approach also has several disadvantages including: @ VlTESSE 1996 Communications Product Data Book Page 615 Implementing the Fixed Clock 7i"ee in FX Gate Attays Application Note 17 Figure 2: Clock Tree with Three Levels of 'H' Patterns 1) Several stages of clock bu1Iers are typically used, increasing clock tree delay and chip-ta-chip skew. 2) Local driver delay variations must be accounted for in the on-chip Skew budget 3) Local clock bu1Iers are placed in the middle of the array, restricting the placement of large on-core megacells such as register files. 4) There are a limited number of local clock. bu1Iers at the end of the tree. Therefore, a significant portion of the clock tree will be routed with a place and route tool, adding to on-chip skew. 5) Depending on clock tree bu1Ier placement, embedded memory blocks can cause unbalanced clock branches. Rebalancing the clock tree may require added bu1Ier stages, leading to higher chip-ta-chip skew. The clock tree must also support I/O bu1Iers and embedded memory blocks. Many designs use registered I/ o synchronized to the core logic. In addition, pipelined memories have registered inputs and outputs. Both of these structures typically connect to the clock tree and must maintain the same clock skew specification as other registers in the design. In many cases, the clock tree must be tailored for these applications. Skew can also be reduced by routing the clock on the thickest metal available. This will minimize RC delay. The RC product for a Imm length of metal versus metal width is shown in Figure 3. In this example, widening the line greater than 5 microns has little effect on the RC delay, because the parallel plate capacitance becomes dominant above this width. Figure 3 clearly shows that Metal 2 and Metal 3 have much lower RC delay than Metal 1. The thicker metal in Metal 2 and Metal 3 reduces resistance but does not significantly affect capacitance. The thicker dielectrics surrounding these metals also contribute to their lower RC delay. Page 616 e VlTESSE Semiconductor Corporation Application Note 17 Implementing the Fixed Clock Tree in FX Gate Arrays Figure 3: RC Product for 1mm Wire vs. Wire Width (Approx for H-GaAs III) I . c:- 10 Q. S ~ 5_ (::: 5 1b I 15 :::.. M3 20 W(Il) Vitesse Clock Trees Vitesse has designed fixed clock trees for the FX gate array family to minimize most of the problems associated with the 'H' clock trees described above. Figure 4 shows the basic architecture and layout of this fixed clock tree. An input receiver at the top of the array drives a single large 'H' pattern through a very large buffer. Across the top and bottom of the array, local drivers feed local clock lines over every utilized column. In the comers, additional local drivers connect to local vertical and horizontal clock lines near the I/O buffers serving any registered I/O requirements. All clock routing is done in vertical Metal 3 and horizontal Metal 2, conforming to the signal routing convention and minimizing place and route blockages. In addition, the thick Metal 2 and Metal 3 used in the clock tree minimizes RC delay as discussed above. Finally. all outputs from the local drivers are shorted together to minimize skew. The single drawback of the fixed clock tree approach is that the RC paths to each local driver are not identical. However, this adds less than lOOps to the skew on the largest array. This minor disadvantage is far outweighed by its many features including: 1) Only two stages of clock buffers are used, minimizing total propagation delay. 2) Since the outputs of all the local buffers are shorted together, local driver variations are virtually eliminated. 3) The local clock drivers are located only on the top and bottom edges of the gate array core. On-core megacells such as register files can therefore be placed anywhere in the core area. 4) Each usable gate array column has a dedicated local clock driver and clock line. Flip-Hops make connections to the local clock lines through short stubs of Metal 2. The small length variations in these Metal 2 stubs add no additional skew. 5) Embedded memory blocks can easily be added by subtracting only local clock lines. This maintains skew balance on the global 'H' clock bus. ® VlTESSE 1996 Communications Product Data Book Page 617 Application Note 17 Implementing the Fixed Clock Tree in FX Gate Aflays Figure 4: Vitesse Fixed Clock Tree Clock Input • Note: drawing not to scale Vitesse offers two types of input buffers for the clock trees. The ECL buffer is a differential input that can be used on EeL only or mixed ECUTTL FX gate arrays. If a high-speed clock is required on a TTL only array, this buffer can also be used, with its input levels referenced to VMM (+2V) instead of ground. The second type of buffer is a TTL single-ended input for the TTL only FX arrays. The I/O buffer and SRAM clock tree interfaces have been designed to add no additional skew to the overall clock tree. On the sides of the arrays, the local clock is routed with a vertical Metal 3 line over the core cells that exist inside the I/O buffer. On the top and bottom of the arrays, the local clock lines are routed in Metal 2 just outside the I/O core cells. To accommodate this, different registered I/O personalizations are used on the sides of the arrays than are used on the top and bottom. The SRAM layouts contain a horizontal Metal 2 clock line that is part of the compiled SRAM layout. Severallocal clock buffers are connected in parallel to drive this line depending on the fan-out load. Table 1 lists some of the key clock tree characteristics for the S gate arrays in the FX family. Skew and power dissipation specifications are all maximums. Keep in mind that the across die skew listed is a maximum value. This skew number must be derated along with the logic delays. Also, the numbers listed are for worst case points on the die. The skew will be much smaller «SOps) for flip-flops in close proximity. Page 618 @VlTESSE Semiconductor Corporation Application Note 17 Implementing the Fixed Clock "ee in FX Gate Anays Table 1: ECl Fixed Clock Tree Characteristics 1) 2) Max. Prop Delay (rise) 1200 ps 1540ps 1610ps 2020ps Across Die Skew 50ps 70ps lOOps 150ps 200ps Chip-Chip Skew 840ps 1080ps 1130ps 1410ps 1720ps Max Frequency! 650 MHz 600 MHz 550 MHz 450 MHz 350 MHz Min Input Pulse 770ps 830ps 910ps 1110ps 1430ps Cells Required' 1198 1284 2544 4848 5200 Max. Flip-Flops 1120 1960 3840 7733 8320 Min Flip-Flops 56 92 192 387 416 Max. DC Power 202mW 316mW 617mW 1145mW 1224mW Assumes maximum jlip-ftip utilization. Subtract from raw cell count. . Table 2: TTL Fixed Clock Tree Characteristics 1) 2) Assumes maximumjlip-ftip utilization. Subtract from raw cell count. @ V1TESSE 1996 Communications Product Data Book 2460ps Implementing the Fixed Clock Tree in FX Gate Armys Application Note 17 CAD Interface This section discusses the clock trees in relation to the Vitesse ASIC CAD flow. Each clock tree is offered as a macrocell in the FX macrocelllibrary. One macrocell is listed for each particular FX array size and are named accordingly; CLK20K, CLK40K, CLKIOOK, CLK200K, or CLK350K for ECL level clocks and CLK20KT, CLK40KT, CLKIOOKT, CLK200KT, or CLK350KT for TTL level clocks. The array specific section of the FX Design Manual lists the specific pad numbers for which the fixed clock inputs are reserved. In utilizing the fixed clock tree the user creates one global clock net and drives it with the special clock tree macrocell during schematic capture. Since the metal in the clock tree is fixed, the change in delay after back annotation is insignificant. Fan-out on the clock tree is automatically extracted from the netlist during netlist compilation so that the overall clocktree delay can be adjusted due to loading. The resulting ERC report will issue errors if the maximum or minimum fan-out is violated for the clock tree in the netlist. The fixed clock tree input buffer is placed in a reserved position in the 110 pad ring and the subsequent branch buffers cannot be placed by the user. Placement is performed automatically and is therefore transparent to the user. As a result, the number of available cells in the gate array socket set is reduced when a fixed clock tree is chosen because the local clock drivers use 5 or 6 rows of core cells at the top and bottom of the gate array. These rows are automatically subtracted from the total available cells by the ERC when estimating gate array utilization. A Vitesse post-placement software routine has been developed that pre-routes the short Metal 2 stubs connecting the pre-placed flip-flops to the local clock lines. This routine also balances the loading across the array. Final timing simUlations including on-chip skew are run on LASAR before CDR. Skew is included by using a fixed value, per a table, and adding it to each connection in the clock tree. This skew is the maximum specified for the global clock tree. Custom Masterslices Custom masterslices require modifications to both the clock tree layout and the CAD software. First, local clock lines are removed in the locations of the embedded memory blocks. In some cases, more extensive modifications are required. Next, SPICE simulations are run on the new tree to determine skew and edge rate. Finally, the socket set and pre-routing software must be modified with the new clock tree information. Because of these steps, a masterslice with a fixed clock tree has a higher NRE charge than a masterslice without one. Page 620 @VITESSE Semiconductor Corporation VITESSE Application Note 18 Generation of +2V or +3.3 V Supplies from a +5V Supply Some Vitesse products require both +2 and +5 Volt power supplies. In the event that a +2 V supply is not available in the system, a simple method exists to generate the +2 V from a +5 V supply. This method involves the use of a low cost voltage regulator. Voltage regulator ICs are offered by several vendors including National Semiconductor Corp., linear Technology Inc., and Advanced Micro Devices. Figure 1: Generating +2V or +3.3V with the LT117A LT117A = VREF ~+~) VOUT OUT IN T + I A(lJ R2 VREF ADJ I RI 1 IADJ - , R2 ==-A voltage regulator IC, such as the LT117A made by Linear Technology, is a 3 terminal device. The LT117A develops a 1.25 V reference voltage between the OUT and theADJ terminal (see Figure 1). By placing a resistor, R l' between these two terminals, a constant current is caused to flow through R 1 and down through R2 to set the overall output voltage. Normally this current is the specified minimum load current (approximately 5 rnA). An additional current, called lAD}' flows from theADJ terminal through R 2 • This is a very small and constant current with a magnitude of approximately 50 !lAo Figure 2: Generating +2V from a +5V Supply LT117A +5 V -l4---I I +2 V OUT~~l---------'----- IN ADJ I ~. 205!l 1.25 V 1 50)lA - - , ~= 121!l >~ ® VlTESSE 1996 Communications Product Data Book Page 621 Application Note 18 Generation-of +2V or +3.3V Supplies from a +5V Supply It can be seen from the equation in Figure 1 that the accuracy of the output voltage is limited by the accuracy of V REF and the tolerance of the R 1 andR2 resistors. The LT117A has a very tight initial tolerance of V REF which permits the use of relatively inexpensive 1% film resistors for R 1 and R2 while setting an output voltage tolerance which is compatible with the ±5% need ofVitesse products. If voltage regulators with wider reference tolerance are used (such as industry standard LMl17), a trim pot may be needed to set the exact value of the output voltage. Figure 2 depicts the LT117A with the resistor values needed to generate the +2 V supply. The output current of the LT117A is limited to 1.5 Amps. For systems which use several chips, and regular larger currents regulation can be accomplished by devices such as the LTl038 (also from Linear Technology) which can handle an output current up to 10 Amps. The use of this larger regulator is identical to the LT117A. Some Vitess~products, such as the VSC7105n106 chipset, require a single +3.3V supply. Such a supply can be created from a +5V supply with theLT117A with the circuit shown in Ft.gUre 3. Figure 3: Generating +3.3V from a +5V Supply +5 V ... .1 I - ":" LT117A IN +3. 3 OUT ADJ l- ~= 205 I ~332 ~ Page 622 @VlTESSE Semiconductor Corporation Application Note 18 Generation of +2V or +3.3V Supplies from a +5V Supply Protection Diodes The LTl17A does not require a protection diode from the adjustment terminal to the output as shown in Figure 2. Improved internal circuitry eliminates the need for this diode when the adjustment pin is bypassed with a capacitor to improve ripple rejection. If a very large output capacitor is used, such as a 1001JP shown in Figure 4, the regulator could be damaged or destroyed if the input is accidentally shorted to ground or crowbarred. This is due to the output capacitor discharging into the output terminal of the regulator. To prevent damage a diode Dl is recommended to safely discharge the capacitor. Rgure 4: Implementing Protection Diodes for a Larger COUT 01 ... IN4002 LT117A OUT IN J+ ADJ 10I'F:: RI -- -- C "ADJ R2 - @ 1OOI'F }:COUT ~""~ L... VlTESSE 1996 Communications Product Data Book Page 623 Application Note 18 Generation of +2V or +3.3V Supplies from a +5V Supply Page 624 e VlTESSE Semiconductor Corporation VITESSE Application Note 20 Plastic Packaging Moisture Sensitivity Levels Plastic packages are moisture sensitive. This may cause problems if not attended to properly. This application note describes suggested handling procedures for Vitesse products shipped in plastic packaging. When the epoxy molding resin used in the plastic package molding process is left in the open, moisture in the air penetrates the package and diffuses internally throughout the package. When plastic packages are subsequently heated during the soldering process, this moisture vaporizes. To minimize the effects of moisture absorbed in the package, these moisture-sensitive parts must be dry prior to being subjected to the high temperatures of second level assembly. A dry pack and handling procedure has been established to help ensure low moisture levels in the components prior to second level assembly. The dry pack procedure consists of a 24-hour bake at 125°C. After baking, the units are virtually dry. Within one hour of completion of the bake cycle, the units are sealed in moisture-barrier bags with a dessicant bag and a humidity indicator. These moisture-barrier shipping bags provide a shelf storage life of 12 months from the date of sealing, when stored at a temperature of :S;30°C and 60% relative humidity. After this time, the parts must be baked again for 24 hours at 125°C to ensure no moisture related problems during second level assembly. Moisture absorption depends upon several factors including package size and thickness. This means that each package may have different moisture sensitivity. JEDEC has standardized moisture sensitivity levels with the proposed specification #A112. It specifies 6 levels of moisture sensitivity as well as the handling procedures to be followed at the customer site to protect the parts against moisture-related problems. These levels are summarized in the table below. Table 1: Levels of Moisture Sensitivity < >... •••••.••• H H ill"a#1IfUrn, jriQQhWe··· ••• ..................... ••••••.••••••••••••• .li@i~"g~...........'" ::;30°C 90% Unlimited 2 ::;30°C 60% 1 year 3 ::;30°C 60% 168 hours 4 ::;30°C 60% 72 hours 5 ::;30°C 60% 24 hours 6 ::;30°C 60% 6 hours 14x14x2.0mm 52L, 144L QFP 28 x 28 x 3.5mm 184L. 208L QFP 14x20x2.7mm 100LQFP lOx 10 2.0 mm 52LQFP Note: 1) Deduct 1 hour from the maximumjtoorlife time to comprehend the time between bake and drypack prior to shipment to the customer. ® VlTESSE 1996 Communications Product Data Book Page 625 Application Note 20 Plastic Packaging Moisture Sensitivity Levels Handling of Devices at Customer Site Moisture sensitive devices require specific care at the customer site where second level assembly is performed. The dry pack bags should be inspected prior to use. If the moisture-barrier bags have been opened at any time prior to the expiration date, or if upon opening, the humidity card reads greater than 30% relative humidity, the following precautions must be taken: • If the humidity card reads greater than 30% relative humidity, the units must be rebaked for 24 hours at 125°C. • If the expiration date on the dry pack bag has elapsed, the units will require a rebake for 24 hours at 125°C prior to second level assembly. • The units must be rebaked for 24 hours at 125°C if the moisture-barrier bag has been opened for longer than specified in the previous table: Levels of Moisture Sensitivity. As an example, consider the 28 rom x 28 rom x 3.5 rom, 208L thermally enhanced PQFP. According to the previoous table, this package is a level 3 package. Vitesse bakes the 208L QFP at 125°C for 24 hours, seals it in a dry pack bag within 1 hour of the completion of the bake cycle, and ships it to the customer. Because this package is a level 3 package, it has a maximum floor life of 168 hours. The customer receives the part, opens the bag after confirming that the dry pack expiration date has not passed, and verifies that the humidity indicator reads :S:30% relative humidity. Since one hour is consumed between bake and dry pack, the customer must assemble the 208L QFP within 167 hours of opening the dry pack bag. During this period, the parts should be stored in a controlled environment as indicated in the table. Vitesse currently ships in high temperature trays that can withstand the 125°C bake temperature. If low temperature trays are used, a low-temperature bake must be used. This has not been specified by Vitesse although other sources have verified that baking at 40°C for 192 hours achieves a moisture level below the critical level necessary lime for second level assembly. Page 626 @VlTESSE Semiconductor Corporation VITESSE Application Note 22 Interfacing Vitesse +3.3V TTL with +5V CMOS Introduction As the world transitions from purely 5V systems to 3V systems, there will be a number of systems incorporating both 3V and 5V logic. Driving 5V logic from 3V logic does not present a problem so long as the V1H and VLL limits are met. However, when driving 3V logic from 5V logic, an overdrive condition may occur. This application note discusses potential problems and suggests two interface techniques for driving a 3.3V Vitesse chip with a 5V CMOS chip. The primary concern when driving a Vitesse TTL input from a +5V CMOS output is exceeding the electromigration limit of the common ESD Bus inside the Vitesse chip. When the signal exceeds VTll,+ 1V (approximately 4.3V), the ESD diodes become forward biased, (see Figure 1). A number of TTL inputs will share a common ESD bus and if all of the TTL input ESD diodes are forward biased at the same time the current on the common ESD bus can become excessive. Exceeding the electromigration limit on the common ESD bus can cause reliability problems over a period of time. Therefore, Vitesse recommends either limiting the current into the ESD diodes or limiting the V OH (max) seen at the TTL input pad. Figure 1: TTL Input ESC Structure +3.3V Common ESD Diode +5VCMOS Outputs CMOS Chip ••• \ / Chip Boundaries ~ • •• Vitesse TTL Inputs Vitesse Chip VlTESSE 1996 Communications Product Data Book Page 627 Application Note 22 Interfacing Vitesse +3.3V Tn with +5V CMOS Solution #1, Series Resistor One solution to the problem is the addition of a current limiting resistor in series with each TIL input, as shown in Figure 2. This will limit the amount of current that each input will contribute to the common ESD bus. The minimum size of the resistor is dependent on the number of TTL inputs sharing the common ESD bus. Rgure 2: Series Resistor +3.3V • Common ESD Bus Series Resistor R l ~ Lr I- :J. L:. ..., lL:J. l- L~ 7.~ Common ESDDiode -- ESDDiodes +5V CMOS "'~m--"'t--fVV'I/\..--+O""'''r-.e-+--+-t--+---;..f» Outputs .. _ ...... ..... - .... - ••• \ I ••• Vitesse TTL Inputs ~ Chip Boundaries The equation for determining the minimum resistor size is as follows: R MlN ;50NIN , Where: = the minimum resistor size number of inputs from a common octant The maximum allowed NIN is 10. RMIN NIN = The Maximum NIN value will degrade V IL noise margin by 250 mY. NINis determined by input location and is therefore design dependent. An octant is a group of IIO's that share a common ESD bus. As the name implies, there are 8 octants per chip, as shown in Figure 3. Figure 3: Octants on a FX Vltesse Ole Page 628 8 VlTESSE Semiconductor Corporation Application Note 22 Interfacing Vitesse +3.3V TTL with +5V CMOS Power dissipated across a single resistor can be calculated using the following equation: P Where: VOH = (VOH- (V:m.+ 1»2R, = the CMOS output high voltage The maximum frequency of an input signal will now depend on the RC time constant where R is Rmin and C is the total capacitance of the package, pad and input buffer. The fewer CMOS driven inputs on a shared com- mon ESD bus, the lower the resistance and the higher the frequency of operation. The maximum frequency can be approximated as follows: Max Freq 1/(27rRC) = Note: This solution is not applicable to bidirectional TTL JlO's. Solution #2 Bus Switch A second recommended solution is to limit the VOH (max) as seen at the TTL input as shown in Figure 4. This approach uses a 3384 chip, available from either Pericom or Quality Semiconductor, which is placed in series with the +5V CMOS output and the +3.3V Vitesse TTL input. This chip has a 10-bit interface, so 10 TTL inputs can be serviced by a single 3384 part. The part is available in a 24 pin DIP, surface mount SOIC or 1/4 size surface mount QSOP with a cost of $1 to $2 depending on quantity and package selection. FIgure 4: Bus SWItch +5V DIODE PI5C3384A 24 Vi/esse 3.3V Circuits Voo I-B ~R r 5V CMOS Circuits BE-WA +'------' R: To maintain a constSllt vo/tllgtl drop of the diode. e VlTESSE 1996 Communications Product Data Book Page 629 Application .Note 22 Interfacing Vitesse +3.3V TTL with +SVCMOS When this part is used to convert from 5V to 3V logic, it consumes almost no power. However; in addition to the 3384 part, this solution requires a diode and a resistor. The diode is required to drop the supply voltage from +5V to 4.2V. The resistor creates a constant voltage drop across the diode. This diode and resistor can be shared between a number of 3384 chips. As shown in the graph in Figure 5, the output signal is limited to 3.2V max which will not cause any problem to the 3.3V TTL circuit. For more information about this part, contact: Quality Semiconductor 851 Martin Avenue Santa Clara, CA 95050 (408) 450-8000 FAX: 496-0773 Pericom Semiconductor Corporation 2380 Bering Drive San Jose, CA 95131 (408) 435-0800 FAX: 435-1100 Agure 5: Input and Output Signals of 3384 at Vee 5.0 I 4.0 !. 3.0 \ utS;gnal \ / 2.0 1.0 \ Input ignal OUI \ / V o =4.2V I' 3.0 9.0 6.0 12.0 15.0 Time (ns) Conclusion The current limiting resistor is simple and inexpensive, however this solution may limit the maximum frequency of the interface. The bus switch is a more elegant solution dissipating little power and able to handle frequencies over 100 MHz. However, the bus switch is more costly at $1 to $2 dollars per bus switch chip (which can service up to 10 inputs) and requires two extra components, a resistor and a diode. Table 1: Bus SWitch Power and Cost Power' Cost -10mW -4mW $0.05 - $0.10 $1.00 - $2.00 Note: 1) For 10 TILInputs Page 630 @VITESSE Semiconductor Corporation VITESSE Application Note 24 Information Sources for Fibre Channel The interest level in Fibre Channel has been running very high. This application note summarizes sources of information about Fibre Channel which can be readily accessed by the public. Fibre Channel is being developed by the ANSI X3T11 Technical Committee with Roger Cummings as the chairman. Formal distribution of Fibre Channel Specification is handled by Global Engineering. An industry trade association to promote Fibre Channel was formed called the Fibre Channel Association. Additionally, a substantial amount of information is available through internet. The listing below summarizes some of the more interesting locations for information. ANSIX3Tll Roger Cummings, Chairman Storage Technology 2270 South 88th Street Louisville, CO 80028-0268 Ph: 303-673-6357 Fx: 303-673-8196 roger3ummings@stortek.com ANSI Documents Global Engineering Ph: 800-854-7179 Fibre Channel Association Jeff Silva, Chairman Fibre Channel Association 12407 MoPac Expressway North 100-357 P.O. Box 9700 Austin, TX 78758 Ph: 5121301-2402 World Wide Web http://www.amdahl.comiextlCARPIFCAlFCAhtml http://www.cern.chlHSIIfcs/fca.htm http://www-atp.llnl.gov/atp/telecom.html ANSI X3T11 Minutes anonymous ftp ftp_site nsco.network.com filename X3T11/minutesldatemin.txt or datemin.ps FC-AL Working Document anonymous ftp ftp_site nsco.network.com filename FCIAUfcal44p.listps ® VlTESSE 1996 Communications Product Data Book Page 631 Application Note 24 Information Sources for Fibre Channel FC.AL Direct Disk Attach Profile ftp_site filename FCSI Documents anonymous ftp ftp.symbios.com pub/standardS/io/fc/profiles/prv_160.ps anonymous ftp playground.sun.com /pubIFCSI login: anonymous password: internet_sign-on to-Bit Interface Specification ftp_site Page 632 anonymous ftp fission.dt. wdc.com directory /home/fissionC/ftp/pub/standards/l Obitlframe directory /home/fissionC/ftp/pub/standards/lObitlpostscript @VlTESSE Semiconductor Corporation VITESSE Application Note 25 Measuring Eye Diagrams on the VSC7105 Transmitter This Application Note describes how Vitesse Semiconductor measures the Data Eye on the VSC7105 fuIlspeed Fibre Channel Transmitter. It includes details of how to generate the data, input data "Jitter", the output Data Eye and the Data Eye at the end of a 60', 50 ohm Coaxial cable. A block diagram of the test setup is shown in Figure #1. In this measurement, an HP 70845A BERT Pattern Generator is used to generate an internaVexternal clock at 1.0625 GHz and a Data pattern of '0000011111' generates a 106.25 MHz output which is used as the REFCLK input to the VSC7105. The VSC71 05 is on a Device Under Test board (DUT) which allows 20 bits of data to be selected through DIP switches which were set to an arbitrary pattern. The Digital Storage Oscilloscope is triggered with the 1.0625 GHz clock from the BERT and the Data Eye is using in relation to this clock. The inputs to the VSC71 05 are very clean. The Data Bus is static and the REFCLK from the BERT has only 5.2ps RMS 140 ps peak-to-peakjitter when measured against the 1.0625 GHz clock (See Figure #2). The resultant data eye from the VSC7105 is shown in Figure #3. This was measured with a short 2' 50 ohm coaxial cable (RG-142U) and has jitter of only 21.5 ps RMS /120 ps pk-pk. The rectangular box in these figures shows the sampling area for the histograms which are shown at the bottom of the scope trace. The data eye was also measured with a 60' coax cable between the VSC7105 DUTboard and the attenuatorinput to the scope. The amplitude and jitter have increased due to the losses in the cable but a very acceptable signal is still available which shows 38.8 ps RMS 1244 ps pk-pkjitter. The Fibre Channel FC-PH document calis for the use of a fourth-order, low-pass Bessel-Thompson filter when measuring Data Eyes but Vitesse has chosen not to use this filter since it would lower the measured jitter. Measuring Data Eye patterns is one of several methods used to determine how signal integrity varies with cable distance and quality. Additional testing is required to better understand these dependencies in order to determine maximum cable distances for Fibre Channel solutions. Eye Diagram Test Setup 1.0625 GHz Clock I------~;.:;.;.....;.;;...::--------_I~ Trigger HP7084SA Pattern Generator ThktroDics 11801A Digital SampUng OsciHoscope = Clock 1.0625GHz Data = 0000011111 Data 106.25 MHz REFCLK 2O-bit Data ---~~ Data VSC7105 TX+---~ 50 Ohm 'ftansmitter * SertekAttenuator l04H-20dB DC-4.0GHz ® V1TESSE 1996 Communications Product Data Book Page 633 Application Note 25 Measuring Eye Diagrams on the VSC7105 Transmitter Figure 1: Data Eye of BERT Data t. ~: :: t~{~ ~ .~) t~ r ~i ll:t~L ·~:.:-:::{1~·:'.. ~~ f.:i n;:.~;· H. ::, (.; ri.::-.:{;r·~·. ~f.~·.i:.:;:·"! '''.~~ :::~:··"f.:lff.i····:~:-~ ~.~::--::o:::: ~ ~~::::::}:::~~: ."l, 'f•..., ...................'................................'.:....................:............................................:.................................... ·.:h) , i:r;:::'i:::;.; rr;:,:~~::;······~:r.:r~r~;:\y ~~'it ~~: ~.··t t ~ .• , -I. o,oy........... ..· )~:li::::V :lJ '.' ? ::~i f~ ::;: .~:.::;~ f.....~~ 8f,lr;~j~~>" ~~ Y« t ~ ;pv ~ ,,:.<'. Page 634 ® VlTESSE Semiconductor Corporation Application Note 25 Figure 2: Measuring Eye Diagrams on the VSC7105 Transmitter VSC71 05 Data Eye, 2' Coax Cable lla0lA nrGIT"'t Sf\MPl.JN6 OSCILLOSCOPE 2B-'FEIll"!35 ~ ll'ltl: ~ 1 :24:33 date~ • @ • • • . . •••• • •• < ••• • ••••••• ~ . . ••• ~ . . . . . . . . . . . . . . . VlTESSE 1996 Communications Product Data Book Page 635 Application Note 25 Measuring Eye Diagrams on the VSC7105 Transmitter Figure 3: Page 636 VSC7105 Data Eye, 60' Coax Cable ® VlTESSE Semiconductor Corporation VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano Camarillo, CA. 93012 Phone: (805) 388-3700 FAX: (805) 987-5896
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