1996_WSI_PSD_Applications_Handbook_Volume_2 1996 WSI PSD Applications Handbook Volume 2

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PSD
Programmable MCU Peripherals
PSD Applications Handbook
Volume2of2

1996
LORI STEINTHAL

12 INCORPORATED
MANUFACTURERS REPRESENTATIVES

3255 Scott Boulevard
Suite 1-102
Santa Clara, CA 95054-3013
Tel: (408) 988-3400
Fax: (408) 988-2079

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PSD
Programmable MCU Peripherals
PSD Applications Handbook
Volume2of2

1996

Copyright © 1996 WajerScale Integration, Inc.
(All rights reserved.)
47280 Kato Road, Fremont, California 94538
Tel: 510-656-5400 Facsimile: 510-657-5916
Printed in U. S. A.
on recycled paper.

-------------------------------------~~Jr-------------------------------------

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-

PSD3XX Family

Table Df CDntents
PSD ApplicatiDn NDtes

Application Note 011

PSD3XX Device Description ......................................................... 1-1

Application Note 013

The PSD301 Streamlines a Microcontroller-Based
Smart Transmitter Design ........................................................... 1-55

Application Note 014

Using the PSD3XX PAD for System Logic Replacement... ......... 1-67

Application Note 015

Using Memory Paging with the PSD3XX .................................... 1-81

Application Note 016

Power Considerations in the PSD3XX ........................................ 1-95

Application Note 017

Track Mode Implementation of PSD3XX ................................... 1-111

Application Note 018

Security of Design in the PSD3XX ............................................ 1-121

Application Note 019

The PSD311 Simplifies an Eight Wire Cable
Tester Design and Increases Flexibility in the Process ............. 1-125

Application Note 020

Benefits of 16-Bit Design with PSD3XX .................................... 1-145

Application Note 021

Interfacing The PSD3XX To The MC68HC16
and The MC68300 Family of Microcontrollers .......................... 1-157

Application Note 022

Using WSI's PSD3XX Programmable
Microcontroller Peripheral Family
with 80C31/80C51 Microcontrollers .......................................... 1-167

Application Note 023

PSD3XX Family - Programmable Microcontroller
Peripheral Design Tutorial ......................................................... 1-179

Application Note 024

Using the PSD311 with a High-Speed
ADSP-2105 DSP .......................................................................1-191

Application Note 025

Interfacing The PSD3XX To The NEURON@
3150™ CHIP ..............................................................................1-201

Application Note 026

PSD3XX Device Fit for PC Notebook Applications:
Keyboard, Power Management and Auxiliary
Peripherals Control ...................................................................1-221

Application Note 027

Simplification of Logic Networks in the
PSD3XX PAD Using DeMorgan's Theorem .............................. 1-227

Application Note 032

Use a ROM Emulator for Rapid Software Debug
of a PSD3XX-Based Design ..................................................... 1-237

Application Note 040

Three-Chip Feature Phone ........................................................ 1-251

Application Note 041

Detailed Step-By-Step Design Implementation
of an M68HC11 and PSD311 or PSD311R ................................. 1-269

iii

Table of Contents - PSD Application NotllS

ZI'SD3XX Family

Application Note 034

ZPSD Power Consumption Calculations .......................................2-1

I'SD4XX/5XX
Family

Application Note 028

PSD5XX CounterfTimers Operation ..............................................3-1

Application Note 029

Interfacing PSD4XXl5XX To Microcontroliers .............................3-73

Application Note 030

PSD4XXl5XX Power Calculations and Reduction .................... 3-145

Application Note 031

PSD4XXl5XX Design Tutorial ...................................................3-161

Application Note 033

Keypad Interface to PSD4XX15XX
with Autoscanning .....................................................................3-245

Application 035

How To Design With The PSD4XXl5XX ZPLD ........................... 3-257

Application 036

How To Fit Your Design Into The PSD4XX15XX ......................... 3-265

Application 037

How to Implement a Latch Function in Port A
of PSD4XXl5XX that is Independent of the System Clock .......... 3-271

Application 038

How to Increase the Speed of the
PSD5XX Counter/Timers ...........................................................3-277

Application 039

Encoder for Shaft Direction and Position Recognition
Using the PSD5XX.....................................................................3-287

Application 042

Four Axis Stepper Motor Control
Using a Programmable PSD5XX
MCU Peripheral from WSI, Inc...................................................3-297

Motorola
Application
Notes

The following are Motorola Application Notes and known as Application Notes 043 and 044
at WSI, Inc.
Application Note 043

Using M68HC11 Microcontrollers
with WSI Programmable Peripheral Devices ................................4-1

Application Note 044

High Performance M68HC11 System Design
Using The WSI PSD4XX and PSD5XX Families ..........................4-9

iv

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~

s

.

__________________________________

w

Sales
Representatives
and Distributors ....................................................................................................................................................5-1

':;';;1.

__________________________________

Table of Contents - PSD Application Notes

PSD3XX
Family

Refer to PSD Products Data Book, Volume 1 of 2, for the Data Sheets listed below.
Field-Programmable Microcontrolier Peripherals .................................................................2-1

ZPSD3XX
Family

Field-Programmable Microcontrolier Peripherals .................................................................3-1

PSD4XX
Family

Field-Programmable Microcontrolier Peripherals ................................................................ .4-1

ZPSD4XX
Family

Field-Programmable Microcontrolier Peripherals .................................................................5-1

PSD5XX
Family

Field-Programmable Microcontrolier Peripherals .................................................................6-1

ZPSD5XX
Family

Field-Programmable Microcontroller Peripherals ................................................................. 7-1

PSD
Development
Systems and
Accessories

PSDsoft ................................................................................................................................8-1
PSD-Gold and PSD-Silver Development Systems ..............................................................8-5
WS6000 MagicPro@ III Memory and Programmable
Peripheral Programmer ........................................................................................................8-7
Electronic Bulietin Board ....................................................................................................8-11

Masked-PSD
Ordering
Information

MPSD Mask-Programmable PSD Ordering Information ...................................................... 9-1

----------------------------------~~~---------------------------------

v

Table of Contents - PSD Application Notes

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iF====~
--r..-.....
-------_

-~

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-.-.~

PSD3XX Family

ZPSD3XX Family

PSD4XX/5XX Family

Motorola Application Notes

Sales Representatives
and Distributors

Section Index
PSD3XX Family

Application Note 011

PSD3XX Device Description ......................................................... 1-1

Application Note 013

The PSD301 Streamlines a Microcontroller-Based
Smart Transmitter Design ........................................................... 1-55

Application Note 014

Using the PSD3XX PAD for System Logic Replacement... ......... 1-67

Application Note 015

Using Memory Paging with the PSD3XX .................................... 1-81

Application Note 016

Power Considerations in the PSD3XX ........................................ 1-95

Application Note 017

Track Mode Implementation of PSD3XX ................................... 1-111

Application Note 018

Security of Design in the PSD3XX ............................................ 1-121

Application Note 019

The PSD311 Simplifies an Eight Wire Cable
Tester Design and Increases Flexibility in the Process ............. 1-125

Application Note 020

Benefits of 16-Bit Design with PSD3XX .................................... 1-145

Application Note 021

Interfacing The PSD3XX To The MC68HC16
and The MC68300 Family of Microcontrollers .......................... 1-157

Application Note 022

Using WSI's PSD3XX Programmable
Microcontroller Peripheral Family
with 80C31/80C51 Microcontrollers .......................................... 1-167

Application Note 023

PSD3XX Family - Programmable Microcontroller
Peripheral Design Tutorial ......................................................... 1-179

Application Note 024

Using the PSD311 with a High-Speed
ADSP-2105 DSP .......................................................................1-191

Application Note 025

Interfacing The PSD3XX To The NEURON®
3150™ CHIP ..............................................................................1-201

Application Note 026

PSD3XX Device Fit for PC Notebook Applications:
Keyboard, Power Management and Auxiliary
Peripherals Control ................................................................... 1-221

Application Note 027

Simplification of Logic Networks in the
PSD3XX PAD Using DeMorgan's Theorem .............................. 1-227

Application Note 032

Use a ROM Emulator for Rapid Software Debug
of a PSD3XX-Based Design ..................................................... 1-237

Application Note 040

Three-Chip Feature Phone ........................................................ 1-251

Application Note 041

Detailed Step-By-Step DeSign Implementation
of an M68HC11 and PSD311 or PSD311R ................................. 1-269

For additional information,
Call BOO-TEAM-WSI (BOO-B32-6914).
In California, Call BOO-562-6363

===:==
--...., .....
_-, .............

-------=== ...
~-'

I/!IIII

Programmable Peripheral
Application Note 011
PSD3XX Device Description

Contents

Chapter 1: PSD301 Dellice Description
Introduction ........................................................................................................................1-3
WSI Software Support for the PSD Family ........................................................................ 1-4
PSD3XX Architecture and Pin Nomenclature ................................................................... 1-4
Performance Characteristics ............................................................................................. 1-6
PSD3XX System Configuration for Port and I/O Options .................................................. 1-6
Address Inputs ..................................................................................................................1-8
PSD3XX Programmable Array Decoder (PAD) ................................................................. 1-9
Microcontrolier/Microprocessor Control Inputs ................................................................ 1-1 0
Input and Output Ports .....................................................................................................1-11
PSD3XX General System Configuration ......................................................................... 1-13
PSD3XX Configuration for Port Reconstruction .............................................................. 1-15

Chapter 2: Applications
8-Bit Microcontrolier to PSD3XX Interface ...................................................................... 1-17
Two PSD3XX Byte·Wide Interfaces to Intel 80C31 ......................................................... 1-19
PSD3XX M68HC11 Byte-Wide Interface .........................................................................1-21
8-Bit Non-Multiplexed PSD3XX Interface to M68008 ...................................................... 1-23
16-Bit Non-Multiplexed Address/Data PSD3XX Interface to M68000 ............................. 1-25
M68000/2X PSD3XX Applications ..................................................................................1-27
16-Bit Address/Data PSD3XX Interface to Intel 80186 ................................................... 1-29
16-Bit Address/Data PSD3XX to Intel 80196 Interface ................................................... 1-31
Interfacing the PSD3XX to 8-Bit Microprocessors Z80 and M6809 Applications ............ 1-33
PSD3XX Interface to the Intel 80286 .............................................................................. 1-36
External Peripherals to the PSD3XXlM68HC11 Configuration ........................................ 1-38
Additional External SRAM ............................................................................................... 1-40
PD3XX Used in Track Mode ............................................................................................1-44

Chapter 3: Software Support
Summary .........................................................................................................................1-53

Figures

Figure 1. PSD3XX Supports CPU as a Complete Peripheral,
Memory, and Logic Subsystem ........................................................................1-3
Figure 2. PSD3XX Architecture .......................................................................................1-5
Figure 3. 8-Bit Multiplexed Address/Data Mode .............................................................. 1-7
Figure 4. 16-Bit Multiplexed Address/Data Mode ............................................................ 1-7
Figure 5. Non·Multiplexed Mode 8-Bit Data Bus .............................................................1-7
Figure 6. Non-Multiplexed Mode 16-Bit Data Bus ........................................................... 1-8
Figure 7. PSD3XX Programmable Array Decoder...........................................................1-9
Figure 8. PSD3XX Port A Structure ...............................................................................1-11
Figure 9. PSD3XX Port B Structure ...............................................................................1-12

1-1

I'SD3XX - AppllcatlDn ND" 011

Figures
(Cont.)

Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.

InteI80C31/PSD3XX Applications ................................................................ 1-18
InteI80C31/21PSD3XX Applications ............................................................. 1-20
M68HC11/PSD3XX Applications ................................................................... 1-22
M68008/PSD3XX Applications .....................................................................1-24
M68000/PSD3XX Applications .....................................................................1-26
M68000/2X PSD3XX Applications ................................................................ 1-28
Intel 80186/PSD3XX Applications ................................................................. 1-30
Intel 80196/PSD3XX Applications Open-Drain Drivers ................................. 1-32
Z80/PSD3XX Applications ............................................................................1-34
6809/PSD3XX Applications ..........................................................................1-35
Inte180286/PSD3XX Applications .................................................................1-37
M68HC11/PSD3XX to M68230 Applications .................................................1-39
M68HC11/PSD3XX to 16K SRAM Applications ............................................1-41
SC80C4511PSD3XX to 16K SRAM Applications ..........................................1-43
Intel 80196/PSD3XX Track Mode to External SRAM .................................... 1-45
MAPLE Main Menu .......................................................................................1-47
MAPLE Menu with PARTNAME Submenu ...................................................1-48
CONFIGURATION Menu ..............................................................................1-49
Port C Configuration Menu ...........................................................................1-50
Port A Configuration Menu, Part 1 ................................................................1-50
Port A Configuration Menu, Part 2 ................................................................1-51
Port B Configuration Menu ............................................................................1-51
Address MAP Menu ......................................................................................1-52
Port B Configuration Menu with Address Map ..............................................1-53

Tables

Table 1.
Table 2.
Table 3.
Table 4.

Port Base Address Offset ..............................................................................1-10
Non-Volatile Configuration Bits .....................................................................1-14
Small Controller System with One 80C31 and One PSD3XX ....................... 1-17
80C31 Interface to Two PSD3XX Devices with Power
Economy Feature ..........................................................................................1-19
M68HC11 to PSD3XX Interface ....................................................................1-21
M68008 to PSD3XX Interface .......................................................................1-23
M68000 Microprocessor to One PSD3XX Interface ..................................... 1-25
M68000 Microprocessor to Two PSD3XX Devices in Parallel ...................... 1-27
Intel 80196 to PSD3XX Configuration for CMOS Ports ................................ 1-29
Intel 80196 to PSD3XX Configuration for LED Drivers ................................. 1-31
Z80B to PSD3XX Interface ...........................................................................1-33
M6809 to PSD3XX Interface .........................................................................1-33
Intel 80286 to PSD3XX Interface .................................................................. 1-36
M68HC11/PSD3XX to External Peripheral M68230 Interface ...................... 1-38
M68HC11/PSD3XX Configured to Address Additional SRAM ...................... 1-40
SC80C451/PSD3XX Configured to Address Additional SRAM .................... 1-42
Intel 80196 to PSD3XX Used to Access External SRAM
in Track Mode ...............................................................................................1-44

Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.

~----------------

1-2

_________

rll'~

'fIN!i1 it

___________________________

Programmable Peripheral
Application Note 011
PSD3XX Device Description
Chapter 1
Introduction

The PSD3XX family of products include
flexible 110 ports, PLD, Page Register,
256K to 1M EPROM, 16K bit SRAM and
"Glueless" Logic Interface to the micro
controller. The PSD3XX is ideal for
microcontroller based applications where
fast time-to-market, small form factor and
low power consumption are essential.
These applications include disk controllers,
cellular phones, modems, fax machines,
medical instrumentation, industrial control,
automotive engine control and many others.
Traditionally, central processing units (CPUs)
require the support of non-volatile memory for
program storage, random access memory
(RAM) for data storage, and some Inputl
output (110) capability to communicate with
external devices. The addition of general
logic circuitry is necessary to 'glue' the parts
of the system together. Figure 1 shows a

Figure 1.
PSD3XX supports
CPU as a Complete peripheral,
memory, and
logic subsystem

block diagram of such a system, configured
with a CPU (or microprocessor). The typical
microprocessor also has Integrated Into it onboard timers, a small amount of RAM and
ROM, as well as a limited 110 capability.
The microprocessor (and often the microcontroller) requires additional external support
EPROM and RAM memory, additional ports,
memory mapping logic, and sometimes
latches to separate address and data from a
multiplexed addressldata bus. Until very
recently, designers had to create a discrete
solution from a number of chips, or generate
a full custom solution. Now, the PSD3XX
integrates the different system support blocks
into a single-chip solution. This relieves the
designer from the constraint of thinking that
memory mapping, ports, and address latch
requirements should be developed from
separate elements.

CENTRAL PROCESSING UNIT

CPU

DECODED
OUTPUTS

INPUT/OUTPUT PORTS

-----------------------------------~Jr~~----------------------------------1--3

PSD3XX - Application 1I0te 011

Introduction
(Cont.)

This high integration of functionality into a
single chip enables designers to reduce the
overall chip count of the system. The result is
increased system reliability, simpler PCB
layout, and lower inventory and assembly
costs. By integrating ports, latches, a Programmable Address Decoder (PAD),
EPROM, and static RAM, the PSD3XX can
bring the system solution down to only two
chips: a microcontroller and a PSD3XX. The
alternative solution would be discrete elements of RAM, EPROM, 1/0 mapped ports,
and latches all mapped into the address
scheme by a programmable logic device
(PLD). This could escalate the chip count to
8-12 packages, depending on size and
complexity.

For larger systems, multiple PSD3XX 's can be
configured. Due to its versatility and flexibility, two or more PSDs can be cascaded either
horizontally (increasing bus width) or vertically
(increasing sub-system depth). This proportionally increases the complement of memory;
I/O ports, and chip-selects without the need
for additional external glue logic.

WSI Software
Support for the
PSDFamily

The PSD family from WSI can be easily
configured from a low-cost software support
package called MAPLE. Designed to run in
an IBM/PC environment, MAPLE makes
design and configuration of the PSD3XX a

simple task. Memory mapping of EPROM
and RAM blocks replaces PLD-like equations
with user-friendly, high-level command
entries.
'

PSD3XX
Architecture and
Pin Nomenclature

The PSD3XX is available in a variety of 44-pin
packages (see the PSD3XX Data Sheet).
Figure 2 is a functional block diagram of the

PSD3XX that shows the pin functions, internal
architecture, and bus structure.

An additional feature of the PSD3XX is its
ability to support a wide range of microcontrollers or microprocessors because it has
been designed with a wide range of configurable options. The designer can program any
one of a number of different options to create
specific compatibility with a host processor.
Furthermore, this can be done without the
need for external glue logic.

-----------------------------------~~~----------------------------------1·4

PSD3XX - Application Note 011

Figure 2.
PS03XX
Architecture.

PAGE LOGIC

~lJ=
--

. - - A11-A15
L
A
T
C
H

AD8-AD15

A16-A18

~

AB-A1O
A19
CSI

PADA

ALE/AS

ALE/AS

LOGIC IN

PAD B

ALE/AS

RD

.--

~!

CSIOPORT
A19
CSI
RD

WR
RESET

WR
RESET

13 PT

---

27 PT

-

PROG
PORT
EXP
PCOPORT
C

~

CSa-CS10

----

'-L
A
T
C
H

A DO-AD7
~~

I'"

I-- 1 -

'---

I ES1

e

.--

~~~

-

~

CSOCS7

..-16/8

~

'---

..--

~ I-~

EPROM
256 K BIT·1 M BIT

ES7
ES6
ES5
ES4
ES3
ES2

1-

.-I"'~

--

'---

11e>

r

D8-D15

'--

-

-+

32K·128K BIT
BLOCK

PROG
PORT
EXP
PBDPORT
B

~

CSIOPORT

DO-D7

~

SRAM
16K BIT
TRACK MODE
SELECTS

AD-A7
ADO-AD7/DO-D7

PROG
PORT
EXP
PAOPORT
A

~

ALE/AS
RO/E

PROG CHIP
CONFIGURATION

t

WR/R/W
BHE/PSEN
RESET

PROG
CONTROL
SIGNALS

SECURITY
LOGIC

X8, X16
MUX or NON-MUX BUSSES

A19/CSI

-----------------------------------------~~~----------------------------------------1·5

PSD3XX - Application Note 011

PSD3XX
Architecture and
Pin Nomenclature
(Cont.)

Inputs ADO-AD15 enter the PSD through
latches. These can be programmed to latch
the address/data inputs, removing the need
for such devices as the 74HCT373 or 573.
Alternatively, in the transparent mode they
simply buffer address inputs. The Address
Latch Enable (ALE) signal is available to
register a valid address input on the
ADO-AD15 lines; its active polarity is programmable. Another name for this input is
Address Strobe (AS). It provides the same
function and the same timing as the ALE, but
this pin name is more appropriate to Motorola-type systems. When either ALE or AS is
valid, the latches are transparent; when
inactive, the address/data inputs on
ADO-AD15 remain latched.
The PSD3XX also contains a Programmable
Address Decoder (PAD). Figure 2 shows that
address inputs A 11-A 15 (and, possibly,
inputs A 16-A 19) go directly to the PAD.
Other inputs to the PAD include RD(E), WR
(R/W), and ALE(AS). Programming of the
PAD enables the designer to internally select
the EPROM banks via internal chip-select
lines ESO-ES7. An additional chip-select for
the internal SRAM is available through RSO.
Port C conveys either CS8-CS 10 to external

devices or receives A 16-A 18 inputs, directing
them to the PAD. Also, A 19 can be programmed to go directly into the PAD. Note
that these lines are not necessarily dedicated
to address inputs; they can be used as
general purpose logic inputs. Thus, the PAD
can be programmed to perform general
combinational logic without adding any 'glue
logic' to the overall system design. Address
inputs A 16-A 19 can be used as general
inputs to the PAD for implementing logic
equations, and not for address decoding. If
they are not used, A 16-A 19 are "don't care"
conditions in memory map allocation. (See
Figure 7 for a more detailed diagram of the
PAD.)
The internal port options (Ports A and B) are
both 8 bit-wide and can be programmed to act
as traditional I/O ports. Port C IS a 3-blt port
designed to output logic functions from the
PAD, receive address inputs A16-A18, or a
combination of both. Ports A and B, however,
are more complex because a number of
different options can be selected with regard
to system configuration. Figures 3, 4, 5, and
6 show the variety of configurations that are
available to these ports.

Performance
Characteristics

Two key timing parameters associated with
the device are the EPROM/SRAM access
times and the propagation delay through
the PAD. The worst-case delay from valid
address input to valid data output is 120 ns
whether the address input is multiplexed or
not. The cycle time of the system is virtually
120 ns with a small margin for address
switching. This gives a system clock rate of

about 8.3 MHz. Considering the powerdown option, it takes 100 ns for active
power input enabled through the CSI to
valid data output. If the chip-select output
option is chosen for either Port B or Port C,
the propagation delay for address and
control input through the PAD to valid chipselect output is 35 ns.

PSD3XX System
Configuration for
Port and I/O
Options

In this section, the EPROM and SRAM are
treated as separate entities and the four
options available for configuring the PSD301
in a processor system are detailed. Figure 3
shows an 8-bit data configuration for systems
that multiplex 8-bits of data (00-07) with the
corresponding address inputs (AO-A7). Lines
A8-A 15 are dedicated to higher-order address inputs. Ports A and B are then available for data I/O and Port C is available for
additional inputs, A 16-A 18 or chip-select
outputs CS8-CS1 O. Port A also has the
option of passing anyone or all of the internally latched lower-order addresses (AO-A7)
to the output. Another mode supported by

Port A is called "track mode." In this mode,
the PSD301 can be programmed to pass the
I/Os ADO-AD7 through the device enabling a
shared memory or peripheral resource to be
accessed. Port B has an additional mode to
the general port mode. The PSD301 's onchip PAD can be programmed to generate
chip-select signals which can be routed to
Port B's output for external chip selection as
CSO-CS7. Port C can be programmed for
inputs A 16-A 18 or as additional chip-select
outputs CS8-CS1 O. Although labeled as
address inputs, A 16-A 18 can be used for
general Boolean Inputs to the PAD array.

_____________________________________ ~AfAf~~------------------------------------1-6

1:IIII"'':8'=:

::=

PSD3XX - ApplicatiDn NDte 011

Figure3.
8-bit multiplexed
address/data
mode

PORTA
A8 - A15

ALE

PORTB

ADO-AD7

PORTC

I
I
I

(1/0) or [AO - A7) or [ADO - AD7)

(1/0) or [CSO - CS7)

240203

Figure 4 extends the option offered in Figure
3 to a 16-bit multiplexed bus. A08-A015
convey address and data I/O. The port
options remain the same as for Figure 3; thus,

Figure 4.
16-bit multiplexed
address/data
mode.

AD8- AD15

PORTA

ALE
PORTB

ADO-AD7
PORTC

these two configurations are suitable for
multiplexed address/data systems of 8 or 16
bits.

I

I
I

(1/0) or [CSO - CS7]

240204

Figures 5 and 6 show options for a nonmultiplexed host processor or controller.
Figure 5 is suited to byte-wide systems and
Figure 6 to 16-bit word-wide configurations.
In Figure 5, Port A is used for data 00-07 but

Figure 5.
Non-multiplexed
Mode 8-bit Data
Bus

AS - A15

AO-A7

ALE
Becomes general
purpose input

Port B is still available for general I/O operations or chip-select outputs. This configuration is suitable for processors such as the
M68008.

PORTA

I

PORTB

I

PORTC

I

DO- D7

(1/0) or [CSO - CS7)

A16,A17,A18 or CS8,CS9,CS10

240205

-------------------------------------~jr~~------------------------------------1·7

I'SII8XX - AppI/t:atItJn IIIIIB 011

Figure 6.
Mon-multiplexed
Mode Iii-bit Data
Bus

PORTA

PORTB

ALE

PORTe

Becomes general

I
I
I

00-07

08- 015

purpose Input
240206

Address Inputs

The function of Port C is the same in all of the
four modes of operation. For 16-bit data
transfers, an additional 8 bits of data is
required. Figure 6 shows Port B as the data
bus for the higher-order data byte 08-015.

With 00-07, this configuration is suitable for
16-bit microprocessors such as the M68000.
Port C is available for address inputs or chipselect outputs.

The processor interface has 16 address
'inputs: AOO-A015. The device can be
programmed to accept either address inputs
or multiplexed address/data inputs. The
address lines can be latched into the one or
two octal latches for multiplexed byte or wordwide buses respectively. The device is
initially programmed with a word configuration
setting the PSD3XX to a specific mode; for
example, one configuration bit selects
whether the address input is multiplexed with
data or is a non-multiplexed dedicated
address. In the non-multiplexed scheme, the
input latches are held as transparent. When
the address inputs are valid on the chip as
AO-A 15, they can be subdivided into two
buses: as lower-order addresses (A 1-A11),
and as higher-order addresses (A 12-A15).
A1-A11 go directly to the EPROM and inputs
A1-A10 go to the SRAM (see Figure 2). The
EPROM blocks are selected through the PAD
via outputs ESO-ES7 as shown in Figure 2;
and the SRAM is selected by the RSO output.
The address input lines A11-A15, along with
possible additional address inputs A16-A19,
go into the PAD array. These address inputs
are available for mapping the blocks of
memory into the map scheme of the system.
One option is to program the additional
address inputs as valid higher-order address
inputs for memory addressing ranges above
64K bytes or 32K words. If A16-A18 are not
required, these PAD inputs can be ignored.
Only microprocessors and microcontrollers
with a large addressing range use these
higher-order address lines. A second option
is to disregard these address inputs to the

chip in favor of additional chip-select outputs.
A third option is available if the designer does
not need additional chip-select outputs or
high-order address inputs. The inputs
A16-A18 can be used as general-purpose
logic inputs. Examples of this are illustrated
in some of the following applications.
An interface with the Z80B microprocessor
uses inputs A16, A17, and A18 for signals
Mf, ti.4REQ, and lORQ, respectively. In the
M68008 application, two of these pins are
programmed as OTACK and BERR from the
PS0301 to the M68008. A wired-OR function
can be implemented on the OTACK or BERR
input if the user takes advantage of Port B's
open-drain feature. If two PSD3XX devices
are used together, the OTACK and BERR
lines can be wired together and the external
pull-up resistors can be used to tie these lines
HIGH. It is also possible to use the internal
PAD of one PSD3XX to gate these lines
together and produce composite ofACK and
i3ERR inputs to the M68008.
Internally, the memory blocks are arranged
word-wide with a byte-wide isolation buffer
separating the lower and upper bytes. This
buffer is controlled from the configuration
section of the PSD3XX. When the PSD3XX is
configured to operate in word-wide mode, this
buffer isolates the two buses into 00-07 and
08-015. In word-wide mode, the control of
the data flow through this buffer is determined
by BHE, AO, and the device's current configuration mode. Accessing byte-wide data can
be thought of as accessing bytes on even and
odd word boundaries or as two separate

------------------I1Jr;-----------------1-8

PSD3XX - ApplicatiDn NDte 011

Address Inputs
(Cont.)

banks of byte-wide data. The total complement of EPROM is shown as eight
banks. The chip-select outputs ESO-ES7
come from the PAD. These are program-

mabie address and control decode signals
from the PAD inputs. Figure 7 provides a
detailed schematic diagram of the PAD in
terms of a traditional PLD.

PSD3XX

The PAD is an EPROM-based reprogrammabie logic fuse array with sum-of-product
outputs. Fer Intel-type configurations, inputs
to the PAD are A11-A19, ALE, RD, and WR.
For Motorola type configurations, they are
R/W, AS, and E. The CSI and RESET inputs
are used to deselect the PAD for power-down
configurations and initialization, respectively.
Internal to the PSD301 are the ESO-ES7

EPROM select lines. There is one product
term dedicated to each EPROM block,
and a single product term (RSO) for the
SRAM selection. Address and control for
each EPROM bank can programmed to a
resolution of a 4K word boundary and positioned anywhere in the mapping scheme of
the designer's system. Similarly, the SRAM
can be positioned on 2K word boundaries.

Programmable
Array Decoder
(PAD)

Figure 7.

PSD3XX
Programmable
Array Decoder

~
~
P,

I

Esa
ES1
ES2

~

'S
V

~
.~

Po
V
ALEorAS

8 EPROM BLOCK
SELECT LINES

PAD
A

ES5
ESS

.~

'S
V

DarE

ES3
ES4

"'!S

-y
~

ES7
RSa-S RAM BLOCK SELECT

'S
~

orR!W

""'"
A1S

eSIOPORT eSADIN
eSADOUT1
eSADOUT2

~

'S

}

I/O BASE ADDRESS
TRACK MODE
CONTROL SIGNALS

~

esa/PBa
A1S

"'S

----

A17

""'S
A1S

-v

""'S

~

A1S

""'S

-y
A14

~

~

---------

eS1/PB1

eS2IPB2

eS3/PB3

eS4/PB4

""'S
eS5/PB5
A13

""'S
-~

A12

PAD
B

~

-v

eSS/PBS

'S
eS7/PB7

A11

""'S

.eSI

...

ess/pca
ess/pC1

iiEsET

CS1a/pC2

-------------------------------------fAfAfjF~------------------------------------e=.,.

PSD3XX - Application Note 011

PSD3XX
Programmable
Array Decoder
(PAD)
(Cont.)

Table 1.
Port Base Address
Offset

Microcontroller/
Microprocessor
Control Inputs

Other internal product term outputs from the
PAD are the CSIOPORT, CSADIN, CSADOUT1 , and CSADOUT2 lines. A single
product term generates the CSIOPORT
signal; this provides a base address for Ports
A and B. The registers relevant to these ports
are addressed as a base offset (see Table 1).
The CSADIN signal is used to control the
input buffer in the track mode. It can be
enabled to read data in a programmed
address space from Port A through the

PSD3XX. CSADOUT1-2 are used to control
the multiplexed address and write data
through the PSD3XX to the Port A pads. The
address range is programmed into the PAD
qualifying the address space, but CSADOUT1
is qualified by the ALE signal outside of the
PAD. This automatically lets the design
distinguish between address and write data.
To qualify valid write data, the PSD3XX
automatically includes the CSADOUT2
product term with the WR or R/W signal.

Register Name

Offset From The CSIOPORT Base Address

Pin Register of Port A

+2 (Accessible only during Read)

Pin Register of Port B

+3 (Accessible only during Read)

Direction Register Port A

+4

Direction Register Port B

+5

Data Register Port A

+6

Data Register Port B

+7

Pin Register of Ports A and B

+2 (Accessible only during Read)

Direction Register of Ports A and B

+4

Data Register of Ports A and B

+6

Byte Wide

Word Wide

The PAD structure enables additional chipselects to be routed to the Port B output pins.
The four chip-select outputs (CSO-CS3) are
supported by four product terms per output.
CS4-CS7 have two product terms per output.
The ability to use more than one product term
from a chip-select enables the mapping of
additional devices to be distributed through
the address space, rather than selecting
memory as a block. Sacrificing Port B
terminals for chip-selects could occur in
systems requiring a larger EPROM, RAM, or

1/0 space. Additional PSD3XX devices can
be designed into a system by using the chipselect outputs from Port C or B of one master
PSD3XX. This is required for addressing a
space greater than 1M. Finally, the outputs of
the sum-of-product terms are inverted to be
consistent with active LOW chip-select inputs
for additional external RAM, EPROM, peripherals, or busses. Port C has the capability of
providing three additional external chipselects, each supporting one product term per
output.

The control inputs are also programmable:
WR or R/W and RD or E are used for readl
write control of the internal EPROM, RAM,
and 1/0 capability. Other control inputs are a
programmable option for Bus High Enable or
Program Store Enable (BHE/PSEN) and
Address Latch Enable or Address Strobe
(ALE/AS). These pins are selected to suit the
bus protocol of the host processor or, where
not applicable, they can be ignored. The CSII
A 19 input is available either for a power-down
chip-select enable or as a higher-order
address input without the power-down
feature. The final control input is the RESET
input; this also is a programmable option. Its
active polarity can be chosen to be compat-

ible with the host system. The function of the
RESET input is to clear and initialize the
PSD301 at start-up. All II0s are set up as
inputs and all outputs are either in a nonactive or three-state condition.

ii'~=

;;::=

--------------------------------;1·10
====

Consequently, the PSD3XX is prevented from
actively driving outputs during start-up. This
feature was incorporated to prevent potential
bus conflicts. In Figure 2, the CSI and
RESET inputs are shown also as PAD inputs.
CSI is a hardwire option into the PAD that
powers down the internal circuitry and is
used in power-sensitive applications. Neither
signal is available as a programmable option.

--------------------------------

PS03XX - Application Note 011

FigureS.
PS03XX Port A
Structure

A1 A2 WR RD CSIOPORT

READ

PIN

MUX
APORTDI

PORT
AlPIN

ADi

Ai

OUTPUT
ENABLE

MULTIPLEX
SELECT
OPTION

READ DIRECTION
REGISTER

Ht---+-----ICONFIGURATION

PORTA STRUCTURE
ANY ONE OF i 0 TO 7

=

ADO - AD7

Input and Output
Ports

ALE

RESET

The port section comprises Port A (8 bits),
Port B (8 bits), and Port C (3 bits). These
support the many different 1/0 operations.
For port expansion, Ports A and B can be
configured as general 1/0 ports, each to

240208

convey eight bits of digital data to and from an
external device. Figure 8 shows a single cell
of Port A, Figure 9 shows a single cell of
Port B.

----------------------------------~~aF~---------------------------------1-11

PSD3XX - Applit:l1lion 110,. 011

FigureS.
PS03XX Port B
Structure

A1 A2WR RD CSIOPORT
CSO-CS7

READ

PIN

PORT
BIPIN

OUTPUT

ENABlE

READ DlREC'nON

REGISTER

CONFIGURATION

PORTS STRUCTURE
ANY ONE OF I = 0 TO 7

RESET

Writing data to a port is similar to writing data
to a RAM location. If a PQrt is programmed as
an output, data is loaded into the output
register as if it were a RAM location. Although the ports are not bit addressable,
individual bits can be selected as either input
or output. Thus, PAO-5 can be set as data
outputs while PA6 and PA7 can be configured
as inputs. Any mix of I/0s is possible giving
the ports additional flexibility.
The diiection of data flow through the port is

240209

determined by the data direction register.
This register is dynamically programmable so
that the 1/0 direction through Ports A and B
can be altered during the microcontroller
program execution. The data direction
register Initializes with logiC zeros after an
active RESET and causes each port bit to be
set as an input. This state of initialization
guarantees that the ports are prevented from
driving the output lines at start-up. If the user
requires all the Port A or Port B bits to be

-,·-,2---------------:....FUJ!!iE
;,,~ -----------'------

PSDaXX - Application Note 011

Input and Output
Ports (Cont.)

I/O control signals to the PAD through the
A 16-A 18 inputs and program an active
CSIOPORT output by decoding these signals.
This can be achieved with Intel- and Zilogtype processors which have separate memory
Due to the internal design: it is possible to
and I/O controls. Signal input through pins
program Port A or Port B bit lines as inputs
A 16-A 18 is made possible through Port C.
and still write data to the port locations. This
This 3-bit port is responsible for either PAD
is because both ports have on-chip latches
chip-select outputs or address/logic inputs.
and can hold data. These registers are
CSIOPORT points to a base address at which
hidden or buried; i.e., they exist in the port
Ports A and B reside. Table 1 provides the
and their condition can be read back at any
offset from the base address and the associtime. However, these outputs do not drive the
output pins because the port has been
' ated port function. Figure 2 shows that Port A
is driven by a multiplexed address/data bus of
enabled as an input.
ADO-AD? and the selection of address/data
To access the port as a memory mapped
is made from the configuration memory and
location, the initial selection is made through
internal control functions.
the PAD's CSIOPORT. This provides a base
The other options available to the user are
address from which the locations shown in
selecting 1) the shared resource or track
Table 1 give access to the various ports or
mode where ADO-AD? is routed directly
their options. The configuration support
through to the Port A output, or 2) the latched
software automatically ensures that there is
address AD-A? In track mode, ADO-AD?
no conflict between an SRAM location and I/O
inputs to the PSD3XX are used to access
port in the case of memory mapped peripherlocal or private memory and peripherals and
als. It is also possible for the PSD3XX to
the outputs ADO-AD? through Port A are
distinguish between I/O and memory mapped
used to access a public resource.
locations. The user can input memory and

PS03XX General
System Configuration

The PSD3XX family devices consists of two
byte-wide configurable I/O ports (Ports A
and B), 256K to 1M bits of EPROM, 16K
bits of RAM, and the PAD. Additional I/O
capability to and from the PAD is through a
3-bit I/O (Port C). There are also on-chip
latches to support processors and
controllers that multiplex address and
data on the same bus. The EPROM memory
section of the device is programmable just
like a standard EPROM device. However,
unlike the single-chip EPROM, the PSD3XX
must also be configured to function into one
of its many possible modes of operation: This
is done by programming a non-volatile
EPROM memory location with 45 configuration bits. These bits select the mode of
operation and are programmed into the
EPROM along with the hexadecimal microprocessor/microcontroller assembly language
object code. When using MAPLE software,

inputs, the data direction register can be left
in this default state. To enable it as an
output, logic ones can be written into the data
direction location.

the assignment of logic conditions to the
configuration bits locations is transparent to
the user; the resultant word is merged with
the EPROM code and the data map for the
PAD.
Table 2 shows the the configuration locations
and their functional assignment. For example, one of the configuration bits enables
the device architecture to be compatible for
either byte- or word-wide data buses. This is
the configuration data or CDATA bit. The 256
Kbits of EPROM can be configured as a 32K
byte-wide bus for applications with an 8031
microcontroller or as a 16K word-wide bus for
applications with an M68000 microprocessor.
These configuration bits are discussed in
detail as each feature is covered in this
application note.

------------------------------~~Jr~-----------------------------1-13

PSD3XX - Application Note 011

Table 2.
Non-volatile
Configuration
Bits

Configuration
Bits
Number of Bits

Function

o = eight bits, 1 = sixteen bits

CDATA

1

CDATA.

CAD DRAT

1

ADDRESS/DATA Multiplexed. 0
1 = Multiplexed

= Non-multiplexed,

= RD and WR, 1 = R/Wand E
= Enable power-down, 1 = Enable A 19
ALE Polanty. 0 = Active HIGH,1 = Active LOW
CRESET. 0 = Active LOW RESET, 1 = Active HIGH RESET

CRRWR

1

CRRWR. 0

CA19/CSI

1

A 19 or CSI. 0

CALE

1

CRESET

1

COMB/SEP

1

Combined or Separate Address Space for SRAM and
EPROM. 0 = Combined, 1 = Separate

CPAF2

1

Port A Track Mode or Port Mode. 0
1 = ADO-AD? Track Mode

CPAF1

8

Port A I/O or AO-A? 0 = Port A pin is I/O,
1 = Port A pin is Address

CPBF

8

Port B I/O or CS. 0 = Port B pins are CSi (i
1 = Port B pins are I/O

CPCF

3

Port C A 16-A 18 or CS8-CS 10. 0 = Port C pins are
Address, 1 = Port C pins are Chip-select

CPACOD

8

Port A CMOS or Open Drain.
1 = Open Drain

o = CMOS drivers,

CPBCOD

8

Port B CMOS or Open Drain.
1 = Open Drain

o = CMOS Drivers,

CADDHLT

1

CSECURITY

1

= Port or Address,

A 16-A 18 Transparent or Latched. 1

o = Address transparent
CSECURITY On/Off. 0

In addition to bus width, the polarity and mode
of the bus control signals are programmable.
There are two types of read/write control: one
is consistent with either a Motorola and Texas
Instruments control bus standard; the other is
consistent with the Intel/National Semiconductor/Zilog control bus standard. The
configure read and write bit (CRRWR),
distinguishes between one of two conventions: either an Intel (8031) or Motorola
(M68HC11) convention can be selected by
programming this single bit in the configuration memory. The Intel device requires the
PSD3XX to be programmed with an active
LOW RD and WR controls (CRRWR = 0).
For applications with the Motorola microprocessor, select the R/W and E option (CRRWR
= 1). In addition to a choice of two READ/
WRITE controls, the user can select either a
multiplexed AddresslData Bus or separate
address and data lines.
Figure 3 shows the configuration that is best
suited for the 8031 microcontrolier; Figure 4
shows the configuration for an 80196 microcontrolier with a 16-bit multiplexed addressed/
data bus. For the non-multiplexed modes:

= 0-7),

= Address latched,

= Off, 1 = On

Figure 5 applies to M6809 microprocessors,
while Figure 6 shows the mode applicable to
the M68000. Selection of multiplexed or nonmultiplexed buses is a programmable option
that can be invoked through the configure
address/data multiplex (CAD DRAT) bit. With
the 8031 controller, address outputs AO-A?
are multiplexed with the data DO-D? input!
output lines to create a composite ADO-AD?
bus.
The PSD3XX's input latches can be programmed to catch a valid address when the
microcontrolier's ALE signal transitions from
active HIGH to inactive LOW. The polarity of
the ALE signal is also a programmable
feature in the CALE field of the configuration
table. Address latching can be programmed
to occur on either an active HIGH or an active
LOW ALE signal. With Intel devices, the address is valid when ALE is HIGH. Once
latched, data or code can be read from, or
written to, the PSD3XX. The CALE active
HIGH or LOW ALE configuration bit only
applies to addresses AO-A 15. A separate
configuration bit, (CADDHLT), exists for the
control of the higher-order address inputs

--------------------------------f===~-------------------------------;:::
1·14

="~=='

I'SIJ3XX - Application IIDte 01 1

PSD3XX General
System Configuration (Cont.)

(A16-A19). If necessary, these addresses
can also be latched by the host system.
The highest address input is A19 but this
signal can be omitted in favor of a powerdown chip-select input (cSI). A19/CSI is
selected by the CA 19/CSI configuration bit.
When the CSI input is selected and the pin is
driven HIGH, the device can be powereddown consuming only standby power. When
configured with other CMOS devices, the
standby power is in the 80-250 IJA range.
Many CMOS microcontrollers do not need a
large memory address space; thus, address
inputs A16-A19 would be unnecessary. The
CA 19/CSI input can be programmed with a
logic LOW to enable a power-down option for
power sensitive applications.
The address/data multiplexed scheme also
supports the 16-bit processors. In this case,
ADO-AD15 convey a 16-bit address qualified
by ALE (or AS for the Motorola convention)
and 16-bits of data I/O. This feature is shown
in Figure 4. A microcontroller that would use
this scheme is the 80C196. The M68HC11,
like the 8031, uses the 8-bit multiplexed
scheme but with the Motorola convention for
bus control.
Another control pin used for 80C31 applications used to distinguish between program

PSD3XX
Configuration

tor Port
Reconstruction

A key feature of the PSD3XX is the concept of
port reconstruction. When using microcontrollers with additional off-chip memory, port
1/0 address lines are sacrificed for address,
data, and memory control lines. With a
multiplexed address/data scheme, two 8-bit
controller ports could be lost to address and
data. Furthermore, in some control applications, many port 1/0 bits are required to send
actuating Signals to solenoids, instrument
displays, etc., and receive data through
sensors and switch panels. In many control
environments, a large amount of 1/0 capability
is required; also, additional external memory
is needed for microcontroller instructions to
perform data manipulation. Without the
PSD3XX , the supplement of extra ports as
discrete latches addressed through logic
decoders can add a number of chips to the
final design. By using the PSD3XX, additional
EPROM, RAM, and ports are all provided on
one Chip. Port reconstruction lets the designer reclaim the two ports sacrificed for the
microcontroller's address and data.
Port configuration is achieved through the
configuration register bits. CPAF1 configura-

and data memory is the PSEN output. The
COMB/SEP configuration bit should be
programmed HIGH if data and memory are
separate and LOW to configure a combined
memory space in the PSD3XX. This is a
useful feature for systems that require program memory and data memory to be in
separate blocks.
For systems that use separate data and
address buses, the address latches can be
set into a transparent mode by clearing the
CADDRDAT bit location. Thus, the PSD3XX
is suitable for multiplexed or non-multiplexed
bus structures employing 8- or 16-bit bus
widths.
The RESET input to the PSD3XX enables the
device to be initialized at start-up. RESET
can be either active HIGH or active LOW
depending on the processor type. The
CRESET configuration bit selects the polarity
of the RESET input: LOW for active LOW and
HIGH for active HIGH RESET. Normally,
memory systems do not require a RESET
input; however, the PSD3XX contains data
direction registers for the ports that must be
initialized at start-up. Note that all port 1/0
buffers are automatically programmed as
inputs during start-up.

tion of Port A contains eight bits; programming a logic LOW assigns the selected bit
with I/O capability as if it were a conventional
port. If programmed HIGH, the internally
latched address inputs AO-A? are routed to
Port A lines PAO-PA? This feature enables
other on-card peripherals to use AO-A? as
latched addresses. Without this feature,
external peripherals to the PSD3XX would
require an external octal latch to catch the
multiplexed address when it becomes valid at
the microcontroller's output. Configuration of
Port A as general 110 or addressldata is on a
bit-wise basis; thus, the choice of port or
addressldata assignment can be mixed. For
example, configuration code 111 OOOOOB
programmed into location CPAF1 passes
addresses AO-A2 to outputs PAO-PA2 and
enables PA3-PA? as conventional port lines.
Configuration bit CPAF2 is a 1-bit location.
When programmed LOW, it selects the port!
address option, as described above. If
CPAF2 is programmed HIGH, port bits
PAO-PA? are set into track mode. Activity on
the PAO-PA? outputs follow logic transitions
on inputs ADO-AD? The multiplexed ad-

-------------------------------------~~~------------------------------------.~
1-15

PSD3XX - Application Note 011

PSD3XX
Configuration
for Port
Reconstruction
(Cont.)

dress/ data input is tracked through
PAO-PA7. Track mode enables the host
microcontroller to access a shared memory
and peripheral resource through the PSD3XX
while maintaining the ability to access its own
(private) memory/peripheral resource directly
from the microcontroller's address/data
outputs. In this mode, the address/data
ADO-AD7 passes through the PSD3XX logically unaltered. In summary, PAO-PA7 can
be programmed as port I/O or latched address outputs AO-A7 (each bit being programmed on an individual basis), or as
ADO-AD7 outputs (track mode).
Port B bits PBO-PB7 can be programmed
either as regular port I/Os, or as chip-select
outputs CSO-CS7 encoded from the PAD
outputs. Figure 7 shows the PAD structure as
a conventional PLD. Eight bits are programmed into CPBF. Logic LOW indicates that
a port pin is a chip-select output derived from
the PAD. Programming a logic HIGH sets the
appropriate pin as an I/O function. The bit
pattern 11111 OOOB programmed into the
CPBF location sets up PBO-PB4 as I/O ports
and PB5-PB7 as chip-selects. The typical
applications, where Port B is programmed as
bi-directional, would be with microcontroller
chips that need additional port bits. This
would be in applications where port reconstruction is needed to drive many indicators,

_____________________________________
1-16

rar~~~

="~=:=

solenoids, read switches, sensors, etc. In
large microprocessor-based systems, the
chip-select option would probably be chosen;
in this case, the PAD outputs select other
PSD devices, DRAM memory chips, and
peripherals such as timers, UARTs, etc.
The three bits comprising Port C can be
programmed by the CPCF configuration bits.
This group of three bits define whether Port C
is used for inputs (typically A 16-A is) or
whether the pins are used as chip-select
outputs from the PAD. Although labeled as
A 16-A is, the nomenclature of these pins
does not constrain the designer to using
these inputs as dedicated higher-order
address inputs. In fact, they can be generalpurpose inputs to the PAD for processors that
do not have an address capability above 64K
locations. When the PSD3XX is used with the
ZSOB microprocessor, the Port C inputs have
been programmed as MREQ, 10RO, and Mi.
In the case of an interface to the M6S09B, two
inputs of Port C have been converted to chipselect outputs for other memory devices and
one output has been used to feedback a
READY input to the M6S09B. Port C can be
used as a general I/O from the PAD in the
form of address, control, and chip-select bits.
A logic LOW programs a port bit as an input;
a HIGH programs it as an output.

_____________________________________

Programmable Peripheral
Application Note 011
Applications
Chapter 2
a-Bit Microcontroller to PSD3XX
• __ ....

.III"II'III:e

Table3.
Small CDntroller
System with One
8OC31 and One
I'SD3XX

Figure 10 illustrates the minimum configuration?f o.ne ~ontroller and one PSD3X~. The
application Illustrates port reconstruction
through the device's Port A and Port B 110,
reconstituting port 2 and port 0 of the microcontroller. Table 3 gives the configuration
information that would be programmed in the
configuration section of the PSD. Table 3
shows that both port II0s have been programmed with CMOS load and drive characteristics. A feature of the 8051/8031 family is
the PSEN signal, which determines whether
the memory selection is active for executable

Configuration

Bits

code or data. This family of controllers has
separate memory locations for code and data .
To maintain full compatibility, the PSD3XX is
also capable of being programmed to respond
to the PSEN signal. When A 16-A18 are
programmed as inputs but not driven, they
should be tied active HIGH or LOW. Unused
inputs to the PSD3XX must not be permitted
to float. Tying can be avoided on unused
A 16-A 18 lines if these are programmed as
'dummy' CS8-CS 10 outputs. A 19/CSI cannot
be programmed as an output; thus, it must be
tied if not used.

Function

CDATA

0

8-bit data bus

CADDRDAT

1

Multiplexed addressldata

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set CSI input power-down mode

CALE

0

Active HIGH ALE

CRESET

1

Active HIGH RESET

COMB/SEP

1

Code and data memory separate

CPAF2

0

Input/Output Port A

CPAF1

OOH

Input/Output Port A (0-7)

CPBF

FFH

Input/Output Port B

CPCF

OOOB

Port C programmed for inputs

CPACOD

OOH

Configure CMOS outputs Port A

CPBCOD

OOH

CADDHLT

0

Transparent inputs A 16-A 19

CSECURITY

0

No security

Configure CMOS outputs Port B

_____________________ r••

______________________

~,=

tINIlA

1.17

~I~
ca'
;::
ir -.di

~
'!.

~I

!:~;;

ia

I
I

::1' t
I:
~
f

I!:i
...

1
I

X1

~

129HI--Z

~C2
20pF

Ii'III,.

T

:::":::C3
20pF

U1
GND

31
19

'---------=-1

'"Illii

' -________---'1,,8'--l

am

PO.o~:

~~

X1

PO.1
PO.2

37
36

~g:~

35

X2

9

RST
-RST
DS1232

I------,--------------------"'--j
NTO
INT1
TO
T1
P1.0

12

~~

15

>+

INTO
INT1
TO
T1
P1.0

5
6

~

~

P1.4
P1.5
P1.6
P1.7

8OC31

__________________,

~6

25
26

ADO/AO
AD1/A1
AD2IA2

PAO
PA1
PA2

27

~g~~~

~~~

17

32

30

AD5IA5
AD6IA6
AD7/A7

PA5
PA6
PA7

14

21
22

31
32

23

33

26

37

P27

27
28

38
39

RD
WR
PSEN
ALEtP

17
16
29
30

22
2
1
13

PO.5
PO.6
PO.7

RESET

~~:~~
~;:~
P1.3
4
P1.3
P1.4
P1.5
P1.6
P1.7

~U~2~

EA/VP

P2.0
P2.1
P22

~~

~~

P2:3~:

P2.4

~~:~

~~

TXD~
RXD

_

I

l.£!2ill>--'

~

AD8IA8
AD9/A9
AD10/A10
AD11/A11
AD12/A12

PBO
PB1
PB2
PB3
PB4

~g~~~;~

~~~

AD15/A15

PB7

AD
WRNPP
BHEIPSEN
ALE
RESET

PSD3XX

A161CS8
A17/CS9
A18/CS10
A19/CSI

19
18

~~

11
10

~
PA1
PA2

~~~

~
~

<.J:£>
~
~

<..J:!ll.>

9

~

6

PB4

~

5
4

~40.
41
42
43
GND

V~

~~~

~

PS03XX - Application Note 011

TwoPSD3XX
Byte-Wide
Interfaces to the
Intel BOC31

Table 4.
BOC31 Interface
to Two PSD3XX
Devices with
Power Economy
Feature

Figure 11 illustrates an extension to the
previous design in that two PSD3XX devices
have been used, doubling the memory and
port resources of the system solution. In this
application, the power-down capability has
been used so that one PSD3XX can be active
while the other device is in power-down
mode. The mean power consumption is
reduced, so this configuration can be considered for power-sensitive applications.

Configuration

Bits

The configuration Table 4 indicates that Port
C has been configured as outputs. Provided
one PSD3XX is powered up for the whole
address range, its PAD can decode an
address range to select and deselect the
second PSD3XX device through the CS 10
output. In Figure 11, the PAD output A 18/
CS10 on PSD3XX U2 can be used to powerdown the second PSD3XX through the A 19/
CSI input.

Function

CDATA

0

8-bit data bus

CADDRDAT

1

Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set CSI input power-down mode

CALE

0

Active HIGH ALE

CRESET

1

Active HIGH RESET

COMB/SEP

1

Code and data memory separate
Input/Output Port A

CPAF2

0

CPAF1

OOH

CPBF

FFH

Input/Output Port B

CPCF

111 B

Outputs CS8-CS1 0

Input/Output Port A (0-7)

CPACOD

OOH

Configure CMOS outputs Port A

CPBCOD

OOH

Configure CMOS outputs Port B

CADDHLT

X

"Don't care" for latched A 16-A19

CSECURITY

0

No security

It is not recommended that the two PSD3XX
devices select each other because the PAD
section of a PSD device is powered down
with the rest of the device. At least one PAD

decoder must be kept active to select and
deselect others. Port C outputs CS16-CS18
can power-down as many as three other
PSD3XX devices.

-----------------------------------~~~~----------------------------------1-19

...

~I::!!

....

I

IS

tIi'

'aQ'I
;:; ;
aiSj .....
S' ;J :"4

~

c::.

~

~
I

I

II

I!!
...

X1

I~~H~
..l
C;'
T
20pF

---L-

Cs
20PP

U1

EAlvP

~II
II

18

~QI
.... In

Xl
X2

P03
P04
PO 5

9

... Ib

U3
PO 0
PO 1
P02

ADO/AO
AD1/Al
AD2IA2
AD3/A3

AD4/A4
AD5/A5
AD6/A6

POS
P07

AD7/A7

RESET

21
22
23
24
25
26
27
28

P20
P21
P22
P23
P24
P25
P26
P27
RD
WR
PSEN
ALE/P
TXD
RXD

31
32
33
35
36
37
38
39

AD8/A8
AD9/A9
ADl O/A1 0
AD11/A11

AD12/A12
ADl31A13
AD14/A14

AD15/A15
RD
WRNPP
BHEIPSEN
ALE
RESET

ADO/AO
AD1/A1
AD2IA2
AD3IA3
AD4/A4
AD5/AS
AD6IA6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD8IA8
AD9/A9
AD10/Al0
AD111A11
ADl21A12
AD131A13
AD141A14
AD151A15

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

A161CS8
A17/CS9
A181CS10
A19/CSI

40
41
42
43
GND

PSD3XX

I

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

RXD::

~

R8T
R8T
D81232

PCOO
peOl

RD
WRNPP
BHEIPSEN
ALE
RESET

PSD3XX

A16/CS8
A17/CS9
A181CS10
A19/CSI

40
41

PC10
PC11

PSlJ3XX - Applit:atlDn lID", Ott

PSD3XX M68HC11

Byte-Wide
Interface

Table 5.
M68HC11 to
l'Soaxx Interface

Figure 12 illustrates the configuration of an
M68HC11 microcontroller which also uses the
8-bits wide multiplexed address/data bus.
The application is similar to that given in
Figures 6 and 7 except that the RiW and E
control lines have been invoked to establish
compatibility with the Motorola device. The
address strobe output from the M68HC11 is
HIGH so the AS(ALE) input is set HIGH. The
SRAM and EPROM section are programmed
as combined and both Ports A and Bare
enabled as I/Os with CMOS drives. Port C is
programmed with chip-select outputs
CS8-CS10. Other PSD3XX devices can be
mapped into the addressing scheme or the
lines can be programmed to transition as
strobes in defined mapping areas. The latch
enable bit for the higher-order address lines
A 16-A19 is not used establishing a don't care
condition. The CADDHLT condition must be
selected if anyone of A 16-A19 lines is
selected as input to the PSD.

Configuration

Bits

In this design, the security bit is programmed.
This bit prevents the reading of the PAD
configuration by an unauthorized user.
Furthermore, if the security bit has been
programmed, standard programming machines can not read the internal code of a
PSD3XX. However, data can always be read
from the EPROM, RAM, and ports. This
provides normal use of the device. If the
address map in the PAD cannot be interpreted, the actual location of data within the
address and I/O space is difficult to determine. Besides programming the CSECURITY bit, added security can be applied by
scrambling the sequence of address and data
inputs. A short PASCAL or 'C' program can
be written to reorganize the original Intel MCS
code to be aligned with the scrambled pins.
Table 5 indicates the configuration for the
M68HC11/ PSD3XX interface.

Function

CDATA

0

CADDRDAT

1

Multiplexed address/data

CRRWR

1

Set R/Vii and E mode

CA19/CSI

0

Enable CSI input

CALE

0

Active HIGH AS (ALE)

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

8-bit data bus

Input/Output Port A

CPAF1

0
OOH

CPBF

FFH

Input/Output Port B

CPCF

111B

Output CS8-CS 10

CPACOD

OOH

CMOS drivers

CPBCOD

OOH

CMOS dnvers

CADDHLT

X

"Don't care" A16-A19 not used

CSECURITY

1

Security on

Input/Output Port A

..

-----------------------------------,= =~~----------------------------------=
1-21

~I:!!
~~;

~I

'15 ;.:~

i~~~
=:i

;,:

a
~,

lIoo

I'

!c;'

~

:::0

~w

i-

~
Ii

......
Q

J_

G~_

1-

18pF

U1

U2

XTAL

pca

XTAL

PC1
PC2
pr;3
PC4
PC5
PC6
PC7

PDO
PD1
PD2
PD3
PD4
PD5

18pF

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

III"''''·
IIIIII
IIIIIIII

Qhll!!1
11111 ""

E

R/W

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

Vee

~ ~~
~~

AS
RESET
XIRQ
'RO

±

GND

23
24
25
26
27
28
29
30

16
17
18
19
20
21
22
23

31
32
33
35
36
37
38
39

5
6

22
2

4
17

~

~gg~ I

I

1-----,:===:===:l5IT:::j.1 ~=~

8
9
10
11
12
13
14
15

~ ~

68HC11
vee

~

U3
2

I

AD2/A2
AD3/A3

AD4/A4
AD5/AS
AD6/A6
A07/A7

ADS/AS

V DD
RESET

~~

GND

MC34064

R1
4K7

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

AD9/AS
AD10/A1Q

AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

R/Wivpp,
BHE/PSEN
AS
RESET

3

~
~
~
~
~
~
~
~
~

~
r--+
~
r-+
~

~
~

A17/CS9

~
r--ll

A18/CS10
A19/CSI

~
~

A16/CS8

E

,-----&-

t:rc

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD1/A1

GND

PSD3XX
Vee

~

18pl-_-_ __

vee

ADO/AO

R1
4K7

~

R1
4K7

~

R1
4K7

PS03XX - Application Note 011

B-BIT Non-Multiplexed PS03XX
Interface to
M6BOOB

Figure 13 illustrates an application in which
the address and data are not multiplexed.
The M68008 has an 8-bit data bus and 20-bit
address bus. The PSD3XX can be programmed to support the microprocessor by
providing data I/O through Port A. The
address lines from the microprocessor go to
inputs AO-A 19. Port B outputs are used for
external chip-selects to other MAP devices or
other memory resources. The configuration
has been set for compatibility with Motorola
control signals. There are six chip-select
outputs (CSO-CS5) and an address decode
for DTACK and BERR. The PAD decodes an
address range which is fed back to the
microprocessor through these inputs. USing
the open-drain configuration has been implemented in Port B bits 6 and? The two pullup resistors enable external memory and
peripherals to access the DTACK and BERR
inputs as a wired-OR function.

needed to avoid possible bus contention on
these lines. In this application, ALE(AS) can
be used as a general-purpose logic input to
the PAD because the function of ALE becomes redundant in a non-multiplexed
address/data bus. Also shown in Figure 13 is
a method of inverting the active LOW OS
(Data Strobe) M68008 output. The A19 input
is enabled to the PSD internal PAD and
inverted at the output of CS1 0 to drive the
PSD3XX E input. The E input must be active
HIGH but OS is active LOW and qualifies a
valid data transfer. Thus, the PAD must
perform a signal Inversion. The E signal
output from the M68008 is used to interface to
Motorola 8-bit peripherals. However, with
Motorola microcontroller families such as the
M68HC11, the E signal output can drive the E
input to the PSD3XX. Table 6 gives the
configuration information associated with the
design given In Figure 13.

If other PSD3XX devices are mapped into the
M68008 system, no additional glue logic is

Table 6.
M68008to
PS03XX
Interface

Configuration

Bits

Function

CDATA

0

CADDRDAT

0

Non-Multiplexed address/data

CRRWR

1

Set RIW and E mode

8-bit data bus

CA19/CSI

1

Enable A19 input 1

CALE

X

"Don't care" non-multiplexed mode

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

X

"Don't care" Port A used for data

CPAF1

XXH

"Don't care" Port A used for data

CPBF

OOH

Port B used for chip-selects

CPCF

001B

Configure A16 and Ai? In, CS10 Out 2

CPACOD

OOH

CMOS drivers

CPBCOD

COH

CMOS drivers, PB6, PB? open drain

CADDHLT

0

Address latch transparent A 16-A 19

CSECURITY

1

Security on

1 The DS output from the M68008 drives the A 19 Input to the PSD3XX
2 The Internal PAD of thePSD3XX Inverts the DS Input to drive Its own E Input from the CS10 PAD output A16 and
A 17 are programmed as PSD Inputs

-----------------------------------f==~~----------------------------------iiiF!!iIiiE =
1-23

~IiIi I

~I

"!.
;:s..

sfA

I:::

~

~

t;;:
I

H
II
~
...

st

I I
Vee

Vee

R1
saOR

R2
560R

DTACK
BERR

~
.....!!E.8B.
U2

U1
CLK

I!
~

LYE&;
IPLOI2
~

f"EiR'::
'"FCli"'

~C~
~

~
E

34
39
42
41

33
31
40
45
44
43
32
38

CLK
VPA
IPLOI2
IPL1

BR
DTACK
BERR
FCO
FC1
FC2

M5
BG
E

-'

~

36

~
29
~
~

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14

HALT
RESET
AS
OS

R!W

68008

46
47
48
1
2
3
4
5
6
7
8
9
10
11
12
14
16

~

A16
A17
A18 ~
A19 ~

DO
01
02
03
04
05
06
07

~
25

~
23
~
21
~

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5IA5
AD6!A6
AD7/A7
ADBlA8
AD9/A9
AD10/A10
AD11/A11
AD121A12
AD131A13
AD14/A14
AD151A15

Vee

T,---?f1
13
3

E
RtWNPP
BHEIPSEN
AS
RESET

PSD3XX

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PBS
PBS
PB7
A1B1CSB
A17/CS9

.,~"
A19/CSI

21
20
19
18
17
16
15
14
11
10
9
8
7
6
5

--i.40
41

IT
.....$!.

Os

--cso
CS1
;>-g~
CS4
~

I'IIIIXX - Appllt:lllltln "*1111

Thlspa,e
Intentionally left blank

------------------------~~,.-----------------------'I"
1.25

PSD3XX - Application Note 011

This page
intentionally left blank

-1--a--------------------------~Jr~----------------------------

IWIXX - lfllllaIJM".,. D11

If68IJIJO/
2XPSD3XX
Applications

TableB.
M68IJIIO Microprocessor to fWo
PSD3XX Dell/C.
InParall.'

With the circuit design given in Figure 15, two
PSD3XX devices are used in a byte-wide
mode. One PSD stores the upper data byte
and one the lower data byte of a 16-bit word.
By using the devices in this way, two 6-bit
wide ports can be created in Port B of each
device. PBS and PB7 are programmed as
open-drain outputs and wired-OR giving

Configuration
CDATA
CADDRDAT
CRRWR
CA19/CST
CALE
CRESET
COMB/SEP
CPAF2
CPAF1
CPBF
CPCF
CPACOD
CPBCOD
CADDHLT
CSECURITY

Bits
0
0
1
1
X
0
0
X
XXH
FFH
111B
OOH
OOH
0
0

composite DTACK and BERR feedback
signals to the M68000. The generation of the
E signal for both PSD devices is achieved in
the same way it was in the M68008. The [OS
and ODS inputs (to U2 and U3 respectively)
are inverted by the PAD and drive the relevant E inputs. Table 8 gives the configuration
information relevant to both PSD devices.

function
8-bit data bus
Non-multiplexed address/data
Set RtW and E control inputs
Enable A19 input'
"Don't care" not used
Active LOW RESET
Combined memory mode
"Don't care" Port A used for data
"Don't care" Port A used for data
Port B used for I/O
Configure OS8-CS102
CMOS drivers
CMOS drivers
Transparent A19
No security

1. A19 input to the PS03XX's is used to rec:eive UOS and LOS from the M68000 microprocessor. These signals are
inverted by the PAD of each PS03XX and fed back to the E input of each divice.
2. CSt 0 of each PS03XX drives the inverted UOS and LOS back to E input. Port C is programmed to output csa and
CS9. Additional byte-wide peripherals can be configured to the system and selected by these signals.

..

----------------------''#II""~,.---------------------1.27

-

~~.~

~;JI;
!:~""~

~

co

Q

51

~

DTACK
U2
U1

~
IP2
~

~btlll

·".I

BGACK~

L!lli...?-

Qbllill
1
1111: \11

~~

24

'FCO-< ~~
~
~11
VMJ!" 21

~22

~

19
20
6
7

8
9

CLK

VPA
IPLO
IPL1
IPL2

BGACK
BR
DTACK

BEAR
FCO
FC1
FC2
BG
VMA
E

HALT
RESET
AS
UOS
LOS
R/W

68000

'I..

~

I'

-

[A1-A18]
R1
470R

15
~23

I

~

I!:f

Vee

rcLK>-

•

i~

A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

~
~
~
~
~
~
~

Vy

--¥-1
13
3

r-&-

I
I
I

U3

ADO/AD
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
ADS/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADS/AS
AD9/A9
AD10/A1Q
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A1S

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

21
20
19
18
17
16
15

00
01
02
03
04
05
<

14

06

07

10
9
8
7

~

R/W/VPP
SHE/PSEN
AS
RESET

P5

4

40
A16JCS8
A17/CS9 ~

E

P1
P2
P3
P4

S11

A18/CS10~

68

~

LOS

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADS/AS
AD6/A6
A07/A7

ADS/AS
AD9/A9
AD10/A1Q
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

E

R/WNPP
SHE/PSEN
AS
RESET

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CS8
A17/CS9

[00-015]

Vee

R2
470R

BERR

21
20
19
18
17
16
15
14

08
09
010
011
012
013
014
015

~

~~O
~
9

~
r-+-<::E 13::>
4
40·--~

r

PO.6

......-,=x::
~XD

p~

~

~~~WIDTH

16
6
S
7
4
11
10
8
9

RESET

ACH7/PO.7
P2.0ITXD
P2.1/RXO
P2.2/EXINT
P2.31T2CLK
P2.41T2RST
P2.S/PWM
P2.6IT2UP-DN
P2.7fT2CAPTURE

18
17

!~

42

P2.S
33
~
P2.7
,~
24
I HSI.O
25
HSI.1
26
HS2I4
27

-<
-<

HSI.O
HSI.1
HSI.2/HSO.4
HSI.3/HSO.5

::...~

'--H--------...!1.,,3--1
12

H'-----------'£2'-1
Vee

~~

~~

58
57
56
55
S4
53

25
26
27
28
29
30

P4.0/AD8;~

~~

50
49
48
47
46
45

33
35
36
37
38
39

61

22

40
41
62

2
1
13

P4.1/AD9

ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.S
ACH6/PO.6

~~

~

P3.0/ADO
P3.1/AD1
P3.21AD2
P3.3/AD3
P3.4/AD4
P3.S/ADS
P3.6/AD6
P3.7/AD7

P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.S/AD13
P4.6/AD14
P4.7/AD15
_

WR~~
WHE/BHE
ADV/ALE
INST
CLKOUT

P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7

VREF

HSO 0

ANGND
EA

HSO:,
HSO.2
HSO.3

~;

-<> INST

S9
S8
S7

-<.

~

~

>- P1 .0 -<
P1.1

>

~

~
48

~
46

~6

ADO/AO
AD1/Al
AD2IA2
AD3/A3
A04/A4
ADS/AS
ADS/AS
AD7/A7

PAD
PAl
19
PA2
18
PA3
17
PA4
16
PAS ~
PAS
14
PA7

ADS/AS
AD9/A9
AD10/A10
AD11/A11
AD121A12
AD13/A13
AD14/A14
AD15/A15
_

peo

~6

PBl
PB2
PB3
PB4
PBS
PBS
PB7

9
8
7
6
S
4

~~
BHE/PS'E'N
ALE
RESET

""">- P1.6

~

~

35

--PB4.0
PB4.1
~

PB4.3
>.PB44
PB4.S
>-PB4.6
PB4.7

~

40

~1~g~~ ~41,
A18/CS10
A19/CSI

42
43
GND

VCC

"f

PSD3XX

1

1

2
R1A
470R

-< P1.4
P1.S

28

~~

U2

1

R1B
470R
1

6

1

5

~

D1

3 R1C
470R

1

4

~

D2

4R1D
470R

3

~

D3

,. D4

~

~

~~

~

I

R1

1~

S

6
R1E
470R

~

T
GND

C3
O.01j.JF

1
2
,,. DS

~

7
R1F
470R

1
1
,. D6

~

8
R1G
470R

1
0
,,. D7

~

R1H
470R

9
,,. D8

~

I'SII3XX - Application lID,. 011

Interfacing the
PSD8XX to '-Bit
Microprocessors

ZBO and M6BD9
AppllcatlDns

Figures 18 and 19 illustrate the PSD3XX used
with 8-bit microprocessors, such as the Z80B
and M6809B. Tables 11 and 12 reflect the
configuration of each design, respectively.
The mode of operation is 8-bit data bus with a
non-multiplexed address/data input. In the
case of the Z80B, CS8-CS"fO inputs are tied
to M1, MREO, and IORO respectively. Since

Table 11.

Configuration

ZBOB to PSD8XX

CDATA

Interface

CADDRDAT
CRRWR
CA19/CSI
CALE
CRESET
COMB/SEP
CPAF2
CPAF1
CPBF
CPCF
CPACOD
CPBCOD

Bits
0
0
0
0
X
0
0
X
XXH
FFH
OOOB
OOH
OOH

the PAD can be programmed to distinguish
between memory and 110 operations, the
Z80B system has access to an 8-bit data port
Port B. With the M6809B system, CS8 is
used to respond to the MRDY input of the
microprocessor and CS9 and CS 10 are
available for external chip-select.

Function
8-bit data bus
Non-multiplexed address/data
Set RD and WR mode
CSI input
"Don't care" (not used)
Active LOW RESET
Combined memory mode
"Don't care" Port A used for data
"Don't care" Port A used for data
I/O Port B
Configure A16-A18 as inputs
CMOS drivers
CMOS drivers

CADDHLT

0

A16-A18 transparent'

CSECURITY

0

No security

1. AI6-AI8 inputs are used as Ml, MREO, and IORO inputs to the PAD from the Z808 output. Use the ALIAS
command in the support software.

Table 12.

M6BD9 to PSD8XX
Interface

Configuration
CDATA
CADDRDAT
CRRWR
CA19/CSI
CALE
CRESET
COMB/SEP
CPAF2
CPAF1
CPBF
CPCF
CPACOD
CPBCOD
CADDHLT
CSECURITY

Bits
0
0
1
0
X
0
0
X
XXH
FFH
111 B
OOH
OOH
0
0

Function
8-bit data bus
Non-multiplexed address/data
Set RIW and E mode
Enable CSI input
"Don't care" non-multiplexed mode
Active LOW RESET
Combined memory mode
"Don't care" Port A used for data
"Don't care" Port A used for data
Port B used for I/O
CS8-CS10 outputs
CMOS drivers
CMOS drivers
"Don't care"
No security

------------------------~JrJr;-----------------------,-~-3

~I:.t!
;:: caI

"Ii

*

II~ ~

I
I

t

I
Is

...

_.

U1
27
19
20
22
21

1IIii::'

ce

..~,

tI=

REFSH

~

HALT

24

~16
17

...NM!....

26

f
G

~O

C1

MREO
IORO
WR
RO

~28

WAIT
R1
10K

M1

BUSRO
BUSACK

~

25
23
6

WAIT
INT
NMI
RESET
BUSRO
BUSAK
CLK

ZSOB

-U2

AD
Ai
A2
A3
A4
AS
A6
A7
AS
A9
AiD
A11
A12
A13
A14
A15
DO
01
02
03
04
05
DB
07

30
31
32
33
34
35
36
37

23
24
25
26
27
28
29
30

38

~
~
33

39
40
1
2
3
4
5

35
36
37
38
39

14

~
~
~
~
~

T-

&
v-+-

G~O

r--L

Vee

13

ADO/AD

A01/A1
A02lA2
A03/A3
AD4/A4
A05/AS
A06lA6
A07/A7

PAD
PA1
PA2
PA3
PA4
PAS
PA6
PA7

ADS/AS
A09/A9
A010/A10
A011/A11
AD121A12
A013/A13
A0141A14
A015!A15

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

AD
iiiiR

10
P1
~
9
P2

8 -
P6
4~

A161CS8
A17/CS9

40
41

M1
MRE

A1s/C..§lll
A19/CSI

42
43

IORO

BHEtPSEN
ALE
RESET

21
20
19
18
17
16
15
14

-=;tNO

PSD3XX

~=~

"Ci ~ CS

..... SOn'~;

a~ . . .
s·
a co

:::a~

fn~

~-

ri
GND

llI.i~:

T

rRS'i"'c
NMI

-

C1
20pF
C1
20 F
P

I

+-------,
..:h- SMH
X1
~
0
T

38

EX2

37
2

RESET
NMI
HALT
IRa

AQ
A1
A2
A3
A4
A5
AS
A7
AS
A9

FIRQ

A10
A11

~

IQII""

HRQ-'S
~

40
3
4
36

DM

33

~

X1

Z

111l1li11

~11111l

u,

~~~1.

~~~

A14
A15

U~

"-

~

~!

10
11
12
13
14
15
16
17

25
26
27
2S
29
30
31
32

ADO/AD
ADlIA1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
ADS/A6
AD7/A7
ADS/AS
AD9/A9

20

36

AD1 0/A1
AD11/A11

21

37

~~

~~

~~

~~

PAQ I ~6
PA1 ~.

PA2~"

°

~g;~;~;~
AD14/A14
AD15/A15

DO~
D1

U!L..'

22

D2~'

D3
D4
D5

~

Vee

~
~

'T'

2
r&13
3

D6~

E
FiMiIVPp
BHE/PSEN
AS
RESET

34

a

35

~~!

~
8

7

r-1-

PB2

~

PB5
~
PB6 r--t-<~
PB7
PB7
A16/CSS!-:4r\0C---===-------,

A17/CS9~
A1S/CS10
A19/CSi

1---=
42 ---cs1'
~

~J..,

GND

PSD3XX

a

BA~
BS~
RtW I 32 ----..
6809B

PB1
PB2

I

D7~
E

PA3 ~"\
PA4 I-1..L.-."\
PA5 ~"
PAS ~"\
PA7 ~
~~~_ _ _ _ __
PBO ~

I
)oj
I

t

I
iii

...

~

I52
...

I'SIJ3XX - Applit:atitln IItItrI 011

PSD3XX
Interlace to the
IntelBD286

Table 13.
Intel BD286 to
PSD3XX Interlace

Figure 20 provides a schematic of the
PSD3XX interface to an 80286. The device is
configured for a 16-bit data bus in the nonmultiplexed mode. Ports A and B are converted automatically for use as a bi-directional
data path into the PSD3XX. (This was also

Configuration
CDATA
CADDRDAT
CRRWR
CA19/CSI
CALE
CRESET
COMB/SEP
CPAF2
CPAF1
CPBF
CPCF
CPACOD
CPBCOD
CADDHLT
CSECURITY

Bits

1
0
0
1
X
1
0
X
XXH
XXH
011 B
OOH
OOH
0
0

the case for the M68000 microprocessor). To
eliminate (or lessen) glue logic, CS1 and CS2
are generated from the internal PAD. This is
programmed as an address decoder. Table
13 provides configuration information relevant
to this system design.

Function
16-bit data bus
Non-multiplexed address/data
Set RD and WR control inputs
Enable A 19 input
"Don't care" non-multiplexed mode
Active HIGH RESET
Combined memory mode
"Don't care" Port A used for data
"Don't care" Port A used for data
"Don't care" Port B used for data
A16 input; CS9 and CS10 outputs
CMOS drivers
CMOS drivers
Transparent A 16-A19 input
No security

-'~-6--------------------------~~Jf----------------------------

~rJ!i;!!

;:

'I
~I-·II
I:~

15 .::i fir

I
U1

c::l ~~ul_1'71

X1

READY
CLK
RESET

X2

PCLK

4
10
12
13

EFI

If"'

ARDY

AYEN
SRDY

SYEN
SO
S1
RES

FIC

I '.

Vee

GJ.NOj

~

CEN/AEN

14

CENL

~

~~DLY

OT/R~
DEN

5

4

82288
U4

U3

READY
CLK
RESET

1111

SO
S1

T 10J.lF
GNO

16

ALE

MCE

82284

~I

IQ-J

15

LOCK
NMI
INTR

67
68
59
57
64
65
53
54
61
6
66
52

AO
A1
A2
A3
A4
A5

AS

M/'i'O'"
LOCK
NMI
INTR
HOLD

HLDA
ERROR

BUSY
PEREa
PEAC.!S.......
CODIINTA

CAP

A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

AD7/A7

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADB/AS
AD9/A9
A01Q/A1D
AD11/A11
AD12/A12
A013/A13
AD14/A14
AD15/A1S

PBO
PB1
PB2
PB3>
PB4
PB5
PB6
PB7

ADO/AD
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS

ADS/AS

RO

:'~E/PSEN
ALE
RESET

PSD3XX

...
~

80286

A1B/CS10
A19/CSI

11
10
9
8
7
6
5
4
40
41
42
43

,I

BHE
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015

A16/csa
A17/CS9

21
20
19
18
17
16
1514

CS1l
CS2l

I

I'ItI
Ii

Is

...

IWIXX - """.",." .... '111
ExfIImtII

The configuration in Figure 21 illustrates how

......vv........"

internal latch to Port A. Addresses AO-A7,
derived from a multiplexed address/data bus,
can go directly to an additional peripheral
without the need for an additional octal latch
such as the 74HC373 or 74HC573. Port A
can be used for address outputs AO-A 7 while
PBO-PB7 can be used as chip-selects. Lines
Ao-A4 of the PSD3XX drive the'RS1-RS5
register select inputs of the M68230. For the
M68HC11, the eight bits of address and data
come from its PC port PCO-PC7 (ADO-AD7)
and are latched by the AS input. Configured
in this mode, the PSD3XX can address and
map additional peripheral chips. Port A of the
PSD3XX conveys the internally latched

"-rip""" ttl tIItI the user can feed address outputs from the
r~,.,--., I

eo",l""",.",

,.1.,4.

M6IIIIC11/I'IIIIXX
ttl ExfIJIuI
1'tIrIp. .

M6II28II
IIIfrItftIt:e

Contll,ratloll

Bill

CDATA
CADDRDAT
CRRWR
CA19/esi
CALE
CRESET

0
1
1
0
0
0
0
0
FFH
OOH
111B
OOH
OOH

~SEP

CPAF2
CPAFl
CPBF
CPCF
CPACOD
CPBCOD
CADDHLT
CSECURITY

X
0

address outputs Ao-A7 to the output and can
be used to address registers in the peripheral
chips while Port B outputs can place individual peripherals at peripheral or memorymapped boundaries. Thus, a number of
additional chips can be sblected through Port
B. This effectively can increase the port
density of the system design. The general 110
capability can then be extended to extra
ports, timers, UARTs, serial communications
channels, keyboard interface devices, CRT
controllers, etc. without the need for additional
glue logic. Table 14 highlights the configuration information programmed into the PSD3XX
when configuring the M68HCll to a M68230
peripheral.

FUllctloll
8-bit data bus
Multiplexed address/data
Set RIW and E mode
Set power·down mode
Active HIGH AS
Active LOW RESET
Combined memory mode
Port A =address Ao-A7
Port A set for address
Port B set for chip-select
Port C set for chip-select
CMOS buffers
CMOS buffers
"Don't care"
No security

-------------------------------------11'/--------------------------1-31
.."..

~ S'II:~
I::

~:=III

;:: Ii~

It
~

Ci1

"-~

I'*l~-

a
~

U2

XTAL

PCO
PC1
PC2
PC3
PC4
PC5
PC6
PC7

XTAL
POO
P01
P02
P03
P04
P05

~:!~

PE1
PE2
PE3
PE4
PE5
PE6
PE7

....

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PEO
PE1
PE2
PE3
PE4
PE5
PE6
PE7

~o

47
49
44
46
48
50

E
RtW

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

---P§

R4
1K

/I

16
17
18
19
20
21
22
23

31
32
33
35
36
37
38
39

5
6

v¥c

4
17

MOOB~

I

22
2
1
13
3

U3
21
PAO
20
PA1
19
PA2
18
PA3
17
PA4
PA5
PA6
PA7 ~

ADO/AD
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/AS

25
26
27
28
29

-i%--J+-

ADS/AS
A07/A7

A08/A8
AD9/A9

11

CSO

PSO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

-L

A16/CS8
A17/C$9

--*--1L

AD1 Q/A1 0

A011/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15
E
"RtWIVPP
BHE/PSEN
AS
RESET

AO
A1
A2
A3
A4

~

-+-4-+-+4-

--*" I

r*&
~
r-¥~
;r2-46

43
41
39

RS1
RS2
RS3
RS4
RS5

oo
01
02
03
04
05
06
07

RtW
CS
RESET

A18/CS10
A19/CSI ~"'I
GNO

PAO
PA1
PA2
PA3
PA4
PA5

---t

-T
----y-F
----'§-

fa

~~~ -t'f

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PCO
PC1
PC2fTIN
PC3/TQUT

PC4/DMAREQ
PC5/PIRQ
PCB/PlACK
PC7/TIACK

PSD3XX

MOOA

~

68HCll

GNO

tLJ
1~F

Vee

Vee

Vee
R1
4.7K

68230

I~
I

GNO
U4

Vee
2

tir

Voo
RESET

-,f8

23
24
25
26
27
28
29
30

R.E2SI
18
XIRQ~
IRQ

~VRH
51
VRL

Vee

8
9
10
11
12
13
14
15

3

GNO

GNO

MC34064

!:
II

ISl

-

I'BIJ3XX - App/1tJtJtItHI "",. 111

Addltlolllll
External IRA.

Tabl.,S.
M"HC11/

PSD3XX

Configured to
AddlllSS
Additional
SRAM

Figure 22 illustrates how additional SRAMs
can be configured into a system. This
PSD3XX configuration is not limited to external peripheral expansion; it can also be used
to add additional memory without the need for
external glue logic. With an S-bit address/
data multiplexed scheme, the higher-order
addresses (AS-A 15) are non-multiplexed.
These address lines are fed directly to the

external SRAM from the microcontroller and
do not need to go through the PSD3XX
These lines can drive the RAM chip directly.
Thus the M6SHC11 system, which is highly
memory-intensive and requires more RAM
than the microcontroller and PSD3XX can
supply, can take advantage of the configuration shown in Figure 23 which is detailed in
Table 15.

Conflgurallon

Blls

Function

CDATA
CADDRDAT
CRRWR
CA19/CSI
CALE
CRESET
COMB/SEP
CPAF2
CPAF1
CPBF
CPCF
CPACOD
CPBCOD
CADDHLT
CSECURITY

0
1
1
0
0
0
0
0
FFH
OOH
111B
OOH
OOH
X
0

8-bit data bus
Multiplexed address/data
Set RIW and E mode
Set power-down mode
Active HIGH AS
Active LOW RESET
Combined memory mode
Port A = address AD-A7
Port A set for address
Port B set for chip-select
Port C set for chip-select
CMOS buffers
CMOS buffers
Latched A16-A19 "don't care"
No security

----------------------~Jr;---------------------1-40

~er.l!
~

_ml

;::~i!Ci1

~:liliin

!010~-~

a'I~!'5

i.~

21
~

G

'~,

GND
U1

gHZ

7

II
P01

22

PD2
PD3

23
24

",q

25

~E5~46
48

1.111~~

~
~34
PA1
33

~

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

-¥.~

VRH
VRL

~
PA4
PAS

~~

oe

29
28

27

R4
1K

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7,

PEO
PE1
PE2
PE3
PE4
PES
PE6
PE7

I ~~~? ~§L

1Qij1111

PCO
PC1
PC2
PC3
PC4
PCS
PC6
PC7

PDO
PD1
PD2
PD3
PD4
PDS

~
I PE2
PE1 ~-4~
47

l.l~

U2

XTAL
XTAL

8

~g:

I

20pF

T

X1

AS
RESET
XIRQ
IRQ
MODB
MODA

16
17
18
19
20
21
22
23

31
32
33
35
36
37
38
39

Vee

6
4
17

~
2

22
2
1
13
3

U3

ADO/AD

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD1/A1

AD2IA2
AD3/A3
AD4/A4

ADS/AS
AD6/A6
A07/A7

ADS/AS

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

AD9/A9
AD10/A1Q
A011/A11
AD121A12
AD131A13
AD14/A14
AD15/A15
E
RlWNPP
BHEIPSEN
AS
RESET

A16/CSB
A17/CS9
A18/CS10
A19/CSI

PSD3XX

21
20
19
18
17
16
15
14

AO
A1
A2
A3
A4
AS
A6
A7

11

CSO

I '~

10
9

8
7

A8
A9
A10
A11
A12

CS11

~I

I--+r---L
~

G~D

20

22

-

~

C3

1~F

R1
4_7K

"r

R1
4.7K

R1
4.7K

20

~
27
22
Vee

U4

Vee

-"L.L

~

Voo
RESET

2

~

GND

'--------

MC34064

3

DO
D1
D2
D3
D4
DS
D6
D7

11
12
13
15
16
17
18
19

CS1
CS2
WE
OE

U4
10
9
8
7
6
5
4
3
25
24
21
23
2

~D

"r

AO
A1
A2
A3
A4
AS
A6
A7
A8
A9
A10
A11
A12

6164

i---#43

~

~

6
5
4
3
25
24
21
23
2

~
27

Vee

68HC11

~D

....
.c..
....

23
24
25
26
27
28
29
30

5
E
RMi

+---

r

8
9
10
11
12
13
14
15

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1l
A12
CS1
CS2
WE
OE

6164

DO
D1
D2
D3
D4
D5
D6
D7

11
12
13
15
16
17
18
19

;,:
~~
I

:iit
a
I-

1=

if

!:i
....

PSD3XX - Application Note mt

Additional
External SRAM
(Cont.)

Table 16.
SC80C451/

PSD3XX

Configured to
Address
Additional
SRAM

data. Since it is a multiplexed 8-bit machine,
it can use the on-chip latches. In highly RAMintensive applications, an additional two 8K x
8 SRAM chips can be included and selected
through Port B. If additional SRAM chips are
not needed, Ports A and B can recreate Ports
o and 2 which are lost in addressing external
memory.

Figure 23 illustrates, and Table 16 details, a
similar system using the Signetics
SC80C451. This microcontroller has many
ports and some SRAM but requires off-chip
EPROM to store programmed instructions.
This device is similar to the 8051/31 family
which uses the active LOW PSEN signal to
differentiate between executable code and

Configuration

Bils

Function
a-bit data bus

CDATA

0

CADDRDAT

1

Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set power-down mode

CALE

0

Active HIGH ALE

CRESET

1

Active HIGH RESET

COMB/SEP

1

Separate data/program memory

CPAF2

0

CPAF1

FFH

Port A set for address

CPBF

OOH
111 B

Port B set for chip-select

CPCF
CPACOD

OOH

CMOS buffers
CMOS buffers

Port A

= address AD-A?

Port C set for chip-select

CPBCOD

OOH

CADDHLT

0

"Don't care" (not used)

CSECURITY

0

No security

----------------------------------rAfAfAr~---------------------------------i!IJJ19EJ! ==
t-42

·S'~se::!!

~ . . . 19 ~'I
5=.~§c;

i-I~~~
5Ia:

~

~
49
P4.2

~

Pi 4

',llliiIQ:
111111

Ilhlllll
11111~q

~~ ~

26
29

~
~62

PO 1/AD1
PQ2/AD2
PO 3/AD3
PQ4/AD4

PO S/AD5
PO S/AD6
PO.7/AD7
P201A8

P21/A9
P22fAl0
P23/A11
P24/A12

P67
P66
P65
P64
P63
P62
PS.l
P60

~61

~60
~59
~58

~

~
AFLAG
BFLAG

POD/ADO

P10
P11
P1.2
P13
P14
P15
P16
P17

~25
~26
~~ 27

~

P2.S/A13
P26/A14
P27/A15
ALE

PSEN
RD/P3.7
WR/P36

AFLAG
BFLAG

~~~

T1/P35
TO/P3.4
INT2/P33
INT1/P32
TXO/P31
RXD/P30

IDS
ODS

G~

~
XTAL2

P4.0

~

C2

12MHz

P43
P42
P4.1

21

-

u

U1
XTAL1

~
~22

J

I
GND
Cl

EA
RESET

SCBOC451

P57
P56
P55
P54
P53
P52
P51
P50

48

U2

17
16
15
14
13
12
11
10

23
24
25
26
27
28
29
30

2
3
4
5
6
7
8
9

31
32
33
35
36
37
38
39

64
63

13
1

39
3B

22
2

Ui
:I
Rt~
I 32

,'L-

U3

ADO/AQ

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7

AD1/A1

AD2fA2
AD3/A3
AD4/A4

ADS/AS
ADS/A6
AD7/A7
ADB/A8
AD9/A9
AD10/A1Q
AD11/A11

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

ADl21A12
AD13/A13
A014/A14
AD15/A1S

ALE
BHE/PSEN

AD
WR
RESET

Al61CS8
A17/CS9

A18/CS10
A19/eSI

21
20
19
18
17
16
15
14
11
10
9

t----!!r--+r--%-

AO
A1
A2
A3

10
9
8
7

A4

6

A5
A6
A7

AS
A9
A10
A11
A12

GSO

~~~D

I

~
27

t---L

22

~
~
~

PSD3XX

::

~
~

t1B
t1B

20

~

~
27
22

...

e

OS1232

P-

P57
P56
P55
P54
P53
P52
P51
P50

Tl/P3.5
TQ/P34
-INT2IP3.3
INT1/P32
TXD/P31
RXD/P30

DO
01
02
03
04
05
06
07

11
12
13
15
16
17
18
19

GS1
GS2
WE
DE

U4

17.,

GND

1

AO
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12

6164
10
9
8
7
6
5
4
3
25
24
21
23
2

.L-

RST

5
4
3
25
24
21
23
2
20

~

Vee

RST

"

AO
A1
A2
A3
A4
A5
A6
A7
AB
A9
A10
A11
A12
GS1
GS2
WE
DE

6164

DO
01
02
03
04
05
06
07

11
12
13
15
16
17
1B
19

~

2:
~I

:...

iI
if

!
i

~
!it

...

~

PSD3XX - AppilcatiDn lID,. 011

PSD3XX Used in
Track Mode

Figure 24 illustrates a design that utilizes the
track mode of operation that has been
discussed but not illustrated in an application.
Here, Port A passes or tracks through the
multiplexed address and data of the 80196.
Address and data outputs ADO-AD7 from the
80196 appear on the PSD3XX Port A pins. In
this mode, the SRAM, shown in Figure 24 as
U4, can be accessed either by the 80196
(used in byte mode) or by a second processor
in the host system. The SRAM in the design
can be used as a common resource. An
example would be a system in which the host
uses the memory to pass parameters to the
local 80196. Table 17 gives the configuration
data for an 80196/PSD301 interface to SRAM
using Track Mode.
A Direct Memory Access can transfer data to
the common memory via a BUSRQ/BUSGR
handshake. Note that the PAD in the
PSD3XX controls the three-state condition of
the octal latch U3 74HCT373 enabling the
host system to control SRAM addresses
AD-A7. Port A of the PSD3XX is also put into

Table 17.
Intel80196 to
PSD3XX Used to
Access Extemal
SRAM in Track
Mode

Configuration

Blls

a three-state condition during host-to-SRAM
activity. In the design given in Figure 24, Port
B outputs PBO, PB1, and PB2 are used to
control the SRAM inputs CE, OE, and WR respectively. Also, A8, A9, and A 10 are fed
through the PAD as identity functions to the
open drain drivers of PB3, PB4, and PB5
respectively. There is no track-through
feature for these address lines; however, if
they are fed through the PAD, they can drive
the external memory resource as if they were
tracked through.
The M80196 can operate in either byte- or
word-wide mode controlled by its BUSWIDTH
input. In this application, the PB6 output
drives the BUSWIDTH line to switch between
the byte-wide bus of the external SRAM and
the word-wide interface of the PSD3XX. All
Port B outputs, with the exception of PB6, are
configured as open-drain. Provided the host
system also has open drainl collector drivers,
both systems can access the SRAM without
bus conflict. The only additional circuitry required would be the pull-up resistors.

Function

CDATA

1

16-bit data bus

CADDRDAT

1

Multiplexed address/data

CRRWR

0

Set RD and WR mode

CA19/CSI

0

Set power-down mode

CALE

0

Active HIGH ALE

CRESET

0

Active LOW RESET

COMB/SEP

0

Combined memory mode

CPAF2

1

Address/data (Track Mode)

CPAF1

XXH

"Don't care" in Track Mode

CPBF

OOH

Port B set for chip-select outputs

CPCF

111 B

Port C set for logic outputs

CPACOD

OOH

CMOS buffers

CPBCOD

FFH

Open drain buffers

CADDHLT

X

Latched A 16-A 19 "don't care"

CSECURITY

0

No security

-----------------------------------~~~----------------------------------1·44

fI=-:!!li'::!'
I' ~~ S' CCj'

:Iii

!l:ItH-;

S'~g~

i~~'
a~
!!.
X1

[r-Jo~
2MHz

1-=1-

T ~.l'PF

T

U1

---ll...-

01
20pF

GNO

12
~

3
43

--iA64
16

~"I~

00-07

GNO

PO.O
PO.1
PO.2

6
5

~

~
PO.4
10
PO.S
POB

8
9

....EQl.....

.-prrP2.1

~
~
~

~~

15

44
42
39

~~
P27

~~

~~~
HSI1 S-26

~~:~~

*

S-27

~

\e

,FE

01UF
C3

U2
P3.OIADO

Xl

P31/AD1
P32/A02

X2
NMI

READY
COE
BUSWIDTH
RESET
ACHOIPOQ
ACH1/PO.1
ACH2/P02
ACH3IP03
ACH4IP04
ACH5IP05
ACH6IPO.6
ACH7/P07

P201TXD
P21/RXO
P2.21EXINT
P231T2CLK
P24fT2RST
P2.51PWM
P2 6fT2UP-DN
P2.7fT2CAPTURE
HSI.O
HSI1
HSI.2/HS04
HSI3IHSO 5
VREF

ANGND
EA

80196

P3.31A03
P34/AD4
P3.51AOS
P3.61AD6
P37/AD7
P40/ADB
P41/AD9
P421AD10
P431AD11
P441AD12
P451AD13
P4.61AD14
P47/AD15

WHElBHE

P10
P11
P12
P1.3
P14
P15
P1.6
P17
HSOO
HSO.1
HS02
HS03

ADO
A01
AD2
AD3
AD4
ADS
ADS
AD7

23
24
25
26
27
2B
29
30

52
51
50
49
4B
47
46
45

AS
A9
A10
A11
A12
A13
A14
A15

31
32
33
35
36
37
38
39

A07/A7

~

AD9IAQ
AD101A10
AD11/A11
AD141A14
AD15/A15

RO
WR
BHEIPSEN
ALE
RESET

3
4
7
8
13
14
17
18
CS1
11

Hr-4-

AD121A12
AD13/A13

~

~

11
PBO
PB1
PB2
PB3 1 8 "
PB4
PBS ~
PBS
PB7

AD8IA8

2
1
13

r-M-

U3
21
20
19
18
17
16
15
14

PAO
PA1
PA2
PA3
PA4
PAS
PAS
PA7

ADO/AD
A01/A1
AD2IA2
AD3IA3
AD4/A4
AD5IAS
AD6IA6

22

61
40
41
62

RO
WRLlWR
ADVIALE
INST
CLKOUT

60
59
58
57
56
55
54
53

...
~

T
~

GNO

C1
10",F

06
07

~

AlB/OSlO

~

AO
A1
A2
A3
A4
AS
AS
A7
AS

A9
A10
CS
RO
WR

74HCT373
ALE

8
7
6
5
4
3
2
1

~
~
18
20
21

AO
A1
A2
A3
A4
AS
A6
A7
AS
A9
A10

DO
01
02
03
04
05
OS
07

P.P
~
=l-P

=fD

CE
OE
WE

6116

A19/0SI ~D

fit
!~ ~

Vee

P12

R1
470R

~

CE

f---< P15
f--~
f-<-E1L...

~

Vee

rBiJSGR>.

Il'ii»l..J1l1!L>-

HSOO

R4
10K

05

r-±-

A161Csa
A17/CS9

GIND

Vee

04

2
5
6
9
12
15
16
19

PSD3XX

~

~
HB

01
02
03

OC
G

I~
~:-... ~
I

U4

ao

DO
01
02
03
04
05
06
07

HS02
JS03

I

OE

>

R2

470R

I

Vee

~

iIoC

R3

470R

FROM HOST SYSTEM

WR
AQ.-A10

OG-DB

I

t(

i'

I52

...

PSD3XX - Application Note 011

--------------------------------f===~-------------------------------1-46

==~=

Programmable Peripheral
Application Note 011
Software Support

Chapter 3

The support software for both PSD3XX
family and MAP168 memory-mapped
peripheral devices is designed to run on
IBM PC XT/AT or 100% compatible
systems. It is menu-driven and very userfriendly. In many cases it has the capability
of preventing the user from creating invalid
configurations. For example, in a nonmultiplexed system with a 16-bit data bus,
Ports A and B are used for data 1/0. The
software recognizes this and prevents the

user from inadvertently programming Ports
A and B as regular ports.
When running in the IBM PC environment,
the PSD development software creates the
menu shown in Figure 25. Initially, the
designer selects the part type with the user
key F8 or moves the screen cursor to
PARTNAME. In the example shown, the
selection for the part type is PSD301.

Figure 25.
MAPLE Main
Menu
F1

DOS

FZ

EXIT

F3
F4

MAPPRO
PARTLIST
LOAD
SAVE
COMPILE

FS

F6
F7

111.min;miil
~

Part naMe
Specify

: PSD301
PART~AME

to be configured and press .

Cursor - Up:t Down:l
C:\WSI
240225

The menu listed to the left of Figure 25 links
the function keys and their association. F1
suspends the MAPLE software to DOS for file
editing or updating. F2 exits the program and
returns the user to the DOS environment. F3
selects the programmer option so the user
can program the compiled object file into the
PSD301 device provided a programmer is
connected to the system. The LOAD selection (F5), loads an existing program into the
MAPLE environment for editing and compiling. F6 saves that program under a user-

defined name. F7 compiles the user-generated file into an object file that can be transferred to the programmer. F8 provides part
type selection, either PSD301 or MAP168.
Figure 26 illustrates a second menu to the
right of the main menu. The list shows
ALIASES, CONFIGURATION, PORT C,
PORT A, PORT B, and ADDRESS MAP. The
designer selects each choice, starting from
ALIASES, and moves down through the list
configuring each option.

-------------------------------------r==~~----------------------------------~
====
1-47

I'SDIXX - Appllt:lllllln "",. DI1

FI,ure26.

MAI'LE Menu
with PARTMAME
Submenu
Fl
FZ
F3
F4

DOS
EXIT
ItAPPRO
PARTLIST

F5
F6

LOAD
SAVE

F7

COItPILE
PARmA"E

F8

I

If you want to nallle

CUI'SUr-

lip t

IJOWIl

SOlIe

! I, I t

I'AKTNAML

I'~J)IOI

CONFIGURATIOH
PORT C
PORT A
PORT B
ADDRESS MAP

signals. press .

Fl ~ Return to Main Menu
Cursor
Up:T Down:'

FZ

~

Temporary exit to Dos

240230

Flgureal.
PortB
Configuration
Menu

Figure 31 gives the configuration of Port B.
This is similar to the configuration pattern for
the M68008 shown in Figure 13. Here, CS6

and CS7 have been programmed as opendrain outputs connected to the microprocessor's DTACK and BERR, respectively.

PORT B

PIIt
PBa
PBi
PBZ
PB3
PB4
PBS
PB&

CS/IO CMOS/OD
csa
CMOS
CSi
CMOS
CSZ
CMOS
CS3
CMOS
CS4
CMOS
CSS
CMOS
CS&
OD
CS7

... -If you haue CMOS output for PB7 press SPACEBAR.

Fl
F3

~

Return to Main Menu
boto CS DefinitIOn

FZ
T"mpnr'dry exit to Dos
Cursor ~ Up:t Down:' Left:<-

Right:~

240231

-----------------------------------~Jr~~----------------------------------1-51

PSD3XX - Application Note 011

Figure 32.
ADDRESS MAP
Menu

Figure 32 shows the ADDRESS MAP menu.
The designer can enter a binary code for the
address range of the various select lines;
ESO-ES7, RSO, and CSP, being the EPROM,
SRAM, and PERIPHERAL assignments,

respectively. A space for individual hexadecimal files is reserved under the FILENAME
section. The Intel MCS files are listed as they
would be compiled and programmed into the
device.

ADDRESS MAP
FILE NAME

Fill in A19-All (Binary) or SEGMT START (Hex); and FILE(START, STOP)
and FILE NAME. Use SPACEBAR to erase any field ualue.
Fl - Return to Main Menu
FZ - Temporary exit to DOS
F3 - Goto Help
Cursor - Up:t Down:.J. Left: .. Right:..
N - Non-editable bit.

240232

After configuration has been established, the
user can return to the main menu and select
the COMPILE option. The configuration is
compiled and converted to a JEDEC array
program map.
When successfully finished, the designer can
select the MAPPRO option (see Figure 25),
and when a WSI MAGICPROTM programmer

is available in the PC system, finalize the
design by programming a PSD301.
The Address Map for Port B can be configured as shown in Figure 33. Per Figure 31,
depress function key F3 to invoke the chip
select definition. The entries can be made for
logic HIGH, LOW, or "don't care" conditions.

===iiiE~
-------------------------------------~~~~-------------------------------------

1-52

PSD3XX - Application Note 011

Figure 33.
PortB
Configuration
Menu with
Address Map

PORT B
PIH
~

PBi
PB2
PB3
PB4
PBS
PB6
PB7

CS/IO CMOS/OD
_ _ CMOS
CSi
CMOS
CS2
CMOS
CS3
CMOS
CS4
CMOS
CSS
CMOS
CS6
CMOS
CS7
CMOS

~fl~ffrl~~

'UiJU]

A14

CS definition is the HOH of the product terms(rows). Enter 1 to select
Actiue High signal, a to select Actiue Low signal, X to mean 'don't
care', SPACEBAR to erase. Enter ualues in columns releuant to your
application: other blank columns will be treated as 'don't care's.
Fi - Return to PORT B

Cursor - Up:! Down:! Left:<- Right: ..

240231

Summary

The PSD3XX microcontroller peripheral with
memory, supported with low-cost software
and programming capability form WSI,
greatly simplifies the overall design of
microcontroller based systems. The key
advantage is the extensive condensing of
glue logic, latches, ports, and discrete
memory elements into a single-device,

enhancing the reliability of the final product.
Applications for the device extend to practically any area that uses microcontrollers or
microprocessors, from modems and vending
machines to disc controllers and high-end
processor systems.

--------------------------------f====~-------------------------------1-53

1.1_~~~---------------------'E;'~-------------------------eesiE

Programmable Peripheral
Application Note 013
The PSD301 Streamlines a Microcontroller-based
Smart Transmitter DeSign
By Seyamak Keyghobad - Bailey Controls,
and Karen Spesard - WSI

Abstract

A smart transmitter design is described
which takes advantage of the integration
capabilities and flexibility of WSI's
PSD301 microcontroller peripheral. The
following discussion illustrates how the

PSD301, in effect, was responsible for
eliminating an extra 2.5 inch diameter
board in a system where real estate is at
a premium by reducing the number of
components from 12 down to 5.

Introduction

Designers of systems using microcontrollers and microprocessors often
face the problem of how to integrate
peripheral logic and memory functions
into their designs without using many
discrete chips and large areas of board
space. For example, when external
EPROM and SRAMs are configured into
systems with ROM less microcontrollers,
general I/O ports are typically sacrificed
for address, data input/output, and control
functions. When these I/O ports are
depleted, the total chip count of the
system is increased by requiring the use
of additional external ports and steering
logic. Designers, who have limited board
space, such as found in the disk drive,

modem, cellular phone, industrial/process
control, and automotive industries, find
this a critical problem.

The Design
Application

The smart transmitter, shown in Figure 1,
was developed by Bailey Controls, a
manufacturer of process control
instruments, to support a popular field
bus protocol. One of its functions in this
sensor application is to measure
pressure, differential pressure, and flow
rates through pipes in industrial
environments such as chemical plants, oil
refineries, or utility plants. A host system
monitors the transmitter via a process
control network.
The completed transmitter design
consists of three main boards. The first
board includes the power supply and
communications hardware to provide
power to the rest of the system and feedback to the process control network. It
consists of communications transformers
and line drivers/receivers.

_____________________________________

rjf~~E

--';111:';;:;;:;::=

The PSD301 programmable peripheral
device from WSI solves this problem by
integrating all SRAM, EPROM, programmable decoding and configurable I/O port
functions needed in 8 or 16-bit microcontroller designs into a single-chip
user-configurable solution. This is
illustrated in the following industrial
control application where the PSD301
eliminates seven chips and saves the
designer from needing another board in
the system.

The second board is the digital microcontroller board and contains the 68HC11
microcontroller as well as the PSD301
programmable peripheral, a PLD, UART,
and LCD display. Its function is to
communicate and receive the inputs from
the third board, process the data, and
display the appropriate results to the LCD.
The third board or input board is mostly
analog. It receives inputs from string gauge
sensors which use a bridge circuit for
measuring pressure using a diaphragm.
The input board then converts the signals
so the microcontroller can read them.

_____________________________________
1-55

PSD3D1- Application Note 013

Figure 1.
"Smart"
Transmitter from
Bailey Controls

• Pressure/Flow

Design
Considerations

The smart transmitter system is rather
small. Its case is only 2.5 inches in
diameter and thus requires boards that
fit this small form factor as shown in
Figure 2. Not surprisingly, the major
design consideration during development
was board space. This was especially
true for the microcontroller/digital board
where real estate is at a very high
premium.
One of the problems was that there were
already requirements for the 68HC11
microcontroller, a 256K EPROM, 16K
SRAM, a PLD, TTL logic, a UART, and
an LCD display on the digital board. This

meant extending the number of boards
used beyond one unless a way could be
found to integrate some of these
elements.
Other important considerations, or goals
actually, for the design were to reduce
power consumption to less than 2.4W,
improve reliability, lower design costs,
and shorten the time-to-market.
To meet these objectives, Bailey Controls
looked to WSI's user-configurable
peripheral, the PSD301, for its integration
capabilities, its flexibility, and its low
power of less than 35 mA active and
90 !1A typical powerdown.

Figure 2.
The Bailey Smart
Transmitter Board
Using the WSI
PSD301.

~~-------------------------------,~~~~----------------------------------1-56
=eiiiiF=

PSD301-Application Note 013

PS0301
Architecture

The PSD301 is a field programmable device
that has the ability to interface to virtually
any 8- or 16-bit microcontroller without the
need for external glue logic. This is possible
because the PSD301 combines the
elements necessary for a complete
microcontroller peripheral solution, such as
user-configurable logic, 1/0 ports, EPROM
and SRAM, all into one device. The
functional block diagram of the PSD301 in
Figure 3 shows its main sections: the
internal latches and control signals, the
programmable address decoder (PAD), the
memory, and the 110 ports.

Figure 3.

A16 - A18

PS0301
Architecture

The control signals and internal latches in
the PSD301 were designed so interfacing
to any microcontroller would be easy and
require no glue logic. For instance, the
PSD301 can interface directly to all
multiplexed (and non-multiplexed) 8- and
16-bit microcontroller addressldata buses
because it has two on-chip 8-bit address
latches. This means no external latches
are required to interface to multiplexed
buses. It also has programmable polarity
on the control inputs ALE/AS and RESET,
so they can be configured to be active high
or active low.

I

; - - A11-A15
L
A
T
C
H

AD8-AD15

~
A19
CSI

'-L
A
T
C
H

-+:1""" 1+

PADA

~

lLOGICIN

RD

WR
RESET

WR
RESET

13 PT

.. -

-

27 P T

~
~
ESO

-

I
t+" -1+

'--

~

CS10

.....
CSOCS7

16i8
~- -1+

foCS8-

PORT
C

~

'---

EPROM
256K BIT

ES7
ES6
ES5
ES4
ES3

-

~~~

PROG
PORT
EXP
PCO-

PADB

ALE/AS

RD

~

~

CSI

ALE/AS

ro-

A Do-AD7

1

J

CSIOPORT
A19

32K BIT
BLOCK

r

08-015

I-

PROG
PORT
EXP
PBOPORT

B

~

'-;--

I--,.

<1 I---

t>

I--

--

--

CSIOPORT

00-07

1-

r-'-~

'--

SRAM
16K BIT
TRACK MODE
SELECTS

AO A7
ADO AD7/DO 07

PROG
PORT
EXP
PAoPORT
A

~

ALE/AS
ROlE

PROG CHIP
CONFIGURATION

~

WR/RlW
BHE/PSEN
RESET

1

X8, X16

PROG
CONTROL
SIGNALS

MUX or NON-MUX BUSSES
SECURITY MODE

A19/CSI

-------------------------------------rJrJr~~--------------------------------------'!i!!1V_
1.57

=

I'S0301- Application Note 013

PSD301
Architecture
(Cont.)

The other control signals, RDIE, and

WR/R/W, are also programmable as IRD
and IWR or E and RIW, enabling direct
interface to all Motorola- and Intel-type
controllers.
The programmable array decoder (PAD) is
an EPROM-based reprogram mabie logic
"fuse" array with 11 dedicated inputs, up to
4 general-purpose inputs, and up to 24
outputs. The PAD is used to configure the a
EPROM blocks on 2K word boundaries and
the SRAM on a 1K word boundary
anywhere within a 1 Meg address space. It
is also used to generate a base address for
mapping ports A and B, as well as to
provide mapping for the track mode. The
PAD, like a traditional PLD, can generate up
to eight sum-of-product outputs to extend
address decoding to external peripherals or
to implement logic replacement on a board.
Memory in the PSD301 is provided by
EPROM for program and table storage and
SRAM for scratch pad storage and
development and diagnostic testing. The
EPROM density is 256K bits and the SRAM
density is 16K bits. Both can be operated in
either word-wide or byte-wide fashion,
which translates to a 32K x a or 16K x 16
EPROM configuration and a 2K x a or 1K x
16 SRAM configuration. As described
above, the EPROM is divided into a blocks
(of 4K x a or 2K x 16), with each block
typically on a 2K boundary locatable within
a 1 Meg address space.
There are 3 ports on the PSD301 that are
highly flexible and programmable: Ports A,
Band C, illustrated in Figure 4. Port A is an

a-bit port that can be configured in a variety
of ways. For example, if the PSD301 is in
the multiplexed mode, port A can be
configured pin-by-pin to be an 1/0 or a lower
order latched address. Alternatively, port A
can be configured in the track mode to
transfer a bits of address and data inputs
through port A. This enables the microcontroller to share external resources, such
as additional SRAM, with other controllers.
In either case, each port A output can be
configured to be CMOS or open drain. If the
PSD301 is in the non-multiplexed mode,
port A becomes the lower order data for the
chip.
Port B is another flexible a-bit port. In the
multiplexed mode or a-bit non-multiplexed
mode, each pin on port B can be
customized to function as an 1/0 or a
chip-select output. The chip-select signals
are determined by the PAD programming
and are used for general logic replacement
or to extend the address decoding to
external peripherals. Each pin in this mode
can also be programmed to have a CMOS
or an open drain output. In the 16-bit
non-multiplexed mode, port B becomes the
higher order data for the chip.
Port C is the third port which is available on
the PSD301. It is a 3-bit port that can be
programmed on a pin-by-pin basis to be
chip-select outputs andlor general-purpose
logic inputs or addresses to the PAD.
Some uses for port C might be to extend the
address range to 1 Meg, or to create finer
address decoding resolution down to 256.
Or, one might use port C to help create a
simple state machine.

Figure 4.

PSD301
Multiplexed
Address/Data
Configuration

AS -

A1S,

ADS - AD1S

ALE

PORT A

PORT B

ADO - AD7

PORT C

1/0 or AO - A7 or ADO - AD7

1/0 or CSO - CS7

A16, A17, A1S or CSS, CS9, CS10

-------------------------------------~jr~Ar------------------------------------1-58

PSD3D1-Application Note 013

Simple
Interfaces
to the PSD301.

One of the overwhelming advantages of the
PSD301 is its ability to interface to virtually
any microcontroller without any glue logic,
while providing additional I/O ports and
memory. This is accomplished by
configuring or programming the part to
function in an operational mode geared for
a specific application.
For instance, there are 45 configuration
bits on the PSD301 that have to be
programmed in addition to the EPROM
prior to usage. These configuration bits are
determined during development by the
designer using the WSI MAPLE software
package. After the configuration bits are
determined, the EPROM code and
configuration data can be merged during
compilation and the part subsequently
programmed.

configuration bits discussed above. To
illustrate how this works, two examples are
provided.
The first example is with the 80C196
microcontroller. This 16-bit microcontroller
from Intel interfaces directly to the PSD301,
providing it with additional off-chip program
store EPROM and data store SRAM, as
well as the flexibility that comes with three
additional I/O ports. As illustrated in Figure
5, the 80C196's 16-bit multiplexed address/
data bus and control signals (RD,WR,
BHE, ALE, RESET) connect directly to the
PSD301. This is achieved with the PSD301
in the following configuration:

o
o
o
o
o
o
o

Interfacing the PSD301 to different
microcontrollers is accommodated by the

Figure 5.
General
Schematic
Diagram of
the BOC196
andPSD301.

80196

1 FT

lC1i

VCC

30PF
11
=X1
8MHZ
12

1

14
64
16

~

6

~

P3.D/ADO
P3.1/AD1
P3.2/AD2

X2
NMI

P3.3/AD3
P3.4/AD4

READY

P3.5!AOS

CDE
BUSWIDTH
REseT

P3.6/AD6

>----i"

ACHO/POQ
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
ACH6/PO.6

~

ACH7/PO.7

~
~
~
~
~

~

~
RXD~
~

~
~

~

~
P2.7 >-----""
~

~;~~
~
~
26

13
12
2

PSD301

X1

l'C2
30pF

~
GNO

16-bit data bus
Multiplexed address/data
RD and WR mode set
Active HIGH ALE
Active LOW RESET
A 16 - A 18 configured as output
Combined memory mode

P2.0/TXD
P21/RXD
P2.2/EXINT
P2.3!T2CLK
P2.41T2RST
P25/PWM
P2.6/T2UP·DN
P2.7fT2CAPTURE
HSI.O
HSI.1
HSI.2/HSO.4
HSI.3/HSO.5

P37fAD7
P4.0/AD8
P4.1/AD9
P42/A010

P43/ADn
P44/AD12
P4.S/AD13
P4.6/AD14
P47/A015

-

RD
WRuWR
WHE/BHE
ADV/AlE
INST
CLKOUT

Pl.0
Pl.1
P1.2
P1.3
P1.4
P1.5
P1.6

Pl.7
VREF
HSO.O
ANGND

HSO.1

EA

HSO.2
HSO.3

U1

60
59
58
57
56
55
54
53

23
24
25
26
27
28
29
30

52
51
50
49
48
47
46
45

31
32
33
35
36
37
38
39

61
40
41
62

22
2
1
13

~
65

ClK

59
~
fa-<
P1.0

~
~
~
~

~

ADO/AO
AD1/A1
AD2/A2
AD3/A3

AD4/A4

ADS/AS
AD6/A6
AD7/A7

ADS/AS
ADS/A9
AD10/A10
AD11JAl1
AD12JA12
AD13/A13
AD14/A14

AD15/A15

-

RD
WR
BHE/PSEN
ALE
RESET

U2

PAO
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7
A16/CS8
A17/CS9

A18fCS1Q
A19/CSI

~
~

~
-in
PA3.3 ,
~

~
~
~

~

~
--i--)
PB4.2 :
~
~44<

~
~PB4.6(
~
40

~
42
43

GND

VCC

47~

~
~

~
29

P1.0

34
35

P1.1
P1.2
P1.3

R1
10K

~

T

.... C3

O.Q1~F

GND

-----------------------------------------~~~Ar----------------------------------------1-59

PSD301- Application Note 013

Simple
Interfaces
to the PSD301
(Cont.)

The other configuration options that are
available, but not listed above, are application dependent and can be changed to
meet the requirements of the design. For
instance, on e!.!!.43 (A 19/CSI), the powerdown option CSI could be selected if
power consumption savings is important.
If it isn't and another logic input to the
PAD would be helpful, A 19 could be
selected. And, if open-drain drivers are
important on one of the ports to drive a
display, for example, they also could be
selected instead of CMOS drivers.

from Motorola. For simplicity's sake, the
PSD301 interface to 68HC11 versions
with multiplexed address/data buses will
be discussed, although the nonmultiplexed versions will interface to the
PSD301 in a similar manner, except in
this case port A will become dedicated for
8-bit data.
Figure 6 illustrates the interconnections
between the PSD301 and the 68HC11
microcontroller with multiplexed
address/data buses. Again, all the
address/data connections are direct, as
well as the control signals (E, R/W, AS,
and /RESET). Because BHE/PSEN is not
used, this PSD301 input signal is tied
HIGH.

All other microcontrollers have simple
interfaces to the PSD301 as well. This
includes all the variations of microcontrollers in the 8-bit 68HC 11 family

Figure 6.
General Schematic
Diagram of the
68HC11and
PSD301.

FI

I20

C2

Cl
20 P

GND

68HC11A8
29

EXTAL

XTAL

IRQ

peO/ADO
PC1IADI

XIRQ
RESET

PC2/AD2
pe3/AD3
PC4/AD4
peS/ADS

PAD/le3
PA1/1C2
PA2/1C1

PC61AD6
pe7/AD7
peD/A8

PB1/A9
PB21Al0

PEO/AND

PB3/All

PE1/AN1
PE2/AN2
PE3/AN3

VCC

PD.4
POI
PD2
PD.3
PD.4
PD.5

42
43
44
45
46
47

PB4/A12

PBS/A13
PB6/A14
PB7/A15

P01/1XD

35
36
37
38

23
24
25
26
27
28
29
30

16
15
14
13
12
11
10
9

31
32
33
35
36
37
38
39

34

22
2
1
13
3
43

PA3/Des/OCl
PA410C410Cl

PAS/De3/0Cl
PA610C210Cl
PA7/PIA/cCl

MODe
MODAlLIR

STABfR/W
STRAIAS

GND

VRL
VRH

27
28
26

ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7

AD8
AD9
AD10
AD11
A012
AD13
AD14
AD15

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

RIW
BHEfPSEN
AS
RESET
A19/CSI

U3

21
22

Vee

Ul

PSD301

GND

30
31
32
33

POD/AXD
PD2/MISO
P03/MOSI
P04/SCK
PDS/S5

PF

GND

vcc

VCC

MC34064
1

Rl
lk

VDD
RESET

GND

U2
GND

1-60

~:f;

R3
lk

PCO
PCl
PC2

21
20
19
18

17
16
15
14

11

PA.O
PA.l
PA.2
PA.3
PA.4
PA.S
PA.6
PA.7

PSD301-Application Note 013

Simple
Interfaces
to the PSD301
(Cont.)

The PSD301 must be programmed using
WSI's MAPLE software package in the
following modes to achieve this
configuration:

The ''Smart''
Transmitter
Design.

The microcomputer-based smart
transmitter design, by Bailey Controls,
requires program store 256K bits EPROM
for storing algorithms and data store 16K
bits SRAM for storing AID, communication and LCD routines. It also
requires two octal latches, a PLD, and a
variety of glue logic to interface to its

o
o
o
o
o
o

Figure 7.
Detailed Block
Diagram of
Bailey Control's
Alternative
De'
t t-lon
sign Sou
W;ithout PSD301.

8-bit data bus
Multiplexed addressldata
RIW and E mode set
Active HIGH AS (ALE)
Active LOW RESET
Combined memory mode

68HC11 microcontroller, UART, and LCD
display. This is illustrated in Figure 7. Of
course, with board space on the digital
board being limited, another board would
have been needed to accommodate
these components, unless they in some
way could be integrated.

!......---i----------.--j----T--li
I
I
I
I

~

INTEGRATOR
&
COMPARATORS

MULTIPLEXERS

SELECTORS

Ii-

r----

I
I
I

T
VOLTAGE
REGULATOR

INPUT BOARD
BLOCK DIAGRAM

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

POWER
SUPPLY

I

I
I
I

GLUE LOGIC

I

: INPUT
I
I
I
I

l-

SENSOR

Again, other parameters on the PSD301
can be set to fit additional design
requirements. These include the security
bit, the port I10s, and the PAD inputs and
outputs.

I
I
I

68HC11E1
MICROCONTROLLER

_____________________________________

74HC10
74HCOO
74HC08
74HC14

Ir-

ItIhl
I

HC373
LCD
OCTAL
LATCH
~~

1 r-~

B '
SMART

'" i

i

r'"~I+

:

UART

COMMUNICATloj
TRANSFORMERS

,..-;-

~
ADDRESS/

1

DATA
BUS

HC373
ADD/DATA
OCTAL
LATCH

~
~

EPROM
32K
'----

;-~

.--~

SRAM
2K

PAL
22V10

l...-

r+

'----

MICROCONTROLLER BOARD
BLOCK DIAGRAM

14
I
I
I

~

LINE
DRIVERS
&
RECEIVERS

I
I
I
I
I

POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM

r=~aF~----------------------------------~

====

1-61

PSD301-Application Note 013

The "Smart"
Transmitter
Design
(Cont.)

This is where the PSD301 provides
exceptional value. As discussed, the
PSD301 already integrates EPROM,l
SRAM,2 a PLD, and other glue logic all
on one chip. It interfaces to the 68HC11
directly and actually integrates 8 chips
from the alternative design into one,
eliminating the need to add another board.
The resultant architecture is illustrated in
Figure 8.

port A is configured as an I/O and mapped
to the byte-wide LCD data inputs. Then to
write to or read from the LCD display, port
A is accessed like a memory-mapped
peripheral via an address offset from the
base CSIOPORT defined in the PAD.
Since port A is qualified by and handled
through the PAD, there is no need for an
external octal latch.
Other TTL logic is not required to interface
to the 68HC11 's control signals, memory,
or peripherals either. It is all integrated in
the PSD301. Thus, a smaller PLD than
originally thought required in the design
was used - a 16V8 instead of a
22V10 - because the PAD was able to
reduce the amount of logic by creating
chip selects for the UART and other logic
functions.

Note that in the alternative design shown
in Figure 7, ports typically lost when
connecting the microcontroller to external
memory had to be recreated externally with
latches and buffers when memory was
connected to the microcontroller. With the
PSD301, these ports are recreated internally, eliminating the latches and buffers.
For example, to interface the PSD301 to
the 24-character LCD display, each pin of

FigureS.
Block Diagram of
Bailey Control's
''Smart'' Transmitter
Design with PSD301

-.

POWER
SUPPLY

INTEGRATOR
&
COMPARATORS

MULTIPLEXERS

SENSOR

SELECTORS

VOLTAGE
REGULATOR

INPUT BOARD
BLOCK DIAGRAM

t

I
I
I
I
I

PORT A DATA

HI
I
I
I
I
I
I
I
I

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

PSD301
W/32K EPROM
2K SRAM
PAD & PORTS

t

68HCllEl

LCD
PORT B

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

ADDRESS/
DATA BUS

MICRO·
CONTROLLER

•
~

SMART
XMITTER
UART

-I

MICROCONTROLLER BOARD
BLOCK DIAGRAM

PAL16V8

I

COMMUNICATION
TRANSFORMERS

•

1+

LINE
DRIVERS
&
RECEIVERS

,

POWER SUPPLY &
COMMUNICATION BOARD
BLOCK DIAGRAM

~1.~62~---------------------------f---~------------------------------__
";I;i:'~::=

PSD3DI-Application Note 013

PS0301

Bonuses

Besides considerably reducing board
space in this smart transmitter design by
reducing parts count, several other
benefits of the PSD301 were also seen.
These include reliability improvement,
power consumption savings, inventory
savings, faster time-to-market, and cost
savings.
Reliability was improved because there
are seven less chips required for
implementation that could fail in the
design. Also, by reducing chip count, 112
pins and about 100 traces were eliminated
and the number of layers on the board
were reduced from 8 to 4, making failures
due to open or shorted pins and traces
less likely to occur.
Power consumption was reduced because
much faster discrete EPROM and SRAM
devices with access times of -75 ns would
have been required in conjunction with
glue logic for selecting different devices
instead of using the PSD301, saving at
least 20 mA Icc. (The access time for the
PSQ301 memories include decoding and
input address latch delays). If the
power-down feature on the PSD301 were
also used, power savings could be
increased further. For example, in a
system which is accessing the PSD301
only a quarter of the time, the power
consumption could be reduced by 75% to
8 mA typical.

As an added benefit, the PSD301 helped
reduce inventory significantly by
obsoleting multiple chips. And, if last
minute changes in the design were
required, the PSD301 would be able to
accomodate them without additional
hardware modifications. So, purchasing
line item management is made simpler
and easier.
With the reprogrammable PSD301 ,
development time was kept to a minimum
by easily accommodating design iterations
in both hardware and software. Changes
in 1/0, address mapping, bus interface,
and code were simple to make. Also,
debugging was made easier with the
PSD301 's on-chip SRAM for downloading test programs. This all helped to
shorten the design development cycle,
reduce development costs, and speed up
market introduction of the smart
transmitter.
By using the PSD301 , cost savings were
realized by reducing system cost with
fewer boards (or reduced board space),
improving reliability, and reducing
inventory levels. Savings were also
attributable to lower manufacturing costs
because there were fewer parts to
program and place. And by getting to
market faster, profits were improved
significantly.

Summary

The PSD301 peripheral solved a fundamental problem often seen in that instead
of getting "locked into" an inflexible
multiple chip memory SUb-system
solution, the PSD301 was able to provide

Notes

1.

If more EPROM was needed, the PSD302/312 w/512K bits EPROM and the
PSD303/313 w/1024K bits EPROM are available in the same pinout and packages
(please call your local WSI sales representative for availability). Or, multiple PSD301s
can be cascaded together with the added benefit of increased functionality and 1/0's.

2.

If more SRAM is needed, it can be added externally without requiring any additional
glue logic. See WSI Application Note 011. Note that many engineers have 8K x 8
SRAM in their systems now - not because they need it, but because 2K x 8 SRAMs
are not as readily available.

_____________________________________

,AJAJ~~

'#til. AJ

much higher integration and flexibility all
at the same time. Clearly, using the
PSD301 was the better choice for the
smart transmitter design.

________________________________

~~

1·63

I'SoaDt -Application Note 013

Appendix 1.
P60301
Configuration
wsi PSD301 configuration Save File for Smart Transmitter Desiqn
ALIASES
CSo = ASICCS

*******************************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/A19:
Reset Polarity:
ALE Polarity:
WRD/RWE:
A16-A19 Transparent or Latched by ALE:
Using different READ strobes for SRAM and EPROM:

MX
8
CSI
LO
HI
RWE
T
N

*******************************************************************************
PORT A CONFIGURATION (Address/IO)

Bit No.

Ai/IO.
IO
IO
IO
IO
IO
IO
IO
IO

a

1
2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

*******************************************************************************
PORT B CONFIGURATION
Bit No.

CS/IO.
cso
CSl
CS2
CS3
CS4
CS5
CS6
CS7

a
1
2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT EQUATIONS
/ASICCS
/CSl

= /A15

'" A14 '" /A13 '" /A12 '"

/A15 '" A14 '" /A13 '" A12 '"

E

E

/CS2

= /A15

/CS3

/A15

/CS4

/A15 '" /A14 '" /A13 '" /A12 '" /All '"

'" A14 '" A13 '" /A12 '"

*

A14

*

A13 '" A12 '"

E
E
E

+ /A15 '" /A14 '" /A13 '" /A12 '" /All '" / R/W
/CS5

= /A15

'" /A14 '" /A13 '" /A12 '" All '"

E

= /A15

'" /A14 '" /A13 '" A12 '" /All '"

E

= /A15

'" /A14 '" /A13 '" A12 '" All '"

+ /A15 '" /A14 '" /A13 '" /A12 '" All '" / R/W
/CS6

+ /A15 '" /A14 '" /A13 '" A12 '" /All '" / R/W
/CS7

E

+ /A15 '" /A14 '" /A13 '" A12 '" All '" / R/W

1-64

rES::
~~=

PS03D1-Appiication Note 013

Appendix 1.
PS0301
Configuration.
(Cont.)
********************************************************************************

PORT C CONFIGURATION
Bit No.

CS/Ai.
CS8
CS9
CS10

o

1
2

CHIP SELECT EQUATIONS
/A15 * /A14 * A13 * /A12 * /A11 *

/CS8

/CS9 .. /A15 * /A14 * A13 * /A12 * All *

R/W
R/W

/CS10 .. /A15 * /A14 * A13 * A12 * /A11 *

R/W

**********.*.*******************************************************************

ADDRESS

ESO
ESl
ES2
ES3
ES4
ESS
ES6
ES7
RSO
CSP

MAP

A A A A A A A A A
19 18 17 16 15 14 13 12 11
N N N N 1 0 0 0 N
N N N N 1 0 0 1 N
N N N N 1 0 1 0 N
N N N N 1 0 1 1 N
N N N N 1 1 0 0 N
N N N N 1 1 0 1 N
N N N N 1 1 1 0 N
N N N N 1 1 1 1 N
N N N N 0 1 1 0 0
N N N N 0 0 1 1 0

******************************

SEGMT
STRT
8000
9000
ACOO
BOOO
COOO
0000
EOOO
FOOO
6000
3000
END

SEGMT
STOP
8FFF
9FFF
AFFF
BFFF
CFFF
DFFF
EFFF
FFFF
67FF
37FF

EPROM
STOP
8fff
9fff
afff
bfff
cfff
dfff
efff
ffff

File Name
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0
BCN2.0

****************************************

CDATA
0
.. 1
CADDRDAT
CRRWR
1
0
CA19/(/CSI)
.. 0
CALE
CRESET
0
.. 0
COMB/SEP
CADDHLT
0

CPAF1
CPAFl
CPAF1
CPAF1
CPAF1
CPAF1
CPAFl
CPAFl

=

0
0
0
0
0
0
0
0

[0]
[1]
[ 2]
[3]
[4)
[ 5)
[6]
[ 7]

.. 0

CPAF2
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF

EPROM
START
8000
9000
aOOO
bOOO
cOOO
dOOO
eOOO
fOOO

[0] .. 0
[1] .. 0
[2]
0
[3]
0
[4]
0
[5]
0
[6)
0
[7] .. 0

CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD

[0)
0
[1) .. 0
[2]
0
[3]
0
[4]
0
[5]
0
[6]
0
[7] .. 0

[4]

[5]
[6]
[7]

CPCF [0]
CPCF [l]
CPCF [2]

FE:: EfEi$

0
0
0
0
0
0
0
0

[0)
[ 1]
[ 2]
[3)

1
1
1

-------------------------------------~~~----------------------------------1-.--65

~~

1-66

_______________________________________ .arar5Faf

rloIl; - - - - - - - - - - - - - - - - - -

Programmable Peripheral
Application Note 014
Using the PSD3XX PAD for System Logic
Replacement
By Jeff Miller

Introduction

In 1990, WSI Introduced the Programmable
System Device (PSD): the first device in
the world Integrating UVEPROM, SRAM
and programmable logic on a single chip of
silicon. The highly-successful PSD301 was
the first device in the PSD family and is
currently used in applications ranging from
fluid analyzers to high performance
computers. The PSD device, by combining
most of the peripheral functionality required
by a typical microcontroller unit into one
package, has enabled designers to greatly
reduce part count, power and board space
which has translated into significant cost
savings.

Even if the PSD3XX family were simply a
collection of EPROM and SRAM with an

PAD
Architectue

The Programmable Array Decoder (PAD)
contained in the PSD3XX family is a standard PLD array designed to provide all of
the internal memory and 1/0 device chip
selects as well as an external logic replacement capability. It has 14 inputs, 24 outputs
and 40 product terms with which to perform
these functions. See Figure 1 for an
illustration of the PAD.
The PAD's 14 inputs are as follows:

o
o
o

U

A11 -A19
ALE or AS
RD or E
WRor Riw

The A 11 - A 19 pins are labeled as address
inputs, however, they do not have to be.
A 11 - A 15 are generally sourced by the
microcontroller or microprocessor that is
connected to the PSD device. If the
controller generates more than 16 bits of
address, the A 16 - A 19 inputs may be
used to connect the high order address bits
for a full 1 MByte of address space. If the
controller does not require this much
address space, A 16 - A 19 may be used for
other purposes, like general 1/0 or logic
inputs.
A19 is multiplexed with the CSI signal,
which is used to place the PSD device in a

on-chip decoder, it would be capable of
adding significant value to the system into
which it were designed. However, the
PSD3XX family is much more than just a
combination of memory devices. The onchip PLD may be used for many useful
purposes in addition to providing the
address decode capability. The purpose of
this note is to demonstrate, in detail, the full
capability of the PAD section of the
PSD3XX family. A basic, though not extensive, knowledge of the PSD 3XX family and
the Maple programming software is
assumed by this note. Please consult
Application Note 011 andlor the appropriate
PSD3XX family data sheet for this general
knowledge.

low power mode when the system requires
it. When configured as CSI, the A 19 pin
may not be used for any other purpose
except the power down mode. In this
mode, the CSI signal is used by the PAD
only to disable it, causing it to expend less
power. When configured as A 19, this signal
may be used as a general purpose input to
the PAD from the external system. This
capability will be described in more detail
later in this note. A 16 - A 18, when not
necessary for address expansion, may also
be used as general purpose inputs to the
PAD. Thus, a total of four of the 14 PAD
inputs may be general purpose, allowing
the replacement of external logic by the
PSD device. These inputs may be
combined with the other PAD inputs to form
complex equations involving addresses,
strobes and external signals.
When attempting to visualize the full capability of the PAD outputs, it is most clear
when it is broken into two sections, labeled
in Figure 1 as PAD A and PAD B. PAD A is
responsible for providing all of the internal
chip selects for the EPROM, SRAM and 1/0
ports and the track mode control signals,
and PAD B is responsible for the external
logic replacement function.

-------------------------------------~~~~----------------------------------1--6-7

PSD3XX - Application Note 014

Figure 1.
PAD
Architecture
ALE

or AS

ESO

~

ESl
ES2

Ro or E

-

WR or R/W

~ES3

y=

8 EPROM Block
ES4
Select Lines
ESS
ES6
ES7
RSO _ _ SRAM Block Select
CSIOPOR T-IIO Base Address
eSADIN
Track Mode
eSADOUT~ } Control Signals
CSADOUT

-q
"

A19

,.....
"'5

A18

-g

A17

,.....

eSO/PBO

"

r

PAD A

!

eSl/PBl

~

":$

"
A16

eS2/PB2

-q
"

A15

A14

A13

A12

A11

---...

~

"~

-q
,.....

RESET

PAD A

PADB

"l:::

eSS/PBS

l:::--'

eS6/PB6

K"

eS7/PB7

"

eS8/PCO

"

eSg/pel

"

eS10/PC2

":$
~

-g

~

N
~

--

eS4/PB4

~

-

CSI

eS3/PB3

•
•

~

II' I

I

I

I

Thirteen of the 24 PAD outputs and thirteen
of the 40 product terms are dedicated to
PAD A. PAD A should be considered the
Internal address decoder, used to select
the various on-chip memories and I/O
devices according to the memory map
programmed by the user. Each output has
a single product term, allowing a particular

resource to be allocated a single
contiguous range of addresses which will
be used to access it. All of the PAD inputs
are available for generation of the PAD A
outputs, allowing the designer to select
internal resources using any combination of
address, strobe and external signals.

-------------------------~Jf~~-----------------------1·68

PSD3XX - Application Note 014

PAD A
(Cont.)

The PAD A outputs are as follows:

o
o
o
o
o
o

ESO-ES7
RSO
CSIOPORT
CSADIN
CSADOUT1
CSADOUT2

ESO - ES7 are used to select the internal
EPROM resources. Using the PSD301 as
an example, there are eight select lines
with which to access 32 KBytes of EPROM.
Thus, each select line can enable a block
of 4 KBytes of EPROM configured as
4K x 8 or 2K x 16. Each block must be
contiguous, but the blocks may be placed
anywhere within the address space of the
microcontroller.
RSO is used to select the SRAM resource.
This single signal accesses a single 2
KByte block of SRAM which may be
configured as 2Kx 8 or 1K x 16. Again, this
block must be contiguous but may be
placed anywhere in the address map.
CSIOPORT is the signal which defines the
base address of the on-chip I/O ports and
control registers. The 110 ports and control
registers occupy a 2K block of addresses
which, like the memories, must be
contiguous but may be located anywhere in
the address space of the microcontroller.
Once configured in the address map,
CSIOPORT defines the base address of
these ports and registers. An offset is
added to the base address to individually
access the registers. Table 1 below lists the
offset values for these registers.

Table 1.
I/O Port
Offset
Addresses

Register Name

CSADIN, CSADOUT1 and CSADOUT2 are
used to control the Track Mode operation.
The Track Mode is an available option for
Port A to allow it to ''track'' the
Address/Data bus inputs to the PSD device
from the microcontroller. This provides the
capability to connect the PSD device, and
therefore the microcontroller, to one or
more shared resources. These resources
may be memory or other deVices which
must be accessed by more than one microprocessor or microcontroller.
CSADIN is generated when the microcontroller is attempting to read data from Port
A in the track mode. It is generated from
one product term involving the address
inputs and the RD strobe (Intel mode) or
R/IN and E (Motorola mode). This allows
the user to configure the address range in
which the data is to be read from Port A.
CSADOUT1 is generated when the microprocessor is accessing a "tracked" address.
It is generated from a single product term
involving the address inputs and ALE.
When the address generated by the microcontroller is within the block specified by
the user for track mode, and the ALE is
active, CSADOUT1 becomes active, transferring the address and outputting it from
Port A. CSADOUT2 is generated when the
microcontroller is performing a write operation to a tracked address. It also has one
product term involving the address inputs
and WR (Intel mode) or R/W and E
(Motorola mode). When the microcontroller
performs a write to the appropriate
address, CSADOUT2 is generated, transferring the data and outputting it from Port
A. For further details on the operation of
the Track Mode, please consult Application
Note 017.

Byte Size Access of the UO Port Registers
Offset from the CSIOPORT

Pin Register of Port A

+ 2 (acceSSible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

--------------------------------~~~------------------------------1.--69

PS03XX - Application Note 014

Example:
Address
Mapping
With PAD A

In this example, we will choose a sample
address map which is similar to those used
in typical microcontroller applications. This
example assumes the use of a PSD301
device with 256 Kbits of EPROM and 16
Kbits of SRAM. Figure 2 below illustrates
our sample address map.
In this example, we have located the boot
code and interrupt service routines beginning at address 0000 in EPROM block O.
The SRAM is located in the 2K block beginning at address Ox1 000 and can be used
for the stack andlor other scratchpad data.
The 1/0 ports occupy the 2K block beginning at address Ox1800. Addresses in this
range will access ports A and B and their
control registers. The area from Ox2000 to
Ox8FFF is unused in this example, though
it could be used for external resources as
will be shown later. Finally, the main
program resides in the 28K block of
EPROM located from address Ox9000 to
OxFFFF and is selected by ES1 - ES7.

Figure 2.
Example
Memory Map

Configuring this memory map would
normally require designing a decoder to
generate the appropriate chip selects for
each given address range. For example,
assuming that a microcontroller with a 16bit address bus is used, the chip select for
EPROM bank 0 (ESO) would be generated
with the following equation:
ESO = IA12 ·/A13 ·/A14 ·/A15
Equations like this one would be formulated
for each of the chip selects, and the entire
function would probably be placed in some
kind of programmable device. When the
PSD device is used, PAD A replaces this
programmable device. Programming PAD
A to perform this function is a simple task
using WSI's Maple software.
Entering the ADDRESS MAP menu in the
Maple software running on a PC compatible computer, the user will see a screen
similar to the one shown in Figure 3.

FFFF

MAIN
PROGRAM

USING

9000

ES7
ES6
ES5
ES4
ES3
ES2
ESl

-

-

-

60
56
52
48
44
40
36

•
•
•
•
•
•
•

64K
60K
56K
52K
48K
44K
40K

8FFF

2000

1

lFFF

USING CSIOPORT -

1/0 PORTS
1800

17FF

SRAM

OFFF I-------~~---BOOT CODE &
1000

L-_IN_T_E_R_R_U_P_T_S_E_R_V_IC_E_-,

1j

USING

USING

6· 8K

RSO

-

4 • 6K

ESO

-

0 • 4K

0000

______________________________
1·70

f=E~~

='"'='==: =:

_______________________________

PSD3XX - Application Note 014

Example:
Address
Mapping With
Pad A (Cont.)

PADS

Upon displaying this screen, the Maple
software is ready for the user to enter the
memory map data. This is performed quite
simply by moving the cursor to the appropriate point with the arrow keys, and then
entering the appropriate data. The address
mapping may be entered in either of two
ways. First, the user may select each
address bit individually for each chip select
and enter a 0 or 1 as appropriate for the
equation desired. In our example, for ESO
we would enter a 0 in the columns for A 12,
A 13, A 14 and A 15. The other bits are don't
cares. In the other method of programming
the pad, the user simply moves the cursor
to the SEGMT START column and enters
the desired starting address for the block.
Again, using our sample memory map, the
user would move to the SEGMT START
column for ESO and enter 0000. Maple
Eleven of the PAD outputs and 27 of the
product terms are dedicated to PAD B.
Where PAD A was used to control the onchip PSD device resources, PAD B controls
any off-chip resources required by the
system. As with PAD A, all inputs to the
PAD are available to PAD B, allowing the
system designer to formulate outputs
involving any combination of address,
strobes and external signals. Unlike PAD A,
several of the outputs of PAD B have up to
four product terrns each.

Figure 3.
Maple Address
Map Entry

then automatically programs the O's and 1's
into the address bits correctly to program a
4K block of EPROM beginning at address
OxOOOO. Note that all EPROM blocks must
begin on 4K boundaries. Figure 3 shows
the resulting address map table for our
example.
The address inputs which were unused in
this example (A16, A17, A18 and A19)
could have been used as general purpose
inputs to the PAD for specialized control of
the on-chip memory and I/O resources.
When this is done, the designer has
complete flexibility as to the configuration
of the PSD device resources and may
easily absorb many system functions into
the PSD device. More detail about the use
of A 16 - A 19 will be provided later in
this note.
The outputs of PAD B are as follows:

o

o

CSO - 7 (Port B)
CS8 -10 (Port C)

The outputs from PAD B are brought to the
outside world through Port B and Port C.
These outputs are called chip selects,
though they may be used for any function
whatsoever. The port pins are configured
as selected by the user when the device is
programmed with the Maple output file.
There are many configuration options for
each port pin.

ADDRESS MAP
A

A

A

A

19 18

17

16 15 14 13 12

11

SEGMT
START

SEGMT
STOP

X
X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

X
X
X
X
X
X
X
X
X

N
N
N
N
N
N
N
N

0000
9000
AOOO
BOOO
COOO
DOOO

OFFF
9FFF
AFFF
BFFF

A
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

X
X
X
X
X
X
X
X
X

x x x

A

A

0
0
1

0
0
0

1
1

0
1

1
1
1
0
0

1
1
1
0
0

A
0
0

A

1

0
1
0
1

0
0
1
1
0
0

0
1
0
1
1
1

1

0
1

EOOO
FOOO
1000
1800

FILE
START

FILE
STOP

FILENAME

CFFF
DFFF
EFFF
FFFF
17FF
1FFF

ALIASES:
Fill in A19 - A11 (Binary) or SEGMT START (Hex): and FILE (START, STOP)
and FILE NAME, Use SPACEBAR to erase any field value.
F1 - Return to Main Menu
F2 - Temporary Exit to DOS
F3 - Go to Help
Cursor - UP: t
Down: ~ Left Col: ~ Right Col: -+Right - F4 Left - F5

=-~~ .:=:~

-------------------------------------~.;'~----------------------------------1--7-1

PSDaxx - Application Note 014

PADB
(Cont.)

Table 2.
Sample Port
Configuration

Example:
Generating a
Logic Equation
WithPADB

If you require more information about port
configuration, please consult application
note 011. If the port outputs are
configured as chip selects (outputs from
the PAD), they may not be used for any
other purpose. For example, the three Port
C signals may be configured as chip
selects (outputs) or addresses (inputs) but
cannot be both. Fortunately, the flexibility of
the PSD device and the Maple software
allows the designer to configure each Port
Band C pin individually, so that the number
of outputs and inputs may be optimized for
a particular design requirement. See Table
2 below for an example of this flexibility.

Pin

This sample port configuration demonstrates all of the possible uses of a particular port pin. Though only Ports Band C
may be inputs or outputs tolfrom the PAD,
Port A is included in the table for completeness. In this example, five of the port pins
are configured as PAD outputs (CS) and
two are configured as PAD inputs (A). The
remaining port pins in this example are
configured as either 1/0 or address outputs.
Several of the CS outputs have been
configured as open drain. This allows them
to be connected together in a wired OR
configuration to increase the number of
product terms even further if desired.

Configuration

PAO
PA1
PA2
PA3
PA4
PAS.
PA6
PA7

Address
Address
Address
Address
1/0
1/0
1/0
1/0

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

CSO
CS1
CS2
CS3
1/0
1/0
1/0
1/0

PCO
PC1
PC2

A16
A17
CS10

Assume that it is necessary to generate the
following equation given the port configuration in Table 2 above. This equation is a
simple OR of three product terms.
CSO =A15 ° A14 o/A13 °/A17 ° RD
+ I A15 ° A14 ° A12 ° WR + A16
Figure 4 illustrates the Maple programming
sequence to generate this equation.
To program this equation, the PORT B
menu is entered from the Maple software.
CSO is selected by moving the cursor to it
using the arrow keys. With CSO selected,
the user then presses the F3 key to bring
up the CHIP SELECT DEFINITION table
for CSO. The table contains four rows for

Out
Out
Out
Out

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS

00
00
CMOS
CMOS
CMOS

00
00
CMOS
CMOS
CMOS
CMOS

-

-

00
data entry, each one corresponding to one
of the available product terms for CSO.
Implementing this equation required using
three of the four available product terms.
The fourth is left blank and will not be used
to generate the output.
To enter the equation into the table, simply
move the cursor around into the appropriate position and enter a 1 if the corresponding Signal should be high for the
equation to be true, 0 if it should be low,
and X or SPACE if the signal is a don't
care. The first term of the equation requires
a low on A17, a high on A15, a high on
A14, a low on A13 and a high on RD for the
term to become active. Thus, 1's are
placed in the A15, A14 and RD positions,

----------------------------~Jr~---------------------------1-72

PSD3XX - Application Note 014

Example:
Generating a
Logic Equation
WithPADB
(Cont.)

Figure 4.
Programming
PAD Outputs

Four product terms are available on each
of the CSO - CS3 outputs, two terms are
available on the CS4 - CS7 outputs and
one term is available on CS8 - CS10.
When planning the use of the PAD outputs,
it is important to consider this so that the
most efficient use of the product terms can
be achieved.

and a's are placed in the A17 and A13
positions. The remaining terms in the
equation are entered in the same way.
Note that A 17 and A 16 in this example
(as well as A19 and A18) need not be
address bits, but may instead be used to
bring external signals into the PAD.

PORTS
PIN

CS/IIO

CMOs/OD

PBO
PB1
PB2
PB3
PB4
PB5
PB6
PB7

CSO
CS1
CS2
CS3
CS4
CS5
CS6
CS7

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT DEFINITION CSO

A19 A18 A17 A16 A15 A14 A13 A12 A11 ALE RD WR
X
X
0
X
1 1 0
X
X X
1 X
X
X X X
1 X 1
X X
X 1
0
X
X X
1 X X X X X X
X X

ALIASES:
CS definition is the NOR of the product terms (rows). Enter 1 to select Active High signal,

oto select Active Low signal, X to mean "don't care", SPACEBAR to erase. Enter values
in columns relevant to your application; other blank columns will be treated as
"don't cares".
F1 - Retum to PORT B

Application
Examples

Cursor - Up: t

The following section will illustrate the use
of the PAD for system logic replacement in
some common microcontroller applications.

Basic Chip Select Generation
One of the simplest uses of PAD B is
the generation of chip selects for off-chip
resources such as 1/0 devices or
memories. Figure 5 below depicts the
connection between a 68HC11
microcontroller, the PSD301 and two
common peripheral devices: the 8250
UART and the 8254 counter/timer.
The 68HC11 is an 8-bit microcontroller with
a 16-bit address bus. The lower 8 bits of
address are multiplexed with the data bus
while the upper 8 bits are transmitted on
their own bus. An address strobe (AS) is
provided to latch the address off of the
multiplexed bus. A RtW signal indicates
whether the current bus transaction is a
read or a write (R/W = 1 = read, RIW =0 =

Down: ,

Left:...

Right:-+

write). The E signal is the clock used
to strobe the data in or out of the
microcontroller. The PSD301 can be
configured to exactly match this signal
definition and then connected as shown in
the diagram. Not all of the 68HC11 or
PSD301 Signals are shown, only those
relevant to this example of PAD capability.
The 8250 is a UART device commonly
used in microcontroller systems to provide
a serial data communication port. It has a
simple bus interface, yet does not directly
connect with the 68HC11 bus architecture.
It requires an 8-bit bus to transfer data to
and from the microcontroller and a
separate 3-bit address bus used to access
its internal registers. It also requires a chip
select and separate read and write strobes
(RD and WR). The chip select is generated
by decoding the address from the microcontroller. The RD and WR signals may be
generated from the RtW and E signals

------------------------------~Jr~----------------------------1.-~

PS03XX - Application Note 014

Figure 5.
A Typical
Microcontroller
System

PSD301

68HC11

pco

INS8250

~
~
~
" ~

AOO
AOl
A02
A03
A04
A05
A06
A07

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

AS
A9
Al0
All
A12
A13
A14
A15

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

E
R/W

E

PCO f - - PCl r---

PCl
PC2
PC3
PC4
PC5
PC6
PC7

I
I
I
I

~~
~~
~~
~~

'\

'\
'\

00
01
02
03
04
05
06
07
AO
Al
A2
CS2
RO
WR

8254
AS

RIW
AS

PC2~

~

8=

~
~

00
01
02
03
04
05
06
07
AO
Al
RO
WR

cs

Application
Examples
(Cont.)

according to the following equations:
/RD = /(R/W • E)
/WR = /(/R/W • E)
These equations may be easily generated
using PAD B and sent out through two of
the chip select outputs. We have chosen
CS5 and CS6, which come out on PB5 and
PB6, for this example.
In order to provide the address lines to the
8250, we have configured Port A to output
the latched address. This eliminates the
need for any external latches to demultiplex
the address/data bus from the microcontroller. Though all eight of the Port A pins
have been configured as address outputs
in this example, it is possible to configure
only those address bits required for the
application, AO - A2 in this example, and
configure the remaining Port A pins as
general I/O.
The 8254 is a programmable interval timer

which, like the 8250, is a peripheral used in
many microcontrolier applications. Its bus
connection is very similar to the 8250,
allowing it to use the same read and write
strobes (RD and WR) and address lines. It
also requires a chip select which is
decoded from the microcontroller address.
The chip selects for both of the peripheral
devices may be easily decoded from the
address inputs to PAD B. Normally, the
addresses which are inputs to the PAD
(A 11 - A 19) would give decoding resolution
down to 2K. This means that each of the
two peripheral devices that require chip
selects would be allocated an address
range of at least 2K. Since these devices
do not require this much space and the
68HC11 has only a 16-bit address bus, it is
possible to use the high order address
inputs of the PSD device to improve the
decoding resolution. To achieve this goal,
we have configured Port C as address
inputs A 16 - A 18, but have connected
them to A8 - A 10 from the microcontroller.
This means that the PAD will now have

f~~AF~------------------------------------.,.-"------------------"---------------'fttFE!!IE

-1•

PS03XX - Application Note 014

Application
Examples
(Cont.)

access to A8 - A15 for decoding, thus
providing a resolution of 256 instead of 2K.
This could actually be further reduced to a
resolution of 128 if we were to configure
the A 19/CSI input to be A 19, and then
connect it to A7 from the microcontroller. In
this example, we have not done this so that
CSI is still available to place the PSD301
into low power mode if required.
We now have to define the addresses of
each of the peripherals so that the chip
select equations may be defined. We will
start from the memory map provided earlier
in Figure 2. This map allocated all of the
internal resources of the PSD device. The
external peripherals may be easily added
to the unused area between addresses
Ox2000 and Ox8FFF. Figure 7 depicts the
new map with the external devices added.
Notice that the internal resources can keep

Figure 6.
Memory Map
With Peripherals

their original address mapping even though
the additional address inputs (A8 - A 10)
have been added. This is because these
inputs may be don't cares in the decoding
for the internal resources even when they
are being used for the external resources.
Now, to wrap up this simple design, we
must enter the configuration and mapping
information into Maple. The configuration of
the PSD device must be consistent with the
operation of the 68HC11 microcontroller.
The address/data mode must be mUltiplexed, the data bus must be 8 bits wide,
CSI/A19 may be configured either way, the
reset polarity should be active low, the ALE
polarity is active high, the read and write
lines must be RfiiJ and E, A 19 - A 16
should be latched so that these bits
become available just like the rest of the
address bus, and the read strobes for the

FFFF

MAIN
PROGRAM

USING

8000
7FFF
7000
6FFF

6000
5FFF
5000
4FFF

PERIPHERAL # 3
1 WS

ES7
ES6
ES5
ES4
ES3
ES2
ES1
ESO

60
56
52
48
44
40
36
32

USING CS7

-

64K
60K
56K
52K
48K
44K
40K
36K

28 - 32K

1-----------

PERIPHERAL # 2
6 WS

USING CS6

-

24 - 28K

PERIPHERAL # 1
3 WS

USING CS5

-

20 - 24K

USING CSIOPORT -

18 - 20K

-

16 - 18K

I/O PORTS
4800
47FF

SRAM
4000
3FFF

I

USING RSO

80C196KB
INTERNAL RESOURCE

0000

-------------------------------------f~~aF~-------~g§

____________________________
1-75

PSD3XX - Application Note 014

Application
Examples
(Cont.)

SRAM and EPROM will be the same. This
configuration should be entered from the
configuration menu of the Maple software.
The address map programming for this
example will remain the same as the one
used earlier in Figure 3. The only items
remaining are the programming of the ports
and the generation of the equations for the
chip selects and read/write strobes. First
we must configure Port A to provide the
latched address to the peripherals. This is
accomplished by entering the PORT A
menu in the Maple software. Maple will
then ask you if you would like Port A
configured for address 1/10 or the Track
Mode. For this example, we will use the
address/I/O configuration. Next, Port A
must be configured pin for pin as an
address output. This is easily performed by
using the cursor keys to select the appropriate pin and pressing the SPACE BAR to
change the configuration. It is also possible
to configure each pin as an open drain or
CMOS output, but for address outputs, it is
better to make them CMOS.

Wait State
Generation

Lastly, we must configure the Port B
outputs to become the chip selects and
read/write strobes. First, the PORT B menu
must be entered. Now, we must configure
each pin as an I/O or CS output.
PBO - PB3 may be configured as general
purpose I/O pins. PB4 - PB7 must be
configured as chip selects. Once configured as chip selects, the equations for each
output may be entered by following the
Maple instructions. The procedure is the
same as the one used in the earlier chip
select example. Our equations, including
the ones developed earlier for the read and
write strobes, are defined for each output
as follows:
PBS

=/CS5 =/RD =/(RIW • "E)

PB6

=/CS6 =IWR =/(/RIW • E)

PB4 =/CS4 =/8250CS = /(/A15· /A14·
A13· /A12· /A11 • /A18· /A17· /A16)
PB7 =/CS7 =/8254CS = /(/A15· /A14·
A13· /A12· /A11 • /A18· /A17· A16)

Now, PORT C must be configured to
provide the three additional address inputs.
This is performed by entering the PORT C
menu in Maple and selecting the appropriate pin with the cursor. Each pin should be
configured as an address bit (Ai). Maple will
call the pins A 16 - A 18 even though we will
be using them as A8 - A 10.

This completes the design integrating these
four components with no additional logic
whatsoever. There is also additional space
in the PAD for more functions if necessary,
so we have not yet reached the limit of the
integration possibilities with the PSD301.

Often, when using some of the newer highperformance microcontrollers with slower
extemal peripherals, it is not possible to
complete a read or write cycle to the
peripheral in the time allowed by the microcontroller's minimum bus cycle. In this
case, one or more wait states must be
added to slow the controller down to the
speed of the peripheral. One way of doing
this is to fix a number of wait states for all
bus cycles to al!ow the slowest device
enough time for its access. Some
controllers even provide the capability to do
this intemally through the programming of a
register. This works, of course, but can
severely impact the performance of the
system. There is no need to penalize the
performance of the entire system, which
can include zero wait state memory
devices and other peripherals, simply
because one or more of the extemal

devices requires some number of wait
states. It is possible, with minimal logic, to
create a completely programmable automatic wait state generator using the
PSD301 which will allow the fast resources
to operate at zero wait states and still
provide from one to eight wait states for the
slower resources.
For this example, we will use an Intel
80C19SKB microcontroller running at 12
MHz. This controller has the capability to
operate in a 16-bit data mode, providing
the opportunity to further increase performance if the system can also operate in
this mode. The PSD301 does have the
capability of operating in the 16-bit mode,
making it a good match for the 80C1 96. We
will assume that the 80C1 96 must be interfaced to several slow 8-bit peripherals
requiring from one to eight wait states. With

-------------------------------------f==~~------------------------------------­
=''='=:: =
1-76

PSD3XX Application Note 014

Wait State

Generation
(Cont.)

the PSD301 , we can provide the correct
number of wait states for each peripheral
with the added capability of dynamically
sizing the bus to the appropriate width for
the current access.
The memory map we will use for this
design is depicted in Figure 6. The internal
resources of some BOC196 derivatives
occupy most of the address space from
OxOOOO to Ox3FFF, though some have less
resources. Therefore, we have constructed
the memory map to place the PSD device
resources above address Ox4000. The
PSD301 SRAM and 1/0 devices occupy
from address Ox4000 to Ox4FFF. This
leaves the area from Ox5000 to Ox7FFF for
external peripherals while leaving OxBOOO
to OxFFFF for the EPROM banks. We
assume that we must connect three external peripherals to the PSD device using
this address space, one requiring one wait
state, one requiring three and one requiring
six. This memory map is entered into the
part similarly to the previous examples.

To achieve the variable number of wait
states, the ideal solution is to decode the
address to determine the number of wait
states required for a particular address
range, and then to use a counter to count
the appropriate number. By using the PAD
to initialize an external counter, a variable
wait state counter can be created in this
manner. This wait state generator requires
only one external device, a 74FCT191
counter. The circuit used to implement this
function is illustrated in Figure B. The
BOC196KB is directly connected to the PSD
device which in turn provides the three chip
select signals for the external peripherals
(PER1CS, PER2CS and PER3CS) as well
as the wait state generator function and the
dynamic bus sizing. Ports Band C are fully
utilized to provide the logic inputs and
outputs required to implement these functions, while Port A is still available for
general 1/0 or address use.
This circuit uses PAD B to decode the
addresses driven by the microcontroller

PSD3XX - Application Note 014

Wait State
Generation
(Cont.)

Figure 8.
Wait State
Generation
Circuit

and provide four outputs, based on these
addresses, which are used to initialize the
74FCT191 counter with its initial value. The
counter is initialized using ALE to latch
these four PAD outputs. The load signal for
the counter is active low, however, while
ALE is active high, so ALE is inverted using
PAD B and sent out through Port C.
Though the 80C196KB can be configured
to provide an active-low address strobe,
ADV, the timing of the signal is inappropriate for use as the LOAD input to the
counter. Once the counter is initialized, it
counts up from the initial value until the
most significant bit increments from 0 to 1.
The output of the most significant counter
bit is routed to the READY input of the
microcontroller. Thus, the controller will be
held in wait states until the most significant
counter bit is incremented. This output is
also routed to the CTEN signal of the
counter so that counting will cease once
the READY signal has been issued to the
controller. The clock for the counter is an
inverted version of the CLKOUT signal
from the controller. This clock must be
inverted since the 80C 196KB uses the
falling edge of the clock to sample the

READY input. PAD B again provides the
inversion function by routing CLKOUT
into one of the Port C pins, inverting it
and routing it back out through another
Port C pin.
The counter provides from zero to eight
wait states depending on the initialized
value. For zero wait states, the most significant counter bit is initialized to a "1", which
provides the READY signal to the controller
immediately and disables the counter from
incrementing. If one wait state is desired,
the counter is loaded with the value 7 (0111
binary) so that after it increments once, the
most significant bit switches to a "1" and
provides the READY to the controller.
When two wait states are required, a 6
(0110 binary) IS loaded into the counter,
and so on for the rest of the wait state
values.
To properly size the bus to the appropriate
width, PAD B is again used to decode the
addresses of the 8-bit devices. When the
address of an 8-bit device is encountered,
the BUSWIDTH signal is driven to
configure the 80C196KB address to eight

PSD301

80C196KB
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7

ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7

PAD
PAl
PA2
PA3
PA4
PA5
PA6
PA7

ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7

ADS
AD9
AD10
ADll
AD12
AD13
AD14
AD15

PBO
PBl
PB2
PB3
"PB4 t---- PERl CS
PB5 t - - PER2CS
PB6 t---- PER3CS ~
PB7

RD
WR
ALE
BHE
CLKOUT

1l

BUSWIDTH
READY f--

RD
WR
ALE
BHE

} GENERAL
PURPOSE
ADDRESS OR 1/0

74FCT191

JrI

pco
PCl
PC2

OA
OB
OC

00
CTEN
__
LOAD
D~

CLK
DIU

r--

I

-----------------------------------f==~~------------~--------------------1-78

==-~=::

==

PS03XX - Application Note 014

Wait State
Generation
(Cont.)

bits. For all other addresses, the width is
set for 16 bits. The BUSWIDTH signal is
output from one of the Port B pins.
The PSD device must now be configured to
provide the functions required by the
example circuit. The configuration of the
PSD must first be programmed to function
with the 80C196KB. This is easily
performed by the Maple software as in the
previous example. The address/data mode
should be multiplexed, the data bus width
should be 16 bits, CSI/A19 may be
configured as required for the application,
the reset polarity should be active low, the
ALE polarity should be active high, separate AD and WR strobes should be used
and A 19 - A16 should be transparent, not
latched, since they are used as logic inputs
to the PAD.
Next, we must program the functionality of
Port C. For this example, PCO and PC1 are
used as outputs from the PAD to provide
the LOAD and CLK Signals for the '191
counter. This is performed by entering the
PORT C menu in Maple and configuring
PCO and PC1 as CS8 and CS9, respectively. PC2 is used to input the CLKOUT
signal from the microcontroller to the PAD
so that it may be inverted. Therefore, it
must be configured as address input A18.
Now, the equations used to generate the
PCO and PC1 outputs must be entered into
the PAD. PCO is the LOAD signal which is
just the ALE input inverted. PC1 is an
inverted version of A18, which contains the

Tablea.
Wait State
Summary

CLKOUT signal. These equations are listed
below:
PCO = /LOAD = /ALE
PC1 = /CLKOUT = /A18
The equations are programmed by entering
the CHIP SELECT DEFINITION menu for
each of the two chip selects, as in the
previous example, and entering the appropriate 1's, O's and DON'T CARES. In the
case of PCO, there are don't cares in all of
the PAD inputs except ALE, where there is
a O. Similarly, for PC1 , the A18 input is a 0
while the rest of the PAD inputs are don't
cares.
Port A is usually configured next, and in
this example it is free to be configured in
any mode necessary for the application. It
may become either I/O or address outputs,
or may be set in the Track Mode as
described earlier.
We are now ready to configure Port B. This
example requires that all of the Port B pins
be used as chip selects (logic outputs) from
PAD B. PBO - PB3 are used to initialize the
counter with the correct number of wait
states for each device. These outputs are
defined according to the address ranges for
each of the peripherals and the number of
wait states required for each. Table 3
summarizes the outputs required for each
peripheral so that we may define the
correct equations for the outputs.

Peripheral No.

Address Range

No. Wait States

PBD-PB3

1
2
3

Ox5000-5FFF
Ox6000-6FFF
Ox7000-7FFF

3
6

1010
0100
1110

------------------------------~~Ar----------------------------1·79

PSD3XX - Application Note 014

Wait State

Generation
(Cont.)

This table can be easily used to form the
necessary equations for PBO - PB3. PB3
can be considered the enable for the wait
state generator which is active low only in
the address ranges of the three peripherals. It must remain high for all other
address ranges. The other three outputs
simply encode the proper number of wait
states. The resulting equations are listed
below:
PBO

= lOA =I(A15 ° A14 ° A13 o/A12)

PB1 =/OB=/(A15°A14°/A13°A12)
PB2 = IOC = I(A15

° A14 ° A13 o/A12)

PB3 = IOD = I(A15 ° A14 o/A13 ° A12 +
IA15 ° A14 ° A13 °/A12 + IA15 ° A14 °
A13 ° A12)
PB4 - PB6 are used as chip selects for
each of the three peripherals and are
simply decoded from the address inputs by
PAD B corresponding to the address
ranges listed in Table 2. These equations
are listed below:

Conclusion

PB4 = IPER1CS = I(A15
IA13 ° A12)

° A14 °

PB5 = IPER2CS = I(A15
A13 0 1A12)

° A14 °

PB6 = IPER3CS = I(A15
A13 ° A12)

° A14 °

The PSD device may be used in a variety
of applications requiring the simplicity,
space savings and performance possible
by the integration of memory and
programmable elements. But a significant
portion of the value of the PSD device, is
its ability to absorb much of the logic
functionality which normally surrounds a

Finally, PB7 is used to perform the bus
sizing function. It should be sized to eight
bits whenever any of the external peripherals is accessed. It should be sized to 16
bits for all other accesses. The 80C196KB
requires a high on the BUSWIDTH input for
16-bit operation and a low for 8-bit operation. This is accomplished by the equation
below:
PB7 = BUSWIDTH = I(A15
IA15 ° A14 o/A13 ° A12)

° A14 ° A13 +

This completes the equations for Port B.
These equations are entered in the Maple
software by selecting the Port B chip select
definition screens as described in the previous example and entering 1's and O's in the
appropriate locations. Remember that don't
cares (X's or blanks) must be entered in all
inputs which are not used by a particular
equation.
Finally, we must enter the memory map
into Maple Address Map screen. This is
performed as in the previous example by
entering 1's, O's or don't cares in the appropriate places.

microcontroller application. The
programmability of the device allows the
designer to make changes to both the
software and the design itself as required.
This is not possible with masked ROM or
ASIC-based designs. The PSD device can
truly turn a microcontroller into a complete
two-chip solution.

IF • • .EE1fff _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

-,-~-O----------------~~·

Programmable Peripheral
Application Note 015
Using Memory Paging with the PSD3XX
By Jeff Miller

Introduction

The PS03XX is a compact, high
performance microcontroller peripheral
used to extend the capabilities of a
microcontroller in a space-limited
embedded control system. It provides the
programmable logic, memory and I/O
requirements needed by most microcontroller designs in a single small package.
The PS0301 , introduced in November
1990, was the first of a six-member family
of devices providing varying amounts of
on-chip resources. The PS0301 contains
32K Bytes of EPROM for program storage
and 2K Bytes of SRAM scratchpad
memory. As the family expanded, the
EPROM memory size grew to 128K Bytes
in some versions. This large memory may
be needed in many applications requiring
large feature sets. In many cases the

What is
Paging?

The primary purpose of a page register is
to extend the width of the address bus by a
number of bits to increase the size of the
address space. These bits are added to the
address bus as outputs of a register which
is loaded from the data bus of the MCU.
Each additional bit doubles the effective
address space. Though the page register
address bits increase address space, they
are not the same as the true address bits
which are generated by the microcontroller
since they do not appear with the same
timing or sequence of the address. They
must be controlled carefully to avoid
unexpected behavior. They can also be a
problem for compiler-generated code since
the compiler does not inherently know how
to use a page register. Because of this,
the designer must take care in designing
software which uses the PS03XX page
register.
The purpose of this note is to explain the
usage of the page register and some of the
techniques which may be used when
designing software which uses the page
register. A typical page register design
is shown in Figure 1. In the figure, a
typical 8-bit microcontroller with a
multiplexed address/data bus is shown

microcontroller is capable of addressing
only 64K Bytes of memory with its
limited 16-bit address bus. In these
applications, the designer is often faced
with the difficult choice of eliminating
features, using a more expensive
microcontroller with a wider address bus,
or adding external paging logic requiring
several extra components.
With this in mind, designers at WSI have
included a simple but very effective paging
system in the PS03XX models containing
more than 32K Bytes of EPROM. This
enables cost effective microcontrollers like
the 80C31 , 80196, Z80, 68HC11 and
others to take full advantage of additional
memory without any additional hardware or
design effort.

connected with the logic required to
implement a 4-bit page register. The least
significant address bits are demultiplexed
from the data bus by the '573 transparant
latch, which is clocked by the ALE signal.
The most significant 8-bits of address are
driven directly by the microcontroller. When
combined with the least significant address
bits from the address latch, the address
bus is 16-bits wide. This provides the
capability to directly access 64K Bytes of
address space, which may be any
combination of program and data storage.
To implement more address space, two '74
devices (a dual Ootype flip flop) have been
used to create a page register. The inputs
of the '74 are four bits of the address/data
bus. These bits are stored into the '74
when a write to a specific address, as
decoded by the '138, is performed by the
microcontroller. The outputs of the '74
form an additional 4 address bits, thus
extending the address bus to 20-bits or 1
MByte of address space. The '74 page
register can be considered to hold
a page number. Each page number
provides a complete duplication of the
microcontroller's memory space. To get to
another 64K Byte page of address space,

---------------------------------------~~~-------------------------------------====

1·81

PSlJ3XX - AppllcatlDn NDte 015

What is
Paging
(Cont.)

the controller simply has to change the
page number by writing a different value to
the page register.
The circuit below has one major
complication. If the microcontroller is
currently in a particular memory page, page
X, and it changes the page number to Y
using a store instruction which it fetched
from page X, as soon as the store is

complete the next instruction fetched will
come from page Y. This means that page
Y must pick up the programming sequence
exactly as it was left off from page X. This
is a complication that must be handled in
software and can make programming very
difficult. Additionally, interrupts can be a
significant problem since they must force
the program to an interrupt vector which
may exist on a different page.

Figure 1.
Discrete Page
Register
ADO:7

'573 ~

-

2X
'74

~

ALE

MCU
A8:15

.....

(AO:19)

WR
'138

ThePSD3XX
Implementation

Figure 2 illustrates the block diagram of the
PSD3XX with the internal page register. It is
similar to the discrete circuit above, but with
some important differences. The page
register provides 4-bits of additional
addressing capability, but does not provide
them directly to the memory devices themselves. Instead, the page register output
bits are taken into the Programmable Array
Decoder of the PSD3XX. This enables the
user to program them as necessary for the
system design.
The PAD provides a flexibility that most
page register implementations are not
capable of providing. If you are unfamiliar
with the capabilities of the PSD3XX PAD,
please consult Application Note 014, Using
the PSD3XX PAD for System Logic
Replacement. Figure 3 illustrates the PAD

logic in a PSD3XX with a page register. The
PAD generates the outputs which are used
to select the PSD3XX's eight EPROM
blocks, the SRAM block, the 1/0 ports, the
shared resource interface, the page register
itself and all external functions which use

the chip selects provided by Port Band
Port C of the PSD3XX. Thus, the page
register bits may be combined with the
address bits and control signals in any
combination to generate the select signals
for all of the above resources. In addition,
any or all of the page register bits may be
don't cares in any or all of the PAD chip
select equations, enabling the user to
select which resources may be selcted
from which page, or to select some
resources from any page. This extremely
useful feature enables the programmer to
avoid the problem of software continuity
between pages described above by making
at least one of the EPROM blocks appear
in all pages and then using that block to
contain code for interrupt servicing and
page switching. This is performed simply
by making the page register bits 'don't
cares' in the chip select equation for that
block. All of this is fully programmable with
the PSD3XX, enabling the designer to
choose the paging scheme that is best for
the application.

---------------------------~Jr~--------------------------1-82

PSD3XX - Application Note 015

Figure 2.

PSD3XX

Architecture

PAGE LOGIC
P3-PO
L
A
T

AD8-AD15

~

A8-A10
A19

c

CSI

H

ALE/AS

.-ALE/AS

L
A
T
C
H

ADO-AD7

A16-A18

PAD A

RD
WR
RESET

13 PT

27PT

~

tEso~
-------.

r-

~~

r;6i8
~

"----

J4-

.-

'i~[>

1+

-

PROG
PORT
EXP
PCOPORT
C

~

CS8CS10

EPROM
256K BIT -1 M BIT

ES7
ES6
ES5
ES4
ES3
ES2

'---

PAD B

ALE/AS

RD

1-

LOGIC IN

CSI

- --

~!

CSIOPORT
A19

WR
RESET

L--

'+

~F

A11-A15

.....
CSOCS7

32K-128K BIT
BLOCK

r

D8-D15

~

PROG
PORT
EXP
PBOPORT
B

~

"----

CSIOPORT

r-

L....-.

 f.-

I-

--

DO-D7

1-

"----

~

SRAM
16K BIT
TRACK MODE
SELECTS

AO-A7
ADD---AD7/DO-D7

PROG
PORT
EXP

PORT
A

PAOPA7

~

ALE/AS

-

PROG CHIP
CONFIGURATION

t

-

RD/E
-

WR/RIW
BHEIPSEN
RESET

PROG
CONTROL
SIGNALS

X8, X16
MUX or NON-MUX BUSSES

A19/CSI

--------------------------------~~~~------------------------------1--8-3

PSD3XX - Application Note 015

ThePSD3XX
Implementation
(Cont.)

Figure 3.
PSD3XXPAD
Diagram

The Microcontroller can write or read the
page register to place a new page number
in it or read the current page number. To
perform this, the microcontroller must
simply access the address programmed in
the PAD for the page register. This address

II

I

~

i

is based on the CSIOPORT select signal
programming. If address 8000 hex is
programmed for CSIOPORT, the
corresponding page register address is
8018 hex and read and write data will be to
and from the page register.

I

1tI.

~~

- j ) - - - ESO

,I

P,

"

I

~

....

I

--_.

--D-- ES4

'S

v

!

k+

1-

~

ALEorAS

'S

v

- ESl
ES2

- - ES3

c-

Po

--

---0---

,

I

,

"

~

-

-[)----

ES7
RSO-S RAM BLOCK SELECT

I'

I

V

CSIOPORT CSADIN

-

orRIW

._-

~
II1111

--{)--- CSADOUTl
-- -{)---- CSADOUT2

il

_~'.9... ~

~-~

}

--~L>~

-ft

A17

PAD
A

H

DorE

---

SELECT LINES

ES5
ES6

I I

I

I

8 EPROM BLOCK

II

"-

--,?-

---]

--

A15

,,~

....

I

CSO/PBO

CS1/PBl

--{}--D-

I

CS2IPB2

CS3/PB3

-j)-~=D-

if]

. .-q ~H

---0----

CS4/PB4

PAD
CS5/PB5

B

I
CS6/PBS

A12

--v

i

"
-:;:;

.

All

v

-

I

t!

,

~

'S

CSI_-.

.~-

I

CS7/PB7

CS8IPCO

,

I

I

-RESET

-

"

I-j

A14

A13

TRACK MODE
CONTROL SIGNALS

.--

A16

--

110 BASE ADDRESS

I
I

I

II
II

I

II

1.1

-{>o--

CS9/PCl
CS10/PC2

-1--8~4---------------------------~~~~---------------------

PSD3XX - Application Note 015

A Simple
Paging
Example

To illustrate the operation of the PSD3XX
page register, assume that a designer
requires a full 128K Bytes of program
storage space, 32K Bytes of buffer SRAM
and three peripheral devices which also
must be memory mapped. We can also
assume that the required program is easily
broken into four modules which are
somewhat independent, but do need the
capability to call one another and must be
able to pass global data among one
another. Further, assume that the
external peripheral devices may be
selected from three of the four modules,
but must not be accessed from the fourth
for security reasons. Lastly, assume that
the designer is constrained by cost and
compatibility considerations to use an 8-bit
microcontroller with a 16-bit address bus
(in this example, an 8031).
These requirements may be easily
implemented using the PSD313 device.
The PSD313 is an 8-bit device with
128K Bytes of EPROM for program
storage. It also contains the PAD and page
register logic described above. The
memory map required for this application is
shown in Figure 4.
The memory map shown utilizes the page
register to provide a unique address for all
of the PSD313's 128K Bytes of EPROM in
addition to the SRAM and peripherals. This
memory map consists of four pages of 64K
Bytes each. The map is further divided into
program and data space by the PSEN and
RD signals which are available in the 8031
microcontroller. This enables the PSD313
to overlap the addresses of the EPROM,
1/0 and SRAM. The pages are numbered
o - 3, and are written into the page register
by the microcontroller. The page register is
part of the 1/0 addressing and resides in
the RD = 0 map.
The software must be broken into four
segments, one residing in each page, in
order to function efficiently with this
memory scheme. The software which
enables the machine to boot, service
interrupts and switch memory pages is
located in a block of EPROM which is
mapped into all memory pages. This
enables simple page switching and
interrupt servicing regardless of the page
that the microcontroller is currently
operating in. Locating an EPROM block in

multiple pages is very simple using the
PAD 'don't care' feature. In this example,
EPROM block 0 has been chosen to hold
the page-independent software. The PAD
output which controls block 0 is ESO.
Therefore, in the definition of the ESO
signal, all four of the page register bits
(PO - P3) are programmed as 'don't cares'.
ESO is further defined to be from address
0000 to 3FFF. Thus, whenever the
microcontroller places an address on the
bus which is in this range with PSEN low,
the data will be read from EPROM block 0,
regardless of the contents of the page
register.
The remaining EPROM blocks are evenly
distributed into the four pages. This
segmentation has been used in this
example, but there is no requirement that
the pages contain equal memory sizes.
Each can have a different amount of
resources contained within it. We have
placed EPROM blocks 1 and 2 in page o.
This is done by requiring PO - P3 to be O's
to generate the ES1 and ES2 selects.
Similarly, ES3 and ES4 in page 1, ES5 and
ES6 in page 2 and ES7 in page 3 require
the PO - P3 signals to be in the correct
states to generate the ES signals.
The SRAM and 1/0 devices most likely
must be accessible from all pages, like the
page switching software and interrupt
service routines. In this way, each of the
program segments may store and load
data from the SRAM which may be used to
pass global parameters among the
programs. All programs may also
communicate with the external 1/0 devices,
which is most likely required. It is very
important that the internal PSD3XX 1/0
registers, which include the 110 port control
and data registers as well as the page
register itself, be mapped into all pages.
Otherwise, after the page has been
switched, there will be no way of switching
back to the original page since the page
register would not be accessible. To rnake
the page register accessible from all
pages, the designer must simply make the
page register bits (PO - P3) 'don't cares' in
the equation for the CSIOPORT signal.
This can also be done for any of the
external chip select equations which are
generated by the PAD and brought to the
outside world through Port B or Port C.

--------------------------------~~~~------------------------------1---85

PS03XX- ApplicatlDn NDte 015

Figure 4.
Memory
Map
PSEN = 0

---------PROGRAM
#4

}

RD=O

CSIOPORT

ES748-64"

RSO
PAGE 3

l_E_S_O_~: ~~~
PROGRAM
#3

}

}

SRAMCS 0 - 32K

CSIOPORT

ES632_64K
ES5

RSO

PAGE 2

} _

PROGRAM
#2

}

J~=

ExtCS1
ExtCS2

:~~_O_~ ~~~

SRAMCS 0 - 32K

CSIOPORT

ES432_64K
ES3

RSO

J~s,

PAGE 1

ExtCS1
ExtCS2

l_~~O_~~!~~
PROGRAM
#1

}

SRAMCS 0 - 32K

CSIOPORT

ES232_64K
ES1

RSO

PAGE 0
EXTERNAL
CHIP SELECTS

l_~~o_~ ~ _1~~
ifIi Ji! !!!'.

1-86

fIIl§

EXTERNAL
SRAM

JE~1

ExtCSO
ExtCS2

SRAMCS 0 - 32K

PS03XX - Application Note 015

A Simple
Paging
Example
(Cont.)

If it is desirable for some pages not to have
access to some resources, this may be
done also. The designer must simply use
the page register bits in the equation which
selects the resource which is to be
protected. This can provide a program
security or error handling feature while
protecting certain liD or memory devices
from accidental corruption.
Figure 5 contains the output of WSi's
Maple software for the above example.
The part chosen to implement the sample
design was the 8-bit only PSD313, chosen
because it contains the required 128K
Bytes of EPROM but is less expensive
than the PSD303. The PSD303, which also
contains 128K Bytes of EPROM, can be
configured in a 16-bit data bus mode which
would be suitable for use with 16-bit
microcontrollers like the 80196.
The PSD313 was programmed and
configured to implement the memory map
shown in Figure 4. Not all of the capability
of the PSD313 has been utilized in this
example but is available to satisfy other
system design requirements if necessary.
The PSD313 has been configured to
function with the 8031 microcontroller and
its associated control signals. This can be
seen in the Configuration portion of the
output file in Figure 5. We have also
configured Port B 0-3 to provide the
required chip select functions for the
external liD and SRAM devices. These
chip selects have been given the aliases
ExtCS 1, ExtCS2 and ExtCS3 for the liD
devices and SRAMCS for the SRAM. The
equations entered for the chip selects
correspond to the addresses for which they
should be active. ExtCS1 will become
active when address 8000 - 87FF hex is
accessed. ExtCS2 and ExtCS3 will
become active for addresses 8800 - 8FFF
hex and 9000 - 97FF hex respectively. The
SRAM chip select will become active for
address 0 - 7FFF hex. All of these chip
selects will function independently from the
page register contents since the page
register outputs (PO - P3) do not appear in
the equations. This means that all of these
external devices will be selectable from
any page.

The address map lists the start and stop
addresses and the page numbers for each
of the blocks of memory and I/O inside the
PSD313. The first EPROM block is
selected by ESO, which has been mapped
from address 0000 to 3FFF hex. This block
has been designated to contain the page
switching software and the boot and
interrupt service routines. Since all pages
need the capability to switch from one to
another, and since an interrupt may be
received at any time while the software is
executing in any page, EPROM block 0
has been made accessible from all pages
by making the page register bits
'don't cares' (x's) in the address map for
ESO.
ES1 and ES2 map EPROM blocks 1 and 2
into address 8000 - FFFF hex in page O.
Thus, whenever a program address
within this range is accessed by the
microcontroller while the page register
contains a 0, ES1 or ES2 will activate
EPROM block 1 or 2. While the
microcontroller is executing code from one
of these blocks in page 1, it may still
access internal or external SRAM, or
internal or external liD without changing
pages. ES3 - ES7 are mapped to pages
1 - 3 in a similar manner.
In addition to the external SRAM, the
PSD313's internal SRAM has been
mapped into all address pages where it
may be used to supplement the
microcontroller's register file and internal
SRAM. This SRAM may be used fer
global variable storage, stack space or
many other purposes. The PSD313's liD
ports have been mapped at address
C800 - CFFF hex in this example. This
places the page register address at C81A
hex (see the PSD3XX data sheet for liD
addressing in the PSD3XX). As discussed
earlier, the page register has been mapped
into the same address from all memory
pages, so that it may be accessed from all
program subroutines in the system.

---------------------------------------~~~~-------------------------------------1-87

PS03XX - Application Note 015

Figure 5.

MAPLE
Software
Example
PSD PART USED: PSD313
********************PROJECT INFORMATION*****************
project Name
Page Register App Note
Your Name
Jeff Miller
Date
1/15/92
Host Processor:
8031
********************************************************
********************ALIASES*****************************

ICS4
/CSS
/CS6
/CS7

ExtCS1
ExtCS2
ExtCS3
SRAMCS

*******************************************************

********************GLOBAL CONFIGURATION***************
Address/Data Mode:
MX
Data Bus Size
8
Reset Polarity
HI
Security
OFF
ALE Polarity
HI
A1S-AO ALE dependent (Y) or Transparent (N):
N
Using Different READ strobes for Data and Program: Y
*******************************************************

********************READ WRITE CONTROL*************
/RO and /WR
**********************************************

********************PORT A CONFIGURATION **********
ADDRESS/IO
**********************************************

********************PORT A (ADDRESS/IO)*****************
PIN
Ai/IO
CMOS/OD
PAO
AO
CMOS
PAl
Al
CMOS
PA2
A2
CMOS
PA3
A3
CMOS
PA4
A4
CMOS
PAS
AS
CMOS
PA6
A6
CMOS
PA7
A7
CMOS
********************************************************

********************PORT B
Pin

CS/IO

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

CSO
CSl
CS2
CS3
CS4
CSS
eS6
CS7

CONFIGURATION***************

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

********************************************************

_________________________________________
1-88

'arar~&F

'.:':11

_________________________________________

PSD3XX - AppllcatlDn NDte 015

Figure 5.

MAPLE
Software
Example
(Cont.)
******************PORT B CHIP SELECT EQUATIONS************
ExtCSl

I (A15 * IA14 * IA13 * IA12 * IAll * Ipo
+ A15 * IA14 * IAl3 * IAl2 * IAll * IP1)

ExtCS2

I (A15 * IAl4 * IAl3 * IAl2 * All * IPO
+ Al5 * IA14 * IA13 * IA12 * All * IP1)

ExtCS3

I (A15 * IA14 * IAl3 * A12 * IAll * IpO
+ A1S * IAl4 * IA13 * A12 * IAll * IP1)

SRAKCS

I (/A15)

******************PORT C
pin

CS/Ai

PCO
PCl
PC2
A19

A16
A17
A18
CSI

CONFIGURATION~******w**********

LOGIC/ADDR
ADDR
ADDR
ADDR

*********************************w**********************

*****************PORT C CHIP SELECT EQUATIONS***********
*******************-**********ADDRESS MAP***********************************

A A A A A A A A A SEGMT SEGMT FILE
19 18 17 16 15 14 13 12 11 STRT STOP STRT
ESO
ESl
ES2
ES3
ES4
ESS
ES6
ES7
RSO
CSP

N
N
N
N
N
N
N
N
l~

N

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
1
1
1
1

1
1
1
1
1

0
0
1
0
1
0
1
1
1
1

N
N
N
N
N
N
N

N
0
0

N
N
N
N
N
N
N
N
0
0

N
N
N
N
N
N
N
N
0
1

0
8000
cOOO
8000
cOOO
8000
cOOO
cOOO
cOOO
c800

3fff
bfff
ffff
bfff'
ffff
bfff
ffff
ffff
c7ff
cfff

0
0
4000
0
4000
0
4000
0
N/A
N/A

FILE
STOP

File Name

3fff
3fff
7fff
3fff
7fff
3fff
7fff
3fff
N/A
N/A

PROGO.HEX
PROG1.HEX
PROG1.HEX
PROG2.HEX
PROG2.HEX
PROG3.HEX
PROG3.HEX
PROG4.HEX
N/A

NIl.

Page Reg Q.F
3210
ALE
XXXX
0000
0000
0001
0001
0010
0010
0011
XXXX
XXXX

X
X
X
X
X
X
X
X
X
X

****************************************END**w*w****** ****************~*******

*********************ADDRESSES OF 1/0 PORTS****************
C802 Page (Binary) : XXXX
Pin Register of Port A :
Direction Register of Port A : C804
C806
Data Register of Port A :
C803
Pin Register of Port B :
Direction Register of Port B
C805
Data Register of Port B :
C807
C8l8
Page Register :
************************************************************

-----------------------------------------rjfAf~~---------------------------------------1-89

=====

PSD3XX - Application Note 015

Software
Considerations

The software example shown In Figure 5,
has been divided into four sections to
facilitate placing it into the four pages.
These four program blocks have been
called PROG1.HEX, PROG2.HEX,
PROG3.HEX and PROG4.HEX. In order to
create these files to be loaded into the
PSD3XX, the software designer must plan
for this event when the software is written.
It is most easily accomplished by breaking
the tasks into logical groups that do not
need to access one another frequently.
Most software can be split in this manner.
Then, the designer can create the page
switching algorithm which is used to jump
between the tasks which are on different
pages.

To build the table, the labels of all
subroutines which may be shared among
pages must be accumulated from all of the
programs. These labels must be placed in
the table along with the corresponding
page numbers. This table must then be
placed in the global EPROM block. The
labels must be made global so that each
program may have access to them. Then
pointers into the table must be assigned,
one for each global subroutine. These
must also be made global so that they may
be used by each program. The pointers
must remain constant, even when the
software is modified. This way, software
modifications may change the values of the
labels, but not the pointers.

There are many ways to implement this
capability, but we will provide as an
example one method which can be used.
This method of memory paging involves
the use of a table of addresses and page
numbers of all program tasks which may be
called from page to page. This table can be
made global when the code is compiled so
that it may be used in all four of the
programs used in this example. This table
would reside in EPROM block 0 along with
the interrupt service routines and page
switching algorithms so that it may be
accessed from all memory pages. Thus,
when PROG1 is executing and must run a
task or subroutine which is in PROG2, the
software should jump to the page switching
algorithm while passing the table lookup
address of the task that it wishes to run. In
this way, only the pointer into the table
must be known by all programs instead of
the address and page number of each
routine. This simplifies the process of
modifying the software by permitting the
programmer to keep all of the pointers Into
the table constant, even if the actual
subroutine addresses change. In this
table, the page switching routine will find
the page that it must switch to as well as
the address to jump to after the page has
been switched. The return address and
page number may simply be pushed onto
the stack, which is stored in the SRAM.
Since the SRAM is also page independent,
all programs may share the same stack.

This provides a very clean paging solution
which may be implemented using high level
language compilers. The only penalty when
using this method is the overhead
experienced when switching from page to
page. This overhead may be minimized by
careful software design which minimizes
the number of program calls and jumps
between routines on different pages. Care
must also be taken when nesting jumps
from page to page if it is important to keep
track of return addresses. Interrupts, since
they are accessible from all pages, are very
simple to handle. The page need not even
be switched to service an interrupt unless
the service routine needs to access a task
which is not located in the global EPROM
block. Even then, the only consideration is
that before returning from the interrupt, the
page number must be restored to its value
prior to the interrupt. This paging scheme
is illustrated in Figure 6.

-1.-9-0-----------------------------~~~~--------------------------------

PS03XX - Application Note 015

Compiler
Issues

The paging algorithm shown below is
relatively easy to implement and somewhat
automatic. However, it is not a totally
transparent solution for the software
programmer. There is such a solution
available from at least one compiler
manufacturer. Archimedes makes
compilers for several microcontrollers
including the 8031 family and 68HC11
family. These compilers are available with
built in memory paging which use some of
the microcontroller's port bits as additional

address bits. These compilers generate
bank switching code automatically which
can be easily modified to utilize the page
register inside the PSD3XX.
When this is done, the use of the page
register becomes transparent to the user.
The attached code excerpt shows the
calling structure resulting from the use of
the Archimedes compiler with the
modifications to utilize the PSD3XX page
register.

Figure 6.
Software
Paging
Flow
SUB# 1

PROG 1PAGE 1

SUB#2
PROG 2PAGE 2

SUB ADDR 1
SUB AD DR 2
SUBADDR 3

PN
PN
PN

n

PN

.

SUB AD DR

PAGING
PROGRAMPAGE 0

,
'~------------~
--------~------------~

-------------------------------------~~~----------------------------------1--9--1

PSD3XX - Application Note 015

Archimedes
Code

836
837
838
,
,
,

0268
026A
026D

7400
900000
120000

/* Init DCC & SCR registers */
init_dsl_hdsl_dcc_scr();
MOV
A,#$BYTE3 init dsl hdsl dcc scr
MOV
DPTR,#REFFN inIt dsl hdsl dec scr
LCALL
?X_CALL_LI8
-

7400
900000
120000

/* Init Master/Slave Polynomial */
init_msJloly();
MOV
A,#$BYTE3 init_msJloly
MOV
DPTR,#$REFFN init_msJloly
LCALL
?X_CALL_LI8

839
840
841
,
,
,

0270
0272
0275
842
843
844
845

}

Notes: 1.
2.

$Byte 3 is a directive that addresses the "page" of the
specified function.
$REFFN Addresses the 16-bit offset of the function.

MODULE
TITL
RSEG

?BANK SWITCHER L18
'8051-- C - BANK-SWITCHER'
RCODE

j-------------------------------------------------------------------j
- L18.S03 Function (s) :

Banked switched CALL and RET

Must be tailored for actual bank-switching hardware.
In the sample system the PI port was used.
version: 4.00

[IANR]

j-------------------------------------------------------------------j
j-----------------------------------------------------i
Call a non-local function

j-----------------------------------------------------;
Inputs:
Stack: 16-bit return address
DPTR: 16-bit function-address
A: 8-bit page address

j-----------------------------------------------------;
The above Archimedes code is courtesy of Jeff Fayne, Tellabs, Inc.

-1--9-~-------------------------------~~~~----------------------------------

PSD3XX - Application Note 015

Archimedes
Code
(Cont.)

PUBLIC
?X CALL LlB
Save old bank

PUSH

Pl

Bank-switch
MOV

PI,A

Go to function
CLR
JMP

A
@A+DPTR

;-----------------------------------------------------;
Leave current function

i-----------------------------------------------------;
Input:
stack:

24-bit return address

i-----------------------------------------------------;
PUBLIC

?X RET LlB

?X RET LIB:
Bank-switch
POP

Pl

Return

RET
END

-------------------------------------------fjfjf~~-----------------------------------------­
'f!ffJ!R5.,iE
1·93

PS03XX - Application Note 015

Conclusion

The PSD3XX page register system can
greatly assist designers of systems
requiring large memory spaces with 16-bit
address buses. The PSD3XX offers
capability not found in most discrete page
register implementations. The capability to
define global resources as well as
page-specific resources enables the
designer to implement the paging
technique most suitable for the application.
The page register is included in the
PSD302, PSD312, PSD303 and PSD313
devices, all of which are pin compatible

with one another. This provides the
capability of expanding the memory size as
required even after a system has been
designed. The designer can simply drop
the new, and larger, PSD3XX into the
same footprint as the old, and update the
software to add more memory pages. This
capability can be important for product
feature additions after a design is
complete. Since the system is fully
programmable, it may be updated and
changed anytime.

---------------------------------------wrJr~~--------------------------------------1-94

!FEE
.=~
.,---.. - ------- ....... - -~

~..-.--

~

Programmable Peripheral
Application Note 016
Power Considerations In The PS03XX/3XXL
By Jeff Miller

Introduction

The PSD3XX is a configurable microcontroller peripheral integrating programmable
logic, EPROM and SRAM technologies into
a single piece of silicon. It has been used
extensively in microcontroller applications
around the world by virtue of its high level
of integration, configurability and ease of
use. This integration makes possible the
design of very compact microcontroller
systems, enabling the user to squeeze a
great deal of functionality into a very small
space. Thus, the PSD3XX has found its
way into many small hand-held and/or
battery operated applications such as
cellular phones, medical instrumentation
and laptop or notebook computers which
usually require, in addition to small space,
a very low power consumption.
The PSD3XX family is based on a patented
high-performance CMOS technology and,

Power Use
In The PSD3XX

The PSD3XX contains several modules
internally, each of which can be considered
a power consumer when in operation.
These modules include the PAD,
(Programmable Address Decoder)EPROM
and SRAM blocks. The key to reducing the
power used by the PSD3XX is to reduce
the power used by each of these modules
individually.
Under normal operation, several of the
functional modules may be operating, while
others may be standing by. A module in
stand by uses much less power than one
that is active. For example, whenever the
SRAM is not being actively used, it is
disabled and therefore consumes less
power. This is also true of the PAD. A PAD
term which is active expends more power
than one which is inactive. This would also
be true of the EPROM. However, in some
PSD3XX models, the EPROM is always
active, in which case it will always draw
power. This is done in order to provide the
best access time possible for the EPROM.
The Low Power family of PSD3XXs does
not keep the EPROM enabled at all times,

like other CMOS devices, requires very
low power consumption even when no
particular effort is made to minimize the
PSD3XX power. But, when some special
care is taken during the programming and
configuration of the device, power can
be reduced even further, making the
PSD3XX even more valuable in these
power-sensitive applications. This
application note will describe the methods
which can be used to reduce the PSD3XX
power consumption in both active and
stand-by modes. It makes sense to use
some of these techniques even when low
power is not a primary design requirement
since they are easy to implement and
require no additional expense. We believe
that proper implementation of the material
in this note will make the PSD3XX an
invaluable member of any low-power
microcontroller system.
and thus the designer can save power by
minimizing the time during which the
EPROM is accessed. Use of this feature
does impact the speed of the PSD3XX
EPROM, which results in the loss of the
120 ns speed grade. There are other
methods of reducing EPROM power even
when the EPROM is enabled. These will
be discussed in detail later in this note.
When the time that each PSD3XX function
is kept in standby mode is maximized, the
power expense is minimized.
There is a way to place the entire PSD3XX
into the standby mode at once, thereby
reducing power usage to the bare
minimum. This can be done through the
use of the CSI (Chip Select Input) pin.
When the PSD3XX is deselected by the
CSI pin, the entire part enters the standby
mode using only about 50 ~A of current.
While in this mode, the PSD3XX is
incapable of performing any functions,
including PAD logic equations, but this is
an excellent method of reducing system
power in designs which have low active
duty cycles.

1-95

PSD3XX - Application Note 016

CMOS
Power
Characteristics

As a CMOS part, the PSD3XX behaves in
the same way as other CMOS devices in
terms of power dissipation. The PSD3XX
consumes the most power when the
temperature is low, the voltage is high and
the frequency is high. Low temperature in
CMOS devices, unlike in bipolar devices,
causes the transistors to speed up, thus
consuming more power. Therefore, if the
system will never operate in low
temperature environments, power
dissipation will be lower. Another result of
this characteristic is that CMOS parts do
not generally experience thermal runaway.
As temperature increases, the power
expended by the CMOS device decreases,
thus the part tends to effectively cool itself
off.
Another characteristic of CMOS devices is
the effect of voltage variations. CMOS
behaves similarly to TTL devices with
respect to Voltage. When input voltage

rises, the current drawn by a CMOS device
also rises. As input voltage falls, input
current also falls. Thus, the CMOS device
will draw the least current at its lowest
allowable supply Voltage. This voltage is
4.5V in the PSD3XX. Taking the voltage
below this level will generally slow the
device down to below its specified speed
as well as jeopardize its data retention
capability. Between 4.5 and 5.5V, the
PSD3XX varies by about 0.85mA per 0.1 V
variation. Thus, the PSD3XX will draw
approximately 0.85 mA less current at 4.9V
than at 5.0V V cc.
Lastly, frequency of operation plays an
important role in the power dissipation of a
CMOS device. A CMOS gate expends the
greatest power while it is switching
between the logic 0 and logic 1 states, or
vice versa. This can be easily understood
when looking at the circuit diagram for a
typical CMOS output shown in Figure 1.

Figure 1.
Typical CMOS
Output Circuit

...----1_- OUTPUT

The circuit above represents a typical
CMOS inverter output. Normally, either the
top transistor is off (output = logic 0) or the
bottom transistor is off (output = logic 1).
MOS transistors have very low leakage
currents which means that under these
normal conditions, very little current will be
passing from Vcc to ground. However,
when the input to the inverter is switching,
both transistors will not switch from their
present conditions to their new conditions
at precisely the same instant. Therefore,
both transistors will be on for a very brief
instant during the transition. During this
time there is a low impedance path from
Vcc to ground and some current is drawn
by the circuit. In addition, the output will
have some load capacitance (C L)
which must be charged during switching,

even if the load itself draws little or no
static current. Thus, during the switching
process the power expended by a CMOS
device is at its highest.
The switching current drawn by the device
is dependent on the number of times the
outputs are forced to switch logic states in
a unit of time. Therefore. the frequency of
operation of the part directly influences its
dynamic power consumption. The lower
the operational frequency, the lower the
dynamic power expended by the device. In
the PSD3XX, frequency of operation is
determined by the rate at which the
addresses are changing, usually indicated
by the frequency of the ALE or AS signal.
Generally, the PSD3XX draws about 3 mA
of additional current for each 1 MHz added
to the frequency of operation.

-----------------------------~~~----------------------------------1-96

PS03XX - Application Note 016

Power
Management
Techniques
In The PSD3XX

Therefore, the PSD3XX should be placed
in the power down mode (CSI inactive) to
reduce the PSD3XX current down to its
standby value.

The above mentioned features and
characteristics can be used to the
designer's advantage when designing
compact microcontroller systems which
have a tight power budget. In the sections
that follow, several methods for reducing
the PSD3XX power will be presented.

The PSD3XX must also be awakened
when the microcontroller is awakened so
that it may provide an instruction to the
controller when it requires one. If the
microcontroller itself has a chip select
output, like the Motorola 683XX series
controllers, it may be used to awaken the
PSD3XX as necessary. However, if it
does not, there will be a problem. If the
microcontroller itself is used to power down
the PSD3XX, through an I/O port pin for
example, there will be no way to power up
the PSD3XX again since the PSD3XX
itself contains the instruction that the
microcontroller must use to activate the
CSI Signal to awaken the PSD3XX. The
way to correct this situation is to design
a circuit which detects when the
microcontroller is coming out of its power
down mode before it must fetch the first
instruction. Such a circuit is depicted in
Figure 2.

Power Down Mode
Many system designs do not require the
microcontroller, and therefore the PSD3XX,
to operate continuously. Systems, like
cellular telephones and notebook
computers, spend a large amount of time
inactive - waiting for something to happen
like a press of a button or keyboard. During
this time, many designers place the
microcontroller into a low power idle or
sleep mode. In the sleep mode, the
controller expends significantly lower
power. The microcontroller is usually awakened by some event - a key on a keypad
being pressed, for instance, which may
result in an interrupt. There is no need for
the PSD3XX to be active during the time
that the microcontroller is not active.

Figure 2.
Simple Power
Down Circuit

>

<>R
<>
68HC11

PSD3XX
74ACT05

Ek>~

-

CSI

-

In this circuit diagram, a Motorola 68HC11
microcontroller is connected to a PSD3XX
in a low power system. The circuit functions
quite simply. The E signal from the HC11 is
normally a free running clock at 1/4 the
frequency of the input clock. When the
HC11 is placed into the sleep mode by the
software (by executing the STOP
instruction), the E Signal stops oscillating
and remains low until an interrupt or
internal timer event occurs. After the

interrupt has been received by the
controller, the E signal resumes toggling,
but there will be a minimum of two E
clock cycles prior to the first AS. This
characteristic can be used to place the
PSD3XX into its low power standby mode
whenever the STOP has been executed in
the HC11 and to awaken it before it must
supply an instruction to the HC11.

-------------------------------------~Jf~~------------------------------------1-97

PSD3XX - Application Note 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

The ACTOS device shown in the diagram is
simply an open collector inverter. When the
E signal is oscillating, the output of the
inverter will be toggling between ground
and high impedance. When the output is at
ground, the capacitor will rapidly discharge
from its present state into the ACTOS.
When the output is high impedance, the
capacitor will slowly charge up to Vee
through the resistor. Thus, under normal
operation the CSI input of the PSD3XX will
be at or near 0 V, provided the RC time
constant is large enough to prevent the
capacitor from charging up beyond a logic
zero level of 0.6 V.
When the HC11 enters the sleep mode the
E signal remains low. This enables the

Figure 3.
6BHC11 Stop
Timing

capacitor to slowly charge up to a logic one
level which then places the PSD3XX into
the standby mode in which it will consume
only about SOIJA of current. After the
controller exits the sleep mode, the E signal
will resume oscillating which rapidly
discharges the capacitor. This, in turn,
activates the CSI input to the PSD3XX,
bringing it out of the power down mode.
Since the E signal will oscillate for at least
two full cycles before the first AS strobe
begins a new bus cycle, the PSD3XX will
have ample time to recover from the power
down mode before having to supply an
instruction to the HC11 for processing. In
operation, the circuit results in a timing
diagram similar to the one in Figure 3.

RECOVERY

STOP ACTIVE

A similar circuit can be used for Intel 8031
type controllers. Controllers conforming to
the Intel 8031 family generally have two
low power modes: IDLE and POWER
DOWN. The IDLE mode causes the
controller to cease instruction execution,
but its internal clocks continue to run. This
saves significant power while leaving the

internal timers and other functions
operational. When in the IDLE mode, both
the ALE signal and the PSEN signal are
held high. A circuit similar to the one
illustrated for the 68HC11 may be used to
detect the end of oscillation on the ALE
signal. This circuit is shown in Figure 4.

Figure 4.
B031 Idle
Circuit

PSD3XX

80C31
l--.......- - - - I

CSI

74ACT09

T

C

~1_~~~--------------------------f====-------------------------------

PSD3XX - AppllcatlDn NDte 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

The circuit operates on the same principle
as the one used earlier for the Motorola
processor. The ALE signal normally
oscillates high for 2 clocks out of every 6 or
12 clocks, depending on whether
instruction or data accesses are being
performed. The software places the 8031
into the Idle mode by setting bit 0 in the
PCON register. Once set, the ALE and
PSEN signals remain high until an interrupt
or hardware reset occur. During this time,
the CSI signal will float high with the RC
circuit, as in the earlier example. The

ACT09 is simply an AND gate with an
open collector output. It performs the same
function as the inverter in the previous
example without inverting the Signal. When
an interrupt or reset is received, the ALE
signal begins to toggle again, but at least
two "dummy" unused ALE cycles will occur
before the first meaningful instruction is
fetched, giving the PSD3XX time to
recover from the power down mode. The
timing for the above circuit is shown in
Figure 5.

FigureS.
B0311dle
Timing
CSI

If the system requires truly the lowest
power available, the 8031 POWER DOWN
mode may be used. This disables all
internal operations of the 8031 as well as
the external ones. Thus, anyon-chip
peripherals like timers and serial communication links will be disabled. This places the
controller into its lowest power mode
possible. Software may place the 8031 into
the POWER DOWN mode by setting bit 1
in the PCON register. When execution of
the instruction is complete, the ALE signal
will be driven low and will remain in this

Figure 6.
B031 Power
Down or Idle
Circuit

state until a hardware reset is received.
Thus, a circuit similar to the one above may
be used to detect the static condition
of the ALE signal, but an inverting gate
must be used instead of the ACT09
(such as the ACTOS used in the Motorola
example earlier).
If both the POWER DOWN and IDLE
modes must be used, the gate may be
replaced with an ACT266 exclusive NOR
with an open collector output. This circuit is
shown in Figure 6.

Voo

>R
80C552
ALE

~D

74ACT266

PSD3XX
CSI

Ie

-----------------------------------~~~-------------------------------------=
1-99

PSD3XX - Application Note 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

The 1/0 bit can be provided by either the
PSD3XX or the controller itself. If the
controller is used to provide the 1/0 bit, it
must hold the correct value on the output
even when in the idle or sleep mode, as the
PSD3XX does. When the 1/0 bit is low, the
POWER DOWN mode is enabled (a low on
ALE and a LOW on the 1/0 bit will result in
a high on CSI). When the 1/0 bit is high,
the IDLE mode is enabled (a high on ALE
and a high on the 1/0 bit will result in a high
on CSI).
For all of the above circuits to operate
correctly, the value of the RC network must
be carefully calculated to insure proper
operation in the normal mode. This means
that under normal operation, CSI must
never climb above 0.4 V, which will
guarantee that it is always recognized by
the PSD3XX as a low.
For example, the 68HC11 circuit shown in
Figure 2 used the E signal from the
controller to disable the PSD3XX. The E
signal oscillates at 1/4 the frequency of the
HC11 's input clock. If an 8 MHz HC11 is
used, the E signal will oscillate at 2 MHz.
This results in an E signal clock period of
500 ns. During this 500 ns the E signal will
be low for 250 ns. Thus, the RC network
must be chosen to prevent the CSI signal
from climbing above 0.4 V for at least
250 ns. The equation below governs the
voltage across the capacitor (Vd, and thus
the voltage present on the CSI pin:
Vc

=Vcd1

- e-tlRe )

where Vc is the voltage across the
capacitor (which is the same as the CSI
pin), Vcc is the supply voltage, and t is the
time in seconds after the output of the open
collector gate switches from a low to an
open circuit. Solving for RC we get:
RC '" -tlln(1-VclVcd
In order to determine the minimum values
for Rand C, we must solve this equation
for the point of time which is of interest. We
must have Vc no greater than 0.4V at time
t = 250 ns. Thus, with Vcc = 5 V, the
equation may be rewritten as follows:
RC

=-250 x 10-9/1n (1 -

0.4/5.0)

An acceptable RC network for this case
might be a resistor of 100KQ and a
capacitor of 30pF. These values will
provide no margin for the circuit so some
additional resistance or capacitance may
be desired. Of course, larger values rnay
be used without harming the circuit, they
will just cause the low power mode to be
entered more slowly. The case of leaving
the low power mode is less critical, since
the capacitor will discharge more quickly
through the gate than it will charge up
through the resistor. In the interest of
minimizing power use by the circuit itself, it
is best to use a larger resistor value and a
smaller capacitor value, since this will
cause less current to be sunk by the gate
which drives the circuit.
Using this equation, it is possible to
determine the RC value required for any
controller andlor frequency. It is only
necessary to determine the length of time
that the RC will be required to hold the CSI
signal below 0.4 V and plug that value into
the above equation.
If a more deterministic method is desired
for placing the PSD3XX in the power
down mode, a fully digital circuit may be
implemented which uses very few additional components. This circuit is shown in
Figure 7 for the 68HC11 controller.
This circuit performs the same function as
the RC circuit described earlier, but does it
digitally. The 74ACT164 is a shift register
which is used in this example to detect
when eight HC11 input clocks occur while
the E signal remains low. In normal
operation, no more than two clocks should
occur without E transitioning from low to
high, thus providing a clear to the ACT164.
If the HC11 is stopped, the E signal will
remain high until an interrupt is received,
but the input clock continues to run freely.
Thus, the shift register wiil shift in "one's"
until the E signal goes high again. When
the ACT164 has shifted eight times, the
CSI signal will go high, placing the
PSD3XX into the power down mode. The
timing diagram corresponding to this circuit
is shown in Figure 8.

=

3.0 x 10-6

--------------------------___________
r~~~~------------------------------------1-100
====

PS03XX - AppllcatiDn NDte 016

Figure 7.
Digital Sleep
Circuit For
BBHCH
74ACT164

A
B

ClK
68HC11A1

FigureB.
BBHCH Stop
Mode Timing

QH

CSI

PSD3XX

74ACT04

STOP ACTIVE

RECOVERY

ClK
E
CSI

Power
Management
Techniques
In The PSD3XX
(Cont.)

----~------------~

A similar circuit may be used for the 8031
family of controllers, and is depicted in
Figure 9.
This circuit, like the others, detects when
ALE stops toggling. Since up to 10 clocks
may normally occur without an ALE pulse,
a counter which can count to at least 11 is
required in order to function properly. Thus,
an 8-bit shift register like the one used with
the HC11 will not work. In this case, a
74ACT191 is used to count 16 clocks prior
to raising its MAXIMIN output high. A low
on the ALE signal will load zero's into the
counter and clear the MAXIMIN output. The
MAXIMIN output is also used as the

counter enable to prevent the counter from
counting further after attaining the count of
16. The circuit shown will function with the
IDLE mode of the 8031. If the POWER
DOWN mode is used, an inverter must be
inserted in the ALE signal path.
Other controllers, not listed here, may also
have power down modes which may
function with these circuits. Any controller
which has some sort of external indication
when the power down mode has been
entered may usually be used to place the
PSD3XX in its low power mode also.

=====!E
-----------------------------------,=--- = ----------------------------------1-101

PSD3XX - Application Nots 016

Figure 9.
Digital Sleep
Circuit for
8031 Family
74ACT191

ClK

80C31

A
B
C MAXI
MIN

D
ALE I---t----i lOAD

CSI

PSD3XX

DIU
CTEN

Power
Management
Techniques
In The PSD3XX
(Cont.)

PAD Programming Techniques
The preceding section has described
methods of using the power down
capability of the PSD3XX with several
microcontrollers. There are also techniques
which may be utilized during programming
of the device to further reduce power.
These techniques can significantly reduce
the power expended by the PSD3XX when
it is in full operation.
The programmable logic section of the
PSD3XX, called the PAD, provides much of
its great flexibility and configurability. It is
used to control the internal resources of the
PSD3XX and can also be used to control
external resources as well. The power
use of the PAD varies greatly depending
on how its product terms are programmed
and used.
The PAD is illustrated in Figure 10. It is
divided into two sections, called PAD A and
PAD B. PAD A is responsible for generating
the control and selection for the internal
resources of the PSD3XX and utilizes 13
product terms to perform these functions.
PAD B provides any external chip selection
and logic replacement that is necessary
for the system and has 27 product terms for
this purpose. A single product term is
functionally illustrated in Figure 11.

---------------------------------------1-102

rar~~=

Each of the PAD inputs and its complement
is available to each of the 40 product terms
of the PAD. Each of these inputs is
connected to an n-channel transistor which
is used to connect the entire line to ground
when the input is in the appropriate state. A
high on the input to the gate causes the
transistor to turn on. When the device is
programmed, each of these transistors may
be left in place or may be functionally
removed (programmed out) from the circuit.
If all of the transistors are programmed out,
the line is left connected only to the pull-up
resistor which makes it always high. Thus,
the output of the inverter is always low. If
an equation such as:

ICSx = In#1 • Iln#2
is programmed into the PAD, the output
CSx must be high except when In#1 is high
and In#2 is low. Thus, all of the transistors
are programmed out except the ones
connected to !n#1 and !n#2. This means
that unless In#1 is high and In#2 is low,
there will always be at least one of the two
remaining transistors turned on, which in
turn results in the CSx output being high.
When the appropriate input condition is
met, the remaining two transistors will turn
off, which allows the output to become low.

_____________________________________

PSD3XX - Application Note 016

Figure 10.
PAD
Illustration
ALE

~

RDor E

'M}

....L

orRi'ii

~

A19

A

j

"'S

....
AlB

1

ESl
ES2
8 EPROM Block
ES3
Selecl Lines
ES4
PAD
ESS
ES6
ES7
RSO - - - SRAM Block Select
CSIOPORT _I/O Base Address
CSADIN
CSADOUTl } Track Mode
CSADOU T2 Control Signals

D.--

"'S

v

CSO/PBO

CSlIPBl
A17

~

.--

....

CS2IPB2
A16

~

"'S

..--

....

CS3/PB3
A1S

"

A14

"
"'S

~

CS4/PB4
--"

CSS/PBS

PADB

A13
CS6/PB6
A12
CS7/PB7
All

.'"'
-"

CSI

-RESET

Figure 11.
Product
Term
Functionality

CS8IPCO

•
•

IN #1

CS9/PCl
CS10/PC2

IN#2

IN#n

CSx

--------------------_________________ f~=~~ _______________________________________
'=='=-~:=

1·103

PSD3XX - AppllcatlDn ND'. 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

As can be seen in the figure, the product
term expends very little power when all of
the transistors are either programmed out
or turned off. The only power used in this
case is the result of the leakage current
through the various off transistors, which is
very low in CMOS technology. When one
or more of the transistors is turned on,
there will be current drawn through the pullup resistor to ground. Therefore, the power
used by a product term varies greatly
according to the way it is programmed.
Experimental data has shown that a
product term with all of the transistors
programmed out draws approximately
380IJA less current at room temperature
and 5.0 V Vcc than a product term which
has some active transistors. WSl's MAPLE
software packages take advantage of this
fact to reduce power as much as possible.
When the user intends to use some or all of
the Port 8 pins as 1/0 Signals, then they are
not connected to the PAD in any way.
Thus, the MAPLE software is free to
program the unused PAD 8 product terms
in any way. In MAPLE versions 4.038 and
subsequent, the software automatically
programs out all transistors in each unused
product term, which can eliminate up to 24
product terms for Port 8. This results in a
power reduction of up to 9.1 mA.
If one or more of the Port C pins is
programmed as an address or logic input,
MAPLE is free again to program out all of
the transistors in each unused PAD 8
product term dedicated to Port C. This can
eliminate up to 3 additional product terms
resulting in a power reduction of over 1 mA.
Finally, there are three product terms from
PAD A which are dedicated to controlling
the Port A Track Mode operation. If the
Track Mode is not used in the application,
these product terms may also be
eliminated by MAPLE for a power reduction
of over 1 mAo
The remaining ten product terms are the 8
EPROM select lines, the SRAM select line
and the 1/0 port select line. These terms
may not be eliminated by MAPLE without
disrupting the operation of the device. But
in a system which uses Port A and Port 8
as 1/0 or address outputs, and Port C as
address or logic inputs, the total system
power saving is 10.2 mA typical.
;;.=,~

The same methods may also be used in
non-multiplexed microcontroller
applications. In this case, Port A and Port 8
may be used as microcontroller data input
pins, depending on whether the controller is
8- or 16-bit. As in the earlier cases, if the
ports are used as data input pins, they are
not connected to the PAD which allows
MAPLE to program out the appropriate
product terms.
Again, MAPLE 4.03B or a subsequent
revision must be used to obtain this
capability. If your software is an older
revision, contact your local WSI regional
sales office for a free update.

EPROM Programming Techniques
Like the PAD, the EPROM in the PSD3XX
uses varying amounts of power depending
on how it is programmed. When
programmed to a one, an EPROM bit
draws more current than when
programmed to a zero. Thus, for minimum
power usage it is best to have the majority
of the EPROM programmed to zeros.
Unfortunately, the contents of the EPROM
are fixed by the program and data
requirements of the system and thus
cannot be easily optimized for power.
However, the user can program all unused
sections of the EPROM to zeros. This will
not substantially cut the power used by the
PSD3XX under normal operation when
EPROM accesses are being performed, but
it will reduce the power consumption during
periods when there is not a valid address
on the bus because these invalid
addresses will often point to unused
EPROM locations. When an EPROM
location is currently addressed, it is
expending power even if the RD or PSEN
Signals are not actually enabling an output.
Therefore, it is best that unused EPROM
locations be filled with zeros so that power
is minimized during these periods of invalid
addresses. It should be noted that all power
figures used in this application note as well
as those specified in the PSD3XX data
sheet are based on an average of 50%
"ones" and 50% "zeros" contained in the
EPROM. An EPROM location programmed
to "ones" will draw approximately 1.5 mA of
additional current over an EPROM location
programmed to "zeros'.

~1-~W~~~-------------------------~~·------------------------------

PSD3XX - Application Nots 016

Power
Management
Techniques
In The PSD3XX
(Cont.)

CMiser-Bit

An even better way to help minimize power
usage is to control the addresses which
appear on the bus when there is no valid
address being driven by the microcontroller.
The least power expense will be when this
unused address points to an area which
has no PSD3XX resource mapped into it.
This will result in no internal resource block
receiving a chip select and thus the least
amount of current will be drawn. The next
best approach is to have the unused
address pOint to an EPROM area
containing zeros. The next lowest power
would be to have the unused address point
to an EPROM area containing something
other than zeros. Finally, the highest power
will occur when the unused address points
to an SRAM location.

Since there is not much that can be done
about the address that is appearing at the
output of the microcontroller, the best that
can be done is to know what address the
controller will have active on its bus at
various non-operational times and insure, if
pOSSible, that the PSD3XX's address map
maps that address into a desired range of
memory (preferably no memory at all). This
will truly minimize the power expended by
the PSD3XX during these times.

The CMiser-Bit provides a programmable
option for power-sensitive applications that
require further reduction in power
consumption. The CMiser-Bit (CMiser = 1)
in the Maple portion of the PSD3XX sytem
development software can be used to
reduce power consumption. The CMiser-Bit
turns off the EPROM blocks in the PSD3XX
whenever the EPROM is not accessed,
thereby reducing the active current
consumed by the PSD3XX.

However, if the CMiser-Bit is programmed
(CMiser 1), the device consumes even
lower current, and is reflected in the data
sheet. This mode has an adder in
propagation delay in T5, T6, and T7
parameters in the A.C. Characteristics, and
should be added to compute worst-case
timing requirements in the application.

=

In the default mode, or if the PSD3XX is
configured without programming the
CMiser-Bit (CMiser = 0), the device
operates at specified speed and power
rating as specified in the A.C. and D.C.
Characteristics.

IFa-11E

-------------------------------------~~~------------------------------------1-105

PSD3XX - Application Note 016

Summing
/tAil Up

After taking all of these factors into
account, what kind of power use can you
expect from the PSD3XX in your own
system? As a guideline, we will calculate
the typical power required of a PSD3XX
installed in a hypothetical system. The
requirements of this system are listed in
Table 1.
Using this information, we can calculate
the approximate typical power
requirements of the PSD3XX. Before we
can begin, we must know what the base
power of the PSD3XX is under the voltage
and temperature conditions specified. The
base power of the PSD3XX is the power
used by the PSD3XX when only the
product terms which control the EPROM,
SRAM and 1/0 ports are not programmed
out (10 active product terms). The base
power also assumes that no internal
resources (EPROM, SRAM and 1/0 ports)
are being currently accessed. The current
drawn by the PSD3XX under these
conditions has been determined
experimentally to be 16 mA. To this
current, we must add additional current for
the other active product terms, SRAM
access and EPROM access.

Table 1.
Hypothetical
System
Requirements

The system is requiring only four of the 11
available chip select outputs. Therefore,
most of the PAD B product terms may be
programmed out. To determine how many
product terms we will be using, we must
look at the equations for the four chip
selects. Assume that the following equations are to be used:

ICS#1 =/(A15· A14· RD + A13· A12· WR)

=1(/A18 + IA17)
=I(A16· A18 + A17· ALE)
ICS#4 =A17
ICS#2
ICS#3

In order to configure the system for the
lowest power usage, we must be sure that
we place these chip selects on the output
pins which will require the minimum
number of product terms to remain
active. Since the maximum number of
product terms required to generate the
above equations is only two, there is no
need to place these chip selects on Port B
pin 0,1,2 or 3 since these pins each have
four product terms. The lower power
configuration would place these chip
selects on Port B pin 4,5,6 and 7, where
only two product terms will be drawing
power for each chip select. One of the
above chip selects, #4, actually requires
only one product term, meaning that it
could be placed on one of the Port C pins
which have only one product term.

Characteristic

Specification

PSD3XX Operational Frequency

2MHz

Port A

Address Output

Port B

4 Chip Select, 4 1/0

Port C

Logic inputs

CSI

Configured for Auto. Power Down
5.0V

Vcc
Temperature

25°C

Standby duty cycle

60%

EPROM duty cycle

30%

SRAM duty cycle

10%

_____________________________________ fafafaFE _____________________________________

1-106

====

PSD3XX - Application Note 016

Summing
It All Up

fCont.}

However, all of Port C is used in this case
as logic inputs (A16, A17 and A18) and
therefore cannot be used as chip selects.
Since the rest of the Port pins are not used
as PAD outputs, the MAPLE software will
automatically program them out.
If we do configure the chip selects to output
on PB[0:3], we must add 8 product terms to
the 10 used in calculating the base power
number. Using the current per product term
of 380~A provided earlier, eight additional
product terms result in an additional 3.0 mA
of current.
Experimental data has shown that
accessing the SRAM results in an
additional current expense of 31 mA above
the base current. Also, accessing the
EPROM draws an additional 0.5 mA over
the base current. The standby current has
been measured at 50 ~A. Finally, we must
consider the additional current used by the
frequency of operation. This is 3 mA per
1 MHz for a total of 6 mA, since the
PSD3XX will be operating at 2 MHz. This
provides us with all of the data that we
need to calculate the total power usage of
the PSD3XX in this system.
Table 2 can be used to calculate the
EPROM access current, the SRAM access
current and the standby cu rrent.

Table 2.
Summary of
PS03XX Current
Usage In
Hypothetical
System

Now we must account for the duty cycle of
the system to determine the total average
power for the PSD3XX. In order to apply
the duty cycle, we simply multiply each
power component by its duty cycle and add
them all together. The equation to perform
this is given below:
Total Current = 0.6(i SBY) + 0.3(iEPROM)
+ 0.1 (iSRAM)
where iSBY is the standby current, iEPROM is
the active EPROM current and iSRAM is the
active SRAM current. Plugging in the
numbers we developed earlier, the equation becomes:
Total Current = 0.6 (50 ~A) + 0.3
(9 mAl + 0.1(47 mAl = 7.4 mA
The average current drawn by the PSD3XX
under the specified conditions of
configuration, frequency and environment
is therefore 7.4 mA. The peak typical
current used by the PSD3XX is 54 mA
while the SRAM is being accessed. The
minimum current is 50 ~A, drawn by the
PSD3XX while it is in the Power Down
mode. This compares very favorably with
the typical current usage of a fully discrete
solution.

Current Used

PS03XX Block
Base Configuration (CMiser = ON)

9mA

PAD (as configured)

3.0mA

EPROM

0.5mA

SRAM

31 mA

Frequency Component

6mA

Standby Current

50~A

Now, summarizing further, the total
EPROM access current is:
Base Current + PAD Current + EPROM
Current + Frequency Component
= 9 mA + 3.0 mA + 0.5 mA + 6 mA
=18.5 mA

The total SRAM access current is:
Base Current + PAD Current + SRAM
Current + Frequency Component
= 9 mA + 3.0 mA + 31 mA + 6 mA
=47.0mA

-------------------------------------~Jf~~------------------------------------1-107

PSD3XX - Application Note 016

Typicalvs.
Maximum
Current

The typical and maximum current numbers
are both specified by most integrated circuit
manufacturers. Many designers are unsure
of what these parameters are and how they
relate to the power which will actually be
dissipated by the system. This is
compounded by the configurability of the
PSD3XX.
The maximum power numbers published in
most product specifications are usually
chosen as the number which will never be
exceeded by the device under any
circumstances, including variations in
processing, Vee and temperature. To truly
be a maximum number, all three of these
parameters must be at their worst cases
simultaneously, which is quite unlikely.
Therefore, power use will more likely follow
the typical values when the system is
actually running.
In the PSD3XX data sheet published by
WSI, two current values are published for
typical conditions and another two are
published for worst case conditions. These
two sets of numbers are used to specify
current use in two different PSD3XX
configurations. The lower numbers
represent the current drawn by the
PSD3XX while configured with 10 active
product terms. To arrive at the maximum
value for this configuration, we assume that
the programming of the device has not
changed, but we take the temperature,
voltage and processing to their worst case

Table 3.
Summary of

PSD3XX

Typical
CUllent
Usage

conditions. These numbers are generated
again, for the configuration of the PSD3XX
which has all 40 product terms active. To
determine the typical current drawn by the
PSD3XX in your system, it is best to use
the techniques presented in this application
note. All of the typical current values
used in this note are the result of careful
experimentation, and should parallel very
closely the values measured in your own
system. To extrapolate the worst case
current for your configuration from your
calculated typical value, you must
add about 50% to account for voltage,
temperature and process variation.
When calculating the worst case current for
your entire system it is usually best to use
the typical current numbers for all of the
components installed and then apply some
margin to allow for worst case conditions.
This is much more accurate than using the
worst case parameters for each
component since it is extremely unlikely
that al/ of the components used are
simultaneously at their worst case process
parameters, though they may all be at
worst case voltage and temperature.
Usually 20% margin above the typical
numbers will sufficiently cover the worst
case for the entire system.
Table 3 summarizes the typical current
numbers for the PSD3XX which can be
used when calculating the current used in
your own system.

Base Current
(10 product terms, SRAM and EPROM Unselected and CMiser =ON)
Additional Current per Product Term
Additional Current for SRAM Access
Additional Current for EPROM Access
Additional Current for Frequency Effects
Additional Current for Voltage> 5V
Standby Current

9mA
0.38 mA
31 mA
0.5mA
3 mA/MHz
0.85 mAlO.1V
50llA

-1--1-0-8---------------------------------~~~-------------------------------------

PSD3XX - Application Note 016

Table 4.
PSD3XXL
Power
Consumption

Using the same example described in Table 1, a PSD3XXL operating at 3 volts and 1 MHz
will exhibit the following values:

PS03XXL Block

Current Used

Base Configuration (CMiser ON)

2mA
0.19 x 10 = 1.9 mA

PAD
EPROM

0.25 mA

SRAM

13 mA

Frequency Component

2mA

Standby Current
EPROM Access Current
SRAM Access Current
Total Current

Conclusion

1 IJA

= 2 + 1.9 + 0.25 + 2 = 6.15 mA
= 2 + 1.9 + 13 + 2 = 18.9 mA

= 0.6 x 1 IJA + 0.3 x 6.15 mA + 0.1

The PSD3XX and PSD3XXL are very
important devices in the design of compact,
low-power systems. It provides a cost
effective minimum part count solution for a
typical microcontroller system. It also
provides a very low power solution for
those designs which are handheld and/or
battery operated. As the PSD3XX family
grows and evolves, more innovations will

x 18.9 mA

= 3.74 mA

be presented in terms of integration and
power usage. The new low power
PSD3XX family will be introduced soon,
providing the designer with an even lower
power solution. Until then, use of the
techniques described in this note will
provide a minimum power solution for your
microcontroller system.

-------------------------------------~~~~------------------------------------1-109

PSD3XX - Application No'" 016

fUiF.E

-1--1-10-----------------------------~-=-aF.--------------------------------

Programmable Peripheral
Application Note 017
Track Mode Implementation of PSD3XX
By Ravi Kumar

Introduction

Resource sharing is becoming an inevitable
issue in ever growing and complex
microcontroller applications. Increased
throughput and efficiency requirements of
complex data acquisition systems such as
automotive electronics, high speed/high
density disk drive electronics, cellular
phones etc., are driving microcontrollers to
share resources. This results in increased
discrete component count, complexity in
design and timing issues and thereby

lengthens the time it takes to get to market.
Using a Dual-port RAM is an expensive
solution. A lower cost solution would be to
use a PSD3XX and SRAM in ''TRACK
MODE". The PSD3XX also replaces the
glue logic, EPROM, SRAM and I/O port
requirements of the microcontroller based
system. The following application note
explains the implementation of the
PSD3XX's "TRACK MODE" using Intel's
80C31 microcontrollers.

Bus Sharing

In a master/slave configuration of
microcontrollers the typical bus sharing
sequence is:

o

o
o

o
o

PSD3XX
Architecture
Related to
TRACK Mode
of Operation

Slave processor sends a request to the
master processor to tri-state its bus in
order to access the resource they
share.
Master processor acknowledges the
slave processor's request and tri-states
its own bus connected to the shared
resource.
Then the slave processor proceeds to
write/read to/from the shared resource.

Then the master processor resumes the
possession of the bus connected to
the shared resource and continues its
interaction with it until it receives a
request from the slave processor to
release the bus.

Although the master/slave processors
tri-state their bus connected to the shared
resource, by using PSD3XX devices
we can avoid the situation where the
processors wait. Therefore the processors
continue to attend to other chores when the
shared resource is not available. This application note explains how this can be
achieved.

After the completion of writing/reading
data to/from the shared resource, the
slave processor relieves the control of
the shared resource.

Tracking of Address/Data inputs to a
PSD3XX is possible only through port A
and only for microcontrollers with a
multiplexed bus. The default configuration
of port A is I/O. Alternately, each bit of port
A can be configured as a lower order
latched address bus bit. Another mode of
port A sets the entire port to track the
inputs ADO/AO-AD7/A7 depending on
specific address ranges defined by the
PAD's CSADIN, CSADOUT1 and
CSADOUT2 signals. This feature lets the
user interface the microcontroller to
shared external resources without requiring

external buffers and decoders. In this
mode, the port is effectively a bidirectional
buffer. The direction is controlled by using
the input signals ALE, RD/E/DS, WENpp
or RIW, and the internal PAD outputs
CSADOUT1, CSADOUT2 and CSADIN
(see Figure 1).
CSADOUT1 is generated when the
microprocessor is accessing a "tracked"
address. It is generated from a single
product term involving the address inputs
and ALE. When an address generated by
the microcontroller is within the block

-------------------------------------f==~~--------------------------------~~
====
1-111

I'SII3XX - Appllt:tJtIllll illite 011

PSD
Architecture
Re/atedto
Track Mode
of Operation
(Cont.)

generated, transferring the data and
outputting it from port A.

specified by the user for track mode and the
ALE is active, CSADOUT1 becomes active,
transferring the address and outputting it
from port A. Carefully check the generation
of CSADOUT1 and ensure that it is stable
during the ALE pulse; i.e. signals in the
product term involved in generating
CSADOUT1 should not be those addresses
which change frequently; instead they
should be stable I/O signals.

CSADIN is generated when the
microcontroller is attempting to read data
from Port A in the track mode. It is
generated from one product term involving
the address inputs and the RD strobe (Intel
mode) or R/W and or DS (Motorola mode).
This enables the user to configure the
address range in which the data is to be
read from Port A.

CSADOUT2 is generated when the
microcontroller is performing a write
operation to a tracked address. It also has
one product term involving the address
inputs and WR (Intel mode) or R/W and E
or DS (Motorola mode). When the
microcontroller performs a write operation
to the appropriate address, CSADOUT2 is

In this operational mode, port A is tri-stated
when none of the above conditions exist.

Figure 1.
PortA
Track Mode
WR

or RIW

-I

ROlE
ADO-AD7

PAo-PA7

ALE or AS

AD8-AD15

•

•

LATCH A11-A15

1--. .--1

PAD

r

A16-A19

CSADOUT2 (1)

-------I

NOTE: 1. The expression for CSADOUT2 must include the following wi rite operetlon cycle signals:
For CRRWR 0, CSADOUT2 must include WR O.
For CRRWR 1, CSADOUT2 must include E 1 and RiW o.

=

=

____________________________
1-112

=

=

=

'#rJ!!.,. ------------------------------'81~~

PSD3XX - Application Note 017

Track Mode of
PSD3XX Using
Intel's BBC31s
in MasterlSlave
Configurations

In this configuration two PSD3XX's are
used with two Intel's 80C31s. In figure 2, a
common SRAM CD6116 and a '373
Latch are the shared resources of the
Master/Slave configuration of these two
microcontrollers.
Referring to the flowchart in figure 3, under
normal operation, the master processor and
the master PSD3XX are in control of the
shared LATCH and SRAM, i.e. pins P1.0
and P1.1 of the master/slave processors
are all HIGH. The slave processor,
whenever it needs to access the shared
LATCH and SRAM, requests the control of
the address/data bus from the master
processor by generating a HOLD signal
from the slave 80C31 's P 1.0 as output
LOW. The master 80C31 takes this HOLD
signal on to its input pin P1.0 and INTO pin
as an interrupt, processes it and
acknowledges by returning HLDACK on
P1.1 (LOW), i.e hold acknowledge signal to
slave processor. Meanwhile the master
PSD3XX senses that both P1.0 and P1.1
pins of the master processor are LOW and
tri-states the ports A,B and C of the
PSD3XX, thereby disabling its control over
the bus connected to the shared LATCH
and SRAM. In order for a successful
interaction between master and slave
processors, care should be taken in the
master processor to properly mask the
interrupt generated on INTO.
The HLDACK signal coming from the
master is fed into P1.1 of the slave 80C31
processor, which processes HLDACK and
takes control of the bus connected to the
shared LATCH and the SRAM. The slave
PSD3XX senses that both P1.0 and P1.1 of
the slave processor are LOW and starts
tracking the address and data flowing into
and out of the CD6116 SRAM. When the
slave processor is successfully accessing
the shared SRAM, the master processor
attends to other chores while polling its
input P1.0 (turned HIGH if the slave is
done). The PAD in the PSD3XX with the
master processor tri-states its PORT A and
port B during slave processor ('373
Latch - SRAM) activity and vice-versa. The
PADs in the master/slave processors
generate the necessary ALE, RD and WR
signals necessary to write into or read out
of the shared SRAM.

The common SRAM (CD6116) is accessed
by both microcontrollers in byte mode. All
the control lines on port B of both PSDs are
configured as open drain drivers. Both
microcontrollers can access the latch and
the SRAM without conflict because the PAD
equations controlling the port B on both
PSD3XXs are based on HOLD and
HLDACK signals generated by the
master/slave processors. The HOLD Signal
is connected to port C pin 0 or A 16 and the
HLDACK signal is connected to port C
pin 1 or A 17 of both master and slave
PSD3XXs and also to INTO (master), P1.0
and P1.1 of both master/slave processors
respectively. Refer to figure 4 for specific
details.
As long as no HOLD request comes from
the slave processor, HLDACK generated by
the master processor remains HIGH which
tri-states the slave processor's PSD3XX's
port B and enables the master processor's
PSD3XX's port B control to the '373 latch
and the SRAM (CD6116). Please refer to
the schematic in figure 4, Master PSD
equations in figure 5 and Slave PSD
equations in figure 6 for specific details.
The CD6116 is a 2K x 8 SRAM and the
PSD3XX's port A address lines (AD-A7)
are connected to the SRAM's address
lines. This implies that only 256 bytes of the
shared SRAM are accessible and these
bytes roll over for every 256 bytes in the
higher address ranges.

-------------------------------------~~~--------------------------------~1-~1~13

~:::;tc:all:ll:l:'ll

-:"
....
....

~ ..... Q'cS'
iD'~~nt::::

iii

""

a

CS'
:::z

~

~~Cil

:00,:

~

1n'

:!!!l

C!i'

~ c:a
i:w~5?~
::i
Qii'.

&tit
_

~

(g

~

;;;;

~

~

tll

""
if

Ii

....
.....

~

MASTER SECTION

SHARED LATCH & SRAM

.-PORT A

MPADO-MPAD7

L
A
T
C
H

MADO-MAD15
MASTER
PROCESSOR

MASTER
PSD3XX

111""1
I111111
II111111

CONTROL

11~lh

1I11i'11\

PORTS B &C

i/o
80C31

PSD3XX

373 7'

AO-A7

S
R
A
M

SLAVE SECTION

SPADO-SPAD7

,--i\

PSD3XX

_1
COMMON CONTROURESPONSE SIGNALS

Legend:
Master Processor's Address/Data Bus.
Master PSD3XX's Address/Data from Port A.
Slave Processor's Address/Data Bus.
Slave PSD3XX's Address/Data from Port A

<

SADO-SAD15

>
SLAVE
PROCESSOR

<

CONTROL

PORTSB&C

r'
ADDRESSIDATA

MADO-MAD15
MPADO - MPAD7
SA DO - SAD15
SPADO - SPAD7

SLAVE
PSD3XX

6116 7"

I<=-

PORTA

>
8OC31

110

PSD3XX - Application Note 017

Figure 3.
Flow Chart of
Track Mode
Implementation
Normally Master is ACTIVE.
HOLD = HIGH (P1.0) (input).
HOLDACK = HIGH (P1.1) (output).
Master PSD's ports ABC active.
Slave PSD's ports tristated.

Master processor senses
HOLD = HIGH (P1.0 = 1)
and turns HOLDACK HIGH

=

Slave PSD senses
HOLD = HIGH & HOLDACK = HIGH.
Tri-states PORTs A, B &C.
Now master PSD takes the control
ofSRAM.

Master Processor
processes INTO &
sets HOLDACK (P1.1)
to LOW, continues
to poll P1.0 while
attending to other
chores.

Master PSD3XX senses
HOLD LOW (P1.0),
HOLDACK LOW (P1.1),
and tristates its
PORTs A, Band C.
SRAM available to
SLAVE PSD processor.
Once done, SLAVE
turns HOLD = HIGH.

=

=

NO

----------------------------------rs=ar.=------------------------------~1-~11~5
---=

";'"
.....
.....

~

Figure 4. Track Mode Schematic

S

."

I

1

::t C3
-=-

Ul

12
13
14
15

RESET

36
PO.41AD4
PO.S/ADS 34
PO.6/AD6 33
PO.7/AD7 32

26
27
28
29
30

AD4
ADS
AD6
AD7

PA4
PAS
PA6
PA7

P2.OIA8
P2.lIA9
P2.21Al0
P2.3/All
P2.4/A12
P2.S/A13

21

31

24
25
26
27

35
36
37
38

AD8
AD9
AD10
ADll
AD12
AD13

PBO 11
PBl ~
PB2 8
PB3
PB4
PBS

28

39

~ Pl.0

111111111

111111111

f-7

(-j
21
PAO 20
PAl 19

T1

Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.6
Pl.7

11111111

MASTER SECTION
23
24 ADO
25 ADl

INTO
INTl
TO

3
4
5
6
7
8

C4

EAlVP

Xl

9

~

18 -=X2 rJilI
PO.O/ADO I ~R
PO.lIADl r"7

19

D

111""11
III111

I

Y11O:

~g:~!g~

~~

~~:~!~~

lID

U2

A~'i~
RXD

18
17
16
15
14

A

~:~ ~

lID

~g!~ T
PCOl40

~~~ET

11
10

-----~
80C31

18
17
16
15
14

rtrt-

WR
BHEIPSEN

~~

21
20 PAO
~9 PAl

If"-

!g~~

17
16

WR
PSEt,!

~!~

PA4
PAS
PA6
PA7

HOLD...../

!g~

23
24
25
26
27
28
29
30

'1,
~. PBO
,~
• PBl
• PB2
o PB3
7 PB4
6 PBS
5 PB6
4 PB7

AD8
AD9
AD10
ADll
AD12
AD13
AD14
AD1S

'0 PCO
I PCl
PC2

lID 22
WR 2
BHEIPSEN ~3
ALE 3

11

V

A19/CSi

PSD311

ADO
ADl
AD2
AD3
AD4
ADS

~!~

! II .!,~

~

C6'T'

llA

18 ~-------XXlll~
X2
--"391
PO.OIADO
38 PO.lIADl
EAlVP I~
-:!:37 PO.21AD2
36 PO.3/AD3
35 PO.41AD4
34 PO.51ADS
33 PO.6/AD6
RESET 9'--_ _-,
32 PO.7/AD7

-=-

U3

!g~

~~

lcs
:::c

SLAVE SECTION

Y21m

A~~~~

31
32
33
35

36
37
38
39

43

------~

PSD311

21
22
23
24

~

26
27
28

P2.0/A8
P2.1/A9
P2.21Al0
P2.3/All
P2.41A12
P2.51A13
P2.6/A14
P2.7/A1S

17 lID
1 WR

PSE~

11 ALEIP
10

~~~

~------~

-=-

HOLDACKJ

1-'1

80C31

HOLDACK

HOLDACK

HOLD

HOLD

:r
'T'

PAO- PA7

PBO-PB2
Cl

'----

R4

3
4

~

Vee

IRl
4700

....L..

Shared PBO
(MALEISALE)
Vee

NOTE:
(R4C1) » (R5C2) Typical
R4 = 8.2 K, C1 = 10 !iF
R5 = 4.1 K, C2 = 10 !iF

13
14
17
18

~R2

4700

1

r

DO
01
02
03
04
05

g~

vee

~RS

U6

US
QO
Ql
Q2
Q3
Q4
QS
Q6
Q7

2
5
6
9
12
15
16
19

AO
Al
A2
A3
A4
2 AS
1 A6
23 A7

!:

22
19 Al0

DC
G

DO
01
02
03
04
05
06
07

9
10
11
13
14
15
16
17

....L..C2

T

(-j Shared
LATCH and SRAM

-=-=-

R3
ee
4700
Shared PBl (MRD / SRD)
Shared PB2 (MWR / SWR)

Legend:
Prefix

M

Master

S

Slave

I
:b.

:f5

~

III

i"

1=
i;'
t:::I

.....
.....

PSD3XX - Application Note 017

Figure 5.
MasterPSD
Equations
ALIASES
/CS8/Al6 = HOLD
/CS9/Al7
HOLDACK
/CSO = MALE
/CSl = MRD
/CS2 = MWR

=

*****************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
MX
Data Bus Size:
8
CSI/Al9:
CSI
Reset Polarity:
LO
ALE Polarity:
HI
WRD/RWE:
WRD
Al6-Al9 Transparent or Latched by ALE:
T
Using different READ strobes for SRAM and EPROM: Y
Separate SRAM and EPROM Address spaces:
N

*****************************************************************
PORT A
CSADIN

Address/Data Direction Control

= HOLDACK

*

CSADOUTl = HOLDACK

HOLD

*

*

Al5

*

/Al4

*

Al3

*

/Al2

HOLD

CSADOUT2 = HOLDACK * HOLD * Al5 * /Al4 * Al3 * /Al2 * RD * /WR

*****************************************************************
PORT B CONFIGURATION
Bit No.
0

1
2
3
4
5
6
7

CS/IO.
CSO
CSl
CS2
CS3
CS4
CS5
CS6
CS7

CMOS/OD.
00
00
00
00
00
00
00
00

CHIP SELECT EQUATIONS
MALE = /( HOLDACK * HOLD * / ALE
MRD = /( HOLDACK * HOLD * Al5 * /Al4 * Al3 * /Al2 * / RD
MWR = /( HOLDACK * HOLD * Al5 * /Al4 * Al3 * /Al2 * / WR

-----------------------------------~~~--------------------------------,--,-,-7

PS03XX - Application Note 017

Figure 5.
MasterPSD
Equations
(Cont.)
*****************************************************************
PORT C CONFIGURATION
Bit No.

o

1
2

CS/Ai.
A16
A17
A18

*****************************************************************
ADDRESS

MAP

A A A A A A SEGMT

SEGMT

EPROM

EPROM

19 18 17 16 15 14 13 12 11 STRT

STOP

START

STOP

A A A
Name

ESO

N

N

ESI

N

N

ES2

N

N

ES3

N

N

ES4

N

N

ES5

N

N

ES6

N

N

ES7

N

N

RSO

N

CSP

N

___________________________________

1-118

fE=aF~

'==§§

File

___________________________________

PSlJ3XX - Appl/atilln Nllt. 017

Figure 6.
Slave'SD
Equations
ALIASES
/CS8/Al6 = HOLD
/CS9/Al7 = HOLDACK
/CSO = SALE
/CSl = SRD
/CS2 = SWR

*****************************************************************
GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/Al91
Reset Polarity:
ALE Polarity:

MX
8
CSI
LO
HI

WRD/RWE I

WRD

Al6-Al9 Transparent or Latched by ALE:
L
Using different READ strobes for SRAM and EPROM: Y
Separate SRAM and EPROM Address spaces:
N

*****************************************************************
PORT A
CSADIN

=

CSADOUTl
CSADOUT2

Address/Data Direction Control

/HOLDACK * /HOLD * Al5 * /Al4 * Al3 * A12

= /HOLDACK *
= /aOLDACK *

/aOLD
/aOLD * A15 * /Al4 * Al3 * Al2 * RD * /WR

*****************************************************************
PORT B CONFIGURATION
Bit No.
0

1
2
3
4
5
6
7

CS/IO.
CSO
CSl
CS2
CS3
CS4
CSS
CS6
CS7

CMOS/OD.
OD
OD
OD
OD
OD
OD
OD
OD

CHIP SELECT EQUATIONS
SALE

= /(

/aOLDACK

*

/aOLD

* /

ALE )

SRD - /( /aOLDACK * /HOLD * AlS * /Al4 * Al3 * /Al2 * / RD
SWR

= /(

/HOLDACK * /HOLD * AlS * /Al4 * AlJ * /Al2 * / WR

--.-~
----------------------------------~~~-------------------------------,--,--,9

PSlJ3XX - Application 1ID18 011

Figure 6.
SlavePSD
Equations
fCont )************************************************ *****************
PORT C CONFIGURATION

Bit No.

CS/Ai.
A16
A17
A18

o

1
2

*****************************************************************
ADDRESS

Name

MAP

A A A A A A SEGMT

SEGMT

EPROM

EPROM

19 18 17 16 15 14 13 12 11 STRT

STOP

START

STOP

A A A

ESO

N

N

ESl

N

N

ES2

N

N

ES3

N

N

ES4

N

N

ES5

N

N

ES6

N

N

ES7

N

N

RSO

N

csp

N

Conclusion

This application note clearly shows how
PSD3XX's track mode could be best
utilized in resource sharing configurations
with microcontrollers. Using PSD3XXs in
this kind of a design provides the following
significant advantages to the designer:
Q Real estate savingll on-board
(reduced chip count).

File

Q Shorter time to market
Q Power savings
Q No additional glue logic.

It also offers flexibility in redesigning efforts
by simply changing the configuration of the
PSD3XXs.

Q Cost savings

-1--1-20-----------------------------~.iFAr--------------------------------

--

--.............
-----.-..-------if iii iii

E:=-

--~~-""

Programmable Peripheral
Application Note 018
Security of Design in the PSD3XX
By Dud; Moran

Introduction

The PSD3XX is a family of field programmable and UV erasable microcontroller
peripherals that have the ability to interface
to virtually any microcontroller without the
need for external glue logic.
Any PSD3XX family member is a complete
microcontroller peripheral solution with
Memory (EPROM, SRAM), Logic, 1/0 Ports
and a Security bit on chip.
In today's competitive business environment, where the cost of the product and its
quick introduction to market are the most
important factors for success, some
companies tend to copy a competitor's
design. By doing so, they can save
development time which can reduce their
engineering cost and eventually reduce the
product's price and its introduction time to
the market.

Use of the
Security Bit

Since the PSD3XX is a field programmable
device, its contents may be read by an I.C.
programmer, decompiled and copied by a
competitor.
Obviously, it is an undesirable situation for
the EPROM, PAD and configuration data of
the PSD3XX to fall into the hands of a
competitor. To prevent this, the PSD3XX
device implements a security "fuse" or
programmable bit feature to protect its
contents from unauthorized access and use
by a competitor.
Uploading the programmed data from
EPROM, PAD, ACR and NVM port configuration sections of a secured PSD3XX
device is disabled by the security bit
(if turned ON). The RAM of the programmer
(after trying to upload a secured PSD3XX
device) will contain invalid random data.

This is true mainly for the consumer and
commodity product markets where microcontrollers are widely used. The PSD3XX,
as the primary microcontroller peripheral,
contains all the important code and
architectural data that a potential competitor
may want to copy.

A secured PSD3XX device will function
properly in the system - the microcontroller
will be able to access the EPROM, SRAM,
PAD and the 1/0 ports but any attempt to
read or verify the contents of a secured
PSD3XX by external hardware will fail.

PSD3XX devices contain non-volatile
configuration bits to enable the user to set
and configure the device to the proper
operational mode. The configuration bits will
configure the device to interface successfully with the microcontroller and also
configure the PSD3XX 1/0 Ports. The
configuration bits are programmed during
the programming phase and cannot be
accessed in operational mode.

2) The NVM section of the PSD3XX device
contains port configuration bits for proper
set up of Ports A, Band C.

During programming the configuration bits
are programmed as two separate sections:
1) The ACR section of the PSD3XX device
contains global configuration bits for
proper microcontroller interface. The
security bit resides as an individual
configuration bit in the ACR section of
the device.

PSD3XX devices use the security bit to
prevent unauthorized access to the
configuration data inside. Since the security
bit is part of the ACR global configuration
bits section, it can be programmed in the
same manner as all other configuration bits.
All ACR and NVM configuration bits of the
PSD3XX are non-volatile, so their contents
will not be erased or corrupted during the
power down mode of the device (when the
PSD3XX is deselected with CSI/A 19 =
High) or during power down when Vcc is
removed.

----------------------------------[~~~------------------------------1---12-1

PSD3XX - Application Note 018

Use of the
Security Bit
(Cont.)

The security configuration bit is user
programmable and UV erasable as well, so
a secured part can be erased completely
and be reprogrammed (only if the device is
in a windowed package).
Setting the security bit will lock all the
contents of the PAD, ACR global configuration bits, and NVM port configuration
bits. By setting the security bit the device
cannot be entered into Initialization and
Override mode (resets the device and
enters it to a known default configuration
before activating the individual read mode
for each section). Any attempt afterwards to
enter the device to DIRECT mode for
uploading or programming will fail. Setting
the security bit prevents a programmer from
directly accessing the various sections of
the device.

setting the security bit, it is impossible to
read them by using external equipment
(except by the microcontroller in the system
where the PSD3XX designed in). This is
because the external equipment will lack
information about the address mapping of
the eight EPROM blocks, SRAM and I/O
ports in the memory map of the
microcontroller and the unknown status of
the global and I/O port configuration bits.
Even if an unauthorized user figures out the
configuration of the part by knowing what
microcontroller is interfaced (ALE polarity,
what type of read and write signals, etc.)
and gets data out of the PSD3XX (after
applying address and control signals to the
device), the user will have no idea where it
came from: EPROM, SRAM, I/O Port
Register, Page Register, etc. This
effectively renders the data useless.

Even though the EPROM, SRAM and 110
port contents are not directly disabled by

Setting the
Security Bit

The security configuration bit is called
CSECURITY.
If CSECURITY = 0, it means security is off
(security bit is not set and its value will be '1'
in the object file).
If CSECURITY = 1, it means security is on
(security bit is set and its value will be '0' in
the object file).
Setting the security bit and activating the
security mode can be done in two different
ways:
1) By turning security ON in the configuration menu of Maple development
software.

2) By setting the security in the
programming software (done after the
device is fully programmed and verified).

addresses of the object file created after
compilation. (See Security Bit File Location
section of this document).

If Setting of the security bit is done in the
programming software (Third party programming software or WSI Mappro
programming software), the user should
program and verify the device using a
Maple generated object file (with security
option OFF) and then set the security ON by
using a separate programming software
command.
Some third party programmer manufacturer's software will load the Maple
generated object file but mask the security
bit before programming the device. In that
case the user will have to set the security
bit (if necessary) by using a separate
command in the programming software
menu.

Using Maple development software to turn
security ON gives the security bit the value
'0', and will integrate it in one of the ACR

________________________________ r===-E________________________________
1-122

PS03XX - Application Note 018

Security
8itFi/e
Location

The object file created by compilation with
Maple software is an Intel Intelec format,
compatible file.
The programming algorithm defines the
address scrambling that translates the file
addresses to device addresses (the address
that the device "sees" on its address pins
during programming). By looking at a
screen dump or a hard copy of the object
file the user can determine the status of the
security bit.
The security bit of the PSD301/311 resides
in data bit #1 of file address 81 D3h. This
address contains three configuration bits
that reside in data bits 0 - 2, so this address
in the file can have any value between 0
and 7.
If this address has a value X1 X (where X
can be either 0 or 1), the security bit is off
('1' value means an unprogrammed bit) and
CSECURITY = 0 (displayed by Mappro WSI
programmer interface software as
SECA = 0).
If this address has a value XOX, the security
bit is on and CSECURITY = 1 (displayed

Summary

The PSD3XX family of programmable
microcontroller peripheral devices provides
security of design not readily available in
conventional PLDs and EPROMs.

by Mappro WSI programmer interface
software as SECA = 1).
The security bit of PSD302/312 resides in
data bit #1 of file address 10253h. This
address contains three configuration bits
that reside in data bits 0 - 3 (bit 3 is
reserved for future usage). This address
can have any value between 0 and F. If this
address has a value XX1 X (where X can be
either 0 or 1), the security bit is OFF
( '1' value means an unprogrammed bit) and
CSECURITY = 0 (displayed by Mappro WSI
programmer interface software as SECA =
0). If this address has a value XXOX, the
security bit is ON and CSECURITY = 1
(displayed by Mappro WSI programmer
interface software as SECA = 1).
If users do not want to look for the security
bit status in the object file, they can call
MAPPRO programming software from the
main menu of MAPLE, Load the RAM with
the object file and Display the ACR
configuration bits status on the screen.
The value of SECA will indicate the status of
the security bit (SECA = 0 means security is
OFF, SECA = 1 means security is ON).
Though not entirely fool-proof, the security
bit feature helps make it more cost effective
for competitors to design their own
hardware instead of trying to copy systems
that already exist.

---------------------------------~~~~-----------------------------1--1--23

PSD3XX - Application Note 018

---------------------------------r==~~---------------------------------1-124
====

ii'EE:=iE
------------------r~

. . . . . .~
. . __

~~~

Programmable Peripheral
Application Note 019
The PSD311 Simplifies an Eight Wire Cable
Tester Design and Increases Flexibility
in the Process - By Timothy E. Ounallin, Antec - Anixter Mfg.
and Karen S. Spesard, WSI

Abstract

With the ever increasing complexity of
wiring networks and cables to match a wide
variety of computer and telecommunication
systems, a means of testing them becomes
a necessity. The wire tester design
described below is a simple yet effective

design which uses the Motorola 68HC11
and WSI PSD311 pairto create a system
that insures 8-wire cables are wired
properly, and at the same time offers a
substantial increase in design flexibility
over alternative hardware solutions.

Introduction

More and more microcontroller and
microprocessor designers are trying to
design integrated core-based systems with
the intention of being able to easily
configure their systems to fit a wide variety
of product applications. The problem is that
when these applications require new or
changing features such as expanding II0s
or address maps, they may find their
designs are not flexible enough to
accommodate the new requirements,
forcing a lengthy and expensive redesign
anyway.

can be re-configured for other applications
using the same core design. Also, the
PSD3XX product family can enhance
microcontroller-based systems in other
ways. For instance, it can improve system
integration resulting in lower system costs,
and it can significantly shorten time to
market resulting in increased revenues and
profits.

A solution to this problem is to design in
user·configurable programmable peripheral
products which are flexible enough to
accommodate future design revisions
without the need for board relayout. The
PSD3XX family from WSI, Inc., fits this
profile exactly in that the products can be
tailored to a specific application and then

The Cable
Tester System
Design

The cable tester described below operates
by sending a known bit pattern through the
cable under test and checking the bit
pattern at the other end. The hardware
configuration utilized to achieve this
function is shown in Figure 1.
Note that there are very few components
overall in the design. The core contains
just the 68HC11 microcontroller from
Motorola, the PSD311 Programmable
Peripheral with Memory from WSI
and a few other key components including
a keypad, LCD display, and an optional
RS232 communications device.

In the cable tester system in which the
PSD311 was used with the 68HC11, the
PSD311 integrates address decoding,
latches, 32K x 8 EPROM, and 2K x 8
SRAM all into a one-chip user-configurable
microcontroller peripheral. It also replaces
the two ports lost by the 68HC11 to extend
program and data memory outside the
MCU with two additional configurable 8-bit
1/0 ports, and adds a third 3-bit port, while
easily enabling still further port expansion.

Also note that the interconnections
between the 68HC11 and PSD311 are
direct and require no "glue logic". That
means that no external latches are needed
to demultiplex the multiplexed address and
data bus from the 68HC11. And, no other
external logic is needed to generate the
address mapping for the on-board EPROM
and SRAM and to select external
peripherals, or create the control signal
interface. The PSD311 already
incorporates these featu res internally,
thereby simplifying the design considerably. In fact, the PSD311 's architecture, as
shown in Figure 2, specifically includes
32K x 8 mappable EPROM for program

1-125

-~

A30i

Figure 1. PSD311/68HC11 Implementation in the Cable Tester Design

~

20""

:J

Vee

f
+---1h
Rl07

1""

C401
1IJF

1~}..L ~JgJl
f-C102

Rl06
T

ADO/AO

8 EXTAL

AD3IA3
AD4fA4

__ ~~O] _____ 20 poO/rum
________ 21 PD1ITXD

PBO/A81141~~~~~~

74C922 9

1111111
111111111

I' 

CSO-CS7

.--

r

00--07

PROG
PORT
EXP
PBOPORT
B

~

CSIOPORT

~

-

~

CS10

.......

l_

-

r--+
CS6-

PORT
C

EPROM
256K BIT

32K BIT
BLOCK

~

PROG
PORT
EXP
PCO--

PADB

ALE/AS

RD
WR

ALE/AS

LOGIC IN

CSIOPORT
A19
CSI

A19
CSI

r-

A16-A18

I

; - - - A11-A15

SRAM
16K BIT
TRACK MODE
SELECTS

AO--A7
ADO-AD7IDO-D7

PROG
PORT
EXP
PAO-PORT
A

~

ALE/AS
RO/E

t

PROG CHIP
CONFIGURATION

WR/RIW
PSEN
RESET

PROG
CONTROL
SIGNALS

MUX or NON-MUX BUSSES
SECURITY MODE
POWER DOWN

A19/CSI

---------------------------------------'jfjf~~--------------------------------------tll#1 §
1.127

PSD3XX - Application Note 019

TheCab/e
Tester System
Design
(Cont.)

storage, 2K x 8 mappable SRAM for data
storage (or 16K x 16 EPROM and 1K x 16
SRAM, if using the similar PSD301
configured to interface to x16 micros) three
highly configurable 1/0 ports, a
programmable address decoder, and chip
select logic.

and an LCD display to the system, as well
as additional output control and input lines
with an 8-bit latch and an 8-bit buffer/line
driver. Besides these components, the
completed cable tester design also includes
an undervoltage sensing circuit for generating a reset signal and an encoder for interfacing to the keypad.

In this design, the reconstructed port space
of the PSD311 is used to add a keypad

Interfacing
To The PS0311

Not only does the PSD311 interface to the
68HC11 simply and directly because of its
internal latches and programmable control
signals - as it does with any 8-bit microcontroller - it also facilitates easy interfacing to
other components. (The PSD301 interfaces
to any 8-or 16-bit microcontrolier.) This is
possible because of its three 1/0 ports and
the Programmable Address Decoder (PAD)
which offer unsurpassed flexibility. The PAD
block diagram is shown in Figure 3.
For instance, the no "glue-logic" interface of
the keypad in the system is accomplished
by using a 74C922 encoder in conjunction
with the PAD section of the PSD311. The
PAD is useful because the Data Available
(DA) line of the 74C922 is a logic "1" when
a key is pressed, and the signal must be
inverted before it reaches the IIRO input of
the 68HC11. Connecting the encoder's DA
line to the PSD311's PC2 pin and
configuring it to be a general-purpose logic
input enables the signal to be inverted
inside the PAD. The inverted signal is then
"outputed" on PC1 which is configured as a
chip select and routed to IIRO. (See Port C
Configuration and Chip Select Equation in
Appendix A.) This simple internal
manipulation inside the PSD311 helps
reduce the number of components in the
system. By connecting the 74C922 outputs
directly to PEO-PE3 on the 68HC11, reading
of the data is straightforward.
The display used in the system is a 16
character by 2 line dot matrix LCD module.
The interface to the LCD display is handled
by mapping the data bus directly to Port A
of the PSD311 , which is configured pin-bypin to be general-purpose 110. The control
logic for the LCD is handled through two
pins on Port B: PBO and PB1, which are
also configured to be general-purpose 1/0.
(See Ports A and B Configuration in
Appendix A.) With the display used as a
"WOM" (Write Only Memory), its R/W

line is tied to ground to free an 1/0 pin of the
PSD311 for other purposes. To free up Port
A completely on the PSD311 , an
alternative approach would have been to
connect the LCD directly to the 68HC11.
To expand the 1/0 capabilities of the system
further, two port pins from the PSD311 are
used with a 74HC574 and a 74HC541 to
create 8 additional inputs and 8 additional
latched outputs, both at the same address.
(This is shown in Figure 1.) The PSD311's
chip select outputs from ports Band Care
derived from the addresses, DS strobe, and
R/W signal available as inputs into the PAD.
These chip selects will enable data to be
latched to the outputs or enable input data
onto the extended address/data bus from
the outside world, imitating the capability of
a PIA.
The chip select equation for the output latch,
74HC574, is decoded from the upper
address byte, the DS/E signal, and the
active low R/W signal as follows:

ICS8 = IA15· IA14' A13' IA12' DS'
IR/W.

The resulting latched address is $2000H
with DS = 1 and R/W = O. The chip select
equation for the input driver, 74HC541, is the
same, because the address is the same
($2000H), except that R/W is active high.
So, this equation becomes:

ICS9 = I A 15 • I A 14 • A 13 • I A 12 • DS •

RfvV.
The PSD311 simplifies the interface to the
program and data memory, external peripherals, and 110 ports in the system by integrating the address decoder internally. This
is illustrated with the direct interconnection
between the microcontroller and other
peripherals and the PSD311, without the
need for a PLD or other logic.

-1-.1-2-8---------------------------------~~~-------------------------------------

PSD3XX - Application Note 019

Figure 3.
Programmable
Address
Decoder
Block Diagram
ALEorAS ~

-

ESO
ES1
ES2
8 EPROM Block
ES3
ES4
Select Lines
ES5
ES6
ES7
RSO _ _ SRAM Block Select
CSIOPORT _1/0 Base Address
CSADIN
Track Mode
CSADOU ~~ } Control Signals
CSADOU

-'"'

D or E

J"\.

'"S

-'"'

or R/W

~

~

A19

J')

'"S

-

PAD A

-'"'

CSO/PBO

A18

'"S

....--

"S

A16

~

~

A15

~

~

_.
A14

A13
A12
A11

CSI
RESET

CSlIPB1

-

A17

-D-

CS2/PB2

CS3/PB3

-'"'
I::

CS4/PB4

-"

CSS/PB5

-'"'
I::

CS6/PB6

~

~

"S

PADB

-

..q
CS7/PB7

-

J".
~

~

[>0..-

....

_

....

~

CS8/PCO
CS9/PC1
CS10/PC2

---------------------------~Jr~------------------------~1~.n~g

PSD3XX - ApplicatiDn NDte 019

Interfacing
To The P80311
(Cont.)

The PAD enables the 8 blocks of 4K bytes
EPROM (256K bits) to be located
anywhere within the available address
space - in this case, the address space of
the 68HC11 is 64K bytes. So, the EPROM
memory is split into two segments of 16K
bytes EPROM each, separated by the 512
bytes of the internal E2PROM on the
68HC11. This means that the first 4
EPROM blocks are mapped contiguously,
as well as the last 4 EPROM blocks.
Here,the program memory (6000H-9FFFH:
EPROM2, and COOOH-FFFFH: EPROM1)
is allocated to the upper portion of address
space.
The data or SRAM memory, on the other
hand, is allocated to the lower portion of
address space and is partitioned into

Benefits
of the P80311
Usage in
System

Board layout of the cable tester design was
greatly simplified with the PSD311. In fact,
when pin 1 of the PSD311 is oriented 180
degrees from pin 1 of the 68HC11 in the
PLCC package, port B of the 68HC 11 is
directly across from the AD8-AD15 pins of
the PSD311. This positioning enables close
layout of the two parts, greatly reducing
costs due to less board space.
Additional space is saved by using the latch
and buffer for general-purpose I/O instead
of the larger and more expensive PIA. And
other I/O port lines are not sacrificed by
using the multiplexed address/data bus
instead of the Serial Peripheral Interface of
the 68HC11.

two segments: one segment containing the
SRAM internal to the 68HC11 (256 bytes)
and the other containing the SRAM
internal to the PSD311 (2K bytes). The
SRAM in the PSD311 is mapped via the
address decoder to location 5000H-5FFFH,
respectively.
Data direction and data registers of the
PSD311 's two ports are paired and
accessed via an offset from a configurable
I/O port mapped base address, such as
4000H in this cable tester design. This
enables 16-bit data instructions to access
the two I/O ports together, which in turn
reduces both the Load and Store times
during program execution.

This translates into requiring a smaller
power supply and a further reduction in
cost.
The flexibility of the PSD311 in the cable
tester design is also an advantage when
design changes need to be made quickly.
Since the I/O ports, PAD, control signals,
and EPROM are all programmable, the
part just needs to be reprogrammed when
the configuration or program memory for
the entire system needs modifying.

In fact, board space is estimated to have
been reduced by more than 50% over the
alternative cumbersome design because of
the PSD311 positioning on the PC board,
its port expansion capabilities, and of
course, the number of parts it replaces:
including a 256K EPROM, a 16K SRAM, a
latch, a decoder, and other miscellaneous
CMOS logic.

For instance, the current system has ten
I/O, eleven input, and eleven output lines
remaining. This can change if other
variables need to be stored or other
peripherals need to be accessed. To
avoid relaying out another board to
accommodate these changes, the PSD311
may be able to be reconfigured to easily
handle them. Also, if more features and/or
capabilities in EPROM are required, the
PSD312 and PSD313 with 512Kbits (64K x
8) and 1Mbits (128K x 8) EPROM, respectively, are available in the same package
and pinout.

A benefit of parts reduction is lower CMOS
power consumption that results from an
integrated single-chip CMOS peripheral/
memory solution. By analyzing the power
that would have been consumed with the
alternative design and comparing that
against the PSD311 solution, it was found
that power was reduced by at least 30%.

The PSD311 also provides additional
SRAM beyond the limited amount that may
be on the microcontroller being used.
This provides obvious benefits including
more scratchpad RAM for such uses as
storing cable "signatures" and system tests
that can be downloaded for diagnostic
purposes.

~~------------------------~Jr;--------------------------1·130

PSD3XX - Application Note 019

Benefits
of the PS0311
Usage in
System
(Cont.)

But other benefits not readily seen are also
important. For product designs that have a
short life cycle and are "pushed" to go to
market quickly, the additional SRAM gives
the designer the option of writing the code
in a high-level language such as "C",
without the worry of running out of variable

storage space. The capability of writing
software in "C" could speed up the software
development cycle, thereby reducing timeto-market!

Configuring and
Programming
thePS0311

All of the control logic, address mapping,
and port configurations for the PSD311 are
handled during device configuration as part
of WSI's easy-to-use, menu-driven PSD
MAPLE software program, which is
included in the PSD-SILVER or PSD-GOLD
software development package. See
Appendix A for the PSD311 configuration
used in this application.

"Compile". "Compile" reads the code written
for the microcontroller (in Intel hex format)
and concatenates or merges it with the
PSD311 configuration data to produce the
desired output file for downloading to a
programmer for programming.

After the configuration for the PSD311 has
been determined and "Save"d, the hex file
that is needed for programming the
PSD311 is created. That is done during

The6BHCl1/
PS0311 System
Software

The software for the 68HC11 was written
with a word processor and assembled using
a cross assembler. A portion of the cable
tester design code which is programmed
into the PSD311 is listed in Appendix B.
Here the register and RAM memory locations are set up within the first 64 clock
cycles from reset of the 68HC11 and
located at OOOOH to enable easy Direct
Addressing and Bit manipulations of often
used registers.
Initialization of the Option Register,
Timer prescaler, Stack and Serial
Communications Interface complete the
basic set up for the 68HC11 operation.
Other initialization operations include: Ports
A and B of the PSD311 which are set up as
outputs for display control and data transfer
operations, and the LCD display which is
set up to display the first screen. Final
initialization is achieved by setting several
internal registers and clearing any
pending interrupts. Now, the IRQ mask bit
can be cleared and the main program loop
entered.

That is all there is to programming the
PSD311 which is now supported on
industry-standard programmers like the
Data 1/0, BP Microsystems, Bytek, and
Logical Devices programmers as well as
the low-cost WSI MagicPro programmer.

Included in the code is a demonstration of
some useful routines which will illustrate
how to easily work with the Latch and
Buffer expansion from the 68HC11!
PSD311. Remember that these extended
addresses off the 68HC11 can be accessed
in several ways. The example code shown
uses the Bit Set and Bit Clear instructions
in the indexed addressing mode. With
these Bit Set and Bit Clear instructions,
which are read-modify-write instructions, an
additional register should be set up in the
internal RAM, not on the latched (writeonly) address, so the
instructions will function properly. Data can
then be manipulated and stored as a
complete byte to the latch enabling data to
be read and the current value in the latch to
be checked. (Bit manipulation on the
latched addresses using the indexed
addressing mode will result in a correct
bit change. However, the rest of the byte
will be unusable as data on the bus will be
scrambled at the rising edge of the chip
select signaL) The latch and buffer
expansion keeps software algorithms
simple.

--------------------------------~~~~-----------------------------1--1-3-1

PSD3XX - Application Note 019

The 68HCl1/
PSD311 System
Software
(Cont.)

Regarding the software for the keypad, no
debounce software is necessary because
the 74C922 has a built in debounce circuit.
Actually, direct access from Port E to the
keypad data and the AND instruction allows
easy compare and execution of the correct
routine.

The remaining subroutines in the program
are straightforward and basic to most
microcontrollers and microprocessors.
Those used by the 68HC11 are found in
previously published handbooks and
articles which can be obtained through
your local Motorola sales office.

Putting the

The 68HC 11/PSD311 cable tester design
could be expanded very easily with
software to learn many dIfferent wIfing
configurations and to check several cables
against a good one. Its usefulness can also
be increased by making it battery operated
for field use because of the low current
draw of the tester.

The cable tester, as designed, will display
the test results and step through the
program to show the pin by pin connections
of the cable. Results are then stored and
later fed into a computer through the
RS232 communications port of the tester.

Requirements for microcontroller-based
designs are continually changing and to be
able to adapt to these changes means
being flexible. Of course, flexibility in
hardware is sometimes hard to achieve,
while flexibility in software is mostly a
given. One of the goals of the PSD3XX
family of products is to bridge the gap in
flexibility between hardware and software.

a user-configurable peripheral solution for
hardware designers. So, if an application is
modified and the 1/0 configuration
changes, or design fixes are required, the
P.C. board does not have to be
re-engineered. The PSD3XX can just be
reprogrammed to reflect the new changes.

System to
Work

Summary

By that, it is meant that hardware will not be
a gating item when developing a new
design that needs to be introduced to
market quickly. And the PSD311 , as
illustrated in this cable tester design,
addresses that issue perfectly by providing

The flexibility provided by the PSD311
solution in this design is crucial in that it
enabled development to be completed
quickly and successfully using a "core"
approach which can handle many different
cable applications, including applications
for telephone interconnections, printers,
and local area networks.

--------------------------------r====-------------------------------=--=-===
1-132

PS03XX - Application Note 019

Appendix A.
P50311 Part
Configuration
Listed in .5V1
File
A16/CS8

ALIASES
CS8
A17/CS9
IRQ
A18/CS10
DA
A19/CSI
CSI
*********************************************************************
GLOBAL CONFIGURATION

Address/Data Mode:
Data Bus Size:
CSI/A19:
Reset Polarity:
ALE Polarity:
WRD/RWE:
A16-A19 Transparent or Latched by ALE:
Using different READ strobes for SRAM and EPROM:

MX
8

CSI
LO
HI
RWE
T

N

*********************************************************************

PORT A CONFIGURATION (Address/IO)
Bit No.

Ai/IO.
CMOS/OD.
IO
CMOS
1
IO
CMOS
CMOS
IO
2
3
IO
CMOS
4
IO
CMOS
IO
5
CMOS
IO
6
CMOS
IO
CMOS
7
*********************************************************************
PORT B CONFIGURATION

a

Bit No.

CS/IO.
IO
IO
IO
IO
IO
IO
IO
CS7

a

1
2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT EQUATIONS
/CS7 = /A15

*

/A14

+

*

A13

*

/A12

*

E

*

R/W

*********************************************************************
PORT C CONFIGURATION

Bit No.

a

1
2

CS/Ai.
CS8
CS9
A18
CHIP SELECT EQUATIONS

/CS8 = /A15 * /A14 * A13 * /A12 * E * / R/W
/IRQ = DA
*********************************************************************
ADDRESS

ESO
ES1

MAP

A A A A A A A A A
19 18 17 16 15 14 13 12 11
N X N N a 1 1 a N
N X N N a 1 1 1 N

SEGMT
STRT
6000
7000

rHl;

SEGMT
STOP
6FFF
7FFF

EPROM
START
6000

EPROM
STOP
6fff

File Name
BASE301.0BJ

1-133

PS03XX - Application Note 019

AppendixA.
PSD311 Part
Configuration
Listed in .SV1
File (Cont.)
ES2

N

x

N

N

1

0

0

0

N

8000

8FFF

ES3

N

X

N

N

1

0

0

1

N

9000

9FFF

ES4
ES5
ES6
ES7
RSO

N
N
N
N
N

X
X
X
X
X

N
N
N
N
N

N
N
N
N
N

1
1
1
1
0

1
1
1
1
1

0
0
1
1
0

0
1
0
1
1

N
N
N
N

0

COOO
DOOO
EOOO
FOOO
5000

CFFF
DFFF
EFFF
FFFF
57FF

CSP

N

X

N

N

0

1

0

0

0

4000

47FF

cOOO
dOOO
eOOO
fOOO

cfff
dfff
efff
ffff

BASE301.0BJ
BASE301.0BJ
BASE301.0BJ
BASE301. OBJ

****************************** END ***********************************

CDATA
CADDRDAT
CRRWR
CA19/(/CSI)
CALE
CRESET
COMB/SEP
CADDHLT

1
0
0
0
0
0

CPAF2

0

CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1
CPAF1

0
0
0
0
0
0
0
0

[0]
[ 1]
[2]
[3]
[4]
[5]
[6]
[7]

CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPACOD
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF
CPBF

0
1

[2]
[3]

[4]
[5]
[6]
[7]

[0 ]
[ 1]
[2]
[3]
[4]
[5]
[ 6]
[7]

CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD
CPBCOD

0
0
0
0
0
0
0
0

[0]
[l]

1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0

[0]
[ 1]
[2]
[3]
[4]
[5]
[6]
[7]

CPCF [0 ]
CPCF [ 1]
CPCF [2]

1
1
0

'--I!'§

-------------------------------------,_~_=_~_ar-------------------------------------

1-134

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design
0000
0000

CPU
HOF

"6Sll.TBL"
"INTS"

i

i***************************************************** *****

,· *
,· *
,· *
,· *
i*

,.*
,.*
,.*
i*
·, *
,· *
,· *
,· *
,· *
,.*

THE 68HCll IN CONJUNCTION WITH THE PSD301
ARE USED IN DEVELOPEMENT OF SOFTWARE FOR
DISPLAY, KEYBOARD FUNCTION, AND OTHER APPL.
MEMORY MAP:EPROM(l)
COOO-FFFF (PROGRAM)
EEPROM
B600-BFFF (68HCll)
EPROM(2)
6000-9FFF (DATA)
RAM
5000-5FFF (PSD30l)
I/O
4000-4007 (PSD30l)
LAT
2000
(LATCH & BUFFER)
RAM
1000-10FF (68HCll)
I/O & REG 0000-003F (6SHCll)

*
*
*
*
*
*

*
*
*
*
*
*

BY TIM DUNAVIN
ANTEC
ANIXTER MANUFACTURING

*

*
*

i***************************************************** *****

6000

,

ORG

06000H

iDATA MEMORY

i***********************
i*
LOOKUP TABLES
*
i***********************
i

6000 363848433lDATTAB:

DFB

i

6011 54494D4F54CREDITS: DFB
6023 4l4E544543
DFB
6037 524F434B20
DFB

"68HCll/PSD311 UP" ,OOH
"TIMOTHY E. DUNAVIN"
"ANTEC - ANIXTER MFG."
"ROCK FALLS, ILL. 61071"

i***************************************************** **

COOO
103D
4000
2000
0000
0001
0002
0003
0004
0005
0006
0007
0008
0009
OOOA
OOOB
OOOC
OOOD
OOOE
OOOF

i

INIT:
PORTBC:
LAT:
KEYl:
KEY2:
KEY3:
KEYA:
KEY4:
KEY5:
KEY6:
KEYB:
KEY7:
KEY8:
KEY9
KEYC
KEYZ
KEYO
KEYY
KEYD

ORG

OCOOOH

i PROGRAM MEMORY

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

103DH
04000H
02000H
OOH
OlH
02H
03H
04H
05H
06H
07H
08H
09H
OAH
OBH
OCH
ODH
OEH
OFH

iRAM AND I/O MAPPING REGISTER
iI/O BASE ADDRESS OF THE 301
iLATCH AND BUFFER
iKEYPAD 1
;KEYPAD 2
iKEYPAD 3
;KEYPAD A
;KEYPAD 4
iKEYPAD 5
iKEYPAD 6
iKEYPAD B
;KEYPAD 7
;KEYPAD 8
;KEYPAD 9
iKEYPAD C
;KEYPAD *
iKEYPAD 0
iKEYPAD #
iKEYPAD D

___________________________________

f==:F~

--==

___________________________________
~m

PSD3XX - Application Note 019'

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
COOO OF
COOl 8610
C003 B7103D

;************************************************
INITIALIZATION ROUTINE
*

;*

;************************************************
;
;NOTE: OPTION and TMSK2 must
cycles out of RESET
;
START:
SEI
LDAA
#010H
STAA
INIT

be programed in first 64 E
;SET IRQ MASK
;SET RAM AT 1000 AND
;SET REGISTERS AT 0000

;************************************************
;

;******* 64 BYTES OF REGISTER AREA
EQU

OOOOH

0002
0003
0004
0005

PORTA:
;
PIOC:
PORTC:
PORTB:
PORTCL:

EQU
EQU
EQU
EQU

0002H
0003H
0004H
0005H

0007
0008
0009
OOOA
OOOB
OOOC
0000
OOOE

DDRC:
PORTO:
DDRD:
PORTE:
CFORC:
OC1M:
OC1D:
TCNT:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0007H
0008H
0009H
OOOAH
OOOBH
OOOCH
OOODH
OOOEH

0010

TIC1:

EQU

0010H

0012

TIC2:

EQU

0012H

0014

TIC3:

EQU

0014H

0016

TOC1:

EQU

0016H

0018

TOC2:

EQU

0018H

TOC3:

EQU

001AH

001C

TOC4:

EQU

001CH

001E

TOC5:

EQU

OOlEH

0020
0021
0022
0023
0024
0025
0026
0027
0028
0029
002A =
002B
002C
0020
002E
002F
0030
0031
0032
0033
0034

TCTL1
TCTL2
TMSK1
TFLG1
TMSK2
TFLG2
PACTL
PACNT
speRl
SPSR:
SPDR:
BAUD:
SCCR1:
SCCR2:
SCSR:
SCDR:
ADCTL:
ADR1:
ADR2:
ADR3:
ADR4:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

0020H
0021H
0022H
0023H
0024H
0025H
0026H
0027H
0028H
0029H
002AH
002BH
002CH
0020H
002EH
002FH
0030H
0031H
0032H
0033H
0034H

0000

001A

=

=

*******

;PORT A DATA REGISTER
;0001 IS RESERVED
;PARALLEL I/O CONTROL REGISTER
;PORT C DATA REGISTER (ADO - AD7)
;PORT B DATA REGISTER (A8 - A15)
;PORT C LATCHED DATA REGISTER
;0006 IS RESERVED
;DATA DIRECTION REG FOR PORT C
;PORT 0 DATA REGISTER (RxD, TxD, AND I/O)
;DATA DIRECTION REG FOR PORT 0
;PORT E DATA REGISTER
;TIMER COMPARE FORCE REGISTER
;OUTPUT COMPARE 1 MASK REGISTER
;OUTPUT COMPARE 1 DATA REGISTER
;TIMER COUNTER REGISTER (16 BIT)
;OOOF LSB TCNT
;TIMER INPUT CAPTURE REGISTER 1 (16 BIT)
; 0011 LSB TIC1
;TIMER INPUT CAPTURE REGISTER 2 (16 BIT)
;0013 LSB TIC2
;TIMER INPUT CAPTURE REGISTER 3 (16 BIT)
;0015 LSB TIC3
;TIMER OUTPUT COMPARE REG 1 (16 BIT)
;0017 LSB TOC1
;TIMER OUTPUT COMPARE REG 2 (16 BIT)
;0019 LSB TOC2
;TIMER OUTPUT COMPARE REG 3 (16 BIT)
;OOlB LSB TOC3
;TlMER OUTPUT COMPARE REG 4 (16 BIT)
;0010 LSB TOC4
;TIMER OUTPUT COMPARE REG 5 / INPUT CAPTURE
;REGISTER 4 (16 BIT) 001F LSB TOC5/TIC4
;TIMER CONTROL REGISTER 1
;TIMER CONTROL REGISTER 2
;MAIN TIMER INT MASK REGISTER 1
; MAIN TIMER INT. FLAG REG 1
;MAIN TIMER INT MASK REGISTER 2
; MAIN TIMER INT. FLAG REG 2
;PULSE ACCUMULATOR CONTROL REG
;PULSE ACCUMULATOR COUNT REG
;SPI CONTROL REGISTER
;SPI STATUS REGISTER
;SPI DATA REGISTER
;SCI BAUD RATE CONTROL REGISTER
;SCI CONTROL REGISTER 1
;SCI CONTROL REGISTER 2
;SCI STATUS REGISTER
;SCI DATA REGISTER
;A/D CONTROL/STATUS REGISTER
;A/D RESULT REGISTER 1
;A/D RESULT REGISTER 2
;A/D RESULT REGISTER 3
;A/D RESULT REGISTER 4
;0035 - 0038 RESERVED

~=-------------------------'_JL_~~.~--------------------------1-136
'Sf"

PS03XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
0039 =
003A =
003B
003C
003E
003F

OPTION:
COPRST:
PPROG:
HPRIO:
;INIT:
TEST1:
CONFIG:

EQU
EQU
EQU
EQU
EQU
EQU
EQU

0039H
003AH
003BH
003CH
003DH
003EH
003FH

SYSTEM CONFIGURATION OPTIONS
ARM/RESET COP TIMER CIRCUITRY
EEPROM PROGRAMMING REGISTER
HIGHEST PRIORITY INTERRUPT
RAM AND I/O MAPPING REGISTER (NEW ADD.)
FACTORY TEST REGISTER
CONFIGURATION CONTROL REGISTER

;

i******* 256 BYTES OF INTERNAL RAM *******

1000
1001
1002
10FF

FLAGS:
LA1:
STOR:
STACK:

EQU
EQU
EQU
EQU

1000H
lOOlH
1002H
10FFH

;FLAG REGISTER
;LATCH DATA REGISTER
;BASIC RAM STORAGE AREA
;STACK AREA

;

;******* 2K x 8 EXTERNAL RAM ********
MASSTOR: EQU
OSOOOH
;MASS STORAGE RAM IN PSD301

5000

;

;******* EEROM AREA, 512 BYTES *******

B600

EROM:

EQU

OB600H

;DATA RETENTION AREA

;
i************************************************

C006 01
C007 a6E3

NOP
LDAA

#OE3H

C009 9739

STAA

OPTION

COOB
COOD
COOF
C012
C01S
C017

8602
9724
7F0028
8EI0FF
8680
9726

C019
C01B
COlD
C01F
C021
C024
C027
C029
C02A

86FC
9709
8600
9708
7F002C
7F002D
962E
4F
972F

ONSCI:

C02C CEFFFF
C02F FF4004

ONPIA:

C032
C03S
C038
C03A
C03D
C040
C043
C046
C049
C04C
C04F
COSl
CO 54
COS7
COSA

DISINIT:

LDAA
#002H
STAA
TMSK2
CLR
SPCR
LDS
#STACK
LDAA
#080H
STAA
PACTL
;PA7 OUTPUT
INITIALIZE THE SCI TO 9600 BAUD AT 8MHZ (DISABLED)
LDAA
#OFCH
;INIT. PORT D DDR (02H)
STAA
DDRD
;PDO, PD1 - INPUT, PD2-PDS - OUTPUT
LDAA
#OOOH
;SET UP PORT D
STAA
PORTD
CLR
SCCR1
;SET UP SER. COM. CON. REG. 1
CLR
SCCR2
LDAA
SCSR
;TO CLEAR TDRE AND TC OF SCSR
CLRA
;READ STATUS REG., LOAD TRANS. DATA REG.
STAA
SCDR
INITIALIZE THE 301 FOR DISPLAY INTERFACE
LDX
#OFFFFH
;SET UP PORTS B & C AS OUTPUTS
STX
PORTBC+4
DISPLAY SET UP (NEW REV. 15 MAY 91) *******
LDX
#02710H
;100mS DELAY (POWER UP DELAY FOR DISPLAY)
JSR
TDELAY
;TlME DELAY
LDAA
#030H
;SET UP DISPLAY
JSR
SEND I
;SEND INSTRUCTION (30 1ST TIME)
LDX
#00300H
;6.1mS DELAY
JSR
TDELAY
;TlME DELAY
JSR
SENDI
;SEND INSTRUCTION (30 2ND TIME)
JSR
TD40
;TlME DELAY
JSR
SEND I
;SEND INSTRUCTION (30 3RD TIME)
JSR
TD40
;TlME DELAY
LDAA
#038H
;FUNCTION SET (8 BIT-SINGLE LINE)
JSR
SENDI
;SEND INSTRUCTION
LDX
#00280H
;smS DELAY
JSR
TDELAY
;TlME DELAY
LDAA
#OOCH
;DISPLAY ON - NO CURSOR

;*******

;*******
;*******
CE2710
BDCOEl
8630
BDCOF4
CE0300
BDCOE1
BDCOF4
BDCODE
BDCOF4
BDCODE
8638
BDCOF4
CE0280
BDCOEl
860C

;SLIGHT DELAY TO ALLOW REGISTER SET UP
;SET UP OPTION REG. - ADPU =1, CSEL = 1,
IRQE = 1
; (ENABLE EEPROM CHARGE PUMP, IRQ EDGE
SENSITIVE)
;SET TIMER PRESCALER TO 8
;AND DISABLE TIMER INTERRUPTS
;DISABLE ALL SPI INT.
;SET UP STACK

---------------------------------------~~~--------------------------------------10137

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

C05C
C05F
C062
C065
C067
C06A
C06D
C070
C073
C076
C079
C07D

BDCOF4
CE0280
BDCOEI
8606
BDCOF4
CE0280
BDCOEI
BDCOEC
CE0190
BDCOEI
l8CE6000
BDCOCC

C080
C082
C084
C086
C088
C08A
C08C

9629
962A
86FF
9723
9725
962E
962F

SEND I
JSR
#00280H
LDX
JSR
TDELAY
#006H
LDAA
JSR
SENDI
#00280H
LDX
JSR
TDELAY
JSR
HOME
#00190H
LDX
JSR
TDELAY
#DATTAB
LDY
JSR
PDOD
;******* FINAL INIT. *******
FINIT:
LDAA
SPSR
SPDR
LDAA
#OFFH
LDAA
STAA
TFLGl
TFLG2
STAA
LDAA
SCSR
LDAA
SCDR

7F2000
CElOOl
lC0200
AGOO
B72000
B62000

;EXAMPLES OF WORKING WITH LATCH AND BUFFER
CLR
LAT
;CLEAR LATCH
LDX
#LAI
;SET INDEX
BSET
2,X,00H
;SET BIT 2 OF LAI
LDAA
O,x
;GET LATCH REGISTER
STAA
LAT
;STORE DATA TO LATCH
LDAA
LAT
;GET DATA FROM BUFFER

;SEND INSTRUCTION
;5mS DELAY
;TlME DELAY
;ENTRY MODE SET
;SEND INSTRUCTION
;5mS DELAY
;TlME DELAY
;DISPLAY CURSOR HOMEI
;4.0mS DELAY
;TlME DELAY
;TOP OF DATA TABLE
;SEND MESSAGE TO DISPLAY
;CLEAR ANY SPI INT.
;CLEAR ANY TIMER INT.
;CLEAR ANY SCI INT.

;

C08E
C091
C094
C097
C099
C09C

C09F BDCOBO

JSR

COA2 OE

BEEP

;SOUND OFFI
; CLEAR IRQ MASK

CLI
;
i*************************

;*

COA3 01
COA4 7ECOA3

MAIN LOOP
*
i*************************
;
LOOP:
NOP
JMP
LOOP

,

; RETURN

i************************************

;*

COA7
COA9
COAB
COAD
COAF

8655
973A
86AA
973A
39

SUBROUTINES
*
i************************************
;
i******* WATCHDOG SERVICE ROUTINE ******
DOG:
LDAA
#055H
;RESET WATCHDOG TIMER
STAA
COPRST
LDAA
#OAAH
STAA
COPRST
RTS
;RETURN FROM SUB.

18CEOIFF
8640
9700
CE0014
BDCOEI
4F
9700
CE0014
BDCOEl
1809
26E9
39

i******* HOOTER OSC. ROUTINE
BEEP:
#OOlFFH
LDY
BEEPl:
#040H
LDAA
PORTA
STAA
#00014H
LDX
TDELAY
JSR
CLRA
STAA
PORTA
#00014H
LDX
JSR
TDELAY
DEY
BEEPI
BNE
RTS

;

COBO
COB4
COB6
COB8
COBB
COBE
COBF
COCI
COC4
COC7
COC9
COCB

_________________________________________

1-138

r3f=aF~

=-~~B

********

;SET COUNT
;BEEPER ON
; DELAY
;BEEPER OFF

; DELAY
;COUNT -1
;IF NOT DONE, KEEP GOING
; RETURN FROM SUB.

_________________________________________

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
i******* PUT DATA ON DISPLAY

cocc
COCF
COD1
COD4
COD6
COD8

18A600
2707
BDC100
1808
20F4
39

PDOD:

PDOD1:

LDAA
BEQ
JSR
INY
BRA
RTS

0, Y
PDOD1
SENDD
PDOD

********

;GET BYTE
;IF END, GOTO NEXT1
;NEXT BYTE
; RETURN TO NEXT
;RETURN FROM SUB.

;
i******* TIME DELAY ROUTINE *********

COD9
CODC
CODE
COE1
COE2
COE5
COE7

CEOO02
2003
CEOOOF
09
8COOOO
26FA
39

TD20:
TD40:
TDELAY:

LDX
BRA
LDX
DEX
CPX
BNE
RTS

#00002H
TDELAY
#OOOOFH
#OOOOOH
TDELAY

;20uS DELAY
;150us DELAY
;DECRAMENT COUNT
;COUNT = O?
;IF NOT DONE, GOTO TDELAY
;RETURN FRO SUB.

;

,.*******

COE8
COEA
COEC
COEE
COFO
COF2
COF4
COF7
COF9
COFC
COFF

8601
2008
8602
2004
86CO
2000
CE4000
A706
1c0702
1D0702
39

CLEAR SCREEN, CURSOR HOME, AND SEND INSTRUCTION *******
CSCREEN: LDAA
#OOlH
;CLEAR DISPLAY
BRA
SENDI
;SEND INSTRUCTION
#002H
HOME:
LDAA
;CURSOR HOME
BRA
SENDI
;SEND INSTRUCTION
LINE2:
#OCOH
LDAA
;SET CURSOR TO LINE 2
BRA
SENDI
;SEND INSTRUCTION
SENDI:
#PORTBC
LDX
;SET UP DATA TRANSFER
STAA
6,X
;STORE AT PIA PORT A
BSET
7,X,02H
;DISPLAY E HIGH
BCLR
7,X,02H
;DISPLAY E LOW
;RETURN FROM SUB.
RTS
;
i******* SEND DATA TO DISPLAY

C100
C103
C105
c108
C10B
C10E
C1ll
Cll4

CE4000
A706
1C0701
1C0702
1D0702
1D0701
BDCODE
39

SENDD:

LDX
STAA
BSET
BSET
BCLR
BCLR
JSR
RTS

#PORTBC
6,X
7,X,01H
7,X,02H
7,X,02H
7,X,01H
TD40

********
;SET UP DATA TRANSFER
;SEND DATA
;DISPLAY RS HIGH
;DISPLAY E HIGH
;DISPLAY E LOW
;DISPLAY RS LOW
;150us TIME DELAY
;RETURN FROM SUB.

;
i******************************************************

;*
i*

;*
i*

ROUTINE TO CHANGE BYTE IN EEROM
*
PRELOADED X = ADDRESS IN EEROM (B600 - B7FF) *
DATA TO BE STORED, IS IN "STOR"
*
(THIS IS A MOTOROLA ROUTINE)
*

i******************************************************

Cll5 AGOO
Cll7 81FF
Cll92717
CllB 8616
C11D 973B
CllF 86FF
C121 A700
C123 8617
C125 973B
C127 3C
C128 CE0300
C12B BDCOE1
C12E 38
C12F 4F
C130 973B
C132 8602

CHGBYT:

LDAA
CMPA
BEQ
LDAA
STAA
LDAA
STAA
LDAA
STAA
PSHX
LDX
JSR
PULX
CLRA
STAA
CHGBYT1: LDAA

O,X
#OFFH
CHGBYT1
#016H
PPROG
#OFFH
O,x
#017H
PPROG

iGET DATA AT ADDRESS TO BE CHANGED
;CHECK IF ERASED
;JUMP IF BYTE ERASED
iSET BYTE, ERASE, AND EELAT

;SET EEPRG
;SAVE x

#00300H
TDELAY
PPROG
#002H

;20mS TIME DELAY
iRESTORE X
iCLEAR BYTE, ERASE, EELAT, AND EEPRG
iEND OF BYTE ERASE
;SET EELAT - DO BYTE PROGRAM

-----------------------------------------f=af~~----------------------------------------====
1-139

PS03XX - ApplicatiDn NDte 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
C134
C136
C139
C13B
C13E
C13F
C142
C145
C146
C149
C14C

973B
B61002
A700
7C003B
3C
CE0300
BDCOE1
38
7A003B
7F003B
39

STAA
LDAA
STAA
INC
PSHX
LDX
JSR
PULX
DEC
CLR
RTS

PPROG
STOR
O,X
PPROG

;GET DATA TO BE STORED
;STORE IN NEW LOCATION IN EEROM
;SAVE

#00300H
TDELAY
PPROG
PPROG

x

;20mS DELAY
;RESTORE x
;CLEAR EEPRG
;CLEAR EELAT, END OF BYTE PROGRAM
;RETURN FROM SUB.

;

i*******·**··******·*·****·***************************
ROUTINE TO SET UP AID CONVERTER
*
ACC A
VALUE TO INITIATE CONVERSION
*
BEFORE ENTRY TO THIS ROUTINE
*
i*****************************************************
CONV:
STAA
ADCTL
;SET UP AID CONVERTER
CONV1:
BRCLR
ADCTL,80H,CONV1 ;WAIT HERE TILL CONVERSION COMPLETE
RTS
;RETURN FROM SUB.
;
i****************************
;*
INTERRUPT ROUTINES
*
i****************************

;*
;*
;*

C14D 9730
C14F 133080FC
C153 39

=

;

j*****************************************************
SERIAL COMMUNICATIONS INTERFACE - IRQ
*

;*

i*****************************************************
;

C154 3B

SCOM:
RTI
;RETURN FROM INT.
;
j******************************
;* SERIAL TRANSFER COMPLETE *
i******************************

C155 3B

TRANC:
RTI
; RETURN FROM INT.
;
j*********************************
;* PULSE ACCUMLATOR INPUT EDGE *

;

j*********************************
C156 3B

;
PULSEE:

RTI

;RETURN FROM INT.

;
i********************************
PULSE ACCUMULATOR OVERFLOW *
i********************************
;
PULSEO: RTI
;RETURN FROM INT.

;*

C157 3B

;

i********************
TIMER OVERFLOW *
i********************
;
TIMEO:
RTI
;RETURN FROM INT.
;
i****************************
; * TIMER OUTPUT COMPARE 5 *
i****************************
;
COMP5:
RTI
;RETURN FROM INT.

;*

C158 3B

C159 3B

~~--------------------------"I~=-----------------------------1.140
:.:.:• •

PS03XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

i***************************

TIMER OUTPUT COMPARE 4 *
i***************************
;
COMP4:
RTI
;RETURN FROM INT.

;*

C15A 3B

,

j****************************

;*

C15B 3B

C15C 3B

TIMER OUTPUT COMPARE 3 *
i****************************
;
COMP3:
RTI
;RETURN FROM INT.
;
i****************************
;* TIMER OUTPUT COMPARE 2 *
i****************************
;
COMP2:
RTI
;RETURN FROM INT.

,

i****************************

;*

*

TIMER OUTPUT COMPARE 1

j****************************
;

C15D 3B

COMP1:
;

RTI

;RETURN FROM INT.

i***************************

;*

TIMER INPUT COMPARE 3

*

j***************************
;

C15E 3B

ICOMP3:
;

RTI

;RETURN FROM INT.

i***************************

;*

TIMER INPUT COMPARE 2

*

i***************************
;

C15F 3B

ICOMP2:

RTI

;RETURN FROM INT.

;
i***************************

;*

TIMER INPUT COMPARE 1

*

i***************************
;

C160 3B

ICOMP1: RTI
;RETURN FROM INT.
;
i****************************
;* REAL TIME INT. ROUTINE *
i****************************

C161 3B

REALT:

;

RTI

;RETURN FROM INT.

;
j**********************

;*

IRQ INT. ROUTINE

*

j**********************
;

C162 960A
C164 840F

DOIT:

C166 8100
C168 2601
C16A 3B

LDAA
ANDA

PORTE
#OOFH

;GET KEYBOARD DATA
;FILTER DATA

CMPA
BNE
RTI

#KEY1
DOIT10

;1 KEY?
;IF NOT GOTO DOITIO
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY2
DOIT20

;2 KEY?
;IF NOT GOTO DOIT20
; RETURN FROM INT.

;

C16B 8101
C16D 2601
C16F 3B

DOIT10:

rg;;

1-141

PSD3XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)
C170 8102
Cl72 2601
C174 3B
C175 8103
Cl77 2601
C179 3B
c17A 8104
C17C 2601
C17E 3B
C17F 8105
C18l 2601
C183 3B

;
DOIT20:
;
DOIT30:
;
DOIT40:
;
DOIT50:

CMPA
BNE
RTI

#KEY3
DOIT30

CMPA
BNE
RTI

#KEYA
DOIT40

;A KEY?
;IF NOT GOTO DOIT40
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY4
DOIT50

;4 KEY?
;IF NOT GOTO DOIT50
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY5
DOIT60

;5 KEY?
;IF NOT GOTO DOIT60
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY6
DOIT70

;6 KEY?
;IF NOT GOTO DOIT70
; RETURN FROM INT.

CMPA
BNE
RTI

#KEYB
DOIT80

;B KEY?
;IF NOT GOTO DOIT80
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY7
DOIT90

;7 KEY?
;IF NOT GOTO DOIT90
; RETURN FROM INT.

CMPA
BNE
RTI

#KEY8
DOIT100

;8 KEY?
;IF NOT GOTO DOIT100
; RETURN FROM INT.

#KEY9
DOITllO

;9 KEY?
;IF NOT GOTO DOITllO
; RETURN FROM INT.

#KEYC
DOIT120

;C KEY?
;IF NOT GOTO DOIT120
;RETURN FROM INT.

#KEYZ
DOIT130

1* KEY?

#KEYO
DOIT140

;0 KEY?
;IF NOT GOTO DOIT140
;RETURN FROM INT.

3 KEY?
IF NOT, GOTO DOIT30
RETURN FROM INT.

;

C184 8106
C186 2601
C188 3B

DOIT60:

C189 8107
C18B 2601
C18D 3B

DOIT70:

;

C18E 8108
C190 2601
C192 3B
C193 8109
C195 2601
C197 3B
C198 8l0A
C19A 2601
C19C 3B
C19D 8l0B
C19F 2601
C1Al 3B
C1A2 8l0C
C1M 2601
C1A6 3B
C1A7 8l0D
ClA9 2601
CIAB 3B
C1AC 8l0E
C1AE 2601
CIBO 3B
C1B1 810F
C1B3 2600
C1B5 3B

1-142

;
DOIT80:
;
DOIT90:

;
DOIT100: CMPA
BNE
RTI
;
DOITllO: CMPA
BNE
RTI
;
DOIT120: CMPA
BNE
RTI
;
DOIT130: CMPA
BNE
RTI

;IF NOT GOTO DOIT130
;RETURN FROM INT.

I

#KEYY
;# KEY?
DOIT140: CMPA
;IF NOT
BNE
DOIT150
RTI
; RETURN
;
#KEYD
DOIT150: CMPA
;D KEY?
BNE
DOIT160
;IF NOT
DOIT160: RTI
;RETURN
;
i*******************************
,.* XIRQ SERVICE ROUTINE
*
i*******************************

tal;

GOTO DOIT150
FROM INT.
GOTO DOIT160
FROM INT.

PS03XX - Application Note 019

AppendixB.
Core System
Software for
Cable Tester
Design (Cont.)

ClB6 3B

NOMASK:
i

RTI

INTER:

RTI

iRETURN FROM INT.

i*******************************
i* SWI SERVICE ROUTINE
*
i*******************************

ClB? 3B

i RETURN FROM INT.

i
i***********************************
i* RESET AND INTERRUPT VECTORS
*
i***********************************

FFCO
FFCO
FFD6
FFD8
FFDA
FFDC
FFDE
FFEO
FFE2
FFE4
FFE6
FFE8
FFEA
FFEC
FFEE
FFFO
FFF2
FFF4
FFF6
FFF8
FFFA
FFFC
FFFE

ORG

OFFCOH

DFS
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM
DWM

11*2
SCOM
TRANC
PULSEE
PULSEO
TIMEO
COMP5
COMP4
COMP3
COMP2
COMPl
ICOMP3
ICOMP2
ICOMPl
REALT
DOlT
NOMASK
INTER
START
START
START
START

i

Cl54
Cl55
Cl56
Cl5?
Cl58
Cl59
Cl5A
Cl5B
Cl5C
Cl5D
Cl5E
Cl5F
Cl60
Cl6l
Cl62
ClB6
ClB?
COOO
COOO
COOO
COOO

RES:
SERCOM:
SPISTC:
PAlE:
PAOV:
TOV:
TOCP5:
TOCP4:
TOCP3:
TOCP2:
TOCPl:
TICP3:
TICP2:
TICPl:
RTlME:
IRQ:
XIRQ:
SWI:
lOT:
COPS:
COPSl:
RESET:

iNOT USED
i SERIAL COMM. INT.
iSERIAL TRANSFER COMPLETE
iPULSE ACCUMLATOR INPUT EDGE
iPULSE ACCUMULATOR OVERFLOW
i TIMER OVERFLOW
iTlMER OUTPUT COMPARE 5
iTlMER OUTPUT COMPARE 4
iTIMER OUTPUT COMPARE 3
iTlMER OUTPUT COMPARE 2
iTlMER OUTPUT COMPARE 1
iTlMER INPUT COMPARE 3
iTlMER INPUT COMPARE 2
iTlMER INPUT COMPARE 1
i REAL-TIME INT.
iTlMER/VIA INT.
iNON-MASKABLE INT.
iSOFTWARE INT.
iILLEGAL OPCODE TRAP (START OVER)
i COP FAILURE (RESET)
iCOP CLOCK MONITOR FAIL (RESET)
iRESET

i

i************************************************

0000

END

iTHE END!!!!!

-----------------------------------------~~~jf----------------------------------------1·143

PS03XX - Application Note 019

-1--1-#-----------------------------~Jr~~--------------------------------

iFliIliI4E6J
--._---r . . - __

~

~_

i!iiF&IIIIf iii

Programmable Peripheral
Application Note 020
Benefits of 16-Bit Design with PSD3XX
By Ching Lee

Introduction

Typical 16-Bit
Microcontrol/er
System
Architecture

Embedded controller architecture has been
evolving from 4-bit, 8-bit to 16-bit through
the years. The increase in the data bus
bandwidth is a natural progression for
microcontrollers to achieve higher
performance. Today, 16-bit embedded
controllers such as the 80C196 and 683XX
families provide excellent performance at
reasonable cost. Yet many designers are
weary of the cost of higher chip count,
more board space and power consumption
in 16-bit applications and prefer to stay with
8-bit designs. Some microcontroller
manufacturers tackle this problem by
introducing processors with 16-bit internal
architectures but have 8-bit external data
busses. Later additional enhancements
such as dynamic bus sizing provide the
choice of selecting either an 8 or 16-bit bus
for further cost reduction. This compromise
There is no one standard 16-bit
architecture, especially in the field of
embedded controller applications. For a
typical 80C196 design, the basic building
block consists of two address latches
(74AC373), address decoding logic (with
PAL or discrete logic), program memory
(EPROMs), data memory (one or more
SRAM), and I/O devices.
Figure 1 is the schematic of such a system.
In this design, 64K bytes of program
memory/EPROM, and a 2K byte SRAM for
scratch pad are required. Since the
80C196 has only 64K byte memory space,
the INST signal provides the paging
capability, with program memory residing in
the first 64K page while SRAM and I/O
devices occupy the second page. The I/O
section consists of one output port
(74AC374) and other peripheral devices.
The chip select signals for the I/O devices
and memory are connected directly from
the decoding PAL outputs. The processor's
data bus width is determined by the type of

certainly increases the performance; it is
still not as good as a true 16-bit implementation.
With the introduction of the PSD3XX family
of field programmable microcontroller
peripherals from WSI, there is no reason
not to use 16-bit microcontrollers. The
PSD3XX provides an integrated solution in
a single chip, which includes user
configurable I/O ports, Chip Select outputs,
logic replacement, Page Register,
Programmable Address Decoder (PAD),
EPROM and SRAM. The PSD3XX is a
perfect match for 16-bit microcontroller
applications. In this application note, we will
look at some of the advantages of 16-bit
designs, and how PSD3XX interfaces to
microcontrollers such as the 80C196 and
68302.

bus cycle. EPROM accesses are 16-bits
wide, SRAM is 8-bits while I/O bus cycles
can be 8 or 16-bits, depending on the
device being accessed. The BWIDTH
output from the PAL informs the processor
what type of bus width is to be expected for
that particular cycle.
An I/O device usually takes longer time to
complete the bus cycle. Let us assume, in
this case, I/O devices require 3 wait states
with the exception of the I/O latch. The
configuration register of the 80C196 is then
programmed to insert 3 wait states.
Whenever there is an I/O bus cycle, the
READY output signal from the PAL goes
low to activate the processor's wait state
control to insert the programmed amount of
wait state. For memory bus cycles, no wait
state is inserted.

1-145

":" I
....

Figure 1. rypical16-Bit Microcontroller System Architecture

~

t;

Al

A2

U5

l~AO

9 I Al
A2

6l~

J.. 16MHz

c:::J

U1

us

LJXl

niiiil~::w.----,~

ICII

I~~

IIIIII,!
"--

NMI
READY
CDE
L-I-~-I BUSWIDTH
IREsET>--!-1II(] RESET
ACHO/PDO
ACH1/PO 1
ACH2/PO 2
ACH3/P0 3
ACH4/P04
ACH5/PD5
PCS6/PO 6
PCS7/P0 7
18 P2 OITXD
P21/RXD
P221EXINT
P231T2CLK
P241T2RST
P25/PWM
P2 6/T2UP-DN
P271T2CAP
HSIO
HSll
HSI2IHSO 4
HSI3IHSO 5

'-

EA

-:-

25
24
21
23

A

8OC196

00
01
02
03
04
05
06
07

13
15
16
17
18
19

~
AD2
AD3
AD4
AD5
AD6
AD7 J

27

A13
A14

M----~CE

OE
vpp

27C256
-'?!!l!-~HDO

~~
t~s.m=i1
03
AD12
3 04
01

14 05
06
07
OC
G

U6

10

I~

'Ali

Ii

~ALE "5

I INST 'I
-A ii.--:m::----t
..

01
02
03
04
05
06
07

20L10

~~~r'"
U3

II I

27C256

ADO

U7

I/O DEVICES

6
I

t:;:::
fa

;t

==
if
e;-

m

..,.,;--....£.2...1~1~

P31/ADl
P31/AD2
P31/AD3
P31/AD4
P31/AD5
P31/AD6
P31/AD7
P40/AD8
P41/AD9
P421AD10
P43/ADll
P44/AD12
P45/AD13
P46/AD14
P47/AD15
RD
WR
BHE
ALE
INST
CLKOUT
Pl0
Pll
P12
P13
P14
P15
P16
P17
HSOO
HSOl
HS02
HS03

AS
A6
A7
A8
A9
Al0

11

~

1

15
16
17
18

AD1:!
AD13
A014
AOl

PSD3XX - Application Note 020

Typical 16-Bit
Microcontroller
System
Architecture
(Cont.)

Table 1 is the memory address map of the
80C196 microcontroller, and the addresses
of the I/O devices. Address locations
OOOOH through OOFFH and 1FFEH through
207FH are reserved for the microcontroller.
The remaining locations can be used for
program/data memory or memory mapped
I/O devices. EPROM occupies the first 64K
bytes, where program codes start from
2080H to FFFFH, and a 2K look-up table
EPROMCS

The address map requires the following
PAL equations to be programmed to the
decoder PAL. The 10_CS lines are enabled
after ALE goes low.

INST
+ INST/ * A15/ * A14/
INST/ * A15/* A14 *A13/*A12/

RAMCS

Table 1.
80C196
Memory Map

resides inside the EPROM from
location 1OOOH to 17FFH. The 2K scratch
RAM and I/O starts from 4000H in the
second page.

BWIDTH

RAMCS
+ 10_CSO
+ 10_CS1
+ 10_LAT

READY

10_CSO
+ 10_CS1
+ 10_CS2
+ 10_CS3

10_LAT
10_CSO
10_CS1
10_CS2

INST/
INST/
INST/
INST/

10_CS3

INST/ * ALE/ * A15 * A14/ * A13/* A12 "I/O DEV.#3

* WR *
* ALE/*
* ALE/ *
* ALE/ *

Device

A15/* A14
A15/*A14
A 15/ * A 14
A15 * A14/

* A13/* A12
*A13*A12/"I/ODEV.#0
* A 13 * A 12 "I/O DEV.#1
* A13/* A12/ "I/O DEV.#2

INST
(Page)

Address
(Hex)

BU5width
(Bit)

EPROM (Code)

1

2080 - FFFF

16

EPROM (Table + Data)

X

1000 -27FF

16

RAM

0

4000 -47FF

8

I/O LATCH

0

5000

8

I/O CSO

0

6000

8

I/O CS1

0

7000

8

I/O CS2

0

8000

16

1/0_CS3

0

9000

16

__________________________________

fSE~~

--==

__________________________________
~U7

PS03XX - Application Note 020

16·8i'
Performance
Advantages

It is obvious that a 16-bit bus provides
more performance than an 8-bit bus,
at least the data bus bandwidth will double.
The following factors contribute to the
performance improvement:

Program Code Fetch
Instructions such as ANDB of the 80C196
consists of 4 bytes. In an 8-bit bus system
it takes 4 bus cycles to fetch the instruction,
while in 16-bit bus designs it takes only 2
bus cycles.

Data Fetch
For applications with high data transfer
rate, where indexed or indirect references
are frequently used, a 16-bit bus takes
much less time to accomplish the same
job.

Queue Flush for Branch/Jump
Instructions
A pre-fetch queue usually speeds up
instruction execution time by providing
instructions to the Execution Unit in a
timely manner. However there is a penalty
which goes with the queue when a
successful branch or jump instruction is
executed. The queue has to be flushed,
Program Counter to be reloaded, and new
instructions to be fetched. A 16-bit bus
helps to fill up the queue much faster. This
is critical to system performance since
Branch/Jump instructions are the most
frequently used instructions in general.

Free Up The System Bus

Let us look at a sample program to
calculate the differences in execution time
between an 8 and a 16-bit bus. In the
typical 16-bit design example above, there
is a look-up table residing in the EPROM.
A look-up table is a quick way for the
program to provide an output to an I/O
device based on the input value without
getting into complex mathematical
operations. The following program, which is
published in Intel application note AP-248,
does table look-up and interpolation.
Assuming the 80C196 queue is always full,
to execute the following code takes 128
state times in a 16-bit bus. In an 8-bit bus, it
takes 32 more state times just to fetch the
codes and data, not including the time the
microcontroller waits for the queue to be
filled. The estimated performance penalty
for an 8-bit bus in this application is at least
25%, and will certainly be more in the
actual run time environment. The published
statement from Intel is that it is difficult to
measure the 8-bit bus performance penalty,
but has shown to be up to 30%, depending
on the instruction mix.
The 16-bit bus design will increase the
system performance, especially for
microcontrollers which usually don't have
internal program cache or a pre-fetch
pipeline queue to lessen the penalty
caused by the bottle neck on the memory
bus. The 80C196 has an internal 4 byte
queue. This helps execution time but bus
width still remains the critical factor.

The microcontroller reduces its number of
operand fetches in a 16-bit bus, freeing the
bus for other devices which share the same
bus. In system which has a DMA Controller
or Slave Processor sharing the same
memory space with the microcontroller, the
less usage of the memory bus will enhance
system performance.

________________________________
1-148

f==:O~

=="'==::

==

________________________________

PSD3XX - Application /lote 020

Table Look-up
and
Interpolation

RSEG

at 22H

IN-VAL:
TABLE LOW:
TABLE HIGH:
IN_DIF:
IN DIFB:
TAB_DIF:
OUT:
RESULT:
OUT DIF:

dsb
dsw
dsw
dsw
equ
dsw
dsw
dsw
dsl

;Actual Input Value

1
1
1

1
;Upper Input-Lower Input
IN_DIF
:byte
1
;Upper Output- Lower Output
1
1

;Delta Out

1

CSEG at 2080H
LD

SP, #lOOh

Look:
LDB
SHRB
ANDB

AL, IN VAL
AL, #3
AL, #11111110B

;Load temp with Actual Value
;Divide the byte by 8
;Insure AL is a word address
;This effectively divides AL by 2
;50 AL = IN_VAL/l6
;Load byte AL to word AX

LDBZE AX, AL
LD
TABLE_LOW, TABLE [AX]

LD

SUB

;TABLE_LOW is loaded with the value
lin the table at table location AX
TABLE_HIGH, (TABLE+2) [AX]
;TABLE_HIGH is loaded with the value
lin the table at table lac. AX+2
; (The next value in the table)
TAB_DIF, TABLE_HIGH, TABLE LOW
;TAB_DIF=TABLE_HIGH - TABLE_LOW

LDBZE IN_DIF,IN_DIFB
MUL
OUT_DIF, IN_DIF, TAB_DIF

SHRAL OUT_DIF, #4
ADD
OUT, OUT_DIF, TABLE LOW

;IN_DIFB=least significant 4 bits of
; IN_VAL
;Load byte IN_DIFB to word IN_DIF
; Output_difference
;Input_difference * Table_difference
;Divide by 16 (2**4)
;Add output difference to output
;generated with truncated IN VAL as

input
SHRA OUT, #4
ADDC OUT, ZERO

; Round to 12-bit answer
; Round up if Carry = 1

No Inc:

-

ST
BR

OUT, RESULT
Look

CSEG

at 2100h

;Store OUT to RESULT
;Branch to "Look"

Table:
DCW
DCW
DCW
DCW
DCW

OOOOH,
5DOOH,
7BOOH,
5DOOH,
lOOOH

2000H,
6AOOH,
7DOOH,
4BOOH,

3400H,
7200H,
7600H,
3400H,

4COOH ;A random function
7800H
6DOOH
2200H

-----------------------------------------~~~-------------------------------------1-.1-4--9

PSD3XX - AppllcatlDn NDt. 020

I'S03XX
Solution
fOl16·Bit
Miclocontlollel

In this section, we will see how a single
PSD302 is able to replace all the basic
building blocks as shown in the design
example in Figure 1. As seen from the
block diagram (Figure 2.), the PSD302
provides the following functional blocks:

o 64K bytes EPROM, as 64K x 8 or
32K x 16

o

2K bytes SRAM, as 2K x 8 or 1K x 16,
expanding the microcontroller's internal
scratch SRAM

o

Address latches/data buffers, bus
interface to most microcontrollers.

o

Programmable Address Decoder (PAD);
provides PAL type function:
18 inputs, 24 outputs and 40 product
terms.

o

Port A: an 8-bit port, each bit can be
configured as :
-I/O line
-latched address output (AD-A?)
- track ADO/AD? as I/O lines in track
mode for shared access.
- data port DO/D? in non-multiplexed
mode
- CMOS or open drain output

o

Port B: an 8-bit port, each bit can be
configured as :
-I/O line
- chip select or logic replacement output
from the PAD
- D8-D15 in non-multiplexed mode
- CMOS or open drain output

o

Port C: 3-bit port, each bit can be
configured as input to or output from the
PAD

o

Page Register: a 4-bit Page Register for
bank switching

o A 19/CSI input pin for power down
configuration
Figure 3 is the schematic of the design
example with the PSD302. Not all the
functions of the PSD3XX are utilized in this
example. The Page Register IS not used
since the INST signal from the 80C196 can
be easily included in the PAD for page
decoding (for design with the Page
Register, see WSI Application Note 015).
The internal EPROM and SRAM of the
PSD302 replaces US, U6, and U? in Figure
1. Port A is configured as an I/O port to
replace U3, the I/O latch. The PAD provides
decoding functions for all the chip selects,
as well as the READY and BWIDTH inputs
to the microcontroller. Please note the
PSD302 is able to provide a 16-bit SRAM
for faster data accesses.
In this application the PSD302 is configured
to operate in a 16-bit, multiplexed mode.
The PAL equations are programmed into
the PAD. Depending on the particular bus
cycle, the PSD302 latches the microcontroller address, determines which
device is to be enabled, and provides data
output for a read cycle. If it is an I/O bus
cycle, either Port A is enabled or one of the
I/O_CS lines are activated. At the same
time, the appropriate READY and BWIDTH
signals are generated.

ru'~- - - - - - - - - - - - - - - - - -

-1-·1-5-0-----------------~,

PSD3XX - Application Note 020

Figure 2.
'SD302
Block
Diagram

PAGE LOGIC

r-L
A
T
C
H

AD6-AD15

,'~t=r

A11-A15

- - CSIOPORT

AS-A10
A19
CSI

A19
CSI
PAD A

ALE/AS

RESET

.. - -

L..--

r---

'--

'1'6i8

.... .1 ~

~.

...... ~

~

~

CS8CS10

CSD-

e

r

D8-D15

~

PROG
PORT
EXP
PBDPORT
B

~

L..--

CSIOPORT

DO D7

~

'---

-.

EPROM
512K BIT

64K BIT
BLOCK

.,.

... - -

r--

27PT

PORT
C

--ES7
ES6
ES5
ES4
ES3
ES2
ES1
.....
ESO .....

L
A
T
C
H

PROG
PORT
EXP.
PCO-

PADB

WR
RESET

13 PT

'--

~~~

LOGIC IN

RD

WR

ALEIAS

,!

ALEIAS

RD

.--

ADD-AD7

A16-A18

SRAM
16K BIT
TRACK MODE
SELECTS

AD-A7
ADD-AD7/DD-D7

PROG
PORT
EXP
PADPORT
A

~

ALE/AS
RO/E/OS

PROG CHIP
CONFIGURATION

t

WRJRIW
BHEIPSEN
RESET

PROG
CONTROL
SIGNALS

X8, X16
MUX or NON-MUX BUSSES
SECURITY MODE
LOW POWER - CMISER

A19/CSI

-----------------------------------------'jf;r~~----------------------------------------===
1·151

PSD3XX - Application Nots 020

Figure 3.
Design Example
wlthPSD302
ADO-AD15

~

16MHz

U8
11

I
I

NMI

RESETI

ADO AD15)

2
43

~
~
16

X1

NMI
READY
CDE
BUSWIDTH
RESET

~
~
~
4

ACHO/PO 0
ACH1/PO 1
ACH2IPO 2
ACH3/PO 3
ACH4/PO 4
ACH5IPO.5
ACH6/PO 6
.....::... ACH7/PO 7

11
To
8

-t

~

.-g
~

--#

-#
-#
-#
.-M
~
~

~
..JJ...

...1!.
~

W<

-=

P20ITXD
P21/RXD
P22/EXINT
P231T2CLK
P241T2RST
P2.5/PWM
P26IT2UP_ON
P27IT2CAP
HSIO
HSI.1
HSI2IHSO 4
HSI3/HSO 5
VREF
ANGND
EA

X2 12
P30/ADO reo----ADO
AD1
P31/AD1 59
58
AD2/
P321AD2
57
AD3
P33/AD3
AD4
P34/AD4 56
AD5
P3.5/AD5 55
AD6
P36/AD6 54
53
AD7
P37/AD7
P40/AD8
P41/AD9
P421AD10
P43/AD11
P44/AD12
P45/AD13
P46/AD14
P47/AD15

52
51

50
49
48
47
46
45

61
RD
40
WR
41
BHE
62
ALE
63
INST
CLKOUT ~
P10
P1.1
P12
P13
P14
P15
P16
P17
HSOO
HSO.1
HS02
HS03

*4
*

~

AD8/
AD9
AD10
AD11
AD12
AD13
AD14
AD15
RDI
WR/
BHE!
ALE
INST

U1
ADO
AD1

23
24
25
26
27
28
29
30
31
32
33
35
36
37
38
39

AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15

22
2
1

r-----%

?
-

PAD
PA1
PA2
PA3
PA4
PA5
PA6
PA7

ADO
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15

21
20
19
18
17
16
15
14

I/O OUTO
I/O OUT1
1/00UT2
1/00UT3
100UT4
1/0 OUT5
lin nlIT6
1/0 OUT7

11 READYI
PBO
10 BWIDTHI
PB1
PB2
8
PB3
f-l1/0 CSOI
PB4
6 1/0 CS11
PB5
5 1/0 CS2I
PB6
4 1/0 CS31
PB7

I-¥-

RD
WR
BHE!PSEN
ALE
RESET
A191CSI

~

PCO
PC1
PC2 f42INST

PSD302

~
~
~

~

...gg..

~
~
..£.

1/0 DEVICES

1/0
1/0
1/0
1/0

CSOI
CS1/
CS2I
CS31

80C196

--------------------------------------,~~~~--------------------------------------tIII"I!J!!I!!!'
1·152

I'SII3XX - ApplicatlDn IIDte 02D

PSD3XX
Solution
for 16·Bit
Microcontrol/er
(Cont.)

WSI supplies PSD users with easy to use
software tools and programming devices.
MAPLE software, which is PC based,
enables designers to configure the
PSD3XX. Some of the computer screen
configuration displays for this design

Figure4A.

ADDRESS MAP

PSD3XX

Address
Map

example are shown in Figure 4. Figure 4A
is the address map decode for the
EPROM, SRAM and Port A. Figure 4B is
the truth table input for the READY signal.

A

ESO
ESl
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

A

A

A

A

A

A

A

A

19 18 17 16 15 14 13 12

11

N
N
N
N
N
N
N
N
N
N

N
N
N
N
N
N
N
N
0
0

0
X
1
1
1
1
1
1
0
0

ALIAS: A 18

X
X
X
X
X
X
X
X
X
X

=

X
X
X
X
X
X
X
X
X
X

0
0
0
0
1
1
1
1
0
0

0
0
1
1
0
0
1
1
1
1

0
1
0
1
0
1
0
1
0
0

N
N
N
N
N
N
N
N
0
1

SEGMT
START

SEGMT
STOP

FILE
START

FILE
STOP

FILENAME

0
2000
4000
6000
8000
AOOO
COOO
EOOO
N/A
N/A

lFFF
3FFF
5FFF
7FFF
9FFF
BFFF
DFFF
FFFF
N/A
N/A

TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
N/A
N/A

INST

Fill in A 19 - A 12 (Binary) or SEGMT START (Hex); and FILE (START, STOP)
FILE NAME, P3 .. PO, and ALE/AS. Use SPACEBAR to erase any field value.
F1 - Return to Main Menu F2 - Temporary Exit to DOS F3 - Go to Help
Cursor - UP:
Down: ~ Left Col: _ Right Col: Right - F4 Left - F5

-

t

PART NAME: PSD302

Figure4B.
READY
Signal
Truth Table

C;\WSI\OLDMAP

PORTB
PIN

CSNO

CMOs/OD

PBO

CSO

CMOS

PB1

CS1

CMOS

PB2

CS2

CMOS

PB3

CS3

CMOS

PB4

CS4

CMOS

PB5

CS5

PB6
PB7

CHIP SELECT DEFINITION READY

A18 A17 A16 A15 A14 A13 A12 A11

RD WR ALE P3

0

X-

x

0

1

1

0

X

X

X

0

0

X

X

0

1

1

1

X

X

X

0

X

CMOS

0

X

X

1

0

0

0

x

x x

0

x

CS6

CMOS

0

x

X

1

0

0

1

X

X

0

X

CS7

CMOS
ALIAS: A 18

=

X

INST

X

-

CS definition is the NOR of the product terms (rows). Enter 1 to select High signal, 0 to
select Active Low signal, X to mean "don't care", SPACEBAR to erase. Enter values in
columns relevant to your application; leave other columns untouched.
F1 - Return to PORT B Menu

PART NAME: PSD302

Cursor - Up:

t

Down: ~

Left: _

Right:_

C:\WSI\OLDMAP

--------------------------~~;------------------------1·153

PSD3XX - Application Note 020

PS03XX
SolutiDn
fDr 16-Bit
ProcessDr with
NDn-Multiplexed
Bus

Table 2.
68302B,te
Enable

A PSD3XX can be configured to operate in
the 16-bit mode with a non-multiplexed bus.
In this case, the microcontroller address
lines AO-A 15 are tied to ADO-AD15 inputs
of the PSD3XX; Port A and B of the
PSD3XX are then configured as data ports,
connecting to data bus DO-D15. In
applications where the EPROM space in a
PSD3XX is not enough, or a large amount
of I/O lines and chip selects are needed,
two PSD3XXs will provide a viable solution.
Connecting two PSD3XXs to a microcontroller needs special consideration.

Figure 5 shows a basic design of a 68302
microcontroller interfacing to two PSD312s.
The implementation is fairly straightforward; the two PSD302's are configured to
work in 8-bit non-multiplexed mode. The
first PSD302 (U2) occupies the even bank
of the memory space of the 68302; the
second PSD302 (U3) occupies the odd
bank. The 68302 has no AO in the address
bus; it depends on signals UDS/ and LDS/
(Upper and Lower Data Strobe) to control
the flow of data on the data bus as shown
in Table 2.

UOS/

LOS/

08-015

00-07

Low

Low

Enabled

Enabled

Low

High

Enabled

Disabled

High

Low

Disabled

Enabled

High

High

Disabled

Disabled

The above table is also true for most other
microcontrollers. Some use different signal
names, such as HBE/ for UDS/ and AO is
equivalent to LDS/. The decoding for bank
select is the same for both cases. The
following pOints must be considered when
configuring the PSD3XX for this type of
application:

o Address inputs to the PSD3XX have to
shift right by one. Address line A 1
connects to ADO pin of the PSD3XX and
so on. For processors which have AO,
AO is no longer used as address input.

o While inside the MAPLE software during
PSD3XX configuration, the address map
decode of the EPROM, SRAM, I/O port
must also reflect the shift of the address
inputs.

o The codes of the user's program have
to be split into two files, one for the
even bank PSD3XX and one for the
odd bank PSD3XX.

o Provide bank select signals to the
appropriate PSD3XX for proper bank
decoding. The even bank PSD3XX must
include signal LDS/ as input to the PAD,
and the odd bank PSD3XX requires the
signal UDS/. These signals can ~
connected to Port C or the A 19/CSI
pin in order to be routed as PAD inputs.

-1--1-54--------------------------------~~~~-----------------------------------

PS03XX - Application Note 020

Figure 5.

PSD3XX

Interface
to 68302

~

Vee
')

'1

~Ul
100
11

A

Al
A2
A3
A4
A5
A6
A7
AB
A9
Al0
All
A12
A13
A14
A15
A16
A17
AlB
A19
A20
A21
A22
A23

EXTAL
XTAL
CLKO

~i

RX01_L 1RXO
TX01_L nxo
RCLK1_L 1CLK
TCLK1_S0Sl
C01U1SYl
CTS1U1CR
<:»'0K
RTS1U1RQ
-'-"- BRCl
RESET! }-~H_ _1-9:c2, RESETI
HALTI
BJ HALTI
L-_+-~9'4H BERRI

*

it

I

'-*

00

48

~"'--,';0"'",---'4~7H
-

02
03
04
05
06
07
OB

BUSW
OISCPU

46
45
43
42
41
40
38

009'0
37
\_~~_""""*,36H
011
35
,~0~12~_",33H
",--,';0",13~--,3;;.:2'-1
,~0~12~_",31H
\.....;0L!.15"--_",30,

00°,
02
03
04
05
06
07

ASI
R_WI
UOS/_AO
LOSCOSI
OTACK!
RMCI
lAC
BCLRI

~~

010
011
012
013
014
0 15

BRI
BGI

OREQUA13
OACKUA14
00NEUA15
IACK7UBO
IACK6UBl
IACK1UB2
TIN1_PB3
TOUT1UB4
TIN2UB5
TOUT2UB6
WOOGUB7
PBB
PB9
PB10
PBll

2D

Al /
A2
A3 -/
A4
A5
A6
A7
AB
A9
Al0
All
A12 -I
A13
A14 -I
A15
A16 -I
A17

24
25
26
27

A21
A22
A23

1
2
3
5
6

7
6
9
10
11
12
14
15

16
17
19

U2

t\\."'~,*~--;~;>;~-I ~~~
\..J;A"l-3_-,2",.5-1
" "-1!;A4!-~2~6
\..J;A,,!-5_-,2~7-1
" "-Jt!A6~_2~B-I

Vee

o

to. \..'i'!A7~_2~9

" "-4l!AB~_3~O
to.\..""A9!,,--_~31,
" \...!!,A1~0_~32-1

to. \..,,!-Al!,'l_~

"C4Al~2=~35
1\
A13
,,-;A>.!.'4;t-",",,,,7-1
"\..4Al~5_~3R

~~ ~-fB

,-,A1J.1S"-~3'"'-19

A20

PAD 1-2~1:--_;c00r---.
PA 1 ..2"'!0~_J!:"".......:\I
PA21--:;;'9:--;;;025-'\,'1
PA3 t-;'!18;.-_",.03,---, 'II
PM ~17:--_;;,04M.'1
PA5 H';lS,-_~05h,'1
PAS ......,.15'--_~OS'"""",'11
PA7 f-!."4,--_",07~,'1

A02
A03
A04
AD5
AOS
A07
ADB
A09
A010
A011
A012
A013
A014
A015

11 ,......-;;;rr-

PBO~

~:~ ~ :;g~

.-1-11----2'+-12 E

---:t1~ ~~/PSEN

.---I~\I--I"''--_-_-_-

PB3
PB4
PB5
PBS
PB7
PCO
PCl
PC2

t4--

1/04

+r--

1/07
1108

0/05
t-;;I os
'40
41
~

r.~1

CSO

AS
'03
1-~'0i4====±ttjjttt==:"~
RESET
1 6
-tt----'4"'-3LA~1~9/:£CS~I_ _....J
J-B'O"'-5----......t-Hr--t"J
~
~

PSD312

rW

U3

~

~

"CA~':::::~234
1\
A2
24

J

Vee

to.\..A;::;3~.....,,25H
"\.4A4~......,2""6-1
to. ,-,A~5_ _2;;;7-1

lQK,
B'---1+-..1\"
BGACK! \-2S
vi"..'\Af\V,-J

",-"A~6_ _2""B-I

IRQ11
IRQ61
IRQ71
FCO
FCl
FC2

to.,-,A~7_ _2,*9-1
",-,A~8_""""*,30-l

to. ,-,A~9.,---*i31,

AVECI ~
CSOI 1ij'2~8::j:==~1
CSll 1-'29
CS21 ~
CS31 ~
FRZI ~Uvee-

RX02_PAO
RX03]AB ~
TX02 PAl
TX03 PA9 -;;,;RCLK2]A2 RCLK3j'Al0
TCLK2_PA3 TCLK3_PAll ~
CTS2_PM CTS3UPRXO
RTS2]A5 RTS3UPTXO
C02UA6 C03CSPCLK
BRG2_PA7 BRG3_PA12 f-=

it
fit
i-#"
fiir

" ,-,A;C;l!}-O_*32-1
to.,-,A?f'-!;-'_",33'-1
t\",A",'"..2_",35H
3
3S'-I
to.",A""''i-

_*

f\:A~'t4=~374
1\
A15
3B

PAO
PAl
PA2
PA3
PA4
PA5
PAS
PA7

AOO
AOl
A02
A03
A04
A05
AOS
A07
AOB
A09
A010
AOll
A012
AD13
A014

~

14

~

09
010
011
012
013
014
015

PBO~
PBl
PB2

~

CS21

rt-) CS31

~~~~
PB5 ~CSSI
PBS t-'f-< CS7I

u A",lS"---,,,39'-1 A015

PB7~

RWI
2 RIW_
t-tlli:tE~::::J22qE

.....Hh-,,-_---,""-j BHE/PSEN

t-~AS~m::::~'3~

21
20
19
18
17
lS

L
RESETi
3 AS
RESET
L---t_'--U"'D"'S"-i_---'''"-I A19/CSi

PCO --'ll1
PCl 41
PC2

f-12-

CSl
r.~(

1...-_ _ _-'

Vee

U

PSD312

68302

-----------------------------f§a-=------------------------~1~-1~~

PS03XX - Application Note 020

PSD3XX
Solution
for 16-Bit
Microcontrol/er
with Non·
Multiplexed
Bus

Figure 6 shows the address map of the odd
bank PSD3XX. In the map table, the
columns A19, A17, A16 are input signals of
UDS, CSO and CS1. Since this is the
decoding for the odd bank, UDS
(column A 19) has to be low for any of the
PSD3XX devices to be enabled.
Furthermore, the CSO selects the EPROM
and CS1 selects SRAM and I/O Port.
The chip select logic of the 68302 also
generates the programmed amount of wait
state Internally.

Figure 6.
Address Map,
Odd Bank

PSD3XX

The columns A 15, A 14, A 13 in the address
map are actually A 16, A 15 and A 14 after
the input address lines to the PSD3XX are
shifted by one. Entries to the SEGMT
START/STOP or FILE START/STOP
columns must also change to relflect the
shift of the address lines. For example,
the top address of the EPROM (128K
bytes) was 1FFFF, and is now OFFFF after
the shift.

ADDRESS MAP

ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

A
19

A
18

A
17

A
16

A
15

A
14

A
13

0
0
0
0

X

0

X
X
X

0
0
0
0

1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1

0
0
1
1

0
1
0
1

0
0
1

0
0

0
1

1
0

0
1
0
1
0

0

0

0
0
0
0
0
0

X
X
X
X
X
X

0
0
0
1
1

12

A

A
11

N
N
N
N
N
N
N
N
0
0

N
N
N
N
N
N
N
N
0
0

SEGMT
START

SEGMT
STOP

FILE
START

FILE
STOP

0
2000
4000

1FFF

6000
8000
AOOO
CODa
EOOO

N/A
N/A

3FFF
4FFF
7FFF
9FFF

FILE NAME
ODD HEX
ODD.HEX
ODD.HEX
ODD.HEX

BFFF
DFFF
FFFF

ODD HEX
ODD.HEX
ODD HEX
ODD.HEX

N/A
N/A

N/A
N/A

ALIAS: A19 = UDS

...

Fill in A19 - A12 (Binary) or SEGMT START (Hex); and FILE (START, STOP)
FILE NAME, P3 .. PO, and ALE/AS. Use SPACEBAR to erase any field value.
F1 - Return to Main Menu
F2 - Temporary Exit to DOS
F3 - Go to Help
Cursor - UP: t
Down: t
Left Col: _
Right Col: ...
Right - F4
Left - F5

Conclusion

After going through the design examples
with the PSD3XX, it is not difficult to see the
advantages the PSD3XX family offers over
designs with discrete ICs. Besides
providing 16-bit performance, PSD3XX
devices are able to replace 7 ICs in the
80C196 example. This not only reduces
the board size dramatically but also
provides benefits such as cost reduction in
board manufacturing, higher product
reliability, lower power consumption and
reduced component cost.

Other PSD3XX advantages over the
discrete component design include the
power down mode to reduce power
consumption when the microcontroller is
idle. The security feature protects the code
stored in the EPROM from illegal copy. The
flexibility, programmability, and ease of use
which come with the PSD3XX truly make it
an optimal solution for 16-bit embedded
applications.

--------------------------------~~~~-------------------------------1-156

Programmable Peripheral
Application Note 021
Interfacing The PSD3XX To The MC68HC16
and The MC68300 Family of Microcontrollers
8yChingLee

Introduction

Typical
MC68331
Design

The MC68331
8us Interface

The PSD3XX devices are user-configurable
microcontroller peripherals which offer an
ideal solution for embedded control
applications. The PSD3XX family provides
basic building blocks to microcontroller
based designs including 110 ports, logic
replacement, programmable address
decoder (PAD), Memory Page Register,
The MC68300 family includes microcontrollers such as the MC68330,
MC68331, MC68332 and MC68340. These
devices share a common MC68020 CPU
core. Although the MC68HC16 is not a
member of the family, it does have a
MC68300 type bus interface and timing.
The MC68331 will be chosen as the
microcontroller used with the PSD3XX

Before interfacing the PSD3XX to the
MC68331, we have to understand the
MC68331 bus and the bus features. Area's
of interest to the PSD3XX interface are
discussed in the following sections.

2K bytes of SRAM and up to 128K bytes of
EPROM. Please consult Application Note
011 for detail features and operations.
In this Application Note we will demonstrate
how the PSD3XX interfaces to the 16-bit
MC68HC16 and the MC68300 family of
32-bit microcontroliers from Motorola.
device in this Application Note, but the
description applies to other members of the
group as well.
A typical MC68331 design consists of two
EPROMs, two SRAMs, an 1/0 block and
glue logic. The complexity of the 1/0 block
and glue logic depends on the application.
Figure 1 shows the block diagram of such a
design.
The MC68331 transfers the even data byte
(with AO =0) through D15 - D8, and the
odd byte (with AO = 1) through D7 - DO.
Table 1 shows the different data transfer
cases for a 16-bit bus, and the status of the
control signals involved in the bus cycles.

Address Bus
The MC68331 bus has 24 non-mUltiplexed
address lines (AO - A23). Address lines
A 19 - A23 can be selected either as
address lines or as chip select signals
(CS6 - CS10) at reset time.

Data Bus

For byte transfer, the positioning of the byte
is determined by address AO. OPO refers to
the most significant byte of a word operand,
and OP1 is the least significant byte.
Operands in parentheses are ignored
during read cycles, but are driven by the
processor during write cycles. Misaligned
words are not supported by the MC68331.

The data bus (D15 - DO) is a non-multiplexed bus which transfers 8 or 16 bits of
data. The processor supports byte, word,
and long word operands.

Table 1.
MC68331 Data
Transfer On
16·8it (Word)
Port

Transfer

Sill

SilO

AD

oSACKI

Upper Byte (even)

0

1

0

0

X

OPO

Lower Byte (odd)

0

1

1

0

X

(OPO)

OPO

Word (aligned)

1

0

0

0

X

OPO

OP1

Long Word
(aligned)

0

0

0

0

X

OPO

OP1

oSACK2 015-08

07-00
(OPO)

1-157

~

;:

Figure 1. MC68331 System Block Diagram

a~
I

~

~

~

r
~

;-

~

AO-A1B

CSBOOT

EPROM

SRAM

EPROM

SRAM

r--

'i~:

,q~'Q

r--

lUi,

-.lllh
l1li1""

MC6B330
MC6B331
MC68332
MC6B340
MC6BHC16

015- DO

07-00

015- DB

07-00

015- DB

CSO-RAMCS

RIW
OS
SIZO
AO
Al
A2
CSl

WRL
WRH
LATCH 110
PAL@

CTRL OUT 0
CTRL OUT-l
CTRL-OUT 2
CTRL-OUT-3
CTRL-OUT 4

110 PORTS
015

DO

~,

l'Soaxx - Application 110" 021

The MC68331
Bus Interface
(Cont.)

Chip Select Logic
The MC68331 provides 12 chi~lect_ _
Q!!!put signals (CSBOOT and CSO - CS10).
CSO - CS 10 are multiplexed with other
signals and default to chip select mode
during reset.
The chip select signals are userprogrammable, flexible and powerful. The
following list outlines some of the
options/features which can be programmed
into any chip select signal:
1. Base Address: Specify base address
and block size.
2. Mode Option: Select asynchronous!
synchronous bus mode.
3. Byte Option: Specify upper byte, lower
byte, or both.

5. Strobe Option: Speci~CS signal to be
synchronized with the DS or AS signal.
6. DSACK Option: Specify internal/
external source of the DSACK signal.
If internal DSACK is specified, then
select the number of wait states.
After system reset, CSO - CS10 lines are
disabled since they should not select any
device until the system is configured. But
CSBOOT has a default reset value such
that it can be used to enable a boot PROM,
or PSD3XX in this case. The other chip
selects are then initialized by the boot
program. CSBOOT mayor may not be
re-programmed to a different value. The
reset value of the CSBOOT signal is listed
in Table 2.

4. ReadlWrlte Option: Specify read or
write bus cycle.

Table 2.
CSBOOT
Reset
Value

A Typical
MC68331
Design
WithPSD3XX

Flelds/DptloR

Reset Values

Base Address

0000 0000

Block Size

1M Byte

Asynchronous/Synchronous Mode

Asynchronous Mode

Upper/Lower Byte

Both Bytes

ReadlWrite

ReadlWrite

Strobe

AS

DSACK

13 Wait States

Address Space

Supervisor/User

Interrupt Priority Level

Any Level

Autovector

Interrupt Vector Externally

As seen in the typical MC68331 design
block diagram in Figure 1, the basic
building blocks include EPROMs, SRAMs,
a PAL®, and 1/0 port. The PSD3XX will
replace all or most of these blocks.
Depending on the amount of EPROM and

__________________________ f • •

______________________

~.?

'ifill j

SRAM space and the I/O port requirement,
one or two PSD3XX devices can be used.
The two PSD3XX system does have a
different interface to the MC68331 than a
single PSD3XX design. The two designs
will be discussed separately.

~~

1-159

PS03XX - Application Note 021

The Two

"SDaXX
Design

Figure 2 shows a two PSD3XX
implementation of a typical MC68331
system. In this design the PSD312s replace
the EPROMs, the SRAMs, the PAL®, and
the 1/0 port in the typical design. The two
PSD312 devices provide 128K bytes of
EPROM and 4K bytes of SRAM. Two
PSD313's can be used if more EPROM
space is needed.
The configurations of the two PSD312's in
this design are as follow:

Bus Width
Each PSD312 is configured to operate in
8-bit non-multiplexed mode. PSD#1
supplies the even data byte to the
processor while PSD#2 supplies the odd
data byte. Together they appear to the
MC68331 as a single 16-bit port.

PortA
Port A in a PSD3XX can be an 1/0 port,
address output latch or as a data port with a
non-multiplexed bus. In this design
example, Port A is configured as a data
port. Port A of PSD# 1 is connected to
015 - 08 and PSD#2 is connected to
07 - DO of the processor.

PortB
Port B can be an 1/0 port, chip select
outputs, or as a data port in a 16-bit
non-multiplexed bus. In this design, half of
Port B is used to replace the 1/0 port in the
typical design, and the other half is used as
logic replacement for the PAL®. The two B
ports together provide two 4-bit 1/0 ports,
and 8 output control signals.

______________________________
1-160

porte
Port C can be used as an addressllogic
input port to the PAD, or as chip select
outputs. In our case, Port C is used as logic
input.

Bus Interface
The PSD312's are configured to interface
to a bus with a read/write signal (R/W) and
a data strobe signal (OS). Since the
MC68331 has a non-multiplexed bus, the
address strobe (AS) input signal is not
required by the PSD312 to latch the
address lines internally. Instead, the AS
and the CSI/A19 pins are used as address
input pins to select the internal PSD312
sections. The 3 signals which select the
PSD312's are CSBOOT, CSO and CS 1.
The CSBOOT selects the EPROMs. The
CSO selects the even byte SRAM and 1/0
Port B; CS1 selects the odd byte only. No
wait states are required if the MC68331 is
running at a 16 MHz system clock. Please
refer to Figure 2 for the bus interface
connections.
After reset, CSBOOT selects the
PSD312's to run the boot program. During
this time, the 3 chip select lines can be
re-programmed to reflect the correct
address range and wait state. This has to
be done before the SRAMs can accessed.
Table 3 shows some typical option values
for this application. There is no 4 KB block
size option, so 8 KB is assigned to the
SRAM.

',~~E------------------------------

'r!N!.1

Figure 2. Me68331/TwD PSD312 Interfacing

DO
01
D2

111
110
109

n~

U~1115
104
103
102
100
99
98
97

4
05
D6
07
08
09
010
011
012
013
014
015

,-..I-~,..
I

94
93
92
91

68

RESET

DO
01
D2
03
04
05
D6
07
DB
D9
010
011
012
013
014
015

RESET

AS

VCC

1
T

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
A11
A12
A13
A14
A15
A16
MC68331
A17
A18
A19_CS6
A20_CS7
A2LCS8
A22_CS9
A23_CS10

90
20
21
22
23
24
25
26
27
30
31
32
33
35
36
37
38
41
42

AO
Al
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18

r-W.--

~
r-mr--m---

rill82

RiW r-rs--RiW
89
88

OS
OSACKO
OSACKl

SIZO
SIZl
CSBOOT
BR_CSO
BG CSl
BGACK=CS2
FCO CS3
FC1=CS4
FC2_CSS

85

OS

~

r-M-112
113
114

~
rm~

~

CSBOOT
CSO
CSl

VCC
(

Al
A2
A3
A4
AS
A6
A7
A8

23
24
25
26
27
28
29
30

A9
Al0
All
A12
A13
A14
A15
A16

31
32
33
35
36
37
38
39

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7

A08
AD9
A010 PSD312
A011 EVEN
A012 BYTE
A013
A014
A015

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

13
CSO
3
RESET
CSBOOT 43

OS
RNi
BHEIPSEN
AS
RESET
A19/CSI

PCO
PCl
PC2

Al
A2
A3
A4
A5
A6
A7
A8

23
24
25
26
27
28
29
30

ADO
AOl
A02
A03
A04
A05
AD6
A07

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

21
20
19
18
17
16
15
14

A9
Al0
All
A12
A13
A14
A15
A16

31
32

A08
A09
A010 PSD312
AD11
ODD
A012 BYTE
A013
A014
A015

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

11
10
9
8
7
6
5
4

OS

PCO
PCl
PC2

40
41
42

os
RIW

os

22
2

33
35

36
37
38
39

22
2
1
13
CSl
3
RESET
CSBOOT 43

RIW

...
~
...

PSD#1
ADO
AOl
A02
A03
A04
A05
AD6
A07

21
20
19
18
17
16
15
14
11
10
9
8
7
6
5
4

BHEIPSEN
AS
RESET
Al91CSI

CTRL OUT-O
CTRL-OUT-l
CTRL-OUT 2
CTRL-OUT-3
110 PORTA
110 PORTA
110 PORTA
110 PORTA

40
41
42

PSD#2

RiW

08
D9
010
011
012
013
014
015

CTRL-IN-O
CTRL-IN-l
CTRL-IN-2

DO
01
02
03
04
05
D6
07
CTR!. OUT-4
CTRL-OUT-5
CTRL-OUT 6
CTRL-OUT-7
1I0PORTB
110 PORT B
110 PORT B
110 PORT B
CTRL-IN-3
CTRL-IN-4
CTRL-IN-5

it~
I

:to.

~
;::
~
r:::t

=
t

II'

!§

PSD3XX - Application Note 021

Table 3.
Chip Select
Option Value

The Two
PSD3XX Design
(Cont.)

Figure 3.
Address Map
Truth Table

Option

CSBooT

CSO

CS1

Base Address

000000

040000

040000

Block Size

256KB

8KB

8KB

Asynchronous/Synchronous Mode

Asynchronous

Asynchronous

Asynchronous

Upper/Lower Byte

Both Bytes

Upper Byte

Lower Byte

Read/Write

Read

Read/Write

Read/Write

Strobe

AS

AS

AS

DSACK

o Wait State

o Wait State

o Wait State

Bus Interface (Cont.)
Figure 3 shows the Address Map from the
PSD#1 configuration file generated by the
WSI Maple configuration software. In the
Address Map truth table, the A 19 column is
the CSBOOT ~t, and the Q.F. AS
column is the CSO input. EPROM is
selected when CSBOOT is low; SRAM or

I/O Port B is selected when CSO is low. The
addresses in FILE STRT/FILE STOP
columns are shifted right by one to reflect
the fact that the A 15 - A 13 input pins on
the PSD312's are connected actually to the
A16 - A14 of the MC68331.

ADDRESS MAP
A
19
ESO 0
ES1 0
ES2 0
ES3 0
ES4 0
ES5 0
ES6 0
ES7 0
RSO 1
CSP 1

A A A A A
18 17 16 15 14
X X X 0 0
X X X 0 0
X X X 0 1
X X X 0 1
X X X 1 0
X X X 1 0
X X X 1 1
X X X 1 1
X X X 0 0
X X X 0 0

A
13
0
1
0
1
0
1
0
1
0
0

A A
12 11

SEGMT
STRT

SEGMT
STOP

FILE
STRT

FILE
STOP

Q. F. AS

11ft
3fft
5fff
7fff
9fff
blff
dlff
flff
N/A
N/A

1
1
1
1
1
1
1
1
0
0

N
N
N
N
N
N
N
N

N
N
N
N
N
N
N

0
2000
4000
6000
8000
aOOO
cOOO
eOOO

0
0

0
1

N/A
N/A

N

END

~~~~~~~~~~~~~~~~--'AfAr~~--~~~~~~~~~~~~~~~--

1-162

~iiE=

PS03XX - ApplicatiDn NDte 021

The TWD
!'SD3XX Design
(CDn'.)

Power Down Mode
The PSD3XX's power down mode is
particularly useful in a system which uses a
PSD3XX mostly as a boot PROM. The
power down mode is controlled by the input
pin A 19/CSI. This pin can be configured by
MAPLE as address input (A 19) or as chip
select input (CSI). To implement the power
down mode to the two-PSD312 design, the
following changes are required:

o Configure the A19/CSI pin by MAPLE as
the CSI pin. Connect the pin to the
CSBOOT signal. The PSD3XX's are
normally in power down mode except
when CSBOOT is asserted.

o The PSD3XX has a 10 ns hold time
requirement on the CSI input with
reference to the trailing edge of the OS
signal. The MC68331 does not provide
this hold time; designers have to delay
the CSBOOT signal to meet this
requirement.

The Single
!'SD3XX Design

The single PSD3XX design is for
applications which need less EPROM and
SRAM space. Figure 4 illustrates the
schematic of a PSD302 interfacing to the
MC68331. The PSD302 provides 64 KB of
EPROM and 2 KB of SRAM; Port A and
Port B are configured as data ports for the
MC68331. Port C generates the 1/0 latch
signal for the 1/0 port and two chip select
signals.
The single PSD3XX interface to the
MC68331 is different from the two PSD3XX
design. In order for the PSD302 to operate
in the 16-bit mode, it needs a Byte High
Enable (BHE) signal. If the design has a
BHE signal available (generated from
decoding to AO and SIZO signals from the
MC68331), connect it directly to the
PSD302's BHE pin. CSBOOT or other high
address bits are then used to select the
PSD302.
If there is no BHE signal available, the
CSBOOT signal can be programmed to
provide this function. After reset, the
CSBOOT signal operates as a chip select
signal with initial values shown in Table 2. It
will serve temporarily as the BHE input to

o The CSBOOT signal is programmed to
have a block size of 512 KB. This will
cover both the EPROM and SRAM
space. When accessing the SRAM, the
CSBOOT signal is asserted to take the
PSD3XX out of power down mode. In
power down mode, the Port B 1/0 ports
will maintain their output values but the
chip select output signals will be
inactive.

o When the CSBOOT is used as CSI
input to the PSD3XX, the access time
from CSI valid to data out is 130 ns
(PSD302-12), 10 ns more than the
normal address valid to data out time.
This requires CSBOOT and CSO - CS1
to be programmed with one wait state.

the PSD302 until the CSBOOT is
programmed as a BHE signal. The
programming should be done shortly after
reset with the value listed in Table 4.
Now that the CSBOOT signal is used as
the BHE signal, the PSD302 needs other
means to select the internal device.
Other chip select signals from the
MC68331 cannot be used since they are
inactive at the time of boot up. Address
lines A 18 - A 19 are used instead as
decoding address inputs to the PSD302 as
shown in Figure 4. For example, the
EPROM is enabled if A 18 - A 19 are equal
to OOH; SRAM and 1/0 Ports are enabled if
A18 - A19 are equal to 01H. Depending on
the application, any other high address bits
can be used for this purpose.
The PSD302 is configured to operate in the
16-bit mode. The high byte is coming from
Port B and is connected to 07 - DO on the
MC68331 data bus. Table 5 shows which
port and byte it is driving for different bus
cycles. Please note the low bytelhigh byte
definition in the PSD302 Data Book is the
opposite to that defined in the MC68331
User's Manual.

--------------------------~Jr;-------------------------1-163

"";4

~

Figure 4. MC68300/PSD3021nterface

~

2
~

•
:to

I\. AO

"
"

III'111111' ' '

00
01
02
03
04
05
06
07
08
09
010
011
012
013
014

""

11111111

111 00
110 01
109 02
108
105 03
104 04
103
102.
100 07
99
98 010
97 011
94
93 012
92 013

AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13

~_68=-

013
014
015

11
10
9
8
7
6
5
4

00
01
02
03
04
05
06
07

."

An

,,"""''''

",,"

015

A15
A16
A17

37
38
41

A15
A16
A17

RESET
A18

3
43

42

A18

I ___

RIESET

A18
A19_CS6
A20_CS7
A2LCS8

O~

-

A~
RIW
OS

~

;-

~

41

P CSO

AS
RESET
A19/CSI
'--_ _ _ _ _ _.1

~

f-lli-

",c, ''''

82

r-;- - =
rR:79.-~R/,!!-W------4-.J
85

OS

81

~
112

~

~
~
~

~

CSBOOT (SHE)

VO PORT

l

,es, 1

~

SIZ1~

BR_CSO
BG_CSl
BGACK_CS2
FCO_CS3
FC1_CS4
FC2 CS5

a:~'=

t-4;i;0i-----.r-;;;~:I

A22CS9~
'"-'''''
fl"----

CSBOOT

>----J

16
15
14

.,,"

SIZO

RESET

PAS
PA6
PA7

'"'

...-_1--......2.
89L j _ _ _ _
1~---+_~8~8---,
OSACKO
_
OSACKl

l

A05
A06
A07

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7
PCO
PCl

MC68331

Q
j

29
30

08
09
010
011
012

A8
31 A08
A9
32
Al0
33 A09
All
35 A010 PSD302
A12
36 AOll
A13
37 A012
A14
38 A013
A15
39 A014
A015
OS
2
RIW
2 2CSBOOT 1 RIW - -

11111111

VCC

A6
A7

~
21
20
19
18
17

AO
Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13

g:

Ilblllh

23 , - - - - - 24 AOO
PAO
25 AOl
PAl
26 A02
PA2
27 A03
PA3
28 A04
PA4

90
20
21
22
23
24
25
26
27
30
31
32
33
35

g~

"

Al
A2
A3
A4
AS

~
,

PSD3XX - Application Note 021

Table 4.
CSBOOTas
BHESignal

Table 5.
PS0302
OataPorts

Conclusion

Fields/Option

CSBOOT Values as BHE

Base Address

000000

Block Size

128 K Byte

Asynchronous/Synchronous Mode

Asynchronous Mode

Upper/Lower Byte

Lower Byte (Odd Byte)

ReadlWrite

ReadlWrite

Strobe

AS

OSACK

o Wait State

-

AD

BHE (CSBOOT)

PortA
(Even Byte)

PortB
(DddByte)

0

0

015 - 08

07-00

0

1

015'- 08

Tri-State

1

0

Tri-State

07-00

1

1

Tri-State

Tri-State

As we have seen from the two PS03XX
design examples, the PS03XX's are able to
replace at least 6 ICs in the typical 16-bit
MC68331 design. The PS03XX
programmable microcontrolier peripheral
not only provides a cost effective solution to
embedded applications, but it also reduces
printed circuit board space, power
consumption and offers code protection
from unauthorized access.

PAL® is a registered trademark of Advanced Micro Devices Corporation.

------------------------------r==-~-----------------------------55'..::;:"'=
1-165

PSD3XX - Application Note 021

~~------------------------------~~g---------------------------------1-166
__ - I

r •• "E

Programmable Peripheral

;;:.:1.

Application Note 022
Using Wll's PSD3XX Programmable
Microcontroller Peripheral Family
with BOC31/BOC51 Microcontrollers
By Dan KIIISBIIa

Introduction

The 80C51 microcontroller family is
composed of several versions from
different manufacturers that are variations
of the basic 80C51 architecture. Different
functions on-chip, a variety of speeds,
packages, etc. are all available while the
80C51 instruction set is maintained on all
variations. Because of the wide variety of
features found with the 80C51 devices,
as well as the usefulness of the general
architecture itself, the 80C51 product group
has become one of the most widely used
microcontroller families in the world. The
purpose of this application note is to
provide some background and
implementation ideas to designers using
the 80C51 microcontroller family along with
the WSI PSD3XX family. A simple 80C31
system will be examined, as well as more
complex systems where memory map
issues become important.
The 80C51 family can be divided into two
basic memory usage types: intemal
memory usage only (80C51, 8751, etc.)

and external memory accesses needed
(80C31, 80C51 with external accesses,
etc.). The PSD3XX family helps solve the
problem of system size and cost by
integrating the typical devices used with
external accesses (logic, SRAM, EPROM,
etc.) onto a single chip. Figure 1 illustrates
a typical80C31 system and how it is
dramatically simplified and improved by
using a PSD3XX device.
The PSD3XX device simplifies the system
by enabling the designer to integrate I/O
ports, the microcontroller to peripherals or
memories interface logic, EPROM code
storage, and scratch pad SRAM data
storage into a single chip. Design changes
that are sometimes required due to
changing market conditions are often
easily and quickly implemented in the
reprogram mabie PSD3XX without adding
extra chips to the system or making board
layout changes.

Figure 1.

80C31

IIC

BDcat System Befote PSD3XX

IDC3t System After PSD3XX
1·167

PSD3XX - AppilcatlDn NDte 022

TheBOC31
Family

A number of 80C31 versions are offered
from several suppliers that include different
functions on-chip, but versions such as the
80C32 have different internal memory sizes
as well. Each of these versions has
retained the core architecture and external
memory access requirements of the basic
80C31.
The 80C51 family memory model is
composed of two separate memory spaces
or allocations. Program space is intended
for storage of the program control code
(usually in EPROM) and data space is
intended for storage of temporary or
changeable information (usually in SRAM).
Data space is also where most memory
mapped I/O is located. In external memory
operation, the 80C31 uses the PSEN signal
to access program memory and the RD
Signal accesses the data memory. The
PSD3XX's programmability provides for
this memory model (called "separate
space") as well as other memory models.

Program and data space do not always
need to be separated. In fact, most
controller architectures make no distinction
between program and data space. If this
memory model is desired, the PSD3XX will
internally OR the PSEN and RD signals
together and EPROM, SRAM and 1/0 will
be available in the same memory space
(called "combined space"). In "combined
space", program code can be stored in
EPROM or SRAM. This can be very
important if the user has program code that
is downloaded into SRAM, or if the system
uses lookup table contents that depend on
system parameters not known until the
system is operating. Anytime the program
code needs to be easily changeable,
SRAM is a convenient way to store it.
Figure 2 illustrates how the PSD3XX would
be connected to the 80C31 and tables 1
and 2 convey some of the choices made
via the PSD Development System Software
to configure the PSD3XX as "separate" or
"combined" address space.

--------------------------------------~~Jr------------------------------------1·168

PSD3XX - Application Note 022

The80C31
Family
(Cont.)

Table 1 shows an EPROM segment
starting at address 0 and covering the
entire 64K program space. The SRAM
block and memory mapped 1/0 are shown
in the same memory space. This is

acc~able since they will be controlled by
the RD signal so there will be no conflict
with the EPROM which is controlled by the
PSEN signal.

Table 1.
''Separate''
ModePSD3XX
Choices
********************** MAPLE 5.00 **********************

PSD PART USED: PSD312
********************PROJECT INFORMATION*****************
Project Name
8031 app. note - Separate address space
Your Name :
Dan Kinsella
Date :
May, 1992
Host Processor
8031
*********************GLOBAL CONFIGURATION***************
Address/Data Mode
MX
Data Bus Size :
8
Reset Polarity
HI
Security :
OFF
ALE Polarity :
HI
Using Different READ strobes for Data and Program: Y
separate Data and Program Address spaces : Y
------> Separate

Mode

********************READ WRITE CONTROL*****************
/RD and /WR
******************************ADDRESS MAP***********************************

A A A A A A A A A SEGMT SEGMT FILE
19 18 17 16 lS 14 13 12 11 STRT STOP STRT
ESO
ES1
ES2
ES3
ES4
ESS
ES6
ES7
RSO
CSP

N
N
N
N
N
N
N
N
N
N

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
1
0
1

0
0
1
1
0
0
1
1
1
1

0
1
0
1
0
1
0
1
1
0

N
N
N
N
N
N
N
N
0
0

N
N
N
N
N

N
N

N
0
0

0
2000
4000
6000
8000
AOOO
COOO
EOOO
6000
COOO

1FFF
3FFF
SFFF
7FFF
9FFF
BFFF
DFFF
FFFF
67FF
C7FF

0000
2000
4000
6000
8000
ACOO
COOO
EOOO
N/A
N/A

FILE File
STOP Name
1FFF
3FFF
SFFF
7FFF
9FFF
BFFF
DFFF
FFFF
N/A
N/A

TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
N/A
N/A

Page Reg Q.F
ALE
3210
N
N
N
N
N
N
N
N
N
N

****************************************END***********************************

*****************************ADDRESSES OF I/O PORTS*************************
Pin Register of Port A :
C002 Page (Binary):
Direction Register of Port A :
C004
Data Register of Port A :
C006
Pin Register of Port B :
C003
Direction Register of Port B
COOS
Data Register of Port B :
C007
Page Register :
C018
*****************************************************************************

-----------------------------------------~~~-----------------------------------------_.
~m

PSD3XX - Application Note 022
Table 2 shows the 1/0, EPROM and SRAM
blocks located throughout the memory map
but not overlapping as in the case of the
"separate" mode.

The BOC31
Fami/y
(Cont.)

If SRAM or 1/0 is overlapped on the
EPROM block in the memory map in the
"combined mode", the SRAM or 1/0 will be
accessed in that address range. The
EPROM portion that is overlapped
becomes inaccessible. In the "separate"
mode, EPROM and SRAM can be

Tab/e2.
"Combined"
ModePS03XX
Choices

overlapped and both are accessible
because the PSEN and RD separately
enable these blocks to the output. In the
"combined" mode, these enables are gated
together and SRAM and 1/0 have priority
over the EPROM (for example, if the
SRAM is mapped at the same start
address as EPROM block 7 (ES7), the first
2K of ES7 will be SRAM access and the
rest of the 8K block will be EPROM
access).

********************** MAPLE 5.00 **********************

PSD PART USED: PSD312
********************PROJECT INFORMATION*****************
Project Name
8031 APP NOTE - Combined address space
DAN KINSELLA
Your Name :
Date:
MAY, 1992
Host Processor
8031
*********************GLOBAL CONFIGURATION***************
Address/Data Mode
MX
Data Bus Size :
8
Reset Polarity
HI
Security :
OFF
ALE Polarity :
HI
Using Different READ strobes for Data and Program: Y
Separate Data and Program Address spaces : N -------> combined Mode
********************READ WRITE CONTROL*****************
/RD and /WR
******************************ADDRESS MAP***********************************

ESO
ES1
ES2
ES3
ES4
ESS
ES6
ES7
RSO
CSP

A A A A A A A A A
19 18 17 16 15 14 13 12 11

SEGMT SEGMT FILE
STRT STOP
STRT

FILE
STOP

File
Name

N
N
N
N
N
N
N
N
N
N

0
6000
BOOO
AOOO
EOOO

0000
2000
4000
6000
BOOO

1FFF
3FFF
SFFF
7FFF
9FFF

TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX
TEST.HEX

N/A
N/A

N/A
N/A

N/A
N/A

0
0
0
0
0

0
0
0
0
0

0
0
0
0
0

0
0
1
1
1

0
1
0
0
1

0
1
0
1
1

0
0

0
0

0
0

0
1

0
1

1
0

N
N
N
N
N
N
N
N
1
0

N
N
N
N
N
N
N
N
0
0

1FFF
7FFF
9FFF
BFFF
FFFF

3000 37FF
COOO C7FF

Page Reg Q.F
3210
ALE
N
N
N
N
N
N
N
N
N
N

****************************************END*******************************

******************************ADDRESSES OF I/O PORTS*************************
Pin Register of Port A :
C002 Page (Binary):
Direction Register of Port A:
C004
Data Register of Port A :
C006
Pin Register of Port B :
C003
Direction Register of Port B
COOS
Data Register of Port B :
C007
Page Register :
C01B
*************************************************************************
~==:= ~5f

-1--1~~~0-------------------------------------~~=

----------------------------------------

psoaxx - Application Note 022

PS03XX
Architecture

Figure 3 illustrates a more detailed block
diagram of the PSD3XX family. Since the
PSD30X can be configured to operate
either x8 or x16, it has the flexibility to

operate with 8 or 16-bit microcontroliers.
The PSD31 X devices are used in 8-bit-only
applications and are available at lower
cost.

Figure 3.

PS03XX

Architecture

PAGE LOGIC
P3-PO
-

L
A
T
C
H

AOS-AOI5

~

A8-Al0
A19
CSI

- --

PCD-

r27 PT

PROG.
PORT
EXP

PORT
C

~

CS8CS10

- - ---

'---

ES7
ES6
ES5
ES4
ES3
ES2
ESI

L
A
T
C
H

AD D-A07

LOGIC IN

PAOB

ALE/AS
RO
WR
RESET

13PT

I ALEIAS

~!

CSIOPORT
A19
CSI

PAOA

ALE/AS
RO
WR
RESET

r-

AI6-AIS

~r

All-A15

'--

EPROM
256K BIT -1 M BIT

~

-r

ESo"I.

r--

CSDCS7

~

-~- .... -1.. ~

'1'6i8

~.

-

32K-12SK BIT
BLOCK

08-015

~.-

L-.....

PROG
PORT
EXP
PBDPORT
B

~

'--

r--

-~

... - -

<1

--

CSIOPORT

0D-07

~

SRAM
16K BIT
TRACK MODE
SELECTS

AD-A7
AOD-A07/0D-07

PROG
PORT
EXP.
PADPORT
A

~

ALE/AS
-

RO/E

PROG CHIP
CONFIGURATION

t

WR/RIW
BHEIPSEN
RESET

XS.XI6
MUX or NON-MUX BUSSES

PROG.
CONTROL
SIGNALS

AI9/CSI

=---

-----------------------------------------,~~~~--------------------------------------~~
1-171

PSD3XX - Application Note 022

PSD3XX
Architecture
(Cont.)

Various EPROM sizes are offered in the
PSD3XX series. The PSD3X1 contains
256K bits of EPROM, the PSD3X2 contains
512K bits and the PSD3X3 provides
1 megabits. The PSD3X2 and PSD3X3
devices contain a 4-bit page register to
enable additional memory map flexibility.
This page register enables memory
expansion by a factor of 16. For example,
8-bit microcontrollers like the 80C31 that
address only 64K of memory space can
now access over 1 meg bytes with either
the PSD3X2 or PSD3X3.

memory map. Some possible examples are
shown in Tables 1 and 2. The Table 1
memory map shows the EPROM blocks
concatenated together and starting at
address 0 as they might look in a simple
80C31 system. Table 2 illustrates the
EPROM blocks separated and spread
throughout the memory map with the
SRAM segment and the memory mapped
I/O between EPROM blocks.
Internally the PSD3XX resolves the issue
of Combined vs. Separate address spaces
by ORing the PSEN and RD signals when
Combined space is specified. The EPROM
and SRAM segments will both be enabled
if either of these signals is present. The
address decoder (PAD) will determine
which of these is actually active. In the
Separate mode, the PSEN will enable only
the EPROM output and the RD will enable
only the SRAM and I/O ports. Figures 4
and 5 illustrate how this is done.

Figure 3 illustrates the block configuration
of the EPROM. It can be selected as separate blocks that can be scattered throughout the memory space or concatenated into
a single block. This feature provides the
designer with a great deal of flexibility and
efficiency by placing EPROM segments
throughout the memory where they are
most needed. The SRAM block can also be
programmed to appear in any part of the

Figure 4.
Separate Code
and Data
Address Spaces

,

I/O PORTS

INTERNAL
RD

ADDRESS

OE

•

CS
J

•

PAD

~

•

OE
CS

SRAM

CS

PSEN

EPROM

OE

--------------------------------------fjf=~~-------------------------------------

1-172

PSD3XX - Application Note 022

Figure 5.
Combined
Address Space

ADDRESS

----... cs

......

PAD

SRAM

J

OE

INTERNAL
RD

-PSEN

I,

Lr

OE

~

,

~

EPROM
CS

CS OE
PORTS

1/0

Simple
BOC31
Design

Figure 6 shows the block diagram of a
typical 80C31 design. The '373 latch is
required to demultiplex the address and
data busses. EPROM is used for program
control memory and the SRAM is required

for stack extension or scratch pad memory.
The Separate memory model is being
used in the design. In addition, two I/O
ports and a PLD based address decoder
are incorporated.

Figure 6.
A Typical
BOC31 Design

DATA
PSEN

EPROM

80C31
IIC

RD
SRAM

------------------------------------~~~~--------------------------------1--1-73-

PSD3XX - Application Note 022

Simple
8DC31
Design

The '373 latch, 1/0 ports, PLD address
decoder, EPROM and SRAM can be easily
replaced by a single PSD31 X device,
connected as shown in Figure 2. (the
EPROM complement for the PSD31X series
is 32K x B for the PSD311 , 64K x B for the
PSD312 and 12BK x B for the PSD313). All
are pin and function compatible.
A PSD3XX device is capable of replacing
up to 6 devices in this fairly routine design.

Adding
Capability...

For designs that require more program and
data space than the BOC31 can directly
address (12BK in Separate address space
and 64K in Combined space), the PSD312
and PSD313 include a paging register to
expand the usable memory space. For a
more complete discussion, see WSI
Application Note 015, "Using Memory
Paging with the PSD3XX". This 4-bit page
register enables the BOC31 to address up
to 16 pages of 64K memory. To change
from one page to the next requires only
that the microcontroller write the page
number of the memory page desired to the
page register.
Although the page register is a good
solution for systems requiring more address
space than provided by the BOC31, there
are times when more memory space is
desired and using the page register may
not be appropriate. Table 3 exhibits a
system address map for a Combined
memory space design that requires more
than 64K of memory space. We do not
want to use the page register in this case
because the data memory must reside in
the same page as the program memory,
such that data can be accessed by the
program without switching pages.
We can see from this memory map that the
Separate mode memory model is not
usable because some EPROM addresses
are in the SRAM data space. Also, the lola!
memory space required is 9BK which
exceeds the 64K memory space normally
available in the Combined mode memory
model.

Table 3.
Combined
Memory Space
System Address
Map

__

~

The solution using the PSD3XX makes
use of a feature included in all PSD3XX
devices. Every PSD3XX can support
up to 20 address inputs, directly enabling
up to 1 meg of address space to be
accomodated. Port C pins can be
configured either as chip select outputs
from the PAD or as address inputs that
can be used in the memory map. Port C
pins can be configured on an individual pin
basis so chip select outputs can be
provided at the same time as address
inputs. By using the RD signal as an
external input to the PAD via Port C, the
RD signal can be used as an extra address
bit to enable up to 12BKB of address space
to be accessed. See Figure 7.
When using this solution, the timing
requirements are more stringent since the
RD signal is valid later than the addresses
are valid. Therefore, the BOC31/PSD3XX
timing that must be satisfied is from RD
valid to PSD3XX data out instead of the
more usual BOC31 address valid to
PSD3XX data out. See Figure B.
This tighter timing might require a higher
speed PSD31X device. Since RD is now
part of the input address, T2 as shown
above must be used as the time required
for memory access instead of T1. For
example, in a 16 MHz BOC31 design, T1 is
257.5 ns (max.) and T2 is 222.5 ns (max.).
!n Ihis case, a higher speed PSD3XX is not
required since a PSD31X-20 would be fast
enough to meet T1 and T2 timings.

Address

Program Space

0000 -71ff

EPROM (32 KB)

SRAM (2 KB)

BOOO - Ifff

EPROM (32 KB)

EPROM Table (32 KB)

__________________________________

1-174

If more complex memory maps are required,
as in the system below, the system savings
can be even greater. In addition, the
hardware design can be easily reused in the
future since 1/0 ports, chip selects, EPROM
addresses and contents, etc., are all
programmed into the PSD3XX. As a result,
the printed circuit board layout will not need
to be changed for significant system design
changes.

Data Space

_____________________________________

fEE~E

----

PS03XX - Application Note 022

flgure 7.
ROUsed
as an Address
Bit to Enable
12SKB
Addressing

Vee

Microcontroller
31

-::-

19

EAIVP
X1

Cl
18

9

12
13
14
15

2
3
4
5
6
7
8

X2

RESET

INTO
INT1
TO
T1
P1.0
P11
P1.2
P1.3
P1.4
P1.5
P16
P1.7

PO.O
PO.1
PO 2
PO.3
PO.4
PO.5
PO.6
PO.7
P20
P21
P2.2
P2.3
P2.4
P25
P26
P27

AD
WR
PSEN
ALE
TXD
RXD

39
38
37
36
35
34
33
32

23
24
25
26
27
28
29
30

21
22
23
24
25
26
27
28

31
32
33
35
36
37
38
39

17
16
29
30
11
10

22
2

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7

PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AD8/A8
AD9/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PBO
PB1
PB2
PB3
PB4
PBS
PB6
PB7

AD

PCO
PC1

WRNp

1 BHEIPSEN
13
ALE
3
RESET

PC2
A19/CSI

21
20
19
18
17
16
15
14
11
10
9
8
7
5
4
40
41
42
43

GND

PSD313
80C31

34

12

-::RD

FigureS.
More Stringent
Ro Valid
to Data Valid
Timing

ALE

ADDRESS/DATA

~~-------------------------------------~~V_A_LI_D_A_D_D_R_E_S~S~r--1~-V-A-L-ID-D-A-T-A~~------­
:

T2

:

'------:

---------------------------------------~~~-----------------------------------1-.1-7--5

PSD3XX - Application IItJte 022

Adding
Capability.•.
(Cont.)

Table 4 shows part of the MAPLE software
solution for this problem which uses the
Combined memory space configuration.

Tablef.
Combined
MemolY Space
MAPLE Software
Solution

********************** MAPLE 5.00 **********************
PSD PART USED: PSD313
********************PROJECT INFORMATION*****************
Project Name :
.. 8031 App. note
Your Name :
= Dan Kinsella
Date :
.. May, 1992
Host Processor :
8031
********************ALIASES*****************************
/CS8/A16
= /RD
*********************GLOBAL CONFIGURATION***************
Address/Data Hode
MX
Data Bus Size :
8
Reset Polarity
HI
Security:
OFF
ALE Polarity :
HI
Using Different READ strobes for Data and Program: Y
Separate Data and Program Address spaces: N
********************READ WRITE CONTROL*****************
/RO and /WR
*****************PORT C CONFIGURATION******************

Pin
CS/Ai
LOGIC/ADDR
PeO
A16
ADDR
PC1
CS9
PC2
CS10
A19
CSI
******************************ADDRESS MAP***·*******************************

/RD = A16
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

A
19
N
N
N
N
N
N
N
N
N
N

A
18
N
N
N
N
N
N
N
N
N
N

A
17
N
N
N
N
N
N
N
N
N
N

A
16
0
0
1
1
1
1

A
15
1
1
0
0
1
1

0
0

0
0

A
14
0
1
0
1
0
1

A
13
N
N
N
N
N
N
N
N
1 0
0 1

A
12
N
N
N
N
N
N
N
N
1
1

A
11
N
N
N
N
N
N
N
N
0
0

SEGHT SECHT
STRT
STOP
18000 1BFFF
1COOO 1FFFF
00000 03FFF
04000 07FFF
08000 OBFFF
OCOOO OFFFF
15000
13000

157FF
137FF

FILE
STRT
10000
14000
00000
04000
08000
OCOOO

FILE
STOP
13FFF
17FFF
03FFF
07FFF
OBFFF
OFFFF

N/A
N/A

N/A
N/A

File Page Reg
Name
3210
TEST.HEX
TEST. HEX
TEST. HEX
TEST.HEX
TEST.HEX
TEST.HEX
N/A
N/A

Q.F
ALE
N
N
N
N
N
N
N
N
N
N

****************************************END***********************************

******************************ADDRESSES OF I/O PORTS*************************
Pin Register of Port A :
3002 Page (Binary):
Direction Register of Port A :
3004
Data Register of Port A :
3006
Pin Register of Port B :
3003
Direction Register of Port B
3005
Data Register of Port B :
3007
Page Register :
3018
**************************************************************************

~~---------------------"'~,.-----------------------1-176
'rINf1"

I'SD3XX - AppllcatlDn NDte 022

Reset
Circuit
Considerations

In a design where the 80C31 shares the
same reset signal with a PSD3XX, a race
condition exists if the reset circuit consists
of RC components only. Due to slow fall
time on the reset signal, the 80C31 could
get out of reset mode and start fetching
codes while the PSD3XX is still in reset.
The following three reset circuits are
recommended for use with 80C31 and
PSD3XX based designs:
1. Use a Reset Chip such as Dallas
Semiconductor's DS1232, or Maxim's
Max 699. Both have space saving, 8-pin
mini-Dip packages. The reset output is
connected directly to the reset pins on
the 80C31 and PSD3XX.

Summary

Using the PSD3XX family of Programmable
Microcontroller Peripherals in 80C51 type
microcontroller designs can significantly
reduce system design complexity and
enhance the end product at the same time.
Reusing hardware sections of existing
designs in new designs becomes an easy
process. Changing memory mapping and
even memory sizes is easily accomplished
by making simple adjustments in the
PSD3XX development software, i.e. by

2. Use two separate RC reset circuits: one
which generates a high reset pulse to
the 80C31 and the other one generates
a low reset pulse to the PSD3XX. The
RC constant of the PSD3XX reset circuit
should be less thant that of the 80C31
such that the PSD3XX reset signal has a
shorter pulse. In this case, the PSD3XX
is configured to have an active low reset
input.
3. Use a buffered reset signal: The ouptut
of an RC reset circuit is buffered by a
gate (such as 74HC14) before it is
connected to reset pins on the 80C31
and PSD3XX.

simply selecting where and how many of
the blocks are required. The flexibility of the
PSD3XX family is demonstrated by the
equal ease of design if a Combined or
Separate address space is needed. In
addition, the 4-bit memory paging register
in the PSD3X2 and PSD3X3 devices
enables the microcontroller to address
additional memory by a factor of 16.

----------------------------r;;~.?------------------------~~
flNfiil j
1-177

PSD3XX - Application Note 022

"~J:"€

~1--1=78~-----------------------------~~=----------------------------------

Programmable Peripheral
Application Note 023
PSD3XX Family
Programmable Microcontroller Peripheral
Design Tutorial
By Mark Elliott

Introduction

The PSD3XX family devices contain
several commonly used microcontroller
peripheral functions combined into one
package. These include EPROM, SRAM,
Chip Selects, and logic functions. Some of
the advantages of the PSD3XX family are:
board space is reduced, power
consumption is reduced, cost is competitive
- usually less, and board complexity is
reduced. Design risk is also reduced
because fewer traces are required on the
PWB and the PSD3XX devices are more
flexible than a discrete component design.
Mistakes or design changes pose less of a
potential problem. Additionally, the
PSD3XX device includes a security option
which, when implemented, protects the
internal configuration data from duplication.
For a particular application, the designer
should learn the PSD3XX family
architecture, understand the configuration
software, and understand the programming
process. While none of these tasks are
complicated, full knowledge of them is not
required to understand the PSD3XX family.

PART I - Using
the PS0312 with
a Standard 8031
System.

Figure 1.1 illustrates a standard 80C31
microcontroller board design. The board
contains a microcontroller, a 512 Kbit
EPROM for program storage, a 16 Kbit
static SRAM, and an address latch. In this
example, all of the circuits on this board,
excluding the microcontroller, will be
replaced. Keep in mind that the PSD312 is
not being used to its full advantage here.
In the second example, Part 2 of this application note, you will see that the PSD312 is
able to provide additional functions,
replacing additional discrete packages.

This application note introduces the
PSD3XX family design process by
example. While going through the
examples, you will learn about the entire
design process including hardware,
software, and programming. Those who
do not have a strong background in the
microcontroller field may also find
themselves able to use the PSD3XX. This
application note uses an 80C31 system as
a model. Even if you intend to use a
different microcontroller, you will find it
useful to read on.
This application note demonstrates two
designs using multiple packages which will
be replaced by a design using the
PSD312. The first example is a standard
80C31 board, one that does not make use
of all the PSD312's potential. This will form
a basis for understanding the product. In a
second example, new functions are added
to the standard design. By the end of the
application note, you should have enough
basic knowledge to understand the
PSD312 device's use in your design.

The PSD312 was chosen for this task
because it has the same SRAM and
EPROM space as that used on the original
design. A similar device, the PSD311,
would be more suitable for replacing a
smaller EPROM space of 256K bits or less.
If a larger EPROM space is required, a
PSD313 with its internal 1M bit UV EPROM
could be used.

1-179

PSD3XX - Application Note 023

Figure 1.1:
8031
Microcontrol/er
Standard System
Block Diagram

512 KBIT PROM

16 KBITRAM
RDWR

t

II

PSEN

A(7:0)
ADDRESS
LATCH

AD(7:0)

A(15:8)

ALE

PSEN

RD

WR

8031
MICROCONTROLLER

NOTE: Each Block represents one

Ie package.

_ ________________________________ F• •

1-180

~E

~41

________________________________

PSD3XX - Application Note 023

Physical
Connections

Figure 1.2:
Standard PSD312
Physical
Connections

The physical connections for the new board
design using the PSD312 are illustrated in
Figure 1.2. The multiplexed address/data
pins, 0 through 7, from the 80C31 port 0
connect to the PSD312 pins AD/A(7:0). The
upper address bits, 8 through 15 from port 1
connect to the pins A(15:8) on the PSD312.
The 80C31 write line is connected to
"WR.Vpp or R/W", the read line to RD/E,
ALE to "ALE or AS". The connections for

PSEN and RESET are straightforward. The
A 19/CSI pin is an unused input in this
application so it is tied low. Last of all, the
power, grounds and the decoupling
capacitor are connected. All other PSD312
pins will remain unconnected. These pins
become useful for a more functional design
such as in the second example.

Vee
O.1mF

.----.-----t------l)

r-----

GND GND
A19/CSI
""-

Vee
PA(7:0) -

NC

PB(7:0) -

NC

PSD312

NC- PC(2:0)
AD/A(7:0)

LATCHED
LOWER
ADDRESS
AND DATA
BUS

RD
WR
ALE
PSEN
A(1S:8) RESET

UPPER
ADDRESS
BUS

PO(7:0)

P1 (7:0)

)~

..

RESET

RD, WR,
ALE, PSEN,
RESET

8031
MICROCONTROLLER

NOTE: Addilional Mlcrocontrolier connecllons are not shown.

-----------------------------------~~~--------------------------------1---18-1

PSD3XX - Application Note 023

Configuration
OataEntry

Before the PSD312 can be programmed,
the MAPLE software is used to define the
PSD312 functionality. The MAPLE
software is menu driven making it very
easy to use. After the software is loaded,
entering the command MAPLE accesses
the software used to program the PSD3XX
device. The main MAPLE menu will appear
on the screen with its seven one-line
options. Highlighting the PARTNAME
option (or pressing F8), typing "PSD312"
and pressing ENTER selects the part
intended for programming. Next, the main
menu will call up the correct subprogram
used to configure the part selected. The
subprogram looks very much like the main
menu except that a second option box will
appear on the right of the screen. See
Figure 1.3 for an illustration of this menu as
it appears on the computer display screen.
In all illustrations, only the menus will be
shown to enhance clarity. Other
information may appear on the screen. For
example, help information often appears to
assist the designer. After an option is
highlighted using the cursor controls,
pressing ENTER will execute that option.
The cursor controls enable the user to
maneuver between option boxes and
among the options within a box.
To configure the PSD312 you must focus
on the option box to the right of the screen.
The first option in this box is PROJECT
INFORMATION which enables the user to
store information about the software file.

The next option is ALIASES which provides
the ability to name a pin with an alias name
to help prevent mistakes. The alias name
will show up in other menus that use the
pin. This option will not be used in this
example.
The next option is CONFIGURATION.
After the CONFIGURATION option is
selected, the CONFIGURATION menu, like
that shown in Figure 1.4, will appear.
Figure 1.4 displays the correct information
for this example. When a line in the
CONFIGURATION menu is highlighted, an
explanation of the question is provided in a
dialogue box at the bottom of the screen.
The last question, "Separate Data and
Address Spaces?" appears when Y is
answered to "Using different READ
strobes ... ". This question will not appear
when the menu is first entered. Each
question has two possible answers.
Pressing the space bar will toggle between
the two answers; no typing is required.
Each answer to an option is explained
here. See Figure 1.4 for reference.
This CONFIGURATION menu contains all
of the necessary information to configure
the PSD312 for use with the 80C31.
Additional information is required in other
menus to program the PSD312 logical
functions. Pressing F1 returns to the main
menu. All of the data entered in the
CONFIGURATION menu (and all other
menus) is automatically saved.

MX

The 80C31 uses a multiplexed address. We have made the correct
connections in the hardware design so that the PSD312 will automatically
know which pins to multiplex and how to multiplex them.

8

The 80C31 has an 8 bit data bus width. This is the only width supported
by the PSD312.

A19

This option is arbitrary at this time because we are not using A 19 as an
input or CSI (the power down option).

HIGH

The reset polarity is high for the 80C31.

WRand RD

The 80C31 uses separate write and read strobes for SRAM.

HIGH

The ALE polarity is high for the 80C31.

y

The separate read strobes are RD for SRAM and PSEN for EPROM.
The Y answer enables the PSEN feature.

y

The data and address space are separated by the read strobes.
Data (SRAM) and program (EPROM) share the same address space.
The different read strobes, RD for SRAM and PSEN for EPROM, enable
them to share this space.

1~-~18~2-----------------------------~Jf~-------------------------------

PSD3XX - Application Note 023

Figure 1.3:
MAPLE
Main Menu

F1
F2
F3
F4
F5
F6
F7

Figure 1.4:
Configuration
Menu

EXIT
DOS
MAPPRO
PARTLIST
LOAD
SAVE
COMPILE

PROJECT INFORMATION
ALIASES
CONFIGURATION
PORT C AND A19/CSI
PORTA
PORTB
ADDRESS MAP

Configuration Bit

Value

AddresslData Mode (Multiplexed: MX, Non-Multiplexed: NM)

MX

Data Bus Width (8/16 Bits)

8

Reset Polarity (Active Low: LO, Active High: HI)

HI

Security (ON/OFF)

OFF

To Select Read, Write Logic, Press SPACEBAR.
ALE Polarity (Active Low: LO, Active High: HI)

Configuration
Data Entr,
(Cont.)

HI

Using Different READ Strobes for Data and Program? (YIN)

Y

Separate Data and Address Spaces? (YIN)

Y

The next option in the option box is PORT
C and A 19/CSI. Although these pins are
not used, they must be correctly
programmed. Figure 1.5 shows the menu
containing the correct information for this
example. Port C consists of three pins
PC(2:0). Each of these pins can be
individually configured as a chip select
(output) or an address (input). If ADDRESS
is selected, there is the choice of using a
LOGIC or ADDRESS input type for each
pin. The space bar is used to toggle among
the selections. (PCO = CS8 or A16,
PC1 =CS9 or A17, PS2 =CS10 or A18.)
An address can exist out of sequence as in
this example where A 19 exists but A 16,
A17, and A18 do not.
The PORT C pins must be tied low if they
are programmed as inputs and are unused.
However, outputs are not required to have
terminations and can remain untied. The
easiest solution is to program all Port C
pins as chip select outputs to avoid
unnecessary board traces. The user could
proceed to define the chip select equations
for the pins defined as chip selects but it is
not important since they will not be used.
Pressing F1 will return the program to the
main menu.
F_S6iEE

Port A is the next menu option on the right
of the main menu screen. The PORT A
ADDRESSIIO menu selections are shown
in Figure 1.6. PORT A will not be used in
this design but it should be programmed
correctly. The default selections are the
same as shown here. The selections are
shown to help the user understand PORT
A functions. After selecting the PORT A
option you are given a choice between
ADDRESSIIO and TRACK MODE. The
ADDRESSIIO option, if chosen, enables
each PORT A pin to output-buffer the
address bits from AD/A(7:0) or transmit bits
through the internal 1/0 ports. Each pin is
individually programmed as either an
ADDRESS or an 1/0 in the AillO column of
the menu. Each pin should be chosen as
an output address. Pressing F1 twice
returns the program to the main menu.
Port B is the next option in the menu.
PORT B pins can be configured as chip
select outputs or 110 ports just like PORT
C. Since PORT B will not be used in this
example, all of the pins should be
configured as outputs for the same reason
as given for the PORT C pins.

-------------------------------------~5fAr----------------------------------1--1--83

I'S03XX - Application Note 023

Figure 1.5:
PortCMenu
Standard

Figure 1.6:
PortA Menu
Standard

Configuration
Data Entry
(Cont.)

PIN
PCO
PC1
PC2
A19

CS/Ai
CS8
CS9
CS10
A19

ADDRILOGIC

PIN
PAO
PA1
PA2
PA3
PA4
PAS
PA6
PA7

AillO
AO
A1
A2
A3
A4
AS
A6
A7

CMOS/OD
CMOS
CMOS
CMOS
CMQS
CMOS
CMOS
CMOS
CMOS

LOGIC

The last option is ADDRESS MAP. The
address map lets the user select address
ranges for EPROM, SRAM, and 1/0 in the
same way that you would using separate
packages. The difference is that, for
separate packages, you would use chip
selects to enable a chip when in its
address range. For the PSD312, you just
enter the conditions that will select each
module. Figure 1.7 shows the correct
address map entries for this design.
Looking at addresses 16,17, and 18, there
is an N listed down the column. This
means that the addresses can not be
used as address inputs. They do not exist
as addresses and can not be used as
select bits. This is so because, in the
configuration of PORT C, we chose all of
these pins to be chip select outputs. If we
had configured the PORT C pins to be
logic inputs, then we would have had to
enter an X for "don't care" in those same
columns. The SEGMT columns are usually
filled in automatically by the program. They
are left blank in this case because the N
listed down the address columns make the
segments undefinable.
Instead of having one contiguous EPROM
space, the PSD3XX family EPROM is
broken up into 8 Kbyte blocks. In this
application, the selects for each block are
ESO through ES3. Notice that no two
blocks of EPROM are selected under the
same address conditions. After all, you
can't look at two different EPROM
addresses at once. The other selects, ES4
through ES8, will not be used in this
example. An N is listed down the columns

r··.Il'

for A 11 and A 12 because the blocks are
bigger than the use of these address bits
permit. The N stands for "not used"
because the bits are not used for selection.
That is, we "don't care" about these bit
values. The EPROM file we will use is
called DEMO. HEX and it exists in the MAP
directory so that the MAP PRO software can
find it when programming the PSD312. The
size of the blocks for DEMO. HEX match the
side of the blocks for the EPROM. RSO is
the select for SRAM. Notice that SRAM
(RSO) and EPROM (ESO) can be selected
under some of the same address
conditions. This is not a problem because
SRAM and EPROM can share address
space since their data is selected by
different read strobes (PSEN and RD). See
the CONFIGURATION menu, Figure 1.4).
CSP is the chip select for the PSD312 I/0s.
1/0 ports are selected by selecting each
appropriate address which is an offset from
the address of CSP. We are not using the
110's so we can disable them by selecting a
true condition for A19. A19 is tied low in
the hardware so this condition will never
occur. This hardware solution is not
required in most cases. Usually, a CSP 1/0
base address can be set aside so that 1/0
data will not interfere with EPROM or
SRAM data.
The ADDRESS MAP menu extends
towards the right of the screen. Pressing
the right cursor pans the menu to the right.
This portion of the menu does not require
input for this example. Leaving the inputs
blank means "don't care". Pressing F1
returns the main menu.

- 1 . - 1 8 - 4 - - - - - - - - - - - - - - . . .A . 1 - - - - - - - - - - - - - - -

PS03XX - AppllcatlDn NDte on

Configuration
BataEntr,
(Cont.)

Figure 1.7:
Standard Address
Map Menu

Programming
ThePSB3XX

At this point, all of the necessary menu
items have been completed. On the left
option block in the main menu is a SAVE
option. You must type a name to store the
file and press ENTER. The name given to
this file will be DEMO. The extension is
automatically appended. Saving is done so
that next time the DEMO file is loaded, the
menus will display the information entered.
This is especially useful when modifying
earlier designs. The file needs to be
compiled to run on the MAPPRO software.

A

A

A

A

A

0
0
0
0

N
N
N
N
N
N
N
N
N
N

N
N
N
N
N
N
N
N
N
N

N
N
N
N
N
N
N
N
N
N

0
0
0
0

0
0

A

A

A

0
0
1
1

0
1
0
1

0
0

0
0

N
N
N
N
N
N
N
N
0
0

19 18 17 16 15 14 13 12
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

0
1

A

11
N
N
N
N
N
N
N
N
0
0

The MAP PRO software is used with the
WSI MagicPro@ PROM programmer to
program the PSD312. MAPPRO can be
started from the main menu or by entering
the command MAP. When started, the
MAPPRO menu appears as a list of
options. Each option is selected by typing
the first letter of the option.
The "Name of the Device" option selects
the device to be programmed. Typing in
PSD312 selects that device. The DEMO
file is loaded by the "Load RAM from disk"
option. After the PSD312 is plugged into
the MagicPro device, program the PSD312
by selecting "Program". The program then
asks for the starting addresses of SRAM
and EPROM for which the default address
is entered. Programming will take a few
minutes.
The PSD3XX Family Device can be made
secure by selecting the "Set Security"
option. Make certain that this option is not
selected until after the device configuration
is programmed. If the security bit is
programmed before the configuration, the
PSD312 will fail the blank test and will
require UV erasing.

Selecting the compile option does this. The
same name DEMO is typed and the correct
extensions will be appended to the files
generated. The user can look at a report
file which is generated during the compilation. It can be used to verify the programming parameters. The COMPILE option
takes a few minutes to run, depending on
the speed of the PC used. The compiled
configuration file can now be used in
MAP PRO to program the PSD312.

SEGMT
START

SEGMT FILE
STOP START

FILE
STOP

FILE NAME

0
2000
4000
6000

1FFF
3FFF
5FFF
7FFF

DEMO.HEX
DEMO.HEX
DEMO.HEX
DEMO.HEX

N/A
N/A

N/A
N/A

The MAPPRO software can check a design
by using the "verify" option. This option
compares a PSD3XX series device, which
is installed in the MagicPro@ PROM
programmer, to configuration and EPROM
data which was previously loaded in the
MAPPRO software. The "previously
loaded" information may have been loaded
during either the "Load RAM from disk" or
"Upload data from device" option.
The "Upload data from device" option
reads the PSD312 information and installs
it into the MAPPRO RAM. With this option,
PSD3XX family devices can easily be
compared to one another or to the
MAPPRO RAM. However, if the security bit
has been set, selecting this option will not
load the data.
The "Display RAM data" option can be
used to display the PSD312 data which is
contained in the MAP PRO RAM. This can
be especially useful when you need to
analyze EPROM data.

-------------------------r~I~,~------------------------'rINTIA

1-185

PSD3XX - ApplicatiDn NDte 023

PART II.
Advanced
PSD3XX Family
Design

By now you should have a basic
understanding of the PSD3XX device so it
is time to introduce some additional
features. This example will solve a slightly
more complicated design problem. By
going through this example you should
understand how to use the PSD3XX device
to realize functions for your own unique
designs.
Assuming the design in Part 1 has been
created and saved under the name DEMO,
you can load that program in the MAPLE
menu to begin this new design. This will
keep you from having to enter redundant
information. For example, the CONFIGURATION menu will not require any changes
in this design. In this second example,
restating the method of navigating through
the menus will be avoided for purposes of
brevity.

Figule 2. 1.
Advanced 8031
Miclocontlollel
System
Block Diaglam

The diagram in Figure 2.1 illustrates the
new microcontroller board design to be
replaced by a design using the PSD312. In
addition to functions previously replaced in
the standard board design, this board
includes chip select logic, 1/0 buffers, and a
logic chip. The logic chip does not perform
microcontroller functions but is included to
show the flexibility of the PSD312. An
additional change is there is now an SRAM
chip select which is an input to the
board. Its logic select function is defined
elsewhere so it does not need to be
recreated in the PSD312's chip select logic.
This scenario would occur when some
other device has a separate SRAM of its
own. This other device will decide whether
the microcontroller writes to the PSD312
SRAM or its own SRAM. The configuration
of this design is mostly the same as in Part
1. We are now using PORT A as an 1/0
buffer, all PORT C pins are now used as
logic inputs, and we must specify the chip
selects in PORT B to conform to our logic
and chip selects.

512 KBIT EPROM

16KBITSRAM
RD WR

- -- ~

i

PSEN

ii
.J

I

I

A(7:0)

AD(7:0)

PSEN

t

ADDRESS
LATCH

,~ 1
~

I

L

VO
BUFFERS

A(15:8)

tt

NOTE: Each Block represents one

I

I

I

MICROCONTROLLER

I.
LOGIC OUTPUTS

RD WR

8031

CHIP
SELECT
LOGIC

LOGIC

t

•
•

I
LOGIC INPUTS

Ie package.

----------------------------~Jrl--------------------------1-186

PS03XX - AppllcatlDn IIDte D23

Advanced
PSD3XX Family
Design
(Cont.)

Figure 2.2 illustrates the physical
connections to the PSD312. The SRAM
chip select is input to A 19 (A 19/CSI), and
the logic inputs are input through A(18:16).
These are arbitrary assignments among
the address inputs. PORT C could not be
used for chip select outputs because we

needed to make room for the inputs. See
Figure 2.3 for PORT C menu selections.
Notice that the address inputs can be used
for logic. Although the name of the inputs
are ADDRESS, they are really either logic
or address inputs.

Figure 2.2:
Advanced D~sign
PSD312/8031
Physical
Connections

Vee
O.1mF

)1---

-::....

GND GND
RAM_CSN
~

Vee
PA(7:0)

A19/CSI

..

110 SIGNALS

PB(7:0)
LOGIC INPUTS

•

PSD312
PC(2:0)

AD(7:0)

LATCHED
LOWER
ADDRESS
AND DATA
BUS

A(1S:8)

UPPER
ADDRESS
BUS

PO(7:0)

P1 (7:0)

RD
WR
ALE
PSEN
RESET

CS (3:0)

••

CHIP SELECTS
AND LOGIC

....---RESET

RD, WR,
ALE, PSEN,
RESET

8031
MICROCONTROLLER

NOTE: Additional Mlcrocontroller connections are not shown.

----------------------------------~
__Jr_JF_~---------------------------------1·187

----~-----

-

---

-------

--

-----

PSD3XX - AppllcatlDn NDte 023

Advanced
PSD3XX Family
Design
(Cont.)

Figule2.3:
Advanced
PortC
Menu
Figule2.4:
Advanced
PortA
Menu

FiguI82.5:
Advanced
Port,
Menu

Table 2.1:
Logic Tluth
Table

The I/O buffers connect to the PSD312
through PORT A. PA(3:0) are inputs,
PA(7:4) are outputs. See Figure 2.4 for
PORT A configuration.
Port B is used for the chip select and logic
outputs. See Figure 2.5, the PORT B menu.
These pins must be defined as chip select
outputs. The CMOS/OD for CMOS or open
drain output is the next option. From here
we go to the chip selects for the PORT B
pins. Table 2.1 describes the function of the
logic chip. This type of logic might be used
in a state machine. In the menu selections

PIN
PCO
PC1
PC2
A19

CS/Ai
A1S
A17
A18
A19

ADDRILOGIC
LOGIC
LOGIC
LOGIC
LOGIC

PIN
PAO
PA1
PA2
PA3
PA4
PA5
PAS
PA7

Ai/IO

10
10
10
10
10
10
10
10

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

PIN
PAO
PA1
PA2
PA3
PA4
PA5
PAS
PA7

Ai/IO
CSO
CS1
CS2
CS3
CS4
CS5
CSS
CS7

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

A

INPUTS

B

C

OUTPUT CONDITION
(CSO)

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0
1
1
0
1
1
0
1

-

for CSO we look at the occurrences of a
logic low from the table and enter that
information into the chip select menu as
shown in Figure 2.S. Notice that all other
columns are left blank since they won't be
part of the chip select equation. That is, we
don't care about their levels. For example,
we could use ALE or the page selects, PO
through P3, as logic inputs. Figures 2.7,
2.8, and 2.9 show the other chip select
menus. These chip selects enable
components on other boards when their
address ranges are encountered.

-------------------------~Jr;------------------------

1-188

PS03XX - Application Note 023

Tab/e2.2:
ChipSe/ect
Address Map

Figure 2.6:
ChipSe/ect
Definition CSO

Figure 2.7:
ChipSe/ect
Definition CS1

Figure 2.8:
ChipSe/ect
Definition CS2

Tab/e2.9:
ChipSe/ect
Definition CS3

CHIP SELECT

ADDRESS RANGE
15

CS1
CS2

DOOO- DFFF
COOO-C7FF

CS3

C800- CFFF

A19 A18 A17 A16 A15 A14 A13 A12 A11

ADDRESS BITS
14 13 12 11

X

1
0
0

0
0
0

0

RD

WR ALE

P3

P2

P1

PO

RD

WR ALE

P3

P2

P1

PO

A19 A18 A17 A16 A15 A14 A13 A12 A11
1
1
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

RD

WR ALE

P3

P2

P1

PO

A19 A18 A17 A16 A15 A14 A13 A12 A11
1
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

RD

WR ALE

P3

P2

P1

PO

o
o

0

0

1

1

0

X

X

X

A19 A18 A17 A16 A15 A14 A13 A12 A11
1
1
0
1
X

X

X

X

X
X

X
X

X
X

X
X

ii' _ _ 4iEE

------------------------------~~;----------------------------1---1H

PS03XX - Application Note 023

Advanced
PSD3XX Family
Design
(Cont.)

Figure 2.10:
Advanced
Address Map
Menu

Conclusion

The address map is shown in Figure 2.10.
Notice that the SRAM chip select, A19,
must be enabled for the microcontroller to
access the SRAM. This will enable another
device to select which SRAM is enabled for
a read or write. Address A 19 is listed as a
"Don't care" or "X" for ESO through ES3
because the SRAM chip select, A19, may
be enabled during an EPROM access. The

ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

19 18 17 16 15 14 13 12

A

A

A

A

A

A

A

A

11

A

X
X
X
X

X
X
X
X

X
X
X
X

X
X
X
X

0
0
0
0

0
0
1
1

0
1
0
1

0
1

X
0

X
0

X
0

0
0

0
0

0
0

N
N
N
N
N
N
N
N
0
0

N
N
N
N
N
N
N
N
0
0

read strobes, PSEN and RD, are used
to separate the EPROM and SRAM. The
CSP is the enable for the I/O functions. It is
selected for address 80 Hex. Since the
EPROM address locations have been
carefully mapped, the 1/0 address
selections will not coincide with EPROM
addresses.

SEGMT
START

SEGMT FILE
STOP START

FILE
STOP

FILE NAME

0
2000
4000
6000

1FFF
3FFF
5FFF
7FFF

DEMO.HEX
DEMO.HEX
DEMO.HEX
DEMO.HEX

N/A
N/A

N/A
N/A

A PSD3XX family device can implement
many common microcontroller functions
and it is flexible enough to be used on
designs requiring special functions. Its use
will reduce the component count, layout
complexity, size, component cost, PCB
cost, and power consumption of a design.
Reliability is increased due to the reduced
chip count. The risk of board redesign is
minimal given the ease of design and the
PSD3XX device's flexibility. The user
friendly software makes it easy to use in
any design.

",iF

E

--------------------------------------~aJJf-------------------------------------

1-190

Programmable Peripheral
Application Note 024
Using the PS0311 with a
High-Speed ADSP-2105 OSP
By Lane llauclc, Proxima Corp.

Introduction

Digital Signal Processor (DSP) chips are
enjoying a surge in popularity with system
designers, due to their high performance
and dropping prices. Fueled by a large PC
peripheral market, primarily in disk drive
controller and "multimedia" signal
processing applications, DSP offerings now
include high-performance processors that

execute instructions in 100 ns or less for
under $10. To achieve a total solution the
designer needs to add periphery circuitry.
The WSI PSD3XX family of programmable
peripherals implement the periphery
functions by effectively integrating
programmable logic, I/O ports and memory
on a single chip.

The Processor

The Analog Devices ADSP-2101 family is
a good example of the inexpensive DSP
power available today. The lowest-cost
member of the family, the ADSP-21 05, has
the following features:

In one 100 ns cycle, the ADSP-2105 can
fetch two operands, update the address
units that pointed to the operands, multiply
the two 16-bit operands and accumulate
(add) the result to a 40-bit total. Program
looping is done in hardware, so one of
these fancy instructions can be executed
every 100 ns.

Q 16-bit multiplier/accumulator
Q Hardware (zero time) looping
Q 1K 24-bit internal program memory
Q 512 16-bit internal data memory

Q
Q
Q
Q

The Periphery

Two hardware address generator units
Barrel shifter
Synchronous serial port
TImer

The WSI PSD3XX family has found wide
application in microcomputer systems.
Because the PSD3XX chips offer all of
the elements and "periphery" required for
many applications in one package, they
make possible very economical two-chip
computer systems. Thumbing through the
WSI PSD Data Book, it soon becomes
apparent that the PSD3XX chips are great
for 8051, 68HC11 and other microcontroller
designs. But what about a chip for a DSP
like the ADSP-2015?

Although a PSD100 chip is available
expressly for DSP support, it's not the
lowest cost choice because of its very high
speed (access time of 45-55 ns).
However, a feature of the ADSP-2101
family makes it possible to use the lowest
cost PSD3XX chip available, the PSD311,
to make a true 2-chip DSP system! In fact,
the 100 ns ADSP-21 05, which requires
program memory access time of around 50
ns, can use the PSD311-12 (or even a
slower version) for all of its system support,
while still executing programs at a
sustained 100 ns cycle time.

1·191

PSD3XX - Application Note 024

ADSP
Memory
Organization
Program
Memory

Program memory for the ADSP-21 05
consists of 1024 24-bit words of RAM
inside the DSP chip. A special external
memory space, called "boot memory," is
supported by the ADSP-2105 to enable
connection of a byte-wide EPROM to the
ADSP-2105 for loading the program
memory at power-up, or subsequently
under program control. A special active-low
strobe signal, BMS (Boot Memory Select),
simplifies the boot memory interface. All
you need to interface a boot EPROM is to
connect the EPROM address and data
lines to the ADSP-2105 (see Figure 1), and'
the BMS signal to the PSD311 chip enable.
The two-chip design uses a 2K byte
section of the PSD311's EPROM as boot
memory. The connection to the PSD311 is
almost as straightforward as connection to

a standard EPROM. Because of the way
the busses are laid out inside the
ADSP-21 OS, the eight PSD311 data lines
are connected not to D7-DO, as you would
expect, but to D15-D8 (see Figure 1).
Also notice that the most significant
address is supplied by the ADSP-21 05
"D22" line - there's no "A 14" address line.
The BMS signal acts as an EPROM chip
select and is connected to the PSD311
"A19" input. A19 is programmed as a chip
enable signal, as described later.
T~e

ADSP-21 05 generates active low read
and write strobes, which are connected to
the corresponding PSD311 RD and WR
inputs. These strobes serve to enable
transfers to and from the PSD311 EPROM
and RAM.

Figure 1.
Schematic
Diagram

SYSTEM RESET

023-016
10MHz

.----.._--1

XTAl

ADSP-2105

I-=

ClKIN

015-08 07-00 022 A13-AO

I-=

BMs OMs RD WR

NC

+5V

PA7-PAO

A14 A13-AO A19 A18 RO WR

ALE

PSD311

RES 1:)-----'

:- ..1>0.-:

··

..

TO SYSTEM
GENERAL
PURPOSE
110 LINES

ONE
MORE
INVERTER

PSD3XX - ApplicatlDn NDte 024

Data
Memory

The ADSP-21 05 has 512 16-bit words of
internal data memory, located at $3800.
This is augmented by the 1024 bytes of
RAM in the PSD311. Fortunately, the data
bus is connected to the same ADSP-2105
data lines -- 015:08 -- as the boot EPROM,
so the address and data connections that
were made for the boot EPROM are also
valid for the RAM. All that is needed for
RAM system integration is to program the
PSD311 to place it's RAM in the desired
slot on the ADSP-21 05 memory space.
Although using the 8-bit wide PSD311 RAM
in a 16-bit system may be troublesome,
remember the ADSP-2105 already has 512
16-bit words of high-speed internal RAM.

This design made good use of the
"extra" RAM in the PSD311, and even
incorporated an additional chip to gain
some speed in using this RAM. Notice that
the ADSP-2105 data lines 023-015, which
constitute the upper byte of the 16-bit data
bus, are driven by an octal, tri-state buffer
whose inputs are tied low. If this were not
done, any 16-bit read of the 8-bit PSD311
RAM would contain garbage in the upper
8 bits (since these inputs are unconnected).
If you can spare a couple of cycles to mask
off the upper bits, or if your application
doesn't look at the upper 8 bits, the buffer
can be eliminated.

Logic
Functions

The Programmable Address Decoder
(PAD) is used to generate miscellaneous
control signals, plus some I/O port bits.
Two active-low strobes, XRD (external
read) and XWR (external write), go to other
I/O peripherals in the system. As with all

designs, this was one inverter short, so the
A 15 line was configured as an input, the
CS6 line as an output, and with the logic
equation CS6 = A15 a chip was saved.
Very handy, that PSD311 PAD!

Configuring
thePSD311

The WSI "PSD-Gold" development system
was used to specify the PSD311 design file,
and the MagicPro® Programmer (included
in the PSD-Gold system) to program
PSD311 parts. Appendix B shows the
".SV1" file that was created from the
design. The" .SV1" file is a convenient
summary of the PSD311 design, which
includes aliases (named signals), global
configuration information (how the part is
set up), Port B configuration (assignment of
port-B pins as I/O bits or chip selects
outputs), Port C configuration, and logic
equations for the two PADs.

For example, CS8 and A16 share the same
pin, so if you use the pin as output CS8,
the input A 16 pin is unavailable (shown
crossed out in the workshee!L.!:ikewise,
the CS9-A 17 pin is used as CS9, so A 17 is
unavailable, and CS10-A18 is used as an
input (A18), so the CS10-PC2 pin is
crossed out.

Before using the PSD-Gold development
system, it is very helpful to make a
configuration worksheet as shown in
Appendix A. This is a version of the
PSD311 PAD description chart that appears
in the WSI Programmable Peripherals
Design and Applications Handbook. Some
of the PSD311 pins can serve as either
inputs or outputs. The worksheet helps to
keep the pin aSSignments clear.

MagicPro

IS

a registered trademark of WaferScale Integration, Inc.

"fllJilE

-------------------------------------~~Jr-------------------------------------

1-193

l

PS03XX-APPlicationNot~e~OZ'4~================-__________
Appendix A
ESO

ES1
ES2
ES3

i

ES4
ES6
IUtWBi*ES5
ES7
RSO

CSIOPORT
CSADIN
CSADOUT1
CSADOUT2
@)A19

@:>A18

LCs~

)4

LCs~

W

GDA15

~A14
G!VA13

~A12

~@)

@)A11
CSI
RESET

K~

MC®

•
•

~\!I18J

-------------------------------------~~.------------------------------------.,.,..-

1-194

~

PSD3XX - Application Note 024

Memory
Space

The ADSP-21 05 outputs a 14-bit address.
The PSD311 has a 32KByte EPROM,
organized as eight 4K byte "blocks," each
with its own internal chip-enable signal that
is programmed in one of the PADs. EPROM
chip select signals are therefore developed
from address lines A12-A14, with AO-A11
(accounting for each 4K block) going to
each of the eight EPROM blocks. It was
puzzling at first to see the signal A 11
appear on the PSD311 PAD description
since it does not participate in any of the
chip select equations. Only after firing up
the PSD-Gold software was it made clear
that this input is not allowed in the EPROM
chip select equations.
A12-A14 are connected to ADSP-2105
A12, A13 and 022 (022 serves as "A14" as
previously mentioned). The remaining
PSD311 address inputs A15, A18, and A19
are available as general purpose inputs:
A18 was used as OMS, the ADSP-2105
Data Memory Select signal, and A 19 as
BMS, the ADSP-2105 Boot Memory Select
~nal. As mentioned previously, the ADSP
RD and WR signals are connected directly
to the corresponding PSD311 signals.

14. CSI/A19: A19
This double-duty pin can be used to
power down the PAD when the CSI
input is held high. The DSP design
does not use this feature so A 19 was
selected, making this pin a general
purpose input.
15. Reset Polarity: LO
This was made the same polarity as
the ADSP-21 05 reset so the two could
be connected together.
16. ALE Polarity: HI
ALE is not used in a non-multiplexed
design, but it must still be accounted
for. ALE must be declared HI or LO,
and then tied HI or LO to make the
address latch '~ransparent". HI was
chosen and tied the ALE pin HI.
17. WRD/RWE: WRD
Selects separate strobes for RD and
WR, rather than R/W and Enable pins.
This enables direct interface to the
ADSP-2105 RD and WR inputs.
18. A16-A19 Trans: T

The inverter consists of the unused A 15
input and the CS6 output. These signals
are labeled "HD" and "HD" in the Appendix
A worksheet.
Appendix B gives a summary of the
questions asked by the configuration
software, and the answers given for the
DSP design. Line numbers have been
added for discussion purposes. On lines
3-7, the signal name assignments are
shown. Lines 12-19 show the configuration
information, as follows:
12. Address/Data lines are NM:
Non-Multiplexed.
This separates the low-8 address and
data lines instead of multiplexing them
onto one 8-bit port and separating them
with an ALE (Address Latch Enable)
signal. In this design the address and
data lines are separate so NM is
chosen.

A 16-A19 are used as general purpose
inputs so they are configured to be
"transparent", i.e. non-latched.
19. Using different. .. N
The RD signal is used for both the
PSD311 RAM and EPROM, so the
answer to this question is "No."
Basically, there are two ways to
develop strobe signals for the
PSD311's internal RAM and EPROM.
In the "Combined Address Space"
option, the RD signal, qualified by the
external PSEN signal, is used to
enable both the RAM and EPROM. In
the "Separate Code and Data Address
Spaces" option, the RD signal enables
the RAM, but the separate PSEN
signal enables the EPROM. This is
how 8031-type systems are hooked up.

13. Data Bus Size: 8
"8" is the only choice in the PSD311
(you can choose 8 or 16 in the PSD301
part).
filiF liFE

-------------------------------------~.r~----------------------------------1--1-9-5

PS03XX - Application Note 024

Memory
Space (Cont.)

Since the ADSP-2105 issues a single RD
strobe for all of its external memory, "NO"
was answered to this option. IMPORTANT:
Since the RD sign~ualified by the
PSEN signal, the PSEN signal must be tied
HI (to Vce) when using this option.
Lines 26-33 of Figure 2 show the output
configurations for the Port B pins. "CMOS"
was chosen over open drain.
Line 37 shows the logic equation for the
inverter. The CS6 signal is shown as it's
alias name, "HD," but the A15 signal is
shown as is (it was named HD in figure 1.)
Lines 46-48 show how the three pins that
can be inputs or outputs were assigned,
and lines 53 and 55 show the logic
equations for the external read and write
strobes.
Finally, lines 67-76 show the logic
equations that select the EPROM and
RAM. "ESO" is the EPROM Strobe for the
first 2048-byte EPROM block. The file
mane "CYRM30.HEX" is entered to show
where to find the Intel Hex format file for
the data to be programmed into this
EPROM block. It's important to remember
to "re-compile" the design anytime the
EPROM file list (lines 67-74) is changed.
The compiler incorporates the hex files into
its programming data only when the
compiler is run.

Notice that the block size of the PSD311 ,
4 kilobytes, happen to be the same "block"
size as the ADSP-2105 boot blocks, so the
logical divisions of ADSP-21 05 boot blocks
and PSD311 chip selects are the same one of those happy accidents that occur
every so often in engineering design.
Only the first block was needed to begin
the design. As the design progresses more
or all of the EPROM blocks will probably be
used. Blocks are added by entering File
Names to the list, or using the same file
name and giving different segment start
and stop addresses within the file.
"RSO" (line 75) is the RAM chip select
equation, and "CSP" (line 76) is the base
address for the output port registers.
Note that the signal shown as "A 19" is
actually the ADSP-21 05 BMS signal, and
thus is LO for the EPROM chip selects (the
EPROM is used as boot memory). Also,
the "A18" signal is actually the ADSP-2105
DMS signal, which is LO for the RAM and
10 chip select equations. Aliases would
have been handy for these signals, but the
development software does not presently
support aliases for all signals.

ADSP-2105
Timing

The ADSP-2105 offers great timing
flexibility in talking to outside peripherals
such as the PSD311. Four separate
memory spaces may be assigned
individual numbers of wait states to
accommodate wide timing differences.

The ADSP-21 05 "Wait Register" was
programmed for 1 wait state, i.e. a 200 ns
cycle time, for EPROM, RAM, and external
memory strobes. This allows comfortable
margins with a PSD311 120 ns part.

Summary

At first glance, the lowest-cost member of
the PSD family might not appear to be a
match for a high-speed number cruncher
like the ADSP-21 05. After some analysis,
however, it turns out 10 be a perfect match,
making possible a very effective two-chip
system. The eight-bit organization of the
PSD311 EPROM makes it suitable
for implementation as the ADSP-21 05 boot
memory, and the 8-bit RAM is easily
interfaced into the ADSP-21 05 datamemory space. The PSD311 1/0 section
provides welcome system interface bits,

and the programmable address decoders
offer the required flexibility to place the
various PSD311 resources where they are
needed in the ADSP-2105 memory space.
If there are pins left over, the PAD can even
be used to implement some "stray" logic, if
required. Because of the ability of the
ADSP-2105 to insert a programmable
number of wait states into external
accesses, the designer may choose the
PSD311 speed necessary for the most
cost-effective design.

-------------------------------------~ar~-------------------------------------

1-196

PS03XX - Application Note 024

AppendixB
The .SV1
File
ALIASES

2
3

/cse/Al6

XRD

4

/CS9/A17

XWR

5

/CSIO/AIB

DMS

6

/CSI/A19

BMS

7

/CS6

= HD

8
9

*********************************************************************

GLOBAL CONFIGURATION

10

11
12

Address/Data Mode:

NM

13

Data Bus Size:

8

14

CSI/Al9 :

A19

15

Reset Polarity:

LO

16

ALE Polarity:

HI

17

WRD/RWE:

WRD

18

Al6-Al9 Transparent or Latched by ALE:

T

19

using different READ strobes for SRAM and EPROM: N

20
21

*********************************************************************

22
23

PORT B CONFIGURATION

24

25

Bit No.

26

0

10

CMOS

27

1

10

CMOS

28

2

10

CMOS

29

3

10

CMOS

30

4

10

CMOS

31

5

10

CMOS

32

6

CS6

CMOS

33

7

10

CMOS

CS/IO.

CMOS/OD.

!F • • .,lE
-------------------------------------------~.,~-------------------------------------------

1-197

PSD3XX - Application Note 024

AppendixB
The .SV1
File (Cont.)
34

35

CHIP SELECT EQUATIONS

36

37

I ( A15 )

HO

38

39

40

*********************************************************************

41

42
43

PORT C

CONF~GURATION

44
45

Bit No.

CS/Ai.

46

o

csa

47

I

CS9

48

2

Ala

49

50
51

CHIP SELECT EQUATIONS

52
53

XRO

I( IOMS * IAl3

* IAl2 *

All

* I

RO )

XWR

I( IOMS * IAl3 * IAl2 * All

* I

WR )

54
55
56
57
58

59

*********************************************************************

-----------------------------------------'jF~~~----------------------------------------:=
1·198
~-=-=='

PSD3XX - Application Note 024

AppendixB
The .SV1
File (Cont.)
60
61
62

ADDRESS

MAP

63
64
65

A A A A A A A A A SEGMT

66

19 18 17 16 15 14 13 12 11 STRT

67

ESO

68

CYRM30.HEX

69

ESI

0

70

ES2

71

ES3

72

0

1

N X 0

0

0

N

1

N N X 0

0

1

N

0

1

N N X 0

1

0

N

0

1

N N X 0

1

1

N

ES4

0

1

N N X 1

0

0

N

73

ES5

0

1

N N X 1

0

1

N

74

ES6

0

1

N N X 1

1

0

N

75

ES7

0

1

N N X

1

1

1

N

76

RSO

1

0

N N X X

1

1

0

77

CSP

1

0

N N X X 0

0

0

N

SEGMT

EPROM

EPROM

STOP

START

STOP

0

File Name

fff

78
79
80

******************************

81

****************************************

END

---------------------------------------,JrArJl:~---------------------------------------.....

1-199

PSD3XX - Application Note 024

____________________________
1-200

',Ir.,~

'rlNl1if ~

___________________________

iFEE :='=
-----==
=:""ii-iii=!ii-3ii-=

--

..."

----

~~

Programmable Peripheral
Application Note 025
Interfacing The PSD3XX To The NEURONqp
3150™CHIP
By Dan J. Friedman, WlI and RtIZII S. Ra/I, Echllion Corporation

Introduction

Interfacing the PSD3XX to the NEURON
3150 CHIP can increase the capability of
the NEURON 3150 CHIP without
significantly increasing the board space
and power consumption. The PSD3XX
enhances the capabilities of the NEURON
3150 CHIP by increasing both its I/O
capability and memory capability. By using
the PSD3XX, the I/O port capability can be
expanded from 11 to 21 I/O ports. This two
chip solution will also give the user
up to 128K bytes of EPROM with built-in
paging logic, 2K bytes of SRAM, and
programmable logic for address decoding
and integration of any glue logic. This
application note describes the process of
interfacing the PSD3XX to the NEURON
3150 CHIP.

The Series 100 operates industry standard
I/O modules and mounting racks. Unlike
previous generations of master/slave
control systems, the controller operates
either as a stand-alone or in a parallel,
peer-to-peer network. This allows each
board to perform a number of difficult tasks
autonomously, while still coordinating with
the rest of the system.
Since the Echelon LONWORKS™ network
uses a high performance peer-to-peer
protocol, there is no host necessary.
Each controller can communicate with any
others within the same network. Many
networks can be linked to other networks
through a router.

The two chip solution discussed in this
application note was implemented into a
Series 100 Distributed Intelligence
Controller developed by DMS Systems.
Figure 1 shows a picture of the Series 100
board containing the PSD312 and the
NEURON 3150 CHIP.

Figure 1.
SBlies 100
Distributed
Intelligence
Controller
(Courtesy of
DMS Systems)

1-201

PSD3XX - ApplicatlDn NDts 025

A Typical
NEURON 3150
CHIP Design

Figure 2 shows a typical NEURON 3150
CHIP node design before and after the use
of a PSD3XX. The Before design includes
an EPROM, SRAM, decoder to generate
external chip selects, and an I/O port. For
applications where space is critical, this
implementation may be unacceptable. In
the NEURON 3150 CHIP, memory

Figure 2.
Before and
After
Interfacing
to the WSI
PSD3XX

Without PSD3XX

locations EBOO through FFFF are reserved
for internal use. All external memory must
be mapped from 0000 to E7FF. In order to
take advantage of the full memory space,
an external address decoder to lhe external
memory devices must be incorporated. The
After drawing shows a simpler smaller
design.

ADDRESS

J
NEURON
3150

EPROM

CHIP

SRAM

es

es

I

DATA

.....

PLD

I-

I/O

~ r- es

-

I/O

es

WithPSD3XX

1/0
LINES

NEURON
3150
CHIP

PSD3XX

-1-~-02--------------------------------~~~-----------------------------------

PSD3XX - Application lIot. 025

NEURON 3150
CHIP and the
Exte,nal

Memo"

Interlace

The NEURON 3150 CHIP provides an
external memory bus to permit expansion of
memory up to 5BK bytes beyond the 512
bytes of EEPROM and 2K bytes of RAM
resident on the chip. The NEURON 3150
CHIP requires 16K bytes of external
non-volatile memory to store its firmware.
The remaining 42K bytes of extemal
memory are available for user application
program and data.

Assessing MemDlY Requirements
LONWORKSTM nodes based on the
NEURON 3150 CHIP use a combination of
three different types of memory:
Q Non-Volatile Memory for NEURON CHIP

Firmware and, optionally, Application
Code.
Q Electrically Rewriteable Non-Volatile

Memory for Network and Application
Code and Data.
Q Read/Write Memory for Packet Buffering,

or, optionally, Application Code and
Data.
A LONWORKS application node may
include the external memory types
described above by partitioning the
available 5BK byte memory space into three
distinct regions aligned on 256-byte page
boundaries. The different memory types do
not need to map to contiguous address
space. However, the LONBUILDER™
NEURON C compiler enforces the ordering
of the types of memory to be ROM/EPROM
first, EEPROM second, and finally RAM.
The NEURON C compiler and
LON BUILDER linker locate parts of an
application in appropriate memory regions
(see Chapter 6 of the NEURON C
Programmer's Guide)

MemDry Interface Logical DeSCliptiDR
Figure 3 shows the memory map of the
NEURON 3150 CHIP. Memory locations
from 0 to E7FF are external to the
NEURON 3150 CHIP. Access to this
memory is through an external memory
bus consisting of eight bi-directional
three-state data lines, 16 unidirectional
address lines driven by the NEURON 3150
CHIP, and two control lines.
The two control lines used for the external
memory interface are:

E-

Enable Clock

This output is a strobe driven by the
NEURON 3150 CHIP to synchronize the
external bus. Its frequency is one-half that
of the input clock or crystal. E is low
during the second half of the memory
cycle, which indicates that the NEURON
3150 CHIP is actively reading or writing
data. During write cycles, the NEURON
3150 CHIP drives the new data onto the
data bus during the time E is low. During
read cycles, the NEURON 3150 CHIP
clocks in the external data on the
transition of E.

RIW - Read/Write
This output indicates the direction of the
data bus. It is set by the NEURON 3150
CHIP to high during a Read cycle, and
low on a Write cycle. R/W changes state
during the time E is high, and is stable
during the time E is low.
See the section on Special Timing
Considerations for more information on the
NEURON 3150 CHIP memory interface
requirements.

----------------------------------,Arjr~jr---------------------------------t6f!i11.t

-~------ ----~-

~---------

.-- _.

-- -- --------

1-203

PSD3XX - Application Note 025

Figure 3.
The NEURON
3150 CHIP
Memory
Map

FFFF

1K MEMORY-MAPPED
1/0 AND RESERVED SPACE
FCOO
FBFF

----r

2.SK RESERVED

F200
F1FF

INTERNAL
O.SK EEPROM

FOOO
EFFF
2KRAM

E800
E7FF
42K MEMORY SPACE
AVAILABLE FOR
APPLICATION USE

4000

j

---r
EXTERNAL

3FFF
16K NEURON CHIP
FIRMWARE &
RESERVED SPACE

0000

PSD3XX
Architecture

The PSD3XX integrates high performance
user-configurable blocks of EPROM,
SRAM, and programmable logic technology
to provide a single chip microcontroller
interface. The major functional blocks as
shown in Figure 4 include two
programmable logic arrays, Programmable
Address Decoder (PAD A and PAD B),
256K bits to 1M bits of EPROM, 16K bits of
SRAM, input latches, and output ports.
The PSD3XX is ideal for applications
requiring high performance, low power, and
very small form factors.
The PSD3XX offers a unique single-chip
solution for users of the NEURON 3150
CHIP that need more memory-mapped I/O,
larger EPROM and SRAM size, external
chip selects, and programmable logic.
Table 1 summarizes the PSD3XX devices
that can interface to the NEURON 3150
CHIP. The PSD3XXL devices can operate
down to 3.0 V for low power applications.

As shown in Figure 5, WSI's PSD3XX can
efficiently interface with, and enhance, the
NEURON 3150 CHIP. This is the first
solution that provides the NEURON 3150
CHIP with port expansion, page logic,
two programmable logic arrays (PAD A and
PAD B), 256K bits to 1M bits of EPROM,
and 16K bits of SRAM on a single chip.
The PSD3XX does not require any glue
logic for interfacing to the NEURON 3150
CHIP.
The PSD3XX on-chip PAD A enables the
user to map the I/O ports, eight segments
of EPROM (8K x 8 each) and SRAM
(2K x 8) anywhere in the address space of
the NEURON 3150 CHIP. PAD B can
implement up to 4 sum-of-product
expressions based on address inputs,
control signals, and other external input
signals.

-----------------------------------fjfjf~~--------------

1-204

:i:JiFs

---L

_____________________

PSOSXX - Application Nottl 025

Figure 4.

PS03XX

Architecture

, ff
PAGE LOGIC

P3-PO

-

A11-A15
L
A
T
C
H

AD6-AD15

A6-A10
A19/CSI
ALE/AS

A16-A18

CSIOPORT
A19/CSI

RD

~

WR

13P.T.

RESET
ALE/AS

PADS

RD

WR

PROG
PORT
EXP
PCO-

ALE/AS

PAD A

-

r--

,!

LOGIC IN

27 P.T.

RESET

PORT
C

~

CS8CS10

.. -- - - -

'--

L
A
T
C
H

ADO-AD7

- -

-

..

ES7
ES6
ES5
ES4
ES3

~
ES1
~

-

CSOCS7

~

--

RESET

R/W

R/W

I

PBO-PB7

RESET

.
III

ALE

OS

E

I

J

PC1-PC2
PCO
A19/CSI

8

;

".
2

) ~.

I---

rl-

Integrating the PSD312 to the NEURON 3150 CHIP adds:
• 10 Chip Selects or Data I/O Ports (in addition to the 11 I/O on the 3150).
• 64K bytes of EPROM (expandable to 128K bytes).
• 2K bytes of SRAM.
• All Decode Logic for External Chip Selects and Internal Memory.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FES gi!#

1-206

~S1~§------------------------------

PSD3XX - Application Nots 025

PSD3XX
Architecture
(Cont.)

Figure 6.
PSD3XX
PAD
Description

PAD B can be used to extend the decoding
to select external devices or as a random
logic replacement. The input bus to both
PAD A and PAD B is the same. Using WSI's
MAPLE software, each programmable bit in
the PAD's array can have one of three logic
states of 0, 1, and don't care (X). In a user's
logic design, both PADs can share the same
inputs using the X for input signals that are
not supposed to affect other functions. The
PADs use reprogram mabie CMOS EPROM
technology and can be programmed
and erased by the user. Figure 6 shows the
PSD3XX PAD description.

~
~
P,

Port Functions
The PSD3XX has three 1/0 ports (Port A,
B, and C) that are configurable at the bit
level.

Port A - When interfacing to the NEURON
3150 CHIP, Port A is used for the lower
order data bus.

ESO
ESI
ES2

~

ES3
ES4

Po

v
ALEorAS

~

v

A

ES7
RSO-S RAM BLOCK SELECT
~

CSIOPORT CSADIN

orRiW

v

PAD

ES5
ES6

~

DorE

v

8 EPROM BLOCK

S ELECT LINES

~

'5
CSADOUT1
CSADOUT2

A19

}

I/O BASE ADDRESS

TRACK MODE
CONTROL SIGNALS

CSOIPBO
AIS

v

CS1/PBl

A17

v

-

A16

v

CS3IPB3

A15

v
A14

CS2IPB2

~

CS4/PB4
~

CSSIPB5
A13

... ~

A12

PAD
B

CSSIPB6

~

...
All

2
roc

CS7IPB7

css/pco
CSI

•

CS9IPCl

RESET •
CS101PC2

NOTES: 1. eSI is a power-down signal. When high, the PAD is in stand-by mode and all its outputs become
non-active.
2. RESET deselects all PAD output sigals
_ _ __
_
3. A1a, A17, and A16 are internally multiplexed with eS10, eS9, and esa, respectively. Either A18 or
es 10, A 17 or eS9, and A 16 or eS8 can be routed to the external pins of Port e. Port e can be
configured as either input or output.

----------------------~~~---------------------1-207

PSD3XX - AppllDBtJon lID", D25

PSDaxx
ArohltBcture
(Cont.)

Port B - The default configuration of Port B
is 1/0. In this mode, every pin can be set as

an input or output by writing into the
respective pin's direction flip flop FF, in
Figure 7). As an output, the pin level can be
controlled by writing into the respective pin's
data flip flop (DFF, in Figure 7). When DIR
FF =1, the pin is configured as an output.
When DIR FF =0, the pin is configured as
an input. The controller can read the
DIR FF bits by accessing the READ DIR
register; it can read the DFF bits by
accessing the READ DATA register. Port B
pin level can be read by accessing the
READ PIN register. Individual pins can be
configured as CMOS or open drain outputs.
Open drain pins require external pull-up
resistors. For addressing information, refer
to Table 2.
Alternatively, each bit of Port B can be
configured to provide a chip-select output
~al from PAD B, PBO - PB7 can provide
CSO - CS7, respectively. Each of the signals
CSO - CS3 is comprised of four product
terms. Thus, up to four ANDed expressions
can be ORed while deriving ~of these
signals. Each of the signals CS4 - CS7 is
comprised of two product terms. Thus, up to
two ANDed expressions can be ORed while
deriving any of these signals.

Figure 1
PortB

Pin Structure

Accessing the VO Port - Table 2 shows
the offset values with the respect to the
base address defined by the CSIOPORT.
They let the user access the corresponding
registers.
Port C in all Modes - Each pin of Port C
(shown in Figure 8) can be configured as
an inpVt to PAD A and PAD B or output
from PAD B. As inputs, the pins are named
A16-A18. Although the pins are given
names of the high-order address bus, they
can be used for any other address lines or
logic inputs to PAD A and PAD B. For
example, A8-A10 can also be connected to
those pins, improving the boundaries of
CSO - CS7 resolution to 256 bytes. As
inputs, they can be individually configured
to be logic or address inputs. A logic input
uses the PAD only for Boolean equations
that are implemented in any or all of the
CSO - CS10 PAD B outputs. Port C
addresses can be programmed to latch the
inputs by the trailing edge ALE or to be
transparent.

Alternatively, PCO-PC2 can become
CS8 - CS10 outputs, respectively,
providing the user with more external chipselect PAD outputs. Each of the signals
CS8 - CS10 is comprised of one product
term.
READ PIN

I
N
T
E
R
N
A
L

I
N
T
E
R
N
A
L

C
S
0
U
T

0
A
T
A

B
U
S

C
S
0

WRITE DATA

CK
0

OUT

R
DI

B
U
S

MUX

CSi

0
8

READDIR

o
1
7

5

WRITEDIR

CONTROL

RESET

NOTE: 4. CMOs/OD determines whether the output Is open drain or CMOS.

~1-~~~8----------------------~~/-------------------------

PSD3XX - Application Nots 025

Tab/e2.
//0 Port
Addresses in
an 8-bit Data
Bus Mode

Byte Size Access of the I/O Port Registers
Offset from the CSIOPORT

Register Name
Pin Register of Port A

+ 2 (accessible during read operation only)

Direction Register of Port A

+4

Data Register of Port A

+6

Pin Register of Port B

+ 3 (accessible during read operation only)

Direction Register of Port B

+5

Data Register of Port B

+7

Figure 8.
porte
Structure

I I
CAD
LOGO
CONF.
BIT

-D

ADDRESS INDICATOR

JJ
PCO

(NOTES)

J ADDRESS I

L

,I

i ..

LATCH

I

CSB (OUTPUT LINE)

I I
CPCFO
CONF.
BIT

I

CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL

AI6
TO PAD

FROM PAD

CADLOGI
CONF.
BIT

1

I

l)-

I

D-

ALE

-

t t
I ADDRESS I

I

PCI /.

LATCH

I

.. CS9 (OUTPUT LlNEl

I I
CPCFI
CONF.
BIT

I

FROM PAD

CADLOG2
CONF. 1
BIT

t t
J ADDRESS I
PC2 /.

AI7
TO PAD

I

LATCH

! .. CSIO (OUTPUT LINEl

I

I
AlB
TO PAD

FROM PAD
TO
EPROM

NOTE: 5. The CADDHLT configuration bit determines if AlB - AI6 are transparent via the latch, or if they must be
latched by the trailing edge of the ALE strobe.

"I=s=~
-----------------------------------~sfl-----------------------------------

1-209

PSD3XX - Application Note 025

PSD3XX

EPROM

Architecture
(Cont.)

The PS03XX has 256K bits to 1M bits of
EPROM and is organized from 32K x 8 to
128K x 8. The EPROM has 8 banks
of memory. Each bank can be placed in
any address location by programming the
PAO. BankO-Sank? can be selected by
PAO outputs ESO-ES?, respectively. The
EPROM banks are organized from 4K x 8
to 16K x 8.

SRAM
The PS03XX has 16K bits of SRAM and is
organized as 2K x 8. The SRAM is
selected by the RSO output of the PAO.

Control Signals
Th~PS03XX

control signals are WR or
RIW, RO/E/OS, ALE, PSEN, RESET, and
A 19/CSI. Each of these signals can be
configured to meet the output control signal
requirements of the NEURON 3150 CHIP.

WR Of R/W - The WR or RIW pin is
configured as RIW. Thi~in works with t~
OS strobe of the RO/E/OS pin. When RIW
is high, an active low signal on the OS pin
performs a read operation. When RIW is
low, an active low signal on the OS pin
performs a write operation.

RD/E/DS - The RO/E/OS pin is configured
as OS. This pin works with the RIW signal
as an active low data strobe signal. As OS,
the RIW defines the mode of operation
(Read or Write). The OS feature is not
available on the PS0311 and PS0301.
The E input must be used. To generate to
correct polarity, an external inverter must
be used. To minimize board space and to
meet critical timing requirements, it is
recommended to use the PSD312 or
PSD313 with the NEURON 3150 CHIP.

PSEN - The PSEN signal is not used with
the NEURON 3150 CHIP and therefore
must be connected to Vcc'
RESET - This is an asynchronous input
pin that clears and initializes the
PS03XXl3XXL. On the PS03XX, reset
polarity is programmable (active low or
active high). Whenever the PS03XX reset
input is driven active for at least 100 ns, the
chip is reset. On the PS03XXL, reset is a
low signal only. This device is reset and
operational only after the reset input is
driven low for at least 500 ns followed by
another 500 ns period after the reset
becomes high. In either device, the part is
not automatically reset internally during
boot-up and an external reset procedure is
recommended for best results. Tables 3
and 4 indicate the state of the part during
and after reset.

A19/CSI - When configured as CSI, a high
on this pin deselects and powers down the
chip. A low on this pin puts the chip in
normal operational mode. For PS03XX
states during the power-down mode, see
Tables 5, 6, and Figure 9. The contents of
the SRAM is preserved during the
power-down mode. There is an Application
Note on the Power-Oown Mode in the
Programmable Peripherals Oesign and
Applications Handbook from WSI.
In A19 mode, the pin is an additional input
to the PAO. It can be used as an address
line or as a general-purpose logic input.
A 19 can be configured as ALE dependent
or as transparent input. In this mode, the
chip is always enabled.

ALE - To prevent a timing violation with the
Address Hold time, the ALE input pin is
used to latch the address into the PSD3XX.
As shown in Figure 5, PCO output signal
from Port C on the PS03XX is connected
to the ALE input to the PS03XX. The PCO
output signal is a delayed version of the E
signal from the NEURON 3150 CHIP.
Further information on this special timing
condition is discussed after Figure 10.

-----------------------------------~~~~----------------------------------1·210

PS03XX - Application Note 025

Table 3.
Signal States
During and Aner
Reset

Signal
All

Input

A8-A15

All

Input

PAO-PA7)
(Port A

I/O
Tracking ADO/AO-AD7
Address outputs AD-A7

Input
Input
Low

110
CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Input
High
Tri-stated

Address inputs A 16-A 18
CS8-CS10 CMOS outputs

Input
High

PBO-PB7
(Port B)
PCD-PC2
(Port C)

Table 4.
Internal States
During and Aner
Reset

Condition

Configuration Mode

ADO/AD-AD7/A7

Signals

Component

PAD

Data register A
Direction register A
Data register B
Direction register B

Contents

CSO-CS10

All = 1 (Note 13)

CSADIN, CSADOUT1,
CSADOUT2, CSIOPORT,
RSO, ESO - ES7

All = 0 (Note 13)

n/a
n/a
n/a
n/a

0
0
0
0

NOTE: 13. All PAD outputs are in a non-active state.

TableS.
Signal States
During
Power-Down
Mode

Table 6.
Internal States
During Power
Down

Configuration Mode

Signal

Condition

ADO/AD-AD7/A7

All

Input

A8-A15

All

Input

PAO-PA7)

I/O
Tracking ADO/AD-AD7
Address outputs AO-A7

Unchanged
Input
A1l1's

PBD-PB7

I/O
CS7-CSO CMOS outputs
CS7-CSO open drain outputs

Unchanged
A1l1's
Tri-stated

PCO-PC2

Address inputs A 16-A 18
CS8-CS10 CMOS outputs

Input
A1l1's

Component

PAD

Data register A
Direction register A
Data register B
Direction register B

Signals

Contents

CSO-CS10

All 1 's (deselected)

CSADIN, CSADOUT1 ,
CSADOUT2, CSIOPORT,
RSO, ESO - ES7

All O's (deselected)

n/a
n/a
n/a
n/a

All
Unchanged

________________________________ f::=E ________________________________
=-~~=

1-211

PSD3XX - Application Note 025

Figure 9.
A19/CSI

ADDRESS INDICATOR
TO EPROM

Cell
Structure
CADDHLT
CONFIGURATION
BIT: LATCH OR
TRANSPARENT
CONTROL
ALE - - - - - - - - - - - - ,
A19
1------.. TO
PAD

A19/CSI ------e

£!

~_-"""'-"-"'-'-'-:!..!..:CS5
ALE-AS c::::::::.....-------4----------I

Figure 6. PAD Conllerslon Multl·Lellel Logic Network
A16

CSO

J:
J:

I

A17

I

AlB

J:
A19

I

"'S

....-

t- -LI

CSl

1

J:

I
J:
ALE-AS

1

-

CS5

---------------------------~Jr;r-------------------------1·231

I'SD3XX - Applltllltltln Ntlt. 027

AppendlxA.
I'SD312
Configuration

********************** MAPLE 5.00 ***************************
PSD PART USED: PSD312
********************PROJECT INFORMATION**********************
Project Name
PAD Logic Reduction
Don Buccini
Your Name
March 31, 1993
Date
Host Processor:
8-Bit Non-Mux'd Bus
*************************************************************
********************ALIASES**********************************
*************************************************************

*********************GLOBAL CONFIGURATION********************
Address/Data Mode:
NM
Data Bus Size
8
Reset Polarity:
LO
Security
OFF
AS Polarity
LO
A15-AO AS dependent (Y) or Transparent (N) : N
Are you using PSEN ? (Y/N)
N
*************************************************************

********************READ WRITE CONTROL***********************
R/ (/W) and E
*************************************************************

*******************Port A Configuration *********************
Port A is Data Bus DO-D7.

________________________________________________

1-232

PaFaF~&f

~~~~---------------------------------------------

I'SD3XX - Application

AppBndlxA.
I'SD312
CDnllguratlDn
(C""t.)

********************PORT B
Pin

CS/IO

CMOS/OD

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

CSO
CSl
IO
IO
CS4
CSS

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

IO

IO

.IIt.

027

CONFIGURATION********************

*************************************************************

****************PORT B CHIP SELECT EQUATIONS*****************
/CSO =
/ (A16
+ /A19 * /A18 * / AS
+ A19 * /A17

ICSl
/

(/A16

+ /A19 * A18 * I AS
+ A17 * AS

ICS4
/ (A19 * /A18
+ /A19 * A18

ICSS
I

(A18 * / AS
AS

+ /A18 *

********************PORT C CONFIGURATION*********************
Pin

CS/Ai

PCO
PCl
PC2
A19

A16
A17
A18
A19

LOGIC/ADDR
LOGIC
LOGIC
LOGIC
LOGIC

*************************************************************

******************PORT C CHIP SELECT EQUATIONS***************

---------------------------~~Ar------------------------1-~--~

PSD3XX - Application Nots 027

AppendixA.
PS0312
Configuration
(Cont.)
**********************************ADDRESS MAP*********************************

A A A A A A A A A SEGMT SEGMT FILE
19 18 17 16 15 14 13 12 11 STRT
STOP STRT
ESO
ESI
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

X
X
X
X
X

a

X
X
X
X
X

X
X
X
X
X

X
X
X
X
X

0
0
0
1

0
0
1
1
0

0
1
0
1
0

X
X

X X X
X X X

1
1

1
1

0
0

N
N
N
N
N
N
N
N
0
1

N
N
N
N
N
N
N
N
0
0

FILE
STOP

File Name

0000
2000
4000

IFFF
3FFF
5FFF

NON_MUX.TXT
NON_MUX.TXT
NON_MUX.TXT

N/A
N/A

N/A
N/A

N/A
N/A

Page Reg Q.F
3210
AS

**************************************END*************************************

****************************ADDRESS MAP (EQUATIONS)***************************
ESO

IA15 * IA14 * IA13

ESI

IA15 * IA14 * A13

ES2

IA15 * A14 * IA13

ES3

IA15 * A14 * A13

ES4

A15 * IA14

RSO

A15 * A14 * IA13

CSP

A15 * A14 * IA13 * A12 * IAll

* IA13
* IA12

* IAll

******************************************************************************

_________________________________________

1-234

Fjf~aF~

~~~----------------------------------------

PSD3XX - Application Nol. 027

AppendixA.

P6D312
Configuration
(ConI.)

**********************CONFIGURATIONBITS**********************
CDATA=
0
CADDRDAT
0
CA19/ (/CSI) = 1

CALE =

1

CRESET=

0

(/COMB) /SEP) = 0

CPAF2=

0

CADDHLT=

0

CSECURITY=

0

CLOT=

0

CRRWR=

1

CEDS=

0

CADLOG19=

0

CPAF1[O]=

1

CPACOD[O] =

0

CPAF1[1]=

1

CPACOD[l] =

0

CPAF1[2]=

1

CPACOD[2]=

0

CPAF1[3]=

1

CPACOD[3]=

0

CPAF1[4]=

1

CPACOD[4] =

0

CPAF1[5]=

1

CPACOD[5] =

0

CPAF1[6]=

1

CPACOD[6] =

0

CPAF1[7]=

1

CPACOD[7]=

0

CPBF[O]=

0

CPBCOD[O]=

0

CPBF[l]=

0

CPBCOD[l]=

0

CPBF[2]=

1

CPBCOD[2]=

0

CPBF[3]=

1

CPBCOD[3]=

0

CPBF[4]=

0

CPBCOD[4] =

0

CPBF[5]=

0

CPBCOD[5]=

0

CPBF[6]=

1

CPBCOD[6]=

0

CPBF[7]=

1

CPBCOD[7]=

0

CPCF[O]=

0

CPCF[l] =

0

CPCF[2]=

0

CADLOG[O] =

0

CADLOG[l]

0

CADLOG[2] =

0

--------------------------~Jr!------------------------1·235
-----

.--~--~.----

.-

-

_...

PSD3XX - Application Note 027

Conclusion

The versatility of the PSD3XX PAD in replacing severallCs in a multi-level logic network
becomes more apparent as the designer applies it to his/her specific application.
Its simplicity negates the need for design entry tools. It is also possible to use one or more
of PAD inputs A 11 - A 15 as logic inputs if they are not used for address lines in systems
requiring 32K bytes or less of memory. The functionality of the PAD will be greatly
expanded as the PSD family of future devices grows.

-1--2-3-6---------------------------------~~~~-------------------------------------

!FEE=:=
----- -r'--~

-

_
_ _
~

--------~~

Programmable Peripheral
Application Note 032
Use AROM Emulator For Rapid Software
Debug Of A PSD3XX-'ased DeSign
By Don 'ucdnl

Intloduction

EPROM Emulation has become a relatively easy and inexpensive method to software
debug a small to medium size microcontroller system which uses external EPROMs.
The EPROM is removed from its socket and the RAM-based Emulator is plugged into the
socket, allowing rapid on-line changes and verification of program code. The PSD3XX
family incorporates EPROM, SRAM, I/O Ports and PLD logic into a single package whose
pinouts differ from conventional EPROMs, preventing direct access to the program code.
This Application Note describes an effective way to gain direct access to the on-chip
EPROM without the need for special circuitry on the system circuit board, using any
commercially available ROM Emulator. This allows quick software debug of the system
under test by running the program in RAM and enabling rapid code changes via the
keyboard of a PC. The remaining functions configured in the PSD3XX - SRAM, I/O, Chip
Selects, etc. - are transparent to the emulator and unaffected by its use. Familiarity with
the PSD3XX Architecture and the MAPLE software is assumed.

Design
Philosophy

The design philosop~ is straightforward - gain access to the required interlace signals
(AO - A15, DO - 07, R, W, E, ALE/AS, etc.) between the selected microcontroller and the
PSD3XX, bypass the EPROM chip selects on the system PSD3XX and program a second
PSD3XX (Emulator PSD3XX) to access the ROM Emulator memory being used to run the
program code. The recent availability of specialized test socket adapters such as
Emulation Technology's Bug Katcher (P/N BC 4-44-PCC3-0000), shown in Figure 1, allows
easy access to these interlace signals without modifying the design of the system circuit
board.
The system PSD3XX is removed from its socket and the test adapter is inserted between
the socket and the System PSD3XX. A short cable is connected between the interlace pins
of the adapter and a small printed circuit adapter board which contains the second PSD3XX
and an EPROM socket(s). This board can be designed for both an a-bit and 16-bit data
bus, although more complex 16-bit designs would most probably use an In-Circuit Emulator
for debugging.
The following design procedure uses some of the more popular microcontrollers for
ill ustration:
1. Design The ROM Emulator Adapter Board.
1) a-Bit Multiplexed Address/Data Bus ... Figure 2 shows an Interlace Diagram for the two
components necessary for this bus interlace - the Simulator PSD3XX and a 32-pin
JEDEC EPROM socket. Port A is used to latch the low order address byte from the
microcontroller. PB7 is used as address line A16 to the EPROM Socket, utilizing the
Page Register logic of the PSD3X2 and PSD3X3 for memory page switching. PB6 is
used to generate the RD signal which is converted to the OE pin of the EPROM.
This same schematic can be used for the 80C31 family by making the following
changes to the PSD3XX interlace signals:
• Change E to RD
• Change AS to ALE
• Disconnect BHEIPSEN from Vee and connect to PSEN

1-237

PSD3XX - Application Not. 032

Design
Philosophy
(Cont.)

2) 16-Bit Multiplexed Address/Data Bus ... (see Figure 3) for this application, an additional
74HC373/S73 latch is required to latch the high order address byte from the
microcontroller. Two EPROM sockets are shown, although one socket could be used
if the Emulator can plug into a 64K x 16 socket.
3) a-Bit Separate Address and Data Bus ... Figure 4 is an Interface Diagram similar to
Figure 2, except that Port A is not needed to separate the Address and Data Buses.
2. Configure all the parameters on the system PSD3XX except the a internal EPROM
Chip Selects (ESC - ES7). These remain inactive and will be emulated by the Emulator
PSD3XX. The level of integration and ease of programming of the PSD3XX allow these
temporary configuraton changes that are necessary to use ROM Emulation without
impacting the existing system hardware design.
3. In the Emulator PSD3XX, configure the eight product terms of Port B pins C and 1
(00 configuration) to correspond to the internal Chip Select (ESC - ES7) addresses of
the EPROM memory map of the System PSD3XX selected by the system software.
This is the combined Chip Select signal to the external memory socket and divides the
external emulation memory into eight independent blocks identical to the PSD3XX.
The three Port C pins are configured for the Memory and I/O signals required by the
specific Microcontroller. All other configuration parameters remain inactive.
In summary, the main function of the ROM Simulator Adapter Board is to allow the use of a
ROM Simulator without any board modification, divide the external memory into eight
blocks identical to the PSD3XX internal EPROM, and enable all other functions of the
System PSD3XX to operate in a normal mode.

Figure 1. Bug Katcher TM

-

PLCC

-------------------------------------rJrAr~~------------------------------------1-238
====

Figure 2. Interface Diagram - 8-Bit Multiplexed Address/Data Bus
~ INTERFACE CABLE

I "'----" r

I

:1

Vee
r

18pF

rt

lXl

c:::J

U1

8MHz

-:f-8

~

18pF

PD3
PD4
P05

4
25

.-==-

43
45
47

~
PEl
PE2

lit....
IIIIt
11 111•

II~~

II.I"~

~

PE3

44

PE4

46

PEG

50

PE5~

~

'ee
r

~

:

PA2
PAS
PA4

31
30
29

PAS
PAS

28
27

PAl

~R2
lK

32

~
'2
51

PCO
PC1
PC2
PC3
PC4
PC,
PC6
PC7

XTAL
XTAL

PDO
PD1
PD2
PD3
PD4
PD5

PBO
PBl
PB2
PB3
PB4
PB'
PBS
PB7

PEO
PEl
PE2
PEO
PE4
PE5
PEe
PE7

E

PAD
PAl
PA2
PAS
PM
PAS
PAS
PA7

R/W

AS
RESET
lORO

iRQ
MOOB
MOCA

VAH
IIRL

8

23
24
2'
26
27
28
2.
30

•

10
11
12
13
14
15
16
17
18
I.
20

31
32
33

22
23

Vee I-

~

ADa/AS
AD9/A9
AD1D/Ale

PBO
PBl
PB2

21
20
I.
I.

17
16
15
14

.

~

2

r

VDD

A16/CS8
A17/CS9

r

3

RESET

PSD3XX

::~ J-~

A18/CS10
A19/cst

~

co

-=

V

CC~

PB7

~

T

--

I
I
I
I

~
43

~

-=

I

22

I
I
I
I
I
I
I
I
I
I

T
]:7 ]:7 ]:7

1
RESET

1\.........

GND

1

SYSTEM BOARD

~

~

-2..

4K7
PAO
PAl
PA>
PM
PA4
PA'
PA6
PA7

ADO/AD

AD1/Ai
AD2/A2
AD3/AS

AD4/M
ADS/AS

ADS/A6
AD7/A7

PBO
PBl
PB2
PB3
PB4
PB'
PB6
PB7

ADa/AS
AD9/A9
AD10/A1D

Am1/All
AIJ121A12
AD13/A13
AD14/A14
AD1s/A15

E

~

RlW/VPP
BHE/PSEN

AS
RESET

21

20
I.
I.

17
16
15
14
11

~>-

•
;t:
~

A18/CS10

~

A19/CS1

p!-

-=

AD
A1

oao

A2
A3
M
A5
A6
A7

002
003

~
~
~
~

q
40

12
11

10
•
8
7
6
5

~

~
+-

A161Csa
A171CS9

PSD3XX

~

J:7

31

~
AD12 36
~
AD14 38

I

3

-

~

E

~R1
~ 4K7

U3

PB1

R/W/vPP

68HC11

Vee

l\..A08

PB2

18pF

=-

PBO

4

AS

I~

~

11
10

PB7

BHE/PSEN

~
~
~

:~
PAS

39

-Ta-

~
AD3 26

PA>
PA3

::! ~

AD15/A15

~~ ~!

~
PAl

~~/~~~
~~ :~!~~~!
2~

5
6

17

PAO
PAl
PA>
PA3
PM
PA'
PA6
PA7

36

21

4

AD2/A2
AD3/AS
AD4/A4
ADS/AS
ADS/A6
NJ7/A7

ADO/AO
AD1/A1

R1

U2

U2

~2

I

22
24

DQ1

DQ4

00'
DQ6
007

13

ADO

~

~

~
18
19

AD4 ~
ADS

~
21

AD7

A8
A.
Al0
A11
A12
A13
A14
A15
A16

CE
OE

EPROM
SOCKET

I
I

I
I
I
I
I
1 ___

;,:
2

ROM EMULATION ADAPTER BOARD

----------------------

~
I

~

:g

:;:::

&l
::::

8
I

&;'

~

...

Figure 3. Interface Diagram - 16-Bit Multiplexed Address/Data Bus

~

~

I

~ INTERFACE CABLE

--------------------------1

I

.... --- ••• : -

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

1

I

8!:t
8

Vee

1

Vee ;l;;i'0pF
_02

e'"

~

J.!!.

U1

TBM-iz
----=-

I '1' 3<\>F

12

X2

1 II r~1·6
PO.a
PO.1

&

2.-.1.

pa.GIADO
P3.1IAD1
pa 2/AD2
pa 3/AD3
P3.41AD4

Xl

:ff

t-t

10
•
9

Pa.51AD5

READY
ODE

PS.61AD6
P37/ADT

RESET

P401AD8
A41/AD9
P4.21AD10
P4.31ADf1
P44/AD12
P4.61AD13
P4.61ADt4
P4.7/AD16

AQ-IO/PO.O
Aail/PO 1
Aa-t2/PO.2
ACH3/PO 3
ACH4/PO 4
ACH5/PO.5

;

:~

NMI

BUSWlDTH

5
7

P04
P05

-= " ~:::

1

nco

q~::.1

RXD

P2.2
P2.3

11'11

P2.4
P2.S
P2.

~

=4

:'~4

2

P21/RXD
P2 2/EXIN'T
P2 3/T2CLK

WHE/BHE
ADVIAUE
ItI.IST
a..KOUT

P2.4/T2RBT

HS3l5~

....!!.

~

P2.0/TXD

17
15
44
42
39
33
38

HSI.O

PI

a

P261PWM

Pl1

P2.6/T2UP-[)N
P2.7/T2CAPruRE

PI 2
PI 3

HSI.O
HSl1
HSl21HSO.4
HSl3/HSO 5

PI 4
PIS
PI 6
PI 7

VREF

~
...!.

ANGND
EA

HSOO
HS01
HSO •
HS03

/.

60
5.
5.
57

U2

23
24
26
2B

AD6IAS
NJ8/M

52/.31:::
61
50

32
33

ADtOlA10

49

35

ADt1/A11

N)gJAQ

AD131A13
AD14/A14

AD151A15
22 ii)
2WFi
BHEJPSEN
13
ALE

't.,-L

62

~

rJ!L-

E

Pl

..

fa4

PA37

PBO
P61

0

P64.
P64.1
P64.2

20
19
18

PAD 121
PA1

PAS.O
PA3.1

::~

~:I·

PM
PAS
PM
PA7

PA3.4

PM.S
PAS.S

11~

••
•

7

PB6

14

_.3

~

-=~-'

.~

~::::t=,~~j~

A17/CS9

A1B1CS10
A191CSi

17
16
15

P64A
PB4.5

42
43

3

~ PSD3XX

FESET

~=

t I I"ICE

If"

A19/CS1
A1B/CS1...J!

.J

. .OE
._ _ _ _

PSD3XX

Pl.
Pl
PI.4
Pl5
Pl6

48
47
46

2.

RESET

21~

PAD
PA1
PA2
PM
PM
PAS
PAS
PA7

PB2
PB3
PB4
PB6

AD12/A12

81
40

!

U2

ADOIAD
AD1/A1
AD2/A2
N>3IM
N>4IM

: Y'l I I

rID

AO
A1
A2
A3
M

,

AS
A6

~

•• """S.HSO.O
34
HS01
35
HS02

............

co

2

Q1

5
6
9

co

~

Q3
Q4

80196

os
Q6
or

Vee

Vee

I

~4K7

11

A7

3
25

A12

29
3

A13
A14
A1S

24

2Fl, ~~7

74HCT373
ALE

A10
A11

28

22

U3

~
OE

EPROM
SOCKETS

RESET

3GND
~
MC34064
-- - --

I

SYSTEM

BOA!~

------

I

______ _

_.1

I;::

ROM EMULATION ADAPTER BOARD
I
- - - - - - - - - - - - - - - - - - - - - - ______ 1

Figure 4. Interface Diagram - 8-Bit Separate Address/llata Bus

..r

- --I
I

I

"

U1

1

2:.:..j7

19

M1

~~

30

23

MREQ

A2

32

25
26

RD
REFSH

AS
A6
A7
AS

~
~
~

~
~6

Ilr"1
II~IIIII

1,11111

".~

HA

~
-t-...,_____2~6!. 1
INT
NMI

17

Ii3UsRQ). 25

{8USACK 2:t
_
6
10lOK).

~!

IT

A9

WAfT

A10
A11
A12
A13

INT
NMI

~

29
30

4~

~
~
L........ff

37
38

1
2

.,

~~~ i-2--

RESET

:u~~

4

~D2~
~

us

~
0

------as
3:

14

g: ~
f{,---..;:

Vee

.,.-

AOOIAD

PAO

21

00

I

A01/A1

PA1

20

01 "

I
I

: I
:

~~:

AD4/A4
AD5/AS
AD6IA6
AD7/A7

~
~
~

PBO..J!,-rPo'
PB1
PB2
PB3

A015/A15

PB6

~~!~~~!

22

RESET

-=-

PA4
17
D4
PA5..lli.:ill[
PA6
15
D6
PA7
14
07

AD9/A9
A01O/A10
A0111A11
A012/A12

n
BQ.
~ ::'~ElPSEN
~ [~ALE
....;C7;,;.,J~

zaOB

~: ~~ ~

AD8/AS

D6

L.._ _ _

PSD3XX

~~: ~
~

~

A16/0sa
A17I0S9

~
~

A18/0510

llr0RQ,

PB7

A19/051

-

~

rl_~ND
....

.......
~

-=-

~~

~

~~! ~7
~

f
: I

I
I

:
:

•

I
I
I
I

: I
I
I
I

I
I

I
I

13

-;::J!.:

~~~~~

~51A15

:':'PSEN
RESET

:."L,.

-=-

PSD3XX

PA3
PA4
PAS
PA6
PA7

PBO
PB1
PB2
PB3

~
~

20

17
16
15

Wi ~
n4

~: I:t
ti:.

PB6

A1610sa~
PB7

A17/CS9
A18/0610

A19/CSI

41 MRE
42 10RQ

~

,,~

§t1
2

~
I-..~
~12

I-..

A10

'

4

AD

A3
A4
AS
A6
A7

AS

~~
1
~~

02 '5

03
04
05 19

06
07

02;

g'4

~ g~

05

A9
A10
A11

~~~

2
"A14
2
2
2ce
RD
24 (jE

~~~

L.._ _ _..J

EPROM
SOCKET

-=-

;:

I

I

I

.>

I

I

I
I
I

I
I

t;:

:

I

;t

Rl

;;- 4K7

Voo

t-...

PAO

~

«

U3

ADOIAO

I
A4 27
AD3/A3
: I
28
AD4/A4
I
A6 29
AD5IAS
: I
AD6IA6
I : I
AS 31
AD7/A7
I
:
A9 32
AD8/AS
0
I
AD9/AS
I
:
AD10/A10
36
0
I "A2.
AD111A11
I
: I
I
: I
AD14/A14
I
: I Vee
22
ARD
I
: I
VT iiiiR _
0

t----. ~
:~ ~
~
~
~~

AO 23 . . - - - - - - -

:

0

n

Vee

~~~ ~:0~

~
0"
~

I

: 1

-b

~..... 41<7
<>
U2

:

I

-

Vee

:

I
: I

D3

OlK

Vee

I
I
: I
I
:
I : I

U2

~~~~~~2~0~ ~~Q

-----

0

o

r ____.....:

~N~E:FACE CABLE

'. I
~ I

I

2

I

~
I

I

1

SYSTEM BOARD
~ .....

--'"

&:

ROM EMULATION ADAPTER BOARD

=
1=

il

~

PS03XX - Application Note 032

System

PSD3XX
Configuration

The Emulator functions by replacing the system's EPROM with SRAM. To accomplish this,
when the system PSD3XX is configured by the MAPLE software, ESO - ES7 are disabled to
prevent their eight respective internal EPROM blocks from attempting to access the external
Data Bus (Segment Start and Stop Columns in the Address Map are left blank). Reference
Figure 5 - PSD3XX PAD Description. Appendix A contains the generalized System
PSD3XX Configuration Printout corresponding to the Interface Diagram in Figure 2 and the
Memory Map in Figure 6 configured as an example. The Address Map is configured such
that all routines are accessible from either Page 1 or Page 2 of main memory.
Note: The Address Map in Appendix A shows ESO - ES7 active to illustrate the block
addresses which will be controlled by PBO - PB1 in the Emulator PSD3XX.
ESO - ES7 are left blank in the actual chip configuration.

FigureS.

PSD3XX
PAD
Description

~
~
,...,

P,

ES3
ES4

8 EPROM BLOCK
SELECT LINES

'S

,...,

ALEorAS

v

v

'S
CSIOPORT CSADIN

"-

l

[,."""
A19

PAD
A

ES5
ES6
ES7
RSO-S RAM BLOCK SELECT

DarE

or ANi

ESl
ES2

~

v
Po

ESO

"'S

CSAOOUTl
CSADOUT2

VO BASE ADDRESS

J

T"'~v ~no
..

CONTROLSIGNALS.

CSOIPBO
A1S

v

'S
CSlIPB1

A17
~

CS2IPB2

A16

'S
V
CS3IPB3

A15

v
CS4IPB4
A14

v
A13

,...,

CSs/PBS

B

-::..
v
CS6IPB6

A12

v
A11

PAD

'S

'S

,...,

CS7iPB7

CS8IPCO
CSI

--

~

~

CS9JPC1
CS101PC2

NOTES: 1. CSI is a power-down signal. When high, the PAD is in stand-by mode and aU its outputs become
non-active.
2. RESET deselects aU PAD output sigals
_ _ __
_
3. ~A17, and A16 are internall~ltiplexed with CS10, CS9, and CS8, respectively. Either A18 or
CS10, A17 or CS9, and A16 or CS8 can be routed to the external pins of Port C. Port C can be
configured as either input or output.

-------------------------------------'Ar;r~~-------------------------------------1-242
====

PSD3XX - Application Nots 032

Figure 6.
Memory Map
System PS0302

MAIN MEMORY
{PAGE 2)
ES7 = 64K -72K

10000
INTERRUPTS
AND SUBROUTINES
EOOO

ES6 = 56K - 64K

TABLES
ES5=48K-56K

COOO
UNUSED
BOOO
1/0 PORTS

CSP = 42K - 44K

A800
SRAM
AOOO

RSO=40K-42K
ES4 = 32K - 40K

MAIN
MEMORY
(PAGE 1)

ES3 = 24K - 32K
ES2 = 16K - 24K
ES1=8K-16K

2000
BOOT CODE
0000

Emulator
PS03XX
Configuration

ESO=OK-8K

The sole function of the Emulator PSD3XX is to access the extemal program memory
whenever the Microcontroller attempts to access the EPROM memory. The addresses of
the memory blocks corresponding to ESO - ES7 of the System PSD3XX internal EPROM
Memory Map are programmed into the Emulator PSD3XX, not as ESO - ES7, but as the
eight PAD product terms for PBO and PB1. These two outputs are configured as Open
Drain outputs and wire-or'd together into a common Chip Select to the external EPROM
socket. This feature ensures that the Emulator memory is not addressed when the internal
SRAM and I/O of the system PSD3XX are accessed. Also, this allows the Emulator SRAM
to truly emulate the EPROM of the system PSD3XX by eliminating the need for the program
code in the SRAM to be contiguous, by dividing it into eight blocks. Port A is configured to
latch the low order address byte for Microcontrollers with Multiplexed Address/Data Buses.
PCO - PC2 can be configured for specific Memory and 110 signals which may be required
by the selected Microcontroller. Appendix B contains the generalized Emulator PSD3XX
Configuration Printout.

-----------------------------------~~~--------------------------------1--2-~3-

PSD3XX - ApplicatiDn NDts 032

AppendixA.

PSO_SYS.SV1

********************** MAPLE 5.00 ***************************
PSD PART USED: PSD302
********************PROJECT INFORMATION**********************
Project Name
ROM Emulation-System PSD
Your Name
Don Buccini
Date
June 30, 1993
Host Processor:
68HCll

*************************************************************
********************ALIASES**********************************
*************************************************************

*********************GLOBAL CONFIGURATION********************
Address/Data Mode:
MX
Data Bus Size
8
Reset Polarity
LO
Security
OFF
AS Polarity
HI
Are you using PSEN ? (YIN)
N
*************************************************************

********************READ WRITE CONTROL***********************
R/ (/W) and E
*************************************************************

*******************Port A CONFIGURATION**********************
ADDRESS/IO
*************************************************************

********************PORT A (ADDRESS/IO)**********************
Pin

Ai/IO

CMOS/OD

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

IO
IO
IO
IO
IO
IO
IO
IO

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

*************************************************************

---------------------------------------------~~~--------------------------------------------1·244
====

PS03XX - Application Not, 032

AppendixA.
PSD_SYS.SV1
(Cont.)

********************PORT B CONFIGURATION*********************
Pin

CS/IO

CMOS/OD

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

10
10
10
10
10
10
10
10

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

*************************************************************

*****************PORT B CHIP SELECT EQUATIONS****************

********************PORT C CONFIGURATION*********************
Pin

CS/Ai

PCO
PCl
PC2
Al9

Al6
Al7
Al8
CSI

LOGIC/ADDR
ADDR
ADDR
ADDR
ADDR

*************************************************************

******************PORT C CHIP SELECT EQUATIONS***************

-------------------------------------~~~---------------------------------1--2-~--5

psoaxx - Application Not. 032
AppendixA.

PSD_SYS.SV1
(CDnt.)

**********************************ADDRESS MAP*********************************

A A A A A A A A A SEGMT SEGMT FILE FILE
19 18 17 16 15 14 13 12 11 STRT STOP STRT STOP
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO·
CSP

N
N
N
N
N
N
N
N
N
N

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0
0
0

0
0
0
0
1
1
1
0
1
1

0
0
1
1
0
1
1
0
0
0

0
1
0
1
0
0
1
0
1
1

N
N
N
N
N
N
N
N
0
0

N
N
N
N
N
N
N
N
0
1

0
2000
4000
6000
8000
cOOO
eOOO
0
aOOO
A800

lfff
3fff
5fff
7fff
9fff
dfff
ffff
lfff
a7ff
afff

0
2000
4000
6000
8000
0
ACOO
cOOO
N/A
N/A

1FFF
3FFF
5FFF
7FFF
9FFF
1FFF
BFFF
DFFF
N/A
N/A

File Name
SYS_PROG.OBJ
SYS_PROG.OBJ
SYS_PROG.OBJ
SYS_PROG.OBJ
SYS_PROG.OBJ
SYS_TABL.OBJ
SYS_PROG.OBJ
SYS_PROG.OBJ
N/A
N/A

Page Reg Q.F
3210
AS
0000
0000
0000
0000
0000
XXXX

0000
0001
XXXX
XXXX

N
N
N
N
N
N
N
N
N
N

**************************************END*************************************

****************************ADDRESS MAP (EQUATIONS)***************************
ESO

/A18 *
*
/A18 *
*
/A18 *
*
/A18 *
*
/A18 *
*
/A18 *

/A17
/P3 *
/A17
/P3 *
/A17
/P3 *
/A17
/P3 *
/A17
/P3 *
/A17

* /A16
/P2 *
* /A16
/P2 *
* /A16
/P2 *
* /A16
/P2 *
* /A16
/P2 *
* /A16

* /A15 * /A14 * /A13
/P1 * /PO
* /A15 * /A14 * A13
/P1 * /PO
* /A15 * A14 * /A13
/P1 * /PO
* /A15 * A14 * A13
/P1 * /PO
* A15 * /A14 * /A13
/P1 * /PO
* A15 * A14 * /A13

RSO

/A18 *
*
/A18 *
*
/A18 *

/A17
/P3 *
/A17
/P3 *
/A17

* /A16
/P2 *
* /A16
/P2 *
* /A16

* A15 * A14 * A13
/P1 * /PO
* /A15 * /A14 * /A13
/P1 * PO
* A15 * /A14 * A13 * /A12 * /A11

CSP

/A18 * /A17 * /A16 * A15 * /A14 * A13 * /A12 * All

ES1
ES2
ES3
ES4
ES5
ES6
ES7

******************************************************************************

*********************ADDRESSES OF I/O PORTS***********************************
Pin Register of Port A:
A802
Page (Binary): XXXX
Direction Register of Port A:
A804
Data Register of Port A:
A806
Pin Register of Port B:
A803
Direction Register of Port B:
A805
Data Register of Port B:
A807
Page Register:
A818

..

******************************************************************************

~~-----------------------------------~
~.-------------------------------------1·246
~I'

PSD3XX - Application .ot. 032

Appendix'.

PSD_SIM.SV1

********************** MAPLE 5.00 ***************************
PSD PART USED: PSD302
********************PROJECT INFORMATION**********************
Project Name
ROM Emulation-Emulate PSD
Don Buccini
Your Name
June 30, 1993
Date
Host Processor:
68HCll
*************************************************************

**************************ALIASES****************************
/CSO
ESO
ES3
/CS1
ES4 - ES?
/CS6
RD
/CS?
A16
*************************************************************

*********************GLOBAL CONFIGURATION********************
Address/Data Mode:
MX
Data Bus Size
8
Reset Polarity
LO
Security
OFF
AS Polarity
HI
Are you using PSEN ? (YIN)
N
*************************************************************

********************READ WRITE CONTROL***********************
R/ (/W) and E
*************************************************************

*******************PORT A CONFIGURATION**********************
ADDRESS/IO
*************************************************************

********************PORT A (ADDRESS/IO)**********************
Pin

Ai/IO

CMOS/OD

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA?

AO
Al
A2
A3

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

A4

AS
A6
A?

*************************************************************

'JlJI'~

--------------------------------~.r,-----------------------------1-~-~-7

",DlXX - Appllt:lltlon 110" 1182

Appendix'.
PSD_SIM.SV1
(Cont.)

********************PORT'B CONFIGURATION*********************
Pin

CS/IO

CMOS/OD

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

CSO
CSl
IO
IO
IO
IO
CS6
CS7

OD
OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

*************************************************************
*****************PORT B CHIP SELECT EQUATIONS****************

ESO - ES3 = /

(/A15 * /A14 * /A13 * /P3 * /P2 * /Pl * /PO

+ /A15 * /A14 * A13 * /P3 * /P2 * /Pl * /PO
+ /A15 * A14 * /A13 * /P3 * /P2 * /Pl * /PO
+ /A15 * A14 * A13 * /P3 * /P2 * /Pl * /PO
)

ES4 - ES7

/ (A15 * /A14
+ A15 * A14 *
+ A15 * A14 *
+ /A15 * /A14

* /A13 * /P3 * /P2 * /Pl * /PO
/A13
A13 * /P3 * /P2 * /Pl * /PO
* /A13 * /P3 * /P2 * /Pl * PO

)

RD
A16

=

/(E * R/W)
/ (/P3 * /P2 * /Pl * PO)

*************************************************************

********************PORT C CONFIGURATION*********************
Pin

CS/Ai

PCO
PCl
PC2
A19

A16
A17

AlB

LOGIC/ADDR
LOGIC
LOGIC
LOGIC

CSI

*************************************************************
******************PORT C CHIP SELECT EQUATIONS***************

----------------_______
1·248

rll~,.

."",11..1

_______________________

PS03XX - Application Not. 032

AppendixB.

PSD_S1M.SV1
(Cont.)
**********************************ADDRESS MAP********************************

A A A A A A A A A SEGMT SEGMT
19 18 17 16 15 14 13 12 11 STRT STOP
ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

N
N
N
N
N
N
N
N

N
N
N
N
N
N
N
N
N
N

FILE
STRT

FILE
STOP

File Name

N
N
N
N
N
N
N
N
N/A
N/A

N/A
N/A

N/A
N/A

Page Reg Q.F
3210
AS
N
N
N
N
N
N
N
N
N
N

**************************************END*************************************

****************************ADDRESS MAP (EQUATIONS)***************************
******************************************************************************

Conclusion

The PSD3XX family was conceived as a cost effective and attractive alternative to discrete
logic and memory used in designing an embedded controller system. Although the
PSD3XX offers an integrated solution, its flexibility allows the use of basic and inexpensive
development tools such as a ROM Emulator. This versatility becomes more important as
the need to rapidly develop and debug a product is realized.

Emulation Technology, Inc.
Worldwide Headquarters:
2344 Walsh Avenue, Bldg. F
Santa Clara, CA 95051-1301 U.S.A
Tel: (408) 982-0660
Fax: (408) 982-0664

Bug Katcher is a trademark of Emulation Technology, Inc.

-------------------------------------fArJr~~---------~#.

___________________________
1-249

PSD3XX - Application Nots 032

5'EESElfff
-1·-25-0----------------------------~~~~------------------------------

- - -_

F=:=:
- - - =--=:
....

..-.~

'=-~_=-i-=

----

---~

Programmable Peripheral

....=:

Application Note 040
Three-Chip Feature Phone
By Steve Torp - Motorola Semiconductor and Karen Spesard - WSI

Introduction

This application note describes how to build a programmable telephone with three
off-the-shelf integrated circuits. The feature phone includes a 16 x 2 LCD display and can
be programmed to offer many popular functions such as last- number redial, autodial by
code number, and hold.

Using The
Motorola
MC34010p,
M68HC11 DO and
WSIPSD311

The three chips used in the feature phone are the Motorola MC34010 Dialer (DTMF tone
generator with speech network and DC line voltage regulator), the Motorola M68HC11 DO
microcontroller, and the WSI PSD311 programmable MCU peripheral. Each device is
carefully chosen for a specific purpose.

The Motorola MC34010
This device is a single-chip integrated telephone circuit that also supplies a microcontroller
interface. It is this interface that enables a simplified connection to the M68HC11 DO and the
PSD311.

The Motorola MC68HC11DO
The MC68HC11 DO is an economical microcontroller with low power consumption.
The instruction set and memory map are very simple to use making the M68HC11 DO an
excellent choice for a low-cost design. The M68HC11 DO also facilitates expansion of the
feature phone in order to take advantage of new telephone services as they become
available. In this application, the MC68HC11 DO operates in expanded mode. This is
important because expanded mode supports interfacing to extemal SRAM and EPROM
devices.

The WSI PSD311
The user-configurable WSI PSD311 Programmable Microcontroller Peripheral is an integral
part of this design. The PSD311 eliminates all glue logic and reconstructs the two ports
lost by the M68HC11 DO when it is in expanded mode. The P$D311 also incorporates
32K bytes of EPROM, 2K bytes of SRAM, and preserves low power operation. With
this programmable device, the feature phone is capable of retaining the last 256 phone
numbers that were dialed, making the automatic recall of numbers effortless.
Since the M68HC11 DO does not contain a ROM, the PSD311 's EPROM will contain the
main program that will service the entire feature phone. The PSD311 will also use its port
pins to send data and control information to the Philips 16 x 2 LCD module. The PSD311 is
an excellent comprehensive choice that enables this feature phone to be comprised of only
three chips.
The design schematic is shown in Figure 1. Note how simple the design becomes with
these readily available components.

1-251

...

PIEZO SOUND B.EMENT

~

Ii!:

o

20K

I

Vee

1

t

L
-=-

f

1N760

!

52

~~ tI

:;::

12 J3 l'

I ~~

Vee VEE Vss

;:-

LCD DISPLAY

•S-

C1.

":"

47pF
R2

25V

TOP' I

~f

DO D1 D2 03 D4 05 De 07

AS PIN E

lll::·11
I
Ic:-J.T
A3

=
"I?

200K

-:!...

I FT

;:r

01 11

01J

Zt

2N4126

2

U4

~N5931A

1

U1

_e11

1I~
II",

-:~

24 A02IA2
ADt/A1
1>D3IA3
27 AD4IM

PC4

28
29

14

pes 15

~

-

-

~:

42

31

:

33

AD5/A5
AD6IA6

Vee

AD7"7

11

~

A08/AS

P80 10

TO

A011/A11

PBS 7

~;:10 ;~:

PB2 39

PEt

PB3 38

36 AOl21At2

PB4

PE2

PEW 37

37

PBS 5

PEa

PB5 36

38 ADl41A14
39 ADUVA15

P8

PE7

~~

5

35

22

EIDS

~ ~=r
30 PM
PM

27

PA7

I-

100K

P86 4
PB7 40

PCO~'~'------1r----------~
PCt 42

-jT

;:

2

C12

12 MS

SC:~

."'

PAS

~OO

I
Jit
pF

PC2J::r43'-t____1'

;: PAD

29

AD1S1A13

~

C1

PED

~~

31

-

~

pea 910
PCt
11
PC2
PC3 13

CJ

J 1'00
C1

11>0 pF

co
DO.F

A10

270

Q

pF

1""

A11

~200K

'--

C4
0111F

20K

A12

'7K
A13

L..-

.7'

C3

~

1 OlE SOV

I;t

!ll

it

;-

a I
~

18K
C24

I

S' ~
I

~RX

30K

C5

01~
ELECTRET
MICROPHONE

;;

•:t
J:a'

PSD3XX - Application Not. 04D

Interconnecting
The Parts

The MC34010 has six pins that are used as the digital interface. They are DP, DO, TO,
MS, CL, and I/O. Pin 12 (A+) allows the digital interface to be active and must have a
voltage, typically connected to pin 34 (V+). The DP pin, which is inverted from active HIGH
to active LOW (~outing through some PSD311 programmable logic), is connected to the
microcontroller IRQ pin. Thus, when a key is depressed on the keypad, the IRQ pin is
asserted on the M68HC11 DO microcontroller. Upon assertion of IRQ, the M68HC11 DO
fetches the interrupt vector and begins to execute interrupt exception code. This code looks
for the DO pin to be low. With the help of the CL input (the clock input), a 4-bit serial data
stream is transmitted into the PSD311 from the I/O pin and is then translated into one of the
16 keys on the keypad. A DTMF tone is generated (TO is driven low) and the number is
saved in the PSD311 's SRAM and subsequently sent to the LCD display. The last output on
the MC34010 is the MS output that serves to enable or disable the tone generator.

Configuring
ThePSD

The user-configurability feature of the WSI PSD311 makes implementing the interface
between the M68HC11 DO and the MC34010 very simple. The PSD311 can be programmed
to connect to the M68HC11 DO on one side and interfaced to virtually any peripheral like
the MC34010 on the other. To achieve this flexibility, the PSD contains non-volatile
configuration bits that are chosen by the user when using WSI's PSD MAPLE software and
are set in the device during programming.
To achieve a direct hardware interface to the M68HC11 HO, the PSD311 options
programmed for this application include: active high AS, active low reset, and R/W and E
mode for the control signals.
The LCD interface incorporates eight bidirectional I/O lines that are connected to Port A on
the PSD311. Port A is configured as a general-purpose I/O to provide the eight bits of data
to the LCD display. In addition, for other applications, Port A is capable of transferring up to
eight low order address bits. The functionality of Port B on the PSD311 is split. While all the
pins are configured as general-purpose I/Os and not chip select or logic outputs, two pins
(PBO and PB1) enable the LCD display and RS line. Another five I/O pins on Port B map
directly to the MC34010's microprocessor interface lines: DO, TO, MS, CL, and I/O. Finally,
two pins on Port C, one used as an input to the internal programmable logic array, and the
other used as a chip select/logic output from the array, are used to invert the active HIGH
DP line from the MC34010 to active LOW so the microcontroller IRQ will recognize a
depressed key.
The PSD311 also specifies the address map for the system. For example, both the LCD
and the MC34010 peripherals start at location h'4000, as shown in the software listing. The
rest of the address map encoded in the PSD311 includes 32K bytes of EPROM beginning
at location h'2000, and the SRAM at location h'5000. A summary of the PSD configurations
is shown in the listing file in Appendix A.

The System
Software

The M68HC11 software is written in assembly code for this application and appears in
Appendix B. It is, for the most part, self-explanatory and is well commented.

-------------------------------------~~jr------------------------------------1-253

PSD3XX - Application Note 040

AppendixA.
PS0311
Listing File For
Feature Phone
Application

*************************** MAPLE 6.21 *********************.**.**

ALIASES
/CS8/A16
/CS9/A17

=INTR
=BINTR

GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSIIA19:
Reset Polarity:
ALE Polarity:
WRD/RWE:
A 16-A19 Transparent or Latched by ALE:
Are you using PSEN? N

MX
8
CSI
LO
HI
RWE

T

PORT A CONFIGURATION (AddressIlO)
Bit No.

o

Ai/IO.

10
10
10
10
10
10
10
10

2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

**********************************************************************

PORT B CONFIGURATION
Bit No.

CSIIO.

0

10
10
10
10
10
10
10
10

2
3
4
5
6
7

CMOS/OD.
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT EQUATIONS
**********************************************************************

PORT C CONFIGURATION
Bit No.

o
1
2

CS/Ai.
A16
CS9
CS10

CHIP SELECT EQUATIONS
BINTR

= /(INTR)

**********************************************************************

-1--2-5-4-------------------------------------~~~----------------------------------------

PSD3XX - Application Not. D40

AppendlxA.
PSD311
Listing File For
Feature Phone
Application
(Cont.)

ADDRESS MAP
AAAAAAAAA
19 18 17 16 15 14 13 1211

SEGMT
STRT

SEGMT
STOP

EPROM
START

EPROM
STOP

FileName

N
N
N
N
N
N
N
N
N
N

2000
3000
FOOO

2FFF
3FFF
FFFF

2000
3000
fOOO

2fff
3fff

FPHONE.HEX
FPHONE.HEX
FPHONE.HEX

5000
4000

57FF
47FF

ESO
ESl
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

N
N
N
N
N
N
N
N
N
N

N
N
N
N
N
N
N
N
N
N

X 0
X 0
X

X 0
X 0

0
0

0
0

0 N
N
N
N
N
N
N
N
0
0 0

flff

***************************** ADDRESS MAP (EQUATIONS) *********'*******************
ESO
ESl
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

= IA15 */A14 * A13 */A12
= IA15 */A14 * A13 * A12
= A15 * A14 * A13 * A12
=

=
=
=

=

= IA15*A14*/A13*A12*/All
= IA15*A14*/A13*/A12*/All
END **** ••*************************************

------------------------~Jr;-----------------------1-255

PSD3XX - Application Not. 04D

AppendixB.
Featule Phone
Software Listing

1-256

0001
0002
0003
0004
0005
0006 2000
0007
0008 003d
0009 4000
0010 0001
0011 0007
0012 OOOb
0013 0003
0014 OOOd
0015 0005
0016 0009
0017 0001
0018 OOOe
0019 0006
0020 OOOa
0021 0002
0022 OOOe
0023 0004
0024 0008
0025 0000
0026
0027 2000 01
0028
0029
0030
00310000
00320002
00330003
00340004
00350007
00360008
00370009
0038000b
0039000e
0040000d
0041000e
00420010
00430012
00440014
00450016
00460018
0047001a
0048001e
0049001e
00500020
0051 0021
00520022
00530023
00540024
00550025
00560026
00570027
00580028
00590029
0060002a
0061002b
0062002c
0063002d

.

.

***************************************************************

Feature Phone Software for use with 68HC11 and PSD
By Karen Spesard and Steve Torp - 1/11/95
***************************************************************
ORG

$2000

PROGRAM MEMORY

INIT:
PORTAB:
KEY1:
KEY2:
KEY3:
KEYA:
KEY4:
KEYS:
KEY6:
KEYB:
KEY7:
KEY8:
KEY9:
KEYC:
KEYS:
KEYO:
KEYN:
KEYD:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$0030
$4000
$OF
$07
$OB
$03
$00
$05
$09
$01
$OE
$06
$OA
$02
$OC
$04
$08
$00

RAM AND 1/0 MAPPING REGISTER
1/0 BASE ADDRESS OF THE PSD311
KEYPAD 1
KEYPAD 2 (ABC)
KEYPAD 3 (DEF)
KEYPAD MODE (NORMAUSTOREIRECALL)
KEYPAD 4 (GHI)
KEYPAD 5 (JKL)
KEYPAD 6 (MNO)
KEYPAD SEND
KEYPAD 7 (PQRS)
KEYPAD 8 (TUV)
KEYPAD 9 (WXYZ)
KEYPAD UP
KEYPAD * (STOP/ERASE)
KEYPAD 0
KEYPAD # (ENTER)
KEYPAD DOWN

START:

SEI

*64

SET INTERRUPT MASK IN CCR REG FOR INIT

Bytes of Register Area

PORTA:
PIOC:
PORTC:
PORTB:
DDRC:
PORTD:
DDRD:
CFORC:
OC1M:
OC1D:
TCNT:
TIC1:
TIC2:
TIC3:
TOC1:
TOC2:
TOC3:
TOC4:
TOC5:
TCTL1:
TCTL2:
TMASK1:
TFLG1:
TMASK2:
TFLG2:
PACTL:
PACNT:
SPCR:
SPSR:
SPDR:
BAUD:
SCCR1:
SCCR2:

EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU

$0000
$0002
$0003
$0004
$0007
$0008
$0009
$OOOB
$OOOC
$0000
$OOOE
$0010
$0012
$0014
$0016
$0018
$001A
$001C
$001E
$0020
$0021
$0022
$0023
$0024
$0025
$0026
$0027
$0028
$0029
$002A
$002B
$002C
$0020

f:'=:=:
IIiE=:
iJfiF§
=:

=reFEff!!E

PORT A DATA REGISTER
PARALLEL 1/0 CTL REGISTER
PORT C DATA REGISTER (ADO-AD7)
PORT B DATA REGISTER (A8-A15)
PORT C DATA DIRECTION REGISTER
PORT D DATA REGISTER (RxD. TxD. AND 1/0)
PORT D DATA DIRECTION REGISTER
TIMER COMPARE FORCE REGISTER
OUTPUT COMPARE 1 MASK REGISTER
OUTPUT COMPARE 1 DATA REGISTER
TIMER COUNTER REGISTER (16-BIT) $OOOF LSB
TIMER INPUT CAPTURE REGISTER 1 (16-BIT)
TIMER INPUT CAPTURE REGISTER 2 (16-BIT)
TIMER INPUT CAPTURE REGISTER 3 (16-BIT)
TIMER OUTPUT COMPARE REGISTER 1 (16-BIT)
TIMER OUTPUT COMPARE REGISTER 2 (16-BIT)
TIMER OUTPUT COMPARE REGISTER 3 (16-BIT)
TIMER OUTPUT COMPARE REGISTER 4 (16-BIT)
TIMER OUTPUT COMPARE REGISTER 5/1NPUT
TIMER CONTROL REGISTER 1
TIMER CONTROL REGISTER 2
MAIN TIMER INTERRUPT MASK REGISTER 1
MAIN TIMER INTERRUPT FLAG REGISTER 1
MAIN TIMER INTERRUPT MASK REGISTER 2
MAIN TIMER INTERRUPT FLAG REGISTER 2
PULSE ACCUMULATOR CONTROL REGISTER
PULSE ACCUMULATOR COUNT REGISTER
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
SCI BAUD RATE CONTROL REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2

PlIJIXX - AppllDilt/on Note IJ4II

Appendix'.
FeatulB Phone
SOftwalB Listing
(Cont.)

SCI STATUS REGISTER
SCSR:
0064002e
EQU
$002E
SCI DATA REGISTER
EQU
$002F
SCDR:
00650021
SYSTEM CONFIGURATION OPTIONS
EQU
OPTION:
$0039
00660039
ARM/RESET COP TIMER CIRCUITRY
0067003a
EQU
$003A
COPRST:
EEPROM PROGRAMMING REGISTER
0068003b
EQU
$003B
PPROG:
HIGHEST PRIORITY INTERRUPT
EQU
$003C
HPRIO:
0069003c
FACTORY TEST REGISTER
0070003e
EQU
$003E
TEST1:
CONFIGURATION CONTROL REGISTER
00710031
EQU
$003F
CONFIG:
0072
*192 Bytes of Internal RAM
0073
0074
$0040
FLAG REGISTER
00750040
EQU
FLAGS:
$0041
DIGIT POINTER FOR PHONE NUMBER
00760041
N:
EQU
M:
EQU
NUMBER OF DIGITS IN PHONE NUMBER
$0042
00770042
P:
EQU
STORED DIGIT WHEN READ
$0043
00780043
P12:
EQU
1ST TWO STORED DIGITS
$0044
00790044
2ND TWO STORED DIGITS
EQU
$0045
P34:
00800045
3RD TWO STORED DIGITS
00810046
P56:
EQU
$0046
4TH TWO STORED DIGITS
P78:
EQU
$0047
00820047
P910:
5TH TWO STORED DIGITS
EQU
$0048
00830048
P1112:
6TH TWO STORED DIGITS
$0049
00840049
EQU
STACK POINTER AREA
008500lf
STPTR:
EQU
$OOFF
0086004a
EQU
$004A
MASS STORAGE RAM WRITE POINTER
SWRPTR:
0087004b
EQU
$004B
MASS STORAGE RAM READ POINTERO
SRDPTR:
0088
*2K x 8 RAM in PSD311
0089
0090
$5000
START OF MASS STORAGE BUFFER RAM IN
00915000
MASSTOR:· EQU
PSD311
0092
*Other register initialization
0093
0094
#$20
SET UP OPTION REGISTERlIRQE=O
LDAA
00952001 8620
0096 2003 97 39
STAA
OPTION
0097 2005 86 04
LDAA
#$04
0098 2007 97 3f
STAA
CONFIG
0099 2009 8e 00 If
#STPTR
SET UP STACK
LOS
0100 200c b6 50 00
LDAA
MASSTOR
SET UP SRAM WRITE POINTERS
0101 2001 97 4a
AND SRAM READ POINTERS
STAA
SWRPTR
01022011 974b
STAA
SRDPTR
0103
0104
*PSD Port Direction Set Up
0105
01062013 ce 40 00
LOX
#PORTAB
PORTS A&B OF PSD
0107201686 If
LDAA
#$FF
SET ALL PORT A PINS AS OUTPUTS
01082018 a7 04
4,X
AND STORE
STAA
0109 201a 86 eb
LDAA
#$EB
SET ALL PORT B PINS AS OUTPUTS BUT
0110 201c a7 05
STAA
PINS PB4 (I/O) AND PB2 (MS) FOR NOW
5,X
0111
0112
'Set Up Values for PSD Port Data Outputs Interfacing to MC34010
0113
01142019 ce 40 00
LOX
#PORTAB
PORTS A&B OF PSD
011520218600 LDAA
#$00
SET PORT B PINS 3,5,6 AS LOW OUTPUTS
01162023a707 STAA
7,X
0117

----------------------------~Jr~--------------------------1-257

"SDIXX - Application Nots 04D

AppendixB.
Feature Phone
Software Listing

0118
0119
01202025 ce 27 10

(Cont.)

0121 2028 bd 30 a4
0122 202b 86 38
0123 202d bd 30 b7
0124 2030 ce 03 00
0125 2033 bd 30 a4
01262036 bd 30 b7
01272039 bd 30 al
0128 203c bd 30 b7
01292031 bd 30 al
0130 2042 86 38
0131 2044 bd 30 b7
01322047 ce 02 80
0133 204a bd 30 a4
0134 204d 86 Oe
01352041 bd 30 b7
0136 2052 ce 02 80
01372055 bd 30 a4
013820588606
0139 205a bd 30 b7
0140 205d ce 02 80
0141 2060 bd 30 a4
0142 2063 bd 30 ab
01432066 ce 02 80
01442069 bd 30 a4
0145 206c bd 30 al
0146 2061 ce 01 90
01472072 bd 30 a4
0148
0149
0150
0151 20758607
0152 2077 97 42
0153 2079 86 00
0154 207b 97 41
0155 207d 97 43
0156 2071 97 44
01572081 9745
0158 2083 97 46
015920859747
016020879748
0161 20899749
0162
0163 208b 18 ce 30 le
01642081 bd 30 al
0165 2092 bd 30 b3
0166 2095 bd 30 8a
01672098 bd 30 al
0168 20gb bd 30 al
0169 20ge Oe
0170 2091 86 00
0171 20al 06
0172 20a2 01
0173 20a3 01
0174 20a4 cl

'Display set up
DISINIT:

LDX

#$2710

JSR
LDAA
JSR
LDX
JSR
JSR
JSR
JSR
JSR
LDAA
JSR
LDX
JSR
LDAA
JSR
LDX
JSR
LDAA
JSR
LDX
JSR
JSR
LDX
JSR
JSR
LDX
JSR

TDELAY
#$038
SENDI
#$300
TDELAY
SENDI
TD150
SENDI
TD150
#$038
SEND
#$280
TDELAY
#$OE
SENDI
#$280
TDELAY
#$06
SENDI
#$280
TDELAY
CSCREEN
#$280
TDELAY
HOME
#$190
TDELAY

lOOms DELAY
(PWR UP DELAY FOR DISPLAY)
TIME DELAY
SET UP DISPLAY
SEND INSTRUCTION (30 1ST TIME)
6.1ms DELAY
TIME DELAY
SEND INSTRUCTION (30 2ND TIME)
TIME DELAY
SEND INSTRUCTION (30 3RD TIME)
TIME DELAY
FUNCTION SET (8-BIT:2-LlNE)
SEND INSTRUCTION
5ms DELAY
TIME DELAY
DISPLAY ON - CURSOR ON
SEND INSTRUCTION
5ms DELAY
TIME DELAY
ENTRY MODE SET
SEND INSTRUCTION
5ms DELAY
TIME DELAY
CLEAR SCREEN
5ms DELAY
TIME DELAY
DISPLAY CURSOR HOME!
4ms DELAY
TIME DELAY

'Final Initialization
REGINIT:

DISPLAY:

STOP1:

LDAA
STAA
LDAA
STAA
STAA
STAA
STAA
STAA
STAA
STAA
STAA

#$07
M
#$00
N
P
P12
P34
P56
P78
P9l0
Pll12

INITIALIZE REGISTER "M"
STORE# OF DIGITS IN TEL NO.
CLEAR FOLLOWING "REGISTERS"

LDY
JSR
JSR
JSR
JSR
JSR
CLI
LDAA
TAP
NOP
NOP
STOP

#$301E
TD150
LlNE2
PDOD
TD150
HOME

NORMAL MODE
TIME DELAY
USE LINE 2
DISPLAY MODE
TIME DELAY
USE LINE 1 NEXT
CLEAR IRQ MASK
LOAD A WITH STOP ENABLE FOR CCR
TRANSFER A ACCUM TO CCR

f.Ji'=

#$00

STORAGE FOR EACH DIGIT OF
PHONE NUMBER ...

-1-~-S8-----------------------------~~§--------------------------------

"OSxx - Application Not. 04D

AppendixB.
Feature Phone
Software Listing
(CDnt.)

0175
0176
0177
0178
0179
0180 20a5 ee 40 00
0181 20a8 86 eb
0182 20aa a7 05
018320ae 86 00
0184 20ae a7 07
0185
0186 20bO bd 30 97
0187 20b3 ee 40 00
0188 20b6 1d 07 40
0189 20b9 bd 30 97
019020be 1e 07 40
0191 20bf bd 30 97
019220e2 1d 07 40
0193 20e5 bd 30 97
0194 20e81e 07 40
0195 20eb bd 30 97
0196
0197 20ee 4f
0198 20ef 18 ee 00 04
019920d30e
0200 20d4 1d 07 40
0201 20d7 11 07 10 01
020220db Od
0203 20de 49
0204 20dd bd 30 97
0205 20eO 1e 07 40
0206 20e3 bd 30 97
020720e6 1809
0208 20e8 18 8e 00 00
0209 20ee 26 e5
0210 20ee 97 43
0211
0212
0213
02142010 81 Of
0215201226 Od
0216
0217 201418 ce 30 00
02182018 bd 30 Ba
0219 20fb bd 30 d8
0220
0221 201e 7e 22 1b
0222

"IRQ Service Routine
"Read Which Key Depressed, Store in Accumulator A
GDATA:

LDX
LDAA
STAA
LDAA
STAA

#PORTAB
#$EB
5,X
#$00
7,X

SET UP PSD PORTB TO READ KEY
SET ALL PORT B PINS AS OUTPUTS EXCEPT
PINS PB4 (I/O) AND PB2 (DP) FOR NOW
INITIALIZE PORT B OUTPUT PINS 3,5,6 LOW

RDATA:

JSR
LDX
BCLR
JSR
BSET
JSR
BCLR
JSR
. BSET
JSR

T20
#PORTAB
7,X$40
T20
7,X$40
T20
7,X$40
T20
7,X$40
T20

TDELAY20uS
SET UP PSD PORTB TO READ KEY
ETC/CLLOW
TDELAY20uS
ETC/CLHIGH
TDELAY20uS
ETC/CLLOW
TDELAY20uS
ETC/CLHIGH
TDELAY20uS

READD:

N1:

CLRA
LDY
CLC
BCLR
BRCLR
SEC
ROLA
JSR
BSET
JSR
DEY
CPY
BNE
STAA

#$04
7,X$40
7,X $10 N1

T20
7,X$40
T20
#$00
READD
P

CLEAR ACCUMULATOR A
READ 4 I/O-DATA BITS
CLEAR CARRY BIT
ETC/CLLOW
BRANCH IF I/O LOW TO CLEAR CARRY,
OTHERWISE, SET CARRY
RD EACH BIT TO DETERMINE KEY PRESSED
TDELAY20uS
ETC/CLHIGH
TDELAY20uS
DECREMENT COUNT
COUNT=O?
IF NOT DONE, GO TO READD
STORE DIALED NUMBER IN P REGISTER

"Start Routine
START1:

RETRY:

CMPA
BNE

#KEY1
DOIT10

1 KEY?
IF NOT GOTO DOIT10

LDY
JSR
JSR

#$3000
PDOD
CHD

DISPLAY "1"
SEND MESSAGE TO DISPLAY
CHK IF 1ST DIGIT & SAVE

JMP

ENDKEYDP

RTI AFTER KEY IS NO LONGER DEPRESSED

-------------------------~Jr;-----------------------1·259

PS03XX - Application Nots 04D

AppendixB.
Feature Phone
Software Listing
(Cont.)

02232101 81 07
0224 2103 26 Od
0225210518 ce 30 03
0226 2109 bd 30 8a
0227 21 Oc bd 30 d8
02282101 7e 22 1b
0229
02302112810b
0231 21142609
02322116 bd 30 8a
02332119 bd 30 d8
0234 211c 7e 22 1b
0235
02362111 81 03
02372121 2613
0238212318 ce 30 30
02392127 bd 30 a1
0240 212a bd 30 b3
0241 212d bd 30 a1
02422130 bd 30 8a
02432133 7e 22 1b
0244
0245213681 Od
02462138260d
0247 213a 1B ce 30 09
024B 213e bd 30 8a
02492141 bd 30 d8
02502144 7e 22 1b
0251
02522147 B1 05
025321492610
0254 214b 1B ce 30 Oc
02552141 bd 30 Ba
0256 2152 bd 30 d8
02572155 bd 31 9d
025B 215B 7e 22 1b
0259
0260 215b 81 09
0261 215d 26 Od
02622151 1B ce 30 01
0263 2163 bd 30 8a
02642166 bd 30 dB
02652169 7e 22 1b
0266
0267 216c B1 01
026B 216e 26 10
0269217018 ce 30 54
02702174 bd 30 b3
0271 2177 bd 30 8a
0272 217a bd 31 ea
0273 217d 7e 22 1b
0274
0275
02762180 B1 Oe
0277 21 B2 26 Od
027B 2184 1B ce 3012
027921 BB bd 30 Ba
02BO 21 Bb bd 30 dB
02B1 218e 7e 22 1b
0282

DOIT10:

DOIT20:

DOIT30:

DOIT40:

DOIT50:

DOIT60:

DOIT70:

DOITBO:

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY2
DOIT20
#$3003
PDOD
CHD
ENDKEYDP

2 KEY?
IF NOT GOTO DOIT20
DISPLAY "2"

CMPA
BNE
JSR
JSR
JMP

#KEY3
DOIT30
PDOD
CHD
ENDKEYDP

3 KEY?
IF NOT GOTO DOIT30

CMPA
BNE
LOY
JSR
JSR
JSR
JSR
JMP

#KEYA
DOIT40
#$3030
TD150
LlNE2
TD150
PDOD
ENDKEYDP

A KEY? (MODE)
IF NOT GOTO DOIT40
NORMAURECALUSTORE

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY4
DOIT50
#$3009
PDOD
CHD
ENDKEYDP

4 KEY?
IF NOT GOTO DOIT50
DISPLAY "4"

CMPA
BNE
LOY
JSR
JSR
JSR
JMP

#KEY5
DOIT60
#$300C
PDOD
CHD
CHAD
ENDKEYDP

5 KEY?
IF NOT GOTO DOIT60

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY6
DOIT70
#$300F
PDOD
CHD
ENDKEYDP

6 KEY?
IF NOT GOTO DOIT70

CMPA
BNE
LOY
JSR
JSR
JSR
JMP

#KEYB
DOITBO
#$3054
LlNE2
PDOD
DIALNO
ENDKEYDP

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY7
DOIT90
#$3012
PDOD
CHD
ENDKEYDP

SAVE DIGIT
RTI AFTER KEY IS NO LONGER DP

SAVE DIGIT
RTI AFTER KEY IS NO LONGER DP

(THIS ROUTINE NOT COMPLETE)

RTI AFTER KEY IS NO LONGER DP

SAVE DIGIT
RTI AFTER KEY IS NO LONGER DP

DISPLAY "5"
SAVE DIGIT
IF ALL DIGITS PRESSED IN NO., STORE

DISPLAY "6"
SAVE DIGIT
RTI AFTER KEY IS NO LONGER DP
B KEY? (SEND)
IF NOT GOTO DOITBO

DISPLAY "SEND"
SEND NO TO DTMF AND DIAL
RTI AFTER KEY IS NO LONGER DP

7 KEY?
IF NOT GOTO DOIT90
DISPLAY "7"
SAVE DIGIT
RTI AFTER KEY IS NO LONGER DP

-1--2-6-0-----------------------------------~~~--------------------------------------

PS03XX - Application Nots 040

AppendixB.
Feature Phone
Software Listing
(Cont.)

028321918106
0284 2193 26 Od
0285219518 ce 3015
02862199 bd 30 8a
0287 219c bd 30 d8
02882191 7e 22 1b
0289
0290 21a2 81 Oa
0291 21a4 26 Od
0292 21a6 18 ce 3018
0293 21 aa bd 30 8a
0294 21 ad bd 30 d8
0295 21bO 7e 22 1b
0296
029721 b3 81 02
0298 21 b5 26 22
0299 21b7 bd 30 ab
0300 21ba 18 ce 30 66
0301 21be bd 30 a1
0302 21c1 bd 30 b3
0303 21 c4 bd 30 8a
0304 21c7 bd 30 a1
0305 21 ca bd 30 al
0306 21 cd 86 08
0307 21cl 90 4b
0308 21d1 974b
0309 21d3 bd 31 c7
0310 21d6 7e 22 1b
0311
031221d9810c
0313 21db 26 03
0314 21dd 7e 221b
0315
031621e081 04
0317 21e2 26 Od
0318 21e418 ce 30 1b
0319 21e8 bd 30 8a
0320 21 eb bd 30 d8
0321 21ee 7e 221b
0322
03232111 81 08
0324 2113 26 03
IF NOT GOTO 00lT150
03252115 7e 22 1b
0326
0327211881 00
0328 21fa 26 1c
IF NOT GOTO 00lT160
0329 21fc 18 ce 30 78
0330 2200 bd 30 a 1
0331 2203 bd 30 b3
0332 2206 bd 30 8a
0333 2209 bd 30 a 1
0334 220c bd 30 al
0335 2201 86 08
03362211 9b 4b
0337 2213 97 4b
0338 2215 bd 31 c7
0339
03402218 7e 22 1b
0341
0342

001T90:

8 KEY?
IF NOT GOTO 00lT100

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY8
00lT100
#$3015
POOO
CHO
ENOKEYOP

CMPA
BNE
LOY
JSR
JSR
JMP

#KEY9
00lT110
#$3018
POOO
CHO
ENOKEYOP

CMPA
BNE
JSR
LOY
JSR
JSR
JSR
JSR
JSR
LOAA
SUBA
STAA
JSR
JMP

#KEYC
00lT120
CSCREEN
#$3066
TD150
LlNE2
POOO
T0150
HOME
#$08
SROPTR
SROPTR
SCROLL
ENOKEYOP

SEND NUMBER TO DISPLAY
RTI AFTER KEY IS NO LONGER OP

001T120:

CMPA
BNE
JMP

#KEYS
00lT130
ENOKEYOP

• KEY?
IF NOT GOTO 00lT130
RTI AFTER KEY IS NO LONGER OP

001T130:

CMPA
BNE
LOY
JSR
JSR
JMP

#KEYO
00lT140
#$301B
POOO
CHO
ENOKEYOP

o KEY?

CMPA

#KEYN
BNE

# KEY?
00lT150

JMP

ENOKEYOP

RTI AFTER KEY IS NO LONGER OP

CMPA

#KEYO
BNE

o KEY? (DOWN)

001T100:

001T110:

001T140:

001T150:

001T160:

LOY
JSR
JSR
JSR
JSR
JSR
LOAA
AOOA
STAA
JSR

#$3078
TD150
LlNE2
POOO
T0150
HOME
#$08
SROPTR
SROPTR
SCROLL

JMP

ENOKEYOP

DISPLAY "8"
SAVE DIGIT
RTI AFTER KEY IS NO LONGER OP
9 KEY?
I F NOT GOTO 00lT11 0
DISPLAY "9"
SAVE DIGIT
RTI AFTER KEY IS NO LONGER OP
C KEY? (UP)
IF NOT GOTO 00lT120

DISPLAY "SCROLL UP"

IF NOT GOTO 001T140
DISPLAY "0"
SAVE DIGIT
RTI AFTER KEY IS NO LONGER OP

00lT160

DISPLAY "SCROLL

~OWN''

RTI AFTER KEY IS NO LONGER OP

';EE~

ifIi:IJiElf ;

--- --

~---~-

---,------

---

-

1-261

PSD3XX - Application Note 040

AppendixB.
Feature Phone
Software Listing

0343
0344
0345 221 b ee 40 00
0346 221 e a6 03

·Check if key no longer depressed
ENDKEYDP:
REPEAT:

LDX
LDAA

#PORTAB
3,X

ANDA

#$04
BNE
CLI
STOP1

(Cont.)
0347 2220 84 04
0348 2222 26 la
034922240e
0350 2225 7e 20 a4
0351
0352
0353
03543000
0355
0356300031
0357 3001 00 00
0358300332
0359 3004 00 00
0360300633
0361 3007 00 00
0362300934
0363 300a 00 00
0364 300e 35
0365 300d 00 00
0366300136
0367 3010 00 00
0368301237
0369 3013 00 00
0370301538
0371 30160000
0372301839
037330190000
0374 301b 30
0375 301e 00 00
0376 301 e 20 20 4e 41 52 4d
414e204d4144
45202020
0377 302e 00 00
0378 3030 20 20 52 45 43 41
4e 4c 20 4d 4144
45202020
0379 3040 00 00
0380 3042 20 20 20 53 54 41
52 45 20 4d 41 44
45202020
0381 3052 00 00
0382 3054 20 20 20 20 20 53
45 4e 44 20 20 20
20202020
0383 3064 00 00
0384 3066 20 20 20 53 43 52
41 4e 4e 20 55 50
20202020
0385 3076 00 00
0386 3078 20 20 53 43 52 41
4c 4c 20 44 41 57
48202020
0387 3088 00 00
0388
0389

JMP

CHECK FOR MS - PORTB PIN 2 (DP) LOW
WHICH MEANS KEY IS NO LONGER
DEPRESSED
REPEAT
CLEAR INTERRUPT
WAIT FOR NEXT KEY TO BE DEPRESSED

·Screens
ORG

$3000
"1"
$00
"2"
$00
"3"
$00
"4"
$00
"5"
$00
"6"
$00
"7"
$00

SCRA1:

FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC
FDB
FCC"

SCRA2:

FDB $00
FCC" RECALL MODE

SCRA3:

FDB $00
FCC" STORE MO

SCRB:

FDB $00
FCC" SEND

SCRC:

FDB $00
FCC" SCROLL UP

SCRD:

FDB $00
FCC" SCROLL DOWN

SCR1:
SCR2:
SCR3:
SCR4:
SCR5:
SCR6:
SCR7:
SCR8:
SCR9:
SCRO:

"8"
$00

"9"
$00
"0"
$00
NORMAL MODE

FDB $00

-:-------------------f== ==------------------1-262

PSD3XX - Application Not. lUll

AppendixB.
Feature Phone
Software Listing
(Cont.)

0390
0391
0392
0393
0394 30Ba 1B a6 00
0395 30Bd 27 07
0396 30Bf bd 30 c3
0397 3092 1B OB
039B 3094 20 f4
0399309639
0400
040
0402
0403 3097 c6 Of
0404 3099 20 00
0405 309b 5a
0406 309c c1 00
0407 30ge 26 fb
040B 30aO 39
0409
041030a1 ce 00 Of
0411 30a409
0412 30a5 Bc 00 00
041330aB 26 fa
041430aa39
0415
0416
0417
041B 30ab B6 01
0419 30ad 20 OB
0420 30at B6 02
0421 30b1 2004
0422 30b3 B6 cO
0423 30b5 20 00
0424 3Ob7 ce 40 00
0425 30ba a7 06
0426 30bc 1c 07 02
0427 30bf 1d 07 02
042B 30c2 39
0429
0430
0431
0432 30c3 bd 30 a 1
0433 3Oc6 ce 40 00
0434 30c9 a7 06
043530cb 1c 07 01
0436 30ce 1c 07 02
043730d1 1d 0702
043B 30d4 1d 07 01
0439 30d7 39
0440
0441
0442
0443
0444 30dB 7c 00 41
0445 30db c6 01
0446 30dd d1 41
0447 30df 26 1a
O44B

'Subroutines
'Put Data on Display
LDAA
BEQ
JSR
INY
BRA
RTS

PDOD:

PDOD1:

O,Y
PDOD1
SENDD
PDOD

'Time Delay Routine
T20:
LOB
#$OF
BRA
TDLY
TDLY:
DECB
CMPB #$00
BNE
TDLY
fiTS
TD150:
TDELAY:

LOX
DEX
CPX
BNE
RTS

#$OOOF
#$0000
TDELAY

GET BYTE
IF END (00), GOTO NEXT 1
NEXT BYTE
RETURN TO NEXT

>20 uS DELAY

150us DELAY
DECREMENT COUNT
COUNT=O?
IF NOT DONE, GOTO TDELAY
RETURN FROM SUBROUTINE

'Clear Screen, Cursor Home, and Send Control Instruction
CSCREEN: LDAA
BRA
LDAA
HOME:
BRA
LlNE2:
LDAA
BRA
SENDI:
LOX
STAA
BSET
BCLR
RTS

#$0001
SENDI
#$0002
SENDI
#$OOCO
SENDI
#PORTAB
6,X
7,X$02
7,X$02

CLEAR DISPLAY
SEND INSTRUCTION
CURSOR HOME
SEND INSTRUCTION
SET CURSOR TO LINE 2
SEND INSTRUCTION
SET UP DATA TRANSFER
STORE AT PIA PORT A
DISPLAY E HIGH (PSD PORT B PIN 1)
DISPLAY E LOW (PSD PORT B PIN 1)

'Send Data to Display
SEN DO:

JSR
LOX
STAA
BSET
BSET
BCLR
BCLR
RTS

TD150
#PORTAB
6,X
7,X$01
7,X$02
7,X$02
7,X$01

150 uS TIME DELAY
SET UP DATA TRANSFER
SEND DATA
DISPLAY RS HIGH
DISPLAY E HIGH
DISPLAY E LOW
DISPLAY RS LOW

'Check if first number dialed is a 1 or 0 (number stored in A
'accum) and if it is, expand expected digits in number to 11.
CHD:

----------------_______________________

INC
LDAB
CMPB
BNE

fJr~~~

';fH!!_ S

N
#$01
N
CH2D

INCREMENT DIGIT IN NUMBER
COMPARE N TO 1 TO SEE IF 1ST DIGIT DIALED
IF N=1, CHECK IF NO. DIALED IS 1 OR 0

______________________________________
1-263

PSDaxx - Application Nots 040

AppendixB.
Feature Phone
Software Listing
(Cont.)

0449
0450
0451 30el e600
0452 30e3 dl 43
0453 30e5 26 14
0454 30e7 c6 01
0455 30e9 dl 43
0456 30eb 26 Oe
0457 30ed e6 Ob
0458 30el d7 42
0459
0460
0461
0462 3011 d6 43
046330130c
0464301459
0465301559
0466301659
0467301759
0468 3018 d7 44
0469 30la 39
0470
0471
0472
0473 30lb c6 02
0474 30ld dl 41
0475 301f 26 07
04763101 d644
0477 3103 de 43
04783105 d7 44
0479310739
0480
0481
0482
04833108 e6 03
0484310ed141
0485 310e 26 Oa
0486310e d6 43
048731100e
0488311159
0489311259
0490311359
0491 311459
04923115 d7 45
0493311739
0494
0495
0496
04973118 e6 04
0498 311a dl 41
0499 311e 26 07
0500 311e d6 45
0501 3120 de 43
05023122 d7 45
0503312439
0504
0505
0506
0507

'Check if first digit 0 or 1 and change M to 11 digits if it is.
LDAB
CMPB
BNE
LDAB
CMPBP
BNE
LDAB
STAB

~

CH2D
#$OB
M

COMPARE 00 TO NUMBER DIALED
IF 1ST NO. ISN'T 0, THEN CONTINUE
COMPARE 01 TO NUMBER DIALED
F 1ST NO. ISN'T 1, THEN CONTINUE
SET M=$OB IF 1ST DIGIT IS lOR 0
OTHERWISE M=$07

'If first digit dialed, save in upper 4 bits of register P12.
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
STAB
RTS

P

LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE IT TO UPPER 4BITS IN REGISTER

P12

STORE IT TEMPORARILY

'Save second digit in lower 4 bits of P12
CH2D:

LDAB
CMPBN
BNE
LDAB
ORAB
STAB
RTS

#$02
CH3D
P12
P
P12

DETERMINE IF DIGIT DIALED WAS
SECOND DIGIT AND
IFITIS
STORE 2ND DIGIT IN LOWER 4 BITS OF P12
BY "OR"ING ITW/P12 WHICH ALREADY HAS 1ST
DIGIT SAVED IN UPPER 4 BITS

'Save third digit in upper 4 bits of P34
CH3D:

LDAB
CMPB
BNE
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
STAB
RTS

#$03
N
CH4D
P

DETERMINE IF DIGIT DIALED WAS
THIRD DIGIT AND
IF IT IS
LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE IT TO UPPER 4BITS IN REGISTER

P34

STORE IT TEMPORARILY

'Save fourth digit in lower 4 bits of P34
CH4D:

LDAB
CMPBN
BNE
LDAB
ORAB
STAB
RTS

#$04
CH5D
P34
P
P34

DETERMINE IF DIGIT DIALED WAS
FOURTH DIGIT AND
IFITIS
STORE 4TH DIGIT IN LOWER 4 BITS OF P34
BY "OR"ING IT W/P34 WHICH ALREADY HAS 3RD
DIGIT SAVED IN UPPER 4 BITS

'Save fifth digit in upper 4 bits of P56

__ ___________________________________
1-264

#$00
P
CH2D
#$01

rarar~~

':ifg=i!~

---------------

PSD3XX - Application Nots 040

AppendixB.
Feature Phone
Software Listing
(Cont.)

05083125 c6 05
05093127d141
05103129260a
0511 312b d6 43
0512 312d Oc
0513 312e 59
0514312159
0515313059
05163131 59
0517 3132 d7 46
0518313439
0519
0520
0521
05223135 c6 06
05233137d141
052431392607
0525 313b d6 46
0526 313d da 43
05273131 d7 46
05283141 39
0529
0530
0531
0532 3142 c6 07
05333144d141
053431462615
0535 3148 d6 43
0536 314a Oc
0537 314b 59
0538 314c 59
0539 314d 59
0540 314e 59
0541 3141 d6 42
05423151 d1 41
0543 3153 27 02
0544 3155 ca Oa
05453157 d7 47
05463159 bd 31 9d
0547 315c 39
0548
0549
0550
0551 315d c6 08
05523151d141
055331612607
05543163 d6 47
0555 3165 da 43
0556 3167 d7 47
0557316939
0558
0559
0560

CH5D:

LDAB
CMPB
BNE
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
STAB P56
RTS

#$05
N
CH6D
P

DETERMINE IF DIGIT DIALED WAS
FIFTH DIGIT AND
IFITIS
LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE IT TO UPPER 4BITS IN REGISTER

STORE IT TEMPORARILY

'Save sixth digit in lower 4 bits 01 P56
CH6D:

LDAB
CMPB
BNE
LDAB
ORAB
STAB
RTS

#$06
N
CH7D
P56
P
P56

DETERMINE IF DIGIT DIALED WAS
SIXTH DIGIT AND
IF ITIS
STORE 6TH DIGIT IN LOWER 4 BITS OF P56
BY "OR"ING IT W/P56 WHICH ALREADY HAS 5TH
DIGIT SAVED IN UPPER 4 BITS

'Save seventh digit in upper 4 bits of P78
CH7D:

NEXT:

LDAB
CMPB
BNE
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
LDAB
CMPB
BEQ
ORB
STAB
JSR
RTS

#$07
N
CH8D
P

M
N
NEXT
#$OA
P78
CHAD

DETERMINE IF DIGIT DIALED WAS
SEVENTH DIGIT AND
IFITIS
LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE IT TO UPPER 4BITS IN REGISTER

CHECK IF M=N? - ALL NUMBERS DIALED

STORE IT TEMPORARILY

'Save eighth digit in lower 4 bits of P78
CH8D:

LDAB
CMPB
BNE
LDAB
ORAB
STAB
RTS

#$08
N
CH9D
P78
P
P78

DETERMINE IF DIGIT DIALED WAS
EIGHTH DIGIT AND
IFITIS
STORE 8TH DIGIT IN LOWER 4 BITS OF P78
BY "OR"ING IT W/P78 WHICH ALREADY HAS 7TH
DIGIT SAVED IN UPPER 4 BITS

'Save ninth digit in upper 4 bits 01 P910

---------------------------------------~~~-------------------------------------1·265

PSD3XX - Application Nots 04D

AppendixB.
Feature Phone
Software Listing
(Cont.)

0561 316a c6 09
0562 316c d1 41
0563 316e 26 Oa
0564 3170 d6 43
056531720c
0566317359
0567317459
0568317559
0569317659
05703177 d7 48
0571317939
0572
0573
0574
0575 317a c6 Oa
0576 317c d1 41
0577 317e 26 07
0578 3180 d6 48
05793182 da 43
05803184 d7 48
0581318639
0582
0583
0584
0585 3187 c6 Ob
05863189 dl 41
0587 318b 26 01
0588 318d d6 43
058931810c
0590319059
0591319159
0592319259
0593319359
05943194 ca Oa
0595 3196 d7 49
05963198 bd 31 9d
0597 319b 39
0598
0599 319c 39
0600
0601
0602
0603 319d d6 42
06043191d141
060531 al 27 01
0606 31a3 39
0607
0608
0609

CH9D:

LDAB
CMPB
BNE
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
STAB
RTS

#$09
N
CH10D
P

DETERMINE IF DIGIT DIALED WAS
NINTH DIGIT AND
IFITIS
LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE iT TO UPPER 4BITS IN REGISTER

P910

STORE IT TEMPORARILY

'Save tenth digit in lower 4 bits of P910
CH10D:

LDAB
CMPB
BNE
LDAB
ORAB
STAB
RTS

#$OA
N
CH11D
P910
P
P910

DETERMINE IF DIGIT DIALED WAS
TENTH DIGIT AND
FITIS
STORE 10TH DIGIT IN LOWER 4 BITS OF P910
BY "OR"ING IT W/P91 0 WHICH ALREADY HAS 9TH
DIGIT SAVED IN UPPER 4 BITS

'Save eleventh digit in upper 4 bits of P910
CH11D:

CDONE:

LDAB
CMPB
BNE
LDAB
CLC
ROLB
ROLB
ROLB
ROLB
ORB
STAB
JSR
RTS

#$OB
N
CDONE
P

DETERMINE IF DIGIT DIALED WAS
ELEVENTH DIGIT AND
IF IT IS
LOAD DIALED DIGIT IN REGISTER
CLEAR CARRY BIT
ROTATE NUMBER LEFT TO MOVE iT TO UPPER 4BITS IN REGISTER

#$OA
Pll12
CHAD

LAST 4 BITS WILL REPRESENT END OF NO.
STORE IT TEMPORARILY

RTS

'Check if all digits in number dialed
CHAD:

LDAB
CMPB
BEQ
RTS

M
N
STBUF

CHECK IF M~N? - ALL NUMBERS DiALED
STORE ENTERED NUMBER IN BUFFER RAM

'Enter Dialed Number in Buffer RAM

-1-~-66-----------------------------~~~~--------------------------------

I'SD3XX - Application Note 04D

AppendixB.
Feature Phone
Software Listing
(Cont.)

0610 31a4 de 4a
0611 31a6 86 08
0612 31a8 9b 4a
0613 31aa 97 4a
0614 31ac 97 4b
0615 31ae 96 44
0616 31bO a7 00
0617 31b2 96 45
0618 31b4 a7 01
0619 31b6 96 46
0620 31b8 a7 02
0621 31 ba 96 47
0622 31bc a7 03
062331 be 96 48
0624 31cO a7 04
0625 31 c2 96 49
0626 31c4 a7 05
0627 31c6 39
0628
0629
0630
0631 31c718 de 4b
0632
0633 31ca 18 a6 00
0634 31cd 44
0635 31ce 44
0636 31cf 44
0637 31dO 44
0638 31d1 8a 30
063931 d3 bd 30 c3
0640 31d6 18 a6 00
064131d9840f
0642 31db 8a 30
0643 31dd 81 3a
0644 31df 27 08
0645 31e1 bd 30 c3
0646 31e418 08
0647 31e6 bd 31 ca
0648 31e9 39
0649
0650
0651
0652 31ea 18 de 4b
0653 31ed 18 e6 00
06543110 ce 40 00
0655 3113 86 fb
06563115 a7 05
065731178600
06583119 a7 07
0659 311b 1c 07 08
0660 311e bd 30 97
0661 3201 1c 07 20
0662 3204 bd 30 97
0663
0664 3207 86 02
0665 3209 18 ce 00 04
0666 320d 1c 07 40
06673210 bd 30 97
0668321359
066932142406
06703216 1c 0710
0671 3219 bd 3211

STBUF:

LDX
LDAA
ADDA
STAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
LDAA
STAA
RTS

SWRPTR
#$08
SWRPTR
SWRPTR
SRDPTR
P12
O,X
P34
1,X
P56
2,X
P78
3,X
P910
4,X
P1112
5,X

STORE SRAM WRITE POINTER IN X REG

STORED PHONE NO. (INCREMENT WRITE PTR)
SET READ POINTER AT LAST WRITTEN LOCATION
STORE FIRST TWO DIGITS IN RAM MEMORY
STORE NEXT TWO DIGITS IN RAM MEMORY
STORE NEXT TWO DIGITS IN RAM MEMORY
STORE NEXT TWO DIGITS IN RAM MEMORY
STORE NEXT TWO DIGITS IN RAM MEMORY
STORE LAST DIGIT IN RAM MEMORY

'Send Stored Number while Scrolling to Display
SCROLL:

LDY

SRDPTR

LOAD ADDRESS OF READ POINTER IN Y REGISTER

NXTNUM:

LDAA
LSRA
LSRA
LSRA
LSRA
ORA
JSR
LDAA
ANDA
ORA
CMPA
BEQ
JSR
INY
JSR
RTS

O,Y
BY

LOAD 1ST DIGIT, PX?, FROM RAM IN A ACCUM
GETTING PXY AND SHIFTING RIGHT
4 TIMES
TO ACHIEVE OOOOIXXXX
THEN MAKE IT
ASCII EQUIVALENT - 0011IXXXX
SEND DATA TO DISPLAY
READ 2ND DIGIT, P?Y, FROM RAM MEMORY
CLEAR UPPER 4 BITS
SET UPPER 4 BITS TO 3 -> 0011IYYYY
CHECK IF LAST NUMBER DIALED
AND IF IT IS, RETURN. OTHERWISE,
SEND DATA TO DISPLAY,
INCREMENT ADDRESS, AND
RETRIEVE NEXT NUMBER

NUMRET:

#$30
SENDD
O,Y
#$OF
#$30
#$3A
NUMRET
SENDD
NXTNUM

'Send Number to Electronic Telephone Circuit for Dialing and Store
DIALNO:
SDDATA:

SCTL:

LDY
LDAB
LDX
LDAA
STAA
LDAA
STAA
BSET
JSR
BSET
JSR

SRDPTR
O,Y
#PORTAB
#$FB
5,X
#$00
7,X
7,X $08
T20
7,X $20
T20

NXT2NUM: LDAA #$02
NXTDIG:
LDY
#$04
S4BIT:
BSET 7,X $40
JSR
T20
ROLB
BCC SNDL01
BSET 7,X $10
JSR
DELAY

TRANSFER CONTENTS AT ADDRESS CONTAINED IN
READ POINTER TO ACCUM B
CONFIGURE PSD PORTB TO SEND NUMBER
SET ALL PORT B PINS AS OUTPUTS EXCEPT
PIN PB2 (DP)
INITIALIZE PORT B PINS 3,4,5,6 AS LOW
OUTPUTS
rro (TONE OUTPUT) HIGH
TDELAY 20uS
/DD (DATA DIRECTION) HIGH FOR OUTPUT
TDELAY 20uS
LOOP TWICE TO SEND 2 DIGITS/8-BITS
LOOP 4 TIMES TO SEND 4 BITS/DIGIT IN NO.
ETC /CL (CLOCK INPUT) HIGH
TDELAY 20uS
SHIFT IN CARRY BIT
BRANCH IF CARRY CLEAR
SET CARRY BIT AND SEND DATA ON I/O

rill;
------_.

1-267

----_.._ - - - - - -

-----,"----

PSD3XX - Application Nots 040

AppendixB.
Feature Phone
Software Listing
(Cont.)

0672 321c 1d 0710
0673 3211 bd 30 97
06743222 1d 07 40
0675 3225 bd 30 97
0676 3228 18 09
0677 322a 18 8c 00 00
0678 322e 26 dd
0679
0680 3230 1d 07 08
0681 3233 bd 30 97
0682 3236 1c 07 08
0683 3239 bd 30 97
0684
0685 323c 4a
0686 323d 81 00
0687 3231 26 01
0688 3241 bd 32 09
0689 3244 18 de 4b
06903247 18 08
0691 3249 18 e6 00
0692 324c bd 32 07
0693324139
0694
0695 3250 c4 10
0696 3252 c1 aO
0697 3254 27 02
0698 3256 20 e9
0699
0700 3258 18 de 4b
0701 325b de 4a
0702 325d 18 a6 00
0703 3260 a7 00
0704 3262 18 a6 01
07053265 a7 01
0706 3267 18 a6 02
0707 326a a7 02
0708 326c 18 a6 03
07093261 a7 03
0710327118 a6 04
0711 3274 a7 04
0712327618 a6 05
0713 3279 a7 05
0714327b 18 a6 06
0715 327e a7 06
0716328018 a6 07
0717 3283 a7 07
0718328539
0719
0720
072
0722 fff2
0723
0724 flf2 20 a5
0725 flf4 20 00
0726 flf6 20 00
0727 flf8 20 00
0728 flfa 20 00
0729 flfc 2000
0730 fife 20 00
0731
0732

SNDL01:
DELAY:

GETNXT:

CHKDIG:

BClR
JSR
BClR
JSR
DEY
CPY
BNE

7,X$10
T20
7,X$40
T20
#$00
S4BIT

CLEAR CARRY BIT AND SEND DATA ON 1/0
TDElAY 20uS - COULD CHANGE TO 10uS
ETC ICl (CLOCK INPUT) lOW
TDELAY20uS
DECREMENT COUNT
COUNT=O?
IF NOT DONE, GO TO S4BIT

BClR
JSR
BSET
JSR

7,X $08
T20
7,X $08
T20

ITO lOW FOR TONE GENERATION INTERVAL
TDElAY 20uS
ITO HIGH FOR TONE GENERATION INTERVAL
TDElAY 20uS

DECA
CMPA
BNE
JSR
lDY
INY
lDAB
JSR
RTS
ANDB
CMPB
BEQ
BRA

STORENO: lDY
lDX
lDAA
STAA
lDAA
STAA
lDAA
STAA
lDAA
STAA
lDAA
STAA
lDAA
STAA
lDAA
STAA
lDAA
STAA
RTS

#$00
CHKDIG
NXTDIG
SRDPTR
O,Y
NXT2NUM

INCREMENT ADDRESS FOR NEXT 2 NUMBERS
AND lOAD IN B ACCUM

#$FO
#$AO
STORENO
GETNXT

CLEAR lOWER 4-BITS
COMPARE DIGIT THAT Will BE SENT W/$AO
IF lAST NO. AO, STORE SINCE All NOS SENT

SRDPTR
SWRPTR
O,Y
O,X
1,Y
1,X
2,Y
2,X
3,Y
3,X
4,Y
4,X
5,Y
5,X
6,Y
6,X
7,Y
7,X

COPY DIALED NUMBER INTO RAM MEMORY

"Reset and Interrupt Vectors

IRQ:
XIRQ:
SWI:
lOT:
COPS:
COPS1:
RESET:

ORG

$FFF2

FDB
FDB
FDB
FDB
FDB
FDB
FDB

GDATA
START
START
START
START
START
START

END

IIRQ· EXTERNAL PIN
IXIRQ PIN (PSEUDO-NONMASKABlE)
SOFTWARE INTERRUPT
IllEGAL OPCODE TRAP (START OVER)
COP FAilURE (RESET)
COP CLOCK MONITOR FAil (RESET)
RESET

THE END

Ji#ifi EE

1-268

DECREMENT COUNT
COUNT=O?
CHECK FOR lAST DIGIT

r;.JI~

iF'====':=
-------i::""":i--=:i-F-= ==
~

----

---~

--

Programmable Peripheral
Application Note 041
Detailed Step-By-Step Design Implementation
of an M68He11 and I'SD311 or I'SD311 R
By Stave Torp - Motorola Ssmlconductor and Karsn SPll$llnJ - WSI, Inc.

Introduction

The purpose of this application note is to show the steps involved in moving from an OTP
M68HC711 or expanded mode M68HC11 multi-chip solution to a two-chip solution using an
expanded mode M68HC11 and a WSI PSD311 or PSD311 R (SRAMless) Programmable
MCU Peripheral. This two-chip approach provides many advantages such as increased
system flexibility and several options for more EPROM and SRAM memory while
maintaining low power system needs.
The main areas to consider when implementing the two-chip M68HC11 and WSI PSD311
solution are discussed below. They are mapping the PSD in the M68HC11 address
space, configuring the PSD using the PSD-SILVER software package, modifying the
microcontrolier code as necessary, and programming the PSD.

M68HC11
Expanded Mode
Considerations

An important advantage of the M68HC11 is that it has many subsystems. They are AID,
E2PROM, synchronous peripheral interface (SPI), and serial communications interface
(SCI). As a result, these subsystems will have to be defined by the system designer in the
address map. In addition, the system design must also incorporate memory and 1/0
mapping definitions.
A typical single-chip OTP design could incorporate an M68HC711 E9 and specific system
1/0. The M68HC711 E9 has 8-bit AID, 512 bytes E2PROM, one SPI, and one SCI as well as
12K bytes of EPROM and 512 bytes of SRAM. A total of 38110 lines are available for the
user to define in the system.
The OTP M68HC711 E9 mapping is specified in Motorola's M68HC11 Reference Manual.
The E2PROM and EPROM are directly mapped at $B600-$B7FF and $DOOO-$FFFF,
respectively. The 64 byte register block and the SRAM areas, however, do require some
consideration. The 64 byte register block specifies the SPI, SCI and 1/0 Ports. After reset, it
is located at $1 000-$1 03F. However, the register block can be relocated, if necessary, on
any 4K block boundary anywhere within the 64K address space. The INIT register is written
to at location $103D but to do this keep in mind there is a time protection limitation of 64
clock cycles out of RESET.
The other area to be considered for mapping is the 512 byte SRAM. After reset, the default
mapping of the SRAM is at $0000-$01 FF but it can also be relocated anywhere in the 64K
address space on a 4K byte boundary by modifying the INIT register.
A typical expanded OTP or ROM less M68HC11 design places address and data signals on
the M68HC11 Port B and Port C pins so it can address 64K bytes of external memory.
Higher-order address bits are output on the Port B pins and lower-order address bits and
the 8-bit data bus are multiplexed on the Port C pins. The AS pin provides the control output
used in demultiplexing the low-order address at Port C. The R/W pin is used to control the
direction of data transfer on the Port C bus. To convert from single-chip to expanded mode
on the M68HC11, simply pull the MODA pin HIGH to Voo.

1-269

PSD3XX - Application Note 041

M68HC11
Expanded Mode
Considerations
(Cont.)

In multi-chip expanded mode designs, an external latch such as a 74HC373 is normally
required with the microcontroller to demultiplex the address from the data. In addition, some
address decoding would have to be defined for memory and peripheral mapping which can
be done in discrete logic, such as by using a 74HC138, or a simple PLD such as a 16V8 or
22V10. And finally, if additional direct mapped I/O is required in expanded mode, additional
logic components will be necessary such as transparent latches, i.e., 74HC374, 74HC341,
and 68HC24.
Figure 1 illustrates the two-chip configuration with the M68HC11 in expanded mode. The
PSD311 or PSD311 R integrates 32K bytes of EPROM, an optional 2K bytes of SRAM, a
demultiplexing latch, programmable address decoding, other programmable logic, and 19
user-configurable I/Os. As a result, the functionality in the PSD incorporates the
components that would be necessary in a cumbersome multi-chip configuration by
integrating on-chip the demultiplexing latches and address decoding. The PSD also
integrates the EPROM and reconstructs the two ports of I/O that are lost when placing the
M68HC11 in expanded mode.
The interface of the M68HC11 with the PSD is quite simple. The address/data bus
(ADO-7 and A8-15) from the expanded mode M68HC11 Ports Band C map directly to the
address/data bus of the PSD (ADO-7, A8-15). The RIW, E, and AS from the M68HC11
map directly to the E/DS, RIW, and ALE/AS of the PSD. The RESET pin on the PSD will be
tied to the RESET of the M68HC11. Since the PSEN pin on the PSD311 is not used, it will
be tied HIGH. Finally, the 19 configurable I/Os and A19/CSI will be available to be used to
reconstruct the M68HC11 Ports Band C and for additional expansion.
The address mapping for expanded mode designs is similar to the OTP design, but now the
external memory and peripheral I/O need to be considered. The external memory and I/O
should be mapped to avoid conflicts with internally mapped resources. If there is a conflict,
the internal resources always have priority and the address and data will not be presented
externally. Keep in mind the interrupt vector assignments are located at $FFCO - $FFFF
and must be physically mapped at these locations.

Figure 1. Two-Chip Configuration with PS0311 and M68HC11In Expanded Mode

68HC11
XT
EX

---

........
........

........

PSD3XX
PCO-7

ADO-7/AO-7

PBO-7

ADS-1S/AS-1S

PCO-2

........

IRQ
XIRQ
MODA
MODB
PAO-7

VCC
E

E
RiW
PSEN
AS

RJW
PEO-7

AS
PDO-6
VRH
VRL

RESET

PAO-7

PBO-7

........
+--+

RESET
A19/CSi

--

-1-~-ro---------------------------~~~~------------------------------

PSD3XX - Application Nots 041

M68HC11
Expanded Mode
Considerations

In the two-chip configuration of the PSD and M68HC11, the memory and peripheral 1/0
mapping in the PSD device is achieved using the WSI PSD software. There are two
software packages available.

(Cont.)

PSD-SILVER software supports the PSD3XX devices and includes the MAPLE and
MAPPRO software modules which run under the DOS platform. MAPLE software is used to
configure the PSD chip. It features simple menu driven commands for selecting different
device configurations. It also provides mapping of the EPROM, SRAM, and chip select
outputs into the user's address space, and locates the files to be programmed into the
EPROM segments. MAP PRO enables the user to program the PSD on a WSI MagicPro III
programmer.
The second software package, PSDsoft™ (WS7001 or WS7002), supports the PSD3XX,
PSD4XX, and PSD5XX families and runs under MicroSoft® Windows®. It includes
PSDabel, PSD configuration, PSD compiler, PSDsiios III simulator and PSD programming
software. The PSDsoft environment allows design and simulation of the PSD on-chip PLD
logic under Data 1/0 ABEL, PSD interface selections to any MCU, configuration of the 1/0,
and address mapping of the EPROM and SRAM memory, among other things.
For simplification, a step-by-step procedure for configuring the PSD311 or PSD311 R using
the PSD-SILVER software is shown below.

Configuring
ThePSD311
With The
PSD-Silver
Software

Before the PSD311 is configured to interface with the M68HC11, the rest of the system
requirements need to be defined. Of course, the memory and 1/0 port mapping will be
needed. In addition, the PSD311 can integrate some chip-select and glue logic, which can
help reduce other logic components on the board. These should be specified by the user in
the application.
The following example shown in Figures 2 and 3 will illustrate an application that reads
eight simple DIP switches and display the values on two 7-segment LEDs. The first
schematic uses a single-chip OTP M68HC711 E9. The second schematic is a simple
conversion to the ROM less M68HC11 E1 used with the PSD311 and is functionally
equivalent. In the second example, the PSD-SILVER software is used to configure the
PSD311 to support this application. The PSD-SIL VER's ease-of-use illustrates the flexibility
of the PSD which will be demonstrated below.
The second example with the PSD311 will include mapping for 12Kbytes of the 32Kbyte
EPROM that is available for program storage, 2Kbytes of SRAM for data storage included
on-chip, and 16 general-purpose MCU 110 pins. Additional system enhancements that could
require chip select or additional logic can also be incorporated in the PSD311 PLD arrays.

-------------------------------------~~~------------------------------------1·271

I'SD3XX - AppllClltl,n ,1,te 041

Conflgullng
ThePSD311
With The
PSD-Sllref
Software

Figure 2. Single-Chip M68HC111E9 Example Application
+5V

+sv
tOkO

(C,nt.)
M68HC711E9

PB7
PBI
PBS
PB4
PB3
PB2
PBt
PBO

Flgul1I3. Twin-Chip M68HC11E1/EO With The Wli PS03ff
Example Application
MI8HCtt EtlEO

PORTB

PORTC

+5V
tOkO

PSD311

A06 -AOtSI
AI -At5

PA7
PAl

ADO -A071
AO -A7

PAS

PB7
PBI
PB5

PM

PB4

PA3

PB3
PB2
PBt
PBO

PAZ
PAt
PAO

-----------------------------~~.~--------------~-----------1-272
'Ii!I j

PSD3XX - Application Not, 041

Configuring
ThePSD311
With The
PSD-Silver
Software
(Cont.)

The PSD-SILVER software menus for the PSD311 are illustrated and described on the
following pages for this application. Figure 4 shows the PSD-SILVER MAPLE MAIN menu.
It is invoked by typing MAPLE at the DOS prompt when in the WSI\MAP subdirectory. It
lists the function keys and their associated operations. F1 suspends the MAPLE software to
DOS for file editing or updating. F2 exits the program and returns the user to the DOS
environment. F3 selects the programmer option so the user can program the compiled
object file into the PSD311 device when a WSI MagicProRIil programmer is connected to
the system. The LOAD selection, (F5), loads an existing PSD configuration into the MAPLE
environment for editing and recompiling. F6 saves that program under a user-defined
name. F7 compiles the user-generated file into an object file that can be transferred to the
programmer. Fa provides part type selection - in this case, the PSD311.

Figure 4. PSO-Silver MAPLE Main Menu

After selecting PARTNAME, Figure 5 illustrates a second menu that appears to the right of
the MAIN menu. The list shows ALIASES, CONFIGURATION, PORT C, PORT A, PORT B,
and ADDRESS MAP. The designer selects each choice, starting from ALIASES, and moves
down through the list configuring each option. The ALIASES menu shown in Figure 6 lets
the user individually define the port pins with user-relevant names. In this example, we will
not enter any alias names.

-----------------------------------~~~----------------------------------1-273

PSD3XX - Application Nots 041

Configuring
ThePSD311
With The
PSD-Si/ller
Software

Figure 5. PSO-Silver Main Menu for Configuring the PSD311

(Cont.}

Figure 6. Aliases Menu for Ports Band C

-1.-2-74----------------------------~~Ar-------------------------------

PSD3XX - Application Nots 041

Configuring
ThePSD311
With The
PSD-Silver
Software
(Cont.)

Figure 7 shows the CONFIGURATION menu which is accessed by selecting
CONFIGURATION in the MAIN menu. In our example, the PSD311 has been configured for
use with the M68HC11 E1, i.e., the 8-bit address/data bus is multiplexed. The chip-select
input is chosen rather than the A 19 input. The RESET polarity is active LOW, the ALE (AS)
polarity is active HIGH, and RIW and E control inputs are enabled. The inputs A 16-A19 are
transparent and the EPROM and SRAM share the same 64K address space (combined
memory mode).

Figure 7. PSD Configuration Menu with the M68HC11 Interface

After the device interface is configured, the PSD311 Port C can be set up. If the MAIN
menu is invoked from the CONFIGURATION menu by pressing F1, PORT C can be
selected as shown in Figure 5. As shown in Figure 8, the individual selection of CS/Ai
configures the three pins as chip-select outputs CS8, CS9, and CS10. The chip-select
equations are specified by selecting F3 for the chip-select definition and entering logic
HIGH, LOW, or "don't care" conditions in the column of the logic inputs that you need
"AND"ed together. For example, if a chip-select is needed at location $5800-$5FFF,
entering 01011 in the row under A 15, A 14, A 13, A 12, and A 11 results in the following active
low chip-select equation as shown created: CS8 = !A 15 & A 14 & !A 13 & A 12 & A 11. Port C
can also be used for general purpose logic inputs to create programmable logic output
equations or it can be used to extend the address space of a microcontroller by bringing in
A16, A17, and A18. If the Port C pins are not needed for any of these functions, leave them
as chip select outputs and don't specify any equation.

--------------------------------~~~~-------------------------------1-275

PSD3XX - Application Nots 041

Configuring
ThePSD311
With The
PSD-Sil,ler
Software

Figure 8. Example of Port CConfiguration for Chip-Selects

(Cont.)

Figure 9 shows the PSD311 PORT A in the Address/IO configuration. Since the
M68HC11 E1 Port B is output only and will be reconstructed on the PSD311 Port A, all eight
of the PSD311 Port A pins will be configured as I/Os with CMOS outputs and the data
direction register for the PSD311 Port A will be set to 'FF' to position it for outputs. If these
eight outputs are not needed, one of the alternate configurations for the PSD311 Port A is
Lower Order Latched Address bits which includes an internal output latch on Port A.
Figure 10 gives the PSD311 PORT B selection as eight I/Os with CMOS outputs which will
reconstruct all eight bidirectionall/Os on the M68HC11 E1 Port C. The direction of the
individual I/O pins in the PSD311 Port B is determined by the original OTP application. The
direction is set by writing to the data direction register. To make a pin an input, the
appropriate bit in the register must be cleared and to make a pin an output, the appropriate
bit must be set. If all eight I/Os are not needed, the alternate configurations for the PSD311
Port B pins are chip selects.

-'-~-~-6-------------------------------~~~~-----------------------------------

PSD3XX - Application Note 041

Configuring
ThePSD311
With The
PSD-Silver
Software

Figure 9. Port A Configuration for All Eight Pins as /IDs

(Cont.)

Figure 10. Port B Configuration for All Eight Pins as I/Os

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FEE #!fff
~.,.-------------------

1-277

,soaxx- Application Not, 041
Configuring
The I'S0311
With The
I'SD-Silrer
Software
(Cont.)

Figure 11 shows the ADDRESS MAP menu. The designer can enter a binary code for the
address range assignments of the various select lines or a hexadecimal starting and
stopping address can be entered to locate the memory and peripherals within the
M68HC11 E1 address space. ESO-ES7 are the chip-selects for the eight 4Kbyte EPROM
blocks, RSO is the chip-select for the 2Kbyte SRAM, and CSP is the chip-select for the
CSIOPORT base address. A space for individual hexadecimal files to be programmed into
the PSD311 EPROM is reserved under the FILENAME section. The M68HC11 E1 code
listed under the FILE NAME "68HC11.hex" must be in Intel MCS hex format. If Intel MCS
hex format is not available, a conversion program to convert Motorola S records to Intel
MCS hex is included with the PSD-SILVER software package.

Figure 71. Address Map Menu for Selecting Address Locations of CSIOPORT
(Ports A and Bl, EPROM, and SRAM

EFFF
FFFF

68HCl1.HEX
68HC11.HEX

In our application example, three 4Kbyte sections of code for a total of 12Kbytes of EPROM
will be mapped from $DOOO-$FFFF. The filename with the code is called 68HC11.HEX and
is located in the same directory as the MAPLE software. The additional PSD311 SRAM will
be located at $3000-$37FF and the CSIOPORT base address will be at location $2000.
After the configuration has been established, the user can return to the MAIN menu and
SAVE (F6) the PSD311 configuration. Saving the configuration creates a filename.SV1 file
which documents all of the selections made during the configuration process. The file
created from our example is shown in Figure 12.

------------------------~rff----------------------1.278
'Ii1l.

PSD3XX - Application Note 041

Configuring
ThePSD311
With The
PSD-Silver
Software
(Cont.)

Figure 12. Example Configuration Output File for PSD311
*************************** MAPLE 6.21

GLOBAL CONFIGURATION
Address/Data Mode:
Data Bus Size:
CSI/A19:
Reset Polarity:
ALE Polarity:
WRD/RWE:
A16-A19 Transparent or Latched by ALE:
Are you using PSEN?

MX
a
CSI
LO
HI
RWE

T
N

PORT A CONFIGURATION (Address/IO)
Bit No.

AilIO

o

~
~

1
2
3
4
5
6
7

10
10
~

~

10
10

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

PORT B CONFIGURATION
Bit No.
0
1
2
3
4
5
6
7

CS/IO

10
10
10
10
10
10
10
10

CMOS/OD
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

CHIP SELECT EQUATIONS
************************************************************************

PORT C CONFIGURATION
Bit No.

CS/Ai

o

csa

1
2

CS9
CS10

CHIP SELECT EQUATIONS

/csa

= /(lA15 * A14 * /A13 * A12 * A11)

************************************************************************

-----------------------------------------f==~~---------------------------------------====

1-279

PSD3XX - Appllatlon No'" 041

Configuring
ThePSD311
With The
PSD-Silller
Software
(Cont.)

ADDRESS MAP

ESO
ES1
ES2
ES3
ES4
ES5
ES6
ES7
RSO
CSP

A
19
N
N
N
N
N
N
N
N
N
N

A
18
N
N
N
N
N
N
N
N
N
N

A
17
N
N
N
N
N
N
N
N
N
N

A A A A A A SEGMT
16 15 14 13 12 11 STRT
N 1 1 a 1 N 0000
N 1 1 1 a N EOOO
N 1 1 1 1 N FOOO
N
N
N
N
N
N
N
N
N
N
N a a
1 a 3000
N a a
a a 2000

SEGMT
STOP
OFFF
EFFF
FFFF

EPROM
START
dOOO
eOOO
fOOO

EPROM
STOP
dfff
efff
ffff

FileName
68HC11.HEX
68HC11.HEX
68HC11.HEX

37FF
27FF

******************************** ADDRESS MAP (EQUATIONS) ********************************

=
=
=
=
=
=

ESO A15 * A14 */A13 * A12
ES1
A15 * A14 * A13 */A12
ES2 A15 * A14 * A13 * A12
ES3
ES4
ES5
ES6 =
ES7 =
RSO = IA15 */A14 * A13 * A12 */A11
CSP
IA15 */A14 * A13 */A12 */A11

=

************************************************ END ************************************************

Finally, the user will invoke the COMPILE (F7) option. The compile option merges the
P$D configuration information with the code that would normally be programmed into
the EPROM to create one output file with a filename.OBJ extension.

~1.~n~o--------------------------~Jr~----------------------------

PS03XX - Application Note 041

Software
Considerations

The code for the M68HC11, when transitioning from an OTP single chip version to a
twin-chip ROMless M68HC11 version and a PSD311, will need to be changed slightly if
reconstructing the M68HC11 Ports Band C to the PSD311 Ports A and B as in this
example.
The two eight-bit I/O port address locations are remapped from the M68HC711 64 byte
register block area to the PSD311 chip-select I/O port base address (CSIOPORT) by using
offsets from this base address. The tables below show the offset with the PSD311 base
address of $2000 appended to form the physical addresses as appropriate for this
example.

M68HC11 PO" B

Maps To

Reglstel Name

Physical Location

Reglstel Name

Physical Location

DDRB
PORTB Data Write
PORTB Pin Read

$1004
$1004

Direction
Data Write/Read
Pin Read

$2004
$2006
$2002

PSD311 Po" A

M68HC11 PO" C

Maps To

Reglstel Name

Physical Location

Registsl Name

Physical Location

DDRB
PORTB Data Write
PORTB Pin Read

$1007
$1003
$1003

Direction
Data Write/Read
Pin Read

$2005
$2007
$2003

PSD311 Po" B

The code differences this translates to can be illustrated with the sample code for both the
single chip M68HC711 E9 and then for the twin chip M68HC11 E1 and PSD311 solution as
shown below.

Single-Chip M68HC711E9 Code
ORG
LDAA
STAA
STAA
LDAA
STAA
BRA

$DOOO
#$00
$1007
$1004
$1003
$1004
$DOOO

"Set M68HC11 Port C pins to inputs
"Turn off all LED segments
"Read port C dip switches
"Turn on or off the appropriate LED segments
"Continue to read Port C and display on Port B

Twin-Chip Solution M68HC11E1 Code
ORG
LDAA
STAA
LDAA
STAA
STAA
LDAA
STAA
BRA

$DOOO
#$FF
$2004
#$00
$2005
$2006
$2003
$2006
$DOOO

"Note: M68HC11 Port B are outputs only
"Set PSD311 Port A to all outputs
"Set PSD311 Port B for all inputs
"Turn off all LED segments
"Read the PSD311 Port B pin register
"Turn on/off the appropriate LEDs
"Continue to read Port B and display on Port A

----------------------------------~~~~--------------------------------1-281

PSD3XX - Application Note 041

Programming
ThePSD311
OrPSD311R

The PSD311 or PSD311 R is programmed with the file that is generated during the
COMPILE section of the PSD-SILVER MAPLE software. It usually has a filename.OBJ
extension. The file is then loaded into programmer RAM on either a WSI MagicPro III
PC-compatible programmer or an industry-standard programmer. Then the PSD device is
ready to be programmed which is very similar to programming a standard EPROM or PLD.
Figure 13 shows the menu for programming the PSD devices using the MAP PRO (F3)
option from the MAIN menu.

Figure 13. MAPPRO Programming Software

Iii'

aa

MAPLE

, , ..,,\!!IS'~!i9~(:p~i(lm)'pmgt~r·"7 vlay RAM' ~iIk

,:,iWIlAM

.,.,.

",::i}~~~!'
':ili:l~rlIm

;"@~4.
, l;e1ect option; _:.,

- - - - - - - - - - - - - - - - - - f ' = - =~-----------------1-282

PSD3XX - Application Nots 041

Programming
Manufacturers

Conclusion

Several of the programming manufacturers that support PSD devices are listed below.
Many of their programmers have been officially qualified by WSI.
WSI
(510) 656-5400
(800) 832-6974

Data 1/0
(800) 426-1045
(800) 247-5700

Advin Systems
(408) 243-7000
(800) 627-2456

B&C Microsystems
(408) 730-5511

BP Microsystems
(713) 688-4600

Bytek
(800) 523-1565

Link Computer
(201) 808-8990

Logical Devices
(303) 279-6868

Needham's Elec
(916) 924-8037

SMS
(206) 883-8447

Stag Microsystems
(408) 988-1118

Sunrise
(909) 595-7774

Systems General
(408) 263-6667

Tribal Microsystems
(510) 623-8860

Implementing a two-chip solution with the M68HC11 E1 and a PSD311 or PSD311 R has
been shown to be a simple process requiring very little code conversion or hardware
modification. As demonstrated, this alternative to using a single-chip OTP M68HC711 or
expanded mode multichip M68HC11 configuration offers flexible integration and can
provide extra memory, logic, and 1/0 to further enhance your system capabilities.

-----------------------------------~~~----------------------------------1-283

PSD3XX - Application Nots 041

-1-~-84-----------------------------~~~--------------------------------

PSD3XX Family

ZPSD3XX Family

PSD4XX/5XX Family

Motorola Application Notes

Sales Representatives
and Distributors

Section Index
ZPSD3XX Family

Application Note 034

ZPSD Power Consumption Calculations ....................................... 2-1

For additional information,
Call800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363

Programmable Peripheral
Application Note 034
IPSO Power Consumption Calculations
By Yoram Cedar

Zero Power

PSD

Background

Portable and battery powered systems have recently become major embedded control
application segments. As a result, the demand has increased dramatically for electronic
components having extremely low power consumption. Recognizing this need, WSI, Inc.
has developed a new ZPSD (Zero Power PSD) technology for use in low power
programmable Microcontroller peripheral circuits.
ZPSD products virtually eliminate the DC component of power consumption reducing it to
standby levels (~A). Eliminating the DC component is the basis for the words" Zero Power"
in the ZPSD name. ZPSD products also minimize the AC power component when the logic
is changing states by using address transition detection, array partitioning and DPTL
(Differential Path Transistor Logic) design techniques. The result is a programmable
microcontroller peripheral family that replaces memory, PLD and discrete logic functions
while drawing much less power than a single EPROM.

Zero Power

PSD

Operation

Upon each address or logic input change to the ZPSD device, the internal logic powers up
from low power standby for a very short time period. During this power up cycle, the ZPSD
consumes only the necessary power to deliver new logic or memory data to its outputs as a
response to the input change. After the new outputs are stable, the ZPSD latches them and
automatically reverts to standby mode.
The Icc current consumed during standby mode and during DC operation (chip enabled,
no toggling) is identical and is only a few microamps (~A). The ZPSD automatically
reduces its DC current drain to these low levels and does not require controlling by the
CSI (Chip Select) input. Disabling the CSI unconditionally disables the MCU interface
causing the PSD to power down independent of any transition on the microcontroller bus
(address, data and control). In the ZPSD3XX family, disabling the CSI input will power
down the entire device while in the ZPSD4XX/5XX products, the memory and address
decoding PLD will power down and the GPLD/PPLD will consume power based on logic
input changes in the system.
The ZPSD contains the first architecture to apply zero power techniques to memory circuit
arrays as well as logic.
Figure 1 describes the operation of the ZPSD compared to the operation of a discrete
solution. A standard microcontroller (MCU) bus cycle usually starts with the generation of
an address and an ALE (or AS) pulse. The ZPSD detects the address transition and powers
up internally. The ZPSD then latches the outputs of the PLD, EPROM and SRAM to the
new values. After finishing this operation, the ZPSD then turns off its internal power and
enters standby mode.

2-1

ZPSD3XX -

Application .ot. 034

ZerDI'Dwer

Figure 1. IPSD PDwer OperatlDn

I'SD
OperatlDn
(Cont.)
ALE

SRAM
ACCESS

EPROM

ACCESS

EPROM

ACCESS

Icc

TIME

The ZPSD will remain in standby mode if the address does not change between bus cycles
(for example, looping on a single address or during a Halt operation). The time taken for the
entire operation is less than the ZPSD "access time" and much less than the MCU bus
cycle (ALE to ALE). The only significant power consumption in the ZPSD occurs during AC
operation and can be calculated using the ALE frequency.
An alternate system implementation using discrete EPROM, SRAM, PLD, latches,and other
individual components will consume operating power during the entire bus cycle.
The ZPSD power consumption is controlled by the Turbo and Cmiser bits. Their operation is
described in each ZPSD data sheet. In general, the Turbo bit controls the power
consumption and speed of the ZPLD while the CMiser bit controls the power consumption
and speed of the EPROM and SRAM. Each ZPSD data sheet provides the power
consumption of each mode of operation using the Turbo and Cmiser bits in the DC
electrical characteristics section.
In addition, each PSD4XX and PSD5XX data sheet describes the operation of the Power
Management Mode Registers (PMMR) that enable controlling the power consumption of
various internal functional modules in those devices. For detailed explanation of the
PSD4XXl5XX PMMR and APD operation please refer to Application Note 030.
Following are examples of the AC/DC Parameter tables and power consumption graphs of
the ZPSD devices.

--------------------------~§F~
2.2
'l!!lfS - - - - - - - - - - - - - - - - - -

Zl'SD3XX - AppllcatlllR NIt. 034

ZPSD3XX DC Characteristics - Commercial
(5 V:I: 10%)

SymbDI

Parameter

CDndltlDns

vee

Supply Voltage

All Speeds

VIH

High-Level Input Voltage

4.5V5.5V

VIL

Low-Level Input Voltage

4.5 V < Vee> 5.5 V

VOH

Output High Voltage

VOL

Output Low Voltage

ISB

Standby Supply Current

CSI > Vee -.3 V

III

Input Leakage Current

Vss < VIN > Vee

ILO

Output Leakage Current

.45 < VIN > Vee

Icc (DC) Operating Supply Current

Min

Typ

4.5

5

Max

Unit

5.5

V

2

Vee +.1

V

-0.5

0.8

V

IOH = -20 IJA, Vee = 4.5 V

4.4

4.49

V

IOH = -2 mA, Vee = 4.5 V

2.4

3.9

V

IOL = 20 IJA, Vee = 4.5 V

0.01

0.1

V

IOL=8mA, Vee=4.5V

0.15

0.45

V

10

20

IJA

-1

:1:.1

1

IJA

-10

:1:5

10

IJA

ZPLD_TURBO = OFF, f = 0 MHz

10

20

IJA

ZPLD_TURBO = ON, f = 0 MHz

0.5

1

mA/PT

ZPLDAC Base

(See Figure 2)

EPROM Access
ACAdder

CMiser = ON and 8-Bit Bus Mode

0.8

2.0

mAlMHz

All Other Cases (Note 4)

1.8

4.0

mAlMHz

CMiser = ON and 8-Bit Bus Mode

1.4

2.7

mAIM Hz

SRAM Access AC Adder

CMiser = ON and 16-Bit Bus Mode

2

4

mA/MHz

3.8

7.5

mA/MHz

Icc (AC)

CMiser=OFF

mA/MHz

NOTES: 1. CMOS inputs: GND ± 0.3 V or Vee ± 0.3V.
2. TTL inputs: VIL S 0.8 V, VIH :a: 2.0 V.
3. eSl/A19 is high and the part is in a power-down configuration mode.
4. All other cases include eMiser = ON and 16·bit bus mode and eMiser = OFF and 8- or 16·bit bus mode.

----------------------------------~~~----------------------------------~.

~~~~---~-----

--~

H

ZPSD3XX - Application Note 034

leroPower
PSD
Operation

Figure 2.1PSD3XX PAD ICC vs. Frequency

(5 V ± 10%)

(Cont.)
45

......

---,-

~

5
40

V

35

30

V

-

--'
~ ~V
..... ....,.........

,.........

,..,.-

..-:::;:; ~

,......... ,......... \-"'

,......... y10

15

20

25

30

35

40

45

50

BUS FREQUENCY (MHz) - NOT MCU OSC. FREQUENCY

-2.-4------------------------------~~~~------------------------------

ZPSD3XX - Application Note D34

IPSD3XX DC Characteristics - Commercial
(zpSD

vVelSlDII$ Only)

Symbol

(3 V ± 10%)

Parameter

Conditions

vee
VIH

Supply Voltage

All Speeds

High-Level Input Voltage

2.7V < Vee >5.5 V

VIL

Low-Level Input Voltage

2.7V < Vee >5.5 V

VOH

Output High Voltage

3

IOH = -1 rnA, Vee = 2.7 V

2.3

Max

Unit

5.5

V

Vee +.5

V

.3 Vee

V

2.69

V

2.4

V

IOL = 20 IJA, Vee = 2.7 V

0.01

0.1

IOL = 4 rnA, Vee = 2.7 V

0.15

0.45

V

1

5

IJA

-1

±.1

1

IJA

-1

.1

1

IJA

1

5

IJA

.17

.35

rnA/PT

ISB

Standby Supply Current

CSI > Vee -.3 V (Vee = 3.0 V)

III

Input Leakage Current

ILO

Output Leakage Current

VIN = Vee or GND
VOUT = Vee or GND
ZPLD_TURBO = OFF,
f=OMHz (Vee = 3.0 V)
ZPLD_TURBO = ON,
f=OMHz (Vee = 3.0 V)

ZPLD AC Base

See Figure 3 (Vee = 3.0 V)

EPROM Access
ACAdder

CMiser = ON and 8-Bit Bus Mode
(Vee = 3.0 V)
All Other Cases (Note 8)
(Vee = 3.0 V)

SRAM Access AC Adder

2.7
.7 Vee
-0.5

IOH = -20 IJA, Vee = 2.7 V

Output Low Voltage

lee (AC)

Typ

2.6

VOL

lee (DC) Operating Supply Current

Min

V

rnA/MHz
0.4

1

rnA/MHz

0.9

1.7

rnA/MHz

CMiser = ON and 8-Bit Bus Mode
(Vee = 3.0 V)

0.7

1.4

rnA/MHz

CMiser = ON and 16-Bit Bus Mode
(Vee = 3.0 V)

1

2

rnA/MHz

1.9

3.8

rnA/MHz

CMiser = OFF (Vee = 3.0 V)

NOTES: 5. eMOS Inputs: GND '*' 0.3 V or Vee '*' 0.3V.
6. TTL inputs: VIL S 0.8 V. VIH <: 2.0 V.
7. eSI/A19 is high and the part is in a power·down configuration mode.
8. All other cases InClude eMiser = ON and 16·bit bus mode and eMiser = OFF and 8· or 16-bH bus mode.

"q~
-------------------------------~L·-----------------------------2--~

lPSD3XX - Appllcatlan Nats 034

leroPower

Figure 3. Typical PLO AC ICC Curve (Vee =3.0 V)

PSD

Operation

ZPS03XXV

(Cant.)

L.-- v.

a
14

,....1.5

V

~

12 I-

0.5

V

1/

./

P

~

1 23" S

10

/ V /V

V

/

4

2

o

A

p
o

1/
~

,.~
5

V

10

-/'

./

-.6.- 40 PTTurbo

-

~

-C-

15

40 PT Non Turbo
10 PTTurbo
10 PT Non Turbo

20

25

30

BUS FREQUENCY (MHz)

-2--6-----------------------------~~~-------------------------------

ZPSD3XX - Application Not. 034

ZPSD4XX/5XX DC Characteristics
(5V±10%)

Symbol

Conditions

Parameter

vee

Supply Voltage

All Speeds

V IH

High Level Input Voltage

4.5 V < Vee < 5.5 V

Min

Typ

4.5

5

2

Max

Unit

5.5

V

Vee +.5

V

V IL

Low Level Input Voltage

4.5 V < Vee < 5.5 V

-0.5

0.8

V

V IH1

Reset High Level Input Voltage

(Note 1)

.8 Vee

Vee +.5

V

(Note 1)

-.5

.2Vee-· 1

V

V IL1

Reset Low Level Input Voltage

V HYS

Reset Pin Hysteresis

VOL

Output Low Voltage

VOH
V SBY

Output High Voltage

0.3
IOL = 20 IJA, Vee = 4.5 V

0.01

0.1

V

IOL= 8 rnA, Vee =4.5V

0.15

0.45

V

IOH = -20 IJA, Vee = 4.5 V

4.4

4.49

V

IOH = -2 rnA, Vee = 4.5 V

2.4

3.9

V

SRAM Standby Voltage

2.7

ISBY

SRAM Standby Current

Vee = 0 V

IIOLE

Idle Current (VSTBY Pin)

Vee> VSBY

V OF

SRAM Data Retention Voltage

Only on VSTBY

Power Down Mode

CSI >Vee -.3 V (Note 10)

Sleep Mode

CSI >Vee -.3 V (Note 11)

ISB

Standby Supply
Current

III

Input Leakage Current

ILO

Output Leakage Current

lee (DC)

Operating
Supply Current

ZPLD Only

V

0.5

Vee

V

1

IJA

0.1

IJA

25

50

IJA

-0.1
2

V

10

20

IJA

VSS < VIN < Vee

-1

±.1

1

IJA

0.45 < VIN < Vee

-10

±5

10

IJA

400

700

IJA/PT

ZPLD3URBO = OFF,
1 = 0 MHz (Note 12)
ZPLD3URBO = ON,
1=0 MHz

ZPLD AC Base

(Note 12)

EPROM AC Adder

CMiser= ON
(8-Bit Bus Mode)

0.8

2

rnA/MHz

All Other Cases

1.8

4

rnA/MHz

CMiser = ON and
8-Bit Bus Mode

1.4

2.7

rnA/MHz

CMiser = ON and
16-Bil Bus MoDe

2

4

rnA/MHz

3.8

7.5

rnA/MHz

lee (AC)

SRAM AC Adder

CMiser= OFF
NOTES: 9. Reset input has hysteresis. VIL 1 is valid at or below .2Vee -.1. VIH1 is valid at or above .8Vee.
10. eSI deselected or internal PO is active.
11. Sleep rnode bit is set and internal PO is active.
12. See Figure 4 for details.

_______________________________________

JArsraF~

~~~------------------------------------2----7

ZPSD3XX - Application Note 034

Zero Power

Figure 4.

ZPSD4XX/5XX ZPLO ICC vs. Frequency (5 V ± 10%)

PSD

Operation
(Cont.)
- : : ; - PT100%
•

PT25%

120 ,---------------------------------------,
100

«

~------------------------------~~~~~

80 1 - - - - - - - -

.§.
~

60 1""""'-----------

JJ
40 1--------

5

10

15

20

25

BUS FREQUENCY - (MHz)

-~-8-----------------------------~~~~-------------------------------

1PS03XX - Application Note 034

Power
Consumption
Calculation
Oefinitions

ISB

=Icc (DC)

Power Consumption when system is in Standby (idle) mode or
system is operating but none of the ZPSD inputs are changing.

ICC

(AC)

Power Consumption when system is operating and ZPSD
inputs are changing.
= ZPLD AC Base @ f ZPLD (Icc vs. frequency as a function of PT)

+ % of EPROM Access X EPROM AC Adder X f MCU BUS
+ % of SRAM Access X SRAM AC Adder X f MCU BUS
+ Timer AC Adder X f timer (only applicable for the ZPSD5XX)
ZPLD AC Base
@

f ZPLD

ZPLD ICC taken from the graph of the PLD AC curve of
Icc Vs. Frequency @ f ZPLD . Based on the number
of product terms (PT) used and if the Turbo bit is
on or off.
The PT number is shown in the PSDsoft fitting report.

EPROM
AC Adder

= The power consumption of the EPROM as a function of

SRAM
AC Adder

= The power consumption of the SRAM as a function of

Timer AC Adder

frequency.

frequency.
The power consumption of the Timer as a function of
frequency

%ofEPROM
Access

Percent of time the MCU is accessing the EPROM

%ofSRAM
Access

Percent of time the MCU is accessing the SRAM
Maximum ZPLD input frequency

f MCU BUS

MCU bus frequency, usually the ALE (or AS) frequency

ftimer

Maximum Timer input frequency

-----------------------------------~~~jf----------------------------------2-9

ZPSD3XX - Application Nots 034

Typical
Operating
Power
Calculation
Example of
ZPSD3XXat
Vce =5.0V

This example is based on the ZPSD3XX data sheet of June, 1995. Please review the
specification of the particular ZPSD device you are using before calculating actual power
consumption in your design.

Example Criteria
- f ZPLD =f MCU BUS

2 Mhz

- % of EPROM Access

80%

- % of SRAM Access

15%

- % of I/O Access

5 % (No additional power above the ZPLD AC Base)

- Number of ZPAD Product Terms Used

10 PT

- 8 Bit Data Bus
CMiser
Turbo

On
Off

- EPROM/SRAM access AC mA/MHz adder is found in 5 Volt DC Characteristics
in the ZPSD3XX data sheet.
ISB

= Icc (DC) = 10 IJA

ICC

(AC)

ZPLD AC Base @ 2 MHz (see Figure 18 in ZPSD3XX data sheet)
(.75mA)
+ % of EPROM access x EPROM AC Adder x 2 MHz
(+ 80% x 0.8 mA/MHz x 2 MHz)
+ % of SRAM access x SRAM AC Adder x 2 MHz
(+ 15% x 1.4 mA/MHz x 2 MHz)

=2.45 mA

Example of
ZPSD3XXV
Typical
Operating
Power
Calculations at
Vee =2.7 V

This example is based on the ZPSD3XX data sheet of June, 1995. Please review the
specification of the particular ZPSD device you are using before calculating actual power
consumption in your design.

- f ZPLD

=f MCU BUS

1 MHz
80%
15%
5 % (No additional power above the
ZPLD AC Base)

- % of EPROM Access
- % of SRAM Access
- % of I/O Access
- Number of ZPAD Product Terms Used
- 8 Bit Data Bus
Cmiser
Turbo

10 PT
On
Off

- EPROM/SRAM access AC mA/MHz adder is found in 3 Volt DC Characteristics in the
ZPSD3XX data sheet.
ISB = Icc (DC)
Icc (AC)

=1 IJA

= ZPLD AC Base @

1 MHz (Figure 19 in ZPSD3XX data sheet) (0.30 mAl

+ % of EPROM access x EPROM AC Adder x 1 MHz
(+ 80% x 0.4 mA/MHz x 1 MHz)

+ % of SRAM access x SRAM AC Adder x 1 MHz
(+ 15% x 0.7 mA/MHz x 1 MHz)

= 0.77 mA x 0.9 (Normalized Icc. See Figure 21) = 693 microamps
iF-=:

~=

-2-.1-0----------------------------~~afli-------------------------------

PSD3XX Family

ZPSD3XX Family

PSD4XX/5XX Family

Motorola Application Notes

Sales Representatives
and Distributors

Section Index
PSD4XX/5XX
Family

Application Note 028

PSD5XX CounterfTimers Operation ..............................................3-1

Application Note 029

Interfacing PSD4XX/5XX To Microcontroliers .............................3-73

Application Note 030

PSD4XXl5XX Power Calculations and Reduction .................... 3-145

Application Note 031

PSD4XXl5XX Design Tutorial ................................................... 3-161

Application Note 033

Keypad Interface to PSD4XXl5XX
with Autoscanning .....................................................................3-245

Application 035

How To Design With The PSD4XXl5XX ZPLD ........................... 3-257

Application 036

How To Fit Your Design Into The PSD4XXl5XX ......................... 3-265

Application 037

How to Implement a Latch Function in Port A
of PSD4XXl5XX that is Independent of the System Clock .......... 3-271

Application 038

How to Increase the Speed of the
PSD5XX Counter/Timers ...........................................................3-277

Application 039

Encoder for Shaft Direction and Position Recognition
Using the PSD5XX ..................................................................... 3-287

Application 042

Four Axis Stepper Motor Control
Using a Programmable PSD5XX
MCU Peripheral from WSI, Inc ................................................... 3-297

For additional information,
Call800-TEAM-WSI (800-832-6974).
In California, Call 800-562-6363

Programmable Peripheral
Application Note 028
PSD5XX Counter/Timers Operation
By Barl Kumar

Abstract

This application note explains the operation
and programming of CounterfTimers on
WSI's PSD5XX Family of FieldProgrammable Microcontroller Peripherals.

Initializations required to implement each of
the five modes of operation of
CounterfTimers are explained. Refer to
appendices for all the relevant files.

Introduction

The PSD5XX on-chip CounterfTimers
provide additional Timer functions to a
Microcontroller.

0 Each CounterfTimer can be controlled

A typical Microcontroller or a Timer
Peripheral chip usually has a set of Timers
controlled by either

0 The Watchdog output is routed

o
o

through the ZPLD and can be
programmed to output at any PSD
output pin.

External Pins
Software

0 Programmable polarity for input control

The PSD5XX has four identical 16-bit
CounterfTimers. Each CounterfTimer is
controlled by either

o
o
o

by an input pin, dedicated PPLD
macrocell or software.

PPLD* outputs

and Timer output.

0 Can be programmed to be UP or
DOWN Counters.

0 Input clock to all CounterfTimers can be

External Pins

from DC to 7.0 MHz. Higher resolution
can be achieved by using in conjunction
with the GPLD macrocells.

Software

Figure 1 shows the I/O pins and the
functional block of the CounterfTimers.

0 High resolution Divisor unit to scale
down the CounterfTimer input clock.

ThePPLD
The Peripheral Programmable Logic
Device (PPLD) provides a powerful
mechanism for the user to control the
operations of the CounterfTimers and the
Interrupt Controller. There are six
Peripheral Macrocells in the PPLD, four are
dedicated to the CounterfTimers, and two
to the Interrupt Controller. Figure 2 shows a
PPLD macrocell for the CounterfTimers.

0 Can easily interface with any 8 or 16-bit
Microcontroller.

o

Terminal Count of each CounterfTimer
can be configured as interrupt input to
the Interrupt Controller.

The PSD5XX CounterfTimers have the
following features:

o

Five Modes of operation

-

Wa'llltonn Mode
PulsaMode
E'IIInt Counte, Mode
Time CaptulB Mode
Watchdog Mode

"Refer to the section "ZPLD Block" in the PSD5XX date sheet.

3-1

- -_ _ _ _ _ _ _

~

_________

-0-

nat

Co>

~

1·a
'"
:;

.....

Q'
::a

i~

)oii
I

~

"Ii

;;::

&1

::t

8
1=

~I;r
~

ciS'

!iii

TIMER
OU
PAl

ADDRESS/DATA/CONTROLBUS

CLOCK INJ PROGRAMMABLE
CLOCK
PRESCALER

0

PRESCALED
CLOCK IN

"Q
II~IIIII

~I.I
11iII-~

TIMER [3 : OI_IN

PIN!
MACROCELL ..
COMMAND
INPUT

PORT
E

~
MC2TMR [3 : 01

TCO-TC3
'---

ZPLD
INPUT
BUS

PPLD

~
CONTR

r-.

r--

---..'

BUS
INTRF

--

I
I
I

I
I

----------- ...

GLOBAL
CMDREG

DLCY REG

TIMER
MACRO· ~tCELL

~1 I

HI

r-: I
f-.'
r.'I
I
I

FREEZE
CMD REG

STATUS
REG

COUNTERI
TIMER 0
CTUO
COUNTERI
TIMER 1
CTUl

I
I

CTU2

+

M~ci:o.

PT21NT [4 : 51

INTERRUPT
CONTROLLER

INTR2PLD

-

~---------------------------------WDOG2PLD

,
I
I

I
I
I
I

I

I

'----

PORT
B

I

MC2INT[6: 71

CELL

-

I

TCO-TC3

-

TIMER
OUTPUTS
PBO-PB3

I

COUNTER!
TIMER 2

I

AND
ARRAY

~-

L :TIMERO_OUT
I :
I: TIMER1_0UT
I

I TIMER2_0UT
I:
,
COUNTER!
I: TIMER3_0UT
TIMER 3
I'
CTU3,
~----------.!
I
I

S'WARE
LOADISTORE

r---

PORT
A

COUNTERmMER
UNIT

I

r---

-

I
I

I
I

I
I
I
I

--------------------------------------

'--

fIi

:"4

"
Ii

if

~

::!

.
"ar
I

;r

ai
i

~

~

:::i'

st
ar
;r
i:l
!!.

!!

g

=-ar
~

fit

~

CIO

ala
~a

tC"a

::!"

Q'

:::a

::!!

';;=

~
TIMER_CLOCK
(PRESCAlED ClK)

TIMER
INPUT PIN

;:
Ii;

TIMER [3 : OJ_IN
ZPlD
INPUT
BUS

"--

r---------------------PTT-O

Ii

PTT-1~

~

~

a

I
I

~

I
MC2TMR*

I

~

INPUT
MUX

I

MUX
AND
ARRAY

D

~I
COUNTERI
nMER

PR

Q

t'
g.

.=
&'

C Q

•abl FILE

BIT50F
COMMAND REGISTER

~
if
!It

;J

WDOG2PlD (INTERNAL FEEDBACK)

it
~

ClKlN

RESET

;&I
...

I

*These are four similar Macrocells with outputs MC2TMR[3:0J

t

l;::

fitr::t
I
f

;r

~

2CI6

PS05XX - Application Note 028

Introduction
(Cont.)

The PPLD (Cont.)
The Operation of a Counterffimer Unit
The basic functional block of a CounterfTimer Unit (CTU) is shown in Figure 4. It consists
of a 16-bit up/down Counter and a 16-bit Image Register. The Counter performs a counting
operation such as generating a waveform output or counting the event occurrence of an
input signal. The Image Register serves as an interface register for the Counter. For
example, in Pulse Mode the length of the pulse width is stored in the Image Register. When
activated, the Counter is loaded with the contents of the Image Register and generates a
pulse output with duration defined by the Image Register. But in the Event Count Mode (or
Time Capture Mode), the number of event count (content of Counter) is stored in the Image
Register so that it can be read by the Microcontroller.
Both the Image Register and Counter can be accessed by the Microcontroller. Usually the
Counter is accessed only for initialization purposes. To access the Image Register when the
Counter is running, you need to first freeze the Image Register via the Freeze Command
Register and wait for the freeze acknowledge bit by reading the Status Flags Register. If the
bit is set, you can then proceed to access the Image Register.

The Counter generates an output if it is configured in Waveform, Pulse or Watchdog Mode.
The Waveform/Pulse output can be routed to an output pin on Port A or B. For Watchdog
output, the signal must go through the GPLD before it is routed to any selected output pin.
For Event Count or Time Capture Mode, the output of the counter is read by the user from
the Image Register.
Figure 3 is the PSD5XX equivalent block diagram depicting the basic input and output
signals of each Counter/Timer unit.

Figure 3. PSD5XX Counterffimer Equivalent Block Diagram

TIMER_CLOCK

EnlDis

....

....

OUTPUT ..

...

(In Waveform, Pulse, Watchdog)

C
0
U
N

T

E
R
TRIGGER
LOAD or STORE

I
M
A

G
E

....

......

FREEZE-AC K

t

IMAGE
FREEZE

-------------------------------------~~------------------------------------3-4

====

~S'

~;:r
..... Q

t

~

::!'
Q'

:::a

I

INIt;t1NAL t'tiU UAIA

PROGRAMMABLE
DIVISOR

CLKINPIN

:i§

.,u::t

I

J

PPLD
}
MACROCELL
TIMER CLOCK

PIN
PE3-6

IlliiiQ:
II111111

Ilklllh
1I111111i

CMDREG.
BIT5
PIN/MC
SELECT

.-'I--

MUX

T

EN/DIS

CONTROL &
MODE UNIT

L

......~

CLK
LOAD
OPERATION

IMAGE
REGISTER

PULSEIWAVE
OR
WATCHDOG

f't.
WATCHDOG
r---

I-- GPLD

_

STORE
OPERATION
LOAD/STORE

EVENT OR
TIME CAPTURE

~
§.

II
....
:::!l

TOPOR:T
A,BOR E

l

!!
Q
~

COUNTER/
TIMER

PUSLEIWAVE
TO PORTA OR B
TCTOPORTE

LOAD/
STORE"

CMDREG.
BIT 7
SOFTWARE
ENIDIS
CMDREG.
BIT6
PIN/MC
LOIST

ENABLEIDISABLE'

.-I-D-

CIi

I

TC
TO
INTERRUPT
CONTROLLER

!SI
1»'

~

;
a

~
§l

iit

.::t
~

ii'

CONTROL

~

~

;D-

CONTROL

"I

~
=:.

:::

5t

SOFTWARE
LDISTREG.

~

cQ'
=:i

~

LOADISTORE

FREEZE
CMDREG.

~

"I

-

• In Time Capture Mode, only software can en/dis CTU.
•• In Waveform Mode, TC of the other CTU can also trigger LOAD function.

~

m
~
I

:to.

~
;::

fa

::!:

8
l=

Ii'

I!:l

Qi

1'SD5XX - Appllcatlllll IItJtI

m

Introduction

The PPLD (Ctlnt.}

(Cont.}

The operation of the CTU is controlled by two signals:
Q The enid Is signal -

To enable or disable the Counter from counting.
Q The load/store signal -

To load the Image Register contents to the Counter or store the Counter value to the
Image Register.
These two signals are defined by the user through the Counter Command Register, the
external pin input, the PPLD macrocell output or by the user software. These multiple
sources of control enable the user to implement very specific counterltimer applications.
Table 1 shows the sources for the load/store operation and the enable/disable function
under different modes of operation, and also what the Counter is doing while the Image
Register Is under freeze.

Table 1. ModllS 01 Operation

Input Mode
01 Operation

Possible
Load/StoTB
SOUICIIS

Load/Store
Function

Possible
Enable/Disable
SOUICes

Counter
DUling
FTBIIZB-ACk

Waveform

Software, pin,
Load counter
PPLD Macrocell, from Image
Register.
TC of the other
counter.

Software, pin,
Continue to
PPLD Macrocell. count. When TC
is reached
output level is
unchanged.

Pulse

Software, pin,
Load counter
PPLD Macrocell. from Image
Register.

Software, pin,
Continue to
PPLD Macrocell. count. When TC
is reached
output level
changes.

Watch-Dog
Software.
(Counter-2 only)

Load counter
from Image
Register.

Always enabled.

No effect.

Event Count

Software, pin,
Store counter
Pin, PPLD
PPLD Macrocell. value in the
Macrocell.
Image Register. Every specified
transition will
increment
(or decrement)
counter.

Counter will
continue to
count events.

Time capture

Software, pin,
Store counter
Software.
PPLD Macrocell. value in the
Image Register.

Counter will
continue to
count timer
clock cycles.

---------------------------r'Jrjf;--------------------------3-6
-- - -

I'SD5XX - AppllcatlDn NDt. 028

PSD5XX
Counter/Timers
INPUT/CLOCK
Scaling

All four Countermmers share a common input clock which can be scaled down.
The CounterlTimers operate in the frequency range up to 7.0 MHz. The maximum input
clock to the PSD5XX is 28 MHz. The default divide factor is 4 and the input clock can
further be scaled down through 280 times.
Figure 5 depicts the relationship between PSD5XX clock input (clkin) and the Timer_Clock
with the default divide factor 4.

Figure 5.

-----------------------------------wr4V~~----------------------------------3·7

PSD5XX - Application 1I0t. 028

PSD5XX
CounterRimers
INPUT/CLOCK
Scaling

The following example has been used for this application note.
External input clock of the PSD5XX is 12 MHz.
The expected Count frequency of all Counter/Timers is 3 MHz.

(Cont.)
Countermmer Clock Input

(External Clock Input to PSD5XX)
- - - - - - .• (1)
(DIV)

The range of DIV is 4 = 
 DIV = 4

... (2)

Hence from the data sheet Table 16, when DIV = 4, set the Scale-bit in the Global
Command Register to 0 and write 00 into the DLCY Register. Note that at power up DLCY
contains 00.
The input clock to the Countermmers is then 3 MHz, scaled down from the external
12 MHz clock.

-~-8-----------------------~Jr;--------------

PSD5XX - Application Nots 028

Different
Operating
Modes

The operations and initializations of the five modes of the CounterfTimers are discussed
in the following sections.

Waveform Mode
The Waveform Mode is also known as the Pulse Width Modulation (PWM) Mode.
In this mode a continuous waveform output is produced using two CounterfTimers. The on
and oft widths of the output Waveform are programmable and are defined by the user, by
writing the desired values into the corresponding Image Registers.
Figure 6 shows a typical PSD5XX based PWM implementation, where the PWM_OUT
is the expected output waveform, and Timer Clock is the clock input to the CTUs.
As seen in Figure 6 a minimum of two CounterfTimers are required to implement the
Waveform mode. There is an alternate implementation of the PWM mode, where each of
the four CounterfTimers can generate PWM waveforms. Refer to Appendix 6 for details.
Typical applications of this mode are:

o
o
o
o

Automotive engine control
Motor speed control
Display intensity control
Sound generation

A waveform output in the above application can easily be produced using PSD5XX
CounterfTimers. Variations of on-time/oft-time of the waveform output is done by modifying
the Image Register contents. The relationship between on-time and oft-time of the waveform
output is expressed as duty cycle.
The duty cycle of the waveform in Figure 6 is expressed as:
Duty Cycle

=

on-time (Ton)
on-time (Ton) + oft-time (Toft)

If Ton equals Toft then the waveform output has a 50% duty cycle and is a square wave.
Suppose PWM is used to increase or decrease the power supply to a motor, with the
larger duty cycle delivering more power to the motor. Obviously more power to the motor
means higher speed in the motor, i.e., motor speed can be controlled by adjusting the ON
time of the signal.
Figure 7.0 depicts the input control signals of PSD5XX in waveform mode.

Figure 6. Waveform Mode Input/Output

33%

TIMER_CLOCK

----II>

' - -_ _ _ _...J

--------------------~~~-------------------3-9

i~~!P.
!tlit.~i
-Cl.~

~

~

"l

=:!' at
:;:t'=a

CCj-

it~
I

t:;::
i

if
=a
if
;!:!

COUNTER OUTPUT (PORT A OR B)
(ONLY COUNTER 0 OR 2)

START COUNTER (Brr 1 OF GLOBAL COMMAND REGISTER)

'I;;

::"-I
CO)
OUTPUT POLARITY SELECT (Brr 3 OF CMD REGISTER)

SOFTWARE SELECT (Brr 2 OF CMD REGISTER)

FREEZE ACKNOWLEDGE
(STATUS FLAGS REGISTER)

ENABLEIDISABLE

r::r

!!.
~

SOFTWARE ENABLE (Brr 7 OF CMD REGISTER)

It:
~
IllItft

TERMINAL COUNT (TC)"
TOOTHERCTU
TERMINAL COUNT OF OTHER CTU"

SOFTWARE GATE Brr
(Brr 6 OF CMD REGISTER)

I
TERMINAL COUNT (TC)
I TO INTERRUPT CONTROLLER
----------~

I
I
I
I

TERMINAL COUNT (TC)
TO PORTE
---------~

SOFTWARE LOAD (SOFTWARE LOAD I STORE REGISTER)

INCREMENTIDECREMENT SELECT (Brr 1 OF CMD REGISTER)

SOFTWARE FREEZE (FREEZE COMMAND REGISTER)

TIMER_CLOCK

"Need two CTUs together in Waveform Mode (CTUO - CTU1 or CTU2 - CTU3).
The Terminal Count of CTUO drives CTU1 and the Terminal Count of CTU1 drives CTUO.
The same applies to CTU2 and CTU3.

'!I
at
"I

;r
...

COUNTER

I
PIN OR MACROCELL
(SELECTED BY Brr 5 OF CMD REGISTER)

a

~
=a

i

C1i

;r

i

•
It

a-

D

PSD5XX - Application Nottl 028

Different
Operating

Modes
(Cont.)

Waveform Mode (Cont.)
The features of the Waveform Mode are:

o

Two Timers configured in Waveform Mode are needed to generate a continuous
Waveform output of the Image Registered duty cycle. The combinations of the two
CounterfTimers are:
CounterfTimer-O and CounterfTimer-1
and/or
CounterfTimer-2 and CounterfTimer-3

o
o

Image Registers of CounterfTimer-O and CounterfTimer-1 are loaded with proper count
values to generate the required Registered duty cycle and duration. The frequency of
the waveform is : 1/T(on) + T(off).
There are four different sources which can load the Counter with contents from the
Image Register:
-

o

by software
by input pin
by PPLD macrocell output
by Terminal Count (TC) of the other Counter configured in the Waveform Mode.

Three different sources are available to enable or disable the Counter:
- by software
- by input pin
- by PPLD macrocell output

o
o

Outputs of these CounterfTimers are available on Port A or Port B.
The fitter reports contain the pin list information. The CounterfTimer outputs are routed
to the corresponding pins via software.
If required the outputs can be fed back to the GPLD through the I/O ports.
This feedback enables the creation of complex waveforms.

A Waveform Mode Design example:

o
o
o

o

In this application example a waveform output (PWM_OUT) of 33.33% duty cycle is
generated. The required Ton time is 666 ns while the Toff time is 1332 ns.
The Waveform period time is 2000 ns.
CounterfTimer-O is configured to generate the Toff pulse and CounterfTimer-1 is
configured to generate the Ton pulse. The Counters are enabled via software.
The loading of the Counters from the Image Registers are automatically triggered
by the TC of the,other Counter. No inputs from the pin or macrocell are used.
The Timer input clock is 3MHz, i.e., PSD5XX input clock of 12 MHz is scaled down
to 3 MHz. To achieve the desired TonfToff time, the Image Register-O is initialized with
a count value of 2 and Image Register-1 with a count value of 4.

"'-=_Iif
-------------------------------------~~~jf----------------------------------3-.1--1

PSlJ5XX - AppllClltion Not. 028

Different
Operating
Modes
(Cont.)

Waveform Mode (Cont.)
The program flow to set up the Waveform Mode operation as described in this example is
as follows:
1.

Define the Timer input clock frequency (see section on clock scaling).

2.

Set up Command Registers for CTUO and CTU1
(CTU is an abbreviation of CounterfTimer unit).

3.

Initialize the Image Registers with the proper count values to define TonfToff time.

4.

Specify the Timer pulse output. This can be done in two ways:
via .abl as PWM_OUT pin 27, which is a user defined name or
via PSDconfiguration software by specifying "waveform/pulse output",
which assigns the default name "timeroutO".

S.

Set up the Special Function Register to specify the pin which is to be used as the
output pin for the signal PWM_OUT.

6.

Set up the Software Load/Store Register to load the CTUs with the initial count values.

7.

Set up the Global Command Register Start Bit and start the operation of the CTUs.

The procedure to set up CounterfTimer Registers in the Waveform Mode in this design
example is:

Counter/Time,.O Registers Initialization:

o

Write "D4"hex to Command Register-O (CMDO) at offset from base address of CSIOP
(Chip Select I/O Port).

CMDO Register
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

1

X

X

0

1

0

0

Bit-O: 0 Mode Select Bit, select Waveform Mode for CTUO.
Blt-1: 0 DecremenVlncrement Bit: select decrement (CTUO counts down from 2 to O.
Blt-2:
Bit-3:
Bit-4:
Bit-5:
Bit-6:
Bit-7:

1
0
X
X
1
1

At 0, TC triggers the loading and operation of the CTU1).
Select CounterfTimer Bit: Select CTUO.
Output polarity: Select output to be active low (Toff time).
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: No pin or macrocell input, don't care.
Load/Store Bit: No pin or macrocellioad/store.
EN/DIS Bit: Enable continuous counting.

IMGO is loaded with 04 (hex) to define the Toff time of the output pulse (PWM_OUT)

-3--1-2--------------------------------~Jr~Ar-----------------------------------

PSD5XX - Application Note 028

Different
Operating
Modes
(Cont.)

Waveform Mode (Cont.)
Countermmer-1 Registers Initialization:

o

Write "CC"hex to Command Register 1 (CMD1).

CMD1 Register
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

1

X

X

1

1

0

0

Bit-O: 0 Mode Select Bit, select Waveform Mode for CTU1.
Bit-1: 0 Decrement/Increment Bit: select decrement (CTU1 counts down from 4 to
At 0, TC triggers the loading and operation of the CTUO).
Bit-2: 1 Select CounterlTimer Bit: Select CTU1.
Bit-3: 1 Output polarity: Select output to be active on (Ton time).
Bit-4: X Input Polarity: No pin input in this mode, don't care.
Bit-S: X Pin or Macrocell input: No pin or macrocell input, don't care.

o.

Bit-S: 1 Load/Store Bit: No pin or macroceilioad/store.
Bit-7: 1 EN/DIS Bit: Enable continuous counting.
IMG1 is loaded with 02(hex) to define the Ton time of the output pulse (PWM_OUT)

After Command Registers 0 and 1 are initialized, other Registers (Special Function
Register, Software Load/Store Register and Global Command Register) must now
be initialized.

o

Configure Port A pin PAO as special function out, dedicating it as a Timer output pin
by setting bit-O to "1" in Port A Special Function Register. This bit is set only when
there is a need to bring the timer output pulse out of the PSD5XX. Refer to .frp report
file to determine where the output is connected (The device fitter might assign it to
Port B pin PBO.

Special Function Register
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

0

1

-----------------------------------~~~~----------------------------------3-13

PS05XX - Application Note 028

Different
Operating
Modes

Waveform Mode (Cont.)

o

(Cont.)

Set Load/Store bit-O and bit-1 (of Timers 0 and 1) to one in the Software Load/Store
Register. This transfers the content of the Image Registers to the Timers to initialize
the waveform mode. The Software Load/Store bits are automatically cleared whenever
the Countermmer starts operating.

Software Load/Store Register

o

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

1

Now to start the Timers: The Global Command Register has to be initialized to 02(hex),
i.e., the following bits are set

Global Command Register
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
Bit-1: 1 Counter start bit: This bit turns on all the selected Timers.
Bit-2: 0 Global Mode bit: All Countermmers operate in Waveform or Pulse Mode.
Bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only Countermmer-2).
After the CounteriTimers start operating, every time a Timer counts to zero, a transition
occurs on the output waveform (PWM_OUT) to generate a pulse with the specified duty
cycle. The Counter/timer-O is reloaded automatically from the Image Register-O when the
Counter/timer-1 reaches the zero count and this process repeats with Counter/timer-1.
The terminal count of each Counter/timer drives the loading of the other Counter/timer.
This results in a continuous waveform output.

-----------------------------------r-~~----------------------------------3-14

====

PSD5XX - AppllClltJDR lIottll12B

Different
Operating
Modes
(Cont.)

Walleform Mode (Cont.)
Figure 8 shows the simulation result of the Wavefo-rm Mode simulated on the
PSDsim simulator.

Figure B. Simulation of Walleform Mode

imgOL
cntrOL
img1L
cntr1L
cmdO
cmd1

o

Input Signals:
Prescaled PSD5XX input clock: Timer_Clock

o

Output Signal:
PWM waveform output: PWM_OUT

The CounterfTimers are enabled by software and as soon as the Global Counter Start bit
is set to 1, the Timers start to output PWM waveform. The total period is the sum of the
count values loaded into the IMGO and IMG1 Registers (04 + 02 = 06). The duty cycle
is (02/06 = 0.33) or 33%. Note that every time the contents of the Image Registers are
changed to vary the duty cycle of the output waveform, the Load/Store bits of both the
CounterfTimers must be set to 1 to initialize a new PWM cycle.

iFSE4S1;

-----------------------------------~J;~~--------------------------------3---15-

PSD5XX - Application Nots 028

Different
Operating
Modes
(Cont.)

The Pulse Mode
In Pulse Mode a CounterfTimer when enabled outputs a mono-shot pulse. The pulse
width is defined by the value loaded into the corresponding Image Register. Any of the four
CounterlTimers are capable of Pulse Mode. Figure 9 depicts a pulse output from
CounterlTimer-O initiated by the PPLD input control signal mc2tmrO.
A typical application of the Pulse Mode is in networking applications using CSMAICA
protocol. The transmission line has to be sensed to check if other stations are accessing
this line. Therefore, based on a signal transition on this line a mono-shot pulse has to be
produced to indicate that the line is busy. This mono-shot pulse stops the host station from
accessing the line and hence avoids data collisions.

o
o
o
o

Up to four pulse outputs are available from the PSD5XX, one per each CounterfTimer.
Polarity of the pulse output is defined by the output polarity bit in the CounterfTimer
Command Register.
To generate the required pulse width, load the Image Register with the required pulse
width value. As soon as the CounterlTimer trigger occurs, the Image Register contents
are transferred to the corresponding CounterlTimer.
Unlike Timers on standard microcontroliers, there are three different ways to enable a
CounterlTimer on the PSD5XX:
- Input pins PE3-PE6(port E).
- mc2tmrO-3 inputs in the PPLD.
- Software Control.

o

The outputs of the CounterfTimers are available on Port A or Port B. The outputs
can be fed back to the ZPLD. Refer to the .frp report file to determine where the
outputs are connected.

Figure 10 depicts the input control signals of a PSD5XX in Pulse mode.

Figure 9. Pulse Mode Input/Output

mc2tmrO
AS TRIGGER 1------'
mc2tmrO
AS TRIGGER

---I

TIMER-O
PULSE

TIMER STARTS
DECREMENTING
AT THIS POINT
TIMER UNDERFLOWS

E --------------------------__
--------------------------r--3-16
====

15 f~S!
~g,~i
SlQj~

"'. CCi-~
S'::i

~

Iii'
§;
CI

COUNTER OUTPUT (PORT A OR B)

START COUNTER (BIT 1 OF GLOBAL COMMAND REGISTER)

....

!=I
~

a
FREEZE ACKNOWLEDGE
(STATUS FLAGS REGISTER)

SOFTWARE FREEZE ( FREEZE COMMAND REGISTER)

S!.
t!

OUTPUT POLARITY SELECT (BrT 3 OF CMD REGISTER)
'''I
~~111111

111111

SOFTWARE SELECT BIT (BrT 2 OF CMD REGISTER)

~

ENABLEIDISABLE
TERMINAL COUNT (TC)
TO INTERRUPT CONTROLLER

11111'1
IIQlnn

ENABLE COMMAND (BrT 7 OF CMD REGISTER)

COUNTER

-1---------I

PIN OR MACROCELL
(SELECTED BY BrT 5 OF CMD REGISTER)

~
=:a
;:r

at
III
~

~
;sCD

LOAD/STORE

I
I

TERMINAL COUNT (TC)
TO PORTE

----------~

I

It

SOFTWARE GATING BIT
(BIT 6 OF CMD REGISTER)

SOFTWARE LOAD (SOFTWARE LOAD/ STORE REGISTER)

i~

:oc
I

INCREMENTIDECREMENT SELECT (BIT 1 OF CMD REGISTER)

TIMER_CLOCK

~

......

t;;:

fit!:!:
II

t

&t

I

PSD5XX - Application Note 028

Different
Operating
Modes
(Cont.)

The Pulse Mode (Cont.)
A Pulse Mode example
The following example explains the Pulse Mode application. The enable inputs to the
Timers are generated by the PPLD.
The program flow to set up the Pulse Mode operation as described in this example is as
follows:
1. Define the Timer input clock frequency (see section on Clock Scaling).
Here 12MHz is scaled down to 3MHz.
2. Set up the Command Register for CTUO.
3. Initialize the Image Register with the proper count values to define the pulse width.
4. Specify the Timer pulse output. This can be done in two ways:
via .abl as pulse_out pin 27, which is a user defined name or
via PSDconfiguration software by specifying "waveform/pulse output",
which assigns the default name "timeroutO".
S. Set up the Special Function Register to specify the pin which is to be used as the
output pin for the signal pulse_out.
6. The following equation is used to trigger CounterlTimer-O (mc2tmrO).
This equation is included in the design entry .abl file.
mc2tmrO

= (exCsignal1

& !exCsignal2 # !exCsignaI3)

The exCsignal1 through exCsignal3 signals are the input signals to the PSDSXX pins.
If these signals satisfy the above equations then CounterlTimer-O is loaded on the rising
edge of mc2tmrO. A pulse with a pulse width specified by the Image Register is generated
on the output pin.
7. Set up the Global Command Register Start Bit and start the operation of the CTU.
The procedure to set up CounterlTimer Registers in the Pulse Mode in this design
example is:

Counternimer-O Registers Initialization

o

Write "9D"hex to Command Register 0 (CMDO) at offset from base address of
CSIOP(Chip Select 110 Port}.

CMOO Register
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

1

1

0

1

Bit-O:
Bit-1:
Bit-2:
Bit-3:
Bit-4:
Bit-5:
Bit-6:
Bit·7:

Mode Select Bit, select Pulse Mode for CTUD.
0 Decrement/Increment Bit: Select decrement (CTUO counts down from 3 to O).
Select CounterlTimer Bit: Select CTUO.
Output polarity: Select output pulse to be active high.
X Input Polarity: No pin input in this mode, don't care.
0 Pin or Macrocell input: Macrocell input control.
0 Load/Store Bit: Enable Load control by macrocell output.
EN/DIS Bit: Enable continuous counting.

IMGO is loaded with 03(hex} to define the pulse width of the output pulse (pulseD_out)

-3-.1-8----------------------------~~~-------------------------------

PSD5XX - Application Note 028

Different
Operating
Modes
(Cont.)

The Pulse Mode (Cont.)
After Command Register 0 is initialized, other Registers (Special Function Register and
Global Command Register) must now be initialized.

o

Configure Port A pin PAO as special function out, dedicating it as a Timer output pin by
setting bit-O to "1" in Port A Special Function Register. This bit is set only when there is
a need to bring the timer output pulse out of the PSDSXX. Refer to the .frp report file to
determine where the output is connected. Note that the device fitter might assign the
pulse output to Port Spin PSO.

Special Function Register

o

Sit-?

Sit-6

Sit-S

Sit-4

Sit-3

Sit-2

Bit-1

Bit-O

0

0

0

0

0

0

0

1

Now to start the Timers the Global Command Register has to be initialized to 02(hex),
i.e., the following bits are set

Global Command Register
Bit-?

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").

Bit-1: 1 Counter start bit: This bit turns on all the selected Timers.
Bit-2: 0 Global Mode bit: All CounterfTimers operate in Waveform or Pulse Mode.
Bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only CounterfTimer-2).

-----------------------------------~~~~----------------------------------3-19

PSD5XX - Application Note 028

Different
Operating
Modes

The Pulse Mode (Cont.)
Figure 11 illustrates the basic pulse mode operation and retriggerability of the
Countermmer in the pulse mode.

(Cont.)

Figure 11. Simulation of Pulse Mode

imgOL
cntrOL
cmdO

o

Input Signals
Countermmer-O trigger signal: mc2tmrO
PSDSXX input clock: Timer_Clock

o

Output Signals
Pulse output at: pulseO_out

Note that mono-shot output, active high (pulse width
output (pulse width =03 + 02 =05) are simulated.

=03) and retriggered mono-shot

Figure 11 shows the simulation result of Pulse Mode on the PSDsim simulator. The
Counterrrimer trigger signal mc2tmrO is enabled as soon as the ext_signal signals listed in
the Abel equation are satisfied. When mc2tmrO is True (= High-State Pulse),
Countermmer-O starts outputting a pulse with programmed pulse width equal to 03. The
second output pulse (when mc2tmrO is True again) is longer although the Countermmer is
loaded with a count value of 03 because the Countermmer is re-triggered for the second
time before the output pulse generated by the first trigger dies. Therefore the pulse width of
the second pulse is 05.

-3-~-O----------------------------------~~~-------------------------------------

PSD5XX - Application Nots 028

Different
Operating
Modes
(Cont.)

The Event Counter Mode
Event counting is a common feature in many Microcontrolier applications. An example
could be counting the number of soda bottles on an assembly line or number of positive
transitions in an incoming signal.
The advantage of using an event counter on the PSD5XX is that the PPLD allows several
external signals to be combined to define an event. The following equation shows how this
can be implemented.
mc2tmrO

= ext_signal1

& !exCsignal2 # !exCsignal3

In this example each time mc2tmrO is true (has a Zero-to-One transition) the count value in
CounterfTimer-O increments by one.
Event Count Mode Features on the PSD5XX:

o
o
o
o

o
o

o

Up to 3 Event Counters are available.
Event latching is input signal edge sensitive.
If the input control is by macrocell, then the input polarity is defined in the .abl file,
which in turn defines the active edge. In order to get falling edge sensitivity the
macrocell equation has to be inverted, i.e., preceded by a negation sign (!).
If the input control is by the pin, then the input polarity bit in the CounterfTimer
Command Register (bit-4) is used to define the edge (example: input polarity active
high => rising edge sensitive).
By using Freeze and Freeze acknowledge signals, the count value can be read
from the Image Register without affecting the actual event count.
For an event to be counted, the minimum time distance between two successive events
should be at least 1 TimecClock period of the CounterfTimer input clock.
Unlike Timers on standard microcontrollers, there are three different ways to create
CounterfTimer events on the PSD5XX:
- Input pin PE3-PE6 (port E).
- mc2tmrO-3 inputs in PPLD.
- Software Load Commands.

Refer to figure 12 for control signals needed to operate in Event Count Mode.
In this example when the CounterfTimer is active every Low-to-High transition on mc2tmrO
will increment the IMGO (Image Register) of CounterfTimer-O.
Once the freeze signal is set, the image content is "Frozen" and the counter keeps on
counting the events. The moment freeze is cleared, the counter updates the Image
Register. Therefore the events will always be counted, independent of the freeze command.

-------------------------------------~~~------------------------------------3·21

Co>

i~~s!

~

cQ.~;:
mQi'!'il

... -m
S":::::a
cca-

i

~I

:to

~
:;::

::I:!:

=

if
::!!
IC:i

~

CIIi

START COUNTER (BIT 1 OF GLOBAL COMMAND REGISTER)

~

C')

c:!

SOFTWARE SELECT (BIT 2 OF CMD REGISTER)

~
:::a

::::

PIN OR MACROCELL
(SELECTED BY BIT 5 OF CMD REGISTER)

II~"'"
IIIII
tllllill

5!.
t!

cg

ENABLE COMMAND
(BIT 7 OF CMD REGISTER)

liD
c;r

.....
;
~

111111-

IIIII "!
~

PIN OR MACROCELL (BIT 5 OF CMD REGISTER)

LOAD/STORE
COUNTER

SOFTWARE GATING BIT
(BIT 6 OF CMD REGISTER)

TERMINAL COUNT (TC)
TO INTERRUPT CONTROLLER

.,----------TERMINAL COUNT (TC)
L _ _ _TO
_ PORTE
_ _ _ _ _ .....

SOFTWARE STORE (SOFTWARE LOAD/ STORE REGISTER)
FREEZE ACKNOWLEDGE
(STATUS FLAGS REGISTER)
SOFTWARE FREEZE (FREEZE COMMAND REGISTER)*

TIMER_CLOCK

*Count updates are continuously stored in the image register, unless frozen by the software freeze command.

a

~

-f
Ii

t

Ii'
~
CI6

I'SD5XX - Appllt:llt/tIII lIe,. DZ8

Di"erent
Operating
Modes
(CDnt.)

The Elfent CDunte, MDde
Elfent CDunte,Oa/gn example:

o

Generating the event input to the CounterlTlmer:
The event input (mc2tmrO) is defined in the following equation:
mc2tmrO = ( exLsignal1 & lexLsignal2 # lexLsignal3)

where ext_signals are control inputs and mc2tmrO is the output from the PPLD.
Any rising edge on the mc2tmrO is counted by the CounterlTimer-O as one event and thus
will increment the counter by one.

o

Input clock to the CounterlTlmer:
In this application note the default scale down factor (4) of the PSD5XX input clock
is used:
default PSD5XX input clock = 12 MHz
Scale down factor = 4
CounterlTimer input clock = 12 MHz/4 = 3 MHz.
For a guaranteed event counting without a miss, the events must be separated
by at least one timer clock plus 2 CLKIN clock periods.

The program flow to set up the Event Count Mode operation as described in this example is
as follows:
1. Define Timer input clock frequency (see section on Clock Scaling).
Here 12 MHz is scaled down to 3 MHz.
2. Set up Command Register for CTUO.
3. Initialize IMGO and CNTRO Registers to 00.
4. The following equation is used to trigger events on CounterlTimer 0 (mc2tmrO).
This equation is included in the design entry .abl file.
mc2tmrO = (ext_signaI1 & lext_signal2 # lext_signaI3)
The ext_signal1 through ext_signal3 signals are the input Signals to the PSD5XX pins.
If these signals satisfy the above equations then the IMGO Register gets incremented at
every rising edge of mc2tmrO.
5. Set up the Global Command Register Start Bit and start the operation of the CTUO.
6. To read the count event count updates, freeze the Image Register(IMGO) by writing 01
into Freeze Command Register.
7. Wait for the Freeze Acknowledge bit to be set to 1 for Countermmer-O and then read
the IMGO Register.

---------------------------~Jr~-------------------------~--n

PSD5XX - Application Note 02B

Different
Operating
Modes
(Cont.)

The Event Counter Mode (Cont.)
The procedure to set up CounterlTimer Registers in the Event Count Mode in this design
example is:

Counternimer-O Registers Initialization:

o

Write "1 E"hex to Command Register 0 (CMDO) at offset from base address of
CSIOP (Chip Select I/O Port).

CMDO Register
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

x

X

1

1

0

Bit-O:
Bit·1:
Bit·2:
Bit·3:
Bit·4:
Bit·5:
Bit·6:
Bit·7:

0 Mode Select Bit, select Event Count Mode for CTUO.
Decrement/Increment Bit: Increment after every event.
Select CounterlTimer Bit: Select CTUO.
X Output polarity: No timer output, don't care.
X Input Polarity: No pin input in this mode, don't care.
0 Pin or Macrocell input: Macrocell input control.
0 Load/Store Bit: Store control from macrocell.
0 EN/DIS Bit: Enable or disable by macrocell.

NOTE: In this mode each event will enable the Counter/Timer for one Timer Clock
cycle only.

IMGO and CNTRO Registers must be cleared to 00.
After Command Register 0 is initialized, other Registers (Global Command Register and
Freeze Command Register) must now be initialized.

o

Now to start the Timers: The Global Command Register has to be initialized to 06(hex),
i.e., the following bits are set.

Global Command Register
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

1

1

0

Bit·O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
Bit·1:
Counter start bit: This bit turns on all the selected Timers.
Bit·2:
Global Mode bit: AI! CounterlTimers operate in Event Count or
Time Capture Mode.
Bit·3: 0 Watch Dog bit: Not Watchdog Mode (affects only CounterlTimer-2).

-3-~-4--------------------------------~~~~-----------------------------------

'BD5XX - Application Not. 028

Di"erent
Operating
Modes
(Cont.)

The Event Counter Mode (Cont.)
The CounterfTimer is turned on after a write takes place on the Global Command
Register. The CounterfTimer will keep on counting the events and update the Image
Register whenever the event count has changed. Follow these steps to read the
Image Register:

o
o

The Image Register must be ''frozen'' before it can be read.
Write "1" to bit 0 of the Freeze Command Register
(Corresponds to CounterfTimer-O).

Freeze Command Register
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

0

1

o
o

This will freeze the Image Register updates by the counter.

o

The Freeze Command bit-O must be cleared to 0 by the Microcontroller to resume
normal counting and to negate the Freeze-Acknowledge signal.

Check the Freeze Acknowledge bit-O in the Status Register. A microcontroller can
access the Image Register accurately only when the Freeze Acknowledge bit-O
is set to "1".

----------------------------~~~--------------------------3·25

PSD5XX - Application Note 028

Different
Operating
Modes

Figure 13. Simulation of Event Counter Mode

(Cont.)

mc2tmrO
cmdO
imgOL
cntrOL

o

Input Signals
CounterfTimer-O event input signal: mc2tmrO
Every rising edge transition on mc2tmrO is considered as an event occurrence.
Prescaled PSD5XX input clock: TimecClock

o

Output Signals: None

In this example each EVENT is counted by the Image Register (ImgOL).
Figure 13 illustrates that at every rising edge transition on mc2tmrO, the count in the imgOL
Register is updated. Register cntrOL serves as the event counter when theFreeze
Command is active so the events are not lost during the freeze.

NOTE: If the Store control bit (bit-6) in the CMDO Register is set to "1" i.e., Store control by
"Software", then before the Freeze Command is issued a Software Store Command must
be issued by writing into the Software Load/Store Register. In this mode cntrOL counts the
incoming events. The Software Store Command updates the Image Register in this case,
prior to the Freeze Command, with the correct numbers of the counted events.

-3--2-6----------------------------~~~~-------------------------------

PS05XX - Application Note 028

Different
Operating
Modes
(Cont.)

The Time Capture Mode
up to three out of four CounterfTimers in the PSD5XX can be configured to operate
in the Time Capture Mode. In this Mode a counter is continuously counting at the
Timer Clock rate. At each transition of the trigger input signal (rising or falling edge),
the counter value is transferred to the associated Image Register.
Typical applications of Time capture Mode are:

o
o
o
o

Measuring Periods
Pulse widths
Frequencies
Phase differences of signals.

To measure the time period of a signal as seen in Figure 14a, a single CounterfTimer
can be used to capture the consecutive rising edges of the input signal. The difference
in the value of these two captures is used to calculate the time period of the signal.
In this application note example, the measuring of "pulse width" of an input signal is
depicted.

Figure 14a. Measuring Time Period Using Time-Capture

I~

TIME PERIOD

t
CAPTURE 1

CAPTURE 2

TIME (CAPTURE 2) - TIME (CAPTURE 1) = TIME PERIOD

-----------------------------------~~~~----------------------------------3-27

PSD5XX - Application Note 028

Different
Operating
Modes
(Cont.) .

The Time Capture Mode (Cont.)
To measure the pulse width of a signal as seen in figure 14b,the CounterfTimers
have to capture both the rising (capture1) and the falling(capture2) edges of the signal.
The difference in the value of these two captures is used to calculate the pulse width of the
signal. Usually one CounterfTimer is configured to capture the falling edge of the signal
from the input pin. Another CounterfTimer is used to capture the rising edge. The time
distance between the two edges must be greater than one CounterfTimer input clock in
order to be captured.
Figure 15 depicts the control signals required for the time capture Mode of operation.
The Counter counts up every Timer Clock cycle. Whenever a Low-to-High transition
occurs on the selected event input (mc2tmr1 in this example) the Image Register is
updated by the count value in the Counter.
The microcontroller reads the image value using the Freeze/Freeze Acknowledge
handshake protocol. The Freeze Command blocks the event input when set to 1.

Figure 14b. Measuring Pulse Width Using Time-Capture

,.

PULSE WIDTH

-,

t

t

CAPTURE 1

CAPTURE 2

TIME (CAPTURE 2) - TIME (CAPTURE 1)

=TIME PERIOD

-3-~-8----------------------------~~~~-------------------------------

"ilIic::a-"':
il:S 51
.::Q.~;'
'I ~;
S'::a

CI5-

;!:!

'=CiI

....

!'I
n

a
&'
III

START COUNTER (BIT 1 OF GLOBAL COMMAND REGISTER)

==r

SOFTWARE SELECT (BIT 2 OF CMD REGISTER)

S!.

ENABLEIDISABLE
FREEZE ACKNOWLEDGE
(STATUS FLAGS REGISTER)

l~

IIII~

SOFTWARE FREEZE (FREEZE COMMAND REGISTER)

~

~

;.
...~

IItIIQ!

,i'
~

PIN OR MACROCELL
(SELECTED BY BIT 5 OF CMD REGISTER)

STORE
COUNTER

SOFTWARE GATE BIT
(BIT 6 OF CMD REGISTER)

TERMINAL COUNT (TC)
TO INTERRUPT CONTROLLER

,--------- .....
I
I
I

!;

TERMINAL COUNT (TC)
TO PORTE

----------~
SOFTWARE STORE (SOFTWARE LOAD/STORE REGISTER)

i...
CIi

I
t

;JI

51

TIMER_CLOCK

~
I

:...

:a:;::

D
::t
8

if
CIo)

~

co

8'

~

CIj

PSD5XX - Application Note 028

Different
Operating
Modes
{Cont.}

The Time Capture Mode {Coni.}
Time Capture Design Example of a Pulse Width Measurement:
In this example, the input signal is named as inpuCpulse. This signal can be input to the
CounterlTimers in two ways:
1. Connected to the input pins PE3 and PE4 of CounterlTimer-O and CounterlTimer-1
respectively. And capture the counters values at the rising and falling edges of
inpuCpulse.
or
2. Connected to the input pin PE3 of CounterlTimer-O. And the input to CounterlTimer-1
comes from the PPLD, defined by

mc2tmr1

= inpuCpulse;

(Refer to the .abl file)

Thereby only one pin (PE3) is used as both CounterlTimers input. This application note
uses the second method to input the inpuCpulse. This method saves pin PE4 for other
purposes.
The capturing of the leading and trailing edge values of counters can be done, by
properly defining the input polarity on the pin PE3 (for CounterlTimer-O) and defining
the input equation in the .abl file for mc2tmr1 (CounterlTimer-1) with proper polarity.
In this example the leading edge of the input signal is captured by CounterlTimer-1 Image
Register and the trailing edge is captured by CounterlTimer-O Image Register.

o

Clock Input to the CounterlTimer:
In this application note, the default scale down factor(4) of the PSD5XX input clock
has been used.
i.e., PSD5XX input clock = 12 MHz
Scale down factor = 4 (default)
CounterlTimer input clock = 12/4
= 3 MHz => 333ns period

Therefore the input pulse width must be greater than 333 ns in order to be captured
by the CounterlTimer. Note that at 3 MHz Timer Clock input the pulse width measurement
will have a resolution of ± 333/2 ns.
The program flow to set up the Time Capture Mode operation as described in this example
is as follows:
1. Define the Timer input clock frequency (see section on clock scaling). Here 12MHz is
scaled down to 3MHz.
2. Set up Command Registers for CTUO and CTU1.
3. Initialize IMGO, CNTRO, IMG1, CNTR1 Registers to 00.
4. The following equation is used to trigger the Time Capture on CounterlTimer-1
(mc2tmr1). This equation is included in the design entry .abl file.

mc2tmr1 = inpuCpulse;
If the signal input_pulse satisfies the above equation, every rising edge on mc2tmr1
causes a Time Capture in IMG1 for CounterlTimer-1. Every Falling edge on inpuCpulse pin
causes a Time Capture in IMGO for CounterlTimer-O.
5. Set up the Global Command Register Start Bit and start the operation of the CTUO
and CTU1.
6. To read the count of Time Capture updates, freeze the Image Registers (IMGO and
IMG1) by writing 03 into Freeze Command Register.
7. Wait for the Freeze Acknowledge bits to be set to 3 for CounterlTimer-O and
CounterlTimer-1 and then read the IMGO and IMG1 Registers.

-----------------------------------f==~g----------------------------------3·30

PSD5XX - Application NotB 028

Different
Operating
Modes

The Time Capture Mode (Cont.)
Procedure to set up CounterfTimer Registers for Time Capture Mode in this design
example:

(Cont.)
CountBr/TImS,.O Rsglstsrs Inltlal/zatlDn

o

Write "BF"hex to Command Register 0 (CMDO) at offset from base address of
CSIOP(Chip Select I/O Port).

CMOO Register
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

X

0

1

1

X

1

1

1

Bit-O:
Bit-1:
Bit-2:
Bit-3:
Bit-4:
Bit-S:
Bit-6:
Bit-7:

X
1

1
0
X

Mode Select Bit, select Time Capture Mode for CTUO.
DecremenVlncrement Bit: Increment mode.
Select CounterfTimer Bit: Select CTUO.
Output polarity: No timer output, don't care.
Input Polarity: Active low.
Pin or Macrocell input: Pin input control.
Load/Store Bit: Store control from pin.
EN/DIS Bit: Don't care. Setting of bit-2 enables the CounterfTimer.

IMGO and CNTRO Registers must be cleared to 00.

CounterRimer-1 Registers Initialization:

o

Write "9F"hex to Command Register 1 (CMD1) at offset from base address of
CSIOP(Chip Select I/O Port).

CM01 Register
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

X

0

X

1

X

1

1

1

Bit-O:
Bit-1:
Bit-2:
Bit-3:
Bit-4:
Bit-S:
Bit-6:
Bit-7:

X
X
0
0
X

Mode Select Bit, select Time Capture Mode for CTU1.
DecremenVlncrement Bit: Increment mode.
Select CounterfTimer Bit: Select CTU1.
Output polarity: No timer output, don't care.
Input Polarity: Don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Store control from macrocell.
EN/DIS Bit: Don't care. Setting of bit-2 enables the CounterfTimer.

IMG1 and CNTR1 Registers must be cleared to 00.

-----------------------------------,ArJr~~----------------------------------~==

3-31

PSD5XX - Application Note 028

Different
Operating
Modes
(Cont.)

The Time Capture Mode (Cont.)
After Command Registers 0 and 1 are initialized, other Registers (Global Command
Register and Freeze Command Register) must now be initialized.

o

Now to start the Timers. The Global Command Register has to be initialized to 06(hex),
i.e., the following bits are set.

Global Command Register
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

1

1

0

Bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").

Counter start bit: This bit turns on all the selected Timers.
Global Mode bit: All Countermmers operate in Event Count or Time Capture
Mode.
Bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only Counterrrimer-2).
Bit-1:
Bit-2:

The Countermmer is turned on after a write takes place on the Global Command Register.
The Countermmer will keep on incrementing at every Timer Clock cycle and update the
Image Register whenever an event has occurred. Follow these steps to read the Image
Register:

o
o

The Image Registers must be "frozen" before they can be read.
Write "3" into the Freeze Command Register (Corresponds to Counterrrimers 0 and 1).

Freeze Command Register

o
o
o
o

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

1

This will freeze the Image Register updates by the counters.
Check the Freeze Acknowledge bit-O and bit-1 in the Status Register.
A microcontroller can access the Image Register accurately only when the Freeze
Acknowledge bit-O and bit-1 are set to "3".
After the completion of the Image Registers read operation, the microcontrolier
lowers the freeze command bits which in turn, cause the Freeze Acknowledge
signals to go to low.
The Freeze Command bit-O and bit-1 must be cleared by the microcontroller to do
enable continuous updates of the Image Registers.

-3--3-2-----------------------------~~~~--------------------------------

I'SD5XX - Application Not. 021

Different
Operating
Modes

Figure 16. Time Capture MDde Simulation

(Cont.)

tmUrez_ack
cmdO
cmdl

,I

I

:

I

Dl

~-l

I,

'I
, !,

=~

o

Input Signals

Input Pulse on pin for pulse width measurement: inpuCpulse
PSD5XX input clock: Timer_Clock

o

Output Signals: None

The Pulse Width Computation:

Figure 16 illustrates that at the falling edge of the input signal on inpuCpulse (pin PE3)
and the rising edge of the input signal on mc2tmr1, the present counts in the
Countermmer-O and Counter/Timer-1 Registers are transferred to Image-O and Image-1
Registers, Here the Image-O Register is updated to count OA and Image-1 Regfster to count
08, Note when the Freeze Command is active high the Image Register updates
are frozen.
The pulse width of the InpuCpulse signal Is

(Image-Q Register - Image-1 Register) = OA-08 = 02
Here each Counter/Timer clo~k cycle = 333 ns.
Therefore, the pulse width of the sample signal is:

= 02 * Counter/Timer clock input period
= 02 * 333ns
= 666 ns

-----------------------------~~~----------------------------3-33

I'BIlSXX - AppIlClltJlllllltJte D2B

Diff"lfInt
Operating
Modes
(Cont.)

Thll Watchdo, Mode
Watchdog Timer is very useful in situations where the software program is repeating in
an endless loop or the program jumps to an unexpected area. When this happens the
Watchdog Timer usually generates a Reset or interrupt to the microcontroller to initialize
the system.
Only CounterlTimer-2 in the PSD5XX is capable of the Watchdog function. While
CounterlTimer-2 operates in Watchdog Mode, the other three CounterlTimers in the
PSD5XX can be configured to operate in different modes. Table 2 shows the possible
mode combinations.

Tablll 2. I'DSSlbl. Mode ComblnatloRS
Global Modll Bit
(Global Command
Re,lster)

0'

Mode Select Bit
Modes
(CMDO, CMDt, CMD2 Counter/Timers
CMD3 Re,lstllrs)
0, t and 3
Waveform

0'

Modes
Counter/Tlmer-2
Waveform or
Watchdog

0

0

0

1

Pulse

Pulse or Watchdog

1

0

Event Counter

Watchdog Only

1

1

Time Capture

Watchdog Only

Special Features of the Watchdog CounterlTimer are:
Q Once set in Watchdog Mode, CounterlTimer-2 cannot be reconfigured by software.

It can get out of the Watchdog Mode only by resetting the PSD5XX.
Q Terminal Count signal of a Watchdog results in a pulse with a width equal to the

duration count value loaded Into the Image Register of the CounterlTimer-2.
Q The active-high Watchdog pulse from the CounterlTimer-2 (wdog2pld) is routed

as input to the ZPLD. The user can select any of the 1/0 pins of the GPLD as the
Watchdog output and invert its active high level, if needed.
Q During Watchdog Mode, CounterlTimer-2 counts down and generates a

Watchdog pulse at the terminal count. To avoid the generation of a Watchdog pulse,
CounterlTimer-2 has to be reloaded before the terminal count occurs. This can be
done by writing "1" into bit-2 of the "Software LoadlStore Register" before the terminal
count occurs.
Figure 17 depicts the inputs and output of CounterlTimer-2 operating in Watchdog mode.

rl,,-,if

-3~-----------------------------==~1------------------------------

I'SD5XX - Applla"", """ IJ2B

Diffe,ent
Operating
Modes

Figure 17. CTU Control Signals Fo, Watchdog Mode
WATCHDOG
GPLD
OUTPUT

(c.nt.)
COUNTER OUTPUT
(ACmIE HIGH)
WDOG2PLD

-

GPLD

OUTPUT

r!!!!-

-

TERMINAL COUNT TO
INTERRUPT CONTROLLER

-----,-------------------.
I
I
I

.

SET WATCHDOG BIT
(BIT 3 OF GLOBAL COMMAND REGISTER)

TO PORT E

EN/DIS

(SELF LATCHING BIT)
C

0

..

_ _ COUNT (TC)

SOFTWARE LOAD
(BIT 2 OF SOFTWARE LOAD/STORE REGISTER)

LOAD

U
N
T
E
R
2

I
M
A
G
E
2

A

..

nMEILCLOCK

ThI Watchdog ModellBsign Exampl.:
This example simulates the occurrence of the Watchdog condition and generation of a
Watchdog output pulse. The procedure to inhibit the Watchdog occurrence has also been
simulated in a later part of this example.
The program flow to set up the Watchdog Mode operation as described in this example is
as follows:
1. Define Timer input clock frequency (see section on clock scaling). Here 12MHz is
scaled down to 3 MHz.
2. Ignore Command Register for CTU2 in Watchdog mode.
3. Initialize CNTR2 Register and IMG2 Register to a required value.
4. Write "1" into the "Counter Start Bit" and "Watchdog bit" of the Global Command
Register simultaneously to start the Watchdog operation.
5. To inhibit the occurrence of th(l Watchdog and generation of the Watchdog output
pulse, write "1" into bit-2 of Software Load/Store Register before CounterlTimer-2
under flows.

------------------------~~,.-----------------------'1j
3-35

PSD5XX - Application Not. 028

Different
Operating
Modes
(Cont.)

The Watchdog Mode (Cont.)
Procedure to set up CounterlTimer Registers for Watchdog Mode in this design example:

Counterflimer-2 Registers Initialization

o

Image-2 Register and CNTR2 are loaded with 02(hex), which is the pulse width of
the Watchdog pulse wdog2pld. Normally this value is very large depending on the
application, since software is not supposed to clear the Watchdog very often.

After CNTR2 and IMG2 are initialized, other Registers (Global Command Register and
Software Load/Store Register) must now be initialized.

o

To start the Timers, the Global Command Register has to be initialized to OA(hex),
i.e., the following bits are set.

Global Command Register
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

1

X

1

0

Bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
Bit-1:
Counter start bit: This bit turns on all the selected Timers.
Bit-2: X Global Mode bit: Watchdog is available in both Global modes.
Bit-3: 1 Watch Dog bit: Watchdog Mode (affects only CounterlTimer-2).
The moment the Watchdog bit and Counter start bit in the Global Command Register are
set to 1, the Watchdog counter starts counting down. To avoid the generation of the
Watchdog output pulse, the software must write "1" to bit 2 of the Software Load/Store
Register before the CounterlTimer-2 under flows.

Software Load/Store Register
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

1

0

0

Once the CounterlTimer-2 is configured to operate in the Watchdog Mode, only a hardware
reset can get it out of the Watchdog Mode.

-----------------------------------rJr4r~----------------------------------3-36
====

"SD5XX - Appllcatilln NIt. D2B

Different
Operating
Modes
(Clint.)

The Watchdog Mode (Clint.)
Figure 18 shows the simulation result of the Watchdog Mode. The CounterfTimer software
load bit was not written into after Watchdog Counter-2 decrements from value 2 through o.
Therefore when Counter-2 under flowed, a Watchdog Pulse is generated. This pulse,
wdog2pld, is inverted by the GPLD and is available on the output pin as "wdout".

FlgUM1S. Simulation of Watchdog Mode

cntr2L
img2L
wdog2pld

o

Input Signals:

PSD5XX input clock: TimecClock

o

Outputs:

Watchdog output from CounterfTimer-2: wdog2pld
Watchdog output from GPLD as: wdout

.iFiF#~

------------------------------~~~---------------------------3-~--7

1'SIJ5XX - AppllClltilln IIot. OIB

Blffefllnt
Operating
Modes
(Clint.)

Ths Watchdo, Mods (Clmt.)
Figure 19 shows the Watchdog occurrence is inhibited by writing "04" hex into Software
Load/Store Register before COUNTER-2 under flows. There are four software loads:
the second, third and fourth software loads are done before COUNTER-2 under flowed
(count of 02 = 666ns)

FI,u"

'9. Simulation 01 Inhibition 01 Watchdo, Occu,,,ncs

The tmcsofUd Register is the Software Load/Store Register.
The first software load pulse initializes the Watchdog operation.

Conclusion

PSD5XX offers a powerful set of four PLD macrocell controlled CounterlTimers.
Included in this application note are some of the files generated for the Waveform Mode
application:
Appendix 1•.abl file
Abel file with Counter/Timer logic equations (Waveform mode).
Appendix 2. .crp file
PSD-Global Configuration1 report file (Waveform mode).
Appendix 3. .stl file
Stimulus file simulating Waveform Mode operation.
Appendix 4•.c file
Initializations of PSD5XX Counter!Timer Registers (each of all 5 modes)
based on 80C196 ·C·.
Appendix 5. .asm file
Initializations of PSD5XX Counter/Timer Registers (each of all 5 modes)
based on 68HC11 assembly.
Appendix 6. 4-PWM Timers
This article depicts the realization of 4-PWM Timers on PSD5XX using PPLD.

The .c and .asm initialization files related to PSD5XX operating in each of the five modes
i.e., the Waveform mode, the Pulse mode, the Event Count mode, the Time Capture mode
and the Watchdog mode are available on WSl's Bulletin Board.
iF _ _

'1$

~3-~~'-------------------------------~~~----------------------------------

PSD5XX - Application Not, D2B

Appendix 1.
.ASL File

module wavfrm" 7/20/93
" Full pathname - c:\psdsoft\simulate\wavfrm\wavfrm.abl
title 'wavform mode';
"Input signals

"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a1 0,a9,a8,a1 ,aO pin;
"Output signals
"The Output signal here has been declared in .abl itself, it can
"also be declared in the configuration file as Waveform/Pulse o/p.
"The user can declare it here or in the configuration menu.
PWM_OUT pin 27; "Port A PAO has been aliased as PWM_OUT,
"if selected in the configuration file instead
"of in the .abl file, pin PAO's default name will be ' TimeroutO '
"Internal PSD5XX PLD output signals.
csiop node;

"More outputs using reserved names.

"Definitions

x = .x. ;
Address

"Don't care

=[a17,a16,a15,a14,a13,a12,a11 ,a10,a9,a8,a7,X,X,X,X,a2,a1 ,aO];

equations
csiop = (Address >= "hOeOOO) & (Address <= "hOeOFF) ; " 256 block
END

-----------------------------~~;---------------------------=="'="===
3·39

PSD5XX - Application Not. 028

Appendix 2.
Waveform
Mode
Configuration

*******************************************************************

W S I - PSDsoft Version 1.02B
Output of PSD Configurations

PROJECT:
DEVICE:

wavfrm
PSD503B1

DATE:
TIME:

08/13/1993
10:17:15

BUS INTERFACE
Data bus width
Address/Data Mode
ALE/AS signal
Read/Write signals

8-Bits
Multiplexed
Active High
/WR, /RD

OTHER CONFIGURATIONS

Timer/Counter 0 INPUT
Timer/Counter 0 OUTPUT
Timer/Counter 1 INPUT
Timer/Counter 1 OUTPUT
Timer/Counter 2 WATCH DOG
Timer/Counter 2 INPUT
Timer/Counter 2 OUTPUT
Timer/Counter 3 INPUT
Timer/Counter 3 OUTPUT

OFF
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF

Power Down Clock
Security Function
Interrupt Function

OFF
OFF
OFF

END OF REPORT FILE: wavfrm.crp

-----------------------------------------~~~---------------------------------------3-40
====

PSD5XX - Application Note 028

Appendix 3.
•STL File

Irrhis is a stimulus file to simulate "Waveform" mode of operation of PSD5XX.
/lCounterrrimers 0 and 1 are used in this simulation. The input clock to PSD is 12 MHz.
The /lduty cycle of the output waveform (PWM_OUT) is 33%

/I
/I
/I

User defined parameters

parameter load_store = 'hCOA5, dlcy='hCOA6, cmdO = 'hCOAO, cmd1 = 'hCOA 1;
parameter imgOJobyte = 'hC090, imgO_hibyte = 'hC091, img1_lobyte = 'hC092;
parameter img1_hibyte = 'hC093, cntro_lobyte='hC098, cntro_hibyte = 'hC099;
parameter cntr1Jobyte='hC09A, cntr1_hibyte = 'hC09B, globaLcommand = 'hCOA8;
parameter speciaUunc = 'hC008;
/lUser-Defined tasks
task write (addcbus, data_in);
input [15:01 addcbus;
input [7:01 datajn;
begin
#20
#20
#20

ale = 1;
adio = addcbus;
ale=O;

#20
#40
#100

adio = data_in;
wr= 0;
wr= 1;

end
endtask
task read (addcbus);
input [15:01 addcbus;
begin
#20
#20
#20

ale = 1;
adio = addr_bus;
ale = 0;

#20
#40
#100

adio = Z16;
rd = 0;
rd = 1;

end
endtask
/lEnd user-defined tasks

___________________________________ ' • • aFE
~4f~·--------------------------------3-~--1

P$lJ5XX - Application Not. 02B

Appendix 3.
.STL File

initial
begin

(Cont.)

clkin = 0; reset = 0; csi = 0;
rd = 1; wr = 1; ale = 0;
adio ='hOOOO; PWM_OUT =Z;
#560

reset = 1;

/I CSIOP selection
read('hC002);

IICounter-O Low Byte data initialized to 0
write(cntrOJobyte, 00);
/lend of writing into CounterO Low-byte reg

/lCounter-O High Byte data initialized to 0
write(cntrO_hibyte, 00);
/lend of writing into CounterO High Byte reg

/lCounter-1 Low Byte data initialized to 0
write(cntr1_lobyte, 00);
/lend of writing into CounterO Low Byte reg

/lCounter-1 High Byte data initialized to 0
write(cntr1_hibyte, 00);
/lend of writing into CounterO High Byte reg

l!Writing DLCY data
write(dlcy, 00);
/lend of writing into Dlcy reg

iF:: I!'..II$

-3-~-2--------------------------------YF~5rjr-----------------------------------

PSD5XX - AppllcatlDn NDte 028

Appendix 3.
.STL File
(Cont.)

/!Writing CMD-O data
write(cmdO, 'hD4);

1*
Write "D4"hex to Command Register-O (CMDO) at offset from base address of CSIOP(Chip
Select I/O Port).
Bit-?

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

1

X

X

0

1

0

0

CMDO Register
• bit·O: 0 Mode Select Bit, select Waveform Mode for CTUO.
• bit·1: 0 Decrement/Increment Bit: Select decrement (CTUO counts down from 2 to
At 0, TC triggers the loading and operation of the CTU1).
• bit·2: 1 Select CounterlTimer Bit: Select CTUO.
• bit·3: 0 Output polarity: Select output to be active low (Toff time).
• bit·4: X Input Polarity: No pin input in this mode, don't care.
• bit·5: X Pin or Macrocell input: No pin or macrocell input, don't care.
• bit·6: 1 Load/Store Bit: No pin or macroceilioad/store.
• bit·7: 1 EN/DIS Bit: Enable continuous counting.

o.

*/
/lend of writing into CMDO reg
/!Writing CMD·1 data
write(cmd1, 'hDC);
/*
Write "CC"hex to Command Register 1 (CMD1).
Bit-?

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

1

X

X

1

1

0

0

CMD1 Register
• bit·O: 0 Mode Select Bit, select Waveform Mode for CTU1 ..
• bit·1: 0 Decrement/Increment Bit: Select decrement (CTU1 counts down from 4 to O.
At 0, TC triggers the loading and operation of the CTUO).
• bit·2: 1 Select CounterlTimer Bit: Select CTU1.
• bit·3: 1 Output polarity: Select output to be active on (Ton time).
• bit·4: X Input Polarity: No pin input in this mode, don't care.
• bit·5: X Pin or Macrocell input: No pin or macrocell input, don't care.
• bit·6: 1 Load/Store Bit: No pin or macroceilioad/store.
• bit·7: 1 EN/DIS Bit: Enable continuous counting.

*/
/lend of writing into CMD1 reg

-----------------------------------~Jr~~--------------------------------3-~--

I'SD5XX - Application Note 028

Appendix 3.
.ST! File
(Cont.)

IIIMG-O high byte data written to
write(imgO_hibyte, 00);
/lend of writing into IMGO high byte reg

/lIMG-O data written to Low Byte
write(imgO_lobyte, 04);
/lend of writing into IMGO reg
/lIMG-1 high byte data written to
write(img1_hibyte, 00);
/lend of writing into IMG1 high byte reg

/lIMG-1 data written to Low Byte
/lSetting up address C092h
write(imgUobyte, 02);
/lend of writing into IMG1 reg low byte

/lDeclare port A as special function port, so that TimerO olp is on PAO

l!Write Data of 01 so that PAO has timer-O olp available on its pin
write(speciaUunc, 01);
/lend of writing into special function reg

~~-------------------------------~~~----------------------------------3-44
====

PS05XX - Application Note 028

Appendix 3.
.SrL File

IlWaveform output is first initialized by setting its two corresponding
Iisoftware Load/Store bits after loading the Image Registers .

(Cont.)

IlWriting into software load/store bi'-O and bit_1 for cntcO and cntr_1
write(load_store, 03);

IIStart CounterfTimer-O and CounterfTimer-1 to produce waveform
IIGlobal Reg data written to

write(globaLcommand, 02);

1*
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Global Command Register
• bit·O: 0 Scale Bit: The clock input to the Timers js divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1 ") .
• bit·1: 1 Counter start bit: This bit turns on all the selected Timers.
• bit·2: 0 Global Mode bit: All Counter/Timers operate in Waveform or Pulse Mode.
• bit·3: 0 Watch Dog bit: Not Watchdog Mode (affects only Counter/Timer 2).

*1
Ilend of writing into Global Reg
Ilread data on Load/Store reg, it should be FO
read(load_store);
end
always
#42 clkin = -elkin; 1112 Mhz PSD5xx input clock

-----------------------------------~~~~----------------------------------3·45

PSD5XX - Application Note 028

Appendix 4.
.eFile

/*************************************************************************************************
The following C program illustrates the initialization procedure to operate the PSD5XX
CounterfTimers interfaced with Intel's 80C196.
*************************************************************************************************/

# define CSIOP Ox3000 I*Chip select & 1/0 offset base address *1

I*Global declarations *1
int *CNTRO, *CNTR1, *CNTR2, *CNTR3 ;
int *IMGO, *IMG1, *IMG2 *IMG3 ;
char *dlcy_reg, *CMDO, *CMD1, *CMD2, ·PORTA, *GLOB, * FREEZE_CMD ;
char *STATUS_FLAGS, *SOFTWARE_LD_ST ;

mainO
{
1* Initialization of PSD5XX CounterfTimers *1
CNTRO = (int *) (CSIOP + Ox98);
*CNTRO= 00;

I*CNTRO offset from CSIOP *1
I*CNTRO initialized to 0 *1

CNTR1 = (int *)(CSIOP + Ox9a);
*CNTR1 = 00;

I*CNTR1 offset from CSIOP *1
I*CNTR1 initialized to 0 *1

CNTR2 = (int *) (CSIOP + Ox9c);
*CNTR2 =00;

I*CNTR2 offset from CSIOP *1
I*CNTR2 initialized to 0 *1

CNTR3 = (int *)(CSIOP + Oxge);
*CNTR3 = 00;

I*CNTR3 offset from CSIOP *1
I*CNTR3 initialized to 0 *1

IMGO = (int *) (CSIOP + Ox90);
*IMGO = 00;

I*IMGO offset from CSIOP *1
I*IMGO initialized to 0 *1

IMG1 = (int *)(CSIOP + Ox92);
*IMG1 = 00;

1*IMG1 offset from CSIOP *1
1*IMG1 initialized to 0 *1

IMG2 = (int *)(CSIOP + Ox94);
*IMG2 = 00;

1*IMG2 offset from CSIOP *1
1*IMG2 initialized to 0 *1

IMG3 = (int *)(CSIOP + OX96);
*IMG3= 00;

1*IMG3 offset from CSIOP *1
1*IMG3 initialized to 0 *1

I*Scaling of Clock input, common to all CounterfTimers *1
dlcy_reg = (char *)(CSIOP + Oxa6);
*dlcy_reg = 00;

I*dlcy reg offset from CSIOP */
I*Also Scale-bit is 0*1
I*Refer to Timer Clock Initialization in the
App note for more details *1

1* Now anyone of the following subroutines pulse(), waveform(), evenCcount(),
time_captureO and watchdogO can be called *1
}
/********************************************************************************************** /

-3--4-6----------------------------------~~~-------------------------------------

I'SIJ5XX - Appilcatlllll

Appendix 4.
.CFile

waveformO
{

(Clint.)

/*Loading of Command Register-O (CMDO) */

""tII D2B

CMDO = (char *)(CSIOP + OxAO);/*CMDO register offset from CSIOP*/
*CMDO = Oxd4;
/* Write "D4"hex to Command Register-O (CMDO) at offset from base address of CSIOP
(Chip Select I/O Port).
Blt-?

Blt-6

Bit-S

Blt-4

Blt-3

Blt-2

Blt-1

Blt-Q

1

1

X

X

0

1

0

0

CMDO Register
• bit-G: 0 Mode Select Bit, select Waveform Mode for CTUO.
• bit-1: 0 Decrement/Increment Bit: Select decrement (CTUO counts down from 2 to O.
At 0, TC triggers the loading and operation of the CTU1).
• bit-2: 1 Select Countermmer Bit: Select CTUO.
• bit-3: 0 Output polarity: Select output to be active low (Toff time).
• bit-4: X Input Polarity: No pin input in this mode, don't care.
• bit-5: X Pin or Macrocell input: No pin or macrocell input, don't care.
• bit-6: 1 Load/Store Bit: No pin or macrocell load/store.
• bit-7: 1 EN/DIS Bit: Enable continuous counting.
*/
/*Loading of Command Register 1 (CMD1) */
CMD1 = (char *)(CSIOP + OxA1);/*CMD1 register offset from CSIOP*/
*CMD1 = OxCC;
/*

Write ·CC"hex to Command Register 1 (CMD1).
Bit-?

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

1

X

X

1

1

0

0

CMD1 Register
• bit-G: 0 Mode Select Bit, select Waveform Mode for CTU1.
• bit-1: 0 Decrement/Increment Bit: Select decrement (CTU1 counts down from 4 to O.
At 0, TC triggers the loading and operation of the CTUO).
• bit-2: 1 Select Countermmer Bit: Select CTU1.
• blt-3: 1 Output polarity: Select output to be active on (Ton time).
• blt-4: X Input Polarity: No pin input in this mode, don't care.
• bit-5: X Pin or Macrocell input: No pin or macrocell input, don't care.
• bit-6: 1 Load/Store Bit: No pin or macrocell load/store.
• blt-7: 1 ENIDIS Bit: Enable continuous counting.

*/

------------------------~~/----------------------3-~-7

PSD5XX - Application Not. 028

Appendix 4.
.C File
(Cont.)

/******* Image Registers Loading *******/
IMGO = (int *)(CSIOP + Ox90);
*IMGO = Ox0004;

/* Load the CounterlTimer_O with necessary */
/* off-time needed according to the duty cycle*/

IMG1 = (int *)(CSIOP + Ox92);
*IMG1 = Ox0002;

/* Load the CounterlTimer_1 with necessary */
/* on-time needed according to the duty cyc\e*/

/*Configure portA output pin in Special Function Out */
PORTA = (char *)(CSIOP + OX08);
*PORTA =Ox0001;

/* Get Special Function Register of PORT A */
/* Activate pin PAO as PWM_OUT.
Timer-O and Timer-1 are internally connected */

/*A waveform output is first initialized by setting its two corresponding software Load/Store
bits after loading the image registers * /
SOFTWARE_LD_ST =(char *)(CSIOP + OxA5);
*SOFTWARE_LD_ST = Ox0003;
/*** Global register configuration ***********/
GLOB = (char *) (CSIOP + Oxa8);
*GLOB = Ox02;
/*

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Global Command Register
• bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
• bit-1: 1 Counter start bit: This bit tums on all the selected Timers.
• bit-2: 0 Global Mode bit: All CounterlTimers operate in Waveform or Pulse Mode .
• bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only CounterlTimer 2).

*/
/*When the Global Command Register is written to the Counter/Timers start decrementing
and at underflow of each timer corresponding waveforms can be noticed on port A at
PWM_OUT .*/
printf("waveform program");

}
/****************************************************/

-3-4-8----------------------------------~~~-------------------------------------

PS05XX - Application Note 028

Appendix 4.
.C File

{

(Cont.)

I*Loading of CounterfTimer-O i.e Command Register 0 (CMDO) *1

pulseO

CMDO = (char *)(CSIOP + OxaO);I*CMDO register offset from CSIOP *1
*CMDO =Ox9D;

1*
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

1

1

0

1

CMDO Register
•
•
•
•
•
•
•
•

bit-O:
bit-1:
bit-2:
bit-3:
bit-4:
bit-5:
bit-6:
bit-7:

1
0
1
1
X
0
0
1

Mode Select Bit, select Pulse Mode for CTUO.
Decrement/Increment Bit: Select decrement (CTUO counts down from 3 to 0).
Select CounterfTimer Bit: Select CTUO.
Output polarity: Select output pulse to be active high.
Input Polarity: No pin input in this mode, don't care.
Pin or Macroceli input: Macroceli input control.
LoadlStore Bit: Enable Load control by macroceli output.
ENIDIS Bit: Enable continuous counting.

*1
1***** Image Register Loading ******* I
1* Load the CounterfTimer_O with necessary count i.e Pulsewidth needed *1
IMGO = (int *)(CSIOP + Ox90);
*IMGO =Ox0003;
I*Configure portA output as Special Function Out so that TimerO olp is on PAO as
pulseO_out * I
PORTA = (char *)(CSIOP + Ox08); 1* Get Special Function Register of PORT A *1
* PORTA = Ox0001;
1* Activate pin PAO as Timer-O output* I

--------------------------------~~~~-------------------------------3-49

PSD5XX - Application Note 028

Appendix 4.
.eFi/e
(Cont.)

/*** Global register configuration ***********/
GLOB = (char *)(CSIOP + Oxa8);
*GLOB = Ox02;
/*

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Global Command Register
• bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
• bit-1: 1 Counter start bit: This bit turns on all the selected Timers .
• bit-2: 0 Global Mode bit: All Counter/Timers operate in Waveform or Pulse Mode.
• bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only Counter/Timer 2).

*/
/*Now, if the conditions setup in PPLD for mc2tmrO are satisfied, a pulse of pulsewidth
can be noticed on port A PAO (pulseO_out) until CounterlTimer-O underflows. * /

=03

printf("pulsewidth program");

}
/******************************************************/

-------------------------------------r-=~~------------------------------------3-50

====

PSD5XX - Application Not. 028

Appendix 4.
.CFile
(Cont.)

evenccount()

{
/*Loading of CounterrTimer-O i.e Command Register 0 (CMDO) */
CMDO = (char *)(CSIOP + OxaO);/*CMDO register offset from CSIOP*/
*CMDO = Ox1 E;
/*

Loading of Command Register 0 (CMDO) at offset AO(hex) from CSIOP'.
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

X

X

1

1

0

CMDO Register
•
•
•
•
•
•
•
•

bit-O:
bit-1:
bit-2:
bit-3:
bit-4:
bit-5:
bit-6:
bit-7:

0
1
1
X
X
0
0
0

Mode Select Bit, select Event Count Mode for CTUO.
Decrement/Increment Bit: Increment after every event.
Select CounterrTimer Bit: Select CTUO.
Output polarity: No timer output, don't care.
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Store control from macrocell.
EN/DIS Bit: Enable or disable by macrocell.

*/
/***** Image Register Loading *******/
/* Initialize IMGO at 0000 */
IMGO = (int *)(CSIOP + Ox90);
*IMGO =OxOOOO;
/*** Global register configuration *********** /
GLOB = (char *)(CSIOP + Oxa8);
*GLOB = Ox06;

/*
Bit-7

Bit-6

Bit-S

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

1

1

0

Global Command Register
• bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
• bit-1: 1 Counter start bit: This bit turns on all the selected Timers.
• bit-2: 1 Global Mode bit: All CounterlTimers operate in Event Count or
Time Capture Mode.
• bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only CounterlTimer 2).
*/

'CSIOP is Chip Select of the InpuVOutput Port.

-------------------------------------~~~-------------------------------------

====

3-51

PSD5XX - Application Nots 028

Appendix 4.
.C File
{Cont.}

I*Now, if the conditions setup in PPLD for mc2tmrO are satisfied as specified in the Abel
software, at every transition on mc2tmrO Counter-O increments its count * I

I * Freeze Command Register* I
1* If the Event count value in the counter needs to be read, the count updates to the image
register have to be frozen * I

I * To Freeze updates to IMGO Register, set bit·O of Freeze Command Register to "1" * I
FREEZE_CMD = (char *)(CSIOP + Oxa4);
* FREEZE_CMD

=Ox01;

1* Freeze acknowledge Register*1
I*Wait for the freeze acknowledge bit to be set and then proceed to read the Event count
value stored in the image register*1
STATUS_FLAGS = (char *)(CSIOP + Oxa9);
while (((*STATUS_FLAGS) & Ox01) == Ox01);
printf("lmage_O register %x", (* IMGO));

1* FREEZE ACKNOWLEDGE BIT 0 * I

=

I*The FREEZE CMD bit 0 of CounterlTimerO must be cleared to 0 and set back to 1, if
another IMGO Register reading needs to be done'l
FREEZE_CMD = (char *)(CSIOP + Oxa4);
* FREEZE_CMD =OxOO;

printf("Event Count program");

}
/*****************************************************I

-3--S-2--------------------------------~~~-----------------------------------

PS05XX - Application Nots 028

Appendix 4.
.C File
{Cont.}

time_capture()

{
/*Loading of CounterlTimer 0 i.e Command Register 0 (CMDO) */
CMDO = (char *)(CSIOP + OxaO);/*CMDO register offset from CSIOP*/
*CMDO =OxBF;
/*

Loading of Command Register-O (CMDO) at offset AO(hex) from 2CSIOP.
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

X

0

1

1

X

1

1

1

CMDO Register
bit-O:
bit-1:
o bit-2:
o bit-3:
o bit-4:
o bit-5:
o bit-6:
o bit-7:
o
o

1
X
1
X
1
1
0
X

Mode Select Bit, select Time Capture Mode for CTUO.
Decrement/Increment Bit: Increment mode.
Select CounterlTimer Bit: Select CTUO.
Output polarity: No timer output, don't care.
Input Polarity: Active low.
Pin or Macrocell input: Pin input control.
Load/Store Bit: Store control from pin.
EN/DIS Bit: Don't care, setting of bit-2 enables the Counter.

*/
/***** Image Register Clearing *******/
IMGO = (int *)(CSIOP + Ox90);
* IMGO =OxOOOO;
/*Loading of CounterlTimer-1 i.e Command Register 1 (CMD1) */
CMD1 = (char *)(CSIOP + Oxa1);/*CMD1 register offset from CSIOP*/
*CMD1 = Ox9f;
/*
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

X

0

0

1

X

1

1

1

CMD1 Register
bit-O:
bit-1:
o bit-2:
o bit-3:
o bit-4:
o bit-5:
o bit-6:
o bit-7:
o
o

1
1
1
X
1
0
0
X

Mode Select Bit, select Time Capture Mode for CTUO.
Decrement/Increment Bit: Increment mode.
Select CounterlTimer Bit: Select CTUO.
Output polarity: No timer output, don't care.
Input Polarity: Active low.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Store control from pin.
EN/DIS Bit: Don't care, setting of bit-2 enables the Counter.

*/

-----------------------------------~jfF~----------------------------------====
3-53

I'IIIJ5XX - App"alllll .",. _

Appendix 4.
.CFlle
{CIIIt"

1***** Image Register Clearing *******1
IMG1 =(int *)(CSIOP + ox92);
*IMG1 =OxOOOO;
/*** Global register configuration ***********1
GLOB = (char *)(CSIOP + Oxa8);
*GLOB =Ox06;

1*
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

1

1

0

Global Command Register

• bit-o: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
• blt·1: 1 Counter start bit: This bit turns on all the selected Timers.
• blt·2: 1 Global Mode bit: All CounterlTimers operate in Event Count or
Time Capture Mode.
• bit-3: 0 Watch Dog bit: Not Watchdog Mode (affects only CounterlTimer 2).

*1
I*Now, if the conditions setup in PPLD for mc2tmr1 are satisfied as specified in the Abel
software, at every rising edge transition on input pin PE3 and mc2tmr1, Counter-O and
Counter-1 transfer their count values into the image register-O and image register-1 *1
I*Freeze Command Register*1

1*lf Time Capture value in the Image register need to be read, the count updates to the
image register have to be frozen *1
1* To freeze updates to IMGO, set bit-O of Freeze Command Register to "1" */
FREEZE_CMD = (char *)(CSIOP + Oxa4);
*FREEZE_CMD = OX01;
1* A high going signal of write freezes the image updates *1
I*Freeze acknowledge Register*1
I*Wait for the freeze acknowledge bit to be set and then proceed to read the Time Capture
value stored in the image register*1
STATUS_FLAGS = (char *)(CSIOP + Oxa9);

-a~-----------------------~Jr;------------------------

'BlJ5XX - AppllatllHl "",. _

Appendix 4.
.CFlIs
(Cont.)

1* Microcontroller loops around the Freeze Acknowledge bit 0: if it's set to 1, then it
proceeds to read the image-O register for time-capture value *1

while«(*STATUS_FLAGS) & Ox01) == OX01);
printf("lmage_reg_O=%x\n", (* IMGO»;
I*The FREEZE CMD bit 0 of CounterfTimer-O must be cleared to 0 and set back to 1 if
another IMGO Register reading needs to be done * 1
FREEZE_CMD = (char *)(CSIOP + Oxa4);
*FREEZE_CMD = OxOO;
I*Now to read the IMG1 Register *1
*FREEZE_CMD = OX02;
I*A high going signal of write freezes the image updates *1
I*Freeze acknowledge Register*1
I*Wait for the freeze acknowledge bit to be set and then proceed to read the Time Capture
value stored in the image register *1

STATUS_FLAGS = (char *)(CSIOP + Oxa9);
1* Microcontroller loops around the Freeze Acknowledge bit 1: if it's set to 1, then it
proceeds to read the image-1 register for time-capture value *1
while «(*STATUS_FLAGS) & Ox02) == OX02);
printf("lmage_re9-1%x =\n", (*IMG1»;
I*The FREEZE CMD bit 10f CounterfTimer1 must be cleared to 0 and set back to 1 if
another IMG1 Register reading needs to be done *1
FREEZE_CMD = (char *)(CSIOP + Oxa4);
*FREEZE_CMD = OxOO;
I*From captured values in image registers pulsewidth can be computed.*1

printf("Time_capture program");
}
r***********************··********··************·I

-------------------------~~i------------------------~~~

PSD5XX - Application Note 028

Appendix 4.
.C File
(Cont.)

watchdogO

{
1*lgnore CounterlTimer-2 Command Register 2 (CMD2) *1

1***** Image Register Loading *******1
IMG2 = (int *)(CSIOP + Ox94);
*IMG2 = Ox0002;
I*Writing into SOFTWARE LOAD reg to load Countec2 *1
SOFTWARE_LD_ST = (char *)(CSIOP + Oxa5);
SOFTWARE_LD_ST = Ox04;
/*** Global register configuration ***********/
GLOB = (char *) (CSIOP + Oxa8);
*GLOB = OXOa;
1*
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

1

X

1

0

Global Command Register
• bit-O: 0 Scale Bit: The clock input to the Timers is divided by 1. This is the first clock
pre-scaler stage (selecting between "divide by 8" or "divide by 1").
• bit-1: 1 Counter start bit: This bit turns on all the selected Timers.
• bit-2: X Global Mode bit: Watchdog is available in both Global modes.
• bit-3: 1 Watch Dog bit: Watchdog Mode (affects only CounterlTimer-2).

*1
I*As soon as the WatchDog bit in the Global Command Register is set to one,
CounterlTimer-2 starts decrementing. If a software load command is not executed before
Counter-2 underflows, watchdog condition occurs *1

printf("watchdog program");

}
/**••• ********************************************/

---_IE

~3-~~6--------------------------------~"~-----------------------------------

PSD5XX - Application Nots 028

Appendix 5.
.ASMFile

*This is the common initialization of WSI's PSD5XX timers
*interfaced with Motorola's 68HC11, using 68HC11 Assembly.
*MemoryMap

*
EPROM(1)
RAM
I/O
EPROM(2)
RAM
1/0& REG

aOOO
4000
3000
5000
1000
0000

org

$aOOO

Program Memory

equ
equ
equ
equ

$103d
$3000
$10ff
$1002

RAM & I/O mapping reg (68HC11)
chip select i/o port addr (PSD5XX)
stack area
basic RAM storage area

*
*
*
*
*

init
csiop
stack
stor

ffff
4fft
3fff
6fff
10ff
003f

(Program PSD5XX)
(RAM PSD5XX)
(CSIOP PSD5XX)
(Data PSD5XX)
(68HC11)
(68HC11)

****** Begin main program ***********
start

sei
Idaa
staa

#010h
init

Set IRa mask
set RAM at 1000
and set registers at 103d

nop
Idaa

#Oe3h

slight delay to allow registers setup
setup option reg.-ADPU = 1,CSEW = 1,IROE = 1

Ids

#stack

setup stack

******* Initialize PSD5XX COUNTERITIMER Counter and Image Registers**********
Idx
stx
stx
stx
stx
stx
stx
stx
stx

#0
csiop+98h
csiop+99h
csiop+9ah
csiop+9bh
csiop+9ch
csiop+9dh
csiop+geh
csiop+9fh

clear counter/timer 0 CNTRO(low byte)
clear counter/timer 0 CNTRO(high byte)
clear counter/timer 1 CNTR1 (low byte)
clear counter/timer 1 CNTR1 (high byte)
clear counter/timer 2 CNTR2(low byte)
clear counter/timer 2 CNTR2(high byte)
clear counter/timer 3 CNTR3(low byte)
clear counter/timer 3 CNTR3(high byte)

stx
stx
stx
stx
stx
stx
stx
stx

csiop+90h
cSiop+91h
csiop+92h
csiop+93h
csiop+94h
cSiop+95h
csiop+96h
csiop+97h

clear counter/timer 0
clear counter/timer 0
clear counter/timer 1
clear counter/timer 1
clear counter/timer 2
clear counter/timer 2
clear counter/timer 3
clear counter/timer 3

IMGO(low byte)
IMGO(high byte)
IMG1 (low byte)
IMG1 (high byte)
IMG2(low byte)
IMG2(high byte)
IMG3(low byte)
IMG3(high byte)

*******Scaling of clock input, common to all counter/timers****
Idx
stx

#OOOOh
cSiop+$a6

=

dlcy 0 (delay cycle reg)
Regarding scale-bit, it'll be set in global reg

**********END OF COMMON INITIALIZATION ***************

----------------------------------~~Ar--------------------------------3-57
--------~--~

--~~~ --~-----

~~~

I'SD5XX - Application Not. 028

Appendix 5.
.ASMFile
(Cont.)

*BASED ON THE MODE OF OPERATION THE FOLLOWING ROUTINES CAN BE USED*
*This is the implementation of ·WAVEFORM MODE" of operation of WSI's PSD5XX
*interfaced with Motorola's 68HC11
*******Counter/Timer 0 initialization (Command Reg 0 i.e. CMDO)
Idx
stx

#OOd4h
cSiop+$aO

*

*
*

*
*
*
*
*

Waveform mode
Decrement mode
select counterltimer
output pulse active low
input polarity on input pin (doesn't matter here)
input control not from PPLD or PIN, don't care
load/store by software
enable continuous counting

*******Counterltimer 1 initialization (Command Reg 1 i.e. CMD1)
Idx
stx

#OOcch
cSiop+$a1

*
*
*
*

*
*
*

Waveform mode
Decrement mode
select counterltimer
output pulse active high
input polarity on input pin (doesn't matter here)
input control not from PPLD or PIN, don't care
load/store by software
enable continuous counting

*

******Image reg (IMGO) loading*************
Idx
stx
Idx
stx

#OO04h
csiop+90h
#OOOOh
cSiop+91 h

load counterltimerO image reg with necessary
count i.e. pulse width needed (off time)

****** image reg(IMG1) loading*************
Idx
stx
Idx
stx

#OO02h
csiop+92h
#OOOOh
csiop+93h

load counterltimer1 image reg with necessary
count i.e. pulse width needed (on time)

~3~.58~------------------------------~Jr~Ar---------------------------------

PSD5XX - Appllcatilln Nllte 028

Appendix 5.
.ASMFile

** A waveform output is first initialized by setting its two corresponding**
**software load/store bits after loading the image registers ***

(Clint.)

Idx
stx

#0003h
cSiop+$a5

**Configure port A output as special function so that waveform output is available at PAO**
Idx
stx

#0001h
cSiop+08h

Activate pin PAO as waveform output
special function reg of port A

******* global register configuration *********
Idx

#0002h

stx

cSiop+$a8

*
*

*

non-watchdog mode
Waveform mode/pulse
all ctus enabled
Scale bit 0

*The counters are always enabled by the software and a waveform
*can be noticed on port A PAO.
*PWM pulse widths equal to count of 04 loaded in the image-O register and 02 in IMG1.

******************** END OF WAVEFORM MODE ********************

-------------------------~,:------------------------ "'"&.

3·59

PS05XX - Appllt:lltl.R N.ts 028

Appendix 5.
.AS.File

*This is the implementation of "PULSE MODE" of operation of WSI's PSD5XX
* interfaced with Motorola's 68HC11 .

(C'Rt.)
******* Counter/Timer 0 initialization (Command Reg 0 i.e. CMDO)
Idx
stx

#009dh
cSiop+$aO

*
*
*
*
*
*
*
*

pulse mode
decrement mode
select counter/timer
output pulse active high
input polarity on input pin (doesn't matter, here it's mcell)
input control from PPLD (not PIN)
load control activated by macrocell output
enable continuous counting

****** image-O reg loading *************
Idx
stx
Idx
stx

#0003h
csiop+90h
#OOOOh
csiop+91 h

load counter/timerO image reg with necessary
count i.e. pulse width needed

*** Configure port A output as special function so that TimerO output is available at PAO ***
Idx
stx

#0001h
csiop+08h

Activate pin PAO as TimerO output
special function reg of port A

******* global register configuration *********
Idx
stx

#0002h
cSiop+$a8

non-watchdog mode
Waveform/pulse mode
all ctus enabled
Scale bit 0

*Appropriate signals on mc2tmrO starts the counter and a pulse
*can be noticed on port A PAO (based on the .abl equation) till Counter/timer-O under flows.

*************************** END OF PULSE MODE ***************************

~~

3·60

___________________________________

'Sa;~~

====

______________________________________

'SD5XX - Application Mottl 028

Appendix 5.
.AS.File
(Cont.)

*This is the implementation of "EVENT MODE" of operation of WSI's PSD5XX
* interfaced with Motorola's 68HC11
*******Counter/Timer 0 initialization (Command Reg 0 i.e. CMDO)
Idx
stx

#1eh
cSiop+$aO

*
*
*
*
*
*
*

Event Count mode
increment mode
select counter/timer
CounterlTimer output (don't care)
input polarity on input pin(doesn't matter not PIN)
input control from PPLD (not PIN)
Store control activated by macrocell
enable activated by macrocell

* Image and Counter Registers are initialized to "00" in the beginning
*******global register configuration*********
Idx
stx

#0002h
cSiop+$a8

*
*
*

non-watchdog mode
Event CountlTime Capture mode
all ctus enabled
Scale bit 0

* Now, if the conditions setup in PPLD for mc2tmrO are satisfied as specified
* in Abel software, at every rising transition on mc2tmrO Counter-O increments its count.
* and updates the IMGO Register.
********Freeze Command register*********
*If the Event Count value in the Counter register need to be read, the count
*updates to the image register have to be frozen.
Idx
stx

#0001h
cSiop+$a4h

a high going signal of write freezes IMGO updates

* Now check if Freeze Acknowledge bit of Counter-O is set and read IMGO reg ev_loop
Idx
Idaa
cmpa
bne

#(csiop+$a9h)
#$fO
O,X
ev_loop

freeze acknowledge bits(status flag reg)
bit 0 for timer-O(upper 4 bits are 1's)
checking if it's set to 1

* Read IMGO reg
Idx
Idx

# (csiop+$90h)
# (csiop+$91 h)

low byte
high byte

*To do another read of the Event Count value, the Freeze Command Register bit 0 has to
cleared to 0 and set back to 1, when necessary.
Idx
stx

#OOOOh
cSiop+$a4h

a 0 clears the FREEZE CMD bit 0 to 0

******************END OF EVENT COUNT MODE ******************

.,JEI!1'._
--------------'NI§
-------------a--6-1

I'SD5XX - Appllclltilln

Appendix 5.
.ASMFile

''1t, 028
*This is the implementation of "TIMER CAPTURE MODE" of operation of WSI's PSD5XX
* interfaced with Motorola's 68HC11

(Clint.)
*******Counter/Timer 0 initialization (Command Reg 0 i.e. CMDO)
Idx
stx

#OObfh
cSiop+$aO

*
*
*
*

*
*

*

Time-Capture mode
increment mode(don't care)
select counter/timer
Counter/Timer output(don't care)
Input polarity active low
input control from PIN(not PPLD macrocell)
Store control activated by pin
en/dis bit don't care, select counter bit is enough

*
*Image and Counter Registers are initialized to "00" in the beginning
*******Counterltimer 1 initialization (Command Reg 1 i.e. CMD1)
Idx
stx

#009fh
csiop+$a1

*
*
*

*
*
*
*

Time-Capture mode
increment mode
select counter/timer
Counter/Timer output (don't care)
input polarity on input pin (doesn't matter)
input control from PPLD (not PIN)
Store control activated by macrocell
en/dis bit don't care, select counter bit is enough

*
*Image and Counter Registers are initialized to "00" in the beginning
*******global register configuration*********
Idx
stx

#0006h
cSiop+$a8

*

*
*

non-watchdog mode
Event Count/Time Capture mode
all ctus enabled
Scale bit 0

*Now, if the conditions setup on PE3 and in PPLD for mc2tmr1 are satisfied as specified in
* Abei software, at every transition on PE3 and mc2tmr1, the Counter-O transfers its count
*value into the image register-O and the Counter-1 to IMG1.
*Freeze Command register bit 0 for CounterlTimer-O
*If the Time Capture value in the image register needs to be read, the count
*updates to the image register have to be frozen.
Idx
stx

#0001h
cSiop+$a4h

a high going signal of write freezes IMGO updates

-------------------------------------fAfAf~~--

3.62

'fifFBi# if

___________________________________

1'SIJ5XX - AppllClltion Note 02B

Appendix 5.
.ASMFlle
(t:ont.)

*Now check if Freeze Acknowledge bit of Counter-O is set and read IMGO reg tcO_loop
Idx
Idaa
cmpa
bne

# (csiop+$aSh)
#$fO
0, x
ev_loop

freeze acknowledge bits(status flag reg)
bit 0 for timer-O(upper 4 bits are 1's)
checking if it's set to 1

*Read IMGO reg
Idx
Idx

# (csiop +$ SOh)
#(cslop+$S1h)

low byte
high byte

*To do another read of the Time Capture value, the Freeze Command Register bit 0
*has to cleared to 0 and set back to 1, when necessary.
Idx

stx

#OOOOh
csiop+$a4h

a 0 clears the FREEZE CMD bit 0 to 0

* Freeze Command register bit 1 for CounterlTimer-1
* If the Time Capture value in the image register needs to be read, the count
* updates to the image register have to be frozen.
Idx
stx

#0002h
cSiop+$a4h

a high going signal of write freezes IMG1 updates

*Now check if Freeze Acknowledge bit of Counter-1 is set and read IMG1 reg tcCloop
Idx
Idaa
cmpa
bne

# (csiop+$aSh)
#$f1
O,x
tcCloop

freeze acknowledge bits (status flag reg)
bit 1 for timer-1 (upper 4 bits are 1's)
checking if it's set to 1

*Read IMG1 reg
Idx
# (csiop+$S2h)
low byte
high byte
Idx
# (csiop+$S3h)
*To do another read of the Time Capture value, the Freeze Command Register bit 1
*has to cleared 0 and set back to 1, when necessary.
Idx

stx

#OOOOh
cSiop+$a4h

a 0 clears the FREEZE CMD bit 1 to 0

**************** END OF TIME CAPTURE MODE ****************

-------------------------~~JI.-----------------------"'" ~

3-63

PSD5XX - Application Note 028

Appendix 5.
.ASMFile

*This is the implementation of "WATCHDOG MODE" of operation of WSI's PSD5XX
*interfaced with MOTOROLA's 68HC11

(Cont.)
*******Counter/Timer 2 initialization
******** Ignore (Command Reg 02ie CMD2)
******* image reg (IMG2)loading***************
Idx
stx
Idx
stx

#0002h
csiop+94h
#OOOOh
csiop + 95h

load counter/timer2 image reg with necessary
count i.e. pulse width needed

**Writing into SOFTWARE LOAD reg to load Counter-2 *****
Idx
stx

#0004h
cSiop+$a5h

Software load for counter-2

*******global register configuration *********
Idx
stx

#OOOah
cSiop+$a8

*
*
*

watchdog mode
Waveform/pulse mode (don't care)
all ctus enabled
Scale bit 0

*** As soon as the WatchDog bit in the Global Command Register is set to one,
*CounterlTimer-2 starts decrementing. If a write into bit-2 of software load register is not
*done before Counter-2 under flows, a watchdog condition occurs.

loop

nop
jmp

loop

end of main loop

******************** END OF WATCHDOG MODE ********************

~~-----------------------------------r=-~~-------------------------------------3-64

====

PSD5XX - AppllclltlllR Nllte 028

Appendix 6.
Realizing

4PWM

Timers on the
PS05XX

Abstract
The PSD5XX has four timers. The Waveform mod~ or the PWM mode needs two timers,
i.e. one to drive the ON time and second one to drive the OFF time. Therefore a maximum
of two PWM timer sets can be realized on the PSD5XX. Using the resources of the PPLD
however, effectively four PWM timers can be realized. This application brief explains the
procedure to "realize 4 PWM timers on the PSD5XX".

The I'I'LD methDd fDr realizing 4 I'WM Timers
In the normal pulse mode operation, a CounterfTimer outputs a mono-shot pulse of
pulsewidth equal to the value loaded into its associated image register. After the pulse is
output the CounterfTimer waits for another load signal to output another pulse and so on.
The procedure used here to generate 4 PWM timers is as follows:

o
o

Set all the four timers into the "pulse mode" of operation.
Use the "PWM_CYCLE" signal which is described below, to generate the LOAD signal
for Counter/Timer 0, 1, 2 and 3.

o

Counter/Timer Image Registers (IMGO,IMG1,IMG2,IMG3) can be loaded with different
"OFF" or "ON" time values based on the mode set up in CMD Registers.

o

Regarding the duty cycle calculation of the resulting PWM waveform, refer to the
section "Duty cycle calculation".

The I'WM_CYCLE Signal
In this application note example the period of the output PWM waveforms generated by the
CounterfTimers operating in the PULSE mode is controlled by the PWM_CYCLE signal.
The PWM_CYCLE signal in this example has been generated internally in the PSD5XX
itself as a GPLD macrocell output. Here the period of the PWM_CYCLE signal is equal to
the PSD5XX clock input divided by 32.
How the generation of the PWM_CYCLE signal is done is up to the user, typically it is
generated externally with longer period.
Input the PWM_CYCLE signal into the CounterfTimer macrocell input, which is the input
control for loading the Counter/Timer Registers from the corresponding Image Registers.
This can be done in the .ABL file using the following PPLD equation:
mc2tmrX := PWM_CYCLE.fb ;
where X = 0, 1, 2, 3 for the CounterfTimers 0,1,2 and 3 and all CounterfTimers are
operating in PULSE mode.
Note: In case PWM_CYCLE is an external input signal, the expression for mc2tmrX will be:
mc2tmrX := PWM_CYCLE ;

-----------------------------------~~.----------------------------------~8
3-65

PSD5XX - Appilcatilln Nllt. 028

Appendix 6.
Realizing

41'WM
Timers Dn the

Counter/Timer Registers set-up procedure to realize the 4 PWM Timers
CMDO, CMD1, CMD2 and CMD3 Registers Initialization

o

I'SD5XX
(Clint.)

Write "95"hex to Command Register 0 (CMDO) at offset from base address of CSIOP
(Chip Select I/O Port).
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

0

1

0

1

CMDO Register

• bit-O:
• bit-1:
• bit-2:
• bit-3:
• bit-4:
• bit-5:
• bit-6:
• bit-?:

o

1
0
1
0
X
0
0
1

Mode Select Bit, select Pulse Mode for CTUO.
DecremenVlncrement Bit: Select decrement (CTUO counts down from 1 to 0).
Select Counter/Timer Bit: Select CTUO.
Output polarity: Select output to be active low.
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Load control from macrocell.
EN/DIS Bit: Enable continuous counting.

Write "9D"hex to Command Register 1 (CMD1) at offset from base address of CSIOP
(Chip Select I/O Port).
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

1

1

0

1

CMD1 Register

• bit-O:
• bit-1:
• bit-2:
• bit-3:
• bit-4:
• bit-5:
• bit-6:
• bit-7:

o

1
0
1
1
X
0
0
1

Mode Select Bit, select Pulse Mode for CTU1.
DecremenVlncrement Bit: Select decrement (CTU1 counts down from 2 to 0).
Select CounterlTimer Bit: Select CTU1.
Output polarity: Select output to be active high.
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Load control from macrocell.
EN/DIS Bit: Enable continuous counting.

Write "95"hex to Command Register 2 (CMD2) at offset from base address of CSIOP
(Chip Select I/O Port).
Bit-?

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

0

1

0

1

CMD2 Register

• bit-O:
• bit-1:
• bit-2:
• bit-3:
• bit-4:
• bit-5:
• bit-6:
• bit-7:

1
0
1
0
X
0
0
1

Mode Select Bit, select Pulse Mode for CTU2.
DecremenVlncrement Bit: Select decrement (CTU2 counts down from 3 to OJ.
Select CounterlTimer Bit: Select CTU2.
Output polarity: Select output to be active low.
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Load control from macrocell.
EN/DIS Bit: Enable continuous counting.

-----------------------------------rJr"~~----------------------------------3-66
====

PSD5XX - Application Not. 028

Appendix 6.
Realizing

o

4PWM
Timers on the

PSD5XX
(Cont.)

Write "9D"hex to Command Register 3 (CMD3) at offset from base address of CSIOP
(Chip Select I/O Port).
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

1

0

0

X

1

1

0

1

CM03 Register
•
•
•
•
•
•
•
•

bit-O:
bit-1:
bit-2:
bit-3:
bit-4:
bit-5:
bit-6:
bit-7:

1
0
1
1
X
0
0
1

Mode Select Bit, select Pulse Mode for CTU3.
Decrement/Increment Bit: Select decrement (CTU3 counts down from 4 to 0).
Select Counter/Timer Bit: Select CTU3.
Output polarity: Select output to be active high.
Input Polarity: No pin input in this mode, don't care.
Pin or Macrocell input: Macrocell input control.
Load/Store Bit: Load control from macrocell.
EN/DIS Bit: Enable continuous counting.

Image Registers loading:

o
o
o
o

IMGO Register is loaded with a value 01 to define pulse width (off time).
IMG1 Register is loaded with a value 02 to define pulse width (on time).
IMG2 Register is loaded with a value 03 to define pulse width (off time).
IMG3 Register is loaded with a value 04 to define pulse width (on time).

After the Command Registers and Image Registers are initialized, the Registers common to
all the CounterlTimers(Special function Register, Global Command Register) are initialized.

o

Write "OF" to Port A Special Function Register. This specifies pins PAO,PA 1,PA2 and
PA3 as pulse output pins.
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

1

1

1

1

Special Function Register

o

Now to start the Counter/Timers: write "02" hex to the Global Command Register.
Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-O

0

0

0

0

0

0

1

0

Global Command Register
•
•
•
•

bit-O:
bit-1:
bit-2:
bit-3:

0
1
0
0

Scale Bit: Clock input to Timers is divided by 1.
Counter start bit: This bit turns on the Timer operation.
Global Mode bit: All CounterlTimers operate in the Waveform or the Pulse Mode.
Watch Dog bit: Not Watchdog Mode.

Figure 20 illustrates the flow chart for initialization procedure to realize 4 PWM
timers on PSD5XX.

-----------------------------------~~~~--------------------------------3--6--7

PSD5XX - Application Note 928

Appendix 6.
Realizing

Figure 20. PSD5XX InitializatiDn TD Generate 4 PWM Timers

4PWM
Timets Dn the

PSD5XX

1

(Cont.)
START 4 PWM
TIMERS
INITIALIZATION

1
INITIALIZE
DLCY
REGISTER
FOR CLK INPUT

1
SET ALL
4 TIMERS
INTO PULSE
MODE

I

INITIALIZE
ALL 4
TIMERCMD
REGISTERS

1
WRITE OFF/ON
TIMER VALUES
INTO IMGO,
IMG1, IMG2, IMG3

1

DECLARE PORT A
AS SPECIAL
FUNCTION
FOR TIMER OlPs

I

1
INITIALIZE 1s1
TIMER PULSE OIP
BY WRITING OFh
INTO SOFTWARE
LOADISTORE
REGISTER

1
INITIALIZE
GLOBALCMD
REGISTER
START TIMERS
O,1,2AND3
TOGETHER

1

4PWM
INITIALIZATION
DONE

-3--U--------------------------~~~---------------------------

PSD5XX - Application Note 028

Appendix 6.
Realizing

4PWM

As illustrated in the following Figure 21, the PWM_CYCLE signal is used as the
Counterffimer load control signal. The period of the PWM_CYCLE is the period of the
PWM waveforms.

Timers on the
PSDSXX
(Cont.}

timerout1
timerout2
timerout3
Timer-Clock
ImgOL
img1L
img2L
img3L
cmdO
cmd1
cmd2
cmd3

"

!

I

0"1

'

,

Notice in Figure 21, the Image Registers are loaded as follows:
Image RegisterO = 01 hex and the output of this CounterffimerO is timeroutO(on time)
Image Register1 = 02hex and the output of this Counterffimer1 is timerout1(off time)
Image Register2 = 03hex and the output of this Counterffimer2 is timerout2(on time)
Image Register3 = 04hex and the output of this Counterffimer3 is tlmerout3(off time)
The Command Registers are loaded as follows:
CMDO = 95hex
CMD1
9Dhex
CMD2 = 95hex
CMD3 = 9Dhex

=

..

~.,
-------------------------------------,==

~.-------------------------------------

3·69

ntJ5XX - ApplicatlOll ".,.

AppendlxB.
Realizing

4'WM

Timers DR the
'SD5XX

12.

Duty CycIII calculatlDn
Figure 22 explains the duty cycle calulatlons. The 'PWM PERIOD" and 'off" time of the
PWM waveform are known. To compute the "on" time of the PWM waveform and hence
the duty cycle:
Ton = (PWM PERIOD) - Toff

(COlI'.)

Ton
PWM Duty Cycle =

PWM PERIOD

This calculation is applicable to CounterlTimers 0 and 2 whose outputs are programmed to
be active low. For Counter/Timers 1 and 3 the outputs are programmed to be active high,
hence the 'on" time Is the value directly loaded into the related Image Registers multiplied
by the Timer Clock unit.

FI,uflllI. Duty Cyclll Plllllld

II' PWAf Usln, PI'LD MaclllclIII TllchnlqulI

,,
,

,,
,

,
I

PWM_CYCLE

I
I

---J

I-I----.L..-__. .
U
u

---u
I

I

I

I

I

I

I

TlMEROUTO
(PULSE MODE)

I

I

I

I

I

I
I

- : Toff : - I

:
I

l-PWM PERIOD-:

CIIncIIISIDn
This Application Brief explained how PSD5XX PPLD macrocells could be used in
combination with timers to generate 4 PWM timers. Relevant PSDabel file,
Configuration File are enclosed.

~--------------------r"~J!.----------------------3-70

""""AI

PSD5XX - Application Mots 028

Appendix 6.
Realizing

4PWM

This is the .abl file required to do the 4-PWM timers simulation
module gpld_pwm " 9-2-93

Timers on the

title '4 pwm channels ';

PSD5XX

"Input signals

(Cont.)

cntouCen pin; "Enable counter outputs to drive out.
loadws pin; " Load and enable generator.
d4,d3,d2,d1,dO pin; "Number of wait-states to load.
clkin, reset pin; "Default these signals are not needed to be defined
"Addr. lines, using reserved names.
a15,a14,a13,a12,a11,a1O,a9,a8,a 1,aO pin;
timerO_in,timer1_in,timer2_in,timer3jn pin;
" Internal PSD5XX PLD output signals.
csiop node;
mc2tmrO, mc2tmr1, mc2tmr2, mc2tmr3 node;

x = .x. ;
Address

" Don't care

=[a15,a14,a13,a12,a11,a1 O,a9,a8,X,X,X,X,X,X,a1,aO);

"Output signals
wstc pin;" Wait-State Terminal Count.
PWM_CYCLE pin istype 'reg';
gpld_cnt3,gpld_cnt2,gpld3nt1,gpld_cntO node istype 'reg'; " This counter outputs are
embedded.
equations
csiop = (Address >= I\hCOOO) & (Address <= I\hCOFF) ; " 256 block
@IF (O){
Reset is available
there through the enable gated reset configuration bit.

}
[PWM_CYCLE).oe

=cntouCen;

[PWM_CYCLE,gpld_cnt3,gpld_cnt2,gpld_cnt1,gpld_cntO).re = reset;
wstc = IPWM_CYCLE.fb & Igpld_cnt3.fb & Igpld_cnt2.fb & Igpld3nt1.fb & Igpld_cntO.fb;

iF• • . , .

-----------------------------------~~~--------------------------------3----71

PSD5XX - Application Note 028

Appendix 6.
Realizing

4PWM

"my stuff to generate PWM_CYCLE using GPLD

[gpld_cntO].clk := clkin;

TimelS on the

PSD5XX
(Cont.)

[gpld_cnt1].clk:= gpld3ntO.fb;

[gpld_cnt2].clk := gpld3nt1.fb;
gpld_cnt2 := Igpld_cnt2.fb;
[gpld_cnt3].clk := gpld3nt2.fb;

[PWM_CYCLE].clk := gpld_cnt3.fb;
PWM_CYCLE := IPWM_CYCLE.fb;
"Pin counterfTimer control inputs.
mc2tmrO:=
mc2tmr1 :=
mc2tmr2 :=
mc2tmr3:=

PWM_CYCLE.fb;
PWM_CYCLE.fb;
PWM_CYCLE.fb;
PWM_CYCLE.fb;

END

-3--n------------------------------~~~--------------------------------

--_ ....
=====~

Programmable Peripheral

~

-----........
Ir

. . . . . . . . ~==

Application Note 029

~~

Interfacing PSD4XX/5XX To Microcontrollers
By Rarl Kumar

Abstract

PSD4XX/5XX
Architecture

This application note is intended to
give the reader a general guideline on how
to interiace PSD4XXl5XX Field
Programmable Microcontroller Peripherals
to specific microcontrollers. Relevant
PSDabel files, bus simulation results and
the PSD bus configurations of the interiace
examples are included in this application
note.

The PSD4XXl5XX series provides the
user with an innovative architecture for
embedded applications. A PSD5XX device
has the following features:

o
o
o
o
o

o
o
o
o
o

The microcontrollers covered in this
application note are:

o
o
o
o
o

o

o

Forty individually programmable I/O
pins that are divided into 5 ports.
Four 16-bit CounterlTimers that periorm
pulse, waveform, time capture, event
counting and watchdog functions.
Eight input priority encoded Interrupt
Controller. Four Interrupts are
generated internally by CounterlTimers
and the other four can be user defined
through the ZPLD.

80C196
68302

o
o
o
o

Z8/Z80
80C166
ST9D26
NEURONd!i 3150""

68332

At the core of the PSD4XXl5XX are 3
dedicated ZPLDs:

Programmable bus interiace, "no glue"
logic interiace to microcontrollers.
Three ZPLDs (Zero Power PLDs) with a
total of 61 inputs, 140 product terms
outputs, 30 macrocells and 24 I/O pins.

BOC31
68HC11

o

DPLD: The Decoding ZPLD.
Its main function is to periorm address
decoding for the internal I/O ports,
EPROM, SRAM and periheral mode of
Port A.
GPLD: The General Purpose ZPLD.
The user can implement state machines
and other logic functions in the GPLD.
It can also gene rare chip selects for
external memories and peripheral
devices.
PPLD: The Peripheral ZPLD.
It provides additional control for the
operation of the CounterlTimer Units
and the Interrupt Controller. The PPLD
is available only in the PSD5XX series.

4-bit Page Register.
Up to 1 Mbit Reprogrammable EPROM,
consists of four 256 Kbit blocks.
16 Kbit of SRAM with battery backup
mode.
Power management unit with automatic
power down and sleep modes.
Security mode for code protection.

Figure 1 is a top level diagram of
PSD4XXl5XX.

3-73

~I

~

_I

RD, WR

P:~
INTRF

f:11 I

SELECT I

_

SRAM

e__l
_I

ADIO
PORT

E
liil..

PORT
C

1111111

25

II

-

PAD - PA7

PORT A MACROCEllS

CLKlN

PORT B MACROCEllS
...... II!ICI""II!IClII!I
PORT E MACROCELLS

I PBO - PB7

_g_g~_=_

PORT
B
__

1CI_I:IIClE;lClE3_

PDO - PD7

RA I

I

lj-. I
PROG.
PORT

MA\;Hu\;I:LL I'I:I:I.JISA\;I\ UH I'UHI INI'UJ

PROG.
PORT
PORT

~

CUON

•

II I • ~] ._-,.. _, fft
--

[" VVVVVVVV .....

'I

.£.~

.

H-+-pFOUR16-BITW~
__ , __ *"_ '- '"

MACROCELLS
____-

II..!WI ~ I~ IIJKI.; :jtj
•

WATCH DOG OUTPU1
INTERRUPT OUTPUT

I

7.

TI::.......

II

PORT
E

roo-GLOBAL
CONFIG.
&
SECURITY

I .w;;;,;;;; ,. L

'"

"-

'Iit
!I

PORT
A

ItO
DECODER

~

iii

!

'I.

24 MACROCELLS
PORT
PROG.

~

~

~ i=
:.c f
i:; Ir
PROG.
PORT

ADO-AD15I

~

! I

ADDRESS/DATA/CONTROL BUS

CONTROL

I~

PEO - PE7

R
CI

I'SD4XX/5XX - AppllcatlDn NDte 029

The Sus
Interface
Of The

PSD4XX/5XX

The PSD4XXl5XX have a user configurable bus interface. This interface can be configured
to allow the PSD4XX/5XX to interface directly to most microcontrollers with "no glue" logic.
There are only five bus control pins on the PSD4XXl5XX. Eac!:!"pin has multi~ functions
as shown in Table 1. For example, the "RD" pin can act as a "RD", or "E", or DS, or LDS,
depending on the microcontroller bus interface. Please note the "RD" and "WR" pins are
dedicated bus pins, but PEO and PE1 are two general purpose I/O pins on port E. If the bus
interface does not require these two pins, they can be configured to perform any of the
other Port E functions.
The selection of these pin functions is implemented in the PSDconfiguration menu inside
the PSDsoft.

Table 1. Alternate Pin Functions
Pin
Name

Pin
Function
1

Pin
Function
2

Pin
Function
3

Pin
Function
4
LDS

RD

RD

E

DS

WR

WR

RIW

WRL

PEO

BHE

PSEN

WRH

PE1

ALE

ADO

AO

Pin
Function
5

UDS

SIZO

BLE

The multiple functions of the PSD bus pins allow the PSD4XXl5XX to support a large
number of microcontrollers. Table 2 shows some of these microcontroller families, the bus
type and control signals associated with the microcontrollers.

Table 2. Typical Microcontrol/er Bus Types
Multiplexed
Mux
Mux
Non-Mux
Mux

Data Bus
Width

Bus Control Signals

Mlcrocontrol/ers

WR, RD, PSEN

80C31 Family

8/16

RIW, E, BHE

68HC11 Family

8/16

WR, RD, BHE

80196/80186 Family
80C166 Family

8

Mux

16

WRL, RD, WRH

80196SP

Mux

8

RIW,DS

ST9 Family

Non-Mux

16

RIW, LDS, UDS

68302

Non-Mux

8/16

RIW, DS, SIZO

683XX Family

Non-Mux

8/16

RIW, DS, BHE, BLE

68330

----------------------------------~~~~-------------------------------3--~--5

PBII4XXISXX - Application Not. 029

PSD4XX/5XX
Interface

PSD4XX/5XX Interface
T" a MultIplexed Bus

Toa
Multiplexed
Bus

Figure 2 shows a typical connection to a microcontroller with a multiplexed bus. The ADIO
port of the PSD4XXl5XX is connected directly to the microcontroller address/data bus. For
an 8-bit bus, the low byte of the ADIO port is connected to ADO - AD7 and the high byte to
A8 - A 15 of the microcontroller. For 16-bit bus, the ADIO port connects to ADO-AD15.
The address lines are latched internally by the ALE Signal. In a read bus cycle, data is
driven out through the ADIO Port transceivers after the specified access time. The ADIO
Port is in tristate mode if none of the internal PSD resources are selected.

PSD4XX/5XX Interface
T" a N"n-Multlplexed Bus
Figure 3 shows a PSD4XXl5XX interfacing to a microcontroller with a non-mUltiplexed
address/data bus. The address bus is connected to the ADIO Port, and the data bus is
connected to Port C and/or Port D, depending on the bus width. If the microcontroller has
an address strobe signal, the user has an option to latch or not to latch the address by the
ALE/AS signal internally in the PSD.

Optl"nal Features
The PSD4XXl5XX provides two optional features to add flexibility to the Bus Interface:

1. AddfflSS In
Port A can be configured as high order address (A16-A23) inputs to the ZPLD for DPLD
or other decoding. Any other signals which also are included in the DPLD chip select
equations must come from Port A.
Port C & D can be configured as address input ports for the ZPLD. These inputs should
not be used for EPROM decoding.

2. AddfflSS Out
For multiplexed bus only. Latched address lines AO-A15 are available on Port A, B, C or
D. The latched address can be used as address to external memory or I/O devices.

7~7n~-------------------------~Jr~-----------------------------

PSD4XX/5XX - Application Nottl 029

Bus

Figure 2. Bus Interface - Multiplexed Bus

Interface
Of The
PSD4XX/5XX
(Cont.)

Ii

::J
<

0;

..

'Q z

t:- o~
I

<

::J
<
z

.= ~
e..

Do.

I

e..

<

U

Q

Ii:0

lII:

<

0

ID
lII:

Do.

Do.

0

0

Do.

Do.

III:

W

01-

III:

i5~
= AhOCOOO) & (Address <= AhOCOFF) ; "Chip Select 256 byte block
rsO = (Address <= AhOB7FF) & (Address >= AhOBOOO); "SRAM 2k block
esO = (Address <= Ah07FFF) & (page == 0); "EPROM 32k block only at page 0
es1 = (Address <= Ah07FFF) & (page == 1); "EPROM 32k block only at page 1
es2 = (Address <= Ah4FFFF) & (Address >= Ah4BOOO); "EPROM 32k block, always visible

END dpld

-3--8-4-------------------------------~~~~---------------------------------

PS04XX/5XX - AppllcatlDn NDts 029

Bus
Interface
Examples

This section demonstrates the interface between the PSD4XXl5XX and some
microcontrollers. The following documents are included in each of the microcontroller
interface examples:

o

o
o

o

The Bus Configuration (PSDconfiguration) screens captured from the
PSDsoft design tool.
The ABEL file which shows only the declaration and DPLD equations of the
targeted microcontroller.
The logic interface schematic showing the connection between the PSD4XXl5XX
and the microcontroller.
The bus interface simulation screen captured from the SILOSIII Simulator.
The Simulator provides a full function, chip level simulation of the PSD4XXl5XX for
design verification. The stimulus input file to the Simulator is written in Veri log .
The results of the simulation is shown in the SDA ( Silos Data Analyzer) window where
user defined signals or PSD internal nodes can be traced/displayed.

In the following examples, only the bus interface function of the PSD4XX/5XX is simulated.
This includes read bus cycles to the PSD EPROM and SRAM, and write cycles to the
SRAM. The EPROM blocks have pre-filled data per Table 4 as the default configuration.
The data should give you an indication if the PSD is enabling the right block and byte of the
EPROM.
Although the SDA can display many PSD signals, only bus related signals are shown in the
examples in this Application Note. Please note the signal names displayed in SDA do not
indicate the signal's polarity. As a rule, internal PSD signals all have active high polarity.
The bus control signals have the same polarity as defined by the
individual microcontrolier. The displayed signals include:

o
o
o

o

Control ~nals _
__
Such as RD, WR, DS, ALE, PSEN, etc.
Address/Data Bus
ADIOH and ADIOL (high and low byte of microcontroller address/data bus)
Data Bus
DATAH and DATAL (high and low byte of data bus, for non-mux bus only)
Chip Selects
Chip select signals to EPROM (esO - es3) and SRAM (rsO).

Table 4.
EPROM Block

Odd Byte

Even Byte

BlockO (ESO)

01h

23h

Block1 (ES1)

45h

67h

Block2 (ES2)

89h

abh

Block3 (ES3)

cdh

efh

----------------------------------~~~~-------------------------------3---85

PlD4XXl5XX - Appllatlon 1I0t, 029

Interfacing
To TheBOC31
Family 01
Mlcrocontrollers

The80C31 Bus
80C31 is an 8-bit microcontroller with multiplexed address/data bus. It has the following bus
signals:
Q Address/Data Bus: AD7 - ADO

CJ Address Bus:

A15-A8

Q Address Strobe:

ALE

Q CoAtI:oI Signals:

RD, WR, PSEN

The PSEN signal is used to fetch code and RD is used to read data. This allows the 80C31
to address up to 64KB of data memory and 64KB of program memory.

7Wo Modes of Memory AccllSS
The PSD4XX15XX provides two modes of memory access: the Separated Space Mode
and the Combined Space Mode (see Tables 5 and 5a). In Separated Mode, the PSEN
signal can access the EPROM only and the RD signal can access the SRAM o~. In
Combined Space Mode, the EPROM can be accessed both by the PSEN and RD signal.
The Combined Mode is for application where blocks of data or look up tables are required
to reside in the EPROM.
The PSD4XXl5XX also provide an option for program code 10 be stored and executed from
the SRAM. This option is enabled if the SRCODE bit in the VM Register is set to "1" during
run time.

Table 5. Separated Space Mode
EPROM AccllSS

SRAM AccllSS

RD Signal

No

Yes

PSEN Signal

Yes

Yes only if SRCODE = 1

EPROM AccllSS

SRAM AccllSS

Table Sa. Combined Space Mode
RD Signal

Yes

Yes

PSEN Signal

Yes

Yes only if SRCODE = 1

,1I.l..g

-3~-----------------------------~.w1-----------------------------

PSD4XX/5XX - Appllcatl.n N.Ie D2I

Interfacing
To The B0C31
Family Of
Microcontrollers
(C.nt.}

The 80C31 and PSD4XX/5XX Interface Schematic
Figure 9 shows the 80C31 and PSD4XXl5XX interface schematic. The address/data bus
and the bus control signals such as ALE, RD, WR, PSEN etc., are directly connected to the
corresponding pins of PSD4XXl5XX without any additional glue logic. Reset for the 80C31
is generated from the RESET input to the PSD4XXl5XX and outputs on pin PE2 in this
example. If clock input is not required, the ClKIN pin should always be grounded.

Reset Cllcult ReCDmmendatlDns
The following three reset circuits are recommended for use with 80C31 and PSD4XXl5XX
based designs:
1. Input RESET signal into the PS4XX15XX RESET pin. Based on the polarity of the
RESET INPUT signal of the microcontroller interfaced to the PSD, generate RSLOUT
through the GPlD and connect it to the microcontroller's RESET INPUT pin
(as illustrated in this application note.)
2.

Use a Reset Chip such as Dallas Semiconductor's DS1232, or Maxim's Max 699.
In case of Maxim's Max 699, the Small Outline (SO) package should be used where
the RESET output without inversion is also available. The inverted RESET signal goes
to the PSD RESET input pin and the non-inverted RESET signal is connectd to the
RESET input of 80C31.

3.

Use two separate RC reset circuits: one which generates a high reset pulse to the
80C31 and the other one generates a low reset pulse to the PSD4XX15XX.
The RC constant of the PSD4XXl5XX reset circuit should be less than that of the
80C31 such that the PSD4XXl5XX reset signal has a shorter pulse and eliminates
any race condition.

----------------------------------;rIL"

.,jf-------------------------------3-~--7

~
gg

:"1'1
cij"

§;

CIi

!D

X2~
Y

311EA/VP

::91

',I~il~
Uillllt
Ilblllll
I.II'~

~

~

Pl.0
P1.1
Pl.2
Pl.3
Pl.4
P1. 5
Pl.6
P1. 7

2
3
4
5
6
7
8

ADO

PO.O/ADO
PO.ll ADl
38
PO.21 AD2 I 37
PO.31 AD3 I 36
PO.41 AD4 1 35
PO.51 AD5 I 34
PO.61 AD6 : 33
PO.71 AD7 : 32

AUl

II

AD2
AD3
AD4
AD5
AD6
AD7

7
6
5
4
3
2

.: 21
.22
1 23
124
1 25
1 26
: 27
1 28

A8
A9
Al0
All
A12
A13
A14
A15

68
67
66
65
64
63
62
61

RESET

INTO
INn
TO
Tl

13
14
15

PSD4XXl5XX

Ul

Xl

P2.01 A8
P2.1/A9
P2.2/Al0
P2.3/All
P2.41 A12
P2.51 A13
P2.6/A14
P2.71 A15

RD
WR
PSEN
AlE/P
TXD
RXD

ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

RD
WR
RESET
CSI

ClKIN

ClKlN

PEO/PSEN
PElIAlE
PE2
PE3
PE4
PE5
PE6
PE7

RST_OUT
VCC

28

I VSTDBY

i~

1& :a..I
tl I::::

::-

80C31

~

2

U2
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

2

~
~

Sir

~

PD~

POl
PD2
PD3
PD4
PD5
PD6
PD7

~

l =
~ iJ:

::

::!:

if

!§

PSD4XX/5XX - Application Note D29

Interfacing
Specify The BoC31 Bus Interface
In PSDcDnfiguratiDn
To The BOC31
As shown in the following windows which are captured from PSDconfiguration, the 80C31
Family Of
Microcontrollers bus interface can be specified by selecting:
(Clint.)

Q Data Bus Width:

X8

Q AddressJData Mode: MX
Q Polarity of ALE:

High

Q RDIWR Setting:

WR, RD, PSEN

The PSDconfiguration also asks the question "Use the read signal to access the EPROM".
A click on "Yes" means you are selecting the Combined Space Mode and that both the
PSEN or RD signal can access the EPROM. A "no" will select the Separated Space Mode
and EPROM can be accessed by PSEN only.

- _IE

----------------------------------~~~---------------------------------3-89

PSD4XX/5XX - Application Note 029

Interfacing
To The80C31
FamilyOt
Microcontrol/ers
(Cont.)

Define The DPLD/Decoding Function In The ABEL file
The following is an example of defining the decoding function for the BOC31 based
application. Please note the reset input to the BOC31 , rs,-out, is also included in the file.
This file is applicable to both the Separated or Combined Space mode. The memory map is
shown in Table 6.
module psen
title 'Design example of BOC31 DPLD source file';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,aB,a1 ,aO pin;
"Output signals
csiop, rsO, esO, es1, es2 node;
reset pin;
rs,-out pin 36;

"DPLD output chip selects
"reset is declared here, used in rs'-out generation

"DEFINITIONS

x

= .x.; "Don't care
Address = [a15,a14,a13,a12,a11 ,a1 0,a9,aB,X,X,X,X,X,X,a1 ,aO];
equations
"DPLD EQUATIONS
csiop
rsO

(Address >= I\hCOOO) & (Address <= I\hCOFF); "CSIOP 256bytes block
(Address <= I\hOOOO) & (Address >= I\h03FF); "SRAM 2KB block

esO
es1
es2
es3

(Address
(Address
(Address
(Address

>= I\hOOOO) & (Address <= I\h3FFF);
>= I\h4000) & (Address <= I\h7FFF);
>= I\hBOOO) & (Address <= I\hBFFF);
>= I\hCOOO) & (Address <= I\hFFFF);

"1st EPROM block cs
"2nd EPROM block cs
"3rd EPROM block cs
"4th EPROM block cs

"GPLD EQUATIONS
rs,-out

= !reset;

"generate a high active reset to BOC31

END

Table 6. System Memory Map
Device

Memory Space

EPROM, Block 0

0000- 3FFF

EPROM, Block 1

4000-7FFF

EPROM, Block 2

BOOO- BFFF

SRAM

0000-03FF

1/0 Devices

COOO-CFFF

Memory Page

-3-.9-0-------------------------------~~~---------------------------------

PSD4XXj5XX - Application Note 029

Overlapping EPROM Space In Combined Mode
Interfacing
If your application requires the data and program to be resided in the EPROM (Combined
To The BOC31
Space Mode}and share the same address space, you need to modify the chip select
Famil,Ot
equations. For example, if EPROM blocks 0-1 are used as code area and blocks 2-3 are
Microcontrollers used as data area, and that code and data space share the same address. In this case,
(Cont.)

the RD signal is used to separate the program and data space. The program space is
enabled by an active PSEN, while the data space is enabled by an active RD. The RD
signal now is considered as an address input and thus the access time of the EPROM
starts from when RD is valid, instead of when address is valid. The following is the chip
select equations of the EPROM blocks.
esO = (Address >= J\hOOOO) & (Address <= J\h3FFF) & RD; "program area
es1 = (Address >= J\h4000) & (Address <= J\h7FFF) & RD ; " program area
es2 = (Address >= J\hOOOO) & (Address <= J\h3FFF) & !RD; "data area
es3 = (Address >= J\h4000) & (Address <= J\h7FFF) & !RD; "data area

Simulation of BOC31 Bus Cycles
With The PSD4XX/5XX
Figure 10 shows the simulation of three 80C31 bus cycles. The first cycle is a code fetch
from EPROM block 0 where code "23" is driven on to the ADIOL bus by the PSD.
The next two cycles are SRAM write (data = 55h) and read cycles to location 0300h.

,sLout

RO

elkin

DO

ale

DO

adioh

FF

adiol

FF

esO

D1

'sO

01

psen

01

w,

B0C31 With PSD4XX/5XX
and External Memory
In applications where large amount of SRAM is required, the PSD4XXl5XX is able to
support an additional external SRAM. Figure 11 illustrates how an external SRAM (6164)
can be interfaced to the PSD4XXl5XX and the 80C31 without additional hardware. Port C
(or any other port) is configured to provide latched output addresses AO - A7, and the
SRAM chip select is generated from the GPLD.

-----------------------------------~~~----------------------------------===
3-91

't>

~I

::"II
cQ'
ADO-AD7

01--

i!

:"'

~
1

CIi

A8-A12

8g

PSD4XX/5XX
X2

ADO
ADl
AD2
AD3
AD4
ADS
AD6
AD7

PO.OI ADO
PO.ll ADl
PO.21 AD2
PO.31 AD3
PO.41 AD4
PO.51 ADS
PMI AD6
PO.71 AD7
P:!.OI A8
P2.11 A9
P2.21 Al0
P2.3/All
P2.41 A12
P2.SI A13
P2.61 A14
P2.71 A15

tll·'' 11
fl'IIIII

A8
A9
Al0
All
A12
A13
A14
A1S

21
22
23
24
25
26
27
28

'1"11

111,11111

9

ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
AD8/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

U2
PCO
PCl
PC2
PC3
PC4
PCS
PC6
PC7

PD~

POl
PD2
PD3
PD4
PD5
PD6
PD7

"1111111

DO
01
02
03
04
05
06
07

11
12
13
15
16
17
18
19

AD0--1
AD1-1
AD2
AD3
AD4
ADS
AD6
ADI..,

'!.

~

;::

.:"'

2

~
~

c:a.
=
~
if

iii
!!.
~
~
iii::

S'
if

~

RSLOUT

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

::-

CE
WR

lID

~

fl

i
PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7

~

!';

-i

Yl

ij'

-=
~

CD

~

CO

PSD4XX/5XX - ApplicatlDn NDt. 029

Interfacing
To The 6BHC11
Family Of
Microcontrollers

The 68HC11 family of microcontrollers have two types of bus interfaces. The
standard HC11 has a multiplexed bus, while the 68HC11 K4 has a non multiplexed bus. The
example here covers both bus configurations.

The 68HC11 Bus
The standard 68HC11 has a multiplexed bus where the lower address lines multiplex with
an 8-bits data bus. It has the following bus signals:

o
o
o
o

Address/Data Bus: AD7 - ADO
Address Bus:

A15 - A8

Address Strobe:

AS

Control Signals:

E, RIW

68HC11 Interface to PSD4XX/5XX
The 68HC11 can interface directly to the PSD4XXl5XX without any additional glue logic.
As shown in Figure 12, the E clock is connected to the "RD" pin, which is configured to act
as the E clock input. The RIW signal is connected to the "WR" pin, which is configured to
act as the RIW input.
The PSD4XX15XX generates internal "write" and "read" signals based on the E clock and
the RIW inputs. If E clock is high and RIW is hgih, then PSD4XXl5XX sees it as a read bus
cycle and drives data on to the data bus through the ADIO Port if any of its internal devices
are selected.

--------------------------------~~ar-------------------------------_f;if=
3.93

~

riq

PSD4XX1SXX

~
7
6

IUi"1Q

Ib

II~.

I.III~

ADO
ADI

Ul

RESET
IRQ
XIRQ

llll!
lIIilllll!

ill

Cil

i~

.....

I!\)

U2

2
I

C3

VCC

:::!!

'I

PAO
PAl
PA2
PEO
PEl
PE2
PE3
VRH
VRL

9
8
7
6

Ao2
ADa

PA3
PA4
PA5
PA6
PA7

5
4
3

Ao4
16
15

PBO :
W
PBl r 13
PB2 I 12
PB3 r 11
10
PB4
9
PB5
PB6 I
PB7

r
r

ADS
ADO
AD7

2

AS

~

M
Al0

67
66
65

All
A12
A13
A14
A15

64
63

62
61

PCO
PCl
pe2
PC3
PC4
PC5
PC6
PC7

E

ADO/AO
ADI/Al
AD2/A2
ADa/A3
AD4/A4
ADS/A5

PCO
PCl
PC2
PC3
PC4

ADO/A6
AD7/A7

PC7

ADS/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

41 , E

I..... t:::::
".....
,@l =t
~
:::t

PC5
PC6

~

2

i~

PDO
PDl
PD2
PD3
PD4
PD5
PDO
PD7

is'
iit

::i

RIW

RESET

PDO
PDl
PD2
PDa
PD4
PD5

PEO
PEl/ALE
PE2
PE3
PE4
PE5
PE6
PE7
VSTDBY

PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

=
ClKIN
MODA
MODB
XlRQ
IRQ

VCC

..
2
CCi

PSD4XX/5XX - Application Note 029

Interfacing
To The 6BHe11
FamilyOt
Microcontrollers
(Cont.)

Specify the 6SHe11 Multiplexed Bus Interface In PSDconflguratlon
As shown in the following windows which are captured from PSDconfiguration, the 68HC11
bus interface can be specified by selecting:

o
o
o
o

Data Bus Width:

X8

Address/Data Mode: MX
Polarity of ALE:

High

RDIWR Setting:

RNI, E

_______________________________ FSSaFE _______________________________

r;':ill

3-95

PSIJ4XX/5XX - Applicatilln NIt. 029

Define The DPLDlDecoding Function In The ABEL File
Interfacing
The following is a an example of defining the decoding function for the 68HC11
To' The 68Hett
application. Table 7 shows the memory map implemented by the DPLD.
Family Of
Microcontrollers
(Clint.)

based

Table 7. System Memory Map

-

Device

Memory Space

EPROM, Block 1

4000-7FFF

EPROM, Block 2

8000- BFFF

EPROM, Block 3

COOO- FFFF

SRAM

1000 -13FF

1/0 Devices

OOOO-OOFF

Memory Page

module hc11
title 'DPLD chip select equations source file ';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
"Output signals
as,rd_wr,e pin 37,29,41; "Motorola related ale and read/write signals
"DPLD output chip selects
csiop, rsO, es1, es2, es3 node;
"DEFINITIONS

x

= .x. ;
" Don't care
Address
[a15,a14,a13,a12,a11 ,a10,a9,a8,X,X,X,X,X,X,a1 ,aO];

=

equations
"DPLD EQUATIONS
csiop = (Address >= AhOOOO) & (Address <= AhOOFF); "CSIOP 256bytes block
rsO
= (Address <= Ah1000) & (Address >= Ah13FF); "SRAM 2KB block
es1
es2
es3

= (Address >= Ah4000) & (Address <= Ah7FFF); "2nd EPROM block cs
= (Address >= Ah8000) & (Address <= AhBFFF); "3rd EPROM block cs
= (Address >= AhCOOO) & (Address <= AhFFFF); "4th EPROM block cs

"The first EPROM block is not used and it is not required to define esO

END

----------------------------------,~~~~--------------------------------3-96
-=-

PSD4XX/5XX - Application Nots IJ29

Interfacing
To The 6BHC11
Family Of
Micfocontfollers
(Cont.)

Simulation of 68HC11 Bus Cycles With the PSD4XX/5XX
Figure 13 shows the output of the 68HC11 bus cycle simulation. Data byte 55h is written to
location 1000h of the SRAM in a write bus cycle with the Am signal low. In the next
cycle, the RIW signal is high and the same data byte is being read back as shown in the
ADIOL bus.
'

68HC11 With PSD4XX/5XX and External Memory
In applications where a large amount of SRAM is required, the PSD4XXl5XX is able to
support an additional external SRAM. Figure 14 illustrates how an external SRAM (6164)
can be interfaced to the PSD4XXl5XX and the 68HC11 with multiplexed address/data bus
without additional hardware. Port C is configured to provide the latched output addresses
AO -A7 (A8 -A15 come directly from the 68HC11). The SRAM chip select and the
read/write signals are generated from the GPLD.

11'_111_.

------------------------------~~1---------------------------3-.9--7

f:>

:!!

=
1.

~-r T

ADO-AD7

I

I

PSD4XX15XX

.L

'I;

I t~
I

U2

U3

c::::JYl

C3

I

"

II

XT

39
41

RESET
IRQ

-+
....!..

...g...

R1

..:,~

30

I ~-!-o

C

-II

6SHC11 AS

~

1~lk

If

4

EX

9
8
7

ADO/AO
AD1/Al
AD2/A2

PCO
PCl

AD3
T5
AD4
rtAD5
IT
AD6
r,-.Ar1J

6
5
4
3

AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7

PC3
PC4
PC5

PAO
PAl
PA2
nmft

~~

I P9-

~

~

r-

XIRQ

vnn

+fJpF

ADO
ADI
AD2

Ul
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4

16

A8

68

,,__

15
14
13
12
11

A9
Al0
All
A12
A13

67
66
65

,--

,y,
,-,

I

33

AD2

~

::::M_

I

L

PD2
PD3
PD4
PD5

"*"

=

E
AS

L
RESET
[CLKlN

1

28

E

::::: 157
,- [jL
PD4 [55

1

ADW---

J!!!

C&.

n..

"L

PA4

38

34

-B.

~
....!!!....
32

E

26
~
=

RIW

I

PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

VSTDBY

~~
~

~

~

CLKlN

~
...1
,1
1

R4
4.7K

R5
4.7K

~f R7

R6
4.7K

A7

AO
AI
A2

Dl

6
5
4
3

A3
A4
A5
A6
A7

D4
D5
D6
D7

__

All ..A

4.7K

~

:..-;~ ~
--

1/
I All
I
vcc 1/
I A12:
T I ---2l!..I CSI

t I I :::1!J

I

CS2
27 WI'

I I I I j16~~4
I I I II

26

11
12
13
15

ADO
ADI
AD2
AD3

16
17
18
19

AD4
AD5
AD6
AD7

....
....
"

I

=

,Ii;

;ioiii

I

~
-..

I iii:

: ...
_

_

1

Ii

I~

I~
at

i

-Po-

~

r:-

"ii""
"if'"
"ii""

rF
~

J
J

JJ

::::

&I

;t

:I

~ I

if

..........
50

t-T.~

4A

DO

::_:_

__

~
PA5~

:~/ALE

-MODe
XIRQ
IRQ

10
9
8
7

...All.

~b:11111

PE2
PE3
PE4
PE5
PE6
PE7

RIW

f58

:~ ~

E

MODA

L

~;;:

~

-F
~

~

25
MODA
MODB ....:..:..,
27

A4

AD1:;;'::
ADI2;;':;
AD13;;.;;
AD14/A14

42

T
rir
r--"'-

13
12
11
10

AI
A2

__

~:a

-

~
PD1~

PDO

PC6

PC7

..M.

AD,u,~.u

63

DDC

PC2

17
16
15
14

--, _ IT9

64

i

~

_

iii'

I

PSD4XX/5XX - AppllcatlDn NDt. 029

Define The DPLD/Decodlng Function In The ABEL File For External SRAM
Interfacing
The following is a an example of defining the decoding function for the 68HC11 based
To The 6BHe11
application with external SRAM. The latched address AO - A7 are assigned to Port C. The
FamilyOt
and "/rd" Signals, which can be used for other devices besides the SRAM, are also
Microcontrollers "/wr"
generated. Table 8 shows the memory map.
(Cont.)

Table B. System Memory Map
Dellice

Memory Space

EPROM, Block 1

4000-7FFF

EPROM, Block 2

8000-BFFF

EPROM, Block 3

COOO- FFFF

SRAM (PSD)

1000 -13FF

SRAM (External)

2000-3FFF

1/0 Devices

0000- OOFF

..

Memory Page

--------------------------------~':ifl~~
~.-------------------------------3·99

PSD4XX/5XX - Application Note 029

Define The DPLD/Decoding Function In The ABEL File For External SRAM (Cont.)
Interfacing
To The 6BHeff
module hc11
Family Of
title 'Design example of 6Bhc11 DPLD source file to interface with external SRAM';
Microcontrollers
(Cont.)

"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a1 0,a9,aB,a1 ,aO pin;
"Output signals
as,rd_wr,e pin 37,29,41; "Motorola related ale and read/write signals
"DPLD output chip selects
cSiop, rsO, esO, es1, es2 node;
"assign pins (port c) for latched address out
addrO, addr1 ,addr2,addr3,addr4,addr6, addr7 pin 17,16,15,14,13,12,11,10;
"External SRAM chip select and read/write signal generation
swr, srd, sram_ce pin;
"DEFINITIONS

x = .x. ;
Address

" Don't care

=[a15,a14,a13,a12,a11 ,a1 0,a9,aB,X,X,X,X,X,X,a1 ,aO];

equations
"DPLD EQUATIONS
csiop = (Address >= I\hOOOO) & (Address <= I\hOOFF); "CSIOP 256bytes block
rsO
= (Address <= I\h1000) & (Address >= I\h13FF); "SRAM 2KB block
es1
es2
es3

= (Address >= I\h4000) & (Address <= I\h7FFF); "2nd EPROM block cs
= (Address >= I\hBOOO) & (Address <= I\hBFFF); "3rd EPROM block cs
= (Address >= I\hCOOO) & (Address <= I\hFFFF); "4th EPROM block cs

"The first EPROM block is not used and it is not required to define esO

"Equations to select/read/write the 6112B, external SRAM through PSD
swr
!(e & !rd_wr); "write signal
srd
!(e & rd_wr); "read signal
sram_ce = (Address >= I\h2000) & (Address <= I\h3FFF); "BK SRAM chip select

END

~3'~1~00~-----------------------------~~~---------------------------------

PSD4XX/5XX - Applicatilln Nllte 029

Interfacing
To The 6BHC11
FamilyD'
Mlcrocontrollers
(Clint.)

The 68HC11K4 Bus
Motorola's 68HC11 K4 has a non-multiplexed 16-bit address and an 8-bit data bus.
The control signals used for accessing 1/0 devices·or memory are the E clock and the
RlWsignal.

The 68HC11K4 Interface tD PSD4XX/5XX:
The 68HC11 K4 can interface directly to the PSD4XXl5XX without any additional
glue logic. As shown in Figure 15, the E clock is connected to the "RD" pin, which is
configured to act as the E clock input. The RIW signal is connected to the "WR" pin,
which is configured to act as the RIW input.
The PSD4XXl5XX generates internal "write" and "read" signals based on the E
clock and the RIW inputs. If E clock is high and RIW is high, then PSD4XXl5XX
sees it as a read bus cycle and drive data onto the data bus through the Port C
if any of its internal devices is selected.

-S-iJIII..li#
----------------------------------~~jF------------------------------3--,-O--,

~

:"II

ciS'

~

~

«II

....

~

::

DO-I)J

68HC11K4
XT
EX

61
30
76
11
10
9
49
48
47

t'1""1

IQIII1

II""
IUIIIIII
I.II'~

46
VCC

45

44
43
42
51
50

IRQ
XlRQ
MODB
PAO
PAl
PA2
PEO
PEl
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL

75
RESET

PFO
PFl
PF2
PF3
PF4
PF5
PF6
PF7
PBO
PBl
PB2
PB3

PB4
PBS
PB6
PB7
PCO
PCl
PC2
Pcl
PC4
PC5
PC6
PC7
PG7

E

60

9
8
7
6
5

53

AD
Al
A2
A3
A4
AS
A6
7

20
19
18
17
16
15
14
13

A8
A9
Al0
All
A12
A13
A14
A15

68

59
58
57
56
55

54

62
63

4
3
2

67

66
65
64
63
62
61

41

E

64
65
66

29

67
68
69

40

33

42

39

72

38
37
36

34
33

RESET

32
31
30

VCC
MODB
XIRQ
IRQ

28
R6
4.7K

-=

ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
AD5/A5
AD6/A6
AD7/A7
AD8/A8
AD8/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

~

=
;,:

PCO
PCl
PC2
PC3
PC4
PC5
PC6

Q"

2

~

~

PC7

PDO
PDl
PD2
PD3
PD4
PD5
PD6
PD7

~

60
59
58
57
56
55

54
53

E
R/W
RESET
CSI
ClKIN
PEO
PEl/ ALE
PE2
PE3
PE4
PES
PE6
PE7
VSTDBY

i~
I

~

'!..
iii
........ i::t

PSD4XXl5XX

Ul

~

2

PAD
PAl
PA2
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

27

26
25
24
23

22
21

20
50
49

48
47
46
45

44
43

ii'

iii'

it
COl
CD

!!I
if
;-

~
co

PSD4XX/5XX - Application Nots 029

Interfacing
To The 68HC11
Family 01
Micfocontfollers
(Cont.)

Specify The 68HC11K4 Non-Multiplexed Bus Interface In PSDconflguration
As shown in the following windows which are captured from PSDconfiguration, the 68HC11
bus interface can be specified by selecting:

o
o
o

Data Bus Width:

X8

Address/Data Mode: NM
RDIWR Setting:

RIW, E

--------------------------------~~~-----------------------------3--1-D-3

I'SIJ4XX/5XX - Application Not, 029

Define The DPLD/Decoding Function In The ABEL File
Interfacing
The following is a an example of defining the decoding function for the 6BHC11 K4 based
To The 6BNe11
application. Table 9 shows the memory map implemented by the DPLD.
FamilyOt
MicfocontfollelS Table 9. System Memory Map
(Cont.)

Device

Memory Space

EPROM, Block 1

4000-7FFF

EPROM, Block 2

BOOO-BFFF

EPROM, Block S

COOO-FFFF

SRAM

1000-1SFF

1/0 Devices

OOOO-OOFF

Memory Page

module hc11k4
title 'Design example of 6BhC11K4 DPLD source file';
"Input signals
"Address lines, using reserved names.
a 15,a 14,a 1S,a12,a11,a1 O,a9,aB,a 1,aO pin;
"Output signals
rd_wr,e pin 29,41; "Motorola related ale and readlwrite signals
csiop, rsO, esO, es1, es2, esS node;
"DPLD output chip selects
"DEFINITIONS

x = .x. ;

" Don't care
Address =
[a15,a14,a1S,a12,a11 ,a10,a9,aB,X,X,X,X,X,X,a1 ,aO];

equations
"DPLD EQUATIONS
csiop = (Address >= I\hOOOO) & (Address <= "hOOFF); "CSIOP 256bytes block
rsO
(Address >= I\h1 000) & (Address <= I\h1SFF); "SRAM 2k block
es1
es2
esS

(Address >= I\h4000) & (Address <= I\h7FFF); "2nd EPROM block cs
(Address >= I\hBOOO) & (Address <= I\hBFFF); "Srd EPROM block cs
(Address >= I\hCOOO) & (Address <= I\hFFFF); "4th EPROM block cs

END

~3.~1N~-------------------------~~Ar----------------------------

PSD4XX/5XX - Application Nottl 029

Interfacing
To The 68HC11
Family Of
Miclocontlollers
(Cont.)

Simulation Of 68HC11K4 Bus Cycles With The PSD4XX/5XX
Figure 16 shows the output of the 68HC11 K4 bus cycle simulation. Data byte 55h is written
to loaction 1000h of the SRAM in a write bus cycle with the RIW signal low. In the next
cycle, the RIW signal is high and the same data byte is being read back as shown in the
DATAL bus.

Figure 16.

Interfacing
To The 80C196
Family Of
Miclocontlollers

The 80C196 Bus
The 80C196 family of microcontroliers has a 16-bit multiplexed address/data bus.
The processor has a dynamic data bus width. In a typical application, the EPROM has an
8-bit data bus while the SRAM has a 16-bit data bus. The PSD4XXl5XX is able to provide
a 16-bit data bus interface to both the SRAM and EPROM, thus increase system
performance and throughput.
The 80C196 bus control signals include the ALE, the RD, the WR and the SHE.
It also has a special mode, the Write Strobe Mode. In this mode, the WR and SHE signals
are replaced by WRL and WRH. The PSD4XXl5XX supports both interfaces.

The 80C196 and PSD4XX/5XX Interface Schematic
Figure 17 shows the 80C196 and PSD4XXl5XX interface schematic. The address/data
bus and the bus control signals such as ALE, RD, ER, SHE etc., are directly connected to
the corresponding pins of PSD4XXl5XX without any additional glue logic.

----------------------------------,~~~~---------------------------------====

3-105

'I~
Ci1

~
8OC196

PSD4XXI5XX

X1

X2
P3.01 ADO
P3.lIAD1
P3.2 I AD2
P3.3/AD3
P3.4 I AD4
P3.5/AD5
P3.8/ADI
P3.7 I AD7

vcc
NMI
READY
CDE
BUSWIDTH
RESET

=
7
4
11
10
8
9

~

IIIIIII\j

18
17
15
44
42
39
33
38

VCC

24
25
2&
27

I

13

~
I

I t

=
11

!

ACHO/PO.O
ACH1/PO.1
ACH2/PO.2
ACH3/PO.3
ACH4/PO.4
ACH5/PO.5
PCS6/PO.&
PCS7/PO.7

P4.0 I ADI
P4.1/ADI
P4.21 AD10
PUI AD11
P4.41 AD12
P4.51 AD13
P4.81 AD14
P4.71 AD15

P2.0/TXD
P2.lIRXD
P2 .2/EXINT
P2 .3/T2ClK
P2.4/T2RST
P2.5/PWM
P2.&/T2UP-DN
P2.7/T2CAP
HSI.O
HSI.1
HSI. 2/HSO 4
HSI.3/HSO:5
VREF

1

RD
WR
BHE
ALE
INST
ClKOUT
P1.0
P1.1
P1.2
PU
P1.4
P1.5
P1.8
P1.7
HSO.O
HSO.1
HSO.2
HSO.3

ADO
AD1

ADO/AO
AD1/A1
AD2/A2
AD3/A3
AD4/A4
AD5/A5
ADl/A8
AD7/A7

Ao2
AD3

ADi
ADS
ADI

Ao'i
52
51
50
48
48
47
48
45
1
40
41
62

88
87
&&

A12

84
63

i1ci
iii

&5

i1i
iii

62

A15

&1

liD

RESET

ClKlN

59
58
57
58
55
48

PEOIBHE
PE1/AlE
PE2
PE3
PE4
PES
PES
PE7

28
RST_OUT

ADI/AS
ADl/A9
AD10/A10
AD11/A11
AD121A12
AD13/A13
AD14/A14
AD15/A15

WR
BHE
ALE

63
&5

AS
A9

IC3
=

=

VSTDBY

U2

~

:;::

!

I

It I:
III
!II
I 1=
fJ iit

~

e
ii:

::~

PS04XX/5XX - Application Nots 029

Interfacing
To The 80C196
Family Of
Microcontrollers
(Cont.)

Specify The BOC196 Bus Interface In PSDconfiguration
As shown in the following windows captured from PSDconfiguration, specify the 80C196
interface bus by selecting:

o
o
o
o

Data Bus Width:

X16

Address/Data Mode: MX
Polarity of ALE:
RDIWR Setting:

High

-WR, RD, BHE
(WRL, RD, WRH for Write Strobe Mode)

-----------------~~_Jr_~---------------3-107

PSD4XX/5XX - Application Note 029

Interfacing
Define The DPLD/Decoding Function In The ABEL File
The following is an example of defining the decoding function for the 80C196 based
To The 80C196
application. The codes are stored in three 32KB EPROM blocks and occupy the same
FamilyOt
address space from OOOOh to 7FFFh. This requires the EPROM blocks to be assigned to 3
Microcontrollers different
pages. Table 10 illustrates the address map.

(Cont.)

Depending on your application, you could also use the GPLD to generate the control
signals for the 80C196 "Ready" and the "Buswidth" input.

Table 10. System Memory Map
Device

Memory Space

Memory Page

EPROM, Block 0

0000 -7FFF

Page 0

EPROM, Block 1

0000-7FFF

Page 1

EPROM, Block 2

0000-7FFF

Page 2

SRAM

8000 - 87FF

All Pages

I/O Devices

COOO-COFF

All Pages

module 80C196
title 'Design example of 80C196 DPLD source file';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
pgr3, pgr2, pgr1, pgrO node;
"Page Register outputs
reset pin;
rsLout pin 34;
"Output signals
csiop, rsO, esO, es1, es2 node;

"DPLD output chip selects

"DEFINITIONS
page = [pgr3,pgr2,pgr1 ,pgrO];
" Don't care
X = .x. ;
,Address =[a15,a14,a13,a12,a11 ,a10,a9,a8,X,X,X,X,X,X,a1 ,aO];
equations
"DPLD EQUATIONS
csiop= (Address
rsO = (Address
esO = (Address
es1 = (Address
es2 = (Address

>=
>=
>=
>=
>=

AhCOOO) & (Address <= AhCOFF) ; "Chip Select 256 block
Ah8000) & (Address <= Ah87FF) ; " SRAM, 2KB
AhOOOO) & (Address <= Ah7FFF) & (page == 0); "EPROM 32KB, page 0
AhOOOO) & (Address <= Ah7FFF) & (page == 1); "EPROM 32KB, page 1
AhOOOO) & (Address <= Ah7FFF) & (page == 2); "EPROM 32KB, page 2

"GPLD EQUATIONS
rsLout = reset;
END

-3-.1-08-------------------------------~~~---------------------------------

PSD4XX/5XX - Application Not. 029

SimulatlDn Of 80C196 Bus Cycle With The PSD4XX/5XX
Interfacing
Figure 1B shows the simulation output of the SILOS3 Simulator. The BOC196 is writing a
To The 80C196
word 6677h to SRAM location BOOOh and reading back the same location in the next bus
FamilyOt
cycle.
Microcontrol/ers
(Cont.)

reset

rsLout
adioh
adiol
ale
bhe

esO
rd

rsO

--------------------------------~~~-----------------------------3-.1-0-9

PSD4XX/5XX - Application Note 029

Interfacing
The PSD4XX/5XX
To The 68302

The 68302 Bus
The Motorola 68302 has a non-multiplexed bus with a 16-bit data bus.
It has the following bus signals:

o
o
o
o

Address Bus:

A23-A 1

Data Bus

D15-DO

Address Strobe:

AS

Control Signals:

RIW, UDS, LDS

The 68302 has no AO in the address bus; therefore the AO (ADIOO) pin on the PSD4XXl5XX
is grounded. The signals UDS and LDS (Upper and Lower Data Strobe) are used to select
whether the low byte, high byte or both bytes for the current bus cycle. See Table 11 for the
byte enable assignment.

Table 11. Byte Enable Assignment
UOS

LOS

08-015

00-07

Low

Low

Enabled

Enabled

Low

High

Enabled

Disabled

High

Low

Disabled

Enabled

High

High

Disabled

Disabled

The 68302 and PS04XX/5XX Interface Schematic
Figure 19 is the 68302 and PSD4XXl5XX interface schematic. The address bus, data bus
and bus control signals such as LDS, UDS, RIW, AS etc., are directly connected to the
corresponding pins of PSD4XXl5XX without any additional glue logic. Please note AO pin
on the PSD4XXl5XX is grounded.
For Motorola 16-bit microcontroliers, the data byte DO - D7 is considered as an odd byte
and D8 - D15 as an even byte. This is just the reverse of Intel and other similar processors.
If you select a Motorola 16-bit bus interface, the PSDcompiler automatically swaps these
bytes such that DO-D7 is programmed to even byte locations and D8 - 15 is programmed to
odd byte locations in the PSD EPROM. This swapping is transparent to the user. In the
interface schematic, connect DO - D7 from the 68302 to Port D (Data Port DO - D7) and
D8 - D15 from the 68302 to Port D (Data Port D8 - D15).
The CSO signal from the 68302 can be connected to the CSI pin on the PSD4XXl5XX for
power management. If the 68302 is not fetching code from the PSD, CSO is high and thus
puts the PSD into power saving Standby Mode.

--~----------------------------r====-------------------------------3-110
==:==

:::!!

'I

DO-D15

Ci1

68302

:r":;"

":;"

...B...
80

C2

62

:!

5i""
""""'i9
76
92

A1U1

EXTAL
XTAL

A4
A2
A2

CLKD

M

RXDCL1RXD
TXD1_L1TXD
RCLK1_L1CLK
TCLKCSDS1
CDt...LISY1
CTSCLIGR
RTSCL1RQ
BRG1
RESET

iiALf
BERR
BUSW

DlSCPU

PSD4XX15XX
A3
A1
A2
A4
M
A6
A7

A6
A7
AI
AI
A10
A11

AI
A9

A13
A14
A15
A16
A17
A18
A19
A20

A11
A12
A13
A14
A15

~

8
9

7
6
5
4
3
2

~

Vee

g

67
66

65

64
83

62
61

Vee

.!!!!.

m.

tl

'-11ft

..m..

A21
A22
A23

~

....I!!.

...m..
.!l§.

AS

1\...3

UDS_AO
R_W
LDS_DS
DATAK

m

.Q!..
D1D
D11

I

iffi'

:m
~

108

111
113

""ii4

115
""'ii7
1ii'"
119

......
':"

I
I

RESET
CLKlN

>>

I

29

~
42

l------~=+=t=~::::=f~37~

iiiOC

DREQ PA13
DACi:PA14
DONE_PA15
IACK7_PBD
1ACK6_PB1
IACKCPB2
TlNCPB3
TDUT1_PB4

""'iii9

-;;0

RIW

40

!J.~~~~~~~~~~3=:I=~

lAC
BCLR

D13
D14

41

10K

RiiC

iffi"

LDS

TIN2_PBS

TDUT2_PB6
WDOG_PB7
PB8
PB9

BGA~ ~~~------t-------~
IRQ1 1-;::;-IRQ6 I-;~
IRQ7
FCO
FC1
FC2

~~
AD2/A2

AD3/A3
AD4/A4
ADS/M
AD6/A6
AD7/A7
ADa/Al
ADS/A9
AD10/A10
AD11/A11
AD12/A12
AD13/A13
AD14/A14
AD15/A15

PCO I- 7
PC1
16
PC2...,J5

":;"

DO

i)1
D2

PC3 1-14

D3

PC4

12
11

PC7

1 10

D4
D5
D6
D7

PDO
PD1
PD2
PD3
PD4

60
59
58
57
5&

D8
DS
D10
D11
D12

PDS
PD6
PD7

::

~3

53

D15

PC5

PC6

>-13

RIW

B
2

;,:=
Q,

!

~

~
:a.c
is'
;-

i

RESET
CSI
CLKIN

36

PEOIUDS

36
34
33
32
31
30

PE1/AS
PE2
PE3
PE4
PE5
PE6
PE7

28

VSTDBY

PAO
PA1
PA2
PA3
PA4
PM
PA6
PA7
PBO

PB1
PB2
PB3
PB4

50

49

48
47
48
45

PBS

44

PB6

43

PB7

VCC

!It

LDS

......

_~

AVEC

I

~
I

CSO

t

m

CI2

IIII

CS3

FiiZ

ADO/AD

....

U1

---'

RESET
CLKlN

......

RSLOur

I

If

II

PS04XX/5XX - Application Note 029

Interfacing
Specify The 68302 Bus Interface In PSDConfiguration
The PSD4XX/5XX As shown in the following windows captured from PSOconfiguration, specify the 68302 bus
To The 68302
interface by selecting:
(Cont.)

o
o
o
o
o

Data Bus Width:

X16

Address/Data Mode:

NM

ALE/AS signal:

Yes (No if you prefer not to use />is to latch address)

Polarity of ALE:

High (if Yes on ALE/AS)

RDIWR Setting:

RIW, LOS, UOS

~~----------------------------f===~-------------------------------3-112

PSD4XX/5XX - Application Nots 029

Interfacing
The
PSD4XX/5XX
To The 68302
(Cont.,

Define the DPLD/Decoding function in the ABEL file
The following is an example of defining the decoding function for the 68302 based
application. The codes are stored in three 32KB EPROM blocks and occupy the same
address space from OOOOh to 7FFFh. This requires the EPROM blocks to be assigned to 3
different pages. Table 12 illustrates the address map.

Table 12. System Memory Map
Device

Memory Space

Memory Page

EPROM, Block 0

0000 - 3FFF

All Pages

EPROM, Block 1

4000 -7FFF

Page 1

EPROM, Block 2

4000 -7FFF

Page 2

SRAM

8000 - 87FF

All Pages

I/O Devices

COOO- COFF

All Pages

module 68302
title 'example of 68302 DPLD source file ';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a1 0,a9,a8,a1 pin;
"Use the reserved names to declare the following special functions
reset pin;
rst_out pin 34;
" Output signals
" Internal PSD5XX PLD output signals.
"DPLD outputs using reserved names.
csiop, rsO, esO, es1, es2, es3 node;
" Definitions
" Don't care
X= .x.;
"Note in the Address definition that a7 - a2 are denoted by don't-cares
Address = [a15,a 14,a13,a 12,a11 ,a 10,a9,a8,X,X,X,X,X,X,a 1 ,X];
equations
"DPLD EQUATIONS
csiop = (Address >= I\hCOOO) & (Address <= I\hCOFF) ; "Chip Select 256 block
rsO = (Address >= I\h8000) & (Address <= I\h87FF) ; "SRAM, 2KB
esO = (Address >= I\hOOOO) & (Address <= I\h3FFF) & (page == X);
"EPROM 16KB, any page
es1 = (Address >= I\h4000) & (Address <= I\h7FFF) & (page == 1); "EPROM 16KB, page 1
es2 = (Address >= I\h4000) & (Address <= I\h7FFF) & (page == 2); "EPROM 16KB, page 2
"GPLD EQUATIONS
rst_out = reset;
END

--------------------------------~~~-~-------------------------------3-113

PSD4XX/5XX - Application Note 029

Interfacing
The
PSD4XX/5XX
To The 68302

Simulation Of 68302 Bus Cycle With The PS04XX/5XX
Figure 20 shows the simulation of 3 bus cycles of the 68302. The 68302 is writing a
byte to SRAM location 8477h and location 8476h. The third bus cycle is a word read to the
same locations.

(Cont.)

Figure 20.

rsCout

R1

elkin

01

adioh

00

adiol

00

as

01

datah
datal

XX
XX

esO

01

es1

00

Ids

01

rdorwr

-3--,-,4-------------------------------~~~---------------------------------

PSD4XX/5XX - Application Nots 029

Interfacing
The
PSD4XX/5XX

To
68HC16/68330/
331/332/340

The 683XX Bus
This group of Motorola 16-bits microcontrollers have similar bus structure and the bus
interface to the PS04XXl5XX are identical. The 68332 microcontroller is used here as an
example. The bus is a non-multiplexed data and address bus and has the following signals:

o
o
o
o

Address Bus:

A23-AO

Data Bus:

015-00

Address Strobe:

AS

Control Signals:

OS, RIW, SIZO, SIZ1

The higher address pins A23-A 19 can be configured either as address lines or as chip
select outputs (CS6 - CS10) at reset time. Two of the signals, SIZO and AO are used to
determine whether the current cycle is a byte or a word operation. If SIZO is low, it is always
a word operation. If SIZO is high, it is a byte operation and AO determines which byte is
enabled.
The PS04XXl5XX generates internal write or read pulses based on the status of the RIW
and OS signal inputs.

The 68332 And PSD4XX/5XX Interface Schematic
Figure 21 is the 68332 and PSD4XXl5XX interface schematic. The address bus, data bus
and the bus control signals such as DS, RIW, SIZO, AS etc., are directly connected to the
corresponding pins of PS04XXl5XX without any additional glue logic.
For Motorola 16-bit microcontrollers the data byte DO - 07 is considered as odd byte and
08 - 015 as even byte, which is the reverse of Intel and other similar processors. If you
select a Motorola 16-bit bus interface, the PSOcompiler automatically swaps these bytes
such that DO - 07 is programmed to even byte locations and 08 - 15 is programmed to
odd byte locations in the PSO EPROM. This swapping is transparent to the user. In the
interface schematic, connect DO - 07 from the 68332 to Port C (Data Port DO - 07) and
08 - 015 to Port 0 (Data Port 08 - 015).
The CSBOOT signal from the 68332 can be connected to the CSI pin on the PS04XXl5XX
to control the device power consumption. If the 68332 is not fetching code from the PSO,
the CSBOOT is high and puts PS04XXl5XX into power saving Standby Mode. After
system reset, the CSBOOT has a default value of 1M byte memory space starting from
address OOOOOOh. This value can be re-programmed after system initialization to include
the PSO EPROM, SRAM and 1/0 space.

-----------------------------------~~~----------------------------------====

3-115

:"'1'1

cii'
~

CIi

00-015

~

:'"
MC68332
DO

m

IW

1M

00
00
~

~
~

W
08
~

III_I
I11I11111
11111"11

AO
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All

MO

A13

A11

A"

M2

0"
oU

MS
M6
M7

M3
M4
M5

oSACKO
DSACKl

A18
A19_CS6
A20_CS7
A21_CS8
A22_CS9
A23_CS10

OS

41

A08/A8
A09/A9
Aol0/Al0
Aoll/All
Ao12/A12
Ao13/A13
Ao14/A14
Ao15/A15

~

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

1...17
L-16
L-15
L...J4
13
12
11
10

POO L60

POl
P02
P03

59
58
57
56
55

P~

P05

P06
P07

I

....5.4
53

lOS
R/W

RESET

~ I~~
SIZO
SIZl
ClKOUT
CSBOOT
BR_CSO
BG_CSl
BGACK_ CS2
FCO_CS3
FC1_CS4
FC2_ CS5

68
67
66
65
64
63
62
61

A8
A9

M2

RESET

AoO/AO
Aol/Al
A02/A2
A03/A3
A04/A4
ADS/AS
A06/A6
A07/A7

Al
A2
A3
A4
AS
A6
A7

CSI

II

ClKIN

81
80
66
112
113
114
115
118
119
120

SIZO
AS

38
37
3
34
33
32
31
30
~8

•

-=-

RESET
ClKlN
RSLOUT

PEO/SIZO
PElIALE
PE2
PE3
PE4
PE5
PE6
PE7
V~IU~Y

i~
I

PSD4XX15XX

M

ow
ml
on

ou

q,lliii;::

" Ul

~

2

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

27
26
25
24
23
22
21
20
50
49
48
47
46
45
44
43

00

ol~
o2~

'1i

:::::

fil

::t

03
04
05

iii
if

07

2
co

~

08.1

~~

010
011
012
013

""'i'ii4
015

S'

PSD4XXj5XX - Application Nots 029

Interfacing
The
PSD4XX/5XX
To
68HC16/68330/
331/332/340
(Cont.)

Specify the 68332 Bus Interface in PSDConfiguration
As shown in the following windows which are captured from PSOconfiguration, the 68332
bus interface can be specified by selecting:

Q Data Bus Width:

X16

Q Address/Data Mode: NM

Q ALE/AS signal:
Q Polarity of ALE:
Q RDIWR Setting:

iii

Yes (No if you prefer not to use AS to latch address)
High (if Yes on ALE/AS)
AIW, OS, SIZO

Data Bus Width: X16 Address/Data Mode: NM

--------------------------------f=~~-------------------------------====

3-117

PSD4XX/5XX - Application Not, 029

Interfacing
The
PSD4XX/5XX
To
68HC16/68330/
331/332/340

Define the DPLD/Decoding function in the ABEL file
The following is an example of defining the decoding function for the 68332 based
application. The codes are stored in three 32KB EPROM blocks and occupy the same
address space from OOOOh to 7FFFh. This requires the EPROM blocks to be assigned to 3
different pages. Table 13 illustrates the address map.

Table 13. System Memory Map

(Cont.)

Device

Memory Space

Memory Page

EPROM, Block 0

0000-3FFF

All Pages

EPROM, Block 1

4000-7FFF

Page 1

EPROM, Block 2

4000-7FFF

Page 2

SRAM

8000 -87FF

All Pages

I/O Devices

COOO-COFF

All Pages

module 68332
title 'example of 68332 DPLD source file ';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
"Use the reserved names to declare the following special functions
reset pin;
rst_out pin 34;
" Output signals
"Internal PLD output signals.
"DPLD outputs using reserved names.
csiop, rsO, esO, es1, es2 node;
" Definitions
"Don't care
X=.x. ;
"Note in the Address definition that a7 - a2 are denoted by don't-cares
Address = [a15,a 14,a 13,a12,a 11 ,a1 0,a9,a8,X,X,X,X,X,X,a 1,aO];
equations
"DPLD EQUATIONS
csiop:; (Address >'" -"hCOOO) & (Address <= AhCOFF) ; "Chip Select 256 block
rsO = (Address >= 1'-ha000) & (Address <= Ah87FF) ; "SRAM, 2KB
esO = (Address >= "hOOOO) & (Address <= "h3FFF) & (page == X);
"EPROM 16KB ,any page
es1 = (Address >= "h4000) & (Address <= "h7FFF) & (page == 1); "EPROM 16KB, page 1
es2 = (Address >= "h4000) & (Address <= "h7FFF) & (page == 2); "EPROM 16KB, page 2
"GPLD EQUATIONS
rs,-out

=reset;

END

----------------------------------~~~--------------------------------3·118
====

PSD4XX/5XX - ApplIcatIon Nots 029

Interfacing
The
PS04XX/5XX
To
B8He1B/B8330/
331/332/340

SimulatiDR Of 68332 Bus Cycle With The PSD4XX/5XX
Figure 22 shows the simulation of five 68332 bus cycles. The first two are byte write cycles
to SRAM locations 8476 and 8477. The next cycle is a word read to the same location.
The next cycle is reading an EPROM block.

Figure 22.

(Cont.)

reset
rSI_oul
adioh
adiol
datah
datal
rsO

esO

es1
rdorwr

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ =ss tEJE
~~~----------------------------3.-1--19

I'SIJ4XX/5XX - Appllt:llf/on Nof. 029

Interlacing
The
PSD4XX/5XX
To 18

The Z8 Bus
The Z8 has an 8-bit multiplexed external memory bus. Port 1 of the Z8 is used as the
multiplexed bus port which provides the multiplexed lower address byte and data. Port 0
can be used as the output port for the non-multiplexed address lines A15-A8. The bus has
the following signals:

o
o
o
o

Address/Data Bus: AO? - AOO
Address Bus:

A15 - A8

Address Strobe:

AS

Control Signals:

OS, RIW, OM

The Z8 has 64KB of ~gram memory space. It can also addre~another 64KB of data
memory if the signal OM (data memory) is enabled. The signal OM can be programmed to
appear on pin 4 of Port 3. If your application does not require separate data space, there is
no need to connect the OM as input to the PS04X15XX.

The Z8 And PSD4XX/5XX Interface Schematic
Figure 23 is the Z8 and PS04XXl5XX interface schematic. The address bus, data bus
and the bus control signals such as OS, RIW, AS etc., are directly connected to the
corresponding pins of PS04XXl5XX without any additional glue logic.
In this example, OM is used to separate the program space from the data space by
including it in the OPLO chip select equations. Oue to the PS04XXl5XX architecture
requirement that any input s!9!lals which are included in the EPROM chip select equations
must come from Port A, the OM signal is connected to pin PAO in the schematic.

=_.

~~------------------------~I'~·--------------------------3-120

~

PSD4XX15XX

Ul

C2
-::"

-::"

II

~-

I

i

I
I

I

1:'
II~I~ I

7

:ET

8

OS

ADO
ADl
AD2
AD3
AD4
ADS

Pl-0
P1-1
Pl-2
Pl-3
Pl-4
Pl-5
Pl-6
Pl-7
po-O
PO-l
PO-2
PO-3
PO-4
PO-5
PO-6
PO-7

AD7

9
8
7
6
5
4
3
2

AS
A9
Al0
All
A12
A13
A14
A15

68
67
66
65
64
63
62
61

OS

;1

ADS

1111

"-1Iti

29

I III

P3-4

I 29

ADO/AO
AD1/Al
AD2/AZ
AD3/A3
AD4/A4
ADS/AS
AD6/A6
AD7/A7
ADS/AS
ADS/AS
ADl0/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

U2
peo
pel
PC2
PC3
PC4
PC5
PC6
PC7

17
16
15
14
13
12
11
10

~

,I:
;J
§

~

~

PDO
PDl
PD2
PD3
PD4
PD5
PD6
PD7

60
59
58
57
58
55
54
53

ar
;-

i

~

DS
RIW

RESET

PEO
PElIAS
PE2
PE3
PE4
PES
PE6
PE7

AS
RST_OUT
Vee

28 I VSTDBY

T e3

'I;;
t:
I'

-::"

DM

PAO
PAl
PAZ
PA3
PA4
PA5
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PB5
PB6
PB7

I

~,
t:;::
:::::t
II:

~

5

I

CD

a

PSD4XX/5XX - Application Nots 029

Interfacing
The
PSD4XX/5XX

To 18
(Cont.)

Specify The 18 Bus Interface In PSOconfiguration
As shown in the following windows which are captured from PSDconfiguration, the Z8 bus
interface can be specified by selecting:

o
o
o
o

Data Bus Width:

X8

AddresslData Mode: MX
Polarity of ALE/AS:

Low

RDIWR Setting:

RIW,DS

-3--1-22-------------------------------~~~~---------------------------------

1'S04XX1SXX - Application Note D29

Interfacing
The
PSD4XX/5XX
To 18
(Cont.)

Define The DPLD/Decodlng Function In The ABEL File
The following is an example of defining the decoding function for the Z8 based application.
64KB of code is stored in EPROM blocks 0 and 1. 'The SRAM, 1/0 space and EPROM
block 2 are assigned as data memory. Table 14 illustrates the address map.

Table 14. System Memory Map
Device

MemolY Space

EPROM, Block 0

0000-7FFF

Code Area

EPROM, Block 1

8000- FFFF

Code Area

EPROM, Block 2

0000-7FFF

Data Area

SRAM

8000-87FF

Data Area

1/0 Devices

COOO-COFF

Data Area

moduleZ8
title 'example of Z8 DPLD source file ';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
"Use the reserved names to declare the following special functions
reset pin;
dm pin 27
"assign pin PAO as input pin for OM
rsLout pin 34;
" Output signals
"Internal PLD output signals.
"DPLD outputs using reserved names.
csiop, rsO, esO, es1, es2, es3 node;
" Definitions
"Don't care
X=.x. ;
"Note in the Address definition that a7 - a2 are denoted by don't-cares
Address = [a 15,a14,a13,a12,a11 ,a1 0,a9,a8,X,X,X,X,X,X,a 1,aO];
equations
"DPLD EQUATIONS
csiop
rsO
esO
es1
es2

=
=
=
=
=

(Address >= I\hCOOO) & (Address <= I\hCOFF)
(Address >= I\h8000) & (Address <= I\h87FF)
(Address >= I\hOOOO) & (Address <= I\h7FFF)
(Address >= I\h8000) & (Address <= I\hFFFF)
(Address >= I\hOOOO) & (Address <= I\h7FFF)

& !DM ; "Chip Select 256 block
& !DM;" SRAM, 2KB
& OM;" EPROM 32KB code
& OM;" EPROM 32KB code
& 10M; • EPROM 32KB data

"GPLD EQUATIONS
rsLout = reset;
END

__________________________________ ,-s ..._________________________________
fN..~.

3-123

PS04XX/5XX - Application Note 029

Interfacing
The
PS04XX/5XX
To 18
(Cont.)

Simulation Of 18 Bus Cycle With The PSD4XX/5XX
Figure 24 shows the simulation of two Z8 bus cycles. The first is a code fetch at
location OOOOh from EPROM block 0, with IDM input high. The second cycle is a data
read at location OOOOh from EPROM block 1.The IDM signal is low since this is a data
memory bus cycle.

Figure 24.

es2
reset

D1

-3--1~24~~~~~~~~~~~~~~---~~~~~~~~~~-------------------

PSD4XX/5XX - Application Nots 029

Interfacing
The
PS04XX/5XX
To 180
(Cont.)

The 180 Bus
The zao has an a-bit non-multiplexed bus. The following signals are used to interface to
memory or I/O devices:

o
o
o

o

Address Bus:

A15 - AO

Data Bus:

D7 - DO

Address Strobe:

None

Control Signals:

M1, MREO, lORa, RD, WR

The zao h~64KB of program memory space and 256 bytes of I/O space. In a memory
cycle both M1 and MREO are low. In an I/O bus cycle, M1 is high and lORa is low. Only
A7-AO are active and thus limit the I/O space to 256 bytes. If M1 is low and lORa is low, it
is an interrupt acknowledge bus cycle. M1 can be ignored if interrupt is not used.

The 180 And PSD4XX/5XX Interface Schematic
Figure 25 is the zao and PSD4XXl5XX interface schematic. The address lines
A 15 - AO are connected to the ADIO Port and the data lines D7 - DO are connected to Port
C. Control signals RD and WR are directly connected to the corresponding pins of the
PSD4XXl5XX without any additional glue logic.
The PSD4XX/5XX does not have specific pins assigned to MREO, lORa and M1. Since
these signals are used in the EPROM chip select equations, you should assign them to
Port A pins in the ABEL file.
\

---=

-----------------------------------f==aF~-----------------------------------

.m

::n

~

i

I

IORO

I

~Rl
:E

4.7K

l
II/iii.:
11111111

111111111
11111 on

r
I

w'""

~

M 111

I

•

-

_

M

M

'

'"

M
A6

M
AS

S
4
9
3
2

IORO
MREO

"""

A3

8

A6
Al
A7
A8

All
A12
A13
A14

A9
Al0
All
A12

68
67
68
65

.-

...

u

"..'
DO

m

m

~M'

.-~

A2

A7
A2
AS
A9
Al0

_________~g~ r

I

.SD4XX/5XX

Z80

I-r=i~========~~
2?

~

~

MREg

U

ADO/AD

AD3/A3
AD4/A4
ADS/AS
ADS/A6
AD7/A7

~ r=~-!!"-

~

r-::~-.!!l!'

pe7

~'M"
~~."
~~4
,m••"

AD13/A13

- ..
y

PAO

elKIN

RD
WR
RST_OUT

Vee

~

38
37
36
34

PEO
PEl
PE2

33
32
31

PE3
PE4
PES

30

~

28

r ___+_~R~E~S~ET!..-_
__

PE6

VSTDBY

I

~~===-t-:::""-.J

t

PA4
PAS
PAS
PA7
PBO
PBl
PB2

50
49

~ 46~

48

PB4
PBS
PB7
PB6

45
43
44

-=
DO-D7

,~
~
I
~
~

ii
~

RESET

WR

~

C5

;;-

~

...J

~
'iiI
;:~

;= t;~

i

I-!= "hCOOO) & (Address <= "hC7FF)
esO
(Address >= "hOOOO) & (Address <= "h3FFF)
es1
(Address >= "h4000) & (Address <= Ah7FFF)
es2
(Address >= "h8000) & (Address <= "hBFFF)
rsCout

& !mreq "SRAM, 2KB
&
&

!mreq; "EPROM 16KB code
!mreq; "EPROM 16KB code
& !mreq; "EPROM 16KB data

= reset;

END

~~----------------------------f===~-------------------------------3-128

====

PS04XXj5XX - Application Nots 029

Interfacing
The
PS04XX/5XX
ToZ80
(Cont.)

Simulation Of 180 Bus Cycle With The PSD4XX/5XX
Figure 26 shows the simulation of three Z80 bus cycles. The first is a code fetch at
location OOOOh from EPROM block O. The second cycle is a data write to SRAM at location
8000h, and a read to the same location in the next cycle.

Figure 26.

rsCout

R1

adioh

00

adiol

00

datal

23

ioreq

01

mreq

00

rd

00

esO

01

rsO

-----------------------------------~~~--------------------------------3.-12--9

PSIJ4XXISXX - Appllaf/on /10111 029

Interfacing

The STSOR26 Bus

1he
PSD4XX/5XX
10S19OR26

The ST90R26 is the ROMless member of the ST9 family of microcontrollers from
SGS-Thomson. The ST9 has an 8-bit multiplexed bus and the following are the bus signals
used to interface to memory or 1/0 devices.

o
o
o
o

Address/Data Bus: A07-AOO
Address Bus:
A15-A8
Address Strobe:

AS

Control Signals:

OS, RIW, P/O

The higher address lines A15-A8 are not multiplexed and are driven from Port P1. The ST9
has two memory spaces: the program and data memory. Each space has 64KB and is
selected by the P/O signals. A high on the P/O signal indicates program space.
The PS04XXl5XX generates internal write or read pulses based on the status of the RIW
and OS Signal inputs.

The ST90R26 And 'SD4XX/5XX Interface Schematic
Figure 27 is the ST90R26 and PS04XXl5XX interface schematic. The address bus, data
bus and the bus control signals such as lOS, RIW, lAS etc., are directly connected to the
corresponding pins of PS04XXl5XX without any additional glue logic. The P/O signal is
connected to one of the pins in Port A as input to the OPLO.

".,.

~~~1~aO~---------------------------=~~.--------------------------------

~

c;"
~
CIj

~

=-'

A8-A15

fI)

I

ClK

ST90R26
./

A8
A9
AlO
AIl
A12
AU
A14
A15
ADO
ADI
AD2
AD3
AD4
ADS
AD6
AD7

..

11~ t
11l1li

-I
1ttQ-.

4L..::f
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

OSCIN
RESET
A8/Pl-0
A9/Pl-l
Al0/PI-2
All1PI-3
AI2/PI-4
AI3/PI-5
AI4/PI-6
AIS/PI-7
AO/DO
A11D1IPO-l
A2/D2/PO-2
A3/D3/PO-3
A4/D4/PO-4
A5/D5/PO-5
A6/D6/PO-6
A7/D7

PSD4XX15XX

Ul
OSCOUT

~

.,

A8
A9
Al0
All
A12
A13
A14
A15

Os

Qh

20

ADO
ADI
AD2
AD3
AD4
AD5
AD6
AD7

9
8
7
6
5
4
3
2
68
67
66
65
64
63
62
61
41
29

P/D/NMt/P2 - 0

40

~ AS
RIW

OS

26

R1WJ

39

25

42

~

AS

~
34

RST OUT

-%
-T,"To-

~

L RESET

RESET

PID

c:>

~

28

!:::-

ADO/AO
ADI/Al
AD2/A2
AD3/A3
AD4/A4
AD5/AS
AD6/A6
AD7/A7
AD8/AS
AD9/A9
AD10/Al0
ADll/All
ADI2/AI2
ADI3/AI3
ADI4/AI4
ADI5/AI5

i

U2
PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

r*r*-15
1*=
r*H?H}r-1L

PD~

~

POI
PD2
PD3
PD4
PD5
PD6
PD7

OS

~
rs7

r56
t55

AF
r-=--

~

Cfi

!.
~

§

iii
~
a;-

lit

i

::

RIW
RESET
CSt
ClKIN
PEO
PEl/AS
PE2
PE3
PE4
PE5
PE6
PE7
VSTDBY

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

27
26

~
~
~

tit-

120
r-=~
~
t47

1-"46
1-44
1-43
r=-

145

I

i

)ol

t

t;::
&'I
::t

=

~
If

~

PSD4XX/5XX - Application Not. fJ29

Interfacing

Specify 1he S190R26 Bus Interface In PSDcDnfiguratiDn

1he
PSD4XX/5XX
10S190R26

As shown in the following windows which are captured from PSDconfiguration, the
ST90R26 bus interface can be specified by selecting:

(Cont.)

o
o
o
o
o

Data Bus Width:

XB

Address/Data Mode:

MX

ALE/AS signal:

Yes

Polarity of ALE:

Low

RDIWR Setting:

RJW,DS

-3-.1-32----------------------------wrJr~~-------------------------------

PSD4XX/5XX - Application Not. 029

Interlacing

Define The DPLDIDBcodlng Function In the ABEL File

1he
PSD4XX/5XX
10S190R26

The following is an example of defining the decoding function for the ST9 based
application. The codes are stored in three 16KB EPROM blocks and occupy address space
from OOOOh to BFFFh. The SRAM space is from BOOOh to B7FFh. The P/D input is used to
separate the EPROM (program) space to SRAM and I/O (data) space.

(Cont.)

Table 16. System Memory Map
Dert/ce

Memor, Space

EPROM, Block 0

0000-3FFF

Code

EPROM, Block 1

4000-7FFF

Code

EPROM, Block 2

BOOO-BFFF

Code

SRAM

BOOO-B7FF

Data

I/O Devices

AOOO-AOFF

Data

module st9
title 'example of st9 DPLD source file';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11,a1 O,a9,aB,a1,aO pin;
reset pin;
pin 27;

pd

"using the right pin #s
"port A pin-O for P/D input

"Output signals
csiop, rsO, esO, es1, es2 node;
rsCout pin 34;

"DPLD output chip selects

"DEFINITIONS

x = .x. ;

" Don't care
Address =
[a 15,a14,a13,a12,a11,a1O,a9,aB,X,X,X,X,X,X,a1,aO];
equations
"DPLD EQUATIONS
csiop
rsO
esO
es1
es2

=
=
=
=
=

(Address >= I\hAOOO) & (Address <= I\hAOFF)
(Address >= I\hBOOO) & (Address <= I\hB7FF)
(Address >= I\hOOOO) & (Address <= I\h3FFF)
(Address >= I\h4000) & (Address <= I\h7FFF)
(Address >= 1\h8000) & (Address <= I\hBFFF)

& Ipd ;
& Ipd;

& pd;
& pd;

& pd;

"Chip Select 256 block
"SRAM,2KB
"EPROM 16KB
"EPROM 16KB
"EPROM 16KB

"GPLD EQUATIONS
rsCout = reset;
END

-------------------------~#_;------------------------'I"
3-133

PfIJ4XX/5XX - Application Note 029

Interfacing
7he
PS04XX/5XX
70S790R26

Simulation Of The ST90R26 Bus Cycle With The PSD4XX/5XX
Figure 28 shows the simulation of three ST90R26 bus cycles. The first two cycles are
byte write (55h) and read to SRAM location 8000h, and the third is a code fetch cycle to
EPROM location OOOOh. Please note that the P/O separates the data and program space.

(Cont.)

Flgure2B.

pd

rsO

DO

rw

01

"""""""1""111'
11'1:;i!lliill'
1_l
l'II:":;,,i:III,11

'1'1"1'11 'lil]'lIr,L':1
I1'1""1'1 IIIII

III

II

"'111'fill

I III Iff

'II

-!lEE

.cr:

-3-.1-34-----------------------------~~~--------------------------------

PSD4XX/5XX - ApplIcation Not. 029

Interfacing
The
PSD4XX/5XX
To80C166

The 80C166 Bus
The Siemens' 80C166 is a very flexible microcontroller which can be operated in
multiplexed or non-multiplexed bus mode. The bus configuration and data bus width
(8 or 16) are determined at reset by sampling the EBCO-1 input pins. The multiplexed
16-bit data/16 bit address bus mode is selected here for PSD4XXl5XX implementation
since it provides the best performance with the least pin count.
The 16-bit multiplexed bus consists of the following signals:

o
o
o

Address/Data:

AD15-ADO

Address Latch:

ALE

Control Signals:

RD, WR, BHE

The 80C166 also provides higher address lines A16-17 (segment address) if required.

The 8oC166 And PSD4XX/5XX Interface Schematic
Figure 29 shows the 80C166 and PSD4XXl5XX interface schematic. The address bus,
data bus and bus control signals such as IRD, twR, IBHE etc., are directly connected to the
corresponding pins of PSD4XXl5XX without any additional glue logic. Note that EBCO is
connected to ground and EBC1 is connected to Vee to select the 16-bit address and 16-bit
data multiplexed bus mode.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FSJlIffISI.

YFJF.,jr----------------a-.-1a-S-

c:o

;!.'!

IQ

iil

§i
CII

;g
PSD4XXl5XX

80C166
ADO
ADl
AD2
AD3
AD4
ADS
ADS
AD7

po.o
PO.l
PO.2
PO.3
PO.4
PO.S
PO.6
PO.7
PO.8
PO.9
PO.l0
PO.ll
PO.12
PO.13
PO .14
PO .15

Ilr'
IIIIQI

RD#

11

IIQ:I~~

P3.13/WR#

80

P3.12/BHE#

77

II~II.I

9
8
7
6
5
4
3
2

AD8
AD9
AD10
ADll
AD12
AD13
AD14
AD15

68
67
66
65
64
63
62
61

RD

41

WR

29

RESET

ADO/AO
AD1/Al
AD2/A2
AD3/A3
AD4/A4
ADS/AS
ADS/A6
AD7/A7

EBCO

AD8/A8
AD9/A9
AD10/Al0
ADll/All
AD12/A12
AD13/A13
AD14/A14
AD15/A15

~

28

60
59
58
7
56
55
54
53

S

VSTDBY

PAO
PAl
PA2
PA3
PA4
PAS
PA6
PA7
PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

27
26
25
24
23
22
21
20
50
49
48
47
46
45
44
43

2

i~
I

~
;::

=2
...
=
8:
In

~

~

~

!

~

~

~

!iii
iii'
....
iir

::

WR

PEOIBHE
PElIAlE
PE2
PE3
PE4
PES
PE6
PE7

9

17
16
15
14
13
12
11
10

RD

ClKIN

1

PDO
PDl
PD2
PD3
PD4
PDS
PDS
PD7

RESET

G: I
-=

PCO
PCl
PC2
PC3
PC4
PC5
PCS
PC7

Q,

CSI

EBCl

~
;;.

U2

~

;:!:

~
~

;r
~

CD

PS04XX/5XX - Application Nots 029

Interfacing
The
PS04XX/5XX
T080C166
(Cont.)

Specify The BOC166 Bus Interface In PSDconfiguration
As shown in the following windows which are captured from PSDconfiguration, the 80C166
bus interface can be specified by selecting:

o
o
o
o
o

Data Bus Width:

X16

Address/Data Mode:

MX

ALE/AS signal:

Yes

Polarity of ALE:

High

RDIWR Setting:

RD, WR, SHE

----------------------------------f=s~~--------------------------------====
3-137

I'SD4XX/5XX - Appl/Clltlon ..ttl D29

Interfacing
The
PSD4XX/5XX
To8DCf.
(1:l1li'.)

Defina Tha 'PLD/Dac.ding Functi.n In Tha ABEL fila
The following is an example of defining the decoding function for the BOC166 application.
The code is stored in two 16KB EPROM blocks and occupies address space OOOOh to
7FFFh. The SRAM space is from BOOOh to B7FFh. Table 17 illustrates the address map.

Tablll 11. Systlllll MIIIII.ry Map
'1I,,/ca

Mllm.ry SpaclI

EPROM, Block 0

0000-3FFF

Code

EPROM, Block 1

4000-7FFF

Code

SRAM

BOOO-B7FF

Data

1/0 Devices

COOO-COFF

Data

module 8Oc166
title 'example of BOc166 DPLD source file';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,aB,a1 ,aO pin;
reset pin;
rsCout pin 34;
"Output signals
csiop, rsO, esO, es1 node;

"DPLD output chip selects

"DEFINITIONS

x

= .x. ; " Don't care
Address =
[a15,a14,a13,a12,a11 ,a10,a9,aB,X,X,X,X,X,X,a1 ,aO];
equations
"DPLD EQUATIONS
cSiop
rsO
esO
es1

=
=
=
=

(Address >= I\hCOOO) & (Address <= I\hCOFF) ;
(Address >= I\hBOOO) & (Address <= I\hB7FF) ;
(Address >= I\hOOOO) & (Address <= 1\h3FFF) ;
(Address >= I\h4000) & (Address <= 1\h7FFF) ;

"Chip Select 256 block
"SRAM,2KB
"EPROM 16KB
• EPROM 16KB

"GPLD EQUATIONS
rsCout = reset;
END

--------------------------------'61~·-------------------------------3·138
iIJ!;!!'= I

I'SD4XX/5XX - Application Nots 029

Interfacing
The
PSD4XX/5XX
T080C166

Simulation Of SOC166 Bus Cycle With The PSD4XX/5XX
Figure 30 shows the simulation of three 80C166 bus cycles. The first two cycles are byte
write (55h) and read to SRAM location 8000h, the second is a code fetch cycle to EPROM
location OOOOh.

(Cont.)

Figure 30.

Figure 30 depicts a WORO read at location OOOOhex when bhe=O and AO=O.

Interfacing
The
PSD4XX/5XX
To Echelon

NEURON@

3150™ Chip

The 3150 Bus
The 3150 has an 8-bit non-multiplexed bus. The following signals are used to interface to
memory or I/O devices:

o
o
o
o

Address/Data:

A 15-AO

Data bus:

07-00

Address Strobe:

None

Control Signals:

RIW, E (Enable Clock)

The 3150 has 64KB of program memory space. The E signal frequency is half that of the
input clock. It is low during the second half of the bus cycle when read or write operation is
taking place. A low RIW signal indicates it is a write bus cycle.

The 3150 and PSD4XX/5XX Interface Schematic
Figure 31 shows the 3150 and PS04XXl5XX interface schematic. The address lines
A15-AO are connected to the AOIO Port and the data lines 07-00 are connected to Port C.
Control signals RIW and Eare directly connected to the corresponding pins of the
PS04XXl5XX without any additional glue logic.

----------------------------------~~&r--------------------------------====

3-139

c:..

,...----------------------------------------------~

i

S;
CD

~

D [7: OJ

:"'"'

~

2

i~
I

§iI :g:to.
:;:::

A[15:0J

i= AhC800) & (Address <= AhC8FF)
rsO
= (Address >= AhCOOO) & (Address <= AhC7FF)
esO
(Address >= AhOOOO) & (Address <= Ah3FFF)
es1
(Address >= Ah4000) & (Address <= Ah7FFF)
es2 = (Address >= Ah8000) & (Address <= AhBFFF)

" 1/0 Chip Select 256 bytes

;
;
;
;
;

"SRAM,2KB
" EPROM 16KB code
" EPROM 16KB code
" EPROM 16KB data

END

~--------------------------------r#fAr~~--------------------------------3-142
====

1'SD4XX/5XX - AppllCllfltln ._1129

Interfacing
The
PSD4XX/5XX
To Echelon
NEUROfF'
315O™ Chip

SlmulatlDn Of The EchelDn NEURON 3150 Bus Cycle With Th. PSD4XX/5XX
Figure 32 shows the simulation of three 3150 bus cycles. The first cycle is a code fetch
cycle to EPROM location OOOOh and the following two cycles are write (55h) and read to
SRAM location FOOOh.

(ClJllt.)

Conclusion

Using the PSD4XXl5XX with microcontrollers in embedded applications provides the
following benefits over designs implemented with discrete components:

o
o
o
o
o
o
o
o
o
o
o

Two chip solution (MCU & PSD) - smaller board size with fewer layers.
ZPLD allows quick logic fixes and updates.
Short development cycle
Increase in system performance
Reprogrammability.
Lower power consumption
Lower manufacturing cost
Lower system cost.
Security of design (security bit)
Increase in system reliability.
Reduced inventory cost.

--------------------------r',"-------------------------=:III
3-143

PSD4XX/5XX - Application Nots 029

-3--1~44-------------------------------~jr~~---------------------------------

:F==~=:
---==
--

Programmable Peripheral

----~

1''-- . . .
-""

~

Application Note 030

-.-..-.-

PS04XX and PS05XX
Power Calculations and Reduction
Introduction

The PSD4XX and PSD5XX families of programmable microcontroller peripherals integrate
many functional blocks such as multiple ZPLD (Zero Power PLD) arrays, EPROM, SRAM,
110 Ports, Counterrnmers and an Interrupt Controller unit. The PSD family is being used
extensively in microcontroller applications around the world by virtue of its flexibility and
high level of integration, configurability and ease of use. This integration makes possible
the design of very compact systems enabling the user to squeeze a great deal of
functionality into a very small space. Thus, PSDs have found their way into small hand-held
and battery operated applications such as cellular phones, medical instrumentation, and
notebook computers that usually require, in addition to small space, very low power
consumption. In many cases the PSDs are the lowest power design alternative possible!
The PSD4XXl5XX families are based on a patented high-performance CMOS technology
and, like other CMOS devices, consume very little power even without the advanced power
management features. However, the architecture of the family provides additional power
management control via configuration bits, automatic power down circuitry, power switches
and sleep mode making the PSD device even more valuable in power-sensitive
applications.
This application note will describe the methods of optimizing and reducing the power
consumption of the PSD device during system operation, standby and sleep mode. It
makes sense to use these techniques even when low power is not a design requirement
since they are easy to implement.

Power Use
In The
PSD4XX
andPSD5XX

The PSD4XX and PSD5XX contain several modules internally, each of which can be
considered power consuming. These modules include the following:

o
o
o
o
o
o

ZPLD (Zero Power PLD)
EPROM
SRAM
1/0 Ports
CounterlTimer (only in PSD5XX)
Interrupt Controller (only in PSD5XX)

The key to reducing the power used by the PSD4XX and PSD5XX is to reduce the power
used by each individual module. There are three groups of power consuming functions that
can work independently of each other and they are:

o

o
o

ZPLD
EPROM, SRAM and 110 Ports
CounterlTimer and Interrupt Logic

For example, the ZPLD could be operating as a state machine while one of the MCU
peripherals (EPROM, SRAM, 1/0 Ports) is being accessed by the MCU and the
Counterrnmer is operating in the PWM mode. Obviously in this operation all modules
operate and consume power. To derive the equations for power consumption it is
necessary to understand the operating modes of each of the PSD modules and how to
control them using the two Power Management Mode Registers (PMMRO and PMMR1).

3-145

PSD4XX/5XX - Application Nots 030

Power
Management
Mode
Registers

The Power Management Mode Registers enable the user to have in-system control of the
power consumption of each PSD module.

PSD4XX Power Management Mode Register 0 (PMMRO)
Bit 7

Bit6

BitS

Bit 4

Bit3

Bit 2

Bit 1

BitO

*

ZPLD
RCLK

ZPLD
ACLK

ZPLD
Turbo

EPROM
CMiser

APD
Enable

ALE PD
Polarity

*

1 = OFF

1 =OFF

1 = OFF

1 = OFF

1 =ON

1 =ON

1 = HIGH

1 =OFF

PSD5XX Power Management Mode Register 0 (PMMRO)
Bit 7

Bit6

BitS

Bit 4

Bit3

Bit 2

Bit 1

BitO

TMR
CLK

ZPLD
RCLK

ZPLD
ACLK

ZPLD
Turbo

EPROM
CMiser

APD
Enable

ALE PD
Polarity

*

1 = OFF

1 =OFF

1 = OFF

1 =OFF

1 =ON

1 =ON

1 = HIGH

1 =OFF

Bit 0 - * = Should be set to High (1) to operate the APD.
Bit 1 - 0 = ALE Power Down (PD) Polarity Low.
1 = ALE Power Down (PD) Polarity High.
Bit 2 - 0 = Automatic Power Down (APD) Disable.
1 = Automatic Power Down (APD) Enable.
Bit 3 - 0 = EPROM/SRAM CMiser is OFF. (See EPROM/SRAM section for explanation)
1 = EPROM/SRAM CMiser is ON. (See EPROM/SRAM section for explanation)
Bit 4 - 0 = ZPLD Turbo is ON. ZPLD is always ON.
1 = ZPLD Turbo is OFF. ZPLD will Power Down when inputs are not changing.
Bit 5 - 0 = ZPLD Clock Input into the Array is connected. Every Clock change will
Power Up the ZPLD when the Turbo bit is OFF.
1 = ZPLD Clock Input into the Array is disconnected.
Bit 6 - 0 = ZPLD Clock Input into the MacroCell registers is connected to the direct
Clock input.
1 = ZPLD Clock Input into the MacroCell registers is disconnected from the direct
Clock input.
Bit 7 - * = In the PSD4XX should be set to High (1).
= In the PSD5XX Clock Input is connected to the Timer.
1 = In the PSD5XX Clock Input is disconnected from the Timer.

o

-3--1-46-------------------------------~~~---------------------------------

PSD4XX/5XX - ApplicatIon Not. 030

Power
Management
Mode
Registers

PS04XX/5XX Power Management Mode Register 1 (PMMR1)
Bit 7

Bit 6

BitS

Bit 4

Bit3

Bit 2

Bit 1

Bit 0

*

*

*

*

*

*

Sleep
Mode

APD
CLK

1 = ON

1 = CLKIN

(Cont.)

NOTE: *

= Reserved for future use, should be set to zero.

Bit 0 - 0

= Automatic Power Down Unit Clock is connected to Port E7 (PE7) alternate
function input.

1
Bit 1 - 0
1

ZPLD

=Automatic Power Down Unit Clock is connected to the PSD Clock input.
= Sleep Mode Disabled.
= Sleep Mode Enabled.

The Zero Power PLD (ZPLD) has two modes of operation:

o
o

Non-Turbo
Turbo

These modes are in-system user programmable on the fly by configuring the ZPLD Turbo
bit (bit 4) in the PMMRO. The difference between the two modes is shown in Figure 1 for
PSD5XXB1 (the PSD4XXA 1 and PSD4XXA2 power figures are in their respective data
sheets). When the ZPLD Turbo bit is OFF (Logic 1), the ZPLD will be in power down if no
inputs are changing for a time of 66 ns. When one or more inputs change the ZPLD
automatically powers up and generates and latches the new outputs. It will retain the output
values as long as the inputs do not change. This is also true in power down and sleep
mode. The inputs that cause the ZPLD to power up are described in Table 1. It is important
to note that those inputs affect the ZPLD only when they are used as inputs to the ZPLD.
In the non-turbo mode there is an additional delay of iOns for some timing parameters
(tpD' tRPD' tEA, tER' tARP' ts, tSA' teOA)· It is important to note that if inputs are changing
at a higher frequency than 15 MHz there is no need to add 10 ns to those timing
parameters. Above 15 MHz the ZPLD will stay powered up all the time independent of the
mode of operation.
The power down specification for the ZPLD is shown in Table 2 under the ZPLD only
section (40 IJA). As the frequency of the inputs to the ZPLD increases, the ICC drain also
increases. For the same frequency the power consumption is proportional to the
percentage of product terms used in the ZPLD in that application. For example, if an
application uses a PSD5XX that has a 140 product term ZPLD but only 35 product terms
participate in generating the user defined equations (the other 105 product terms are
automatically turned off by the PSDsoft) then the 25% (35/140) product term graph should
be used to calculate the ICC consumption. At 10 MHz the ICC equals 29 mAo

-------------------------------------~~~------------------------------------3-147

PSD4XX/5XX - Application Note 030

ZPLD

Figure 1. PS05XXB1 1PLO Icc VB. Frequency Consumption

(Cont.)
120
100% PRODUCT TERM
100
75% PRODUCT TERM
80

50% PRODUCT TERM
25% PRODUCT TERM

60
c(

E 56
I

~40
20

4Ol'A
0

10

5

15

20

25

fZPLD-MHz

Equations Representation of the ZPLD Power Graphs:

1.

If ZPLD_TURBO Bit = OFF and fZ PLD <= 15 MHz then
ICCZPLD

2.

=

(

2 (rnAlMHz * 15 (MHz) + # PT * 0.4 (mAlPT))

If ZPLD3URBO Bit
ICC ZPLD

15

= ON orfZ PLD > 15 MHz then

= 2 (mAIM Hz)

* f ZPLD + # PT * 0.4 (mAlPT)

If the ZPLD Turbo bit is ON (Logic 0) the ZPLD will not enter standby mode and it will
always consume power even when inputs are not changing. In this mode the ICC power
usage of the ZPLD is also based on the percent of product terms being used in the
application. At 10 MHz, for the same example above, the ICC equals 34 mAo
Above 15 MHz both modes operate with the same ICC power curves. The reason is that a
non-Turbo ZPLD at frequencies below 15 MHz is capable of powering down before the next
input changes. For customers that use the ZPLD at frequencies above 15 MHz but still
have modes that require powering down the PSD4XXl5XX, the non-turbo mode should be
used. If Sleep mode is enabled (see Sleep Mode Section) and executed, the ZPLD will
enter into Sleep overriding the condition of the ZPLD Turbo bit. The ZPLD will return to the
previous mode of operation when exiting Sleep Mode.

-3--1-48-----------------------------~~~--------------------------------

PS04XX/5XX - Application Nots 030

1PLO
(Cont.)

EPROM

Table 1. PS04XX/5XX 1PLO Inputs
Function Name

1PLD Input Condition

A8-AD15

Always ZPlD Input

AO-A1

Always ZPlD Input

RD

Always ZPlD Input

WR

Always ZPlD Input

CSI

. Always ZPlD Input

RESET

Always ZPlD Input

ClKIN

Upon reset ClKIN is an input to the ZPlD array.
ClKIN can be masked from the ZPlD array by the
user, if it is not used as part of logic equation or to
reduce power in the system by setting PMMRO bit 5.

PAO- PA?

Only when used as ZPlD inputs

PSO- PS?

Only when used as ZPlD inputs

PCO- PC?

Only when used as ZPlD inputs
(Not available in PSD4XXA1)

PDO- PD?

Only when used as ZPlD inputs
(Not available in PSD4XXA1)

PEO- PE?

O...!!!y..when used as ZPlD inputs or alternate functions
(SHE, PSEN, WRH, UDS, SIZO, ALE, APD ClK)

PGRO-PGR3

Always ZPlD Input

INT2PlD

Always ZPlD Input (Only in PSD5XX)

WDOG2PlD

Always ZPlD Input (Only in PSD5XX)

ZPlD MacroCell Feedback

If ZPlD MacroCell is used as a buried feedback
(Combinatorial or Registered) accounts as a
ZPlD input.

The EPROM power consumption in the PSD is controlled by bit 3 in the PMMRO - EPROM
CMiser. Upon reset the CMiser bit is OFF. This will cause the EPROM to be ON at all times
as long as CSI is enabled (low). The reason this mode is provided is to reduce the access
time of the EPROM by 10 ns relative to the low power condition when CMiser is ON. If CSI
is disabled (high) the EPROM will be deselected and will enter standby mode (OFF)
overriding the state of the CMiser.
If CMiser is set (ON), the EPROM will enter the sta~ mode when not selected. This
condition can take place when CSI is high or when CSI is low and the EPROM is not
accessed. For example, if the MCU is accessing the SRAM, the EPROM will be deselected
and will be in low power mode.
An additional advantage of the CMiser is achieved when the PSD is configured in the by 8
mode (8-bit data bus). In this case an additional power savings is achieved in the EPROM
(and also in the SRAM) by turning off 1/2 of the array even when the EPROM is accessed
(the array is divided internally into odd and even arrays).
Power consumption for the different EPROM modes is given in Table 2 under ICC (DC)
EPROM Adder.

-----------------------------------~~~~----------------------------------3-149

PSII4XXI5XX - Application Not. 030

SRAM

The SRAM in the PSD will always be in the Standby mode when not selected.
An additional advantage of the CMiser is when the PSD is configured in the by 8 mode
(8-bit data bus). In this case an additional power saving is achieved in the SRAM by turning
off 1/2 of the array even when the SRAM is accessed (the array is divided internally to odd
and even arrays).
The SRAM also has a dedicated supply voltage VSBY that can be used to connect a battery.
When Vee becomes lower than VSBY -0.6, the PSD will automatically connect the VSBY as
a power source to the SRAM. The SRAM Standby Current (ISBY) is typically 0.5 !-lA.
The SRAM data retention voltage VDF is 2 V minimum.

Standby
Modes

There are two standby modes in the PSD4XX/5XX:

o
o

'oworOown
SI••p

Power Down Mode
Power Down mode causes all the memory blocks (EPROM, SRAM) that are connected to
the MCU to enter their low power modes. Traditionally the power down mode is controlled
by the CSI pin on peripherals and memories. In addition to the CSI pin causing power down
in the PSD4XXl5XX, there is also an Automatic Power Down Unit (APD) which will be
described later. When CSI is high or APD reaches an overflow condition the EPROM and
SRAM will power down. In addition, all the MCU interface buffers will be disabled to reduce
power consumptio..!.!:Jhe MCU interface includes signals ADIOO - 15, RD, WR, ALE
(disabled only by CSI and not by APD), PSEN, UDS, LDS and other alternate functions.
The PSD4XXl5XX non-memory internal blocks such as CounterlTimers, Interrupt
Controller, I/O Ports and ZPLD (in non-turbo mode) continue to function independently of
the power down mode. It is important however to note that if no inputs are changing these
peripherals do not consume any power.
The PSD4XXl5XX also includes an APD unit that enables the user to enter a power down
mode independent of controlling the CSI input. This feature eliminates the need for external
logic (decoders and latches) to power down the PSD. The APD unit concept is based on
tracking the activity on the ALE pin. If the APD unit is enabled and ALE is not active, the
4-bit APD counter starts counting and will overflow after 15 clocks, generating a PD
signal powering down the PSD. If sleep mode is enabled, then the PD signal will also
activate the sleep mode. Immediately after ALE starts pulsing the PSD will exit the power
down or sleep mode.

--------------------------_________
f_~_._~_~----------------------------------3-150

PSD4XX/5XX - Application Not. 030

Standby

Figure 2. PSD4XX/5XX Automatic Power Down Unit (APD) Block Diagram

Modes
(Cont.)
SLEEP-ENABLE
PMMR1 -BIT 1

APDENABLE
PMMRO-BIT2
ALE PO POLARITY
PMMRO-BIT1
ALE

TO OTHER
CIRCUITS
SLEEP
MODE

APD
CLEAR
LOGIC

Z

RESET
APDCLK
POWER
DOWN
MODE

CLKIN
CSI

EPROM
SELECT

P

SRAM
SELECT

L

VO

0

SELECl

APDCLK
PMMR1-BITO

Power Down Mode (Cont.)
The operation of the APD is controlled by the PMMR (see Figure 3). PMMR1 bit 0 selects
the source of the APD counter clock. After reset the APD counter clock is connected
to the ClKIN pin of the PSD. In order to guarantee that the APD will not overflow there
should be less than 15 APD clocks between two ALE pulses. If the ClKIN frequency is not
adequate, then a different clock can be connected to PE7 which is used as an Alternate
Function In - APD ClK.
The next step is to select the ALE power down polarity. Usually, MCUs entering power
down will freeze their ALE at logic high or low. By programming bit 1 of PMMRO the power
down polarity can be defined for the APD. If the APD detects that the ALE is in the power
down polarity for 15 APD counter clocks, the PSD will enter a power down mode. To enable
the APD, operation bit 2 in the PMMRO should be set high.

-----------------------------------~~~----------------------------------3·151

1'SD4XX/6XX - Appl/Clltlon Not. 030

Standby
Modes

Figure 3. AutDmatic PDwer DDwn Unit (APD) FIDW Chart

(Cont.)

RESET

CS="1

11

SET APD CLK IN PMMR1 BIT 0

SET ALE PD POLARITY
IN PMMRO BIT 1

YES

SET SLEEP MODE IN PMMR1 BIT 1

SET ENABLE APD IN PMMRO BIT 2
SET PMMRO BIT 0

SET ENABLE APD IN PMMRO BIT 2
SET PMMRO BIT 0

DISABLE CLOCKS
ZPLD ACLK, ZPLD RCLK, TMR ZPLD*

DISABLE CLOCKS
ZPLD ACLK, ZPLD RCLK, TMR ZPLD*

ALE IDLE AND
15 APD CLOCKS
PSD IN POWER DOWN MODE

ALE IDLE AND
15 APD CLOCKS
PSD IN SLEEP MODE

*TMR ZPLD is only on PSD5XX.

-~-'-52-----------------------------~Jr"'Ar--------------------------------

PSD4XX/5XX - Application Nottl 030

Standby
Modes
(CDnt.)

Sleep Mode
Sleep Mode provides capability to reduce the power consumption of the PSD4XXl5XX
to 5 lolA. In addition to the Power Down mode state: in Sleep Mode also all reference
voltages are turned off.
The Sleep Mode is enabled by executing the same operations required for automatic power
down. In addition PMMR1 bit 1 (Sleep Mode) should be set to high. When the APD counter
overflows the PSD will enter Sleep Mode.
Two conditions can cause the PSD to exit the Sleep Mode: either the ALE starts pulsing or
the CSI pin changes its state from high to low. The PSD access time from Sleep Mode is
specified by the tLVDVl parameter. In the Sleep Mode the ZPlD still monitors the inputs and
responds to them with a delay time of tLVDV2. See Table 2 for a summary of timing during
Power Down and Sleep Mode.

Input
Clock

The PSD4XXl5XX clock input (ClKIN) is used as a source for driving the following
modules:

o
o
o
o

ZPLD Array Clock Input
ZPLD MacroCell Clock Flip-Flop
APD Counter Clock
CounterlTimers Clock

During power down or if any of the modules are not being used the clock to these modules
should be disabled. To reduce AC power consumption, it is especially important to disable
the clock input to the ZPlD array if it is not used as part of a logic equation.
The ZPlD Array Clock can be disabled by setting PMMRO bit 5 (ZPlD AClK). The ZPlD
MacroCell Clock Input can be disabled by setting PMMRO bit 6 (ZPlD RClK). The Timer
Clock can be disabled by setting PMMRO bit 7 (TMR ClK). The APD Counter Clock will be
disabled automatically if Power Down or Sleep Mode is entered through the APD unit.
The input buffer of the ClKIN input will be disabled if bits 5 - 7 PMMRO are set and the
APD has overflowed.
The Countermmers can operate in Sleep Mode if the TMR ClK bit is low, but the power
consumption will be based on the frequency of operation (ClKIN frequency).

Table 2. Summary of PSD4XX/5XX Tlmln, and Standby Current During Power
Down and Sleep Modes
PLD
Propagation
Delay

PLD
Recovery
TIme
To Normal
Dperation

Access
Time

Access
Recovery
Timll
To Normal
Access

Typical
Standby
Cu"ent
Consumed

Power
Down

Normal tpD
(Note 1)

0

No Access

t LVDV

40 lolA
(Note 4)

Sleep

tLVDV2
(Note 2)

tLVDV3
(Note 3)

No Access

tLVDVl

5 lolA
(Note 5)

NOTES 1. Power Down does not affect the operation of the ZPLD. The ZPLD operation in this mode is based
only on the ZPLD_Turbo Bit.
2. In Sleep Mode any input to the ZPLD will have a propagation delay of tLVDV2.
3. PLD recovery time to normal operation after exiting Sleep Mode. An input to the ZPLD during the
transition will have a propagation delay time of tLVDV3.
4. Typical current consumption assuming all clocks are disabled and ZPLD Is in non-turbo mode.
5. Typical current consumption assuming all clocks are disabled.

--------------_____________________

,~Ar~~

'e!!l'l!!T68

___________________________________
3-153

flSD4XX/5XX - Application lIot. 03D

PSD4XX/5XX

To calculate the PSD4XX15XX power consumption the following assumptions are made:

Consumption
Equations

o In Sleep Mode none of the internal blocks are operating.
o The ZPLD can operate at times when the MCU is idle. Operating frequency of the
ZPLD is based on the highest frequency input signal connected to it.
o The total power consumption is based on the percentage of PSD operation in each

Powe,

mode of operation.
The PSD4XXl5XX power consumption equation is given by the following:
[1]ICCTOTAL

ISBSLEEP + ICCZPLD + ICCMCU_ACCESS + ICCTIMER
ISBpD + ICCEPROM + ICCSRAM + ICCOTHER

NOTATION:

o
o
o
o
o
o
o
o

ISBSLEEP
ICCZPLD

-

Standby current in sleep mode

-

ICC current when ZPLD is operating

ICCMCU~CCESS ICCTIMER

ICC current when MCU is accessing the PSD
ICC current when Timer is operating. This current is only
AC and is based on the CLOCK in frequency.

19B

-

Standby current in power down mode

ICCEPROM

-

ICC current when EPROM is operating

ICCSRAM

-

ICC current when SRAM is operating

ICCOTHER

-

ICC current when other peripherals are being accessed
such as the internal CounterfTimers, 1/0 Ports or external
peripherals to the PSD4XXl5XX. In this case only the ZPLD is
used and the power is calculated based on the ZPLD Only
section in Table 3.

Equation [1] describes the total ICC consumed by the PSD in the system while equation [2]
is the current consumed by the PSD blocks that are accessed by the MCU. The sum of the
currents is proportional to the time that the PSD is in each mode.
Table 3 includes the power specifications required to calculate the PSD4XX or PSD5XX
power consumption (see data sheet for most recent ICC values). All parameters are
specified for VCC = 5V ± 10%. The standby current (ISB) is specified with the assumption
that all internal blocks are idle. The ICC (DC) is specified for 3 blocks: ZPLD, EPROM and
SRAM. If the ZPLD is active (all other modules idle) and ZPLD_Turbo bit is OFF then the
PSD will be in one of the standby modes
(based on the PMMR configuration). If ZPLD_Turbo is on, the DC power consumption has
to be calculated based on the number of product terms used. When the EPROM or
SRAM are accessed, power is added to the power consumed by the ZPLD. The AC
parameters are also specified and should be added based on the percentage of activity of
each module.

-3.-1H--------------------------~Jr~---------------------------

PSD4XX/5XX - Application Nots D3D

Table 3. PSD4XX/5XX AC/DC Powe, Consumption Pa,ametelS
Symbol

Parameter

VCC

Operating Supply Voltage

ISB

Standby Supply Power Down Mode
Current
Sleep Mode

ZPLD Only

EPROM Adder
ICC (DC)

Operating
Supply Current

SRAM Adder

ZPLD

Min

Typ

Max

Units

4.5

5

5.5

V

CSI >VCC -.3 V

40

100

IJA

CSI >VCC -.3 V

5

10

IJA

Conditions

ZPLD_TURBO = OFF,
f=O MHz

40

ZPLD_TURBO = ON,
f=O MHz

400

IJA
700

IJA/PT

CMiser= ON
and Not Selected

0

CMiser = ON and Selected
(x8 Data Mode)

10

15

rnA

CMiser = ON and Selected
(x16 Data Mode)

15

20

rnA

CMiser = OFF Selected
or Not Selected

15

20

rnA

SRAM Not Selected

0

CMiser = ON and Selected
(x8 Data Mode)

25

40

rnA

CMiser = ON and Selected
(x16 Data Mode)

30

45

rnA

IJA

IJA

ZPLD_TURBO = OFF
(See Figure 1)
ZPLD_TURBO = ON

2

rnA/MHz

EPROM or SRAM

2

rnA/MHz

TIMER

1

rnA/MHz

ICC (AC)

NOTE: See data sheet for the most recent ICC values.

--------------------------------'§§~~-------------------------------~......
3·155

PSD4XX/5XX - Application Note 030

Examples

Here are three examples of power calculations for an application that has a high
percentage of tim'e in Sleep mode. It is important to note the measured ICC in the system
could be lower because the parameters provided in Table 3 are conservative. Following is
the PSD5XX configuration in the system used to calculate those examples:
Data Bus Width

8-Bit

PSD MCU Access Frequency

2 MHz (ALE Frequency)

% of Time in Sleep Mode

90%

% of Time MCU Access the PSD

10%

% of MCU Access in PO

30%

% of MCU Access to EPROM
% of MCU Access to SRAM
% of MCU Access to Other

50%
10%
10%

% of Time ZPLD Operating

10%

ZPLD Operational Frequency

12 MHz

ZPLD Product Terms Active

40

= (40/140)* 100=28%

Table 4 shows calculation of the power consumption assuming CMiser = ON and
ZPLD_Turbo = OFF,
Table 5 shows calculation of the power consumption assuming CMiser = OFF and
ZPLD_Turbo = OFF.
Table 6 shows calculation of the power consumption assuming CMiser = ON and
ZPLD_Turbo = ON.

~3--15~6~--------------------------~~~-------------------------------

s-

-I
i

Table 4. eMiser =O.,ZPLD_ Turbo =OFF
Mllde

%

ICC (DC)

ICC (DC)

ICC (DC)

ICC (AC)

ICC (AC)

ICC (AC)

ICC

DIS

Equatillns

Tlltal

DIS

Equatillns

Tlltal

(DC + AC}

SIJA

.9*SIJA

4.SIJA

0

0

0

4.SIJA

IS8 (Sleep)

~'-iii

Sleep

90%

MCU_Access

10%

PO

30%

40IJA

.1*.3*40IJA

1.21JA

0

0

0

1.21JA

EPROM

SO%

10mA

.1 *.S*10 mA

.SmA

2mAlMHz

.1 *.S *2 mAIMHz *2 MHz

.2mA

0.7mA

SRAM

10%

2SmA

.1 *.1*2S mA

.2SmA

2mAIMHz

.1 *.1*2 mAIMHz*2 MHz

.04mA

0.39mA

Other

10%

0

0

.1*.1*1 mAIM Hz *2 MHz

.02mA

0.12 mA

10%

0

0

.1 *36mA

3.6mA

3.6mA

3.86mA

4.63mA

1 mAlMHz
(Figure 1)

ZPLD

TOTAL

0
.7SmA

36mA

The ZPLD does not consume DC power and the EPROM consumes power only when selected.

~

I
~
I

t

I

ct'

~

I:=
til

I

I=-I~2

c:o
....
g:

1;
I

t::::
fit
;::
8

=

Table 5. CMiser OFF,ZPLD_ Turbo = OFF
Mode

%

'ee(DC}
DIS

1=

'ee(DC}
Equations

'ee(DC}

.9*5I1A

lit

Tota'

'ee(AC}
DIS

'ee(AC}
Equations

'ee(AC}
Total

'ee
(DC + AC}

4.511A

0

0

0

4.511A

ISB (Sleep)
Sleep

90%

MCU_Access

10%

511A

Ie"

PD

30%

4Ol1A

.1*.3* 4O I1A

1.211A

0

0

0

1.211A

-'III~'
18:

EPROM

50%

15mA

.1 *.5*15 mA

.75mA

2mNMHz

.1 *.5*2 mNMHz*2 MHz

.2mA

0.95mA

SRAM

10%

45mA

.1 *.1*45 mA

.45mA

2mNMHz

.1 *.1*2 mNMHz*2 MHz

.04mA

0.49 rnA

Other

10%

15mA

.1*.1*15mA

.15mA

1 mNMHz

.1*.1*1 mNMHz*2MHz

.02 rnA

0.17 mA

10%

0

0

0

.1 *36mA

3.6mA

3.6mA

3.S6rnA

5.21 rnA

(Figure 1)
ZPLD
TOTAL

36mA

1.35 rnA

The ZPLD does not consume DC power. The EPROM is on when the PSD is not in PD and the by
8 configuration does not provide the advantage of turning off 112 of the arrays in the SRAM and
EPROM. This is the reason that the EPROM, SRAM and other power consumption increases.

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -... ..... _ - - _ ... __ .. - - - - - - - - - - - - _

---

--

-----

- - - - _.. _ - - - - -

I

.S'
i

=

Table 6. CMIse, OFF, ZI'LD_ Turbo =011
Mode

%

ICC (DC)
Equations

ICC (DC)
Tlllal

ICC (AC)

DIS

ICC (AC)
Equations

ICC (AC)
Tlltal

Icc
(DC + AC}

5IJA

.9*5IJA

4.51JA

0

0

0

4.51JA

ICC (DC)

DIS
ISB (Sleep)

Ii
~

Sleep

90%

MCU~ccess

10%

PO

30%

40IJA

.1*.3* 4O IJA

1.21JA

0

0

0

1.21JA

EPROM

50%

15mA

.1*.5*15mA

.75mA

2mAIMHz

.1 *.5*2 mAIMHz*2 MHz

.2mA

0.95mA

SRAM

10%

45 rnA

.1*.1*45 mA

.45 rnA

2 mAIMHz

.1 *.1*2 mAIM Hz *2 MHz

.04mA

0.49mA

Other

10%

15mA

.1*.1*15 rnA

.15mA

1 rnAIMHz

.1 *.1*1 mAIMHz*2 MHz

.02mA

O.17mA

10%

.4mAlPT

.1 *.4*40 PT

1.6 rnA

.1 *40 rnA

4mA

5.6mA

4.26mA

7.21 mA

I

(Figure 1)
ZPLO
TOTAL

40 rnA

2.9SmA

The ZPLO is on 10% of the time also when inputs are not changing.

I

~
I

t;::
::

;t

~

5

=
If

If

I

PSD4XX/5XX - Application Note 030

Conclusion

The PSD4XXl5XX provides an extremely low power programmable solution to any system.
The capability of the user to configure the power consumption in-system using the power
management registers enables speed/power optimization. If the designer uses all of the
power saving features in the PSD, the result will be a lower power consumption than that of
any alternative.

-3--1~6~0---------------------------------~~~------------------------------------

Programmable Peripheral
Application Note 031
PSD4XX/5XX Design Tutorial

Introduction

This tutorial takes you step by step through the development cycle of a PSD4XXl5XX
based design, from design entry to programming the device. A simple design example is
used to demonstrate how some of the key functions in the PSD4XXl5XX are utilized.
At the end of this chapter, the following materials are included:

o
o

o

Files generated during the design cycle
Files generated for applications with various bus types
Chip architecture overview

The following information is covered in the tutorial:

o
o
o

DeSign
Example

Design Example
PSDsoft Development Tools
Using the Design Example

A typical yet simple design is used as an example to illustrate the development cycle.
This design example can be a part of a larger system where it communicates to other
peripherals or to a host through I/O ports. Although a PSD5XX is selected for the design,
this tutorial is applicable to both PSD4XX and PSD5XX based designs.
The PSD5XX family includes the following three PLDs (Programmable Logic Devices):

o

GPLD (General Purpose PLD)

o

DPLD (Decoding PLD)

o

PPLD (Peripheral PLD)

Functional Specifications
The main functional specifications of this deSign are shown in Table 1.

Table 1. Functional Specification
Processor

16 MHz microcontroller with 16-bit multiplexed address/data bus;
non-multiplexed address A 16 - A19. With RD, WR, ALE and BHE
control signals.

Memory

128KB EPROM (64K x 16), 2KB SRAM (1 K x 16), with paging
support.

CounterlTimers

Event Counter, Watchdog Timer.

Loadable Down
Counter

PLD to implement 5-bit down counter.

I/O Ports

1. One 6-bit output port.
2. One 4-bit input port.

Address Decoder

PLD generates all chip select signals

3-161

PSD4XX/5XX DtlSlgn Tutorial - Application Not. 031

Design
Example

Functional Specifications (CDnt.)
The system memory map is shown in Table 2. The EPROM/code memory consists of three
32KB blocks, where two of the blocks share the same address space (0-07FFF) and are in
different memory pages.
Figure 1 is the functional block diagram of the tutorial design. PLDs are used wherever
possible to reduce board space. Power consumption is also a major concern of this design.

Table 2. System Memory Map
Dell;ce

Memory Space

Memory'a,e

EPROM, Block 0

00000 - 07FFF

Page 0

EPROM, Block 1

00000 - 07FFF

Page 1

EPROM, Block 2

48000 - 4FFFF

All Pages

SRAM

08000 - 087FF

All Pages

I/O Devices

OCOOO - OCFFF

All Pages

Figure 1. Tutorial Design Example Block Diagram
AO-A15

~TCH~------------------~-------r-

CS
ADO-AD15
A16-A19

PLD

MICROCONTROLLER

TIMER
WATCHDOG
AND
_EV_E_N_T[_1:_31-+...~ COUNTER

CNTEN

~~----------------------

3-162

DOWN
CNT4
COUNTER

EPROM
128KB
64KX 16

SRAM
2KB
1KX16

OUTPUTI-__~
PORT

INPUT
PORT

fooIIIl--

_____ "IAF~_______________________________
'Ii!Hii. i6

1'SD4XX/5XX o../gn lWtltlal - Appl/at/tln.tItII 031

Design

FuncUonalPanHlon

Exampl.

With the tutorial design defined, we can investigate the block diagram to see how much of
the logic can be implemented in the PSD5XX. Some of the functions, such as the Event
Counter, are available in the microcontroller but might require additional discrete logic to
support specific applications. This imposes no problem in the PSD5XX because the
Peripheral PLD (PPLD) can be programmed to implement any logic function.
The partitioning of the logic between the PSD5XX and the rest of the design example can
be viewed as a top-level fitting process. First, we must go through the design functional
specifications and block diagram to identify functions that can be implemented in the
PSD5XX. The PSDsoft Development Tool performs the final fitting process.
From Table 3, it is obvious that the PSD5XX is more than able to meet all the required
functional specifications of the design example.
A microcontroller running at 16MHZ has a Tavdv (address valid to data valid time) of 138
ns. In order for the processor to run with zero wait states, it requires a PSD5XX-12 (120 ns
part), which has sufficient speed to meet the Tavdv requirement.

Table 3. FuncUonal PanHlon
Systetn Funell••, BI.ek

Mlltehin, PSD5XX
Funell.IIII' BI.et.

Processor

16-bit mUJ!!l?lexed address/data
bus with RD, WR

Bus Interface accepts processor
bus. No glue logic required.

Memory

128KB EPROM with memory
paging support and 2KB SRAM

Meets memory access time
requirement; provides x16
configuration. A page register
provides paging support.

Timers

Event Counter, Watchdog Timer

Event Counter: Use CTU 0
Watchdog: Use CTU 2

Loadable Down
Counter

PLD: State machine to
implement down counter

Use GPLD to implement state
machine, Port B used as 1/0

UO Ports

1. One 6-bit output port
2. One 4-bit input port

1. PortC or 0
2. PortC or 0

----------------------------~~Ar-------------------------3--1--~

PSD4XX/5XX Design Tutorial - Application Note 031

Design
Example

Functional Blocks
The PSD5XX provides multiple system-level functional blocks and allows you to define and
configure the blocks to meet the design specifications. There are three main blocks that you
need to define and configure the PSD5XX.

o Bus Interface
o lero Power PLD (ZPLD) Block
o I!DPorts
Bus Interface - The PSD5XX Bus Interface allows communication to a microcontroller
with no glue logic.

IPLD Block -

The DPLD defines the decoding function of the DPLD.
The decoding function defines the memory address map and generates
chip selects to internal PSD blocks, including the EPROM, SRAM,
and I/O ports.
The GPLD defines the operation of the state machines and
general-purpose logic.
The PPLD defines the CounterlTimer and Interrupt Controller
control conditions.

//OPorts -

PSDsoft
Development
Tools

The I/O ports assign the functions of the forty I/O pins, including the
MCU I/O function, ZPLD 110 function, CounterlTimer I/O function
and other I/O functions.

The PSD5XX functional blocks just described are supported by PSDsoft, an integrated
system development software tool from WSI, which runs on a PC in the Microsoft
Windows® environment. The PSDsoft tool consists of the following major modules:

o
o

PSDabBl

o

PSDcompller

o

PSDs/mulator

o

PSDprogrammer

PSDconfigurat/on

PSDabel
PSDabel is the WSI Windows version of the Data I/O ABEL design software. The .abl file,
which defines the logic functions of the ZPLDs, can be compiled, optimized, and simulated
in PSDabel. The PSDabel output is the .tt2 file, which is the optimized PLA file.

PSDconfiguration
The PSDconfiguration software tool allows you to specify the PSD5XX bus interface type
and I/O port pin assignments. The output is the .gle configuration file.

-3--1-6-4-------------------------------~~~-----------------------------------

PSD4XX/5XX Design TUtorial - Application Note 031

PSDsoft
Development
Tools
(Cont.)

PSDcompiler
The PSDcompiler software consists of two portions: the Filler and Address Translator.
The Fitter, based on .112 and .glc input files, fits the logic and 1/0 functions you have
specified into the PSD5XX.
The Address Translator performs address translation on your code (HEX) file. PSDcompiler
also generates the object output file (.obj) for the programmer. The .obj file includes on-chip
configuration data, the ZPLD fuse map, and user program codes.
The PSDcompiler also provides a decompilation function. Based on the .obj file, the
Decompiler generates ZPLD and EPROM fuse map files for chip-level simulation.

PSDsimulator
PSDsimulator is the WSI version of SIMUCAD PSDsilosll1 Simulation Software.
PSDsimulator provides PSD5XX chip-level simulation.

PSDprogrammer
The PSDprogrammer software is the programming interface to the WSI PSD MagicPro™
Programmer. PSDprogrammer is used for downloading, uploading, and programming the
PSD device.

PSDsoft Program Flow
Figure 2 shows the PSDsoft program flow in configuring, defining and programming the
PSD5XX. Each PSDsoft submodule is enclosed by dashed lines. The figure illustrates the
normal steps you follow in creating a design. These steps are enumerated below. The files
generated during the process are named using the project name you specify.

1. Create or open a project after entry into PSDsoft.
2. Use an editor in Windows or PSDsoft to generate the project.abl file.
3. Use PSDabel to compile and optimize the project.abl file. Perform simulation if needed.
Generate an optimized PLA file (project.tt2) for the Fitter.
4. Configure the Bus Interface in PSDconfiguration. Generate the project.glc file for the
Fitter.
5. Compile the design using PSDcompiler. Compilation consists of two steps:
Filling and Address Translation.
The Filler generates the project.fob and fuse map based on the PSDabel and
PSDconfiguration output files.
Address Translation combines the code file and the project.fob file into a project.obj file.
This .obj file includes the program code, the PSD5XX fuse map, and the configuration
bits.
6. Verify the design using PSDsimulator. Chip level simulation is based on the stimulus file
(project.stl) and fusemap files from the Fitter.
7. Download the project.obj file to the PSD MagicPro programmer and use the PSDpro
software to program the chip. A compatible third-party EPROM programmer can also be
used.
For a description of all the files generated by PSDsoft, please refer to the appendixes of the
PSDsoft manual.

-------------------------------~~~~----------------------------3--1--65

PSD4XX/5XX Design Morlat - Application Not, 031

Figure 2. PSD5XX PSDsoft Program Flow

--------------------------------------,,
,

FROM MCU COMPILER

PSDsiloslll
WINDOW
MENU

.CMM· CURRENT STATE OF SIMULATOR
.SIM • SIMULATION HISTORY
.ERR • ERROR MESSAGES

PSDsimulator
-----------------------------------------------------~

PSD PROGRAMMING ALGORITHMS

PSD

Device

PSDprogrammer

TO THIRD PARTY PROGRAMMERS

~~~-----------------------------------~~i1~----------------------------------------3·166

PSD4XX/5XX DBllgn Tutllrlal - Appilcatilln NIts 031

Using the
Design
Example

This section uses the tutorial design example to illustrate the steps to invoke the software
and create a design of your own. The files required, which are generated for the tutorial
design, can be found in the \TUTORIAL directory after the PSDsoft software is installed. If
changes are made during this tutorial, the corresponding file in the TUTORIAL directory will
be changed as well. If you are unsure as to the status of the tutorial files when you are
finished going through the tutorial design example, you may reinstall the software to restore
the files to their original state.
To enter the PSDsoft program
1. Install the PSDsoft software.
The WSI-PSDsoft window with four distinct icons appears.

I

PSDsoft

I,

PSDsilosli1

PSDsda

ReadMe

2. Double-click the ReadMe icon.
Important information you should know about PSDsoft is presented. Read this information
before proceeding. A list of the PSDcontrol error messages is included in the ReadMe file.
The PSDsiloslll™ icon invokes the PSDsilosl1i simulator for chip-level simulation. The
PSDsda (PSDsiloslll Data Analyzer) icon, which is also available under PSDsiloslll, allows
you to display multiple simulation results.

rIL;~
--------------------------------==
..·-----------------------------3--1-6-7

PSD4XX/5XX DtlSlgn Tutorial - Application Nots 031

Using the
Design

Example
(Cont.)

Managing the ProJect
Each new project may have its own working directory where all the files generated by
PSDsoft reside. Once you specify the new project name, the PSDsoft Project Management
passes the working directory and pertinent information to other functional modules.
In the following sections, key windows are displayed to explain the step-by-step operation
of PSDsoft.
1. Double-click the PSDsoft icon in the WSI-PSDsoft window.
The Main PSDsoft window is displayed.

2. Pull down the Project menu and select New.
The project window appears.

___________________________

~~E----------------------------

3-168

-

--

PS04XX/5XX Osslgn Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

Managing the Project (Cont.)
3. Enter the name of the directory in which you want the new project to reside in the
Directory window.
4. Enter the project name in the Project Name window. The examples in this tutorial are
based on the name "tutor."
The project name you enter will be used as the file name in all the files generated,
including the .abl file.
5. Specify the device family and part name (PSD503B1 for Design Tutorial).
6. Click OK after all the parameters are entered to your satisfaction.
PSDsoft creates a new project named TUTOR, generates a tutor.ini file for the TUTOR
project, and presents the PSDsoft Menu, which now reflects the name of the project.

--------------------------------~~~-----------------------------3-.1-6-9

PS04XX/5XX OflSlgn JUto,'al - Application lIot. 031

Using the
Design
Example
(Cont.)

Entering the Design Source File
PSDabel is the design entry tool used to define the ZPLD and some 1/0 constructs.
Because the tutorial design example has already been created for you, you do not need to
create a design from scratch. However, if you were creating a new design, you would pull
down the PSDsoft menu and choose PSD ABEL Design Entry. A window would open to
allow you to enter the design. The material that follows is presented for you to understand
the components of a source file. Following the source file explanation, we will continue by
compiling the tutorial source file.
PSDabel is WSl's version of Data 1I0's ABEL-HDL Design Software, and includes all the
ABEL functions required to compile, optimize, and simulate the PLD source file written in
ABEL Hardware Description Language (PSDabel-HDL).
The logic functions of the PSD5XX's ZPLDs can be defined entirely by PSDabel-HDL.
PSDabel takes the PLD input source file and generates an output file (.tt2) after compilation
and optimization. A source file consists of one or more modules, and each module has its
own beginning and end. The source file that describes the PSD5XX's ZPLDs can consist of
one large module, or it can be implemented in three modules, one each for the DPLD,
GPLD, and PPLD.
A module usually consists of five sections:

1. Header. A header consists of a module name andlor title. The module name must be the
same as the file name of the .abl file.
2. Declarations. Declarations define Signals, constants, and macros.
No device declaration is required.
3. Logic Description. The logic description defines the PLD functions in terms of
equations, truth tables, and state diagrams.
4. TesCVectors. The TesCVectors are used in logic simulation
(only in the ABEL Simulator).
5. End. A module must include the End statement.

'.6JJ!!1l/¥

-3--1~70-------------------------------~~afjr----------------------------------

PSD4XX/5XX DBslgn Tutorial - Application NotB 031

Using the
Design
Example

Entering the Design Source File (Cont.)
The listing of a typical source file is shown below. Source statements end with semicolons;
comments begin with a double quotation mark. Keywords are indicated in bold letters.

(Cont.)
module

DPLD

title

'Decoding equations for internal PSD5XX devices'

Declarations
"Input Signals, external or internal PSD5XX signals
pin; "address lines,
pin; "using reserved names
pin; "page register embedded inputs

a18,a17,a16,a15,a14,a13
a12,a11 ,a10,a9,a8,a1 ,aO
pgr3,pgr2,pgr1,pgrO

"Output signals, internal PSD5XX DPLD output signals.
csiop,rsO,esO,es1,es2,es3 node; "using reserved names.
"definitions

x

.x.;

page

[pgr3,pgr2,pgr1,pgrO];

Address = [a18,a17,a16,a15,a14,a13,a12,a11,
a 10,a9,a8,X,X,X,X,X,X,a1 ,aO];
Equations
csiop = (Address >= I\hOeOOO) &
(Address <= I\h087FF) &
rsO
esO
(Address <= I\h07FFF) &
(Address <= I\h07FFF) &
es1
es2
(Address <= I\h4FFFF) &
TesLVectors
([ page, Address]
[ 0 , I\h07020]
I\h07020]
[
[ 0 , I\h4AOOO]
[ 0 , I\h50000]

>
>
>
>
>

[esO,
[1 ,
[0
[0
[0 ,

es1,
0 ,
1 ,
0 ,
0 ,

(Address
(Address
(page ==
(page ==
(Address

<= I\hOeOFF);
>= I\h08000);
0);
1 );
>= I\h48000);

es2])
0];
0];
1 ];
0];

End DPLD

-----------------------------------r====----------------------------------===E
3.171

PSD4XX/5XX OllSlgn Tutorial - Appllt:Btlon Nota 031

Using the
Design
Example
(Cont.)

Entering the Design Source File (Cont.)
Writing tha Soun:a (.abl) Fila
Keep the following things in mind when you write the .abl file:

a
a
a

a
a

Nodss and Pins
Embeddad .odss
RIISB(Wld Namss
Pin Asslgnmants
'od. Asslgnm.nts

.odss and Pins
In PSDabel-HDL, the keyword PIN refers to input and output signals that are available on
the device's pins. For the PSD5XX family, signals such as RD, WR, and A8-A15 are
defined as pin inputs to the ZPLD. The NODE keyword refers to signals that are buried or
embedded inside the device. However, the Fitter does have the option to assign a NODE to
a pin. The ZPLDs in the PSD5XX are embedded inside the chip and some of its input and
output signals are actually internal nodes. For example, the outputs from the Page Register
are internal nodes.
Embeddad Nodas
Not all state outputs of a state machine need to be routed to an output pin. For example, in
a state machine (8-bit counter) that takes up all eight PA macrocells (macrocells connected
to Port A), only the MSB of the counter is needed for external logic. In this case, pin PAO is
fitted to provide the MSB, while PA 1-PA7 are available for other Port functions such as 1/0
ports for the microcontroller.
RlISBmd Namss
There are 61 input signals to each of the ZPLDs. The number of ZPLD outputs are variable
and depend on user application. Some of these signals have reserved names (dedicated
names), as they represent a hardwired function. The reserved names are required by the
Fitter (PSDcompiler), which has to recognize the functions of these signals in order to
perform the proper fitting and generate the correct fusemap. For example, the reserved
names for the address lines are AO-A23. Wherever the address lines are involved, you must
use the reserved names AO-A23 or aliases of these signals.
Some of the pins on the PSD5XX have multiple functions. Pin 41 is the "read" pin with the
reserved name "RD". The RD pin can also be configured to accept other bus control signals
(E, DS, or LDS/). If you prefer to use the name "DSr (for 68332-based design) instead of
RD, the .abl file should contain the declaration:
ds pin 41;
The ZPLD input signals are listed in Table 4 with their corresponding reserved names.
Table 5 shows the output signals of the ZPLD that have a reserved name.

iFils #5
~3~-1~72~---------------------------~"'--------------------------------

1'SD4XX/SXX IhIslgn 'Mollal - Application Mottl 031

Using the
Design
Example

Table 4. ZPLD Input Signals
Signal Source

SignalsIReselred Names

(Cont.)

paO - pa7 (a16 - a23)1

PortA

pbO-pb7

Port B

pcO - pc7 (a16 - a23)2

Port C

pdO - pd7 (a16 - a23)3

Port 0

peO-pe7

Port E

pgrO -pgr3

Page Mode Registers

wdog2pld

CounterfTimer

intr2pld

Interrupt Controller

aO - a15, aO, a1

MCU Address Bus

rdt

MCU Bus Control Signal

wrt

MCU Bus Control Signal

clkin

Input Clock

reset

Reset Input

csit

CSI Pin

timeroutO - ~

Input Clock

NOTES:

1. Port A can be assigned by the Fitter or by the user as high address line inputs to the DPLD for decoding.
2. II A16 - A23 are not used as Inputs to the DPLD, the Fitter can assign A16 - A23 to Port C or D.
3. I A16 - A23 are not used as inputs to the DPLD, the Fitter can assign A16 - A23 to Port C or D.
4. Available only II Timer Output Is selected.

Table 5. ZPLD Output Signals
Signal Source/Destlnatlon

SlgnalsIReselred Names
esO-es3

DPLDtEPROM Block Chip Selects

rsO

DPLDtSRAM Chip Select

csiop

DPLDtPSD I/O Port Chip Select

pselO - psel1

DPLDtPort Peripheral I/O

mc2tmrO - mc2tmr3

PPLDtCountermmer

pt2int4 - pt2int5

PPLDllnterrupt Controller

mc2int6 - mc2int7

PPLDllnterrupt Controller

----------------------------------~~.~----------------------------------

- - - - - - - - ------

3·173

-

-----------

--------

PSD4XX/5XX Dsslgn Tutollal - Application Not, 031

Using the
Design
Example
(Cont.)

Entering the Des/gn Source File (Cont.)
Pin Asslgnm,nts
The GPLD has a maximum of 24 macrocells. The inputs or outputs of the macrocells are
connected to Ports A, Band E. Unless you specify otherwise, the Fitter assumes all the
port pins are available for the GPLDs. If the ports are used for other functions, such as to
provide latched address out or as I/O ports for the microcontroller, you must specify in the
.abl file that these port pins are not available for fitting. For example, if Port A pins PAO-PA3
are used as latched address pins out or as MCU I/O ports, the .abl file should include the
statement:
paO, pa1, pa2, pa3 pin;

Nod' Asslgnm,nts
The macrocells of Port A, Band E all have dedicated node numbers. If you have an
embedded function and wish to assign it to a specific macrocell, you need to assign the
function (signal) to the macroceli node number. Table 6 shows the node number of the
macrocells.

Table 6. Macrocel/s Node Number
Macrocel/

Node
Number

Macrocel/

Node
Number

Macrocell

Node
Number
38

PAO

27

PBO

50

PEO

PA1

26

PB1

49

PE1

37

PA2

25

PB2

48

PE2

36

PA3

24

PB3

47

PE3

34

PA4

23

PB4

46

PE4

33
32

PAS

22

PBS

45

PES

PA6

21

PB6

44

PE6

31

PA7

20

PB7

43

PE7

30

--------------------------_______ ,JrJr~~ __________________________________
3.174

'fi!il##J!

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example

The tutor.abl Source File
The ZPLD source file for the Tutor design (tutor.abl) is shown in the listing that follows.
Source statements end with semicolons; comments begin with a double quotation mark.

(Cont.)
module tutor
title 'tutor design example ZPLD source file';
"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
a18,a17,a16 pin;
"high order address
"input for fitting
pgr3,pgr2,pgr1 ,pgrO pin;
"page register embedded inputs
bhe pin 38;
"reserving peO for bhe
elkin, reset pin 42, 40;
"using the right pin numbers,
"inames are modified.
"General inputs for fitting
event1 ,event2,event3 pin;
cntouCen pin;
load pin;
d4, d3, d2, d1, dO pin;

wdog2pld node;

"Enable down counter output
"Load and enable down counter
"Number of counts to load,
"connect to processor data bus
"watch dog output from Countermmer

-----------------------------------wrJr~jr----------------------------------3-175

PSD4XX/5XX O.'gn Tutlllial - Appllcatilln NIt, 031

Using the
Design
Example

Entering the Design SDurce File (Clint.)
Th, tutlll.abi SIIUIC' FII, (Clint.)

(Clint.)
"Output signals
csiop, rsO, esO, es1, es2 node;
"DPLD output chip selects
mc2tmrO node;

"PPLD output to Event Counter

"General outputs
wstc pin;

"down counter terminal count

cnt3, cnt2, cnt1, cntO node istype 'reg';
cnt4 pin istype 'reg';
"Cnt4-cntO implement a down counter with a parallel load.
"Only Cnt4 can drive out, cnt3-cntO are embedded in the chip.
ouU>O,out-p1,ou'-p2 pin 60,59,58;
"assign 3-bit output port to PDO-PD2
wdout pin;

"watch dog output

"DEFINITIONS
din

[d4,d3,d2,d1,dO];

cnt

[cnt4,cnt3,cnt2,cnt1,cntO];

page = [pgr3,pgr2,pgr1,pgrO];
CK

x

= .c.;

.x. ;

"Clock pulse definition
"Don't care

Address =
[a18,a17,a16,a15,a14,a13,a12,a11,a1 O,a9,a8,X,X,X,X,X,X,a1,aO];
event_in = [event3,event2,event1];

----------________________________
3-176

,JrJJAF~

i!r11i14IiI if

__________________________________

PSD4XXj5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Entering the Design Source File (Cont.)
The tutor.abl Source File (Cont.)
equations
"DPLD EQUATIONS
csiop = (Address >= I\hOCOOO) & (Address <= I\hOCOFF) ;
"256 block

= (Address <= I\hOB7FF) & (Address >= I\hOBOOO);
"2k block

rsO

esO

(Address <= I\h07FFF) & (page == 0);

es1

(Address <= I\h07FFF) & (page == 9);

"32k block only at page 0

"32k block only at page 9
(Address <= I\h4FFFF) & (Address >= I\h4BOOO);

es2

"32k block, always visible
"GPLD Equations
cn!.clk =clkin;
cn!. re

" The global clock is the counter clock

=! reset;
= !cntout_en;

" The global Reset is the counter reset

cnt4.oe

wstc = (cnUb == 0);
WHEN (load) THEN cnt

"wstc is true when the counter outputs a~e zeroes

:= din;
"Load cnt with din if load is true

ELSE WHEN (wstc) THEN cnt := 0;
"Wait for a load pulse
ELSE cnt := cnUb - 1;

"Count-down

"PPLD Equations
" PLD-driven Event Counter event inputs.
mc2tmrO

=event1

& !event2 # !eyent3;

wdout = !wdog2pld & (cnUb == 2);

-----------------------------------~~~----------------------------------3·177

I'SD4XX/5XX Design TUtorial - Application Note 031

Using the
Design
Example

Entering the Design SDurce File (Cont.}
The tutor.abl Source File (Cont.}

(Cont.}
"*****************************************************

" TEST VECTORS
11*****************************************************

tescvectors([clkin,reset,load,din]->[wstc,cnt])

[CK,1 ,X,X]->[1 ,0];
[CK,0,0,X]->[1,0];
[CK,0,1, 17]->[0, 17];
[CK,0,0,X]->[0,16];
[CK,0,0,X]->[O,15];
[CK,0,0,X]->[O,14];
[CK,0,0,X]->[0,13];
[CK,0,0,X]->[0,12];
[CK,0,0,X]->[O,11];
[CK,0,0,X]->[O,10];
[CK,0,0,X]->[0,9];
[CK,0,0,X]->[O,8];
[CK,0,0,X]->[0,7];
[CK,0,0,X]->[O,6];
[CK,0,0,X]->[0,5]i
[CK,0,0,X]->[0,4];
[CK,0,0,X]->[0,3];
[CK,0,0,X]->[O,2];
[CK,0,0,X]->[0,1];
[CK,0,0,X]->[1 ,0];
[CK,0,0,21]->[1,0];
[CK,0,1,21]->[0,21];
[CK,0,0,X]->[0,20];
[CK,0,0,X]->[0,19];
[CK,0,0,X]->[0,18];

"Reset is on, cnt reg. is at zero
"No output change, wait for a load pulse
"Load 17 to down-counter
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Count down
"Countdown
"Count down
"Count down
"Count down
"Wait-State Terminal Count is set
"Maintain same state
"Load a new value
"Count down
"Count down
"Count down

END tutor

-3--1-n-----------------------------~Jr~~--------------------------------

PS04XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Entering the Design Source File (Cont.)
Equations for the DPLD, GPLD and PPLD are included in one file. Some of the logic
implementation and signal names are described in the following paragraphs.

Down Counter (S-blt)
load
cntout_en
d[O:4]
cnt[O:4]

input, load input
input, OE/ to counter output cnt4
input, data input for loading
counter outputs

The Down Counter is implemented in the GPLD. Signals cntO-cntS are embedded internal
nodes. Only the cnt4 signal is driven out to a pin.

Elfent Counter
event[1-S]
mc2tmrO

event inputs
count enable input to Counter, function of
event[1-S]. Count if (event1&!event2 # !eventS)

The Event Counter is implemented by CounterlTimer Unit o. The output of the counter can
be read by the microcontroller.

I/DPorts
in_p[O:S]
oUCp[O:5]

input port, assign to Port C
output port, assign to Port D

Watchdog Timer
wdout

output to pin, wdout= wdog2pld

The Watchdog Timer is implemented in the CounterlTimer Unit 2. Output of timer,
wdog2pld, is routed to output pin wdout.

Checking for Errors
Now that the tutor.abl file is complete, the next step is to check the syntax of the file. If there
are no errors, the file is compiled and/or optimized to generate the tutor.tt2 file for the Fitter.
In the previous section, PSDsoft was invoked and the project Tutor was specified.
1. Pull down the PSDsoft menu and select PSDabel.
The tutor.abl file is displayed.

i'i1i1 J1:!i¥

--------------------------------~~§-----------------------------3--1-7-9

PSII4XX/5XX OBI/gn 'Morlal - Application Not, 031

Using the
Design
Example

Entering the Design SDurce File (Cont.)
ChllCklng for E""IS

(Cont.)

design example ZPLD

sou~ce

file';

"Input signals
"Add~ess

lines~

using

~ese~ued

names.

a15~a14.a13~a12~a11.a10~a9~a8~a1.a0
a18~a1?a16
pin
pg~3~pg~2~pg~1.pg~0

bhe pin 38;

clkin~

~eset

"Gene~al

pin;

pin 42. 40;

inputs

fo~

pin;
"page ~egiste~ embl "
" ~ese~uing pe0

fitting

PSDsoft automatically opens the window displaying the tutor.abl file, which already exists.
If you were creating a new design, the window would be empty and you would need to
enter a design.
2. Pull down the Compile menu and select Error Check.
If any errors are present, a window is created to display the error file, TUTOR.err.
1~~1

Error

e:\psdsoft\tlltorial\tlltor.err

~a

AHDL2PLA ABEL-HDL Processor
ABEL 4.38 Copyright 1998-1992 Data I/O Corp. All Rights Reserved
Licensed fro~ Data I/O Corp. by WSI Inc.
Hodule: ' tutor'
8832 IGeneral outputs

A

Syntax Error 1829: PIN. NODE. DEUICE. ISTYPE. HACRO. STATE. PARTITION.
GROUP. PLACE. PROPERTY. STATE-REGISTER or '-' expected
AHDL2PLA complete - 1 errors. 8 warnings. Time: 2 seconds

1:11

--------------------------______ rll~~ ________________________________
3.180

~~J!

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example

Compiling the Source File
With the tutor.abl window still displayed, pull down the Compile menu and select Compile.

(Cont.)

a15.a14.a13.a12.a11.a10.a9.a8.a1.a0 pin;
a18.a1?a16 pin ;
I
pg~3.pg~2.pg~1.pg~0

pin;
bhe pin 38;
elkin. ~eset pin 42. 40;
"Gene~al

inputs

fo~

fitting

Compile generates two PLA output files: tutor.tt1 and tutor.tt2. The tutor.tt2 file is the
optimized PLA file based on the reduction algorithm specified in the Optimize menu. A
default optimize setting is used during the tutorial.

--------------------------------------~J'~~-----------------------------------3--1-8--1

I'SIUXX/5XX '.,n Tutorl" -

Using the
Design
Example
(Cont.)

Application Not. 031

ChllDSlng Ttace Optillns IlIr fh, SlIurc, File
The Compile Menu includes items that will be used by the PSDabel simulator, which
simulates the equations generated in the tutor.tt1 file.
1. Pull down the Compile menu and select Trace Options.
The Simulate Trace Option window appears, allowing you to select the simulation output
format and other options.

2. Click Wave format.
Table format is the default option. It generates a file during simulation that produces a
waveform for each of the signals simulated (test vectors).
3. Click OK.
The PSDabel main window reappears.

--------------------------________ ,ArjfjF~ __________________________________
3-182
'liif!i!iIF •

I'SD4XX/5XX Dsslgn Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

Choosing Optimize Options for the Source File
You can choose different reduction algorithms to optimize the tutor.abl file.
1. Pull down the Optimize menu and select Options.
The Reduction Options window appears.

The default option is the Reduce by Pin, Auto Polarity reduction. This is the option that is
used for the tutorial design example. The purpose of optimization is to provide the optimal
PLA file to the Fitter.

2. Click OK.
The main PSDabel menu reappears.

!'• • 6=

-----------------------------------~~~6--------------------------------~-1-83-

PSD4XX/SXX Design Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

Simulation Within PSDabel
A presimulation capability is available within PSDabel. Simulation at this level is
device- and pin-independent. The advantage of this is that you can generate waveforms
based on the logic design or logic equations without any concern about a package for the
design.
To perform a presimulation and view the results, pull down the Compile menu from the
PSDsoft main menu and select Simulate Eqn.
The Simulate Equation progress window appears.

This window indicates that PSDabel is performing a simulation of the logic equations for the
tutorial example and generating a waveform file for viewing.

-3--1-8-4-------------------------------~~~-----------------------------------

PS04XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example

The View Menu allows you to view the following:

(Cont.)

o

Viewing Soulce File Components

o
o
o

o

Compiler Listing
Simulation Results
Compiled Equations
Optimized Equations
Errors

The Compiler Listing and Simulation Results are given here as examples of what might be
displayed.

1. Pull down the View menu to display all the items that are available for display.
The items available are shown below.

2. Choose the Compiler listing item.
The compiler listing tutor. 1st appears in a window.

8881
8882
8883
8884
8885
8886
8887
8888
8889
8818
8811
8812
8813
8814
8815
8816

·••
I

design exallIple ZPLD soul"ce file';

:"Input signals

••
•

:"Addl"ess lines ~ us ing I"esel"ued nallIes.
I

:a15~a14~a13~a12~all~a18~a9~a8~al~a8
:a18~a17~a16

I

pin

•

:pgI"3~pgI"2~pgI"1~pgI"8

Ibhe pin 38;
:clkin~ I"eset pin

:

42~

pin;

pin;
48;

I

•

-----------------------------------~~~----------------------------------====
3-185

PSIJ4XX/SXX '_gn Tutllrl., - Appllcatilln /lilt. 031

Using the
Design
Example

Viewing Source File Components (Clint.}
3. Return to the PSDabel main menu by double-clicking the close box (upper left corner) of
the tutor.lst window.

(Cont.}

4. Pull down the View menu and select Simulation Results.
A window showing the simulation results appears.

ABEL 4.32 Date: non Jun ? 1i19:11i1:1iI1i1 1993
iIe: JE:'PSDSOFT'TUTORIAL'tutop.tt2 J Uectop
design example ZPLD soupce file

c
I
k

p

e
s
e

i
n

t

I

°a
d

w

d

4

d
3

d

2

d
1

s
t
c

d
iii

L...-

U081i14
U081i15
U081i16
UIiIIiIIiI?
UIiIIiI1iI8
U081i19
U01i110
UIiIIiI11
UIiIIiI12
UIiIIiI13
UIiIIiI14

c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
c:
r"

, :'

",.,

,':

'.

Exiting PSDabel
Pull down the PSDsoft menu in the main PSDsoft window and choose Exit PSDabel.
You are now ready to configure the tutorial design.

--~------------------------------~~~---------------------------------3·186

PSD4XX15XX IIs,lgn TUtorial - Application Not. 031

Using the
Design
Example
(Cont.)

Configuring the Design
Generating the optimal PLA file is critical in the fittillg of the ZPLD and the development of
the PSD5XX. After simulating the PLA file and verifying that the logic functions are correct,
the next step is to invoke the PSDconfiguration software.
The PSD5XX has a programmable bus interface and is able to interface directly to
many microcontrollers. The PSDconfiguration software allows you to specify the bus
configuration of the PSD5XX. The tutorial design is based on a microcontroller having
a 16-bit multiplexed bus with RD, WR/, and BHE/as control signals.
To perform the design configuration
1. Pull down the PSDsoft menu in the main PSDsoft window and choose PSDconfiguration.
The PSDconfiguration main window appears.

....

----------------------------------- rt-"-

~

----------------------------------3-187

PSD4XX/SXX Design Tutorial - Application Nots 031

Using the
Design
Example

CDnflguring the Design (Cont.)
2. Pull down the Configuration menu and select Bus Interface.

(Cont.)

The Bus Interface window appears.

~3-~1~88~-----------------------------~~~----------------------------------

PSD4XX/5XX Design TIItolial - Application Note 031

Using the
Design
Example
(Cont.)

Configuring the Bus Interface
To program the Bus Interface
1. Select the data bus width (X8 or X16) and type of microcontroller bus.
MX deSignates a multiplexed microcontroller bus and NM designates non-multiplexed.
There are four combinations of bus types, as follows:
Q 16-Bit Data Bus
Multiplexed address/data bus
Q 16-Bit Data Bus

Non-multiplexed bus
Q a-Bit Data Bus

Multiplexed address/data bus
Q 8-Bit Data Bus

Non-multiplexed bus
The tutorial design uses the 16-bit, multiplexed address/data bus.
2. Click OK.
The Control Signal window for a 16-bit, multiplexed bus appears.

3. Specify your selections for the Address Latch Enable (ALE) polarity and the control
signals.
For the tutorial design example, the microcontroller bus configuration is a 16-bit
multiplexed bus, the ALE polarity is high, and the RD, WR, and BHE setting is used.

-----------------------------------~~~--------------------------------3-~1-89-

PSD4XX/5XX OllSlgn Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

Configuring the Bus Interface (Cont.)
Configuring tbs Rsst of tbs OllSlgn
Besides configuring the Bus Interface, you must program the 1/0 configuration of the
CounterlTimers and Interrupt Controller. To do this
1. Return to the main PSDconfiguration menu.
2. Pull down the Configuration menu and select Other Configuration.
The Other Configuration window appears.

3. Select the configuration for the four CounterlTimers inputs and outputs.
The PSD5XX has reserved input and output pins that are routed directly to the
CounterlTimer Units and the Interrupt Controller. PAO-PA3 and PBO·PB3 can be
assigned as output ports and PE3-PE6 as input ports for the CounterlTimers.
In the tutorial design, the input to CounterlTimer 0 cannot be assigned to pin PE3
because it consists of three signals (event[1-3]). For this reason, the CounterlTimer 0 is
not selected in the Configuration Window.
4. Select the automatic power-down configuration.
The input clock to the Automatic Power Down counter is pin PE7. If PE7 is not used,
the Fitter considers it available for fitting ZPLD functions.

EFEI. . . .E

-3--t-90----------------------------~~§-------------------------------

PS04XX/5XX DBllgn TUtorial - Application Not. 031

Using the
Design
Example
(Cont.)

Configuring the Bus InterfaclI (Cont.)
Configuring the RBSt of tbtlDBSlgn
5. Select the security bit configuration.
The security bit can be set in the Other Configuration window and is then
embedded in the tutor.obj file generated by the Address Translator. Once the security bit
is set, the EPROM or the ZPLD fusemap cannot be copied until it is erased.
6. Select the interrupt controller output configuration.
The output of the interrupt controller is pin PE2. If PE2 is not used, the Fitter considers it
available for fitting ZPLD functions.

VI.wlng tbtl DBllgn Summa"
When you are ready to conclude your configuration session
1. Pull down the Summary menu in the main PSDconfiguration menu and choose
Summary.
The Summary window appears and displays the configuration specified in the Bus
Interface and Other Configuration menus.

2. Return to the Configuration menu in the main PSDconfiguration window if you want to
change any of the PSD5XX configuration parameters.

________________________ 'rlNlIII

',I~,~------------------------

j

3.191

PSD4XX/5XX Design TUtorial - Application Note 031

Using the
Design
Example
(Cont.)

Configuring the Bus Interface (Cont.)
Viewing the Design Summary (Cont.)
3. Pull down the PSDsoft menu in the main window and choose Exit PSDconfiguration.
The Configuration Save Confirmation window appears.

~

o

Configuration Save Confirmation

Would you like to save the Configurations?

4. Click Yes to save the new configuration in the tutor.glc file.

Compiling the Design
The PSDcompiler consists of the Fitter and the Address Translator programs. The function
of the Fitter is to fit the logic functions into the ZPLD. Once this is done, pin assignments
may be made on the design schematic. The constraint of the fitting process is imposed by
the GPLD architecture and the availability of 1/0 pins on the PSD5XX.
The input files to the Fitter are as follows:

o tutor.tt2
o tutor.glc

PLA file
PSD5XX configuration file

The output files generated by the Fitter are:

o
o

tutor.fob
tutor.tt3

Fitted PLA file

o

tutor.afu

Configuration fuse file for PSDsimulator

o
o
o
o

tutor.pfu

PLD fuse file for PSDsimulator

tutor.feq

Fitter equation file using device reserved names

tutor.frp

Fitter pin assignment file

tutor.err

Fitter error file

Fusemap file in Hex format (PLD+Configuration) for Address Translator

The Address Translator combines the tutor.fob fuse map file with the EPROM codes file and
generates the tutor.obj file, which is to be downloaded to EPROM programmer for PSD5XX
programming.
Figure 3 shows the flow and input and output files of the PSDcompiler.

~3--1~92~------------------------------~~~-----------------------------------

PSD4XX/5XX Design TUtotlai - Application Not. 031

Using the
Design
Example

Figure 3. PSDcompller Program Flow
From'MCU Complier

(Cont.)

DECOMPILATION

To compile a design
1, Pull down the PSDsoft menu in the main PSDsoft window and choose PSD Compiler.
The PSD Compiler window appears.

-----------------------------------f~Ar~=----------------------------------~-.

3·193

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Compiling the Design (Cont.)
Fitting the Design
2. Pull down the Options menu and choose Fit Options.

The Fit Options window appears. The Fit Options window allows you to specify the fitting
algorithm before invoking the Fitter.

~~

3·194

_______________________________

raa~~

====

___________________________________

PSD4XX/5XX Design TUtorial - Application NDte 081

Using the
Design
Example
(Cont.)

Compiling the Design (Cont.)
Fitting the OllSlgn
3. Click one of the three fitting options given in the Fit Options window.
For the tutorial, you may choose Keep. The functions of the three Fitter options are
listed below.

Fitter Option

Description

Keep

The Fitter should maintain the pin assignment defined by the user.
The Keep option is the default.

Try

Maintain as much current pin assignment as possible.

Ignore

The Fitter is free to make any pin assignment and ignores the
user's pin assignments.

4. Go back to the PSDcompiler main menu.
5. Pull down the Compile menu and choose Fit.

___________________________________

r_~_~_~-----------------------------------

3·195

PSD4XXj5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Compiling the Design (Cont.)
Fitting the Design
The Fitter window appears, indicating a successful or unsuccessful fitting process.
Fitting must be completed successfully before invoking the Address Translator.

PSDCompiler
Successful Fitting Process!

If the fitting is not successful, you will have to examine the tutor.feq file to see which logic
function causes the fitting problem and modify the tutor.abl file accordingly.
Recompile and optimize the modified tutor.abl file again, if necessary, before you proceed
with the fitting process.
6. Examine the tutor.frp report file generated by the Fitter.
The tutor.frp file shows the results of the fitting and the pin assignment of the design.
If you want a certain fitting other than the one generated, return to the tutor.abl file to
specify the signal and pin assignments.

Capturing the Schematic
Begin the actual detailed schematic capture.
Now that the PSD5XX pins have been assigned to specific names and functions, you can
create the schematic. The schematic of the tutorial design example is shown in Figure 4.
The pins are assigned signal names from the tutor.frp file.

~~---------------------------------'~jfJF~-------------------------------------

.m

==-~

PSD4XX/SXX Design Tutorial - Application Note 031

Figure 4. Logie Schematic, Tutorial Design Example
D[15:0]
A[19:16]

D[15:0]

>

A[19:16]

I

MICROCONTROllER
ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7

ADO
ADl
AD2
AD3
AD4
AD5
AD6
AD7

9
8
7
6
5
4
3
2

ADOIAO
AD11Al
AD2IA2
AD3IA3
AD4IA4
AD5IA5
AD6IA6
AD71A7

PCO
PCl
PC2
PC3
PC4
PC5
PC6
PC7

17
16
15
14
13
12
11
10

IN PO
IN Pl
IN P2
IN P3
EVENTl
EVENT2
EVENT3
CNTOUT EN

AD8
AD9
AD10
ADll
AD12
AD13
AD14
AD15
A16
A17
A18
A19

AD8
AD9
AD10
ADll
AD12
AD13
AD14
AD15

68
67
66
65
64
63
62
61

AD8IA8
AD91A9
AD101Al0
ADlllAll
ADl21A12
ADl31A13
ADl41A14
ADl51A15

PDO
PDl
PD2
PD3
PD4
PD5
PD6
PD7

60
59
58
57
56
55
54

53

OUT PO
OUT Pl
OUT P2
OUT P3
DUT P4
OUT P5
lOAD
D4

PAO
PAl
PA2
PA3
PA4
PA5
PA6
PA7

27
26
25
24
23
22
21
20

A18
A17
A16

PBO
PBl
PB2
PB3
PB4
PBS
PB6
PB7

50
49
48
47
46
45
44
43

CNT4

RDI
WRI
BHE!
ALE

~
A17

~.1
~
RDI
WRI
BHE!
ALE

~
40

Ir--!42

-

~

ClK

I

RESETI

38
37
WSTC
36
WDOUT 34
D3
33
D2
32
31
Dl
DO
30

r
-

;:::=::::

=

::::..
;::::::
=
=
'"==

;::::::

-="

RD
WR
RESET
CSI
ClKIN

-:!:RESETI

-

==::
==::
==::

PEOIBHE
PE11AlE
PE2
PE3
PE4
PES
PE6
PE7
VSTBY

--

PSD5XX

* NOTE: PA3-PA7 and PB1-PB7 are not used.

----_______________________________________

rArAr&F~

~-.

___________________________________________
3-197

PSD4XX/5XX Design Tutorial - Application Not. 031

Using the
Design
Example
(Cont.)

Compiling the Design (Cont.)
P.rformlng Address Trans/atlon
The Address Translator in PSDsoft integrates your code file (EPROM file) and the
PSD5XX's configuration and fuse map files.
1. Pull down the Compile menu and choose Address Translate.

The Address Translation menu appears.

The Address Translation menu has two sections: EPROM ADDRESS and EPROM FILES.
2. Verify that the EPROM ADDRESS section of the menu displays the four chip select
equations (ESO-ES3) for the four EPROM blocks defined in the tutor.abl file.

-3-.1-98------------------------------~~~----------------------------------

PSD4XX/5XX Design TIItorlal - Application Note 031

Using the
Design
Example
(Cont.)

Compiling the Design (Cont.)
Performing Address Translation
3. Assign to each EPROM block in the EPROM FILES section the file address range
and the name of the EPROM file.
For example, the tutor. hex file consists of codes of a small test program which begins at
address 2000H. The hex file's data record indicates that the starting address is 2000H
and the ending address is 3FFOH, which indicates that it should be assigned to block O.
The Address Translator maps the code from the hex file at the file address specified
under File Address Start to the first location of the EPROM block. Since the tutor. hex
program has to be stored in EPROM location 2000H, you need to enter OOOOH - 3FFFH
to the File Address StarVStop columns. As there are no codes between OOOOH and
1FFFH in the tutor.hex file, tje Address Translator fills the EPROM block 0 locations
OOOOH to 1FFFH with "FF".
Each EPROM block in the PSD503B1 has 32K bytes and you must be careful not to
enter an address space of more than 32K bytes in the file starVstop columns.
4. Select the Intel Hex Record as the file type of tutor. hex.
The Address Translator accepts the input file in Intel Hex format or in
Motorola S-Record format.
5. Click OK to Compile.
The status of the Address Translation is indicated in the window that follows .

.Ii

Address Translation

Address Translation has been done successfully

If there are no errors, the tutor.obj file is generated. Click OK to exit the Address Menu.
The compilation of the PSD5XX is finished.

-----------------------------------~Ar~~----------------------------------_=_iE
3-199

PSD4XX/5XX Design Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

Simulating the Design
The PSDsimulator software, WSI's version of PSDsiloslll, provides chip level simulation and
design verification. PSDsilosll1 can model designs using the Verilog Language. Due to the
size of the PSD5XX model, a PC system requires at least 8 MB of DRAM and 8 MB of hard
disk swap area (specified as virtual memory in Windows).
The PSD5XX model consists of three components (files):

o

PSD5.V

(the PSD5XX netlist)

o

template.pfu

(the ZPLD fuse map)

o

template.afu

(the PSD5XX configuration fuse map)

Many of the intemal nodes of the PSD5XX are available for tracing. A description of the
signals that can be traced by the simulator are listed in the PSD5XX.MST file.
The input files required by the PSDsilosll1 simulator are generated by the Simulator
Preprocessor in PSDsoft. The file you must create is the stimulus file. In the stimulus file
(tutor.stl), you must use user-defined names (as in the tutor.abl file) or nellist node names
(as in the psd5xx.mst file). The files generated by the Simulator Preprocessor are as
follows:

o
o

template.pfu

Fusemap of the ZPLD

template.afu

Fusemap of the PSD configuration

project.grp

Group names of signals for PSDsilosll1 Data Analyzer

o
o

project.top

Top level invocation with user-defined signal names.

PSDsoft.run

A PSDsilosll1 command batch file which loads the PSD5.V, project.top,
and project.stl before invoking the simulator.

o

project.bus

Same as psd5xx.mst, except default signal names are replaced with
user defined names. Required in simulation display.

o

__________________ f'ss § g
3-200

~:if ~

------------------

PSD4XX/5XX OtlSlgn Tutlllial - ApplicatlDn Note 031

Using the
Design
Example

Simulating the Design (Clint.)
A sample of the stimulus file (tutor.stl) is shown at the end of this chapter. A typical stimulus
file (microcontroller writing/reading SRAM) is shown below.

(Clint.)
initial
begin
/lgenerate reset

reset=O;
wr =1; rd=1; bhe = 1;

/linitialize control signal

ale =0;
adio = 16'bz;

/linitialize'addr/data bus

/1(16 bit) to high impedance
a18=0;a17=0;a16=0;
cs =0;
#300

/lset high address bits to low
/lset PSD5XX chip select low

reset = 1;

/lafter 300ns, reset inactive

#100

ale = 1;

/lMCU start bus cycle, set up ale

#20

adio = 'h8476;

/ldrive addr on adio bus 20ns after ale

#30

ale=O;

/lale goes low

#30

adio = 'h5a27;

/ldrive data out to bus

bhe = 0;

/lbhe low, word operation

#40

wr=O;

/lgenerate 100ns write

#100

wr= 1;

/lend wr

bhe = 1;
#20

adio = 16'bz;

#50

ale= 1;

/lstart the read cycle, byte read

#20

adio = 'h8476;

/ldrive addr

#30

ale=O;

#30

adio = 16'bz;

/lMCU floats bus

#40

rd = 0;

/lgenerate rd pulse

#100

rd = 1;

/lend of rd cycle

/lend of bus cycle

end

Please note that the project. top file includes all the necessary data and port declarations,
and that the project.stl written by you will be appended to the projecttop file.

-----------------------------------,•• ~=- - - - - - - - - - - - - - 3 - · 2 - 8 - 1
~#.

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Simulating the EPROM in the PSD5XX
The PSDsimulator allows code files to be loaded to the EPROM blocks for simulation.
However, if code simulation is not specified, the PSD5XX model fills up the EPROM with a
fixed data pattern as shown in Table 7.

Table 7. EPROM Data Pattern
EPROM Block

Odd Byte

Even Byte

blockO (ESO)

01h

23h

block1 (ES1)

45h

67h

block2 (ES2)

89h

ASh

block3 (ES3)

CDh

EFh

With the pre-filled data pattern, you can verify the EPROM address decoding logic and the
even/odd by1e orientation.

Running the Logic Simulator
1. Write the stimulus file, project.st!.
2. Pull down the PSDsoft menu in the main PSDsoft window and select PSD Simulator.

-3~~~02~~~~~~~~~~~~~~--~~~~~~~~~~~~~~~~~~~--

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Running the Logic Simulator (Cont.)
The preprocessor software generates the necessary command files for PSDsiloslll, and the
window below appears.

Simulator PreProcessor
Successful in creating WSI-SILOS Command Files

3. Exit from PSDsoft and double-click the PSDsilosl1i icon to invoke the Simulator.
The PSDsilosll1 window appears, and displays the functions and menus available to you.

Eile

.Edit

!,ogicSim

Analyzer

Reports

Qebug

Qptions

!:!elp

--------------------------------~~~~-----------------------------3-~-D-3

PSD4XXj5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Running the Logic Simulator (Cont.)
4. Pull down the Debug menu and choose Reset All.

The system is reset before loading any new models or stimulus files.
5. Pull down the File menu and choose New (input files) and Working Directory.

-3-4~04~----------------------~-----~~~----------------------------------

PSD4XX/5XX DlIslgn Tutolial - Application Notll 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Running thll Lllf/lc Simulator (Cont.)
The Set Working Directory window appears.

Set Working Directory

Current Directory:
e:\p sd soft\tuto ri 81

[..]
[-8-]
[-b-]
[-c-]
[-d-]

6. Click the directory where the tutorial files reside.
7. When you are satisfied with the working directory path, click OK.
8. Pull down the Files menu and choose File New (input files) Input.

.Qpen (saved simulation) ...
~l)ve

Ctrl+W

-------------------------------~~~----------------------------3.-2--05

PSD4XX/5XX DIIS/gn TUtorial - Application Nots 031

Using the
Design
Example

Simulating the Design (Cont.)
Running ths Logic Simulator (Cont.)
The Input File window appears.

(Cont.)

Input File
File Name:

Input next file or Close

It~/lneuti~';d

Ipsdsoft.run
e:\... \tutorial

Directories:

Files:

..

[ )
[-a-)
[-b-)

[-c-)
[-d-]
[-e-]

save.his
save.sim

-f-

Ipsdsoft.run

File input list:

9.

Click the PSDsoft.run batch file in the Files window so that PSDsofl.RUN appears
in the File Name window.

10. Click Input.
The PSDsofl.run batch file executes, loading the tutor.stl and the PSD5XX module
into PSDsilosll1.
If a syntax error is detected in the project.stl file while loading the file or running the
simulator, an error message is displayed.
SILOS Error

o

warning# 1.307 line 21 file tutor.top
'define adiol adio(7:0)
.. fe-definition of name 'adiol
3 error(s): See Error Report

Every time the tutor.stl file is modified to correct the errors, PSDsilosll1 has to be reset
before loading the PSDsofl.run file again.

11. Click Close.
Now that the PSD5XX model and the stimulus file have been loaded, you are ready to
invoke the simulator.
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ii'66
iiF~

3-206

~~§-------------------

PSD4XX/5XX Design TUtorial - Application Nots 031

Using the
Design
Example

Simulating the Design (Cont.)
Running ths Logic Simulator (Cont.)
12. Pull down the LogicSim menu and choose Run logic simulation.

(Cont.)

Ereprocess data
Bun logic simulation ... F5

The Simulate dialog box is displayed. The Simulate dialog box allows you to specify
the simulation time range defined by t1 and t2.

Simulate

n:

t2:

10

100000n5

Simulation Type - - - - - - - - - ,
@ Normal

o Zero Delay

13. Click Simulate
The result of the simulation is stored in the tutor.sim file.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FES #!E
~~jf----------------3-4-0--7

PS04XX/5XX Design TUtorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Running the Analyzer
Now that logic simulation is complete, the result can be displayed with the PSDsilosl1i Data
Analyzer (PSDsda) by performing the following steps:
1. Pull down the Analyzer menu and choose Start analyzer.

2. The Select Display List window appears.

Select Display List
Display List:

Circuit Node List:

clkin
ale
rd
wr
bhe
rsO
csiop
adioh
adiol
wdog2pld
cntO

Add blank line
III

I

ii'i

•

Display Groups - - - - - ,

Idefault

I[I
esl

es2
es3
Type:

unknown node

The first time the Analyzer is invoked, a list of signals arranged in alphabetical order are
displayed. You can re-arrange the order of the signals and save this list (click Save and
save the list in tutor.grp) so that it can be used in the next invocation.

-3-~-O-8----------------~~~-------------------

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Running the Analyzer
3. Select the list of signals to be displayed by the Analyzer.
4. Click OK when you are satisfied with the signal list.
The PSDsilosll1 Data Analyzer window is displayed.

The waveforms of the selected signals are displayed. Signals inside the signal box can
be moved by dragging and the window can be moved up or down with the scroll bar.
The Zoom buttons (* = zoom full, 0 = zoom out, I = zoom in) and the time scale control
the display window. The two time markers, T1 (the left mouse button) and T2 (the right
mouse button) specify the range to be displayed.
A signal trace can be displayed in four colors on the PC monitor, depending on the nature of
the signal, as follows:

Blue
Green
Red
Black

The signal is being driven as an input.
The signal is being driven as an output.
The signal is floating.
The signal is in an undefined state.

-----------------------------------~~~~--------------------------------3--2-09-

PSD4XX/5XX Design TUtorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Creating a Bus
The PSDsda allows you to put together a group of signals into a bus, which can be
displayed in the PSDsda window. To create such a bus
1. In the PSDsda window, pull down the Select menu and choose Buses.

The Select Bus Items window appears. At this point, you can create a bus to add to the
PSDsda window for display during debugging. A sample bus will be created using the
signals A16, A17, and AlB.

Select Bus Items
Bus Item List:

(msb)

Circuit Node List:
la18
(
D15-D8(non-mux)
D7-DO(non-mux)
a16
a17

...

a17
a16

(Isb)
Bus----------------------~

Name
L-Iad_d_bu_s_ _-II

Radix

[iJ

IHex

Iii

1:'h~i,J

adioh
adiol
ale
bhe
c...
dO
dl
d2
d3
dol
deep pwrdn

*

~

.,','

~

Type: scalar net alias

lei4iij;1

--__
-------------------------------f===~--------------------------------3-210
==~=

1'SD4XX/5XX IIBsIgn TUtllrl" - Appllcatilln illite 031

Using the
Design
Example

Simulating the Design (Clint.)
C",atlng, Bus
2. Click Clear to erase any signal names that appear in the Bus Item List window.

(Cont.)

3. Enter addbus in the name window within the Bus window.
add bus will become the name of the new item to eventually be displayed in the PSDsda
window. It will consist of the combined A16, A17, and A18 values.
4. Click the A16 signal in the Circuit Node List.
5. Click Add.
The A16 signal is added to the Bus Item List window.
6. Repeat steps 4 and 5 for A17 and A18.
At this point, the A16, A17, and A18 signals appear in the Bus Item List window.
7. Click Save in the Bus window.
The add bus name is now added to the Circuit Node List, with a notation at the bottom of
the list that it is a user-defined bus type.
Select Bu;:, Items

Bus Item List:

(msb)

Circuit Node List:

illl

a17
a16

1-

(Isb)
Bus
Name
laddbus

Radix
II

IHex

II

III
III

adrlbus

adioh
adiol
ale
bhe
c...
dO
d1
d2
d3
d.ll

~

.',

Type: user defined bus

!MIl

8. Click OK.
The PSDsda window reappears.

----------------------------~_'~_;---------------------------'IJ
3-211

PSlJ4XX/5XX Design Tutorial - Application Not, 031

Using the
Design
Example
(Cont.}

Simulating the Design (Cont.}
C",tlng a Bus
9.

Pull down the Select menu and choose Display list.
The Select Display list window appears.

Select Display list
Display List:

Circuit Node List:

reset
tmr frez ack
tmr-frez - cmd
tmr=glob-='cmd_reg
imgOH
imgOL
pgrO_3
portc
d2
d3

addbus
Add blank line

'··"1-

(...

Timer-Sync

''"'I'"
"''''1-

Display Groups-----,

I. .d_ef_a_ult_ _ _---'II

all
III

11_

a16

a17
a18
addbus
adioh
adiol
ale
bhe

c...

I"':~o
esl

----J_

es2

=.::..;;:..._ _ _ _ _

Type:

user defined bus

The addbus name appears in the Circuit Node list because it was added as a bus in the
previous steps.
10. Click addbus in the Circuit Node list to select it.
11. Click Add.
The addbus name now appears in the Display list, indicating that addbus is now
available for display in the PSDsda window.

~~-----------~~~--------------3.212
'If

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Simulating the Design (Cont.)
Creating a Bus
12. Click OK.
The PSDsda window reappears.

a16
al?
alB
addbus
adioh
adiol

tmUrez_cmd

13. Scroll down the Signal name window until you see addbus.
The signal waveform corresponding to the addbus value is displayed in the window to
the right.
The addbus name is saved in the tutor. bus file and is available for display each time
you use PSDsda.

-----------------------------------~~~----------------------------------====
3-213

~---~---~----

PSD4XX/5XX Design Tutorial - Application Note 031

Using the
Design
Example
(Cont.)

Programming The PSD5XX
Take the following steps to program the PSD5XX after the design has been verified through
simulation. For more detailed information, refer to the PSDprogrammer chapter in this
manual.
1. Pull down the PSDsoft menu in the main PSDsoft window and choose

The main PSD Programmer window appears.

~3~~~1~4-------------------------------~~~-----------------------------------

PSD4XX/5XX Design Tutorlsl - Appllt:lltlon Note 031

Using the
Design
Example

2. Pull down the File menu and choose Open.

(Cont.)

3. Select the tutor.obj file to be loaded to the PSDpro buffer.

PrDgrammlng The PSD5XX (Cont.)

The contents of the tutor.obj file are displayed. Use the Edit menu for making any
code modifications.

There are several options available to you for working with a device. Some of these
functions are shown under the Functions menu of the main PSDprogrammer window.
4. Pull down the Functions menu to see the available options.

----------------------------------,_~_Ar~_~---------------------------------'4fIf!..t
3.215

PSD4XX/5XX Design Tutorial - Application Not, 031

Using the
Design
Example
(Cont.)

Programming The PS05XX (Cont.)
The Functions menu provides the following options in programming the PSD5XX:

o
o
o

Blank Test Verify the device is blank.
Program

Program the device.

o

Verify

Verify the programmed device against
the .obj file in the buffer.

Upload

Upload the programmed part contents to the buffer.

The Control Panel also displays several functions, some of which are duplicated under the
Functions menu in the main window.

11 Controls aa
IiilfiiiilriiilriiDill

_~UII_

r;;;Iijiiiijijllil.i!
I~
Imlallll
~ ~~

~3-~-16--------------------------------~~~-----------------------------------

PSD4XX/5XX Dsslgn Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

To Program a Part
1. Pull down the Functions menu in the main PSDpJogrammer window and select
Program or
click the Prgm button of the Control Panel.
The Confirmation dialog box appears, which allows you to program the EPROM,
PLD, or Acr regions of the device.

'iilil

PSDPro - Confirmation Dialog

jgI All

D Eprom
DPld

DAcr

2. Select one or more of the boxes to indicate the regions of the device you want
programmed.
3. Click Range to specify the address range within the device where the programming is to
take place.
The Eprom Address Range dialog box appears.

___________________________________

FES~E

~~e

--------------------------------3.-2-,7-

PSD4XX/5XX Design Tutorial - Application Nots 031

Using the
Design
Example
(Cont.)

To Program a Part (Cont.)
4. Enter the starting and ending addresses where indicated and click OK when you are
satisfied with the values.
The Eprom Address Range dialog box disappears. By default, the address range is set
to the beginning and ending address of the EPROM, so that the entire range of the
EPROM is specified. The range can be specified only for the EPROM, not the PLD or
Acr regions.
5. Click OK in the Confirmation dialog box when you are satisfied with the address range
that will be programmed as well as with the functional parts of the device that will be
programmed (Eprom, PLD,Acr).
A bar graph showing programming progress as well as percent complete is shown on the
screen. As the programming takes place, the MagicPro® programmer checks each location
as it is programmed to make sure it matches the hexadecimal file contents. If a particular
location cannot be programmed properly, an error message appears. If this occurs, you
must start over and program a new fully erased and functional part.
When the device has been successfully programmed, the PSDpro software verifies the
device by comparing its contents with the contents of the hexadecimal file in system
memory. If the device does not properly verify, an error message appears, and you must
start over and program a new fully erased and functional part.

--__
3-218---------------------------------rArJr~~------------------------------------_illlY.

PSD4XX/5XX Design Tutofial - Application Note 031

PSDsoft
Input/Output
File List

File Extension

Description

project. ERR

- Error log file generated by various PSDsoft programs

project.INI

- Project information file

project.ABL

- PSDabel-HDL language equation file created by you

project.TT1

- Non-optimized PLA file

project.TT2

- Optimized PLA file

project.TT3

- Fitted PLA file

project.TMV

- Test vector file automatically generated by PSDabel compiler

project.LST

- PSDabel compiler listing file

project.SMn

- PSDabel simulation output result file generated from .TTn file

project. EOn

- PSDabel equation files generated from .TTn file

project.AOP

- PSDabel options file generated automatically upon exiting PSDabel

project.GLC

- Global configuration file

project.CRP

- Global configuration report file

project.HEX

- EPROM Hex object file

project.FOB

- Fuse map file in Hex format (PLD + Configuration)

project.OBJ

- Fuse map file in Hex format (PLD + Configuration + EPROM)

project.AFU

- Architecture configuration fuse file for simulation use

project.PFU

- PLD fuse file for simulation use

project.EFn

- EPROM fuse file for simulation use where n = 0 through 3,
each representing EPROM block ESO through ES3, respectively

project.FEO

- Fitter equation file using only device reserve names

project.FRP

- Fitter pin assignment report file

project.ASV

- Address translator save file

project.ARP

- Address translator report file

project.STL

- PSDsilosl1i stimulus file created by you

project.TOP

- PSDsilosll1 top level model file

TEMPLATE:

- Intermediate fuse files for PSDsilosll1 Logic simulation use

project.BUS

- User-defined bus names for the PSDsilosll1 Data Analyzer

project.CMM

- Current state of the simulator

project.GRP

- Group names of signals for the PSDsiloslll Data Analyzer

project.HIS

- History of any commands used for this session of PSDsilosll1

project. LOG

- PSDsilosllllog file

project.SIM

- PSDsilosll1 simulation history

project.STM

- Stimulus yalues related to expected results

project.VTR

- Vector names for the PSDsilosll1 Data Analyzer

PSDsoft.RUN

- For automatic loading of user netlist file and device model library

------------------------------~Jr~---------------------------3-~~19

PS04XX/5XX OIlS/gn Mor/al - Application Nots 031

Tutor
Equation File tutor.eq2

3-220

MODULE tutor
TITLE 'tutor design example ZPLD source file

,

a15
a14
a13
a12
a11
a10
a9
a8
a1
aO
a18
a17
a16
pgr3
pgr2
pgr1
pgrO
bhe
elkin
reset
event1
event2
event3
entouCen
load
d4
d3
d2
d1
dO
in_pO
in_p1
in_p2
in_p3
wste
ent4
ouCpO
ouCp1
ouCp2
ouCp3
ouCp4
ouCp5
wdout
wdog2pld
esiop
rsO
esO
es1
es2
me2tmrO
ent3
ent2
ent1
entO

PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN
PIN
PIN
PIN;
PIN
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN
PIN
PIN
PIN
PIN;
PIN;
PIN
PIN
PIN
PIN
PIN
PIN
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;
PIN;

38;
42;
40;

17;
16;
15;
14;

60;
59;
58;
57;
56;
55;

V;i;

PSD4XXj5XX Design TUtorial - Application Note 031

Tutor
Equation File tutor.eq2

EQUATIONS

= (a15 & a14 & !a13 & !a12 & !a11

csiop

& !a10 &.!a9 & !a8 &

!a18 & !a17 & !a16);
rsO

= (a15 & !a14 & !a13 & !a12 & !a11

esO

= (!a15 & !a18 & !a17 & !a16 & !pgr3 & !pgr2 & !pgr1 & !pgrO);

es1

= (!a15 & !a18 & !a17 & !a16 & pgr3 & !pgr2 & !pgr1
= (a15 & a18 & !a17 & !a16);

es2

& !a18 & !a17 & !a16);

& pgrO);

wstc = (!cnt4.FB & !cnt3.FB & !cnt2.FB & !cnt1.FB & !cntO.FB);

:= (!Ioad & !wstc & !cnt4.FB & !cnt3.FB & !cnt2.FB & !cnt1.FB & !cntO.FB
# load & d4
# !load & !wstc & cnt4.FB & cntO.FB
# !load & !wstc & cnt4.FB & cnt1.FB
# !load & !wstc & cnt4.FB & cnt2.FB
# !load & !wstc & cnt4.FB & cnt3.FB);

cnt4

= (clkin);
cnt4.RE = (reset);
cnt4.0E = (!cntout_en);
cnt4.C

:= (!load & !wstc & !cnt3.FB & !cnt2.FB & !cnt1.FB &

cnt3

#
#
#
#

!cntO.FB
!load & !wstc & cnt3.FB & cntO.FB
!load & !wstc & cnt3.FB & cnt1.FB
!load & !wstc & cnt3.FB & cnt2.FB
load & d3);

=(clkin);
cnt3.RE = (reset);

cnt3.C

cnt2

:= (!load & !wstc & !cnt2.FB & !cnt1.FB & !cntO.FB
# !load & !wstc & cnt2.FB & cntO.FB
# !load & !wstc & cnt2.FB & cnt1.FB
# load & d2);

= (clkin);
cnt2.RE = (reset);

cnt2.C

cnt1

:= (!Ioad & !wstc & !cnt1.FB & !cntO.FB

# !load & !wstc & cnt1.FB & cnto.FB
# load & d1);
cnt1.C

= (clkin);
= (reset);

cnt1.RE
cntO

:= (!load & !wstc & !cnto.FB
# load & dO);

cntO.C

=(clkin);
= (reset);

cntO.RE

mc2tmrO = (event1 & !event2
# !event3);
wdout

=(!wdog2pld);

END

----------------------------------~~~------------------------------3-~~2--1

I'SII4XX/5XX IkIIl,n TutDrial - AppllClltlDn Note 031

PSDXXX.mst
FilllS

PS05".mst FilII
The following 1S9 signals are available to you for PSDsilosll1 simulation of a PSDSXX
device.
1.

datah

2.

datal

3.
4.
S.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1S.
16.
17.
18.
19.
20.
21.
22.
23.
24.
2S.
26.
27.
28.
29.
30.
31.
32.
33.
34.
3S.
36.
37.
38.
39.
40.
41.
42.
43.
44.
4S.

intr-J)riocstat
pe_mcO
pe_mc1
pe_mc2
pe_mc3
pe_mc4
pe_mcS
pe_mc6
pe_mc7
pb_mcO
pb_mc1
pb_mc2
pb_mc3
pb_mc4
pb_mcS
pb_mc6
pb_mc7
pa_mcO
pa..mc1
pa..mc2
pa..mc3
pa..mc4
pa..mcS
pa_mc6
pa_mc7
deep_pwrdn
pwrdn
psen_to_ram_en
periph_mode
pmmr1
pmmrO
wdog2pld
intr2pld
mc2tmrO
mc2tmr1
mc2tmr2
mc2tmr3
mc2int6
mc2int7
pt2int4
pt2intS
douCb
dirfCb

;Upper byte of the 16-bit data bus in
non-mux mode only
;Lower byte of the 8/16-bit data bus in
non-mux mode only
;Interrupt Priority Status register
;Port E macrocell output-O
;Port E macrocell output-1
;Port E macrocell output-2
;Port E macrocell output-3
;Port E macrocell output-4
;Port E macrocell output-S
;Port E macrocell output-6
;Port E macrocell output-7
;Port B macrocell output-O
;Port B macrocell output-1
;Port B macrocell output-2
;Port B macrocell output-3
;Port B macrocell output-4
;Port B macrocell output-S
;Port B macrocell output-6
;Port B macrocell output-7
;Port A macrocell output-O
;Port A macrocell output-1
;Port A macrocell output-2
;Port A macrocell output-3
;Port A macrocell output-4
;Port A macrocell output-S
;Port A macrocell output-6
;Port A macrocell output-7
;Deep Sleep mode of PSD
;Standby mode of PSD
;SRCODE bit in VM register
;Peripherall/O mode
;Power Management mode register-1
;Power Management mode register-O
;WatchDog output routed as a PPLD input
;Interrupt output routed as a PPLD input
;CounterlTimer-O PPLD macrocell output
;CounterlTimer-1 PPLD macrocell output
;CounterlTimer-2 PPLD macrocell output
;CounterlTimer-3 PPLD macrocell output
;lnterrupt-6 PPLD macrocell output
;lnterrupt-7 PPLD macrocell output
;lnterrupt-4 PPLD product term output
;Interrupt-S PPLD product term output
;Port B data out register
;Port B direction register

-----------------------------------~~.!'------------------~--------------3-222
~

PSD4XX/5XX Dsslgn Tutorial - Application Nots 031

PSDXXX.mst
Files

PSD5B1.mst File (Cont.)
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.

ctrLb
spec_b
ctrLe
douLe
dirfCe
spec_e
intUevel
intcmsk
intr_req
tmr_waiLcnt

56.
57.
58.

tmr_glob_cmd_reg
tmUrez_cmd
tmUrez_ack

59.

tmcsofUd

60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.

cmd3
cmd2
cmd1
cmdO
ctrLd
douLd
dirfLd
opn_drn_d
douLc
ctrLc
dirfCc
opn_drn_c
pgrO_3
psel1
pselO
csiop
es3
es2
es1
esO
rsO
pbO
pb1
pb2
pb3
pb4
pb5
pb6
pb7
paO
pa1

77.
78.
79.
80.
81.
82.
83.

84.
85.
86.
87.
88.
89.
90.

;Port B control register
;Port B special function register
;Port E control register
;Port E data register
;Port E direction register
;Port E special function register
;Interrupt Edge/Level definition register
;Interrupt Mask register
;Interrupt request latch register
;DLCY(delay) value of Countermmers
clock input
;Global command register of Countermmers
;Freeze Command register of Coutermmers
;Freeze Acknowledge status register of
Countermmers
;Software load command register of
Countermmers
;Countermmer-3 command register
;Countermmer-2 command register
;Countermmer-1 command register
;Counterffimer-O command register
;Port D control register
;Port D data register
;Port D direction register
;Port D Open Drain/CMOS definition register
; Port C data register
;Port C control register
;Port C direction register
;Port C Open Drain/CMOS definition register
;Page Registers 0 through 3
;Peripherall/O mode select product term 2
;Peripheral I/O mode select product term 1
;Chip Select I/O ports
;EPROM Chip select for block-3
;EPROM Chip select for block-2
;EPROM Chip select for block-1
;EPROM Chip select for block-O
;PSD SRAM Chip Select
;Port B pin-O
;Port B pin-1
;Port B pin-2
;Port B pin-3
;Port B pin-4
;Port B pin-5
;Port B pin-6
;Port B pin-7
;Port A pin-O
;Port A pin-1

-=

--------------------------------~-~~~----------------------------~~
3-223

PSD4XX/5XX Design Tutorial - Application Nots 031

PSOXXX.mst
Files

PSD5B1.mst File (Cont.)
91.
92.
93.
94.
95.
96.
97.
98.
99.
100.
101.
102.
103.
104.
105.
106.
107.
108.
109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
119.
120.
121.
122.
123.
124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
134.
135.

pa2
pa3
pa4
paS
pa6
pa7
pe2
pe3
pe4
peS
pe6
pe7
pdO
pd1
pd2
pd3
pd4
pdS
pd6
pd7
pcO
pc1
pc2
pc3
pc4
pcS
pc6
pc7
spec_a
dirfCa
ctrLa
dou'-a
cntr3H
cntr3L
cntr2H
cntr2L
cntr1 H
cntr1 L
cntrOH
cntrOL
img3H
img3L
img2H
img2L
img1H

;Port A pin-2
;Port A pin-3
;Port A pin-4
;Port A pinoS
;Port A pin-6
;Port A pin-7
;Port E pin-2
;Port E pin-3
;Port E pin-4
;Port E pinoS
;Port E pin-6
;Port E pin-7
;Port D pin-O
;Port D pin-1
;Port D pin-2
;Port D pin-3
;Port D pin-4
;Port D pinoS
;Port D pin-6
;Port D pin-7
;Port C pin-O
;Port C pin-1
;Port C pin-2
;Port C pin-3
;Port C pin-4
;Port C pinoS
;Port C pin-6
;Port C pin-7
;Port A special function register
;Port A direction register
;Port A Control register
;Port A data register
;CounterlTimer-3 high byte register
;CounterlTimer-3 low byte register
;CounterlTimer-2 high byte register
;CounterlTimer-2 low byte register
;CounterlTimer-1 high byte register
;CounterlTimer-1 low byte register
;CounterlTimer-O high byte register
;CounterlTimer-O low byte register
;CounterlTimer-3 Image high byte register
;CounterlTimer-3 Image low byte register
;CounterlTimer-2 Image high byte register
;CounterlTimer-2 Image low byte register
;CounterlTimer-1 Image high byte register

-----------------------------------r~~~~----------------------------------3-224
~iiiE 51!

PSD4XXj5XX Des/gn Tutorial - Application Note 031

PSDXXX.mst
Files

PSD5B1.mst File (Cont.)
136.
137.
138.
139.
140.
141.
142.
143.
144.
145.
146.
147.
148.
149.
150.
151.
152.
153.
154.
155.
156.
157.
158.
159.
160.

img1L
imgOH
imgOL
portb
clkin
reset
csi
pe1
peO
wr
rd
portd
portc
adioh
adiol
porta
timeroutO
timerout1
timerout2
timerout3
pgrO
pgr1
pgr2
pgr3
timer_elk

;CounterlTimer-1 Image low byte register
;CounterlTimer-O Image high byte register
;CounterlTimer-O Image low byte register
;Port S register
;PSD input Clock
;PSD input reset
;PSD Chip Select
;Port E pin-1 (ALE etc.,)
;Port E pin-O (PSEN, SHE etc.,)
;PSD write signal
;PSD read signal
;Port D register
;Port C register
;Address/Data bus high byte
;Address/Data bus low byte
;port A register
;CounterlTimer-O output (only when used)
;CounterlTimer-1 output (only when used)
;CounterlTimer-2 output (only when used)
;CounterlTimer-3 output (only when used)
;Page Register bit 0
;Page Register bit 1
;Page Register bit 2
;Page Register bit 3
;The actual clock input to the CounterlTimers

-----------------------------------r~~~~----------------------------------i!ffRiiFS.
3-225

PSD4XX/5XX Dflslgn Tutorial - Application Notfl 031

PSDXXX.mst
Files

PSD4A1.mst File
The following 100 signals are available to you for PSDsilosll1 simulation of a
PSD4XXA 1 device.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.

34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
47.
48.

3-226

datah
datal
pb_mcO
pb_mc1
pb_mc2
pb_mc3
pb_mc4
pb_mc5
pb_mc6
pb_mc7
deep_pwrdn
pwrdn
psen_to_ram_en
periph_mode
pmmr1
pmmrO
douLb
dirfCb
ctrl_b
spec_b
ctrl_e
douLe
dirfCe
spec_e
ctrl_d
douLd
dirfCd
opn_dm_d
dout_c
ctrLc
dirfCc
opn_dm_c
pgrO_3
psel1
pselO
csiop
es3
es2
es1
esO
rsO
pbO
pb1
pb2
pb3
pb4
pbS
pb6

;Upper byte of the 16-bit data bus in non-mux mode only
;Lower byte of the 8/16-bit data bus in non-mux mode only
;Port B macrocell output-O
;Port B macrocell output-1
;Port B macrocell output-2
;Port B macrocell output-3
;Port B macrocell output-4
;Port B macrocell output-5
;Port B macrocell output-6
;Port B macrocell output-7
;Deep Sleep mode of PSD
;Standby mode of PSD
;SRCODE bit in VM register
;Peripheral I/O mode
;Power Management mode register-1
;Power Management mode register-O
;Port B data out register
;Port B direction register
;Port B control register
;Port B special function register
;Port E control register
;Port E data register
;Port E direction register
;Port E special function register
;Port D control register
;Port D data register
;Port D direction register
;Port D Open Drain/CMOS definition register
;Port C data register
;Port C control register
;Port C direction register
;Port C Open Drain/CMOS definition register
;Page Registers 0 through 3
;PeripheralllO mode select product term 2
;Peripheral I/O mode select product term 1
;Chip Select I/O ports
;EPROM Chip select for block-3
;EPROM Chip select for block-2
;EPROM Chip select for block-1
;EPROM Chip select for block-O
;PSD SRAM Chip Select
;Port B pin-O
;Port B pin-1
;Port B pin-2
;Port B pin-3
;Port B pin-4
;Port B pin-5
;Port B pin-6

r#~=';

PSII4XX/SXX lIft/gn .,.,."., - Application .",.1137

PSDXXX.mst
Flies

I'SD4A1.mst FII, (Cont.)
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.
94.
95.
96.
97.
98.
99.

100.

pb7
paO
pa1
pa2
pa3
pa4
pa5
pa6
pa7
pe2
pe3
pe4
pe5
pe6
pe7
pdO
pd1
pd2
pd3
pd4
pd5
pd6
pd7
pcO
pc1
pe2
pc3
pc4
pe5
pc6
pc7
spec_a
dirfCa
ctrLa
douLa
portb
clkin
reset
csi
pe1
peO
wr
rd
portd
portc
adioh
adiol
porta
pgrO
pgr1
pgr2
pgr3

;Port B pin-7
;Port A pin-O
;Port A pin-1
;Port A pin-2
;Port A pin-3
;Port A pin-4
;Port A pin-5
;Port A pin-6
;Port A pin-7
;Port E pin-2
;Port E pin-3
;Port E pin-4
;Port E pin-5
;Port E pin-6
;Port E pin-7
;Port 0 pin-Q
;Port 0 pin-1
;Port 0 pin-2
;Port 0 pin-3
;Port 0 pin-4
;Port 0 pin-5
;Port 0 pin-6
;Port 0 pin-7
;Port C pin-O
;Port C pin-1
;Port C pin-2
;Port C pin-3
;Port C pin-4
;Port C pin-5
;Port C pin-6
;Port C pin-7
;Port A special function register
;Port A direction register
;Port A Control register
;Port A data register
;Port B register
;PSD input Clock
;PSD input reset
;PSD Chip Select
;Port E pin-1 (ALE etc.,)
;Port E pin-O (PSEN, BHE etc.,)
;PSD write signal
;PSD read signal
;Port 0 register
;Port C register
;AddresslData bus high byte
;Address/Data bus low byte
;port A register
;Page Register bit 0
;Page Register bit 1
;Page Register bit 2
;Page Register bit 3

WI;

3-227

PSD4XX/5XX Dssign Tutorial - Application Nots 031

PSDXXX.mst
Files

PSD4A2.mst File
The following 116 signals are available to you for PSDsilosll1 simulation of a PSD4XXA2
device.
1.
2.
3.
4.
S.
6.
7.
8.
9.
10.
11.
12.
13.
14.
1S.
16.
17.
18.
19.
20.
21.
22.
23.
24.
2S.
26.
27.
28.
29.
30.
31.
32.
33.
34.
3S.
36.
37.
38.
39.
40.
41.
42.
43.
44.
4S.

datah
datal
pe_mcO
pe_mc1
pe_mc2
pe_mc3
pe_mc4
pe_mcS
pe_mc6
pe_mc7
pb_mcO
pb_mc1
pb_mc2
pb_mc3
pb_mc4
pb_mcS
pb_mc6
pb_mc7
pa_mcO
pa_mc1
pa_mc2
pa_mc3
pa_mc4
pa_mcS
pa_mc6
pa_mc7
deep_pwrdn
pwrdn
psen_to_ram_en
periph_mode
pmmr1
pmmrO
dout_b
dirfCb
ctrl_b
spec_b
ctrl_e
douLe
dirfCe
spec_e
ctrLd
douLd
dirfCd
opn_drn_d
douLc

_____________________________________
3-228

;Upper byte of the 16-bit data bus in non-mux mode only
;Lower byte of the 8/16-bit data bus in non-mux mode only
;Port E macrocell output-O
;Port E macrocell output-1
;Port E macrocell output-2
;Port E macrocell output-3
;Port E macrocell output-4
;Port E macrocell output-S
;Port E macrocell output-6
;Port E macrocell output-7
;Port B macrocell output-O
;Port B macrocell output-1
;Port B macrocell output-2
;Port B macrocell output-3
;Port B macrocell output-4
;Port B macrocell output-S
;Port B macrocell output-6
;Port B macrocell output-7
;Port A macrocell output-O
;Port A macrocell output-1
;Port A macrocell output-2
;Port A macrocell output-3
;Port A macrocell output-4
;Port A macrocell output-S
;Port A macrocell output-6
;Port A macrocell output-7
;Deep Sleep mode of PSD
;Standby mode of PSD
;SRCODE bit in VM register
;Peripheral I/O mode
;Power Management mode register-1
;Power Management mode register-O
;Port B data out register
;Port B direction register
;Port B control register
;Port B special function register
;Port E control register
;Port E data register
;Port E direction register
;Port E special function register
;Port D control register
;Port D data register
;Port D direction register
;Port D Open Drain/CMOS definition register
;Port C data register

FAFAFSF~

~=ifg

_____________________________________

PSD4XX/5XX Design TUtorial - Application Not. 031

PSOXXX.mst
Files

PSD4A2.mst File
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.

64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.

77.
78.
79.
80.
81.
82.
83.

84.
85.
86.
87.
88.
89.
90.

ctrLc
dirfCc
opn_dm_c
pgrO_3
psel1
pselO
csiiop
es3
es2
es1
esO
rsO
pbO
pb1
pb2
pb3
pb4
pb5
pb6
pb7
paO
pa1
pa2
pa3
pa4
pa5
pa6
pa7
pe2
pe3
pe4
pe5
pe6
pe7
pdO
pd1
pd2
pd3
pd4
pd5
pd6
pd7
peO
pc1
pc2

;Port C control register
;Port C direction register
;Port COpen Drain/CMOS definition register
;Page Registers 0 through 3
;Peripheral 1/0 mode select product term 2
;Peripheral 1/0 mode select product term 1
;Chip Select 1/0 ports
;EPROM Chip select for block-3
;EPROM Chip select for block-2
;EPROM Chip select for block-1
;EPROM Chip select for block-O
;PSD SRAM Chip Select
;Port B pin-O
;Port B pin-1
;Port B pin-2
;Port B pin-3
;Port B pin-4
;Port B pin-5
;Port B pin-6
;Port B pin-7
;Port A pin-O
;Port A pin-1
;Port A pin-2
;Port A pin-3
;Port A pin-4
;Port A pin-5
;Port A pin-6
;Port A pin-7
;Port E pin-2
;Port E pin-3
;Port E pin-4
;Port E pin-5
;Port E pin-6
;Port E pin-7
;Port D pin-O
;Port D pin-1
;Port D pin-2
;Port D pin-3
;Port D pin-4
;Port D pin-5
;Port D pin-6
;Port D 'Pin-7
;Port C pin-O
;Port C pin-1
;Port C pin-2

----------------------------------~~.!'----------------------------------

3-229

ntl4XX/5XX 11M", 'fitwIal - App/latI", "_.7

PSDXXX.mst
Filss

~~

3-2311

PSIUA2._ FII. (CIIIt.}
91.
92.
93.
94.
9S.
96.
97.
98.
99.
100.
101.
102.
103.
104.
10S.
106.
107.
108.
109.
110.
111.
112.
113.
114.
11S.
116.

pe3
pc4

peS
pe6
pe7
spec_a
dirfCa
ctrLa
douLa
portb
clkln
reset
csi
pe1
peO
wr
rd

portd
portc
adloh
adiol
porta
pgro
pgr1
pgr2
pgr3

;Port C pin-3
;Port C pin-4
;Port C pinoS
;Port C pin-6
;Port C pin-7
;Port A special function register
;Port A direction register
;Port A Control register
;Port A data register
;Port B register
;PSD input Clock
;PSD input reset
;PSD Chip Select
;Port E pin-1 (ALE etc.,)
;Port E pin-O (PSEN, BHE etc.,)
;PSD write signal
;PSD read signal
;Port 0 register
;Port C register
;AddresslData bus high byte
;AddresslData bus low byte
;port A register
;Page Register bit 0
;Page Register bit 1
;Page Register bit 2
;Page Register bit 3

__________________

r'I~,.

.",.1..

_____________________

PSD4XX/5XX lleslgn rut"lal - AppllCllfIDn NDt. 031

Stimulus
File
tutor.stl

H+++++++++++++++++++++++++++++++++++++++++++++++++

H

User-Defined Parameters

H+++++++++++++++++++++++++++++++++++++++++++++++++
parameter pmmrO='hCOBO, cntrO='hC098, imgO='hC090;
parameter dlcy='hCOA6, cmdO='hCOAO, global='hCOA8;
parameter freeze='hCOA4, status='hCOA9, page='hCOEO;
parameter sram_loc='h8476, es_loc1 ='h39FE, es_loc2='h146C;
parameter es_loc3='h39FD;
parameter bhe_on=O, bhe_off=1, page9=9;
parameter clear=O, freeze_on=1, unfreeze=O;

H+++++++++++++++++++++++++++++++++++++++++++++++++

H

User-Defined Tasks

11+++++++++++++++++++++++++++++++++++++++++++++++++
task write (addr_bus,bhe_value,data_in);
input [15:0] addr_bus;
input [15:0] data_in;
input bhe_value;
begin
#20 ale = 1; IILatch the address lines
#20 adio = addr_bus; IISet-up the right address
bhe = bhe_value;
#20 ale = 0; IIAle inactive
#20 adio = data_in; II Write operation
#40 wr = 0; II Write pulse
#100 wr = 1; II Write ends
#10 adio = Z16; bhe =Z;
end
endtask
task read (addr_bus);
input [15:0] addcbus;
begin
#20 ale = 1; IILatch the address lines
#20 adio = addr_bus; IISet-up the right address
bhe = 0;·
#20 ale = 0; HAle inactive
#20 adio = Z16; H Float Address bus
#40 rd = 0; II Rd pulse
#100 rd = 1; H Rd ends
#10 bhe = Z;
end
endtask

----------------------------~Jrjr---------------------------3-231

PSD4XX/5XX Design Tutorial - Application Not, 031

Stimulus
File
tutor.stl
(Cont.)

11+++++++++++++++++++++++++++++++++++++++++++++++++
II
USER defined buses
11+++++++++++++++++++++++++++++++++++++++++++++++++
reg [4:0] din;
assign {d4, d3, d2, d1, dO} = din;
IIdin defines the 5 parallel-in bits loaded to the down-counter.
liThe down-counter is implemented using the PLD macrocells
II( unrelated to timer-O unit that is configured here as an event-counter}.
reg [2:0] evenUn;
assign {event3, event2, event1} = evenUn;
lIevenUn combines the 3 bits whose level changes are regarded as events.
reg [2:0] hi_ad;
assign {a18, a17, a16} = hLad;
Ilhi_ad groups together high-order address lines.

II 16-Bit, mux mode, ale is used.

11+++++++++++++++++++++++++++++++++++++++++++++++
/1--> Starting Point of Stimulus File <--

11+++++++++++++++++++++++++++++++++++++++++++++++
initial
begin
wr = 1; rd = 1; clkin = 0;
reset = 0; csi = 0; adio ='hOOOO;
bhe = 1; cnt4 = Z; wstc = Z;
wdout = Z; hi_ad = 0;

IId4 - dO have a value of 29
din = 29;
IIMc2tmrO pulses create timer-O events on their low-to-high transitions.
II mc2tmrO = event1 & !event2 + !event3,
II according to the ABEL description.
evenUn =7;
load = 0; Illnitialize the down-counter to no-load
cntout_en = 1; IIcnt4 is tri-stated
#500 reset = 1;
!/Initialize the part to power-saving mode. Write 38H to the PMMRO reg:
IIDisable clkin from the PLD-AND array, put PLD in non-turbo mode, EPROM in
IICMISER mode.

-3-.2-3-2---------------------------------~~~-------------------------------------

PSD4XX/5XX Design TUtorial - Application Note 031

Stimulus
File
tutor.s"
(Cont.)

//Invoke the task with the right parameters
#10
write (pmmrO,bhe_off,'h38); //Byte-Iow write operation

IITimer-O data initialized to 0
write (cntrO,bhe_on,clear); /NJord-write operation
IILoad down-counter with 29, enable cnt4 to output pin
load = 1; cntouCen = 0; II Counter starts
#32 load = 0; IIEnd of load pulse, load duration is a clock cycle
IIClear IMGO high & low byte registers
write (imgO,bhe_on,clear); /NJord-write operation
IIread-back data on IMGO reg
read (imgO); /NJord-read operation
IIWriting DLCY data. Timer Clock is the clock input (clkin) frequency
IIdivided by 7.
write (dlcy,bhe_off,3); IIByte-write operation
IIWriting CMD-O data to configure Timer-O
/NJrite Data of 6:

110
111
1/1

/IX
/IX
II
II

110
110
110

Event Count mode/waveform
Increment mode
Enable Timer_O
Timer output active level (don't care - no timer output)
Determines whether the timer increments on
the rising or falling edge of the PIN. Since Macroceli is
selected, this is a don't care bit.
Trigger(=load/store) from Macroceli, not from pin
Enable trigger command from macroceli
Enable/Disable by MACROCELUPIN
write (cmdO,bhe_off,6); IIByte-write operation

//Issue another load down-counter pulse.
II Load counter with 26, enable cnt4 to output pin
din =26; load = 1; cntouCen = 0;
#32
load = 0;
I/Global Reg data written to
#200
write (global,bhe_off,6); IIByte-write operation
/NJrite Data of 06h, no clock division, Event Count mode/Time Capt mode

1/ d4 - dO have a value of 31, load down-counter
din = 31;
load = 1;
#32 load = 0; IIEnd of load pulse

-------------------------------------~~~------------------------------------3-233

PSD4XX/SXX D.'gn TutDllal - Application Not. 031

Stimulus
File
tutor.stl
(CDnt.)

II Timer starts counting here I
II Create events. Note that their width is not important.
II Timer-O increments on every low-to-high transition of
II the mc2tmrO PPLD signal.
#40 evenUn = 1;
#30 evenUn = 7;
#290 evenUn = 1;
#30 evenUn = 7;
#290 evenUn = 1;
#30 evenUn = 7;
#290 evenUn = 1;
#25 evenUn = 7;
#365 evenUn = 1;
#22 evenUn = 7;

IICreate 1st event
IICreate 2nd event
IICreate 3rd event
IICreate 4th event

IICreate 5th event

II Write to Freeze Command Reg data
#240

write (freeze,bhe_off,freeze_on); IIByte-write operation

II Create 6th event. It occurs together with the issuance of a freeze command.
evenUn = 1;
#24 evenUn =7;
II Create more events, the timer continues counting while IMGO is frozen.
#365 evenUn 1; IICreate 7th event
#30 evenUn 7;

=
=

II read data on Status reg, verify that freeze_ack is high
read (status); IIByte-High read operation
II read data on IMGO reg since the counter is frozen.
read (imgO); IIWord-read operation

#61

evenUn = 1; IICreate 8th event
evenUn = 7;

II Write to Unfreeze the Freeze Command Reg data
#700

write (freeze,bhe_off,unfreeze); IIByte-write operation

~~~------------------------

3-234

_______ '~ArjF~ _____________________________________
ilHfs II

PSD4XX/5XX Design Tutorial - Application Note 031

Stimulus
File
tutor.stl
(Cont.)

//----------------MEMORY TESTS

II

//----------------IISetting up address 8476h of SRAM
write (sram_loc,bhe_on,'h5A27); //Word-write operation
IIread data of EPROM location 39FEh, esO is active
read (esJoc1); //Word-Read operation
IIExpect 0123h on data bus
IIread data of EPROM location 146Ch, esO is active
read (es_loc2); //Word-Read operation
IIExpect 0123h on data bus
IISetting up address COEOh of Page-Reg. Write #9 to it.
write (page,bhe_off,page9); IIByte-write operation
IIread data of SRAM location 8476h
read (sram_loc); //Word-Read operation
IIExpect 5A27 on the data bus
#20 din = 12; II Change din to 12
#10 load = 1; IILoad 12 to down-counter
#32 load =0; lIend of down-counter load

IIread data of Page-Reg. location COEOh
read (page); //Word-Read operation
IIExpect 9 on the low order byte of data bus
IIRead data of EPROM location 39FOh, es1 will be selected( based on page 9)
read (es_loc3); IIByte-high read operation
IIExpect 45 on 015-08
IIRead data of EPROM location 146Ch, es1 will be selected
read (es_loc2); //Word-Read operation
IIExpect 4567h on 015 - 00
end

IIGenerate a continuous clock signal
always
#16 clkin = -clkin;

-----------------------------------~~~-------------------------------3~-~23~5~

PS04XX/5XX Design Tutorial - Application Note 031

Files
For Other
Bus
Structures

PSD5XX/4XX
Architecture
Overview

Included in the Examples subdirectory is a set of .abl, .glc and .stl files for four design
examples. These designs are similar to the tutorial design example except for the bus
interface configuration. More examples will be included later.
The following is the current file list:

mux8.abl
mux8.stl

ABEL file for 8-bit multiplexed bus
Stimulus file for mux8.abl

nmux8.abl
nmux8.stl

ABEL file for 8-bit non-multiplexed bus
Stimulus file for nmux8.abl

nmux16.abl
nmux16.stl

ABEL file for 16-bit non-multiplexed bus
Stimulus file for nmux16.abl

m683xx.abl
m683xx.stl

ABEL file for Motorola 683XX type bus
Stimulus file for m683xx.abl

The PSD5XXJ4XX devices are new members of the Field Programmable Microcontroller
Peripheral product line from a WSI. The PSD5XXJ4XX devices provide advanced features
such as a complex ZPLD, Timer/Counters, Interrupt Controller, Page Logic, and expanded
I/O Ports to greatly enhance the performance of virtually any microcontroller.
The PSD5XXJ4XX also replaces the basic building blocks in embedded designs. These
include the EPROM block, SRAM, decoders, address latches, I/O Ports and other discrete
components. Two of the advantages of the PSD5XXJ4XX are the flexibility and
programmability of the part. Chip functions can be modified or changed by reconfiguration
or by redefining the ZPLD logic equations.
Because of its flexible configuration options, the PSD5XXJ4XX is able to interface to a wide
range of microcontrollers or microprocessors.

PSD5XX/4XX
Architecture

Figure 5 is the top-level block diagram of the PSD5XX/4XX. The PSD5XXJ4XX consists of
the following main functional blocks and features:
Q Bus Interface
Q ZPLDSlock
Q Memory Block

Q I/OPorls
Q Counterff/mer and Inte"upt Controller Block (PS05XX only)
Q Power Management
Q Chip Security

Q PageLog/c
Q Per/pherall/O Mode
All the functional blocks are connected to the internal Address and Data bus. The Data Bus
is 8- or 16-bit, depending on the PSD5XXJ4XX configuration. The Address Bus width is
variable and is defined by the user. The ZPLD (Zero Power PLD) has its own input and
output buses. The GPLD (General Purpose PLD) and PPLD (Peripheral PLD) can operate
by themselves and be independent from the microcontroller.
During normal bus cycles, the Decoding PLD (DPLD) monitors the Address Bus and
determines if any of the PSD5XXJ4XX internal devices should be selected and enabled.
All the internal blocks can be accessed by the microcontroller, including the output of
macrocells in the ZPLDs.

-----------------------------------,~~~~----------------------------------3-236
!i"lii!'_ =

~

ciS'

ADDRE~ATNCONTROlBUS

§!
CD

I

......~:EI

II~"

~~.#N
mmtmm7"

,_'.;-_

PF-·_··-_u

I

POWER
VSTDBY
MGR...........- UNIT

,"""M 1.1:

IlLlnt
1U111,

I-II~

PDO-PD7

&I

2!
g
~

I I ~ IPORTA

ZPLD
INPUT
BUS

...

~II..

;g

i~

II

60

I I • I

PI

·I.~

!::I

S'

1!!

PROG.
PORT
PORTB

PROG.
PORT

I PED-PE7

,"oJ] 1.1 -: . . . ~<~._.L,~l II .''0""
GLOBAL

CONRG.
AND
SECURITY

I

~

r

liS'
:Ii

...S'

i

I

~

ClKIN
'TIMERIINTERRUPT BLOCK
AVAILABLE IN PSD5XXX ONLY

Co>

~

~

WATCH DOG OUTPUT

I

I=
If
2....

PSD4XX/5XX DflSlgn 'Mor'.' - Appl/m/on lot. 031

PSD5XX14XX
Archltectute
{Cont.}

Bus Interface
The PSD5XXl4XX can interface to many microcontrollers or microprocessors. The Bus
Interface is user configurable, and is able to support many types of bus structures.
Figure 6 shows the interface between the PSD5XXl4XX and a processor with a 16-bit
multiplexed address/data bus (ADO-AD15). The AD bus from the processor connects
directly to the ADIO port on the PSD5XXl4XX. The Bus Interface latches the address lines
at the falling edge of the ALE signal. Data is driven onto the AD bus in a read bus cycle.
Bus control signals (RD/, WRI, and so on) from the processor also connect directly to the
PSD5XX14XX with no gluelogic.
For processors that have non-multiplexed buses, the bus interface configuration requires
that the address bus connect to the ADIO port, while the data bus goes to Port C and Port
D, depending on the bus width.
The data ports of the PSD5XX14XX are in tri-state mode if none of the internal devices are
selected.

Figure 6. Bus Interface Connection
PSD5XX
AD[7:0]

~

AD[15:5]

ADIO

f-~

PORT

f-MICROCONTROLLER

..

WRI
RDI
RSTI
CSI

BHE!

PORT
C

~

~

~

•

PORT

0

PORT
A

-

ALE PORT PORT
B
E

• .• •

~--------------------'.'~,~----------------------3-238
.,.."J

PSD4XX/SXX Design TUtorial - Application

PSD5XX/4XX
Architecture
(Cont.)

'ot, 031

ZPLDBIock
The ZPLD Block consists of three embedded ZPLDs: the DPLD, GPLD, and PPLD.

o

DPLD

The Decoding PLD (DPLD) generates select signals to internal 1/0 devices, EPROM
blocks, and SRAM. The DPLD has 61 inputs and 8 outputs. Each output has one product
term.

o

SPLD

The General Purpose PLD (GPLD) provides up to 24 programmable macrocelis for general
or complex logic implementation. The GPLD shares the same input bus as the DPLD. The
inpuVoutput of the 24 macrocelis are connected to 1/0 pins on Port A, B, and E. Figure 7
shows a macroceli circuit that is connected to Port B. Macrocelis connected to Port A and E
have similar circuitry.
The PSD4XXA2 has 16 macrocelis on Port A and B, while the PSD4XXA 1 has only eight
macrocelis on Port B, with eight combinatorial macrocelis on Port A.

o

PPLD

The Peripheral PLD (PPLD), which is available in the PSD5XX only, has six programmable
macrocells. The output of the macrocells are used as inputs to the Timer and Interrupt
Controller, which provide additional control over the operation of the Timers.
The three ZPLDs share the same input bus which consists of up to 61 signals. These
signals include the address lines and control signals from the microcontroller, the
Timerllnterrupt Controller outputs, the Page Logic outputs, and inputs from Ports A, B, C, D,
and E. Ports A, B, and E can also be configured as output ports for the GPLD's macrocells.
You can reduce the power consumption of the ZPLDs by turning the ZPLD Turbo bit off in
the Power Management Mode Register. In this mode, the ZPLD puts itself into standby
mode if none of the 61 inputs are switching for a period of 100 ns or more.

Figure 7. Port BMaclOcell Circuit
PT

PT

P LOE

,-----------------------------------------,
,
,

AND
ARRAY

PT~~P~B~I.C~L~R~------_4

PT~~P~BLI--~--_+--------_+--~

PBI.CLK
MACRO· fiST
CLKlN
NOTE:I.7TOO

INTERNAL
ADDRESSIDATA
BUS

-------------------------------',#Jr.~------------------------------rtfIIt!!., II
3.239

PSD4XX/SXX Design Tutorial - Application Note 031

PSD5XX/4XX
Architecture
(Cont.)

Memory Block
The PSD5XXl4XX Memory Block consists of two sections, EPROM and SRAM.

CJ EPROM
EPROM is used for program code and data storage. The EPROM consists of four separate
blocks, each having its own chip select signal defined by you through the DPLD. There are
three EPROM sizes, as follows:

.256 Kbits
.512 Kbits
.1 Mbit

CJ SRAM
SRAM supplements to the microcontroller's internal RAM. The SRAM has one
16Kbit block, which has a battery back-up mode.
Both the EPROM and SRAM can be configured as X8 or X16, depending on the data bus
width of the microcontrolier.

VOPorts
The PSD5XXl4XX has five 8-bit I/O Ports. Each port performs multiple functions and is
user-programmable. The port functions can be classified into three groups, I/O Ports to the
microcontroller, Address or Data Ports, and I/O Ports for internal PSD5XX devices.

CJ VO POrts to the Microcontrol/er
I/O Ports to the Microcontroller (Standard MCU I/O can be read or written to by the
microcontroller).

CJ Address or Data Ports
For microcontrollers with non-multiplexed buses, Port C is connected to the low byte
on the data bus and Port D is connected to tire high byte (Address Bus connects to the
ADIO Port).
Port A can also be used as input for the higher address lines (A 16 and up). These address
lines are included in the ZPLD input bus and are used in address decoding.
In applications where lower order address lines are needed for peripheral I/O devices, the
I/O Ports can be configured to provide latched address output.

-:-::-:-::-________________ !Fs. #5
3-240

',;.6=i!~

-----------------

1'SD4XX/5XX IItIslgn Tutorial - Appllt:at/on lIot. 031

PSD5XX/4XX
Architecture
(Cont.)

Q I/O Ports 'or Internal PSD5XX/4XX Devices
Ports C and D may serve as input ports for the GPLD, and Port A, B, and E may serve as
1/0 ports for the macrocells.
.
Ports A, B, and E may serve as 1/0 ports for the TimerlCounter and Interrupt Controller.
There are additional functions that are unique to each port. Port A has a Peripheral 1/0
mode which, if activated, allows Port A to serve as a transceiver on the microcontroller data
bus.
Figure 8 shows the pin structure and circuitry of an 1/0 pin on Port B. The PCR (Port
Configuration Register) controls the operation of the Port. As an output port, the MUX select
one of the four sources as an output. For Port B, these outputs are as follows:
Q Standard MCU 1/0
Q Latched address output
Q GPLD macrocelil/O
Q Timer output (Special Function)

As an input pin, the pin can be configured as an input to the ZPLD, or as an input for the
Standard MCU 1/0 mode. Other registers in the pin structure can be accessed by you
through the PDR (Port Data Register).

Figure 8. Pin Structure, Port B

110
WRI
ADDRESS
ALE

A [8-15]

INTERNAL
ADDRESS
/DATA
BUS

PORT B PIN

A [0-7] OR
MUX

GPLD • OUTPUT
SPECIAL FUNCTION
PBX.OE
ALE

PCR

1 + - - -....

PCR

GPLD·INPUT

WRI
DIR.REG.

-------------------------------~JI:~------------------------------3~1

--=

PSD4XX/5XX OtlSlgn TUtorial - Application Not. 031

I'SD5XX/4XX
Architecture
(Cont.)

CounterRimer and Interrupt Controller
The Countermmer block, which is available in the PSD5XX only, consists of four 16-bit
counters. All four counters run on the same input clock. The desired clock frequency (the
maximum input clock, CLKIN, is 30 MHz-the maximum counter/timer clock is 7.5 MHz) is
selected by programming the Clock Scaler with the proper divisor.
The Countermmers have five modes of operation:
Q Waveform Mode
Q Pulse Mode
Q Event Counter Mode
Q Time Capture Mode
Q WatchDog Mode
The mode of operation is specified through the Command Register. Figure 9 shows the
Countermmer and Interrupt Controller block diagram. The MUX selects the source of the
CounterlTimer control inputs. The control source can come from user software, external
inputs, or macrocell outputs from the PPLD. Outputs from the Countermmers in Waveform
or Pulse Mode are routed to Port A or B. WatchDog output, WDOG2PLD, needs to go to
the ZPLD before it can be taken to an I/O pin as a ZPLD output defined by you.
The Interrupt Controller provides a convenient way to manage a design with multiple interrupts. The Interrupt Controller accepts eight interrupt inputs, including four Terminal Counts
from the Countermmers, two from the macrocells and two from the AND ARRAY of the
PPLD. The PSD5XXl4XX does not have dedicated pins for external interrupt inputs. You
have to specify the input as ZPLD input on Port C or D in order to generate the proper
product term for the Controller.
Interrupt inputs can be either level or edge sensitive. The inputs are priority decoded,
where IR7 has the highest priority. The Controller also has the ability to mask out any
unwanted input.

Power Management
The PSD5XXl4XX has a Power Management Register that allows you to configure the chip
power consumption in real time. You may activate four power saving options.
Q Power Down Mode
In this mode, the PSD5XXl4XX automatically puts itself into power-down mode if the
microcontroller is inactive. You can also put the PSD5XX14XX into power-down mode by
deselecting the chip select input (CSI) pin.
Q

S/eepMode

Once in the Power Down Mode, the PSD5XXl4XX has the option to go into Sleep Mode.
The PSD5XXl4XX consumes less power but requires recovery time to get back to normal
operation.
Q EPROM CMISER Mode
This mode allows the PSD5XXl4XX to turn off the EPROM when it is not being accessed.
Q Zl'LD Turbo Mode
The PSD5XXl4XX's ZPLD saves power by turning off the Turbo bit. This adds 10 ns
additional delay to the ZPLD.
Through the Power Management Register, the input clocks to the ZPLD and
Countermmers can be turned off to save power due to AC activity.
~~----------------------

3-242

______ "IAF~________________________________
"",4118

PSD4XX/5XX ODslgn Tutorial - Application NotD 031

PSD5XX/4XX
Architecture

Figure 9. Counterflimer and Interrupt Block

{Cont.}

TIMER[3:0] • IN

PT(8)

nMERI
COUNTER
(4)

nMER·OUTO
nMER·OUT1
nMER·OUT2
TIMER·OUT3
TC[3:0]

WDOG2PLD
PT
PT

AND
ARRAY

PT21NT4
PT2INT5
MC21NT6
MC2INT7

PT(4)

INTR2PLD

Chip Security
The PSD5XXl4XX has a programmable security bit that offers protection from unauthorized
duplication. When the security bit is active, the contents of the EPROM, ZPLD fusemap,
and nonvolatile configuration bits are prevented from being read by an EPROM
programmer. If a special decoding technique is implemented, it will also prevent the codes
from being disassembled by Emulators.

Page Logic
For microcontrollers with limited addressing capability, the PSD5XXl4XX provides a four-bit
Page Register that increases the memory space by a factor of 16. Outputs from the Page
Register are available as inputs to the ZPLD for decoding purpose.

Peripheral I/O Mode
The Peripheral I/O Mode is available on Port A only. In this mode, Port A acts as a tri-state
transceiver on the microcontroller data bus. The enable and directional control signals to
the Port are defined in the DPLD.

---------------------------------------,jfjf~~--------------------------------------5l':i!liiE •
3-243

'SD4XX/5XX D.'gn 'MII".' - AppllClltlllR lilt. 031

________________________ '88';_______________________
3.244

'fINI1 &

Programmable Peripheral
Application Note 033
Keypad Interface to PSD4XX/5XX
with Autoscanning
By Ching Lss

Introduction

The integration of complex PLD and I/O functions in the PSD4XXl5XX is well suited to the
implementation of I/O interface logic such as a keypad controller. This application note
describes how to take advantage of this PSD4XXl5XX feature to design an efficient and
power saving keypad interface.

Typical
Keypad
Interface

A keypad consists of a matrix of pressure or touch activated switches. Figure 1 shows a
typical keypad interface using a PIO (parallel I/O) chip. It is assumed that the keypad has
internal pull ups for the rows and columns. The keypad has 25 keys, and is arranged in a 5
(row) x 5 (column) matrix. In this example, Port B is configured as an output port
(PBO - PB4) and driving logic "0" to the 5 row inputs of the keypad. Port A is configured as
an input port (PAO - PA4). PAO - PA4 are normally pulled high by internal keypad resistors
until one of the keys is pressed. For example, if key [3,1] (row 3, column 1) is pressed, then
the "0" on PB3 is passed through the closed switch to column 1.

Figure 1. Keypad Interface

COLUMN SENSING
PORTA

AO
r PA4

MICROCONTROLLER

-

PARALLEL
VOCHIP
ROW SCANNING
PORTB

rBO

ROWO

~

PB4fl1
ROW4
COLO

COL4

5X5 KEYPAD

3-245

'SlUXX/5XX - Application Not. 033

Typical
Keypad
Interface

Detection of the key closure usually involves the following steps:

o

The microcontroller program continues to poll Port A to determine if any of the inputs are
low. If data on Port A is switched from "1F" (no keys are pressed) to "17" (PA3 is low).
the microcontroller can then identify that one of the keys in column 1 is pressed.

o

To eliminate erroneous read due to key switch bouncing. the software executes a
delay routine and reads Port A again after the column inputs are stable.

o

After a key closure from column 1 is detected. the microcontroller reverses the
direction bits of Port A and Port B. Now Port A acts as an output port and Port B as an
input port. Port A drives back "17" to the column inputs.

o

The microcontroller then reads Port B which acts as an input port for the rows. If it
reads "17" (PB3 is low). then it can identify that the key common to row 3 and column 1
(key [3.1]) is pressed. This can be done through a look up table.

(Cont.)

This keypad interface technique can also be implemented in the PSD4XXJSXX by
connecting the rows and columns to the I/O ports as described above. The microcontroller
must be always active and must keep on polling the Ports for keypad input.

AMore
Efficient
Keypad
Interface
Implementation

The major overhead of the above keypad interface is:

o

The microcontroller must poll the port at a fixed frequency. thus reduce the processor
performance.

o

The microcontroller must remain active and consumes power even when the keypad
is idle.

A more efficient way of interfacing to a keypad which reduces the above overhead is
described here. The PSD device will perform the interface function automatically by:

o

Implementing a hardware debounce circuit in the GPLD of the PSD4XXJSXX. replacing
software debouncing.

o

Implementing a state machine in the GPLD to scan the rows of the keypad
automatically. replacing software polling.

o

Setting Port A as a column input port and Port B as a scan output port.

o

Generating an interrupt to the microcontroller only when a key is pressed.

The concept of this design is shown in the block diagram in Figure 2. The block diagram
shows only the 1/0 Ports and GPLD portion of the PSD4XXJSXX which are used in the
keypad interface. The following paragraphs describe the PSD configuration and GPLD logic
function.

-~-Z-~6----------------------------~~Jr-------------------------------

PSD4XX/5XX - Application Not. 033

AMo"
E"'c/ent
Keypad
Interface
Implementation

Figure 2. PSD ImplementatlDn
PSD4XXISXX
TO
PROCESSOR

(Cont.)
CLKIN

DATA [0-7]

Lr~ ,I DEBDUNCE

I CIRCurr

11
PORTA
BUFFER

PORTB
BUfFER

FREZ

;--

~TDINTR
CONTROLLER
OR PROCESSOR
GPLD

L::::

PSD

lID Po"

Configuration

STATE
MACHINE

COLUMN SENSING

PAO
PAl
PM
PA3
PA4
S
T
A
T
E
4

I---

t--

r-

PBO
PB'
PBZ
PB3
PB4

S
T
A
T
E
3

S
T
A
T
E
Z

S
T
A
T
E

s

T
A
T
E
0
0

, ,, ,, ,, ,,
, , ,, ,
1

1 1

ROWO

0

1
0
1 0

0

ROW4

ROW SCANNING
STATE MACHINE
COLO

COL 4

SX5KEYPAD

Port B is configured as an output port for the GPLD. Outputs of the scanning state machine
are routed to Port B and are connected to the row inputs of the keypad. The outputs of the
state machine can be read by the microcontroller via the Port B Buffer (Data In Register or
Macrocell Out Register).
Port A is configured as an input port for the GPLD and is connected to the column outputs
of the keypad. The column outputs can also be read by the microcontroller via the Data In
Register of Port A.

BPLD

Logic
Implementation

The GPLD implements both a debounce circuit and a scanning state machine. Both
functions can be fitted in the PB macrocells and can run on the same input clock (clkin).
The state machine is clocked by the rising edge of clkin, while the debounce circuit uses
the falling edge of clkin.

-----------------------~Jr;-----------------------3·247

PSD4XX/5XX - Application Note 033

The
Debounce
Circuit

The bounces on the keypad column outputs due to switch opening/closing can lead to an
erroneous result. The debounce circuit performs two functions:

o

Generates a "freeze" signal when a key is pressed. This signal, frez, is used to stop the
state machine until the key is released. The ABEL equation is
frez := !(coIO· col1 • col2· col3· coI4);

o

Generates an interrupt, "intr", to the microcontroller when the column outputs stay low
for two (or more) consecutive clocks. This is to ensure that the inputs are stable before
interrupting the microcontroller. The ABEL equation is
intr := frez • ! (colO. col1 • col2 • col3 • coI4);

The clock input to the debounce circuit can be derived from the system clock, but the clock
period should be larger than the switch bounce time.

The Scanning
State Machine

The state machine does the keypad scanning by sending a "running 0" pattern to the row
inputs at the rising edge of the input clock via Port B. For a 5 row keypad, the "running 0"
patterns at each clock are:

Clock

Row 0

Row 1

Row 2

Row 3

Row 4

1

0

1

1

1

1

2

1

0

1

1

1

3

1

1

0

1

1

4

1

1

1

0

1

5

1

1

1

1

0

6

0

1

1

1

1

7

1

0

1

1

1

The pattern is repeated every five clocks. The sequence of events when a key [3,1] (row 3,
column 1) is pressed at clock 2 are:

o
o
o

o
o
o
o
o

o

At clock 2: Key [3,1] is pressed. The "0" in the pattern (row 1) is not passed to column
1 output.
At clock 3: The "0" in the pattern (row 2) is not passed to column 1 output.
At clock 4: The "0" in the pattern (row 3) is passed to column 1 output via the
closed/pressed key [3,1].
At the falling edge of clock 4, the "0" causes the debounce circuit to generate the "frez"
signal and freezes the state machine.
At the next clock, if column inputs are stable and remain low, the deb ounce circuit
generates an interrupt which wakes up the microcontroller.
The microcontroller reads Port A. The column inputs are "17h" which indicates a key in
column 1 was pressed.
The microcontroller reads the output of the state machine ("running 0" pattern). The
value is "1 Dh". This indicates a key in row 3 was pressed.
By using a look up table, the microcontroller identifies the pressed key to be key [3,1].
The microcontroller puts itself back to power down/sleep mode.
The state machine remains in a stop condition until the pressed key is released. After
the key is released, the state machine returns to generating the "running 0" pattern.

-3--2-~-8---------------------------------~~~------------------------------------

PSD4XX/SXX - Applicatilln Nllt. 033

The Scanning
State Machine
(Clint.)

The state machine has 5 states and you can assign the "running 0" pattem as the state
value. The operation of the state machine, including the debounce circuit, is described in
ABEL as follows:
'
"state values (running 0 pattern)
sreset = AbOOOOO;
scanrO = Ab11110;
scanr1 = Ab111 01;
scanr2 = Ab11011;
scanr3 = Ab10111;
scanr4 = Ab01111;
frez:= !(coIO * col1 * col2 * col3 * coI4); active high
intr := frez * !(coIO * col1 * col2 * col3 * coI4); active high
"frez is active when key is pressed
rowreg.c = clk;
rowreg.re = !rst;

"scanning clk = clk
"clear registers at reset

state_diagram rowreg;
state sreset:
state scanro:
state scanr1 :
state scanr2:
state scanr3:
state scanr4:

goto scanrO;
if Ifrez then
if !frez then
if Ifrez then
if !frez then
if !frez then

scanr1
scanr2
scanr3
scanr4
scanrO

else
else
else
else
else

scanrO;
scanr1;
scanr2;
scanr3;
scanr4;

"if no frez, state machine runs continuously

Implement
The Keypad
Interface
In The
PS04XX/5XX

This Keypad design can be implemented in any of the PSD4XXl5XX devices. There are
two ways to implement the keypad row scanning function:

o

Use the state machine as described above. This approach is restricted to a keypad with
a few rows. As the number of rows increase, the number of product terms required by
the state machine also increases and soon there will not be enough product terms. The
ABEL file which defines the GPLD logic function of this implementation, keya.abl, is
shown in Appendix A.

o

Use a circular shift register to generate the "running 0" pattern instead of a state
machine. The shift register needs only one product term per output and can interface to
keypads with large row counts. During reset, the register is seVpreset with the
"running 0" pattem (11110). After reset, the "0" in the pattern is shifted and repeated
between the row inputs. The clock input to the shift register is "anded" with the frez
signal and will stop shifting after a key is pressed. The ABEL file of this implementation
is shown in Appendix B.

A stimulus file, keypad.stl, which simulates the keypad operation is included in Appendix C.
The stimulus file shows the steps required to set up Port A and the reading of column and
row values by the microcontroller after a key is pressed.
The PSD4XX15XX frees up valuable 110 ports on the microcontroller, and off-loads
some of the keypad software overhead. The resulting design allows better utilization of
microcontroller resources.

---------------------------~Jrjf------------------------3-4--~

1'SD4XX/5XX - AppllClltlon Note oal

AppBndlxA.
KEYA.ABL
File

module keya
title 'test:keyboard autoscanning, 80C196 bus interface';
"Input signals
colO, col1, col2, col3, col4 pin 27,26,25,24,23; "key bd column inputs
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
clkin, rst pin 42, 40;
"PLD output signals.
csiop, rsO, esO, es1 , es2, es3 node;
intr pin;
frez node;
nclkin node;

"More outputs using reserved names.
"key board interrupt
"reverse of clkin

rowO, row1, row2, row3, row4 pin 50,49,48,47,46; "row scanning outputs
rowO, row1, row2, row3, row4 is type 'buffer, reg_d';
"Definitions
rowreg = [row4, row3, row2, row1, rowO];
"state values
sreset
scanrO
scanr1
scanr2
scanr3
scanr4

=
=
=
=
=
=

"b00000;
"b11110;
"b111 01;
I\b11011;
"b1 0111 ;
"b01111;

c = .c.; " Clock pulse definition
X = .x.; " Don't care
Address =[a15,a 14,a13,a12,a11,a1O,a9,a8,X,X,X,X,X,X,a1,aO];

-~-2-50-----------------------------

.,.-------------------------------rII'~

PSD4XX/SXX - Application Not. D33

AppendixA.
KEYA.ABL
File
(Cont.)

equations
csiop = (Address >= I\hOCOOO) & (Address <=l\hOCOFF); "256 block
rsO = (Address <= I\h087FF) & (Address >= I\h08000); "2k block
esO = (Address <= I\h01 FFF) & (Address >= I\hOOOOO); "32KB block
frez
intr

:= !(coIO * col1 * col2 * col3 * coI4); "active high frez
:= frez * ! (colO * col1 * col2 * col3 * coI4); "active high intr

"intr is active when key is pressed
nclkin
frez.c
rowreg.c
frez.re
rowreg.re

=
=
=
=
=

!clkin; "reverse clkin for debounce circuit
nclkin; intr.c = nclkin;
clkin; "scanning clk = clkin
!rst; intr.re = !rst;
! rst; "reg. clear input

state_diagram rowreg;
state sreset:
state scanrO:
state scanr1:
state scanr2:
state scanr3:
state scanr4:

goto scanrO;
if !frez then
if !frez then
if !frez then
if Ifrez then
if !frez then

scanr1
scanr2
scanr3
scanr4
scanrO

else
else
else
else
else

scanrO;
scanr1;
scanr2;
scanr3;
scanr4;

"if no interrupt, state machine runs continously
tesevectors
([clkin,
[ c,
[ c,
[ c,
[ c,
[ c,
[ c,
[ c,

rst, colO, col1, col2, col3, col4] -> [rowO,
0,
] -> [ 0
0,
] -> [ 0
1 ,
] -> [ 0
1
] -> [ 1
1 ,
] -> [ 1
1
]-> [ 1
1 ,
] -> [ 1

"key (1,1) is pressed/closed
[ c,
1 , 1 , 1 , 1 , 1 ,
[ c,
1 , 1 , o , 1 , 1 ,

row 1,
0
0
1
0
1
1
1

row2,
0
0
1
1
0
1
1

row3,
0
0
1
1
1
0
1

row4,
0
0
1
1
1
1
0

intr])
1 ];
1 ];
1 ];
1 ];
1 ];
1 ];
1 ];

] -> [ 0 , 1 , 1
] -> [ 0 , 1
1

, 1
];
, 1 ,0 ];
"column (coI1) detects key is pressed, intr is generated. Scanning stops
"until intr goes away
1 , 1
[ c,
0
, 1 ,
] -> [ 0 ,
1
1
1 ,0 ];
[ c,
1
1
0
1
] -> [ 0
1
1
1 ,0 ];
[ c,
1 , 1
0
, 1 ,
]-> [ 0
, 1 , 1 , 1 , 0 ];

"MCU reads column inputs and scanning outputs, determined key (1,1) has been
"closed. Later key (1,1) is released, intr becomes inactive and scanning resumes
1, 1 , 1 , 1 , 1 , 1 ] -> [ 1 , 0 , 1 ,1
1, 1 ] ;
[ c,
1, 1 , 1 , 1 , 1 , 1 ] -> [ 1 , 1 , 0 , 1 , 1 ,1] ;
[ c,

END

_II!!.

-----------------------------~~~----------------------------3.251

PSD4XX/SXX - ApplicatIon 1I0t. 033

AppendixB.
KEYB.ABL
File

modulekeyb
title 'test:keyboard autoscannlng, 80C196 bus interface';
" Input signals
colO, col1, col2, col3, col4 pin 27,26,25,24,23; "column inputs, Port A
"Address lines, using reserved names.
a15,a14,a13,a12,a11,a10,a9,a8,a1 ,aO pin;
clkin, rst pin 42, 40;

.. PLD output signals.
csiop, rsO, esO, es1, es2, es3 node;
intr pin
frez node;
nclkin node;
rowO, row1, row2, row3, row4 pin 50, 49, 48, 47, 46;
rowO, row1, row2, row3, row4 is type 'buffer, reg_d';

"More outputs using reserved names.
"key board interrupt
"reverse of clkin
"row scanning outputs

" Definitions
rowreg = [row4, row3, row2, row1, rowO 1;
c
= .c.; " Clock pulse definition
= .x.; "Don't care
X
Address [a15,a14,a13,a12,a11 ,a 10,a9,a8,X,X,X,X,X,X,a1 ,aO 1;

=

equations
csiop
rsO
esO
es1

=
=
=
=

(Address
(Address
(Address
(Address

>=
>=
>=
>=

AhOCOOO)
Ah08000)
AhOOOOO)
Ah02000)

&
&
&
&

(Address
(Address
(Address
(Address

<=
<=
<=
<=

AhOCOFF);
Ah087FF);
Ah01 FFF);
Ah03FFF);

"256 block
"2k block
"8KB block
"8KB block

frez := ! (colO * col1 * col2 * col3 * coI4); "active high frez
intr := frez * I (colO * col1 * col2 * col3 * coI4); "active high intr

"frezlintr is active when key is pressed

~~

3.252

________________________

~-s

~_rr,------------------

1'SD4XX/5XX - Appl/t:IItlon Note 033

AppendlxB.
KEYB.ABL
File
(Com.)

nclkin
frez.c
frez.re
rowreg.c

= !clkin; "reverse clkin for debounce circuit
= nclkin; intr.c = nclkin;
=! rst; intr.re = I rst;
= clkin & !frez; "scanning clk = clkin if no frez

rowO.re = !rst
row1.pr = !rst
row2.pr
!rst
I rst
row3.pr
row4.pr
I rst

"set row registers initial value to 11110
"PSD macrocell has active high reset

rowO.d
row1.d
row2.d
row3.d
row4.d

"5-bit shift register
"shifting stops if frez is active

row4.q;
rowO.q;
row1.q;
= row2.q;
= row3.q;

"if no frez, shift register runs continously

tesCvectors
([clkin, rst, colO, col1, col2, col3, col41 ->
[c,
0, 1
1, 1
1, 1 1 ->
[c,
0, 1 , 1 , 1 , 1 , 1 1 ->
[c,
1 ,1
1
1, 1 , 1 1 ->
[c,
1 , 1 , 1 , 1 , 1 , 1 1 ->
[c,
1
1, 1 , 1 , 1 , 1 1 ->
[c,
1
1, 1 , 1 , 1 , 1 1 ->

[rowO, row1, row2, row3, row4, intr))
[0
1
1
1
1 , 1 I;
[ 0 ,1 ,1 , 1 , 1 ,1 I;
[ 1 , 0 ,1
1
1 , 1 I;
[ 1 ,1 ,0
1
1 , 1 I;
[ 1 ,1 ,1 , 0 , 1 ,1 I;
[ 1 ,1 ,1 , 1 ,0 ,1 I;

"key (1,1) is pressed/closed
[c,
1 , 1 , 1 , 1 , 1 , 1 1 -> [ 0 ,
, 1 , 1
[c,
1 , 1 , o , 1 , 1 , 1 1-> [ 0 ,
1 , 1
"column (coI1) detects key is pressed, intr is generated. Scanning stops
"until intr goes away
[c,
1 , 1 , o ,
, 1 , 1 1-> [ 0 ,
, 1 , 1
[c,
1 , 1 , 0 ,
1 , 1 1 -> [ 0 ,
1
1
[ c,
1 , 1 , 0 ,
1 , 1 1 -> [ 0 ,
, 1
1

, 1 I;
,01;

,01;
,01;
,01;

"MCU reads column inputs and scanning outputs, determined key (1,1) has been
"closed. Later key (1,1) is released, intr becomes inactive and scanning resumes
[ c,
1, 1 , 1 , 1 , 1 , 1 1 -> [ 1 ,0 , 1 , 1 , 1 ,1 I;
[ c,
1, 1 , 1 , 1 , 1 , 1 1 -> [ 1 ,1 ,0 ,1 , 1 ,1 I;

END

------------------------~Jr;------------------------3-253

I'SII4XX/5XX - AppllestlDn NDt81133

Append/xC.

KEYPAD.STL

lIauto scanning simulation
IIstart scanning, press key, read port A (column) and port B (row)

'lie
11+++++++++++++++++++++++++++++++++++++++++++++++++
II Defining tasks to simplify the stimulus file

11+++++++++++++++++++++++++++++++++++++++++++++++++
task write (addcbus,bhe_value,data_in); 1/ 80196 write bus cycle
input [15:0] addr_bus;
input [15:0] data_in;
input bhe_value;
begin

#20

ale = 1; I/Latch the address lines
adio = addcbus; IISet-up the right address
bhe = bhe_value;
ale = 0; IIAle inactive

#20

adio = data_in; II Write operation

#20
#20

#40 wr = 0; II Write pulse
#100 wr = 1; II Write ends
#10 adio Z16; bhe Z;

=

=

end
endtask
task read (addr_bus);

1180196 read bus cycle

input [15:0] addcbus;
begin
#20
#20

=
=
=
=

1; l/Latch the address lines
addr_bus; IISet-up the right address
0;
0; IIAle inactive

#20

ale
adio
bhe
ale

#20

adio = Z16; II Float Address bus

#40 rd = 0; II Rd pulse
#100 rd = 1; II Rd ends
#10 bhe
Z;

=

end
endtask
reg [4:0] column;
assign {coI4, col3, col2, col1, colO} = column;
assign {row4, row3, row2, row 1, roWO} = row;
reg intr, frez;
initial

-.-~----------------------~~i-----------------------

PSD4XX/5XX - Application Note 038

Append/xC.
KEYPAD.Sn
File
(eont.J

begin
rst
wr
ale
adio
intr
clkin

= 0; /lgenerate reset
= 1; rd = 1; //initialize control signal
0; bhe
1;
= 16'bz; //initialize addr/data bus
= 'bz; frez = 'bz;
0; pdS
0; pd6 0; pd7 0; /lin it not used port pins
paS
0; pa6 0; pa7 0;
row
= S'bz;
column = S'b11111;
csl
= 0; /lset PSDSXX chip select low

=

=

=

=
=

#300 rst = 1;

=
=

=
=

/lafter SOOns, rst Inactive

/lwrite and read to the sram, verify bus interface is ok
write ('h8476,O,'hSa27);
/lread sram,word
read ('h8476);

I/Word-read operation

l/write Port A Control Register, configure Port as I/O
write ('hC002,1,'hff);

l/write Port A Direction Register, configure Port A as input
write ('hC006,1 ,'hOO);
#635 column = 'b11101;

IIpresskey(3,1) -- row3,column1
IIstate machine is freezed
llintr is generated to the MCU

IIMCU reads Port A Data In Reg. (column Inputs)
read ('hcOOO);
IIMCU reads Port B Macrocell Out Reg. (state machine row pattern)
read ('hcOOd);
#SOO column = 'b11111;

l/key is released
state machine resumes operation

end
always
#200 clkin = -clkin;

-----------------------~Jri---------------------3-255

1'SD4XX/5XX - Appl/ClltloR Not. 1133

~~------------------"I':_--------------------3-256
.",.111It

- ==iE
::' ==- ==

---

~~

~

-

:':===~==

~-~~-~====

----

----~

Programmable Peripheral
Application Note 035
How To Design With The
PS04XX/5XX ZPLD
By Dan Friedman

Abstract

The PSD4XX and PSD5XX programmable MCU peripherals both contain a Zero-power
PLD (ZPLD) array. Below are several tips, information and procedures for working with the
ZPLD.

Generate
Address A7-A2
as ZPLD Input

Address lines A7-A2 are not routed directly into the ZPLDs. They can be routed into the
ZPLD by configuring an I/O port to the Address Out Mode and routing these signals into the
ZPLDs. Listed below is the method of implementing this function.

For a Multiplexed MCU
In PSDabel define 6 inputs (Port C for example):
addr7, addr6, addr5, addr4, addr3, addr2 pin 10, 11, 12, 13, 14, 15;
I/O port pins 7-2 must be used. These input signals then can then be used in your logic
equations in PSDabel.
In the initialization software executed by the MCU;
Initialize Port C to the Address Out Mode by writing OOH (actually 0000 OOXX in
binary) to the Configuration Register. The default condition, after reset, of the
Configuration Register is OOH.
Write FFH (actually 1111 11 XX in binary) to the Direction Register.
The default condition, after reset, of the Direction Register is OOH.
The address signals A7-A2 will always appear on Port C7-2 and will be routed to the
ZPLDs.

For a Non-multiplexed MCU
Route Address lines A7-A2 to any unused I/O port pins.
In PSDabel define 6 inputs (Port A for example):
addr7, addr6, addr5, addr4, addr3, addr2 pin 10, 11, 12, 13, 14, 15;
These input signals then can then be used in your logic equations in PSDabel.
There is no software initialization. Any Port A I/O port pins can be used in this example.

3-257

PSD4XX/5XX - Application Note 035

Load Data
DT-DOto
Macfocel/s

On a multiplexed MCU, the data bus is not routed into the GPLD. This application note
discusses how to write data from the data bus on the MCU to the macrocells inside the
General PLD (GPLD) inside the PSD4XXl5XX parts. Three methods are discussed in
this application note. The detailed implementation of each of these methods can be found in
application note 034 called "Loading Data into the PSD4XXl5XX GPLD Macrocells". This
application note can be found on the WSI bulletin board. The file name is "appnote34.zip".

Method 1
The MCU writes the lower 4 bits of data into the 4-bit page register. It then writes to an
arbitrary address to generate a clock input to the macrocells to transfer the data
from the page register to 4 of the macrocells. The MCU repeats this process for the upper
4 bits of data.

Example: Transfer A5H from the MCU to 8 macrocells (Port B) inside the GPLD. Assume
CSIOP is defined from 2000H to 20FFH. Assume the arbitrary addresses the macrocells
are mapped into are 21 OOH to 21 FFH and these 256 bytes are used for this address range
because the resolution of address decoding is 256 bytes. This address range cannot be
used by anything else in the system.

Step 1:
The MCU will write X5H to memory location 20EOH. This is the location of the page register
inside the PSD4XX and PSD5XX devices. "X" address means "don't care".

Step 2:
The MCU will write XXH (don't care condition) to memory location 2100H. This will
generate a clock input to the macrocells (clock defined as "Ah21 00 & !wr") and will transfer
the 4 bits of data in the page register to the four least significant bit macrocells.

Step a:
The MCU will write XAH to memory location 20EOH.

Step 4:
The MCU will write XXH to memory location 2101H. This will generate a clock input to the
macrocells (clock defined as "Ah21 00 & !wr") and will transfer the 4 bits of data from the
page register to the most significant bit macrocells.

Step 5:
The value of the Port B Macrocells can be read from the Macrocell Out Register of
Port B at 200DH.

-3--2-S-8---------------------------------~~~-------------------------------------

PSIJ4XX/5XX - Appllcatllln Nllt. 035

Load Data
D7-DOto
Macrocel/s
{Clint.}

MethDd2
The processor will write data to an 1/0 port. The data on the 1/0 port will be routed back into
the GPLD and latched into the macrocells. No external signal routing is required to route the
output port back into the GPLD. The MCU will write the data to an 1/0 port. The data is
transferred to the macrocells when the MCU generates a clock input to the macrocells by
writing to an arbitrary address.

Example: Transfer A5H from the MCU to 8 macrocells (Port B) inside the GPLD. Assume
CSIOP is defined from 2000H to 20FFH. Any 1/0 port can be used on the PSD4XXA2 and
the PSD5XXB1. On the PSD4XXA 1, Ports A or B must be used. Port C will be used in this
example. Assume that the arbitrary address that the macrocells are mapped into is from
2100H to 21 FFH. 256 bytes are used for this address range because the resolution of
address decoding is 256 bytes. This address range cannot be used by anything else in the
system.

Step 1:
The MCU writes FFH to memory location 2012H to the Control Register. This will change
Port C to the MCU 1/0 Mode.

Step 2:
The MCU writes FFH to memory location 2016H to set Port ClIO port pins to all outputs.

StepS:
The MCU writes A5H to memory location 2014H to latch the data out on Port C.

Step 4:
The MCU generates a clock input (defined as "l\h2100 & !wr") to the macrocells by writing
XXH (don't care condition) to memory location 2100H to latch the data on Port C to the
internal macrocells in Port B.

StepS:
The value of the Port B Macrocells can be read from the Macrocell Out Register at 200DH.

------------------------------~Jr~-----------------------------3-259

PSD4XX/5XX - Application Nots 035

LoadOata
07-00 to
Macrocel/s
(Cont.)

Method 3
This method will use the individual Preset and Reset signals from Port B to initialize
(or load) data into the Port B Macrocells. An active Preset will load a logical "1" into the
corresponding macrocell and an active Reset will load a logical "0". Each Preset/Reset
occupies an address and is activated when the MCU writes to that address.

Example: Transfer ASH from the MCU to 8 macrocells in Port B. Assume Preset/Reset of
the macrocells occupy address 2100H to 24FFH. For example,
PB7.RE ="h2402
PB6.RE ="h2400
PBS.RE ="h2302
PB4.RE ="h2300
PB3.RE ="h2202
PB2.RE ="h2200
PB1.RE = "h21 02
PBO.RE = "h21 00

&
&
&
&
&
&
&
&

!WR
!WR
!WR
!WR
!WR
!WR
!WR
!WR

PB7.PR ="h2403
PB6.PR ="h2401
PBS.PR ="h2303
PB4.PR ="h2301
PB3.PR ="h2203
PB2.PR ="h2201
PB1.PR = "h21 03
PBO.PR = "h21 01

&
&
&
&
&
&
&
&

!WR
!WR
!WR
!WR
!WR
!WR
!WR
!WR

Step 1:
The MCU writes XXH (a don't care condition) to 2403H. This will set Port B Macrocell PB7
to a rogic 1.

Step 2:
The MCU writes XXH (a don't care condition) to 2400H. This will set Port B Macrocell PB6
to a logic O.

Step 3:
The MCU writes XXH (a don't care condition) to 2303H. This will set Port B Macrocell PBS
to a logic 1.

Step 4:
The MCU writes XXH (a don't care condition) to 2300H. This will set Port B Macrocell PB4
to a logic O.

Step 5:
The MCU writes XXH (a don't care condition) to 2203H. This will set Port B Macrocell PB3
to a logic O.

Step 6:
The MCU writes XXH (a don't care condition) to 2200H. This will set Port B Macrocell PB2
to logic 1.

Step 7:
The MCU writes XXH (a don't care condition) to 2103H. This will set Port B Macrocell PB1
to a logic O.

StepS:
The MCU writes XXH (a don't care condition) to 2100H. This will set Port B Macrocell PBO
to a logic 1.

Step 9:
The value of the Port B Macrocells can be read from the Macrocell Out Register at
location 200DH.
The method best to use depends on the resource still available after implementing the rest
of the design. If speed is critical, Method 2 will execute the fastest. One write cycle can be
achieved by using Method 2 and routing the data bus to the 1/0 Port.

------------------------------_____
rE~~~----------------------------------3-260
====

PSD4XX/5XX - Application Note 035

Use a MacIoce"
to Latch External
Data/Status
and Read with
anMCU

When the 1/0 ports are configured as an input port in the MCU 1/0 Mode, the input pins are
sampled by the MCU. In some designs it is desirable to latch the data. This data is latched
by an external strobe signal. The GPLD macrocells can be used to latch data from an
external source with an external strobe signal and have the MCU read this latched data.
In the PSDabel file specify the following:
module example
"input data
din7, din6, din5, din4, din3, din2, din1, dinO pin;
"data flip-flops containing the latched data in
data7, data6, data5, data4, data3, data2, data1, dataO node istype 'reg';
"strobe or clock signal to latch the data into 8 macrocells.
strobe pin;
"DEFINITIONS
data_in =[din7,din6,din5,din4,din3,din2,din1,dinO];
latch_data = [data7,data6,data5,data4,data3,data2,data1,dataO];
EQUATIONS
latch_data := data_in;
latch_data.c =strobe;
end
The MCU can read the latched data by reading the Macrocell Out Register. There is a
Macrocell Out Register for Port A, B, and E. The address locations are specified in the
Systems Configuration section of the WSI "PSD Programmable Peripherals Design and
Applications Handbook".

-------------------------~Jr;-----------------------3-261

PlIUXX/5XX - "pllatl,n N,,. D86

IIs8 Macfllesll.
to Latch MCU
Data and Rsad
with a

CO·pfIICBSSOf

The MCU can use the macrocells to latch data out on an I/O port. The Output Enable
Control of this 1/0 port can be controlled by an extemal device such as a co-processor.
If you are trying to pass data from the MCU to a co-processor, connect an I/O port directly
to the co-processor's data bus. The Output Control of this I/O port will be controlled by the
co-processor thus avoiding any conflicts on the co-processor's data bus. The MCU will load
data into S macrocells and those macrocells will be routed to the I/O port connected to the
co-processor's data bus. The method of loading data into the macrocells is described in
section 2.0 of this Application Note.
In the PSDabel file specify the following:
Method 1 was used from Section 2.0 to load data into the macrocells from the MCU.
module example
"define the page reg
pgr3, pgr2, pgr1, pgrO node;
"define the macrocells to latch the data out
data7, data6, data5, data4 pin Istype 'reg';
data3, data2, data1, dataO pin istype 'reg';
"This Signal is the output enable signal from the co-processor.
"This signal will enable the output of the I/O port.
proc_enable pin;
"DEFINITIONS
page_reg = [pgr3,pgr2,pgr1,pgrO);
"Since the page register is only 4 bits wide, the byte of data must
"be split into two nibbles.
uppecnibble = [data7, data6, data5, data4);
lower_nibble = [data3, data2, data1, dataO);
EQUATIONS
"Because of the resolution of the address decoding (from A15 to AS),
"the address range from 1Ifl2000 to I\h20FF is reserved for loading the
"macrocells with data from the page register.
lowecnibble.oe =proc_enable;
lower_nibble.c =(Address == 1Ifl2000) & Iwr;
lowecnibble := page_reg;
uppecnibble.oe = proc_enable;
uppecnibble.c =(Address == I\h2001) & Iwr;
upper_nibble := page_reg;
end

..

----------------------,
_,.---------------------3-262
"",,,
A

PSD4XX/5XX - Application Nots 035

Generate Reset,
I'reset, Clock
and Output
Enable Inputs to
the Macrocel/s

Port B macrocells are the most flexible macrocells. Each macrocell on Port B can have
individual preset, reset, and clock product terms. The reset, preset, and output enable
signals for Port A and E are grouped together. The clock input for all macrocells associated
with Port A and E comes from the clkin signal. The Reset, Preset, and Output Enable input
signals to the macrocells are all active high. The following definitions are available for each
port.
Port A
boo_a.re
boo_a.pr
boo_a.c
boo_a.oe

"same reset product term for all 8 macrocells
"same preset product term for all 8 macrocells
"same clock input (clkin) for all 8 macrocells
"same output enable product term for all 8 macrocells

PortB
boo_ai.re
boo_ai.pr
boo_ai.c
boo_ai.oe

"individual reset product term for each of the 8 macrocells
"individual preset product term for each of the 8 macrocells
"individual clock product term or the clkin signal for each of the 8 macrocells
"individual output enable product term for each of the 8 macrocells

Port E
boo_e.re
boo_e.pr
boo_e.c
boo_e.oe

"same reset product term for all 8 macrocells
"same preset product term for all 8 macrocells
"same clock input (clkin) for all 8 macrocells
"same output enable product term for all 8 macrocells

Listed below are the most powerful to the least powerful macrocells:
Port B macrocells
Port A macrocells
Port E macrocells

Macrocel/s
Implement
Buriedl'LD
Function, I'ort
Configured as
MCUI/O

If an 1/0 port cell is configured as a MCU 1/0, the associated macrocell can still be used as
a buried feedback macrocell.
module example
"example of a two bit shift register
iosignal pin 50; "Port BO is used as a general MCU 1/0 port, reserving this pin.
burried_mc node 50 istype 'reg'; "The macrocell associated with Port BO.
data_in pin; "input data to be shifted in.
data_out pin istype 'reg'; "output of shift register
equations
burried_mc.c =clkin;
burried_mc := data_in;
data_out.c = clkin;
data_out .= burried_mc.fb;
end

------------------------~Jr;-----------------------3-263

PS04XX/5XX - Application Not. 035

-3-~-6-4-------------------------------~~~-----------------------------------

--....,

-

===== ==~
-------....
---_
.....

~~

Programmable Peripheral

~

I'~--.-

--""" " - "

Application Note 036

~

How To Fit Your Design Into The
PSD4XX/5XX
By Dan Friedman

Abstract
Method of
Fitting Your
Design

This application brief is a step-by-step procedure for fitting your design. This is not the only
method of fitting your design but is an effective one.

Step 1
When specifying a new project name, specify a project directory under the PSDsoft
directory.

Step 2
Copy an old PSDabel (.ABL) file from a previous project into your project directory. There
are some examples of PSDabel files in the "C:\psdsoft\examples" directory.

Step 3
When declaring input and output signals, do not specify pin assignments. After the design
fits, add pin assignments and move signals to more desired pin locations.

Step 4
Any signals used as Standard MCU I/O or Latched Address Out can be declared in the
PSDabie file. As long as these signals are not used in the PLD equations, they will default
as Standard MCU I/O or Latched Address Out. There are some exceptions to this rule.
These exceptions relate to Bus Interface Signals, Special Function Signals, and Alternate
Function Signals.

Step 5
Compile the design in PSDabel Design Entry.

Step 6
After eliminating all syntax errors, view Optimized Equations. For a given signal, there are
two numbers indicating the number of product terms (one from the Default Polarity and one
from the Reverse Polarity). The fitter will always use the lowest number of the two columns.
If the lowest number for a given signal is greater than 6, this signal will not fit. To solve this
problem, break up the product terms and use a buried register as shown below.
before:
boo pin;
"Output signal
a,b,c,d,e,f,g,h,i,j pin;
"Input signals
equations
boo = (a & b) # (c & d) # (e & f) # g # h # i # j;

"This equation uses 7 product terms.

after:
"Output signal
boo pin;
a,b,c,d,e,f,g,h,i,j pin;
"Input signals
buried_reg node;
"Intermediate term
equations
buried_reg = (a & b) # (c & d) # (e & f);
boo = buried_reg.fb # g # h # i # j;
The above example shows one method of manually performing product term expansion.
However, PSDsoft automatically performs product term expansion based on the available
device resource. When PSDsoft automatically performs product term expansion, see the
Fitter report for detailed information.

3-265

PSD4XX/5XX - Application Not. 036

Method of
Fitting Your
Design
(Cont.)

Step 6 (Cont.)
Note: Product terms for ESO-3 and RSO for internal EPROM and SRAM respectively have
only one product term as defined in the Decoding PLD (DPLD). If more product
terms are required, the above method (using a buried macroceli from the GPLD)
can be used.

Note: General PLD (GPLD) features for the PSD4XXA2 and PSD5XXB1 products:
-

Port A Macrocelis have 3 product terms each.
Port B Macrocelis have 6 product terms each.
Port E Macrocelis have 1 product term each.
Ali Port B Macrocells can use the clkin signal or product term clocks (clocks other
than the clkin signal). These product term clocks can come from any I/O port pin.
Each Port B Macroceli can have individual product term clocks.
- Port A and E Macrocells are clocked by the clkin signal only.
- All Port B Macrocells have individual preset, reset, and output enable product
terms.
- Port A and E Macrocells have common preset, reset, and output enable
product terms.

Note: GPLD features for the PSD4XXA 1 products:
-

-

Port A Macrocelis have 3 product terms each.
Port B Macrocelis have 6 product terms each.
Port E Macrocelis do not exist
Ali Port B Macrocelis can use the elkin signal or product term clocks (clocks other
than the clkin signal). These product term clocks can come from any I/O port pin.
Each Port B Macroceli can have individual product term clocks.
Port A Macrocells do not contain flip-flops. They are combinational outputs only.
Therefore there is no clock, preset, or reset inputs to these macrocelis.
All Port B Macrocells have individual preset, reset, and output enable product
terms.
Port A Macrocelis have common output enable product terms.
Port C, Port D, and Port E (PE2-7 only) are not routed into the PLDs. Therefore,
inputs on these port pins can not be used as part of the PLD logic equations.

In the Optimized Equations Report, determine the number of Signals requiring 4 to 6
product terms and 2 to 3 product terms. If there are more than 8 signals requiring 4 to 6
product terms, the design will not fit. If there are more than 16 signals requiring 2 to 6
product terms, the design will not fit. By splitting up the product terms and using a buried
register as described above, this problem can be solved.
Designs often do not fit because the designer has defined too many product term clocks
(clocks other than the elkin signal). Two methods of working around this problem are
shown below.

-------------------------------------._~_!f_~~------------------------------------3-266
l1li

PSD4XX/5XX - Application Not. 036

0'

Method
Fitting Your
Design

Step 6 (Cont.)
••thod 1. Take the largest group of signals associated with a clock and route that clock into
the clkin pin.

(Cont.)
Example: Make the following list on paper.
Clock W
sig 1
sig 2
sig 3

Clock X
sig4
sig 5
sig6
sig 7

Clock Y
sig 8
sig 9

Clock Z
sig 10

If the designer is using a PSD4XXA2, route Clock X into the clkin pin.
Route sig4, sig5, sig6, sig7 to port A or E macrocells.
Route sig1, sig2, sig3, sig8, sig9, sig10 to port B macrocells .

••thod 2. If the designer is using the following definition,
x:=1;
x.re = !reset
x.clk=A&B;
Convert the above function as follows:
x.re = !reset;
x:= x.fb # (A&B);
x.clk = clkin;
period of clkin < pulse width generated by (A&B)

Note: The number of signals with 4 to 6 product terms plus the number of signals requiring
a product term clock with less than 4 product terms on the D input of the flip-flop
cannot exceed ~.

,-.-.

- - - - - - - - - - - - - = - i l r . - - - - - - - -_ _ _ __

'#t!!!. b

3.267

PSD4XX/5XX - Application No'" 036

Method of
Fitting Your
Design
(Cont.)

Step 7
Fit the design in PSD compiler under the Compile Menu.
To understand why a signal does not fit, look at the Report File under the View Menu. Look
at the Resource Usage Summary along with the OMC Resource Assignment. The
Resource Usage Summary will tell the designer how the pins on a given 1/0 Port were
assigned and how those resources were allocated. The OMC Resource Assignment will
indicate which macrocell was utilized for each output signal used in an equation in the
PSDabel file.
Example:
OMC Resource Assignment
Resources Used

User Name

PortA:
macro cell 3

cntO => Register

"cntO used as a buried register.
"cntO was defined as a node.
"cntO is a registered output node.

Port B:
macro cell 7

cnt4 (mc_pb7) => Register

"cnt4 is routed to an output pin on
"PB7.
"cnt4 was defined as a pin.
"cnt4 is a registered output.

Port E :
macro cell 2

wstc (mc_pe2) => Combinatorial

"wstc is routed to an output pin
"on PE2.
"wstc was defined as a pin.
''wstc is a combinatorial output.

All Signals followed by "(mc_pxx)" are output pins. If "(mc_pxx)" is omitted, the signal was
defined as a node and is a buried register. From this report the designer can determine the
exact reason why a given signal would not fit.
Note: In the Options menu, Fitter Options are Keep, Try, or Ignore.
Keep Current - Uses the pin assignments specified in the PSDabel file.
Keep Previous - Uses the pin assignment from the previous fitting process.
Try - Tries to use the pin assignments specified in the PSDabel file.
Ignore - Does not use the pin assignments specified in the PSDabel file.
This is the same as not specifying any pin assignments in the PSDabel file.
For pins which use reserved names, the pin assignments are always fixed.

-------------------------------~~iIi~------------------------------3·268

--

PSD4XX/5XX - Application Not. 036

0'

Method
Fitting Your
Design
(Cont.)

StepS
If several signals will not fit, start by commenting out all unfitted signals until the design fits.
Fit one signal at a time by using some of the above methods and other methods described
in other Application Notes.

Step 9
Assign pin numbers to all the signals in the PSDabel file. Move signals around to desired
pin numbers. The designer may not be able to move certain signals to desired pin numbers
as a design violation may occur.

Note: Some important things to remember about the PSD4XXA2 and PSD5XXB1 devices
are that only Ports A, B, and E have PLD I/O. Port C and Dare PLD inputs only.
If Port A, B, or E is used as a PLD input, the macrocell associated with that pin
cannot be used as a buried register or routed to an output pin. It is best to use Port
C and D and PLD inputs first. On the PSD4XXA 1 devices, Ports A and B can be
used as PLD I/O while port pins EO and E1 can be used as PLD inputs only.
Any signal pins reserved in the PSDabel file that are used as Latched Address

Out Signals must be in sequential order (i.e., addrO must be assigned to PCO,
addr1 must be assigned to PC1 etc.).

___________________________________

F.JJ~~

~~.,,-----------------------------------

3·269

PSD4XX/SXX - Appllt:BtllIR , I . _

~~

3.270

__________________ r••'¥_____________________
'tINII&

Programmable Peripheral
Application Note 037
How to Implement a Latch Function in Port A
of PSD4XX/5XX that is Independent of the
System Clock
By Mohan MaghsfB

Introduction

The macrocells in PSD4XXl5XX devices include D-type registers. When mapping discrete
solutions to these PSDs, it is sometimes necessary to replace transparent latches (e.g.,
'573) with the PSD macrocells. Since the PSDs do not have transparent latches, the easiest
alternative is to make the design edge-triggered and use the D-type registers. However,
there are some situations where the designer must use a transparent latch. In these cases
it is possible to use a 2:1 multiplexer configured to perform the function of a latch.
There is an added bonus in using this approach: the PSD4XXl5XX devices offer up to 24
macrocells in the GPlD. Of these, 16 Port-A and Port-E macrocells are clocked by the
system clock on the ClKIN pin. The other 8 (Port-B) macrocells may be individually
configured to use either the system clock or a product term clock.
For designs that fully utilize the Port-B macrocells and still need further register elements
that must remain independent of the system clock (but do not have to be edge triggered),
it is possible to realize up to 8 more registers by using 2:1 multiplexers configured as
transparent latches.
Two examples are shown in this application note. The first shows the basic idea by realizing.
a latch with one Port-A macroceli, and the second example shows a "real life" situation
where a one-way communications port (e.g., Centronics: host to target, where the PSD
would be located in the target) is realized in the Port-A macrocells.

Example 1

Figure 1 shows how one of the Port-A macrocells performs this latch function:
Port-C has been used to input the signal to be latched, as well as the lE control signal.
Of course, another port (or ports) may be used as long as it is usable as an input to the
ZPlD-bus. The output of the macrocell may then be brought out to the respective Port-A
pin, if needed. Otherwise, if it is to be accessed by the MCU, the pin may be kept free for
some other 1/0 function since the MCU can access the outputs of the macrocells directly by
reading the "Macrocell Out" register of Port-A.
When PC1 is HIGH, PCO is enabled through to PAO - Transparent.
When PC1 is lOW, PAO is looped back on itself - latched.

Figure 1.

-B

0
PCO

PAO

A
AlB

PCl

NOTE:

I

The A/_B input is equivalent to the high-true LE input on a latch: when LE is 1, the latch is transparent
and when LE is 0, the input is latched.

3-271

PS04XX/5XX - Application Not, 037

Example 1

Below is a sample ABEL file that describes this function:

(Cont.)
module latch1
title 'transparent latch using a 2:1 mux.';
"Since the PSDs offer D_type registers and not transparent latches, the easiest alternative
"for the designer is to make the design edge triggered and use the D-type registers.
"However, there are some situations where the designer must use a transparent latch.
"In these cases it is possible to use a 2:1 multiplexer configured to perform the function
"of a latch.

"INPUTS and OUTPUTS
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
wr, rd pin;
psen, ale pin 38,37;
"PEO-1
clkin, reset pin;
csi pin;

"PAO acts as the latch output
paO_latch_out pin 27;
"PCO acts as the input to the latch, and PC1 as the latch
"enable signal.
pcO_latchjn, pcUe pin 17, 16;

"base address for i/o chip selects
csiop node;

"DEFINITIONS

x =.x.;
CK=.c.;
addr=[a15,a14,a13,a12,a11 ,a10,a9,a8,X,X,X,X,X,X,a1 ,aO];

EQUATIONS
"DPLD equations
csiop = (addr >= AhOCOOO) & (addr <= AhOCOFF);
"GPLD equations
paO_latch_out = (pcO_latch_in & pcUe)
"transparent"
# (paO_latch_out.fb & !pcUe)
"latched"
# (paO_latch_out.fb & pcO_latch_in); "removes any glitches"
end latch1

_____________________________________
3-272

farar~~

';#..§II

_____________________________________

PSD4XX/5XX - ApplIcatIon Not. 037

Examp/e2

Figure 2 shows a communications port that allows a host to write data into an 8-bit register
with the _HST_ WR signal. Simultaneously, this signal is used to set a_BUSY_2_HST flag
which is polled by the host to see if the MCU has read the data. When reading this data
LMCU_RD), the MCU clears the _BUSY_2_HST flag, thus indicating to the host that it may
write the next data byte.
In a discrete solution the _HST_WR signal would be used as a clock to the D-type registers,
but in this example it is assumed that the Port-B macrocells are used for functions that need
ClKIN (system clock) and other independent (product term) clock inputs. In this situation
the D-type registers in Port-A would be clocked by ClKIN and thus cannot be driven by the
_HST_WR signal. Since the data is required to be stable when _HST_WR is High and is
"Don't Care" when _HST_WR is low, we can replace the edge-triggered registers with a
transparent latch function realised using 2:1 multiplexers.
Figure 2 also shows that the _RESET signal is ORed with _HST_ WR. So, after a system
reset it will be necessary for the MCU to do a dummy read of the data register to clear the
busy flag. The reason for including this is to ensure that the host does not try and write to
this port while the MCU is still in a reset cycle.

Figure 2.
8

'-----fA

PR

o
CK

RE

-----------------------------~JrJF~----------------------------3-273

PS04XX/SXX - ApplIcation Note 031

Example 2
(Cont.)

Figure 3 shows how the data register can be realised in the Port-A macrocells on the PSD.
The _HST_ WR flag is generated in the Port-E macrocells and avoids using the clock on the
D-type register by implementing an S-R flip-flop using cross-coupled NAND functions (thus
giving the same functionality as the preset and reset functions of a D-type register).
The MCU would either use the _HST_WR signal's rising edge to generate an interrupt to
indicate that a valid data byte is available, or would test for the _BUSY_2_HST flag being
Low and _HST_WR signal being High (Le., host write cycle is complete). When the MCU
reads the data register (Le., reads the "Macrocell Out" register of the Port-A macrocells), the
_BUSY_2_HST register must be cleared. In order to do this, it is necessary to decode the
full address of the Port-A Macrocell Out register ANDed with the MCU's _RD signal. In the
PSD4XXl5XX, the address lines A8-A15 and AO-A1 are directly available on the ZPLD
but in order to have access to the A2-A7 lines we must configure Port-C to output these
latched addresses (on PC2-7). These Port-C pins are then available for decoding on the
ZPLD-bus.
Since the busy flag will clear as soon as the _RD signal goes low, the host must avoid
writing the next data byte too early, Le., after seeing _BUSY_2_HST go High, it must
insert a short delay equivalent to, or greater than, the _RD Low width before writing the
next data byte.

Figure 3.

MCU ADDRESS!
OATAlCONTROL BUS

ZPLDBUS

-

r--

_RESET

~

j)- f-+

HST_DATA

-

8

In

OATA_2..MCU

I

PORTA

'---

PORT A MACROCELLS
PORTO

8
MCU_RD

-.. --I--l>-~

_HST_WR

j)- -I-t>o-

AD-A6
6

I

_-I-t>o-I-

BUSY 2 HST

PORTE

PORT E MACROCELLS
PORTC

BUSY 2 HST
BUSY_2_HST

PSD4XXA2I5XX

-3--2-~-~---------------------------------~1f~~------------------------------------

PSD4XX/5XX - Application Nots 037

Example 2

Below is a sample ABEL file that describes this function:

{Cont.}
module latch2
title 'One way comms. link: Host-to-MCU/PSD using Port-A macrocelis configured as
transparent latches';
"This example shows a simple, mono-directional communications link between a remote
"host and a local MCU. The MCU uses the PSD to latch the incoming data and to generate
"a busy flag back to the host.
"Since the PSDs offer D-type registers and not transparent latches, an octal 2:1 mux
"realised in the Port-A macrocelis is configured to perform the transparent latch function.
"The design pre-supposes that the Port-B macrocelis and the ClKIN pin are not available.

"INPUTS and OUTPUTS
"MCU interface signals (using a mixture of reserved names and explicit pin number
"declarations)
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
wr, rd pin;
psen, ale pin 38,37;
"PEO-1
clkin, reset pin;
csi pin;
"Port-A macroceli outputs (nodes) are reserved for the 2:1 mux-Iatch outputs
data_2_mcu7, data_2_mcu6, data_2_mcu5, data_2_mcu4,
data_2_mcu3, data_2_mcu2, data_2_mcu1, data_2_mcuO
node 20, 21, 22, 23, 24, 25, 26, 27;
"Port-CO is used as the _HST_WR input pin
_hsCwr pin 17;
"Port-C2-7 are configured to output latched addresses A2-A7 and these are fed back on to
"the ZPlD-bus for use in decoding a read of the Port-A Macroceli Out register address
"(= mcu_rd = csiop + AhOC for an Intel MCU design, and = csiop + AhOD for a Motorola
"16-bit MCU design). AO-1 are always available on the ZPlD-bus
pc2, pc3, pc4, pc5, pc6, pc7 pin;
"Port-D is used to input the host data onto the ZPlD-bus
hsCdata7, hsCdata6, hsCdata5, hsCdata4,
hsCdata3, hsCdata2, hsCdata1, hsCdataO
pin 53, 54, 55, 56, 57, 58, 59, 60;
"Port-E2 macroceli and its pin is used as the _BUSY_2_HST flag output
"via one half of an S-R flip-flop (cross-coupled NAND gates)
_busy_2_hst pin 36;
"Port-E3 macroceli is used to generate the other half of the S-R flip-flop
busy_2_hst node 34;

-------------------------------------~~~------------------------------------3-275

I'SD4XX/5XX - Application Nots 031

Examp/e2

Sample ABEL file (Cont.)

(Cont.)
"Port-E4 macrocell is used to decode MCU read of Port-A Macrocell Out Register address.
"This is necessary because Port-E macrocells can only support a single product term
mcu_rd node 33;
"base address for 1/0 chip selects "address is AhCOOO
csiop node;

for this design it will be assumed that this

**********
"DEFINITIONS

x =.X.;
CK=.c.;
addr=[a15,a14,a13,a12,a11 ,a10,a9,a8,X,X,X,X,X,X,a1 ,aO];
fulLaddr = [a15,a14,a13,a12,a11 ,a1 0,a9,a8,
pc? ,pc6,pc5,pc4,pc3,pc2,a1 ,aO];
data_2_mcu = [data_2_mcu?, data_2_mcu6, data_2_mcu5,
data_2_mcu4, data_2_mcu3, data_2_mcu2,
data_2_mcu1, data_2_mcuO];
hsCdata = [hsCdata?, hsCdata6, hsCdata5, hst_data4,
hsCdata3, hsCdata2, hsCdata1, hsCdataO];
**********

EQUATIONS
"DPLD
csiop = (addr >= AhOCOOO) & (addr <= AhOCOFF);
"GPLD
"realise the 8-bit latch
data_2_mcu = (hsCdata & !_hsCwr)
# (data_2_mcu.fb & _hsCwr)
# (data_2_mcu.fb & hsCdata);

"transparent"
"latched"
"removes any glitches"

"busy flag
mcu_rd = (fulLaddr == AhOCOOC) & !rd;
_busy_2_hst = !(!mcu_rd & busy_2_hst.fb);
busy_2_hst = ILhsCwr & reset & _busy_2_hst.fb);

end latch2

~~----------------------------"ljF~_------------------------------3-216
'!r!fiI# if

iF::
==_
-- . ..., .. - -r~

..........

--~---

_

~~~-

Programmable Peripheral
Application Note 038
How to Increase the Speed of the PSD5XX
Counter/Timers
By Mohan Magh.ra

Introduction

The PSD5XX family is presently the most capable programmable peripheral family that WSI
produces. Among the standard features, such as EPROM, SRAM, I/O port expansion,
Decode PlD (DPlD) and General Purpose PlD (GPlD), it also offers the designer a third
PlD area known as the Peripheral PlD, four 16-bit counter/timer units (CTUs), and an 8-bit
Interrupt Control Unit (ICU).
The PSD5XX has four 16-bit counter/timer units (CTUs) and this application note will
examine the CTU block with respect to enhancing the speed of its operation (up to 28 MHz).

CTUBlock

All four CTUs work off the same clock source: ClKIN, the system clock. Before this clock
goes to the CTUs, it passes through a pre-scaler that divides the system clock by a
programmable value between 4 and 280. The maximum frequency of the ClKIN input to
the pre-scaler is 28MHz. If the pre-scaler is set to divide by the minimum value of 4, the
maximum frequency of operation of the CTU is 7MHz. However, there are many
applications where it is required to count at much higher frequencies.
The GPlD on the PSD5XX-90 (90 nanosecond device), when used in synchronous clock
mode (i.e., ClKIN is used as the clock input for the macrocell flip-flops), is capable of
supporting internal feedback signals at frequencies up to 37.3 MHz, and when it is used in
asynchronous clock mode (i.e., a product term clock is used for the macrocell flip-flops), the
GPlD is capable of supporting internal feedback signals at frequencies up to 28.5 MHz.
If the design requires counter sizes of 5-bits or less (where 5-bits is the maximum size of a
pre-Ioadable counter with count enable which can be realised in the GPlD Port-B
macrocells without resorting to product term expansion), then it is possible to achieve
counter frequencies of 37.5 MHz with ClKIN and 28.5 MHz with a product term clock.
However, for those situations where the counter needs to be larger, it is possible to build
such a counter from a CTU and the GPlD that operates at a much higher frequency
than 7 MHz.
In any counter, the least significant bits are the ones that change the fastest and, therefore,
need the faster clock. The least significant bit (lSB) changes state with every input clock
cycle, the second lSB changes state with every second clock cycle, the third lSB with
every fourth clock cycle, etc. (See Figure 1).

3-277

PSD4XX/SXX - Application Not. 038

crUB/oct

FI,ure 1. CDunter Output WavefDrms

(Cont.)

elK
lSB

2nd lSB

L

3rd lSB

L

If we examine the waveform produced by the outputs of the counter, we see the LSB
produces a waveform at half the counter clock frequency (Fcnt), the second LSB at a
quarter of Fcnt, the third LSB at an eighth of Fcnt., etc. The relationship being:
Fcnt

2r1
where n

= 1,2, 3, etc., i.e., the position of the bit.

From this relationship, if we were to realise the least significant part of the counter in the
GPLD, and from this generate a terminal count that could be used to gate one of the 16-bit
CTUs, then the pre-scaled clock to the CTU need only be a fraction of the frequency used
for the GPLD part of the counter. (See Figure 2.)
In order for the CTU to function correctly, it needs to be configured to run in the EVENT
counter mode. This means that when the GPLD counter generates a terminal count, the
positive going edge of this signal is latched as an event, and the CTU will be updated at the
next CTU clock. For another event to be counted by the CTU, the terminal count of the
GPLD counter must generate another rising edge, i.e., it must go low and back high again.
Thus, the CTU clock must operate at a frequency above the events that are occurring to
ensure that no events are missed and still satisfy the requirement that it remain below
7MHz., i.e.,
CTU clock = (CLKIN/pre-scaler value) <= 7 MHz
The relationship between CLKIN, Fcnt, pre-scaler value and the size of the GPLD counter
(2n) is given by:
Fcnt
(2n) < (CLKIN/pre-scaler value) <= 7MHz
This is true for all Fcnt frequencies up to 28.5 MHz and CLKIN frequencies up to 28 MHz.
When Fcnt is the same clock as CLKIN (see Figure 3.), this relationship can be
expressed as:
CLKIN
< (CLKIN/pre-scaler value) <= 7MHz
(2n)
This is true for CLKIN frequencies up to 28MHz.

------------------------____ r;;;r~ ___________________________
3.278

'rlNl1III II

I'SD4XX/5XX - Appllat/on

CruBIDCk

""te_

FI,uIfI2

(CtIIIt.}
ZPLDBUS

Fent -

+-...+--+

......

CLKlN-..................

PSD5XX
NOTE: Fent _ 28.5 MHz and CLKIN _ 28 MHz.

FI,uIfI3
ZPLDBUS

CLKlN -

..."H......

·1
____
_____

PAE-8CALER

J

CTU CLjK.. r-r_ _ _ _--,
COUNTERmMER

PPLD

TERMINAL COUNT
(EVENT)

PSD5XX
NOTE: Fent = CLKIN <= 28 MHz.

----------------------IJJrI---------------------3·279

I'SIl4XX/5XX - Appilcatilln IIl1t. 038

CrUB/ock
(Clint.)

Below are sample ABEL and Verilog stimulus files for a design that needs a counter greater
than 5 bits to run at a clock frequency up to 28 MHz. The Fcnt and ClKIN sources are the
same, therefore, the relationship needed to be satisfied is:

Le.,

ClKIN
(2n)

< (ClKIN/pre-scaler value) <= 7 MHz

28 MHz
(2n)

< (28 MHz/pre-scaler value) <= 7 MHz

This requires n to be at least 3 and the pre-scaler value to be between 4 and 7. In order to
reduce the A.C. power consumption, it is best to use the biggest pre-scaler value possible
(taking into account the clock frequency needs of the other three CTUs), Le., 7 in this case.
The GPlD counter will be a 3-bit counter, whose terminal count is used to generate events
to one of the 16-bit CTUs (CNTRO). The events (terminal counts) will occur at a frequency
of (28/8) = 3.5 MHz, and the CTUs will be clocked by (2817) = 4 MHz, which ensures that all
events will be captured and counted.
The GPlD counter is cleared at power-up or with reset and will start to count only if the
cnCen pin is held active (HIGH in this case). CNTRO, however, will need to be cleared by
software by writing zero to it before it is enabled in the Command Register, CMDO, and in
the Global Command Register (see stimuh,ls file).
The GPlD counter in this example is made pre-Ioadable (cnUd and dinO-2) so that this,
together with CNTRO, provides a 19-bit pre-Ioadable counter (CNTRO is pre-loaded by
writing the required upper 16-bit value to it before it is enabled in the CMDO and Global
Command Registers).
The terminal counts of the CTUs are available on Port-E and are also routed to the ICU to
allow an interrupt to occur when a CTU reaches terminal count.
In order to read back the value of the complete 19-bit counter, the GPlD 3-bit counter
outputs are available to the MCU via the Macrocell Output register. Assuming that all of the
counter is realised in the Port-B macrocells, then a read of the Port-B Macrocell Output
Register would access the counter bits. In order to ensure that the value does not change
during the read cycle, it will be necessary to disable the counter (cnCen = lOW) before
reading. To read back the 16-bit value of CNTRO, it is necessary to freeze the counter
value by setting bit-O in the Freeze Register and then polling bit-O in the Freeze
Acknowledge register until it reads 1. At this point CNTRO's value is transferred to the
Image Register, IMGO. The value is then read from IMGO while CNTRO can continue
counting (if cnCen is active). After IMGO has been read, bit-O in the Freeze Register should
be reset to o.
The CTUs in the PSD5XX can be used either in pulse or waveform modes, or in event
count and time capture modes. Selection of these modes and the enabling of the CTUs to
count are set via the command registers CMDO-3 and the Global Command Register. The
pre-scaler value is set via a 5-bit value in the DlCY Register and a "scale bit" in the Global
Command register. The order in which the various registers must be initialised and the
values required for this example are given in the stimulus file.

-----------------------------------~~~--------------------------------~
3·280

PSD4XX/SXX - ApplIcation No'. 038

ABEL
File

ABEL file:
MODULE ctu_spd
title 'How to increase speed of CTU operation .. .';

"INPUTS and OUTPUTS
a15,a14,a13,a12,a11,a10,a9,a8,a1 ,aO pin;
wr, rd pin;
"PEO-1
psen, ale pin 38,37;
clkin, reset pin;
csi pin;
"base address for the PSD's internal I/O ports and
"configuration registers
csiop node;
"GPLD 3-bit up counter signals
"count enable input
"counter data input pins
"enable input for loading of
"counter input data (din2-1)

cnCen pin;
din2, din1 , dinO pin;
cnUd pin;

"counter outputs
cnt2, cnt1, cntO node istype 'reg';
"macrocell event (terminal count from GPLD counter
"to CNTRO - the CTU to be used for event counting
mc2tmrO node;
***************************

"Definitions

x =.x.;
CK=.c.;
addr = [a15,a14,a13,a12,a11 ,a10,a9,a8,
X,X,X,X,X,X,a1,aO];

=

din [din2, din1, dinO];
cnt = [cnt2, cnt1, cntO];
***************************

__________________________________

,Ar·~~

~.I!

__________________________________
3·281

PSD4XX/5XX - Application Nots 038

ABEL
File
(Cont.)

EQUATIONS
"DPLD equations
"I/O base address for PSD internal register - defined
"to be a 256 address block starting at "hCOOO
csiop = (addr >= "hOCOOO) & (addr <= "hOCOFF);

"GPLD equations
cnt.clk = clkin;
cnt.re = reset;
WHEN (cnUd) THEN cnt := din;

"pre-load counter

ELSE WHEN (!cnCen) THEN cnt := cnt.fb;
ELSE cn!:= (cnt.fb + 1)

"counting is not enabled

"increment count

"PPLD equations
"generate event for CNTRO using the CTU macrocelis in PPLD
"the terminal count is gated by the LOW part of clkin to
"ensure that no decoding spikes (after the rising edge of
"clkin) generate any false events
mc2tmrO = (cnt.fb == "h7) & !clkin;

-3--2-82--------------------------------~~~-----------------------------------

PSD4XX/5XX - Appllcatilln Nllt.

VERILOG
Stimulus
File

os,

VERI LOG stimulus file:
IIStimulus file for setting up the timer/counter, CNTRO,
llin event count mode, and for testing the 3-bit GPLD
IIcounter used to increase the speed of the PSD's
IICounter/timer units (CTUs).

reg [7:0] daCval;
reg [7:0] din;
assign {din2, din1, dinO} = din;

IIUsed to hold data read from PSD
IIpre-load value for GPLD counter

11++++++++++++++++++++++++++++++++++++++++++++++++++++++++
II
User-Defined parameters
11++++++++++++++++++++++++++++++++++++++++++++++++++++++++
parameter pb_mc_out='hCOOD;
parameter cntrOL='hC098, cntrOH='hC099, imgOL='hC090, imgOH='hC091;
parameter cmdO='hCOAO;
parameter g_cmd='hCOA8;
parameter dlcy='hCOA6;
parameter freeze='hCOA4, status='hCOA9;

11++++++++++++++++++++++++++++++++++++++++++++++++++++++++
II Defining tasks to simplify writing the stimulus file
11++++++++++++++++++++++++++++++++++++++++++++++++++++++++
task write (addcbus,data_in);
input [15:0] addr_bus;
input [7:0] data_in;
begin
#20 ale = 1;
#20 adio = addcbus;
#20 ale = 0;
#20 adio = data_in;
#40 wr=O;
#100 wr = 1;
#10 adio = Z16;
end

IIHigh true ale
IISet-up the right address
IILatches address
l!Write operation
l!Write pulse
l!Write ends

endtask

rAL.'?

--------------------------------~1---------------------------3--2~--

PSD4XX/5XX - Appilcatilln Nllts 038

VER/LOG
Stimulus
File

task read (addcbus);
input [15:0] addr_bus;

(Clint.)

begin
#20 ale = 1;
#20 adio = addcbus;
#20 ale = 0;
#20 adio = Z16;
#40 rd =0;
#50 daCval = 'adiol;
#50 rd = 1;
end

//Active high ale
IISet-up the right address
IILatches address
IIFloat Address bus
IIRead starts
IIStore low byte of adio
IIRead ends

endtask
task psen (addcbus);
input [15:0] addr_bus;
begin
#20 ale = 1;
#20 adio = addcbus;
#20 ale = 0;
#20 adio = Z16;
#40 psen = 0;
#100 psen = 1;
end

IIActive high ale
IISet-up the right address
IILatches address
IIFloat Address bus
IIRead starts
IIRead ends

endtask
//************* Begin stimulus ******.***** •• *•• ** •••• * ••

initial
begin
wr = 1; rd = 1; psen = 1;
ale = 0;
clkin = 0;
reset = 0;
csi = 0;
adio ='hOOOO;
din = 'hO;
cnCen = 0;
cnUd=O;

IIGPLD counter disabled

#500 reset = 1;
IIClear timer/counter-O

#10 write(cntrOL, 'hOO);
write(cntrOH, 'hOO);
IIClear image register-O

write(imgOL, 'hOO);
write(imgOH, 'hOO);
___________________________________ fss:F§ ___________________________________

3-284

'#.!!I.

PSD4XX/5XX - Application Nots 038

VER/LOG
Stimulus
File
(Cont.)

IISet delay cycle register to 3, so that clkin is pre·scaled
Ilby 7 (pre·scale value = K(delay reg. + 4), where the
Iiscale bit, K, in the Global Command register is
Iiset to 0, Le., scale factor is 1 - when set to 1 the scale
Ilfactor would be 8)
write(dlcy, 'h03);

IISet command register, CMDO, to configure CNTAO for event mode
Ilwith the event coming from the macrocell, mc2tmrO
IILSB
II
II
II
II
II
II
II
II
II .
IIMSB

0
1
1

X
X
0

0
0

Event count mode (if set to 1 = time capture mode)
Increment mode
Select (enable) CNTAO
No timer output in this mode
Pin·input polarity is not needed since the
event is macrocell driven
Input command from macrocell
(if set to 1 then from pin)
Load/Store command from Pin/Macrocell (in this
case macrocell) allowed through
Enable/Disable by Pin/Macrocell

write(cmdO,'h1 E);

IISet the Global command register to enable the Counterltimers
Ilin event/time-capture mode
IILSB
0
Scale bit (0 =scale factor, k, is 1, 1 =scale factor is 8)
II
1
Counter start bit - enables all the selected counters
II
1
Global mode bit - set for eventltime capture mode
II
(if set to 0 then pulselwaveform mode is selected)
II
0
Watchdog disabled
IIBit4-7 are reserved and set to 0
write(g_cmd,'h06);

IIPre·load GPLD counter with 5
#10 din = 'h5;
cnUd = 1;
#40 cnUd = 0;
IIDisable load after 1 clkin cycle
#10 din = 'hO;
liEnable counting
#10 cnLen

= 1;

-----------------------------------~~~----------------------------------3·285

PSD4XX/5XX - Application Not. D38

VER/LOB
Stimulus
File
(Cont.)

!!Disable GPLD counter and perform a
IIfreezelfreeze acknowledge cycle on CNTRO
#2000 cnt_en =0;
write(freeze,'h01 );
!/Wait for freeze acknowledge flag to be set in
IIstatus register (status ='h01)
daCval = 'hOO;
IIClear temporary storage
IIregister for read data
while ((daCval & 'h01) != 'h01)
IIMask off CNTRO Freeze
IIAcknowledge bit and test if set
begin
read(status);
IIRead Freeze Acknowledge
IIStatus Register into daCval.
end

IIRead GPLD counter ouputs and CNTRO value stored in IMGO
read (pb_mc_out);
read (imgOL);
IILow byte of Image Register
read (imgOH);
II High byte of Image Register
IIReset freeze bit and enable GPLD counter
#1000 write(freeze, 'hOO);
cnCen = 1;
end

11··*···_--*··· Continuous signals **************
IIGenerate a continuous clock signal
always
#18 clkin = -clkin;
II approximately 28MHz

-----------------------------------~-~-~-~-~----------------------------------3-286

Programmabl, P,riph,ral
Application Note 039
Encodet fOI Shaft Direction and Position
Recognition Using the PSD5XX

By IIIollBn _""",

Intmdut:tiDn

In many applications the designer is provided with two input signals where one signal
leads the other by some phase difference (perhaps 90 degrees, or even some variable
amount). It is necessary to recognize which signal is leading and then either generate a
pulse count from one of the signals (or some multiple, e.g., a pulse for each edge of the two
signals - 4X clock), or be able to measure the phase difference between the two signals.
In a typical application the two signals are provided by a shaft encoder. These signals
(A & B) are always 90 degrees out of phase. Depending on which signal is leading, it is
possible to determine if the shaft is rotating clockwise or counterclockwise. By using a
counter set to zero when the shaft is at the reference point and then counting up pulses
(A and/or B) when the shaft is rotating clockwise and down pulses when rotating
counterclockwise, it is possible to know the exact position of the shaft at any time from the
value present in the counter. Integrated circuits are available on the market that input the
two signals, perform the phase detection, and generate a direction signal (up/down),
a 4x clock, and a 12- or 16-bit count value. These devices tend to be rather expensive and
the designer is forced to integrate this function into an ASIC, or realize it in an EPLD, or
some mixture of EPLD + discrete logic. The WSI, Inc. PSD5XX programmable MCU
peripheral provides a space effective and optimal cost alternative to the designer - and at
the same time providing EPROM, SRAM, interrupt control, chip selects and five I/O ports in
one device.
Figure 1 shows the PSD5XX and the resources that are taken up by the inputs, outputs,
state machine and counters.
The DIR_UP signal needs eight product terms (PTs) and the PSD5XX Port-B macrocells
can handle a maximum of six PTs. It is necessary to break this down into two smaller PT
groups: DIR_INT (4PTs) and DIR_UP (5PTs including DIR_INT).
The state machine needs two bits (SO, S1) to cover the four possible states that can exist
for the shaft encoder, and a 4X clock is generated (a pulse for every edge of A and B) in
order to realize a finer position resolution. This clock is used to generate the events that the
counterltimers count. The value of the DIR_UP direction signal is used to gate the 4X clock
to either the ·Up" counter (TIMERO) or the "Down" counter (TIMER1).
The reason for using two counters is that when used in the event count mode, the
counterltimers can only be used in the increment mode (up counting only). This requires
that one counter is used for counting "Up Pulses" and a second counter used for counting
"Down Pulses". The actual position of the shaft is then the difference between the two
counter values.
Below are the .abl and the .stl files that show how this design is realized. The software
configuration necessary for the counters to operate in the event count mode is included,
where the event is input via the macrocells (MC2TMRO and MC2TMR1).

3-287

PSD5XX - Appl/t:IItl. Nllt. 039

Figure 1.
ZPLD
BUS

h

~

D-

0
0
D

Q

j

SO

CK

~

RF

-

D

S1

Q

CK

RF

PORT A
MACROCELLS

DPORT C

-

0
D

Q

DIR_UP

CK

RF

-

-

r+

A

-

PORT B
MACROCELLS

DIR_INT

=D=D-

4x_CLK

...
B

A_DLY

-

r.

-

...
CLKIN
~

r.

,

,

D-

-

=D=D-

B_DLY

PORT E
MACROCELLS

MC2TMRO
PERIPHERAL
PLD

MC2TMR1

PSD5XX

TIMERO

~

TIMER1
MCU ADDRIDATAI ,
CONTROL BUS

r

~3.-28~8---------------------------~~jr------------------------------

PSD5XX - AppllcatlDn NDt. 039

Abel File

ABEL file:
MODULE motcdir
title 'Shaft encoder for motor direction and position
recognition';

"INPUTS and OUTPUTS
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
wr, rd pin;
psen, ale pin 38,37;
"PEO-1
clkin, reset pin;
csi pin;
"base address for i/o chip selects
csiop node;
"inputs for frequency quadrupler and phase discriminator
" a and b are always 90 degrees out of phase
a, b, pin;
"internal signals for frequency quadrupler delayed versions
"of a and b
a_dly, b_dly node;
"output from phase discriminator used to gate UP and DOWN
"event counters: dir_up=1 ==> UP, dicup=O ==> DOWN
dir_up node istype 'reg_D';
dicint node;
"partial PT's for dir_up

"output at quadruple frequency used to generate events "gated by dicup
a_b_x4 node;
"internal signals from phase discriminator state counter
sO, s1 node istype 'reg_D';
"macrocell events to UP (timero) and DOWN (timer1) counters
mc2tmrO, mc2tmr1 node;

"Definitions

x

=.X.;
CK= .C.;
addr = [a15,a14,a13,a12,a11,a10,a9,a8,
X,X,X,X,X,X,a1,aO];

"state values for state machine
ss = [s1, sO];
****.**********************

-------------------------~Jr;-----------------------3·289

PSD5XX - Appllt:lltiOR No'. 039

Abel File
(COR'.)

EQUATIONS
"DPLD equations
"i/o base address for PSD internal register - defined
''to be a 256 address block starting at JlhCOOO
csiop = (addr >= JlhOCOOO) & (addr <= JlhOCOFF);
"GPLD equations
"phase discriminator equations
a_dly=a;
b_dly=b;

"delay a and b by macrocell delay

"generate a pulse for each edge transition of a and b - pulse
''width is equal to the macrocell delay of a_dly and b_dly
a_b_x4 = (a $ a_dly) # (b $ b_dly);
"generate events for the UP and DOWN counters using the
"counterltimer macrocells
mc2tmrO = dicup.fb & a_b_x4.fb;
mc2tmr1 = !dir_up.fb & a_b_x4.fb;
"state machine for detecting motor direction
"dir_up as a complete equation needs 8 PTs, but since the PSD
"supports a maximum of 6 PTs (Port-B macrocells), it is necessary
''to split this in two: diUnt and then dicup
dicint = (!a & b & sO.fb & s1.fb
# !a & !b & !sO.fb & s1.fb
# a & b & sO.fb & !s1.fb
# a & !b & !sO.fb & !s1.fb);
dicup := (dicinUb
# b & sO.fb & s1.fb & dicup.FB
# !a & !sO.fb & s1.fb & dicup.FB
# a & sO.fb & !s1.fb & dir_up.FB
# !b & !sO.fb & !s1.fb & dicup.FB);
dicup.C = (clkin);
dicup.RE = (Ireset);
"the state counter comprises sO and s1
sO.D = (a & sO.fb
# a & b & s1.fb
# a & !b & !s1.fb);
sO.C = (clkin);
sO.RE = (Ireset);
s1.D = (a & b & sO.fb
# !a & b & !sO.fb
# b & s1.fb);
s1.C = (clkin);
s1.RE = (lreset);

•••

~~----------------------~=-------------------------3-290
~I.

I'SIJ5XX - Appilcatilln illite _

Abel File
(Clint.)

11********************************************.*******____._ •• _. ___ ._. ___._.__ _

11***************************************************._____ • __._ ••_. ________._.

"Below is the original method used for entering the,state machine
"description. The above method was cut-&-pasted from the .eq2 file
"generated after running the ABEL compiler and optimizer.

".*---------------------------------_._._-_._._._._._.._........_....._.-._--.
"state machine for detecting motor direction
ss.clk = clkin;
sS.re = Ireset;
dir_up.clk = clkin;
dicup.re =!reset;
"state_diagram ss
"
state 0: if «a==O) & (b==O))
then 0 with
dir_up := dir_up.fb;
endwith;
else if «a==1) & (b==0))
then 1 with
dir_up := 1;
endwith;
else if «a==O) & (b==1))
then 2 with
dicup := 0;
endwith;
state 1: if «a==1) & (b==O))
then 1 with
dicup := dir_up.fb;
endwith;
else if «a==1) & (b==1))
then 3 with
dicup := 1;
endwith;
else if «a==O) & (b=O))
then 0 with
dir_up := 0;
endwith;
state 2: if «a==O) & (b==1))
dicup := dicup.fb;
then 2 with
endwith;
else if «a==1) & (b==1))
dicup := 0;
then 3 with
endwith;
else if «a==O) & (b==O))
then 0 with
dir_up := 1;
endwith;
state 3: if «a==1) & (b==1))
dicup := dir_up.fb;
then 3 with
endwith;
else if «a==O) & (b==1))
then 2 with
dicup := 1;
endwith;
else if «a==1) & (b=-O))
then 1 with
dir_up := 0;
endwith;

endmotcdir

______________~-----------',I~~--------------------------'#(#1.
3-291

I'SD5XX - Application Nots 039

Stimulus File

STIMULUS file:
IIStimulus file for setting up of the counter/timers in
Ilevent count mode, and for testing the direction
Ilrecognition state machine.

Ilused to hold data read from PSD

reg [7:0] dat_val;

a+++++++++++++++++++++++++++++++++++++++++++++++++
II

User-Defined parameters

a+++++++++++++++++++++++++++++++++++++++++++++++++
parameter cntrOL='hC098, cntrOH='hC099, imgOL='hC090,
imgOH='hC091 ;
parameter cntr1 L='hC09A, cntr1 H='hC09B, img1 L='hC092,
img1 H='hC093;
parameter cmdO='hCOAO, cmd1 ='hCOA 1;
parameter g_cmd='hCOA8;
parameter dlcy='hCOA6;
parameter freeze='hCOA4, status='hCOA9;

a+++++++++++++++++++++++++++++++++++++++++++++++++
II

Defining tasks to simplify writing the stimulus file

a+++++++++++++++++++++++++++++++++++++++++++++++++
task write (addr_bus,data_in);
input [15:0] addr_bus;
input [7:0] datajn;
begin
#20 ale = 1;
#20 adio = addcbus;
#20 ale = 0;
#20 adio = data_in;
#40 wr= 0;
#100wr= 1;
#10 adio = Z16;

Ilhigh true ale
Iiset-up the right address
Illatches address
Ilwrite operation
Ilwrite starts
Ilwrite ends

end
endtask
task read (addr_bus);
input [15:0J addr_bus;
begin
#20 ale = 1;
daLval = 'hOO;
#20 adio = addr_bus;
#20 ale = 0;
#20 adio = Z16;
#40 rd = 0;
#50 daLval = 'adiol;
#50rd=1;

Ilactive high ale
Ilclear daLval register
Iiset-up the right address
Illatches address
Ilfloat address bus
Ilread starts
astore low byte of adio
Ilread ends

end
endtask

-3--2-9-2---------------------------------~~~~------------------------------------

PSD5XX - Application Nots 039

Stimulus File

task psen (addcbus);

(Cont.)
input [15:0] addr_bus;
begin
#20
#20
#20
#20
#40
#100

/lactive high ale
/lset-up the right address
//Iatches address
//float address bus
//PSEN read starts
//PSEN read ends

ale = 1;
adio = addcbus;
ale=O;
adio = Z16;
psen = 0;
psen = 1;

end
endtask

11*·*·*******·****·***·*·*·* Begin stimulus **************************

initial
begin
wr = 1; rd = 1; psen = 1;
ale = 0;
clkin = 0;
reset = 0;
csi = 0;
adio ='hOOOO;
a = 0; b = 0;
#500 reset = 1;

/lend reset cycle

/lClear counter/timers-O and -1
#300 write(cntrOL, 'hOO);
write(cntrOH, 'hOO);
write(cntr1 L, 'hOO);
write(cntr1 H, 'hOO);

//Clear image registers-O and -1
write(imgOL, 'hOO);
write(imgOH, 'hOO);
write(img1 L, 'hOO);
write(img1 H, 'hOO);

//Clear delay cycle register so that clkin is scaled by 4
//(i.e. when the scale bit in the Global Command register
//is set to 0)
write(dlcy, 'hOO);

-----------------------------------~~~--------------------------------3.-2--93

Stimulus File
(Cent.}

I/Set command register, CMDO, to configure tlmerO for event mode
l/with the event coming from the macrocell, rnc2tmrO

IILSB
/I
/I
/I
/I
/I
/I
/I
/I
/I
I/MSB

0
1
1

X
X
0
0
0

Event count mode
Increment mode
Select (enable) timerO
No timer output in this mode
Pin-input polarity is not needed since the
event Is macrocell driven
Input command from macrocell
(if set to 1 then from pin)
Load/Store command from PinlMacrocell (in this
case macrocell) allowed through
EnableIDlsable by PinlMacrocell

write (cmdO,'h1 E);
I/Set command register, CMD1, to configure timer1 for event mode
l/wlth the event coming from the macrocell, mc2tmr1

IILSB

0

/I
/I
/I
/I
/I
/I
/I
/I
/I

1
1

IIMSB

X
X
0
0
0

Event count mode
Increment mode
Select (enable) timerO
No timer output in this mode
Pin-input polarity is not needed since the
event is macrocell driven
Input command from macrocell
(if set to 1 then from pin)
Load/Store command from PinlMacrocell (in this
case macrocell) allowed through
EnablelDisable by PlnlMacrocell

write (cmd1,'h1E);
I/Set the Global command register to enable the counterltlmers
/lin eventltime-capture mode

IILSB

0
Scale bit (0 = divide by 1, 1 = divide by 8)
/I
1
Counter start bit - enables all the selected
/I
counters
/I
Global mode bit - set for eventltime capture mode
/I
0
Watchdog disabled
IlBlt4-7 are reserved and set to 0
write (Q..cmd,'h06);
I/perform a freeze!freeze acknowledge cycle on both tlmerO and-1
#2000 wrlte(freeze,'h03);
l/walt for both freeze acknowledge flags to be set in
I/status register (status = 'h3)
while (daLval <= 'h2)
begin
read(status);
end

-3--2.N----------------------~~/-----------------------

I'SII5XX -

StImulus File
(Cent.)

_"_',n "".

1181

llreset freeze bits
#1000 write(freeze, 'hOO);
llperform a second freeze/freeze acknowledge cycle on both
l!timerO and·1
#10000 write(freeze,'h03);
IIwait for both freeze acknowledge flags to be set in
IIstatus register (status = 'h3)
while (daLval <= 'h2)
begin
read (status);
end
llreset freeze bits
#1000 write(freeze, 'hOO);
end

1/*···············

Continuous signals •••••••••••••• *••

IIGenerate A and B pulse streams
always
begin
IIProduce "a" and "b" input pulses with "a" leading "b" by 90 degrees
repeat (6)
begin
#500a=-a;
#500 b= -b;
end
IIProduce pulses with "b" leading "a" by 90 degrees
repeat (3)
begin
#500b= -b;
#500a= -a;
end
end
IIGenerate a continuous clock signal
always
#25 clkin = -clkin; 1/20 Mhz

----------------------~Jr;----------------------3·295

PSD5XX - Application Note Oa9

~~~

a.296

____________________________

'.8~E

'tii#.::/I! "

_________________________________

=

--..5F==~~
_--~

=:"""=-iii=_=-!!i"'::

~~~-

Programmable Peripheral
Application Note 042
Four Axis Stepper Motor Control Using

a Programmable PS05XX MCU Peripheral
from WSII Inc.
By NaSSllr PoD/ad/an, Data Card Corp.

Introduction

The design of a stepper motor control requires various timers and electronic controls. This
application note explains the basic operation of a stepper motor. It also presents the theory,
implementation and electronic control of a four axis stepper motor control using the
PSD5XX family of products from the WSI Inc. The PSD5XX, as a field programmable
microcontroller peripheral device, provides a high degree of integration on the embedded
controller design. Configuration of the memory, ease of interface to various different
microcontroller buses, interrupt handling, I/O ports, and four sixteen bit counter/timers make
this device a great candidate for embedded applications.

Stepper Motor
Operation

A stepper motor is basically a rotational actuator which rotates a fixed anglewhen excited.
A stepper motor can be directly controlled electronically without the need for a feedback
element (encoder, tachometer feedback, etc.) as required in servo applications. The simpler
drive and control electronics needed by a stepper motor makes it a good candidate for a
positioning actuator in many different motion control applications. Several different types of
stepper motors are used in the industry.
A hybrid stepping motor is used in this application. The rotor and stator are multi-toothed in
a hybrid stepping motor and the rotor is magnetized in the axis of the rotor shaft. When
properly driven, a hybrid stepping motor will step 1.8 degrees in the full step mode and 0.9
degrees in the half step mode. Figure 1 shows a typical hybrid motor.

Figure 1. Hybrid Stepping Motor

3-297

'SD5XX - AppllcatlllR Nllt. 042

Stepper Motor
Operation
(CIIRt.)

The stator windings in a Hybrid stepper motor are distributed in 90-degree quadrants
around the motor case. See Figure 1 for the phase winding distribution of the hybrid motor.
Different methods are used for the excitation of a stepper motor. In this application a bipolar
drive circuit is used for the power stage. The motor windings are connected 90 degrees
apart such that the stepper motor looks like a two-phase motor. In this case there are four
motor leads to be powered from the amplifier stage. Each phase of this stepper motor is
powered by an H bridge. Figure 2 shows a typical H bridge that drives a stepper motor and
Figure 3 illustrates the driving waveforms.

Figure 2.

nvo HBridges for Driving a nvo Phase Stepper Motor.
+V

PHASE A

PHASES

Figure 3. Phase Excitation in a Bipolar Stepping Motor.

Q1 AND Q4 ON

I

Q2 AND Q3 ON

I

Q1 AND Q4 ON

I
...---

PHASE A

I

Q1 AND Q4 ON

PHASE B

90° PHASE SHIFT

I

Q2 AND Q3 ON

I

Q1 AND Q4 ON

!---I~I----.
--.1 1.-

-----------------------------------rAr4f~~----------------------------------3.298
=== !!E

PSD3XX - Application Note 042

Stepper Motor
Operation
(Cont.)

Phase timing for a stepper motor could be designed by either a combination of logic and
linear electronics or by some stepper motor control IC's such as the L297 stepper motor
controller. Figure 4 shows a block diagram of a stepper motor control and the L297 is used
as the stepper motor control IC. The L297 provides control to an amplifier in the current
mode. The chop frequency for the L297 is set to 20KHz. Chop frequency is used to regulate
the amount of current in the motor windings. The current reference to the motor windings is
set by a pair of resistors. The L297 is configured to FULL STEP mode. The
ENABLE/DISABLE and axis DIRECTION control are controlled from PORT B of the
PSD503B1. An electrical schematic using the L297 is given in Figure 13.

Figure 4. Simplified Block Diagram for a Stepper Motor Control

-..

DIRECTION

PHASE A
CONTROL

CLOCK

PHASEB
CONTROL

ENABLE

BRIDGE
CONTROL

CURRENT

PHASE B
POWER
BRIDGE

PHASE A

SENSE
SENSE PHASE 1
SENSE PHASE 2

-----------------------------------~Jr~~----------------------------------3-299

PSD5XX - Application Note 042

Stepper Motor
Clock
Generation
by Using a
PSD5XX

Figure 5 shows a timing diagram for the control of the phases in a stepper motor control
where the steps and the step rate are controlled by clocks. The variation of the clock rate or
the variation of the time between the two clock pulses determines the step rate. Change in
the step rate determines the acceleration, deceleration, and the slew rate in a given motion
profile.
Figure 6 shows a typical trapezoidal motion profile. In the acceleration mode the step rate
starts slowly and as the motion progresses the step rate increases according to a step rate
table until it reaches the slew rate. At the slew rate the step rate is fixed and the period of
the step clocks is constant. At the end of the slew rate the deceleration starts. In this part of
the profile the step rate decreases according to a step rate table until the last step. The
repeatability and accuracy of the step clocks in a stepper motor plays a major role in the
stepper motor performance.

Figure 5. Timing Diagram for a Stepper Motor Control

-'1
STEP CLOCK
FROM PSD503
TIMER
PHASEA

PHASEB

1'-

ONE STEP TIME

--~Ir-----'~--~

~

I

-------------------------------------,~~~~-----------------------------------3-300
~ii!§ i6

PS05XX - Application Not, 042

Stepper Motor
Clock
Generation
by Using a
PSD5XX
(Cont.)

Figure 6. Typical Trapezoidal Speed Profile

.

STEP CLOCKS

RAMP UP

I

SLEW RATE

I

RAMP DOWN

~~.~----------~~~.

~

I

MOTOR VELOCITY PROFILE

11. . .
. ----------

PROFILE TIME

------------...~I

Figure 7 shows the programmable PLD (PPLD) macrocell for each counter/timer block
diagram in the PSD5XX. In this design the four 16 bit timers on the PSD5XX are used to
control a four axis stepper motor under microprocessor control. The four 16-bit timers in the
PSD5XX are configured in the pulse mode. The Timers are loaded with a given step count
for the duration of a pulse. When the pulse duration has expired, the logic on the PSD5XX
is programmed such that the respective timer is preloaded with the count from the Image
Registers. By preloading the timer, the step pulse duration will be exact with respect to the
applied clock frequency. The timer clocks are configured to run at 1-MHz. In this case the
preloading time on this system is based on a "one step ahead" stepper motor control. On
the ramp up and ramp down mode each step clock will be preloaded in the image register
because of the step rate changes. When the time for each step has expired the respective
timer automatically preloads the image register in the count register and continues the new
count. In this design the terminal count outputs (TCO - TC3) of the timers are routed to the
four inputs (INTO- INT3) of the interrupt controller on the PSD5XX device. The timer
outputs are inverted and connected to the timer macrocell outputs MC2TMRx (x = 0-3 for
three timers) in the PPLD logic. Figure 8 shows a simplified block diagram for the four axis
stepper motor control.

-----------------------------------r=~~~----------------------------------~'::"=:=

3-301

~~~~t!~
:::at;
:::IQQi

~
~

'::~&=Qln~
~S·; ~Qi

:.c-!"to
- -.

-g

...
=~

i!
~
:.c:
I

i"::::

S'
fa
"'i
;t
1&
~

cQ'
~
CII
~

TIMER_CLOCK
(PRESCAlED ClK)

TIMER
INPUT PIN

;g

s

TIMER [3 : OJ_IN
ZPlD
INPUT
BUS

In
an

--------PTT-O
PTT-1

I

Q
~iQIII
IUi
"

MC2TMR

MUX

II:~

AND
ARRAY

D

*

---

I

INPUT
MUX

I

PR

•I
COUNTER/
TIMER

Q

!:
...c:r
t'
g.
f1

...§

C Q

~

~
§,

COMB/REG
SELECT
.ablFllE

BIT 5 OF
COMMAND REGISTER

WDOG2PlD (INTERNAL FEEDBACK)

ClKlN

RESET

"These are four similar Macrocells with outpU1s MC2TMR[3:0J

!t

it
;r

~

I'SD5XX - Application Note D42

Steppef MOtOf
Clock
Generation
byUs/nga
PSD5XX

Figure 8. Simplified Block Diagram for the System

.It

"~

(CDnt.)

8OC186
MICROPROCESSOR

~

I

"

I I

I:

"

16 BITS ADDRESS/DATA BUS

17 BITS ADDRESS
PSD503

"- CONTROL SIGNALS & INTERRUPT
'I

,

SRAM

...

"-

TIMERS [0:31 OUTPUTS & LOGIC CONTROL BUS

4

~

LOGIC FOR
STEPPER
MOTOR
CONTROL

4

4
4

AXIS #1
AXIS #2
AXIS #3
AXIS #4

•

..
..
..

POWERAMP'1
POWERAMP'2
POWERAMP'3
POWERAMP'4

-

--.
---.

r-

I
STEPPER'1
STEPPER'2
STEPPER'3
STEPPER #4

The output of the PSD5XX interrupt controller is connected to one ot the interrupt inputs
on the 80C186 microprocessor. The PSD5XX interrupt controller interrupts the
microprocessor in response to the timer underflow. In response to this interrupt, the
microprocessor reads the INTERRUPT PRIORTY STATUS REGISTER and updates the
respective timer image register. The output of a timer makes a high to low transition when a
timer count expires.The high to low transition of the timer is inverted and is used to preload
the respective timer from the last image register. In the slewing mode the IMAGE
REGISTER for a timer does not need to be preloaded on each step interrupt. As the timer
count expires the old count will be pre-loaded automatically. Figure 9 shows the logic
configuration for a given axis and Figure 10 shows the *.abl file listing for the preloading
capability of the timers.

----------------------------~Jrjr------------------------~~
3-303

~
~

i~~~t!~
=at;
::I Cfti
.s: ~
i=
fti ~~
:aoc S' ia
•

&l

~

~
'15
::::

~1Ci::t

-!$I

...

...

S'

~

~
I

&I
;t
II

1=

~

cQ'
~
CIi

......

......

COUNTER OUTPUT (PORT A OR B)

START COUNTER (BIT 1 OF GLOBAL COMMAND REGISTER)

!O
po.

.:;:;'
FREEZE ACKNOWLEDGE
(STATUS FLAGS REGISTER)

SOFTWARE FREEZE ( FREEZE COMMAND REGISTER)

f1
=:a

.;:
~

OUTPUT POLARITY SELECT (BIT 3 OF CMD REGISTER)

Qj

'lIii""

Ilil=
llbll~
II_I,,"

;!:

SOFTWARE SELECT BIT (BIT 2 OF CMD REGISTER)

ENABLEIDISABLE
TERMINAL COUNT (TC)
TO INTERRUPT CONTROLLER

ENABLE COMMAND (BIT 7 OF CMD REGISTER)

COUNTER

-1---------I

PIN OR MACROCELL
(SELECTED BY BIT 5 OF CMD REGISTER)

LOAD/STORE

I
I

=
~
~

m
~

TERMINAL COUNT (TC)
TO PORT E

-----------.-

iii'

~
;sCD

SOFTWARE GATING BIT
(BIT 6 OF CMD REGISTER)

SOFTWARE LOAD (SOFTWARE LOAD/ STORE REGISTER)

INCREMENTIDECREMENT SELECT (BIT 1 OF CMD REGISTER)

TIMER_CLOCK

f

:t

iit

~

PS05XX - Application Not. 042

Stepper Motor
Clock
Generation
by Using a

PSD5XX

(Cont.)

80C186
Interface to the

PSD503

Figure 10. ASample PPLD Configuration in an *.abl File for the PSD5XX
"PPLD Equation for the Timer to Preload
mc2tmrO
mc2tmr1
mc2tmr2
mc2tmr3

=
=
=

(!timeroutO);
(!timerout1 );
(!timerout2);
(!timerout3);

Figure 11 shows a block diagram of a PSD5XX family product. In this design the PSD503 is
used. The PSD503 is configured to 64K x 16 EPROM in MUX mode. The address and data
on the 80C186 are multiplexed so the PSD503 latches the address internally. The address
lines A16 and A17 are internally latched using PA6 and PA5 from the PSD503 ports. Ports
PCO - PC7, PD~ - PD7, PE3 and PE4 on the PSD503 are used to output the address
AO - A 17 externally to be used by the 128K x 16 SRAM external to the PSD503 device.
PAO through PA3 are used as timer outputs to provide clocks for the stepper motor control.
Figure 12 shows the schematic for the processor connection to the PSD503 and Figure 13
shows a schematic for a typical stepper motor control unit interface to the PSD503. The
stepper motor interface control uses PBO - PB5 to control the four L297 stepper motor
control chips. PBO and PB1 are used to enable and disable the four axis of the motion. PB2
through PB5 are used to control the direction of the motor motion. PBO through PB7 are
configured in the software. Figure 14 shows the *.ABL file used in this design.

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ i'iIiI Efii§
~~·---------------3-~-O-5

~
g:

.-----------------------------------------------------------------------------------------------------,I~

~

ADDRESS/DATA/CONTROL BUS

~

~

~

ZPlD
INPUT
BUS
VSTDBY
CONTROL
RD,WR

PROG.
BUS
INTRF

~

ADO-AD15

111"011

PCO-PC7

111111

1IIIftii
Ilhlllll
Ilftlllll

ADIO
PORT

61

p

PROG.
PORT

•

I~nl·lc:": •

~

;~:~

PROG.
PORT

p

PORT
D

ClKIN

I

I

60..

ClKIN

--

;

PROG.
PORT
PORT
E

PERIPHERAL
PlD (PPlD)

.---=::---t,.--+-.J~

.:;:.

ClKIN

WATCH DOG OUTPUT

GLOBAL
CONFIG.
&
SECURITY

I
:to

~ ==::::
2
~ ::!:

ii'

~

~

A

,,..anl""CII

PDO-PD7

PAO-PA7

PORT

PROG.
PORT

~

~ :51~
!!
;Q
Q. ~
It::!

Ir----.

I

;,:
51

PBO-PB7

PEO-PE7

~

cQ'
!;

.5V

CIi

186..A(O

117)

"""
~
~
=*'

I

1\1

if-

...cr
sCII

RST_188

.5V

~

R23
47K

51

a!i'
iit

R24
47K

WSU(O

3), 'NSLT(O

3)

1

',,""
1101
116
,Jloo

'.lllh

STEP_D (0

3)

11011111
"

STEP_0 (O

1)

STEP_D (0
( STEP E (0

3)
1)

i
Q
a1\1

=
It
~

::,

g
U56

l.'

ll:Sti-Al

• ..,<> .. "

U
..

lAO
A1

a
s:

A2
A2
A4
AS

A6
A7
AS

A9
A10

A11
A12
A13
A14
A15

.5V

\

1111

~liJ
MB841000-BO

~

186_AD (O

15)

~

5t
~
I

t

~

;:

8

~
Cit

!

c:>
~

~, __we~~J~(~O_3~)__________,

Co

T

R11

I

r

U7

i-1~

I33 I

22K

STE~
P_DO

.,

STEPPER

0"9

~~[]J~
2

~
HOME

T

ISTEPLc~

~

HlF

EN

CW/CCW
CLK

.---:;....1:"
S2

GNo

::

Sf-6

C 7

AMP FOR

o

STEPPER
.2

9

~,

STEPPER MOTOR
= 2 CONNECTION

CONN 4
INH1
INH2

HOME

lit

a

I

=
Q,

r--------------~====~=t=t~~~~~~~~~~'2~~~-----:~
grr:
1~

'111'1111

5V

STEP_E1
_

~
~
R
R
R

_T2

Vee

~F

19
11

SYNC
HIF

B

10
17

eNTAl.

C

EN

18

ccw

R

51

'r
~
~
R
R
R

I

R

STEP_D (0 3)
STEP_E(O 1)

~~

I'~~~==~~~~~~~~~C~
EN

CW/CCW
CLK

51

RES

)

~€

STEPPER MOTOR
= 3 CONNECllON

INH1

~

INH2
HOME

!t

~
::.

~
;::
!t

A"4

S,6
C"7
0. 9

INH1.~!========::l

INH2
HOME

3

AMP FOR
STEPPER

#4

Ii.....

il

CONN 4

U7

VREF
SYNC
HIF

SlEP....AESET

E (0. 1n

'3

S
CI

1

GND

I ,STEP

AMPFQR
STEPPER

0

--::c

52

SlEP_D (0 3

t-----------------J

RES
S2
GND

.5V

A

-

I'
Ig

;J

tbH~!========I
t-r--

U1

lIIi'IbI

~

iii'
S'

A"4

.5V

I~

if

;;:

II

U1

~ E t~=l=J~~~~~~~~~~C~
R

....

:Iool

i

t:1~
15

R22-

R

II

---:r
VREF
SYNC

1

~

CI

~

STEPPER MOTOR
'" 1 CONNECTION

CONN 4

PF

.5V

AMP FOR

C" 7

-l-C7

R12

;?'!
§;
~

A" 4

S"6

A7

CCIi

~~

CONN4

STEPPER MOTOR
= 4 CONNECllON

~
I

t::::::

=
II
;t

~
Il

~

PSD5XX - Application Note 042

80Ct86

Figure 14. Program Listing for the ABEL File Used in this Design

Interface to the

PS0503
(Cont.)

module mfhs_1S
title 'DESIGN FOR PSD503 ABEL source file to interface with 80C18S';

"Input signals
"Address lines, using reserved names.
a15,a14,a13,a12,a11 ,a10,a9,a8,a1 ,aO pin;
wr pin;
rd
pin;
bhe pin;
a16 pin
a17 pin
add_16
add_17

21;
22;
pin 34;
pin 31 ;

"high order address input
"high order address input
"address 16 latched output
"address 17 latched output

" PINS DEDFINED BY NPK "
umcs pin;
Imcs pin;

" Upper Memory Chip Select
" Lower Memory Chip Select

emcs pin;
omcs pin;

" even memory chip select for external SRAM
" odd memory chip select for external SRAM

pcs3 pin;
pcs2 pin;

" PSD Upper 256 bytes address chip select space
" PSD Lower 256 bytes address chip select space

pbO, pb1, pb2, pb3, pb4, pb5 pin; "Stepper motor Control Port
" Timer Contol Pins"
timeroutO
timerout1
timerout2
timerout3

pin;
pin;
pin;
pin;

"
"
"
"

Stepper 1 Clock 1
Stepper 2 Clock 2
Stepper 3 Clock 3
Stepper 4 Clock 4

" Port Control"
pdO, pd1, pd2, pd3, pd4, pd5, pd6, pd7 pin;

" Upper Address Output"

pco, pc1 , pc2, pc3, pc4, pc5, pc6, pc7 pin;

" Lower Address Output"

clkin, reset pin;

"using the reserved names.

"Output signals
csiop, rsO, esO, es1, es2, es3 node; "DPLD output chip selects
mc2tmrO node;
" PPLD Output To Timer
mc2tmr1 node;
" PPLD Output To Timer 1 "
mc2tmr2 node;
" PPLD Output To Timer 2 "
mc2tmr3 node;
" PPLD Output To Timer 3 "

°"

-----------------------------------~.;r~----------------------------------3·309

I'SII5XX - Ap"II.'#IIIIII.tell42

8DC186

FI,u1II14. Pto,ram UBlln, fDr the ABEL File Used In this Desl,n (c.nt.)

PS05D3

"General outputs

Int.tfac. to the

(c.nt.)
"DEFINITIONS

"page =
CK =
=
X
Address

[pgr3,pgr2,pgr1,pgrO];"
.C.;
" Clock pulse definition
.x.;
" Don't care
= [a16,a 1S,a14,a13,a12,a11 ,a10,a9,a8,X,X,X,X,X,X,a1,aO];

Add = [pc7,pc6,pcS,pc4,pc3,pc2,pc1,pcO];

equations
"DPLD EQUATIONS
csiop = «Address >= Ah00100) & (Address <= Ah001ff»;
rsO
0; " Disable The 2k On Board SRAM "
(Address >= AhOOOOO) & (Address <= Ah07fff) & (!umcs);
esO
(Address >= Ah08000) & (Address <= AhOffff) & (Iumcs);
es1
es2
(Address >= Ah10000) & (Address <= Ah17fff) & (!umcs);
es3
(Address >= Ah18000) & (Address <= Ah1ffff) & (!umcs);

add_16 = a16;
add_17 = a17;

"32k block 0
"32k block 1
"32k block 2
"32k block 3

"Address 16 latched output"
" Address 17 latched output"

emcs = (IImcs & bhe & laO) + (IImcs & !bhe & laO);
omcs = (IImcs & Ibhe & aO) + (IImcs & lbhe & laO);

" even address SRAM chip select
" odd address SRAM chip select

"PPLD Equations
mc2tmrO = (!timeroutO);
mc2tmr1 = (Itimerout1);
mc2tmr2 = (Itimerout2);
mc2tmr3 = (!timerout3);

" Pre
" Pre
" Pre
"Pre

Load Timer 0 "
Load Timer 1 "
Load Timer 2 "
Load Timer 3 "

" *************************.*.**********************************.************.****** •• ************** •••

TEST VECTORS
'I ***************************************************************** ••• *******************************.*

----------------------',,':----------------------3-310
JINIIIIt

I'S/J6XX -

_186
Infllrlac. to the

_"C1t/,,, 1Iote.

FI,.re 15. BI.ck Dla,,.., fill tile ''Ilster CtnIfI,.tBtl.alld
Int."""t Optntl.n

PSD51J3
{CoIIt.}
PSD503 Timer Initialization
Load Command Register for Each Timer by Oxe9
Read Interrupt Read Register To Clear All Interrupts
Select all Interrupt Inputs to Rising Edge
Unmask the Timer Interrupt in Mask Register
Configure the 800186 Interrupt
Load Counter Count Register with New Count
Load Image Register for the Timers
Set DLCY Register to Ox04
Select Port A for Timer Output
Load Image Register for The Timers
Select Software LoadIStart for the Start up
Enable the Timers from Global Register

I

Enable the Respective Timer for Operation

I

I

I

r - - - - - Il Walt for Interrupt 1
. .- - - - - - - - - - - - ,

NO
Interrupt Occurred?

YES

Read Interrupt Priority Register
Determine the Respective Timer Interrupt
Load the Respective Image Register for the Timer

-----------------------~Jrl----------------------3-311

I'SD5XX - Application Note D42

8OC1B6
Interface to the

PSD5D3

(Cont.)

Figure ". ASamplll *.C Program fOl this Application (Cont.)
linclude
linclude
linclude
linclude






typedef unsigned short USHORT;
typedef short
SHORT;
typedef unsigned long* PULONG;

1* Stepper Profile Table *'

linclude "x_step.dat"
Idefine
Idefine
Idefine
Idefine
Idefine
Idefine

PCSO
PCS1
PCS2
PCS3
PCS4
PCS5

OxOOO
Ox080
Ox100
Ox100
0x200
0x280

1* WSi Registers
*'

3-312

Idefine
Idefine
Idefine
Idefine
Idefine

WSilNTRREAD
WSilNTRMASK
WSilNTRMODE
WSilNTRREQ
WSilNTRPRI

PCS2+0xD4
PCS2+0xD3
PCS2+0xD2
PCS2+0xD1
PCS2+0xDO

1* Interrupt Read Clear *'
1* Interrpt Mask Register *'
1* Interrupt Edge'Level *'
1* Interrupt Request Latch *'
1* Interrupt Priority *'

Idefine

WSiSLR

PCS2+0xa5

1* Software Load'Stor *'

Idefine
Idefine
Idefine
Idefine

WSiCNTRO
WSiCNTR1
WSiCNTR2
WSiCNTR3

PCS2+0x98
PCS2+0x9A
PCS2+0x9C
PCS2+0x9E

1* Timer 0 control
1* Timer 1 control
1* Timer 2 control
1* Timer 3 control

Idefine
Idefine
Idefine
Idefine
Idefine
Idefine
Idefine
Idefine
Idefine

WSiCMDO
WSiCMD1
WSiCMD2
WSiCMD3
WSiDLCY
WSilMGO
WSilMG1
WSilMG2
WSilMG3

PCS2+0xaO
PCS2+0xa1
PCS2+0xA2
PCS2+0xA3
PCS2+0xa6
PCS2+0x90
PCS2+0x92
PCS2+0x94
PCS2+0x96

1* Timer 0 Control Register *'
1* Timer 1 Control Register *'

Idefine
Idefine
Idefine

WSiGLBREG
WSiSFR
WSiFREEZ

PCS2+0xa8
PCS2+0x08
PCS2+0xA4

1* Timers Global Register *'
1* Special function register for port A *'

Idefine
Idefine

WSiPORTB_CNTR
WSiPORTB_DIR

PCS2+0x03
PCS2+0x07

1* Port B Configuration *'

Idefine
Idefine

WSiPORTC_CNTR
WSiPORTC_DIR

PCS2+0x12
PCS2+0x16

1* Port C Configuration *'

Idefine
Idefine

WSiPORTD_CFG
WSiPORTD_DIR

PCS2+0x13
PCS2+0x17

1* Port 0 Configuration *'

Idefine
Idefine

WSiPORTE_SFR
WSiPORTE_DIR

PCS2+0x28
PCS2+0x26

1* Port E Configuration *'

".'~

'f!!H!!1I! ,

*'
*'
*'
*'

1* Scale Factor Control Of Timers *'
1* Timer 0 Image Register*'
1* Timer 1 Image Register*'
'* Timer 0 Image Register*'
'* Timer 1 Image Register*'

PSD5XX - Application Not. 042

80C186
Interface to the
PSD503
(Cont.)

Figure 16. A Sample *.C Program for this Application (Cont.)
#define
#define
#define

WSiPORTE_OUT
WSiPORTE_IN
WSiPORTE_CFG

PCS2+0x24
PCS2+0x20
PCS2+0x22

#define
PULSE_MODE_DISABLED
#define
ENABLE
1* 188 Registers

*'

#define
#define
#define
#define

'*
*'
int
int
int
int
int
int
int
int
int
int
int
int

IOCON
11CON
IMASK
EOI

Ox99
Ox04

*'

1* was 99
1* was 00*'

OxFF38
OxFF3A
OxFF28
OxFF22

Global Variables Here

SteppeU_Total_Step_Count;
Step_1_Max_Slew_Count;
Step_1_Motion_lndex;
Step_1_Motion_Stat;
Step_1_Slew_Count;
Stepper_1_Ramp_Up_Count;
Stepper_1_Ramp_Down_Count;
Stepper_1_Step_Count;
Stepper_1_Step_Time;
Step_1_Time;
Step_1_CounCOld;
Stepper_1_Profile[20];

USHORT Image;
USHORT MotorNum;
1*
INTERRUPT 1 ROUTINE

*'
USHORT Port = WSilNTRREAD;
USHORT iw;
void _interrupt WSiHandler(void)
{
static USHORT Read;
Image = Ox200;
switch( inportb(WSilNTRPRI) & Ox07)

{

..

.,

;~

----------------------------------~Sf.---------------------------------

3·313

PSD5XX - Application Note 042

SOC1S6

Figule 16. A Sample '/t.e Ploglam tOI this Application (Cont.)

Interface to the
PSD503

case 0:
outport(WSilMGO, Step_13ime);
Stepper_1_Step_Count++;
break;
case 1:
outport(WSiIMG1, Image);
break;
case 2:
outport(WSilMG2, Image);
break;
case 3:
outport(WSilMG3, Image);
break;

(Cont.)

1* Load Timer 0 for step pulse *f

}
outport(EOI,Ox8000);
_enableO;
}
void IniCTimers(void)

{
PULONG pIVT=NULL;
_disableO;
Image = 100;

1* Pulse Mode Timer 0-3
*f

1* Program Command Register For The Counters *f
1* All Counters to Pulse Mode *f
1* All Counters Disabled *f

outportb(WSiCMDO, Ox99);
outportb(WSiCMD1, Ox99);
outportb(WSiCMD2, Ox99);
outportb(WSiCMD3,Ox99);

1* Interrupt WSi Setup
*f
inportb( WSilNTRREAD);
outportb(WSiINTRMODE,OxOO);
outportb(WSiINTRMASK,OxOf);

1* Clear All The Interrupts *f

outportb(WSiPORTE_SFR,OxOd);

1* Confgure Port E For Special Function *f

1* Unmask Timers Interrupt *f

1* Interrupt 188 Setup
*f
pIVT[12] = (PULONG)SensorlntO;
outportb (IOCON ,Ox012);
pIVT[13] = (PULONG)WSiHandler;
outportb(11 CON,Ox01 0);
outportb (IMASK,OxDD);
Image

1* Sensor Interrupt *f
1* Disable sensor inerrupt *f
1* Interrupt # 1 Initilization *f
1* Was level sensetive Ox07 */

= 0;

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ !f'IiI= #Sff

3·314

.".#~§

----------------

PSD5XX - Application Nots 042

BoCtB6

Figure 16. A Sample *.C Program for this Application (Cont.)

Interface tD the

'50503
(Cont.)

outport(WSiCNTRO,
outport(WSiCNTR1,
outport(WSiCNTR2,
outport(WSiCNTR3,

OxOO);
oxOO);
oxOO);
OxOO);

outportb(WSiDLCY,
outportb(WSiSFR,

Ox04);
OxOf);

outport( WSilMGO,
outport( WSilMG1,
outport( WSiIMG2,
outport( WSilMG3,

Image+Ox340);
Image+Ox300);
Image+0x260);
Image+0x220);

outportb(WSiSLR,OxOF);
outportb(WSiGLBREG,Ox02);

/* Configure The Wsi Global Register *f

_enableO;

/* Enable Interrupt *f

/*
This Routine Sets up timer 0 for the start up profile

*f
void Step_1_lnit(void)

(
static SHORT s_en1 ,s1_c;
static SHORT c_r1 ,c_r2,m_c;
Stepper_1_Step_Count = 0;
Step_1_CounCOld = 0;
Stepper_1_Step_Count = 0;
Steppec1_Total_Step_Count =1000;
Step.:...1_Max_Slew_Count = 998;
Step_1_Motion_lndex = 0;
Step_1_Slew_Count = 0;
SteppecCRamp_Up_Count = 5;
Stepper_1_Ramp_Down_Count = 7;
Step_1_Motion_Stat = 0;
Step_1_Time = Ox3000;
outportb(Step_Motor1_Control,s_en1);
outportb(WSiCMDO, Ox9d);

f* Set Up For Ramp Up *f
/* Reset Motor State *f
/* Enable Timer 0 for stepper 1 *f

f*
This routin is used to update the profile table for motor 1

*f
void Steppec1_Move(void)

(
if( SteppeU_Step_Count > Step_1_CounCOld)

{

----------------------------------~~~---------------------------------3-315

PSDSXX - Application Not. 042

SOC1S6

Figure 16. A Sample *.C Program for this Application (Cont.)

Interface to the
I'S0503

if( Step_1_Motion_Stat == 0 )

{

(Cont.)

Step_1_Motion_lndex++;
1* ••••• RAMP UP STEPPER 1
Step_1_Time = x_axis[Step_1_Motion_lndex];
if( Step_1_Motion_lndex == 132)

······f

{
1* Set Status For Slew 'f

if( Step_1_Motion_Stat == 1 )

{
Step_1_Slew_Count++;
1* ••••• SLEW FOR STEPPER 1
if( Step_1_Slew_Count == Step_1_Max_Slew_Count)

······f

{
Step_eMotion_Stat = 2;
1* Set Status For Ramp Down'f
Step_1_Motion_lndex = 132;

if( Step_1_Motion_Stat == 2)

{
Step_1_Motion_lndex-;
if( Step_1_Motion_lndex!= 0)

1* ••••• RAMP DOWN FOR STEPPER 1

······f

{
}
if( Step_1_Motion_lndex == 0)
{
SteppeU_Step_Count = 0;
Step_1_CounCOld = 0;
outportb(WSiCMDO, Ox99);
1* Disable Motor'f
outportb(WSiCMDO, OX99);
1* Disable Motor. This is Just For Ice 'f

Step_1_CounCOld = Stepper_1_Step_Count;

}
}

:I';;:,gilJ/llJ#E

-3--3-16----------------------------~Jr~~------------------------------

I'SD5XX - Application NDt. D42

BOC1B6

FI,ure 16. ASample

!/t.e l'nI,ram fDr this AppllcatlDn (CDnt.}

Interface tD the

PSD503

(CDnt.}

main()

{
static USHORT Read, y, d1=OxAA,d2=OxAA;
static USHORT key;
IniCTimers();

key = 1;
while(1)

{
switch( key)
{
case 1:
Stepper_1_Move( );
break;
case 2:
stp_2();
break;
case 3:
dcm_1();
break;
case 4:
dcm_2();
break;
case 5:
cres_12();
break;
case 6:
C188_1520;
break;

return 0;

}

-----------------------------~~~----------------------------3-317

",D5XX - Appllt:JItion Not. D42

Software
Configuration
of the PS0503

Figure 15 shows a block diagram of the steps needed to configure the registers of the
PSD503 for this application. Figure 16 shows a sample software program written in C that is
used in this application to configure the PSD503. This software programs the special
function register of Port A to be used as the timer outputs. Figure 17 shows the PSDSOFT
configuration of the timers. The PSD503 must be configured through PSDSOFT for the
BUS type, WR, RD, INTR and PORT operation.
The timer clock frequency is configured through the DLCY register to 1MHz. As the step
rate increases the step rate accuracy deteriorates due to the quantization effect. The
quantization effect is not a problem in this application. The output pulse width of each timer
is one microsecond which is sufficient for this application.

Figure 17. PSDsoft Configuration 01 the Timers

Conclusion

Counter / Timer 0:

Waveform/Pulse Mode.

Counter / Timer 1:

Pulse Output.

Counter / Timer 2:

Waveform/PulseMode.

Counter / Timer 3:

Pulse Output

Do you need Automatic Power Down Clock Input?

NO

Do you want to set the security bit?

NO

Do you need the Intr output signal?

YES

In this application the PSD503 provided a very useful integrated means of design. The
following were benefited from this design:
•
•
•
•
•
•

64 K x 16 EPROM
Eighteen bits of latched output for demultiplexing ADDRESS from DATA.
An 8-bit Interrupt Controller Equivalent to an 8259.
Four 16-bit preloadable timers with a prescaler for the timer clocks.
Logic for decoding.
Programmable external PORTS.

The board space reduction and the amount of noise reduction that resulted from this design
is immeasurable.

--------------------_______________
~_Ar_~~----------------------------------3-318
;:;:

I'SDSXX - AppllClltlDR NDte D42

Deslgnfot
PSDS03ABEL
SOUIC. FII. to
Int.rface with

8OC186

_._._--_._._-------_._._-------------------------------**_.._--_._._.-._--.......-----_...._----------W S I - PSDsoft Version 1.05B

Output of PSD Fitter

**._._--------------_._._-------------_._---------._.---------.-._------_
..._._-----_._._-------------DESIGN FOR PSD503 ABEL source file to interface with 80C186
TITLE
PROJECT
mfhs_16
DEVICE
PSD503B1
FIT OPTION : Keep Current

DATE: 04107/1995
TIME: 09:31 :05

._._------------------------------------------------------_..-._----------.-._----.-._----------------Pin Assignment

---------------------Address/Data Bus ADIO_7
Address/Data Bus ADIO_S
Address/Data Bus ADIO_5
Address/Data Bus ADIO_4
Address/Data Bus ADIO_3
Address/Data Bus ADIO_2
Address/Data Bus ADIO_l (al)
Address/Data Bus ADIO_O (aO)
pe7
peS
pe5
pe4
peS
pe2
pel
peO

umes
alS
a17
omes
timerout3
timerout2
timeroutl
timeroutO
wr
pcs3
add_17
Imes
emes
add_16

l]GND
2]adio7
3] adioS
4] adio5
5]adio4
S] adio3
7] adio2
8] adiol
9] adioO
10]pe7
11] peS
12] pe5
13] pe4
14] pe3
15]pe2
lS] pel
17] peO
18]VCC
19] GND
20]pa7
21] paS
22] pa5
23]pa4
24]pa3
25]pa2
2S] pal
27]paO
2B]VSTBY
29]wr
3O]pe7
31] peS
32] pe5
33]pe4
34]pe3

GND [35
pe2 [3S
pel [37
peO[38
esi [39
reset [40
rd [41
elkin [42
pb7 [43
pbS [44
pb5[45
pb4[46
pb3[47
pb2[48
pbl [49
pbO[50
GND [51
VCC[52
pd7[53
pdS [54
pd5 [55
pd4[56
pd3[57
pd2 [58
pdl [59
pdO[SO
adio15 [Sl
adio14 [62
adio13 [63
adio12 [S4
adiol1 [S5
adiol0 [66
adio9[S7
adioB[6B

----------------------

introut
ale
bhe
esi
reset
rd
elkin
pcs2
(Not Used)
pb5
pb4
pb3
pb2
pbl
pbO

pd7
pdS
pd5
pd4
pd3
pd2
pdl
pdQ
Address/Data Bus ADIO_15 (a15)
Address/Data Bus ADIO_14 (a14)
Address/Data Bus ADIO_13 (a13)
Address/Data Bus ADIO_12 (a12)
Address/Data Bus ADIO_l1 (all)
Address/Data Bus ADIO_l 0 (a 10)
Address/Data Bus ADIO_9 (a9)
Address/Data Bus ADIO_B (as)

Global Configuration
Data Bus:
ALE/AS Signal:
WatchDog Mode:
Security Protection:

16 Multiplexed
Active High

Off
Off

Address It Data Bus Assignment
Stimulus Bus Name
Signal Description
'adiol
'adioh
adio

= adio[7:0]
= adio[15:8]
= adio[15:0]

AddresslData Bus ADI03 - ADIO_O
Address/Data Bus ADIO_15 - ADIO_8
AddresslData Bus ADIO_15 - ADIO_O

-------------------------------~~~------------------------------3-319

PSD5XX - Application Note 042

Design for
PSD503ABEL
Source File to
Interface with
80C186
(Cont.)

Resource Usage Summary
Device Resources

Port A: (pin 20 - pin 27)
1/0 pins
MCU 1/0 or Address Out
Peripheral 1/0
ZPLD Inputs
ZPLD Combinatorial Outputs
ZPLD Registered Outputs
Other Information
Buried Macrocells
Product Terms
Timer Outputs

Percentage

8/8
01 8
01 8
31 8
1I 8
01 8

100%
0%
0%
37%
12%
0%

01 7
1127
4/4

0%
3%
100%

Port B: (pin 43 - pin 50)
1/0 pins
MCU 1/0 or Address Out
ZPLD Inputs
ZPLD Combinatorial Outputs
ZPLD Registered Outputs
Other Information
Buried Macrocells
Product Terms
Timer Outputs

7I 8
7I 8
0/8
01 8
01 8

87%
87%
0%
0%
0%

01 8
0/80
0/4

0%
0%
0%

Port C: (pin 10 - pin 17)
1/0 Pins
MCU 1/0 or Address Out
ZPLD Input Pins
Data Port (Non-Mux Bus)

8I
8I
01
01

8
8
8
8

100%
100%
0%
0%

Port D: (pin 53 - pin 60)
1/0 Pins
MCU 1/0 or Address Out
ZPLD Input Pins
Data Port (16-Bit Non-Mux Bus)

81 8
8I 8
01 8
0/8

100%
100%
0%
0%

Port E: (pin 30 - pin 34, pin 36 - pin 38)
1/0 pins
MCU 1/0 or Address Out
ZPLD Inputs
ZPLD Combinatorial Outputs
ZPLD Registered Outputs
Control Signal Inputs
Timer Control Inputs
Interrupt Control Output
APD Clock Input
Terminal Counts (TC)
Other Information
Buried Macrocells
Product Terms

81 8
1I 8
1I 8
31 8
0/8
21 2
01 4
1I 1
01 1
01 4

100%
12%
12%
37%
0%
100%
0%
100%
0%
0%

0/5
3 I 11

0%
27%

CounterlTimer: Embedded Nodes
Product Terms

41 8

50%

Interrupt: Embedded Nodes
Product Terms

01 4

0%

f§a#1!#

3-320

UsedlTotal

~E;

PSDSXX - Application Nots 042

Design for
PSD503ABEL
Source File to
Interface with
80C186
(Cont.)

OMC Resource Assignment
User Name

Resources Used
Port A:
macro cell 4

omcs

(mc_pa4) => Combinatorial

add_16
emcs
add_17

(mc_pe3) => Combinatorial
(mc_pe4) => Combinatorial
(mc_pe6) => Combinatorial

Port B:
Port E:
macro cell 3
macro cell 4
macro cell 6

EQUATIONS
DPLD EQUATIONS:

esO
es1
es2
es3
rsO
csiop =

!a15 & !a16 & !umcs;
a15 & la16 & !umcs;
!a15 & a16 & lumcs;
a15 & a16 & !umcs;
0;
!a15&!a14&!a13&la12&la11 &la10&la9&a8&la16;

TIMER

EQUATIONS:

mc2tmrO

= ItimeroutO;

mc2tmr1 = Itimerout1;
mc2tmr2 = Itimerout2;
mc2tmr3

= Itimerout3;

INTERRUPT EQUATIONS:
PORT A EQUATIONS:

omcs = Ibhe & IImcs;
[omcs].OE

= 1;

PORT B EQUATIONS:

PORT E EQUATIONS:

add_16 = a16;
emcs
add_17

= laO & IImcs;
= a17;

[add_16, emes, add_17].OE = 1;

--------__________________________

,ArJf~~

. . ." .

_________________________________
3·321

'SD5XX - App/lt:lltlon Note 04Z

~3~~2~~-------------------------~Jrjr---------------------------

PSD3XX Family

ZPSD3XX Family

PSD4XX/5XX Family

Motorola Application Notes

Sales Representatives
and Distributors

Section Index
Motorola
Application
Notes

The following are Motorola Application Notes and known as Application Notes 043 and 044
at WSI, Inc.
Application Note 043

Using M68HC11 Microcontroliers
with WSI Programmable Peripheral Devices ................................4-1

Application Note 044

High Performance M68HC11 System Design
Using The WSI PSD4XX and PSD5XX Families ..........................4-9

FDr additiDnal infDrmatiDn,
Call800-TEAM-WSI (800-832-6974).
In CalifDrnia, Call 800-562-6363

Order this document by
AN1237/D

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - -

APPLICATION NOTE

Using M68HC11 Microcontrollers with
WSI Programmable Peripheral Devices
by Steve Torp - Motorola Semiconductor
Karen Spesard - WSI

INTRODUCTION
Following system development using M68HC711 microcontroller (MCU) devices with EPROM or one time
programmable ROM (OTPROM), a final design is often implemented using an equivalent mask-programmed M68HC11 device. However, there is a quick, cost-effective alternative to this method of going to
production.
WSI manufactures a complete line of PSD programmable MCU peripherals that make it possible to use a
ROM-less M68HC11 derivative instead of a mask-programmed device. PSD devices combine EPROM,
SRAM, programmable logic for memory map decoding, programmable I/O ports, an address latch, power
management, and other capabilities on a single chip. A "twin chip" solution can increase flexibility, provide
expanded memory and enhanced I/O, lower power consumption, and lower cost - all with a minimum of
software and hardware modifications.
This application note describes the process of converting from a prototype design that uses an M68HC711
device to a production design that uses a low-cost M68HC11 derivative and a WSI PSD.

CONVERSION PROCEDURES
There are eight steps in the conversion process. Each is discussed in detail in the following text.
1. Choose the M68HC11 and PSD
2. Add the PSD to the design

3. Configure the M68HC11 for expanded mode operation
4. Configure the PSD
5. Make memory map and I/O port selections
6. Modify M68HC11 code to address memory and I/O
7. Integrate M68HC11 code with PSD configuration data
8. Program the PSD
CHOOSE THE M68HC11 AND PSD
The M68HC11 family offers a wide range of operating voltage and frequency selections. Table 1 shows
M68HC11 Family devices, including M68L 11 low-power devices, that can be used in two-chip systems.
EPROM/OTPROM devices are shown in bold. WSI PSDs are available in a variety of configurations. PSDs
provide a larger memory size, I/O port expansion, and programmable logic to an M68HC11 system. Lowpower PSDs are a perfect complement to M68L 11 MCUs.

---------@
© MOTOROLA INC., and WSI1995

MOTOROI.A_
4-1

Table 1 Motorola M68HC11 Devices

4·2

MOTOROLA

Motorola Part Number

ROM

RAM

EEPROM

1/0

MC68HC11AO
MC68L11AO
MC68HC11A1
MC68L11A1
MC68HC11A7
MC68L11A7
MC68HC11A8
MC68L11A8

0

256

0

22

0

256

512

22

8K

256

0

38

8K

256

512

38

MC68HC11CO
MC68HC711 D3

0
4K

256
192

0
0

35
32

MC68HC11D0
MC68HC11D3
MC68HC711 E9

0
4K
12K

192
192
512

0
0
512

14
32
38

MC68HC11EO
MC68L11EO
MC68HC11E1
MC68L11E1
MC68HC11E8
MC68L11E8
MC68HC11E9
MC68L11E9
MC68HC711 E20

0

512

0

22

0

512

512

22

12K

512

0

38

12K

512

512

38

20K

768

512

38

Yes

MC68HC11 E20

20K

768

512

38

Yes

MC68HC811 E2

0

256

2K

38

Yes

MC68HC11F1
MC68L11F1

0

1K

512

30

MC68HC711 K4

24K

768

640

62

MC68HC11KO
MC68L11KO
MC68HC11K1
MC68L11K1
MC68HC11K3
MC68L11K3
MC68HC11K4
MC68L11K4
MC68HC711 L6

0

768

0

37

0

768

640

37

24K

768

0

62

24K

768

640

62

16K

512

512

46

0

512

0

30

0

512

512

30

16K

512

0

46

AID

Yes

Yes
No
No
Yes

Yes

Yes
Yes

Yes

Yes

MC68HC11LO
MC68L11LO
MC68HC11L1
MC68L11L1
MC68HC11L5
MC68L11L5
MC68HC11L6
MC68L11L6
MC68HC711 P2

16K

512

512

46

32K

1K

640

62

Yes

MC68HC11P2

32K

1K

640

62

Yes

Yes

AN1237/D

Table 2 shows PSD devices that are recommended for use with M68HC11 and M68l11 family members.

Table 2 Recommended Devices
Device

EPROM

RAM

I/O

PSD311Cl

32K

-

19

PSD311

32K

2048

19

PSD411Al

32K

2048

40

Table 3 shows typical twin-chip alternatives to particular M68HC711 or M68l711 systems.

Table 3 Alternative System Configurations
Device

ROM

RAM

EEPROM

UO

AID

Single Chip

MC68HC71103

4K

192

0

32

Twin Chip

MC68HC11D0 + PSD311Cl

32K

192

0

33

No
No

Single Chip

MC68HC711 E9/20

12K120K

512/768

512

38

Ves

Twin Chip

MC68HCllAO/l + PSD311Cl

32K

256

0/512

41

Ves

Twin Chip

MC68HCllAO/l + PSD311

32K

2304

0/512

41

Yes

Twin Chip

MC68HC11D0 + PSD311 Cl

32K

192

0

33

No

Twin Chip

MC68HCllEO/l + PSD311Cl

32K

512

0/512

41

Ves

Twin Chip

, MC68HCll EDO + PSD311 Cl

32K

512

0

33

No

62

Ves

Single Chip

MC68HC11K4

24K

768

640

Twin Chip

MC68HCllKO/l +PSD411Al

32K

2816

0/640

n

Ves

Twin Chip

MC68HCllKO/l + PSD311

32K

816

0/640

56

Ves

Single Chip

MC68HC11L6

16K

512

512

46

Ves

Twin Chip

MC68HCllL1 +PSD311Cl

32K

512

0/512

49

Ves

ADD THE PSD TO THE DESIGN
Migration from an M68HC711 single-chip system to an M68HC11/PSD system can be accomplished in one
of three ways.
1. By building a daughter board that plugs into the MCU socket on an existing printed circuit board. The
board includes the M68HC11, the PSD, and system clock generation circuitry. Including the clock
generator on the daughter board is important to minimize radiated EMI.
2. By placing an edge or row connector on an existing printed circuit board to allow access to a PSD
device on a daughter board. The minimum signals needed include the address/data lines and control
signals (R/W, E, AS, RESET). This requires changing the existing schematic.
3. By redesigning the existing printed circuit board to accommodate the PSD device.
Figure 1 and Figure 2 are examples of interfacing an M68HC11 to particular PSD devices. Please refer to
the appropriate Motorola data book and to the WSI PSD Design and Applications Handbookfor more information.

AN12371D

MOTOROLA

4-3

PSD3XX

M68HC11
XTAL
EXTAL

PC[7:0]

AD[7:0YA[7:0]
AD[15:8YA[15:8]

PB[7:0]
IRQ

VCC

PA[7:0]
PE[7:0]
PD[7:0]

E
RIW
AS

RESET

VRH
VRL

PA[7:0]
PB[7:0]

XiRei
MODA
MODB

PC[2:0]

E
RIW
AS
RESET
A19/CSi

NOTES.
I. HCII reset line must be pulled up to VOO.

HCll PSD3 SCHEM

Figure 1 Typical M6SHCll and PSD3XX System

PSD4XX15XX

M68HC11
XTAL
EXTAL

PC[7:0]
PB[7:0]

AD[7:0YA[7:0]
AD[15:8YA[15:8]

PC[2:0]
PD[7:0]

iRO
XiRei

E

RIW

MODA
MODB

AS

PA[7:0]
PE[7:0]
PD[7:0]

RESET

VRH
VRL

E

RIW

PA[7:0]

PEl/ALE

PB[7:0]

RESET
PE[7:2]
eLKIN
VSTBY
CSI

CLOCK
NOTES'
I. HCII reset line must be pulled up to voo

Hell PSD415 SCHEM

Figure 2 Typical M6SHCll and PSD4XXl5XX System

4-4

MOTOROLA

AN1237/0

CONFIGURE THE M68HC11 FOR EXPANDED MODE OPERATION
M68HC11 operating mode is determined by the logic state of the MODA and MODB pins during system reset or power up. To configure the MCU for expanded mode operation, make the reset state of the MODA
pin HIGH by pulling it up to VDD through a pullup resistor.

CONFIGURE THE PSD
PSD software must be used to configure the PSD. There are two different software packages available.
PSD-SILVER software supports the PSD3XX devices and includes the MAPLE and MAP PRO software
modules which run under the DOS platform. MAPLE software is used to configure the PSD chip. It features
simple menu driven commands for selecting different device configurations. It also provides mapping of the
EPROM, SRAM, and chip select outputs into the user's address space, and locates the files to be programmed into the EPROM segments. MAPPRO enables the user to program PSDs on a WSI MagicPro III®
programmer.
PSDsoft WS7001 or WS7002 software supports the PSD3XX, PSD4XX, and PSD5XX families and runs
under MicroSoft® Windows® (PSD3XX support included in PSDsoft available Q295). It includes PSDabel,
PSD configuration, PSD compiler, PSDsilos III simulator, and PSD programming software. The PSDsoft environment allows design and simulation of the on-chip PLD logic under Data I/O ABEL®, PSD interface selections to any MCU, configuration of the I/O, and address mapping of the EPROM and SRAM memory,
among other things.
PSD-to-M68HC11 interface configuration is simple and straightforward. Configuration is performed by selecting certain option bits in the PSD software package. For MC68HC11 A, C, D, E, and L devices, the PSD
is configured for multiplexed mode. For MC68HC11 F, K, and P devices, the PSD is configured for non-multiplexed mode. For all versions of the M68HC11, the other option bits on the PSD device are set as follows:
RiW and E mode, active high AS (ALE), active low RESET, and combined memory mode. To complete the
configuration process, PSD Ports A and B must be configured as general-purpose I/O, to replace M68HC11
Ports Band C, which are used for address and data lines when the MCU is operating in expanded mode.
For a better understanding of the M68HC11 to PSD interface configuration information, please refer to the
pin descriptions section of the appropriate Motorola data book and to Table 5 and Figure 12 in WSI Applications Note 011 for PSD3XX devices, and the section beginning with Figure 12 in Applications Note 029
for PSD4XXl5XX devices.

MAKE MEMORY MAP AND 110 PORT SELECTIONS
To convert from an M68HC711 system to a system that uses a ROM-less M68HC11 and a PSD, the content
of the M68HC711 ROM must be transferred to PSD EPROM, and mapped externally. The default state of
the ROMON bit in the CONFIG register of ROM-less M68HC11 devices is zero, so all accesses to the ROM
address space automatically go external. Virtually no change in the MCU address map is required because
PSD EPROM can be mapped anywhere on a block boundary using the address map menu in the PSD software.
For example, assume a PSD device with 32 Kbytes of EPROM is selected. The PSD311 has eight blocks
of 4 Kbyte x 8 EPROM. Each block can be mapped on a 4-Kby1e block boundary in the address range as
originally defined in the OTP application. The PSD411A 1 has four blocks of 8 Kby1e x 8 EPROM, and each
can be mapped to an 8-Kbyte block boundary. Please refer to the modes and memory section of the appropriate Motorola data book, to Figure 32 in WSI Applications Note 011 for the PSD3XX, and to Table 7 in
WSI Applications Note 029 for the PSD4XX/PSD5XX devices.
For PSDs that include an additional 2 Kbyte x 8 SRAM, the SRAM can be mapped anywhere within the address space on a 2-Kbyte boundary to extend the SRAM already supplied on the M68HC11.
PSDs also offer from 19 to 40 configurable I/O pins that can replace I/O pins that are used for other purposes
when the M68HC11 operates in expanded mode or enhance the function of the available ports. The programmable I/O is addressed via an offset from a base address that is selected in the PSD software. These

AN1237/D

MOTOROLA

4-5

offsets are shown in Table 6 in the PSD3XX data sheets, Tables 21-23 in the PSD4XX data sheet, and in
Tables 29-31 in the PSD5XX data sheet.
For example, the following steps must be performed to replace ports Band C on an M68HC711 with ports
A and B on a PSD311 device.
1. Refer to the appropriate PSD data sheet to determine the correct offsets.
2. Set the CSIOPORT (CSP) base address of the PSD. The base address can be mapped to any
boundary from 256 bytes to 2 Kbytes. In this example, the CSIOPORT base address starts at $2000.
3. Port B on the M68HC11 is mapped to port A on the PSD311. For compatibility with port B on the
M68HC11, which is an output-only port, port A on the PSD311 is set for output. This is accomplished
by writing $FF (output) to the PSD311 port A data direction register, located at $2004 (offset four
from base address).
4. Port C on the M68HC11 is mapped to port B on the PSD311. The direction of the individual 110 pins
in PSD311 port B is determined by the definition in the original OTP application. The direction is set
by writing to $2005 (offset five from base address). To make a pin an input, the appropriate bit in the
register must be cleared; to make a pin an output, the appropriate bit must be set.
5. To write data to PSD311 port A and port B pins, the data must be written to $2006 for port A and to
$2007 for port B. Data from the PSD311 port A and port B pins must be read from $2002 and $2003,
respectively.
Other M68HC11 resources, such as EEPROM, SRAM, vectors, and the control registers are mapped internally and do not require any memory map redirection.
MODIFY M68HC11 CODE TO ADDRESS PSD MEMORY AND I/O
Change M68HC11 1/0 port addresses to match the port address at the appropriate offset from the specified
PSD 1/0 port base address (CSIOPORT).
INTEGRATE M68HC711 CODE WITH PSD CONFIGURATION DATA
Code that would normally be programmed into M68HC711 EPROM must be merged with PSD configuration
information to create one output file. This is done during the compile procedure in the PSD software. The
single output file is then downloaded to an industry-standard programmer (or the WSI MagicPro III PC-compatible programmer) and used to program the PSD device.
PROGRAM THE PSD
The output file (filename. obi) generated from the PSD software compiler is now ready to be programmed
into a device from one of the three PSD families (PSD3XX, PSD4XX, or PSD5XX). A list of programmer
manufacturers that support the PSD devices can be obtained from a WSI sales office or sales representatives. Programmers which support the PSD devices are available from Data 1/0, BP Microsystems, and Logical Devices.

CONCLUSION
A single-chip Motorola M68HC711 control system can be quickly and easily converted to a system that uses
a ROM-less M68HC11 and a WSI Programmable MCU peripheral. A small investment in hardware and software modification can provide an increase in system memory, expanded 1/0, lower power consumption,
greater design flexibility, and lower cost.

NOTE: This Motorola document is also known as Application Note 043 at WSI, Inc.

4-6

MOTOROLA

AN1237/D

NOTES

AN1237/D

MOTOROLA

4-7

Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty, representation or guarantee regarding the sUitability
of Its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or CirCUit, and specifically disclaims any and
ali liability, Including without limitation consequential or incidental damages, "TYPical" parameters can and do vary in different applications All operating parameters, Including
"TYPlcals" must be validated for each customer application by customer's techmcal experts Motorola does not convey any license under Its patent rights nor the rights of others
Motorola products are not deSigned, Intended, or authorized for use as components In systems Intended for surgical Implant Into the body, or other applications Intended to
support or sustain hfe, or for any other application In which the failure of the Motorola product could create a SItuation where personal inJury or death may occur Should Buyer
purchase or use Motorola products for any such unintended or unauthOrized apphcatlon, Buyer shall Indemmfy and hold Motorola and Its officers, employees, subsldlanes,
affiliates, and distributors harmless agamst all claims, costs, damages, and expenses, and reasonable attorney fees anslng out of, d!rectly or indirectly, any cla!m of personal
injury or death assocIated with such unintended or unauthOrized use, even If such claim alleges that Motorola was negligent regarding the deSign or manufacture of the part
MOTOROLA and
are registered trademarks of Motorola, Inc Motorola, Inc, IS an Equal Opportunity/Affirmative Action Employer

@

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JAPAN: Nippon Motorola Ltd: 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors HK Ltd.; Silicon Harbour Center, No.2 Dai King Street, Tal Po Industrial Estate,
Tal Po, NT, Hong Kong.

4-8

Order this document
by AN12421D

MOTOROLA

-

SEMICONDUCTOR - - - - - - - - - - -

APPLICATION NOTE

High Performance M68HC11 System Design
Using The WSI PSD4XX and PSD5XX Families
by John Bodnar

INTRODUCTION
This application note covers conversion from a single-chip MC68HC711 K4 microcontroller (MCU) system
to a two chip MC68HC11 K1 + PSD412A 1 combination. It is not intended to be a comprehensive guide to
using Motorola M68HC11 microcontrollers with WSI PSD4XX or PSD5XX microcontroller peripherals.
These flexible devices provide a wide array of features, many of which cannot be adequately discussed
within the context of this note. Designers with a more general interest in this topic should examine published
material available from both Motorola and WSI. These documents are listed under REFERENCES.

GENERAL INFORMATION
M68HC11 K-series MCUs are highly integrated derivatives of the MC68HC11 F1, the first member of the
M68HC11 family with a non-multiplexed address and data bus. Features common to the K series include:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

M68HC11 CPU core capable of dc to 4 MHz operation
Power-saving STOP and WAIT modes
768 bytes of SRAM, with separate standby power input for battery backup
Four programmable chip selects with clock stretching for expanded mode intertacing
On-chip memory paging logic to allow expansion of the address space to 1 Mbyte
16-bit timer with programmable prescaler that includes 3 input capture (IC) channels, 4 output compare (~C) channels, and a single switchable IC or DC channel
8-bit pulse accumulator (PAC)
Four 8-bit pulse width modulation (PWM) timer channels, pairs of which can be concatenated into two
16-bit channels
Real-time interrupt circuit (RTI)
Computer operating properly (COP) watchdog and clock monitor circuits
Eight channel 8-bit analog-to-digital converter (ADC)
Enhanced asynchronous non-return to zero serial communications intertace (SCI)
Enhanced synchronous serial peripheral intertace (SPI)
Maximum of 54 bits of bi-directional liD available in single-chip mode of operation
8-bit fixed input-only port

The MC68HC11 K4 device provides 24 Kbytes of masked ROM, 768 bytes of SRAM, and 640 bytes of
EEPROM. Cost-reduced versions of this device are available without EEPROM andlor masked ROM. The
MC68HC711 K4 is functionally equivalent to the MC68HC11 K4 but has 24 Kbytes of one-time programmable or UV-erasable EPROM instead of masked ROM. This programmable memory is typically used for prototyping, just-in-time inventory management, and applications requiring small production quantities or
frequent code updates.

---------@
© MOTOROLA INC., and WSI1995

MOTOROI.A_
4·9

The MC68HC711 K4 provides a great deal of flexibility for single-chip applications, but in some instances, it
may be necessary to find an alternate solution that provides equivalent functionality. These situations may
arise because:
• Pins used by the on-chip peripherals are also used to implement digital I/O ports, so use of peripherals
can limit the available discrete digital I/O.
• Addition of new features may increase object code size beyond the 24 Kbytes provided by the internal
EPROM. None of the M68HC11 K-series devices provide more than 24 Kbytes of ROM or EPROM,
and expanded operating mode uses 25 digital 110 pins for the address/data bus and read/write line.
• Reduced software maintenance costs due to source code development in a high-level language can
initially be offset by greater object code size, causing a memory crunch and loss of I/O resources.
• Some applications require peripherals that are either not available on an M68HC11 derivative or not
available with an SCI- or SPI-compatible interface. These devices usually have an address/data bus,
and must be mel1)ory mapped, causing a loss of I/O resources.
Some of these problems may seem insurmountable without extensive hardware and/or software redesign,
but there is a solution that offers both the flexibility of expanded operating mode and the I/O preservation of
single-chip operating mode.
WSI PSD4XX and PSD5XX programmable system devices (PSDs) are peripherals with flexible bus interfaces that provide microcontroller system designers an integrated memory solution consisting of SRAM,
EPROM, and programmable logic. PSDs can also provide up to 40 digital 110 lines to replace those occupied by the MCU address/data bus. PSD4XX and PSD5XX devices share the following features:
• Bus access speeds of 90,120,150, and 200 nanoseconds
·37 (PSD4XXA 1), 59 (PSD4XXA2), or 61 (PSD5XX) PLD inputs
·113 (PSD4XXA1), 126 (PSD4XXA2), or 140 (PSD5XX) PLD product terms
·8 (PSD4XXA1), 24 (PSD4XXA2), or 30 (PSD5XX) registered macrocells
·40 bi-directional digital I/O pins
• Power management unit (PMU)
·32 K x 8 (PSDX11), 64 K x 8 (PSDX12), or 128 K x 8 (PSDX13) of EPROM
• 2 K x 8 of SRAM
The PSD5XX family builds upon the PSD4XX family by adding a peripheral module that contains four 16bit counters/timers, a watchdog timer, and an eight level interrupt controller. On all PSDs, some of the programmable logic is used to map the different memory blocks and control registers for the I/O ports, the PMU,
and (on PSD5XX devices) peripheral control registers. Usually, sufficient programmable logic remains after
memory decoding to implement chip-select signals for external memory mapped peripherals, other bus control signals, and even state machines to perform useful peripheral functions.
The discussion which follows covers the process of converting a hypothetical single-chip M68HC11 application to an equivalent or enhanced "two-chip solution" consisting of a non-multiplexed bus M68HC11 and
a PSD4XX or PSD5XX device. Please refer to the DEVICE REFERENCE TABLES, at the end of this note,
lor a list of compatible devices. Table 4 shows suitable non-multiplexed bus M68HC11 devices. Table 5
shows PSD4XX and PSD5XX devices.

4-10

MOTOROLA

AN1242/D

THE PROBLEM
Figure 1 shows a single-chip MC68HC711 K4 application that makes extensive use of MCU on-chip peripheral and memory resources. An ASCII terminal interface that facilitates user interaction is an important featlJre of this design. However, the customer has requested that the next generation product be substantially
smaller. This can best be achieved by eliminating the ASCII terminal.

VDD

L{V55
VDD

~~ ~
~
ANALOG INPUTS {

•

!:1

~

..... PB7/ADDR15

~ PB6/ADDR14
~ PB5/ADDR13

iE

PB4/ADDR12
PB3fADDR11
PB2/ADDR10
PB1/ADDR9
PBOIADDRa
VDD
V55

MC68HC711 K4

..

-

PULSE-ACTUATED OUTPUTS
~
EDGE-TRIGGERED INPUTS

{

VDD

V55

PF7IADDR7
PF6IADDR6
PF5JADDRS
PF4IADDR4
PF3IADDR3
PF2IADDR2

PF1fADDRl

.{

PFO/ADDRQ

VDD

PA2ACl

-=CV5S

AN1242 SCHEM 1

Figure 1 Existing Single-Chip MC68HC711 K4 Application
The redesign promising the greatest size reduction integrates a large LCD panel and keyboard with an
M68HC11-based control unit. These changes meet customer requirements for a more compact, tightly integrated control solution, but as Figure 2 indicates, the keyboard and LCD interfaces could exhaust the digital I/O resources of the MC68HC711 K4.

AN12421D

MOTOROLA

4-11

VDD

LIV55
VDD

PB7/ADDR15
PBs/ADDR14
PB5/ADDR13
PB4/ADDR12
PB3/ADDR11

~~~D ~~~
ANALOG INPUTS {
~

VS5

t--------.---I

... - --

PULSE-ACTUATED OUTPUTS

EDGE-TRIGGERED INPUTS

PE7/AN7
PEe/AN6
PE5!AN5
PE4/AN4
PE3IAN3
PE2IAN2
PE1/AN1
PEOIANO
VRL
AV55

~~

§
a...

PB2/ADOR10

PB1/ADOR9
PBO/ADORa
VDD
v55
PF7IADDR7
PF61ADDR6
PF5/ADDR5
PF4JADDR4
PF3/ADDR3
PF2/ADDR2

MC68HC711 K4

{

PF1/ADDRl
PFO/ADDRO

~

{

V55

}

VDD

MODBN5TBY
~ ~ ~ .:!: ~ MOOAIiJR

;:i«;:i<
v~~~g

~~a:a:a:

6 ROW X 16 COLUMN
KEYBOARD

COLUMNS

AN1242 SCHEM:2

Figure 2 Next Generation MC68HC711 K4 Application With Keyboard and LCD
To complicate matters further, these changes make greater demands of the MCU firmware. As shown in
Figure 3, application control code and constant tables fit neatly into the 24 Kbytes of EPROM on the
MC68HC711 K4. The ASCII terminal connection to the SCI reduces the user interface to simple character
110 functions, but addition of a parallel input keyboard and a large LCD panel requires supplemental firmware support that increases permanent storage requirements to more than 24 Kbytes.

4-12

MOTOROLA

AN1242/D

$0000
REGISTERS

$007F
--- --$0080

-

-"

768 BYTES SRAM

$037F
SRAM, REGISTERS, EEPROM

$0380
EXTERNAL ADDRESSES

$007F
$0080
640 BYTES EEPROM

EXTERNAL ADDRESSES

$OFFF

$AOOO

$AOOO ASCII TERMINAL DATA

24 KBYTES EPROM

______$~~~F
$COOO

PAGES AND CONSTANTS

CONTROL ALGORITHMS

$FFBF
$FFCO
$FFFF

$FFBF
VECTORS

AN1242 SCM MEM MAP

Figure 3 Initial Single-Chip Mode Memory Map
Sophisticated control algorithms are required to support the increased functionality of the keyboard and
LCD panel. To speed code development, reduce the cost of support, and provide for future enhancements,
the firmware for the next generation product will be ported from M68HC11 assembly language to C_ While
high-level languages simplify the development of complex control applications, they do so at the expense
of greater storage requirements_ The reduction in object code size achieved by hand-tuning assembly language programs begins to disappear as application functionality and complexity increase_
One possible method of providing for increased storage demands would be to use the flexible memory expansion capabilities of an M68HC11 K-series device_ This would lead to the simple expanded memory map
shown in Figure 4_ Estimates indicate that the control algorithms will require 32 Kbytes of EPROM and that
the LCD data tables will require an additional 32 Kbytes_ A 16-Kbyte memory paging window can be used
to access the LCD data and stili provide 12 Kbytes of contiguous address space for any other memory
mapped peripherals that may be needed_

AN12421D

MOTOROLA

-----------

-

.-----

4-18

$0000
REGISTERS

$007F
. - ---$0080

---

768 BYTES SRAM

$037F
SRAM, REGISTERS, EEPROM

$0380

i

EXTERNAL ADDRESSES

$OD7F
. -- ---$OD80

-.

EXTERNAL ADDRESSES

640 BYTES EEPROM

1

$OFFF

$4000
LCD AND CONSTANT
DATA PAGE 0

OR

16K X 2 EPROM PAGES

LCD AND CONSTANT
DATA PAGE 1

$7FFF
$8000

$7FFF
$8000
CONTROL ALGORITHMS

32 KBYTES EPROM
$FFBF
$FFCO
$FFFF

$FFBF
VECTORS
AN1242 EXP MEM MAP

Figure 4 Proposed Memory Map Expansion
Unfortunately, access to the MC68HC711 K4 address and data buses results in the complete loss of 1/0
ports B, C, and F, as well as bit 7 of port G. In addition, other port G bits would be used as expansion address lines and some port H bits may be used as chip selects. These lost 1/0 pins can be rebuilt with simple
latches or more complex peripherals at the risk of decreased flexibility and more complicated circuit design
and debugging.

4-14

MOTOROLA

AN1242/0

THE SOLUTION
Before proceeding with a design solution based on a WSI PSD4XX or PSD5XX device, it is instructive to
review the problem as it now stands.
• The existing MC68HC711 K4-based system makes extensive use of the integrated MCU peripheral
resources. In particular, the SCI connects to an ASCII terminal that simplifies interactive user control.
• Size reductions specified for the next generation of this product are best achieved by replacing the
ASCII terminal with a keyboard and LCD panel that are integrated with the control unit.
• The digital I/O requirements for the keyboard and LCD interfaces could exhaust the MC68HC711 K4
I/O resources.
• Application storage demands increase for two reasons. The keyboard and LCD panel require additional interface code, and the firmware is to be ported from assembly language to C.
• To support the proposed expansion of storage capacity from 24 Kbytes to 64 Kbytes, the MCU must
use expanded operating mode rather than single-chip operating mode.
• Expanded mode operation requires at least 25 pins for the non-multiplexed address/data bus and the
read/write line. These pins are currently used for digital I/O. Other digital I/O pins must be used to support chip selects and memory expansion beyond 64 Kbytes.
It appears that the proposed system would require a 32 Kbyte EPROM for control routines, another 32 Kbyte
EPROM for LCD data tables, several latches to rebuild lost I/O ports, and some programmable logic to map
all of these devices into the MC68HC711 K4 address space. This design clearly jeopardizes cost savings
achieved by the existing implementation and future high-level language software development.
Some of the savings can be restored by switching MCUs. The 24 Kbyte EPROM on the MC68HC711 K4 is
not needed for the new design, so either the ROM-less MC68HC11 K1 or the ROM-and-EEPROM-Iess
MC68HC11 KO could be used. These devices retain the specialized peripherals available on the
MC68HC(7)11 K4, and are ideal for expanded mode applications where the I/O pins used by the bus interface are not required or are otherwise rebuilt.
Both cost reduction and increased flexibility can be achieved by using a WSI PSD4XX or PSD5XX programmable system device in place of the memory and logic components that would otherwise be needed to realize this design.
As shown in Table 4 and Table 5, a PSD412A 1 can easily provide the required additional memory, I/O, and
logic resources. If subsequent specifications dictate increased memory, logic, or even peripheral functionality, other members of the PSD4XX and PSD5XX families could be used, while maintaining close compatibility with the PSD412A 1.

Table 1 compares the memory, I/O, and logic resources of both the initial MC68HC711 K4 system and the
proposed MC68HC11 K(O/1) + PSD412A 1 system.

Table 1 M68HC11 Single-Chip vs M68HC11 + PSD4XX Resource Comparison
MC68HC711 K4

MC68HC11K(11O) + PSD412A1

24 Kbytes

SRAM

768 bytes

768 + 2048 =2816 bytes

16 Kbytes + 16 Kbytes + 32 Kbytes

EEPROM

640 bytes

640 byteslO bytes

Available bi-directional 1/0

54 lines

61 lines

PLD input terms

None

61

PLD product terms

None

113

Registered macro cells

None

8

AN12421D

=64 Kbytes

EPROM

MOTOROLA

4-15

In essence, the combination of a non-multiplexed bus M68HC11 MCU and a PSD4XX or PSD5XX device
restores much of the functionality of a single-chip system. While not providing the ultimate size and power
consumption features of such a design, the increased flexibility of this pairing and the freedom it provides
to system designers is a competitive advantage.

THECONVER~ONPROCESS
Converting a single-chip M68HC11 application to a two chip system consisting of a non-multiplexed bus
M68HC11 and a PSD4XX or PSD5XX is a five step process:
1. Assess the memory, I/O, and logic requirements of the combined system
2. Select the appropriate M68HC11 and PSD combination.
3. Produce the two chip system memory map.
4. Determine which PSD I/O ports replace M68HC11 I/O ports used for expanded mode operation.
5. Generate a schematic for the combined system.

1. Assess the Memory, 110, and Logic Requirements of the Combined System
This step has already been discussed. Key determinations to be made in this step include:
• How much I/O is required for the combined application?
- Consider single-chip usage and any additional I/O that will be necessary for current and/or future
product enhancements.
• How much memory is required for the combined application?
- Consider potential firmware enhancements and the possibility of source code migration from assembly language to a high-level language like C or a visual application builder.
- Also consider additional RAM requirements. PSD4XX and PSD5XX devices provide 2K x 8 of
SRAM that can be powered from backup batteries, and future derivatives may eliminate the SR~M
to reduce cost. If even more RAM is necessary, the PSD can provide the decode logic needed to
memory map larger devices .
• How much logic will be required?
- Any conversion to a two chip solution will use at least some of the PSD decode logic for memory,
liD port, and control register mapping. If the existing single-chip system uses PALs or 74HC family
logic, consider using the PSD to replace as much of this as possible. The lower chip count reduces
cost and use of the PSDsiios IIITM simulation software can reduce system debug time.

2. Select the Appropriate M68HC11 and PSD Combination
Choose the M68HC11 and PSD combination carefully.
• When compatibility between the single-chip M68HC11 system and its PSD-based expanded mode
counterpart is essential, use a ROM-less version of the single-chip MCU. In the example application,
the MC68HC711 K4 can be replaced with an MC68HC11 K1 or MC68HC11 KO paired with the
PSD412A1.
• In applications where maximum compatibility is not required, carefully selecting the M68HC11 MCU
and PSD can realize considerable cost savings.
- If the M68HC11 device is used because it has a large EPROM array, consider replacing it with a
smaller ROM-less derivative. The PSD can be chosen to maximize available EPROM and I/O.
- If the M68HC11 device is used to provide large amounts of liD, choose the nearest equivalent
ROM-less version and a PSD that will maximize available I/O.

4·16

MOTOROLA

AN12421D

-

If the M68HC11 device is used for high-speed execution, consider using a smaller ROM-less derivative capable of the same performance. The PSD can be chosen to maximize available EPROM
and I/O.
- If the M68HC11 device is used because it has a specific on-chip peripheral complement, choose
the nearest equivalent ROM-less version and PSD that approximate the functionality of the singlechip device.
• Selection of an appropriate PSD is relatively straightforward. The device must meet the memory, I/O,
and logic requirements determined in Step 1. If necessary, the MCU can be chosen to augment PSD
resources, such as I/O and logic used for chip selects.

3. Produce the Two-Chip System Memory Map
This step is best explained by continuing with the example application. First, examine the memory map of
the M68HC11 derivative to be used and locate areas not occupied by internal memory resources. These
openings in the 16-bit address space are available for memory mapping external devices. The following
ranges are externally addressable for MC68HC11 K(0/1) devices:
$0380 to $OD7F
$1000 to $FFFF ($2000 to $FFFF if CSIO is used)
A 60-Kbyte block of space is available from $1000 to $FFFF in expanded operating mode. However, if the
chip select I/O (CSIO) function implemented in M68HC11 K-series devices is used, this area is reduced to
56 Kbytes available from $2000 to $FFFF.
Allocating space to CSIO allows use of a memory-mapped display controller instead of a display controller
with a serial or a parallel interface. A number of manufacturers provide a complete LCD solution that includes an intelligent display controller. The controller can be connected directly to a microcontroller address/
data bus if slow access times can be managed. The CSIO signal is ideal for this purpose because it can be
stretched by up to three E clock cycles. CSIO requires the fixed 4-Kbyte block of addresses from $1000 to
$1 FFF in order to operate.
Compile the memory map for the two chip system by listing the following address ranges:
•
•
•
•
•
•
•

M68HC11 SRAM
M68HC11 register block
M68HC11 EEPROM, if used
M68HC11 fixed chip-select address ranges, if used
256-byte PSD register block
PSD SRAM, if used
PSD EPROM blocks

Figure 5 shows the combined memory map for the example application.

AN12421D

MOTOROLA

4-17

$0000

SRAM, REGISTERS, EEPROM

REGISTERS

$007F
--- -$0080

•

---

CSIO ADDRESS SPACE

t

768 BYTES SRAM

$2000
$037F
--- -- ---

2 KBYTES PSD SRAM

PSD SRAM, PSD REGISTERS

$0380

$27FF

. - - - - -$2800

$28FF PSD REGISTER BLOCK

EXTERNAL ADDRESSES

---=::.:....:..

$OD7F

$2900

$OD80
640 BYTES EEPROM

EXTERNAL tDRESSES

~

$OFFF
$1000

$3FFF
$4000 LCD AND CONSTANT

$1FFF

DATA PAGE 0
(PSD EPROM BLOCK 0)

OR

16K X 2 EPROM PAGES

LCD AND CONSTANT
DATA PAGE 1

$7FFF (PSD EPROM BLOCK 1)
---:$8=0=-=0-=-0

$7FFF
$8000

CONTROL ALGORITHMS
(PSD EPROM BLOCKS 2 & 3)

32 KBYTES EPROM
$FFBF
$FFCO
$FFFF

$FFBF

VECTORS
AN1242 pSD MEM MAP

Figure 5 Combined MC68HC11 K1 + PSD412A 1 Memory Map
The ultimate purpose of this memory map is to guide development of a PSDabel™ file. PSDabel is one component of WSI's comprehensive PSDsoft™ design package that also includes PSDcontrol™ (configuration,
compilation, de-compilation, fitting, address translation, hex data file conversion, and device programming)
and PSDsiios IIITM (Verilog-based device simulation). PSDabel is based on Data 110 Corporation's ABEL
Hardware Description Language. It is used to describe the logical operation of the PSD4XX and PSD5XX
decode ZPLD (DPLD) and general-purpose ZPLD (GPLD).
A listing of the PSDabel file used to implement the memory map shown in Figure 5 follows. The included
comments provide a basic understanding of how a PSDabel file is constructed. Refer to the PSDabe{fM
Manua/for further documentation and a tutorial.

4-18

MOTOROLA

AN12421D

module K4_TO_PSD_CONVERSION
title 'MC68HC711K4 to MC68HC11K1 + PSD412A1 Conversion'
"The followlng sectlon llsts the input signals.
"First come the address lines using their reserved names. Note that only those signals
"listed are routed to the DPLD.
a1S,a14,a13,a12,a11,a10,a9,a8,a1,aO pin;
"Next come the general purpose inputs used for the paging scheme. Uncomment the lines
"implementing the desired paging. For this application, the PSD page register will be used
"because it requires no additional I/O pins. The Kl memory expansion address lines may be
"used if additional address bits or the page register inputs are required for specific
"decoding purposes. Use of the page register will be discussed later.
pgr3,pgr2,pgr1,pgrO pin;
xapage pin 20;

"These are the 4 input bits of the PSD page register.

"This is XA14 from the MC68HC11K1 and is used to select one of the 16K LCD
"data table pages.

"The M68HC11 non-multiplexed bus control signals are specified here.
rd_wr,e pin 29,41;

"M68HCll R/W* and E specified here as PSD pins 29 (WR) and 41 (RD).

"Now the DPLD chip select outputs are listed.
"CSIOP is the chip select for the PSD register block.
"RSO is the chip select for the 2K PSD SRAM.
"ES[0:3J are the chip selects for -PSD EPROM blocks 0, 1, 2, and 3.
csiop,rsO,8s0,esl,es2,es3 node;

"Signal definitions and groupings now follow.
X = .x.;

"This is how a don't care term is specified.

"This definition groups together the CPU address lines.
CPUaddress

~

[alS,a14,a13,a12,a1l,a10,a9,a8,X,X,X,X,X,X,al,aOJ;

"This definition groups together the page register bits.
PAGE

[pgr3,pgr2,pgrl,pgrOJ;

~

"DPLD Chip Select Equations.
"This maps the PSD register block from $2800 to $28FF.
~

csiop

(CPUaddress

>~

Ah2800) & (CPUaddress

<~

Ah28FF);

"This maps the PSD 2K SRAM from $2000 to $27FF.
rsO

(CPUaddress

~

>~

Ah2000) & (CPUaddress

<~

Ah27FF);

"This maps 16K PSD EPROM block 3 from $COOO to $FFFF.
es3

(CPUaddress

~

>~

AhCOOO) & (CPUaddress

<~

AhFFFF);

"This maps 16K PSD EPROM block 2 from $8000 to $BFFF.
es2

(CPUaddress

~

>~

Ah8000) & (CPUaddress

<~

AhBFFF);

"This maps 16K PSD EPROM block 1 from $4000 to $7FFF when XA14 is logic one, i.e. this is LCD
"data table page 1. Use this equation when the K1 memory expansion is used in place of the
"PSD page register.
"es1

~

xapage & (CPUaddress

>~

Ah4000) & (CPUaddress

<~

Ah7FFF);

"This maps 16K PSD EPROM block 1 from $4000 to $7FFF when PAGE ~ $1, i.e. this is LCD
"data table page 1. Do not use this equation if the K1 memory expansion is being used.
es1

(PAGE

~

~~

Ahl) & (CPUaddress

>~

Ah4000.) & (CPUaddress

<~

Ah7FFF);

"This maps 16K PSD EPROM block 0 from $4000 to $7FFF when XA14 is logic zero, i.e. this is LCD
"data table page O. Use this equation when the K1 memory expansion is used in place of the
"PSD page register.
"esO

~

!xapage & (CPUaddress

>~

Ah4000) & (CPUaddress

<~

Ah7FFF);

"This maps 16K PSD EPROM block 0 from $4000 to $7FFF when PAGE ~ $0, i.e. this is LCD
"data table page O. Do not use this equation if the Kl memory expansion is being used.
esO ~ (PAGE ~~ AhO) & (CPUaddress >~ Ah4000) & (CPUaddress <~ Ah7FFF);
end K4_TO_PSD_CONVERSION

AN12421D

MOTOROLA

4-19

4. Determine Which PSD 1/0 Ports Replace M68HC11 1/0 Ports
PSD4XX and PSD5XX devices have five 8-bit I/O ports, labeled A, S, C, D, and E. When used with a nonmultiplexed bus M68HC11, port C becomes the 8-bit data bus. Of the available 32 bits of general-purpose
1/0,24 are used to rebuild M68HC11 ports S, C, and F (the addressldata bus), and the remaining eight can
be used to rebuild port G bit 7 (the Rfiiii line) and other port G or port H I/O pins used for expansion address
lines or chip selects.
To modify existing single-chip M68HC11 software to take advantage of PSD 110 ports, simply substitute
PSD register addresses for M68HC11 register addresses. A typical M68HC11 I/O port has both a data direction register and a port data register. Every PSD I/O port has a control register that determines port function, a data direction register, a data in register, and a data out register. Some PSD I/O ports also have
registers to enable open drain operation, to determine if a pin is used as a PLD signal or I/O bit, and to read
the outputs of the GPLD.
A good way to view the port relationships between a PSD and an M68HC11 is to construct a table that lists
each port and its associated registers. On one side of the table, list the M68HC11 I/O port and its registers,
and on the other side, list the equivalent PSD I/O port and its registers. Use this table as a guide when modifying single-chip firmware to support the two chip M68HC11/PSD system. Table 2 is an I/O mapping table
for the example application. Remember that CSIOP is mapped from $2800 to $28FF.

Table 2 M68HC11 to PSD 1/0 Conversion Table
MC68HC711 K4
Port B

Port C

Port F

Occupied
Port G/H

DDRB
PORTB

DDRC
PORTC

DDRF
PO RTF

$0002
$0004

$0007
$0006

$0003
$0005

DDRG/H

$007F
or
$007D

PORTG/H

$007E
or
$007D

1/0

Port B

PortA

Port E

PSD412A1
PB_DDR

$2801
$2805

PB_CONTROL
PB_PLD_IO

$2803
$2806

P6_MAC_OUT

$280D

PA_DDR
PA_I N DATA

$2806
$2800

PA_OUTDATA

$2804

PA_CONTROL
PA_PLD_IO

$2802
$280A

PA_MAC_OUT

$280C

PE_DDR
PE_INDATA
PE_OUTDATA

$2826
$2820
$2824

PE_CONTROL
PE_PLD_IO

$282A

PE_MAC_OUT

$282C

PD_DDR

$2817

PD_INDATA

$2811

PD_OUTDATA
PD_CONTROL

$2815
$2813
$2819

MOTOROLA

$2822

Port D

PD_OPN_DRN

4-20

$2807

PB_INDATA
PB_OUTDATA

AN1242/D

As Table 2 indicates, the location of each PSD register is specified as an 8-bit offset from the CSIOP base
address specified in the PSDabel file. The PSD4XX and PSDSXX documentation lists these 8-bit offsets.
A few small differences in I/O functionality should be noted:
• I/O ports on some M68HC11 devices have assignable pull-up resistors. For example, the PPAR register at $002C on M68HC11 K-series MCUs can enable pull-up devices on ports G and H in all modes
and on ports Band F only in single-chip mode. This feature is not available on PSD4XX or PSDSXX
devices, so external pull-ups may be needed.
• I/O ports B, C, and F on M68HC11 K-series MCUs do not have any sort of control or alternate function
registers, although port C can be placed in open drain mode with the CWOM bit in the OPT2 register
at $0038. If this functionality must be maintained, replace port C on the MC68HC711 K4 with PSD4XX
or PSDSXX port D. The open drain control register (PD_OPN_DRN in the table above) allows each
PSD port D I/O pin to be configured for normal or open drain mode.
• The PGAR register at $002D is used to enable the memory expansion address lines associated with
port G bits 0 to S. Setting bits in this register to one overrides the port G I/O functions and enables the
associated XA lines. This register is cleared to $00 after reset.
• Chip select control registers CSCTL, GPCS1A, and GPCS2A, located respectively at $OOSB, $OOSC,
and $OOSE, override the I/O functions of port H bits 4 to 7. In expanded operating mode, GPCS1A and
GPCS2A are set to $00 after reset, thus disabling general-purpose chip selects 1 and 2 (CSGP1 and
CSGP2). CSCTL will be set to $04 after reset, leaving the I/O chip select (CSIO) disabled and the program chip select (CSPROG) enabled. Write CSCTL to $00 to disable CSPROG and make the PH7/
CSPROG pin available for I/O. CSPROG is not required for interfacing to the PSD, although it can be
used in conjunction with the PSD power management unit (PMU) to reduce power consumption.
The code examples that follow demonstrate how the PSD I/O ports are accessed in comparison with
M68HC11 I/O ports. Access to the other PSD control registers is achieved in the same straightforward fashion. Please refer to PSD4XX and PSDSXX documentation for more information.

AN1242/D

MOTOROLA

4-21

Single-Chip MC68HC711 K4

MC68HC11K(O/1) + PSD412A1

* port B, e, and F I/O

* port B, A, and E I/O

REGBASE
DDRB
PORTB
DDRC
PORTC
DDRF
PORTF

REGBASE
PB_DDR
PB_INDATA
PB_OUTDATA
PB_CONTROL
PA_DDR
PA_INDATA
PA_OUTDATA
PA_CONTROL
PE_DDR
PE_INDATA
PE_OUTDATA
PE_CONTROL

equ
equ
equ
equ
equ
equ
equ

$0000
$02
$04
$07
$06
$03
$05

* read port B [7: 0]
clr
ldaa

REG BASE + DDRB
REG BASE + PORTB

equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ
equ

$2800
$07
$01
$05
$03
$06
$00
$04
$02
$26
$20
$24
$02

* write pattern to port C [7: 0]

ldaa
staa
ldaa
staa

*
*
*
*

#$FF
REG BASE + DDRC
#$55
REG BASE + PORTC

configure PF[3:0] for inputs,
PF[7:4] for outputs, poll until PFO
is set to 1, then write pattern to
PF [7: 4] .

ldx
ldaa
staa
POLLPFO brclr
bset

#REGBASE
#$FO
DDRF,X
PORTF,X,$Ol,POLLPFO
PORTF,X,$AO

* make ports B, A, and E exclusively
* available for I/O
ldaa
staa
staa
staa

#$FF
REGBASE + PB_CONTROL
REGBASE + PA_CONTROL
REGBASE + PE_CONTROL

* read port B[7:0]
clr
ldaa

REGBASE + PB_DDR
REGBASE + PB_INDATA

* write pattern to port A[7:0]
1daa
staa

#$FF
REGBASE + PA_DDR

ldaa
staa

#$55
REGBASE + PA_OUTDATA

* configure PE[3:0] for inputs,

* PE[7:4] for outputs, poll until PEO
* is set to 1, then write pattern to
* PE [7: 4] .

POLLPEO

4-22

MOTOROLA

ldx
ldaa
staa
brclr
bset

#REGBASE
#$FO
PE_DDR,X
PE_INDATA,X,$Ol,POLLPEO
PE_OUTDATA,X,$AO

AN12421D

5. Generate a Schematic for the Combined System
Table 3 shows the connections between a non-multiplexed bus M68HC11 and a PSD4XX or PSD5XX

Table 3 M68HC11 to PSD Connections
M68HC11

PSD4XX or PSD5XX

ADDR[15:0]

ADIO[15:0]

DATA[7:0]

PC[7:0]

E

RD

RNI

WR

An expansion address line (XA14) could be connected to one of the PSD port A inputs, and used to select
the 16-Kbyte LCD table EPROM pages. In the example application, however, it is easier to use the PSD
page register. The four page register bits (PG[3:0]) can be used as inputs to the DPLD. In the example
PSDabellisting, the ESO and ES1 EPROM chip selects are decoded when the page register value is $0 or
$1 and the CPU address is between $4000 and $7FFF.
The page register is accessed as follows.

REG BASE
PSD_PAGE

equ

$2800

equ

$EO
$00

PAGEO
equ
PAGEl
equ
LCD_LINE1 equ
LINE_LEN

equ

$01
$4000
$FO

* select EPROM page O/LCD table 0
ldaa

#PAGEO

staa

REGBASE + PSD_PAGE

* read data from selected page

SEND_ Ll

ldx
ldab

#LCD_LINEl
#LINE_LEN

ldaa
jsr

SEND_DATA

O,X

inx
decb
bne

SEND_Ll

etc.

The page register bits are available as inputs to both the DPLD and the GPLD. In fact, the DPLD can generate two additional chip selects called PSELO and PSEL 1 that can be used to connect other peripheral devices to the combined system. Using the page register, these devices could be mapped into the $4000 to
$7FFF range used for EPROM blocks 0 and 1. If a more complex decoding function is needed, the GPLD
and its associated macrocells can be used.

AN1242/D

MOTOROLA

4-23

CONCLUSION
Figure 6 shows the newly-enhanced system, which has plenty of free general-purpose 1/0 to handle a large
parallel interface keyboard. A number of different LCD solutions can be supported - the choices range from
simple 1/0 driven devices to complete intelligent controller-based displays with synchronous serial or memory mapped interfaces. The system is capable of meeting next generation product specifications with room
to spare for future expansion.

Highly integrated M68HC11 derivatives, such as the MC68HC711 K4, can often serve as complete solutions
for single-chip embedded control systems. Cost-effective designs with these devices make extensive use
of on-board peripherals like the SCI, SPI, timer, and AID converter. However, an application can outgrow
the original design, and when this happens, it may be difficult to find an enhanced derivative to meet new
peripheral and memory requirements.
To solve this problem, users of high performance M68HC11 devices can pair a ROM-less M68HC11 derivative with a WSI PSD4XX or PSD5XX programmable system device. WSI's highly integrated microcontroller peripherals can deliver a cost-effective combination of EPROM, RAM, programmable logic, digital 1/0,
timer, and interrupt control modules. The M68HC11/PSD combination retains many advantages of the original single-chip MCU solution while providing a flexible resource complement for future application growth.

REFERENCES
Motorola MC68HC11 K4 Technical Data Book (MC68HC11 K4/D)
Motorola MC68HC11 K4 Programming Reference Guide (MC68HC11 K4RG/D)
WSI PSD Programmable Peripherals Design and Applications Handbook.

4-24

MOTOROLA

AN1242/D

VDD

~ss

L1ss
VDD

~ 1l;~

n ""I H

r\I ....

it5

0

~

:I: C<5

C\I

....

~a

P87/ADDR15
PB6iADDR14

PB5IADDA13

!i:if~o..ifs:a:ZEpB4/ADDR12
PB3IADDR11

Q.

ANALOG INPUTS {

•

PB2iADDR10
PB1/ADOR9
PBOIADORB
VOD
VSS

MC68HCllKl

...-.. -

PULSE-ACTUATED OUTPUTS

EDGE-TRIGGERED INPUTS

PF7/ADOR7
PF6IADORB
PF5IADDR5

~~:~:

{

vss
}

...

----

PF2IADOR2
PF1/ADDR1

.{

VDD

PFOIADORO

8ffl

»

'--y---J

voo
DAT.\I7 OJ - pe[7 0]
VSS

AN1242SCHEM3

Figure 6 Keyboard and LCD Ready MC68HC11K1 + PSD412A1 System

AN12421D

MOTOROLA

4·25

DEVICE REFERENCE TABLES
Table 4 M68HC11 Derivatives with Non-Multiplexed Address/Data Bus
Motorola
Part Number

ROM

RAM

or EPROM (Bytes)

EEPROM
(Bytes)

Total
I/O

On-Chip
Peripherals

Technical
Data

MC68HC11F1

0

1024

512

30

Standard 1
+ 4 chip selects

MC68HC11F1/D

MC68HC11G5

16K

512

0

66

Standard
+ 10-bit ADC
+ event counter

MC68HC11 G5/D

MC68HC711 G5

16K

512

0

66

Standard
+ 10-bit ADC
+ event counter

MC68HC 11 G5/D

MC68HC11G7

24K

512

0

66

Standard
+ 10-bit ADC
+ event counter

MC68HC11 G5/D

MC68HC11KO

0

768

0

37

Enhanced 2
+ 4 chip selects
+ memory expansion

MC68HC11 K4/D

MC68HC11K1

0

768

640

37

Enhanced
+ 4 chip selects
+ memory expansion

MC68HC11 K4/D

MC68HC11K4

24K

768

640

62

Enhanced
+ 4 chip selects
+ memory expansion

MC68HC11 K4/D

MC68HC711 K4

24K

768

640

62

Enhanced
+ 4 chip selects
+ memory expansion

MC68HC11 K4/D

MC68HC11KA4

24K

768

640

51

Enhanced

MC68HC11 KA4TS/D

MC68HC711 KA4

24K

768

640

51

Enhanced

MC68HC11 KA4TS/D
MC68HC11 P2/D
MC68HC11 P2ID

MC68HC11 P2

32K

1024

640

62

Enhanced
+ 2 SCI+

MC68HC711 P2

32K

1024

640

62

Enhanced
+ 2 SCI+

NOTES:
1. The standard peripheral complement consists of an 8-bit, 8 channel AID converter (ADC), senal communications interface (SCI), serial peripheral interface (SPI), 16-bit timer with 3 or 4 input captures (ICs), 4 or 5
output compares (OCs), pulse accumulator, real-time interrupt, and computer operating properly (COP)
watchdog monitor.
2. The enhanced peripheral complement improves on the standard peripheral complement with an SCI+ (enhanced SCI with parity generation and more flexible baud rate generator) and an enhanced SPI (additional
baud rates and selectable bit shifting order) and four pulse width modulation (PWM) timers.

4-26

MOTOROLA

AN1242/D

Table 5 PSD4XX and PSD5XX Derivatives
WSI
Part Number

Bus Width
(Bits)

Inputs

Product
Terms

Registered
Macrocells

EPROM
Density

PSD401A1

x8orx16

37

113

8

32K x 8 or 16K x 16

PSD411A1

x8

37

113

8

32K x 8

PSD402A1

x 8 orx 16

37

113

8

64K x 8 or 32K x 16

PSD412A1

x8

37

113

8

64K x 8

PSD403A1

x 8 orx 16

37

113

8

128K x 8 or 64K x 16

PSD413A1

x8

37

113

8

128K x 8

PSD401A2

x 8 or x 16

59

126

24

32K x 8 or 64K x 16

PSD411A2

x8

59

126

24

32Kx8

PSD402A2

x 8 orx 16

59

126

24

64K x 8 or 32K x 16

PSD412A2

x8

59

126

24

64Kx8

PSD403A2

x 8 orx 16

59

126

24

128K x 8 or 64K x 16

PSD413A2

x8

59

126

24

128K x8

PSD501B1

x 8 or x 16

61

140

30

32K x 8 or 16K x 16

PSD511B1

x8

61

140

30

32Kx8

PSD502B1

x 8 orx 16

61

140

30

64K x 8 or 32K x 16

PSD512B1

x8

61

140

30

64K x 8

PSD503B1

x80rx 16

61

140

30

128K x 8 or 64K x 16

PSD513B1

x8

61

140

30

128Kx 8

PSD4XX and PSD5XX devices have SRAM that can be configured as 2K x 8 or 1K x 16, 40 I/O pins, and
a power management unit (PMU). PSD5XX devices have a peripheral unit consisting of four 16-bit counters/
timers, a watchdog timer, an eight-level interrupt controller, and programmable logic for memory mapping.
All PSDs are available with access speeds of 90, 120, 150, or 200 nanoseconds.

NOTE: This Motorola document is also known as Application Note 044 at WSI, Inc.

AN12421D

MOTOROLA

4-27

Motorola reserves the nght to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the sUitability
of ItS products for any particular purpose, nor does Motorola assume any liability anslng out of the application or use of any product or CircUit, and specifically disclaims any and
all liability, Including without limitation consequential or Incidental damages "Typical" parameters can and do vary In different apphcatlons All operating parameters, Including
"TYPlcals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under Its patent nghts nor the rights of others.
Motorola products are not designed, Intended, or authorized for use as components In systems Intended for surgical Implant IOta the body, or other applications Intended to
support or sustain hfe, or for any other application In which the failure of the Motorola product could create a Situation where personal InJUry or death may occur Should Buyer
purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall Indemnify and hold Motorola and ItS officers, employees, subsidiaries,
affiliates, and distributors harmless a9amst all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or mdlrectly, any claim of personal
Injury or death associated With such unintended or unauthorized use, even If such claim alleges that Motorola was neghgent regarding the design or manufacture of the part
MO"'OROLA and
are registered trademarks of Motorola, Inc Motorola, Inc IS an Equal Opportunity/Affirmative Action Employer.

®

Literature Distribution Centers:
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EUROPE: Motorola Ltd.; European Literature Centre; 88 Tanners Drive, Blakelands, Milton Keynes, MK14 5BP, England.
JAPAN: Nippon Motorola Ltd.; 4-32-1, Nishi-Gotanda, Shinagawa-ku, Tokyo 141 Japan.
ASIA-PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No.2 Dal King Street, Tai Po Industrial Estate,
Tai Po, N.T., Hong Kong.

4·28

@ MOTOROLA

===:='~
------

.:'=iiiII-.-= -==
~

---~.-..

PSD3XX Family

ZPSD3XX Family

PSD4XX/5XX Family

Motorola Application Notes

Sales Representatives
and Distributors

- -----

- - - - - -----

------ ---

~--~----

Section Index
Sales
Representatives
and Distributors

Domestic
Representatives ...................................................................................................................5-1
Domestic
Distributors ...........................................................................................................................5-1
International
Distributors ...........................................................................................................................5-1
WSI Direct

Sales Offices ........................................................................................................................5-1

For additional Information,
Cal/BOO-TEAM-WSI (BOO-B32-6974).
In California, CaI/BOO-562-6363

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Fax. (770) 938-0194

Fax. (607) 722-3774

Fax. (847) 490-1499

- - ==IE
_====
-------...-

,.-~

~

I'~~-~.-.--

----~~

CDrporate Headquarters
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Fremont, Califomia 94538-7333
Tel: 510-656-5400 Fax: 510-657-5916
800-TEAM-WSI (800-832-6974)
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Web Site: http://www,wsipsd.com

6114196 Rev 2 8

OHMS Technology, Inc.
Tel (612) 932-2920
Fax. (612) 932-2918

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Fax: 972-3-6960255
ITALY
Comprel SPA
Tel. 39-3625781

Fax: 39-362553967
Sllverstar
Tel. 39 2661251
Fax' 39 266101359
JAPAN
InternlX, Inc.
Tel 813-3-369-1105

Laser & Electro",c
EqUipment
Tel 41-1-4223330
Fax 41-1-4223458
TAIWAN
Ally, Inc
Tel' 886-2-768-6399
Fax 886-2-768-6390

Fax 813-3-363-8486
Kyocera Corporation
Tel 813-3-708-3111

Fax. 813-3-708-3372
Nippon Imex CorporatIOn
Tel 813-3-321-8000
Fax 813-3-325-0021
KOREA
Woo Young Tech Co ,
Ltd.
Tel 82-2-369-7099
Fax 82-2-369-7091

EUROPE SALES

ASIA SALES

WSI- France
2 VOle La Cardon
91126 Palalseau
Cedex, France
Tel 33 (1) 69-32-01-20
Fax 33 (1) 69-32-02-19

WSI - Asia, Ltd
1006 C.C Wu Bldg
302-308 Hennessy Rd
Wan Chal, Hong Kong
Tel' 852-2575'()112
Fax 852-2893-0678
Korea Branch
Tel. 82-2-761-128112
Fax 82-2-761-1283

5-1

WSI Worldwide Sales, Service and Technical Support

5·2

WaferScale Integration, Inc. (WSI) reserves the right to make changes without further notice to any products herein. WSI makes no
warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does WSI assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including
"Typicals" must be validated for each customer application by customer's technical experts. WSI does not convey any license under its
patent rights nor the rights of others. WSI products are not designed, intended, or authorized for use as components in systems intended
for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of
the WSI product could create a situation where personal injury or death may occur. Should Buyer purchase or use WSI products for any
such unintended or unauthorized application, Buyer shall indemnify and hold WSI and its officers, employees, subSidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that WSI was
negligent regarding the design or manufacture of the part.

Information furnished herein by WaferScale Integration, Inc. (WSI) is believed to be accurate and reliable. However, no responsibility is
assumed for its use. WSI makes no representation that the use of its products or the interconnection of its circuits, as described herein,
will not infringe on existing patent rights. No patent liability shall be incurred by WSI for use of the circuits or devices described herein. WSI
does not assume any responsibility for use of any circuitry described, no circuit patent rights or licenses are granted or implied, and WSI
reserves the right without commitment, at any time without notice, to change said circuitry or specifications. The performance
characteristics listed in this book result from specific tests, correlated testing, guard banding, design and other practices common to the
industry. Information contained herein supersedes previously published specifications. Contact your WSI sales representative for specific
testing details or latest information.

Products in this book may be covered by one or more of the following patents. Additional patents are pending.
U.S.A: 4,328,565; 4,361,847; 4,409,723; 4,639,893; 4,649,520; 4,795,719; 4,763,184; 4,758,869; 5,006,974; 5,016,216; 5,014,097;
5,021,847; 5,034,786; 5,136,186; 4,939,392; 4,961,172
West Germany: 3,103,160
Japan: 1,279,100
England: 2,073,484; 2,073,487

PSDsoft is a trademark of WaferScale Integration, Inc.
MagicPro and PSD301 are registered trademarks of WaferScale Integration, Inc.
ABEL, ABEL-HDL, and ABEL-PLA are trademarks of Data 1/0 Corporation.
Data 110 is a registered trademark of Data 1/0 Corporation.
SIMUCAD and SILOS III are trademarks of SIMUCAD, Inc.
IBM and IBM Personal Computer are registered trademarks of International Business Machines Corporation.
PAL is a registered trademark of Advanced Micro Devices, Inc.
Copyright © 1996 WaferScale Integration, Inc. All Rights Reserved.

Rev 1 B

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47280 Kato Road
Fremont, California 94538-7333
Phone: 510/656-5400
Fax: 510/657-5916
800/ TEAM-WSI (800/832-6974)
In California 800/562-6363
Printed in U. S.A. 6/96
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