1996_Xilinx_Programmable_Logic_Data_Book 1996 Xilinx Programmable Logic Data Book

User Manual: 1996_Xilinx_Programmable_Logic_Data_Book

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HAMILTON .

HALLMARK

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~ XILlNX"

~XILINX®

The Programmable Logic
Data Book
Technical Support Telephone Hotline:

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On behalf of the employees of Xilinx, our sales representatives, our distributors, and our
manufacturing partners, welcome to our 1996 Data Book, and thank you for your interest in
Xilinx products and services.
As the inventor of Field Programmable Gate Array technology and the world's leading
supplier of programmable logic, we would like to pledge our continuing commitment to
providing you, our users, with the best possible integrated circuit components, development
systems, and technical and sales support.
Over the past year, we have substantially broadened our product line with the introduction of
the XC4000E, XC4000EX, XC5000, and XC6000 series of FPGAs and the XC9500 family of
CPLDs. The recently-introduced XACTstep v6 and Foundation series products have set a
new standard for functionality and ease-of-use in programmable logic development systems.
You can expect this pace of innovation to continue, and even increase, as we maintain our
leadership role in bringing leading-edge programmable logic solutions to the market.
We look forward to satisfying all of your programmable logic needs.

Sincerely,

Wim Roelandts
Chief Executive
Officer

Section Titles

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

Table of Contents

Introduction
An Introduction to Xilinx Products .................. " ... " .................... 1-1

Development System Products
Development Systems Products Overview .•.......... ; . . . . . . . . . .. . . . .. . . . . . . . . .2-1
Bundled Packages ProductDescriptions .................... , . • . . . . . . . . . . . . . .. . . . 2-9
Individual ProductDescriptions ............................................... 2-27

CPLD Products
XC9500 Series Table of Contents. . . . . . . .. . . . . . . . . . . . . . . . . . . . .•. . . .. . . . . . . . . . . 3-1
XC9500 In-System Programmable CPLD Family ................................. 3-3
XC9536 In-System Programmable CPLD ..................... , .............. , .. 3-17
XC9512 In-System Programmable CPLD .. , .................... ; ....... , , , , , . , . 3-23
XC95108 In-System Programmable CPLD , . , , , , , , , , .... , , , ., , . , , , , , , . , . , , . , , , , , 3-27
XC95144 In-System Programmable CPLD , , , " , , , " , , , , , , , , . , " ,. , , , " , " , " , , , 3-35
XC95180

In~System

Programmable CPLD , " '" , , , , , , , , , , , , , , , , ., , . , ; , , .,. , , , , , . 3-4 t

XC95216 In-System Programmable CPLD , , , , , , , , , , . , , . , , . , , . , , , , , . , .. , . , .. , , , , 3-47
XC95288ln-Systern Programmable CPLD , , , , ., " , , , , , , , , , , , , , , , , " , , . , , , , , , , , , 3-57
XC95432 In-System Programmable CPLD ., , , . , . , , . , , , , , , , , ' , , . , . , , , , . , , , , , , . , , 3-65
XC95576 In-System Programmable CPLD " , , , , . , . , , , , . , , ., , , , , " , , , , , . , . " , , , , 3"67

XC7300Series Table of Contents, .. , . , , ..• , .. , .... , .... , .... , ....... , . , , ; , . , 3-69
XC7300 CMOS CPLDFamily , . , ., , . , . , , , .. , .. , . , .. , ... , .... , . , .... , ....... , . 3-71
XC7318 18-MacrocelliCMOS CPl..D , . , , , ., .. , " ., , . , ., .. , . '" , .. " .. , ....... , , 3-81
XC73361XC7336Q36-Macrocell CMOS CPLD ... , ..•.... , . , ..... , ....•... , .. , . . . . 3-89
XC7354 54-Macrocell CMOS CPLb , ........ , .. , . , .... , ...... , .. , . , ......... , .3-99
XC7372 72-MacroceIICfy10S CPl..D; ... , , ...... ' ..........•..... , . , .... , ;.... , .... , . 3~1 07.
XC73108 108-Macrocell CMOS CPLD ....... , .... , , ...... , ........... , .... , . , . 3-115
XC73144 144-Macrocell CMOS CPLD . , . , , , , .. , , . , , .. , ..... , .. , . , .... , , ...... , 3-125
XC7300 Characterization Data . , .. , ........ , , ...... , ...... , ........... , . . . . . . 3-135

XC7200 Series Table of Contents . ........................................... 3-145
XC7236A 36-Macrocell CMOS CPLD .......................................... 3-147
XC7272A 72-Macrocell CMOS CPLD .......................................... 3-163

SRAM-Based FPGA Products
XC4000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
XC4000 Series Field Programmable Gate Arrays ................................. 4-5
XC5200 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-179
XC5200 Field Programmable Gate Arrays ....................................... 4-181
XC5200L Field Programmable Gate Arrays ...................................... 4-249
XC6200 Series Table of Contents . ........................................... 4-251
XC6200 Field Programmable Gate Arrays ....................................... 4-253
XC3000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287
XC3000 Series Field Programmable Gate Arrays ................................. 4-289
XC3000A Field Programmable Gate Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-341
XC3000L Field Programmable Gate Arrays ...................................... 4-349
XC3100A Field Programmable Gate Arrays ..................................... 4-357
XC3100L Field Programmable Gate Arrays ...................................... 4-365

SPROM Products
XC1700D Family of Serial Configuration PROMs ................................. 5-1

3V Products
3.3 V and Mixed Voltage Compatible Products ................................... 6-1

HardWire Products
Xilinx HardWire™ Array Overview ............................................. 7-1

Military Products
High-Reliability and Military Products ........................................... 8-1

Programming Support
HW-130 Programmer ....................................................... 9-1

Packages and Thermal Characteristics
Packages and Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 10-1

~XILINX
Testing, Quality, and Reliability
Quality Assurance and Reliability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11-1

Technical Support
Technical Support ......................................................... 12-1

Product Technical Information
Product Technical Information Table of Contents ................................. 13-1
Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-3
XC4000 Series Technical Information .......................................... 13-9
XC3000 Series Technical Information .......................................... 13-13
FPGA Configuration Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-25
Configuring Mixed FPGA Daisy Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-33
Configuration Issues: Power-up, Volatility, Security, Battery Back-up .................. 13-35
Dynamic Reconfiguration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-39
Metastable Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-41
Set-up and Hold Times ..................................................... 13-45
Overshoot and Undershoot .................................................. 13-47
Boundary Scan in XC4000 and XC5000 Series Devices ............................ 13-49

Index
Index ................................................................... 14-1

Sales Offices, Sales Representatives, and Distributors
Sales Offices, Sales Representatives, and Distributors. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15-1

Introduction

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability

12 Technical Support
13 Product Technical Information

14 Index
15 Sales Offices, Sales Representatives, and Distributors

Introduction Table of Contents

An Introduction to Xilinx Products
About this Book. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Sheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Book Contents ........... '................................................
About the Company . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Product Line Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Programmable Logic vs. Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Faster Design and Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Changes without Penalty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Shortest Time-to-Market. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Component Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Field Programmable Gate Arrays (FPGAs) ....................................
Complex Programmable Logic Devices (CPLDs) ................................
HardWire devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Serial PROMs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High-Reliability Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Development System Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

1-1
1-1
1-1
1-2
1-2
1-3
1-3
1-3
1-3
1-3
1-4
1-4
1-4
1-4
1-5
1-5
1-5

An Introduction to Xilinx Products

About this Book
This Data Book provides a "snapshot in time" in its listing of
IC devices and development system software available
from Xilinx as of early 1996. New devices, speed grades,
package types and development system products are continually being added to the Xilinx product portfolio. Users
are encouraged to contact their local Xilinx sales representative and consult the WebLlNX World Wide Web site (http:/
/www.xilinx.com) and the quarterly XCELL newsletter for
the latest information regarding new product availability.
The product specifications for several older Xilinx FPGA
families are not included in this Data Book. This does not
imply that these products are no longer available. However,
for new deSigns, users are encouraged to use the newer
products described in this book, which offer better performance at lower cost than the older technologies. Product
specifications for the older products are available at
WebLlNX, the Xilinx site on the World Wide Web, or through
your local Xilinx sales representative. These products
include the following FPGA families: the XC2000, XC3000,
XC3100, XC4000, XC4000A, XC4000D, and XC4000H
families.

Data Sheet Categories
In order to provide the most up-to-date information, some
component products included in this book may not have
been fully characterized at the time of publication. In these
cases,the AC and DC characteristics included in the data
sheets will be marked as Advance or Preliminary information. (Not withstanding the definitions of such terms, all
specifications are subject to change without notice.) These
deSignations have the following meaning:
•

•
•

Advance - Initial estimates based on simulation and/
or extrapolation from other speed grades, devices, or
device families. Use as estimates, but not for final
production.
Preliminary - Based on preliminary characterization.
Changes are possible, but not expected.
Final (unmarked) - Specifications not identified as
either Advance or Preliminary are to be considered
final.

Data Book Contents
Chapter 1 is a general overview of the Xilinx product line,
and is recommended reading for designers who are new to
the field of high-density programmable logic.

Chapter 2 contains a discussion of the overall design
methodology when using Xilinx programmable logic and
descriptions of Xilinx development system products. This
chapter is placed at the beginning of the book since these
development tools are needed to design with any of the Xilinx programmable logic devices.
Chapter 3 contains the product descriptions for the Xilinx
Complex Programmable Logic Device (CPLD) products,
including the XC7000 and XC9000 series.
Chapter 4 includes the product descriptions for the Xilinx
static-memory-based Field Programmable Gate Array
(FPGA) products, including the XC3000, XC4000, XC5000,
and XC6000 series.
Chapter 5 holds the product descriptions for the XC1700
family of Serial PROM devices.. These Serial PROMs provide a convenient, low-cost means of storing configuration
programs for the SRAM-based FPGAs described in Chapter 4.
Chapter 6 is an overview of Xilinx components appropriate
for 3.3 V and mixed-voltage systems. This chapter will refer
you back to the appropriate product descriptions in the earlier chapters.
Chapter 7 contains a brief overview of the HardWire product line. Detailed product specifications are available in
separate Xilinx data sheets.
Chapter 8 is an overview of Xilinx High-Reliability/Military
products. Detailed product specifications are available in
separate Xilinx data sheets.
Chapter 9 describes the HW130 device programmer for
the XC1700 series of Serial PROMs and the XC7000 and
XC9000 series of CPLDs.

a

Chapter 10 contains description of all the physical packages for the various IC products, including information
about the thermal characteristics of those packages.
Chapter 11 discusses the testing, quality, and reliability of
Xilinx component products.
Chapter 12 includes a listing of all the technical support
facilities provid!'ld by Xilinx.
Chapter 13 contains additional information about X/linx
components that is not provided in the. product. specifications of the earlier chapters. This includes some additional
electrical parameters that are not in the product specifications because they are not part of the manufacturing test
program for the particular device, but may be of interest to
the user. Also included in this chapter is a discussion of the

1-1

I

An Introduction to Xilinx Products

JTAG boundary test scan logic found in several Xilinx component families.
The final two sections contain an index to the topics
included in this Data Book and a listing of Xilinx sales
offices, sales representatives, and distributors.

About the Company
Xilinx, Inc., offers the industry's broadest selection of programmable logic devices. With 1995 revenues of over $500
million, Xilinx is the world's largest supplier of programmable logic, and the market leader in Field Programmable
Gate Arrays (FPGAs).
Xilinx was founded in 1984, based on the revolutionary idea
of combining the logic density and versatility of gate arrays
with the time-to-market advantages and convenience of
user-programmable standard parts. One year later, Xilinx
introduced the world's first Field Programmable Gate Array.
Since then, through a combination of architectural and
manufacturing process improvements, the company has
continually increased device performance, in terms of
capacity, speed, and ease-of-use, while lowering costs.
In 1992, Xilinx expanded its product line to include
advanced Complex Programmable Logic Devices (CPLDs,
also known as EPLDs). For the user, CPLDs are an attractive complement to FPGAs, offering simpler design software and more predictable timing.

1-2

As the market leader in one of the fastest growing segments of the semiconductor industry, Xilinx strategy is to
focus its resources on creating new ICs and development
system software, providing world-class technical support,
developing markets, and building a diverse customer base
across a broad range of geographic and end-use application segments. The company has avoided the large capital
commitment and overhead burden associated with sole
ownership and operation of a wafer fabrication facility.
Instead, Xilinx has established alliances with several highvolume, state-of-the-art CMOS IC manufacturers. Using
standard, high-volume processes assures low manufacturing costs, produces programmable logic devices with wellestablished reliability: and provides for early access to
advances in CMOS processing technology.
Xilinx headquarters are located in San Jose, California. The
company markets its products wQrldwide through a network
of direct sales offices, manufacturers' representatives, and
distributors (as listed in the back of this book). The company has representatives and distributors in over 38 countries.

Product Line Overview
Field Programmable Gate Arrays (FPGAs) and Complex
Programmable Logic Devices (CPLDs) can be used in virtually any digital logic system. Over 35 million Xilinx components have been used in a wide variety of end-equipment
applications, ranging from supercomputers to hand-held

~XILINX
instruments, from central office switches to centrifuges, and
from missile guidance systems to guitar synthesizers.
Xilinx achieved its leading position through a continuing
commitment to provide a complete product solution. This
encompasses a focus on all three critical areas of the highdensity programmable solution "triangle": components (silicon), software, and service (Figure 1).

Programmable Logic vs. Gate Arrays
Xilinx programmable logic devices provide the benefits of
high integration levels without the risks or expenses of
semi-custom and custom IC development. Some of the
benefits of programmable logic as versus mask-programmed gate arrays are briefly discussed below.

Faster Design and Verification
Xilinx FPGAs and CPLDs can be designed and verified
quickly while the same process requires several weeks with
gate arrays. There are no non-recurring engineering (NRE)
costs, no test vectors to generate, and no delay while waiting for prototypes to be manufactured.

Design Changes without Penalty
Because the devices are software-configured and userprogrammed, modifications are much less risky and can be
made anytime - in a manner of minuies or hours, as
opposed to the weeks it would take with a gate array. This
results in significant cost savings in design and production.

Shortest Time-to~Market
When designing with Xilinx programmable logic, time-tomarket is measured in days or a few weeks, not the months
often required when using gate arrays. A study by market
research firm McKinsey & Co. concluded that a six-month
delay in getting to market can cost a product one-third of its

lifetime potential profit. With mask-programmed gate
arrays, design iterations can easily add that much time, and
more, to a product schedule.
Once the decision has been made to use Xilinx programmable logic, a choice must be made from a number of product families, device options, and product types. The
information in the product selection matrices that follow can
help guide that selection; detailed product specifications
are available in subsequent chapters of this book. Since
many component products are available in common packages with common footprints, designs often can be
migrated to higher or lower density devices, or even across
some product families, without any printed circuit board
changes. Design ideas, represented in text or schematic
format, are converted into a configuration data file for an
FPGA or CPLD device using the Xilinx XACTstep development software running on a PC or workstation.

Component Products
Xilinx offers the broadest line of programmable logic
devices available today, with hundreds of products featuring
various combinations of architectures, logic densities,
package types, and speed grades in commercial, industrial,
and military grades. This breadth of product offerings
allows the selection of· the programmable logic device that
is best suited for the target application.
Xilinx programmable logic offerings include several families
of reprogram mabie FPGAs, one-time-programmable
FPGAs, EPROM-based CPLDs, and FLASH-memorybased CPLDs (Figure 2). HardWire devices are mask-programmed versions of the reprogrammable FPGAs, and
provide a transparent, no-risk migration path to lower-cost
devices for high-volume, stable designs. Additionally, a
family of Serial PROM devices is available to store configuration programs for the reprogram mabie FPGA devices.

• Optimized circuits/architectures

• Powerful but easy

• Highest performance/densities

• Integrated across families

• Deep submicron processes

• Seamless integration into
customer CAE system

• Unmatched quality
and reliability

SERVICE
• Global world class sales/distribution support
• Global world class technical support: FAEs/support center/on-line/internet
• Global world class manufacturing: quality/capacity/delivery

X5955

Figure 1: The Xilinx Programmable Solution Triangle

1-3

An Introduction to Xilinx Products

Many devices are available in military temperature range
andlor MIL-STD-883B versions, for high-reliability and military applications.

Field Programmable Gate Arrays (FPGAs)
FPGA devices feature a gate-array-like architecture, with a
matrix of logic cells surrounded by a periphery of liD cells,
as diagrammed in Figure 3. Segments of metal interconnect can be linked in an arbitrary manner by programmable
switches to form the desired signal nets between the cells.
FPGAs combine an abundance of logic gates, registers,
and lIDs with fast system speed. Xilinx offers several families of reprogram mable, static-memory-based (SRAMbased) FPGAs, including the XC2000, XC3000, XC4000,
XC5000, and XC6000 series.
ASIC Alternatives
Gate Arrays

Custom
Highest Density
ASIC Tools

Xilinx

Product Line

CPLD
ISP
PAL Architecture

FPGA
Programmable
Gate Array
Architecture
High Density
ASIC Tools

HartlWire™
Custom
Transparent Conversion
100% Tested

Complex Programmable Logic Devices (CPLDs)
Designers more comfortable with the speed, design simplicity, and predictability of PALs may prefer CPLD devices.
Conceptually, CPLDs consist of multiple PAL-like function
blocks that can be interconnected through a switch matrix
(Figure 4). The Xilinx XC7000 CPLD series is based on
EPROM technology. The new XC9000 CPLD series features 5V in-system programmable FLASH technology, and,
like most of the FPGA families, includes built-in JTAG
boundary scan test logic.

HardWire devices
HardWire devices are masked-programmed versions of the
SRAM-based FPGAs. The HardWire products provide an
easy, transparent migration path to a cost-reduced device
without the engineering burden associated with conventional gate array re-design. The HardWire gate array is
architecturally identical to its FPGA counterpart, but the
programmable elements in the FPGA are replaced with
fixed metal connections. The resulting die is considerably
smaller, with a correspondingly lower cost. Using proprietary automatic test vector generation software and patented test logic, Xilinx guarantees over 95% fault coverage,
while eliminating the need for user-generated test vectors.
The mask and test programs are generated automatically
by Xilinx from the user's existing FPGA design file.

Serial PROMs
The XC1700 family features one-time programmable serial
PROMs ranging in density from about 18,000 bits to over
260,000 bits. These serial PROMs are an easy-to-use,
cost-effective method for storing configuration data for the
SRAM-based FPGAs.

PAL Devices
Programmable AND/OR
Architecture
Low Density
Simple Tools

Figure 2: Application-Specific

Ie Products

~

ottc

PROGRAMMABLE
INTERCONNECT

goo

00000
00000
00000

DOOOOOOOOg

~ggggggggg
ooooooog

D

~~L,:iCl~c;:lL,:i~OO~L,:idL,:ic:'J

X1153

LOGIC BLOCKS

Figure 3: FPGA Architecture

1-4

~XILINX

Interconnect
Matrix

I/O

•

X5956

Figure 4: CPLD Architecture

High-Reliability Devices
Xilinx was the first company to offer high-reliability FPGAs
by introducing MIL-STD-8f:13B qualified XC2000 and
XC3000 series devices in 1989. MIL-STD-883B members
of the XC4000 FPGA series also are available, and qualified versions of additional Xilinx families are in development. The product line also includes Standard Microcircuit
Drawing (SMD) versions of several families. Some Xilinx
devices are available in tested die form through arrangements with manufacturing partners.

Development System Products
Xilinx offers a complete software environment for the implementation of logic designs in Xilinx programmable logic
devices. This environment, called XACTstep, combines
~owerful technology with a flexible, easy-to-use graphical
Interface to help users achieve the best possible designs,
regardless of experience level. The user has a wide range
of choices between a fully-automatic implementation and
detailed involvement in the layout process. The XACTstep
system provides all the implementation tools required to
design with Xilinx logic devices, including the following:
•
•
•
•
•
•
•

Xilinx is committed to an "open system"approach to frontend design creation, synthesis, and verification. Xilinx
devices are supported by the broadest number of EDA vendorsand synthesis vendors in the industry, Supported platforms include the ubiquitous PC .and several popular
workstations.

Service
Providing global, world-class manufacturing, technical support, and sales/distribution support is an essential foundation of the Xilinx product strategy. Xilinx manufacturing
facilities have earnedlS09002 certification, and Xilinx
quality and reliability achievements are among the world's
best - not just for programmable logic suppliers, but among
all semiconductor companies. Comprehensive technical
support facilities include training courses, extensive product documentation and application notes, a quarterly technical newsletter, automated document servers, a technical
bulletin board, the WebLiNX World Wide Web site, technical support hotlines, and a cadre of Field Application Engineers. Sales support is provided by a wOrldwide network of
representatives and distributors.

libraries and interfaces for popular schematic editors,
logic synthesis tools, and simulators
design manager/flow engine
module generator
map, place, and route compilation software
graphical floorplanner
static timing analyzer
hardware debugger

1-5

An Introduction to Xilinx Products

FPGA Product Selection Matrix
III

w

(J

XC3000 Series

:>
W

..J

..J

..J

0
N
0

0
C"l
0

N

C"l
()

c

..J

..J

10
0

CJ)

< < < <
<
"'" "'"
><

0

C"l
()

C"l

C"l
()

~

><

><

0

0

C"l
()

ct

ct

ct

ct

ct

C"l
.,..

10

0

CJ)
.,..

C"l
()

.,..
"'"

CJ)
.,..

C"l

.,..
"'"

ct
It)

N
.,..

C"l
()

C"l
()

C"l
()

0

I ()
><
><

0

><

N

C"l
()

><

><

><

><

III

w
>11:

Low Cost!
Low Power

w~
:.::!;j:

..J

..J

.,..
"'"

CJ)
.,..

N

C"l
()

><

0

C"l
()

><

Low Voltage
(3.3 V)
Highest
Performance

Highest Performance

w

II-

Max Logic Gates (K)

1.5

2

3

5

6

1.5

2

3

5

6

8

3

6

Max RAM Bits

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

iii

Typical Gate Range (K)

H.5

1.5-2

2-3

4-5

5-6

H.5

1-2

2-3

4-5

5-6

7-8

2-3

5-6

W

CLBs

64

100

144

224

320

64

100

144

224

320

484

144

320

Flip-Flops

256

360

480

688

928

256

360

480

688

928

1320

480

928

III

Output Drive (mA)

4

4

4

4

4

8

8

8

8

8

8

4

4

IX

JTAG (IEEE 1149.1)

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N

N
1.5

~

Z

C

w

~

l-

Dedicated Arithmetic

N

N

N

N

N

w

Quiescent Current (mA)

0.51
0.02

0.51
0.02

0.51
0.02

0.51
0.02

0.51
0.02

8

8

8

8

8

8

1.5

Fastest Speed Grade

-6/-8

-6/-8

-6/-8

-6/-8

-6/-8

-09

-09

-09

-09

-09

-09

-2

-2

124/69 124/69 124/69 124/69 124/69

312

312

312

312

312

312

256

256

e(

II-

Shift Register (MHz)
Small State Machine (MHz)

42123

42/23

42/23

42/23

42/23

112

112

112

112

112

112

68

68

Large State Machine (MHz)

21/14

21/14

21/14

21/14

21/14

55

55

55

55

55

55

33

33
33

4-Bit Multiply-Accumulator (MHz)

20/12

20/12

20/12

20/12

20/12

51

51

51

51

51

51

33

W
(J

16-Bit Accumulator (MHz)

25/15

25/15

25/15

25/15

25/15

58

58

58

58

58

58

41

41

Z

Address Map Decoder (MHz)

52127

52127

52/27

52/27

52/27

127

127

127

127

127

127

84

84

e(

:a
II:

Data Path (MHz)

147/86 147/86 147/86 147/86 147/86

335

335

335

335

335

335

84

84

0

Counter Timer (MHz)

37/23

37/23

37/23

37/23

37/23

81

81

81

81

81

81

56

56

II:

16-Bit Non Loadable Counter (MHz)

135/81

135/81

135/81

135/81

135/81

370

370

370

370

370

370

323

323

D-

16-Bit Loadable Binary Up Counter (MHz)

39/25

39/25

39/25

39/25

39/25

91

91

91

91

91

91

63

63

16-Bit Loadable Prescaled Counter (MHz)

100/59 100/59 100/59 100/59 100/59

228

228

228

228

228

228

154

154

II-

W

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

Pad to Setup (ns)

14/12

14/12

14/12

14/12

14/12

2.5

2.5

2.5

2.5

2.5

2.5

4

4

Clock to Pad (ns)

7/18

7/18

7/18

7/18

7/18

4

4

4

4

4

4

5

5

Combinatorial Pad to Pad (ns)

14/25

14/25

14/25

14/25

14/25

6

6

6

6

6

6

8

8

RAM Read Modify Write (MHz)

1-6

~XILINX
FPGA Product Selection Matrix (continued)
W

U>

w
;:
w

0

XC4000 Series

W

~

...<=
0

:g

0

0

~

><

0

W

8

><

§

~

><

w

I

"-

Max Logic Gates, (no RAM) (K)

~z

w

0

en

Max RAM Bits (no Logic)

I

><

u

x

><

><
w

g
<

...
~

~
<.>

><

..J

><

ill

~

><

:z:

3

5

6

8

10

13

20

25

:J:

.

:g

8

<=

~
<.>

u
><

><

><

36

44

52

0;
<.>

><

62

3

5

5

73728

3200

6272

6272

10

2-5

3-9

4-12

6-15

7-20

10-30

13·40

15-45

18-50 22-65

27-80 33-100 40·130

2·5

3-9

3·9

7·20

196

256

324

400

576

784

1024

1024

1296

1600

1936

2304

100

196

196

400

576

Flip-Flops

360

616

768 . 936

1120 I 1536

2016

2560

2560

3168

3840

4576

5376

200

392

616

1120

1536

12

12

12
y

12
y

12
y

12
y

24
y

24
y

4
y

4
y

4
y

12

JTAG (IEEE 1149.1)

Y

Dedicated Arithmetic

Y

Y
y

Y
y

"-

Quiescent Current (rnA)

10

10

10

12
y

12
y

12
y

y

12
y

y

y

y

y

y

Y
y

10

10

10

10

10

10

·2

-2

I

I

I

Fastest Speed Grade

·2

·2

-2

·2

·2

·2

·2

Shift Register (MHz)

190

190

190

190 I 190

190

190

190

190

,

I

y

y

y

y

10

10

10

10

y
I 10

y

y

y

y

0.05

0.05

0.05

-2

-2

-2

-2

-5

-5

190

190

190

190

105

105

Small State Machine (MHz)

69

69

69

69

69

69

69

69

69

69

69

69

69

48

48

Large State Machine (MHz)

43

43

43

43

43

43

43

43

43

43

43

43

43

37

37

4-8it Multiply-Accumulator (MHz)

39

39

39

39

39

39

39

39

39

39

39

39

39

20

20

16-Bit Accumulator (MHz)

65

65

65

65

65

65

65

65

65

65

65

65

65

36

36

>a:
~
()

z

Address Map Decoder (MHz)

71

71

71

71

71

71

71

71

71

71

71

71

71

43

43

:!l

Data Palh (MHz)

156

156

156

156

156

156

156

156

156

156

156

156

156

105

105

Ll-

~

Counter Timer (MHz)

117

117

117

117

117

117

117

117

117

117

117

117

117

58

58

I-

II:

16-Bit Non Loadable Counter (MHz)

180

180

180

180

180

180

180

180

180

180

180

180

180

95

95

"-

16-Bit Loadable Binary Up Counter (MHz)

87

87

87

87

87

87

87

87

87

87

87

87

87

42

42

115

115

115

115

115

115

115

115

115

115

63

63

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

50

50

16-Bit Loadable Prescaled Counter (MHz)

115

115

115

RAM Read Modily Write (MHz)

N/A

N/A

N/A

Pad to Setup (ns)

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

2.6

7

7

Clock to Pad (ns)

6.5

6.5

6.5 I 6.5

6.5

6.5

6.5

6.5

6.5

6.5

6.5

6.5

6.5

10

10

Combinatorial Pad to Pad (ns)

10.5

10.5

10.5

10.5

10.5

10.5

10.5

10.5

10.5

10.5

10.5

10.5

5

5

I

10.5

10·30

10

w

w

13

12800 18432

100

12



><

Typical Gate Range (Logic and RAM) (K)

12

II:

.,...

Low Voltage
(3 V)

I/O

28

...<=

..

elBs
Output Drive (rnA)

0

...
g

...
<.>

High

3200 6272 8192 10368 12800 18342 25088 32768 32768 41472 51200 61952

w
II:
=>

!Cw

><
w

8

High Density
High Performance
Select-RAM'M Memory

>11:

w=>

"'!Cw

....

><
w

...~ I <.>...~
0

u
! ><

><

U>

w

~
~

II

u

u
><

0

><

w

~

~

W

:g

<{

()
<{

I-

Z

0

()

'Usable gates assume 20% of CLBs used as RAM
rJl

w
0
;:
w

XC5000, XC6000 Series

~

§
><

0

II

;!;

fll

<.>

><

en
w

<=

~

><

<>
><

§

~'"

fll

I

u
><

High Density
Low Cost

>11:

w=>

"'!Cw

. .~ .....
I

iji
u
><

I

><

JlP Interface
Fast Configuration

I

"-

Max Logic Gates (K)

~

u
><

<.>

24

55

Max RAM Bits

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

en
z

Typical Gate Range (K)

2-3

4-6

6-10

10-16

15-23

9-13

16-24

36-55

64-100

e

CLBsiLogic Cells

64

120

196

324

484

2304

4096

9216

16384

Flip-Flops

256

480

784

1296

1936

4096

9216

16384

8
y
y

8
y

8
y
y

8
y
y

8
y

2304
8-

8

8

8

N

N

N

N

y

N

N

N

N

15

15

-

-

-

-

w

en
w

Output Drive (rnA)

II:

=>

JTAG (IEEE 1149.1)

!Cw

Dedicated Arithmetic

"-

Quiescent Current (mA)

6

10

16

23

100

13

>

t::

3

15

y
15

15

I

Fastest Speed Grade

-4

-4

-4

-4

-4

Shift Register (MHz)

83

83

83

83

83

Small State Machine (MHz)

50

50

50

50

50

Large State Machine (MHz)

35

35

35

35

35

4-8it Multiply-Accumulator (MHz)

24

24

24

24

24

w

16-Bit Accumulator (MHz)

60

60

60

60

60

0

----

>-

II:

0

I-

()
<{
Ll-

z

Address Map Decoder (MHz)

69

69

69

69

69

:!l

Data Path (MHz)

83

83

83

83

83

e

Counter Timer (MHz)

59

59

59

59

59

II:

16-Bit Non Loadable Counter (MHz)

N/A

N/A

N/A

N/A

N/A

()
<{

58

IZ

<

0

~
~

0

><

"

"

'"w

"'t1!l
><

:?;
~

"
><

~

~
><

:g
~

.

"'

~

><

><

fZ
l!l
" 5 "'" "
><

><

'""
:;;

"><'"

100% Routable
100% Utilization

>-'"
w::>

"'!i:w

"'"><

~

~

I

~

"><

'"'"fll
'""><

~

~

l!l

"><

"><

JTAG
5VISP
3Vor5V 1/0

5 ns TpD

u.

:J
:;;

>-

Gates (K)

0.4

0.8

0.8

1.5

1.9

3.0

3.8

0.8

1.6

2.4

3.2

4.0

4.8

6.4

9.6

12.8

'"zw

Macrocalls

18

36

36

54

72

108

144

36

72

108

144

180

216

288

432

576

c

Flip~Flops

18

36

36

108

126

198

234

36

72

108

144

180

216

288

432

576

'"
'"
<

Output Drive (rnA)

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

JTAG (IEEE 1149.1)

N

N

N

N

N

N

Y

Y

y

y

y

y

y

y

y

Dedicated Arithmetic

N

N

N

y

y

N
y

y

N

N

N

N

N

N

N

N

N

-

-

-

-10

-10

-10

-

-

168

192

232

232

232

232

!:

w
::>
0-

w
u.

Quiescent Current (rnA)

90

126

50

140

187

227

250

-

Fastest Speed Grade

-5

-5

-10

-7

-7

-7

-7

-5

Shift Register (MHz)

125

125

95

95

95

95

Small State Machine (MHz)

108

108

95

95

95

95

Large State Machine (MHz)

102

102

95

95

95

95

4-Bit Multiply-Accumulator (MHz)

46

46

52

52

52

52

16-Bit Accumulator (MHz)

40

40

63

63

63

63

"<:IEz

Address Map Decoder (MHz)

108

108

95

95

95

95

Data Path (MHz)

125

125

95

95

95

95

0

Counter Timer (MHz)

94

94

47

47

47

47

...

16-Bit Non Loadable Counter (MHz)

125

125

95

95

95

95

()

16-Bit Loadable Binary Up Counter (MHz)

125

125

95

95

95

95

I-

16-8it Loadable Prescaled Counter (MHz)

125

125

95

95

95

95

RAM Read Modify Write (MHz)

N/A

N/A

N/A

NlA

NlA

N/A

Pad to Setup (ns)

3.5

3.5

4

4

4

4

Clock to Pad (ns)

4.5

4.5

7

7

7

7

5

5

7

7

7

7

84

120

156

w

a:

u.
a:
w

Combinatorial Pad to Pad (ns)

-7

140

-

-7

-7

-

>-

0::

0

I()


PropB;gation Delay =tpD

=================i>
Setup Time:;: tsu
Clock to Out Time teo

(a)

(b)

=

o
tpco

==========~
Setup TilT!e

=tpsu

Clock to Out Time = tpco

Internal System Cycle Time = tSYSTEM

(d)

(e)

o
D
Internal Cycle Time = teNT

-----'-===:>

(e)

Propagation Delay:::.; tpD +tFBK
With Feedback

Setup

(I)

Time

(··O-o~
1--'
-

-

-

Setup'Time :;: tsu +
With Fe,edback

-

Lt°

-

teo

====:>
tFBK
Clock to Out Time = teo
(g)

X5903

Figure 14: Basic Timing Model

August 1, 1996 (VerSion 1.1)

3-15

XC9500 In-System Programmable CPLD Family

Power-Up Characteristics

other HDL languages in a variety of ·software front-endtools. The XACT step development system can be used to
implement the design and generate a JEDEC bitmap which
can be used to program the XC9500 device.The XACTstep
development system includes JTAG download software
that can be used to program the devices via a download
cable.

The XC9500 devices are well behaved under all operating
conditions. During power-up each XC9500 device employs
internal circuitry which keeps the device in the quiescent
state until VCCINT supply voltage is at a safe level (approximately 3.8 V). During this time, all device pins and JTAG
pins are disabled, and all device outputs are disabled with
the lOB pull-up resistors (- 10K ohms) enabled. See
Table 5. When the supply voltage reaches a safe level, all
user registers become initialized (within 100 ~s typical),
and the device is immediately available for operation, as
shown in Figure 15.

FastFLASH Technology
An advanced 0.6 ~m CMOS Flash process is used to fabricate all
XC9500 devices. Specifically developed for Xilinx in-system programmable CPLDs, the process provides high performance
logic capability and endurance of 10,000 program/erase
cycles.

If the device is in the erased state (before any user pattern
is programmed), the device outputs remain disabled with
the lOB pull-up resistors enabled. The JTAG pins are
enabled to allow the device to be programmed at any time.

VCCINT

If the device is programmed, the device inputs and outputs
take on their configured states for normal operation. The
JTAG pins are enabled to allow device erasure or boundary-scan tests at any time.

3.8V
(Typ)

In mixed 3.3 V/5 V systems, itis recommended that VCCINT
;::: VCCIO at all times during the power-up sequence.

ov
No

XACT stepTM Development System

Power

Quiescent
State

User Operation

L

The XC9500 CPLD family is fully supported by the Xilinx
XACTstep development system. The designer can create
the design using ABEL, schematics, equations, VHDL or

QU~~:f:nt

Initialization of User Registers

No

Power
X5904

Figure 15: Device Behavior During Power-up

Table 4: Timing Model Parameters
Description

Parameter

Propagation Delay
Global Clock Setup Time
Global Clock-to-output
Product Term Clock Setup
Time
Product Term Clock-to-output
Internal System Cycle Period
Feedback Time

tpD

Product Term
Allocator1

Macrocell
Low-Power Setting

Output Slew-Limited
Setting

+ tpTA • S
+ tpTA * S

+ tLP
+ t LP

+ tSLEW

-

-

+ tSLEW

+ tpTA * S

+ t LP

-

tsu
tco
tpsu

-

tpco

-

-

+ tSLEW

tSYSTEM
tFBK

+ tpTA * S
+ tpTA • S

+ t LP
+ tLp

-

Note: 1. S = the logic span of the function, as defined in the text.
Table 5: XC9500 Device Characteristics

3-16

Device
Feature

Quiescent
State

Erased Device
Operation

Valid User
Operation

lOB Pull-up Resistors
Device Outputs
Device Inputs and Clocks
Function Block
JTAG Controller

Enabled
Disabled
Disabled
Disabled
Disabled

Enabled
Disabled
Disabled
Disabled
Enabled

Disabled
As Configured
As Configured
As Configured
Enabled

August 1, 1996 (Version 1.1)

XC9536 In-System
Programmable CPLD
June 1, 1996 (Version 1.0)

Preliminary Product Specification

Features

Power Management

•
•
•
•
•

Power dissipation can be reduced in the XC9536 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.

•
•

•
•
•
•
•
•
•
•
•

5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
36 macrocells with 800 usable gates
Up to 34 user I/O pins
5 V in-system programmable
Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
PClcompliant (-5, -7, -10 speed grades)
Advanced 0.6 11m CMOS 5V FastFLASH technology
Available in 44-pin PLCC and 44-pin VQFP packages

Description
The XC9536 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of two
36V18 Function Blocks, providing 800 usable gates with
propagation delays of 5 ns. See Figure 2 for the architecture overview.

June 1, 1996 (VerSion 1.0)

Operating current for each design can be approximated for
specific operating conditions using the following equation:

Icc (mA)

=

MCHP (1.7) + MCLP (0.9) + Me (0.006 mA/MHz) f
Where:

= Macrocells in high-performance mode
= Macrocells in low-power mode
=Total number of macrocells used

MCHP
MCLP
MC
f

=Clock frequency (MHz)

Figure 1 shows a typical calculation for the XC9536 device.

(83)

;?

.s

(50)

(50)

0

.9

1l
'5.

'"

>-

(30)

50
Clock Frequency (MHz)

Figure 1: Typical Icc

100
X5920

vs. Frequency For XC9536

3-17

XC9536 In-System Programmable CPLD

JTAG Port {

18

I/O
I/O
I/O
x
·c

I/O

Cii

:;:;

•

•
•
•

18

.<::

I/O
Blocks

..g
;;:

(/)

I-

I/O

'-'
w

I/O

0

z
z

'-'
1ii

I/O

ro

LL

I/O

3
I/O/GCK
I/O/GSR

2
I/O/GTS

X5919

Figure 2: XC9536 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks

3-18

June 1, 1996 (Version 1.0)

~XIUNX
Absolute Maximum Ratings
Symbol

Warning:

I

Parameter

Value

Units

:

-0.5 to 7.0

i

-0.5 to Vee + 0.5
-0.5 to Vec + 0.5
-65 to +150
+260

V
V
V
°C
°C

I

Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
! Storage temperature
Max soldering temperature (10 ns @ 1/16 in = 1.5 mm)

Vee
VIN
VTS
TSTG
TSOL

i

I
!

I

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.

Recommended Operating Conditions'
Symbol

I

VeelNT
Ivcelo

VIL
V IH
Vo
TIN

Parameter

Min

Supply voltage for internal logic and input bulfer
Supply voltage lor output drivers for 5 V operation
Supply voltage lor output drivers lor 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
Input signal transition time

4.75
(4.5)
4.75 (4.5)
3.0

I

I

Max
5.25
(5.5)
5.25 (5.5)
3.6

I

I
I
I

Units
V

I

V
V

!
0.80

0
2.0
0

VeCINT+0.5
VeelNT + 0.5
50

V
V
V
ns

Note 1. Numbers in parenthesis are for industrial-temperature range versions.

DC Characteristics Over Recommended Operating Conditions
Symbol
VOH

VOL

IlL
IIH
CIN
ICC

Parameter
Output high voltage for 5 V operation

Test Conditions

IOH = -4.0 mA
Vee = Min
Output high voltage for 3.3 V operation IOH = -3.2 mA
Vee = Min
Output low voltage for 5 V operation
IOL = 24 mA
Vee = Min
Output low voltage for 3.3 V operation IOL = 10 mA
Vee = Min
Input leakage current
Vee = Max
V IN = GND or Vec
1/0 high-Z leakage current
Vee = Max
V IN = GND or VCC
1/0 capacitance
V IN = GND
1= 1.0 MHz
Operating Supply Current
VI = GND, No load
f= 1.0 MHz
(low power mode, active)

June 1, 1996 (Version 1.0)

Min

Max

2.4

Units
V
V

2.4
0.5

V

0.4

V

±10.0

IlA

±10.0

IlA

10.0

pF

I

30 mA Typ

3-19

I

XC9536 In·System Programmable CPLD

AC Characteristics

Note:

1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.

VTEST

Output Type
Device Output

o--~~----~--@.

VCC10
5.0V

VTEST
5.0 V

R1

R2

CL

160n

120n

35 pF

3.3V

3.3V

260n

360n

35 pF
X5906

Figure 3: AC Load Circuit

3·20

June 1, 1996 (Version 1.0)

~XILINX
XC9536110 Pins
Function
Block

Macrocell

PC44

VQ44

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

2
3
5
4
6
8
7
9
11
12
13
14
18
19
20
22
24

40
41
43
42
44
2
1
3
5
6
7
8
12
13
14
16
18
-

Note:

-

BScan
Notes
Order

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54

Function
Block

Macrocell

PC44

VQ44

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
44
42
43
40
39
38
37
36
35
34
33
29
28
27
26
25
-

39
38
36
37
34
33
32
31
30
29
28
27
23
22
21
20
19
-

[1]
[1]
[1]

BScan
Notes
Order

51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

[1]
[1]
[1]

I

[1J Global control pin

XC9536 Global, JTAG and Power Pins
Pin Type

PC44

VQ44

1/0/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR

5
6
7
42
40
39
17
15
30
16
21,41
32
23,10,31

43
44
1
36
34
33
11
9
24
10
15,35
26
17,4,25

TCK
TDI

TOO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GNO
No Connects

June 1, 1996 (Version 1.0)

-

-

3-21

XC9536 In-System Programmable CPLD

Ordering Information

-'T~

rpL

XC9536 - 5

~

Speed

va 44 C

T_mwrn"Number of Pins
Package Type

Speed Options
-15
15 ns pin-to-pin delay
-10
10 ns pin-to-pin delay
-7
7.5 ns pin-to-pin delay
-5
5 ns pin-to-pin delay

Temperature Options
C
Commercial
I
Industrial

Packaging Options
PC44
44-Pin Plastic Leaded Chip Carrier (PLCC)
VQ44 44-Pin Very Thin Quad Flat Pack (VQFP)

O°C to 70°C
-40°C to 85°C

X5952

Component Availability

X5907

3-22

June 1, 1996 (Version 1.0)

XC9572 In-System
Programmable CPLD
June 1, 1996 (Version 1.0)

Advance Product Specification

Features

Description

•

The XC9572 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised ot four
36V18 Function Blocks, providing 1,600 usable gates with
propagation delays of 7.5 ns. See Figure 1 for the architecture overview.

•

•
•
•

•
•

•
•
•
•
•
•
•
•
•

7.5 ns pin-to-pin logic delays on all pins
tCNT to 125 MHz
72 macrocells with 1,600 usable gates
Up to 72 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
PCI compliant (-7, -10 speed grades)
Advanced 0.6 11m CMOS 5V FastFLASH technology
Available in 84-pin PLCC, 1~O-pin PQFP and 1~O-pin
TQFP packages

June 1,1996 {Version 1.0)

Power Management
Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power
dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:

Icc (mA)

=

MC HP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:

=Macrocells in high-performance mode
= Macrocells in low-power mode
=Total number of macrocells used

MCHP
MC LP
MC
f

= Clock frequency (MHz)

3-23

XC9572 In-System Programmable CPLD

JTAG Port {

36
18

I/O

Function
Block 1

I/O
I/O
x
·c

I/O

1il

•

•
•
•

::t;

18

.s:;

I/O
Blocks

g

;:

C/)

f-

()

I/O

llJ

z
z

I/O

0

~

I/O

18

'"

LL

I/O

3
I/O/GCK,
18

I/O/GSR
I/O/GTS

2

X5921

Figure 1: XC9572 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks

3-24

June 1, 1996 (Version 1.0)

~XIUNX
XC9572 1/0 Pins
Function
Macrocell
Block

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PC84

PQ100

TQ100

BScan
Order

4
1
6
7
2
3
11
5
9
13
10
18
20
12
14
23
15
24
63
69
67
68
70
71
76
72
74
75
77
79
80
81
83
82
84

18
15
20
22
16
17
27
19
24
30
25
35
38
29
31
41
32
42
89
96
93
95
97
98
5
99
1
3
6
8
10
11
13
12
14
94

16
13
18
20
14
15
25
17
22
28
23
33
36
27
29
39
30
40
87
94
91
93
95
96
3
97
99
1
4
6
8
9
11
10
12
92

213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108

-

Notes

[1]
[1]

[1]

[1]
[1]
[1]

Function
Macrocell
Block

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PC84

PQ100

TQ100

BScan
Order

25
17
31
32
19
34
35
21
26
40
33
41
43
36
37
45
39

43
34
51
52
37
55
56
39
44
62
54
63
65
57
58
67
60
61
68
66
73
74
69
78
79
70
72
83
76
84
87
80
91
88
92
81

41
32
49
50
35
53
54
37
42
60
52
61
63
55
56
65
58
59
66
64
71
72
67
76
77
68
70
81
74
82
85
78
89
86
90
79

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

46
44
51
52
47
54
55
48
50
57
53
58
61
56
65
62
66
-

Notes

I

Notes: [1] Global control pin

June 1, 1996 (Version 1.0)

3-25

XC9572 In-System Programmable CPLD

XC9572 Global, JTAG and Power Pins
Pin Type

PC84

I/O/GCK1
1I0/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2

9
10
12
76
77
74
30
28
59
29
38,73,78
22,64
8,16,27,42,49,60

I/O/GSR
TCK
TOI
TOO
TMS
V CCINT 5 V
VCC10 3.3 V/5 V
GNO
No Connects

3-26

-

PQ100

TQ100

24
22
25
23
27
29
5
3
4
6
1
99
48
50
47
45
85
83
49
47
7,59,100
5,57,98
28,40,53,90
26,38,51,88
2,23,33,46,64,71,77,86 100,21,31,44,62,69,75,84
4,9,21,26,36,45,48,75,82 2,7,19,24,34,43,46,73,80

June 1, 1996 (Version 1.0)

XC95108 In-System
Programmable CPLD
June 1, 1996 (Version 1.0)

Preliminary Product Specification

Features

Power Management

•
•
•
•
•

PoweJ dissipation can be reduced in the XC95108 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.

•
•

•
•
•
•
•
•
•
•
•

7.5 ns pin-to-pin logic delays on all pins
fCNT to 125 MHz
108 macrocells with 2400 usable gates
Up to 108 user I/O pins
5 V in-system programmable
- Endurance of 10,000 programierasecycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18macrocells
within Function Block
Global and product term clocks, output enables, set
and reset Signals
Extensive IEEE.Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
PCI compliant (-7, -10 speed grades)
Advanced 0.6 11m CMOS 5V FastFLASH technology
Available in 84-pin PLCC, 1~O-pin PQFP, 1~O-pin TQFP
and 160-pin PQFP packages

Operating current for each design can be approximated for
specific operating conditions using the following equation:
Icc (mA)

=

MC HP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP

=Macrocells in low-power mode

=Total number of macrocells used
= Clock frequency (MHz)

MC
f

Figure 1 shows a typical calculation for the XC95108
device.

300 r - - - - - - - , - - - - - - - - ,

~

1

~Or---~~~---r------------~

(180)

()

Description

.2

The XC95108 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is· comprised of six
36V18 Function Blocks, providing 2,400 usable gates with
propagation delays of 7.5 ns. See Figure 2 for the architecture overview.

~

~

100 t - " ' = = - - - - - - - t - - - - - - - I

50
Clock Frequency (MHz)

100
X5898

Figure 1: Typical Icc vs. Frequency for XC95108

June 1, 1996 (Version 1.0)

I

XC951 08 In-System Programmable CPLD

Ie

3
JTAG Port {

JTAG
Controller

1

t

I ..

I

.. I
I

In-System Programming Controller

t

t

36

Function
Block 1

18/

I/O

:

I/O

1

II

~

I/O

36

.~

I/O

•
•
•
•

til
:2
I/O
Blocks

1

I/O ~

..g

II

:;:

en
LJ.J

I/O

0

~ca

I/O

36/

1

lJ

I/O
I/O/GCK

36

I/O/GTS ~

II

1

2

II

tt

Function
Block 6

18

--

Macrocells
1 to 18

~

36

L..J

tt

Function
Block 5

18/

1

Macrocel,ls
1 to 18

~

36

1

tt

Function
Block 4

18/

I/O/GSR

tt

Macrocells
1 to 18

~

3/
1

I

Function
Block 3

18

u..

tt

Macrocells
1 to 18

~,

t-

O

z
z

I

Function
Block 2

18/

'.s::

Macrocells
1 to 18

I

Macrocells
1 t018

~t
X5897

Figure 2: XC95108 Architecture
Note: Function Block outputs indicated by bold line drive directly to 110 Blocks

3-28

June 1, 1996 (Version ,1.0)

~XILINX
Absolute Maximum Ratings
Symbol

Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 ns @ 1/16 in = 1.5 mm)

Vee
VIN
VTS
TSTG
TSOL

Value

Units

-0.5 to 7.0
-0.5 to Vee + 0.5
-0.5 to Vee + 0.5
-65 to + 150
+260

V
V
V
DC
DC

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed .under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.

Recommended Operation Conditions 1
Symbol

Parameter

VeelNT

Supply voltage for internal logic and input buffer

Veelo

Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltageOutput voltage
Input signal transition time

V IL
VIH
Vo
TIN

Min

Max

Units

4.75
(4.5)
4.75 (4.5)
3.0
0
2.0
0

5.25
(5.5)
5 . 25 (5.5)
3.6
0.80

V

I

V
V
V
V
V
ns

VeeINT+0.5
VeelNT + 0.5
50

Note: 1. Numbers in parenthesis are for industrial-temperature range versions.

DC Characteristics Over Recommended Operating Conditions
Symbol
VO H

Parameter
Output high voltage for 5 V operation
Output high voltage for 3.3 V operation

VOL

Output low voltage for 5 V operation
Output low voltage for 3.3 V operation

IlL

Input leakage current

IIH

I/O high-Z leakage current

CIN

I/O capacitance

Icc

Operating Supply Current
(low power mode, active)

June 1, 1996 (Version 1.0)

Test CondiUons
IOH =-4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min
IOL = 24 mA
Vee = Min
IOL = 10 mA
Vee = Min
Vee = Max
VIN = GND or Vee
Vee = Max
VIN = GND or Vee
VIN= GND
f = 1.0 MHz
VI = GND, No load
f = 1.0 MHz

Min

Max

2.4

Units
V
V

2.4
0.5

V

0.4

V

±10.0

!LA

±10.0

!LA

10.0

pF

100 mA Typ

3-29

XC951 08 In-System Programmable CPLD

AC Characteristics

Note: 1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.

Device Output

o--+-----+---@
X5906

Figure 3: AC Load Circuit

3-30

June 1, 1996 (Version 1.0)

~XILINX
XC95108 1/0 Pins
Function
BScan
Function
BScan
Macrocell PC84 PQ100 TQ100 PQ160
Notes
Notes
Macrocell PC84 PQ100 TQ100 PQ160
Block
Order
Block
Order

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

1
2
3
4
-

5
6
7
9
10
11
12
13
71
72
74
75
76
77
79
80
81
82
83
84
-

15
16
21
17
18
19
20
26
22
24
25
27
29
30
98
99
4
1
3
5
6
9
8
10

13
14
19
15
16
17
18
24
20
22
23
25
27
28
96
97
2
99
1
3
4
7
6
8

-

-

11
12
13
14
-

9
10
11
12
-

-

25
21
22
29
23
24
27
26
28
36
30
33
34
35
37
42
44
43
158
154
156
4
159
2
9
6
8
12
11
13
14
15
17
18
19
16

321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216

[1]
[1]
[1]

[1]

[1]
[1]

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17

18

14
15
17
18
19
20

21
23
24
25
26
31
57
58
61
62
63
65
66
67

31
32
36
34
35
37
38
45
39
41
42
43
44
51
83
84
82
87
88
89
91
92
93

-

-

68
69
70
-

95
96
94
97
-

29
30
34
32
33

35
36
43
37
39
40
41
42
49
81
82
80
85
86
87
89

90
91
93
94
92
95

-

45
47
49
57
54
56
50
58
59
69
60
62
52
63
64
68
77
74
123
134
135
133
138
139
128
140
142
147
143
144
153
146
148
145
152
155

213
210
207
204
201
198
195
192
189
,186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108

I

Notes: [1] Glob.al control pin

June 1, 1996 (Version 1.0)

3-31

XC951 08 In-System Programmable CPLD

XC951 08 1/0 Pins (continued)
Function
Function
BScan
BScan
Macrocell PC84 PQ100 TQ100 PQ160
Notes
Macrocell PC84 PQ100 TQ100 PQ160
Notes
Order
Block
Order
Block
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5

-

-

-

32
33

52
54
48
55
56

50
52
46
53
54

34
35

-

-

-

36
37

57
58

55
56

-

-

-

39
40

60
62

58
60

-

-

-

41
43
44

63
65
61
66

61
63
59
64

-

-

-

-

76
79
82
72
86
88
78
90
92
84
95
97
87
98
101
96
102
89

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54

6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

-

-

-

45
46

67
68
75
69
70

65
66
73
67
68

47
48

-

-

-

50
51

72
73

70
71

-

-

-

52
53

74
76

72
74

-

-

-

54
55
56

78
79
81
80

76
77
79
78

-

-

-

-

91
103
104
116
106
108
105
111
113
107
115
117
112
122
124
129
126
114

51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

XC95108 Global, JTAG and Power Pins
Pin Type

PC84

PQ100

TQ100

PQ160

I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GSR
TCK
TOI

9
10
12
76
77
74
30
28
59
29
38,73,78
22,64
8,16,27,42,49,60

24
25
29
5
6
1
50
47
85
49
7,59,100
28,40,53,90
2,23,33,46,64,71,77,86

22
23
27
3
4
99
48
45
83
47
5,57,98
26,38,51,88
100,21,31,44,62,69,75,84

-

-

-

33
35
42
6
8
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141
20,31,40,51,70,80,99
100,110,120,127,137
160

Too
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GNO
GND
GND

3-32

June 1, 1996 (Version 1.0)

~XIUNX
Ordering Information

--=
1- 11 T 1
~ L
XC95108 -7 PQ 160 C

""'''' Type
Speed

Tempe"''''' Ran"
Number of Pins
Package Type

Speed Options
-20
-15
-10
-7

20 ns pin-to-pin delay
15 ns pin-to-pin delay
10 ns pin-to-pin delay
7 ns pin-ta-pin delay

Temperature Options
C
I

Commercial
Industrial

0°Ct070°C
-40°C to 85°C

I

Packaging Options
PC84
84-Pin Plastic Leaded Chip Carrier (PLCC)
PQ100 100-Pin Plastic Quad Flat Pack (PQFP)
TQ100 100-Pin Thin Quad Flat Pack (TQFP)
PQ160 160-Pin Plastic Quad Flat Pack (PQFP)

X5953

Component Availability

X5941

June 1, 1996 (Version 1.0)

3-33

XC951 08 In-System Programmable CPLD

3-34

June 1, 1996 (Version 1.0)

XC95144 In-System
Programmable CPLD
June 1, 1996 (Version 1.0)

Advance Product Specification

Features

Description

•
•
•
•
•

The XC95144 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of eight
36V18 Function Blocks, providing 3,200 usable gates with
propagation delays of 7.5 ns. See Figure 1 for the architecture overview.

•
•

•
•
•
•
•
•
•
•
•

7.5 ns pin-to-pin logic delays on all pins
fCNTto 111 MHz
144 macrocells with 3,200 usable gates
Up to 133 user I/O pins
5 V in-system programmable
Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
PCI compliant (-7, -10 speed grades)
Advanced 0.6 llm CMOS 5V FastFLASH technology
Available in 100-pin PQFP, and 160-pin PQFP
packages

June 1, 1996 (Version 1.0)

Power Management
Power dissipation can be reduced in the XC95144 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:

Icc (mA) =
MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
MCLP = Macrocells in low-power mode
MC = Total number of macrocells used

f

=Clock frequency (MHz)

3-35

I

XC95144 In-System Programmable CPLD

3
JTAG Port {

I

1

JTAG
Controller

t

I ..

I

~I

1

t

36

Function
Block 1

18

I/O

I

1

I/O
I/O

~

•
•

:2

1

~
3:

I/O
Blocks

i

I

II

(f)

I/O

IU

I/O

z
z

UJ

0

U

1

l1l

U.

lJ

+

3
36
18/

I/O/GSR
I/O/GTS

II

1

2

I

ii

Function
Block 4

/

1

tt

Macrocells
1 to 18

I/O
I/O/GCK

I

Function
Block 3

18/

(j)

I/O

Macrocells
1to 18

~

36

I

ii

Function
Block 2

18

.<::

Macrocells
1 to 18

+

36

x

I/O

•
•

I

In-System Programming Controller

Macrocells
1 to 18

I
I

~ tt
•
•
•

~

36
18/

--.J

-

1

tt

Function
Block 8

II

Macrocells
1 to 18

tt
X5922

Figure 1: XC95144 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks

3-36

June 1, 1996 (Version 1.0)

~XILINX
XC95144 1/0 Pins
Function
Block

1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2'
2
2

Macrocell

PQ100 PQ160

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

15
16
17
18
19
20

1

-

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

4
5
6

21
22

24
25
26
-

.8

9
10
11

12
13
14
-

38
21
22
25
23
24
32
26
28
74
29
30
39
33
35
78
36
3
4
147
158
6
8
7
11
12
155
13
15
5
17
18
105
19
-

BScan
Notes
Order

429
426
423
420
417
414
411

408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324

[1]
[1]

[1]

[1]
[1]

Function
Block

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

Macrocell

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ100 PQ160

27
-

29
30
31
32

34
35
36
37
38

92

93
94

95
96

97
98

99
1

3

-

53
37
84
45
42
44
48
47
49
89
54
56
55
57
58
34
59

149
143
107
123
144
145
151
146
148
114
152
154
150
156
159
14
2
-

BScan
Notes
Order

321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216

Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.

June 1, 1996 (Version 1.0)

[1]

I

[1]
[1]

XC95144 In-System Programmable CPLD

XC95144 1/0 Pins (continued)
Function
Block

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

3-38

Macrocell PQ100 PQ160

1

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

39

41
42
43
44

45
48

51
52
54
79
80
81
82
83

84
87
88
89

91
-

65
60
27
76
62
63
67
64
68
93
69
72
66
77
79
52
82
124
9
91
126
129
131
133
134
130
135
138
132
139
140
153
142
-

BScan
Notes
Order

213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108

Function
Block

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

Macrocell PQ100 PQ160

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

55
56
57
58
60
61
62
63
65
66
67

68
69
70
72
73
74
75
76
78
-

86
50
43
88
90
83
92
95
109
96
97
85
98
101
87
102
103
128
16
104
106
118
108
111
125
113
115
119
116
117
112
122
-

BScan
Notes
Order

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

June 1, 1996 (Version 1.0)

~XILINX
XC95144 Global, JTAG and Power Pins
Pin Type

PQ100

PQ160

IIO/GCK1
IIO/GCK2
IIO/GCK3
I/O/GTS1
IIO/GTS2
I/O/GTS3
IIO/GTS4
I/O/GSR

24
25
29
5
6
3
4
1
50
47
85
49
7,59,100
28,40,53,90
2,23,33,46,64,71,
77,86

33
35
42
6
8
2
4
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141
20,31,40,51,70,80,
99,100,110,120,127,
137,160

-

-

TCK

TOI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GND

No Connects

June 1, 1996 (Version 1.0)

I

3·39

XC95144ln,System Programmable CPLD

3-40

June 1, 1996 (Version 1.0)

XC95180 In-System
Programmable CPLD
August 1, 1996 (Version 1.1)

Advance Product Specification

Features

Description

•
•
•
•
•

The XC95180 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of ten
36V18 Function Blocks, providing 4,000 usable gates with
propagation delays of 10 ns. See Figure 1 for the architecture overview.

•
•

•
•
•
•
•
•
•
•
•

10 ns pin-to-pin logic delays on all pins
fCNT to 111 MHz
180 macrocells with 4,000 usable gates
Up to 166 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
- 90 product terms drive any or all of 18 macrocells
within Function Block
- Global and product term clocks, output enables, set
and reset Signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 mA outputs with 3.3 V or 5 V I/O
capability
PCI compliant (-10 speed grade)
Advanced 0.6 11m CMOS 5V FastFLASH technology
Available in 160-pin PQFP, and 208-pin HQFP
packages

August 1, 1996 (Version 1.1)

Power Management
Power dissipation can be reduced in the XC95180 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.
Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)

=

MCHP (1.7) + MCLP (0.9) + MC (0.006 mNMHz) f
Where:
MCHP
MCLP

= Macrocells in high-performance mode
= Macrocells in low-power mode

MC = Total number of macrocells used
f

= Clock frequency (MHz)

3-41

I

XC95180 In-System Programmable CPLD

3'
JTAG Port {

1

JTAG
Controller

t

,I,.

·1

1-

t

36

Function
Block 1

18

I/O

1

I/O

1

36

x

•
•
•
•

~
~

I/O
Blocks

1

£

I/O

z
z

UJ

0
0

36

1

co

LL

J

3
36

1
I/O/GTS

18/

1

2

Macrocells
1 to 18

I

Function
Block 4

/

I/O/GSR

tt

t tt

I/O
I/O/GCK

I

Function
Block 3

18

1i5

tt

Macrocells
1 to 18

~

I-

0

I/O

1

I

.~

(j)

I/O

I

Function
Block 2

18/

.c

Macrocells
1 to 18

~

I/O
I/O

I

In-System Programming Controller

.1

I

Macrocells
1 to 18

~

I

tt
•

•
•

~

36

18

1

LJ

tt

Function
Block 10

i1

Macrocells
1 to 18

I

tt
X5923

Figure 1: XC95180 Architecture
Note: Function Block outputs indicated by bold line drive directly to I/O Blocks

3-42

August 1, 1996 (Version 1.. 1)

~XILINX
XC95180 I/O Pins
Function
Block

Macrocell

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ160 HQ20B

22
23
24
25
26
27
28
29
30
32
33
34
35
36
6
7
8
9
11

12
13
14
15
16
17
18
19
21
-

39
30
31
32
33
34
40
35
36
37
38
43
41
44
45
46
47

14
7
8
9
10
15
28
16
17
18
19
20
29
21
22
23
25

-

BScan
Notes
Order

537
534
531
528
525
522
519
516
513
510
507
504
501
498
495
492
489
486
483
480
477
474
471
468
465
462
459
456
453
450
447
444
441
438
435
432

[1]
[1]

[1]
[1]

Function
Block

Macrocell

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ160 HQ20B

37
38
39
42
43
44
45
47
48
49
50
52
53
56
150
151
152
153
154

155
156

158
159
2
3
4
5
-

48
49
50
51
55
56
54
57
58
60
61
63
62
64
70
71
74
196
194
197
198
199
200
203
201
202
208
205
206
12
3
4
5
6
-

BScan
Notes
Order

429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
387
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324

[1]

I

[1]
[1]
[1]

Notes: [1] Global control pin
Macrocell outputs to package pins subject to change, contact factory for latest information. Power, GND, JTAG and Global
Signals are fixed.

August 1, 1996 (Version 1.1)

3-43

XC95180 In-System Programmable CPLD

XC951801/0 Pins (continued)
Function
Block

Macrocell

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ160 HQ208

54
55
57
58
59
60
62
63
64
65
66
67
68

72
73
75
76
77
67
78
82

83
84
80
85
86
87
88

-

-

134
135
138
139
140
142
143
144
145

169
174
175
178
179
180
183
182
185
189
186
187
195
188
191
192
193

146
147
148
149
-

-

BScan
Notes
Order

321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216

Function
BloCk

Macrocell

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

1
2
3.
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ160 HQ208

69
72
74
76
77

78
79
82
83

84
85
86
87
118
119
122
123
124
125
126
128
129
130
131
132
133
-

90
89
95
97
99
100
91
102
103
101
110
111
106
112
113
114
115

144
154
155
158
159
160
151
161
162
165
164
166
168
167
170
171
173

-

BScan
Notes
Order

213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108

August 1, 1996 (Version 1.1)

~XILINX
XC95180 I/O Pins (continued)
Function
Block

Macrocell

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

PQ160 HQ208

88
89
90
91
92
93
95
96
97
98
101
102
103
-

116
117
118
121
122
107
123
125
109
126
127
119
128
131
133
134

-

BScan
Notes
Order

Function
Block

Macrocell

10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54

PQ160 HQ208

104
105
106
107
108
109
111

112
113

114
115
116
117
-

135
136
137
138
139
120
140
145
142
146
147
143
148
149
150
152
-

BScan
Notes
Order

51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

I

XC95180 Global, JTAG and Power Pins
Pin Type

I/O/GCK1
I/O/GCK2
I/O/GCK3
IJO/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR

TCK
TDI
TOO
TMS
VCCINT 5 V
VCCIO 3.3 V/5 V
GND

No Connects

August 1, 1996 (Version 1.1)

PQi60

HQ208

44
46
55
7
9
3
5
206
98
94
176
96
11,59,124,153,204
1,26,53,65,79,92,105,
132,157,172,181,184
20,31,40,51,70,80,99, 2,13,24,27,42,52,66,
68,69,81,93,104,108,
10~ 110, 12~ 12~ 13~
160
129,130,141,156,163,
177,190,207
33
35
42
6
8
2
4
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141

3·45

XC95180 In-System Programmable CPLD

3-46

August 1, 1996 (Version 1,1)

XC95216 In-System
Programmable CPLD
August 1, 1996 (Version 1.1)

Preliminary Product Specification

Features

Power Management

•
•
•
•
•

Power dissipation can be reduced in the XC95216 by configuring macrocells to standard or low-power modes of
operation. Unused macrocells are turned off to minimize
power dissipation.

•
•

•
•
•
•
•
•
•
•
•

iOns pin-to-pin logic delays on all pins
fCNTto 111 MHz
216 macrocells with 4800 usable gates
Up to 166 user I/O pins
5 V in-system programmable
- Endurance of 10,000 program/erase cycles
- Program/erase over full voltage and temperature
range
Enhanced pin-locking architecture
Flexible 36V18 Function Block
90 product terms drive any or all of 18 macrocells
within Function Block
Global and product term clocks, output enables, set
and reset signals
Extensive IEEE Std 1149.1 boundary-scan (JTAG)
support
Programmable power reduction mode in each
macrocell
Slew rate control on individual outputs
User programmable ground pin capability
Extended pattern security features for design protection
High-drive 24 rnA outputs with 3.3 V or 5 V I/O
capability
PCI compliant (-10 speed grade)
Advanced 0.6 11m CMOS 5V FastFLASH technology
Available in 160-pin PQFP and 208-pin HQFP
packages

Description
The XC95216 is a high-performance CPLD providing
advanced in-system programming and test capabilities for
general purpose logic integration. It is comprised of twelve
36V18 Function Blocks, providing 4,800 usable gates with
propagation delays of 10 ns. See Figure 2 for the architecture overview.

Operating current for each design can be approximated for
specific operating conditions using the following equation:
ICC (mA)

=

MCHP (1.7) + MCLP (0.9) + MC (0.006 mA/MHz) f
Where:

= Macrocells in high-performance mode
=Macrocells in low-power mode
=Total number of macrocells used

MCHP
MCLP
MC
f

= Clock frequency (MHz)

Figure 1 shows a typical calculation for the XC95216
device.

600,-------,---------,

(500)

~

400~-~~~-_r-----~~

1 (360)

(340)

13
~

'0.

~

50
Clock Frequency (MHz)

100
X5918

Figure 1: Typical IcC vs. Frequency For XC95216

August 1, 1996 (Version 1.1)

3-47

XC95216 In-System Programmable CPLD

3/

JTAG Port {

JTAG

1

Controller

t

I ..
J

·1

t

t

36

Function
Block 1

18

110

I

1/0

II

36

x

•
•
•
•

~

:::E

Blocks

II

1

..g

;;:

Cf)

LU

z
z

1/0

0

g

36

I

ro

lL

II
II

1/0
36
1

J

2

IIO/GTS

Function
Block 4

18

I/O/GSR
/

Macrocells
1 to 18

t tt

3

I/O/GCK

I

Function
Block 3

18

U)

1/0

Macrocells
1 to 18

J tJ

I-

0

1/0

I

Function
Block 2

18

~

1/0

Macrocells
1 to 18

t tt

1/0
1/0

I

In-System Programming Controller

II

Macrocells
1 to 18

t tt
•
•
•
•

t tt

36

Function
Block 12

18

1

LJ

""---

I

Macrocells
1 t018

tt
X5917

Figure 2: XC95216 Architecture
Note: Function Block outputs indicated by bold line drive directly to 1/0 Blocks

3-48

August 1, 1996 (Version 1.1)

~XILINX
Absolute Maximum Ratings
Symbol
Vee
VIN
-.--;"-'--VTS
TSTG

~--

TSOL

Parameter
Supply voltage relative to GND
DC input voltage relative to GND
Voltage applied to 3-state output with respect to GND
Storage temperature
Max soldering temperature (10 ns @ 1/16 in = 1.5 mm)

Value

Units

-0.5 to 7.0

V
V
V

-0.5 to Vee + 0.5
-0.5 to Vee + 0.5
-65 to +150
+260

°C
°C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods
of time may affect device reliability.

Recommended Operating Conditions'
Symbol
VeelNT
-;-:--

Min

.-~~~

Supply voltage for output drivers for 5 V operation
Supply voltage for output drivers for 3.3 V operation
Low-level input voltage
High-level input voltage
Output voltage
Input signal transition time

Veelo
VIL
VIH
Vo
TIN
Note:

Parameter
Supply voltage for internal logic and input buffer

-~

Max

4.75
(4.5)
4.75 (4.5)
f--------.
3.0

5.25
(5.5)
5.25 (5.5)
3.6
0.80

0
2.0

VeeINT+0.5
Ve eINT + 0.5
50

0
.-

1. Numbers in parenthesis are for industrial-temperature range versions,

DC Characteristics Over Recommended Operating Conditions
Symbol
VOH

Parameter
Output high voltage for 5 V operation
Output high voltage for 3.3 V operation

VOL

Output low voltage for 5 V operation
Output low voltage for 3.3 V operation

IlL

Input leakage current

IIH

I/O high-Z leakage current

CIN

I/O capacitance

Icc

Operating Supply Current
(low power mode, active)

August 1, 1996 (Version 1.1)

Test Conditions

Min

IOH = -4.0 mA
Vee = Min
IOH = -3.2 rnA
Vee = Min
IOL = 24 rnA
Vee = Min
IOL = 10 rnA
Vee = Min
Vee = Max
VIN = GND or Vee
Vee = Max
VIN = GND or Vee
VIN =GND
f = 1.0 MHz

2.4

VI = GND, No load
f = 1.0 MHz

Max

Units
V
V

2.4
0.5

V

0.4

V

±10.0

~

±10.0

J.!A

10.0

pF

200mA

3-49

I

XC95216 In-System Programmable CPLD

AC Characteristics

Note:

1. fSYSTEM = internal operating frequency for general purpose system designs spanning multiple FBs.

Device Output (}---+------.--~

X5906

Figure 3: AC Load Circuit

3-50

August 1, 1996 (Version 1.1)

~XILINX
XC95216 I/O Pins
Function
Block

1
1
1
1

1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

Macrocell

PQ160

1
2
3
4
5
6·
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
.12
13
14
15
16

18
19
21
22
23
24

17 ..

18

August 1, 1996 (Version 1.1 )

25
26

27
28
29
30
6
7
8
9

HQ208

22
23
28
25
30
31
32
12
33
34
35
36
37
38
7
8
29
9
10

-

-

11

15
16

12

-

-

13
14
15
16

17
18
19
20
14
21

17
-

-

BScan
Order

645
642
639
636
633
630
627
624
621
618
615
612
609
606
603
600
597
594
591
588
585
582
579
576
573
570
567
564
561
558
555
552
549
546
543
540

Notes

[1]

[1]

Function
Block

3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4

Macrocell

PQ160

1
2
3
4
5
6
7
8
9
10

32
33

11

12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

34
35
36
37
38
39
42
43
44
-

152
153

154
155

HQ208

43
44
39
45
46

47
49
67
50
51

55
56
80
57

198
199
196
200
201

-

-

156
158

202
205

-

-

159
2

206
3

-

-

3
4

4
5
203
6
-

5

-

BScan
Order

537
534
531
528
525
522
519
516
513
510
507
504
501
498
495
492
489
486
483
480
477
474
471
468
465
462
459
456
453
450
447
444
441
438
435
432

Notes

[1]

[1]

I
[1]

[1]
[1]

[1]

3-51

XC95216 In-System Programmable CPLD

XC95216 1/0 Pins (continued)
Function
Block

Macrocell

PQ160

5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

45
47
48
49
50
52
53
54
55
56

3-52

57

140
142
143
144
145
146
147
148
149
150
151

-

HQ208

58
60
41
61
63

64
70
109
71
72

73
74
40
75
180
182
208
185
186

187
188
183
191
192
193
194
169
197
-

BScan
' Order

429
426
423
420
417
414
411
408
405
402
399
396
393
390
387
384
381
378
375
372
369
366
363
360
357
354
351
348
345
342
339
336
333
330
327
324

Notes

Function
Block

Macrocell

PQ160

7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

58
59
60
62
63
64
65
66
67
68

69

HQ208

76
77

54
78
82
83
84
91
85
86
87
88
48
89

-

-

126
128

162
164
143
166
167
170
171
195
173
174

-

129
130
131
132
133
134

-

-

135
138
139

175
178
189
179

-

-

BScan
Order

321
318
315
312
309
306
303
300
297
294
291
288
285
282
279
276
273
270
267
264
261
258
255
252
249
246
243
240
237
234
231
228
225
222
219
216

Notes

,

August 1,1996 (Version1.1)

~XILINX
XC95216 1/0 Pins (continued)
Function
Block

Macrocell

9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

P0160

August 1, 1996 (Version 1.1)

HQ208

-

-

72
74

95
97
101
99
100
102
103
90
110
111
112
113
62
114
147
148
144
149
150
152
154
168
155
158
159
160
165
161
-

76
77
78
79
82
83
84
85
86
113
114
115
116
117
118
119
122
123
124

125

-

BScan
Order

213
210
207
204
201
198
195
192
189
186
183
180
177
174
171
168
165
162
159
156
153
150
147
144
141
138
135
132
129
126
123
120
117
114
111
108

Notes

Function
Block

Macrocell

PQ160

HQ208

BScan
Order

11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

87
88
89
90

115
116
119
117
118
121
122
107
123
125
126
127
120
128
131
133
106
134
135
136
137
151
138
139
140
145
142
146
-

105
102
99
96
93
90
87
84
81
78
75
72
69
66
63
60
57
54
51
48
45
42
39
36
33
30
27
24
21
18
15
12
9
6
3
0

91
92
93
95
96
97
98
101
102
103
104
105
106
107
108
109
111
112
-

Notes

I

3-53

XC95216 In-System Programmable CPLD

XC95216 Global, JTAG and Power Pins
Pin Type

PQ160

HQ208

I/O/GCK1
I/O/GCK2
I/O/GCK3
I/O/GTS1
I/O/GTS2
I/O/GTS3
I/O/GTS4
I/O/GSR
TCK
TDI

33
35
42
6
8
2
4
159
75
71
136
73
10,46,94,157
1,41,61,81,121,141

44
46
55
7
9
3
5
206
98
94
176
96
11,59,124,153,204
1,26,53,65,79,92,105,132,
157,172,181,184
2,13,24,27,42,52,66,68,69,
81,93,104,108,129,130,141,
156,163,177,190,207

TOO
TMS

VCCINT5V
VCCIO 3.3 V/5 V

3-54

GND

20,31,40,51,70,80,99,100,
110,120,127,137,160

No Connects

-

-

August 1, 1996 (Version 1.1)

~XILINX
Ordering Information

1T

XC95216· 10 PO 208 C

De_ Speed

-=r T
~.

I

Tempe--+-------------------------------------------------------------------,
12 from Fast
Input Pins

24
Inputs from
UIM

Sum-af-Products
from

I
Input-Pad
Register/Latch
(optional)
(XC73144 only)

Fe~~b~~ --+-----------------------------------1-----------------------------'
Sum-af-Products to
Succeeding Macrocell
Pin Fe~~b~~ __- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -__- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
X5725

Figure 2: Fast Function Block and Macrocell Schematic for the XC7318, XC7336, and XC73144
2 Global
Fast OE

-L::>__~----------------------------------------------------------------____,

12 from Fast
Input Pins

24
Inputs from
UIM

Sum-af-Products
from

9 from FF8
Macrocell
Feedback

9

Input-Pad
Register/Latch
(optional)
(XC7354 only)

Pin

+ ________________________________-+__________________________---'

Fe~~b~~~

...

Fe~~b~~

Sum-at-Products to
Succeeding Macrocell
...__________________________________________________________

==c:....::='-______-'

X5761

Figure 3: Fast Function Block and Macrocell Schematic for the XC7354, XC7372, and XC73108

June 1, 1996 (Version 1.0)

3-73

XC7300 CMOS CPLD Family

Product Term Assignment
Each macrocell sum-of-product OR gates can be expanded
using the FFB product term assignment scheme. Product
term assignment transfers product terms in increments of
four product terms from one macrocell to the neighboring
macrocell (Figure 4). Complex logic functions requiring up
to 36 product terms can be implemented using all nine
macrocells within the FFB. When product terms are
assigned to adjacent macrocells, the product term normally
dedicated to the Set or Reset function becomes the input to
the macrocell register.
From Previous
Macrocell

Global
Clocks

Single-ProductTerm As

nment

configured for either registered or combinatorial logic. A
detailed block diagram of the FB is shown in Figure 5.
Each FB receives 21 signals and their complements from
the UIM and an additional three inputs from the Fast Input
(FI) pins.

Shared and Private Product Terms
Each macrocell contains five private product terms that can
be used as the primary inputs for combinatorial functions
implemented in the Arithmetic Logic Unit (ALU), or as individual Reset, Set, Output-Enable, and Clock logic functions
for the flip-flop. Each FB also provides an additional 12
shared product terms, which are uncommitted product
terms available for any of the nine macrocells within the FB.
Four private product terms can be ORed together with up to
four shared product terms to drive the D1 input to the ALU.
The D2 input is driven by the OR of the fifth private product
term and up to eight of the remaining shared product terms.
The shared product terms add no logic delay, and each
shared product term can be connected to one or all nine
macrocells in the FB.

Eight-ProductTerm Assignment

SIR

h'--J~f--=:jT)-t+-~ OfT

The functional versatility of each macrocell in the FB is
enhanced through additional gating and control functions
available in the ALU. A detailed block diagram of the
XC7300 ALU is shown in Figure 6.
The ALU has two programmable modes; logic and arithmetic. In logic mode, the ALU functions as a 2-input function generator using a 4-bit look-up table that can be
programmed to generate any Boolean function of its D1
and D2 inputs as illustrated in Table 1.

Q

X5220

Figure 4: Fast Function Block Product Term Assignment

High-Density Function Blocks
The XC7354, XC7372, XC73108 and XC73144 devices
contain multiple, High-Density FBs linked though the UIM.
Each FB contains nine macrocells. Each macrocell can be

3-74

Arithmetic Logic Unit

The function generator can OR its inputs, widening the OR
function to a maximum of 17 inputs. It can AND them, which
means that one sum-of-products can be used to mask the
other. It can also XOR them, toggling the flip-flop or comparing the two sums of products. Either or both of the sumof-product inputs to the ALU can be inverted, and either or
both can be ignored.

June 1, 1996 (Version 1.0)

~XILINX

21
Inputs
from
UIM

3

Feedback
Enable

from
Fast
Inpu1
Pins

Override

(FI)

4

I
To 8 More
Macrocells

Arithmetic
Carry-Out to Next

" DE is forced high when P-term is not used

Macrocell

X5485

Figure 5: High-Density Function Block and Macrocell Schematic
Table 1: Function Generator Logic Operations
Function
01:+: 02

01:+: 02

01 * 02

01 * 02

01 + 02

01 + 02

01

02

01

02

01 * 02

01 * 02

01 + 02

01 + 02

In arithmetic mode, the ALU block can be programmed to
generate the arithmetic sum or difference of the 01 and 02
inputs. Combined with the carry input from the next lower
macrocell, the ALU operates as a 1-bit full adder generating
a carry output to the next higher macrocell. The carry chain
propagates between adjacent macrocells and also crosses
the boundaries between FBs. This dedicated carry chain
overcomes the inherent speed and density problems of the
traditional CPLO architecture when trying to perform arithmetic functions.

Carry Lookahead

Carry Output

D1

p~g~:t~ +--t-~
D2
Sum-ofProducts

+-.0.-----11-._ _.......1

Therefore, the ALU can implement one additional layer of
logic without any speed. penalty,

To Macrocell
Flip-Flop

Each FBprovides a carry lookahead generator capable of
anticipating the carry across all nine macrocells. The carry
lookahead generator reduces the ripple-carry delay of wide
arithmetic functions such as add, subtract, and magnitude
compare to that of the first nine bits, plus the carry lookahead delay of the higher-order FBs.

Macrocell Flip-Flop
X3206

Figure 6: ALU Schematic

June 1, 1996 (Version 1.0)

The ALU block output drives the input of a programmable
Ootype flip-flop. The flip-flop is triggered by the rising edge
of the clock input, but it can be configured as transparent,

3-75

XC7300 CMOS CPLD Family

making the Q output identical to the D input, independent of
the clock, or as a conventional flip-flop.
The macrocell clock source is programmable and can be
one of the private product terms or one of two global FastClK signals (FClKO and FClK1). Global FastClK signals
are distributed to every macrocell flip-flop with short delay
and minimal skew.
The asynchronous Set and Reset product terms override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set.
In addition to driving the chip output buffer, the macrocell
output is routed. back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output buffer and/or the feedback to the UIM.
If it is configured to control UIM feedback, the Output
Enable product term forces the UIM feedback line High
when the macrocell output is disabled.

Universal Interconnect Matrix
The UIM receives inputs from each macrocell output, I/O
pin, and dedicated input pin. Acting as fully connected
crossbar switch, the UIM generates 21 output signals to
each FB and 24 output signals to each FFB.

Each UIM input can be connected to any UIM output. The
UIM delay is constant, regardless of the routing distance,
fan-out, or fan-in.
When multiple UIM inputs are connected to the same output, their wire-AND is formed by using internally available
inversions. This AND logic can also be used to. implement
wide NAND, OR or NOR functions. T.his offers an additional
level of logic without any speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Programming several such macrocell outputs onto the
same UIM output emulates a 3-state bus line. If one of the
macrocell outputs is enabled, the UIM output assumes the
enabled output's level.

Input/Output Blocks
Macrocells drive chip outputs directly through 3-state output buffers, each individually controlled by the Output
Enable product term mentioned above. The macrocell output can be inverted. An additional configuration option
allows the output to be disabled permanently. Two dedicated FastOE inputs can also be configured to control any
of the chip outputs instead of, or in conjunction with, the
individual Output Enable product term. See Figure 7.
Fast OED
FastOE1

FCLKlO. CKENIO
FOEIO
Pins Only

~----~;'lJOPin

--<=:J
--<=:J
ToUIM

CKENO
CKEN1

.....-,.-----~

To Function Block
AND-Array (on

Fastlnput - - - - - - -

FastCLKO

Pins Only)
FastCLK1

Input and
110 Pins Only

FastCLK2

X5463

Figure 7: Input/Output SchematiC (except XC7318IXC7336 which do not include I/O flip-flops)

3-76

June 1, 1996 (Version 1.0)

~XILINX
Output buffers, except those connected to FFBs, can sink
12 mA when Vcc/o = 5 V. FFB outputs can sink 24 mA
when Vcc/o =5 V.

is brought high after tWMR ' but before tRESET' the outputs
will become active after tRESET' It is essential that the MR
pin remain static during power on reset (tRES ET )'

Each signal input to the chip is connected to a programmable input structure that can be configured as direct, latched,
or registered. The latch and flip-flop can use one of two
FastClK signals as latch enable or clock. The two FastClK
signals are FClKO and a global choice of either FClK1 or
FClK2. latches are transparent when FastClK is High,
and flip-flops clock on the rising edge of FastClK. The flipflop includes an active-low clock enable, which when High,
holds the present state of the flip-flop and inhibits response
to the input signal. The clock enable source is one of two
global Clock Enable signals (CEO and CE1). An additional
configuration option is polarity inversion for each input signal.

During the initialization sequence, all input registers or
latches are preloaded High and all FB and FFB macrocell
registers are preloaded to a known state. For FFB macrocell registers where the Set/Reset product term is defined,
the preload is accomplished by asserting the product term
shortly before the end of the initialization sequence. When
the Set/Reset product term is configured as Reset, the register preload value is Low. When the Set/Reset product
term is configured as Set, the register preload value is
High. For FFB macrocell registers where the Set/Reset
product term is not used, the register preload value is High.

3.3 V or 5 V Interface Configuration
XC7300 devices can be used in systems With two different
supply voltages: 3.3 V and 5 V. Each XC7300 device has
separate Vcc connections to the internal logic and input
buffers (V CC /NT) and to the 1/0 drivers (Vcc/o). VCC/NT must
always be connected to a nominal 5 V supply, while Vcc/o
may be connected to either 3.3 V or 5 V, depending on the
output interface requirement.
When VCc/o is connected to 5 V, the input thresholds are
TTL levels, compatible with 3.3 V and 5 V logic. The output
High levels are also TTL compatible. When Vcc/o is connected to 3.3 V, the input thresholds are still TTL levels, and
the outputs pull up to the 3.3 V rail. This makes the XC7300
family ideal for interfacing directly to 3.3 V components. In
addition, the output structure is designed so the 1/0 can
also safely interface to a mixed 3.3 V and 5 V bus.

Power-On Characteristics/Master
Reset
Each XC7300 device undergoes a short internal
initialization sequence upon device powerup. During this
time (tRESET), the outputs remain 3-stated while the device
is configured from its internal EPROM array and all
registers are initialized. If the MR pin is tied to VCC/NT, the
initialization sequence is completely transparent to the user
and is completed in tRESET after V CC/NT has reached 4.75
V. If MR is held low while the device is powering up, the
internal initialization sequence begins and outputs will
remain 3-stated until the sequence is complete and MR is
brought High. VCC rise must be monotonic to ensure the
initialization sequence is performed correctly.
For additional flexibility, the MR pin is provided so the
device can be reinitialized after power is applied. On the
falling edge of MR, all outputs become 3-stated and the initialization sequence begins. The outputs remain 3-stated
until the internal initialization sequence is complete and MR
is brought High. The minimum MR pulse with is tWMR' If MR

June 1, 1996 (Version 1.0)

For FB macrocell registers, the preload value is defined by
a separate preload configuration bit, independent of the Set
and Reset product terms. The value of this preload configuration bit may be determined by the user. If unspecified,
the register preload value is Low.

Power Management
The XC7300 family features a power-management scheme
permitting non-speed-critical paths of a design to be operated at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a small
portion is speed critical.
Macrocells can individually be specified for high performance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To further reduce power dissipation, unused
FBs are turned off and unused macrocells in used FBs are
configured for low power operation.

Erasure Characteristics
In windowed packages, the EPROM array can be erased by
exposure to UV light with wavelengths of approximately
4000 A. The recommended erasure time is approximately 1
hr. when the device is placed within 1 in. of an UV lamp with
12,000 ',LW/cm2 power rating. To prevent unintentional
exposure, place opaque labels over the device window.
When the device is exposed to high intensity UV light for
much longer periods, permanent damage can occur. The
maximum integrated dose the XC7300 CPLDs can be
exposed to without damage is 7000 W' s/cm 2 , or approximately one week at 12,000 ',LW/cm2.

Design Recommendations
For proper operation, all unused input and 110 pins must be
connected to a valid logic level (High or Low). The recommended decoupling for all VCC pins should total 1 ',LF using
high-speed (tantalum or ceramic) capacitors.

3-77

I

XC7300 CMOS CPLD Family

Use electrostatic discharge (ESD) handling procedures
with the XC7300 CPlDs to prevent damage to the device
during programming, assembly, and test.

Design Security
Each member of the XC7300 family has a multibit security
system that controls access to the configuration programmed into the device. This security scheme uses multiple EPROM bits at various locations within the EPROM
array to offer a higher degree of design security than other
EPROM and fused-based devices. Programmed data
within EPROM cells is invisible-even when examined
under a microscope-and cannot be selectively erased. The
EPROM security bits, and the device configuration data,
reset when the device is erased.

High-Volume Production
Programming
The XC7300 family is available as a factory programmed
product. For factory programming procedures, contact your
local Xilinx representative.

3-78

XACTstep Development System
The XC7300 CPlD family is fully supported by the Xilinx
XACTstep development system. The designer can create
the design using ABEL, schematics, equations, VHDl or
other HDl languages in a variety of software front-end
tools. The XACT step development system can be used to
implement the design and generate a bitmap which can be
used to program the XC7300 devices.

Timing Model
Timing within the XC7300 family is accurately determined
using external timing parameters from the device data
sheet, a variety of CAE simulators, or with the timing model
shown in Figure 8.
The timing model is based on the fixed internal delays of
the XC7300 architecture which consists of four basic parts:
1/0 Blocks, the UIM, FFBs and FBs. The timing model identifies the internal delay paths and their relationships to ac
characteristics. Using this model and the ac characteristics,
designers can calculate the timing information for a particular device.

June 1, 1996 (Version 1.0)

~:XILINX

tSUI
teol

1,110

@-

tpOI

'HI
tAOI

CE

I
FCLK

D-------
liFO
liFO
liFO
liFO
I
IIFI

MC1-9

IIFI
IIFI

June t,1996 (Version 1.0)

VCCINT

I

PQ44
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

PC44
23
24
25
_ 26
27
28
29

35
36
37

30
31
32
33
34
35
36
37
38
39
40
41
42
43

38

44

Input

XC7318

Output

GND
I
1
I
I
IIFI
liFO
liFO

-:

0

:

MC2·9
MC2-8

GND
V CC10

liFO

MC2-7
MC2-6
MC2-5
MC2-4
MC2-3
MC2-2
MC2-1

lIFO
liFO
liFO
liFO
liFO
FOE1/FO
FOEO
VCCINTNpp

IIFI
IIFI
11Ft

3- 87

XC731818-Macrocell CMOS CPLD

Ordering Information

1L

XC7318 - 5 PC 44 C

Dev~ T~J
Speed·

..
L--_

Temperatuffi Range

Number of Pins
Package Type

Speed Options

-7
-5

7.5 ns pin-to-pin delay (commercial only)
5 ns pin-to-pin delay (commercial only)

Packaging Options
44-Pin Plastic Leaded Chip Carrier
44-Pin Plastic Quad Flat Pack

PC44
PQ44

Temperature Options

C

Commercial

Component Availability
Pins

44
Plastic
PLCC

Type
Code
XC7318

1-7
1-5

PC44
C
C

Plastic
. PQFP
PQ44
C
C

C = Commercial = 0° to +70°C

3- 88

June 1, 1996 (Version 1.0)

XC7336IXC7336Q
36-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

General Description

•

The XC7336 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like
24V9 Fast Function Blocks interconnected by the 100%populated Universal Interconnect Matrix (UIMTM). See
Figure 1 for the architecture overview.

•
•
•
•
•
•

•
•
•
•

Ultra high-performance Complex Programmable Logic
Devices (CPLDs)
- 5 ns pin-to-pin speeds on all fast inputs
- Up to 167 MHz maximum clock frequency
New low power XC7336Q
100% PCI compliant
High-drive 24 mA output
I/O operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
Multiple security bits for design protection
Incorporates four PAL-like 24V9 Fast Function Blocks
0.8!1 CMOS EPROM technology
Available in 44-pin VQFP, PQFP and PLCC/CLCC
packages

The XC7336 is designed in 0.8 !1 CMOS EPROM technology, in speed grades ranging from 5 to 15 ns. The
XC7336Q is also available now, providing lower power consumption in -10, -12 and -15 ns speed grades.

PQ44

PC44

PC44

PQ44

j

j

j

j

22

28

IIFI

42

36

29
30
33
34
35
36
37
38
39

23
24
27
28
29
30
31
32
33

40
43
44
1

34
37
38
39
40
41
42
43
44

IIFI

19
12

FFBl

1
2
3
5
6
7
8
9
10

7
8
9
11
12
13
14
15
16

IIFOIFI
liFO

f-/

MCH

P

MC1·2

liFO

MC1·3

f-/

MC1-4

liFO

p

MC1·5

liFO

f-/

MC1·6

liFO

'--'

MCl-?

liFO

r-'

MC1·8

liFO

liFO

,........,

,.
""
"""z
a:
a:

""

MC1·9
9

Kts:

MC4·1

liFO
liFO
liFO
liFO
liFO

I/FO/FI
I/FOIFI
I/FO/FI
liFO

MC4·2
MC4-3
~

r--"

FFB2

-

12

bd}
12
3

9

9

[if

IUl
UIM

MC4-7

~

MC4-8

-

MC4·9
9

liFO
lIFO

MC2·7
MC2·6

'----'-----

liFO

liFO

MC2·5

'-----

MC2-4

'-----

liFO
liFO

MC2·3

'-----

liFO

MC2·2

'-----

MC2·1

liFO
FO/FOEl

Kts:

FFB3

~

12

12

MC3·9

FO/FOEO

MC3·8

I/FO/FI
I/FO/FI

Me3-?

MC3·6
3

3

MC4·6
~

'----'-----

12

MC4·4
MC4·5

,.
""a:a:
"""z
""

MC2·9
MC2-8

9

12

27
26
25
24
22
20
19
18
17

15
12

3

FFB4

21
20
19
18
16
14
13
12
11

J:.

MC3·5

I'--I'---

MC3·4
9

9

~

[if

MC3·3

'---

I/FO/FI/MR
I/FO/FI
I/FO/FI
I/FO/FI

MC3·2

FO/FCLKO

MC3·1

FO/FCLKl

2
3
4
5
6

9

'---

X5452

Figure 1: XC7336 Architecture

June 1, 1996 (Version 1.0)

3- 89

I

XC7336IXC7336Q 36-Macrocell CMOS CPLD

Power Estimation
Figure 2 shows a typical power .estimation for the XC7336
and the XC7336Q device, programmed as two 16-bit
counters and operating at the indicated clock frequency.

200

o

50

100

Clock Frequency (MHz)

X5085

Figure 2: Typical Icc vs. Frequency for XC7336

Absolute Maximum Ratings
. -

Symbol

Parameter

Vcc

Supply voltage with respect to GND

VIN
V TS
T8TG

Storage temperature

TSOL

Maximum soldering temperature (lOs

Value

Units

-0.5 to 7.0

V

DC Input voltage with respect to GND

-0.5 to Vcc +0.5

V

Voltage applied to 3-state output with respect to GND

-0.5 to Vcc +0.5

V

-65 to.. + 150
...

°C

+250

°C

@

1/16 in.

~

= 1.5 mm)

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Expos\.Ire to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol
VCCINT
VCCIO
V CCIO

3- 90

Parameter

Min

Max

Units

= O°C to 70°C

4.75

5.25

V

Industrial T A =-40°C to 85°C
110 supply voltage relative to GND

4.50

5.50

V

3.0

3.60

V

Supply voltage relative to GND Commercial

TA

Supply voltage relative to GND

V IL
V IH

Low-level input voltage

0

0.80

V

High-level input voltage

2.0

V

Vo

Output voltage

VCC +0.5
VCCIO

V

TIN

Input signal transition time

50

ns

0
. -

I

--

June 1, 1996 (Version 1.0)

~:XIUNX
DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter

Test Conditions

Min

Max

Units

5 V TTL High-level output voltage

IOH = -4.0 mA
Vee = Min

2.4

V

3.3 V High-level output voltage

IOH = -3.2 mA
Vee = Min

2.4

V

5 V TTL Low-level output voltage

IOl = 24 mA
Vee = Min

0.5

V

3 . 3 V Low-level output voltage

IOl = 24 mA
Vee = Min

0.4

V

±10.0

itA

±10.0

itA

6.0

pF

VOH

VOL

III

Input leakage current

loz

Output high-Z leakage current

CIN

Input capacitance for Input and I/O
pins

Vee =.Max
V IN = GND or Veelo
Vee = Max
V IN = GND or Veelo
V IN = GND
f = 1.0 MHz

CIN

Input capacitance for global control
pins (FCLKO, FCLK1, FOEO, FOE1)

V IN = GND
f = 1.0 MHz

8.0

pF

CIN

Input capacitance for Fast Inputs

V IN = GND
f=1.0MHz

12.0

pF

Output capacitance

V IN = GND
f = 1.0 MHz

10.0

pF

COUT

lee

1

2

(Non Q)

Supply current

(Q)
Notes:

V IN = Vee or GND
VeelNT = Veelo = 5V
f = 1.0 MHz @ 25°C

.

126 Typ

mA

55Typ

1. Sample tested.
2. Measured with device programmed as two 16-bit counters.

Power-up/Reset Timing Parameters
Symbol
tWMR
tRESET

Parameter
Master Reset input Low pulse width
Configuration completion time

Min
100

Typ

Max

Units
ns

80

160

its

Figure 3: Global Reset Waveform

June 1, 1996 (Version 1.0)

3-.91

I

XC7336IXC7336Q 36-Macrocell CMOS CPLD

Fast Function Block (FFB) External AC Characteristics
XC7336-5

Symbol
tpo

Parameter
Fast input to output valid

Min

tsu

Max

XC7336-10

XC7336-12

XC7336-15

Min

Min

Min

7.5
12.0

Max
10.0
15.0

Max
12.0
19.0

Max Units
15.0

ns

23.0

Fast input setup time before FCLK

4.5

5.0

5.0

6.0

7.0

ns
ns

I/O or input setup time before FCLK

7.0

8.5

10.0

13.0

15.0

ns

0

0

0

0

0

--

Fast Function Block

Pin

X5221

Figure 6: XC7336 Timing Model

Timing Model
Timing within the XC7336 is accurately determined using
external timing parameters from the device. data sheet,
using a variety of CAE simulators, or with the timing model
shown in Figure 6.
The timing model is based on the fixed internal delays of
the XC7336 architecture that consists of three basic parts:

June 1, 1996 (Version 1.0)

1/0 Blocks, the UIM and Fast Function Blocks. The timing
model identifies the internal delay paths and their relationships to ac characteristics. Using this model and the ac
characteristics, designers can easily calculate the timing
information for the XC7336.

3- 93

XC7336IXC7336Q 36-Macrocell CMOS CPLD

Fast Function Block (FFB) Internal AC Characteristics
~-

XC7336-5

Parameter

Symbol
tFLOGI
tFLOGILP
tFSUI
tFHI
tFCOI
t FPOI
tFAOI
tpTXI
tFFO

FFB logic array delay
Low-power FFB logic array delay 1
FFB register setup time
FFB register hold time
FFB register clock-to-output delay
FFB register pass through delay
FFB register async. set delay
FFB p-term assignment delay
FFB feedback delay

Min

Max

XC7336-7

Min

Max

XC7336-10

XC7336-12

XC7336-15

Min

Min

Min

Max

Max

Max Units

1.0

1.5

1.5

2.0

2.0

ns

2.0

3.5

5.5

7.0

8.0

ns

2.5

1.5

2.5

3.0

4.0

1.0

2.5

2.5

3.0

3.0

ns
ns

1.0

1.0

1.0

1.0

1.0

ns

0.5

0.5

0.5

1.0

1.0

ns

2.0

2.0

2.5

3.0

4.0

ns

0.6

0.8

1.0

1.2

1.5

ns

0.5

4.0

5.0

6.5

8.0

ns

XC7336Q-10 XC7336Q-12 XC7336Q-15

Symbol

Parameter

tFLOGI

FFB logic array delay

tFLOGILP

Low-power FFB logic array delay

tFSUI

FFB
FFB
FFB
FFB
FFB
FFB
FFB

tFHI
tFCOI
t FPOI
t FAOI
t pTXI
tFFO
Note:

Min

1

Max

Min

Max

Min

Max Units

3.0

3.0

2.0

ns

5.5

7.0

8.0

ns

register setup time

2.5

3.0

4.0

register hold time

2.5

3.0

3.0

ns
ns

register clock-to-output delay

1.0

1.0

1.0

ns

register pass through delay

0.5

1.0

1.0

ns

register async. set delay

2.5

3.0

4.0

ns

p-term assignment delay

1.0

1.2

1.5

ns

feedback delay

5.0

6.5

8.0

ns

1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

Internal AC Characteristics
XC7336-5

Symbol

Parameter

Min

Max

XC7336-7

Min

Max

XC7336-10

XC7336-12

XC7336-15

Min

Min

Min

Max

Max

Max Units

tiN

Input pad and buffer delay

1.5

2.5

3.5

4.0

5.0

ns

tFOUT

FFB output buffer and pad delay

2.0

3.0

4.5

5.0

7.0

ns

tUIM

Universal Interconnect Matrix delay

3.5

4.5

5.0

7.0

8.0

ns

tFCLKI

Fast clock buffer delay

1.5

1.5

2.5

3.0

4.0

ns

XC7336Q-10 XC7336Q-12 XC7336Q-15

Symbol

Parameter

Min

Max

Min

Max

Min

Max Units

tiN

Input pad and buffer delay

3.5

4.0

5.0

ns

tFOUT

FFB output buffer and pad delay

3.0

4.5

7.0

ns

tUIM

Universallnt.erconnect Matrix delay

5.0

7.0

8.0

ns

tFCLKI

Fast clock buffer delay

2.5

3.0

4.0

ns

3-.94

June. t, 1996 (version 1.0)

~XILINX
Combinational Switching Characteristics
--tIN-

Input, I/O Pin
--tUIM-

UIM Delay

----

-

tLOGI
tFLOGI

Logic Delay

---

P-Term
Assignment
Delay

--

tpTXI

----

Transparent
Register
Delay

I

tpDI
tFPDI

---

1tOUT
tFQUT

I-

Output Buffer

Output Pin
X3339

Asynchronous Switching Characteristics

INPUT, I/O Pin

INPUT, I/O DELAY

I

--.:
UIM DELAY

I

\
tUIM

/
~

---..-:

!

\
t LOOI

CLOCK at
REGISTER

/

\

:...--.:

tSUI

tCOI

:-

________________
----+-:

REGISTER to
OUTPUT Pin

June 1, 1996 (Version 1.0)

!

\~----

~~--------~~~----

~
---....!

REGISTER to
UIM

\

~

tHI

DATA from
LOGIC ARRAY

\

:-

tUIM

-.:

:.tAOI:
....'-.- t UIM!
-.'
,

X

L -_ _ _ _ _ _ _ _ _ _ _ _

touT

~

C

~--~

~ tOUT---"i

~r_~~~~~~~~~=====r=
X3580

3- 95

XC7336IXC7336Q 36-Macrocell CMOS CPLD

Synchronous SWitching Characteristics
FCLK Pin
tSUIN

tsue EI~,-+

----.1,--

DatafCE at Input
1/0 Register

-

~,-

I--

tHIN
lLtHCEIN

~
-

tC~I__
...-tUIM

Input, I/O Register

toUIM
tFCLKI

-+

Fast Clock
Input Delay

1-I

?'-.'

Data at Input
1/0 Pin

DtlN

r-

---..

tUIM

tlOGI
tFLOGI

Data at Input
Register

\

\

---

-

tHI

tSUI

-I

tFSUI

tFHI

X

"I

_ _ _E=
tCOI

I.

tOUT
• tFOUT

tFCCI

Register to

Output Pin

X3494

XC7336 Pinouts
VQ44/PQ44

PC44

Input

XC7336

Output

VQ44/PQ44

PC44

39

1

IIFO/FI

MR

MC3-6

17

23

40

2

I/FO/FI

MC3-5

18

24

liFO

MC4-4

41

3

IIFO/FI

MC3-4

19

25

liFO

MC4-3

42

4

IIFO/FI

MC3-3

20

26

liFO

MC4-2

43

5

FO/FCLKO

MC3-2

21

27

liFO

MC4-1

44

6

FO/FCLK1

MC3-1

22

28

IIFI

Input

Output

GND

1

7

I/FO/FI

MC1-1

23

29

liFO

2

8

liFO

MC1-2

24

30

liFO

3

9

liFO

MC1-3

25

31

MC2-9
MC2-8
GND

4

10

26

32

5

11

liFO

MC1-4

27

33

liFO

MC2-7

6

12

liFO

MC1-5

28

34

liFO

MC2-6

7

13

liFO

MC1-6

29

35

liFO

MC2-5

8

14

liFO

MC1-7

36

liFO

MC2-4

9

15

liFO

MC1-8

30
31

37

liFO

MC2-3

10

16

liFO

MC1-9

32

38

liFO

MC2-2

11

17

liFO

MC4-9

33

39

FO/FOE1

MC2-1

12

18

I/FO/FI

MC4-8

34

40

FO/FOEO

MC3-9

13

19

IIFOIFI

MC4-7

35

41

14

20

IIFOIFI

MC4-6

36

42

I/FI

15

21

37

43

IIFO/FI

MC3-8

16

22

38

44

I/FO/FI

MC3-7

3- 96

GND

XC7336

VCCINT
liFO

MC4-5

VCCIO

VCCINTNpp

June 1, 1996 (Version 1.0)

~XILINX
Ordering Information

TJ -lL

XC7336 Q - 5 PC 44 C

~

DeViCeTy:T
Power Option

Speed

Temperature Range

Number of Pins
'----- Package Type

Power Options
Q

Packaging Options

Low Power -10, -12, -15 speeds

Speed Options
-15
-12
-10
-7
-5

15 ns pin-to-pin delay
12 ns pin-to-pin delay
iOns pin-to-pin delay
7.5 ns pin-to-pin delay (commercial only)
5 ns pin-to-pin delay (commercial only)

PC44 44-Pin Plastic Leaded Chip Carrier
WC44 44-Pin Windowed Ceramic Leaded
Chip Carrier
PQ44 44-Pin Plastic Quad Flat Pack
VQ44 44-Pin Thin Quad Pack

I

Temperature Options
C

CommercialO°C to 70°C
Industrial-40°C to 85°C

Component Availability
Pins
Type

44

Code

XC7336

XC7336Q
C = Commercial

-15
-12
-10
-7
-5
-15
-12
-10

Plastic
PLCC
PC44
CI
CI
CI
C
C
CI
CI
C

= 0° to +70°C

June 1, 1996 (Version 1.0)

Ceramic
CLCC
WC44
CI
CI
CI
C
C
CI
CI
C

Plastic
PQFP
PQ44
CI
C
C
C
C
C
C
C

Plastic
VQFP
VQ44

C
C
C

I = Industrial = -40° to 85°C

3- 97

XC7336IXC7336Q 36-Macrocell CMOS CPLD

3- 98

June 1,1996 (Version 1.0)

XC7354
54-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

Operating current for each design can be approximated for
specific operating conditions using the following equation:

•

•
•
•
•
•

•

•
•
•
•
•
•

•
•

High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
100% PCI compliant
18 outputs with 24 mA drive
1/0 operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1 A) for 3.3 V ±0.3 V
100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 61 MHz 18-bit accumulators
Multiple independent clocks
Up to 54 inputs programmable as direct, latched, or
registered
Power management options
Multiple security bits for design protection
54 macrocellswith programmable 1/0 architecture
Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 4 High-Density Function Blocks
0.8 Ii CMOS EPROM technology
Available in 44-pin and 68-pin PLCC and CLCC
packages

Icc (mA)=MC HP (3.0) + MC LP (2.6) +
MC (0.006 mA/MHz) f
Where:
MCHP = Macrocells in high-performance mode
= Total number of macrocells used
= Clock frequency (MHz)

Figure 1 shows a typical power calculation for the XC7354
device, programmed as three 16-bit counters and operating
at the indicated clock frequency.
200

150

--

High pe ormance

-

Low power

~

.S-

° 100

_0
(ii
()

'0.

~
50

General Description
The XC7354 is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and four High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIMTM).

I

MC LP = Macrocelis in low-power mode
MC
f

0

I
I
I
50
Clock Frequency (MHz)

100
X5286

Figure 1: Typical Icc vs. Frequency for XC7354

Power Management
The XC7354 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed pritical.
Macrocells can individually be specified for high performance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocelis in used
Function Blocks are configured for low power operation.

June 1, 1996 (Version 1.0)

3- 99

XC7354 54-Macrocell CMOS CPLD

PC44

PCBS

I

I

43
42
28

67
65
,43

PC6S PC44

IIFI
IIFI
IIFI

r----r----r-----

4
9
11

12
13
14
15
16

liFO
liFO
liFO
liFO
liFO
liFO
liFO

MC1-1

liFO

MC1-8

liFO

MCl-9

MCl-2
MCl-3
MCl-4
MC1-S
MCl-6
MCl-7

~

>a:
a:

MC2-9

~

a:
a:

~

""z
"

rot If

20

IIOIFI
OIFCLKO
OIFCLKl
0lFCLK2
IIOIFI
IIOIFI
IIOIFI
IIOIFI

32
33
35
37
16
18
25
31
36

1/0
1/0
1/0
1/0
1/0
1/0
IIOIFI
IIOIFI
IIOIFI

IIOIFI

MC6-1
MC6-2
MC6-3
MC6-4
MC6-S
MC6-6
MC6-7
MC6-8
MC6-9

JJ

17
22
24

MCS-l
MC5-2
MC5-3
MC5-4
MCS-5
MCS-6
MeS-?

MCS-8
MCS-9

l~

46
48
51
52
55
56
57
58
66

IIOIFI
IIOIFI
IIOIFI
OIFOEl
OIFOEO
OICKENl
OICKENO

47
45
44
64
62
61
60

39

IIOIFI
IIOIFI
IIOIFI

42
40
39

27
26
25

1/0
1/0
1/0

54
53
38

3
4
7

MC2·2

29
30
33

34
35
36
37
38

9
18
18

18

27
28
8
9
10
29
6
24
26

MC2-8
MC2-7
MC2-6
MC2-S
MC2-4
MC2-3
MC2-1

24

18
19
5
6

liFO
liFO
liFO
liFO
liFO
liFO
liFO
liFO
liFO

1

2
3
5
11

FF82

h»

"
""z I~
"

9

((

44
1
2

12

12J:

FFBl

12
13
15
17
19
21
22
23

I

68

6

6

8

I
IIFI
IIFIIMR
IIFI
IIFI
IIFI
IIFI

Arithmetic

Carry

Serial

Shift

FBB

FB3

UIM

>-

~

"a:a: I~
""z

a:

!----4- "a:
"z

"

"

FB4

FBS

~
a:

a:

""z
"

~

a:

!----4- "a:
"z
"

I~

-

Serial Shift
Arithmetic Carry

II

MC3-9
MC3-8
MC3-7
MC3-6
MC3-5
MC3-4
MC3-3
MC3-2
MC3-l

!!

MC4-9
MC4-8
MC4-7
MC4-6
MC4-S
MC4-4
MC4-3
MC4-2
MC4-l

))

-

40

X5458

Figure 2: XC7354 Architecture

3- 100

June 1, 1996 (Version 1.0)

~XILINX
Absolute Maximum Ratings
Symbol
Vee
V IN

Parameter
Supply voltage with respect to GND

Value
-0.5 to 7.0

DC Input voltage with respect to GND

TSTG
TSOL

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

V
V

-0.5 to Vee +0.5
--0.5 to Vee +0.5
-65 to +150

°C

+260

°C

~-~--~--

Voltage applied to 3-state output with respect to GND
Storage temperature

VTS

Units
V

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress.
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol

Parameter
Supply voltage relative to GND Commercial TA = O°C to 70°C
Supply voltage relative to GND Industrial TA = -40°C to 85°C

Min
4.75

Supply voltage relative to GND Military TA = -55°C to T e + 125°C
I/O supply voltage relative to GND

V IL
V IH

Low-level input voltage
High-level input voltage

Vo

Output voltage
Input signal transition time

VeelNT
Veelo
Veelo

TIN

Max
5.25

Units
V

4.5

5.5

V

4.5

5.5

V

3.0

3.6

V

0
2.0

0.8

V
V

Vee +0.5
Veelo

0

--

50

V
ns

Max

Units

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter
5 V TTL High-level output voltage

VOH
3.3 V High-level output voltage

5 V TTL Low-level output voltage
VOL
3.3 V Low-level output voltage

Test Conditions
IOH = -4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min
IOL = 24 mA (FO)
IOL = 12 mA (I/O)
Vee = Min
IOL=10mA
Vee = Min
Vee = Max
VIN = GND or Veelo
Vee = Max
VIN = GND or Veelo
VIN = GND
f = 1.0 MHz

Min
2.4

V

2.4

V

0.5

V

0.4

V

±10.0

JlA

±10.0

JlA

8.0

pF

IlL

Input leakage current

loz

Output high-Z leakage current

CIN

Input capacitance for Input and I/O pins

CIN

Input capacitance for global control pins (FCLKO,
FCLK1, FCLK2, FOEO, FOE1)

VIN =GND
f = 1.0 MHz

12.0

pF

Output capacitance

VIN = GND
f = 1.0 MHz

10.0

pF

Supply current (low power mode)

VIN = Vee or GND
VeelNT = V eelo = 5V
f = 1.0 MHz @ 25°C

COUT

lee

1

2

140 Typ

mA

Notes: 1. Sample tested.
2~

Measured with device programmed as three 16-bit counters~

June 1, 1996 (Version 1.0)

3- 101

I

XC7354 54-Macrocell CMOS CPLD

Power-up/Reset Timing Parameters
Symbol

Parameter

Min

tWMR

Master Reset input Low pulse width

tRESET

Configuration completion time

Typ

Max

Units

80

160

Ils

100

ns

Fast Function Block (FFB) External AC Characteristics3
XC7354-7
(Com only)
Parameter

Symbol
fCF
tSUF
tHF
tCOF

Max count frequency" ~,

Min
4

Fast input setup time before FCLK
Fast input hold time after FCLK
FCLK

t '

t

125,0
4.0
0

t to output valid

tpDFO

Fast input to output valid" ~

tpDFU

liD to output valid" "

tCWF

Fast clock pulse width

Max

XC7354-10
(Com/lnd only)
Min

Max

100,0
5.0
0
5.5
7.5
12.0

4.0

XC7354-12
Min

XC7354-15

Max

5.0

Max

66.7
7.0
0

80.0
6.0
0
8.0
10.0
16.0

Min

9.0
12.0
19.0
5.5

Units
MHz
ns
ns

12.0
15.0
23.0
6.0

ns
ns
ns
ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip-flop toggle rate.

High-Density Function Block (FB) External AC Characteristics
XC7354-7
(Com only)
Symbol
fc
tsu
tH

Parameter
Max count frequency

FCLK

tpsu

liD

tpH
tpca

t

,<:

setup time before p-term clock

liD hold time after p-term clock
P-term clock

t

t

t

<:

4.0
0

tcw

Fast clock pulse width
P-term clock pulse width

4.0
5.0

XC7354-12
Min
Max

66.7
15.0
0
10.0

6.0
0
13.5
16.5

to output valid

liD to output valid" ~

76.9
13.0
0
7.0

to output valid

tpD
tpcw

t

Max

95.2
10.5
0

,<:

liD setup time before FCLK
liD hold time after FCLK t

tco

Min

XC7354-10
(Comllnd only)
Min
Max

7.0
0

Units
MHz
ns
ns

15.0
9.0
0

20.0
27.0
5.5
7.5

Max

55.6
18.0
0
12.0

17.0
22.0
5.0
6.0

XC7354-15
Min

ns
ns
ns

2:4.0
32.0
6.0
8.5

ns
ns
ns
ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

3- 102

June 1, 1996 (Version 1.0)

~XILINX
Fast Function Block (FFB) Internal AC Characteristics
XC7354-7
(Com only)
Symbol

Min

Parameter
FFB logic array delay 1

tFLOGI
tFLOGILP Low-power FFB logic array delay
tFSUI FFB register setup time
FFB register hold time
tFHI

Max

XC7354-10
(Comllnd only)

Min

Max

1.5

1.5

3.5

1

XC7354-12

Min

Max

XC7354-15
Min
Max

2.0

5.5

7.0

1.5

2.5

3.0

4.0

2.5

2.5

3.0

3.0

2.0

Units
ns

8.0

ns
ns
ns

t FCOI

FFB register clock-to-output delay

1.0

1.0

1.0

1.0

ns

tFPOI

FFB register pass through delay

0.5

0.5

1.0

1.0

ns

tFAOI

FFB register async. set delay

2.0

2.5

3.0

4.0

ns

tpTXI

FF6 p-term assignment delay

0.8

1.0

1.2

1.5

ns

tFFO

FFB feedback delay

4.0

5.0

6.5

8.0

ns

Note:

I

1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

High-Density Function Block (FB) Internal AC Characteristics
Symbol

tLOGI

XC7354-7
(Com only)
Min
Max
;3.5

Parameter
FB logic array delay

tLOGILP Low power FB logic delay'
FB register setup time
tSUI
tHI
tCOI
tpOI

XC7354-10
(Comllnd only)
Min
Max
3.5

7.0

FB register hold time

XC7354-12.
Min
Max
4.0
9.0

7.5

1.5

2.5

3.5

3.5

XC7354-15
Min
Max
5.0
11.0

ns
ns

4.0

.3.0
4.0

Units
ns

ns

5.0

FB register clock-to-output delay

1.0

1.0

1.0

1.0

ns

FB register pass through delay

1.5

2.5

4.0

4.0

ns

tAOI

FB register async. set/reset delay

tRA

Set/reset recovery time before FCLK t

tHA

Set/reset hold time after FCLK

0

0

tpRA

Set/reset recovery time before p-term
clock t

7.5

10.0

tpHA

Set/reset hold time after p-term clock t

5.0

tpCI

FB p-term clock delay

1.0

tOE I

FB p-term output enable delay

t

tCARY8 ALU carry delay within 1 FB"
ICARYFB Carry lookahead delay per additional
Functional Block 2

2.5
13.5

3.0
16.0

4.0

6.0

ns
ns

0

0

ns

12.0

15.0

ns

8.0

I

5.0
21.0

18.0

--

ns

9.0

0

0

0

ns

3.0

4.0

5.0

7.0

ns

5.0

6.0

8.0

12.0

ns

1.0

1.5

2.0

3.0

ns

Notes: 1. Specifications account for logiC paths that use the maximum number of available produclterms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.

June 1, 1996 (Version 1.0)

3- 103

XC7354 54-Macrocell CMOS CPLD

1/0 Block External AC Characteristics
Symbol
fiN

....
Parameter
Max pipeline frequency (input register to FFB
FB register) 1

tSUIN

Input register/latch setup time before FCLK

tHIN

Input register/latch hold time after FCLK

tCOIN

FCLK

or

XC7354-7

XC7354-10

(Com only)

(Com/lnd only)

Min
95.2

t

t

Min
76.9

t

XC7354-15
Min
Max
55.6

5.0

6.0

7.0

0

0

0

0

2.5

t

XC7354-12
Min
Max
66.7

Max

4.0

t to input register/latch output

tCESUIN Clock enable setup time before FCLK
tCEHIN Clock enable hold time after FCLK

Max

4.0

3.5

Units
MHz
ns
ns

5.0

ns

5.0

7.0

8.0

10.0

ns

0

0

0

0

ns

tCWHIN

FCLK pulse width high time

4.0

5.0

5.5

6.0

ns

tcwlIN

FCLK pulse lJ\Iidth low time

4.0

5.0

5.5

6.0

ns

Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

Internal AC Characteristics
XC7354-7

XC7354-10

(Com only)

(Comllnd only)

Input pad and buffer delay

2.5

3.5

XC7354-12
Min
Max
4.0

tFOUT

FFB output buffer and pad delay

3.0

4.5

5.0

7.0

tOUT

FB output buffer and pad delay

4.5

6.5

8.0

10.0

ns

tUIM

Universal Interconnect Matrix delay

4.5

6.0

7.0

8.0

ns

Symbol
tiN

Parameter

Min

Max

Min

Max

XC7354-15
Min
Max
5.0

ns
ns

Units

tFOE

FOE input to output valid

7.5

10.0

12.0

15.0

ns

tFOD

FOE input to output disable

7.5

10.0

12.0

15.0

ns

tFCLKI

Fast clock buffer delay

1.5

2.5

3.0

4.0

ns

Device Output o----.-----.----@.TestPoint

r

Device Imput
Rise and Fall
Times < 3 ns

Output Type
FO

VCCIO
5.0V

VTEST
5.0V

R1
160 n

R2

CL

120n

35 pF

3.3 V

3.3V

260n

360n

35 pF
X3491

Figure 3: AC Load Circuit

3- 104

June 1, 1996 (Version 1.0)

l::XIUNX
XC7354 Pinouts
PC68
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

PC44
1
2
3

4

5
6

7
8
9
10
11

12

13

Input
I/FI/MR
IIFI
IIFI
lIFO
IIFI
IIOIFI

17

18
19
20
21
22

-

Output

MCH
MC6~7

GND
O/FCLKO
0/FCLK1
O/FCLK2
IIFI
lIFO
lIFO

MC6-3
MC6-4
MC6-5
MC1-2
MC1-3

GND
lIFO
1/0
lIFO
1/0
lIFO

14
15
16

XC7354

MC1-4
MC5-5
NiC1-5
MC5-6
MC1-6
VCC10

lIFO
lIFO
lIFO
IIOIFI
IIOIFI
IIOIFI
IIOIFI
IIOIFI
IIOIFI

MC1-7
MC1-8
MC1-9
MC6-8
MC5-7
MC6-9
MC6-1
MC6-2
MC6~6

.. '

. VCC1NT

IIOIFI
1/0
1/0

23

June 1, 1,996 (Verslon 1.0)

"
GNO

.

MC5-8'
MC5-1
MC5-2

PC68
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

pC44

Input
1/0
IIOIFI
1/0
1/0
IIOIFI
IIOIFI

24

25
26

XC7354

-

GND

27
28

IIOIFI
11Ft
IIOIFI
IIOIFI
liFO
IIOIFI
liFO

;-

29

30
31
32
33
34

-

35
36
37
38

·40

42

43
44

MC3-7
MC3-8
MC2-9
MC3-9
MC2-8

GND

.

lIFO
liFO
1/0
1/0
lIFO
lIFO
lIFO
lIFO

MC2-7
MC2-6
MC4-2
MC4-3
MC2-5
MC2-4
MC2-3
MC2-2
VC C1NT

OfCKENO
0/e-KEN1
OIFOEO

:41

-

MC4-9

VCC10

39

Output
MC5-3
MC5-9
MC5-4
MC4-1
MC4-7
MC4-8

..

,.
,

MC3"3
MC3-4
MC3-5

VCCINTNpp

0/FOE1
IIFI
lIFO
IIFI
IIFI

MC3-6
MC2-1

3-105

I

XC73S4 54-Macrocell CMOS CPLD

Ordering Information
XC7354 - 7 PC 68 C

Device

TYP~J.
Speed

TL
L

Tempemture Range

Number of Pins

'---- Package Type
Speed Options
-15
-12
-10
-7

15 ns pin-to-pin delay
12 ns pin-to-pin delay
10 ns pin-to-pin delay (commercial and industrial only)
7.5 ns pin-to-pin delay (commercial only)

Packaging Options
PC44
44-Pin Plastic Leaded Chip Carrier
WC44
44-Pin Windowed Ceramic Leadec;l Chip Carrier
PC68
68-Pin Plastic Leaded Chip Carrier.
WC68
68-Pin Windowed Ceramic Leaded Chip Carrier
Temperature Options
C
CommercialO"C to 70°C
I
Industrial -40°C to 85°C
M
Military -55°C (Ambient) to 125°C (Case)

Component Availability
Pins

44

Type
Code
XC7354

-15
-12
-10
-7

C = Commercial = 0° to +70°C

3-106

Plastic
PLCC
PC44
CI
CI
CI
C

68
Ceramic
CLCC
WC44
CI
CI
CI
C

I = Industrial = -40° to 85°C

Plastic
PLCC
PC68
CI
CI
CI
C
M = Military

Ceramic
CLCC
WC68
CIM
CIM
CI
C

=-55°C(A) to 125°C (C)

June 1;1996 (Version'1.0)

XC7372
72-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

tion Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.

•

•
•
•
•
•

•

•
•
•
•
•
•

•
•

High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
100% PCI compliant
18 outputs with 24 mA drive
I/O operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1A) for 3.3 V ±0.3 V
100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 61 MHz 18-bit accumulators
Multiple independent clocks
Up to 84 inputs programmable as direct, latched, or
registered
Power management options
Multiple security bits for design protection
72 macrocells with programmable I/O architecture
Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 6 High-Density Function Blocks
0.8!l CMOS EPROM technology
Available in 68-pin and 84-pin PLCC/CLCC and 100-pin
PQFP packages

Operating current for each design can be approximated for
specific operating conditions using the following equation:
Icc (mA)=MC HP (3.1) + MC LP (2.6) +
MC (0.012 mA/MHz) f

I

Where:
MC HP = Macrocells in high-performance mode
Macrocells in low-power mode
MC LP
MC
= Total number of macrocells used
f
= Clock frequency (MHz)
Figure 1 shows a typical power calculation for the XC7372
device, programmed as four 16-bit counters and operating
at the indicated clock frequency.

General Description
The XC7372 isa high performance CPLD providing general purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and six High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIMTM). See Figure 2 for the architecture
overview.

50
Clock Frequency (MHz)

100
X5287

Figure 1: Typical Icc vs. Frequency for XC7372

Power Management
The XC7372 features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced· significantly, since, in most systems only a few
paths are speed critical.
Macrocells can individually be specified for high performance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To minimize power dissipation, unused Func-

June 1, 1996 (Version 1.0)

3- 107

XC7372 72-Macrocell CMOS CPLD

PC68

PC84

PQ100

PQ100

PC84

j

j

j

j

j

j

68
67
66
65
64

84
83
82
81
80
79

14
13
12
11
10
8

16
17
18
19
20
22

2
3
4
5
6
7

2
3
4
5
6

91
92
93
95
96
97
98
99
4

65
66
67
68
69
70
71
72

51
52
53
54
55
56
57
58

77
76
75
74

62
61
60

89
88
87
84
73
74
85
83
80

63
62
61
58
51
52
59
57
56

48
47
46

79
78
76
72
70
69
68
67
66

55
54
53
50
48
47
46
45
44

45
44
43
42
40
39
38
37
36

IIFI
11Ft

t--------t---------

IIFI

~
~

liFt
11Ft

t--------t---------

11Ft

IIFI
11Ft
11Ft

IIFI
11Ft

11Ft

'~J:~'
12

11
12
13
15
16
17
18
19

13
14
15
17
18
19
20
21

26
30
31
32
34
35
37
38
39

12

12

MC1-1 FFB 1

FFB2

MC2-9

FO

FO

MC1-2

MC2-B

FO

FO

MC1-3

MC2-7

FO

FO

FO

MC1-4

FO

MC1-5

FO

Mel-6

FO

Mel-?

FO

Mel-S
Mel-9

FO

>«
a:

12

>«
a:

12

a:

c:

~

« l~
0
z

«~

«
0
z
«

rro-

9

((
8
9
10

9
10
12

11

21
22
23
24

23
24
25
34
35
26
28
29
30

41
42
43
55
56
44
47
49
50

31
32
33
36
37
39
40
41
43

51
52
54
57
58
60
62
63
65

FO

MC2-5

FO

MC2-4

FO

MC2-3

FO

MC2-2

FO
FO

9
21

27
Arithmetic

Carry

Serial

Shift

27

FBB

FB3

II

0

MC8-1

Me3-9

I/O/Ft

0

MC8-2

Me3-S

I!O!FI

Q/FCLKO

Mea-3

Me3-?

IIOFI

O/FCLK1

MC8-4

O/FCLK2

MCB-5

0
IIOIFI
IIOIFI

Mea-6

I/O/Ft

Mea-9

MeS-?

UIM

~
a:

~14-

r-4--

z
«

~
a:

a:
«
0
z
«

MCB-B

LI

FB7

FB4

Me3-6

0/FOE1

Me3-S

O/FOEO

MC3-4

O/CKEN1

MC3-3
MC3-2

O/CKENO
0

MC3-1

0

II

110

MC7-1

MC4-9

110

MC7-2

MC4-B

IIOIFI
I/O/FI

MC4-7

I/OiFt

MC4-6
MC4-5

110
110

MC4-4

110

110

~

Me7-3

110

MC7-4

liD

Me7-S

>«
a:

r-4--

~14-

~
a:
a:

«
0
z
«

110

Me7-6

I/O/Ft

Me?-?

1I0/FI

Me7-S

MC4-2

!101Ft

Me7-9

MC4-1

jj
25
26
27
28
29
31
32
33
35

MC2-6

MC2-1

21

36
45
24
25
29
48
61
21
27

z
«

FBB

FB5

MC4-3

II

-

110
110
110

110
110

MC6-1

MC5-9

I/O/Ft

MC6-2

MC5-8

I/OIPI

liD

MCB-3

110

MCS-4

110
110

Me6-S

IIOIFI

Me6-?

IIO/FI

MC6-8

IIOIFI

MC6-9

Me6-6

~~

PC68

>«

~
a:

~14-

-4--

z
«

-

Serial Shift
Anthmetlc Carry

a:
a:

«
0
z
«

MeS-?

IIO/FI

MC5-6

110

MC5-5

110
110

MC5-4
MC5-3

110

MC5-2

110
110

MC5-1

))

94
82
9
6
5
3
1
81
75

X5464

Figure 2: XC7372 Architecture

3- 108

June 1, 1996 (Version 1.0)

~XILINX
Absolute Maximum Ratings
Symbol

-

Vee
V IN
VTS

Parameter
Supply voltage with respect to GND

Value
-0.5 to 7.0

DC Input voltage with respect to GND

-0.5 to Vee +0.5

Voltage applied to 3-state output with respect to GND

-0.5 to Vee +0.5
-65 to +150

TSTG

Storage temperature

TSOL

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

+260

Units
V
V
V
°C
°C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol

Parameter
Supply voltage relative to GND Commercial

Min
4.75
4.5

5.5

Supply voltage relative to GND Military TA = -55°C to T e + 125°C
1/0 supply voltage relative to GND

4.5

5.5

3.0
0
2.0

3.6
0.8

V IH

Low-level input voltage
High-level input voltage

Vo

Output voltage

TIN

Input signal transition time

VeelNTI
Veelo
Veelo
V IL

T A = O°C to 70°C
Supply voltage relative to GND Industrial TA = -40°C to 85°C

50

Units
V
V
V
V
V
V
V
ns

Max

Units

Max
5.25

Vee +0.5
V eelo

0

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter
5 V TTL High-level output voltage

VOH
3.3 V High-level output voltage

5 V TTL Low-level output voltage
VOL
3.3 V Low-level output voltage

Test Conditions
IOH = -4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min
IOL = 24 mA (FO)
IOL = 12 mA (I/O)
Vee = Min
IOL = 10 mA
Vee = Min
Vee = Max
V IN = GND or Veelo

Min
2.4

V

2.4

V

0.5

V

0.4

V

±10.0

J..lA

±10.0

J..lA

IlL

Input leakag.e current

loz

Output high-Z leakage current

Vee = Max
V IN = GND or Veelo

CIN

Input capacitance for Input and 1/0 pins

V IN =GND
f = 1.0 MHz

8.0

pF

CIN

Input capacitance for global control pins
(FCLKO, FCLK1, FCLK2, FOEO, FOE1)

V IN =GND
f = 1.0 MHz

12.0

pF

Output capacitance

V IN = GND
f = 1.0 MHz

10.0

pF

Supply current (low power mode)

V IN = Vee or GND
VeelNT = Veelo = 5V
f = 1.0 MHz @ 25°C

COUT

lee

2

1

187 Typ

mA

Notes: 1. Sample tested.
2. Measured with device programmed as four 16-bit counters.

June 1,1996 (Version 1.0)

3- 109

I

XC7372 72-Macrocell CMOS CPLD

Power-up/Reset Timing Parameters
Parameter

Symbol

Min

tWMR

Master Reset input Low pulse width

tRESET

Configuration completion time

Typ

Max

Units

80

160

Jls

100

ns

Fast Function Block (FFB) External AC Characteristics3
XC7372-7
(Com only)
Min

Parameter

Symbol
fCF

Max count frequency ,", '+

tSUF

Fast input setup time before FCLK

tHF

Fast input hold time after FCLK

tCOF

FCLK

i

i '

i

Max

XC7372·10
(Comllnd only)
Min

100.0
5.0
0

125.0
4.0
0
5.5
7.5
14.0

to output valid

tpDFO

Fast input to output valid" 2

tpDFU

1/0 to output valid "

tCWF

Fast clock pulse width (High or Low)

2

Max

4.0

XC7372-12
Min

XC7372-15

Max

80.0
6.0
0
8.0
10.0
17.0

5.0

Min

Max

66.7
7.0
0

5.5

MHz
ns
ns

12.0
15.0
24.0

9.0
12.0
20.0

Units

6.0

ns
ns
ns
ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate specifications tested using Figure 3 as the test load circuil.
4. Export Control Max. flip-flop toggle rate.

High-Density Function Block (FB) External AC Characteristics
Symbol
fc
tsu
tH

XC7372-7
(Com only)
Min
Max

Parameter

1/0 setup time before FCLK i
1/0 hold time after FCLK i

i

,""

tco

FCLK

tpsu

1/0 setup time before p-term clock i
1/0 hold time after p-term clock i

tpH
tpco

P-term clock

i

2

6.0
0

tcw

Fast clock pulse width

2

P-term clock pulse width

4.0
5.0

XC7372-12
Min
Max

XC7372-15
Min
Max

62.5
16.0
0

52.6
19.0
0

10.0
6.0
0

13.5
18.5

to output valid

1/0 to output valid "

71.4
14.0
0
7.0

to output valid

tpD
tpcw

95.2
12.5
0

Max count frequency ,""

XC7372-10
(Comllnd only)
Min
Max

12.0
7.0
0

18.0
23.0
5.0
6.0

5.5
7.5

MHz
ns
ns

15.0
9.0
0

21.0
28.0

Units

ns
ns
ns

25.0
33.0
6.0
8.5

ns
ns
ns
ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

3- 110

June 1, 1996 (Version 1.0)

~XILINX
Fast Function Block (FFB) Internal AC Characteristics
Symbol

Parameter
tFLOGI FFB logic array delay
tFlOGllP Low-power FFB logic array delay'
tFSUI FFB register setup time
FFB register hold time
tFHI
tFCOI FFB register clock-to-output delay
IfPOI FFB register pass through delay
tFAol FFB register async. set delay
tpTXI FFB p-term assignment delay
tFFo FFB feedback delay
Note:

XC7372-7
(Com only)
Min
Max
1.5
3.5
1.5
2.5
1.0
0.5
2.0
0.8
4.0

XC7372-10
(Comllnd only)
Min
Max
1.5
5.5
2.5
2.5
1.0
0.5
2.5
1.0
5.0

XC7372-12
Min
Max

XC7372-15
Min
Max

2.0
7.0
3.0
3.0

2.0
8.0
4.0
3.0

1.0
1.0
3.0
1.2
6.5

1. Specifications account for logic paths that use the maximum number of available product

1.0
1.0
4.0
1_5
8.0

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns

ter~s for a given macrocell.

High-Density Function Block (FB) Internal AC Characteristics
Symbol

Parameter
tlOGI FB logic array delay
tLOGllP Low power FBlogic delay
FB register setup time
tSUI
FBregister hold time
tHI
FB register clock-to-output delay
tCOI
FB register pass through delay
. tpol
FB register async. set/reset delay
tAOI
Set/reset recovery time before FCLK i
tRA
Set/reset hold time after FCLK i
tHA
Set/reset
recovery time before p-term
tpRA
clock i
tpHA Set/reset hold time after p-term clock i
FB p-term clock delay
tpCI
FB p-term output enable delay
tOEI
ALU
carry delay within 1 FB ----OOe Test Point

r

Device Imput
Rise and Fall
Times < 3 ns

Output Type
FO

VCClo
5.0V
3.3V

VTEST
5.0V
3.3V

R1
160(1
260(1

R2
120(1
360(1

CL
35 pF
35 pF
X3491

Figure 3: AC Load Circuit

3-112

June 1, 1996 (Version 1.0)

~XILINX
XC7372 Pinouts
PQ100

PC84

PCG8

Input

65

43

35

IIFI

66

44

36

3

IIFI

67

45

37

4

4

IIFI

68

46

38

19

5

5

IIFI

69

47

39

20

6

6

IIFI

70

48

40

I/O/FI
1/0
1/0
1/0
1/0
110

21

-

IIOIFI
IIFI

71

49

41

72

50

42

73

51

-

PQ100

PC84

PCG8

15

1

1

16

2

2

17

3

18

22

7

-

23

8

7

Input

XC7372

Output

MR

MC8-8

24

9

8

O/FCLKO

MC8-3

74

52

-

25

10

9

0/FCLK1

MC8-4

75

-

-

0

26

-

76

53

43

I/O/FI

11

FO
IIOIFI

MC1-1

27

MC8-9

77

-

-

28

-

-

78

54

44

29

12

10

0/FCLK2

MC8-5

79

55

45

30

13

11

FO

MC1-2

80

56

46

31

14

12

FO

MC1-3

81

-

32

15

13

FO

MC1-4

82

-

-

33

16

14

83

57

47

34

17

15

FO

MC1-5

84

58

-

35

18

16

FO

MC1-6

85

59

48

36

-

-

0

MC8-1

86

60

49

VCCIO

GND

Output
MC6-9
MC5-1
MC5-2
MC5-3
MC5-4
MC5-5

GND
1/0
110
1/0

GND

XC7372

MC5-6
MC4-5
MC3-1

MC4-4
MC5-7

GND
1I0/FI
I/O/FI
1/0

MC5-8

0

MC3-2

IIOIFI
1/0
1/0
1/0

MC3-8

MC5-9
MC4-1

MC4-2
MC4-6
MC4-3

GND

37

19

17

FO

MC1-7

87

61

38

20

18

FO

MC1-8

88

62

39

21

19

FO

MC1-9

89

63

-

40

22

20

90

64

50

41

23

-

110

MC7-1

91

65

51

FO

MC2-9

42

24

-

110

MC7-2

92

66

52

FO

MC2-8

43

25

-

MC7-3

93

67

53

FO

MC2-7

44

26

21

MC7-6

94

-

-

-

MC8-2

95

68

54

46

27

-

96

69

55

47

28

22

48

-

-

49

29

23

IIOIFI
FO
FO
FO
FO
FO

MC3-9

45

1/0
1/0
0

50

30

24

51

31

25

52

32

26

53

-

-

54

33

27

VCCIO

GND

MC4-7

IIOIFI
1I0lFI
1I0lFI

MC4-8
MC4-9

VCCIO

MC2-6
MC2-5

IIOIFI
0
IIOIFI
IIOIFI

MC7-7

97

70

56

MC8~6

98

71

57

MC7-8

99

72

58

MC7-9

100

73

59

1/0
1/0

MC6-1

1

74

60

MC6-2

2

-

-

3

75

61

0/CKEN1

MC3-4

MC6-3

4

-

-

FO

MC2-1

MC7-4

5

76

62

O/FOEO

MC3-5

MC7-5

6

77

-

0/FOE1

MC6-4

7

78

63

MC6-5

8

79

-

IIFI

9

-

-

10

80

64

IIOIFI
IIFI
IIFI
IIFI
IIFI
I/FI

VCCIO

55

34

56

35

-

57

36

28

1/0
1/0
110
1/0

58

37

29

1/0

59

38

30

60

39

31

110

MC6-6

1I0lFI
IIOIFI
IIOIFI

MC8-7

11

81

65

MC6-7

12

82

66

13

83
84

68

MC2-4
MC2-3
MC2-2

VCCINT
MC3-3

O/CKENO

GND

MC3-6

VCCINTI
Vpp

61

-

-

62

40

32

63

41

33

64

42

34

VCCINT

June 1, 1996 (Version 1.0)

MC6-8

GND

14

67

MC3-7

3- 113

XC7372 72-Macrocell CMOS CPLD

Ordering Information

XC7372 - 7 PC 84 C

.Device

TYP~

TL

I

L

Speed

Temperature Range

Number of Pins

'---,- Package Type
Speed Options
-15
15 ns pin-to-pin delay
-12
12 ns pin-to-pin delay
-10
10 ns pin-to-pin delay (commercial and industrial only)
-7
7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PCB8
68-Pin Plastic Leaded Chip Carrier
WC68
68-Pin Windowed Ceramic Leaded Chip Carrier
PC84
84-Pin Plastic Leaded Chip Carrier
WC84
84-Pin Windowed Ceramic Leaded Chip Carrier
PQ100 100-Pin Plastic Quad Flat Pack
Temperature Options
C
. CommercialO°C to 70°C
I
Industrial -40°C to 85°C
M
Military -55°C (Ambient) to 125°C (Case)

Component Availability
Pins

68

Type
Code

XC7372

-15
-12
-10
-7

Plastic
PLCC
PC68
CI
CI
CI
C

C = Commercial = 0° to +70°C

3- 114

84
Ceramic
CLCC
WC68
CIM
CIM
CI
C

Plastic
PLCC
PC84
CI
CI

GJ
..

I = Industrial = -40° to l35bC·

C,

-

_..

Ceramic
CLCC
WC84
CIM
CI
CI
C

100
Plastic
PQFP
PQ100
CI
CI
CI
C

"

M ",Militar{"'~55°C(A) to 125°C (C)

June 1, 1996 (Version 1.0)

XC73108
108-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

Macrocells can individually be specified for high performance or low power operation by adding attributes to the
logic schematic, or declaration statements to the behavioral
description. To mi'nirrifze power dissipation, unused Function Blocks are turned off and unused macrocells in used
Function Blocks ·arecOnfigured for low power operation.

•

•
•
•
•
•

•

•
•
•
•

•

•
•

High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 125 MHz maximum clock frequency
100% PCI compliant
1B outputs with 24 mA drive
I/O operation at 3.3 V or 5 V
Meets JEDEC Standard (B-1 A) for 3.3 V ±0.3 V
100% interconnect matrix
-' Maximizes resource utilization
- Wire-AND capability via SMARTswitch
High-speed arithmetic carry network
- 1 ns ripple~carry delay per bit
- 56 MHz 1B-bit accumulators
Multiple independent clocks
Up to 120 inputs programmable as direct, latched, or
registered
Power management options
Multiple security bits for design protection
10B macrocells with programmable I/O architecture
Advanced Dual-Block architecture
- 2 Fast Function Blocks
- 10 High-Density Function Blocks
O.B 11 CMOS EPROM technology
Available in B4-pin and B4-pin PLCC/CLCC, 144-pin
PGA, 100-pin and 160-pin PQFP, and 225-pin BGA
packages

Operating current for each design can be approximated for
specific operating conditions using the following equation:
Icc (mA)=MC HP (2.4) t MC LP (2.1) +
MC (0.015 mA/MHz) f
Where:

= Macrocells in high-performance mode

MC HP
MC LP
=
MC
f
=

Macrocells in low-power mode
Total number of macrocells used
Clock frequency (MHz)

Figure 1 shows a typical power calculation forthe XC7310B
device, programmed as six 16-bit counters and operating at
the indicated ylock frequency.

·······························l
............j

300

<'

E-

o

..9 200

General Description
The XC7310B is a high performance CPLD providing general purpose logic integration. It consists of two PAL-like
24V9 Fast Function Blocks and ten High Density Function
Blocks interconnected by the 100%-populated Universal
Interconnect Matrix (UIMTM).

Power Management
The XC7310B features a power-management scheme that
permits non-speed-critical paths of a design to be operated
at reduced power. Overall power dissipation is often
reduced significantly, since, in most systems only a few
paths are speed cr.itical.

June 1, 1996 (Version 1.0)

~

'Ci

~
100

o

50
Clock Frequency (MHz)

100
X5697

Figure 1: Typical Icc vs. Frequency for XC731 08

3- 115

I

XC73108108-Macrocell CMOS CPLD

BG225!
PC84 PQ100

PQ160

PQ160

I

I

I

I

I

84

14
13
12
11

H1

G1

19
18
17

G3

15

10

E1

8

F3

13
11

26
3D
31
32
34

N3
P4

36

P5

47
49

83
82
81
80
79

13

14
15

17
18
19
20
21

35

37

38
39

BG2251

PG144

H2

N6
P7
R6

P8
R8
N8

44
54

r-----I-~IIF~I_~ 22

1--'::::::'-:--1~
1--':::::::'-:--1~

r----- I FI
Lr----r__-1~i"F~'=~
11Ft

~==;FO~==~:::==±==t~MC~'~.3

I--:;FO~-1_-l._j-.M~C::';'..::.-I-4 £>-

~

12

~

If

~==fFO~==~:==±==t~MC~'~.7 ~

FO

Me2-6

FO

~

Me2·S
MC2-4

FO
FQ

<

MC2·'

FO
FO

..

MC2·2

'--~

,

Arithmetic

(

E15
015

E13
815
A14

C11
A12

75

81
82
94

9

24

10

25

12

29

C13

130
147

110

A4
84
83
C3

151

110

153

110

158

C10

129

A11

133
145

86

25

Ll

27
33

21

M1

27

P2

23

41

R9

24
25
34
35

42
43
55
56
44
47
49
50

R10
P9

26
28
29
30
31
32
33
36
37
39
40
41
43

155

K2
N2
M3
P3

M14
N15

Nl0
R12

P12
P13

51
52
54

N12

57
58
60
62
63
65

M15
K14
J13
J15
H14
G13

P14
N14

~~;::; ~

Shift FB3

35

42
34
32
29
37
62
63
64

110

r---

MC3-8

i

12J.-

I/OlFt

o
o
OIfCLKO

MC4-5

:::

'---Tr

i

I~-"'----

.....

L-~
MC6-9
MC6-8

12J.-

MCB..

1I01F1
I!O/FI
I/O/Ft

16
14

OIFOE'
O/FOEO

8
6
2
159
9

OICKEN!
O/CKENO

o
o
I/OIFI

110

MC6-5

110
110

M07-9
MC7-8
Me7-7
MC7-S
MCNi
MC7-4
MC7-3
MC7-Z

~~ f---o~~-I-+-l~.J7.M;c.CB;:;.':1 ~ 12J.IIOfFI

~

R4
N5
R2

43

12

7

140
139
138

'---

Rl1
R7
P10
N7

48
45

36

P6

F1
G2
F2
Cl
02
C2
82
E2
E3
C8
A8

88
C9

9

6
5
3
1

77
76
75
74

89
88
87

63
62
61
58
51

135
113
115

C14

136

A10

134

89

73
74
85
83

126

A13

80

I/O/FI

124

f/OlFI

122
117

812
813

79
78
76
72
70
69
68
67
66

1/0
110
110

FB7,--lL

~

::~ ~
:O~ r-...,:",~~;;-:--r-=~==~~"~~;-;~:1

48
45

MC6-6

L-~

MCS-!

110

1/0
1/0
1/0

110

61

L13
P1S
N13
R14
Nl1
R13

llOlFI
1/0
1/0

I/O/FI
I{O/FI

Mce-3
MC6-2

K15
L15
K13
L14

72
69
57
67
55
50

I/00Ft
1I01F1

Mee-7

MCS-4

II FBB
MC8-2

1/0

FB6-LL

MC9-2

Me8-3

MC5-5

MC5-2

MC9-1

110

MC5-6

~ :~:::

n' FB>

110

110

FBSJl

i~

r---

97

MC4-S

MC5-8
MCS-7

~~~~~ ~

1/0

~

MC4-8
MC4-7

MC5-9

MC1G-S

110

84

MClO-2
MC1o.3

86 1--:::~-{:=:w._j-.M"'~"~:7I~ ~
88
110
MC'·' ~
68 /--;;'IO;;--1-+-I~-I7.M"C,;-;.,:1 ~
1f00Ft
MC9-7
71
IfOlFI
MC9-8
73
MC9-9
IIOIFI
75

77
79
82
90

UIM

96
93
91
89
87
78
76
74

....

F6tO

.....

lf01F1

110
110

MC4-2

IfOfFI

1/0

4

~ ~:

i

~

1/0If1

I/OIFI

C5
A2
Bl

110

MC1()'1

/-O;;.IF",C;;:LK;;;':-I_-l-I~.j-M",C;;';;.-O.4,"
OIFCLK2
Me10·S
o

A3

154
156

1/0

MC4-9

MCll·7
MC1H
MC11-9

II

IfOfF!
IIOIFI

FB4-LL

MGll-1

MC11·'

MC'"
MC3-2

n'MC11·2 FB11
MC11·4

f---.o:--

152

MC3-6
MC3-5

....

L-.!TT

/--;;";;.O_-r.:r---=4~-tM",C""-:-'.';;I
~ 12J.I/O
MCtl·e ~
I/O/Ft
I/Olft

87
C6
85

7

.Jl
MC3-9

~~: /-"":"'~"'I:;-:_i-:)::):=:rM
",C,.,'; .-2.'; J

810
A5

Pi
L3
11

__-' __~_r.JL~J:~F~B'~2

1f~~FI

148

A7
A6

6

45

Carry

Serial

105 I
110
Me12·'
107 /--;;'10;,,--r.=+l~.j-M"'C"";;'-2.2'"
109 /--;;II;;'-O--1-=4~-tM~C::';';;'-~'~
112
110
MC12·4 ~
114
110
MC12·' !Ii

~ ~~

65
66
67
68
69
70
71
72

N1

3B

45

_~

91
92
93
95
96
97
98
99
4

J2

9

39

F14

FO

3
4
5

K3
L2

j IMiCI2·i7~!~~~~~FO~~ 146
144

12

'----';:FO;;---1_-l._j-.M"'C,.,'.,,"s ~ I-t-

MC1-6 a
56 I· FO
58
l1
59 I--:;FO~-1_-l._~MC::';'..::.-I.8
60
~_

I
2

23

rFF~~~~~~~~~~=l====J==:~~~~~:~

PC84

16
17
18
19
20
22

Jl

24
26

, ~2 }12~2 '

PQ100

II
K1

~I-~::~:--~ ~~

~==;~~==~:==l==b~~~~~~:;+F~ffi~'

PG144

I/OIFI

1/0
1/0
110
110
1/0
1/0

111

013

814

014

108
106

E14
F13

104
103

G14
F15
G1S

102

84

52

59
57
56

55
54
53

50
48

47
46
45
44

Serial ShIft

Anlhmellc eany

Figure 2: XC73108 Architecture

3- 116

June 1, 1996 (Version 1.0)

~XILINX
Absolute Maximum Ratings
Parameter

Symbol

Value
-0.5 to 7.0

Supply voltage with respect to GND
DC Input voltage with respect to GND

Vee
V IN
VTS

Voltage applied to 3-state output with respect to GND

TSTG

Storage temperature

TSOL

Maximum soldering temperature (lOs @ 1/16 in. = 1.5 mm)

Units

-0.5 to Vee +0.5

V
V

-0.5 to Vee +0.5
-65 to + 150

°c

+260

°C

V

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol
VeelNT
Veelo

Parameter
Supply voltage relative to GND Commercial

TA = O°C to 70°C
Supply voltage relative to GND Industrial TA = -40°C to 85°C

Min
4.75

Max
5.25

4.5

5.5

4.5

5.5
3.6

Supply voltage relative to GND Military TA = -55°C to T e + 125°C
I/O supply voltage relative to GND

3.0

V IL
V IH

Low-level input voltage
High-level input voltage

0
2.0

Vo

Output voltage

TIN

Input signal transition time

V eelo

0

50

Units
V
V
V
V
V
V
V
ns

Max

Units

0.8
Vee +0.5
V eelo

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter
5 V TIL High-Jevel output voltage

VOH
3.3 V High-level output voltage

5 V TIL Low-level output voltage
VOL
3.3 V Low-level output voltage
',L

Input leakage current

'OZ

Output high-Z leakage current

C,N

Input capacitance for Input and 110 pins

C,N

Input capacitance for global control pins
(FCLKO, FCLK1, FCLK2, FOEO, FOE1)

COUT1
ICC2

Output capacitance

Supply current (low power mode)

Test Conditions
10H = -4.0 mA
VCC= Min
10H =-3.2 mA
VCC = Min
IOL = 24 mA (FO)
10L = 12 mA (1/0)
VCC= Min
10L = 10 mA
VCC= Min
VCC= Max
V,N = GND or VCCIO
VCC= Max
V,N = GND or VCCIO
V,N =GND
f = 1.0 MHz
V,N =GND

f = 1.0 MHz
V,N = GND

f = 1.0 MHz
V,N = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C

Min
2.4

V

2.4

V

0.5

V

0.4

V

±10.0

llA

±10.0

llA

8.0

pF

12.0

pF

20.0

pF

227 Typ

mA

Notes: 1. Sample tested.
2. Measured with device programmed as six 16-bit counters.

June 1, 1996 .(Version 1.0)

3- 117

XC73108 108·Macrocell CMOS CPLD

Power-up/Reset Timing Parameters
Symbol

Parameter

tWMR

Master Reset input Low pulse width

tRESET

Configuration completion time

Min

Typ

Max

Units
ns

80

160

lls

100

Fast Function Block (FFB) External AC Characteristics3
Symbol
fCF

Parameter
Max count frequency ,~, 4

tsuF

Fast input setup time before FCLK l'

tHF

Fast input hold time after FCLK l'

XC731 08-7

XC731 08·1 0

XC731 08·12

(Com only)

(Com only)

(Comllnd only)

Min

125.0
4.0
0

FCLK l' to output valid

leOF
tpOFO

Max

Min

100.0
5.0
0

tpoFU

110 to output valid ,"

tCWF

Fast clock pulse width (High or Low)

4.0

Min

Max

80.0
6.0
0
8.0
10.0
19.0

5.5
7.5
13.5

Fast input to output valid ' ~

Max

5.0

XC731 08·15
Min

Max

66.7
7.0
0

Min

Max

50.0
10.0
0
12.0
15.0
27.0

9.0
12.0
22.0
5.5

XC731 08·20

6.0

Units
MHz
ns
ns

15.0
20.0
35.0
6.0

ns
ns
ns
ns

Notes: 1. This parameter is given for the high·performance mode. In low·power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit.
4. Export Control Max. flip·flop toggle rate.

High-Density Function Block (FB) External AC Characteristics
Symbol

XC731 08·7

XC731 08·10

XC731 08·12

(Com only)

(Com only)

(Comilnd only)

Parameter

Min

fc

Max count frequency , ~

tsu

110 setup time before FCLK l'
110 hold time after FCLK l'

83.3
12.0
0

tH

,2

tco

FCLK l' to output valid

tpsu

110 setup time before p-term clock l' "
110 hold time after p-term clock l'

tpH
tpco
tpo

Fast clock pulse width
P-term clock pulse width

Min

XC73108·15
Min

12.0

20.0
25.0

XC731 08·20
Min

ns
ns

20.0

28.0
36.0

Units
MHz

12:0
0

9.0
0

6.0
8.5

Max

35.7
28;0
0
15.0

23.0
30.0
5.5
7.5

Max

45.5
22.0
0

7.0
0

6.0
0

5.0
6.0

Max

55.6
18.0
0
10.0

15.0
18.0
4.0
5.0

Max

62.5
16.0
0

4.0
0

110 to output valid ,"

tcw

Min

7.0

P-term clock l' to output valid

tpcw

Max

ns
ns
ns

36.0
45.0
6.0
12.0

ns
ns
ns
ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms lor a givenmacrocell.

3- 118

June 1, 1996 (Version 1.0)

~XIUNX
Fast Function Block (FFB) Internal AC Characteristics
Symbol

Parameter

XC731 08-7

XC731 08-10

XC731 08-12

(Com only)

(Com only)

(Com/lnd only)

Min

tFLOGILP Low-power FFB logic array delay 1
FFB register setup time
tFSUI
FFB register hold time

tFHI
tFCOI
t FPOI

FFB register clock-to-output delay

tFAOI
t pTXI
t FFO

FFB register async. set delay

Min

1.5
3.5

FFB logic array delay

tFLOGI

Max

1.5
2.5

Max

FFB p-term assignment delay
FFB feedback delay

Max

3.0
3.0

2.5
2.5

XC731 08-15

XC731 08-20

Min

Min

2.0
7.0

1.5
5.5

1.0
0.5
2.0
0.8
4.0

FFB register pass through delay

Min

1.0
0.5
2.5
1.0
5.0

Max

2.0
8.0
4.0
3.0

Units

3.0
11.0

ns

6.0
4.0
1.0
1.0
4.0
1.5
8.0

1.0
1.0
3.0
1.2
6.5

Max

ns
ns
ns

1.0
2.0
6.0
2,0
10.0

ns
ns
ns
ns
ns

I

Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocelL

High-Density Function Block (FB) Internal AC Characteristics
Symbol
tLOGI

Parameter

XC731 08-7

XC731 08-1 0

XC73108-12

(Com only)

. (Com only)

(Comllnd only)

Min
1

tHI

FB register hold time

tCOI

FB register clock-to-output delay

tpOI

FB register pass through delay

tAOI

FB register async.set/reset delay

tRA

Set/reset recovery time before FCLK i

tHA

Set/reset hold time after FCLK i

tpRA

Set/reset recovery time before p-term
clock i

tpHA

Set/reset hold time after p-term clock i

tpCI

FB p-term clock delay

tOEI

FB p-term output enable delay

tCARY8 ALU carry delay within 1 FB 2
tCARYFB Carry lookahead delay per additional
Functional Block 2

Min

1.5
3.5

Max

1.0
1.5
2.5

6.0
1.0
3.0
5.0
1.0

0
4.0
6.0
1.5

XC731 08-20

Min

Min

Max

5.0
11.0
4.0
5.0

25.0
0
15.0

8.0

Units

6.0
14.0

ns

ns

1.0
4.0
7.0

ns
ns
ns
ns
ns
ns

12.0
0
7.0
12.0
3.0

ns
ns

31.0
0
20.0

9.0
0
5.0
8.0
2.0

Max

6.0
6.0
1.0
4.0
5.0

1.0
4.0
4.0
21.0
0
12.0

-

XC731 08-15

4.0
9.0

1.0
2.5
3:0
19:0
0
10.0

5.0

Max

3.0
4.0

2.5
3.5

15.0
0
7.5

Min

3.5
7.5

3.5
7.0

FB logic array delay

tLOGILP Low power FB logic delay
FB register setup time
tSUI

Max

ns

0
9.0
15.0
4.0

ns
ns
ns
ns

Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.

June 1, 1996 (Version 1.0)

3- 119

XC73108108·Macrocell CMOS CPLD

I/O Block External AC Characteristics
Symbol

Parameter

XC731 08·7

XC731 08-10

XC73108·12

(Com only)

(Com only)

(Comilnd only)

Min

Max

Min

Max

Min

XC731 08·15

Max

Min

Max

XC731 08·20
Min

Max

Units

fiN

Max pipeline frequency (input register
to FFB or FB register) 1

83.3

62.5

55.6

45.5

35.7

MHz

tSUIN

Input register/latch setup time before
FCLKt

4.0

5.0

6.0

7.0

10.0

ns

tHIN

Input register/latch hold time after
FCLKt

0

0

0

0

0

ns

tCOIN FCLK t to input register/latch output
IcESUIN Clock enable setup time before FCLK t
tCEHIN Clock enable hold time after FCLK t

2.5

3.5

4.0

5.0

6.0

ns

5.0

7.0

8.0

10.0

12.0

ns

0

0

0

0

0

ns

tCWHIN

FCLK pulse width high time

4.0

5.0

5.5

6.0

6.0

ns

tCWLlN

FCLK pulse width low time

4.0

5.0

5,5

6.0

6.0

ns

Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocelL

Internal AC Characteristics
Symbol

Parameter

XC731 08·7

XC731 08·1 0

XC731 08·12

(Com only)

(Com only)

(Com/lnd only)

Max

Min

Max

Min

Max

XC731 08·15

XC731 08·20

Min

Min

Max

Units

Input pad and buffer delay

2.5

3.5

4.0

5.0

6.0

ns

tFOUT

FFB output buffer and pad delay

3.0

4.5

5.0

7.0

9.0

ns

tOUT

FB output buffer and pad delay

4.5

6.5

8.0

10.b

14.0

ns

tiN

Min

Max

tUIM

Universal Interconnect Matrix delay

6.0

9.0

10.0

12.0

15.0

ns

tFOE

FOE input to output valid

7.5

10.0

12.0

15.0

20.0

ns

FOE input to output disable

7.5

10.0

12.0

15.0

20.0

ns

Fast clock buffer delay

1.5

2.5

3.0

4.0

5.0

ns

tFOD
tFCLKI

VTEST

Device Output

cr---i~------",---@.

r

Device Imput
Rise and Fall
Times < 3 ns

Output Type
FO

Test Point

VCCIO
5.0V

VTEST
5.0V

3.3V

3.3V

Rl
1600
2600

R2
1200
3600

CL

35 pF
35 pF
X3491

Figure 3: AC Load Circuit

3· 120

June 1, 1996 (Version 1.0)

~:XILINX
XC73108 Pinouts
P01S0

PG144
BG225

P0100

PC84

1

03

-

-

Input

XC73108

Output

VCCIO

0/CKEN1

MC5-4

pal SO

PG144
BG225

pal 00

PC84

41

N4

28

-

42

P3

29

12

O/FCLK2

MC1O-5

43

R2

-

-

MC4-1

44

P4

30

13

45

N5

-

46

R3

-

-

1/0
FO
1/0

2

C2

3

75

3

-

-

4

B1

4

FO

5

-

-

-

6

02

5

76

O/FOEO

MC5-5

7

E3

-

-

0

MC5-1

47

P5

31

14

8

C1

6

77

0/FOE1

MC5-6

48

R4

-

-

0

N/C
MC2-1

N/C

9

E2

-

-

10

01

7

78

11

F3

8

79

IIFI

MC5-2
VCCINT/VpP

12

F2

9

-

I/O/FI

13

E1

10

80

IIFI

14

G2

-

-

I/O/FI

15

G3

11

81

IIFI

16

F1

-

-

I/O/FI

17

Gl

12

82

18

H2

13

83

19

H1

14

84

20

H3

-

-

21

J3

15

1

MC5-7

FO
1/0
FO
1/0

32

15

P6

-

-

51

R5

33

16

GND

52

-

-

-

-

N/C
N/C

P7

34

17

FO

-

-

56

R6

35

18

IIFI

57

R7

IIFI

58

P8

36
37

19

IIFI

59

R8

38

20

GND

60

N8

39

21

1/0
FO
I/O/FI
FO
FO
FO

MR

61

N9

40

22

22

J1

16

2

IIFI

62

R9

41

23

23

K1

17

3

IIFI

63

R10

42

24

24

J2

18

4

IIFI

64

P9

43

25

25

K2

-

-

0

65

26

K3

19

5

IIFI

66

-

-

27

L1

-

-

0

67

P10

-

-

28

L2

20

6

IIFI

68

N10

44

26

29

M1

21

-

I/O/FI

69

R11

45

-

30

N1

22

7

IIFI

70

P11

46

27

MC10-8

GND

MC1-3
MC4-3

N6

N7

MC10-2

MC4-2
VCCINT

54

MCtO-1

MC1-2

49

-

Output

VCCIO

55
MC5'9

XC73108

50

53
MC5-8

Input

MC1-4
MC4-4

I
MC1-5
MC4-5
MC1'6
MC4-7
MC1-7
MC1-8
MC1-9

VCCIO

1/0
1/0
1/0

MC9-1
MC9-2
MC9-3

N/C
N/C
110

MC4-6

1/0
l/O/FI

MC9-6
MC4-8

GND

31

M2

23

8

71

R12

47

28

I/O/FI

MC9-7

32

L3

-

-

I/O/FI

MC10-7

72

R13

48

-

IIOIFI

MC4-9

33
34

N2

24

9

O/FCLKO

MC1O-3

73

P12

49

29

1I0lFI

MC9-8

P1

-

-

0

MC10-6

74

N11

-

MC3-1

35

M3

25

10

0/FCLK1

MC10-4

75

P13

50

30

36

N3

26

-

FO

MC1-1

76

R14

-

-

37

P2

27

11

I/O/FI

MC10-9

77

N12

51

31

38

-

-

-

N/C

78

N13

-

-

-

-

N/C

79

P14

52

32

1/0
IIOIFI
1/0
1/0
1/0
1/0

-

GND

80

R15

-

-

39
40

R1

MC9-9
MC3-2
MC8-1
MC3-3
MC8"2

GND

Note: With the XC73108 in the 225-pin bali grid array package, only 144 of the solder balls are connected, the remaining solder bails should be left unconnected.

June 1, 1996 (Version 1.0)

3- 121

XC73108108-Macrocell CMOS CPLD

XC73108 Pinouts (continued)
PQ160

PG144
BG225

PQ100

PC84

81

M13

53

-

Input

XC73108

Output

V CC10

82

N14

54

33

83

-

-

84

P15

-

-

I/O

85

-

I/O

MC8-3
N/C
MC3-4
N/C

PQ160

PG144
BG225

PQ100

PC84

121

C12

-

-

122

813

78

54

I/O/FI

MC7-8

123

A14

-

-

I/O

MC12-6

124

812

79

55

I/O/FI

MC7-9

125

Cll

-

-

I/O/FI

MC12-7

I/O

86

M14

55

34

I/O

MC9-4

126

A13

80

56

87

L13

-

-

I/O

MC3-5

127

811

-

Input

XC73108

Output

V CC10

MC6-1

88

N15

56

35

I/O

MC9-5

128

A12

-

89

L14

-

-

I/O

MC3-6

129

Cl0

81

90

M15

57

36

I/O

MC8-4

130

810

91

K13

-

-

I/O/FI

MC3-7

131

92

K14

58

37

I/O

MC8-5

132

-

-

93

L15

-

-

I/O/FI

MC3-8

133

All

82

-

94

J14

59

38

134

89

83

57

I/O

MC6-2

95

J13

60

39

I/O

MC8-6

135

C9

84

58

I/O

MC6-6

96

K15

61

-

I/O/FI

MC3-9

136

Al0

85

59

I/O

97

J15

62

40

I/O/FI

MC8-7

137

A9

86

60

I/O/FI

VCCINT

98

H14

63

41

99

H15

-

-

100

H13

64

42

101

G13

65

43

I/O/FI

102

G15

66

44

I/O

103

F15

67

45

104

G14

68

105

F14

106
107
108
109
110

C15

71

49

111

D14

72

50

112

E13

-

113

C14

73

MC8-8

GND
I/O/FI

MC12-8

I/O/FI

MCll-7
MC11-1

I/O
N/C
N/C
I/O/FI

MC11-8

MC6-3

GND

138

88

87

61

I/O/FI

139

A8

88

62

I/O/FI

MC6-8

140

C8

89

63

I/O/FI

MC6-9

MC8-9

141

C7

90

64

MC7-1

142

A7

91

65

FO

MC2-9

I/O

MC7-2

143

A6

92

66

FO

MC2-8

46

I/O

MC7-3

144

87

93

67

FO

MC2-7

-

-

I/O

MC12-1

145

86

94

-

I/O/FI

MCll-9

F13

69

47

I/O

MC7-4

146

C6

95

68

FO

MC2-6

E15

-

-

I/O

MC12-2

147

A5

-

-

I/O

MC11-2

E14

70

48

I/O

MC7-5

148

85

96

69

FO

D15

-

-

I/O

MC12-3

149

-

-

150

-

MC7-6

151

A4

-

-

I/O

-

I/O

-

I/O

MC12-4

152

A3

97

70

FO

MC2-4

51

I/O

MC6-5

153

84

-

-

I/O

MCll-4

GND
GND

GND

MC6-7

V CC10

MC2-5
N/C
N/C
MCl1-3

114

815

-

-

I/O

MC12-5

154

C5

98

71

FO

MC2-3

115

013

74

52

I/O

MC6-4

155

83

-

-

I/O

MCl1-5

116

C13

75

-

I/O/FI

MC12-9

156

A2

99

72

FO

117

814

76

53

I/O/FI

MC7-7

157

C4

100

73

118

-

-

119
120

A15

77

3- 122

-

MC2-2
VCCINT

-

N/C

158

C3

-

-

I/O

-

N/C

159

82

1

74

O/CKENO

GND

160

Al

2

-

MCll-6
MC5-3

GND

June 1, 1996 (Version 1.0)

~:XILINX
Ordering Information

J TLL

XC73108 - 7 PC 84 C
Device Type ]
Speed

Temperature Range

Number of Pins

L..--_

Package Type

Speed Options

-20
-15
-12
-10
-7

20 ns pin-to-pin delay
15 ns pin-to-pin delay
12 ns pin-to-pin delay
10 ns pin-to-pin delay (commercial and industrial only)
7.5 ns pin-to-pin delay (commercial only)

I

Packaging Options
PC84
84-Pin Plastic Leaded Chip Carrier
WC84
84-Pin Windowed Ceramic Leaded Chip Carrier
PQ100 100-Pin Plastic Quad Flat Pack
PG 144 144-Pin Windowed Pin-Grid-Array
PQ160 160-Pin Plastic Quad Flat Pack
BG225 225-Pin Plastic Ball-Grid-Array
Temperature Options

C
I
M

CommercialO°C to 70°C
Industrial -40°C to 85°C
Military -55°C (Ambient) to 125°C (Case)

Component Availability
Pins

84

Type
Code

XC73108

C =Commercial

-20
-15
-12
-10
-7

100

144

160

225

Plastic
PLCC

Ceramic
CLCC

Plastic
PQFP

Ceramic
PGA

Plastic
PQFP

Plastic
BGA

PC84

WC84

PQ100

PG144

PQ160

BG225

CI
CI
CI
C
C

CI
CI
CI
C
C

CI
CI
CI
C
C

CIM
CIM
CI
C
C

CI
CI
CI
C
C

CI
CI
CI
C
C

=0° to +70°C

June 1, 1996 (Version 1.0)

I = Industrial

=-40° to 85°C

M = Military =-55°C(A) to 125°C (C)

3-123

XC73108108-Macrocell CMOS CPLD

3-124

June 1, 1996 (Version 1.0)

XC73144
144-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

description. To minimize power dissipation, unused Function Blocks are turned off and unused macrocells in used
Function Blocks are configured for low power operation.

•

•
•
•
•
•

•

•
•
•
•
•
•

•
•
•
•

High-performance Complex Programmable Logic
Devices (CPLDs)
- 7.5 ns pin-to-pin speeds on all fast inputs
- Up to 100 MHz maximum clock frequency
100% PCI compliant
18 outputs with 24 mA drive
I/O operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1 A) for 3.3 V ±0.3 V
100% interconnect matrix
- Maximizes resource utilization
- Wire-AND capability via SMARTswitch
High-speed arithmetic carry network
- 1 ns ripple-carry delay per bit
- 43 MHz 16-bit accumulators
Multiple independent clocks
Up to 132 inputs programmable as direct, latched, or
registered
Power management (Jptions
Multiple security bits for design protection
144 macrocells with programmable I/O architecture
Advanced Dual-Block architecture
- 4 Fast Function Blocks
- 12 High-Density Function Blocks
Programmable slew rate
Programmable ground control
0.8 ~ CMOS EPROM technology
Available in 84-pin and 84-pin PLCC/CLCC, 144-pin
PGA, 100-pin and 160-pin PQFP, and 225 BGA
packages

General Description
The XC73144 is a high performance CPLD providing general purpose logic integration. It consists of four PAL-like
24V9 Fast Function Blocks and twelve High Density Function Blocks interconnected by the 1OO%-populated Universal
Interconnect Matrix (UIMTM).

Operating current for each design can be approximated for
specific operating conditions using the following equation:
Icc (mA)=MC HP (2.4) + MC lP (2.1) +
MC (0.015 mA/MHz) f

I

Where:
MC HP = Macrocells in high-performance mode
MC lP
Macrocells in low-power mode
MC

= Total number of macrocells used
= Clock frequency (MHz)

Figure 1 shows a typical power calculation for the XC73144
device, programmed as eight 16-bit counters and operating
at the indicated clock frequency.
500
400

~---t-----,

::?

.s 300
()

..9
-

Ci

hD- ~

~
12

~

~ ~

If

~~: ~~

MC4·8

liFO

~-

~

~

liFO
liFO
,~o

liFO
MC34

liFO

MC~

:;~

-~

~

<

MC3·2

150
3

9

Carry

105
107
109
112
114
123
125
128
116

F14
E15
015
E13
B15
A14
Cll
A12
C13

130
147
151
153
155
158
129
133
145

Bl0
AS
A4
B4
B3
C3
Cl0
All
B6

25
27
33
35
42
34
32
29
37

Ll
N2
M3
P3
Pl
L3
Ml
P2

65
66
83
85

Ml0
L10
L12
K12
Kll
L11
Mll
J12
G12
K9
R1D
P9
M14
N15
Nl0
R12
P12
P13

77
79
82
90
92
95
97
98
101

N12
P14
N14
M15
K14
J13
J15
H14
G13

Mets·,

li

MC16·2

Mcs·e

MC5-9

"0
"0

MCt6-3

vo

Mets·s

MCS·3

"0

IIOIFI

Mets·s

MCS·2

'10

IIOIFI

MC16-9

~ft
",

MCte-S

14-

r----'l-

~

II "l5

Moe-9

MOtS·'

'10
'10
'10
'10

=

MC6-8

MetS·2

MCtS·S

MOS·7

~

!4-

VOl"

MCtS-7

IIO/FI

MOtS·9

~

UIM

"0

~

'10
Me&.4

IIO/FI

MC14-6

~4-

f--'J-

~

QIFOEO

MC7·3

MC7-2

MC14·8

MCt3·S

Moe·s
Mee·7

IIOIFI

MOB-S

°

MOtS-4

Me,,.
MC13-5

MC1lo7
MC1lo8
MC13·9

~
~ -4-

I---'l<-.

MC8·2

-;;-Tr

IT ""
MC12·l
MC12·2
MC12·3

MC12·7

G12
F12

C9
C14
013
Al0
89
A13

140
139
138
135
113
115
136
134
126

812
B13
814
014
E14
F13
G14
F15
G15

124
122
117
111
108
106
104
103
102

C8

A8

~4-

MCS·4
MC9-3
MC9-2

L-ft

B8

FB10

MC10·9

~

~ 2J.-

r----'l-

~

1C~

I/O/FI
'10

r----'l-

~

MCll·,
MCl1·2

MC11·4
MC11·5
MC1Hl
MCtl·7
MC11-$

°

~

MCS·9

MC12·9

'10

--"------

MCS·4

~

II ""
'10

°

MOllo1

II ""

~

OICKENt
OICKENO

;;~
Mee·g

MC14·9

I/OIFI
IIOIFI

IIOIFI
I/O/FI

MC14-5

=

'10

MC14·2

°

""

MC6·2

MC14-3
QIFCLK2

'10

"0

MC7·9

MC14-1

I/OIFI
I/OIFI
I/OIFI

MC6-3

--ft
'"

II ""

K2

62
63
64
86
88
68
71
73
75

~FB16

~ift
AnthmetlcCarry

MC10·4
MC10·3
MC1o-2

~J)

'10
'10

X5653

Figure 2: XC73144 Architecture

3- 126

June 1, 1996 (Version 1.0)

~XILINX
Absolute Maximum Ratings
Symbol

Value

Parameter

Vee
VIN
VTS
T STG

Supply voltage with respect to GND

TSOL

Maximum soldering temperature (10s

-0.5 to 7.0

DC Input voltage with respect to GND
Voltage applied to 3-state output with respect to GND

-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to + 150

Storage temperature
@

1/16 in, = 1.5 mm)

+260

Units
V
V
V
°C
°C

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol

Min

Max

TA = O°C to 70°C
Supply voltage relative to GND Industrial TA = -40°C to 85°C

4.75

5.25

4.5

5.5

Supply voltage relative to GND Military TA = -55°C to T e + 125°C

4.5

5.5

I/O supply voltage relative to GND

3.0

3.6

V IL
V IH

Low-level input voltage
High-level input voltage

0
2.0

0.8

Vo

Output voltage

TIN

Input signal transition time

VeelNT
V eelo
Veelo

Parameter
Supply voltage relative to GND Commercial

50

Units
V
V
V
V
V
V
V
ns

Max

Units

Vee +0.5
Veelo

0

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter
5 V TTL High-level output voltage

VOH
3.3 V High-level output voltage
5 V TTL Low-level output voltage
VOL
3.3 V Low-level output voltage
IlL

Input leakage current

10Z

Output high-Z leakage current

CIN

Input capacitance for Input and I/O pins

CIN

Input capacitance for global control pins
(FCLKO, FCLK1, FCLK2, FOEO, FOE1)

COUT 1
ICC2

Output capacitance

Supply current (low power mode)

Test Conditions
10H = -4.0 mA
VCC = Min
10H = -3.2 mA
VCC= Min
10L =24 mA
VCC = Min
10L = 10 mA
VCC= Min
VCC= Max
VIN = GND or VCCIO
Vce= Max
VIN = GND or VCCIO
VIN=GND
f = 1.0 MHz
VIN = GND

f = 1.0 MHz
VIN = GND

f = 1.0 MHz
VIN = VCC or GND
VCCINT = VCCIO = 5V
f = 1.0 MHz @ 25°C

Min
2.4

V

2.4

V
0.5

V

0.4

V

±10.0

I1A

±10.0

/!A

8.0

pF

12.0

pF

10.0

pF

250Typ

mA

Notes: 1. Sample tested.
2. Measured with device programmed as eight 16-bit counters.

June 1, 1996 (Version 1.0)

3- 127

I

XC73144 144-Macrocell CMOS CPLD

Power-up/Reset Timing Parameters
Symbol

Parameter

tWMR

Master Reset input Low pulse width

tRESET

Configuration completion time

Min

Typ

Max

Units

80

160

iJ-s

100

ns

Slew Rate and Programmable Ground Control
Due to the large number of high current drivers available on
the XC73144, two programmable signal management
features have been included - slew rate control (SRC) and
ground control (GC). Slew rate control is primarily for
external system benefit, to reduce ringing and other
coupling phenomenon. SRC permits designers to select
either 1 VIns or 1.5 VIns slew rate on a pin-by-pin basis for
any output or 1/0 signal. This can be done with PLUSASM
or schematically, as needed. The default slew rate is 1 V/ns.
To assign the pins with equations (PLUSASM), the
designer needs to only declare them as follows:
FAST ON 
This will assign the signals in the list to have a 1.5 V/ns slew
rate. Omitting the signal name list will globally set all signals
to be 1.5 V/ns. Specific signals therefore can be declared
with 1 V/ns slew rate as follows:
FAST OFF 
Schematic control of SRC is also straightforwarc::I. Again,
the default is 1 V/ns, but to assign specific pins fast, the

designer need only attach the "FAST" attribute to the 1/0 or
output buffer or the corresponding pin.
Programmable ground control is useful for internal chip signal management. The output buffers of the Fast Function
Blocks have an impedance of approximately 7 n when
switching high to low, where the High Density Function
Blocks irnpedance is around 14 n. Since this low impedance is negligible compared to the impedance of the pin
inductance when output current transients occur, a reasonable ground connection can be made by driving unused
output pins low and physically attaching them to external
ground. The XC73144 architecture permits the automatic
assignment of external ground signals to all macrocells that
are not declared as primary outputs or 1I0s. Note that the
logical function of the buried macrocell is fully preserved,
while its output driver is driving low and physically attached
to ground. Should designers not wish to employ programmable ground control, they need only declare all such pins
as primary II0s whether they will be attached externally or
not.

Fast Function Block (FFB) External AC Characteristics3

Symbol
fCF
tSUF
tHF

Parameter
Max count frequency ,«, 'I
Fast input setup time before FCLK

t

Fast input hold time after FCLK t

tpDFU

FCLK t to output valid
Fast input to output valid ,«
I/O to output valid 1, 2

tCWF

Fast clock pulse width (High or Low)

tCOF
tpDFO

XC73144-10
(Com Only)
Min
Max

XC73144-12
(Comllnd Only)
Min
Max

105.0

100.0

4.0

5.0

80.0
6.0

0

0

0

XC73144-7
(Com Only)
Min
Max
1

Min
66.7

Max

Units
MHz

7.0

ns

0

ns

5.5

7.0

9.0

12.0

ns

7.5

9.0
17.0

12.0
22.0

15.0
27.0

ns
ns

13.5
4.0

XC73144-15

5.0

5.5

6.0

ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
3. All appropriate AC specifications tested using Figure 3 as the test load circuit
4. Export Control Max. flip-flop toggle rate.

3- 128

June 1, 1996 (Version 1.0)

~XILINX
High-Density Function Block (FB) External AC Characteristics

Symbol

fc

Parameter
Max count frequency 1, ,

110 setup time before FCLK i

tsu
tH

1, ,

110 hold time after FCLK i
FCLK

i

XC73144-10

XC73144-12

(Com Only)

(Com Only)

(Comllnd Only)

Min

Min

Max

110 hold time after p-term clock i

tpco
tpo

110 to output valid ,"

110 setup time before p-term clock i '
P-term clock

i

Max

Min

Max

XC73144-15
Min

Max

Units

83.3

62.5

55.6

45.5

MHz

12.0

13.5

18.0

22.0

ns

0

0

0

0

to output valid

tco
tpsu
tpH

tcw
tpcw

XC73144-7

7.0

9.0

4.0

6.0

7.0

9.0

0

0

0

0

to output valid

ns
15.0

12.0

ns
ns
ns

15.0

19.0

23.0

28.0

ns

18.0

22.0

30.0

36.0

ns

Fast clock pulse width

4.0

5.0

5.5

6.0

ns

P-term clock pulse width

5.0

6.0

7.5

8.5

ns

Notes: 1. This parameter is given for the high-performance mode. In low-power mode, this parameter is increased due to additional
logic delay of tFLOGILP - tFLOGI or t LOGILP - tLOGI'
2. Specifications account for logic paths that use the maximum number of available product terms for a given macroceli.

Fast Function Block (FFB) Internal AC Characteristics
XC73144-7 XC73144-10
Symbol

Parameter

FFB logic array delay
tFLOGILP Low-power FFB logic array delay 1
tFSUI FFB register setup time
FFB register hold time
tFHI
tFCOI FFB register clock-to-output delay
tFPOI FFB register pass through delay
tFAOI FFB register async. set delay
FFB p-term assignment delay
tpTXI
FFB feedback delay
tFFO

(Com Only)

(Com Only)

Min

Min

1.5

tFLOGI

Note:

Max

Max

XC73144-12
(Comllnd Only)

Min

XC73144-15
Min

2.0
7.0

1.5
5.5

3.5

Max

1.5

2.5

3.0

4.0

2.5

2.5

3.0

3.0

Max Units

2.0

ns

8.0

ns
ns
ns

1.0

1.0

1.0

1.0

ns

0.5

0.5

2.0

1.0
4.0

ns
ns

0.8

2.5
1.0

1.0
3.0
1.2

1.5

ns

4.0

5.0

6.5

8.0

ns

1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

June 1, 1996 (Version 1.0)

3- 129

I

XC73144144-Macrocell CMOS CPLD

High-Density Function Block (FB) Internal AC Characteristics
XC73144-7 XC73144-10
Symbol
Parameter
t LOGI FB logic array delay

(Com Only)

Min

Min

Max

3.5
7.0

tLOGILP Low power FB logic delay'
FB register setup time
tSUI

1.5
3.5

FB register hold time

tHI

(Com Only)

FB register clock-to-output delay

tAOI

FB register async. set/reset delay

tRA

Set/reset recovery time before FCLK

tHA

Set/reset hold time after FCLK

tpRA

Set/reset recovery time before p-term clock

tpHA

Set/reset hold time after p-term clock

tpCI

FB p-term clock delay

tOE I

FB p-term output enable delay

FB register pass through delay

t

2.5
3.5

t
t

t

15.0
0
7.5
5.0

Max

3.0
4.0

19.0
0
10.0
6.0

XC73144-15
Min

4.0
9.0

1.0
2.5
3.0

1.0
3.0
5.0
1.0

tCARY8 ALU carry delay within 1 FB ~
tCARYFB Carry lookahead delay per additional
Functional Block 2

Min

3.5
7.5

1.0
1.5
2.5

tCOI
tpDI

Max

XC73144-12
(Comllnd Only)

5.0
11.0
4.0
5.0

1.0
4.0
4.0
21.0
0
12.0
8.0

0
4.0
6.0
1,5

Max Units
ns
ns
ns

1.0
4.0
5.0
25.0
0
15.0
9.0

0
5.0
8.0
2.0

ns

ns
ns
ns
ns
ns
ns
ns

0
7.0
12.0
3.0

ns
ns
ns
ns

Notes: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macrocell(s) for adder with
registered outputs.

1/0 Block External AC Characteristics
Symbol

Parameter

fiN

Max pipeline frequency (input register to FFB
or FB register) 1

tSUIN

Input register/latch setup time before FCLK

tHIN

Input register/latch hold time after FCLK t

tCOIN

FCLK

t

XC73144-7 XC73144-10
(Com Only)
(Com Only)
Min Max Min Max

(Comllnd Only)

Min

Max Units

83.3

62.5

55.6

45.5

MHz

4.0
0

5.0
0

6.0
0

7.0
0

ns

t to input register/latch output

tCESUIN Clock enable setup time before FCLK
tCEHIN Clock enable hold time after FCLK t
tCWHIN FCLK pulse width high time
tCWLlN FCLK pulse width low time

2.5

t

5.0
0
4.0
4.0

XC73144-12
Min

3.5
7.0
0
5.0
5.0

Max

XC73144-15

4.0
8.0
0
5.5
5.5

ns

5.0
10.0
0
6.0
6.0

ns
ns
ns
ns
ns

Note: 1. Specifications account for logic paths that use the maximum number of available product terms for a given macrocell.

3- 130

June 1, 1996 (Version 1.0)

~XILINX
Internal AC Characteristics
XC73144-7 XC73144-10

Symbol
tiN
tFOUT
touT
tUIM
tFOE
tFOD .
tFCLKI

Parameter
Input pad and buffer delay
FFB output buffer and pad delay
FB output buffer and pad delay
Universal Interconnect Matrix delay
FOE input to output valid
FOE input to output disable
Fast clock buffer delay

(Com Only)

(Com Only)

Min

Min

Max
2.5
3.0
4.5
6.0
7.5
7.5
1.5

Max
3.5
4.5
6.5
9.0
10.0
10.0
2.5

XC73144-12
(Comllnd Only)

Min

Max
4.0
5.0
8.0
10.0
12.0
12.0
3.0

XC73144-15

Min

Max Units
5.0
ns
7.0
ns
10.0 ns
12.0 n$
15.0 ns
15.0 ns
4.0
ns

I
Device Output o - - - + - - - - _ - - - C e e ) Test point

r

Device Imput
Rise and Fall
Times < 3 ns

Output Type

1"0

VCCIO
5.0V
3.3 V

VTEST

5.0V
3.3 V

R1
160n
260n

R2
120n

360n

C(
35pF
35pF
X3491

Figure 3: AC Load Circuit

June 1, 1996 (Version 1.0)

3- 131

XC13144144-Macrocell CMOS CPLD

XC73144 Pinouts
BG225 PQ160
03 .
1
E4
F4
C2
F5
G4
81
J4
02
E3
C1
E2
01
F3
F2
E1
G2
G3
F1
G1
H2
H1
H3
J3
K5
J1
K1
J2
K2
K3
L1
L2
M1
N1
M2
L3
N2
P1
M3
N3
K4
L4
P2
M4
L5
R1

-

2
3
4
5
6
7
8
9
10
11
12
13
14
15
. 16
17
18
19
20
21

Input

30
31
32
33
34
35
36

37
38
39
40

Output

VCCIO
liFO
lIFO
0/CKEN1
lIFO
lIFO
lIFO
liFO
O/FOEO

MC3'-4
MC3-2
MC7-4
MC3-1
MC3-5
MC2-1
MC3-3 I
MC7-5
MC7-1
MC7-6
MC7-2

0
0/FOE1
0
VCCINTNpp
IIFI
IIO/FI
IIFI
I/O/FI
I/FI
I/O/FI
IIFI
IIFI
IIFI

MC7-7
MC7-8
MC7-9

GND

MR

IIFI

22
23
24
25
26
27
28
29

XC73144

VCCIO

IIFI
IIFI
IIFI

,

0
IIFI

MC14-1

0
IIFI
IIO/FI
IIFI

MC14-2
MC14-8
GND

IIO/FI
O/FCLKO

MC14-7
MC14-3

0
0/FCLK1
liFO
liFO
liFO
IIO/FI
liFO
liFO

MC14-6
MC14-4
MC1-1
MC4-1
MC4-2
MC14-9
MC4-3
MC4-5
GND

BG225 PQ160
N4
41
P3
42
R2
43
P4
44
N5
45
R3
46
M5
P5
47
R4
48
L6
M6
N6
49
P6
50
R5
51
M7
52
M9
53
P7
54
N7
55
R6
56
R7
57
P8
58
R8
59
N8
60
N9
61
M10
L10
R9
62
R10
63
P9
64
L11
65
M11
66
M12
67
P10
N10
68
R11
69
P11
70
R12
71
R13
72
P12
73
N11
74
P13
75
R14
76
N12
77
N13
78
P14
79
R15
80

Input

XC73144

Output

VCCIO
O/FCLK2
110
liFO
'110

MC14-5
MC6-1
MC1-2
MC6-2
VCCINT

-

liFO'

-

liFO
110
liFO
liFO

MC4-4
. MC1-3
MC6-3
MC4-6
MC4-8
MC1-4
MC6-4

liFO
I/O
GND

MC4-7
MC4-9
MC1-5
MC6-5

liFO
liFO
liFO
I/O
liFO
IIO/FI
I/FO
liFO
liFO

MC1-6
MC6-7
MC1-7
MC1-8
MC1-9
VCCIO
MC13-1
MC13-2
MC12-1
MC12-2
MC12-3
MC13-6
MC13-7

0
0
110
I/O
I/O
0
I/O/FI
GND

MC6-6
MC12-6
MC6-8

110
110
IIO/FI
GND
I/O/FI
IIO/FI
IIO/FI
110
IIO/FI
110
I/O
110
I/O

MC12-7
MC6-9
MC12-8
MC5-1
MC12-9
MC5"2
MC11-1
MC5-3
MC11-2
GND

June 1, 1996 (Ver.sion 1.0)

~XIUNX
XC73144 Pinouts (continued)
BG225

PQ160

M13
L12
K12
N14
K11
J12
P15
G12

81

M14
L13
N15
L14
M15
K13
K14
L15
J14
J13
K15
J15
H14
H15
H13
F11
G13
G15
F15
G14
F14
F13
E15
E14
015
C15
014
E13
C14
B15
013
C13
F12
E12
B14
E11
012
A15

Input

0
0

82

1/0

-

0

83
84
85
86
87

IIOIFI

96
97
98
99
100

103
104
105
106
107
108

MC13-3
MC13-4
MC11-3
MC13-5
MC13-8
MC5-4
MC13-9
MC12-4
MC5-5
MC12-5
MC5-6
MC11-4

1/0
I/OIFI

1/0
1/0
1/0
1/0
1/0
IIOIFI

MC5-7
MC11-5

1/0
IIOIFI

MC5-8
VCCINT

1/0

MC11-6
MC5-9
MC11-7
MC11-8

IIOIFI
IIOIFI
IIOIFI

GND
GND

101
102

Output

V CC10

-

88
89
90
91
92
93
94
95

XC73144

VCCINT

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

109
110
111
112
113
114
115
116

IIOFI

-

0
0

117
118
119
120

IIOIFI

MC11-9
MC10-1
MC10-2
MC10-3

June 1, 1996 (Version 1.0)

GND

0.10
C10
B10
09
07
A11
B9
C9
A10
A9
B8
A8
C8
C7
A7
A6
B7
B6

MC10-6
MC16-4
MC9-5
MC16-5

E5
A4

MC8-1
MC8-2
MC10-7
MC8-6
MC8-7

IIOIFI

121
122
123
124
125
126

C6
.06
E6
A5
B5
05

MC9-4
MC16-9

0

PQ160

C12
B13
A14
B12
C11
A13
011
B11
A12
E10

MC16-1
MC10-4
MC16-2
MC10-5
MC16-3

GND
1/0
1/0
1/0
1/0
1/0

BG225

" A3
B4
C5
04
B3
A2
C4
C3
B2
A1

Input

MC10-8
MC16-6
MC10-9
MC16-7
MC9-1
MC8-3

IIOIFI

110
IIOIFI
IIOIFI

1/0

0

127
128

. IIOIFI

GND

-

0
0

129
130
131

IIOIFI

MC16-8
MC8-4
MC8-5
MC15-7
MC15-1
MC8-8
MC8-9
MC15-8
MC9-2
MC9-6
MC9-3

1/0
IIOIFI

132
l/O/FI
IIOIFI
133
134
1/0
135 '
I/O
136
1/0
137
138
IIOIFI
IIOIFI
139
IIOIFI
140
141
142
liFO
liFO
143
., liFO'
144
145
IIOIFI
146
liFO
liFO
liFO
1/0
147
148
lIFO
149
lIFO
" liFO
150

GND
MC9-7
MC9-8
MC9-9
V CC10

MC2-9
MC2-8
NlC2c7·

•.

... MC15"9
MC2-6

-

151
·152·
153
154

159
160

MQ3-8
MQ3-6
MC15~2

MC2-5
MC3-9
MC3-7
·MC15-3
MC2-4

I/O

liFO·
1/0

MC15-4

liFO

155
156
157
158

Output

V CC10

-

-

XC73144

MC2"3

GND
1/0

MC15-5
MC2-2

liFO
V CC1NT

MC15-6
MC7-3

1/0
O/CKENO

GND

3- 133

I

XC73144144-Macrocell CMOS CPLD

Ordering Information

J IL

XC73144 - 7 PQ 160 C
Device Type

J
Speed

Temperature Range

Number of Pins
'---- Package Type

Speed Options
-15
15 ns pin-to-pin delay
-12
12 ns pin-to-pin delay
-10
10 ns pin-to-pin delay (commercial and industrial only)
-7
7.5 ns pin-to-pin delay (commercial only)
Packaging Options
PQ160 160-Pin Plastic Quad Flat Pack
BG225 225-Pin Plastic Ball-Grid-Array
Temperature Options
C
Commercial O°C to 70°C
I
Industrial -40°C to 85°C

Component Availability
Pins
Type
Code

XC73144

-15
-12
-10
-7

c= Commercial = 00 to +70°C.

3- 134

160
Plastic
PQFP
PQ160
CI
CI
C
C

225
Plastic
BGA
BG225
CI
CI
C
C

1= Industri!ll = -40~.to 85°C .

June 1, 1996 tVersion 1.0)

XC7300 Characterization Data
June 1, 1996 (Version 1.0)
The following section includes typical characterization data
for the XC7354, XC7372 and XC731 08. Frequently consulted timing parameters were characterized under variations in temperature, voltage and number of simultaneously
switching outputs. As demonstrated by the graphical data
presented, all products are well within published data sheet
limits for commercial temperature and voltage ranges.
Though this set of characterization data does not include
explicit information on the XC7318, XC7336 and XC73144,
all XC7300 products are designed using the same circuit
configurations, design rules and process technology.
Therefore, the XC7318, XC7336 and XC73144 timing
parameters· are also safely guard banded with respect to
their published data sheet limits.

t co vs Voltage
XC7354-7 @ 25C 1 Output SWitching

I": I·· .... .. .......... ....... ....... ·1
!

,::r: .•. :.:::::.::

x . . :::: .. :::

4.75 V

:r

5.00 V

I

5.25 V
X7011

Voltage

XC7354

----X_

t co vs Temperature

tsu vs Voltage

10><_
<7041

1

-

1

12

16

20

# Oulputs

X7040

i'::j:::::::':::::::~~~1
June 1, 1996 (Version 1.0)

- - - -- - -

14~.

-8

~

70
X7001

:::::::::::::::::::::::::~..:.-~ -~ ~T

15

~ _;: 1~::: -------: :::::::::: :::::: :: ::: :: j
Temperature

1

25
Te~perature

~::

t HA va Temperature
XC7372-7 @ 5V 1 Output Sw~ching

o

.

o

~ ::1 ::::::::: ::~7::;~~:::: -:: : : j

~ :~: t::::::::::::::::::::::::::::::::
4.75 V

I

J::r:::: .::::::: .~::::: :::1
t PO

I

'C"""."".

I

~X

- - - - - - - - - - - - - - - - - -::::::::

X7039

i HA vs Voltage

X7002

. .'

16

ro

~

5.25

tpo vs Temperature
XC7372-7 @5 V l' Output Switching

12~

o

f: ~

-I

u_

1 .

4.75 V

.,

____________ _

X7QOO

tpDFO vs Voltage
XC7372-7 @25C 1 Output Switching

;:I:::::::::::::::::
:1

~

~

7

- - - - - - - - - - - - - - - - - - - - - - - - - - - -- - - - --

:1----u

~V

-

-

u u

-

u

~--

~V

Volts

-

--

--

-

-

u

-

--

-

-

-,

~V
X7OO3

XC730d Characterization Data

XC7372 (continued)
t POFU vs Temperature

tpOFO vs Temperature
XC7372-7 @5V 1 Output Switching

~
~

,+a: - - - - - - - - ~II

1" --- ---------- ~~- ----------- ----

513 ------------------~--------~ 12 --------~~~----------------11X~---------------------------

I

1

1

1

~

0

~

ro

10

o

ro

~

Temp

t POFO vs # Outputs
XC7372-7 @25C5V

:I--- - _ --> --: - --r
X - -- - --

4

12
# Outputs

8

16

20
X7005

t POFU vs Voltage

":: l~X:" .2~',"'"

X7007

t POFU vs # Outputs

~ l--------- ---------------------I
~

00

Temperature

X7004

~::!
~

:::::7:3~-" .~,.:::::::::

:1

12XI ________~ ________X

::

~
4

- - - -- - - ,-

~
8

_______ :X _______

X

- - - - - - - -: - - - - - - - -1- - - - - - - -

-I

12
# Outputs

16

20
X7008

=_- - _
I

5m 13j~-----------------------X__
.
~

_"":":X-:=: --

-X

12

--: -- - -- - -- -- - - -- - --

::

- - - - - -- - - - -1--: - - - - - - - - -1-- - - - - - - - - -

4.50 V

4.75 V

5.00 V
Volts

3-140

-I

5.25 V
X7006

Jun'e 1,1996 (Version 1.0)

~XILINX
XC73108
tsu vs Voltage
XC73108-7 @ 25C

-------x------------xI

9x-=
~

.s

~ 8
1=

7+---------------~--------------~
4.75 V
5.00 V
5.25 V
X7042
Voltage

teo vs #Outputs SWitching
XC73108-7 @ 25C

il_-x.-~:-~
4

t SU vs Temperature
XC73108-7 @ 5 V

8

12
# Outputs

16

tSUF vs Voltage
XC73108-7 @ 25C

81

i :r------------~--------7+---------------~----------------~

o

25
Temperature

70

4.75 V

X7043

teo vs Voltage
XC73108-7 @25C 1 Output Switching

f- ,n;

-I

--'x

_ -- _ -- _ -- _ -- _ -- -- -- _ -- _ -- -- _ -- _ -- __

3.5
4.75 V

I
5.00 V
Voltage

I

~v

June 1, 1996 (Version 1.0)

70
X7045

~v

Voltage

X7044

:r~------- ~~~------------I
25
Temperature

X7047

•,: I-- ----- --- -;- ------ --_ --I

5.25 V

I: j----------------- --J
o

1
5.25 V

~ :~l- •••••••••••••••••••••••••••••• :• 1

teo vs Temperature
XC73108-7. @ 5 V 1 Output Switching

c

5.00 V
Voltage

1

teoF vs Voltage
XC7310B-7 @25C 1 Output Switching

-.: 1------------------------ -- -----! 41- ----------------~-:-:-- -------

20
X7046

~v
X7046

'teoF vs Temperature
XC73108-7 @5 V 1 Output

f :j--------:----- -- -- -- ---- -- j
,I
-~~I

F

0

25
Temperature

70
X7049

3-141

XC7300 Characterization Data

XC73108 (continued)

j

5.5

~

4.5

~

t HA vs Temperature
XC73108-7 @ 5 V 1 Output Switching

t COF vs #Outputs Switching
XC73108-7 @ 25C
1

------------------------------------x
X
X

I

X~X

3.51

1

1

1

•

4

8

12
#Oulputs

16

20

o

25
. Temperature

~

u

•••

u

••••••

~~

•••••••••••••

1uu.. .. ~ m

15

--------------------

9

F :: _

8.5

70
X7054

tPD vs Voltage
XC73108-7 @25C 1 Output Switching

1"

I ::

-X

9.5

E
i=

---------------~X

::: ------------------------------------I

'I

10

Q)

,."

~.".uuuu

X:7'~-:--:_~_;_;_-_~-_,...__-_~_-....--_--;.:.-)<-.:....-----_
_
-_-__-_-_-_-_-_-_-__

10.5

I

uu.. u. u.. u'1
....
I················~···

X7050

t RA vs Voltage
XC73108-7 @25C

. 1 \~

~ .;:Iu. u.. u. u.. '::'X"

---

-----

U

U

••

·1

••

U.

u1

8~~----------~------------~
4.75 V

5.00 V

5.25 V

4.75 V

tRA vs Temperature
14

'1

XC7310B-7 @ 5 V 1 Output

I

..

:[:: :::::::::::::::::::::::::::~XI
~
:..;..X~1: 1----------------11

u

-

-

--

-

--

-

-

-

-

- - -- - --

u

-1- - - -- - - - - - - - - - - - - -

o

5.00 V
Voltage

X7051

Voltage

25

70

Temperature

X7052

:~!

:[
~

16

___
u

-

:: X:-::
::

-

-

u

X7055

tPDvS Temperature

~~~3_1~~-~ ~_5_~ ~ ~~t~~t_S~~t~h~n~

u

-

-

-

u

-

~ ~ ~ ~ ~ ~ ~u

f----

5.25 V

-

--

-

0

-

c

___

-

-

-

~X.:.:. --

u

-

-

-

I

""'"'XI

-

~~~~~~~~~~~~~~~~~~~~~
-

-

-

:

-

-

--

-

-

-

-

-

25
Temperature

tHA. v~ Voltage
XC7310B-7 @25C

_______

-

-

-

-

-

-

-

-

70
X7056

t PD liS # Outputs
XG7310B-7 @25C5V

"I "~.
'. ---*
f.:Jt,
~
:
:
:
:
~
:
:
.
:
~
~
:i :•:: .:'. ::.,. :1 f:: ::::::::::. :.'~ ~ ~ ~ ~ ~.:::'::.::::::::: j
,,1U .......
u .. __ , . - , . , . u

•

·1

-14

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --

-15

.

4.75 V

3"t42

....
5.00 V
'Voijage

15

-------------------

X

.
5.25 V
X7053

14 I
4

X~

--------------

I'

1

1

B

12
# Outputs

16

20
X7057

June 1,1996 (Version 1.0)

~XILINX
XC73108 (continued)
t PDFU vs Voltage
XC73108-7 @25C 1 Output Switching

t PDFO vs Voltage
XC73108-7 @25C 1 Output Switching

~ I

I

7

1:1"-<1
4.75 V

5.00 V
Voltage

~ :: 1------------- ----------------------I

511j----------------x

!

-----------------------------------1
-----------------------------------

10
9

8

5.25 V

I

4.75 V

~

C

5.00 V
Voltage

X7058

tPDFO vs Temperature
XC731 08-7 @5V 1 Output Switching

g

5.25 V
X7061

tpDFU vs Temperature
XC731 08-7 @5V1 Output Switching

lu-uuuu~x
UUU)I
~-; 11;:I------------------~Xl'
X-:-:=- ----------------------------------------------_X- ---------------u
U
_
U
_
U
U
U
U
U
_
U
U
U
U
_
_
•
"ju_ uUU_U_UU _U U _U __
1
5

,

3

91

I

o

25
Temperature

I

o

70

25
Temperature

X7059

t PDFO VS # Outputs
XC73108-7 @25C 5 V

J-----~
8

X

12

16
# Outputs

June 1, 1996 (Version 1.0)

70
X7062

t PDFU vs # Outputs Switching
XC73108-7 @25C 5 V

! ]------------- _u _________________
X_
~

---------5<

g

::juuuumuuuu_u_uul

1

I ~ ::I~~u~~u-u>~1
20

X7060

4

8

12

# Outputs

16

20
X7063

3-143

XC7300 Characterization Data

3-144

J.une 1, 1996 (Version 1;0)

XC7200 Series Table of Contents

XC7236A 36-Macrocell CMOS CPLD
Features ........................................................................ .
General Description ............................................................... .
Architectural Overview ............................................................. .
FBs and macrocells ......................................................... .
Universal Interconnect Matrix .................................................. .
Outputs ................................................................... .
Inputs .................................................................... .
3.3 V or 5 V Interface configuration ............................................. .
Programming and Using the XC7236A ................................................. .
Absolute Maximum Ratings ......................................................... .
Recommended Operating Conditions .................................................. .
DC Characteristics Over Recommended Operating Conditions .............................. .
AC Timing Requirements ........................................................... .
Propagation Delays ................................................................ .
Incremental Parameters ............................................................ .
Power-up/Reset Timing Parameters ................................................... .
Timing and Delay Path Specifications .................................................. .
Timing and Delay Path Descriptions ............................................. .
XC7372 Pinouts .................................................................. .
Ordering Information ............................................................... .
Component Availability ............................................................. .

3-147
3-147
3-147
3-148
3-149
3-150
3-150
3-150
3-151
3-152
3-152
3-152
3-153
3-154
3-154
3-155
3-156
3-156
3-161
3-162
3-162

I

XC7272A 72-Macrocell CMOS CPLD
Features ........................................................................ .
General Description ............................................................... .
Architectural Overview ............................................................. .
Function Blocks and Macrocells ................................................ .
Universal Interconnect Matrix .................................................. .
Outputs. . . . . . . . . .. . ...................................................... .
Inputs .................................................................... .
Programming and Using the XC7272A ................................................. .
Absolute Maximum Ratings ......................................................... .
Recommended Operating Conditions .................................................. .
DC Characteristics Over Recommended Operating Conditions .............................. .
AC Timing Requirements ........................................................... .
Propagation Delays ................................................................ .
Incremental Parameters ............................................................ .
Power-up/Reset Timing Parameters ................................................... .
Timing and Delay Path Specifications .................................................. .
Timing and Delay Path Descriptions ............................................. .
XC7372 Pinouts .................................................................. .
Ordering Information ............................................................... .
Component Availability, ............................................................ .

3-163
3-163
3-163
3-165
3-166
3-167
3-167
3-167
3-168
3-168
3-168
3-169
3-170
3-170
3-171
3-172
3-172
3-177
3-178
3-178

3-145

XC7200 Series Table of Contents

3-146

XC7236A
36-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

This additional ALU in each macrocell can generate any
combinatorial function of two sums of products, and it can
generate and propagate arithmetic-carry signals between
adjacent macrocells and FBs.

•
•
•

•

•

•
•
•

•
•
•
•

Second-Generation High Density Programmable Logic
Device
UV-erasable CMOS EPROM technology
36 macrocells, grouped into four Function Blocks(FBs),
interconnected by a programmable Universal
Interconnect Matrix
Each FB contains a programmable AND-array with 24
complementary inputs, providing up to 17 product terms
per macrocell
Enhanced logic features:
- 2-input Arithmetic Logic Unit in each macrocell
Dedicated fast carry network between macrocells
- Wide AND capability in the Universal Interconnect
Matrix
Identical timing for all interconnect paths and for all
macrocell logic paths
36 signal pins
- 30 I10s, 2 inputs, 4 outputs
Each input is programmable
- Direct, latched, or registered
1/0 operation at 3.3 V or 5 V
Meets JEDEC Standard (8-1 A) for 3.3 V ± 0.3 V
Three high~speed, low-skew global clock inputs
Available in 44-pin PLCC and CLCC packages

General Description
The XC7236A combines the classical features of the PALlike CPLD architecture with innovative systems-oriented
logic enhancements. This favors the implementation of fast
state machines, large synchronous counters and fast arithmetic, as well as multi-level general-purpose logic. Performance, measured in achievable system clock rate and
critical delays, is not only predictable, but independent of
physical logic mapping, interconnect routing, and resource
utilization. Performance, therefore, remains invariant
between desigq.)terations. The propagation delay through
interconnect alid'iogic is constant for any function implemented in anyone of. the output macrocells.

The Universal Interconnect Matrix (UIM) facilitates unrestricted, fixed-delay interconnects from all device inputs
and macrocell outputs to any FB AND-array input. The UIM
can also perform a logical AND across any number of its
incoming signals on the way to any FB, adding another
level of logic without additional delay. This supports bidirectional loadable synchronous counters of any size up to 36
bits, operating at the specified maximum device frequency
As a result of these logic enhancements, the XC7236A can
deliver high performance even in designs that combine
large numbers of product terms per output, or need more
layers of logic than AND-OR, or need a wide AND function
in some of the product terms, or perform wide arithmetic
functions.

Architectural Overview
Figure 1 shows the XC7236A structure. Four Function
Blocks(FBs) are all interconnected by a central UIM. Each
FB receives 21 signals from the UIM and each FB produces
nine signals back into the UIM. All device inputs are also
routed via the UIM to all FBs. Each FB contains nine output
macrocells .that draw from a programmable AND array
driven by the 21 signals from the UIM. Most macrocells
drive a 3-state chip output. All feed back into the UIM.

The. functional. versatility of the traditional programmable
logic array architecture is enhanced through additional gating and control functions available. in an Arithmetic Logic
Unit (ALU) in each macrocell. Dedicated fast arithmetic
carry lines runnipg directly between adjacent macrocells
and FBs suppor{fast adders, subtractors and comparators
of any length up to 36 bits.

June 1, 1996 (Version 1.0)

3- 147

I

XC7236A 36-Macrocell CMOS CPLD

15

17
18

18

Arithmetic

44

Lee

I

2
3
4
5
6
8
9
10
11

13
14
15
16
18
19
20
21
22

((
110

,-

I

~

I
110
110

'-----~

:--'

Carry

Serial

Shift FB3
FB2

II

44

Lee

I

35
36

MC2-1

MC3-9

IIOIFI

MC2-2

MC3-8

IIOIFI

MC3-7

IIOIFI

37

MC3-6

110

38
40
41
42
43
44

MC2-3
MC2-4
MC2-5

;;:0:
~

;;:
0:
0:

12J.-

~ «

MC3-5

Cl

MC3-4

110

MC3-3

110

~

110

110

MC2-6

Cl

FCLKOIO

MC2-7

FCLK110

MC2-a

'"

FCLK210

MC2-9

110

MC1-1

MC4-9

IIOIFI

110

MC1-2

MC4-8

IIOIFI

110

MC1-3

MC4-7

IIOIFI

110

MC1-4

MC4-6

110

110

MC1-5

110

MC1-6

I/OIFI

MC1-7

IIOIFI
IIOIFI

II

z

z

«

UIM
FB1

FB4

;;:0:

~ 12J.-

'-4-

>«
0:
0:
«
Cl
z
«

MC3-2

va

MC3-1

110

11

24
25
26
27

MC4-5

va

28

MC4-4

110

MC4-3

110

MC1-8

MC4-2

FOEIO

MC1-9

MC4-1

110

30
31
32
33

(~

z«

))

Serial Shift
AnthmetIC Carry

X3492

Figure 1: XC7236A Architecture

FBs and macrocells
The XC7236A contains 36 macrocells with identical structure, grouped into four FBs of nine macrocelis each.
Figure 2 shows the macroceli structure. Each macroceli is
driven by product terms derived from a programmable AND
array in the FB. The AND array in each FB receives 21 signals and their complements from the UIM. In three FBs, the
AND array receives three additional inputs and their complements directly from Fastlnput (FI) pins, thus offering
faster logic paths.
Five product terms are private to each macroceli; an additional 12 product terms are shared among the nine macrocelis in each FB. Four of the private product terms can be
selectively ORed together with up to four of the shared
product terms, and drive the D1 input to the ALU. The other
input, D2, to the ALU is driven by the OR of the fifth private
product term and up to eight of the remaining shared product terms.
As a programmable option, four of the private product
terms can be used for other purposes. One of the private
product terms can be used as a dedicated clock for the flipflop in the macrocell. (See the subsequent description of
other clocking options.) Another one of the private product
terms can be the asynchronous active-High Reset of the
macroceli flip-flop, another one can be the asynchronous
active-High Set of the macroceli flip-flop, and another one
can be the Output Enable signal.
As a configuration option, the macroceli output can be fed
back and ORed into the D2 input to the ALU after being

3- 148

ANDed with three of the shared product terms to implement
counters and toggle flip-flops.
The ALU has two programmable modes. In the logic mode,
it is a 2-input function generator, a 4-bit look-up table, that
can be programmed to generate any Boolean function of its
two inputs. It can OR them, widening the OR function to 17
inputs; it can AND them, which means that one sum of
products can be used to mask the other; it can XOR them,
toggling the flip-flop or comparing the two sums of products. Either or both of the sum-of-product inputs to the ALU
can be inverted and either or both can be ignored. The ALU
can implement one additional layer of logic without any
speed penalty_
In the arithmetic mode, the ALU block in each macroceli
can be programmed to generate the arithmetic sum or difference of two operands, combined with a carry signal coming from the next lower macrocell. It also feeds a carry
output to the next higher macrocell. Thiscarry propagation
chain crosses the boundaries between FBs. This dedicated
carry chain overcomes the inherent speed and density
problems of the tra:ditional CPLD architecture when trying
to perform arithmetic functions.
The ALU output drives the D input of the macroceli flip~flop.
Each flip-flop has several programmable options. One
option is to eliminate the flip-flop by making it transparent,
which makes the Q output identical with the D input, independent of the clock. Otherwise, the flip-flop operates in the

June 1, 1996 (Version 1.0)

~XILINX
AND Array

21
Inputs
from
UIM
Feedback
Enable

Override

I
To a 'More
Macrocells

Arithmetic
Carry-Out to Next
* DE is forced high,when P-term is not used

Macrocell

X1829

Figure 2: FB and macrocell Schematic
conventional manner, triggered by the rising edge on its
clock input.

input pins. Acting as an unrestricted crossbar switch, the
UIM generates 84 output signals, 21 to each FB.

The clock source is programmable and is either the dedicated product term mentioned earlier, or one of two global
FastCLK Signals (FLCKO or FLCK1) that are distributed
with short delay and minimal skew over.the whole chip.

Anyone of the 68 inputs can be programmed to be connected to any number of the 84 outputs. The delay through
the array is constant, independent of the apparent routing
distance, the fan-out, fan-in, or routing complexity.

The asynchronous Set and Reset (Clear) inputs override
the clocked operation. If both asynchronous inputs are
active simultaneously, Reset overrides Set. Upon powerup, each macrocell flip-flop can be pre loaded with either 0
or 1.

Routability is not an issue in that any UIM input can drive
any UIM output or multiple outputs without additional delay.

In addition to driving a chip output pin, the macrocell output
is also routed back as an input to the UIM. One private
product term can be configured to control the Output
Enable of the output pin driver andlor the feedback to the
UIM. If configured to control UIM feedback, when the OE
product-term is de-asserted, the UIM feedback line is
forced High and thus disabled.

Universal Interconnect Matrix
The UIM receives 68 inputs: 36 from the macrocell feedbacks, 30 from bidirectional 1/0 pins, and 2 from dedicated

June 1., 1996 (Version 1.0)

When multiple inputs are programmed to be. connected to
the same.output, this output becomes the AND of the input
signals if the levels are interpreted as active High. By
choosing the appropriate signal inversion at the input pin,
macrocell outputs and FB AND-array input, this AND-logic
can also be used to implement a NAND, OR, or NOR func7
tion. This offers an additional level of logic without any
speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Several such macrocell outputs programmed onto the
same UIM output emulate a 3-state bus line. If one of the
macroceli outputs is enabled, the UIM output assumes that
same level.

3- 149

XC7236A 36-Macrocell CMOS CPLD

Outputs
Thirty-four of the 36 macrocell drive chip outputs directly
through individually programmable inverters followed by 3state output buffers; each can be individually controlled by
the Output Enable product term mentioned above. An additional configuration option disables the output permanently.
One dedicated FastOE input also can be configured to control any of the chip outputs instead of, or in conjunction with,
the individual OE product term.

Inputs
Each signal input to the chip is. programmable as either
direct, latched, or registered in a flip flop. The latch and flipflop can be programmed with either of two FastCLK signals
as latch enable or clock. The two FastCLK signals are
FCLKO and a global choice of either FCLK1 or FCLK2.
Latches are transparent when FastCLK is High, and flipflops clock on the rising edge of FastCLK. Registered
inputs allow high system clock rates by pipelining the inputs
before they incur the combinatorial delay in the device, provided the one-clock-period pipeline latency is acceptable.

The direct, latched, or registered inputs then drive the UIM.
There is no propagation-delay difference between pure
inputs and I/O inputs.

3.3 V or 5 V Interface configuration
The XC7236A can be used in systems with two different
supply voltages, 5 V and 3.3 V. The device has separate
VCC connections to the internal logic and input buffers
(VCCINT) and to the 1/0 output drivers (VCC10 )· VCCINT is
always connected to a nominal +5 V supply, but VCCIO may
be connected to either +5 V or +3.3 V, depending on the
output interface requirement.
When VCCIO is connected to +5 V, the input thresholds are
TTL levels, and thus compatible with 5 V or 3.3 V logic, and
the output high levels are compatible with 5 V systems.
When VCC10 is connected to 3.3 V, the input thresholds are
still TTL levels, and the outputs pull up to the 3.3 V rail. This
makes the XC7236A ideal for interfacing directly to 3.3 V
components. In addition, the output structure is designed
such that the 1/0 can also safely interface to a mixed 3.3-V
and 5-V bus.
Global

,----------------<---,FastOE
Pin

I/O. FCLKlO
and FOE/O

Pins Only

ToUIM - - - - - - -

To Function Block
AND-Array (on

Fastlnput - - - - - - -

FastCLKO

Pins Only)

FastCLK1

Input and
110 Pins Only

FastCLK2

X5338

Figure 3: Input/Output Schematic

3- 150

June 1, 1996 (Version 1.0)

~XILINX
Programming and Using the XC7236A
The features and capabilities described above are used by
the Xilinx development software to program the device
according to the specification given either through schematic entry, or through a behavioral description expressed
in Boolean equations.
The user can specify a security bit that prevents any reading of the programming bit map after the device has been
programmed and verified.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex format. Programming support is available from a number of programmer manufacturers. The
UIM connections and FB AND-array connections are made
directly by non-volatile EPROM cells. Other control bits are
read out of the EPROM array and stored into latches just
after power-up. This method, common among EPLD
devices, requires application of a master-reset signal
delayed at least until Vee has reached the required operating voltage. This can be achieved using a simple capacitor
and pull-up resistor on the MR pin (the RC product should
be larger than twice the Vee rise time). The power-up or
reset signal initiates a self-timed configuration period lasting about 350 Ils (tRESET), during which all device outputs
remain disabled and programmed preload state values are
loaded into the macrocell registers.

June 1, 1996 (Version 1.0)

150

<"

.s
c
~

100

()

75

:;
>-

0.
0.

...

125

I,...- ~
~

~ ~ ~ t::::-

~
j;...-

.....

~

t:; e:

TA = -55°C
TA = 25°C
TA =125°C

~ I-""

50

::J

Cfl

25
0

5

10

15

20

25

30

Frequency (MHz)

35

40

X3255

Figure 4: Typical lee vs. Frequency for XC7236A
configured as sixteen 4·bit counters
(Vee = +5.0 V, VIN = Vee orGND, ali outputs open)

Unused input and 1/0 pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current through
the input pad circuitry.
The recommended decoupling capacitance on the three
Vee pins should total 1 IlF using high-speed (tantalum or
ceramic) capacitors.

3- 151

I

XC7236A 36-Macrocell CMOS CPLD

Absolute Maximum Ratings
Parameter

Symbol
Vee

Supply voltage with respect to GND

VIN
VTS

Value

Units

-0.5 to 7.0

V

DC Input voltage with respect to GND

-0.5 to Vee +0.5

Voltage applied to 3-state output with respect to GND

-0.5 to Vee +0.5
-65 to +150

V
V
°C

+260

°C

TSTG

Storage temperature

TSOL

Maximum soldering temperature (1 Os

@

1/16 in.

= 1.5 mm)

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol
VeeINT/
V eelo
V eelo

Min

Parameter
Supply voltage relative to GND Commercial

T A = O°C to 70°C
Supply voltage relative to OND Industrial TA =-40°C to 85°C
Supply voltage relative to GND Military TA =-55°C to T e + 125°C

V IL

I/O sL!Pply voltage 3.3 V
Low-level input voltage

V IH

High-level input voltage

Vo

Output voltage

4.75

Max
5.25

Units
V

4.5

5.5

V

4.5

5.5

V

3.0

3.6

V

0
2.0

0.8

V
V

Vee +0.5
Veelo

0

V

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter
5 V TTL High-level output voltage

VOH
3.3 V High-level output voltage
5 V TTL Low-level output voltage
VOL
3.3 V Low-level output voltage

Test Conditions
IOH = -4.0 mA
Vee = Min
IOH = -3.2 mA
Vee = Min

Supply current

VIN = 0 V
Vee = Max
f = 0 MHz

IlL

Input leakage current

Vee = Max
VIN = GND or Veelo

loz

Output high-Z leakage current

CIN

Input capacitance (sample tested)

Vee = Max
Vo = GND or Veelo
VIN = GND
f = 1.0 MHz

Max

Units

2.4

V

2.4

V

IOL = 24 mA
Vee = Min
IOL = 24 mA
Vee = Min

Icc

3- 152

Min

0.5

V

0,4

V

126 Typ

mA

-10

+10

JlA

-100

+100

JlA

10

pF

June 1, 1996 (Version 1.0)

~XILINX
AC Timing Requirements
Symbol

Parameter

Fig.

XC7236A-25
Min
Max

XC7236A-20
Min
Max

XC7236A-16
(Com/lnd only)
Min

Max

Max sequential toggle frequency
fcyc
(Note 1) (with feedback) using FastCLK

6

40

50

60

Units
MHz

f CYC1 Max sequential toggle frequency
(Note 1) (with feedback) using a Product-Term Clock

6

40

50

60

MHz

f CYC4 Max macrocell toggle frequency
(Note 2) using local feedback and FastCLK

50

50

60

MHz

Max macrocell register transmission frequency
fClK
(Note 2) (without feedback) using FastCLK

45

50

60

MHz

Max macrocell register transmission frequency
fClK1
(Note 2) (without feedback) using a Product-Term Clock

42

50

60

MHz

fClK2 Max input register transmission frequency
(Note 2) (without feedback) using FastCLK

50

50

60

MHz

7

33

40

60

MHz

11

10

fClK3 Max input register to macrocell register pipeline
(Note 1) frequency using FastCLK
tw
fTOG

FastCLK pulse width (High/Low)

8
50

Export Control Max. flip-flop toggle rate

6
62

ns

83

MHz

tm

Product-term clock pulse width (active/inactive)

11
9

9
24

ns

Input to macrocell register set-up time
before FastCLK

12
29

7

tsu

18

ns

tH

Input to macrocell register hold time
after FastCLK

9

-7

-4

-4

ns

8

16

14

10

ns

Input to macrocell register set-up time
tSU1
(Note 1) before Product-term clock
tH1

Input to macrocell register hold time
after Product-term clock

8

0

0

0

ns

tSU2

Input to register/latch set-up time
before FastLCK

10

8

8

6

ns

tH2

Input to register/latch hold time
after FastLCK

10

0

0

0

ns

tsus

Fastlnput to macrocell register set-up time
before FastCLK

20

18

15

ns

tHs

Fastlnput to macrocell register hold time
after FastCLK

0

a

a

ns

tWA

Set/Reset pulse width (active)

tRA

Set/Reset input recovery set-up time
before FastCLK

11
11

12
30

12
25

10
20

ns

tHA

Set/Reset input hold time
after FastCLK

11

-5

a

a

ns

tRA1

Set/Reset input recovery set-up time
before Product-term clock

11

15

15

12

ns

tHA1

Set/Reset input hold time
after Product-term clock

11

9

9

8

ns

tHRS

Product-term clock width (active/inactive)

10

10

8

ns

ns

Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the AlU.
2. Not tested but derived from appropriate pulse-widths, set-up time and hold-time measurements.

June 1, 1996 (Version 1.0)

3- 153

I

XC7236A36·Macrocell CMOS CPLD

Propagation Delays

Symbol

Parameter

teo

FastCLK input to registered output delay

te01

P-term clock input to registered output delay
SeVReset input to registered output delay

tAO
tpD
(Note

Input to non-registered output delay

XC7236A·16
(Com/lnd only)

XC7236A·25

XC7236A-20

Fig.

Min

Max

Min

Max

Min

Max

Units

11
11
11
11

5
10
10
10

14
30
40
40

3
5
5
5

13
24
32
32

3
5
5
5

10
20
25
25

ns

11
11

10
10
10

32
32
31

5
5
5

25
25
25

5
5
5

20
20
20

ns

5
5
5
5

23
23
15
15

3
3
3
3

20
20
14
14

3
3
3
3

15
15
12
12

ns
ns
ns

1)

tOE

Input to output enable

tOD

Input to output disable

tpD5

Fastlnput to non-registered macrocell
output delay

tOE5
t OD5

Fastlnput to output enable

tFOE

FOE input to output enable

tFOD

FaD input to output disable

Note:

Fastlnput to output disable

ns
ns
ns
ns
ns
ns

1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.

Incremental Parameters

Parameter

XC7236A·20

Min

Min

Max

Units

1.2

1.2

1

ns

12

6

5

3

ns

t pDT9 Arithmetic carry delay through 10 macrocells
(Note 2) from macrocell #n to macrocell #n in next FB

12

9

6

4

ns

Incremental delay from UIM-input (for P-term
clock) to registered macrocell feedback

13

12

7

5

ns

teoF2 Incremental delay from FastCLK net to
(Note 3) latched/registered UIM-input

13

1

1

1

ns

Incremental delay from UIM-input to
tpDF
(Note 1) non-registered macrocell feedback

13

22

14

10

ns

tpDT1
(Note 2)

Arithmetic carry delay
between adjacent macrocells

tpDTS Arithmetic carry delay through
(Note 2) macrocells in a FB

teoF1

9 adjacent

Max

XC7236A·16
(Comllnd only)

12

Symbol

Fig.

XC7236A-25

Max

Min

tAOF

Incremental delay from UIM-input (SeVReset) to
registered macrocell feedback

13

22

14

10

ns

tOEF
tODF

Incremental delay from UIM-input (used as output-enable/disable) to macrocell feedback

13

14

7

5

ns

13

18

18

15

ns

tlN+ tOUT Propagation delay
(Note 4) through unregistered input pad (to UIM)
plus output pad driver (from macrocell)

Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the. ALU:
2. Arithmetic carry delays are measured as the increase in required set-up time to adjacent macroCell(s) for an adder with
registered outputs.
3. Parameter tCOF2 is derived as the difference between the clock period for pipelininginput-to-macrocell registers (1/fcLK3 ) and
the non-registered input set-up time (tsU)'
4. Parameter tiN represents the delay from an input or 1/0 pin to a UIM-input (or from a FastCLK pin to the Fast CI:.K net); loUT
represents the delay from a macrocell output (feedback point) to an output orllO pin. Only the sum of ~N + tOUT can be
derived from measurements, e.g., tiN + tOUT = tsu + tco - l/fCyc·

3- 154

June

1, 1996 (Version 1.0)

~XILINX
Power-up/Reset Timing Parameters
Symbol

Parameter

tWMR

Master Reset input Low pulse width

trvee

Vee rise time (if MR not used for power-up)

tRESET

Configuration completion time (to outputs operational)

Min

Typ

Max

Units

5

Jls

1000

Jls

100

ns
350

Note: Due to the synchronous operation of the power-up reset and the wide range of ways Vee can rise to its steady state, Vee rise
must be monotonic. Following reset, the Clock, Reset and Set inputs must not be asserted until all applicable input and
feedback set-up times are mel.

I
Device Output

0 - -.....-----<1>----00.

Test Point

Device Imput
Rise and Fall

Times < 3 ns

X3489

Figure 5: AC Load Circuit

June 1, 1996 (Version 1.0)

3-155

XC7236A 36,Macrocell CMOS CPlD

Timing and Delay Path Specifications
The delay path consists of three blocks that can be connected in series:

Figure 8 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register.

•
•
•

Figure 9 defines the set-up and hold times from the data
inputs to the FastGLK used by the output register.

Input Buffer and associated latch or register
Logic Resource (UIM, AND-array and macrocell)
Three-state Output Buffer

All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.

Timing and Delay Path Descriptions
Figure 6 defines the maximum clock frequency (with feedback). Any macrocell output can be fed back to the UIM as
an input for the next clock cycle. Figure 6 shows the relevant delay path. The parameters fCYC and fCYC1 specify
the maximum operating frequency for FastGLK and product-term clock operation respectively.
Figure 7 specifies the max operating frequency (fClK3 ) for
pipelined operation between the input registers and the
macrocell registers, using FastGLK.
UIM

Figure 10 defines the set-up and hold times from the data
input to the FastGLK used in an input register.
Figure 11 shows the waveforms for the macrocell and control paths
Figure 12 defines the carry propagation delays between
macrocells and between FBs. The parameters describe the
delay from the GIN' D1 and D2 inputs of a macrocell ALU to
the GIN input of the adjacent macrocell ALU. These delays
must be added to the standard macrocell delay path (t pD or
tSU ) to determine the performance of an arithmetic function.
Figure 13 defines the incremental parameters for the standard macrocell logic paths. These incremental parameters
are used in conjunction with pin-to-pin parameters when
calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.

Function Block

Output or
1/0 Pin

Input or
1/0 Pin

J .~___

1_/fC_Y_C....,,/ICYC,

FASTClK or
Product Term Clock

~/

\

1_____

6

'--------'

X3279

Figure 6: Delay Path Specification for fCYC and f CYC1

3- 156

June 1, 1996 (Version 1.0)

~XIUNX

UIM

Input or
I/O Pin

Function Block

Output or
1/0 Pin

..
.. ..

FASTClK
Pin

1/fClK3

I...

FASTClK

~

~
X

j)

\

I

/'"

Input-Pad
Register Output

X3280

Figure 7: Delay Path Specification for fCLK3

UIM

Function Block

Input or
1/0 Pin

Output or
1/0 Pin

Input or
1/0 Pin

i

Clock
Output

---------ts-U-1---

I~fou~~~

tH1

xxxf,------o-a-ta----c-hxxx
X3281

Figure 8: Delay Path Specification for fSU1 and fH1

June 1, 1996 (Version 1.0)

3- 157

XC7236A 36-Macrocell CMOS CPLD

Function Block

UIM

"-----'__, Output or
1/0 Pin

Input or
1/0 Pin

FASTCLK
Pin

r

FASTCLK
Input

tsu
Input or
1/0 Pin

xxJ-oata----.fu§ik
X3282

Figure 9: Delay Path Specification for fsu and fH

UIM

Input or
1/0 Pin

Input-Pad
Register
:>---..... 0
Q

• • • _ _ _ • •1

FASTCLK
Pin

FASTCLK
Pin

..
Input or
1/0 Pin

Data
X3283

Figure 10: Delay Path Specification for fSU2 and fH2

3- 158

June 1, 1996 (Version 1.0)

~XILINX

* tSU2 and tH2 are measured with respect to the high-going

Registered
Inputs

edge of FastCLK for registered inputs, and with respect to
the low-going edge of FastCLK for latched inputs. Only the
high going edge is used for clocking the macrocell registers.

FastCLK

Input Used
as Clock

)I(

Active
•

.1

tsu

................ -----------., ,.----1. , - - - - .

________________________ -----1

Inactive

•tWA

-tH

tSUt,~

Unlatched
Inputs

-~

j~
"''''''':x'''':xIrlJ('''~1\Ir-V-a-lid-D-i-sa-b-Ie--'

I.
Non-Registered
Outputs

Active
tHA1

____

t~D

'--__
V_al_id_E_n_a_bl_e_---J

Valid ReseUSet

..

.

~

.

Inactive
tRAt

Active

•

ReseUSet
De-Asserted

too

~_+-- ~)K~_.------J.r---~~__--~------------------__

-

....
Registered
Outputs

~

teOt

,..-----------..
X3284

Figure 11: Principal Pin·to·Pin Measurements

AO

A1

AS

A9

Figure 12: ArithmeticTiming Parameters

June 1, 1996 (Version 1.0)

3- 159

XC7236A 36-Macrocell CMOS CPLD

UIM

Function Block

Output or
1/0 Pin
Input or
110 Pin

Input or
1/0 Pin

Output or
1/0 Pin

Input or
1/0 Pin

Output or
1/0 Pin

FASTCLK
Pin

X3288

Figure 13: Incremental Timing Parameters

3- 160

June 1, 1996 (Version 1.0)

~XILINX
XC7372 Pinouts
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

Input
Master Reset
Input
Input

Output
vpp
MC2-1

Input
Input
Input

MC2-4
MC2-5
GND

Input
FastCLKO
FastCLK1
FastCLK2

MC2-6
MC2-7
MC2-8
MC2-9
VCCIO

Input
Input
Input
Input

MC1-1
MC1-2
MC1-3
MC1-4
GND

Input
Input
InputiFI
InputiFI
InputiFI

June 1, 1996 (Version 1.0)

MC1-5
MC1-6
MC1-7
MC1-8
MC1-9

Pint
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

Input

Output
VCCIO

InputlFI
InputiFI

MC4-9
MC4-8
MC4-7
MC4-6

InputlFI
Input
Input

MC4-5
GND
MC4-4
MC4-3
MC4-2
MC4-1

Input
Input
FastOE
Input

------

VCCINT
InputlFI
InputiFI
InputlFI
Input

MC3-9
MC3-8
MC3-7
MC3-6
GND

Input
Input
Input
Input
Input

MC3-5
MC3-4
MC3-3
MC3-2
MC3-1

3- 161

I

XC7236A 36-Macrocell CMOS CPLD

Ordering Information

j

XC7236A - 16 PC 44 C
Device Type ]

TL
L

Speed

Temperalure Range

Number of Pins

" - - - Package Type
Speed Options

-25
-20
-16

25 ns (40 MHz) sequential cycle time
20 ns (50 MHz) sequential cycle time
16 ns (60 MHz) sequential cycle time (commercial/industrial only)

Packaging Options
PC44
44-Pin Plastic Leaded Chip Carrier
WC44
44-Pin Windowed Ceramic Leaded Chip Carrier
Temperature Options

C
I
M

CommercialO°C to 70°C
Industrial -40°C to 85°C
Military -55°C (Ambient) to 125°C (Case)

Component Availability
44

Pins
Type
Code

Plastic
PLCC
PC44

Ceramic
CLCC
WC44

CI
CI
CI

CIM
CIM
CI

XC7236A

-25
-20
-16

C = Commercial = 0° to +70°C

I = Industrial = -40° to 85°C

3- 162

M = Military = -55°C(A) to 125°C (C)

June 1, 1996 (Version 1.0)

XC7272A
72-Macrocell CMOS CPLD
June 1, 1996 (Version 1.0)

Product Specification

Features

This additional ALU in each macrocell can generate any
combinatorial function of two sums of products, and it can
generate and propagate arithmetic-carry signals between
adjacent macrocells and Functional Blocks.

•
•
•

•

•

•
•
•
•
•
•

Second-Generation High Density Programmable Logic
Device
UV-erasable CMOS EPROM technology
72 macrocells, grouped into eight Function Blocks
(FBs), interconnected by a programmable Universal
Interconnect Matrix
Each FB contains a programmable AND-array with 21
complementary inputs, providing up to 16 product terms
per macrocell
Enhanced logic features:
2-input Arithmetic Logic Unit in each macrocell
- Dedicated fast carry network between macrocells
Wide AND capability in the Universal Interconnect
Matrix
Identical timing for all interconnect paths and for all
macrocell logic paths
72 signal pins in the 84-pin packages
- 42 1I0s, 12 inputs, 18 outputs
Each input is programmable
- Direct, latched, or registered
I/O-pin is usable as input when macrocell is buried
Two high-speed, low-skew global clock inputs
Available in 68-pin and 84-pin PLCC/CLCC, 84-pin PGA
packages

General Description
The XC7272A combines the classical features of the PALlike CPLD architecture with innovative systems-oriented
logic enhancements. This favors the implementation of fast
state machines, large synchronous counters and fast arithmetic, as well as multi-level general-purpose logic. Performance, measured in achievable system clock rate and
critical delays, is not only predictable,· but independent of
physical logic mapping, interconnect routing, and resource
utilization. Performance,· therefore, remains invariant
between design iterations. The propagation delay through
interconnect and logic is constant for any function implemented in anyone of the output macrocells.

The Universal Interconnect Matrix (UIM) facilitates unrestricted, fixed-delay interconnects from all device inputs
and macrocell outputs to any Function Block AND-array
input. The UIM can also perform a logical AND across any
number of its incoming signals on the way to any Functional
Block, adding another level of logic without additional delay.
This supports bidirectionalloadable synchronous counters
of any size up to 72 bits, operating at the specified maximum device frequency
As a result of these logic enhancements, the XC7272A can
deliver high performance even in designs that combine
large numbers of product terms per output, or need more
layers of logic than AND-OR, or need a wide AND function
in some of the product terms, or perform wide arithmetic
functions.

Architectural Overview
Figure 1 shows the XC7272A structure. Eight Function
Blocks(FBs) are all interconnected by a central UIM. Each
FB receives 21 signals from the UIM.andeach FB produces
nine signals back into the UIM. All device inputs are also
routed via the UIM to all FBs. Each FB contains nine output
macrocells that draw from a programmable AND array
driven by the 21 signals from the UIM. Most Macro-cells
drive a 3-state chip output. All feed back into the UIM.

The functional versatility of the traditional programmable
logic array architecture is enhanced through additional gating and control functions available in an Arithmetic Logic
Unit (ALU) in each macrocell. Dedicated fast arithmetic
carry lines running directly between adjacent macrocells
and FBs support fast adders, subtractors and comparators
of any length up to 72 bits.

June 1, 1996 (Version 1.0)

3- 163

I

XC7272A 72·Macrocell CMOS CPLD

1-1-1- --1-1-1- -1-1-1l l II

l

l

l

l

l

l12

20

22
36

68

84

Lee Lee

i 12i

[10]
[9]
[8]
[7]

11
1.0
9

rj

Arithmetic

r

1/0

~

MC4-1

110

~

MC4-2

FCLKlO

MC4-3

FCLKlO

MC4-4
MC4-5
MC4·6

MC4-7

36

FB4

Carry

MC5-9
MC5-8

~
a:

~

Q

>«
a:
a:
~ «

1..1J.-

Q

z

z
«

«

MC4-8
MC4-9

[14]
[13]
[12]
[11]

21
20
19
18
16
15
14
13

[26]
[25]
[24]
[23]
[22]
[20]
[19]
[18]
[17]

32
31
30
29
28
26
25
24
23

[34]
[33]
[32]
[30]
[29]
[28]
[27]

42
41
40
39
38
36
35
34
33

JI

I

I

FB5

MC5-6

FB6

MC5-4

1/0

MC5-2

1/0
1/0

MC6-9
MC6-8

MC3-4
MC3-5
MC3-6
MC3-7

~

~ 1..1J.-

a:
a:
--<}-. «
Q

z
«

z

«

MC3-8

//

MC6-7
MC6-6
MC6-5
MC6-4
MC6-3
MC6-2

MC3-9

MC6-1
FB2

FB7

0
0
0
0
0
0
0
0

11

MC2-1

MC7-9

1/0

MC2-2

MC7-8
MC7-7

1/0
1/0

MC7-6

1/0

MC7-5

1/0

MC2-3

1/0

MC2-4

1/0
1/0
1/0

MC2-5
MC2-7

MC7-3

1/0
1/0
1/0

1/0

MC2-8

MC7-2

110

1/0

MC2-9

MC7-1

1/0

1/0

MC2-6

IJ

~

'"

1..1J.-

z
«

'"

FBl

FB8

MC7·4

11

MC1-1

MC8-9

1/0

1/0

MCl-2

MC8-8

1/0

1/0
1/0

MCl-3

Mea-?

110

MCl-4

MC8-6

1/0

MCl-5

a:
a:

--<}-. «

MC8-5

1/0
1/0

1/0

MCl-6

MC8-4

1/0

110

MCl-7

'«z"

1/0

MCl-8

1/0

f-----'

f-----'

*:P in not present on 68 Lee

>«
a:

>«

~ 1..1J.z
«

~

MC8-3

110

MC8-2

1/0
1/0

MC8-1

MCl-9

Arithmetic Carry

[60]
[61]
[62]
[63]

65
66
67

[55]
[56]
[57]
[58]

70
71
72
73

110

>«
a:
a:
--<}-. «
z
«

i

74
75
76
77

68

1/0

>«
a:

68

Lee

11

MC3-1

>«
a:

1/0

MC5-3

MC3-2
MC3-3

j

MC5-5

MC5-1

UIM
FB3

84
Lee

MC5-7

54
55
56
57
58
60
61
62
63

[44]
[45]
[46]
[47]
[48]
[50]
[51]
[52]
[53]

44
45
46
47
48
50
51
52
53

[36]
[37]
[38]
[40]
[41]
[42]
[43]

)
X3493

Figure 1: XC7272A Architecture

3- 164

June 1, 1996 (Version 1.0)

1:XIUNX
Function Blocks and Macrocells
The XC7272A contains 72 identical macrocells, grouped
into eight FBs of nine macrocells each. Each macrocell is
driven by product terms derived from the 21 inputs from the
UIM into the Function Block. Figure 2 shows the macrocell
structure.
Five product terms are private to each macrocell; an additional 12 product terms are shared among the nine macrocells in any Function Block. One private product term is a
dedicated clock for the flip-flop in the macrocell.
The remaining four private product terms can be selectively
ORed together with up to three of the shared product
terms, to drive one input to an Arithmetic Logic Unit (ALU).
The other input tethe ALU is driven by the OR of up-to-nine
product terms from the remaining shared product terms.
As a programmable option, two of the private product terms
can be used for other purposes. One is the asynchronous
active-High Reset of the macroceU flip-flop, the other can
be either an asynchronous active-High Set of the macrocell
flip~flop, or provide an active-High Output-Enable signal
from any one of the Function Block inputs.

The ALU has two programmable modes. In the logic mode,
it is a 2-input function generator, a 4-bit look-up table, that
can be programmed to generate any Boolean function of its
two inputs. It can OR them, widening the OR function to 16
inputs; it can AND them, which means that one sum of
products can be used to mask the other; it can XOR them,
toggling the flip-flop or comparing the two sums of products. Either or both of the sum-of-product inputs to the ALU
can be inverted, and either or both can be ignored. The
ALU can implement one additional layer of logic without
any speed penalty.
In the arithmetic mode, the ALU block can be programmed
to generate the arithmetic sum or difference of tw() operands, combined with a carry signal coming from the lower
macrocel1; it also feeds a carry output to the next higher
macrocell. This carry propagation chain crosses the boundaries between FBs, but it can al.so be configured as a 0 or 1
when it enters a Function Block.
This dedicated carry chain overcomes the inherent speed
and density problems of the traditional CPLD architecture;
when trying to perform arithmetic functions like add, subtract, and magn"itude compare. "

One Function I

Arithmetic Carry-In from
Previous Macrocell

3

• OE is forced high when P-term is not used

Arithmetic
Gerry-Out to NeXt
Macrocell

X5490

Figure 2: Function Block and MacroceU Schematic

Junet, 1996 (Version 1.0)

3-165

I

XC7272A 72-Macrocell CMOS CPLD

The ALU output drives the D input of the macrocell flip-flop.

Universal Interconnect Matrix

Each flip-flop has several programmable options:

The UIM receives 126 inputs: 72 from the 72 macrocelis, 42
from bidirectional 110 pins, and 12 from dedicated input
pins. Acting as an unrestricted crossbar switch, the UIM
generates 168 output signals, 21 to each Function Block.

One option is to eliminate the flip-flop by making it transparent, which. makes the .Q output identical with the D input,
independent of the clock.
If this option is not programmed, the flip-flop operates in the
conventional manner, triggered by the rising edge on its
clock input.
The clock source is programmable: It is either the dedicated product term mentioned above, or it is one of the two
global FastCLK signals that !3,re distributed with short delay
and minimal skew over th$. whole chip.
The asynGhronous Set and Reset (Clear) inputs override
the clocked operation. If. both asynchronous inputs are
active simultaneously, Reset overrides Set. Upon powerup, each macrocell flip-flop can be preloaded with either 0
or 1.
.
In addition to driving the chip output buffer,the maqroceli
output is also routed back as an input to the UIM. When the
Output Enable product term mentioned above is not active,
this feedback line is forced High and thus disabled.

Anyone of the 126 inputs can be programmed to tie connected to any number of the 168 outputs. The delay
through the array is constant, independent of the apparent
routing distance, the fan-out, fan-in, or routing complexity.
Routability is not an issue: Any UIMinput can drive anyUIM
output, even multiple outputs, and the delay is constant.
When multiple inputs are programmed to be connected to
the same output, this output becomes the AND of the input
signals if the levels are interpreted as active High. By
choosing the appropriate signal inversion in the macroceli
outputs and the Function Block AND-array input, this ANDlogic can also be used to implement a NAND, OR, or NOR
function, thus offering an additional level of logic without
any speed penalty.
A macrocell feedback signal that is disabled by the output
enable product term represents a High input to the UIM.
Several such macroceli outputs programmed onto the
same UIM output emulate a 3-state bus line. If one of the
macroceli outputs is enabled, the UIM output assumes that
same level.

Macrocell

Feedback
to UIM - - - - - - ' - - - - '
To UIM - - - - - - - ' - - -

FastCLKl
FastCLKO
Inpuland

1/0 Pins Only

X5339

Figure 3: Input/Output Schematic

3-166

June 1, 1996 (Version 1;0)

~:XILINX
schematic entry, or through a behavioral description
expressed in Boolean equations.

Outputs
Sixty of the 72 macrocells drive chip outputs directly
through 3-state output buffers, each individually controlled
by the Output Enable product term mentioned above. For
bidirectional 1/0 pins, an additional programmable cell can
optionally disable the output permanently. The buried flipflop is then still available for internal feedback, and the pin
can still be used as a separate input

The user can specify a security bit that prevents any reading of the programming bit map after the device has been
programmed and verified.
The device is programmed in a manner similar to an
EPROM (ultra-violet light erasable read-only memory)
using the Intel Hex or JEDEC format. Programming support
is available from a number of programmer manufacturers.
The UIM connections and Function Block AND-array connections are made directly by non-volatile EPROM cells.
Other control bits are read out of the EPROM array and
stored into latches just after power-up. This method, common among CPLD devices, requires either a very fast Vee
rise time «5 Ils) or the application of a master-reset signal
delayed at least until Vee has reached the required operating voltage. The latter can be achieved using a simple
capacitor and pull-up resistor on the MR pin (the RC product should be larger than twice the Vee rise time). The
power-up or reset signal initiates a self-timed configuration
period lasting about 350 Ils (tRESET), during which all
device outputs remain disabled and programmed preload
state values are loaded into the macrocell registers.

Inputs
Each signal input to the chip is programmable as either
direct, latched, or registered in a flip-flop. The latch and flipflop can be programmed with either of the two FastCLK signals as latch enable or clock. The latch is transparent when
FastCLK is High, and the flip-flop clocks on the rising edge
of FastCLK. Registered inputs allow high system clock
rates by pipelining the inputs before they incur the combinatorial delay in the device, in cases where a pipeline cycle is
acceptable.
The direct, latched, or registered inputs then drive the UIM.
There is no propagation-delay difference between pure
inputs and 1/0 inputs.

Programming and Using the
XC7272A

Unused input and 1/0 pins should be tied to ground or Vcc
or some valid logic level. This is common practice for all
CMOS devices to avoid dissipating excess current through
the input-pad circuitry.

The features and capabilities described above are used by
the Xilinx XACTstep development software to program the
device according to the specification given either through

The recommended decoupling capacitance on the three
Vee pins should total 1 IlF using high-speed (tantalum or
ceramic) capacitors.

350
TA = -55°C
300 f---+--+--+--+--+---d._""""I~o....I T A = 25°e
TA = 125°C

:;(

250

-S
C
~

200

:;
(J

>.

150

"

100

a.
Q.
C/)

50

0

5

10

15

20

25

eount Frequency (MHz)

30

35

40
X3254

Figure 4: Typical lee vs. Frequency for XC7272A configured as sixteen 4-bit counters
(Vee =+5.0 V, VIN =Vee or GND, all outputs open)

June 1, 1996 (Version 1.0)

3-167

I

XC7272A 72-Macrocell CMOS CPLD

Absolute Maximum Ratings
Symbol
Vee
VIN
VTS
T STG
TSOL

Parameter
Supply voltage with respect to GND
DC Input voltage with respect to GND
Voltage applied to 3-state output with respect to GND
Storage temperature

Value

Units

-0.5 to Vee +0.5

V

-0.5 to Vee +0.5
-0.5 to 7.0

V

-65 to +150

°C

+260

°C

Maximum soldering temperature (10s @ 1/16 in. = 1.5 mm)

V

Warning: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

Recommended Operating Conditions
Symbol

Parameter
Supply voltage relative to GND Commercial

Min

TA = O°C to 70°C
Supply voltage relative to GND Industrial T A = -40°C to 85°C

4.75

Max
5.25

Units
V

4.5

5.5

V

4.5

5.5

V

V IH

Supply voltage relative to GND Military TA = -55°C to T e + 125°C
High-level input voltage

2.0

V

V IL

Low-level input voltage

Vee +0.5
0.8

V

Max

Units

VeelNTI
Veelo

0

DC Characteristics Over Recommended Operating Conditions
Symbol

Parameter

V OH

TTL High-level output voltage

VOL

TTL Low-level output voltage

lee

Supply current

IlL
loz
C IN

3- 168

Test Conditions
IOH = -4.0 mA
Vee Min
IOL = 8 rnA
Vee = Min
VIN = 0 V
Vee = Max
f = 0 MHz

=

Min

0.5

222 Typ

Input leakage current

-10

Output high-Z leakage current

-100

Input capacitance (sample tested)

V

2.4

V

mA

+10
+100

j.lA

10

pF

j.lA

June 1, 1996 (Version 1.0)

~:XILINX
AC Timing Requirements
Parameter
Max sequential toggle frequency
fCYC
(Note 1) (with feedback) using FastCLK
Symbol

Fig.

XC7272A-25

XC7272A-20

Min

Min

Max

Max

XC7272A-16
(Comllnd only)

Min

Max

Units

40

50

55

MHz

fCYCI Max sequential toggle frequency
(Note 1) (with feedback) using a Product-Term Clock

40

50

55

MHz

Max macrocell register transmission frequency
fClK
(Note 2) (without feedback) using FastCLK

40

50

55

MHz

Max macrocell register transmission frequency
fClKI
(Note 2) (without feedback) using a Product-Term Clock

40

50

55

MHz

fCLK2 Max input register transmission frequency
(Note 2) (without feedback) using FastCLK

67

67

67

MHz

7

40

50

60

MHz

11
11

7.5
7.5

7.5
7.5

6
6

ns

fCLK3 Max input register to macrocell register pipeline
(Note 1) frequency using FastCLK
FastCLK Low pulse width
tWL
tWH

FastCLK High pulse width

fTOG

Export Control Max. flip-flop toggle rate

tWI

Product-term clock pulse width .(active/inactive)
Input to macrocell register set-up time
before FastCLK

11
9

10
24

9
19

7
15

ns
ns

Input to macrocell register hold time
after FastCLK

9

-7

-4

-4

ns

8

10

8

6

ns

tsu
tH

Input to macrocell register set-up time
tSUI
(Note 1) before Product-term clock

67

ns

83

67

MHz

tHI

Input to macrocell register hold time
after Product-term clock

8

0

0

0

ns

tSU2

Input to register/latch set-up time
before FastLCK

10

8

8

6

ns

tH2

Input to register/latch hold time
after FastLCK

10

0

0

0

ns

tWA

Set/Reset pulse width

tRA

Set/Reset input recovery set-up time
before FastCLK

11
11

12
20

10
20

8
16

ns

tHA

Set/Reset input hold time
after FastCLK

11

-5

-3

-3

ns

tRAI

Set/Reset input recovery set-up time
before Product-term clock

11

6

5

4

ns

tHAt

Set/Reset input hold time
after Product-term clock
Set/Reset input hold time
after Reset/Set inactive

11

9

8

6

ns

10

8

6

ns

tHRS

ns

Notes: 1. Spec1fications account for logic paths that use the maximum number of available product terms and the ALU.
2. Not tested but derived from appropriate pulse-widths, set-up time and hold,time measurements.

June 1, 1996 (Version 1.0)

3- 169

I

XC7272A 72·Macrocell CMOS CPLD

Propagation Delays

Symbol

Parameter
FastCLK input to registered output delay

teo

P·term clock input to registered output delay

teo1
SeVReset input to registered output delay
tAO
Input to non· registered output delay
tpDD
(Note 1)
Input to output enable
tOE

Note:

XC7272A·20

Fig.

Min

Max

Min

Max

Min

Max

Units

11
11
11
11

5
10
13
13

16
30
40
40

3
6

3
6
8
8

12
21
25
25

ns
ns

8
8

14
25
32
32

11

11
11

32
32

7
7

25
25

7
7

22
22

ns

Input to output disable

tOD

XC7272A·16
(Com/lnd only)

XC7272A·25

ns
ns

ns

1. Specifications account for logic paths which use the maximum number of available product terms and the AlU.

Incremental Parameters
Fig.

XC7272A·25

XC7272A·20

Min

Min

XC7272A·16
(Com/lnd only)

Max

Units

12

1.6

1.2

1

ns

12

10

8

6

ns

12

14

12

10

ns

13

1

1

1

ns

13

1.5

12

10

ns

teoF2 Incremental delay from FastCLK net to
(Note 3) latched/registered UIM·input

13

1

1

1

ns

Incremental delay from UIM·input to
tpDF
(Note 1) non·registered macrocell feedback

13

25

19

14

ns

Parameter
Arithmetic carry delay
tpDT1
(Note 2) between adjacent macrocells
tpDT8 Arithmetic carry delay through 9 adjacent
(Note 2) macrocells in a FB
Symbol

tpDT9 Arithmetic carry delay through 10 macrocells
(Note 2) from macrocell #n to macrocell #n in next FB
Incremental delay from FastCLK net to registered
output feedback
Incremental delay from UIM·input (for P·term
clock) to registered macrocell feedback

teoF
teoF1

Max

Max

Min

tAOF

Incremental delay from UIM·input (SeVReset) to
registered macrocell feedback

13

25

19

14

ns

tOEF
tODF
tiN + tOUT
(Note 4)

Incremental delay from UIM·input (used as out·
put·enable/disable) to macrocell feedback
Propagation delay
through unregistered input pad (to UIM)
plus output pad driver (from macrocell)

13

17

12

11

ns

13

15

13

11

ns

Notes: 1. Specifications account for logic paths that use the maximum number of available product terms and the ALU.
2. Arithmetic carry delays are measured as the increase in required set·up time to adjacent macrocell(s) for an adder with
registered outputs.
3. Parameter tCOF2 is derived as the difference between the clock period for pipelining input·to·macrocell registers (1/fcLK3 ) and
the non-registered input set-up time (tsu).
4. Parameter tiN represents the delay from an input or 1/0 pin to a UIM-input (or from a FastClK pin to the Fast ClK net); toUT
represents the delay from a macrocell output (feedback point) to an output or I/O pin. Only the sum of tiN + tOUT can be
derived from measurements, e.g., tiN + tOUT = tsu + tco - 1/fcyc·

3-170

June 1, 1996 (Version 1.0)

~XIUNX
Power-up/Reset Timing Parameters
Symbol

Parameter

tWMR

Master Reset input Low pulse width

trvee
tRESET

Vee rise time (if MR not used for power-up)
Configuration completion time (to outputs operational)

Min

Typ

Max

Units

350

5
1000

Ils
Ils

ns

100

Device Output o---+-----..---@.TestPoint

Device Imput
Rise and Fall
Times < 3 ns

X3490

Figure 5: AC Load Circuit

June 1, 1996 (Version 1.0)

3- 171

XC7272A 72-Macrocell CMOS CPLD

Timing and Delay Path Specifications
The delay path consists of three blocks that can be connected in series:

Figure 8 defines the set-up and hold times from the data
inputs to the product-term clock used by the output register.

•
•
•

Figure 9 defines the set-up and hold times from the data
inputs to the FastCLK used by the output register.

Input Buffer and associated latch or register
Logic Resource (UIM, AND-array and macrocell)
Three-state Output Buffer

All inputs have the same delay, regardless of fan-out or
location. All logic resources have the same delay, regardless of logic complexity, interconnect topology or location
on the chip. All outputs have the same delay. The achievable clock rate is, therefore, determined only by the input
method (direct, latched or registered) and the number of
times a signal passes through the combinatorial logic.

Timing and Delay Path Descriptions
Figure 6 defines the maximum clock frequency (with feedback). Any macrocell output can be fed back to the UIM as
an input for the next clock cycle. Figure 6 shows the relevant delay path. The parameters fCYC and fCYC1 specify
the maximum operating frequency for FastCLK and product-term clock operation respectively.
Figure 7 specifies the max operating frequency (fCLK3) for
pipelined operation between the input registers and the
macrocell registers, using FastCLK.
UIM

Figure 10 defines the set-up and hold times from the data
input to the FastCLK used in an input register.
Figure 11 shows the waveforms for the macrocell and control paths
Figure 12 defines the carry propagation delays between
macrocells and between FBs. The parameters describe the
delay from the CIN' 01 and 02 inputs of a macrocell ALU to
the CIN input of the adjacent macrocell ALU. These delays
must be added to the standard macrocell delay path (t pD or
t SU ) to determine the performance of an arithmetic function.
Figure 13 defines the incremental parameters for the standard macrocell logic paths. These incremental parameters
are used in conjunction with pin-to-pin parameters when
calculating compound logic path timing. Incremental
parameters are derived indirectly from other pin-to-pin
measurement.

Function Block

Output or
1/0 Pin

Input or
1/0 Pin

J ~""------'\I....-~~...---,/'
____ ___________
1/fCYC,1/fCYC1

FASTCLK or
Product Term Clock

Macrocell Register
Output

~x~

~I.

X3279

Figure 6: Delay Path Specification for fcyC and f CYC1

3- 172

June 1, 1996 (Version 1.0)

~XILINX

UIM

Function Block

Input or
I/O Pin

Output or
I/O Pin

FASTCLK
Pin

FASTCLK

~

1/fCLK3

~/

),)

\

I

X

Input-Pad
Register Output

X3280

Figure 7: Delay Path Specification for fCLK3

UIM

Function Block

Input or
I/O Pin

Output or
I/O Pin

Input or
I/O Pin

Clock
Output

1

I~iou~ ~ xxxf!--'- _tS: :U:':1-D-at-a- -I~ .'"'hxxx
X3281

Figure 6: Delay Path Specification for fSU1 and fH1

June 1. 1996 (Version 1.0)

3- 173

XC7272A 72-Macrocell CMOS CPLD

Function Block

UIM

Output
Driver
Output or
I/O Pin

Input or
I/O Pin

FASTCLK
Pin

FASTCLK
Input

tsu
Input or
I/O Pin

r

xxJ""'--oata-fu§ik
X3282

Figure 9: Delay Path Specification for fsu and fH

UIM

Input or
I/O Pin

FASTCLK

Input-Pad
Register

>---.-110

Q

• • • • • _ • •1

Pin

FASTCLK
Pin

Input or
I/O Pin

Data
X3283

Figure 10: Delay Path Specification for fSU2 and fH2

3- 174

June 1, 1996 (Version 1.0)

~XILINX

* tSU2 and tH2 are measured with respect to the high-going

Registered
Inputs

FastClK

edge of FastClK for registered inputs, and with respect to
the low-going edge of FastClK for latched inputs. Only the
high going edge is used for clocking the macro cell registers.

Active

Inactive

Input Used
as Clock

Unlatched
Inputs

Valid Reset/Set

I

Reset/Set
De-Asserted

Non-Registered
Outputs

Registered
Outputs

X3284

Figure 11: Principal Pin-to-Pin Measurements

tpDF

AD

S1
Al

S8
A8

A9

>--C=-:>S9

Figure 12: Arithmetic Timing Parameters

June 1, 1996 (Version 1.0)

3-175

XC7272A 72-Macrocell CMOS CPLD

UIM

Function Block

Output or
1/0 Pin
Input or
1/0 Pin

Input or
I/O Pin

Output or
1/0 Pin

Input or
1/0 Pin

Output or
1/0 Pin

FASTCLK
Pin

X3288

Figure 13: Incremental Timing Parameters

3- 176

June 1, 1996 (Version 1.0)

~XILINX
XC7372 Pinouts
PC68

1
2

in
XC7272A
Master Reset

out

PC84

PG84

PC68

1

F-9
F-ll

35

Input
Input

2
3

-

Input

3

Input

4
5
6
7
8
9
10
11
12
13
14
15

Input
Input

4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

GND

FastCLKO
FastCLKl

MC4-4

Input

MC4-2
MC4-1

MC4-3

Input

MC3-8
MC3-7
MC3-6
MC3-5
GND

-

MC3-4
MC3-3
MC3-2
MC3-1

Vee

16
17
18

Input
Input

MC2-9
MC2-8

19

Input

20

Input

MC2-7
MC2-6

21

GND

22
23

Input
Input

MC2-5
MC2-4

24

Input
Input

MC2-3

25
26

MC2-2

Input

MC2-1

27
28

Input
Input

MCl-9
MCl-8

29

Input

MCl-7

30
31

Input

MCl-6

32

Input
Input

33
34

-

37

GND

Input
Input
Input

June 1, 1996 (Version 1.0)

35
36

E-ll

in

XC7272A

out

Vee
Input
Input

MC8-9
MC8-8

PC84

43
44
45

E-l0
E-9

36

Input

MC8-7

37

Input

MC8-6

46
47

D-ll

38

Input

MC8-5

48

D-l0

39
40
41

Input

C~ll

B-ll

49

GND

H-2
J-l

52

J-2

53
54

L-l
K-2

55

K-3

56
57

L-2

43

Input

MC8-1

B-l0
B-9

44
45

Input
Input

MC7-9
MC7-8

A-l0

46

Input

MC7-7

A-9

47
48

Input

MC7-6
MC7-5

49

F-l
H-l

MC8-2

Input
Input

A-8
B-6

G-2

50
51

42

Input

F-3
G-3
G-l

MC8-4
MC8-3

C-l0
A-ll

B-8

PG84

GND

Input

MC7-4

58
59

K-l

L-3
K-4
L-4
J-5

B-7

50
51

MC7-3

A-7

52

Input
Input

60
61

MC7-2

62

L-5

C-7

53

Input

MC7-1

63

K-6

C-6

54

64

J-6

A-6
A-5

55

MC6-8
MC6-7

65
66

J-7
L-7

MC6-6

67

K-7

MC6-5

68

L-6
L-8

Vee

56
57

K-5

B-5
C-5

58

A-4

59

B-4
A-3

-

MC6-4
MC6-3

B-3

-

MC6-2
MC6-1

73

A-l

60
61
62

Input
Input
Input

MC5-4

74

L-ll

MC5-3

75
76

K-l0
J-l0

63
64

Input

77

K-l1

GND

A-2

B-2
C-2
B-1
C-l

MC5-2
MC5-1
GND

69
7()
71
72

K-8
L-9
L-l0
K-9

78

J-ll

D-2
D-l

65

Input

79

H-l0

66

Input

67
68

Input
Input

80
81
82

H-ll
F-l0

MCl-5

38

MCl-4
MCl-3

E-3
E-2

MCl-2

39
40
41

E-l

Input

MC1-l

42

F-2

Input

83
84

G-l0
G-ll
G-9

3- 177

I

XC7272A 72-Macrocell CMOS CPLD

Ordering Information

J

XC7272A - 16 PC 84 C
Device Type ]

TL
L

Speed

Temperature Range

Number of Pins

'---- Package Type
Speed Options
-25
25 ns (40 MHz) sequential cycle time
-20
20 ns (50 MHz) sequential cycle time
-16
16 ns (60 MHz) sequential cycle time (commercial/industrial only)
Packaging Options
PC68
68-Pin Plastic Leaded Chip Carrier
WC68
68-Pin Windowed Ceramic Leaded Chip Carrier
PC84
84-Pin Plastic Leaded Chip Carrier
WC84
84-Pin Windowed Ceramic Leaded Chip Carrier
PG84
84-Pin Ceramic Windowed Pin Grid Array
Temperature Options
CommercialO°C to 70°C
C
I
Industrial -40°C to 85°C
M
Military -55°C (Ambient) to 125°C (Case)

Component Availability
Pins

68

Type
Code
XC7272A
C =Commercial

3- 178

-25
-20
-16

Plastic
PLCC
PC68
CI
CI
CI

=0° to +70°C

Ceramic
CLCC
WC68
CI
CI
CI

Plastic
PLCC
PC84
CI
CI
CI

I =Industrial =-40° to 85°C

84
Ceramic
CLCC
WC84
CIM
CIM
CI

M =Military

Ceramic
PGA
PG84
CI
CI
CI

=-55°C(A) to 125°C (C)

June 1, 1996 (Version 1.0)

SRAM-8ased FPGA Products

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

SRAM-Based FPGA Products Table
of Contents

SRAM-Based FPGA Products
XC4000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
XC4000 Series Field Programmable Gate Arrays ................................. 4-5
XC5200 Series Table of Contents . ........................................... 4-179
XC5200 Field Programmable Gate Arrays ....................................... 4-181
XC5200L Field Programmable Gate Arrays ...................................... 4-249
XC6200 Series Table of Contents . ........................................... 4-251
XC6200 Field Programmable Gate Arrays ....................................... 4-253
XC3000 Series Table of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-287
XC3000 Series Field Programmable Gate Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-289
XC3000A Field Programmable Gate Arrays ..................................... 4-341 .
XC3000L Field Programmable Gate Arrays ...................................... 4-349
XC3100A Field Programmable Gate Arrays ..................................... 4-357
XC3100L Field Programmable Gate Arrays ...................................... 4-365

XC4000 Series Table of Contents

XC4000 Series Field Programmable Gate Arrays
XC4000-Series Features .............................................•...............
Low-Voltage Versions Available ...................................................... .
Additional XC4000EXlXL Features .................................................... .
Introduction ...................................................................... .
Description ................................................................ .
Taking Advantage of Reconfiguration ............................................ .
XC4000E and XC4000EX Families Compared to the XC4000 ............................... .
Improvements in XC4000E and XC4000EX ....................................... .
Additional Improvements in XC4000EX Only ...................................... .
Detailed Functional Description " .................................................... .
Basic Building Blocks ........................................................ .
Configurable Logic Blocks (CLBs) .............................................. .
Function Generators ..................................................... .
Flip-Flops ............................................................. .
Latches (XC4000EX only) ......................................... , ...... .
Clock Input ............................................................ .
Clock Enable ........................................................... .
Set/Reset ........................... : ................................. .
Global Set/Reset. ......................................................... .
Data Inputs and Outputs .................................................. .
Control Signals ......................................................... .
Using FPGA Flip-Flops and Latches ......................................... .
Using Function Generators as RAM ......................................... .
Fast Carry Logic ........................................................ .
Input/Output Blocks (lOBs) .................................................... .
lOB Input Signals ....................................................... .
lOB Output Signals ...................................................... .
Other lOB Options ...................................................... .
Three-State Buffers .......................................................... .
Three-State Buffer Modes ................................................ .
Three-State Buffer Examples .............................................. .
Wide Edge Decoders ........................................................ .
On-Chip Oscillator ........................................................... .
Programmable Interconnect ......................................................... .
Interconnect Overview ........................................... : ........... .
CLB Routing Connections ..................................................... .
Programmable Switch Matrices ............................................ .
Single-Length Lines ..................................................... .
Double-Length Lines ..................................................... .
Quad Lines (XC4000EX only) .............................................. .
Longlines .. , .. , ...... '" ., ...... , ....................... , ...... , " ., .. .
Direct Interconnect (XC4000EX only) ........................................ .
1/0 Routing ................................................................ .
Octal 1/0 Routing (XC4000EX only) ......................................... .
Global Nets and Buffers ...................................................... .
Global Nets and Buffers (XC4000E only) ..................................... .
Global Nets and Buffers (XC4000EX only) .................................... .
Power Distribution ......................•...........................................

4-5
4-5
4-5
4-5
4-6
4-7
4-8
4-8
4-9
4-11
4-11
4-11
4-11
4-12
4-12
4-12
4-13
4-13
4-13
4-13
4-13
4-13
4-14
4-21
4-24
4-24
4-27
4-29
4-29
4-30
4-30
4-31
4-31
4-32
4-32
4-32
4-35
4-35
4-35
4-36
4-37
4-37
4-38
4-40
4-41
4-41
4-43
4-46

I

4-1

XC4000 Series Table of Contents

Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Boundary Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bit Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Including Boundary Scan in a Schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Avoiding Inadvertent Boundary Scan Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Special Purpose Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Modes ..........................................................
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Peripheral Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode ........................................................
Express Mode (XC4000EX only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Setting CCLK Frequency . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Data Stream Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Cyclic Redundancy Check (CRC) for Configuration and Readback ......................
Configuration Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Memory Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initialization .............................................................
Configuration ...........................................................
Delaying Configuration After Power-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-Up. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DONE Goes High to Signal End of Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Release of User I/O After DONE Goes High ...................................
Release of Global Set/Reset After DONE Goes High ............................
Configuration Complete After DONE Goes High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Through the Boundary Scan Pins .....................................
Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Readback Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Read Capture ...........................................................
Read Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Clock Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Violating the Maximum High and Low Time Specification for the Readback Clock. . . . . . . . ..
Readback with the XChecker Cable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave Serial Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Master Parallel Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synchronous Peripheral Mode ..................................................
Asynchronous Peripheral Mode .................................................
Write to FPGA ................ " ........... , ... '" .... '" ............... ,
Status Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Express Mode (XC4000EX only) ................................................
Configuration Switching Characteristics ...........................................' ......
Master Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Slave and Peripheral Modes ....................................................
XC4000E SWitching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . ..
Definition of Terms ...........................................................
XC4000E Operating Conditions . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E DC Characteristics Over Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Program Readback Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . ..
XC4000E Global Buffer Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Wide Decoder Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000E Horizontal Longline Switching Characteristic Guidelines. . . . . . . . . . . . . . . . . . . . ..

4-2

4-46
4-50
4-50
4-50
4-53
4-53
4-53
4-54
4-54
4-54
4-54
4-54
4-55
4-55
4-56
4-56
4-57
4-59
4-59
4-59
4-60
4-60
4-60
4-62
4-63
4-63
4-63
4-64
4-64
4-65
4-65
4-65
4-65
4-65
4-65
4-66
4-66
4-68
4-70
4-72
4-74
4-74
4-74
4-76
4-79
4-79
4-79
4-80
4-80
4-80
4-80
4-81
4-81
4-82
4-83
4-84

1:XIUNX
XC4000E CLB Switching Characteristic Guidelines ................................. .
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines ... .
XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic
Guidelines .............................................................. .
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines ................ .
XC4000E CLB Level-Sensitive RAM Timing Characteristics .......................... .
XC4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O) ............... .
XC4000E lOB Input Switching Characteristic Guidelines ............................. .
XC4000E lOB Output Switching Characteristic Guidelines ........................... .
XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines .................. .
XC4000L Switching Characteristics ................................................... .
XC4000EX Switching Characteristics .................................................. .
XC4000XL Switching Characteristics .................................................. .
Device-Specific Pinout Tables ....................................................... .
Pin Locations for XC4003E Devices ................... , ......................... .
Pin Locations for XC4005E/L Devices ........................................... .
Pin Locations for XC4006E Devices ............................................. .
Pin Locations for XC4008E Devices ............................................. .
Pin Locations for XC4010E/L Devices ........................................... .
Pin Locations for XC4013E/L Devices ........................................... .
Pin Locations for XC4020E Devices ............................................. .
Pin Locations for XC4036EX/XL Devices ......................................... .
Pin Locations for XC4044EXlXL Devices ......................................... .
Pin Lpcations for XC4052XL Devices ............................................ .
Package-Specific Pinout Tables ..................................................... .
PC84PilCkage Pinouts ....................................................... .
PQ100 Package Pinouts ...................................................... .
VQ100 Package Pinouts ...................................................... .
PG120 Package Pinouts ...................................................... .
TQ144 Package Pinouts ...................................................... .
PG156 Package Pinouts ...................................................... .
PQ160 Package Pinouts ...................................................... .
TQ176 Package Pinouts ...................................................... .
PG191 Package Pinouts (see PG223) ........................................... .
PG223 and PG191 Package Pinouts ............................................ .
BG225 Package Pinouts ...................................................... .
PQ240, HQ240 Package Pinouts ............................................... .
PG299 Package Pinouts ........................ " ....... " . " ..... " ..... " ...... " .
HQ304 Package Pinouts .. " ....... " ....... " .... " . " " .. " .. " . " .. " " . " .. " .. " .. " . " . " .
BG352 Package Pinouts .. " .......... " .... " ....... " . " " .... " . " ......... " . " .... " .
PG411 Package Pinouts .. " " . " ...... " ...... " .... " " ... " " " .. " . " " . " " ... " ... " ..... "
BG432 Package Pinouts .. " .... " . " " . " " .. " " . " " . " " . " .. " . " . " ... " . " ... " .. " ........ .
Product Availability" . " .. " , .. " " .. " " . " " ........ " .. " . " " ... " " . " ........ " " .... " " .. " . " . " . "
User I/O Per Package" . " .... " .... " . " ...... " .. " .... " ... " . " .... " .. "" .. " " .. " . " . " ..... " ..
Ordering Information. " . " " . " . " .. " . " .. " " " " .. " .. " " .. " " " " " .. " " . " ....... " . " ... " " " ....... .

4-85
4-87
4-88
4-89
4-90
4-91
4-92
4-94
4-96
4-96
4-96
4-96
4-97
4-97
4-98
4-100
4-102
4-104
4-107
4-110
4-118
4-123
4-128
4-133
4-133
4-134
4-135
4-136
4-138
4-140
4-142
4-144
4-145
4-149
4-152
4-154
4-157
4-160
4-163
4-166
4-170
4-174
4-176
4-178

I

4-3

XC4000 Series Table of Contents

4-4

XC4000 Series
Field Programmable Gate Arrays
July 30, 1996 (Version 1.03)

Product Specification

XC4000-Series Features

Additional XC4000EXlXL Features

Note: XC4000-Series devices described in this data sheet
include the XC4000E, XC4000EX, XC4000L, and
XC4000XL. This information does not apply to the older
Xilinx families: XC4000, XC4000A, XC4000D or XC4000H.
For information on these devices, see the Xilinx WEBLINX
at http://www.xilinx.com.

•
•

•

•
•
•

•
•
•
•

Third Generation Field-Programmable Gate Arrays
- Select-RAMTM memory: on-chip ultra-fast RAM with
- synchronous write option
- dual-port HAM option
- Fully PCI compliant (speed grades -3 and faster)
- Abundant flip-flops
- Flexible function generators
- Dedicated high-speed carry logic
- Wide edge decoders on each edge
- Hierarchy of interconnect lines
Internal 3-state bus capability
- 8 global low-skew clock or signal distribution
networks
System Performance to 66 MHz
Flexible Array Architecture
Systems-Oriented Features
IEEE 1149.1-compatible boundary scan logic
support
Individually programmable output slew rate
- Programmable input pull-up or pull-down resistors
- 12-mA sink current per XC4000E output (4 mA per
XC4000L output)
Configured by Loading Binary File
- Unlimited reprogrammability
Readback Capability
Backward Compatible with XC4000 Devices
XACTstep Development System runs on '386/'486/
Pentium-type PC, Sun-4, and Hewlett-Packard 700
series
Interfaces to popular design environments
Fully automatic mapping, placement and routing
Interactive design editor for design optimization
RAM/ROM compiler

•
•
•
•

•
•
•
•

Highest Capacity - Over 130,000 Usable Gates
Additional Routing Over XC4000E
- almost twice the routing capacity for high-density
designs
Buffered Interconnect for Maximum Speed
New Latch Capability in Configurable Logic Blocks
Improved VersaRing™ I/O Interconnect for Better Fixed
Pinout Flexibility
Flexible New High-Speed Clock Network
8 additional Early Buffers for shorter clock delays
- 4 additional FastCLI(TM buffers for fastest clock input
- Virtually unlimited number of clock signals
Optional Multiplexer or 2-input Function Generator on
Device Outputs
High-Speed Parallel Express™ Configuration Mode
Improved 1/0 Setup and Clock-to-Output with FastCLK
and Global Early Buffers
4 Additional Address Bits in Master Parallel
Configuration Mode

Introduction
XC4000-Series high-performance, high-capacity Field Programmable Gate Arrays (FPGAs) provide the benefits of
custom CMOS VLSI, while avoiding the initial cost,long
development cycle, and inherent risk of a conventional
masked gate a r r a y . '
The result of eleven years of FPGA design experience and
feedback from thousands of customers, these FPGAscombine architectural versatility, on-Chip Select-RAM memory
with edge-triggered and dual-port modes, increased speed,
abundant routing resources, and new, sophisticated software to achieve fully automated implementation of complex, high-density, high-performance designs.
The XC4000 Series currently has 19 members, as shown
in Table 1.

Low-Voltage Versions Available
•
•
•

Low-Voltage Devices Function at 3.0 - 3.6 Volts
XC4000L: Low-Voltage Versions of XC4000E devices
XC4000XL: Low-Voltage Versions of XC4000EX
devices

July 30, 1996 (Version 1.03)

4-5

I

XC4000 Series Field Programmable Gate Arrays

Table 1: XC4000-5eries Field Programmable Gate Arr,ays
!

Device
XC4003E'
XC4005E1L
XG4006E
XC4008E
XC4010ElL
XC4013E1L
XC4020E
XC4025E
XC4028EXlXL
XC4036EXlXL
XC4044EXlXL
XC4052XL
XC4062XL

"

Typics'l.
Max Logic Max. RAM
Bits
Gates
Gate Range
CI:-B
(No RAM) (No Logie) (Logip and RAM)"
Matrix
10 x 10
3,200
2,000 -5,000
3,000
6,272
3;000 - 9,000
~4x 14
5,000
8,192
4,000-12,qOO
6,000
16 x 16
10,368
6,000 c 15;000
18 x18
8,000
10,000
12,800
20 x20
7,000 - 20,000
18,432
10,000 - 30,000
24x2~
13,000
13,OQO - 40,000
28x28
20,000
25,088
32,768
15,000 - 45,000
25,000
32 x32
32,768
18,000 - 50,000
32x32
28,000
36,000
41,472
22,000 - 65,000
36qa
51,200
44,000
27,000 - 80,000
40x40
61,952
33,000 - 100,000
44x44
52,000
73,728
48 x48
62,000
40,000 - 130,000
Larger De\lices Available in the

Total
Logic
Blocks
100

Number
of
Flip-Flops
360
196
616
256
768
324
936
1,120
400
576
1,536
784
2,016
1,024
2,560
1,024
2,560
1,296
3,168
1,600
3,840
1,936
4,576
2,304
5,376
First Half of 1997

Max.
Decode
Inputs
per side
30
42
48
54
60
72
84
96
96
108
120
132
144

Max.
UserVO
80
112
128
144
160
192
224
256
256
288
320
352
384

* Max values of Typical Gate Rangeincluoe 20-30% of CLBs useo as RAM.

Note: Throughout the functional despfiptions in this document, references to the XC4000E device family include the
XG4000L, and references to the XG4000EX device family
include the XG4000XL, unless expliOitly stated otherwise.
References to the XG4000 Series include, the XG4000E,
XG4000EX, XG4000L, and XG4000XL families. All functionality in low-voltage families is the same as in the corresponding 5- Volt family, except where! numerical references
are made to timing, power, or current-sinking capability.

Description
XC4000-Series devices are implemented with. a regular,
flexible, programmable architecture of Configurable Logic
Blocks (CLBs), interconnected by a powerful hierarchy of
versatile routing resources, and surrounded by a perimeter
of programmable Input/Output Blocks (lOBs). They have
generous rou~irigresources to accommodate the most
complex interconnect patterns.
The. devices are, customi~d by loading configuration datIl
into internal memory celis. The FPGA can either actively
read its configuration data from an external serial or byteparallel PROM (master modes), or the configuration data

4-6

can .be written into the FPGA from an external device
(slave, peripheral and Express modes).
XC4000-Series FPGAs are supported by powerful and
sophisticated software, covering every aspect of design
from schematic or behavioral entry, floorplanning, simulation, automatic block placement and routing of interconnects, to the creation, downloading, and read back of the
configuration bit stream:
Because Xilinx FPGAs can be reprogrammed an unlimited
number of times, they can be used in innovative designs
where hardware is changed dynamically, or where hardware must be adapted to differentpser applications.
FPGAs are ideal for shortening. design and development
cycles, and also offer a cost-effective solution for production rates well beyond 5,000 systems per. month. For lowest
high-volume unit cost, a design can first be implemented in
the XC4000E or XC4000E.X, then migrated to. one of Xilinx'
compatible HardWire mask-programmed devices.
Table 2 shows density and performance for a few common
circuit functions that can be implemented in XC4000-Series
devices.

July 30;i1996 (Version 1.03)

~XILINX
Table 2: Density and Performance for Several Common Circuit Functions in XC4000E 1
Design Class
Memory

Logic

Note:

Function
256 x 8 Single Port (read/modify/write)
32 x 16 bit FIFO
simultaneous read/write
MUXed read/write
9 bit Shift Register (with Elnable)
16 bit Pre-Scaled Counter
16 bit Loadable Counter
16 bit Accumulator
8 bit, 16 tap FIR Filter sample rate
parallel
serial
8 x 8 Parallel Multiplier
,
single stage, register to register
'
16 bit Address Decoder (internal decode)
9 bit Parity Checker

CLBs Used
72

XC4000E-3

XC4000E-2

Units

63

80

MHz

48

63
63

5

170

80
80
200

8
8
9

142

170

a5

76
76

MHz
MHz
MHz
MHz
MHz
MHz

8.1

65
10

MHz
MHz

37
4.7
4.3

30

3.9
2.7

ns
ns
ns

32

400
68
73
3
1

65

55

I

1. Most functions are faster In XC4000EX due to faster carry logic, direct connects, and other additional Interconnect.

Taking Advantage of Reconfiguration
FPGA devices can. be reconfigured to change logic function
while resident in the system. This capability gives the system designer a·new degree of freedom·not available with
any other type of logic.
Hardware can be changed as easily as software. Design
updates or modifications· are easy, and can be made to.
products already in the field. An FPGA can even be recon-

July 30, 1996 (Version 1.03)

figured dynamically to peiform different functions at differenttimes.
Reconfigurable logic can be used to implement system
self-diagnostics, create systems capable of being reconfigured for different environments or operations, or implement
multi-purpose hardware for a given. application. As an
added benefit, using reconfigurable FPGA devices simplifies hardware design and debugging and shortens product
.
time-to-market. .

4-7

XC4000 Series Field Programmable Gate Arrays

XC4000E and XC4000EX Families
Compared to the XC4000
For readers already faniiliar with the XC4000 family of XiIinx Field Programmable Gate Arrays, the major new features in the XC4000-Series devices are listed in this
section.
The biggest advantages of XC4000E and
XC4000EX devices are significantly increased system
speed, greater capacity, and new architectural features,
particularly Select-RAM memory. The XC4000EX devices
also offer many new routing features, including special·
high-speed clock buffers that can be used to capture input
data with minimaldelay.
Any XC4000E device is pinout- and bitstream-compatible
An existing
with the corresponding XC4000 device.
XC4000 bitstream can be used to program an XC4000E
device. However, since the XC4000E includes many new
features, an XC4000E bitstream cannot be loaded into an
XC4000 device.
Most XC4000EX devices have no corresponding XC4000
devices, because of the larger CLB arrays. The XC4028EX
has the same array size as the XC4025 and XC4025E, but
is not bitstream-compatible.
However, the XC4025,
XC4025E, and XC4028EX are all pinout-compatible.

Improvements in XC4000E and XC4000EX
Increased System Speed

Delays in FPGA-based designs are layout dep.endent.
There is a rule of thumb designers can consider-the system clock rate should not exceed one third to one half of the
specified toggle rate. Critical portions of a design, such as
shift registers and simple counters, can run faster-approximately two thirds of the specified toggle rate.
XC4000E and XC4000EX devices can run at synchronous
system clock rates of up to 66 MHz, and internal performance can exceed 150 MHz. This increase in performance
over the previous families stems from improvements in both
device processing and system architecture.
XC4000Series devices use a sub-micron triple-layer metal process.
In addition, many architectural improvements have been
made, as described below.

Select-RAM Memory: Edge-Triggered, Synchronous
RAM Modes

The RAM in any CLB can be configured for synchronous,
edge-triggered, write operation. The read operation is not
affected by this change to an edge-triggered write.
Dual-Port RAM

A separate option converts the 16x2 RAM in any CLB into a
16x1 dual-port RAM with simultaneous ReadlWrite.
The function generators in each CLB can be configured as
either level-sensitive (asynchronous) single-port RAM,
edge-triggered (synchronous) single-port RAM, edge-triggered (synchronous) dual-port RAM, or as combinatorial
logic.
Configurable RAM Content

The RAM content can now be loaded at configuration time,
so that the RAM starts up with user-defined data.
H Function Generator

In XC4000-Series devices, the H function generator is
more versatile than in the XC4000. Its inputs can corne not
only from the F and G function generators but also from up
to three of the .four control input lines. The H function gen.
erator can thus be totally or partially independent of the
other two function generators, increasing the maximum
capacity of the device.
lOB Clock Enable

The two flip-flops in each lOB have a common clock enable
input, which through configuration can be activated individually for the input or output flip-flop or both. This clock
enable operates exactly like the EC pin on the XC4000
CLB. This new feature makes the lOBs more versatile, and
avoids the need for clock gating.
Output Drivers

XC4000-Series -3 and faster speed grades are fully PCI
compliant. XC4000E and XC4000EX devices can be used
to implement a one-chip PCI solution.

The output pull-up structure defaults to a TTL-like totempole. This driver is an n-channel pull-up tranSistor, pulling
to a voltage one transistor threshold below Vcc, just like the
XC4000 outputs. Alternatively, XC4000-Series devices can
be globally configured with CMOS outputs, with p-channel
pull-up transistors pulling to Vcc. Also, the configurable pullup resistor in the XC4000 Series is a p-channel transistor
that pulls to Vcc, whereas in the XC4000 it is an n-channe.1
transistor that pulls to a voltage one transistor threshold
belowVcc.

Carry Logic

InputThresholds

The speed of the carry logic chain has increased dramatically. Some parameters, such as the delay on the carry
chain through a single CLB (TBYp), have improved by as
much as 50% from XC4000 values. See "Fast Carry Logic"
on page 21 for more information.

The input thresholds can be globally configured for either
TTL (1.2 V threshold) or CMOS (2.5 V threshold), just like
XC2000 and XC3000 inputs. The two global adjustments of
input threshold and output level are independent of each
other.

PCI Compliance

4-8

July 30,1996 (Version 1.03)

~XILINX
Global Signal Access to Logic

Faster Input and Output

There is additional access from global clocks to the F and G
function generator inputs.

A fast, dedicated early clock sourced by global clock buffers
is available for the lOBs. To ensure synchronization with
the regular global clocks, a Fast Capture latch driven by the
early clock is available. The input data can be initially
loaded into the Fast Capture latch with the early clock, then
transferred to the input flip-flop or latch with the 'low-skew
global clock. A programmable delay on the input can be
used to avoid hold-time requirements. See "lOB Input Signals" on page 24 for more information.

Configuration Pin Pull-Up Resistors

During configuration, the three mode pins, MO, M1, and
M2, have weak pull-up resistors. For the most popular configuration mode, Slave Serial, the mode pins can thus be
left unconnected.
The three mode inputs can be individually configured with
or without weak pull-up or pull-down resistors after configuration.
The PROGRAM input pin has a permanent weak pull-up.
Soft Start-up

Like the XC3000A, XC4000-Series devices have "Soft
Start-up:' When the configuration process is finished and
the device starts up, the first activation of the outputs is
automatically slew-rate limited. This feature avoids potential ground bounce when all outputs are turned on simultaneously. Immediately after start-up, the slew rate of the
individual outputs is, as in the XC4000 family, determined
by the individual configuration option.
XC4000 and XC4000A Compatibility

Existing XC4000 bitstreams can be used to configure an
XC4000E device. XC4000A bitstreams must be recompiled for use with the XC4000E due to improved routing
resources, although the devices are pin-for-pin compatible.

Additional Improvements. in XC4000EX
Only
Increased Routing

New interconnect in the XC4000EX includes twenty-two
additional vertical lines in each column of CLBs and twelve
new horizontal lines in each row of CLBs. The twelve
"Quad Lines" in each CLB row and column include optional
repowering buffers for maximum speed. Additional highperformance routing near the lOBs enhances pin flexibility.

July 30, 1996 (Version 1.03)

Latch Capability in CLBs

Storage elements in the XC4000EX CLB can be configured
as either flip-flops or latches. This capability makes the
FPGA highly synthesis-compatible.
lOB Output MUX From Output Clock

A multiplexer in the lOB allows the output clock to select
either the output data or the lOB clock enable as the output
to the pad. Thus, tWo different data signals can share a single output pad, effectively doubling the number of device
outputs without requiring a larger, more expensive package. This multiplexer can also be configured as an ANDgate to implement a very fast pin-to-pin path. See"IOB
Output Signals" on ,page 27 for more information.
Express Configuration Mode

A new slave configuration mode accepts parallel data input.
Data is processed in parallel, rather than serialized internally. Therefore, the data rate is eight times that of the six
conventional configuration modes.
Additional Address Bits

Larger devices require more bits of configuration data. A
daisy chain of several large, XC4000EX devices may
require a PROM that cannot be addressed by the eighteen
address bits supported in the XC4000E.. The, XC4000EX
family therefore extends the addressing in Master Parallel
configuration mode to 22 bits.

4-9

I

XC400li Series Field Programmable Gate Arrays

Table 3: CLB Count of SElIected XC4000-Series Soft Macros
7400 Equivalents

CLBs Barrel Shifters

'138
5
'139
2
'147
5
'148
6
'150
5
'151
3
'152
3
'153
2
'154
16
'157.
2
'158
2
'160
5
'161
6
'162
8
'163
8
'164
4
'165s
9
'166
5
'168
7
'174
3
'194
5
'195
3
'280
3
'283
8
'298
2
'352
2
'390
3
'518
3
'521
3
Explanation of RAM nomenclature·
s single-port edge-triggered
d dual-port edge-triggered
no extension level-sensitive

=
=

4-10

=

brlshft4
brlshft8

CLBs Multiplexers
4
13

4-Bit Counters
cd4cd
cd4cle
cd4rle
cb4ce
cb4cle
cb4re

3
5
6
3
6
5

Registers

6
10
9
9
21

sr8ce
sr16re

8- and 16-Blt Counters
cb8ce
cb8re
cc16ce
cc16cle
cc16cled

4
9
20

RAMs
ram16x4
ram16x4s
ram16x4d

3
5

rd4r
rd8r
rd16r

2
4
8

4
8

Decoders
d2-4e
d3-8e
d4-16e

2
4
16

1
2
5

Magnitude Comparators
compm4
compm8
compm16

1
1

Shift Registers

Identity Comparators
comp4
comp8
comp16

CLBs

m2-1e
m4-1e
m8-1e
m16-1e

Explanation of counter nomenclature
cb binary counter
cd BCD counter
cc cascadable binary counter
bidirectional
d
I
loadable
e
clock enable
synchronous reset
r
c
asynchronous clear

=
=
=
=
=
=
=
=

2
2
4

July 30, 1996 (Version 1.03)

£:XILINX
Detailed Functional Description
XC4000-Series devices achieve high speed through
advanced semiconductor technology and improved architecture. The XC4000E and XC4000EX support system
clock rates of up to 66 MHz and internal performance in
excess of 150 MHz. Compared to older Xilinx FPGA families, XC4000-Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on 1/0 flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. DeSign cycles are faster due to a combination of
increased routing resources and more' sophisticated software.

Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (lOBs).
o

o

CLBs provide the functional elements for constructing
the user's logic.
lOBs provide the interface between the package pins
and internal signal lines.

Three other types of circuits are also available:
o
o
o

3-State buffers (TBUFs) driving horizontallonglines are
associated with each CLB.
Wide edge decoders are available around the'periphery
of each device.
An on-chip oscillator is provided.

Programmable interconnect resources provide routing
paths to connect the inputs and outputs ofthese configurable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Each of these available circuits is described in this section.

Configurable Logic Blocks (GLBs)
ConfigurableLogic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure 1. The number of CLBs needed to implement
selected soft macros is shown in Table 3. '
Two 4-input function generators (F and G) offer unrestricted
versatility. Most combinatorial logic functions need four or
fewer inputs. However, a third function generator (H) is provided. The H function generator has three inputs. Either

zero, one, or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The
CLB can, therefore, implement certain functions of up to
nine variables, like parity check or expandable-identity
comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the storage elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000EX devices; in
the XC4000EX they can optionally be configured as
latches. DIN can be used as a direct input to either of the
two storage elements. H1 can drive the other through the H
function generator. Function generator outputs can also
drive two outputs independent of the storage element outputs. This versatility increases logic capacity and simplifies
routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to tne programmable interconnect resources outside the block.

Function Generators
Four independent inputs are provided to each of twofunction generators (F1 - F4 and G1 - G4). These function generators, with outputs labeled F' and G', are each capable of
implementing any arbitrarily defined Bool,ean function of
four inputs. The function generators are implemented, as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled'H', can implement any
Boolean nlllction of its three inputs. Two of these inputs
canoptiQnally be4he F' ,and G' functional generator outputs. Alternatively, one or both of these inputs can come
from, outside the, CLB (H2, HO). The third input must come
from outside the block (H1).
Signals from the function generators can exit the CLB.on
two outputs. F' or H' can be connected to the X output. G'
or H' can be connected to the Y output.
' ,
A CLBcanbe used to implement any of the following functions:
'
o

o
o

o

any function of up to fOur variables, plus any second
function of, ~p four unrelated variables, plus any third
fllnction of, up to three unrelated Variables 1
any sing/efunction of five variables
any function of four variables together with some
functions of six variables'
some functions o~ up to nine variables.

to

1. When three separate functionsaregenerated~ one Ofthe functil;m outputs must be captured in a flip-flop internal to the ClB, Only two
unregistered function generator outputs aie available (rom the CLB,

July'30;1996 (Version 1.03)

4-11

I

XC4000 Series Field Programmable Gate Arrays

C1 "'C4

4
---,;"---------------1 ,GSR

.

EC,- Enable Clock
WE - Write Enable
DO - .Data Input to F and/O~ G function generator
D1 - Data input to G function generator(16xt and
16x2 modes) or 5th Address bit (32x1 mode).

X5260

Figure 2: Schematic Symbols for Global SetiReset

July 30, 1996 (Version 1.03)

4-13

I

XC4000 Series Field Programmable Gate Arrays

Using Function Generators as RAM

RAM Configuration Options

Optional modes for each CLB make the memory look-up
tables in the F' and G' function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000lAlH families), edgetriggered, and dual-port edge-triggered. Depending on the
selected mode, a single CLB can be configured as either a
16x2,32x1, or 16x1 bit array.

The function generators in any CLB can be configured as
RAM arrays in the following sizes:

Supported CLB memory configurations and timing modes
for single- and dual-port modes are shown in Table 5.
XC4000-Series devices are the first programmable logic
devices with edge-triggered (synchronous) and dual-port
RAM accessible lothe user. Edge-triggered RAM simplifies system timing. Dual-port RAM' doubles the effective
throughput of FIFO applications. These features can be
individually programmed in any XC4000-Series CLB.

•

•

One F or G function generator can be configured as a 16x1
RAM while the other function generators are used to implement any function of up to 5 inputs,
Additionally, the XC4000-Series RAM may have either of
two timing modes:
•

•

Advantages of On-Chip and Edge-Triggered RAM
The on-chip RAM is extremely fast. The read access time
is the same as the logic delay. The write access time is
slightly slower. Both access times are much faster than
any off-chip solution, because they avoid I/O delays.
Edge-triggered RAM, also called synchronous RAM, is a
feature never before available in a Field Programmable
Gate Array. The simplicity of designing with edge-triggered
RAM, and the markedly higher achievable performance,
add up to a significant improvement over existing devices
with on-chip RAM.
Three application notes are available from Xilinx that discuss edge-triggered RAM: "XC4000E Edge-Triggered and
Dual-Port RAM CapabilitY;' "Implementing FIFOs in
XC4000E RAM," and "Synchronous and Asynchronous
FIFO Designs." All three application notes apply to both
XC4000E and XC4000EX RAM.

Table 5: Supported RAM Modes

Two 16x1 RAMs: two data inputs and two data outputs
with identical or, if preferred, different addressing for
each RAM
One 32x1 RAM: one data input and one data output.

Edge-Triggered (Synchronous): data written by the
deSignated edge of the CLB clock. WE acts as a true
clock enable.
Level-Sensitive (Asynchronous): an external WE signal
acts as the write strobe.

The selected timing mode applies to both function generators within a CLB when both are configured as RAM.
The number of read ports is also programmable:
•
•

Single Port: each function generator has a common
read and write port
Dual Port: both function generators are configured
together as a single 16x1 dual-port RAM with one write
port and two read ports. Simultaneous read and write
operations to the same or different addresses are
.
supported.

RAM configuration options are selected by placing the
appropriate library symbol.
Choosing a RAM Configuration Mode
The appropriate choice of RAM mode for a given design
should be based on timing and resource requirements,
desired functionality, and the simplicity of the design process. Recommended usage is shown in Table 6.
The difference between level-sensitive, edge-triggered,
and dual-port RAM is only in the write operation. Read
operation and timing is identical for all modes of operation.
Table 6: RAM Mode Selection

Use for New
Designs?
Size (16x1,
Registered)
Simultaneous
ReadlWrite
Relative
Performance

4-14

.

Level.
Sensitive

. EdgeTriggered

Dual-Port
EdgeTriggered

No

Yes

Yes

1/2 CLB

1/2 CLB

1 CLB

No

No

Yes

X

2X

2X (4X
effective)

.

July 30, 1996 (Version 1 .03)

~:XILINX

G'

I

F'

K

(CLOCK)

--------~----~

X6752

Figure 3:

16x2 (or 16x1) Edge-Triggered Single-Port RAM

H'

K ---~-----I
(CLOCK)

Figure 4: 32x1 Edge-Triggered Single-Port RAM (F and G addresses are identical)

July 30, 1996 (Version 1.03)

4-15

XC4000 Series Field Programmable Gate Arrays

RAM Inputs and Outputs
The F1-F4 and G 1-G4 inputs to the function generators act
as address lines, selecting a particular memory cell in each
look-up table.

- - - - - - - - - - - - - - - - - - - - - - .Ir----=:.:.:"::O"'-"""\

WCLK(K) _ _ _ _ _ _ _ _ _ _ _- J

The functionality of the CLB control signals changes when
the function generators are configured as RAM. The DIN/
H2, H1, and SR/HO lines become the two data inputs (DO,
D1) and the Write Enable (WE) input for the 16x2 memory.
When the 32x1 configuration is selected, D1 acts as the
fifth address bit and DO is the data input.
The contents of the memory cell(s} being addressed are
available at the F' and G' function-generator outputs. They
can exit the CLB through its X and Y outputs, or can be captured in the CLB flip-flop(s}.
Configuring the CLB function generators as ReadlWrite
memory does not affect the functionality of the other portions of the CLB, with the exception of the redefinition of the
control signals. In 16x2 and 16x1 modes, the H' function
generator can be used to implement Boolean functions of
F', G', and D1, and the D flip-flops can latch the F', G', H', or
DO signals.
Single-Port Edge-Triggered Mode
Edge-triggered (synchronous) RAM simplifies timing
requirements. XC4000-Series edge-triggered RAM timing
operates like writing to a data register. Data and address
are presented. The register is enabled for writing by a logic
High on the write enable input, WE. Then a riSing or falling
clock edge loads the data into the register, as shown in
Figure 5.
Complex timing relationships between address, data, and
write enable signals are not required, and the external write
enable pulse becomes a simple clock enable. The active
edge of WCLK latches the address, input data, and WE signals. An internal write pulse is generated that performs the
write. See Figure 3 and Figure 4 for block diagrams of a
CLB configured as 16x2 and 32x1 edge-triggered, singleport RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port, edge-triggered mode are shown in
Table 7.
The Write Clock input (WCLK) can be configured as active
on either the rising edge (default) or the falling edge. It
uses the same CLB pin (K) used to clock the CLB flip-flops,
but it can be independently inverted. Consequently, the
RAM output can optionally be registered within the same

4-16

DATA IN

ADDRESS

DATA OUT
X6461

Figure 5:

Edge-Triggered RAM Write Timing

CLB either by the same clock edge as the RAM, or by the
opposite edge of this clock. The sense of WCLK applies to
both function generators in the CLB when both are configured as RAM.
The WE pin is active-High and is not invertible within the
CLB.
Note: The pulse following the active edge of WCLK (TWPS
in Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are configured as edge-triggered RAM.
Table 7: Single-Port Edge-Triggered RAM Signals
RAM Signal
D

A[3:0]
A[4]
WE
WCLK
SPO
(Data Out)

CLB Pin
DO or D1
(16x2, 16x1)
DO (32x1)
F1-F4 or
G1-G4
D1 (32x1)
WE
K
F' orG'

Function

IData In
I
Address
Address
Write Enable
Clock
Single Port Out
(Data Out)

July 30, 1996 (Version 1.03)

~XILINX
Dual-Port Edge-Triggered Mode
In dual-port mode, both the F and G function generators
are used to create a single 16x1 RAM array with one write
port and two read ports. The resulting RAM array can be
read and written simultaneously at two independent
addresses. Simultaneous read and write operations at the
same address are also supported.
Dual-port mode always has edge-triggered write timing, as
shown in Figure 5.
Figure 6 shows a simple model of an XC4000-Series CLB
configured as dual-port RAM. One address port, labeled
A[3:0], supplies both the read and write address for the F
function generator. This function generator behaves the
same as a 16x1 single-port edge-triggered RAM array. The
RAM output, Single Port Out (SPO), appears at the F function generator output. SPO, therefore, reflects the data at
address A[3:0j.

Therefore, by using A[3:0j for the write address and
DPRA[3:0] for the read address, and reading only the DPO
output, a FIFO that can read and write simultaneously is
easily generated. Simultaneous access doubles the effective throughput of the FIFO.
The relationships between CLB pins and RAM inputs and
outputs for dual-port, edge-triggered mode are shown in
Table 8. See Figure 7 for a block diagram of a CLB configured in this mode.
~ot~: The pulse following the active edge of WCLK (Twps
In Figure 5) must be less than one millisecond wide. For
most applications, this requirement is not overly restrictive;
however, it must not be forgotten. Stopping WCLK at this
point in the write cycle could result in excessive current and
even damage to the larger devices if many CLBs are configured as edge-triggered RAM.

Table 8: Dual-Port Edge-Triggered RAM Signals

The other address port, labeled DPRA[3:0j for Dual Port
Read Address, supplies the read address for the G function
generator. The write address for the G function generator,
however, comes from the address A[3:0]. The output from
this 16x1 RAM array, Dual Port Out (DPO), appears at the
G function generator output. DPO, therefore, reflects the
data at address DPRA[3:0j.

RAM16X1D Primitive

---------

,

o ~-o-I----1

,,
,

Function
Data In
Read Address for F,
Write Address for F and G

DPRA[3:0j
WE
WCLK
SPO

G1-G4
WE
K

DPO

G'

Read Address for G
Write Enable
Clock
Single Port Out
(addressed by A[3:0])
Dual Port Out
(addressed by
DPRA[3:0])

F'

, - - - - - - OPO (Dual Pori Out)

WE~-~~WE

DPAA[3:01~

RAM Signal
CLB Pin
0
DO
F1-F4
A[3:0]

Registered OPO
AR[3:0]

I

L

AW[3:0]

I

I

G Function Generator

, - - - - - - spa (Single Port Out)

WE
Registered spa
A[3:0] --'-4-----l--JAR[3:0]
AW[3:0]

F FunctIon Generator

WCLK---+----~

Figure 6: XC4000-Series Dual-Port RAM, Simple
Model

July 30, 1996 (Version 1.03)

4-17

XC4000 Series Field Programmable Gate Arrays

WRITE
DECODER

16-LATCH
ARRAY

MUX 1 - - + - - - G'

1 of 16

WRITE PULSE

4

WRITE
DECODER

16-LATCH
ARRAY

MUX 1 - - + - - - F'

1 of 16

(CLOCK~ -----4>=---1

WRITE PULSE

X6748

Figure 7: 16x1 Edge-Triggered Dual-Port RAM

4-18

July 30, 1996 (Version 1.03)

~XILINX
Single-Port Level-Sensitive Timing Mode
Note: Edge-triggered mode is recommended for all new
designs. Level-sensitive mode, also called asynchronous
mode, is still supported for XC4000-Series backward-compatibility with the XC4000 family.
Level-sensitive RAM timing is simple in concept but can be
complicated in execution. Data and address signals are
presented, then a positive pulse on the write enable pin
(WE) performs a write into the RAM at the designated
address. As indicated by the "level-sensitive" label, this
RAM acts like a latch. During the WE High pulse, changing
the data lines results in new data written to the old address.
Changing the address lines while WE is High results in spurious data written to the new address-and possibly at
other addresses as well, as the address lines inevitably do
not all change simultaneously.
The user must generate a carefully timed WE signal. The
delay on theoWE signal and the address lines must be carefully verified to ensure that WE does not become active until
after the address lines have settled, and that WE goes inactive before the address lines change again. The data must
be stable before and after the falling edge of WE.
In practical terms, WE is usually generated by a 2X clock. If
a 2X clock is not available, the falling edge of the system
clock can be used. However, there are inherent risks In this
approach, since the WE pulse must be guaranteed inactive
before the next rising edge of the system clock. Several
older application notes are available from Xilinx that discuss the design of level-sensitive RAMs. These application
notes include XAPP031, "Using the XC4000 RAM Capability,".and XAPP042, "High-Speed RAM Design in XC4000:'

However, the edge-triggered RAM available in the XC4000
Series is superior to level-sensitive RAM for almost every
application.
Figure 8 shows the write timing for level-sensitive, singleport RAM.
The relationships between CLB pins and RAM inputs and
outputs for single-port level-sensitive mode are shown in
Table 9.
Figure 9 and Figure 10 show block diagrams of a CLB configured as 16x2 and 32x1 level-sensitive, single-port RAM.
Initializing RAM at Configuration
Both RAM and ROM implementations of the XC4000Series devices are initialized during configuration. The initial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide.
If not defined, all RAM contents are initialized to all zeros,
by default.
RAM initialization occurs only during configuration. The
RAM content is not affected by Global Set/Reset.
Table 9: Single-Port Level-Sensitive RAM Signals
RAM Signal
D
A[3:0]
WE

a

CLB Pin
DO or D1
F1-F4 or
G1-G4
WE
F' or G'

Function
Data In
Address
Write Enable
Data Out

ADDRESS

WRITE ENABLE

DATA IN
X6462

Figure 8: Level-Sensitive RAM Write Timing

July 30, 1996 (Version1.03)

4-19

I

XC4000 Series Field Programmable Gate Arrays

q

6

'1

EC

DO

DIN

I'---

16-LATCH
ARRAY

MUX

Enable

f---- - WRITE
DECODER

4

1 of 16

~

II

I

I

i.--(

READ ADDRESS

DIN

Enable

--

WRITE
DECODER

4

r---- !----- G'

16-LATCH
ARRAY

I'--MUX

r---- r----

F'

1 of 16

I

l-1

4

READ ADDRESS

X6746

Figure 9: 16x2 (or 16x1) Level-Sensitive Single-Port RAM

q

0 Q
WE

DiA4

r-----]

-

4

0

~
I

I'---

DIN

Enable

-1-------

1-----

16-LATCH
ARRAY

WRITE
DECODER

MUX

1---

1 of 16
~-

---

--

~-=----vr

4

READ ADDRESS

I
Enable

DIN

._-----

~.-

--~

G'

i"---

)l

"-

y.:-::

H'

~--

4

WRITE
DECODER

16-LATCH
ARRAY
---.~

1 of 16

--

-_._-

MUX

F'

--

~--

l--(

4

READ ADDRESS

X6749

Figure 10: 32x1 Level-Sensitive Single-Port RAM (F and G addresses are identical)

4-20

July 30, 1996 (Version 1.03)

~XILINX
Fast Carry Logic
Each CLB F and G function generator contains dedicated
arithmetic logic for the fast generation of carry and borrow
signals. This extra output is passed on to the function generator in the adjacent CLB. The carry chain is independent
of normal routing resources.
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in
microprocessor or graphics systems, and high-speed addition in digital signal processing are two typical applications.

The dedicated carry logic is discussed in detail in Xilinx
document XAPP 013: "Using the Dedicated Carry Logic in
XG4000." This discussion also applies to XC4000E
devices, and to XC4000EX devices when the minor logic
changes are taken into account.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Macros (RPMs) that already include these symbols.

The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level.

I

This fast carry logic is one of the more significant features
of the XC4000 Series, speeding up arithmetic and counting
into the 70 MHz range.
The carry chain in XC4000E devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. (See Figure 11.) In order to improve speed in the
high-capacity XC4000EX devices, which can potentially
have very long carry chains, the carry chain travels upward
only, as shown in Figure 12. This restriction should have little impact, because the smallest XC4000EX device, the
XC4028EX, can accommodate a 64-bit carry chain in a single column. Additionally, standard interconnect can be
used to route a carry signal in the downward direction.
Figure 13 on page 22 shows an XC4000E CLB with dedicated fast carry logic. The carry logic in the XC4000EX is
similar, except that COUT exits at the top only, and the signal CINDOWN does not exist. As shown in Figure 13, the
carry logic shares operand and control inputs with the function generators. The carry outputs connect to the function
generators, where they are combined with the operands to
form the sums.
Figure 14 and Figure 15 on page 23 show the details of the
carry logic for the XC4000E and the XC4000EX respectively. These· diagrams show the contents of the box
labeled "CARRY LOGIC" in Figure 13. As shown, the
XC4000EX carry logic eliminated a multiplexer to reduce
delay on the pass-through carry chain. Additionally, the
multiplexer on the G4 path now has a memory-programmable input, which permits G4 to directly connect to COUT.
G4 thus becomes an additional high-speed initialization
path for carry-in.

July 30, 1996 (VerSion 1.03)

X6687

Figure 11: Available XC4000E Carry Propagation
Paths

E1B-d~~~lB

Bi6. i-Bia
j..:Y:j..:j..

8'8j{~:8
~

iii

~

~8!8~
+

:

+

+

X6610

Figure 12: Available XC4000EX Carry Propagation
Paths (dotted lines use general interconnect)

4-21

XC4000 Series Field Programmable Gate Arrays

CARRY
LOGIC

I--------Y

G4--~-+-4----r---

G3--~-+------r---

G
G2--~-+------~--

YO
G1--~~------+---

Figure 13: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000EX)

4-22

July 30, 1996 (Version 1.03)

~:XILINX

G1-----i

G2
G4--------~----------~

G3
TO
FUNCTION
GENERATORS

F2 -----+---I

F1--------~----------~--------~

F4

I

F3--------~----------~~------------------"~

X2000
GIN DOWN

Figure 14: Detail of XC4000E Dedicated Carry Logic

COUT
G1-----------r~

j------\,"

G4--------1-------------+-------~~

________________

~

COUTO
F2--------1--r~

}-------t--n

TO
FUNCTION
GENERATORS

F1--------1-------------+--------.

F3--------1----=~=-------~----------------__d

Figure 15: Detail of XC4000EX Dedicated Carry Logic (shaded areas show differences from XC4000E carry logic)

July 30, 1996 (Version 1.03)

4-23

XC4000 Series Field Programmable Gate Arrays

Input/Output Blocks (lOBs)
User-configurable inpuVoutput blocks (lOBs) provide the
interface between external package pins and the internal
logic. Each lOB controls one package pin and can be configured for input, output, or bidirectional signals.
Figure 16 shows a simplified block diagram of the
XC4000E lOB. A more complete diagram of the XC4000E
lOB can be found in Figure 42 on page 51, in the "Boundary
Scan" section. Figure 42 includes the boundary scan logic
in the lOB.
Figure 17 shows a simplified block diagram of the
XC4000EX lOB. The XC4000EX lOB contains some special features not included in the XC4000E lOB. These features are highlighted in Figure 17, and discussed
throughout this section. When XC4000EX special features
are discussed, they are clearly identified in the text. Any
feature not so identified is present in both XC4000E and
XC4000EX devices.

lOB Input Signals
Two paths, labeled 11 and 12 in Figure 16 and Figure 17,
bring input signals into the array. Inputs also connect to an
input register that can be programmed as either an edgetriggered flip-flop or a level-sensitive latch.
The choice is made by placing the appropriate library symbol. For example, IFD is the basic input flip-flop (rising
edge triggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are available, and
some combinations of latches and flip-flops can be implemented in a single lOB, as described in the XACT Libraries
Guide.
The inputs can be globally configured for either TTL (1.2V,
default) or CMOS thresholds, using an option in the MakeBits program. There is a slight hysteresis of about 300mV.
The output levels are also configurable; the two global
adjustments of input threshold and output level are independent.
Inputs of the low-voltage devices must be configured as
CMOS at all times. They can be driven by the outputs of all
5-Volt XC4000-Series devices, provided that the 5-Volt outputs are in TTL mode. They can also be driven by any TTL
output that does not exceed 3.7 V. 5-Volt XC3000-family
device outputs, for example, are TTL-compatible, but since
the output voltage can exceed 3.7 V, they cannot be used to
drive an XC4000L or XC4000XL input.

Table 10: Supported Sources for XC4000-Series Device
Inputs

3.3 V,
CMOS

Source
Any device, Vcc = 3.3 V,
CMOS outputs
XC4000-Series, Vcc = 5 V,
TTL outputs
Any device, Vcc = 5 V,
TTL outputs (Voh ~ 3.7 V)
Any device, Vcc = 5 V,
CMOS outputs

..j

..j

..j

..j

..j

..j

1. Acceptable for XC4000XL if the deSignated 5-Volt
supply pad (Vn ) is tied to 5V.

Registered Inputs
The 11 and 12 signals that exit the block can each carry
either the direct or registered input signal.
The input and output storage elements in each lOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000-Series CLB. It cannot be inverted within
the lOB.
The storage element behavior is shown in Table 11.
Table 11: Input Register Functionality
(active rising edge is shown)
Mode

Clock

Power-Up or
GSR
Flip-Flop

X

Latch

0' ~~=-~
o
1

Both

Clock
Enable
X

X

.

l'
1*

D

a

X

SR

-1-T-D--r-O
~ =p
t1·
X

oL_~.-9__

Legend:

X

_F
SR
O'
1•

Don't care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)

The inputs of XC4000-Series 5-Volt devices can be driven
by the outputs of any 3.3-Volt device, if the 5-Volt inputs are
in TTL mode.
Supported sources for XC4000-Series device inputs are
shown in Table 10.

4-24

July 30, 1996 (Version 1 .03)

~XILINX
1---------------------------------------------------,

T ,

Out---T-,4-----l

Output ~'~----l
Clock

'

Clock

'

I

Enable -+,-------+---1

Input

Clock ~,--+----l
- - - ... -

____ 1

X6704

Figure 16: Simplified Block Diagram of XC4000E lOB

T -;-4-----1

Out

Output Clock

~--I----------__l

11 - - + - - I - - - - - - - - - - - j

12 - - + - - I - - - - - - - - - - - j

Clock Enable

Input Clock

-.-~~----------+_~

~-----4_--__l

,
,

-------------------------------------~-------------------------~

X5984

Figure 17: Simplified Block Diagram of XC4000EX lOB (shaded areas indicate differences from XC4000E)

July 30; 1996 (Version 1.03)

4-25

XC4000 Series Field Programmable Gate Arrays

Optional Delay Guarantees Zero Hold Time
The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.
The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
lOB (not at the clock pin). Any routing delay from the
device clock pin to the clock input of the lOB must, therefore, be subtracted from this setup time to arrive at the real
setup time requirement relative to the device pins. A short
specified setup time might, therefore, result in a negative
setup time at the device pins, i.e., a positive hold-time
requirement.
When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maximum delay is therefore inserted as the default.
The XC4000E lOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See "Global Nets
and Buffers (XC4000E only)" on page 41 for a description
of the global clock buffers in the XC4000E.) For a shorter
input register setup time, with non-zero hold, attach a
NODELAY attribute or property to the flip-flop.
The XC4000EX lOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in Table 12. The choices are no added attribute,
MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000EX clock buffers, including the Global LowSkew buffers. MEDDELAY ensures no hold time with
respect to the Global Early and FastCLK buffers. Inputs
with NODELAY may have a positive hold time with respect
to all Clock buffers, including the FastCLK buffers. For a
description of each of these buffers, see "Global Nets and
Buffers (XC4000EX only)" on page 43.
Table 12: XC4000EX lOB Input Delay Element
Value
full delay
(default, no
attribute added)
MEDDELAY
--NODELAY

When to Use
Zero Hold with respect to Global LowSkew Buffer, Global Early Buffer, or
FastCLK Buffer
Zero Hold with respect to Global Early
Buffer or FastCLK Buffer
Short Setup, positive Hold time

Additional Input Latch for Fast Capture (XC4000EX
only)
The XC4000EX lOB has an additional optional latch on the
input. This latch, as shown in Figure 17, is clocked by the
output clock - the clock used for the output flip-flop rather than the input Clock. Therefore, two different clocks
can be used to clock the two input storage elements. This
additional latch allows the very fast capture of input data,
which is then synchronized to the internal clock by the lOB
flip-flop or latch.
To use this Fast Capture technique, drive the output clock
pin (the Fast Capture latching signal) from the output of one
of the Global Early or FastCLK buffers supplied in the
XC4000EX. The second storage element should be
clocked by a Global Low-Skew buffer, to synchronize the
incoming data to the illternallogic. (See Figure 18.) These
special buffers are described in "Global Nets and Buffers
(XC4000EX only)" on page 43.
The Fast Capture latch is designed primarily for use with a
Global Early buffer. For Fast Capture, a single Clock signal
is routed through both a Global Early buffer and a Global
Low-Skew buffer. (The two buffers share an input pad.)
The Fast Capture latch is Clocked by the Global Early
buffer, and the standard lOB flip-flop or latch is clocked by
the Global Low-Skew buffer. This mode is the safest way to
use the Fast Capture latch, because the clock buffers on
both storage elements are driven by the same pad. There
is no external skew between clock pads to create potential
problems.
Alternatively, a FastCLK buffer can be used to minimize the
setup time of device inputs, if a positive hold time is acceptable. Use the FastCLK buffer to clock the Fast Capture
latch, and a slower clock buffer to clock the standard lOB
flip-flop or latch. Either the Global Early buffer or the Global
Low-Skew buffer can be used for the second storage ele-

ILDFFDX
IPAD>-----r;:D;--r

Q

to internal

logic

BUFGLS

ILDFFDX
IPADl>-------' D

Q

BUFGLS

to internal
logic

X6705

Figure 18: Examples Using XC4000EX Fast
Capture Latch

4-26

July 30, 1996 (Version 1.03)

~XIUNX
ment, but whichever one is used should be the same clock
as the related internal logic. Since the FastCLK pads are
different from the Global Early and Global Low-Skew pads,
care must be taken to ensure that skew external to the
device does not create internal timing difficulties.
To place the Fast Capture latch in a design, use one of the
special library symbols, ILOFFOX or ILOFLOX. ILOFFOX
is a transparent-Low Fast Capture latch followed by an
active-High input flip-flop. ILOFLOX is a transparent-Low
Fast Capture latch followed by a transparent-High input
latch. Any of the clock inputs can be inverted before driving
the library element, and the inverter is absorbed into the
lOB. If a single BUFG output is used to drive both clock
inputs, the software automatically runs the clock through
both a Global Low-Skew buffer and a Global Early buffer,
and clocks the Fast Capture latch appropriately.
Figure 17 on page 25 also shows a two-tap delay on the
input. By default, if the Fast Capture latch is used, the Xilinx
software assumes a Global Early buffer is driving the clock,
and selects MEOOELAY to ensure a zero hold time. This
default can be overridden to remove the delay, if FastClk is
used, by attaching a NOOELAY attribute or property to the
ILOFFO or ILOFLOlatch. Select the desired delay based
on the discussion in the previous subsection.

lOB Output Signals
Output signals can be optionally inverted within the lOB,
and can pass directly to the pad or be s.tored in an edgetriggered flip-flop. The functionality of this flip-flop is shown
in Table 13.
An active-High 3-statesignal canbe used to place the output buffer in a high-impedance state, implementing 3-state
outputs or bidirectional I/O. Under configuration control,
the output (OUT) and output 3-state (T) signals can be
inverted. The polarity of these Signals is independently
configured for each lOB.
The 4-mA maximum output current specification of many
FPGAs often forces the user to add external buffers, which
are especially cumbersome on bidirectional I/O lines. The
XC4000E and XC4000EX devices solve many of these
problems by providing a guaranteed output sink current of
12 mA. Two adjacent outputs can be interconnected externally to sink up to 24 mA. (XC4000L and XC4000XL outputs can sink up to 4 mA, and two adjacent XC4000L and
XC4000XL outputs. can sink up to 8 rnA.) The XC4000E
and XC4000EX FPGAs can thus directly drive buses on a
printed circuit board.

Table 13: Output Flip-Flop Functionality (active rising
edge is shown)
Mode
Power-Up
orGSR

Clock
X

Flip-Flop

--.J

X
X
0

Clock
Enable
X

T
0*

D
X

SR

0
1*
X
X

0*
0*
1
0*

X

Q

0

0
Z

X
X

Q

Q

Legend:

X

__F
SR
0*
j*

z

Don't care
Rising edge
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
3-state

By default, the output pull-up structure is configured as a
TTL-like totem-pole. The High driver is an n-channel pullup transistor, pulling to a voltage one transistor threshold
below Vcc. Alternatively, the outputs can be globally configured as CMOS drivers, withp-channel pull-up transistors
pulling to Vcc. This MakeBits option applies to all outputs
on the device. It is not individually programmable.
Outputs of low-voltage devices must be configured as
CMOS at all times. They can drive the inputs of any 5-Volt
device with TTL-compatible thresholds.
Any XC4000-Series 5-Voltdevice with its outputs configured in TTL mode can drive the inputs of any typical 3.3Volt device. (For a detailed discussion of how to interface
between 5 V and 3.3 V devices, see the 3V Products section of The Programmable Logic Data Book.)
Supported destinations for XC4000-Series device outputs
are shown in Table 14.
Table 14: Supported Destinations for XC4000-Series
Outputs

Destination

XC4000-Series
Outputs
3.3 V,
5V,
5V,
CMOS TTL CMOS

Any typical device, Vce =3.3
CMOS-threshold inputs
Any device, Vcc =5 V,
TTL-threshold inputs
Any device, Vcc =5 V,
CMOS-threshold inputs
1. Only if destination device has 5-V tolerant inputs

July 30, 1996 (Version 1.03)

4-27

XC4000 Series Field Programmable Gate Arrays

J>--_~~
r-t?BUFT
X6702

Figure 19: Open-Drain Output
An output can be configured as open-drain (open-collector)
by placing an OBUFT symbol in a schematic or HDL code,
then tying the 3-state pin (T) to the output signal, and the
input pin (I) to Ground. (See Figure 19.)

Output Slew Rate
The slew rate of each output buffer is, by default, reduced,
to minimize power bus transients when switching non-critical signals. For critical signals, attach a FAST attribute or
property to the output buffer or flip-flop.
For XC4000E devices, maximum total capacitive load for
simultaneous fast mode switching in the same direction is
200 pF for all package pins between each Power/Ground
pin pair. For XC4000EX devices, additional internal Power/
Ground pin pairs are connected to special Power and
Ground planes within the packages, to reduce ground
bounce. Therefore, the maximum total capacitive load is
300 pF between each external Power/Ground pin pair.
Maximum loading may vary for the low-voltage devices.
For slew-rate limited outputs this total is two times larger for
each device type: 400 pF for XC4000E devices and 600 pF
for XC4000EX devices. This maximum capacitive load
should not be exceeded, as it can result in ground bounce
ofl;Jreater than 1.5 V amplitude and more than 5 ns duration. This level of ground bounce may cause undesired
transient behavior on an output, or in the internal logic.
This restriction is common to all high-speed digital ICs, and
is not particular to Xilinx or the XC4000 Series.
XC4000-Series devices have a feature called "Soft Startup," designed to reduce ground bounce when all outputs
are turned on simultaneously at the end of configuration.
When the configuration process is finished and the device
starts up, the first activation of the outputs is automatically
slew-rate limited. Immediately following the initial activation
of the I/O, the slew rate of the individual outputs is determined by the individual configuration option for each lOB.

GTS can be driven from any user-programmable pin as a
global 3-state input. To use this global net, place an input
pad and input buffer in the schematic or HDL code, driving
the GTS pin of the STARTUP symbol. A specific pin location can be assigned to this input using a LOC attribute or
property, just as with any other user-programmable pad.
An inverter can optionally be inserted after the input buffer
to invert the sense of the Global 3-State signal. Using GTS
is similar to GSR. See Figure 2 on page 13 for details.
Alternatively, GTS can be driven from any internal node.

Output Multiplexer/2-lnput Function Generator
(XC4000EX only)
As shown in Figure 17 on page 25, the output path in the
XC4000EX lOB contains an additional multiplexer not available in the XC4000E lOB. The multiplexer can also be configured asa 2-input function generator, implementing a
pass-gate, AND-gate, OR-gate, or XOR-gate, with 0, 1, or 2
inverted inputs. The logic used to implement these functions is shown in the upper gray area of Figure 17.
When configured as a multiplexer, this feature allows two
output signals to time-share the same output pad; effectively doubling the number of device outputs without requiring a larger, more expensive package.
When the MUX is configured as a 2-input function generator, logic can be implemented within the lOB itself. Combined with either a FastCLK or Global Early buffer, this
arrangement allows very high-speed gating of a single signal. For example, a wide decoder can be implemented in
CLBs, and its output gated with a Read or Write Strobe
driven by a FastCLK buffer, as shown in Figure 20. The
critical-path pin-to-pin delay of this circuit is less than 6
nanoseconds. (This value may not be achievable in
XC4000XL devices.)
As shown in Figure 17, the lOB input pins Out, Output
Clock, and Clock Enable have different delays and different
flexibilities regarding polarity. Additionally, Output Clock
sources are more limited than the other inputs. Therefore,
the Xilinx software does not move logic into the lOB function generators unless explicitly directed to do so.

Global Three-State
A separate Global 3-State line (not shown in Figure 16 or
Figure 17) forcesall FPGA outputs to the high-impedance
state, unless boundary scan is enabled and is executing an
EXTEST instruction. This global net (GTS) does not compete with other routing resources; it uses a dedicated distribution network.

4-28

from
intemal
logic

OAND2
X6698

Figure 20: Fast Pin-to-Pin Path in XC4000E

July 30, 1996 (Version 1.03)

~XILINX

=0OAND2

DO [520
01

~

Figure 21: Output AND and MUX Symbols in
XC4000EX lOB

The user can specify that the lOB function generator be
used, by placing special library symbols beginning with the
letter "0." For example, a 2-input AND-gate in the lOB function generator is called OAND2. Use the symbol input pin
labelled "F" for the signal on the critical path. This signal is
placed on the OK pin - the lOB input with the shortest
delay to the function generator. Two examples are shown in
Figure 21.

Other lOB Options
There are a number of other programmable options in the
XC4000-Series lOB.
Pull-up and Pull-down Resistors

Programmable pull-up and pull-down resistors are useful
for tying unused pins to Vcc or Ground to minimize power
consumption and reduce noise sensitivity. The configurable
pull-up resistor is a p-channel transistor that pulls to Vcc.
The configurable pull-down resistor is an n-channel transistor that pulls to Ground.
The value of these resistors is 50kn - 100 kg,· This high
value makes them unsuitable as wired-AND pull-up resistors.
The pull-up resistors for most user-programmable lOBs are
active during the configuration process, See Table 24 on
page 78 for a list of pins with pull-ups active before and during configuration.
After configuration, voltage levels of unused pads, bonded
or unbonded, must be valid logic levels, to reduce noise
sensitivity and avoid excess current. Therefore, by default,
unused pads are configured with the internal pull-up resistor active. Alternatively, they can be individually configured
with the pull-down resistor, or as a driven output, or to be
driven by an external source. To activate the internal pullup, attach the PULLUP library component to the net
attached to the pad. To activate the internal pull-down,
attach the PULLDOWN library component to the net
attached to the pad.
Independent Clocks

Separate clock signals are provided for the input and output
flip-flops. The clock can be independently inverted for each
flip-flop within the lOB, generating either falling-edge or rising-edge triggered flip-flops. The clock inputs for each lOB

July 30, 1996 (Version 1.03)

are independent, except that in the XC4000EX, the Fast
Capture latch shares an lOB input with the output clock pin,
Early Clock for lOBs (XC4000EX only)

Special early clocks are available for lOBs, These clocks
are sourced by the same sources as the Global LOW-Skew
buffers, but are separately buffered, They have fewer loads
and therefore less delay. The early clock can drive either
the lOB output clock or the lOB input clock, or both, The
early clock allows fast capture of input data, and fast clockto-output on output data. The Global Early buffers that
drive these clocks are described in "Global Nets and Buffers (XC4000EX only)" on page 43.
Fast Clock for lOBs (XC4000EX only)

Very fast clocks driven by FastCLK buffers are also available for lOBs. These clocks are sourced by semi-dedicated
pads-the pads can be used as general 110 if not used to
drive FastCLK buffers. There are two FastCLK buffers on
the left edge, and two on the right edge of the device. They
provide the fastest method of reaching the lOB clock pins.
The FastCLK buffer can drive either the lOB output clock or
the lOB input clock, or both, These buffers allow the fastest
possible setup times and clock-to-output times. The FastCLK buffers are described in "Global Nets and Buffers
(XC4000EX only)" on page 43.
Global Set/Reset

As with the CLB registers, the Global Set/Reset signal
(GSR) can be used to set or clear the input and output registers, depending on the value of the INIT attribute or property, The two flip-flops can be individually configured to set
or clear on reset and after configuration. Other than the
global GSR net, no user-controlled set/reset signal is available to the 110 flip-flops. The choice of set or clear applies
to both the initial state of the flip-flop and the response to
the Global Set/Reset pulse. See "Global Set/Reset" on
page 13 for a description of how to use GSR,
JTAG Support
Embedded logic attached to the lOBs contains test structures compatible with IEEE Standard 1149,1 for boundary
scan testing, permitting easy chip and board-level testing.
More information is provided in "Boundary Scan" on
page 50.

Three-State Buffers
A pair of 3-state buffers is associated with each CLB in the
array. (See Figure 27 on page 34.) These 3-state buffers
can be used to drive signals onto the nearest horizontal
longlines above and below the CLB. They can therefore be
used to implement multiplexed or bidirectional buses on the
horizontal longlines, saving logic resources, Programmable pull-up resistors attached to these longlines help to
implement a wide wired-AND function,

4-29

I

XC4000 Series Field Programmable Gate Arrays

The buffer enable is an active-High 3-state (i.e. an activeLow enable), as shown in Table 15.

WAND4, WAND8, and WAND16 are also available. See
the XACT Libraries Guide for further information.

Another 3-state buffer with similar access is located near
each I/O block along the right and left edges of the array.
(See Figure 33 on page 39.)

The T pin is internally tied to the I pin. Connect the input to
the I pin and the output to the 0 pin. Connect the outputs of
all the WAND1s together and attach a PULLUP symbol.

The horizontallonglines driven by the 3-state buffers have a
weak keeper at each end. This circuit prevents undefined
floating levels. However, it is overridden by any driver, even
a pull-up resistor.

Wired OR-AND

Special longlinesrunning along the perimeter of the array
can be used to wire-AND signals coming from nearby lOBs
or from internal longlines. These longlines form the wide
edge decoders discussed in "Wide Edge Decoders" on
page 31.

Three-State Buffer Examples

Three-State Buffer Modes
The 3-state buffers can be configured in three modes:
•
•
•

The buffer can be configured as a Wired OR-AND. A High
level on either input turns off the output.
Use the
WOR2AND library symbol, which is essentially an opendrain 2-input OR gate. The two input pins are functionally
equivalent. Attach the two inputs to the 10 and 11 pins and
tie the output to the 0 pin. Tie the outputs of all the
WOR2ANDs together and attach a PULLUP symbol.

Standard 3-state buffer
Wired-AND with input on the I pin
Wired OR-AND

Figure 22 shows how to use the 3-state buffers to implement a wired-AND function. When all the buffer inputs are
High, the pull-up resistor(s) provide the High output.
Figure 23 shows how to use the 3-state buffers to implement a multiplexer. The selection is accomplished by the
buffer 3-state signal.

Standard 3-State Buffer
All three pins are used. Place the library element BUFT.
Connect the input to the I pin and the output to the 0 pin.
The T pin is an active-High 3-state (i.e. an active-Low
enable). Tie the T pin to Ground to implement a standard
buffer.

Pay particular attention to the polarity of the T pin when
using these buffers in a design. Active-High 3-state (T) is
identical to an active-Low output enable, as shown in
Table 15.

Table 15: Three·State Buffer Functionality
IN

Wired·AND with Input on the I Pin

T

OUT

o

IN

x

The buffer can be used as a Wired-AND. Use the WAND1
library symbol, which is essentially an open-drain buffer.

z

IN

WOR2AND

WOR2AND

Figure 22: Open·Drain Buffers Implement a Wired·AND Function

;------------------------------------------1

i
.

r-~!--------~r---Z-=D-A-.A--+-D-B-.B~+~D-C-.C-+-D-N.-N----~--------__~~
.

o . _ _ _ _ _ _ _ _ _ _ _ _ _ _ . _ • • _ _ _ _ _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ • ___ I

"Weak Keeper"

Figure 23: 3-State Buffers Implement a Multiplexer

4-30

July 30, 1996 (Version 1.03)

~XILINX
Wide Edge Decoders
INTERCONNECT

Dedicated decoder circuitry boosts the performance of
wide decoding functions. When the address or data field is
wider than the function generator inputs, FPGAs need
multi-level decoding and are thus slower than PALs.
XC4000-Series CLBs have nine inputs. Any decoder of up
to nine inputs is, therefore, compact and fast. However,
there is also a need for much wider decoders, especially for
address decoding in large microprocessor systems.
C) .....

An XC4000-Series FPGA has four programmable decoders located on each edge of the device. The inputs to each
decoder are any of the lOB 11 signals on that edge plus one
local interconnect per CLB row or column. Each row or column of CLBs provides up to three variables or their compliments., as shown in Figure 24. Each decoder generates a
High output (resistor pull-up) when the AND condition of
the selected inputs, or their complements, is true. This is
analogous to a product term in typical PAL devices.
Each of these wired-AND gates is capable of accepting up
to 42 inputs on the XC4005E and 72 on the XC4013E.
There are up to 96 inputs for each decoder on the
XC4028EX and 132 on the XC4052EX. The decoders may
also be split in two when a larger number of narrower
decoders are required, for a maximum of 32 decoders per
device.
The decoder outputs can drive CLB inputs, so they can be
combined with other logic to form a PAL-like ANDIOR structure. The decoder outputs can also be routed directly to the
chip outputs. For fastest speed, the output should be on
the same chip edge as the decoder. Very large PALs can
be emulated by ORing the decoder outputs in a CLB. This
decoding feature covers what has long been considered a
weakness of older FPGAs. Users often resorted to external PALs for simple but fast decoding functions. Now, the
dedicated decoders in the XC4000-Series device can
implement these functions fast and efficiently.
To use the wide edge decoders, place one or more of the
WAND library symbols (WAND1, WAND4, WAND8,
WAND16). Attach a DECODE attribute or property to each
WAND symbol. Tie the outputs together and attach a PULLUP symbol. Location attributes or properties such as L
(left edge) orTR (right half of top edge) should also be used
to ensure the correct placement of the decoder inputs.

---4-+---1-+----4.---+----

(A' B· C)

..

---4-+----<~+---+_--*---- (A' B .C) ....

--+-+-----.jf--+--+---+---- (A' B· C) ..
X2627

Figure 24: XC4000·Series Edge Decoding Example

On-Chip Oscillator
XC4000-Series devices include an internal oscillator. This
oscillator is used to clock the power-on time-out, for configuration memory clearing, and as the source of CCLK in
Master configuration modes. The oscillator runs at a nominal 8 MHz frequency that varies with process, Vcc, and
temperature. The output frequency falls between 4 and 10
MHz. (The oscillator operates more slowly at lower voltages. The output frequency may be reduced by as much
as 10% for low-voltage devices.)
The oscillator output is optionally available after configuration. Any two of four resynchronized taps of a built-in
divider are also available. These taps are at the fourth,
ninth, fourteenth and nineteenth bits of the divider. Therefore, if the primary oscillator output is running at the nominal 8 MHz, the user has access to an 8 MHz clock, plus any
two of 500 kHz, 16kHz, 490Hz and 15Hz (up to 10% lower
for low-voltage devices). These frequencies can vary by as
much as -50% or +25%.
These signals can be accessed by plaCing the OSC4
library element in a schematic or in HDL code (see
Figure 25).
The oscillator is automatically disabled after configuration if
the OSC4 symbol is not used in the design.

OSC4
FsM
F500K
F16K
F490
F15
X6703

Figure 25: XC4000-Series Oscillator Symbol

July 30, 1996 (Version 1.03)

4-31

I

XC4000 Series Field Programmable Gate Arrays

Programmable Interconnect

CLB Routing Connections

All internal connections are composed of metal segments
with programmable switching points and switching matrices
to implement the desired routing. A structured, hierarchical
matrix of routing resources is provided to achieve efficient
automated routing.

A high-level diagram of the routing resources associated
with one CLB is shown in Figure 26. The shaded arrows
represent routing present only in XC4000EX devices.

The XC4000E and XC4000EX share a basic interconnect
structure. XC4000EX devices, however, have additional
routing not available in the XC4000E. The extra routing
resources allow high utilization in high-capacity devices.
All XC4000EX-specific routing resources are clearly identified throughout this section. Any resources not identified
as XC4000EX-specific are present in all XC4000-Series
devices.
This section describes the varied routing resources available in XC4000-Series devices. The implementation software automatically assigns the appropriate resources
based on the density and timing requirements of the
design.

Interconnect Overview
There are several types of interconnect.
•

CLB routing is associated with each row and column of
the CLB array.
• lOB routing forms a ring (called a VersaRing) around
the outside of the CLB array. It connects the I/O with
the internal logic blocks.
• Global routing consists of dedicated networks primarily
designed to distribute clocks throughout the device with
minimum delay and skew. Global routing can also be
used for other high-fanout signals.
Five interconnect types are distinguished by the relative
length of their segments: single-length lines, double-length
lines, quad and octal lines (XC4000EX only), and longlines.
In the XC4000EX, direct connects allow fast data flow
between adjacent CLBs, and between lOBs and CLBs.
Extra routing is included in the lOB pad ring. The
XC4000EX also includes a ring of octal interconnect lines
near the lOBs to improve pin-swapping and routing to
locked pins.

Table 16 shows how much routing of each type is available
in XC4000E and XC4000EX CLB arrays. Clearly, very
large designs, or designs with a great deal of interconnect,
will route more easily in the XC4000EX. Smaller XC4000E
designs, typically requiring significantly less interconnect,
do not require the additional routing.
Figure 27 on page 34 is a detailed diagram of both the
XC4000E and the XC4000EX CLB, with associated routing. The shaded square is the programmable switch
matrix, present in both the XC4000E and the XC4000EX.
The L-shaped shaded area is present only in XC4000EX
devices. As shown in the figure, the XC4000EX block is
essentially an XC4000E block with additional routing.
CLB inputs and outputs are distributed on all four sides,
providing maximum routing flexibility. In general, the entire
architecture is symmetrical and regular. It is well suited to
established placement and routing algorithms. Inputs, outputs, and function generators can freely swap positions
within a CLB to avoid routing congestion during the placement and routing operation.
Table 16: Routing per CLB in XC4000-Series Devices

Singles
Doubles
Quads
Longlines
Direct
Connects
Globals
Carry Logic
Total

XC4000EX
XC4000E
Vertical Horizontal Vertical Horizontal
8
8
8
8
4
4
4
4
12
12
0
0
10
6
6
6
2
2
0
0
4
2
24

0
0
18

8
1

45

0
0
32

XC4000E devices include two types of global buffers, while
XC4000EX devices have three different types. These global buffers have different properties, and are intended for
different purposes. They are discussed in detail later in this
section.

4-32

July 30, 1996 (Version 1.03)

~:XILINX

Quad
Single
Double
Long

Direct
Connect

I

Long

Quad

Long

Global
Clock

Long

Double Single Global
Clock

Carry Direct
Chain Connect
x5994

Figure 26: High-Level Routing Diagram of XC4000-Series CLB (shaded arrows indicate XC4000EX only)

July 30, 1996 (Version 1.03)

4-33

XC4000 Series Field Programmable Gate Arrays

~

1111~r;:~*=DIRECT

o

CLB ~;
::~=n=} FEEDBACK

,
'0

Common to XC4000E and XC4000EX

D XC4000EX only
•

Programmable Switch Matrix

Figure 27: Detail of Programmable Interconnect Associated with XC4000-Series CLB

4-34

July 30, 1996 (Version 1.03)

~XILINX
Single-Length Lines
~0

Double

~,0

o~o/~/! . . ~_

Double

"",,., j

~00

--.---H-1--t-H-t-t-H-r-

,.

.,

Six Pass Transistors
Per Switch Matrix
Interconnect Point

X6600

Figure 28: Programmable Switch Matrix (PSM)

Programmable Switch Matrices
The horizontal and vertical single- and double-length lines
intersect at a box called a programmable switch matrix
(PSM). Each switch matrix consists of programmable pass
transistors used to establish connections between the lines
(see Figure 28).
For example, a single-length signal entering on the right
side of the switch matrix can be routed to a single-length
line on the top, left, or bottom sides, or any combination
thereof, if multiple branches are required. Similarly, a double-length signal can be routed to a double-length line on
any or all of the other three edges of the programmable
switch matrix.

Single-length lines provide the greatest interconnect flexibility and offer fast routing between adjacent blocks. There
are eight vertical and eight horizontal single-length lines
associated with each CLB. These lines connect the switching matrices that are located in every row and a column of
CLBs.
Single-length lines are connected by way of the programmable switch matrices, as shown in Figure 29. Routing
connectivity is shown in Figure 27.
Single-length lines incur a delay whenever they go through
a switching matrix. Therefore, they are not suitable for routing signals for long distances. They are normally used to
conduct signals within a localized area and to provide the
branching for nets with fanout greater than one.

Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a switch matrix. Double-length
lines are grouped in pairs with the switch matrices staggered, so that each line goes through a switch matrix at
every other row or column of CLBs (see Figure 29).
There are four vertical and four· horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility. Double-length lines are connected by way
of the programmable switch matrices. Routing connectivity
is shown in Figure 27.

Doubles

~~~~

Singles
Doubles

X660i

Figure 29: Single- and Double-Length Lines, with Programmable Switch Matrices (PSMs)

July 30, 1996 (Version 1.03)

4-35

I

XC4000 Series Field Programmable Gate Arrays

Quad Lines (XC4000EX only)
XC4000EX devices also include twelve vertical and twelve
horizontal quad lines per CLB row and column. Quad lines
are four times as long as the single-length lines. They are
interconnected via buffered switch matrices (shown as diamonds in Figure 27 on page 34). Quad lines run past four
CLBs before entering a buffered switch matrix. They are
grouped in fours, with the buffered switch matrices staggered, so that each line goes throLlgh a buffered sWitch
matrix at every fourth CLB location in that row or column.
(See Figure 30.)
The buffered switch matrixes have four pins,one on each
edge. All of the pins are bidirectional. Any pin can drive
any or all of the other pins.

Each buffered switch matrix contains one buffer and six
pass transistors. It resembles the programmable switch
matrix shown in Figure 28, with the addition of a programmable buffer. There can be up to two independent inputs
and up to two independent outputs. Only one of the independent inputs can be buffered.
The place and route software automatically uses the timing
requirements of the design to determine whether or not a
quad line signal should be buffered. A heavily loaded signal is typically buffered, while a lightly loaded one is not.
One scenario is to alternate buffers and pass transistors.
This allows both vertical and horizontal quad lines to be
buffered at alternating buffered switch matrices.
Due to the buffered switch matrices, quad lines are very
fast. They provide the fastest available method of routing
heavily loaded signals for long distances across the device.

ICLBI

\CLBI

ICLBI

ICLBI

ICLB I

ICLBI

ICLB I

ICLBI

ICLB I

ICLB I

ICLB I

ICLB I

ICLBI

ICLBI

ICLBI

ICLBI

ICLBI

\CLB I

ICLBI

ICLBI

ICLB\

ICLBI

ICLB I

ICLBI

ICLB I

~

-

-

-

~

I
X6602

Figure 30: Quad Lines (XC4000EX only)

4-36

July 30, 1996 (Version 1.03)

~XILINX
Longlines

Direct Interconnect (XC4000EX only)

Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances. In XC4000EX
devices, quad lines are preferred for critical nets, because
the buffered switch matrices make them faster for high fanout nets.

The XC4000EX offers two direct, efficient and fast connections between adjacent CLBs. These nets facilitate a data
flow from the left to the right side of the device, or from the
top to the bottom, as shown in Figure 31. Signals routed on
the direct interconnect exhibit minimum interconnect propagation delay and use no general routing resources.

Two horizontal long lines per CLB can be driven by 3-state
or open-drain drivers (TBUFs). They can therefore implement unidirectional or bidirectional buses, wide mUltiplexers, or wired-AND functions. (See "Three-State Buffers" on
page 29 for more details.)
Each horizontal longline driven by TBUFs has either two
(XC4000E) or eight (XC4000EX) pull-up resistors. To activate these resistors, attach a PULLUP symbol to the longline net. The software automatically activates the appropriate number of pull-ups. There is also a weak keeper at
each end of these two horizontallonglines. This circuit prevents undefined floating levels. However, it is overridden by
any driver, even a pull-up resistor.

The direct interconnect is also present between CLBs and
adjacent lOBs. Each lOB on the left and top device edges
has a direct path to the nearest CLB. Each CLB on the
right and bottom edges of the array has a direct path to the
nearest two lOBs, since there are two lOBs for each row or
column of CLBs.
The place and route software uses direct interconnect
whenever possible, to maximize routing resources and minimize interconnect delays.

I

Each XC4000E longline has a programmable splitter switch
at its center, as does each XC4000EX longline driven by
TBUFs. This switch can separate the line into two independent routing channels, each running half the width or height
of the array.
Each XC4000EX long line not driven by TBUFs has a buffered programmable splitter switch at the 1/4, 1/2, and 3/4
points of the array. Due to the buffering, XC4000EX longline performance does not deteriorate with the larger array
sizes. If the longline is split, the resulting partial long lines
are independent.
Routing connectivity of the longlines is shown in Figure 27
on page 34.

July 30,1996 (Version 1.03)

Figure 31: XC4000EX Direct Interconnect

4-37

XC4000 Series Field Programmable Gate Arrays

1/0 Routing
XC4000-Series devices have additional routing around the
lOB ring. This routing is called a VersaRing. The
VersaRing facilitates pin-swapping and redesign without
affecting board layout. Included are eight double-length
lines spanning two CLBs (four lOBs), and four longlines.
Global lines and Wide Edge Decoder lines are provided.
XC4000EX devices also include eight octal lines.

Figure 33 is a detailed diagram of the XC4000E and
XC4000EX VersaRing. The area shown includes two lOBs.
There are two lOBs per CLB row or column, therefore this
diagram corresponds to the CLB routing diagram shown in
Figure 27 on page 34. The shaded areas represent routing
and routing connections present only in XC4000EX
devices.

A high-level diagram of the VersaRing is shown in
Figure 32. The shaded arrows represent routing present
only in XC4000EX devices.

•

• • •~Quad

~----,::--" Single
Double
Long
• • • • • Direct
Connect
Long

Direct
Connect

Edge Double Long Global Octal
Decode
Clock
X5995

Figure 32: High-Level Routing Diagram of XC4000-Series VersaRing (Left Edge)
WED = Wide Edge Decoder, lOB = 1/0 Block (shaded arrows indicate XC4000EX only)

4-38

July 30, 1996 (Version 1.03)

~:XILINX

IOUAD

T

0
DOUBLE

}"NG~

C
L
B

DOUBLE

LONG

DIRECT

A
R
R
A
Y

LONG

D

Common to XC4000E and XC4000EX
XC4000EX only

Figure 33: Detail of Programmable Interconnect Associated with XC4000-Series10B (Left Edge)

July 30, 1996 (Version 1.03)

4-39

I

XC4000 Series Field Programmable Gate Arrays

Octal 110 Routing (XC4000EX only)
Between the XC4000EX CLB array and the pad ring, eight
interconnect tracks provide for versatility in pin assignment
and fixed pinout flexibility. (See Figure 34.)
These routing tracks are called octals, because they can be
broken every eight CLBs (sixteen lOBs) by a programmable buffer that also functions as a splitter switch. The buffers are staggered, so each line goes through a buffer at
every eighth CLB location around the device edge.
The octal lines bend around the corners of the device. The
lines cross at the corners in such a way that the segment

most recently buffered before the turn has the farthest distance to travel before the next buffer, as shown in
Figure 34.
lOB inputs and outputs interface with the octal lines via the
single-length interconnect lines. Single-length lines are
also used for communication between the octals and double-length lines, quads, and longlines within the CLB array.
Segmentation into buffered octals was found to be optimal
for distributing signals over long distances around the
device.

•••
lOB

lOB

Segment with nearest buffer
connects to segment with furthest buffer

I

¢

•

•
•

•

•
•

lOB

~

lOB

lOB

lOB

§t

•••

Figure 34: XC4000EX Octal VO Routing

4-40

July 30, 1996 (Version 1.03)

~:XlllNX
Global Nets and Buffers
Both the XC4000E and the XC4000EX have dedicated global networks. These networks are designed to distribute
clocks and other high fanout control signals throughout the
The global buffers are
devices with minimal skew.
described in detail in the following sections. The text
descriptions and diagrams are summarized in Table 17.
The table shows which CLB and lOB clock pins can be
sourced by which global buffers.
In both XC4000E and XC4000EX devices, placement of a
library symbol called BUFG results in the software choosing the appropriate clock buffer, based on the timing
requirements of the design. The detailed information in
these sections is included only for reference.

Global Nets and Buffers (XC4000E only)
Four vertical longlines in each CLB column are driven
exclusively by special global buffers. These longlines are
in addition to the vertical longlines used for standard interconnect. The four global lines can be driven by either of
two types of global buffers. The clock pins of every CLB
and lOB can also be sourced from local interconnect.
Two different types of clock buffers are available in the
XC4000E:
•
•

Primary Global Buffers (BUFGP)
Secondary Global Buffers (BUFGS)

Four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to potentially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs.
The Primary Global buffers must be driven by the semidedicated pads. The Secondary Global buffers can be
sourced by either semi-dedicated pads or internal nets.
Each CLB column has four dedicated vertical Global lines.
Each of these lines can be accessed by one particular Primary Global buffer, or by any of the Secondary Global buffers, as shown in Figure 35. Each corner of the device has
one Primary buffer and one Secondary buffer.
lOBs along the left and right edges have four vertical global
longlines. Top and bottom lOBs can be clocked from the
global lines in the adjacent CLB column.
A global buffer should be specified for all timing-sensitive
global signal distribution. To use a global buffer, place a
BUFGP (primary buffer), BUFGS (secondary buffer), or
BUFG (either primary or secondary buffer) element in a
schematic or in HDL code. If desired, attach a LOC
attribute or property to direct placement to the designated
location. For example, attach a LOC=L attribute or property
to a BUFGS symbol to direct that a buffer be placed in one
of the two Secondary Global buffers on the left edge of the
device, or a LOC=BL to indicate the Secondary Global
buffer on the bottom edge of the device, on the left.

Table 17: Clock Pin Access

lOBs on Adjacent Vertical
Half Edge
lOBs on Adjacent Vertical
Full Edge
lOBs on Adjacent Horizontal
Half Edge (Direct)
lOBs on Adjacent Horizontal
Half Edge (through CLB globals)
lOBs on Adjacent Horizontal
Full Edge (through CLB globals)
L = Left, R = Right, T

=Top, B = Bottom

July 30, 1996 (Version 1.03)

4-41

I

XC4000 Series Field Programmable Gate Arrays

108

108

BUFGS

BUFGP

D-t>---

----+-D
PGCK4

SGCK1

108

108
}

Any BUFGS

1

Any BUFGS

One BUFGP
per Global Line

108

i

One BUFGP
per Global Line

108

PGCK2

SGCK3

~

0--.-

SGCK2

BUFGP

PGCK3

BUFGS

108

108

108

108

Figure 35: XC4000E Global Net Distribution

lOB

BUFGLS

lOB

lOB

lOB

BUFGLS

n

GCK7

---+------'I---r-------t-B"'U·FG-E-'OO.,

GCK6

""ffi"

f----~--I SUFFCLK

XB

k::::::~~--:g
8 BUFGlS
FCLK4
locals-

lOB

lOB

CLOCKS

I'OB
lOB

CLOCKS

GLS CLOCKS
(PER COLUMN)

CLB CLOCKS
(PER COLUMN)

CLB CLOCKS
(PER COLUMN)

ClB CLOCKS
(PER COLUMN)

lOB
CLOCKS

I

lOB

lOB
CLOCKS

lOB

B

locals
FCLK2

SUFFCLK

BUFGlS

Aj

f-J
D

SUFFCLK

BUFGE

BUFGE

BUFGE

BUFGE

GCK2

lA
4D

BUFGLS

GCK5

BUFGLS

lOB

lOB

lOB

lOB

BUFGlS

X6694

Figure 36: XC4000EX Global Net Distribution

4-42

July 30, 1996 (Version 1.03)

~XILINX
Global Nets and Buffers (XC4000EX only)
Eight vertical longlines in each CLB column are driven by
special global buffers. These longlines are in addition to
the vertical longlines used for standard interconnect. The
global lines are broken in the center of the array, to allow
faster distribution and to minimize skew across the whole
array. Each half-column global line has its own buffered
multiplexer, as shown in Figure 36. The top and bottom global lines cannot be connected across the center of the
device, as this connection might introduce unacceptable
skew. The top and bottom halves of the global lines must
be separately driven - although they can be driven by the
same global buffer.
The eight global lines in each CLB column can be driven by
either of two types of global buffers. They can also be
driven by internal logic, because they can be accessed by
single, double, and quad lines at the top, bottom, half, and
quarter points. Consequently, the number of different
clocks that can be used simultaneously in an XC4000EX
device is very large.
There are four global lines feeding the lOBs at the left edge
of the device. lOBs along the right edge have eight global
lines. There is a single global line along the top and bottom
edges with access to the lOBs. All lOB global lines are broken at the center. They cannot be connected across the
center of the device, as this connection might introduce
unacceptable skew.
lOB global lines can be driven from any of three types of
global buffers, or from local interconnect. Alternatively, top
and bottom lOBs can be clocked from the global lines in the
adjacent CLB column.
Three different types of clock buffers are available in the
XC4000EX:
•
•
•

Global Low-Skew Buffers (BUFGLS)
Global Early Buffers (BUFGE)
FastCLK Buffers (BUFFCLK)

Global Low-Skew Buffers a:re the standard clock buffers.
They should be used for most internal clocking, whenever a
large portion of the device must be driven.
Global Early Buffers are designed to provide a faster clock
access, but CLB access is limited to one-fourth of the
device. They also facilitate a faster 1/0 interface.
FastCLK buffers are specifically designed to provide the
fastest possible I/O clock. They have only the standard
input access to CLBs, through local interconnect.
Figure 36 is a conceptual diagram of the global net structure in the XC4000EX.
Global Early buffers and Global Low-Skew buffers share a
single pad. Therefore, the same IPAD symbol can drive
one buffer of each type, in parallel. This configuration is
particularly useful when uSing the Fast Capture latches, as
described in "lOB Input Signals" on page 24. Paired Global

July 30, 1996 (Version 1.03)

Early and Global Low-Skew buffers share a common input;
they cannot be driven by two different signals.
Choosing an XC4000EX Clock Buffer

The clocking structure of the XC4000EX provides a large
variety of features. However, it can be simple to use, without understanding all the details. The software automatically handles clocks, along with all other routing, when the
appropriate clock buffer is placed in the design. In fact, if a
buffer symbol called BUFG is placed, rather than a specific
type of buffer, the software even chooses the buffer most
appropriate for the design. The detailed information in this
section is provided for those users who want a finer level of
control over their designs.
If fine control is desired, use the following summary and
Table 17 on page 41 to choose an appropriate clock buffer.
•
•

•

•

The simplest thing to do is to use a Global Low-Skew
buffer.
If a faster clock path is needed, try a BUFG. The
software will first try to use a Global Low-Skew Buffer. If
timing requirements are not met, a faster buffer will
automatically be used.
If a single quadrant of the chip is sufficient for the
clocked logic, and the timing requires a faster clock than
the Global Low-Skew buffer, use a Global Early buffer.
In special cases, where both external and internal
timing have been carefully studied, a FastCLK buffer
can be used, for the fastest possible I/O clock path.

Global Low-Skew Buffers

Each corner of the XC4000EX device has two Global LowSkew buffers. Any of the eight Global Low-Skew buffers
can drive any of the eight vertical Global lines in a column
of CLBs. In addition, any of the buffers can drive any of the
four vertical lines accessing the lOBs on the left edge of the
device, and any of the eight vertical lines accessing the
lOBs on the right edge of the device. (See Figure 37 on
page 44.)
lOBs at the top and bottom edges of the device are
accessed through the vertical Global lines in the CLB array,
as in the XG4000E. Any Global Low-Skew buffer can,
therefore, access every lOB and CLB in the device.
The Global Low-Skew buffers can be driven by either semidedicated pads or internal logic.
To use a Global Low-Skew buffer, place a BUFGLS element in a schematic or in HDL code. If desired, attach a
LOC attribute or property to direct placement to the designated location. For example, attach a LOC= T attribute or
property to direct that a BUFGLS be placed in one of the
two Global Low-Skew buffers on the top edge of the device,
or a LOC=TR to indicate the Global Low-Skew buffer on the
top edge of the device, on the right.

4-43

I

XC4000 Series Field Programmable Gate Arrays

8

1",

I> _ , "I

I
I

7
"a •••
, "'•••
ala"" ",6

I
I
A5

4

X6751

X6753

Figure 37: Any BUFGLS (GCK1 - GCK8) Can
Drive Any or All Clock Inputs on the Device

Figure 38: Left and Right BUFGEs Can Drive Any or
All Clock Inputs in Same Quadrant or Edge (GCK1 is
shown. GCK2, GCKS and GCK6 are similar.)

Global Early Buffers
Each corner of the XC4000EX device has two Global Early
buffers. The primary purpose of the Global Early buffers is
to provide an earlier clock access than the potentially
heavily-loaded Global Low-Skew buffers. A clock source
applied to both buffers will result in the Global Early clock
edge occurring several nanoseconds earlier than the Global Low-Skew buffer clock edge, due to the lighter loading.
Global Early buffers also facilitate the fast capture of device
inputs, using the Fast Capture latches described in "lOB
Input Signals" on page 24. For Fast Capture, take a single
clock signal, and route it through both a Global Early buffer
and a Global Low-Skew buffer. (The two buffers share an
input pad.) Use the Global Early buffer to clock the Fast
Capture latch, and the Global LOW-Skew buffer to clock the
normal input flip-flop or latch, as shown in Figure 18 on
page 26.
The Global Early buffers can also be used to provide a fast
Clock-to-Out on device output pins. However, an early
clock in the output flip-flop lOB must be taken into c;onsideration when calculating the internal clock speed for the
design.

The left-side Global Early buffers can each drive two of the
four vertical lines accessing the lOBs on the entire left edge
of the device. The right-side Global Early buffers can each
drive two of the eight vertical lines accessing the lOBs on
the entire right edge of the device. (See Figure 38.)
Each left and right Global Early buffer can also drive half of
the lOBs along either the top or bottom edge of the device,
using a dedicated line that can only be accessed through
the Global Early buffers.
The top and bottom Global Early buffers can drive half of
the lOBs along either the left or right edge of the device, as
shown in Figure 39. They can only access the top and bottom lOBs via the CLB global lines.

7
'--_-"'IO"'B_----.11  D

10B.0

UPDATE

DATAOUT

SHIFT!
CAPTURE

EXTEST

CLOCK DATA

REGISTEA

Figure 43: XC4000-Series Boundary Scan Logic

4-52

July 30, 1996 (Version 1.03)

~:XILINX
Bit Sequence
The bit sequence within each lOB is: In, Out, 3-State. The
input-only MO and M2 mode pins contribute only the In bit
to the boundary scan I/O data register, while the outputonly M1 pin contributes all three bits.
The first two bits in the I/O data register are TDO.T and
TDO.O, which can be used for the capture of internal signals. The final bit is BSCANT.UPD, which can be used to
drive an internal net. These locations are primarily used by
Xilinx for internal testing.
From a cavity-up view of the chip (as shown in XDE or
Epic), starting in the upper right chip corner, the boundary
scan data-register bits are ordered as shown in Figure 44.
The device-specific pinout tables for the XC4000 Series
include the boundary scan locations for each lOB pin.
BSDL (Boundary Scan Description Language) files for
XC4000-Series devices are available on the Xilinx BBS.

Including Boundary Scan in a Schematic
If boundary scan is only to be used during configuration, no
special schematic elements need be included in the schematic or HDL code. In this case, the special boundary scan
pins TDI, TMS, TCK and TDO can be used for user functions after configuration.

Even if the boundary scan symbol is used in a schematic,
the input pins TMS, TCK, and TDI can still be used as
inputs to be routed to internal logic. Care must be taken not
to force the chip into an undesired boundary scan state by
inadvertently applying boundary scan input patterns to
these pins. The simplest way to prevent this is to keep TMS
High, and then apply whatever signal is desired to TDI and
TCK.

Avoiding Inadvertent Boundary Scan
Activation
If TMS or TCK is used as user I/O, care must be, taken to
ensure that at least one of these pins is held constant during configuration. In some applications, a situation may
occur where TMS or TCK is driven during configuration.
This may cause the device to go into boundary scan mode
and disrupt the configuration process.
To prevent activation of boundary scan during configuration, do either of the following:
•
•

TMS: Tie High to put the Test Access Port controller
in a benign RESET state
TCK: Tie High or LOW-don't toggle this clock input.

For more information regarding boundary scan, refer to the
Xilinx Application Note XAPP 017.001, "Boundary Scan in
XC4000E Devices."

To indicate that boundary scan remain enabled after configuration, place the BSCAN library symbol and connect the
TDI, TMS, TCK and TDO pad symbols to the appropriate
pins, as shown in Figure 45.

Bit 0 ( TOO end)
Bit 1
Bit 2

TOO.T
TOO.O
{ Top-edge lOBs (Right to Left)

{ Left-edge lOBs (Top to Bottom)
MD1.T
MD1.0
MD1.1
MDO.I
MD2.1
{ Bottom-edge lOBs (Left to Right)

Figure 45: Boundary Scan Schematic Example

{ Right-edge lOBs (Bottom to Top)
(TOI end)

B SCANT.UPD

X6075

Figure 44:

Boundary Scan Bit Sequence

July 30, 1996 (Version 1.03)

4-53

I

XC4000 Series Field Programmable Gate Arrays

Confi~uration

Table 20: Configuration Modes

Configur!3.tion is the process of loading design-specific programming data into one or more FPGAs to define the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip.
XC4000-Series devices use several hundred bits of configuration data per CLB and its associated interconnects.
Each configuration bit defines the state of a static memory
cell that controls either a function look-up table bit, a mUltiplexer input, or an interconnect pass transistor. The XACTstep development system translates the design. into a
nellist file. It automatically partitions, places and routes the
logic and generates the configuration data in PROM format.

Mode
Master Serial

Special Purpose Pins
Three configuration mode pins (M2, M1, MO) are sampled
prior to configuration to determine the configuration mode.
After configuration, these pins can be used as auxiliary
connections. M2 and MO can be used as inputs, and M1
can be used as an output. The XACTstep development
system does not use these resources unless they are
explicitly specified in the design entry. This is done by placing a special pad symbol called MD2, MD1, or MOO instead
of the input or output pad symbol.
In XC4000-Series devices, the mode pins have weak pullup resistors during configuration. With all three mode pins
High, Slave Serial mode is selected, which is the most popular configuration mode. Therefore, for the most common
configuration mode, the mode pins can be leftunconnected. (Note, however, that the internal pull-up resistor
value can be as high as 100 !4-bit length count, the FPGAs begin the start-up
sequence and become operational together. FPGA I/O are
normally released two CCLK cycles after the last configuration bit is received. Figure 49 on page 61 shows the startup timing for anXC4000-Series device.
The daisy-chained bitstream is not simply a concatenation
of the individual bitstreams. The MakePROM program
must be used to combine the bitstreams for· a daisychained configuration.

CCLK pulses until it reaches its finish point F. The different
families generate or require different numbers of additional
CCLK pulses until they reach F. Not reaching F means that
the device does not really finish its configuration, although
DONE may have gone High, the outputs became active,
and the internal reset was released. For the XC4000Series device, not reachingF means that readback cannot
be initiated and most boundary scan instructions cannot be
used.
The user has some control over the relative timing of these
events and can, therefore, make sure that they occur at the
proper time and the finish point F is reached. Timing is controlled using MakeBits options.
XC3000 Master with an XC4000-Series Slave
Some designers want to use an inexpensive lead device in
peripheral mode and have the more precious I/O pins of the
XC4000-Series devices all available for user 1/0. Figure 46
provides a solution for that case.
This solution requires one CLB, one lOB and pin, and an
internal oscillator with a frequency of up to 5 MHz as a
clock source. The XC3000 master device must be configured with late Internal Reset, which is the default option.
One CLB and one lOB in the lead XC3000-family device
are used to generate the additional CCLK pulse required by
the XC4000-Series devices. When the lead device
removes the internal RESET signal, the 2-bit shift register
responds to its clock input and generates an active Low
output signal for the duration of the subsequent clock
period. An external connection between this output and
CCLK thus creates the extra CCLK pulse.

Express Mode (XC4DDDEX only)
Express mode is similar to Slave Serial mode, except the
data is presented in parallel format, and is clocked into the
target device a byte at a time rather than a bit at a time. The
data is loaded. in parallel into eight different columns: it is
not internally serialized. Eight bits of configuration data are
loaded with every CCLK cycle, therefore this configuration

Multi-Family Daisy Chain
All Xilinx FPGAs of the XC2000, XC3000, and XC4000
Series use a compatible bitstream format and can, therefore, be connected in a daisy chain in an arbitrary
sequence. There is, however, one limitation. The lead
device must belong to the highest family in the chain. If the
chain contains XC4000-Series devices, the master normally cannot be an XC2000 or XC3000 device.
The reason for this rule is shown in Figure 49 on page 61.
Since all devices in the chain store the same length count
value and generate or receive one common sequence of
CCLK pulses, they all recognize length-count match on the
same CCLK edge, as indicated on the left edge of
Figure 49. The master device then generates additional

July 30, 1996 (Version 1.03)

Output
~--j

Reset

o

0

1
1

0
1

o
o

-'

Connected
toCCLK

Active Low Output
Active High Output

1
1

etc
X5223

Figure 46: CCLK Generation for XC3000 Master
Driving an XC4000-Series Slave

4-55

I

XC4000 Series Field Programmable Gate Arrays

mode runs at eight times the data rate of the other six
modes. A length count is not used in Express mode.
Express mode must be specified as an option to the MakeBits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six configuration modes.
Multiple slave devices with identical configurations can be
wired with parallel 00-07 inputs. In this way, multiple
devices can be configured simultaneously.
Pseudo Daisy Chain
Multiple devices with different configurations can be connected together in a pseudo daisy chain, provided that all of
the devices are in Express mode. A single combined bitstream is used to configure the chain of Express mode
devices, but the input data bus must drive 00-07 of each
device. Tie High the CS1 pin of the first device to be configured. Connect the DOUT pin of each FPGA to the CS1
pin of the next device in the chain. The 00-07 inputs are
wired to each device in parallel. The DONE pins are wired
together, with one or more internal DONE pull-ups activated. Alternatively, a 4.7 kQ external resistor can be used,
if desired. (See Figure 63 on page 76.)
The requirement that all DONE pins in a daisy chain be
wired together applies only to Express mode, and only if all
devices in the chain are to become active simultaneously.
All XC4000EX devices in Express mode are synchronized
to the DONE pin. User I/O for each device become active
after the DONE pin for that device goes High. (The exact
timing is determined by MakeBits options.) Since the
DONE pin is open-drain and does not drive a High value,
tying the DONE pins of all devices together prevents all
devices in the chain from going High until the last device in
the chain has completed its configuration cycle.

Data Stream Format
The data stream ("bitstream") format is identical for all configuration modes, with the exception of Express mode. In
Express mode, the device becomes active when DONE
goes High, therefore no length count is required. Additionally, CRC error checking is not supported in Express mode.
The data stream formats are shown in Table 21. Express
mode data is shown with DO at the left and 07 at the right.
For all other modes, bit-serial data is read from left to right,
and byte-parallel data is effectively assembled from this
serial bitstream, with the first bit in each byte assigned to
DO.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Express
mode). This header is followed by the actual configuration
data in frames. The length and number of frames depends
on the device type (see Table 22 and Table 23). Each
frame begins with a start field and ends with an error check.
In all modes except Express mode, a postamble code is
required to signal the end of data for a single device. In all
cases, additional start-up bytes of data are required to provide four clocks for the startup sequence at the end of configuration. Long daisy chains require additional startup
bytes to shift the last data through the chain. All startup
bytes are don't-cares; these bytes are not included in bitstreams created by the Xilinx software.
Table 21: XC4000-Series Data Stream Formats
Data Type

Express Mode
(00-07)

All Other
Modes (DO ... )

Because only XC4000EX and XC5200 devices support
Express mode, only these devices can be used to form an
Express mode daisy chain. XC5200 devices used in a
combined daisy chain with XC4000EX devices should be
configured as synchronized to DONE (MakeBits option
CCLK_SYNC or UCLK_SYNC), and their DONE pins wired
together with those of the XC4000EX devices.

Setting CCLK Frequency
For Master modes, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency
ranges from 0.5 MHz to 1.25 MHz (up to 10% lower for lowvoltage devices). In fast CCLK mode, the frequency ranges
from 4 MHz to 10 MHz (up to 10% lower for low-voltage
devices). The frequency is selected by an option when running MakeBits, the bitstream generation software tool. If an
XC4000-Series Master is driving an XC3000- or XC2000family slave, slow CCLK mode must be used. Slow mode is
the default.

4-56

LEGEND:

July 30, 1996 (Version 1.03)

~XILINX
Table 22: XC4000E Program Data
Device
Max Logic Gates
CLBs
(Row x Col.)
lOBs

Program Data
PROM Size
(bits)
Notes:

XC4006E

XC4008E

XC4010ElL XC4013E/L

XC4020E

XC4025E

5,000
196
(14 x 14)
112
616
28

6,000
256
(16x16)
128
768
32

8,000
324
(18 x 18)
144
936
36

10,000
13,000
400
576
(20 x 20)
(24 x 24)
160
192
, 1,536
1,120
40
48

20,000
784
(28 x 28)
224
2,016
56

25,000
1,024
(32 x 32)
256
2,560 --

12

16

18

20

126
428

166
572

53,936
53,984

94,960
95,008

186
644
119,792
119,840

206
716
147,504
147,552

I

I

64

--

Bits per Frame
Frames

XC4005E1L

3,000
100
(10 x 10)
80
360
20

Flip-Flops
Horizontal
Longlines
TBUFs per
Longline

XC4003E

22

26

30

34

226
788
178,096
178,144

266
932
247,920
247,968

306
1,076
329,264
329,312

346
1,220
422,128
422,176

I
1

I

I

I

1. Bits per Frame = (10 x number of rows) + 7 for the top + 13 for the bottom + 1 + 1 start bit + 4 error check bits
Number of Frames = (36 x number of columns) + 26 for the left edge + 41 for the right edge + 1
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one"
bits, even for extra leading ones at the beginning of the header.

The MakeSits software creates the configuration bitstream.
In Express mode, only non-CRC error checking is supported. In all other modes, MakeSits allows a selection of
CRC or non-CRC error checking. The non-CRC error
checking tests for a designated end-of-frame field for each
frame. For CRC error checking, MakeSits calculates a running CRC and inserts a unique four-bit partial check at the
end of each frame. The ii-bit CRC check of the last frame
of an FPGA includes the last seven data bits.
Detection of an error results in the suspension of data loading and the pulling down of the INIT pin. In Master modes,
CCLK and address signals continue to operate externally.
The user must detect !NIT and initialize a new configuration
by pulsing the PROGRAM pin Low or cycling Vcc.

Cyclic Redundancy Check (CRC) for
Configuration and Readback
The Cyclic Redundancy Check is a method of error detettion in data transmission applications. Generally, the transmitting system performs a calculation on the serial
bitstream. The result of this calculation is tagged onto the
data stream as additional check bits. The receiving system

July 30, 1996 (Version 1.03)

performs an identical calculation on the bitstream and compares the result with the received checksum.
Each data frame of the configuration bitstream has four
error bits at the end, as shown in Table 21. If a frame data
error is detected during the loading of the FPGA, the configuration process with a potentially corrupted bitstream is
terminated. The FPGA pulls the INIT pin Low and goes into
a Wait state.
During Readback, 11 bits of the 16-bit checksum are added
to the end of the Readback data stream. The checksum is
computed using the CRC-16 CCITT polynomial, as shown
in Figure 47. The checksum consists of the 11 most significant bits of the 16-bit code. A change in the checksum
indicates a change in the Readback bitstream. A comparison to a previous checksum is meaningful only if the readback data is independent of the current device state. CLS
outputs should not be included (Read Capture MakeSits
option not used), and if RAM is present, the RAM content
must be unchanged.
Statistically, one error out of 2048 might go undetected.

4-57

I

XC4000 Series Field Programmable Gate Arrays

Table 23: XC4000EX Program Data
Device
Max Logic Gates
CLBs

(Row x Col.)
lOBs
Flip-Flops
Horizontal Longlines
TBUFs per Longline
Bits per Frame
Frames
Program Data
PROM Size (bits)
Notes:

XC4028EXlXL

XC4036EXlXL

XC4044EXlXL

XC4052XL

XC4062XL

28,000
1,024
(32 x 32)

36,000
1,296
(36 x 36)
288
3,168
216

44,000
1,600
(40 x 40)
320
3,840
240
42
517
1963
1,014,879
1,014,919

52,000
1,936
(44 x 44)
352
4,576
264
46
565
2151
1,215,323
1,215,363

62,000
2,304
(48 x 48)

256
2,560
192
34
421
1587
668,127
668,167

38
469
1775
832,483
832,523

384
5,376
288
50
613
2,339
1,433,807
1,433,847

1. Bits per Frame = (12 x number of rows) + 8 for the top + 16 for the bottom + 8 + 1 start bit + 4 error check bits
Number of Frames = (47 x number of columns) + 27 for the left edge + 52 for the right edge + 4
Program Data = (Bits per Frame x Number of Frames) + 8 postamble bits
PROM Size = Program Data + 40
2. The user can add more "one" bits as leading dummy bits in the header, or, if CRC = off, as trailing dummy bits at the end of
any frame, following the four error check bits. However, the Length Count value must be adjusted for all such extra "one"
bits, even for extra leading ones at the beginning of the header.
3. Express mode bitfiles are slightly larger (see Table 21).

SERIAL DATA IN

I
I
I
I
I
I
I
I

Polynomial: Xi6 + X15 + X2 + 1

r--------------------------- I
111111111

•

01511411311211111019181716151
t-

LAST DATA FRAME -+- i:ii - - CRC-CHECKSUM---

ti:

g
Readback Data Stream

X1789

Figure 47: Circuit for Generating CRC-i6

4-58

July 30, 1996 (Version 1.03)

~XILINX
Configuration Sequence
There are four major steps in the XC4000-Series power-up
configuration sequence.
•
•
•

Configuration Memory Clear
Initialization
Configuration
Start-Up

Boundary Scan
Instructions
Available:

The full process is illustrated in Figure 48.

Configuration Memory Clear
When power is first applied or is reapplied to an FPGA, an
internal circuit forces initialization of the configuration logic.
When Vcc reaches an operational level, and the circuit
passes the write and read test of a sample pair of configuration bits, a time delay is started. This time delay is nominally 16 ms, and up to 10% longer in the low-voltage
devices. The delay is four times as long when in Master
Modes (MO Low), to allow ample time for all slaves to reach
a stable Vcc. When all INIT pins are tied together, as recommended, the longest delay takes precedence. Therefore, devices with different time delays can easily be mixed
and matched in a daisy chain.

EXTEsr
SAMPLE/PRELOAD
BYPASS
CONFIGURE'
(' if PROGRAM = High)

-1.3 f..ls per Frame

I
Master Waits 50 to 250 )ls
Before Sampling Mode Lines

This delay is applied only on power-up. It is not applied
when reconfiguring an FPGA by pulsing the PROGRAM pin
Low. During this time delay, or as long as the PROGRAM
input is asserted, the configuration logic is held in a Configuration Memory Clear state. The configuration-memory
frames are consecutively initialized, using the internal oscillator.
At the end of each complete pass through the frame
addressing, the power-on time-out delay circuitry and the
level of the PROGRAM pin are tested. If neither is
asserted, the logic initiates one additional clearing of the
configuration frames· and then tests the INIT input.

J:

"

!
0)

"

J:
..f

'5"
~
19
SAMPLE/PRELOAD
BYPASS

Configuration
memory

No

Full

Yesi-------,

Initialization
During initialization and configuration, user pins HOC, LDC,
INIT and DONE provide status outputs for the system interface. The outputs LDC, INIT and DONE are held Low and
HOC is held High starting at the initial application of power.
The open drain INIT pin is released after the final initialization pass through the frame addresses. There is a deliberate delay of 50 to 250 J..ls (up to 10% longer for low-voltage
devices) before a Master-mode device recognizes an inactive INIT. Two internal clocks after the INIT pin is recognized
as High, the FPGA samples the three mode lines to determine the configuration mode. The appropriate interface
lines become active and the configuration preamble and
data can be loaded.

CCLK

Count Equals

>N:.::o_ _...J

Length
Count

t

EXTEST
SAMPLE PRELOAD
BYPASS

USER 1
USER 2
CONFIGURE
READBACK

}

Operational

If Boundary Scan
is Selected

X6076

Figure 48: Power-up Configuration Sequence

July 30; 1996 (Version 1.03)

4-59

XC4000 Series Field Programmable Gate Arrays

Configuration
The 0010 preamble code, included for all modes except
Express mode, indicates that the following 24 bits represent the length count. The length count is the total number
of configuration clocks needed to load the complete configuration data. (Four additional configuration clocks are
required to complete the configuration process, as discussed below.) After the preamble and the length count
have been passed through to all devices in the daisy chain,
DOUT is held High to prevent frame start bits from reaching
any daisy-chained devices. In Express mode, the length
count bits are ignored, and DOUT is held Low, to disable
the next device in the pseudo daisy chain.
A specific configuration bit, early in the first frame of a master device, controls the configuration-clock rate and can
increase it by a factor of eight. Therefore, if a fast configuration clock is selected by the bitstream, the slower clock
rate is used until this configuration bit is detected.
Each frame has a start field followed by the frame-configuration data bits and a frame error field. If a frame data error
is detected, the FPGA halts loading, and signals the error
by pulling the open-drain INIT pin Low. After all configuration frames have been loaded into an FPGA, DOUT again
follows the input data so that the remaining data is passed
on to the next device. In Express mode, when the first
device is fully programmed, DOUT goes High to enable the
next device in the chain.

De/aying Configuration After Power-Up
There are two methods of delaying configuration after
power-up: put a logic Low on the PROGRAM input, or pull
the bidirectional INIT pin Low, using an open-collector
(open-drain) driver. (See Figure 48 on page 59.)
A Low on the PROGRAM input is the more radical
approach, and is recommended when the power-supply
rise time is excessive or poorly defined. As long as PROGRAM is Low, the FPGA keeps clearing its configuration
memory. When PROGRAM goes High, the configuration
memory is cleared one more time, followed by the beginning of configuration, provided the INIT input is not externally held Low. Note that a Low on the PROGRAM input
automatically forces a Low on the INIT output. The
XC4000-Series PROGRAM pin has a permanent weak
pull-up.
Using an open-collector or open-drain driver to hold INIT
Low before the beginning of configuration causes the
FPGA to wait after completing the configuration memory
clear operation. When INIT is no longer held Low externally, the device determines its configuration mode by capturing its mode pins, and is ready to start the configuration
process. A master device waits up to an additional 250 ~s

4-60

to make sure that any slaves in the optional daisy chain
have seen that INIT is High.

Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This transition involves a
change from one clock source to another, and a change
from interfacing parallel or serial configuration data where
most outputs are 3-stated, to normal operation with I/O pins
active in the user-system. Start-up must make sure that the
user-logic 'wakes up' gracefully, that the outputs become
active without causing contention with t~e configuration signals, and that the internal flip-flops are released from the
global Reset or Set at the right time.
Figure 49 describes start-up timing for the three Xilinx families in detail. Express mode configuration always uses
either CCLK_SYNC or UCLK_SYNC timing, the other configuration modes can use any of the four timing sequences.
To access the internal start-up signals, place the STARTUP
library symbol.
Start-up Timing

Different FPGA families have different start-up sequences.
The XC2000 family goes through a fixed sequence. DONE
goes High and the internal global Reset is de-activated one
CCLK period after the I/O become active.
The XC3000A family offers some flexibility. DONE can be
programmed to go High one CCLK period before or after
the I/O become active. Independent of DONE, the internal
global Reset is de-activated one CCLK period before or
after the I/O become active.
The XC4000 Series offers additional flexibility. The three
events - DONE going High, the internal Set/Reset being
de-activated, and the user I/O going active - can all occur
in any arbitrary sequence. Each of them can occur one
CCLK period before or after, or simultaneous with, any of
the others. This relative timing is selected by means of software options in MakeBits, the bitstream generation software.
The default option, and the most practical one, is for DONE
to go High first, disconnecting the configuration data source
and avoiding any contention. when the I/Os become active
one clock later. Reset/Set is then released another clock
period later to make sure that user-operation starts from
stable internal conditions. This is the most common
sequence, shown with heavy lines in Figure 49, but the
designer can modify it to meet particular requirements.
Normally, the start-up sequence is controlled by the internal
device oscillator output (CCLK), which is asynchronous to
the system clock.

July 30,1996 (Version 1.03)

~XILINX

CCLK

XC2000

F = Finished, no more
configuration clocks needed
Daisy-chain lead device

XC3000

must have latest F

Heavy lines describe
default timing

I
XC4000ElEX
CCLK_NOSYNC

XC4000ElEX
CCLK_SYNC

XC4000E/EX
UCLK_NOSYNC

XC4000ElEX
UCLK_SYNC

---.J'-__~~=~::~ UCLK Period
X6700

Figure 49: Start-up Timing

July 30, 1996 (Version 1.03)

4-61

XC4000 Series Field Programmable Gate Arrays

The XC4000 Series offers another start-up clocking option,
UCLK_NOSYNC. The three events described above need
not be triggered by CCLK. They can, as a configuration
option, be triggered by a user clock. This means that the
device can wake up in synchronism with the user system.
When the UCLK_SYNC option is enabled, the user can
externally hold the open-drain DONE output Low, and thus
stall all further progress in the start-up sequence until
DONE is released and has gone High. This option can be
used to force synchronization of several FPGAs to a common user clock, or to guarantee that all devices are successfully configured before any lias go active.
If either of these two options is selected, and no user clock
is specified in the design or attached to the device, the chip
could reach a point where the configuration of the device is
complete and the Done pin is asserted, but the outputs do
not become active. The solution is either to recreate the bitstream specifying the start-up clock as CCLK, or to supply
the appropriate user clock.
Start-up Sequence
The Start-up sequence begins when the configuration
memory is full, and the total number of configuration clocks
received since INIT went High equals the loaded value of
the length count.
The next rising clock edge sets a flip-flop 00, shown in
Figure 50. 00 is the leading bit of a 5-bit shift register. The
outputs of this register can be programmed to control three
events.
o
o

o

The release of the open-drain DONE output
The change of configuration-related pins to the user
function, activating all lOBs.
The termination of the global Set/Reset initialization of
all CLB and lOB storage elements.

The DONE pin can also be wire-ANDed with DONE pins of
other FPGAs or with other external signals, and can then
be used as input to bit 03 of the start-up register. This is
called "Start-up Timing Synchronous to Done In" and is
selected by the CCLK_SYNC and UCLK_SYNC MakeBits
options.
When DONE is not used as an input, the operation is called
"Start-up Timing Not Synchronous to DONE In;' and is
selected by the CCLK_NOSYNC and UCLK_NOSYNC
MakeBits options.
As a configuration option, the start-up control register
beyond 00 can be clocked either by subsequent CCLK
pulses or from an on-chip user net called STARTUP.CLK.
These signals can be accessed by placing the STARTUP
library symbol.

4-62

Start-up from CClK
If CCLK is used to drive the start-up, 00 through 03 provide the timing. Heavy lines in Figure 49 show the default
timing, which is compatible with XC2000 and XC3000
devices using early DONE and late Reset. The thin lines
indicate all other possible timing options.
Start-up from a User Clock (STARTUP.ClK)
When, instead of CCLK, a user-supplied start-up clock is
selected, 01 is used to bridge the unknown phase relationship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.

DONE Goes High to Signal End of Configuration
In all configuration modes except Express mode, XC4000Series devices read the expected length count from the bitstream and store it in an internal register. The length count
varies according to the number of devices and the composition of the daisy chain. Each device also counts the number of CCLKs during configuration.
Two conditions have to be met in order for the DONE pin to
go high:
o
o

the chip's internal memory must be full, and
the configuration length count must be met, exactly.

This is important because the counter that determines
when the length count is met begins with the very first
CCLK, not the first one after the preamble.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the first CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of configuration, the configuration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [2 24 * CCLK periodjwhich is sometimes interpreted as the device not configuring at all.
If it is not possible to have the data ready at the time of the
first CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value. The
XACT User Guide includes detailed information about manually altering the length count.
In Express mode, there is no length count. The DONE pin
for each device goes High when the device has received its
quota of configuration data. Wiring the DONE pins of several devices together delays start-up of all devices until all
are fully configured.

July 30, 1996 (VerSion 1.03)

1:XILINX
03----,
STARTUP

02

,-----01/04
DONE

IN
hH~~----------------- IOBsOPEAATIONALPERCONFIGUAATION

CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)

}----1t_--------

GLOBAL 3-STATE OFALL l08s

"FINISHED'
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR

ao

01

as

Q2

FULL
LE~GTH

o

COUNT

Q4

o

CLEAR MEMORY --'-If--e~--+--t--____- - l f - - - t t - - - - - - I - - - 1 _ - - t - -....- - - - . . . J

CCLK----L---fo'-,
STARTUP.CLK _ _ _ _ _

-lkl-l-....---..,......- - - - - -.....- - -....

USER NET

*

CONFIGURATION eIT OPTIONS SELECTED BY USER IN "MAKEBITS'

X1528

Figure 50: Start-up Logic
Note that DONE isan open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by MakeBits, the bitstream generation software.

Release of User VO After DONE Goes High
By default, the user 1/0 are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state 3-stated, with a 50 kf.l - 100 kn pull~up. The delay from
DONE High to active user 110 is controlled by a MakeBits
option.

July 30, 1996 (Version 1.03)

Release of Global SetlReset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by a MakeBits option.

Configuration Complete After DONE Goes High
Three.full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 49 on page 61. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be us.ed ..

4-63

I

XC4000 Series Field Programmable Gate Arrays

Configuration Through the Boundary Scan
Pins
XC4000-Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:

•

Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CON FIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CON FIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.

The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note XAPP017, "Boundary Scan in XC4000 Devices." This
application note also applies to XC4000E and XC4000EX
devices.

Readback
The user can read back the content of configuration memory and the level of certain internal nodes without interfering with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and lOBs, as well as the content of function generators used as RAMs.
Note that in XC4000-Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
Readback of Express mode bitstreams results in data that
does not resemble the original bitstream, because the bitstream format differs from other modes.
XC4000-Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any lOB.
To access the internal Readback signals, place the READBACK library symbol and attach the appropriate pad symbols, as shown in Figure 51.
After Readback has been initiated by a Low-to-High transition on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this' clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
'

IF UNCONNECTED,

DmULT"

=, ~.-___. .
ClK,

, READ_TRI'GGER
READBACK
MDOI>------'=.;..;..;;..;c..:=-_--l >-_T""R..::..IG=-i
IBUF

DATA'

>---,-R:=E:...:AD=.o_=::D"-A",,TA,,-·~'·--I MD1
OBUF

RIP
X1786

Figure 51: Readback Schematic Example

4-64

July 30, 1996 (Version 1.03)

~XILINX
Readback Options
Readback options are: Read Capture, Read Abort, and
Clock Select. They are set with MakeBits, the bitstream
generation software.

/

PHOGRAMMABLE
INTERCONNECT

Read Capture
When the Read Capture option is selected, .the read back
data stream includes sampled values of ClB and lOB signals. The rising edge of RDBK.TRIG latches the inverted
values of the four ClB outputs, the lOB output flip-flops and
the input signals 11 and 12. Note that while the bits describing configuration (interconnect, function generators, and
RAM content) are not inverted, the ClB and lOB dutput signals are inverted.
When the Read Capture option is not selected, the values
of the capture bits reflect the configuration data originally
written to those memory locations.
If the RAM capability of the ClBs is used, RAM data are
available in read back, since they directly overwrite the F
and G function-table configuration of the ClB.
RDBK.TRIG is located in the lower-left corner of the device,
as shown in Figure 52.

Read Abort
When the Read Abort option is selected, a High-to-low
transition on RDBK.TRIG terminates the read back operation and prepares the logic to accept another trigger.
After an aborted readback, additional clocks (up to one
read back clock per configuration frame) maybe required to
re-initialize the control logic. The status of read back is indicated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.

X1787

Figure 52: READBACK Symbol in Graphical Editor

Violating the Maximum High and Low Time
Specification for the Readback Clock
The readback clock has a maximum High and low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling read back, an
interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
. specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mechanism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the following frame. This loading process is dynamic, and is the
source of the maximum High and low time requirements.

Clock Select

Therefore, the specification only applies to the six clock
cycles prior to and including any start bit, including the
clocks before the first start bit in the read back data stream.
At other times, the frame data is already in the register and
the register is not dynamic. Thus, it cari be shifted out just
like a regular shift register.

CClK is the default clock. However, the user can insert
another clock on RDBK.ClK. Readback control and data
are clocked on rising edges of RDBK.ClK. If read back
must be inhibited for security reasons, the read back control
nets are simply not connected.

The user must precisely calculate the location of the readback data relative to the frame. The system must keep
track of the position within a data frame, and disable interrupts before frame .boundaries. Frame lengths and data
formats are listed in Table 21, Table 22 and Table 23.

RDBK.ClK is located in the lower right chip corner, as
shown in Figure 52.

Readback with the XChecker Cable
The XChecker Universal Download/Readback Cable and
logic Probe uses the read back feature for bitstream verification. It can also display selected internal signals on the
PC or workstation screen, functioning as a low-cost in-circuit emulator.

July 30, 1996 (Version 1.03)

4-65

I

XC4000 Series Field Programmable Gate Arrays

In MakeBits, the user can specify Fast ConfigRate, which,
starting several bits into the first frame, increases the CCLK
frequency by a factor of eight. The value increases from
between 0,5 and 1.25 MHz, to a value between 4 and 10
MHz. (For low-voltage devices, the frequency can be up to
10% lower.) Be sure that the serial PROM and slaves are
fast enough to support this data rate. XC2000, XC3000/A,
and XC3100A devices do not support the Fast ConfigRate
option.

Configuration Timing
The seven configuration modes are discussed in detail in
this section. Timing specifications are included.

Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The lead FPGA accepts this data on the subsequent rising
CCLKedge.

The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output after configuration. Using DONE can also avoid contention on DIN,
provided the early DONE option is invoked.

The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
There is an internal pipeline delay of 1.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.

Master Serial mode is selected by a <000> on the mode
pins (M2, M1, MO).

NOTE:
M2, M1, MO ean be shorted
to Vee if not used as I/O

NOTE:
M2, M1, MO ean be shorted
to Ground if not used as I/O

4.7KQ

47Knl

l~

Vee
N/e

MO M1

'-------

N/e~

M2

XC4000ElEX

MASTER
SERIAL

c-

OONE

47 Knit'Kj
MO M1

' - - - M2

XC1700D
4.7 Kn

elK

DIN
lDe

DATA

-

-

INIT

RESET/OE

eE

I

vpp

W

CEo r--

(Low Reset Option Used)

PROGRAM

DOUT

;--

CCLK

XC4000ElEX,
XC5200

+5V

PWRDN

DIN

DOUT

CCLK

Vee

CCLK

PROG.RAM

MO M1
M2

DIN

DOUT

,---

4.71<.0:

JT

4.7Kn

XC3100A

SLAVE

SLAVE

,---I

PROGRAM

DONE

M~

,- REsET
r-

DIP

~c:
X6608

Figure 53: Master Serial Mode Circuit Diagram

4-66

July 30, 1996 (Version 1.03)

~XILINX
CCLK
(Output)

Serial Data In

Serial DOUT
(Output)

n-3

n-2
X3223

I

I
Notes.

CCLK

Description
DIN setup
DIN hold

Symbol
T DSCK
I
2 I TCKDS

1

Min

20
0

Max

Units
ns
ns

I

1. At power-up, Vee must nse from 2.0 V to Vee min In less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vee is valid.
2. Master Serial mode timing is based on testing in slave mode.

Figure 54: Master Serial Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-67

XC4000 Series Field Programmable Gate Arrays

means that DOUT changes on the falling CCLK edge, and
the next FPGA in the daisy chain accepts data on the subsequent rising CCLK edge.

Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input of the FPGA. The serial configuration bitstream must
be available at the DIN input of the lead FPGA a short setup
time before each rising CCLK edge.

Slave Serial mode is selected by a <111> on the mode pins
(M2, M1, MO). Slave Serial is the default mode if the mode
pins are left unconnected, as they have weak pull-up resistors during configuration.

The lead FPGA then presents the preamble data-and all
data that overflows the lead device-on its DOUT pin.
There is an internal delay of 0.5 CCLK periods, which

NOTE:
M2, M1. MO can be shorted
t0 Vcc I'f not used as I/O

NOTE:
M2. M1, MO can be shorted
to Ground if not used as I/O

4.7KQ

milt

l

4,7

Vee
N/C

=

MO Ml

'----

N/C- M2
DOUT

XC4000ElEX
MASTER
SERIAL

DIN

XC1700D
4.7Kn

eLK

DIN

DATA

LOe

eE

-

INIT

~

CEO f--

I

RESET/DE

----.

(Low Reset Option Used)

PROGRAM

-

PWRDN

DOUT

f--

CCLK

PROGRAM

DONE

47Kn I

MO M1
M2

XC4000ElEX,
XC5200
SLAVE

+5 V

vppU

~

DONE

tt

DIN

DOUT

CCLK

Vee

CCLK

PROGRAM

mil

MO M1

~M2

r---

4.7Kn

II

Kr~

~~
"------

XC3100A
SLAVE

---.
~

RESET

DIP

INIT~

X6608

Figure 55: Slave Serial Mode Circuit Diagram

4-68

July 30, 1996 (Version 1.03)

l:XILINX
DIN

CCLK

DOUT
(Output)
X5379

Description

CCLK

Symbol
1

DIN hold

2

TCCD

DIN to DOUT

3

Tcco

High time

4
5

TCCH

45

TCCL
Fcc

45

Low time
Frequency
Note:

Min
20
0

DIN setup

Tocc

Max

30

10

Units
ns
ns
ns
ns
ns
MHz

I

-

Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High.

Figure 56: Slave Serial Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-69

XC4000 Series Field Programmable Gate Arrays

Master Parallel Modes
In the two Master Parallel modes, the lead FPGA directly
addresses an industry-standard byte-wide EPROM, and
accepts eight data bits just before incrementing or decrementing the address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data-and all data that overflows the lead device-on its DOUT pin. There is an internal delay of 1.5 CClK periods, after the rising CClK edge
that accepts a byte of data (and also changes the EPROM
address) until the falling CClK edge that makes the lSB
(DO) of this byte appear at DOUT. This means that DOUT
changes on the falling CClK edge, and the next FPGA in
the daisy chain accepts data on the subsequent rising
CClKedge.

MO

NOTE:MO can be sho'rted
to Ground if not used

Ml

DOUT

as VO.
VCC

NIC
TO CCLK OF OPTIONAL
DAISY-CHAINED FPGAS

A17

-

...

A16

-

...
...

A13

-

...

I I I
MO

4
EPROM
(8Kx8)
(OR LARGER)

...

A12 ~ A12

-

r
r
r
r
r
r
r
r

,----A...--.

CCLK

A14
INIT

Master Parallel Down mode is selected by a <110> on the
mode pins. The EPROM addresses start at 3FFFF and
decrement.

Nt
M2

A15
4.7Kn

Master Parallel Up mode is selected by a <100> on the
mode pins (M2, M1, MO).The EPROM addresses start at
00000 and increment.

TO DIN OF OPTIONAL
DAISY-CHAINED F~GAS

HIGH
or

~r

The PROM address pins can be incremented or decreniented, depending on the mode pin settings. This option
allows the FPGA to share the PROM with a wide variety of
microprocessors and microcontrollers. Some processors
must boot from the bottom of memory (all zeros) while others must boot from the top. The FPGA is flexible and can
load its configuration bitstream from either end of the memory.

Ml

M2
DOUT

DI.N
CCLK

USER CONTROL OF HIGHER
ORDER PROM ADDRESS BITS
CAN BE USED TO SELECT BElWEEN
ALTERNATIVE CONFIGURATIONS

XC4OQOE!EX
SLAVE

-PROGRAM

All ~ All
Al0 ~ Al0
PROGRAM

A9~ A9

D7

A8~ A8

OS

A7~ A7

D5

A6~ AS

OS""""'\,

D4

A5~ AS

D5 """"'\,

D3

A4

r----+

A4

D4""""'\,

A3

D3 """"'\,

D2
Dl
DO

DATA BUS

A3~
A2~
Al~

.----D7 """"'\,

A2 •

02 """"'\,

Al

Dl """"'\,
DO """"'\,

AO~

AO

DONE I------'~

OE

f-

eE

r--

DONE

INIT

-

8

X6697

Figure 57: Master Parallel Mode Circuit Diagram

4-70

July 30, 1996 (Version 1.03)

~XILINX
AO-A17
(output)

'>K

_ _ _ _ _ _ _ _ _A_d_dr_es_s_f_Or_B_y_te_n_ _ _ _ _ _ _

'I~CDTRAC

00-07

Address for Byte n + 1

Byte

®TDRC-

RCLK
(output)

/
_ _ _-'

t:======~r,-7-C-C-lK-5::::::::::'''''_I_'---

CCLK

(output)

OOUT

06

(output)

07

Byte n-1

Description
RCLK

Notes.

Symbol

Delay to Address valid

1

Data setup time

2

Data hold time

3

X6078

Min

Max

Units

0

200

ns

RAC
T ORC
T RCD
T

60

ns

0

ns

1. At power-up, Vee must rise from 2.0 V to Vee min In less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until Vee is valid.
2. The first Data by1e is loaded and CCLK starts at the end of the first RCLK active cycle (rising edge).

This timing diagram shows that the EPROM requirements are extremely relaxed. EPROM access time can be longer than
500 ns. EPROM data output has no hold-time requirements.

Figure 58: Master Parallel Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-71

I

XC4000 Series Field Programmable Gate Arrays

The lead FPGA serializes the data and presents the preamble data (and all data that overflows the lead device) on
its DOUT pin. There is an internal delay of 1.5 CCLK periods, which means that DOUT changes on the falling CCLK
edge, and the next FPGA in the daisy chain accepts data
on the subsequent rising CCLK edge.

Synchronous Peripheral Mode
Synchronous Peripheral mode can also be considered
Slave Parallel mode. An external signal drives the CCLK
input(s) of the FPGA(s). The first byte of parallel configuration data must be available at the Data inputs of the lead
FPGA a short setup time before the rising CCLK edge.
Subsequent data bytes are clocked in on every eighth consecutive rising CCLK edge.

In order to complete the serial shift operation, 10 additional
CCLK rising edges are required after the last data byte has
been loaded, plus one more CCLK cycle for each daisychained device.

The same CCLK edge that accepts data, also causes the
RDY/BUSY output to go High for one CCLK period. The pin
name is a misnomer. In Synchronous Peripheral mode it is
really an ACKNOWLEDGE signal. Synchronous operation
does not require this response, but it is a meaningful signal
for test purposes. Note that RDY/BUSY is pulled High with
a high-impedance pullup prior to INIT going High.

Synchronous Peripheral mode is selected by a <011> on
the mode pins (M2, M1, MO).

NOTE:
M2 can be shorted to Ground
if not used as I/O
N/C
.---'----.,

I

I I

MO M1
• CCLK

CLOCK

~=
M2

---,---

4.7 kQ

DOUT f----

DIN

DOUT
VCC

I
M2

• CCLK

0 0-7

/

I I
MO M1
OPTIONAL
DAISY-CHAINED
FPGAs

8/

DATA BUS

N/C

4.7 kQ

XC4000E/EX
SYNCHRONOUS
PERIPHERAL

XC4000E/EX
SLAVE

--

-ROY/BUSY

CONTROL {
SIGNALS

INIT

DONE

-

-

DONE I---

INIT

4.7 kQ
PROGRAM

=

PROGRAM

r-----" PROGRAM

X5996

Figure 59: Synchronous Peripheral Mode Circuit Diagram

4-72

July 30, 1996 (Version 1.03)

~:XILINX

CCLK

I~"------

I

I

-------+I

______~--~I--.~~O~~~.I~T

~

DOUT
I

RDY/BUSY

__~r--\~_______________~_________~;--\~----X6096

Description
INIT (High) setup time

CCLK

DO - D7 setup time
DO - D7 hold time
CCLK High time
CCLK Low time
CCLK Frequency

Notes:

Symbol

TIC
TDC
TCD
TCCH
TCCL

Min

Max

5

60
0

Ils
ns
ns

50

ns

60

Fcc

8

I

Units

ns
MHz

1. Peripheral Synchronous mode can be considered Slave Parallel mode. An external CCLK provides timing, clocking in the
first data byte on the second rising edge of CCLK aller INIT goes High. Subsequent data bytes are clocked in on every
eighth consecutive rising edge of CCLK.
2. The ROY/BUSY line goes High for one CCLK period aller data has been clocked in, although synchronous operation does
not require such a response.
3. The pin name ROY/BUSY is a misnomer. In Synchronous Peripheral mode this is really an ACKNOWLEDGE signal.
4. Note that data starts to shill out serially on the OOUT pin 0.5 CCLK periods aller it was loaded in parallel. Therefore,
additional CCLK pulses are clearly required aller the last byte has been loaded.

Figure 60: Synchronous Peripheral Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-73

XC4000 Series Field Programmable Gate Arrays

Asynchronous Peripheral Mode

The READY/BUSY handshake can be ignored if the delay
from anyone Write to the end of the next Write is guaranteed to be longer than 10 CCLK periods.

Write to FPGA
Asynchronous Peripheral mode uses the trailing edge of
the logic AND condition of WS and CSO being Low and RS
and CS1 being High to accept byte-wide data from a microprocessor bus. In the lead FPGA, this data is loaded into a
double-buffered UART-like parallel-to-serial converter and
is serially shifted into the internal logic.

Status Read
The logic AND condition of the CSO, CS1and AS inputs
puts the device status on the Data bus.
•
•
•

The lead FPGA presents the preamble data (and all data
that overflows the lead device) on its OOUTpin. The ROY/
BUSY output from the lead FPGA acts as a handshake signal to the microprocessor. ROY/BUSY goes Low when a
byte has been received, and goes High again when the
byte-wide input buffer has transferred its information into
the shift register, and the buffer is ready to receive new
data. A new write may be started immediately, as soon as
the ROY/BUSY output has gone Low, acknowledging
receipt of the previous dat.a. Write may not be terminated
until ROY/BUSY is High again for one CCLK period. Note
that ROY/BUSY is pulled High with a high-impedance pullup prior to INIT going High.

It is mandatory that the whole start-up sequence be started
and completed by one byte-wide input. Otherwise, the pins
used as Write Strobe or Chip Enable might become active
outputs and interfere with the final byte transfer. If this
transfer does not occur, the start-up sequence is not completed all the way to the finish (point F in Figure 49 on page
61).
In this case, at worst, the internal reset is not released. At
best, Readback and Boundary Scan are inhibited. The
length-count value, as generated by MakeBits and
MakePROM, ensures that these problems never occur.
Although ROY/BUSY is brought out as a separate signal,
microprocessors can more easily read this information on
one of the data lines. For this purpose, 07 represents the
ROY/BUSY status when RS is Low, WS is High, and the
two chip select lines are both active.

The length of the BUSY signal depends on the activity in
the UART. If the shift register was empty when the new
byte was received, the BUSY signal lasts for only two CCLK
periods. If the shift register was still full when the new byte
was received, the BUSY signal can be as long as nine
CCLK periods.

Asynchronous Peripheral mode is selected .by a <101> on
the mode pins (M2, M1, MO).

Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with OOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.

~e,;q
I

N/e

MO

M2

4.7kO

6

DATA
BUS

D0-7

ADDRESS

BUS

';,"E~~";.s ~

:

4.7kn

MO

CCLK

lOGIC

M1

M2

CCLK

DOUT
eso

-'---4.7 kQ

M1

Nle

'III

I

OPTIONAL
DAISY-CHAINED
FPGAs

_r--Vee

07 High indicates Ready
07 Low indicates Busy
DO through 06 go unconditionally High

DOUT

DIN

XC4000ElEX
ASYNCHRONOUS
PERIPHERAL

r--

XC4000ElEX
SLAVE

eS1

-

AS

iNs
CONTROL
SIGNALS

ROY/BUSY

-

INIT

INIT

DONE

DONE

REPROGRAM

PROGRAM

,----.

PROGRAM

4.7kn

"
X6696

Figure 61:

4-74

Asynchronous Peripheral Mode Circuit Diagram

July 30, 1996 (Version 1.03)

~XILINX
Read Status

Write to LCA

RS,CS1

WS,CS1

07

DO-07

CCLK

_ _ _ _ _ _..,.-_ _ _ _ _--,.-----

CD TBUSY----'c~1 r - - - - - - - - - - - - -

ROY/BUSY

-'X'-______

OOUT _ _ _ _

......JX

p_re_v_iO_US_B_Y_te_D_6_--'_ _ _

D7

x

DO

X

D1

E
X6097

-----

Write

ROY

Description
Effective Write time
(CSO, WS=Low; RS, CS1 =High)

Symbol
1

Min

Units~

100

ns
ns

2

Toe

60

DIN hold time
ROY/BUSY delay after end of
Write or Read
ROY/BUSY active after beginning
of Read

3
4

Teo
T WTRS

0

7
6

Max

TeA

DIN setup time

IROY/BUSY Low output (Note 4)
Notes:

!

TSUSY

2

60

ns
ns

60

ns

9

CCLK
periods

1, Configuration must be delayed until the INIT pins of all daisy-chained FPGAs are High,
2. The time from the end of WS to CCLK cycle for the new byte of data depends on the completion of previous by1e processing
and the phase of the internal timing generator for CCLK,
3. CCLK and DOUT timing is tested in slave mode,
4, T BUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TBUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.

This timing diagram shows very relaxed requirements, Data need not be held beyond the rising edge of WS, ROY/SUSY will
go active within 60 ns after the end of WS. A new write may be asserted immediately after ROY/BUSY goes Low, but write
may not be terminated until ROY/BUSY has been High for one CCLK period.

Figure 62: Asynchronous Peripheral Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-75

I

XC4000 Series Field Programmable Gate Arrays

nized as High, and remains Low until the device's configuration memory is full. DOUT is then pulled High to signal
the next device in the chain to accept the configuration data
on the DO-D7 bus.

Express Mode (XC4000EX only)
Express mode is similar to Slave Serial mode, except that
data is processed one byte per CCLK cycle instead of one
bit per CCLK cycle. An external source is used to drive
CCLK, while byte-wide data is loaded directly into the configuration data shift registers. A CCLK frequency of 1 MHz
is equivalent to a 8 MHz serial rate, because eight bits of
configuration data are loaded per CCLK cycle. Express
mode does not support CRC error checking, but does support constant-field error checking.

The DONE pins of all devices in the chain should be tied
together, with one or more active internal pull-ups. If a
large number of devices are included in the chain, deactivate some of the internal pull-ups, since the Low-driving
DONE pin of the last device in the chain must sink the current from all pull-ups in the chain. The DONE pull-up is
activated by default. It can be deactivated using a MakeBits option.

In Express mode, an external signal drives the CCLK input
of the FPGA device. The first byte of parallel configuration
data must be available at the D inputs of the FPGA a short
setup time before the second rising CCLK edge. Subsequent data bytes are clocked in on each consecutive rising
CCLK edge.

XC4000EX devices in Express mode are always synchronized to DONE. The device becomes active after DONE
goes High. DONE is an open-drain output. With the DONE
pins tied together, therefore, the external DONE signal
stays low until all devices are configured, then all devices in
the daisy chain become active simultaneously. If the DONE
pin of a device is left unconnected, the device becomes
active as soon as that device has been configured.
XC5200 devices in the chain should be configured as synchronized to DONE (MakeBits option CCLK_SYNC or
UCLK_SYNC), and their DONE pins wired together with
those of the XC4000EX devices.

Express mode is only supported by the XC4000EX and
XC5200 families. It may not be used, therefore, when an
XC4000EX or XC5200 device is daisy-chained with
devices from other Xilinx families.
If the first device is configured in Express mode, additional
devices may be daisy-chained only if every device in the
chain is also configured in Express mode. CCLK pins are
tied together and DO-D7 pins are tied together for all
devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or floating, since there is an internal pullup). Frame data is
accepted only when CS1 is High and the device's configuration memory is not already full. The status pin DOUT is
pulled Low two internal-oscillator cycles after INIT is recog-

Express mode must be specified as an option to the MakeBits program, which generates the bitstream. The Express
mode bitstream is not compatible with the other six configuration modes.
Express mode is selected by a <010> on the mode pins
(M2, M1, MO).

Vee

I

NOTE:

47KO
~

8

1--MO

~
DATA BUS

8

M1

MO

4->-

To Additional
Optional

M2

Daisy-Chained
Devices

DOUT

00-07

Optional
Daisy-Chained
XC4000EXI
XC5200

XC4000EXI
XC5200

4.7KO

M1

eS1

00-D7
Vee

M2. M1, Me can be shorted
to Ground if not used as I/O

+

M2

Dour

eS1

~

~~

,--------->

PROGRAM

PROGRAM

-

INIT

lNIT

DONE~

CCLK

t
i
I

1

CCLK

PROGRAM

I":~l}

To Additional
Optional
Dai~Y-Chained

Devices

X6611

Figure 63: Express Mode Circuit Diagram

4-76

July 30, 1996 (Version 1.03)

~XILINX

CCLK

CCLK

CD TIC·

~

IN IT

DOUT

I

P--

00-07

-L,~~,,"

i~FPGAFilied

ROY/BUSY

CS1

X671 0

Note: If not driven by the preceding DOUT, CS 1 must remain High until the device is fully configured.

Figure 64: Express Mode Programming Switching Characteristics

July 30, 1996 (Version 1.03)

4-77

XC4000 Series 'Field Programmable Gate Arrays

Table 24: Pin Functions During Configuration

• XC4000EX only
Notes 1. A shaded table cell represents a 50 k!l - 100 kQ pull-up before and during configuration.
2. (I) represents an input; (0) represents an output.
3. INIT is an open-drain output during configuration.

4-78

July 30, 1996 (Version 1.03)

~:XILINX
Configuration Switching Characteristics

Vee

J---------

T POR - - - - - . 1
RE-PROGRAM

PROGRAM

- - - - - - ' 1*_ _ _

T PI

---~

CCLK OUTPUT or INPUT

MO, M1, M2
(Required)

DONE RESPONSE

X1532

~r- <300ns

I/O~

Master Modes
Description

I

Symbol

l
J

II Power-On Reset
IProgram Latency
L

MO = High
MO = Low

T pOR
T pOR
Tpi

Min

Max

10
40
---30

40
130
200

I

ICCLK (output) Delay

T 1CCK

ICCLK (output) Period, slow

TCCLK

ICCLK (output)

TCCLK

Period, fast

40
640
80
-.~.-.

Units
ms
ms
Ils per
CLB column

250
2000
250
---_.-

Ils
ns

Units
ms

ns

Slave and Peripheral Modes
Symbol

Min

Max

Power-On Reset

Description

T pOR

Program Latency

T p1

10
30

33
200

CCLK (input) Delay (required)
CCLK (input) Period (required)

July 30, 1996 (Version 1,03)

T 1CCK
TCCLK

4
100

Ilsper
CLB column
IlS
ns

4-79

I

XC4000 Series Field Programmable Gate Arrays

XC4000E Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:

Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final.'

XC4000E Operating Conditions
Symbol

V IH

Description
Supply voltage relative to GND, TJ = -0 °C to +S5°C
Supply voltage relative to GND, TJ = -40°C to +100°C
Supply voltage relative to GND, Te = -55°C to + 125°C
High-level input voltage

V IL

LOW-level input voltage

TIN

Input signal transition time (Note 2)

Vee

Note 1:
Note 2:
Note 3:

Commercial
Industrial
Military
TTL inputs
CMOS inputs
TTL inputs
CMOS inputs

Min
4.75
4.5
4.5
2.0
70%
0
0

Max
5.25
5.5
5.5
Vee
100%
O.S
20%
250

Units
V
V
V
V
Vee
V
Vee
ns

At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per DC.
Typical value only. Not tested or characterized.
Input and output measurement thresholds for TTL are 1.5 V. Input and output measurement thresholds for CMOS are 2.5 V.

XC4000E DC Characteristics Over Operating Conditions
Symbol
VOH
VOL

Description
High-level output voltage @ IOH = -4.0mA, Vee min
High-level output voltage @ IOH = -1.0mA, Vee min
Low-level output voltage @ IOl = 12.0mA, Vee min
(Note 1)

leeo

Quiescent FPGA supply current (Note 2)

'L
C IN

Input or output leakage current
Input capacitance (sample tested)

'RIN
IRLL

Pad pull-up (when selected) @ V IN = OV (sample tested)
Horizontal Longline PUll-up (when selected) @ logic Low

Note 1:
Note 2:

TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
TTL input levels
CMOS input levels

Min
2.4

Max

Vee-0.5

-10
PQFP and MQFP
packages
Other packages
0.02
0.2

0.4
0.4
10
1
+10
10

Units
V
V
V
V
rnA
mA

16
0.25
2.5

JlA
pF
pF
mA
mA

With 50% of the outputs simultaneously sinking 12mA, up to a maximum of 64 pins.
. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
configured with a MakeBits Tie option.

1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.

4-S0

July 30, 1996 (Version 1.03)

~XILINX
XC4000E Absolute Maximum Ratings
Symbol

Units

Description
-0.5 to +7.0

V

Input voltage relative to GND (Note 1)

-0.5 to VCC +0.5

V

VTS

Voltage applied to 3-state output (Note 1)

-0.5 to Vcc +0.5

TSTG

Storage temperature (ambient)

-65 to +150

V
DC

TsOL
TJ

+260

DC

Junction temperature

Vcc
V IN

Supply voltage relative to GND

Note 1:

Note 2:

Maximum soldering temperature (10 s @ 1/16 in.

= 1.5 mm)
ICeramic packages

+150

DC

IPlastic packages

+125

DC

Maximum DC overshoot or undershoot above Vee or below GND must be limited to either 0.5 V or 10 mA, whichever is
easier to achieve. During transitions, the device pins may undershoot to -2.0 V or overshoot to Vcc + 2.0 V, provided this
over- or undershoot lasts less than 20 ns.
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.

I

XC4000E Program Readback Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements.
The following guidelines reflect worst-case values over the recommended operating conditions.

j r - - - - - - - - - - - - \ \ \-\- - - - - - - - l \ \-\- - - - - ' - - - - -

Finished
Internal Net

rdbk.TRIG

~

~---'------I: :fT,(i)

:

1--:
-

-

~~

rdclk.1

\~

rdbk.RIP

rdbk.DATA

I

Description

Symbol

rdbk.TRIG

rdbk.TRIG setup
rdbk.TRIG hold
rdbk.TRIG Low to abort Readback

1
2
3

rdclk.1

rdbk.DATA delay
rdbk.RIP delay
High time
Low time

7
6
5

Note 1:
Note 2:

4

T RTRC
T RCRT
TRTL
T RCRD
T RCRR
T RCH
T RCL

Min

Max

Units

200
50
100

-

ns
ns
ns

-

250
250
500
500

ns
ns
ns
ns

250
250

Timing parameters apply to ali speed grades.
If rdbk.TRIG is High prior to Finished, Finished will trigger the first Readback.

July 30, 1996 (Version 1.03)

4-81

XC4000 Series Field Programmable Gate Arrays

XC4000E Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions.

Units
From pad through
Primary buffer,
to any clock K

From pad through
Secondary buffer,
to any clock K

4-B2

TSG

XC4005E
XC4006E
XC400BE
XC4010E
XC4013E
XC4020E
XC4025E

7.5
8.0
11.0
11.5
12.0
12.5

5.3
6.1
6.3

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

7.5
7.5
8.0
8.5
11.5
12.0
12.5
13.0

5.2
5.2

6.B
7.0
7.2

5.B
6.6
6.8
7.3
7.5
7.7

4.0
4.0
4.5
5.2
5.4
5.8
6.2
6.3

ns
ns
ns
ns
ns
ns
ns
ns

4.4
4.4
4.9
5.6
5.8
6.2
6.6

ns
ns
ns
ns
ns
ns
ns
ns

6.B

July 30, 1996 (Version 1.03)

~XILINX
XC4000E Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38S10/60S. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions.

..."'....., ' .....,...,,
Full length, both pull-ups,
inputs from lOB I-pins

Full length, both pull-ups,
inputs from internal logic

Speed Grade
Device
XC4003E
TWAF
XC400SE
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC402SE
XC4003E
TWAFL
XC400SE
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC402SE

Symbol

Half length, one pull-up,
inputs from lOB I-pins

TWAO

Half length, one pull-up,
inputs from internal logic

TWAOL

Note 1:
Note 2:

XC4003E
XC400SE
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC402SE
)(r.4nn~F

XC400SE
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC402SE

-4
Max
9.2
9.S
12.0
12.S
1S.0
16.0
17.0
18.0
12.0
12.S
14.0
16.0
18.0
19.0
20.0
21.0
10.S
10.S
13.S
14.0
16.0
17.0
18.0
19.0
12.0
12.S
14.0
16.0
18.0
19.0
20.0
21.0

-3

-2

Max
S.O
6.0
7.0
8.0
9.0
11.0
13.9
16.9
7.0
8.0
9.0
10.0
11.0
13.0
1S.S
18.9
6.0
7.0
8.0
9.0
10.0
12.0
15.0
17.6
8.0
9.0
10.0
11.0
12.0
14.0
16.8
19.6

Max
4.3
S.1
6.2
7.0
8.1
9.9
12.S
1S.2
6.0
6.8
7.9
8.8
9.7
11.7
14.0
17.0
S.1
6.0
6.8
7.9
8.8
10.8
13.S
1S.8
6.8
7.7
8.S
9.4
10.2
11.9
14.3
16.7

Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

These values include a minimum load. The values reported by LCA2XNF -S include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (TPID)
and output delay (TOPF or TOPS), as listed under "lOB Switching Characteristic Guidelines."

July 30, 1996 (Version 1.03)

4-83

XC4000 Series Field Programmable Gate Arrays

XC4000E Horizontal Longline Switching Characteristic Guidelines
Testing of the switchingparameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions.

-~~~

·t.. ·~,

TBUF driving a Horizontal Longline
(LL):
I going High or Low to LL going High or
Low, while T is Low.
Buffer is constantly active.
(Note1 )
I going Low to LL going from resistive
pull-up High to active Low.
ITBUF configured as open-drain.

Max

-2
Max

Units

XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

5.0
5.0
6.0
7.0
8.0
9.0
10.0
11.0

4.2
5.0
5.9
6.3
6.4
7.2
8.2
9.1

3.4
4.0
4.7
5.0
5.1
5.7
6.6
7.3

ns
ns
ns
ns
ns
ns
ns
ns

T I02

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

5.0
6.0
7.8
8.1
10.5
11.0
12.0
12.0

4.2
5.3
6.4
6.8
6.9
7.7
8.7
9.6

3.6
4.5
5.4
5.8
5.9
6.5
7.4
8.2

ns
ns
ns
ns
ns
ns
ns
ns

TON

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

5.5
7.0
7.5
8.0
8.5
8.7
11.0
11.0

4.6
6.0
6.7
7.1
7.3
7.5
8.4
8.4

3.9
5.4
5.7
6.0
6.2
6.4
7.1
7.1

ns
ns
ns
ns
ns
ns
ns
ns

TOFF

All devices

1.8

1.5

1.3

ns

Tpus

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

20.0
23.0
25.0
27.0
29.0
32.0
35.0
42.0

14.0
16.0
18.0
20.0
22.0
26.0
32.5
39.1

11.9
13.6
15.3
17.0
18.7
22.1
27.6
33.2

ns
ns
ns
ns
ns
ns
ns
ns

TpUF

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

9.0
10.0
11.5
12.5
13.5
15.0
16.0
18.0

7.0
8.0
9.0
10.0
11.0
13.0
14.8
16.5

6.0
6.8
7.7
8.5
9.4
11.0
12.6
14.0

ns
ns
ns
ns
ns
ns
ns
ns

(Note1 )

IT going Low to LL going from resistive
pull-up or floating High to active Low
ITBUF configured as open-drain or active
buffer with I = Low.
(Note1 )
T going High to TBUF going inactive,
not driving LL
T going High to LL going from Low to
High, pulled up bya single resistor.
(Note 2)

T going High to LL going from Low to
High, pulled up by two resistors.
(Note1 )

Note 1:
Note 2:

4 c84

-3

-4
Max

Speed Grade
.S}'mb()! Device
XC4003E
T I01

These values include a minimum load. The values reported by LCA2XNF -8 include only a portion of this delay, therefore
the values cannot be directly compared. Use XDelay to determine the delay for each destination.
This value includes a minimum load. The value reported by LCA2XNF -8 is increased to allow for potentially heavy loading,
therefore the values cannot be directly compared. Use XDelay to determine the delay for each destination.

July 30, 1996 (Version 1.03)

~:XILINX
XC4000E CLB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Speed Grade

-3

-4

-2

Descriptio,",

Symbol

Combinatorial Delays
FIG inputs to XIY outputs
FIG inputs via H' to XN outputs
C inputs via SR through H' to XN outputs
C inputs via H' to XIY outputs
C inputs via DIN through H' to XN outputs

T ILO
T IHO
T HHOO
T HHlO
T HH20

2.7
4.7
4.1
3.7
4.5

2.0
4.3
3.3
3.6
3.6

1.6
2.7
2.4
2.2
2.6

TOPCY
T ASCY
T INCY
TSUM

3.2
5.5
1.7
3.8

2.6
4.4
1.7
3.3

2.1
3.7
1.4
2.6

TSYp

1.0

0.7

0.6

T CKO

3.7

2.8

2.8

CLB Fast Carry Logic
Operand inputs (Fl, F2, Gl, G4) to COUT
AddlSubtract input (F3) to COUT
Initialization inputs (Fl, F3) to COUT
CIN through function generators to
XIY outputs
CIN to COUT, bypass function generators
Sequential Delays
Clock K to outputs Q
Setup Time before Clock K
FIG inputs
FIG inputs via H'
C inputs via HO through H'
C inputs via HI through H'
C inputs via H2 through H'
C inputs via DIN
C inputs via EC
C inputs via SIR, going Low (inactive)
CIN input via FIG'
CIN input via FIG' and H'

July 30, 1996 (Version 1.03)

TICK
T IHCK
THHOCK
T HH1CK
THH2CK
T OICK
T ECCK
T RCK
TCCK
T CHCK

Min

4.0

6.1
4.5
5.0
4.8
3.0
4.0
4.2

Max

Min

3.0
4.6
3.6
4.1
3.8
2.4
3.0
4.0

Max

Min

Max

2.4
3.9
3.5
3.3
3.7
2.0
2.6
4.0

4-85

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Hold Time after Clock K
FIG inputs
FIG inputs via H'
C inputs via HO through H'
C inputs via H1 through H'
C inputs via H2 through H'
C inputs via DIN
C inputs via EC
C inputs via SR, going Low (inactive)
Clock
Clock High time
Clock Low time
Set/Reset Direct
Width (High)
Delay from C inputs via SIR,
going High to Q
Master Set/Reset (Note 1)
Width (High or Low)
Delay from Global SeUReset net to Q
Global SeUReset inactive to first

Note 1:
Note 2:

4-86

TCKI
TCKIH
TCKHHO
TCKHH1
TCKHH2
TCKDI
TCKEC
T

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

TCH
TCL

4.5
4.5

4.0
4.0

4.0
4.0

T RPW
TRIO

5.5

T MRW
TMRQ
TMRK

13.0

4.0
6.5

4.0
4.0

11.5
23.0

4.0

11.5
18.7

17.4

Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Export Control Max. flip-flop toggle rate.

Juty 30, 1996 (Version 1,03)

~XILINX
XC4000E CLB Edge-Triggered (Synchronous) RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. Th.ese values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

write cycle time
(clock K period)
Clock K pulse width
(active edge)
Address setup time
before clock K
Address hold time
after clock K
DIN setup time
before clock K
DIN hold time
after clock K
WE setup time
before clock K
WE hold time
after clock K
Data valid
after clock K

Note 1:
Note 2:

16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1

Twcs
TWCTS
TwPS
T WPTS
TASS
T ASTS
T AHS
T AHTS
T DSS
T DSTS
T DHS
T DHTS
Twss
T WSTS
T WHS
T WHTS
Twos

15.0
15.0
7.5
7.5
2.8
2.8
0
0
3.5
2.5
0
0
2.2
2.2
0
0

1 ms
1 ms

14.4
14.4
7.2
7.2
2.4
2.4
0
0
3.2
1.9
0
0
2.0
2.0
0
0

10.3
11.6

1 ms
1 ms

11.6
11.6
5.8
5.8
2.0
2.0
0
0
2.7
1.7
0
0
1.6
1.6
0
0

8.8
10.3

1 ms
1 ms

I

6.3
7.4

Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
Applicable Read timing specifications are identical to Level-Sensitive Read timing.

WCLK(K)

----------------~-----\

Twss

TWHS

TDss

TDHS

TASS

TAHS

WE

DATA IN

ADDRESS

DATA OUT
X6461

July 30,1996 (Version 1.03)

4-87

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Edge-Triggered (Synchronous) Dual-Port RAM Switching Characteristic
Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Operation
ress write cycle time
(clock K period)
K pulse width (active edge)
ress setup time before clock K
ress hold time after clock K

setup time before clock K
hold time after clock K
valid after clock K

Note:

16x1

T WCDS

15.0

16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1

T WPDS

7.5
2.8
0
2.2
0
2.2
0.3

TASDS
T AHDS
T DSDS
TDHDS
T WSDS
TWHDS

14.4
1 ms

10.0

7.2
2.5
0
1.9
0
2.0
0

11.6
1 ms

5.8
2.1
0
1.6
0
1.6
0

7.8

1 ms

6.2

Applicable Read timing specifications are identical to16x2 Level-Sensitive Read timing.

WCLK(K)

----------------------\Ir---~~~--~

TWSDS

WE

DATA IN

ADDRESS

DATA OUT
X6474

4-88

July 30, 1996 (Version 1.03)

~XILINX
XC4000E CLB Level-Sensitive RAM Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL -M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1

Twc
TWCT
Twp
T WPT
T AS
T AST
TAH
TAHT
Tos
TOST
TOH
TOHT

8.0
8.0
4.0
4.0
2.0
2.0
2.5
2.0
4.0
5.0
2.0
2.0

8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
2.2
2.2
2.0
2.0

8.0
8.0
4.0
4.0
2.0
2.0
2.0
2.0
0.8
0.8
2.0
2.0

T RC
T RCT
T ILO
T IHO

4.5
6.5

3.1
5.5

2.6
3.8

Data valid after address
change (no Write Enable)

16x2
32x1
16x2
32x1

Read Operation, Clocking
Data into Flip-Flop
Address setup time
before clock K

16x2
32x1

TICK
T IHCK

4.0
6.1

2.7
4.7

2.0
4.3

3.0
4.6

I

1.6
2.7

2.4
3.9

Read During Write
Data valid after WE goes
active (DIN stable
before WE)
Data valid after DIN
(DIN changes during WE)

16x2
32x1

Two
TWOT

10.0
12.0

6.0
7.3

4.9
5.6

16x2
32x1

Too
TOOT

9.0
11.0

6.6
7.6

5.8
6.2

Read During Write, Clocking Data into Flip-Flop
WE setup time
before clock K
Data setup time
before clock K

16x2
32x1
16x2
32x1

TWCK
TWCKT
TOCK
TOCKT

Note:

8.0
9.6
7.0
8.0

6.0
6.8
5.2
6.2

5.1
5.8
4.4
5.3

Timing for the 16x1 RAM option is identical to 16x2 RAM timing.

July 30,1996 (Version 1.03)

4-89

XC4000 Series Field Programmable Gate Arrays

XC4000E CLB Level-Sensitive RAM Timing Characteristics

ADDRESS

WRITE
TWp
WRITE ENABLE

DATA IN

READ WITHOUT WRITE

X,YOUTPUTS

VALID

VALID

READ, CLOCKING DATA INTO FLIP-FLOP

1··----- TICK ------J·-rl~·- TCH----I
CLOCK

XQ, VQ OUTPUTS

READ DURING WRITE

~------------TWp

WRITE ENABLE

DATA IN
(stable during WE)

X, V OUTPUTS

DATA IN
(changing during WE)

X, V OUTPUTS

READ

-----9____

D~R~:~:N:~~TE' CLOCKING DATA INTO Ei-oL~lf-P~-F~L~O~P~':'T--W-=-C-=-K-=-~-_=~-_=~-~=~TW_P
DATA IN

CLOCK

XQ, VQ OUTPUTS
X2640

4-90

July 30, 1996 (Version 1,03)

~XILINX
XC4000E Guaranteed Input and Output Parameters (Pin-te-Pin, TTL 1/0)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the lOB and Global Buffer specifications. The XACT delay calculator uses this indirect method.
When there is a discrepancy between the two methods, the values listed below should be used, and the derived values must
be ignored. All values are expressed in units of nanoseconds.
-4

-3

-2

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

12.5
14.0
14.5
15.0
16.0
16.5
17.0
17.0

10.2
10.7
10.7
10.8
10.9
11.0
11.0
12.6

8.7
9.1
9.1
9.2
9.3
9.4
9.4
10.7

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

16.5
18.0
18.5
19.0
20.0
20.5
21.0
21.0

14.0
14.7
14.7
14.8
14.9
15.0
15.1
15.3

11.5
12.0
12.0
12.1
12.2
12.8
12.8
13.0

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

2.5
2.0
1.9
1.4
1.0
0.5
0
0

2.3
1.2
1.0
0.6
0.2
0
0
0

2.3
1.2
1.0
0.6
0.2
0
0
0

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

4.0
4.6
5.0
6.0
6.0
7.0
7.5
8.0

4.0
4.5
4.7
5.1
5.5
6.5
6.7
7.0

4.0
4.5
4.7
5.1
5.5
5.5
5.7
5.9

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

8.5
8.5
8.5
8.5
8.5
8.5
9.5
9.5

7.0
7.0
7.0
7.0
7.0
7.0
7.0
7.6

6.0
6.0
6.0
6.0
6.0
6.0
6.0
6.5

XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

0
0
0
0
0
0

0
0
0
0
0
0
0
0

0
0
0
0
0
0
0
0

Speed Grade

U""'w' 'I'''U' I

Symbol

Device

Global Clock to Output
(fast) using OFF

TICKOF

~
Global Clock-la-Output Delay

(Max)

:

X3202

Global Clock to Output
(slew-limited) using OFF

T 1CKO

~
Global Clock-la-Output Delay

(Max)

:

X3202

Input Setup Time, using IFF
(no delay)
Input
Set.U£
Hold

1

~-;-[]
T

TpSUF

(Min)

IFF

PG

C>--

Time

Input Hold Time, using IFF
(no delay)

I
f1~~ [c>-

Set-Uf

'''"'' D

"~

T pHF

[J

(Min)

TIFF
pG

X3201

Input Setup Time, using IFF
(with delay)
Input

t

=~[]

I
TIFF
Hold
PG
Time I c:>---I>--

Sel-U~

Tpsu

I
I
(Min)

X3201

Input Hold Time, using IFF
(with delay)
Input

Set - Up

TpH

0

r

(Min)
IFF

HOI~ I c:>---\>--\>
TpG

Time

X320t

OFF= Output Flip-Flop

July 30, 1996 (Version 1.03)

IFF = Input Flip-Flop or Latch

lJ

0

I

,

XC4000 Series Field Programmable Gate Arrays

XC4000E lOB Input Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -8.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

_~~v

Speed Grade
Device

Sym~ol

.....-"v,

Propagation Delays
(TTL Inputs)
Pad to 11,12
Pad to 11, 12 via transparent
latch, no delay
with delay

4-92

-2
Max

Min

Max

3.0

2.5

2.0

TI
TpDLI

All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

4.8
10.4
10.8
10.8
10.8
11.0
11.4
13.8
13.8

3.6
9.3
9.6
10.2
10.6
10.8
11.2
12.4
13.7

3.6
7.0
7.3
7.8
8.1
8.2
8.5
9.5
9.5

T plDC

All devices

5.5

4.1

3.7

T pLiC
T pDLlC

All devices
XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

8.8
16.5
16.5
16.8
17.3
17.5
18.0
20.8
20.8

6.8
12.4
13.2
13.4
13.8
14.0
14.4
15.6
15.6

6.2
11.0
11.9
12.1
12.4
12.6
13.0
14.0
14.0

All devices

5.6

2.8

2.8

All devices

6.2

4.0

3.9

TIKRI

TIKLI
Hold Times (Note 1)
Pad to Clock OK), no delay
T 1KP1
with delay
TIKPID
Clock Enable (EC) to Clock (IK)
no delay
T 1KEC
with delay
TIKECD

Note 2:

Min

All devices

I

Note 1:

Max

T plD

(CMOS Inputs)
Pad to 11, 12
Pad to 11, 12 via transparent
latch, no delay
with delay

(TTL or CMOS)
Clock (IK) to 11, 12 (flip-flop)
Clock (IK) to 11, 12
(latch enable, active Low)

-3

-4
Min

All devices
All devices

0
0

0
0

0
0

All devices
All devices

1.5
0

1.5
0

0.9
0

Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

July 30, 1996 (Version 1.03)

~XIUNX
XC4000E lOB Input Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device intrOduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Setup Times (TTL Inputs)
Pad to Clock (IK), no delay
with delay

Inputs)
Pad to Clock (IK),

no delay
TPICKC All devices
with delay TplCKDC XC4003E
XC4005E
XC4006E
XC4008E
XC4010E
XC4013E
XC4020E
XC4025E

T ECIK
TECIKD

Set/Reset (Note 3)
Delay from GSR net
through Q t~ 11, 12
R width
R inactive to first active.
Clock (IK) edge

Note 1:
Note 2:
Note 3:

All devices
XC4003E
XC4005E
XC4006E
XC4008E
XG4010E
XC4013E
XC4020E
XC4025E

4.0
10.9
10.9
10.9
11.1
11.3
11.8
14.0
14.0

2.6
8.2
8.7
9.2
9.6
9.8
10.2
11.4
11.4

1.7
5.5
5.5
6.6
6.9
7.0
7.3
8.2
8.2

6.0
12.0
12.0
12.3
12.8
13.0
13.5
16.0
16.0

3.3
8.8
9.7
9.9
10.3
10.5
10.9
12.1
12.1

2.4
6.2
6.2
7.3
7.6
7.7
8.0
8.9
8.9

3.5
10.4
10.4
19.4
10.4
10.7
11.1
14.0
14.0

2.5
8.1
8.5
9.1
9.5
9.7
10.1
11.3
11.3

2.0
5.6
5.6
6.9
72.
7;3
7.6
8.5
8.5

12.0

TRRI
TMRW
TMRI

13.0

7.8
11.5

I

6.8
11.5

Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to
the clock input pin, see ihe pin-to'pin parameters in the Guaranteed Input and Output Parameters table.
Voltage levels of unused pads,bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.

July 30, ·1996 (Version 1.03)

4-93

XC4000 Series Field Programmable Gate Arrays

XC4000E lOB Output Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more preCise, and more up-todate information,use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Delays
(TTL Output Levels)
Clock (OK) to Pad, fast
slew-rate limited
Output (0) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited

TOKPOF
TOKPOS
T OPF
Tops
TTSHZ

7.5
11.5
8.0
12.0
5.0

6.5
9.5
5.5
8:5
4.2

4.5
7.0
4.8
7.3
3.8

TTSONF

9.7
13.7

8.1
11.1

7.3
9.8

TOKPOFC
ToKPOSC
T OPFC
ToPSC
TTSHZC

9.5
13.5
10.0
14.0
5.2

7.8
11.6
9.7
13.4
4.3

7.0
10.4
8.7
12.1
3.9

TTSONFC

9.1
13.1

7.6
11.4

6.8
10.2

(CMOS Output Levels)
Clock (OK) to Pad, fast
slew-rate Ii
Output (0) to Pad, fast
slew-rate limited
3-state to Pad hi-Z
(slew-rate independent)
3-state to Pad active
and valid, fast
slew-rate limited

Note 1:

Note 2:

4-94

Output timing is measured at pin threshold, with 50pF external capacitive loads (inc\. test fixture). Slew-rate limited output
riselfall times are approximately two times longer than fast output riselfall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or un bonded, must be valid logic levels. Each can be configured with the internal
pull·up (default) or pUII'down resistor, or configured as a driven output, or can be driven from an external source.

July 30, 1996 (Version 1.03)

~XILINX
XC4000E lOB Output Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Setup and Hold

Output (0) to clock (OK)
setup time
Output (0) to clock (OK)
hold time
Clock Enable (EC) to
clock (OK) setup
Clock Enable (EC) to
clock (OK) hold

TOOK

5.0

4.6

3.8

T OKO

0

0

0

TECOK

4.8

3.5

2.5

TOKEC

1.2

1.2

0.5

TCH
T

4.5
4.5

4.0
4.0

4.0
4.0

T RPO
TMRW
TMRO

13.0

I

Clock

Clock High
Clock Low
Global Set/Reset (Note 3)

Delay from GSR net to Pad
GSR width
GSR inactive to first active
clock (OK)

Note 1:

Note 2:
Note 3:

15.0

8.7

11.8
11.5

11.5

Output timing is measured at pin threshold, with 50pF external capacitive loads (inc!. test fixture), Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
.

July 30,1996 (Version 1.03)

4-95

XC4000 Series Field Programmable Gate Arrays

XC4000E Boundary Scan (JTAG) Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing meth6ds specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-todate information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -So
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.

Setup and Hold
Input (TOI) to clock (TCK)
setup time
Input (TOI) to clock (TCK)
hold time
Input (TMS) to clock (TCK)
setup time
Input (TMS) to clock (TCK)
hold time

TTDITCK
TTCKTDI
TTMSTCK
TTCKTMS

Propagation Delay
Clock (TCK) to Pad (TOO)
Clock
Clock (TCK) High
Clock (TCK) Low
r-On Reset
AG operation after valid
Vcc

Note 1:
Note 2:

Note 3:

TTCKH
T
T RJTAG

Input pad setup and hold times are specified with respect to the internal clock (lK). For setup and hold times with respect to
the clock input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
Output timing is measured at pin threshold. with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the "Additional XC4000 Data" section of the Programmable Logic Data BOOk.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.

XC4000L Switching Characteristics
XC4000L timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

XC4000EX Switching Characteristics
XC4000EX timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

XC4000XL Switching Characteristics
XC4000XL timing parameters were not available at the time this document was released. See the Xilinx WEBLINX at
http://www.xilinx.com for the latest available information.

4-96

July 30, 1996 (Version 1.03)

~XIUNX
Device-Specific Pinout Tables
Pin Locations for XC4003E Devices
XC4003E
Pad Name
VCC
1/0 (A8)
1/0 (A9)
1/0
1/0.
1/0 (Al0)

I/O (All)
(A12)
(A13)
I/O (A14)
'170, SGCKl (A 15)
VCC
GNO
I/O, PGCKl (A16)
I/O (A17)
I/O, TOI
1/0, TCK
1/0, TMS
1/0
1/0

1/0
1/0
1/0
1/0

w--GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0,

SCGK2
o (Ml)
GNO
I (MO)
VCC
I (M2)
1/0, PGCK2
1/0 (HOC)

PC
84
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18

-

-

P19
P20
P21
P22
P23
P24

Pll
P12
P13
P14
P15
P16
P17
P18

P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36

1/0

W(LOC)
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)

VCC

'<;No
1/0

I/O

P37
P38
P39
P40
P41
P42
P43
P44
P45

1/0
1/0

I/O

PQ
100
P92
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0

P46

-

P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46

July 30, 1996 (Version 1.03)

VQ
100
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15

P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43

PG
120
G3
Gl
Fl
El
F2
F3
01
Cl
02
C2
03
C3
C4
82
83
C5
84
85
A4

C6
A5
86
A6
87
C7
A7
A8
A9
88
C8
Al0
89
All
C9
A12
811
Cl0
Cll

011
812
C12

A13
012
C13

E12
013
Fl1
E13
F12
F13
G12
Gll
G13
H13
J13
H12
Hll

Bndry
Scan
32
35
38
41
44
47
50
53
56
59
62
65

68~

71
74
77
80
83
86
89

92
95
98
101
104
107
110
113
116
119
122
125
126
127
130
133
136
139
142
145
148
151
154

XC4003E
Pad Name
1/0
1/0
1/0

I/O
SGCK3
GNO
OONE
VCC
PROGRAM
1/0,

1/0(07)

I/O, PGCK3
1/0(06)
1/0
1/0 (05)

I/O «(;SO)
1/0
1/0
1/0 (04)
1/0

VCC
GNO
1/0 (03)
1/0 (RS)
1/0
1/0
1/0 (02)
1/0
1/0 (01)
1/0 (RCLK,

-

PQ
100
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70

VQ
100
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67

P67
P68
P69
P70

P71
P72
P73
P74

P68
P69
P70
P71

PG
120
K13
J12
L13
M13
L12
Kll
L11
Ll0
M12
Mll
N13
Ml0
Nll
M9
Nl0
L8
N9
M8
N8
M7
L7
N7
N6
N5
M6
L6
N4
M5
N3

P7l
P72

P75
P76

P72
P73

N2
M3

241
244

P73
P74
P75
P76
P77
P78
P79
P80
P8l
P82

P77
P78
P79
P80
P8l
P82
P83
P84
P85
P86
P87
P88
P89
P90
P9l

P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88

L4
L3
M2
K3
L2
Nl
K2
L1
J2
Kl
H3
J1
H2
H1
G2

-

PC
84
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60

-

P61
P62
P63
P64
P65
P66

Bndry
Scan
172
175
178
181
184

-

-~

187
190
193
196
199
202
205
208
211
214
217
220
223
226
229
232
235
238

I
I

ROY/8USY)
1/0 (00, OIN)
1/0, SGCK4

(OOUT)
CCLK
VCC
O,TOO
GNO
1/0 (AO, WS)
1/0, PGCK4 (Al)
1/0 (CS1, A2)
1/0 (A3)
1/0 (A4)
1/0 (A5)
1/0
1/0
1/0 (A6)

I/O (A7)
GNO

P83
P84
Pl

0

2
5
8
11
1417
-~

23
26
29

-

4/2/96

Additional No Connect (N.C.) Connections on PG120 Package

-

157
160
163
166
169_

2/28/96

4-97

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4005E/L Devices
XC4005
ElL

Pad Name
VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
GNO
I/O (A12)
I/O (A13)
I/O
I/O
I/O (A14)
I/O,
SGCK1
(A15)
VCC
GNO
I/O,
PGCK1
(A16)
I/O (A17)
I/O
I/O
I/O, TOI
I/O, TCK
GNO
I/O
I/O
I/O, TMS
I/O
I/O
I/O
I/O
I/O
GNO

vec
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

4-98

XC4005
ElL

PC
84
P2
P3
P4

PO
100

TO
144

P92
P93
P94
P95
P96
P97
P98

P128
P129
P130
P131
P132
P5
P133
P6
P134
- - P135
- - P136
- - P137
P7 P99 P138
P8 P100 P139
- P140
- - P141
P9 P1 P142
P10 P2 P143

PG
156
H3
H1
G1
G2
G3
F1
F2
E1
E2
F3
E3
C1
C2
03
B1
B2

PO
160
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P154
P155
P156
P157
P158
P159

PO Bndry
208 Scan
P183
P184
P185
P186
P187
P190
P191
P192
P193
P194
P199
P200
P201
P202
P203
P204

P11
P12
P13

P3
P4
P5

P144 C3 P160 P205
P1
C4 P1
P2
P2 B3
P2 P4

P14

P6

-

-

P15
P16

P7
P8

-

-

P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26

P17 P9
P18 P10

P19
P20
P21
P22
P23
P24

-

P11
P12
P13
P14
P15
P16
P17
P18

-

P25
P26

P19
P20

-

-

A1
A2
C5
84
A3
C6
85
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
89
A9
B10
C10
A10
A11
B11

P3
P4
P5
P6
P7
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28

P5
P6
P7
P8
P9
P14
P15
P16
P17
P18
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P33
P34
P35
P36

44
47
50
53
56
59
62
65

68
71
74
77
80
83

86

89
92
95
98
101

104
107
110
113
116
119
122
125

128
131
134
137
140
143
146
149

Pad Name
GNO
I/O
I/O
I/O
I/O
I/O
I/O,
SCGK2
o (M1)
GNO
I (MO)
VCC
I (M2)
I/O,
PGCK2
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O,
SGCK3
GNO

PC
84

PO
100

TO
144

PG
156

PO
160

PO Bndry
208 Scan

-

-

P21
- P22
- P28 P23
P29 P24

P27
P28
P29
P30
P31
P32
P33

C11
B12
A13
A14
C12
B13
B14

P29
P32
P33
P34
P35
P36
P37

P37
P42
P43
P44
P45
P46
P47

P30
P31
P32
P33
P34
P35

P25
P26
P27
P28
P29
P30

P34
P35
P36
P37
P38
P39

A15
C13
A16
C14
815
B16

P38 P48
P39 P49
P40 P50
P41 P55
P42 P56
P43 P57

170

P36
-

P31

014
C15
015
E14
C16
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
P16
M14
N15
P15
N14
R16

P44
P45
P46
P47
P48
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P73
P74
P75
P76
P77
P78

178
181
184
187
190
193
196
199
202
205
208
211
214

P48
P49
- P50 P50
P51 P51

P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70

P52 P52

P71

P14 P79 P101

P27

-

P32
P37 P33
P38 P34
P39 P35
P36
P37
P40 P38
P41 P39
P42 P40
P43 P41
P44 P42
P45 P43
- P44
P45
P46 P46
P47 P47

-

P48
P49
-

-

P58
P59
P60
P61
P62
P67
P68
P69
P70
P71
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P86
P87
P88
P89
P90
P95
P96
P97
P98
P99
P100

152
155
158
161
164
167

173

174
175

217
220
223
226
229
232
235
238

241
244
247
250
253
256

-

July 30, 1996 (Version 1.03)

F.:XILINX
XC4005

ElL
Pad Name

OONE

Vec

PROGRAM
110 (07)
I/O,
PGCK3
I/O
I/O
I/O (06)
I/O
GNO
I/O
I/O
I/O (05)
110 (CSO)
110
110
110 (04)
110
VCC
GNO
110 (03)
110 (RS)
I/O
I/O
110 (02)
I/O
I/O
I/O
GNO
I/O (01)
I/O (RCLK,
ROY/
BUSY)
I/O
I/O
I/O
(OO,OIN)
1/0,
SGCK4
(OOUT)
'CCLK
VCC
0, TOO
IGNO
I/O
(AO, WS)

PG
156

PQ
160

PQ Bndry
208 Scan

PC
84

PQ
100

TQ
144

PS3
PS4
PSS

PS3
P54
P55

P72 R1S P80 P103
P73 P13 P81 P106
P74 R14 P82 P108

P56
PS7

P56
PS7

P7S T16
P76 TiS

P83 P109
P84 P110

PS8

-

P77 R13
P78 P12
P79 T14
P80 T13
P81 P11
P82 R11
P83 T11
P84 Ti0
P8S P10
P86 RiO
P87 T9
P88 R9
P89 P9
P90 R8
P91 P8
P92 T8
P93i T7
P94 T6
P95 I R7
P96 P7
P97 TS
P98 R6
P99 T4
P100 P6
P101 T3
P102 PS

P85
P86
P87
P88
P91
P92
P93
P94
P9S
P96
P97
P98
P99
Pi00
P101
P102
P103
P104
Pi0S
P106
P107
Pi08
P109
P110
P113
P114

PS9
P60

P58
PS9

-

-

P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70

-

-

P61
P62
P63
P64
P6S
P66

P67 P71
P68 P72

P69
P70

P73

I P74

-

259
262

P111 265
P112 268
P113 271
P114 274
P119
P120 277
P121 280
P122 283
Pi23 286
P126 289
P127 292
P128 ~
P129 298
P130
Pi31
P132 301
P133 304
P134 307
P13S 310
P138 313
P139 316
P140 319
P141 322
P142
P147 325
Pi48 328

P71

P103 R4 P11S Pi49
P104 R3 P116 P1S0
P75 P10S P4 P117 P1S1

331
334
337

P72

P76 P106 T2

340 I

P73
P74
P7S
P76
P77

-

-

P118 P1S2

1

P77
P78
P79
I P80
P8i

I

P107
P108
P109
P110
P111

July 30, 1996 (Version 1.03)

R2 P119 P1S3
P3 P120 P1S4
T1 P121 PiS9
N3 P122 P160
R1 P123 P161

I

XC4005

ElL
Pad Name

I/O,
PGCK4
(A1 )
I/O
I/O
I/O
(CS1, A2)
I/O (A3)
GNO
I/O
110
I/O (A4)
110 (AS)
I/O
I/O
I/O (A6)
I/O (A7)
GNO

PC
84

PQ
100

TQ
144

PG
156

P78

P82 P112

P2

P79
P80

PQ Bndry
208 Scan

P124 P162

5

P113 N2 P12S P163
P114 M3 Pi26 P164
P83 P115 Pi P127 P16S

8
11
14

-

P84 P116 N1
- P118 L3
- P119 L2
- P120 L1
P81 P8S P121 K3
P82 P86 P122 K2
- P87 P123 K1
- P88 P124 J1
P83 P89 P125 J2
P84 P90 P126 J3
Pi P91 P127 H2

-

PQ
160

P128
P131
P132
P133
P134
P135
P137
P138
P139
P140
P141

P166
Pi71
P172
P173
Pi74
P17S
P178
P179
P180
Pi8i
P182

17

20
23
26
29
32
35
38
41
-

4/2/96

Additional No Connect (N.C.) Connections onTQ144,
PG156, PQi60 & PQ208 Packages

0
2
3/12/96

4-99

I

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4006E Devices
PC
84

TQ
144

PG
156

PQ
160

PQ
208

VCC
P2
P3
If0 (A8)
P4
If0 (A9)
110
If0
If0 (Al0)
P5
If0 (All)
P6
If0
If0
GNO
If0
If0
If0 (A12)
P7
If0 (A13)
P8
If0
If0
If0 (A14)
P9
If0, SGCKl (A15) Pl0
VCC
Pll
P12
GNO
If0, PGCKl (A16) P13
P14
If0 (A17)
If0

P128
P129
P130
P131
P132
P133
P134
P135
P136
P137

P15
P16

P138
P139
P140
P141
P142
P143
P144
Pl
P2
P3
P4
P5
P6
P7

H3
Hl
Gl
G2
G3
Fl
F2
El
E2
F3
01
02
E3
Cl
C2
03
Bl
B2
C3
C4
B3
Al
A2
C5
B4
A3

-

-

A4

P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27

C6
B5
B6
A5
C7
B7
A6
A7
A8
C8
B8
C9
B9
A9
Bl0
Cl0
Al0
All
Bl1
Cll
A12

P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
Pl
P2
P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31

P183
P184
50
P185
53
P186
56
P187
59
P190
62
P191
65
P192
68
P193
71
P194
P197
74
P198
77
P199
80
P200
83
P201
86
P202
89
P203
92
P204
95
P205
P2
P4
98
P5
101
P6
104
P7 t-- 10i110
P8
P9
113
P10
116
Pll
119
P14
122
P15
125
P16
P17
128
P18
131
P21
134
P22
137
P23
140
P24
143
P25
P26
146
P27
149
P28
152
P29
155
P30
158
P33
P34
161
164
P35
P36
167
P37
P40
170
P41
173

XC4006E
Pad Name

IfO

If0, TOI
If0, TCK
If0
If0
GNO
If0
If0
If0, TMS
If0
If0
If0
If0
If0
GNO
VCC
If0
110
If0
If0
110
If0
If0
110
GNO
If0
If0

4-100

-

P17
P18

P19
P20
P21
P22
P23
P24

P25
P26

-

-

Bndry
Scan

XC4006E
Pad Name

If0
If0
If0
If0
If0
If0, SCGK2
o (Ml)
GNO
I (MO)
VCC
I (M2)
If0, PGCK2
If0 (HOC)
If0
110
If0
110 (lOC)
If0
If0
GNO
110
If0
If0
If0
If0
If0
If0
If0 (INIT)
VCC
GNO
If0
110
If0
If0
If0
If0
If0
If0
GNO
If0
If0
110
If0
If0
If0
110
110, SGCK3
GNO
OONE
VCC
PROGRAM

PC
84

TQ
144

PG
156

PQ
160

PQ
208

Bndry
Scan

P27

-

-

B12
A13
A14
C12
B13
B14
A15
C13
A16
C14
B15
B16
014
C15
015
E14
C16
E15
016
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
U6
M16
U5
U4
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14

P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82

P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P67
P68
P69
P70
P71
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P86
P87
P88
P89
P90
P93
P94
P95
P96
P97
P98
P99
Pl00
Pl01
Pl03
Pl06
Pl08

176
179
182
185
188
191
194

P37

P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44

P28
P29
P30
P31
P32
P33
P34
P35
P36

-

P38
P39

P40
P41
P42
P43
P44
P45

P46
P47

-

P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P6l
P62
P63
P64

I
P48
P49

P50
P51
P52
P53
P54
P55

P65
P66
P67
P68
P69
P70
P71
P72
P73
P74

197

198
199
202
205
208
211
214
217
220

223
226
229
232
235
238
241
244

247
250
253
256
259
262
265
268

271
274
277
280
283
286
289
292

July 30, 1996 (Version 1.03)

~XILINX
XC4006E
Pad Name
1/0
1/0,

(D7)
PGCK3

PC
84

TQ
144

PG
156

PQ
160

PQ
208

Bndry
Scan

P56
P57

P75
P76
P77
P78
P79
P80

T16
T15
R13
P12
T14
T13
R12
T12
P11
R11
T11
T10
P10
R10
T9
R9
P9
R8
P8
T8
T7
T6
R7
P7
T5
R6
T4
P6
R5

P109
P110
P111
P112
P113
P114
P115
P116
P119
P120
P121
P122
P123
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P138
P139
P140
P141
P142
P145
P146
P147
P148

295
298
301
304
307
310
313
316

379
382
385
388

-

-

P69
P70

P101
P102

T3
P5

P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114

P103
P104
P105
P106

R4
R3
P4
T2

P115
P116
P117
P118

P149
P150
P151
P152

P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117

R2
P3
T1
N3
R1
P2
N2
M3
P1
N1
M2
M1
L3
L2

P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132

P153
P154
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P171
P172

1/0
1/0
1/0

(D6)

P58

1/0

-

1/0

-

I/O
GND
1/0
1/0
1/0
1/0

(D5)
(CSO)

P59
P60

(D4)

P61
P62
P63
P64
P65
P66

1/0
1/0
1/0
1/0

VCC
GND
1/0 (D3)
1/0 (RS)

-

1/0
1/0
1/0

(D2)

1/0

P67
P68

1/0
1/0

GND
1/0
1/0

(D1)
1/0 (RCLK,
RDY/BUSY)
1/0

1/0
1/0

I/O (DO, DIN)
1/0, SGCK4
(DOUT)
CCLK
VCC
0, TDO
GND
1/0 (AO, WS)
1/0, PGCK4 (A1)
I/O

P71
P72
P73
P74
P75
P76
P77
P78

1/0

(CS1, A2)
I/O (A3)
I/O

1/0

P79
P80

P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100

-

1/0

GND
I/O

-

-

P118
P119

July 30, 1996 (Version 1.03)

319
322
325
328
331
334
337
340

XC4006E
Pad Name

PC
84

1/0

1/0(A4)
1/0

(A5)

1/0

P81
P82

-

1/0

(A6)
(A7)
GND
1/0
1/0

P83
P84
P1

TQ
144

PG
156

PQ
160

PQ
208

Bndry
Scan

P120
P121
P122
P123
P124
P125
P126
P127

L1
K3
K2
K1
J1
J2
J3
H2

P133
P134
P135
P137
P138
P139
P140
P141

P173
P174
P175
P178
P179
P180
P181
P182

29
32
35
38
41
44
47

4/2/96

Additional No Connect (N_C.) Connections on PQ160 &
PQ208 Packages

I

343
346
349
352
355
358
361
364

367
370
373
376

0

-

2/28/96

2
5
8
11
14
17
20
23
26

4-101

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4008E Devices,
XC4008E Pad Name
VCC
1/0 (A8)
1/0 (A9)
1/0
1/0
1/0
1/0
1/0 (A10)
1/0 (All)
1/0
1/0

GNO
1/0
1/0
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0 (A14)
1/0, SGCKl (A15)

VCC
GNO
1/0, PGCKl (A16)
1/0 (A17)
I/O
1/0
1/0, TOI
1/0, TCK
1/0
1/0

PC
84
P2
P3
P4

P5
P6

P7
P8

·

-

P9
P10
Pll
P12
P13
P14

·
P15
P16

GNO
1/0
1/0
1/0, TMS
1/0
1/0
1/0
1/0
1/0
1/0
1/0

GNO
VCC
1/0
1/0
1/0
1/0
1/0

W
1/0

4-102

PQ
160
P142
P143
P144
P145
P146

P17
P18

P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P158
P159
P160
Pl
P2
P3
P4
P5
P6
P7
P8
P9
P10
Pll
P12
P13
P14

·
P19
P20
P21
P22
P23
P24

-

P15
P16
P17
P18
P19
P20
P21
P22
P23
P24

P25

P25

fiG
191
J4
J3
J2
Jl
Hl
H2
H3
Gl
G2
Fl
El
G3
Cl
E2
F3
02
B1
E3
C2
B2
03
04
C3
C4
B3
C5
A2
84

C8
A~

87

M
A5
B7
A6
C8
A7
B8
A8
B9
C9
09
010
C10
B10
A9
A10
All
Cll
Bll

PQ

208
P183
P18'!
P185
P1B6
P187
P1B8
P189
P190
P191
P192
P193
P194
P197
P198
P199
P200
P201
P202
P203
P204
P205
P2
P4
P5
P6
P7
,f8
P9
P10
Pll
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33

XC4008E Pad Name
BlJdry
Scan

1/0
1/0

~

-

I/O
GNO

56
59
62
65
68
71
74
77
80
83

1/0
1/0
1/0

P27

lib
1/0
1/0
1/0
1/0, SCGK2

O(Ml)
GNO
I (MO)
VCC
I (M2)
1/0, PGCK2
1/0 (HOC)

.,

86
89
92
95
98
101
104
107

1/0
1/0
1/0
1/0 (LOC)
1/0
1/0

110
113
116
119
122
125
128
131

GNO
1/0
1/0
1/0

I/O

P28
P29
P30
P31
P32
P33
P34
P35
P36

·
·
P37

P38
P39

1/0
1/0

-

I/O
I/O
I/O
I/O (INIT)

134
137
140
143
146
149
152
155
158
161

vee
GNO
1/0
1/0
1/0
1/0
1/0

PQ
160
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55

.

P40
P41
P42
P43
P44
P45

P56
P57
P58
P59
P60
P61
P62
P63
P64
P65

·

-

P46
P47

P66
P67
P68
P69
P70
P71
P72
P73

I/O

.
164
167
170
173
176
179
182

PC
84
P26

1/0
1/0
~-

I/O
I/O
GNO

-

1/0

I/O
1/0

P48

PG
191
A12
B12
A13
C12
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
016
C16
B17
E16
C17
017
B18
E17
F16
C18
G16
E18
F18
G17
G18
H16
H17
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16
T18
P17
N16

-

PQ
208
P34
P35
P36
P37
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P93
P94
P95

Bndry
Scan
185
188
191

194
197
200
203
206
209
212
215
218
221

222
223
226
229
232
235
238
241
244
247
250
253
256
259
262
265
268
271
274

277
280
283
286
289
292
295
298
301
304
307
310
313

July 30, 1996 (Version 1.03)

~XILINX
--

XC4008E Pad Name

I/O
1/0
1/0
1/0

PQ
160

PG
191

PQ
208

Bndry
Scan

P49

P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95

T17
R17
P16
U18
T16
R16
U17
R15
V18
T15
U16
T14
U15
V17
V16
T13
U14
T12
U13
V13
U12
V12
Tll
U11
V11
V10
U10
Tl0
R10
R9
T9
U9
V9
V8
U8
T8
V7
U7
V6
U6
T7
U5
T6
V3
V2

P96
P97
P98
P99
P100
P101
P103
P106
P108
P109
P110
P111
P112
P113
P1l4
Pl15
Pl16
P119
P120
P12l
P122
P123
P124
P125
P126
P127
P128
P129
P130
P13l
P132
P133
P134
P135
P136
P137
P138
P139
P140
P14l
P142
P145
P146
P147
P148

316
319
322
325
328

U4
T5
U3
T4
V1
R4

P149
P150
P151
P152
P153
P154

427
430
433
436

P50
P51
P52
P53
P54
P55
P56
P57

I/O, SGCK3
GNO
DONE
VCC
PROGRAM
1/0 (07)
1/0, PGCK3
1/0
1/0
1/0 (06)
1/0
1/0
1/0

P58

-

GNO
1/0
1/0
1/0 (05)
1/0 (CSO)

I/O
I/O

PC
84

P59
P60
..

11/0
1/0

1/0(04)
I/O
VCC
GNO
1/0(03)
1/0 (RS)

P61
P62
P63
P64
P65
P66

1/0
1/0
1/0
1/0

TtO([)2)
1/0
1/0
1/0

P67
P68

-

-

GNO

W
1/0
1/0 (01)

I/O
(RCLK, ROY/BUSY)
I/O
1/0

T!O(i)O,OIN)
1/0, SGCK4 (OOUT)
CCLK
VCC

P69
P70

P71
P72
P73
P74

July 30, 1996 (Version 1.03)

P96
P97
P98
P99
PlOD
P10l
Pl02
Pl03
P104
Pl05

P106
Pl07
P108
P109
P110
Plll
P112
P113
P114
P115
P116
P117
P118
P119
P120

I

331
334
337
340
343
346
349
352
355
358
361
364
367
370
373
376
379
382

XC4008E Pad Name

0, TOO
GNO
1/0 (AD, WS)
I/O, PGCK4 (A1)

PC
84

PQ
160

PG
191

PQ
208

Bndry
Scan

P75
P76
P77
P78

P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135

U2
R3
T3
U1
P3
R2
T2
N3
P2
T1
M3
P1
N1
M2
M1
L3
L2
L1
Kl
K2
K3
K4

P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P17l
P172
P173
P174
P175
P176
P177
P178
P179
P180
P18l
P182

0

-

1/0
1/0

I/O (CS1, A2)
I/O (A3)
I/O
1/0

GNO
I/O
1/0
1/0 (A4)
1/0 (A5)
1/0

P79
P80
--

P81
P82

-

~b

1/0
1/0
1/0 (A6)
1/0 (A7)

P83
P84
P1

GNO

P136
P137
P138
P139
P140
P14l

2
5
8
11
14
17
20
23

26
29
32
35
38
41
44
47
50
53

-

4/2/96

Additional No Connect (N.C.) Connections on PG191 &
PQ208 Packages

385
388
391
394
397
400
403
406
409
412
415
418
421
424

PG191

PQ208

PQ208

A14
B5
B6
B13
01
018
F2
F17
N2
N17
R1
R18
V4
V5
V14
V15

Pl
P3
P12
P13
P38
P39
P51
P52
P53
P54
P65
P66
P91
P92
Pl02
P104
Pl0S

P107
P117
PH8
P143
P144
P155
P156
P157
P158
P169
P170
P195
P196
P206
P207
P208

.-

2/28/96

-4-103

I

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4010E/L Devices
XC4010E/L PC
Pad Name 84

PQ TQ PG
160 176 191

PQI

HQ
208
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204

BG Bndry
225 Scan

P2 P142 P155 J4
08
P3 P143 P156 J3
E8
62
P4 P144 P157 J2
87
65
1/0
A7
- P145 P158 J1
68
1/0
- P146 P159 H1
C7
71
1/0
- P160 H2
07
74
- P161 H3
1/0
E7
77
1/0 (A10)
P5 P147 P162 G1
A6
80
1/0 (A11)
P6 P148 P163 G2
86
83
1/0
A5
86
- P149 P164 F1
1/0
- P150 P165 E1
85
89
GNO*
- P151 P166 G3
GNO
1/0
F2
06
92
- P167 01
1/0
C5
95
- P152 P168 C1
1/0
A4
98
1/0
- P153 P169 E2
E6
101
P7 P154 P170 F3
84
1/0 (A12)
104
05
107
1/0 (A13)
P8 P155 P171 02
1/0
83
110
- P156 P172 81
1/0
F6
113
- P157 P173 E3
1/0 (A14)
P9 P158 P174 C2
A2
116
1/0, SGCK1 P10 P159 P175 82
C3
119
(A15)
P11 P160 P176 03 P205 82
VCC
GNO
P12 P1
P1
04 P2 A1
I/O, PGCK1 Pi3 P2 P2 C3 P4 04
122
(A16)
P14 P3 P3 C4 P5
81
1/0 (A17)
125
1/0
P4 P4 83 P6 C2
128
1/0
P5 P5 C5 P7
E5
131
1/0, TOI
P15 P6 P6 A2 P8 03
134
1/0, TCK
P16 P7 P7 84 P9 C1
137
1/0
- P8 P8 C6 P10 02 140
1/0
- P9 P9 A3 P11 G6 143
1/0
- - 85 P12 E4 I 146
1/0
- - - 86 P13 01 149
GNO
- P10 P10 C7 P14 GNO* 1/0
- P11 P11 A4 P15 F5
152
1/0
- P12 P12 A5 P16 E1
155
1/0, TMS
P17 P13 P13 87 P17 F4
158
1/0
P18 P14 P14 A6 P18 F3
161
- P15 C8 P19 G4 164
1/0
- P16 A7 P20 G3
[i/o
1671
170 II
- I P15 P17 88 P21 G2
~~~ f--173
- I P16 P18 A8 P22 G1
VCC
1/0 (A8)
1/0 (A9)

1

~4-104

XC4010ElL PC
Pad Name 84
1/0
1/0

GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

GNO
I/O
1/0

I/O

P19
P20
P21
P22
P23
P24
-

-

PQ TQ PG
160 176 191
P17
P18
P19
P20
P21
P22
P23
P24

-

P25 P25
P26 P26
- P27
- P28
- P29

-

-

-

P27
-

P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54

iliO

-

1/0

P38
P39

P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55

I/O

-

-

1/0

I/O
I/O
I/O
1/0
1/0

-

1/0
1/0
1/0
1/0 (LOC)
1/0
1/0
1/0
1/0

-

P28
I/O, SCGK2 P29
o (M1)
P30
GNO
P31
P32
I (MO)
VCC
P33
P34
I (M2)
I/O, PGCK2 P35
I/O (HOC) P36

GNO
11/0

w--

'----

P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33

P37

-

P55
P56
P57
P58
P59
P60

89
C9
09
010
C10
810
A9
A10
A11
C11
811
A12
812
A13
C12
813
A14
A15
C13
814
A16
815
C14
A17
816
C15
015
A18
016
C16
817
E16
C17
017
818
E17
F16
C18
018
F17
G16
E18
F18
G17
G18
H16

PQI

BG Bndry
HQ
225 Scan
208
P23 G5
176
P24 H3
179
P25 H2
P26 H1
P27 H4
182
P28 H5
185
P29 J2
188
P30 J1
191
P31 J3
194
P32 J4
197
P33 K2
200
P34 K3
203
P35 J6
206
P36 L1
209
P37 GNO*
P38 L3
212
P39 M1
215
P40 K5
218
P41 M2 221
P42 L4
224
P43 N1
227
P44 M3 230
P45 N2
233
236
P46 K6
P47 P1
239
P48 N3
242
P49 GNO*
P50 P2
245
P55 R1
P56 M4 246
P57 R2
247
P58 P3
250
253
P59 L5
256
P60 N4
P61 R3
259
P62 P4
262
265
P63 K7
P64 M5 268
P65 R4
271
-P66 N5
274
P67 GNO*
P68 R5
277
P69 M6 280
P70 N6
283
P71 P6
286
P72 R6 i 289

July 30, 1996 (Version 1.03)

~:XILINX
iXC4010E/L
Pad Name

1/0
1/0
dlO
1/0
1/0 (INIT)
VCC
GNO
1/0
1/0
I/O
1/0
1/0

~~

PC
84

PQ
160

TQ
176

PG I
191, 208

BG Bndryi
l
225 Scan

XC4010ElL
Pad Name

PC
84

P40
P41

P56
P57
P58
P59

P61
P62
P63
P64
P65

H17!
H18
J18
J17
J16

P73
P74
P75
P76
P77

M7
R7
L7
N8
P8

P60
-

P42
P43
P44
P45
-

P60
P61
P62i
P63'
P64
P65

P66
P67
P68
P69
P70
P7l

J15

P78

I/O (CSO)
1/0
1/0
I/O
I/O
I/O (04)

-

-

P72

K16
K17
K18
L 18

P80
P81
P82
P83

R8
M8
L8
P9
R9
N9

L~

P84

M9

I K15 P79

I-I/~O _ _-l+-_---+_--+-P73 I L16 I P85
1/0
1/0
1/0
1/0

"GNis-

w--

P46
P47
-

-

I

P66
P67
P68
P69
P70

1/0
1/0
P71
I/O
P72
fc-=----+l-=---+_=_
1/0
P48 P73
1/0
P49 P74
P75
P76
1/0
P50 P77,
1/0, SGCK3 P51 P78
GNO
P52 P79
OONE
P53 P80
VCC
P54 P81
PROGRAM P55 P82

W---

'i/b

-

CVb (07)

M18
M17
i N18
P18
M16

P86
P87
P88
P89
P90

L9
Nl0
K9
Rl1
Pll
GNO*

N17
R18
P79 T18
P80 P17
P81, N16
P82 T17
P83 R17

P9l
P92
P93
P94
P95
P96
P97

R12
Ll0
P12
Mil
R13
N12
P13

P98
P99
Pl00
Pl0l
Pl03
Pl06
Pl08

Kl0
R14
N13
GNO*
P14
H15
M12

P74
P75
P76
P77
P78

P84
P85
P86
P87
P88
P89
P90

P56
1/0, PGCK3 P57
1/0
1/0
-

P83
P84
P85
P86

P91
P92
P93
P94

1/0(06)
1/0

P87
P88

P95
P96

WO
I/O
1/0
1/0
,GNO
I/O
11/0
11~()(05)

P58
-

i

P16
U18
T16
R16
U17
R15
V18

292
295
298
301
304

307
310
313
316 I
319
322
325
328
331 '

I/O

'i/o
I/O
I/O (02)
1/0

1/0
337

,1/0
'GNO

340
343
346
349
352
355
358
361
364

~

1/0
1
r11/0
1/0
1/0 (01)
1/0 (RCLK,
ROYI
BUSY)
'110
11/0

-

I

-

!

36~j

I T15 Pl09 P15
U16 Pl10 N14
T14' Pll1 L11
U15 P112

370
373'

Ml~

V17 P113 Jl~~
V16 P114 L12

1-3s2l

P89 I P971 T13 Pl151 M15

-

P90 P981 D14'P116 L13 I
V15 iPl17j L14 '
V14!P1181 1<11
P9l P99 T12 P119 GNO*
P92 Pl00 U13 P120! K13
P93 Pl01 V13 P121 K14

388
391
394
397
400

P94 Pl02i U12 jP122 K15

403

July 30, 1996 (Version 1.03)

roo

334l

-

P59

I/O
VCC
GNO
I/O (03)
1/0 (RS)

~

PG I PQI
HQ
191 208

TQ
176

V12
Tll
Ull
Vl1
Vl0
P6l
Ul0
P62
Tl0
P63
Rl0
P64
R9
P65
T9
P66
U9
V9
V8
U8
T8
P67 Pl06P118 V7
P68 iP107 P119 U7
Pl08 P120 V6
ipl09
PllO P122 T7

-

P95 Pl03
Pl04
IplO5
P96 Pl06
P97 Pl07
P98 Pl08
P99 Pl09
I Pl00 Pll0
Pl0l Plll
'Pl02 Pll2
Pl03 P113
Pl04 P114
Pl05P115
P116
Pll7

-

-

-

P~6

,

-

-

-

Pl1l
Pll2
P69 P113
P70 P114

-

P123 J12
P124 J13
P125 J14
P126 J15
P127 Jl1
P128 H13 I
P129 H14
P130 H15
P13l GNO*
P132 H12
P133 Hl1
P134' G14
P135 G15
P136 G13
'P137 G12
P138 G11
P139 F15
IP140 F14

-

1

P115 P127

- iPl16

BG IBndry
225 Scan

IP141 F13
P142 GNO*
V5 IP143 E13
V4 ,P144 015
P123 U5 P145, Fl1
P124 T6 ,P146 014
P125 V3 P147 E12
P126fV2 P148 C15

P149 013

P128' T5 iP150 C14

P71 IP117 P12-9U3 Ip1511 FlO

~UT)
CCLK
VCC
0, TOO

P73
P74
P75
~ND_ _ P76

1P119
P120
P121
P122
P123

P131

i

'

T4 IP152 B15

427
430

433
436
439
442
445
448
451
454
457
460
463
466
469
472

47~
481

784
-

C13
B14
A15
012

0
-

T3 IP1611 A14

2

11/0, PGCK4 P781P124 P136

Ul IP162 B13

5

P3
R2
T2

P163 Ell
P164 C12
P165 A13

8
11
14

N3

P166 B12

17

1

1/0
(AO,WS)

~)
1/0
1/0
I/O
(CS1, A2)
1/0 (A3)

"-----

P77

P153
P154
P159
P160

47S

P132
P133
P134
P135

i

Vl
R4
U2
R3

406
409
412
415
418
421
424

I

U4

1(00, DIN)
1110, SGCK4 P72 P118 P130

385
I

PQ
160

I
-

'P125 P137
P126 P138
P79 P127 P139

-

I

P80 P128 P140

4-105

I

XC4000 Series Field Programmable Gate Arrays

XC4010ElL
Pad Name

110
110
110

PO I TO
160 1176

PG
191

POI

BG Bndry
HO
225 Scan
208
- jP129 P141 P2 P167 A12
20
P130 P142 T1 P168 C11
23
R1 P169 B11
26
29N2 P170 E10
P131 P143 M3 P171 GNO*
P132 P144 Pi P172 A11
32 I
I
P133 P145 N1 P173 010 1 35 I
I
P8i Pi34 P146 M2 P174 Ai0 I 38 I
P82 P135 P147 M1 P1751 09
41
44
P1481 L3 P176i C9
P136 P1491 L2 P177 B9
47
P137 P150 L1 P178 A9
50
- P138 P151 K1 P179 E9
53
P83 P139 P152 K2 P180 C8
56
P84 P140 P153 K3 P181 B8
59
Pi P141 P154 K4 P182 A8

Additional No Connect (N.C.) Connections on PQI
H0208 & BG225 Packages

-

I/O
GNO

110
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

PC
84

(A4)
(A5)

-

-

-

-

-

(A6)
(A7)

[GN0

-

4/2/96

* Pads labelled GNO* are internally bonded to a Ground
plane within the BG225 package. They have no direct connection to any package pin.

Additional Ground (GND) Connections on BG225
Package
GND
F8

G7

~

G8
G9
H6
H7
H8
H9
H10
J7
J8
J9
K8

I
3/12/96

2/28/96

Note: The package pins in this table are bonded to an
internal Ground plane within the BG225 package. They
should all be externally connected to Ground.

4-106

July 30, 1996 (Version 1.03)

~XILINX
Pin Locations for XC4013E1L Devices
XC4013E1L

PQ

Pad Name

160

VCC
1/0 (A8)
1/0 (A9)
1/0
1/0

110
1/0
1/0 (Al0)
1/0 (All)

P142
P143
P144
P145
P146

P147
P148

PQI

HQ
208
P183
P184
P185
P186
P187
P188
P189
P190
P191

PG

BG

223

225

J4
J3
J2
Jl
Hl
H2
H3
Gl
G2

D8
E8
B7
A7
C7
D7
E7
A6
B6
VCC*
C6
F7
A5
B5
GND*
D6
C5

VCC
1/0
1/0
1/0
1/0

GND
1/0
1/0
1/0
1/0
1/0 (A12)
1/0 (A13)
1/0
1/0
1/0
1/0
1/0 (A14)
1/0, SGCKl

(A15)
VCC
GND
1/0, PGCKl
(A16)
1/0 (A17)

~-

1/0
1/0

IIO,TOI
1/0, TCK
1/0
1/0
1/0
1/0
1/0
1/0

GND
1/0
1/0
1/0, TMS
1/0

VCC

-

PQI
HQ Bndry
Scan
240

E6
B4
D5
A3
C4
B3
F6
A2
C3

110
113
116
119
122
125
128
131
134
137
140
143

146

P152
P153
P154
P155

P192
P193
P194
P195
P196
P197
P198
P199
P200

-

-

P156
P157
P158
P159

P201
P202
P203
P204

H4
G4
Fl
El
G3
F2
Dl
Cl
E2
F3
D2
F4
E4
Bl
E3
C2
B2

P160
Pl
P2

P205
P2
P4

D3
D4
C3

B2
Al
D4.

P240
Pl
P2

P3
P4
P5
P6
P7
P8
P9

P5
P6
P7
P8
P9
Pl0
Pll
P12
P13

C4
B3
C5
A2
B4
C6
A3
B5
B6
D5
D6
C7

Bl
C2
E5
D3
Cl
D2
G6
E4
Dl
E3
E2
GNO*
F5
El
F4
F3
VCC*

P3
P4
P5
P6
P7
P8
P9
Pl0
Pll
P12
P13
P14
P15
P16
P17
P18
P19

P149
P150
P151

-

Pl0
Pl1
P12
P13
P14

-

P14
P15
P16
P17
P18

- --

July 30, 1996 (Version 1.03)

A4

A5
B7
A6

-

P212
P213
P214
P215
P216
P217
P218
P220
P221
P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233
P234
P235
P236
P237
P238
P239

A4

74
77

80
83
86
89
92
95
98
101
104
107

-

149
152
155
158
161
164
167
170
173
176
179

182
185
188
191

-

XC4013E1L

PQ

Pad Name

160

1/0
1/0

-

110
1/0

-

110
110

P15
P16
P17
P18
P19
P20
P21
P22
P23
P24

1/0

110
GND
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

VCC
1/0
1/0
1/0
1/0

GND
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0, SCGK2

-

P33
P34
P35
P36
P37

-

-

110
1/0
1/0 (UiC)
1/0

P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32

P25
P26
P27
P28
P29

1/0

1/0 (HOC)
1/0

208
-

-

110

~PGCK2

HQ

-

P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50

O(Ml)
GNO
I (MO)
VCC
I (M2)

PQI

PG

BG

223

225

D7
D8
C8
A7
B8
A8
B9
C9
09
010
Cl0
Bl0
A9
Al0
All
Cll
011
012

F2
Fl
G4
G3
G2
Gl
G5
H3
H2
Hl
H4
H5
J2
Jl
J3
J4
J5
Kl
VCC'
K2
K3
J6
Ll
GNO'
L2
K4
L3
Ml
K5
M2
L4
Nl
M3
N2
K6
Pl
N3
GNO'
P2
Rl
M4
R2
P3
L5
N4
R3
P4
K7
M5
R4

-

P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65

Bll
A12
B12
A13
C12
013
014
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
D16
C16
B17
E16
C17
D17
B18
E17
F16
Ct8
D18

PQI

HQ
240
P20
P21
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51
P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71

Bndry
Scan
194
197
200
203
206
209
212
215

218
221
224
227
230
233
236
239

242
245
248
251

254
257
260
263
266
269
272
275
278
281
284
287
290
293
294
295
298
301
304
307
310
313
316
319

4-107

I

XC4000 Series Field Programmable Gate Arrays

XC4013E1L

PQ

Pad Name

160

1/0
1/0
1/0
1/0

VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)

VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0

208
P66

1/0
1/0
1/0

GNO

PQl
HQ

P51
P52
P53
P54
P55

P67
P68
P69
P70
P71

-

-

P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P85

110
110
VCC
1/0
1/0
1/0
1/0

GNO
110
1/0
1/0

110
1/0
1/0
1/0, SGCK3

GNO
OONE
VCC
PROGRAM
1/0 (07)

'--- . . . _ _ .

4-108

223

225

F17
E15
F15
G16
E18
F18
G17
G18

N5
P5
L6
GNO*
R5
M6
N6
P6
VCC*
R6
M7
N7
P7
R7
L7
N8
P8
R8
M8
L8
P9
R9
N9
M9
L9
R10
P10
VCC*
N1G
K9
R11
P11
GNO*
M10
N11
R12
L10
P12
Ml1
R13
N12
P13
K10
R14
N13
GNO*
P14
R15
M12
P15

H16
H17
G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
L15
M15

P66
P67
P68
P69
P70

-

110
1/0
1/0
1/0
1/0

BG

P72
P73

P56
P57
P58
P59
P60
P61
P62
P63
P64
P65

PG

P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83

P86
P87
P88
P89
P90

P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101
P103
P106
P108
P109

M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17
N16
T17
R17
P16
U18
T16
R16
U17
R15
V18
T15

PQl
HQ Bndry
240
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P99
P100
P101
P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123

. Scan
322
325
328
331
334
337
340
343
346
349
352
355
358
361
364

.~----

367
370
373
376
379
382
385
388
391
394
397
400

403
406
409
412
415
418
421
424
427
430
433
436

439

XC4013E1L

PQ

Pad Name

160

110, PGCK3

PQI

HQ
208

013

P175

571

P106
P107

1/0
1/0
1/0
1/0

P1G8
P109

P140
P141

GNO

P110

1/0

VCC
GNO
1/0 (03)
I/O(RS)
1/0
1/0
1/0
1/0
1/0 (02)

I/O
VCC

1/0
1/0
1/0
1/0
1/0
1/0

1/0(01)
1/0 (RCLK,

P113
P114
P115
P116
P117
P118
P119

442
445
448
451
454
457
460
463
466
469
472

U12
V12
T11
U11
V11
V10
U1G
T10
R10
R9
T9
U9
V9
V8
U8
T8
V7
U7

110(04)

P87
P88
P89
P90

P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174

P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139

1/0
1/0

-

N14
L11
M13
N15
M14
J10
L12
M15
L13
L14
K11
GNO*
L15
K12
K13
K14
VCC*
K15
J12
J13
J14
J15
J11
H13
H14
H15
GNO*
H12
H11
G14
G15
G13
G12
G11
F15
VCC*
F14
F13
G1G
E15
GNO*
E14
F12
E13
015
F11
014
E12
C15

P94
P95

VCC
1/0(05)
1/0 (CSO)
110
110

-

225

P120
P121

1/0
1/0
1/0
1/0

P110
P111
P112

223

P92
P93

GNO

P84
P85
P86

BG

U16
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
T12
R12
R11
U13
V13

1/0
1/0
1/0
1/0
1/0 (06)
1/0
1/0
1/0
1/0
1/0

P91

-

P96
P97
P98
P99
P100
P101
P102
P103
P104
P105

-

P111
P112
P113
P114

V6
U6
R8
R7
P142
T7
R6
R5
V5
P~
P144 . V4
P145
U5
P146
T6
P147
V3
P148
V2

P115

P149

-

-

PQI

PG

HQ
240

Bndry
Scan

475
478
481
484
487
490
493
496
499
502
505
508

511
514
517
520
523
526
529
532
535
538
541

544
547
55-0
553
556
559
562
565
568

ROY/BUSY)
1/0

U4

July 30, 1996 (Version 1.03)

~XILINX
XC4013E1L
Pad Name

PQ
160

PQI
HQ
208

PG
223

I/O
I/O
(DO, DIN)
I/O, SGCK4
(DOUT)
CCLK
VCC
O,TDO
GND
I/O
(AO,WS)
I/O, PGCK4
(A1)
I/O
I/O
I/O
(CS1, A2)
I/O (A3)
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCC
I/O (A4)
I/O (A5)
I/O
I/O
I/O
I/O
I/O (A6)
I/O (A7)
GND

P116
P117

P150
P151

T5
U3

C14
F10

P176
P177

574
577

P118

P152

T4

815

P178

580

P119
P120
P121
P122
P123

P153
P154
P159
P160
P161

V1
R4
U2
R3
T3

C13
814
A15
D12
A14

P179
P180
P181
P182
P183

0

P124

P162

U1

813

P184

5

P125
P126
P127

P163
P164
P165

P3
R2
T2

E11
C12
A13

P185
P186
P187

8
11
14

P128

P166

P188
812
F9
P189
D11
P190
A12
P191
C11
P192
811
P193
E10
P194
GND* P196
A11
P197
D10 P198
C10 P199
P200
810
VCC* I P201
P202
A10
P203
D9
P205
C9
89
P206
A9
P207
E9
P208
P209
C8
88
P210
A8
P211

17
20
23
26
29
32
35

P131
P132
P133

P167
P168
P169
P170
P171
P172
P173

-

-

N3
P4
N4
P2
T1
R1
N2
M3
P1
N1
M4
L4

P134
P135

P174
P175
P176
P177
P178
P179
P180
P181
P182

M2
M1
L3
L2
L1
K1
K2
K3
K4

P129
P130

-

P136
P137
P138
P139
P140
P141

BG I PQI
. HQ
240
225

Additional Ground (GND) Connections on BG225
Packages

Bndry
Scan

BG225

BG225

K8
J7
J8
J9
H6
H7
H8

H9
H10
G7
G8
G9
F8

3/11/96

2

The BG225 package pins in this table are bonded to an internal Ground plane on the XC4013E/L die. They must all
be externally connected to Ground.

Additional No Connect (N.C.) Connections on PQI
HQ208 & PQ/HQ240 Packages

38
41
44
47

50
53
56
59
62
65
68
71

3/20/96

I

4/2/96
Pads labelled GNO* are internally bonded to a Ground
plane within the BG225 package. They have no direct connection to any package pin.

:j: Pins marked with this symbol are reserved for Ground
connections on future revisions of the device. These pins
do not physically connect to anything on the current device
revision. However, they should be externally connected to
Ground, if possible.

Pads labelled VCC' are internally bonded to a Vcc plane
within the BG225 package. They have no direct connection
to any package pin.

July 30, 1996 (Version 1.03)

4-109

I

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4020E Devices
XC4020E Pad Name

VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O
I/O
I/O (A10)
I/O (A11)
I/O

HQ
208

PG
223

HQ
240

P183
P184
P185
P186
P187
P188
P189
P190
P191

J4
J3
J2
J1
H1
H2
H3
G1
G2

P212
P213
P214
P215
P216
P217
P218
P220
P221

-

-

I/O

VCC

-

I/O
I/O

-

I/O

P192
P193
P194
P195
P196
P197
P198
P199
P200

I/O

GNO
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)

H4
G4
F1
E1
G3
F2
01
C1
E2
F3
02

-

~--

I/O

-

I/O
I/O

-

I/O

P201
P202
P203
P204
P205
P2
P4
P5
P6
P7
P8
P9

I/O
I/O (A14)
I/O, SGCK1 (A15)
VCC
GNO
I/O, PGCK1 (A16)
I/O (A17)
I/O
I/O
I/O, TOI
I/O, TCK

P222
P223
P224
P225
P226
P227
P228
P229
P230
P231
P232
P233

F4
E4
B1
E3
C2
B2
03
04
C3
C4
B3
C5
A2
B4

P234
P235
P236
P237
P238
P239
P240
P1
P2
P3
P4
P5
P6
P7

-

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

GNO
I/O
I/O

4-110

P10
P11
P12
P13

P14
P15
P16

C6
A3
B5
B6
05
06
C7
A4

A5

P8
P9
P10
P11
P12
P13
I P14
I P15
i P16

XC4020E Pad Name
Bndry
Scan

I/O, TMS
I/O

HQ
240

Bndry
Scan

P17
P18

B7
A6

218
221

-

07
08

P17
P18
P19
P20
P21

-

I/O
I/O
I/O
I/O

-

-

I/O

P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32

C8
A7
B8
A8
B9
C9
09
010
C10
B10
A9
A10
A11
C11

P23
P24
P25
P26
P27
P28
P29
P30P31
P32
P33
P34
P35
P36

011
012

P38
P39
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P50
P51

I/O
I/O
I/O
I/O
I/O

GNO
VCC

116
119
122
125

I/O
I/O

-

I/O

-

I/O

128
131
134
137
140
143
146
149
152
155
158
161
164
167

I/O
I/O
I/O
I/O
I/O
I/O

VCC
I/O
I/O
I/O
I/O
~~-

GNO

P33
P34
P35
P36
P37

I/O
I/O

-

212
215

PG
223

VCC

86
89
92
95
98
101
104
107
110
113

170
173
176
179
182
185
188
191
194
197
200
203
206
209

HQ
208

I/O
I/O
I/O
I/O

P38
P39
P40
P41

B11
A12
B12
A13
C12
013
014
B13
A14
A15
C13

-

I/O
I/O

-

I/O

P42
P43
P44
P45
P46
P47
P48
P49
P50
P55
P56
P57
P58

I/O
I/O
I/O
I/O

W,ScGK2

CO(M1}
,

i GNO

II (MO)

IVCC
II (M2)

1iI0, PGCK2

tva (HOC)

B14
A16
B15
C14
A17
B16
C15
015
A18
016
C16
B17
E16

P52
P53
P54
P55
P56
P57
P58
P59
P60
P61
P62
P63
P64 I

224
227
230
233
236
239
242
245
248
251
--

254
257
260
263
266
269
272
275
278
281
284
287
290
293

296
299
302
305
308
311
314
317
320
323
326
329
332
335
338

341

342
343
346

July 30, 1996 (Version 1.03)

~:XILINX
HQ
208

PG
223

HQ
240

Bndry
Scan

1/0
1/0
1/0
1/0 (LOC)
1/0
1/0

P59
P60
P61
P62

C17
017
B18
E17

P65
P66
P67
P68

I/O

P63
P64
P65
P66

349
352
355
358
361
364
367
370
373
376
379
382

XC4020E Pad Name

1/0
1/0
1/0
1/0

I/O
GNO
1/0
1/0
1/0
1/0

-

P67
P68
P69
P70
P71

-

-

P72
P73

H16
H17

VCC
1/0

00--

F16
C18
018
F17
E15
F15
G16
E18
F18
G17
G18

I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)

VCC
GNO
I/O
1/0
1/0
~1/0
1/0
1/0
1/0
1/0
1/0

P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
PB5

-

-

I/O
1/0
1/0

GNO
1/0
1/0
1/0

I/O
I/O
11/0

L15
M15

-

VCC
1/0

G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
U8
L17
L16

P86
P87
P88
P89
P90

P91
P92
P93
P94

July 30, 1996 (Version 1.03)

I

M18
M17
N18
P18
M16
N15
P15
N17
R18
T18
P17

P69
P70
P71
P72
P73
P74
I
P75
P76
385
P77 ~88
P78
391
P79
394
P80
P81
397
P82
400~
403
406
P84
409
P85
412
PB6
415
P87
418
421
P88
P89
424
P90
P91
P92
427
P93
430
P94
433
P95
436
P96
439
442
P97
445
---rI 448
P99
451
P100
454
P101
P102
457
P103
460
P104
463
466
P105
P106
P107
469
472
P108
P109
475
Pl10
478
P111
481
P112
484
-~

XC4020E Pad Name

HQ

PG
223

I/O
1/0, SGCK3

GNO
OONE
VCC
PROGRAM
1/0(07)
1/0, PGCK3
1/0
1/0

i=
1/0

-

P95
N16
P96
T17
P97
R17
P98
P16
P99
U18
Pl0a
T16
P101
R16
P103
U17
P106
R15
P108 -\-\118
P109
T15
Pl10
U16
P111 I T14
P112
U15
R14
R13

11/0

Bndry
Scan

240

-

I/O
1/0
1/0
1/0
1/0
1/0
I

HQ
208

P113
P114
P1l5
P116
P117
P118
Pl19 I
P120
I
P121
P122
P123
P124
P125
P126
P127
P128

I

1/0

1/0(06)
1/0

I/O
I/O
1/0

I/O
GNO

P113
P114
P115
P116
P117
P118
P119

P120
P121

V17
V16
T13
U14
V15
V14
T12
R12
R11
U13
V13

P122
P123

U12
V12

-

-

P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137

T11
U11
Vl1
VtO
U10
T10
R10
R9
T9
U9
V9
V8
U8
T8

1/0

-

I/O
I/O
1/0

I

I

-~

VeC

176- (05)

Po

(CSO)

11/0
1/0
1
1/0
1/0
1/0
1/0
1/0 (04)

I/O
VCC
GNO
1/0 (03)

I/O(RS)
I/O
1/0
1/0
1/0
1/0

I/O

-

t:

P129
P130 I
:
P131
P132
...
P133
P134
P135
P136
P137 I
P138
P139
P140 I
P141
P142
-

P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154
P155
P156
P157
I

I

I

487
490
493
496
499
502
505
508

-

-

I

511
514
517
520
52-3
526
529
532
535
538
:
541 I
544
547
550
553
556
559
562

565
568
571
574
577
580
583
586
589
592

595
598
601
604

-607

j

I

610
613
616
4-111

I

j

I

XC4000 Series. Field Programmable Gate Arrays
XC4020E Pad Name
I/O (D2)
I/O

HQ

PG

HQ

208
P138
P139

223
V7
U7

P140
P141

-

V6
U6
R8
R7

P142

T7

P143
P144
P145
P146
P147
P148

R6
R5
V5
V4
U5
T6
V3
V2

240
P159
P160
P16l
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174

U4
T5
U3
T4
Vl
R4
U2
R3
T3
Ul
P3
R2
T2
N3

P175
P176
Pl77
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188

P4
N4
P2
Tl
Rl
N2
M3
Pl
Nl
M4
L4

P189
P190
P191
P192
P193
P194
P196
P197
P198
P199
P200
P201

vee
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O (Dl)
I/O (RCLK, RDY/BUSY)
I/O
I/O
I/O
I/O
I/O (~O, DIN)
I/O, SGCK4 (DOUT)
CCLK
VCC
0, TDO
GND
I/O (AO,WS)
I/O, PGCK4 (Al)
I/O
I/O
I/O (CS1, A2)
I/O (A3)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O

vec

-----

I/O
I/O
I/O (A4)
I/O (A5)
I/O
I/O
4-112

-

P149
P150
P151
P152
P153
P154
P159
P160
P16l
P162
P163
P164
P165
P166

-

P167
P168
P169
P170
P171
P172
P173

-

-

P174
P175
P176
P177

M2
Ml
L3
L2

P202
P203
P205
P206

Bndry
Scan

619
622

625
628
631
634
637
640
643
646
649
652
655
658
661
664
667
670
673
676

XC4020E Pad Name
I/O
I/O
I/O (A6)
I/O (A7)
GND

HQ

PG

HQ

208
P178
P179
P180
P181
P182

223
Ll
Kl
K2
K3
K4

240
P207
P208
P209
P210
P211

Bndry
Scan

74
77
80
83

4/2/96

Additional No Connect (N.C.) Connections on HQ208 &
HQ240 Packages

0

2
5
8
11
14
17
20
23
26
29
32
35
38
41

3/20/96

:+

Pins marked with this symbol are reserved for Ground
connections on future revisions of the device. These pins
do not physically connect to anything on the current device
revision. However, they should be externally connected to
Ground, if possible.

44
47
50
53
56
59
62
65
68
71
July 30,1996 (Version 1.03)

~XIUNX
Pin Locations for XC4025E, XC4028EX, &
XC4028XL Devices
XC4025E,
128EXlXL
Pad Name

VCC
1/0 (A8)
1/0 (A9)
1/0 (A19)
1/0 (A18)
110
1/0
1/0 (A10)
1/0 (A11)

GNO
1/0

110
1/0

HQ
208

PG
223

P183
P184
P185
P186
P187
P188
P189
P190
P191

J4
J3
J2
J1
H1
H2
H3
G1
G2

-

1/0

VCC
1/0
1/0

-

110

P192
P193
P194

1/0

GNO

-

1/0
1/0
1/0

110
1/0
1/0
1/0 (A12)

W(A13)-

H4
G4
F1
E1
G3

P195
P196
P197
P198
P199
P200

F2
01
C1
E2
F3
02

GNO
VCC
1/0

110
1/0
1/0

F4
E4
81
E3
C2
82

HQ
240

HQ

PG
299

304

BG
352

P38 VCC*
P37 014
P36 C14
P35 A15
P34 815
P33 C15
P32 015
P31 A16
P30 816
- GNO*
J4
P29 C16
J5
P28. 817
H2
P27 C17
G1
P26 818
P222 E1
P25 VCC*
P223 H3
P23 C18
P224 G2
P22 017
P225 H4
P21 A20
P226 F2 I P20 819
P227 F1
P19 GNO*
P18 C19
H5
G3
P17 018
P228 01
P16 A21
P229 G4
P15 820
P230 E2
P14 I C20
P231 F3
P13 821
P232 G5
P12 822
P233 C1
P10 C21
GNO*
I
- VCC* i
020 .
F4
P9
P8
E3
A23
P234 02
P7
021
P235 C2
P6
C22
P236 F5
P5
824
P237~ P4 , C23
P238 03
P3
022
P239 C3 . P2 I C24
P212
P213
P214
P215
P216
P217
P218
P220
P221

K1
K2
K3
K5
K4
J1
J2
H1
J3

P201
P202
P203 i
1/0 (A14)
1/0, SGCK1, P204
GCK8 (A15)
VCC
P205 03 P240 A2
Pi VCC'
GNO
P2
P1
04
81 ! P304 GNO'
110, PGCK1, P4
P2
04 P303 023
C3
GCK1 (A16)
1/0 (A17)
P5
C4
P3
82 P3021 C25
P6
1/0
83
P4
83 P301 I 024
P7
1/0
C5
P5
E6 P300 I E23
IIO,TOI
P8 I A2
P6
05 P299 I C26
1/0, TCK
P9~ P7+C4 P298 E24
A3 I P297 F24
!
1/0

1/0
,1/0

XC4025E,
128EXlXL
Pad Name

July 30, 1996 (Version 1.03)

VCC
GNO
110

98
101
104
107
110
113
116
119

1/0
1/0
1/0

-

-

-

GNO
1/0, FCLK1
110
,1/0, TMS
1/0

P10
P11
P12
P13

134
137
140
143

PG

HQ

299

304

06

P296

-

C6
A3
85
86
05
06

P8
pg
I

P10
P11
P12
P13

I

P14
P15
P16
P17
P18

C7

-

07
08

A4

A5
87
A6
-.

VCC
!I/O
1/0

HQ
240

-

1/0
1/0

!

P14
P15
P16
P17
P18
P19
P20
P21

1/0

110
GNO:j:
1/0

146
149
152
155
158
161
164
167

110
110
I/O

Ii;o-1/0

I/O
1/0

GNO
VCC

170
173
176
179
182
185
188
191

PG
223

1/0
1/0

122
125
128
131

1

r--::-

1/0

Bndry
Scan

HQ
208

1/0
1/0
1/0
1/0
1/0
1/0

-

-

I

GNO:j:

P23
C8
P24
A7
88
P25
A8
P26
P27
89
C9
P28
09 I P29
010 P30
C10 ! P31
810 i P32
A9 I P33
A10 I P34
A11 P35
Cl1 P36

-

C12

-

1/0

197
200
203
206
209
212
--

I/O

-

011
012

P33
P34
P35
P36
P37

B11
A12
B12
A13
C12

1/0

VCC
1/0

I/O
1/0
1/0, FCLK2
LGNO

P276
P275
P274
P273
P272
P271
P270
P269
P268
P267
P266
P265

P37

1/0

194

88
A8
C9
89
E10
A9
010
C10
A10
A11
810
811
C11
E11
011
A12
812
A13

--".-

1/0
1/0

P295
P294
P293
P292
P291
P290
P289
P288
P287
P286
P285
P284
P283
P282
P280
P279
P278
P277

P22

-

P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P3l
P32

E7
84
C5
A4
07
C6
E8
85
A5
86
08
C7
87
A6
C8
E9
A7
09

-'---

- 012P38tii2
P39 B13
P40 A16
P41 A14
P42 C13
P43 B14
P44 I 013
P45 I A15

---

BG
352

Bndry
Scan

E25
VCC'
GNO'
026
G24
F25
F26
H23
H24 I
, G25 ,
G26
GNO'
J23
J24
H25
K23
VCC'
K24 I
J25

215

I

L24
K25
'GNO"
I
L25
L26
M23
M24
M25
M26
N24
N25
GNO*
VCC'I
N26
I P25 i
!

218
221
224
227
230
233
236
239
242
245
248
251
254
257

I

260
263

I

266
269

272275
278
281
284
287

290
293

P2~*23 ,I 296
c-::I P263 P241 299
R26 I 302
R25
305
R24
308
311
R23
GNO'
314
P258 T26
317
P257 T25
320
P256 T23
P255 1V26 323--P253 VCC'
P252 U24
3~
P251 V25
329 i
P250 V24
332 I
335!
P249 U23
P248 GNO'
~
P262
P261
P260
P259

~--

4-113

XC4000 Series Field Programmable Gate Arrays

XC4025E,
128EXlXL
Pad Name

1/0
1/0
1/0
1/0
1/0

110
1/0
1/0

HQ

PG
223

240

-

-

-

P38
P39
P40
P41

013
014
B13
A14
A15
C13

GNO
VCC
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0, SGCK2,

GCK2
o (Ml)
.
GNO..,-_.-.I (MO)
VCC
I (M2)
1/0, PGCK2,
GCK3
1/0 (HOC)
~--

1/0
1/0
1/0
1/0 (LOC)
1/0
1/0

'ifc)1/0
1/0
1/0
1/0

GNO
1/0
1/0
1/0
1/0

1/0

4-114

304

P46
P47
P48
P49
P50
P51

B15
E13
C14
A17
014
B16
C15
E14

P247
P246
P245
P244
P243
P242
P241
P240

-

-

-

-

P42
P43
P44
P45
P46
P47

B14
A16
B15
C14
A17
B16

P52
P53
P54
P55
P56
P57

A18
015
C16
B17
B18
E15
016
C17

P239
P238
P237
P236
P235
P234
P233
P232

BG
352

Bndry
Scan

Y26
W25
W24
V23
AA26
Y25
Y24
AA25
GNO'
VCC*
AB25
AA24
Y23
AC26
AA23
AB24
A025
AC24

338
341
344
347
350
353
356
359

362
365
368
371
374
377
380
383

P48
P49
P50
P55
P56
P57

C15
015
A18
016
C16
B17

P58
P59
P60
P61
P62
P63

A20
A19
C18
B20
017
B19

P231
P230
P229
P228
P227
P226

AB23
GNO*
A024
VCC*
AC23
AE24

386

P58
P59
P60
P61
P62

E16
C17
017
B18
E17

P64
P65
P66
P67
P68

C19
F16
E17
018
C20
F17
G16

P225
P224
P223
P222
P221
P220
P219

394
397
400
403
406
409
412

-

019
E18
020
G17
F18
H16
E19
F19
E20
H17
G18
G19
H18
F20
J16
G20

A023
AC22
AF24
A022
AE23
AE22
AF23
VCC*
GNO*
A020
AE21
AF21
AC19
A019
AE20
AF20
AC18
GNO*
A018
AE19
AC17
A017
VCC*
AE18
AF18

-

-

-

P63
P64
P65
P66

F16
C18
018
F17
E15
F15

P69
P70
P71
P72
P73
P74

-

-

-

P67
P68
P69
P70
P71

G16
E18
F18
G17
G18

P72
P73

H16
H17

P75
P76
P77
P78
P79
P80
P81
P82

-

VCC

110

HQ

PG
299

-

VCC
GNO
1/0
1/0
1/0

HQ

208

P218
P217
P216
P215
P214
P213
P212
P211
P210
P209
P208
P207
P206
P204
P203
P202

389

390
391

415
418
421
424
427
430
433
436
439
442
445
448
451
454

XC4025E,
128EXlXL
Pad Name

1/0
1/0

HQ
208

-

GNO:j:

PG
223

-

HQ

PG
299

240

J17
H19
P83

110
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)

VCC
GNO
1/0
1/0
1/0
1/0

110
1/0
1/0
1/0

GNO:j:

P74
P75
P76
P77
P78
P79
P80
P8l
P82
P83
P84
P85

G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16

-

P98

P86
P87
P88
P89
P90

M18
M17
N18
P18
M16

-

-

-

N15
P15
N17
R18
T18
P17

P107
P108
P109
P110
Pili
P112

-

-

-

L15
M15

VCC

I/O
GNO
I/O
1/0
1/0

-

110
1/0

110
I/O
110
GNO
VCC
110
110
I/O
I/O
110
I/O

P84
P85
P86
P87
P88
P89
P90
P9l
P92
P93
P94
P95
P96
P97

M17
M16
N19
P20
T20
N18
P19
N17
R19
R20
N16
P18
U20
P17
T19
R18
P16
V20

1/0
1/0
1/0
1/0
1/0
1/0
1/0

H2O
J18
J19
K16
J20
K17
K18
K19
L20
K20
L19
L18
L16
L17
M20
M19
N20
M18

P91
P92
P93
P94

-

-

-

-

N16
T17
R17
P16
U18
T16

R17
T18
U19
V19
R16
T17
U18
X20

-

P95
P96
P97
P98
1/0
P99
I/O, SGCK3, Pl00
GCK4

P99
P100
P101
P102
P103
P104
P105
P106

P1l3
Pll4
P115
P116
P117
P118

HQ
304

BG
352

P20l AE17
P200 AE16
GNO*
P199 AF16
P198 AC15
P197 A015
P196 AE15
P195 AF15
P194 A014
P193 AE14
P192 AF14
P19l VCC*
PleO GNO*
P189 AE13
P188 AC13
P187 A013
P186 AF12
P185 AE12
P184 A012
P183 AC12
P182 AF11
- GNO*
P181 AE11
P180 A011
P179 AF9
P178 A010
P177 VCC*
P175 AE9
P174 A09
P173 AC10
P172 AF7
P171 GNO*
P170 AE8
P169 A08
P168 AC9
P167 AF6
P166 AE7
P165 A07
P164 AE6
P163 AE5
GNO*
- VCC*
P162 A06
P161 AC7
P160 AF4
P159 AF3
P158 A05
P157 AE3
P156 A04
P155 AC5

Bndry
Scan

457
460

463
466
469
472
475
478
481
484

487
490
493
496
499
502
505
508
511
514
517
520

523
526
529
532
535
538
541
544
547
550
553
556

559
562
565
568
571
574
577
5:J

July 30, 1996 (Version 1.03)

~XILINX
XC4025E,
128EXlXL
Pad Name

GNO
DONE
VCC
PROGRAM
I/O (07)
I/O, PGCK3,
GCK5
110
I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O (06)
I/O
I/O
I/O
I/O
I/O
I/O
110
GNO
110
I/O
I/O, FCLK3
I/O
VCC
I/O (05)
I/O (CSO)
GNO:f:
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O (04)
I/O
VCC
GNO
1/0(03)
I/O(RS)
I/O
I/O
I/O
I/O

HQ
208

223

HQ
240

P101
P103
P106
P108
P109
P110

R16
U17
R15
V18
T15
U16

P119 W20 P154 GNO'
P120 V18 P153 A03
P121 X19 P152 VCC'
P122 U17 P151 AC4
P123 W19 P150 A02
P124 W18 P149 AC3

P111
P112

-

T14
U15
R14
R13

P125
P126
P127
P128

-

-

-

-

-

-

-

P113
P114
P115
P116
P117
P118

V17
V16
T13
U14
V15
V14

-

-

-

P119

P120
P121

PG

T12
R12
Rll
U13
V13

-

-

P122
P123

U12
V12

-

-

-

-

-

P124 Tll
P125 U11
P126 Vll
P127 Vl0
P128 Ul0
P129 T10
P130 Rl0
P131 R9
P132 T9
P133 U9
P134 V9
P135 V8
P136 U8
P137 T8

PG

299

T15
U16
V17
X18
U15
T14

HQ
304

P148
P147
P146
P145
P144
P143

-

P129 Wi? P142
P130 V16 P141
P131 X17 P140
P132 U14 P139
P133 V15 P138
P134 T13 P137
W16 P136
- W15 P135
P135 X16 P134
P136 U13 P133
P137 V14 P132
P138 W14 P131
P139 V13 P130
P140 X15 P129
P141 T12 P127
P142 X14 P126
P143
U12 P125
W13 P124
-

-

X13 P123
V12 P122
P144 W12 P121
P145 T11 P120
P146 X12 Pl19
P147 un Pl18
P148 Vll Pl17
P1.49 Wll Pl16
P150 X10 P115
P151 Xl1 Pl14
P152 W10 Pl13
P153 Vl0 Pl12
P154 Tl0 Pl11
P155 Ul0 Pll0
P156 X9 Pl09
P157 W9 Pl08

July 30, 1996 (Version .1.03)

BG

352

AB4
A01
AA4
AA3
AB2
AC1
VCC'
GNO'
Y3
AA2
AA1
W4
W3
Y2
Y1
V4
GNO'
V3
W2
U4
U3
VCC'
V2
Vl

Bndry
Scan

583
586
589
592
595
598
601
604

607
610
613
616
619
622
625
628
631
634
637
640
643
646

-

-

U2
T2
GNO'
Tl
R4
R3
R2
Rl
P3
P2
Pl
VCC'
GNO'
N2
N4
N3
Ml
M2
M3

649
652
655
658
661
664
667
670
673
676

-

679
682
685
688
691
694

XC4025E,
128EXlXL
Pad Name

110
I/O
GNO:f:
I/O
I/O
110(02)
110
VCC
I/O
I/O, FCLK4
I/O
I/O
GNO
I/O

w----

I/O
I/O
110
I/O
I/O
I/O
GNO
VCC
I/O (01)
I/O (RCLK,
ROY/BUSY)
I/O
110
I/O
110
I/O
(Ob,DIN)
I/O, SGCK4,
GCK6
(OOUT)
CCLK
VCC
0, TOO
GNO
I/O (AO, WS)
I/O, PGCK4,
GCK7 (Al)
I/O
I/O
I/O
(CS1, A2)
I/O (A3)
I/O
I/O
VCC
GNO
I/O

HQ
208

P138
P139

223

HQ
240

-

-

PG

-

P158

V7
U7

P159
P160
P161
P162
P163
P164
P165
P166

299

HQ
304

X8
V9

Pl07
P106

-

-

PG

U9 P105
T9 P104
W8 P103
X7 P102
X5 Pl01
V8
P99
W7 P98
U8
P97
W6 P96
X6
P95
T8
P94
V7
P93
X4
P92
U7
P91
W5
P90
V6
P89
r---.T7
P88
"----.
X3
P87

BG

352

M4

Bndry
Scan

L1

697
700

GNO' r--L2
703
L3
706
Jl
709
K3
712
VCC'
J2
715
J3
718
K4 I 721
Gl
724
GNO'
H2
727
H3
730
J4
733
Fl
736
G2
739
G3
742
.. _---- ---_._----F2
745
E2 , 748
GNO'
i
VCe'
------F3
751
G4
754

-

-

P140
P141

P142

V6
U6
R8
R7
T7

-

-

-

-

-

R6
R5
V5
V4
U5
T6

P16?
P168
P169
P170
P17l
P172

-

-

-

-

V3
V2

P173
P174

U6
V5

P86
P85
P84
P83
P82
P81
P80

02
F4
E3
C2
03

757
760
763
766
769

E4

772

-

P143
P144
P145
P146

PH7
P148

--

-

--,.

P149
P150
P151

U4
T5
U3

P175
P176
Pl77

W4
W3
T6
U5
V4

P152

T4

P178

Xl

P79

P153
P154
P159
P160
P161
P162

V1
R4
U2
R3
T3
U1

P179
P18D
P18l
P182
P183
P184

V3
Wl
U4
X2
W2
V2

P78 C3
P77 VCC'
P76 04
P75 GNO'
P74 B3
P73 C4

2
5

P163
P164
P165

P3
R2
T2

P185
P186
P18?

R5
T4
U3

P72
P71
P70

05
A3
06

8
11
14

P166

N3

P188

Vi
R4
P5

P69
P68
P67

C6
B5

-

-

17
20
23

-

-

-

P4

P189

U2

VCC'
- GNO'
P66 C7

-

I

I

A4

0

I

I

26

4-115

XC4000 Series Field Programmable Gate Arrays
XC4025E,
128EXlXL
Pad Name
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GNO
I/O (A4)
I/O (A5)
I/O
I/O
I/O (A21)
I/O (A20)
I/O (A6)
I/O (A7)
GNO

HQ

208

P167
P168
P169
P170

-

PG
223

PG
299

HQ

240

N4 P190
P2 P191
T1 ' P192
Rl P193
N2 P194
- Pi95

T3
Ul
P4
R3
N5
T2
R2
Tl
N4
P3
P2
N3
Rl
M5
Pl
M4
N2

P171
P172
P173

-

M3
Pi
N1
M4
L4

P196
P197
P198
P199
P200
P201

-

-

-

-

I

P174
P175
P176
Pl77
P178
P179
P180
P181
P182

M2 P202
Ml P203
L3 P205
L2 P206
L1 P207
Kl P208
K2 P209
K3 P210
K4 , P211

I

N1
M3
M2
L5
M1
L4
L3
L2
L1

HQ

304

BG
352

P65 B6
P64 A6
P63 08
P62 B7
P61
A7
P60 09
P59 C9
P58 GNO*
P57 B8
P56 010
P55 Cl0
P54 B9
P52 VCC*
P51
A9
P50 011
P49 B11
P48 All
- GNO*
P47 012
P46 C12
P45 B12
P44 A12
P43 C13
P42 B13
P41 A13
P40 B14
P39 GNO'

Bndry
Scan

Additional No Connect (N.C.) Connections on HQ208
Package

29
32
35
38
41
44
47
50
53
56
59
62
65
68
71
74
77
80
83
86
89
92
95

-

~

4/2/96

3/15/96
Additional Ground (GND) Connections on HQ240
Package

3/21/96
The Ground (GNO) package pins in the above table should
be externally connected to Ground if possible; however,
they can be left unconnected if necessary for compatibility
with other devices.

Additional No Connect (N.C.) Connections on HQ304
Package

Pads labelled GNO' are internally bonded to a Ground
plane within the BG352 package. They have no direct connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the BG352 package. They have no direct connection
to any package pin.

t---

Pads labelled GNO:j: should be connected to Ground if possible; however, they can be left unconnected if necessary
for compatibility with other devices.

N.C.
P11
P24
P53
PlOD
P128
P176
P205
P254
P281

3/21/96
Note: In XC4025 (no extension) devices in the HQ304
package, P101 is a No Connect (N.C.) pin. P101 is Vcc in
XC4025E/L and XC4028EX/XL devices. Where necessary
for compatibility, this pin can be left unconnected.

4-116

July 30, 1996 (Version 1.03)

~:XILINX
Additional No Connect, Vcc & Ground Connections on
BG352 Package

I

3/21/96

July 30, 1996 (Version 1.03)

4-117

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4036EXlXL Devices
I XC4036EXlXL
Pad Name
GNO
i
11/0, GCK1 (A16)
I/O (A17)
I/O
I/O
~io, TOI
I/O, TCK
I/O
'----I/O
I/O
I/O
VCC
GNO
I/O
I/O
I/O

HQ304 PG411
P304
P303
P302
P301
P300
P299
P298

P297
P296

-

1/0
1/0

P295
P294
P293
P292
P291
P290
P289
P288
P287
P286
P285
P284
P283
P282
P280
P279

I/O
I/O

-

1/0
1/0

P278
P277

-----

1/0
1/0
1/0
-~--

-

--

--

I/O
1/0

GNO
1/0, FCLK1
1/0
1/0, TMS
1/0

VCC

GNO
VCC
1/0
1/0
f-1/0
1/0
1/0
1/0

'vb

1/0

GNO
IvCC

1

4-118

-

P276
P275
P274
P273
P272
P271
P270
P269
P268
P267

GNO*
H8
F6
B4
04
B2
G9
F8
C5
A7
A5
VCC*
GNO*
B8
C9
E9
F12
010
B10
F10
F14
GNO*
C11
B12
E11
E15
VCC*
F16
C13
B14
E17
E13
A15
GNO*
VCC*
B16
016
018
A17
E19
B18
C17
C19
GNO*
VCC*

BG432

Bndry
Scan

GNO*
029
218
221
C30
E28
224
E29
227
030
230
031
233
E30
236
E31
239
242
G28
245
G29
VCC*
GNO*
H28
248
H29
251
G30
254
H30
257
J28
260
J29
263
H31
266
269
J30
+- -~
GNO*
K28
272
K29
275
K30
278
K31
281
VCC*
L29
284
L30
287
M29
290
M31
293
N31
296
N28
299
GNO*
VCC*
P30
302
P28
305
P29
308
R31
311 ,
R30
R28
317
R29
320
T31
323
GNO*
VCC*
-

~~

XC4036EXlXL
Pad Name
1/0
1/0
11/0
1 1/0

I/O
1/0
1/0
1/0

VCC
GNO
1/0

W
1/0
1/0
1/0
1/0

VCC
1/0
1/0
1/0
1/0, FCLK2

GNO
1/0
1/0
1/0
1/0
1/0
1/0
1/0
,1/0

GNO
VCC

~
1/0
1/0

I/O
1/0
1/0
1/0
1/0

I/O
1/0, GCK2

0(M1)-- --

~
I (MO)
VCC
I (M2)

--

--

HQ304 PG411
P266
P265
P264
1-=.P263
P262
P261
P260
P259

P258
P257
-

P256
P255
P253
P252
P251
P250
P249
P248
P247
P246
P245
P244
P243
P242
P241
P240

-

P239
P238
P237
P236
-

P235
P234
P233
P232
P231
P230
P229
P228
P227

I

BG432

F20
T30
B20
T29
C21
U31
B22
U30
E21
U28
022
U29
A23
V30
B24
V29
VCC* VCC*
GNO* GNO*
A25
W30
024
W29
B26
Y30
A27
Y29
C27
Y28
F24
AA30
VCC* VCC*
E25
AA29
E27
AB31
B28
AB30
C29
AB29
GNO* GNO*
F26
AB28
028
AC30
B30
AC29
E29
AC28
A029
F28
F30
A028
C31
AE30
E31
AE29
GNO* GNO*
VCC* VCC*
B32
AF31
A33
AE28
A35
AG31
F32
AF28
C35
AG30
B38
AG29
AH31
E33
G31
AG28
H32 I AH30
B36
AJ30
AH29
A39
GNO* GNO*
AH28
E35
VCC* VCC*
AJ28
G33

Bndry
Scan
326
329
332
335
338
341
344
347

350
353
356
359
362
365
368
371
374
377

380
383
386
389
392
395
398
401

404
407
410
413
416
419
422
425
428
431
434

437

438._--

July 30, 1996 (Version 1.03)

~XILINX
- - "

XC4036EXlXL
Pad Name

I/O, GCK3
I/O (HOC)
I/O
I/O
I/O
I/O (LOC)
I/O
I/O
I/O
I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (INIT)
VCC
GNO
I/O
I/O
I/O

---

- -

HQ304

PG411

P226
036
P225
C37
P224
F34
P223
J33
P222
038
P221 G35
E39
K34 I
P220
F38
P219
G37
VCC'
GNO*
P218
H38
P217
J37
P216
G39
P215
M34
P214
N35
P213
P34
P212
J35 ,
P211
L37
P210 GNO' I
P209
M38
P208
R35
P207
H36
P206
T34
vce*
P204
P203
N37
P202
N39
U35
R39
P201
M36
P200
V34 I
GNO*
VCC·
P199
R37
P198
T38
P197
T36
V36
P196
P195
U37
P194
U39
P193
V38
P192
W37
vcc·
P191
GNO*
P190
Y34
P189
P188
AC37
P187 .
AB38
-

July 30, 1996 (Version 1.03)

BG432

AK29
AH27
AK28
AJ27
AL28
AH26
AL27
AH25
AK26
AL26
VCC'
GNO*
AH24
AJ25
AK25
AJ24
AL24
AH22
AJ23
AK23
GNO*
AJ22
AK22
AL22
AJ21
VCC·
AH20
AK21
AK20
AJ19
AL20
AH18
GNO*
VCC*
AK19
AJ18
AL19
AK18
AH17
AJ17
AJ16
AK16
VCC·
GNO*
AL16
AH15
AK15

Bndry
Scan

439
442
445
448
451
454
457
460
463
466
469
472
475
478
481
484
487
490

493
496
499
502

505
508
511
514
517
520

523
526
529
532
535
538
541
544
547
550
553

XC4036EXlXL
Pad Name

I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O
I/O

T!O
I/O
I/O
110

VCC
I/O
11/0

I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O, GCK4
GNO

I~NE

~~~GRAM

110 (07)

I/O, GCK5
I/O
I/O

HQ304

PG411

BG432

P186
P185
P184
P183
P182
P181
P180

A036
AA35
AE37
AB36
A038
VCC*
GNO*
AB34
AE39
AM36
AC35
AG39
AG37
VCC*
A034
AN39
AE35
AH38
GNO*
AJ37
AG35
AF34
AH36
AK36
AM34
AH34
AJ35
GNO*
VCC·
AL37
AT38
AM38
AN37
AK34
AR39
AN35
AL33
AV38
AT36
GNO*
AR35
VCC·
AN33
AM32
AP34
AW39
AN31

AJ14
AH14
AK14
AL13
AK13
VCC*
GNO*
AJ13
AH13
AL12
AK12
AH12
AJ11
VCC·
AL10
AK10
AJ10
AK9
GNO'
AL8
AH10
AJ9
AK8
AK7
AL6
AJ7
AH8
GNO*
VCC·
AK6
AL5
AH7
AJ6
AK5
AL4
AK4
AH5
AK3
AJ4
GNO'
AH4
VCC·
AH3
AJ2
AG4
AG3
AH2

P179
P178
P177
P175
P174
P173
P172
P171
P170
P169
P168
P167
P166
P165
P164
P163
-

P162
P161
P160
P159
Pi58
P157
P156
P155
P154
P153
P152
P151
P150
P149
P148
P147

,

Bndry
Scan

556
559
562
565
568

571
574
577
580
583
586

589
592
595
598

-

---

601
604
. ---607
610
613
616
619
622

625
628
631
634
637
640
643
646
649
652

,-

655
658
661
664

I

XC4000 Series Field Programmable Gate Arrays
-.~

XC4036EXlXL
Pad Name
I/O
I/O
I/O
I/O
I/O
I/O
VCC
GNO
I/O (D6)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O, FCLK3
I/O
VCC
I/O (D5)
I/O (CSO)
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O.
I/O
I/O
I/O (04)
I/O
VCC
GNO
I/O (D3)
I/O (RS)
I/O
I/O
I/O
I/O
I/O

4-120

HQ304

PG411

BG432

-

AV36
AR33

P146
P145
P144
P143

AP32
AU35
AW33
AU33
VCC*
GND*
AV32
AU31

AH1
AF4
AF3
AG2
AE3
AF2
VCC*
GND*
AF1
AD4

P142
P141
P140
P139
P138
P137
P136
P135
P134
P133
P132
P131
P130
P129
P127
P126

-

P125
P124

P123
P122
P121
P120
P119
P118
P117
P116
P115
P114
P113
P112
P111
P110
P109
P108
P107

AR31
AP28
AT32
AV30
AR29
AP26
GND*
AU29
AV28
AT28
AR25
VCC*
AP24
AU27
AR27
AW27
AT24
AR23
GND*
VCC*
AP22
AV24
AU23
AT22
AR21
AV22
AP20
AU21
VCC*
GND*
AU19
AV20
AV18
AR19
AT18
AW17
AV16

AD3
AE2
AC3
AD1
AC2
AB4
GNO*
AB3
AB2
AB1
AA3
VCC*
AA2
Y2
Y4
Y3
W4
W3
GND*
VCC*
V4
V3
U1
U2
U4
U3
T1
T2
VCC*
GND*
T3
R1
R2
R4
R3
P2
P3

Bndry
Scan
667
670
673
676
679
682

685
688
691
694
697
700
703
706

709
712
715
718

XC4036EXlXL
Pad Name
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O (D2)
I/O
VCC
I/O
I/O, FCLK4
I/O
I/O
GND
I/O
I/O
I/O
I/O

721
724

I/O
I/O
I/O
I/O
GND

727
730
733
736

VCC
I/O (D1)
I/O (RCLK,
RDY/BUSY)

-

739
742
745
748
751
754
757
760

763
766
769
772
775
778
781

I/O
I/O
I/O
I/O
I/O
I/O
I/O (~O, DIN)
I/O, GCK6 (DOUT)
CCLK
VCC
O,TDO
GND
I/O (AO, WS)
I/O, GCK7 (A1)
I/O
I/O
I/O
I/O
I/O (CS1, A2)

HQ304

PG411

BG432

P106

AP18
vec*
GND*
AR17
AT16
AV14

P4
VCC*
GND*
N3
N4
M1
M2
L2
L3
VCC*
K1

P105
P104

-

AW13
P103
AR15
IP102- AP16
P101
P99
P98
P97
P96
P95
P94
P93
P92
P91
P90
P89
P88
P87

P86
P85

P84
P83
P82
P81
P80
P79
P78
P77
P76
P75
P74
P73
P72
P71

P70

VCC*
AV12
AR13
AU11
AT12
GND*
AP14
AR11
AV10
AT8
AT10
AP10
AP12
AR9
GND*
VCC*
AU7
AW7
AW5
AV6
AR7
AV4
AN9
AW1
AP6
AU3
AR5
VCC*
AN7
GND*
AT4 ,
AV2
AM8
AL7
AR3
AR1
AK6

K2
K3
K4
GND*
J2
J3
J4
H1
H2
H3
H4
G2
GND*
VCC*
G4
F2

Bndry
Scan
784

787
790
793
796
799
802

805
808
811
814

817
820
823
826
829
832
835
838

841
844

F3
E1
E3
01
E4
D2

847
850
853
856
859
862

C2
D3
D4
VCC*
C4
GND*

865
868

B3
D5
B4
C5
B5
C6
A5

2
5
8
11
14
17
20

0

-

July 30, 1996 (Version 1.03)

~XILINX
XC4036EXlXL
Pad Name

--

HQ304

PG411

BG432

Bndry
Scan

XC4036EXlXL
Pad Name

HQ304

PG411

BG432

Bndry
Scan
134

I/O (A3)

P69

AN3

07

23

110

P29

U5

019

110

P68

AM6

B6

26

I/O

P28

T4

A20

137

110

P67

AM2

A6

29

110

P2

B20

140

-

VCC*

VCC*

-

I/O

-

N1

C20

143

GND*

GND*

-

I/O

P27

R5

C21

146

I/O

P66

AL3

08

32

110

P26

M2

A22

149

I/O

P65

AH6

C7

35

VCC

P25

VCC*

VCC*

-

110

P64

AP2

B7

110

P23

L3

B22

152

I/O

P63

AK4

09

38
41

I/O

P22

T6

C22

155

I/O

P62

AG5

010

44

I/O

P21

N5

B23

158

I/O

P61

AF6

C9

47

I/O

P20

M4

A24

161

110

P60

AL5

B9

50

GND

P19

GND'

GND'

-

I/O

P59

I/O

P18

K2

022

164

P58

C10
GND*

53

GND

AJ3
GND*

-

I/O

P17

K4

C23

167

I/O

P57

AH2

B10

56

I/O

P16

P6

B24

170

I/O

P56

AE5

A10

59

I/O

P15

M6

C24

173

I/O

P55

AM4

C11

62

I/O

P14

J3

A26

176

I/O

P54

AD6

012

65

110

P13

H2

C25

179

VCC

P52

VCC*

VCC*

-

I/O (A12)

P12

H4

024

182

I/O

P51

AG3

B11

68

I/O (A13)

P10

G3

B26

185

I/O

P50

AG1

C12

71

GND

GND'

-

AC5

C13

74

VCC

VCC*

VCC*

-

I/O

-

-

GND'

I/O

AE1

A12

77

I/O

P9

K6

A27

188

110

P49

AH4

014

80

I/O

P8

G1

025

191

I/O

P48

AB6

B13

83

I/O

E1

C26

194

-

GND*

GND*

I/O

E3

B27

197

VCC*

VCC*

-

-

I/O

P7

J7

C27

200

110 (A4)

P47

AD2

C14

86

I/O

P6

H6

828

203

I/O (A5)

P46

AB4

A13

89

I/O

P5

C3

027

206

I/O

P45

AE3

B14

92

I/O

P4

02

B29

209

I/O

P44

AC1

015

95

I/O (A14)

P3

E5

C28

212

110 (A21)

P43

AD4

C15

98

I/O, GCK8 (A15)

P2

G7

028

215

110 (A20)
00(1).6)

P42

AA5

B15

101

VCC

P1

VCC'

VCC*

-

P41

AA3

B16

104

4/2/96

I/O (A7)

P40

Y6

A16

107

GND

P39

GND*

GND*

VCC

P38

VCC*

VCC*

-

I/O (A8)

P37

W3

D17

110

I/O (A9)

P36

Y2

A17

113

I/O (A19)

P35

V4

C18

116

110 (A18)

P34

T2

018

119

I/O

P33

U1

B18

122

110

P32

V6

A19

125

I/O (A10)

P31

U3

B19

128

I/O (A11)

P30

R1

C19

131

-

VCC*

VCC'

-

GND'

GND'

-

VCC
GND

GND
VCC

VCC
GND
I

July 30, 1996 (Version 1.03)

---

f-. __ . --.- ..

--

Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the associated package. They have no direct connection to any package pin.

4-121

XC4000 Series Field Programmable Gate Arrays

Additional No Connect (N.C.) Connections on HQ304
Package

Additional No Connect, Vcc & Ground Connections on
BG432 Package

3/22/96

Additional No Connect, Vcc & Ground Connections on
PG411 Package

3/26/96
3/22/96

4-122

July 30, 1996 (Version 1.03)

~XILINX
Pin Locations for XC4044EXlXL Devices
XC4044EXlXL
Pad Name

BG432

PG411

PG411

BG432

Bndry Scan

110

B20

T29

365

11/0
'110
110

C21

U31

368

GNO'

GNO'

-

H8
F6

029

242

C30

245

,1/0

B4

E28

248

1/0

04

E29

251

GNO

1/0, GCK1 (A16)
1/0 (A17)

j----

~---"-

f - , - - - - - - - - - - - 1---

I/O, TOI

B2

030

110, TCK
I/O

G9

031

F8

E30

110

C5

1/0

A7

E31
r-- G28

---

1/0

rvcc
GNO

- - t-

A5

G29

VCC*

VCC*

GNO*

GNO*

I

254
257

r-1

260~

263
266
269

~
,

-

C7

F30

272

08

F31

275

1/0

B8

H28

278

1/0
1/0

XC4044EXlXL
Pad Name

H29

E9

G30

281
284--

F12

H30

287

1/0

010

J28

290

H31

,

I/O

E15

K31

311

~~-----'~--~-t__~~~-r-------

CUa

1/0

_V_C
__C_*___ t-_~:---,~
L29
314

~-

C13
B14

L30
M29

317
320

1/0

E17

M31,

323

I/O

E13
A15
GNO*

110
f-:Gcc-N=o-------YCC

VCC*

110
1/0

F18
C15

1/0

B16

,1/0
1/0

016
018

I

N31==t=
N28
GNO*

I

+

-ivcc*
,

=t

N29
N30
P30

1/0

A1~

1/0

E1 ~--l-

326
329
-

,335

P29

341
344

R31

347

I
I

'vee-

w---

F20

July 30, 1996 (Version 1.03)

R30

I,

GNO'
VCC'

-+---:::::1

'I

C23

V28

386

F22

W31

389

VCC'

VCC*

-

GNO

GNO'

GNO'

170

A25

W30

392

110

024

W29

395

1/0

B26

Y30

A27

Y29

I,

-

I
I

,

377

I

1/0
f------vcc

C27
F24
i
VCc*-+-

--l

--

398

E25

-:J"

l

l, _ _
T3_0_~!____3_6_2__ j

AA29

410

AB31

413

110, FCLK2

C29

AB29

GNO*

GNO'

F26
028

I/O

B30

f-=--

i
,

407

-

AB30

1/0

404

,

VCC*

B28

1/0

401

-----

Y28
AA30

1/0

41-~
-_ .... _.. - -

--,.. _- ...

419

-----,-- _._._.

AB28

422

AC30

425

AC29

428
431

--

E29

AC28

1/0

030

A031

434

11/0

032

AD30

437

11/0
110

F28

A029

F30

A028

4~

1/0

C31

AE30

446

110

AE29

'GNQ'

E31

44~

GNO*

GNO*

VCC

VCC*

I

B32

!

§=

110

~/O
1/0
~

W
O
1/0

--

AE28

A35

AG31

F32
B38
E33

I

t
I

AG29
AH31
AH30

B36

AJ30

GNO

A39
GNO*

I

AH29
GNO*

I (MO)

E35

.1/0,
GCK2
1
o (M1)

Ycc

H32

VCC'

I (M2)

G33

1/0, GCK3
110 (HOC)

036
C37

I

I

1
I

452

45~

I

AF281
AG30

AG28

G31

440

-

AF31

f-- A33

C35

----

VCC*

I

1/0

R29
356
-T3--1---+--3-5-9--1

GNO'
VCC*

383

=,_,~

~ _____~t__~B~18~,
GNO

V29

~

11/0
1 110

I
--+-1-

B24

1110

I
350_R~2~8--~--~35~3,--~-

C17
C19

380

1/0
~-

j

338,

+-' P28
,

l
I

-

I

V3G

GNO

296

308

VCC'
F16

U29

1/0

~C-=~-----~E1:-1
--t---K-3-0-~--~~--

VCC

022

110--- ,---- ~7

1/0
,_F_1_
4_r_---:c-:J.,,30c-:-± 299
GNO
GNO*
GNO* ~
I-:-I/C=O'-,-=FC=LcK-:c1:------M---C11
K28
302
c:---------++-----c=-:-:::---+--~;-;;--- -+----:-=-5.c-11/0
B12
K29
30
'1/0, TMS

374

A23

vcc

'i7o -------- t-El10~--:j29----1--~
I

371

U28

1/0

1110

C9

F10

U30

-

110

- - t--

B22
E21

1/0

I/O
'1/0

1/0
1/0

1/0

Bndry Scan

AH28
vCC'
AJ28
AK29

~AH27

458461
464

I

467

i

470

,I

476

I

1

473
479

I

482

I
1

485

1
1

486
487 - -

--t--~

4·123

I

XC4000 Series Field Programmable Gate Arrays

XC4044EXlXL
Pad Name

XC4044EXlXL
Pad Name

-- - - - - - -

PG411

BG432

Bndry Scan

I/O

F34

AK28

493

I/O

J33

AJ27

496

I/O

D38

AL28

499

I/O (LDC)

G35

AH26

502

I/O

I/O

E39

AL27

505

VCC

I/O

K34

AH25

508

GND

GND*

GND*

I/O

F38

AK26

511

I/O

AB34

AJ13

637

I/O

G37

AL26

514

I/O

AE39

AH13

640

VCC

VCC*

VCC*

I/O

AM36

AL12

643

GND

GND*

GND*

-

I/O

AC35

AK12

646

H38

AH24

517

I/O

AG39

AH12

649
652

I/O

PG411

BG432

Bndry Scan

I/O

AA35

AH14

625

I/O

AE37

AK14

628

I/O

AB36

AL13

631

AD38

AK13

634

VCC*

VCC*

-

I

I/O

J37

AJ25

520

I/O

AG37

AJ11

I/O

G39

AK25

523

VCC

VCC*

VCC*

I/O

M34

AJ24

526

I/O

AD34

AL10

I/O

K36

AH23

529

110

AN39

AK10

658

I/O

K38

I

AK24

532

I/O

AE35

AJ10

661

I/O

N35

AL24

535

I/O

AH38

AK9

664

I/O

P34

I

AH22

538

GND

GND*

GND*

541

I/O

AJ37

AL8

667

I

AK23

544

I/O

AG35

AH10

670

I/O

AF34

AJ9

673

I/O

AH36

AK8

676

I/O

J35

110

L37

GND

--

AJ23
I

655

GND*

GND*

M38

AJ22

547

I/O

R35

AK22

550

I/O

AK38

AJ8

679

I/O

H36

AL22

553

I/O

AP38

AH9

682

AK7

685

AL6

688

110

I/O

T34

AJ21

556

I/O

AK36

VCC*

VCC*

-

I/O

AM34

--~.-

VCC
I/O

N37

AH20

559

I/O

AH34

AJ7

691

110

N39

AK21

562

I/O

AJ35

AH8

694

I/O

U35

AK20

565

GND

GND*

GND*

AJ19

568

VCC

VCC*

VCC*

AL20

571

I/O

AL37

AK6

697

I/O

AT38

AL5

700

I/O

AM38

AH7

703

110

AN37

AJ6

706

110

R39

I/O

M36

I/O

V34

AH18

574

GND

GND*

GND*

-

VCC

VCC*

VCC*

I/O

R37

AK19

577

I/O

AK34

AK5

709

I/O

T38

AJ18

580

I/O

AR39

AL4

712
715

I

I/O

T36

AL19

583

I/O

AN35

AK4

I/O

V36

AK18

586

I/O

AL33

AH5

718

110

U37

AH17

589

I/O

AV38

AK3

721

-c::--

I/O

U39

AJ17

592

I/O, GCK4

AT36

AJ4

724

I/O

W35

AK17

595

GND

GND*

GND*

-

I/O

AC39

AL17

598

DONE

AR35

AH4

-

I/O

V38

i

AJ16

601

VCC

VCC*

VCC*

I/O (INIT)

W37

I

PROGRAM

AN33

AH3

VCC

VCC*

VCC*

I/O (D7)

AM32

AJ2

727

GND

GND*

GND*

110, GCK5

AP34

AG4

730

607

I/O

AW39

AG3

733

610

I/O

AN31

AH2

736

----

AK16

I/O

Y34

AL16

I/O

AC37

AH15

,

604

I

--

I/O

Y38

AL15

613

I/O

AV36

AH1

739

I/O

AA37

AJ15

616

I/O

AR33

AF4

742

I/O

AB38

AK15

619

I/O

AP32

AF3

745

I/O

AD36

AJ14

622

I/O

AU35

AG2

748

4-124

July 30, 1996 (Version 1.03)

~XILINX
XC4044EXlXL
Pad Name

XC4044EXlXL
Pad Name

PG411

BG432

Bndry Scan

PG411

BG432

Bndry Scan

I/O

AW33

AE3

751

I/O

AR17

N3

877

I/O

AU33

AF2

754

I/O

AT16

N4

880

VCC

VCC*

VCC*

I/O

AV14

M1

883

GNO

GNO*

GNO*

AW13

M2

886

1/0(06)

AV32

AF1

757

AR15

L2

889

I/O

AU31

A04

760

I/O

AP16

L3

892

I/O

AR31

A03

763

VCC

VCC*

VCC*

~ ...

-

I/O (02)

I/O

AP28

AE2

766

110

AV12

K1

895

I/O

AP30

A02

769

I/O, FCLK4

AR13

K2

898

I/O

AT30

AC4

772

I/O

AU11

I/O

AT32

AC3

775

I/O

K3

901

AT12

K4

904

I

I/O

AV30

A01

778

GNO

GNO*

GNO*

-

I/O

AR29

AC2

781

110

AP14

J2

907

I/O

AP26

GNO

GNO*

I/O
I/O

AB4

784

GNO*

-

AU29

AB3

787

AV28

AB2

I

I/O

AR11

J3

910

11/0
11/0

AV10

J4

913

AT8

Hi

916

I/O

AT10

H2

919

I/O, FCLK3

AT28

AB1

790
7.93--

I/O

AP10

H3

922

I/O

AR25

AA3

796

I/O

AP12

H4

925

VCC

VCC*

VCC*

-

I/O

G2

928

AP24

AA2

799

AU9

G3

I/O (CSO)

AU27

Y2

802

~
I/O

AR9

1/0(05)

931
934--

I/O

AR27

Y4

805

GNO

AV8

F1

GNO*

GNO*

"------

I/O

AW27

Y3

808

VCC

VCC*

VCC*

110

AT24

W4

811

110 (01)

AU7

G4

937

110

AR23

W3

814

AW7

F2

940--

GNO

GNO*

GNO*

I/O (RCLK,
ROY/BUSY)

VCC

VCC*

VCC*

-

I/O

AW5

F3

943

I/O

AW25

W2

817

I/O

AV6

E1

946

110

AW23

V2

820

I/O

AR7

E3

I/O

AP22

V4

823

AV4

01

I/O

AV24

V3

826

I/O

AU23

U1

829

I/O

AT22

U2

832

I/O

AR21

U4

835

I/O

AV22

U3

838

I/O (04)

AP20

T1

841
844

110

AU21

T2

VCC

VCC*

VCC*

GNO

GNO*

GNO*

I/O (03)

AU19

T3

847

AV20

R1

850

I/O

AV18

R2

853

I/O

AR19

R4

856

I/O

AT18

R3

859

I/O

AW17

862

110

AV16

P2
. P3

I/O

AP18

P4

868

I/O

AU17

N1

871

I/O

AW15

N2

874

VCC

VCC*

VCC*

GNO

GNO*

GNO*

July 30, 1996 (Version 1.03)

I

865

~

-

t

-.

949
,

952

I/O

AN9

E4

7;0

AW1

02

1I0(00,0IN)

AP6

C2

961

110, GCK6
(OOUT)

AU3

03

964

CCLK

AR5

04

VCC

VCC*

VCC*

0, TOO
GNO

I/O (RS)

-

w--

I

I/O (AO, WS)

AN7

C4

GNO*

GNO*

AT4

B3

955
958--

I
I

0

-

2--

I/O, GCK7 (Ai)

AV2

05

5

I/O

AM8

B4

8

I/O

AL7

C5

I/O

AR3

B5

I/O

AR1

C6

17

1/0 (CS1, A2)

AK6

A5

20
23

11
--i~4--

I/O (A3)

AN3

07

I/O

AM6

B6

26

I/O

AM2

A6

29

-

VCC

VCC*

VCC*

GNO

GNO*

GNO*

--

I

4-125

j

I

XC4000 Series Field Programmable Gate Arrays
XC4044EXlXL
Pad Name

XC4044EXlXL
Pad Name

PG411

BG432

Bndry Scan

I/O

R5

C21

I/O

M2
VCC·

A22
VCC*

164
167

922

170

I/O

L3
T6
NS

C22
923

173

I/O

M4

A24

179

GNO*
K2

GNO*
022

182

I/O
I/O

K4

C23

185

P6

924

62

I/O

M6

C24
023

188
191

PG411

BG432

AL3
AH6

08

32

I/O

C7

35

I/O
I/O

AP2
AK4

97
09

38
41

VCC
I/O

I/O

ANl

98

44

I/O

AK2

47

I/O

AG5

A8
010

I/O

I/O
I/O

AF6
AL5

C9
99

50
53

I/O
GNO

AJ3
GNO*

Cl0
GNO*

I/O

AH2

910

I/O

Bndry Scan

56
59

GNO
I/O

I/O

AE5

Al0

65

I/O

L5

I/O
I/O
VCC

AM4
A06

Cll
012

68
71

I/O
I/O

VCC*

VCC*

I/O

AG3

911

74

I/O
I/O (A12)

J5
J3
H2

I/O

AGl

C12

77

I/O (A13)

I/O
I/O

AC5
AE1

C13
A12

80
83

GNO
VCC

I/O

AH4

014

86

I/O
GNO

A96

913

89

GNO*
VCC·

GNO*
VCC·

A02

C14

92

I/O (A5)

A94

A13

95

I/O

AE3

914

98

I/O

AC1

015

I/O (A21)
I/O (A20)

A04

C15
915
A15

VCC
I/O (A4)

I/O
I/O
I/O (A6)
I/O (A7)
GNO
VCC

H4

203
206

G3
GNO*
VCC*

926
GNO*
VCC*

209

I/O

K6

A27

I/O

025

212
215

I/O

G1
E1

C26

218

I/O
I/O

E3
J7

927
C27

I/O
I/O

H6

928

C3

027

230

101
104

I/O

02

929

233

E5

107

I/O, GCK8 (A1S)
VCC

C28
028
VCC*

239

.--

C16
916

116

Y6
GNO*

A16
GNO*

119

VCC*

I/O (A9)

017
A17

I/O

Y2
V2

I/O
I/O (A19)

W5
V4

I/O (A18)

T2

I/O

U1
V6

I/O
I/O (A10)

200

AA3

W3

C17
917
C18
018

125
128
131
134
140

A19

143
146

I/O (A11)
VCC

C19
VCC*

149

GNO

GNO*

GNO*

-

U5
T4

019

152

A20

155

P2
N1

920
C20

158
161

W
4-126

G7
VCC*

~---

-

221
224
227

236

4/2/96

Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC' are internally bonded to a Vcc plane
within the associated package. They have no direct connection to any package pin.

137

918
919

I/O
I/O

I/O (A14)

197

122

U3
R1
VCC·

I/O

194

C25
024

110
113

VCC*

176

925
A26

AA5
A92
AC3

I/O (A8)

-

July 30, 1996 (Version 1.03)

~XIUNX
Additional No Connect, Vcc & Ground Connections on
PG411 Package

Additional No Connect, Vcc & Ground Connections on
BG432 Package

3/22/96

3/26/96

July 30, 1996 (Version 1.03)

4-127

XC4000 Series Field Programmable Gate Arrays

Pin Locations for XC4052XL Devices
XC4052XL Pad Name

GNO
1/0, GCK1 (A16)
110 (A17)
1/0
1/0
1/0, TDI
1/0, TCK

GNO
1/0
1/0
1/0
1/0
1/0
1/0

VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0

GNO
1/0
1/0
1/0
1/0

GNO
1/0, FCLK1
1/0
1/0, TMS
1/0

VCC
1/0
1/0

GNO
1/0
1/0
1/0

110
1/0
1/0

GNO
VCC
1/0
1/0

110
110
1/0
1/0

GNO

4-128

BG432

GNO*
029
C30
E28
E29
030
031
GNO"
F28
F29
E30
E31
G28
G29
VCC*
GNO"
F30
F31
H28
H29
G30
H30
GNO*
J28
J29
H31
J30
GNO*
K28
K29
K30
K31
VCC"
L29
L30
GNO*
M30
M28
M29
M31
N31
N28
GNO*
VCC*
N29
N30
P30
P28
P29
R31
GNO*

XC4052XL Pad Name

Bndry Scan

266
269
272
275
278
281

284
287
290
293
296
299

302
305
308
311
314
317
320
323
326
329

332
335
338
341
344
347
350
353
356
359
362
365

368
371
374
377
380
383

1/0
1/0
1/0
1/0

GNO
VCC
1/0
1/0
1/0

110
GNO
1/0
1/0

110
1/0
1/0
1/0

VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0

GNO
1/0
1/0

VCC
1/0
1/0

110
110, FCLK2

GNO
1/0
1/0
1/0
1/0

GNO
1/0
1/0
1/0
1/0
1/0
1/0

GNO
VCC
1/0
1/0
1/0
1/0
1/0

BG432

Bndry Scan

R30
R28
R29
T31
GNO*
VCC*
T30
T29
U31
U30
GNO*
U28
U29
V30
V29
V28
W31
VCC*
GNO"
W30
W29
W28
Y31
Y30
Y29
GNO*
Y28
AA30
VCC"
AA29
AB31
AB30
AB29
GNO*
AB28
AC30
AC29
AC28
GNO*
A031
A030
A029
A028
AE30
AE29
GNO"
VCC*
AF31
AE28
AF30
AF29
AG31

386
389
392
395

- - - --

-

398
401
404
407

410
413
416
419
422
425

428
431
434
437
440
443
446
449

452
455
458
461
464
467
470
473
476
479
482
485
488
491

494
497
500
503
506

July 30, 1996 (Version 1.03)

~XILINX
XC4052XL Pad Name

1/0

GNO
1/0
1/0
1/0
1/0
1/0
1/0, GCK2

o (M1)
GNO
I (MO)
VCC
I (M2)
1/0, GCK3
110 (HOC)
1/0

110
1/0
1/0 (LOC)
GNO
110
1/0
1/0
1/0
1/0
1/0

VCC
GNO
1/0
1/0
1/0
1/0
1/0
1/0

GNO
1/0
1/0
1/0
1/0

GND
1/0
1/0
1/0
1/0

VCC
110
1/0

GNO
1/0
1/0
1/0

110

July 30, 1996 (Version 1.03)

BG432

Bndry Scan

AF28
GNO'
AG30
AG29
AH31
AG28
AH30
AJ30
AH29
GNO'
AH28
VCC'
AJ28
AK29
AH27
AK28
AJ27
AL28
AH26
GNO'
AK27
AJ26
AL27
AH25
AK26
AL26
VCC'
GNO'
AH24
AJ25
AK25
AJ24
AH23
AK24
GND'
AL24
AH22
AJ23
AK23
GNO'
AJ22
AK22
AL22
AJ21
VCC'
AH20
AK21
GNO'
AJ20
AH19
AK20
AJ19

509

1/0
1/0

512
515
518
521
524
527
530

GNO
VCC

533

534
535
538
541
544
547
550
553
556
559
562
565
568

XC4052XL Pad Name

1/0
1/0
1/0
1/0

110
1/0

GNO
1/0
1/0
1/0

110 (INIT)
VCC
GNO
1/0

110
1/0
1/0

GNO
1/0
1/0
1/0
1/0
1/0
1/0

571
574
577
580
583
586

VCC
GNO

589
592
595
598

1/0

1/0
1/0
1/0
1/0

110

601
604
607
610

GNO
1/0

110
VCC
1/0
,1/0
1/0
1/0

GNO

613
616

619
622
625
628

'i7C)1/0
1/0
1/0

1---

GNO
1/0
1/0

BG432

BndryScan

AL20
AH18
GNO'
VCC'
AK19
AJ18
AL19
AK18
AH17
AJ17
GNO'
AK17
AL17
AJ16
AK16
VCC'
GNO'
AL16
AH15
AL15
AJ15
GNO'
AK15
AJ14
AH14
AK14
AL13
AK13

631
634

637
640
643
646
649
652

655
658
661
664

I

667
670
673
676
679
682
685
688
691
694

vce'
GNO'
AJ13
AH13
AL12
AK12
AJ12
AK11
GNO'
AH12
AJ11
VCC'
AL10
AK10
AJ10
AK9
GNO'
AL8
AH10
AJ9
AK8
GNO'
AJ8
AH9

697
700
703
706
709
712
715

,

718
721

724
727
730
733

736
739
742
745
748
751

4-129

XC4000 Series Field Programmable Gate Arrays
----

,-------XC4052XL Pad Name

I/O
I/O

BG432

Bndry Scan

AK7
AL6

754
757

I/O
AJ7
'ij--=0----------+t----A
cc·H
-:-:::8- - GNO

I

I/O
I/O

769

AH7
772
-+!---A-J-6--+1--7-7-5-

I/O
I/O
GNO

787
790

I

I

796

GNO*
AH4

-

VCC*

-

I/O

AE3

I/O

AF2
VCC*

I/O

889

I/O

W1
W4

895
898

W3

901

W<:>.

793

-I

I/O

886

Y3
Y1

--

--~-

I
I

832
835

-

---

GNO*
AF1
A04
-A03-

838
841
844

V2

110
I/O

V4

I/O

--

I/O

'GNQ-

rooI/O

I/O (04)

V3

907
910
913 - -

U1

916

U2
GNO*

I/O (03)
I/O (RS)

T3
R1

I/O

R2

va

R4
GNO*

GNO

4-130

I

9~

I/O
I/O

P4
N1

955
958

N2

961

949

I/O
VCC

VCC'

GNO

GNO*

-

N3
N4

964

I/O

M3
M4

A01
AC2

859
862-

GNO*
L2

I/O

I

I

952

I/O
GNO
I/O (02)
IVCC

~

I/O, FCLK4

-----

L3
VCC*
K1
K2

--

940
943--

I/O

856

868

i

P2
P3

AC3

871

934

I/O

~~D

--

937

R3

M2

AB3
AB2

I

I/O

I/O

--

928
931

VCC*
GNO*

853

----

925

T2

I/O
VCC
GNO

919

U3
T1

AC4
GNO*

865

I

922

M1

AB4
GNO*

+-

U4

I/O
I/O

110
1/0-----------++-

904--

-

11/0

AE2
847
~--------~--~~-+---~~
A02
850

1

~

--

892

VCC*
W2 - - c--

I/O

~-~-----~t__-~~- - - - c - - - c - -

-

GNO*

tvec

784

AH3
-AJ2
802
~() (07L _ _ _ _ _ _--++-_ _
_
805
,110, GCK5
AG4
I/O
808
AG3
110
AH2
811
~-----------#--~~-~---AH1
814 __
I
I/O
AF4
!8~
GNO*
f=-=----~'
GNOI/O
AF3
820
I
---------+!--~~
AG2
II/O-----------+t----c--::-c----+----,~--c-1
AG1
826
829-I/O
AE4

11/0 (06)

Y4

I/O

'Ito

~~

VCC
GNO

I/O

I/O
GNO

_.- - - - - -

=-

-

781

AK3

.

GNO*

~\O)

AL4
GNO*

I/O

VCC
PROGRAM

880
883

I/O

110
I/O

GNO
OONE

AA2
Y2

778

AJ5
AK4
--AH5

110, GCK4

877

AK5

~1I:-:::0----------++-~AH'6

I/O

I

AA3
VCC*

110(05)

f-:-1/·;-::0:-------------++----,A,--:KO-:6--t---~
AL5

I

874

rvcc-

760

--76~

VCC*-~

I/O

Bndry Scan

AB1

I/O, FCLK3
110

GNO* - - - -

VCC

- - - - - ---=--:
BG432

XC4052XL Pad Name

967

I

97~
973

i

976

I

979

I

+-r-9a5'
-

--9~jI

I

I

988
991

I
I

July 30, 1996 (Version 1,03)

~:XILINX
---~-~.

XC4052XL Pad Name

~--

~-~

BG432

Bndry Scan

BG432

Bndry Scan

I/O

K3

994

110

B8

50

I/O

K4

997

I/O

A8

53

GNO*

-

I/O

J2

1000

110

J3

110

J4

110

H1

GNO

GNO

XC4052XL Pad Name

GNO*

-

I/O

010

56

1003

I/O

C9

59

1006

110

B9

62

1009

I/O

C10

65

IGNO
I/O

GNO*

-

B10

68

GNO

GNO*

I/O

H2

1012

I/O

H3

1015

I/O

A10

I/O

H4

1018

I/O

C11

I/O

G2

1021

I/O

012

I/O

G3
F1

1024
1027 - -

VCC

I/O
GNO

GNO*

VCC

VCC'

-

I/O
110
~-~

--

-----

I

71

I

74
77

VCC*

-

B11

80

C12

83

I

--

GNO*

I/O (01)

G4

1030

I/O

013

86

110 (RCLK, ROY/BUSY)

F2

1033

I/O

B12

89

I/O

F3

1036

I/O

C13

92

I/O

E1

1039

I/O

A12

95

110

F4

1042

I/O

014

98

I/O

E2

1045

I/O

B13

101

GNO*

-

GNO

GNO*

I/O

E3

1048

VCC

VCC*

I/O

01

1051

I/O (A4)

C14

104

I/O

E4

1054

I/O (A5)

A13

107

110

02

1057

I/O

B14

110

I/O (00, OIN)

C2

1060

I/O

015

113

I/O, GCK6 (OOUT)

03

1063

I/O (A21)

C15

116

CCLK

04

-

I/O (A20)

B15

119

VCC

VCC*

I

~~-

GNO

O,TOO

C4

GNO

GNO*
122--

0

I/O

A15
C16

125

B16

128

110 (AO,WS)

B3

2

I/O, GCK7 (A1)

05

5

~

A16

131

110

B4

8

GNO

GNO*

-

I/O

C5

11

VCC

VCC*

I/O

A4

14

I/O (A8)

017

134

I/O

06

17

I/O (A9)

A17

137

GNO

GNO*

I/O (A6)
I/O (A7)

I/O

C17

140

I/O

B5

20

1/0

B17

143

I/O

C6

23

GNO

I/O (CS1, A2)

A5

26

I/O (A19)

C18

146

110 (A3)

07

29

I/O (A18)

018

149

GNO

GNO*

--

GNO*

I/O

B6

32

I/O

B18

152

I/O

A6

35

I/O

A19

155

VCC

VCC*

110 (A10)

B19

158

GNO

GNO*

I/O (A11)

C19

161

I/O

08

38

I/O

C7

41

If0

B7

44

I/O

09

47

July 30, 1996 (Version 1.03)

VCC

VCC*

GNO

GNO*

-

019

164

A20

167

~-

I/O

4-131

XC4000 Series Field Programmable Gate Arrays

XC4052XL Pad Name

I/O
I/O
I/O
I/O
GNO
I/O
I/O
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
11/0

I/O (A14)
I/O, GCK8 (A15)
VCC

BG432

Bndry Scan

B20
C20
B21
020
GNO*
C21
A22
VCC*
B22
C22
B23
A24
GNO*
022
C23
B24
C24
GNO*
023
B25
A26
C25
024
B26
GNO*
VCC*
A27
025
C26
B27
A28
026
GNO*
C27
B28
027
B29
C28
028
VCC*

170
173
176
179

Additional No Connect, Vcc & Ground Connections on
BG432 Package

182
185

188
191
194
197

200
203
206
209

212
215
218
221
224
227

230
233
236
239
242
245
248
25f254
257
260
263

4/2/96
Pads labelled GND* are internally bonded to a Ground
plane within the associated package. They have no direct
connection to any package pin.
Pads labelled VCC* are internally bonded to a Vcc plane
within the associated package. They have no direct connection to any package pin.

3/22/96

4-132

July 30, 1996 (Version 1.03)

~XILINX
Package-Specific Pinout Tables
PC84 Package Pinouts
Pin

XC4003E

P1
P2
P3
P4
P5
P6
P7
P8
P9
Pl0

GND
VCC
I/O (A8)
110 (A9)
I/O (Ala)
110 (All)
I/O (A12)
I/O (A13)
110 (A14)

I Pl1
P12

P13

P14
P1S
P16
P17
P18
Pi9
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
Cp30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44

I/O,
SGCKl
(A15)
VCC
GND
I/O,
PGCKl
(A16)
I/O (A17)
I/O, TDI
I/O, TCK
I/O, TMS
I/O
I/O
I/O
GND

Pin

XC4005E
XC4006E
XC4005L
GND
GND
VCC
VCC
110 (A8)
I/O (A8)
I/O (A9)
I/O (A9)
I/O (Ala) I/O (Ala)
I/O (All) I/O (All)
110 (A12) I/O (A12)
I/O (A13) I/O (A13)
I/O (A14) I/O (A14)
I/O,
I/O,
SGCKl
SGCKl
(A1S)
(A15)
VCC- --VCC

GND

I

I/O (A12)
110 (A13)
I/O (A14)

-G~

GND
I/O,
110,
PGCKl
PGCKl
(A16)
(A16)
110 (All) I/O (A17)
I/O, TOI
I/O, TDI
I/O, TCK
I/O, TCK
I/O, TMS I/O, TMS
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
vccvcc
VCC
I/O
I/O
I/O
1/0--- c-- I/O
I/O

1/0
1/0
1--1/0
I/O
I/O
I/O
I/O
I/O
I/O,
I/O,
SCGK2
SCGK2
(Ml)- :---0 (Ml)

110-

I

I/O
I/O

I

[

I

i
i

I/O (A12)
I/O (A13)
I/O (A14)
I/O,
SGCKl
(A15)
VCC
GND
110,
PGCKl
(A16)
I/O (A17)
I/O, TDI
I/O, TCK
I/O, TMS
I/O

I/O
I/O
I/O,
SCGK2
o (Ml)--

I

GND
GND
GND
I (MO)-I (MO)
I (MO)
I (MO)
VCC
vcc
vcc
vcc
VCC
I (M2)
I (M2)
I (M2)
I (M2)
I (M2)
---!-----I/O, -1/0,
110,
I 1/0,
PGCK2
PGCK2
PGCK2
PGCK2
PGCK2
I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)
I/O (LDC) I/O (]])C) I/O (LDC) I/O (LDC) I/O (]])C)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-I/O
I/O
I/O
I/O
I/O
-I/O (INIT) I/O (INIT) I/O (INIT) I/O (lNIT) I/O (INIT)
VCC
VCC
vcc
vcc
vcc
GND
GND
GND
GND
I/O
I/O
I/O
I/O
I/O

1;0,'---

l

~

--~-

July 30, 1996 (Version 1.03)

I/O
I/O,
SGCK3

I/O
I/O
I/O
I/O,
SGCK3
GND

I/O
I/O
I/O
I/O,
SGCK3
GND

XC4008E

XC4010E
XC4010L
I/O
I/O - 1/0--

I/O
I/O
I/O

I/O
I/O
I/O
I/O -I/O-I/O
1/0,-- --~
SGCK3
SGCK3
:----GND-GND

PS2
GND
DONE
DONE
DONE
DONE- - DONEP53
f---P-5-4+t-----V-C~Cc--+--V-Cc-C~+--V--C=-Cc----- I--VCCVCC
PRO-

PROGRAM
!--P=-5"""C6+t----C-C
1/0=--C(DC-=7=-)+--:--:1/0=--C(D~=7=-)+--:--:1/0=--=-:(D7)
P55

GRAM

I/O,
PGCK3
P58 I/O (D6)
PS9 I/O (D5)
Cpoo i/o (CSO)
P61
P62

!P63
P64

PROGRAM

-----

P57

I/O,
PGCK3
I/O (D6)
I/O (DS)
I/O (CSO)

I/O,
PGCK3
I/O (D6)
I/O (DS)
1/0 (CSO)

PRO- ---

PRO--

I GRAM

GRAM

I/O (D7)

I/O (D7)

I/O'iJ~ I/O,

PGCK3
I/O (D6)
I/O (D5)
I/O (CSO)

PGCK3
I/O (~
I/O (DS)

--i/O(CSO)

I/O (D4)
I/O (D4)
I/O (D4)
I/O (D4)
I/O (D4)
I/O --r---IfC)"""--I7O- -~ -----,;c)--vcc
GND

P65

-I~

I/O
I/O,
SCGK2
O(Ml)
GND

I/O
I/O

vcc
GND

vcc
GND

I

vcc
I-- GND

VCC

GN~

P67
P68

I/O (D3)
I/O (RS)
1/0 (D2)
I/O

I/O (D3)
I/O (D3)
I/O (D3)
I/O (D3)
I/O (RS)
I/O (RS)
I/O (RS)
I/O (RS)
I/O (D2)
I/O (D2)
I/O (D2) i/o ((2)
I/O~ --I76~!---i/O-i--176--

P69

I/O (Dl)

I/O (Dl)

'P66

j
vcc
I/O
I/O
I/O
I/O
- 1/0-- -- I/O -I/O

GND
I (MO)

P48
P49
P50
P5i

I/O
I/O
GND
vcc

-----r-I/O

I/O
I/O,
SCGK2
O(Ml)

o

VCC
I/O (A8)
I/O (A9)
I/O (Ala)
I/O (All)

I/O,
SGCKl
(A15)
vcc
GND
I/O,
PGCKl
(A16)
I/O (A17)
I/O, TDI
I/O, TCK
I/O, TMS
I/O
I/O
I/O
GND

XC4005E XC4006E
XC4005L
I/O
I/O
I/O
P45
110
1/0
I/O
P46
I--P=-4:-=7+t--------cI/c:=0-+-----cI/c:=0-+-----cI/~0-

XC4010E
XC4010L
GND
VCC
I/O (A8)
110 (A9)
1/0 (Ala)
I/O (All)

XC4008E

XC4003E

I/O (Dl)

Go (Dl)-

I/O (Dl)

P70 I/O (RCLK, 11/0 (RCLK, I/O (RCLK, 11/0 (RCLK,ll/o (RCLK,
RDY/
RDYI
RDYI
RDY/
RDY/
BOSY)
BOSY)
BOSY)
BUSY)
BUSY)
I/O
I/O
I/O
:----170---110P71
(DO, DIN) (DO, DIN) (DO, DIN) (DO, DIN) (DO, DIN)
I/O,
I/O,
I/O,
I/O,
P72
SGCK4
SGCK4
SGCK4
SGCK4
SGCK4 1
(DOUT)
(DOUT)
PO,:!T)
(D~lJ!U (DOUT)-j
P73
CCLK I CCLK
CCLI{--'---+-CCLK -+-CCLK

---m,-

P74

VCC

VCC

VCC

VCC- 0~

_L _

0, TOO
0, TDO
0, TOO _0!_~Q
()o!DO
GND
GN-O-OND ~D
i GND-I/O
I/O ----I/O _ I _I/O
I I/O
(AO, WS) (AO, WS) (AO, WS) (AO, WS) (AO, WS)
!--P-7-8-+-1--'--'-c-I/O=--,--C-I--' I/O,
I/O,
- I/O,
1/0:-PGCK4
PGCK4
PGCK4
PGCK4
PGCK4
(Al)
(Al) --l-----iA1)
(Al)
(Al)
,
I/O
I/O __ 1 _ _I/O
I/O
1--1/0 - P79
(CS1, A2) (CSi, A2) (CS1, A2) (CSi, A2) (CSi, A2)
Cp8Q I/O (A3) I/O (A3) I/O (A3) I/O(A3jr---T!O-iA3)
P7S
P76
P77

P81
P82
P83

I/O (A4)
I/O (AS)
I/O (A6)

I/O (A4)
I/O (AS)
I/O (A6)

I/O (A4)
I/O (AS)
I/O (A6)

I/O (A4)
I/O (A4)
I/O (A5) '176(As)
1/0 (A6)
I/O (A6)

P84

I/O (A7)

I/O (A7)

I/O (A7) ~~_

I/O (A7)

2/28/96

4-133

I

XC4000 Series Field Programmable Gate Arrays

PQ100 Package Pinouts
PQ100 Pin

XC4003E

XC4005E

Pi

I/O (A14)

I/O (A14)

P2

I/O, SGCK1 (A15)

I/O, SGCK1 (A15)

P3

VCC

VCC

P4

GNO

GNO

P5

I/O, PGCK1 (A16)

I/O, PGCK1 (A16)

P6

I/O (A17)

I/O (A17)

P7

I/O, TDI

I/O, TOI

P8

I/O, TCK

I/O,TCK

P9

I/O, TMS

I/O, TMS

P10

I/O

I/O

P11

I/O

I/O

P12

I/O

I/O

P13

I/O

110

P14

GNO

GNO

P15

VCC

VCC

P16

I/O

I/O

P17

I/O

I/O

P18

I/O

I/O

P19

I/O

I/O

P20

I/O

I/O

P21

I/O

I/O

P22

I/O

I/O

XC4005E

PQ100 Pin

XC4003E

P52

GNO

GNO

P53

OONE

DONE

P54

VCC

VCC

P55

PROGRAM

PROGRAM

P56

I/O (07)

110(07)

P57

I/O, PGCK3

I/O, PGCK3
1/0(06)

P58

I/O (06)

P59

I/O

I/O

P60

I/O (05)

1/0(05)

P61

I/O (CSO)

I/O (CSO)

P62

I/O

I/O

P63

I/O

I/O

P64

I/O (04)

1/0(04)

P65
P66
-P67

I/O

I/O

VCC

VCC

GNO

GNO

P68

1/0(03)

1/0(03)

P69

I/O (RS)

I/O (RS)

P70

I/O

I/O

P71

I/O (02)

I/O (02)

P72

I/O

I/O

P73

I/O (01)

1/0(01)

P74

I/O (RCLK,
ROY/BUSY)

I/O (RCLK,
ROY/BUSY)

P23

I/O

I/O

P75

I/O (DO, DIN)

I/O (00, OIN)

P24

I/O, SCGK2

I/O, SCGK2

P76

I/O, SGCK4 (OOUT)

I/O, SGCK4 (OOUT)

P25

O(M1)

O(M1)

P77

CCLK

CCLK

P26

GNO

GNO

P78

VCC

VCC

P27

I (MO)

I (MO)

P79

0, TOO

0, TOO

P28

VCC

VCC

P80

GNO

GNO

P29

I (M2)

I (M2)

P81

I/O (AO, WS)

I/O (AO, WS)

P30

I/O, PGCK2

I/O, PGCK2

P82

I/O, PGCK4 (Ai)

I/O, PGCK4 (Ai)

P31

I/O (HOC)

I/O (HOC)

P83

I/O (CS1, A2)

I/O (CS1, A2)

P32

I/O

I/O

P84

I/O (A3)

I/O (A3)

P33

I/O (LOG)

I/O (LOC)

P85

1/0(A4)

I/O (A4)

P34

I/O

I/O

P86

I/O (A5)

I/O (A5)

P35

I/O

I/O

P87

I/O

I/O

P36

I/O

I/O

P88

I/O

I/O

P37

I/O

I/O

P89

I/O (A6)

I/O (A6)

P38

I/O

I/O

P90

I/O (A7)

I/O (A7)

P39

I/O (lNIT)

I/O (lNIT)

P91

GNO

GNO

P40

VCC

VCC

P92

VCC

VCC

P41

GNO

GNO

P93

I/O (A8)

110 (A8)

P42

I/O

I/O

P94

I/O (A9)

I/O (A9)

P43

I/O

I/O

P95

I/O

I/O

P44

I/O

I/O

P96

I/O

I/O

P45

110

I/O

P97

I/O (A10)

110 (A10)

P46

I/O

I/O

P98

I/O (A11)

I/O (A11)

P47

I/O

I/O

P99

I/O (Ai2)

I/O (A12)

P48

I/O

I/O

P100

I/O (A13)

I/O (A13)

P49

I/O

I/O

P50

I/O

I/O

P51

I/O, SGCK3

I/O, SGCK3

4-134

-

2128/96

July 30, 1996 (Version 1.03)

~:XILINX
I

VQ100 Package Pinouts
VQ100 Pin

XC4003E

Pl

GNO

P2

I/O, PGCKl (A16)

P3

I/O (A17)

P4

I/O, TOI

P5

I/O, TCK

P6

I/O, TMS

P7

I/O

P8

I/O

P9

I/O

Pl0

I/O

Pll

GNO

P12

VCC

P13

I/O

P14

I/O

P15

I/O

P16

I/O

P17

I/O

P18

I/O

P20

I/O

P21

I/O, SCGK2

P22

O(Ml)

P23

GNO

P24

I (MO)

P25

VCC

P26

I (M2)

P27

I/O, PGCK2

P28

I/O (HOC)

P29

I/O

P30

I/O (LOG)

P31

I/O

P32

I/O

P33

I/O

P34

I/O

P35

I/O

P36

I/O (INIT)

P37

VCC

P38

GNO

P39

I/O

P41

i

--

--

----

P43

1/0

P44

I/O

P45

I/O

P46

I/O

P47

I/O

P48

I/O, SGCK3

P49

GNO

P50

DONE

P51

VCC

July 30, 1996 (Version 1.03)

f
1---

P53

I/O (07)

P54

I/O, PGCK3

P55

1/0(06)

P56

I/O

P57

I/O (05)

P58

--

~

--

I
I

I/O (CSO)

P59

I/O

P60

I/O

P61

1/0(04)

P62

I/O

P63

VCC

P64

GNO

P65

1/0(03)

P66

I/O (RS)

P67

I/O

P68

1/0(02)

P69

I/O

---rI

---l

~

--

I/O (01)

P71

I/O (RCLK, ROY/BUSY)
I/O

----

P73

r------

--

P74
P75

0, TOO
GNO
I/O (AO, W8)

P78
P79

j---

P81

I/O (A3)
I/O (A4)

P83

I/O (A5)

P84

I/O

P85

I/O

PB6

I/O (A6)

VCC
I/O (AB)

P91

I/O (A9)

---

- - f---

I

I

I

-3

GND

P90

P93

l

I/O (A7)

PB9

P92

i---

f--

I
1

I/O, PGCK4 (Al)
I/O (CS1, A2) - -

P82

PBB

~
I

~~~------l

P77

PB7

f----

DIN)

P76

1--------- - - -

--

(~O,

I/O, SGCK4 (OOUT)

P80
--

-- -

P70

c----------

I/O
I/O

PROGRAM

P72

I/O

P42

XC4003E

P52

--

I/O

-

P19

P40

I
I

VQ100 Pin

I/O
I/O

---

P94

I/O (Al0)

P95

I/O (All)

P96

I/O (A12)

P97

I/O (A13)

••

P98

I/O (A14)

P99

I/O, SGCKl (A15)

Pl00

VCC

~
-

J

2/28/96

I
4-135

I

XC4000 Series Field Programmable Gate Arrays

PG120 Package Pinouts
PG120 Pin

XC4003E

N13

I/O, PGCK3
N.C.

N12
N11

I/O

N10

I/O (CSO)

N9

I/O

N8

I/O
I/O (03)
I/O (RS)

N7
N6

.----

N5
N4

I/O
I/O

N3

I/O (RCLK, ROY/BUSY)

N2
N1

I/O, PGCK4 (Ai)

M13
M12
M11

1/0(07)

M10

1/0(06)

M9

I/O (05)

M8

1/0(04)

M7

VCC

M6
M5

I/O
I/O (01)

M4

N.C.

M3

I/O, SGCK4 (OOUT)

M2

O,TOO

M1
Li3

N.C.

L12

I/O, SGCK3
OONE

L10

VCC

L9
L8
L7

N.C.
I/O

L6
L5
L4

I/O (AD, WS)

L1

I/O (A3)

K13

I/O

K12
K11

N.C.
GNO

K3

GNO

K2

I/O (CS1, A2)

K1
J13

I/O (A5)
I/O

1/0(A4)

J1

I/O
I/O

H12

I/O

H11

I/O
I/O

H3
H2

I/O (A6)

Hi

I/O (A7)
I/O
VCC
GNO
VCC
GNO

G1

I/O (A8)

F13
F12

I/O (INIT)

F11

I/O
I/O (A10)

F2
F1
E13

I/O

I/O
I/O (A9)
I/O

E12

I/O

E11

N.C.

E3

N.C.

E2
E1
013

N.C.
I/O

012

I/O
VCC

011

i-------

N.C.

H13

F3

N.C.

L2

J3
J2

G2

I/O (02)

L3

N.C.

G3

GNO

CCLK
VCC

I/O

J11

G11

I/O

XC4003E

J12

G13
G12

I/O (00, OIN)
I/O
PROGRAM

L11

4-136

PG120 Pin

I/O

03
02

I/O, SGCK1 (A15)

01
C13

I/O (A11)
I/O (LOC)

C12

I/O, PGCK2

C11
C10

I (MO)
GNO

C9

I/O

C8
C7

VCC

C6
C5
C4

I/O (A13)

---

I/O
I/O
I/O, TOI
GNO

C3

VCC

C2
C1

I/O (A14)
I/O (A12)

July 30, 1996 (Version 1.03)

~XILINX
PG120 Pin

XC4003E

PG120 Pin

XC4003E

813
812
811
810
89

N.C.
I (M2)
0(M1)
N.C.

A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

I/O
I/O

88
87
86
85
84
83
82
81
A13
A12
A11

July 30,1996 (Version 1.03)

I/O
I/O
GNO
I/O
I/O, TMS
I/O, TCK
I/O (A17)
I/O, PGCK1 (A16)
N.C.
I/O (HOC)
I/O, SCGK2
I/O

I/O
I/O
I/O
I/O
I/O
N.C.
N.C.
N.C.

~--

3/13/96

Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

4-137

I

XC4000 Series Field Programmable Gate Arrays

TQ144 Package Pinouts
TQ144 Pin

XC4005E

P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
P21
P22
P23
P24
P25
P26
P27
P28
P29
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P40
P41
P42
P43
P44
P45
P46

GND
I/O, PGCK1 (A16)
I/O (A17)
I/O

4-138

XC4006E

1/0,

GND
PGCK1 (A 16)
I/O (A17)

1/0
1/0, TDI
1/0, TCK

1/0
1/0
1/0, TDI
1/0, TCK

GND

GND

1/0

1/0
1/0
1/0, TMS
1/0

I/O
I/O, TMS
1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0

I/O
GND
VCC

GND
VCC

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

GND

GND

1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0

SCGK2
o (M1)
GND
I (MO)
VCC
I (M2)
1/0, PGCK2
1/0 (HOC)
1/0,

1/0

I/O
1/0

(LDC)
GND
I/O

1/0

SCGK2
o (M1)
GND
I (MO)
VCC
I (M2)
1/0, PGCK2
1/0 (HOC)
1/0,

1/0
1/0
1/0

110 (LDC)
GND
1/0

TQ144 Pin

XC4005E

XC4006E

P47
P48
P49
PSO
P51
PS2
P53
P54
P5S
P56
PS7
PS8
P59
P60
P61
P62
P63
P64
P65
P66
P67
P68
P69
P70
P71
P72
P73
P74
P75
P76
P77
P78
P79
P80
P81
P82
P83
P84
P8S
P86
P87
P88
P89
P90
P91
P92
P93
P94

1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0

(INIT)
VCC
GND
I/O
I/O
I/O

(INIT)
VCC
GND

1/0

1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0

I/O
1/0
1/0
1/0

GND
I/O
110
I/O

GND
1/0
1/0
1/0
1/0
1/0

1/0
1/0

SGCK3
GND
DONE
VCC
PROGRAM
1/0 (D7)
1/0, PGCK3

1/0,

1/0, SGCK3~

GND
DONE
VCC
PROGRAM
1/0 (D7)
1/0, PGCK3

1/0
1/0

1/0

I/O (D6)

I/O

1/0

1/0 (D6)
1/0

GND

GND

1/0
1/0
1/0 (DS)
1/0 (CSO)
1/0
1/0
1/0 (D4)
1/0

1/0
1/0
1/0 (DS)
1/0 (CSO)
1/0
1/0
1/0 (D4)
1/0

VCC
GND
I/O (03)
1/0 (RS)

VCC
GND
1/0 (D3)
1/0 (RS)

1/0

1/0

July 30, 1996 (Version 1.03)

~XILINX
TQ144 Pin

XC4005E

XC4006E

P142
P143
P144

1/0 (A14)
110, SGCK1 (A1S)
VCC

1/0 (A14)
1/0, SGCK1 (A1S)
VCC

2/28/96

Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by different devices.

I

July 30, 1996 (Version 1.03)

4-139

XC4000 Series Field Programmable Gate Arrays

PG156 Package Pinouts

4-140

July 30, 1996 (Version 1.03)

~~~~

~~~~~-

~:XILINX

I

2/28/96

Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by different devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

July 30, 1996 (Version 1.03)

4-141

XC4000 Series Field Programmable Gate Arrays

PQ160 Package Pinouts

PQ

160
XC4005E

4-142

XC4005E

XC4006E

XC4008E XC4010E XC4013E

XC4006E XC4008E XC4010E XC4013E

July 30, 1996 (Version 1.03)

~XILINX
PQ

160

PQ

XC4005E

XC4006E

Pin

XC4008E

XC4010E

XC4013E

160

XC4005E

XC4006E

XC4008E

XC4010E

XC4013E

Pin

I

2/28/96

Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by different devices.

July 30, 1996 (Version 1.03)

4-143

XC4000 Series Field Programmable Gate Arrays

TQ176 Package Pinouts
'----YQ176 Pin

TQ176 Pin

,
XC4010L

P1

GNO

_----=P=-:2_ _---l+- __ 1/0, PGCK1 (A16)
!------ P3

~----_n~----~-------1/0~(A~1~7~)~--~
P4
P5

I/O

1/0

c----..!-~----___
P7

r--______.JIO, TOI

1/0, TCK

1-------1---_ _ _P_8_

____
P9
--P10
IP11
I----------~
P12
P13
P14
---------------P15
1----P16

_

I/O
I/O
GNO
1/0

I/O
1/0, TMS

~------

--

--

--

~-

1---

1/0

--

1/0
1/0

I---

~------ _;;:;-~:;-;:~;-----ft-----~I~/O~-----i
1------ P-19 ----++---------:c:~=~--------i

-------P20----

r-------------:I-;::/O=-----------i

~------'P~-;:2~.;-1--- -tt-----G~N=-O---­

!--------~P~22~----H-------~V'C~c~-------

---P2S---- ------110---1----------

P24

1/0-1/0

1----P-2-5- - - - - -

- - - - - - - - - - - - ---- - - - - - - ;:::---------1

P26

1/0

---~i-----

r---------~----

---~P;:;;2:;-;;8------+t-------;-;1/0-;::--------I

1--

P29
P30
P31

1/0
1/0
-------c1/0-c------------l

1------~P~32~---ff-------~-----~

1/0

1---______

P33

GNO

------P3-4-------I-I-----------c10-=------~

1 - - - - - - - - - - - - + 1 - - - - - - - -__1c=-----------.j

1-______;P:;-;3:;_;;5-----lt-----.....1/..-:0'-------I
P36
1/0

____

t---_=-=~~7
~___

P38

t==-:-~~~--~ ~=

1:-cc/0=--____---l
1/0

--- ---~-

--=

f--_P41
1/0, SCGK2
I
P42
0 (M1)
-P43
GNO
---~:~--~----~-=---------,P44
I (MO)
P45
VCC
===-~_~~?
I (M2) - - - - - -

~

E

__-__ _ _

P47
P48
P49
P50
P51
P52
~P53
P54
-P55
P56
P57
I--P58
IP59
P60
P61
P62
P63
P64
1--P65
P66
,-P67
P68
P69
P70
P71
P72
1-P73
I--P74
f----P75
P76
1---P77
1-P78
P79
P80
P81
P82
P83
P84
~
P85
P86
1-P87
P88
1-P89
I--P90
1---'
P91
P92
P93

XC4010L
110, PGCK2
1/0 (HOC)
1/0
1/0
1/0
1/0 (LOC)
1/0
1/0

GND
I/O
I/O
I/O
I/O
1/0
1/0
1/0
1/0
1/0
1/0 (INIT)

VCC
GNO
1/0
1/0
1/0

~

1/0

110
1/0
1/0
1/0
1/0
1/0

GNO
1/0
--

110
1/0

r

---~-.

L~-P94----

1/0
I/O----~

--

1/0
1/0
1/0, SGCK3

GNO
DONE
VCC
PROGRAM
1/0 (D7)
f--o-___ ~O, !,GCK3
--'------

1/0
1/0

_ _ _" _ 0_ _ _ _ _ -

4-144

July 30, 1996 (Version 1.03)

~XILINX
TQ176 Pin
P95
P96
P97
P98
P99
Pl00
Pl0l
Pl02
I----~Pl 03

XC40i0L
I/O (06)
I/O
I/O
I/O
GNO
I/O
I/O
I/O (05)
I/O (CSO)

TQi76 Pin
P143
P144
P145
P146
P147
P148
P149
P150
P151

Pl04
I/O
Pl05
I/O
Pl06
I/O
Pl07
I/O
Pl08
I/O (04)
Pl09
I/O
~----~------~--------Pll0
VCC
-~ Plll
GNO
I/O (03)
I/O (RS)

Pl15

I/O

Pl17

I/O

r---~

f------~

--~~---P-1-1-6-----H----------1/0~------~

~--P118-----4~------I/~0-(~0~2)------~

f--~

~----P~1-1-9----~---------I~/0~~---~--­

~--~P~1-2-0-----H---------I/cO~---------

P121-~--~------------'1/0cc----------l

P122
P123
P124
P125
P126
P127
P128
P129
P130

GNO
I/O
I/O
I/O (01)
I/O (RCLK, ROY/BUSY)
I/O
I/O
I/O (~O, DIN)
I/O, SGCK4 (OOUT)-

P131
P132
P 133

CCLK
VCC
----cO:-,-=T=O-=Oc---------l

P134
P135
P136

GNO
I/O (AO, WS)
-:.'-:-c-----__j
I/O, PGCK4 (Al)

-----~P~13~7:----~r-----~~1/~0--~-~--~

~___

P138

I/O

P139

I/O (CS1, A2)

P140
P141

I/O (A3)
110

Cj

P154
P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176

I/O
I/O
I/O (A6)
I/O (A7)
GNO
VCC
I/O (A8)
I/O (A9)

--

-

P152

--~--~-P-l~1-4-----4~--------1/~0-~----~~

f---

1/0
I/O
110 (A4)
I/O (A5)
I/O
I/O

r------ P153

----------1

P112
Pl13

XC40i0L
GNO

~

~~

I/O
I/O
c--'-'I/O
I/O
I/O (Al0)
I/O (All)
I/O
I/O
GNO
I/O
110
I/O
I/O (A12)
-110 (A13)
I/O
I/O
110 (A14)
I/O, SGCKl (A15)
VCC
~-

~----c

--- f--

~-

3/15/96

PG191 Package Pinouts (see PG223)
The PG191 package pinout has been combined with the
PG223 in a single table, because of their physical compatibility. The PG191 has the same dimensions as the PG223,
but has 32 fewer pins on the inner ring.

P~1~4~2----~--------~I!·=0----------j
______

~L_~

_______ __________

July 30, 1996 (Version 1.03)

~

~

4-145

I

XC4000 Series Field Programmable Gate Arrays

PQ208, HQ208. Package Pinouts

4-146

July 30,. 1996 (Version 1.03)

------~

.~~~-

---- - - -

...

----~--

~:XILINX

I

July 30, 1996 (Version .1,03)

4-147

XC4000 Series Field Programmable Gate Arrays

3/13/96

Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices.

4-148

July 30, 1996 (Version 1.03)

~:XILINX
PG223 and PG191 Package Pinouts
These two packages have been combined into a single table because of their physical compatibility. The PG191 has
the same dimensions as the PG223, but has 32 fewer pins
on the inner ring.
PG
223
Pin

PG
191
Pin

IXC'~OOIIE

PG191

XC4010E XC4013E XC4020E XC4025E
PG191
PG223
PG223
PG223

PG
223
Pin
T3
T4

PG
XC4008E XC4010E XC4013E XC4020E XC4025E
191
PG191
PG191
PG223
PG223
PG223
Pin
I/O
I/O
T3
I/O
110
110
(AO,WS) (AO,WS) (AO,WS) (AO,WS) (AO,WS)
T4

I/O,
SGCK4
(OOUT)

T5

T5

T6

T6

T7

T7

T8

T8

I/O

I/O

I/O

I/O

1/0

T9

T9

I/O (03)

I/O (03)

1/0(03)

I/O (03)

I/O (03)

T10

T10

I/O

I/O

I/O

I/O

I/O

T11

T11

I/O

I/O

I/O

I/O

I/O

T12

T12

GNO

GNO

GNO

GNO

GNO

T13

T13

I/O

I/O

I/O

I/O

I/O

T14

T14

I/O

I/O

I/O

I/O

110

T15

T15

I/O (07)

110(07)

I/O (07)

110(07)

I/O (07)

T16

T16

I/O,
SGCK3

I/O,
SGCK3

110,
SGCK3

I/O,
SGCK3

I/O,
SGCK3

I/O,
SGCK4
(OOUT)

I/O,
SGCK4
(OOUT)

I/O,
SGCK4
(OOUT)

I/O,
SGCK4
(OOUT)

I/O

I/O

I/O

I/O

I/O

I/O

110

I/O

I/O

I/O

GNO

GNO

GNO

GNO

GNO

T17

T17

I/O

I/O

I/O

I/O

I/O

T18

T18

I/O

I/O

110

110

I/O

I/O

I/O

I/O

R1
R2

R2

I/O

I/O

110

I/O

I/O

R3

R3

GNO

GNO

GNO

GNO

GNO

R4

R4

VCC

VCC

VCC

VCC

VCC

R5

110

I/O

I/O

R6

110

I/O

I/O

R7
R8

I/O

I/O

I/O

I/O

I/O

I/O

R9

R9

GNO

GNO

GNO

GNO

GNO

R10

R10

VCC

VCC

VCC

VCC

VCC

I/O

I/O

I/O

~

I/O

I/O

I/O

R13
R14

110

110

110

R11

.

110

110

110

R15

R15

VCC

VCC

VCC

VCC

VCC

R16

R16

GNO

GNO

GNO

GNO

GNO

R17

R17

I/O

I/O

I/O

I/O

110

110

I/O

I/O
I/O

R18 ~.
P1

I/O

I/O

I/O

110

P2

P2

I/O

110

110

I/O

110

P3

P3

I/O

I/O

110

I/O

I/O

P4

I/O

I/O

I/O

P15

I/O

I/O

I/O

P16

P16

I/O

110

I/O

I/O

I/O

P17

P17

I/O

I/O

I/O

I/O

I/O

P18

P18

I/O

I/O

I/O

I/O

I/O

N1

N1

I/O

I/O

I/O

I/O

I/O

110

I/O

110
I/O (A3)

N2IIA',
I/O (A3)
N3
N3

110 (A3)

I/O (A3)

N4

I/O

I/O

I/O

'N15

I/O

110

110

I/O

I/O

--L_I/O

N16

July 30, 1996 (Version 1.03)

N16

I/O

110 (A3)

I/O

4-149

I

XC4000 Series Field Programmable Gate Arrays

~~~,]~C4008E
Pin

PG
223
Pin

XC4010E XC4013E XC4020E XC4025E
PG191
PG223
PG223
PG223

PG
XC4008E XC4010E XC4013E XC4020E XC4025E
191
PG191
PG191
PG223
PG223
PG223
Pin

Pin

PG191

N18

N18

I/O

I/O

Ml

Ml

I/O (A5)

I/O (A5)

I/O (A5)

I/O (A5)

I/O (A5)

F4

I/O

I/O

M2

M2

I/O (A4)

I/O (A4)

1/0(A4)

1/0(A4)

1/0(A4)

F1s

I/O

I/O

I/O

M3

M3

GND

GND

GND

GND

GND

F16

I/O

M4

I/O

I/O

I/O

F17

M15

I/O

I/O

I/O

F18

N17

I/O

I/O

110

F2

I/O

I/O

I/O

F3

I/O
F3

I/O

I/O

I/O (A12) I/O (A12) I/O (A12) I/O (A12) I/O (A12)
I/O

F16

I/O

I/O

I/O

I/O

I/O

I/O

I/O

F18

I/O

I/O

I/O

I/O

I/O
I/O

M16 M16

GND

GND

GND

GND

GND

E1

1::1

I/O

I/O

I/O

I/O

M17 M17

I/O

I/O

I/O

I/O

I/O

E2

E2

I/O

I/O

I/O

110

I/O

M18

M18

I/O

I/O

I/O

I/O

I/O

E3

E3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

L1

L1

I/O

I/O

I/O

I/O

I/O

L2

L2

I/O

I/O

I/O

I/O

I/O

E4
11::15

L3

L3

I/O

I/O

I/O

I/O

I/O

E16

E16 I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC) I/O (HDC)

L4

I/O

I/o

I/O

E17

E17 I/O (LDC) I/O (LDC) I/O (LDG) I/O (LDG) I/O (LDC)

LiS

I/O

I/O

I/O

E18

E18

I/O

I/O

i<

I/O

I/O

I/O

I/O

I/O

I/O

L16

L16

I/O

I/O

I/O

I/O

I/O

Dl

L17

L17

I/O

I/O

I/O

I/O

I/O

D2

D2

L18

L18

I/O

I/O

I/O

I/O

I/O

D3

D3

VCC

VCC

VCC

VCC

VCC

Kl

Kl

I/O

I/O

I/O

I/O

I/O

b4

D4

GND

GND

GND

GND

GND

I/O (A13) I/O (A13) I/O (A13) I/O (A13) 110 (A13)

K2

K2

I/O (A6)

I/O (A6)

I/O (A6)

I/O (A6)

I/O (A6)

D5

I/O

I/O

I/O

K3

K3

I/O (A7)

I/O (A7)

I/O (A7)

I/O (A7)

I/O (A7)

c---oo-

I/O

I/O

I/O

K4

K4

GND

GND

GND

GND

GND

I/O

I/O

I/O

K15

K15

GND

GND

GND

GND

GND

~

i/O

I/O

I/O

K16

K16

I/O

I/O

I/O

I/O

I/O

D9

D9

GND

GND

GND

GND

GND

K17

K17

I/O

I/O

I/O

I/O

I/O

D1D

D1D

VCC

VCC

VCC

VCC

VCC

K18

K18

I/O

I/O

I/O

I/O

I/O

D11

I/O

I/O

Jl

Jl

I/O

I/O

I/O

I/O

I/O

'D12.

I/O
I/O

I/O

110

J2

J2

I/O (A9)

I/O (A9)

I/O (A9)

I/O (A9)

I/O (A9)

'D13

I/O

I/O

J3

J3

110 (A8)

I/O (A8)

I/O (A8)

I/O (A8)

I/O (A8)

~

I/O

J4

J4

VCC

VCC

VCC

VCC

VCC

D15

J15

J15

VCC

VCC

VCC

VCC

VCC

J16

J16 I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT) I/O (INIT)

J17

J17

I/O

I/O

I/O

I/O

I/O

J18

J18

I/O

I/O

I/O

I/O

I/O

D18 OOl!m1l!Ir!'!1I!
Cl
C1

r-w

i

I/O

I/O

I/O

D15

GND

GND

GND

GND

GND

D16

D16

VCC

VCC

VCC

VCC

VCC

D17

D17

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

H1

Hl

I/O

I/O

I/O

I/O

I/O

C2

C2

H2

H2

I/O

I/O

I/O

I/O

I/O

C3

C3

H3

H3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

C4

C4

C5

C5

I/O

I/O

I/O

I/O

I/O

C6

C6

I/O

I/O

I/O

I/O

I/O

C7

C7

GND

GND

GND

GND

GND

C8

C8

I/O

I/O

I/O

I/O

I/O

C9

C9

I/O

I/O

I/O

I/O

I/O

C1D

C1D

I/O

I/O

I/O

I/O

C11

C11

I/O

I/O

I/O

I/O

C12

C12

GND

GND

GND

GND

C13

C13

I/O

I/O

I/O

I/O

C14

C14

I/O

I/O

I/O

110

I/O

C15

C15

o (M1)

0{M1)

o (M1)

o (M1)

o (Ml)

C16

C16.

I (M2)

H4

i=it5

I

H16

H16

I/O

I/O

I/O

I/O

I/O

H17

H17

I/O

I/O

I/O

I/O

I/O

H18

H18

I/O

I/O

I/O

I/O

I/O

G1

G1

I/O (A1D) I/O (A1D) I/O (A1D) I/O (A1D) I/O (A10)

G2

G2

I/O (A11) ! I/O (A11) I/O (A11) I/O (A11) I/O (A11)

G3

G3

G4

G15

GND

G16

G16

GND

G17

G17

I/O

.Gi8
F1

4-150

G18

I/O

Fl

I/O

GND

I

I

GND

GND

GND

I/O

I/O

I/O

I/O

I/O

I/O

GND

GND

GND

GND

I/O

I/O

I/O

I/O
I/O-~

I/O

I/O

I/O

I/O

I/O

I/O

I

I/O

I/O (A14) I/O (A14) I/O (A14) I/O (A14) I/O (A14)
I/O,
PGCKl
(A16)

I/O,
PGCK1
(A16)

1/0,
PGCK1
(A16)

I/O,
PGCK1
(A16)

I/O,
PGCKl
(A16)

I/O (A17) I/O (A17) I/O (A17) 1/0 (A17) I/O (A17)

I

I (M2)

1(~I(M2)

I/O
I/O
GND-I/O

I (M2)

July 30, 1996 (Version 1.03)

~:XIUNX
PG
223

PG
IXC40CI8E XC4010E XC4013E XC4020E XC4025E
191
PG191
PG191
PG223
PG223
PG223

Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by different devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

I

2/28/96

July 30, 1996 (Version 1.03)

4-151

XC4000 Series Field Programmable Gate Arrays

BG225 Package Pinouts
BG225 Pin
Ri
R2
R3
R4
R5
R6
R7
RB
R9

XC4010E
VCC
I/O, PGCK2
I/O
I/O
I/O
I/O
I/O
VCC
I/O

XC4013E1L
VCC
I/O, PGCK2
I/O
I/O
I/O
I/O
I/O
VCC
I/O

Rii
Ri2
Ri3
Ri4
Ri5
Pi
P2
P3
P4

I/O
I/O
I/O
I/O
VCC
I/O, SCGK2
I (MO)
I/O (HOC)
I/O ([[)C)

I/O
I/O
I/O
I/O
VCC
I/O, SCGK2
I (MO)
I/O (HOC)
I/O ([[)C)

P6

I/O

I/O

PB
P9

I/O (INIT)
I/O

I/O (lNIT)
110

Pii
Pi2
Pi3
Pi4
Pi5
Ni
N2
N3
N4
N5
N6

I/O
I/O
I/O
OONE
I/O (07)
110
110
O(Mi)
I/O
110
110

I/O
I/O
I/O
OONE
1/0(07)
I/O
I/O
O(Mi)
110
I/O
I/O

NB
N9
Ni0

I/O
I/O
I/O

I/O
I/O
I/O

-

I

""I1i!iki,iHis ,

Ni2
Ni3
Ni4

II
II
II

Mi
M2
M3
M4

d
I
4-152

I/O
I/O
I/O
I (M2)
I/O
I/O
I/O
GNO
I/O

M6
M7
MB
M9
Mi1
Mi2
Mi3

I/O
110, SGCK3
JI9,-PGCK3

I

I/O
PROGRAM
I/O

,

110
I/O, SGCK3
1/(),PGCK3
I/O
I/O
I/O
I
I (M2)
110
I/O - -

'-----I

I/O
GNO
I/O
I/O
PROGRAM
I/O

July 30, 1996 (Version 1.03)

~XILINX
BG225 Pin
014
015
Cl
C2
C3

XC4010E
1/0
1/0
1/0, TCK
1/0
I/O, SGCKl (A 15)

XC4013E1L
1/0
1/0
1/0, TCK
1/0
1/0, SGCKl (A15)

C5

1/0

1/0

C7
C8
C9

1/0
1/0 (A6)
1/0

1/0
1/0 (A6)
1/0

Cll
C12
C13
C14
C15

1/0
I/O
CCLK
1/0
1/0 (RCLK,
ROY/BUSY)
1/0 (A17)
VCC
1/0
1/0 (A12)
1/0
1/0 (All)
1/0 (A9)
I/O (A7)
1/0

Bl
B2
B3
B4
B5
B6
B7
B8
B9

I

Bll
B12
B13
B14
B15
Al
A2
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15

1/0
I/O
CCLK
1/0
1/0 (RCLK,
ROY/BUSY)
1/0 (A17)
VCC
1/0
1/0 (A12)
1/0 ---'----1/0 (All)
1/0 (A9)
1/0 (A7)
1/0

I
I

1/0
I/O
1/0 ( A 3 ) 1/0 (A3)
1/0, PGCK4 (Al)
1/0, PGCK4 (Al)
VCC
VCC
1/0, SGCK4 (OOUT) 110, SGCK4 (OOUT)
GNO
GNO
I
1/0 (A14)
I/0jAl_4)
1/0
1/0
1/0 (Al0)
1/0
GNO
1/0
1/0(A4)
1/0
1/0
I/O (CS1, A2)
I/O(AO, WS)
O,TOO

1/0
1/0
1/0 (Al0)
1/0
GNO
-1/0
1/0 (A4)
1/0
1/0
I/O (CS1, A2)
I/O (AO,WS)
0, TOO

2/28/96

Note: Shaded pins should be taken into account when
designing PC boards, in case of future replacement by different devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

July 30, 1996 (Version 1..03)

4-153

XC4000 Series Field Programmable Gate Arrays

PQ240, HQ240 Package Pinouts

4-154

July 30, 1996 (Version 1.03)

~XILINX

I

July 30, 1996 (Version 1.03)

4-155

XC4000 Series Field Programmable Gate Arrays

3/11/96

t Pins labelled GNDt should be connected to Ground if
possible; however, they can be left unconnected if necessary for compatibility with other devices. Pins labelled
N.C.t are reserved for Ground connections on future revisions of the device. These pins do not physically connect
to anything on the current device revision. However, they
should be externally connected to Ground if possible.
Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices.

4-156

July 30, 1996 (Version 1.03)

~XIUNX
PG299 Package Pinouts
PG299 Pin

XC4025E

XC4028EXlXL

X1

I/O, SGCK4 (OOUT)

I/O, GCK6 (OOUT)

X2

GNO

GNO

X3

110

I/O

X4

I/O

I/O

X5

VCC

VCC

X6

GNO

GNO

X7

I/O

I/O

X8

I/O

I/O

X9

I/O

I/O

X10

VCC

VCC

X11

GNO

GNO

X12

I/O

110

X13

I/O

I/O

X14

I/O (CSO)

I/O (CSO)

X15

VCC

VCC

X16

GNO

GNO

X17

110
110

I/O

X18
X19

VCC

VCC

X20

I/O, SGCK3

I/O, GCK4

VCC

VCC

W2

I/O (AO, WS)

I/O (AO, WS)

W3

I/O

I/O

W4

I/O

I/O

W5

I/O

I/O

W6

I/O

W7

I/O

W8

I/O (02)

~

I/O

110,

FCLK4

I/O (02)

W9

I/O

I/O

W10

I/O (03)

I/O (03)

W11

I/O

I/O

W12

I/O

I/O

W13

I/O

110

W14

I/O

I/O, FCLK3

W15

I/O

I/O

W16

I/O

I/O

W17

110(06)

110 (06)

W18

I/O, PGCK3

I/O, GCK5

W19

I/O (07)

I/O (07)

W20

GNO

GNO

V1

I/O (A3)

I/O (A3)

V2

I/O, PGCK4 (A1)

I/O, GCK7 (A 1)

V3

CCLK

CCLK

XC4025E

XC4028EXlXL

V11

1/0(04)

1/0(04)

V12

I/O

110

V13

I/O

I/O

V14

I/O

I/O

V15

I/O

I/O
I/O

V16

I/O

V17

I/O

I/O

V18

DONE

DONE

V19

I/O

I/O

V20

110

I/O

U1

I/O

I/O

U2

I/O

I/O

U3

I/O (CS1, A2)

I/O (CS1, A2)

U4

0, TOO

0, TOO

U5

I/O

I/O

U6

I/O (01)

I/O (01)

U7

110

I/O

U8

I/O

I/O

U9

I/O

I/O

U10

I/O

U11

110
110

U12

I/O

I/O

U13

I/O

I/O

U14

I/O

I/O

U15

I/O

I/O

U16

I/O

I/O

U17

PROGRAM

PROGRAM
I/O

U18

110

U19

I/O

I/O

U20

110

I/O

T1

GNO

GNO

T2

I/O

110

T3

I/O

I/O

T4

110

I/O

T5

GNO

GNO

T6

I/O

I/O

T7

I/O

I/O

T8

I/O

I/O

T9

I/O

I/O

T10

I/O

I/O

T11

110

I/O

T12

I/O (05)

I/O (05)

T13

110

I/O

T14

I/O

I/O

T15

I/O

I/O

T16

VCC

VCC
I/O

f----- .. ~

110

(DO, DIN)

I/O (DO, DIN)

V5

I/O (RCLK,
ROY/BUSY)

I/O (RCLK,
ROY/BUSY)

T17

110

V6

I/O

110

T18

I/O

I/O

V7

I/O

I/O

T19

I/O

110

V8

110
110
110 (RS)

I/O

T20

VCC

VCC

I/O

R1

VCC

VCC

I/O (RS)

R2

I/O

I/O

V10

July 30, 1996 (Version 1.03)

I

I/O

V4

V9
-

I/O

PG299 Pin

4-157

XC4000 Series Field Programmable Gate Arrays
PG299 Pin

XC4025E

XC4028EXlXL

R3

I/O

I/O

PG299 Pin

XC4025E

XC4028EXlXL

R4

I/O

R5

I/O

110

K16

I/O

I/O

K17

I/O

110
110

R16

I/O

I/O

R17

I/O

I/O

R18

110

R19

I/O

R20
Pl

K18

I/O

I/O

K19

I/O (INIT)

110 (INIT)

110
110

K20

GND

Jl

I/O

GND
,I/O

GND

GND

J2

I/O

I/O

I/O

I/O

I/O

I/O

P3

I/O

JS

P4

110
110

I/O

J16

PS

I/O

I/O

J17

110 (All)
110
110
110
110

I/O (All)

P2

J3
J4

P16

I/O

I/O

J18

I/O

I/O

P17

I/O

I/O

J19

I/O

I/O

P18

I/O

I/O

J20

I/O

I/O

P19

110

I/O

P20

I/O

I/O

-

I/O
I/O
I/O
I/O

Hl

I/O (Al0)

I/O (Al0)

H2

I/O

I/O

~-

Nl

I/O (A4)

I/O (A4)

H3

I/O

I/O

N2

I/O

I/O

H4

I/O

N3

I/O

I/O

HS

I/O

I/O
1/0

N4

I/O

I/O

H16

1/0

1/0

NS

I/O

I/O

H17

I/O

N16

I/O

I/O

H18

I/O

110
110

N17

I/O

I/O

H19

I/O

1/0

N18

I/O

I/O

H2O

I/O

N19

I/O

I/O

Gl

1/0

1/0
1/0

N20

I/O

110

G2

I/O

1/0

G3

I/O

I/O

M2

I/O

I/O

G4

1/0

I/O

M3

I/O (AS)

I/O (AS)

1/0 (A12)
1/0

I/O (A12)
I/O
1/0

M4

I/O

I/O

GS
G16

MS

I/O

I/O

G17

1/0

M16

I/O

I/O

G18

I/O

M17

I/O

I/O

G19

M18

I/O

I/O

G20

I/O
1/0

M19

I/O

I/O

Fl

GND

M20

110

I/O

F2

1/0

I/O

U

GND

GND

F3

110

1/0

L2

I/O (A7)

I/O (A7)

F4

I/O

I/O

L3

I/O (A6)

I/O (A6)

FS

I/O

I/O

F16

110

1/0
1/0

I

I/O

I/O

1/0
GND

L5

I/O

110

F17

1/0

L16

I/O

I/O

F18

110

1/0

U7

I/O

I/O

F19

1/0

1/0

U8

I/O

I/O

F20

L19

I/O

I/O

El
E2

I/O

I/O

Kl

vee
vee

vee
vee

L20

vee
vee

vee
vee

E3

I/O

1/0

K2

I/O (A8)

I/O (A8)

E4

1/0

K3

I/O (A9)

I/O (A9)

ES

vee

vee

E6

I/O

110

4-158

"

1/0

July 30, 1996 (Version 1 ,03)

~XILINX
PG299 Pin

XC4025E

XC4028EXlXL

PG299 Pin

XC4025E

XC4028EXlXL

E7

I/O

I/O

C19

I/O (HDC)

I/O (HDC)

E8

I/O

I/O

C20

I/O (LOC)

I/O (LDC)

E9

I/O

I/O

B1

GND

GND

E10

I/O

I/O

B2

I/O (A17)

I/O (A17)

E11

I/O

I/O

B3

I/O

I/O

E12

I/O

I/O

B4

I/O

I/O

E13

I/O

I/O

B5

I/O

I/O

E14

I/O

I/O

B6

I/O

I/O, FCLK1
I/O

E15

I/O

I/O

B7

I/O

E16

GND

GND

B8

I/O

I/O

E17

I/O

I/O

B9

I/O

1/0

E18

I/O

I/O

B10

I/O

I/O

E19

I/O

I/O

B11

I/O

I/O

E20

GND

GND

B12

1/0

I/O

D1

I/O

I/O

B13

I/O

I/O

D2

I/O

I/O

B14

1/0

I/O

D3

I/O (A14)

I/O (A14)

B15

I/O

I/O

D4

I/O, PGCK1 (A16)

I/O, GCK1 (A16)

B16

I/O

I/O

D5

I/O, TDI

I/O, TDI

B17

I/O

I/O

D6

I/O

I/O

B18

I/O

I/O

D7

110

I/O

B19

I/O, PGCK2

I/O, GCK3

D8

I/O

I/O

B20

VCC

VCC

D9

I/O

I/O

A2

VCC

VCC

D10

I/O

I/O

A3

I/O

I/O

D11

I/O

I/O

A4

I/O

I/O

D12

I/O

I/O

A5

GND

GND

D13

I/O

I/O, FCLK2

A6

VCC

VCC

D14

I/O

I/O

A7

I/O

I/O

D15

I/O

I/O

A8

I/O

I/O

D16

I/O

I/O

A9

I/O

I/O

D17

I (M2)

I (M2)

A10

GND

GND

D18

I/O

I/O

A11

VCC

VCC

D19

I/O

I/O

A12

1/0

1/0

D20

I/O

I/O

A13

I/O

I/O

C1

I/O (A13)

I/O (A13)

A14

1/0

I/O

C2

I/O

I/O

A15

GND

GND

C3

1/0, SGCK1 (A15)

I/O, GCK8 (A15)

A16

VCC

VCC
I/O

.

C4

I/O, TCK

I/O, TCK

A17

I/O

C5

I/O

I/O

A18

I/O

I/O

C6

I/O

I/O

A19

GND

GND

C7

I/O, TMS

I/O, TMS

A20

0(M1)

o (M1)

C8

I/O

I/O

C9

I/O

I/O

C10

I/O

I/O

C11

I/O

I/O

C12

1/0

I/O

C13

I/O

C14

I/O

1/0
1/0

C15

I/O

I/O

C16

I/O

1/0

C17

I/O, SGCK2

I/O, GCK2

C1S

I (MO)

I (MO)

July 30, 1996. (Version 1.03)

I

~-

3/18/96

Note: .Shaded pins should be taken into account when designing PC boards, incase of future replacement by different devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

4-159

XC4000 Series Field Programmable Gate Arrays

HQ304 Package Pinouts
HQ304
Pin

XC4025E

XC4028EX
XC4028Xl

HQ304
Pin
XC4036EX
XC4036Xl

XC4028EX
XC4028Xl

XC4036EX
XC4036Xl

P51

I/O

I/O

I/O

P52

VCC

VCC

P53
P54

N.C.
I/O

N.C.
I/O

VCC
N.C.

P55

I/O

I/O

I/O

P56

I/O

I/O

I/O

P57

I/O

I/O

P58
P59

GND

GND
I/O

I/O
GND

P60

I/O
I/O

P61

I/O

I/O

I/O

I/O

I/O

I/O

I/O

P62

I/O

110

I/O

P63

I/O

I/O

I/O

P64
P65

I/O

I/O
I/O

P66

I/O

P67

I/O

P68

I/O
If0 (A3)
1/0 (CS1, A2)

1/0
I/O
I/O
I/O
If0
1/0 (A3)
I/O (CS1, A2)
1/0
1/0
I/O, GCK7 (A1)
1/0 (AO, WS)
GND
O,TDO
VCC
CClK
1/0, GCK6
(DOUT)
1/0 (DO, DIN)
I/O
1/0
I/O
I/O
I/O (RClK,
ROY/BUSY)
1/0 (D1)
I/O
1/0

P69
P70

I/O

P71

110

P72

P80

1/0
1/0, PGCK4 (A1)
1/0 (AO, WS)
GND
O,TDO
VCC
CClK
1/0, SGCK4
(DOUT)
1/0 (DO, DIN)

P81

110

P82

1/0
1/0
1/0
1/0 (RClK,
ROY/BUSY)
I/O (01)
I/O
1/0
I/O
1/0
I/O
1/0
1/0
1/0
GND
1/0
1/0
1/0
1/0
N.C.
VCC

P73
P74
P75
P76
P77
P78
P79

P83
P84
P85
P86
P87
P88
P89
P90
P91
P92
P93
P94
P95
P96
P97
P98
P99
P100
P101

4-160

XC4025E

110
1/0
1/0
I/O
1/0
1/0
GND

1/0
1/0
1/0, FClK4
1/0
N.C.
VCC

I/O
I/O
I/O

1/0 (A3)
1/0 (CS1, A2)
1/0
1/0
1/0, GCK7 (A 1)
1/0 (AO, WS)
GND
0, TDO
VCC
CClK
1/0, GCK6
(DOUT)
1/0 (DO, DIN)
I/O
1/0
1/0
1/0
1/0 (RClK,
ROY/BUSY)
1/0 (D1)

110
1/0
1/0
I/O
1/0
1/0
1/0
I/O
GNO
1/0
1/0
1/0, FClK4

110
N.C.
VCC

July 30, 1996 (Version 1.03)

---~--~-----

~---

--

-------~-~~~~---~~

-~--

~XILlNX
HQ304
Pin

P102
P103
P104
P105
P106
P107
P108
P109
P110
P111
P112
P113
P114
P115
P116
P117
P118
P119
P120
P121
P122
P123
P124
P125
P126
P127
P128
P129
P130
P131
P132
P133
P134
P135
P136
P137
P138
P139
P140
P141
P142
P143
P144
P145
P146
P147
P148
P149
P150
P151
P152
P153
P154

--

XC4025E

1/0

1/0(02)
I/O
I/O
1/0
1/0
1/0

I/O
1/0
1/0
1/0 (RS)
1/0 (03)

GNO
VCC
I/O
I/O (04)
I/O
1/0
1/0
1/0
1/0
1/0
1/0
1/0

XC4028EX
XC4028XL

XC4036EX
XC4036XL

HQ304
Pin

1/0
1/0 (02)
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0 (02)
1/0
1/0
1/0
1/0
1/0
1/0

I/O (RS)
1/0 (03)

1/0 (RS)
1/0 (03)

GNO
VCC

GNO
VCC

1/0

1/0
1/0 (04)

P155
P156
P157
P158
P159
P160
P161
P162
P163
P164
P165
P166
P167
P168
P169
P170
P171
P172
P173
P174
P175
P176
P177
P178
P179
P180
P181
P182
P183
P184
P185
P186
P187
P188
P189
P190
P191
P192
P193
P194
P195
P196
P197
P198
P199
P200
P201
P202
P203
P204
P205
P206
P207

I/O
1/0

---

1/0(04)
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0
1/0
1/0

1/0 (05)

1/0
1/0 (CSO)
1/0 (05)

1/0 (CSO)
1/0 (05)

N.C.
VCC

N.C.
VCC

N.C.
VCC

1/0
1/0
1/0
1/0

1/0
1/0, FCLK3
1/0
1/0

1/0
1/0, FCLK3
1/0
1/0

GNO

GNO

GNO

1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (06)
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 (06)
1/0
1/0
1/0
1/0
1/0

I/O (CSO)

1/0
1/0
1/0
1/0
1/0
1/0 (06)

I/O
1/0
1/0
1/0
1/0
1/0
1/0, PGCK3
1/0 (07)

PROGRAM
VCC
OONE
GNO

July 30, 1996 (Version -1.03)

I

I/O
1/0
1/0
1/0

I/O
1/0, GCK5
1/0 (07)

PROGRAM
VCC
DONE
GND

I

I/O
1/0, GCK5
110 (D7)
PROGRAM
VCC
OONE
GNO

I
I

I

i
!

XC4028EX
XC4028XL

XC4036EX
XC4036XL

1/0, GCK4
1/0
1/0
-1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0, GCK4
1/0
1/0
1/0
1/0

GND

GNO

1/0
1/0
1/0

1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0

N.C.
VCC

N.C.
VCC

N.C.
VCC

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0

I/O

I/O
I/O

1/0

1/0
1/0

1/0
1/0

1/0
1/0
1/0
1/0
1/0

GNO
VCC
1/0 (INIT)

GNO
VCC
1/0 (INIT)

GND
VCC
1/0 (INIT)

1/0
1/0
1/0
1/0

1/0
1/0
110
1/0

I/O

110
1/0

1/0
1/0
1/0
1/0
1/0

XC4025E

I/O, SGCK3
1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0

GNO
I/O

1/0

I/O

I/O

1/0
1/0
1/0
1/0

I/O
1/0
1/0
1/0

I/O
1/0
1/0

I/O
I/O
I/O~

1/0
1/0

I/O

I/O
1/0

1/0
1/0

1/0
1/0
1/0
1/0
1/0

VCC
N.C.

VCC
N.C.

VCC
N.C.

1/0
1/0

1/0
1/0

1/0

1/0

I/O

I

]

I

I

I/O~
1/0
1/0
1/0

I/O
4-161

XC4000 Series Field Programmable Gate Arrays

HQ304
Pin

XC4025E

XC4028EX
XC4028XL

XC4036EX
XC4036XL

HQ304
Pin

P208

I/O

I/O

I/O

I/O

I/O

I/O

P261
P262

I/O

P209
P210
P211

GND
I/O

GND
I/O

GND
I/O

P263
P264

I/O
I/O

XC4025E

I/O

P212

I/O

I/O

I/O

P265

I/O

P213

I/O

I/O

I/O

P266

I/O

P214

I/O

I/O

I/O

P267

VCC

P215

I/O

I/O

P268

GND

P216

I/O
I/O

I/O

P217

I/O

I/O
I/O

P269
P270

I/O
I/O

P218

I/O

I/O
I/O

P219

I/O

P220
P221

1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C.
VCC
I/O
I/O, TMS
I/O
1/0
GND
1/0
I/O
1/0
1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O, TCK
I/O,TDI
I/O
I/O
I/O (A17)
I/O, PGCK1
(A16)
GND

I/O

P271

I/O

P272

I/O

I/O
I/O

I/O

P273

I/O (LDC)

I/O (LDC)

I/O (LDC)

P222

I/O

I/O

P274
P275

P223

I/O

I/O
I/O

I/O
I/O (HDC)

I/O
I/O (HDC)

I/O
I/O

P276

P224

I/O (HDC)

P278

P226
P227

I/O, PGCK2

I/O, GCK3

I/O, GCK3

P279

I (M2)

I (M2)

I (M2)

P280

P228

VCC

VCC

VCC

P281

P229

I (MO)

I (MO)

I (MO)

P282

P225

P277

P230

GND

GND

GND

P283

P231

0(M1)

o (M1)

o (M1)

P284

P232

I/O, SGCK2
I/O

I/O, GCK2
I/O

1/0,GCK2
I/O

P285
P286
P287

P233
P234

I/O

I/O

I/O

P235
P236

I/O

I/O

I/O

P288

I/O

I/O

P289

P237
P238

I/O
I/O

I/O
I/O

I/O
I/O
I/O

P239
P240

I/O

I/O

I/O

P292

I/O

I/O

I/O

P293

I/O
I/O

I/O

P243

I/O

I/O

P244
P245

I/O
I/O

I/O
I/O

P246
P247

I/O
I/O

I/O

P248

GND

P249
P250

I/O
I/O

P251

I/O

I/O
1/0
1/0
I/O
I/O
I/O
I/O
GND
I/O, FCLK2
I/O
I/O
I/O
VCC
N.C.
I/O
I/O
I/O
I/O
I/O
1/0

P294

P242

P241

I/O

I/O
GND
I/O, FCLK2
I/O
I/O

P252

I/O

1/0

P253
P254

VCC

VCC
N.C.

P255
P256
P257
P258
P259
P260

4-162

N.C.
I/O

1/0
I/O
I/O
I/O
1/0

1/0
1/0
I/O
I/O
I/O
1/0

P290
P291

P295
P296
P297
P298
P299
P300
P301
P302
P303
P304

XC4028EX
XC4028XL

XC4036EX
XC4036XL

1/0
I/O
I/O
I/O
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C.
VCC
I/O
1/0, TMS
I/O
I/O, FCLK1
GND
I/O
1/0
I/O
1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O, TCK
I/O, TDI
I/O
I/O
I/O (A17)
I/O, GCK1
(A16)
GND

1/0
I/O
I/O
1/0
I/O
I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C.
VCC
I/O
I/O, TMS
I/O
I/O, FCLK1
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
1/0
I/O
1/0
I/O, TCK
I/O, TDI
1/0
I/O
I/O (A17)
I/O, GCK1
(A16)
GND

3/20/96

Note: Shaded pins should be taken into account when designing PC boards, in case of future replacement by different devices.

July 30, 1996 (Version 1.03)

~XILINX
BG352 Package Pinouts
BG352 Pin
AF1
AF2
AF3
AF4
AF5
AF6
AF7
AF8
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
A01
A02
A03
A04
A05
A06

July 30, 1996 (Version 1.03)

XC4028EXlXL
GNO
GNO
I/O
I/O
GNO
I/O
I/O
GNO
I/O
VCC
I/O
I/O
GNO
I/O (INIT)
I/O
I/O
VCC
I/O
GNO
I/O
I/O
GNO
I/O
I/O
GNO
GNO
GNO
VCC
I/O
N.C.
I/O
I/O
I/O
I/O
I/O
N.C.
I/O
i/O
1/0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (iJ5C)
I/O, GCK3
VCC
GNO
I/O
I/O (07)
OONE
I/O
I/O
I/O

BG352 Pin
A07
A08
A09
A010
A011
A012
A013
A014
A015
A016
A017
A018
A019
A020
A021
A022
A023
1----A024
A025
A026
AC1
AC2
AC3
AC4
AC5
AC6
AC7
AC8
AC9
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
AC21
AC22
AC23
AC24
AC25
AC26
AB1
AB2.
AB3
1----AB4
AB23
AB24
AB25
AB26
AA1
AA2
AA3
AA4
AA23
AA24

XC4028EXlXL
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C.
I/O
I/O
I/O
I/O
N.C.
I/O
I/O (HOC)
I (MO)
I/O
N.C.
I/O
N.C.
I/O, GCK5
PROGRAM
I/O, GCK4
N.C.
I/O
VCC
I/O
I/O
N.C.
I/O
I/O
VCC
I/O
N.C.
I/O
I/O
I/O
VCC
N.C.
I/O
I (M2)
I/O, GCK2
N.C.
I/O
GNO
I/O
N.C.
I/O
0(M1)
I/O
I/O
GNO
I/O
I/O
I/O
I/O
I/O
I/O

I

4-163

XC4000 Series Field Programmable Gate Arrays

-

4-164

BG352 Pin
AA25
AA26
Y1
Y2
Y3
Y4
Y23
Y24
Y25
Y26
W1
W2
W3
W4
W23
W24
W25
W26
V1
V2
V3
V4
V23
V24
V25
V26
U1
U2
U3
U4
U23
U24
U25
U26
T1
T2
T3
T4
T23
T24
T25
T26
R1
R2
R3
R4
R23
R24
R25
R26
P1
P2
P3
P4
P23
P24
P25
P26
N1
N2

XC4028EXlXL
I/O
I/O
I/O
I/O
I/O (06)
VCC
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
VCC
I/O
I/O
GNO
I/O (CSO)
I/O (05)
I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O, FCLK3
I/O, FCLK2
I/O
N.C.
VCC
I/O
I/O
N.C.
N.C.
I/O
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O (04)
I/O
VCC
I/O
I/O
I/O
GNO
GNO
I/O (03)

-~

-

BG352 Pin
N3
N4
N23
N24
N25
---N26
M1
M2
M3
M4
M23
M24
M25
M26
L1
L2
L3
L4
L23
L24
L25
L26
K1
K2
K3
K4
K23
K24
K25
K26
J1
J2
J3
J4
J23
J24
J25
J26
H1
H2
H3
H4
H23
H24
H25
H26
G1
G2
G3
G4
G23
G24
G25
G26
F1
F2
F3
F4
F23
F24

XC4028EXlXL
I/O
I/O (RS)
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N.C.
N.C.
I/O
I/O
I/O
VCC
N.C.
I/O
I/O
I/O
I/O
I/O
VCC
I/O (02)
I/O
I/O, FCLK4
I/O
I/O, FCLK1
I/O
I/O
N.C.
GNO
I/O
I/O
VCC
I/O
I/O
I/O, TMS
GNO
I/O
I/O
I/O
I/O (RCLK, ROY/BUSY)
VCC
I/O
I/O
I/O
I/O
I/O
I/O (01)
I/O
N.C.
I/O

July 30, 1996 (Version 1.03)

~XILINX
BG352 Pin
F25
F26
E1
E2
E3
E4
E23
E24
E25
E26
01
02
03
04
05
06
07
08
09
010
011
012
013
014
D15
016
017
018
019
020
021
022
023
024
025
026
C1
C2
C3

c4
C5
86
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24

July 30, 1996 (Version 1.03)

XC4028EXlXL
I/O
110
GNO
I/O
I/O
I/O, GCK6 (OOUT)
I/O
I/O, TCK
I/O
GNO
N.C.
I/O
I/O (00, OIN)
(TOO)
I/O
I/O (C81, A2)
VCC
I/O
I/O
I/O
110
I/O (A4)
VCC
I/O (A8)
I/O
N.C.
I/O
I/O
VCC
I/O
I/O
I/O (A14)
I/O, GCK1 (A16)
I/O
N.C.
I/O
N.C.
I/O
CCLK
110, GCK7 (A1)
N.C.
I/O (A3)
I/O
N.C.
I/O
I/O
N.C.
I/O (A5)
I/O (A21)
I/O (A9)
I/O
I/O
I/O
I/O
I/O
I/O
I/O (A13)
I/O
I/O
I/O, GCK8 (A15)

BG352 Pin
C25
C26
81
82
83
84
85
86
87
88
89
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
At8
A19
A20
A21
A22
A23
A24
A25
A26

o

XC4028EXlXL
I/O (A17)
I/O, TOI
GNO
VCC
I/O (AO, W8)
N.C.
I/O
I/O
I/O
I/O
I/O
N.C.
110
I/O
I/O (A20)
I/O (A7)
I/O (A18)
I/O (A11)
I/O
I/O
I/O
I/O
I/O
I/O (A12)
N.C.
I/O
VCC
GNO
GNO
GNO
I/O
I/O
GNO
I/O
I/O
GNO
I/O
VCC
I/O
I/O
110 (A6)
GNO
I/O (A19)
110 (A10)
VCC
N.C.
GNO
I/O
I/O
GNO
I/O
N.C.
GNO
GNO

I

2/28/96

Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from .the top side, the pins start at the top row and
go from the right edge to the left edge.

4-165

XC4000 Series Field Programmable Gate Arrays

PG411 Package Pinouts

4-166

July 30, 1996 (Version 1.03)

~:XILINX

I

July 30, 1996 (Version 1.03)

4-167

XC4000 Series Field Programmable Gate Arrays

4-168

July 30, 1996 (Version 1.03)

~XILINX
PG411 Pin

XC4036EXlXL

XC4044EXlXL

C33

N.C.

N.C.

C35

1/0

110

C37

1/0 (HDC)

1/0 (HDC)

C39

VCC

VCC

B2

1/0, TDI

B4

1/0, TDI
1/0

B6

N.C.

N.C.

110

B8

1/0

110

B10

I/O

1/0

B12

1/0

I/O

B14

I/O

I/O

B16

I/O

I/O

B18

110

110

B20

I/O

I/O

B22

I/O

I/O

B24

110

I/O

B26

I/O

I/O

B28

I/O

I/O

B30

I/O

110

B32

I/O

I/O

B34

N.C.

N.C.

B36

I/O, GCK2

I/O, GCK2

B38

I/O

I/O

A3

VCC

VCC

A5

I/O

110

A7

I/O

110

A9

GND

GND

A11

VCC

VCC

A13

N.C.

N.C.

A15

I/O

I/O

A17

I/O

I/O

A19

GND

GND

A21

VCC

VCC

A23

I/O

I/O

A25

I/O

I/O

A27

I/O

110

A29

GND

GND

A31

VCC

VCC

A33

I/O

110

A35

110

I/O

A37

GND

GND

A39

0(M1)

0(M1)

I

3/26/96

Note: Shaded pins Should be taken into account when designing PC boards, in case of future replacement by different devices.
Note: Viewed from the bottom side, the package pins start
at the top row and go from the left edge to the right edge.
Viewed from the top side, the pins start at the top row and
go from the right edge to the left edge.

July 30, 1996 (Version 1.03)

4-169

XC4000 Series Field Programmable Gate Arrays

BG432 Package Pinouts
BG432 Pin

AL1
AL2
AL3
AL4
AL5
AL6
AL7
AL8
AL9
AL10
AL11
AL12
AL13
AL14
1

XC4036EX
XC4036XL
VCC
GND
GND

XC4044EX
XC4044XL
VCC
GND
GND

XC4052XL

1/0
1/0
1/0

1/0
1/0
1/0

1/0
1/0
1/0

GND

GND

1/0

1/0

GND

GND

BG432 Pin

XC4036EX
XC4036XL

XC4044EX
XC4044XL

AK25
AK26

1/0
1/0

1/0
1/0

AK28
AK29
AK30
AK31
AJ1
AJ2
AJ3
AJ4

1/0

1/0

1/0, GCK3

1/0, GCK3

1/0
1/0, GCK3

GND
GND
GND
110 (D7)
VCC
1/0, GCK4

GND
GND
GND
1/0 (D7)
VCC
1/0, GCK4

GND
GND
GND
1/0 (D7)
VCC
1/0, GCK4

AJ6
AJ7

1/0
1/0

1/0

1/0
1/0

AJ9
AJ10
AJ11

1/0

1/0
1/0
1/0

AJ13
AJ14

1/0
1/0

110

AJ16
AJ17
AJ18
AJ19

1/0
1/0

1/0
1/0

1/0

I/O
I/O

I/O

110

1/0

I/O

I/O
I/O
I/O

110

VCC
GND
GND

GND

1/0

GND

1/0

1/0

1/0

VCC

VCC

1/0
1/0

1/0
1/0

1/0
1/0

GND

GND

GND

1/0

1/0

1/0

AL18
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL27
AL28
AL29
AL30
AL31
AK1
AK2
AK3
AK4
AK5
AK6
AK7
AK8
AK9
AK10

GND

GND

GND

1/0
1/0

1/0
1/0

1/0
1/0

VCC

VCC

VCC

1/0

1/0

1/0

GND

GND

GND

1/0

1/0

1/0

GND

GND

GND

1/0
1/0
1/0

1/0
1/0
1/0

1/0
1/0
1/0

GND
GND
VCC
GND
GND

GND
GND
VCC
GND
GND

GND
GND
VCC
GND
GND

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0 (INIT)

1/0
1/0
1/0
1/0
1/0 (TNiT)

1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0
1/0
1/0
1/0

<
I

=x

I

~

I-~®

Versa-

~ 1--+.. ®

'V/I:

@)

~I'

• Single-length Lines

=>eX Double-length Lines

3
4

~HTJG~~

V,

VersaVersa-+-+X-+++I BIOCkjl--t-XI-4-f-+1 BIOCk

I

1-1-

I-o-I~""'J_"-~...... f.i\

GR~ ~ "- ~~ GR~

1-/ "- ... :

r~

f-7ii

~

VersaBlock 1--1-...

I _++--..
-+-I--+-+-f_

I

I

I

Direct Connects
~

~

LIM

6

Longlines and Global Lines
Local Interconnect Matrix
Logic Cell Feedthrough
Path (Contained within each
Logic Cell)
Direct Connects

X4963

Figure 11: XC5200 Interconnect Structure

August 6, 1996 (Version 4.01)

4-195

XC5200 Field Programmable Gate Arrays

The global lines provide direct input only to the CLB clock
pins. The global lines also connect to the General Routing
Matrix to provide access from these lines to the function
generators and other control signals.
Four clock input pads at the corners of the chip, as shown in
Figure 12, provide a high-speed, low-skew clock network to
each of the four global-line buffers. In addition to the dedicated pad, the global lines can be sourced by internal logic.
PIPs from several routing channels within the VersaRing
can also be configured to drive the global-line buffers.

The input buffer has globally selected CMOS and TTL input
thresholds. The input buffer is invertible and also provides a
programmable delay line to assure reliable chip-to-chip setup and hold times. Minimum ESD protection is 3 KV using
the Human Body Model.

VersaRing

8

VersaRing Input/Output Interface

2

The VersaRing, shown in Figure 13, is positioned between
the core logic and the pad ring; it has all the routing
resources of a VersaBlock without the CLB logic. The VersaRing decouples the pad ring's pitch from the core's pitch.
Each VersaRing Cell provides up to four pad-cell connections on one side, and connects directly to the CLB ports on
the other side. Depending on placement and pad-cell pitch,
any number of pad cells to a maximum of four can be connected to a VersaRing cell.

2
GRM

Input/Output Pad
The liD pad, shown in Figure 14, consists of an input buffer
and an output buffer. The output driver is an 8-mA full-rail
CMOS buffer with 3-state control. Two slew-rate control
modes are supported to minimize bus transients. Both the
output buffer and the 3-state control are invertible.

2
GRM

GCK4

GCK1

8
X5705

Figure 13: VersaRing 110 Interface

Vee

GCK2

.... ""

GCK3

1--0------- 0
><5700>

r-~-------OE

Figure 12: Global Lines
X4964

Figure 14: XC5200 1/0 Block

4-196

August 6, 1996 (Version 4.01)

~:XILINX
Pin Descriptions
Permanently Dedicated Pins

MO, M1, M2

Vee

As mode inputs, these pins are sampled before the start of
configuration to determine the configuration mode to be
used.

Eight or more (depending on package type) connections to
the nominal +5-V supply voltage. All must be connected.
GNO

After configuration, MO, M1, and M2 become user-programmable I/O.

Eight or more (depending on package type) connections to
ground. All must be connected.

TOO

CCLK

If boundary scan is not used, this pin becomes user-programmable I/O.

During configuration, Configuration Clock is an output of
the FPGA in master modes or Asynchronous Peripheral
mode, but is an input to the FPGA in Slave Serial mode,
Synchronous Peripheral mode, and Express mode.
After configuration, CCLK has a weak pull-up resistor and
can be selected as Readback Clock.
OONE

This is a bidirectional signal with optional pull-up resistor.
As an output, it indicates the completion of the configuration process. The configuration program determines the
exact timing, the clock source for the Low-to-High transition, and enable of the pull-up resistor.
As an input, a Low level on DONE can be configured to
delay the global logic initialization or the enabling of outputs.

If boundary scan is used, this is the Test Data Output.

TOI, TCK, TMS
If boundary scan is used, these pins are Test Data In, Test
Clock, and Test Mode Select inputs, respectively, coming
directly from the pads, bypassing the lOBs. These pins can
also be used as inputs to the CLB logic after configuration
is completed.
If the boundary scan option is not selected, all boundary
scan functions are inhibited once configuration is completed. These pins become user-programmable I/O.
HOC

High During Configuration is driven High until configuration
is completed. It is available as a control output indicating
that configuration is not yet completed. After configuration,
this is a user-programmable I/O pin.

PROGRAM

This is an active-Low input, held Low during configuration,
that forces the FPGA to clear its configuration memory.
When PROGRAM goes High, the FPGA executes a complete clear cycle, before it goes into a WAIT state and
releases INIT. After configuration,it has an optional pull-up
resistor.

User 1/0 Pins That Can Have Special
Functions
ROY/BUSY

During peripheral modes, this pin indicates when it is
appropriate to write another byte of data into the FPGA
device. The same status is also available on D7 in Asynchronous Peripheral mode, if a read operation is performed
when the device is selected. After configuration, this is a
user-programmable I/O pin.
RCLK

During Master Parallel configuration, each change on the
AO-17 outputs is preceded by a rising edge on RCLK, a
redundant output signal. After configuration, this is a userprogrammable I/O pin.
August 6,1996 (Version 4.01)

Low During Configuration is driven Low until configuration
completes. It is available as a control output indicating that
configuration is not yet completed. After configuration, this
is a user-programmable I/O pin.

Before and during configuration, this is a bidirectional signal. An external pull-up resistor is recommended.
As an active-Low open-drain output, INIT is held Low during the power stabilization and internal clearing of the configuration memory. As an active-Low input, it can be used to
hold the FPGA device in the internal WAIT state before the
start of configuration. Master-mode devices stay in a WAIT
state an additional 50 to 250 llS after INIT has gone High.
During configuration, a Low on this output indicates that a
configuration data error has occurred. After configuration,
this is a user-programmable I/O pin.
GCK1 - GCK4

Four Global Inputs each drive a dedicated internal global
net with short delay and minimal skew. If not used for this
purpose, any of these pins is a user-programmable I/O pin.

4-197

I

XC5200 Field Programmable Gate Arrays

eso, eS1, WS, RS

DIN

These four inputs are used in peripheral modes. The chip is
selected when CSO is Low and CS1 is High. While the chip
is selected, a Low on Write Strobe (WS) loads the data
present on the DO - D7 inputs into the internal data buffer; a
Low on Read Strobe (RS) changes D7 into a status
output: High if Ready, Low if Busy, and DO ... D6 are active
High. WS and RS should be mutually exclusive, but if both
are Low simultaneously, the Write Strobe overrides. After
configuration, these are user-programmable I/O pins. In
Express mode, CS1 is also used as a serial-enable signal
for daisy chaining.

During Slave Serial or Master Serial configuration modes,
this is the serial configuration data input receiving data on
the rising edge of CCLK.

AO - A17
During Master Parallel mode, these 18 output pins address
the configuration EPROM. After configuration, these are
user-programmable I/O pins.

00- 07
During Master Parallel, peripheral, and Express configuration modes, these eight input pins receive configuration
data. After configuration, they are user-programmable I/O
pins.

4-198

During parallel configuration modes, this is the DO input.
After configuration, DIN is a user-programmable I/O pin.
DOUT

During configuration in any non-Express mode, this is the
serial configuration data output that can drive the DIN of
daisy-chained slave FPGA devices. DOUT data changes
on the falling edge of CCLK. After configuration, DOUT is a
user-programmable I/O pin.
In Express mode, this is the enable output that can drive
CS1 of daisy-chained FPGA devices.

Unrestricted User-Programmable 110 Pins
1/0
A pin that can be configured to be input and/or output after
configuration is completed. Before configuration is completed, these pins have an internal high-impedance pull-up
resistor that defines the logical level as High.

August 6, 1996 (Version 4.01)

~XILINX
Configuration
Configuration is the process of loading design-specific programming data into one or more FPGA devices to define
the functional operation of the internal blocks and their
interconnections. This is somewhat like loading the command registers of a programmable peripheral chip. Each
configuration bit defines the state of a static memory cell
that controls either a function LUT bit, a multiplexer input, or
an interconnect pass transistor. The XACTstep development system translates the design into a nellist file. It automatically partitions, places, and routes the logic and
generates the configuration data in PROM formal.

Modes
The XC5200 family has seven modes of configuration,
selected by a 3-bit input code applied to the FPGA mode
pins (MO, M1, and M2). There are three self-clocking Master modes, two Peripheral modes, a Slave serial mode, and
a new high-speed Slave parallel mode called the Express.
See Table 4.
Brief descriptions of the seven modes are provided below.

Master Modes
The Master modes use an internal oscillator to generate
CCLK for driving potential slave devices, and to generate
address and timing for external PROM(s) containing the
configuration data. Master Parallel (up or down) modes
generate the CCLK signal and PROM addresses, and
receive byte parallel data, which is internally serialized into
the FPGA data-frame format. The up and down selection
generates starting addresses at either zero or 3FFFF, to be
compatible with different microprocessor addressing con-

ventions. The Master Serial Mode generates CCLK and
receives the configuration data in serial form from a Xilinx
serial-configuration PROM.

Peripheral Modes
The two Peripheral modes accept byte-wide data from a
bus. A READY/BUSY status is available as a handshake
signal. In the asynchronous mode, the internal oscillator
generates a CCLK burst signal that serializes the byte-wide
data. In the synchronous mode, an externally supplied
clock input to CCLK serializes the data.

Slave Serial Mode
In the Slave Serial mode, the FPGA device receives serialconfiguration data on the rising edge of CCLK and, after
loading its configuration, passes additional data out, resynchronized on the next falling edge of CCLK. Multiple slave
devices with identical configurations can be wired with parallel DIN inputs so that the devices can be configured
simultaneously.

Daisy Chaining
Multiple devices may be daisy-chained together so that
they may be programmed using a single bitstream. The first
device in the chain may be set to operate in any mode; all
other devices in the chain must be set to operate in Slave
Serial mode. Express-mode daisy chains are the only
exception: every device in such a chain must be set to
operate in Express mode.
All CCLK pins are tied together, and the data chain passes
from DOUT to DIN of successive devices along the chain.

Table 4: Configuration Modes
Mode

Master Serial
Slave Serial
Master Parallel up
Master Parallel down
Peripheral Synchronous *
Peripheral Asynchronous
Express
Reserved

.

M2

M1

MO

0
1
1
1
0
1
0
0

0

0
1
0

1
0
1
1

0
1

0

0
1
1
0
1

CCLK

output
input
output
output
input
output
input

-

Data

Bit-Serial
Bit-Serial
Byte-Wide, 00000 T
Byte-Wide, 3FFFF .j,
Byte-Wide
Byte-Wide
Byte-Wide
-

Peripheral Synchronous can be conSidered byte-Wide Slave Parallel

August 6, 1996 (Version 4.01)

4-199

I

XC5200 Field Programmable Gate Arrays

+5V

I

I
I
MO

M1

L . - CS1

DATA BUS

8

5K

MO

Y----

~

CCLK

M2

I

J-

To Additional
Optional
} Daisy-Chained
Devices

DOUT

DO-D7

Optional
Daisy-Chained
XC5200

XC5200

INIT

M1

CS1

DOUT

PROGRAM
INIT

I

M2

DO-D7

~

I

8

I

,-------c

PROGRAM

---< INIT
CCLK

CCLK
X5086

To Additional
Optional
Daisy-Chained
Devices

Figure 15: Express Mode

Express Mode
The Express mode (see Figure 15) is similar to the Slave
serial mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An external
source is used to drive CCLK while byte-wide data is
loaded directly into the configuration data shift registers. In
this mode the XC5200 family is capable of suppOrting a
CCLK frequency of 10 MHz, which is equivalent to an 80MHz serial rate, because eight bits of configuration data are
being loaded per CCLK cycle. An XC5210 in the Express
mode, for instance, can be configured in about 2 ms. The
Express mode does not support CRC error checking, but
does support constant-field error checking.
In the Express configuration mode, an external signal
drives the CCLK input(s) of the FPGA device(s). The first
byte of parallel configuration data must be available at the
D inputs of the FPGA devices a short set-up time before the
second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge. See
Figure 16.
Bitstream generation currently generates a bitstrel'lm sufficient to program in all configuration modes except Express.
Extra CCLK cycles are necessary to complete the configuration, since in this mode data is read at a rate of eight bits
per CCLK cycle instead of one bit per cycle. Normally the
entire start-up sequence requires a number of bits that is
equal to the number of CCLK cycles needed. An additional

4-200

five CCLKs (equivalent to 40 extra bits) will guarantee completion of configuration, regardless of th.e start-up options
chosen.
The Express mode is supported by the XC5200 and
XC4000EX families. It may be used, if XC5200 and
XC4000EX devices are daisy-chained.
If the first device is configured in the Express mode, additional devices may be daisy-chained only if every device in
the chain is also configured in the Express mode. CCLK
pins are tied together and D7-DO pins are tied together for
all devices along the chain. A status signal is passed from
DOUT to CS1 of successive devices along the chain. The
lead device in the chain has its CS1 input tied High (or floating, since there is an internal pull-up). The status pin DOUT
is pulled LOW two internal-oscillator cycles (nominally
1 MHz) after INIT is recognized as High, and remains Low
until the device's configuration memory is full. Then DOUT
is pulled High to signal the next device in the chain to
accept the configuration data on the 07-DO bus. All devices
receive and recognize the six bytes of preamble and length
count, irrespective of the level on CS1; but subsequent
frame data is accepted only when CS1 is High and the
device's configuration memory is not already full.

Format
Table 5 describes the XC5200 configuration data stream.
Table 6 describes the internal configuration data structure.

August 6,1996 (Version 4.01)

~XILINX

CCLK

INIT

00-07

L' ';~' "'

Serial Data Out
(OOUT)

I

ROY/BUSY

CS1

X5087

Figure 16: Express Mode Programming Switching Characteristics

Description
CCLK

INIT (High) Setup time required
DIN Setup time required
DIN Hold time required
CCLK High time
CCLK Low time
CCLK Frequency

August 6, 1996 (Version 4.01)

Symbol

1
2
3

TIC
Toe
Tco
TeCH
TCCL
Fcc

Min

Max

Units

5

~s

30
0
30
30

ns
ns
ns
ns
MHz

10

4-201

XC5200 Field Programmable Gate Arrays

Table 5: XC5200 Bitstream Format
Data Type

Value

Occurrences

Fill Byte
Preamble

11111111
11110010

Length Counter

COUNT(23:0)
11111111

Fill Byte
Start Byte

11111110

Data Frame'
Cyclic Redundancy Check or
Constant Field Check
Fill Nibble
Extend Write Cycle
Postamble
Fill Bytes (30)

DATA(N-1:0)
CRC(3:0) or
0110

Boundary Scan
Instructions

Available:

~eT~~;~;~~p""e
I,
~

PROGRAM
",Low

a/4ms

Once per data
frame

~~~~~--'Y"

EXTEsr
SAMPLEIPRELOAO"
BYPASS
CONFIGURE"

1111
FFFFFF
11111110
FFFF ... FF
FF

Start -U P Byte

Once per bitstream

Once per device
Once per bitstream

"u

Sample
Mode Lines

i

MasterCCLK
Goes Active after

0

()

50 to 250 IJ.S

C

"u

_J

~

0

Table 6: Internal Configuration Data Structure

Device
XC5202
XC5204
XC5206
XC5210
XC5215

VersaBlock
Array
8x8
10 x 12
14 x 14
18 x 18
22 x 22

PROM
Size
(bits)
42,416
70,704
106,288
165,488
237,744

Xilinx
Serial Prom
Needed

Is
No

SAMPLE/PRElOAD

Config-

BYPASS

uralicn
memory
Full

y"

XC1765D
XC17128D
XC17128D
XC17256D
XC17256D

Bits per Frame = (34 x number of Rows) + 28 for the top + 28 for
the bottom + 4 splitter bits + 8 start bits + 4 error check bits + 4 fill
bits * + 24 extended write bits
= (34 x number of Rows) + 100
* In the XC5202 (8 x 8), there are 8 fill bits per frame, not 4
Number of Frames = (12 x number of Columns) + 7 for the left
edge + 8 for the right edge + 1 splitter bit
= (12 x number of Columns) + 16
Program Data = (Bits per Frame x Number of Frames) + 48 header
bits + 8 postamble bits + 240 fill bits + 8 start-up bits

No

cou~f€~ua's No
Length
Count

Ye,
F
EXTEST
SAMPLE PRELOAD
BYPASS
USER 1
USER 2
CONFIGURE

If Boundary Scan
is Selected
X6037

READBACK

Figure 17: Configuration Sequence

= (Bits per Frame x Number of Frames) + 304
PROM Size

4-202

=Program Data

August 6, 1996 (Version 4.01)

~XILINX
Configuration Sequence

Configuration

Figure 17 illustrates the XC5200 configuration sequence.
This section describes the configuration sequence in detail.

The length counter begins counting immediately upon entry
into the configuration state. In slave-mode operation it is
important to wait at least two cycles of the internal 1-MHz
clock oscillator after INIT is recognized before toggling
CCLK and feeding the serial bitstream. Configuration will
not begin until the internal configuration logic reset is
released, which happens two cycles after INIT goes High.
A master device's configuration is delayed from 32 to 256
jls to ensure proper operation with any slave devices driven
by the master device.

Power-On Time-Out
An internal power-on reset circuit is triggered when power
is applied. When Vcc reaches the voltage at which portions
of the FPGA begin to operate (i.e., performs a write-andread test of a sample pair of configuration memory bits), the
programmable 110 buffers are 3-stated with active highimpedance pull-up resistors. A time-out delay - nominally
4 ms - is initiated to allow the power-supply voltage to stabilize. For correct operation the power supply must reach
Vcdmin) by the end of the time-out, and must not dip below
it thereafter.
There is no distinction between master and slave modes
with regard to the time-out delay. Instead, the INIT line is
used to ensure that all daisy-chained devices have completed initialization. Since XC2000 devices do not have this
signal, extra care must be taken to guarantee proper operation when daisy-chaining them with XC5200 devices. For
proper operation with XC3000 devices, the RESET signal,
which is used in XC3000 to delay configuration, should be
connected to INIT.
If the time-out delay is insufficient, configuration should be
delayed by holding the INIT pin Low until the power supply
has reached operating levels.
During all three phases - Power-on, Initialization, and
Configuration - DONE is held Low; HOC, LOC, and INIT
are active; DOUT is driven; and all 1/0 buffers are disabled.

Initialization
This phase clears the configuration memory and establishes the configuration mode.
The configuration memory is cleared. at the rate of one
frame per internal clock cycle (nominally 1 MHz). An opendrain bidirectional signal, INIT, is released when the configuration memory is completely cleared. The device then
tests for the absence of an external active-low level on INIT.
The mode lines are sampled two internal clock cycles later
(nominally 2 jls).
The master device waits an additional 32 jls to 256 jls
(nominally 64-128 jls) to provide adequate time for all ofthe
slave devices to recognize the release of INIT as well. Then
the master device enters the Configuration phase.

August 6, 1996 (Version 4.01)

A preamble field at the beginning of the configuration data
stream indicates that the next 24 bits represent the length
count. The length count equals the total number of configuration bits needed to load the complete configuration data
to all daisy-chained devices. Once the preamble and
length-count values have been passed through to the next
device in the daisy-chain, DOUT is held High to prevent
start bits from reaching any daisy-chained devices. After
fully configuring itself, the device passes serial data to
downstream daisy-chained devices via DOUT until the full
length count is reached.
Errors in the configuration bitstream are checked at the end
of a frame of data. The device does not check the preamble
or length count for errors. In a daisy-chained configuration,
configuration data for downstream devices are not checked
for errors. If an error is detected after reading a frame, the
ERR pin (also known as INIT) is immediately pulled Low
and all configuration activity ceases. However, a master or
Peripheral Asynchronous device will continue outputting a
configuration clock and incrementing the PROM address
indefinitely even though it will never complete configuration.
A reprogram or power-on must be applied to remove the
device from this state.

Start-Up and Operation
The XC5200 start-up sequence is identical to that of the
XC4000 family. Each of these events may occur in any
order: (a) DONE is pulled High; andlor (b) user II0s
become active; andlor (c) Internal Reset is deactivated. As
a configuration option, the three events may be triggered by
a user clock rather than by CCLK, or the start-up sequence
may be delayed by externally holding the DONE pin Low.
In any mode, the clock cycles of the start-up sequence are
not included in the length count. The length of the bitstream
is greater than the length count.

4-203

I

XC5200 Field Programmable Gate Arrays

Pin Functions During Configuration
CONFIGURATION MODE:
SLAVE
<1:1:1>

TDI
TCK

MASTER-SER
<0:0:0>

TDI

SYN.PERIPH
<0:1 :1>



ASYN.PERIPH MASTER-HIGH MASTER-LOW
<1:0:1>
<1:1:0>
<1:0:0>

TDI

EXPRESS
<0:1 :0>

USER
OPERATION

GCK1-1/0

A16
A17

A16
A17

TOI

TOI

TOI

I/O
TOI-I/O

TCK
TMS

TOI
TCK

TCK

TCK

TMS

TMS

TMS

TCK
TMS

TCK
TMS

TMS-I/O

M1 (HIGH) (I)
MO (HIGH) (I)

M1 (lOW) (I)

M1 (HIGH) (I)

M1 (lOW) (I)

M1 (HIGH) (I)

M1 (lOW) (I)

M1 (HIGH) (I)

1/0
1/0

MO (lOW) (I)

MO (HIGH) (I)

MO (HIGH) (I)

MO(lOW) (I)

MO(lOW) (I)

MO(lOW) (I)

I/O

M2 (HIGH) (I)

M2(lOW) (I)

M2(lOW) (I)

M2 (HIGH) (I)

M2 (HIGH) (I)

M2 (HIGH) (I)

M2(lOW) (I)

TMS

TCK-I/O

1/0
GCK2-1/0

HDC (HIGH)
lDC (lOW)

HDC (HIGH)
LDC(LOW)

JNTf-ERROR *

INIT-ERROR *

DONE
PROGRAM (I)

DONE

1/0

HDC (HIGH)
LDC (lOW)
INIT-ERROR *

HDC (HIGH)
lDC (lOW)
INIT-ERROR *

HDC (HIGH)
LDC (LOW)
INIT-ERROR *

HDC(HIGH)
LDC (LOW)
INIT-ERROR *

HDC (HIGH)
lDC (lOW)
INIT-ERROR *

I/O
I/O

DONE
PROGRAM (I)

DONE

DONE

DONE

DONE

DONE

PROGRAM (I)

PROGRAM (I)

DATA 7 (I)

DATA 7 (I)

PROGRAM (I)
DATA 7(1)

PROGRAM (I)
DATA 7 (I)

PROGRAM

DATA 7 (I)

1/0
PROGRAM (I)

1/0
GCK3-1/0

DATA 6 (I)

DATA 6 (I)

DATA 6 (I)

DATA 5 (I)

DATA 5 (I)

DATA 5 (I)

DATA 4 (I)
DATA 3 (I)

DATA 4 (I)
DATA 3 (I)

DATA 4 (I)
DATA 3 (I)

DATA 2 (I)
DATA 1 (I)

DATA 2 (I)

DATA 2 (I)

DATA 2 (I)

DATA 1 (I)

DATA 1 (I)

DATA 1 (I)

RDY/BUSY

RDY/BUSY
DATA 0 (I)
DOUT

RClK
DATA 0 (I)

RClK
DATA 0 (I)

DOUT
CClK(O)

DOUT
CClK(O)

TDO

TDO
AO

DATA 6 (I)
DATA 5 (I)

DATA 6 (I)
DATA 5 (I)

DATA 4 (I)
DATA 3 (I)

CSO(I)
DATA 4 (I)
DATA3(1)

DATA 2 (I)
DATA 1 (I)

RS(I)

DIN (I)
DOUT
CClK(I)

DIN (I)
DOUT
CClK(O)

DATA 0 (I)
DOUT
CClK(I)

TOO

TOO

TDO

CClK(O)
TOO
WS(I)
CS1 (I)

AO
A1
A2
A3

A3

A4

A4

A5

A5
A6

A6
A7

DATA 0 (I)
DOUT
CClK(I)

CClK(I)

TOO

TOO-I/O

1/0

A1
A2

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

GCK4-1/0
CS1 (I)

1/0
1/0
1/0
1/0
1/0

A7

I/O

A8
A9

AS

A10

A10

A11
A12

A11
A12

A13
A14

A13
A14

1/0
1/0
1/0
1/0
1/0
1/0

A15

A15

A9

I/O

1/0
All OTHERS

* INIT IS an open-dram output dUring configuration

(I) Represents an Input

(0) Represents an output

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kQ to 100-kQ pull-up
resistor.

4-204

August 6, 1996 (Version 4.01)

~XIUNX
Configuration Switching Characteristics
-I'''~I----------

Vee

T POR

-----.1

RE·PROGRAM

PROGRAM
------'

~--- Tpi _ _ _-+I

eeLK OUTPUT or INPUT

MO,M1,M2
(Required)

QONE RESPONSE

-=-..r-...

X1532

«33'00 ns

I/0----A--

Master Modes
Description

Symbol

Min

Max

T pOR

2

T pi

TCCLK

6
40
640
100

15
70
375
3000
375

Symbol

Min

Max

Power-On-Reset

T pOR

2

15

ms

Program Latency

T pi

6

70

I1s per CLB column

Power-On-Reset
Program Latency
CCLK (output) Delay
period (slow)
period (fast)

T ICCK
TCCLK

Units
...

, ms

I1s per CLB column
I1s
ns
ns

Slave and Peripheral Modes
Description

CCLK (input) Delay (required)
T ICCK
period (required)
TCCLK
Note.
At power-up, Vee must rise from 2.0 to Vee min
Vee

is valid.

August 6,1996 (Version 4.01)

5
100
In

Units

I1s
ns

less than 15 ms, otherwise delay configuration uSing PROGRAM until

I

XC5200 Field Programmable Gate Arrays

XC5200 Switching Characteristics
Definition of Terms
In the following tables, some specifications may be designated as Advance or Preliminary. These terms are defined as
follows:
Advance:

Initial estimates based on simulation and/or extrapolation from other speed grades, devices, or device
families. Use as estimates, not for production.
Preliminary: Based on preliminary characterization. Further changes are not expected.
Unmarked: Specifications not identified as either Advance or Preliminary are to be considered Final. 1

XC5200 Operating Conditions
Symbol

Description
Supply voltage relative to GNDCommercial:O°C to 85°C junction
Supply. voltage relative to GNDlndustrial:-40°C to 100°C junction
High-level input voltage - TTL configuration
Low-level input voltage - TTL configuration
High-level input voltage - CMOS configuration
Low-level input voltage - CMOS configuration
Input signal transition time

Vee
VIHT
V ILT
V IHe
VILe
TIN

Min

Max

Units

4.75
4.5
2.0
0
70%
0

5.25
5.5

V
V
V
V

Vee
0.8
100%
20%
250

Vee
Vee
ns

Max

Units

XC5200 DC Characteristics Over Operating Conditions
Symbol
VOH
VOL
leeo
IlL
CIN
IRIN
Note:

Description

Min

High-level output voltage @ IOH = -8.0 mA, Vee min
Low-level output voltage @ IOL = 8.0 mA, Vee max (Note 1)
Quiescent FPGA supply current (Note 1)
Leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ VIN =OV (sample tested)

3.86

-10
0.02

0.4
15
+10
15
0.25

V
V
mA
llA
pF
mA

1. With no output current loads, all package pms at Vcc or GND, either TTL or CMOS Inputs, and the FPGA configured with a
MakeBits tie option.

1. Notwithstanding the definition of the above terms, all specifications are subject to change without notice.

4-206

August 6,1996 (Version 4.01)

~XILINX
XC5200 Absolute Maximum Ratings
Symbol
Vee
V IN
VTS
TSTG
Tsol
TJ

Description
Supply voltage relative to GND
Input voltage with respect to GND
Voltage applied to 3-state output
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
Junction temperature in plastic packages
Junction temperature in ceramic packages

Units
-0.5 to +7.0
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
+260
+125
+150

V
V
V

°C
°C
°C
°C

Note: Stresses beyond those hsted under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect
device reliability.

XC5200 Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.

Description
Global Signal Distribution
From pad through global buffer, to any clock (CK)

Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

August 6, 1996 (Version 4.01)

4-207

XC5200 Field Programmable Gate Arrays

XC5200 Longline Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38S10/60S. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACTstep timing calculator
and used in the simulator.

Speed
Description

Symbol

Device

Max
(ns)

Max

(ns)

Max
(ns)

Max

(ns)

TS --;:]

I--t?-0
TBUF
I to Longline, while TS is Low; i.e., buffer is constantly
active

High or

High to TBUF going inactive, not driving

Note: 1. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

4-208

August 6,1996 (Version 4.01)

~XIUNX
XC5200 CLB Switching Characteristic Guidelines
Testing ofthe switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information; use the values provided by the XACTstep timing calculator
and used inthe simulator.

Grade
Description

Symbol

F inputs to X output
PI inputs to PO output (Logic-Cell
Feedthrough)
F
via F5_MUX to PO output

I
to ouf (Q) (Flip-Flop)
Gate
enable) going active to out (Q)
Set-up Time Before Clock (CK)
F inputs
F inputs viaF5_MUX
PI input
CE

Note: 1. The CLB K to Qoutput delay (TCKO) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold-1ime requirement (TCKDI) of any CLB on the same die.
2. Timing is based upon the XC5215 device. For other devices, see XACTstepTiming Calculator.

August 6, 1996 (Version 4.01)

XC5200 Field Programmable Gate ArraY$

XC5200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be
derived indirectly from the Global Buffer specifications, The XACTstep delay calculator uses this indirect method, and may
overestimate because of worst-case assumptions. When there is a discrepancy between these two methods,the values
listed below should be used, and the derived values should be considered conservative overestimates.

Description

lOB

Direct
Connect

CLB

i~!i~~ 1c:>-[>----....,U
c:>-[>
r;Dl
Time

TeUFG
Input Hold Time (no delay) to
lOB
Direct

Connect

CLB

.

i~~~ 1~-----tJ
TeuFG

o
Inputl~

0

(Min)

Set-up

& Hold
Time

-----

TeUFG
Note: 1. These measurements assume that the flip-flop has a direct connect to or from
assure thatdirect connects are used.
2. When testing outputs (fast or slew-limited), half of the outputs on one side of the device are switching.
3. Die-size-dependent parameters are based upon XC5210 characterization. Production specifications will vary with array
size.

4-210

August 6, 1996 (Version 4.01)

~XIUNX
XC5200 lOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up~to-date,tim,ng information, use the values provided by the XACTsteptiming calculator
and used in the simulator.
..

Description

Symbol

Max
(ns)

Max
(ns)

Max
(ns)

Max
(ns)

Propagation Delays to CMOS or TTL Levels
Output (0) to Pad (fast)
Output (0) to Pad (slew-limited)
From clock (CK) to output pad (fast), using direct connect between Q
and output (0)
From clock (CK) to output pad (slew-limited), using direct connect between Q and output (0)
3-state to Pad active (fast)
3-state to Pad active (slew-limited)
Internal GTS to Pad active (see Note 3)

I

Note: 1. Timing is measured at pin threshold, with 50-pF external capacitance loads. Slew-limited output rise/fall times are
approximately two times longer than fast Oljtput rise/fall times. For the effect afcapacitive loads on groljnd bounce, see
"XC4000 Series Technical Information" in ·Section 13, Prodljct Technical Information" in the 1996 Xilinx Programmable
Logic Data Book.
2. Unused and unbonded 108s are configured by default as inputs with internal pull-up resistors.
3. Timing is based upon theXC521 0 device. For other devices, see XACTstepTiming Calculator.

August 6, 1996 (Version 4.01)

4-211

XC5200 Field Programmable Gate Arrays

XC5200 CLB-to-Pad Diagrams
Top

••••••••••••••••••••••••••••••••

Left

•••
•••
••
•
•••
•••
•
•••
••
••
••
•••
••
••

I,R1C1 I R1C211 R1C31lR1C411 R1C511 R1C611 R1C711 R1csi

•
••
••
•
•••
•
•••
•••
••

•••

BDDDDDDB
BDDDDDDB
EJDDDDDDB
EJDDDDDDB •
EJDDDDDDB ••••
EJDDDDDDB ••••
I RaC1 II RSC211 RSC311 RSC411 RSC511 RaC611 RSC711 RScsl

••••••••••••••••••••••••••••••••

Right

••

Bottom
KEY:
•

I R#C# I

1/0 Pad
CLB, identified by R#C# = row and column numbers

Figure 18: XC5202 CLB-to"Pad Relationship

4-212

August 6,1996 (Version 4.01)

~:XILINX
Left

••
•
•
•
•
•
•
••

11 •
12 •
13 •
14 •

15 •
16 •
17 •
18 •

19 •
20 •
21 •
22 •
23 •

24 •
25 •
26 •
27 •

28 •

29 •
30 •
31 •
32 •

Bottom
33 •
34 •

••
•
•
•
•
•
••
••

35 •
36 •

37 •

38 •
39 •
40 •
41

•

42 •
43 •

44 •
45 •

46 •

47 •
48 •
49 •

50 •
51 •
52 •
53 •

Right

••
•
••
•
••
•
•
••

Top
•

•

73

•
•
•

71
70
69

•

68

•

72

•

67

•
•

66
65

•

64

•
•

63
62

•
•

61
60

•

59

•

58

•

56

•

•
•

57

55
54

•
•=

10

• 9
• 8
7
• 6
•

5
4

=
=
=~
• 83
=
• 80
•=79
3

•

84
82

•

81

.77
••
•

78

•

76

•

75

•

74

•

Note: Pad numbers (1,2, ... ,84) refer to die pads, not external device pins.
See the XC5202 pinout table beginning on page 223.

Figure 19: XC5202 CLB-to-Pad Relationship (Detail)

August 6, 1996 (Version 4.01)

4-213

I

XC5200 Field programmable Gate Arrays

Top

••••••••••••••••••••••••••••••••••••••••••••••••

Left

•
•
••• ~[;][;][;][;][;]~[;][;]BBB •••
•••
•••
•
•••
•••
••
•••
••
•••
••
•••
•••
•••
•••
••
••
•
•••
•••
••
•
•••
••
••
•••
••
•• I Al0Cl II Al0C211 Al0C311 Al0C411 Al0Csii Al0C611 Al0C711 Al0Csii Al0C911 Al0Cl0 IIA10Cll II Al0C12I •••
••
••

BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB
BDDDDDDDDDDB

Right

••••••••••••••••••••••••••••••••••••••••••••••••
Bottom

KEY:

•
IR#C# I

1/0 Pad
CLB, identified by R#C#

= row and column numbers

Figure 20: XC5204 CLB-to-Pad Relationship

4-214

August 6, 1996 (Version 4.01)

---

--------

---

---

- - - -_.-

---"--

~XILINX

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

••
••
•••
••
••
••
••
••
••
••
•••
••
•
•••
•••
••
••
•••

EJ

EJ
EJ
EJ
EJ
EJ

EJ

EJ
EJ
j R10C1 j

Right

Bottom

Left
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79

••
••
•••
•••
••
•••
•••
•••
•••
••
••
••
•••
••
••
•••
••
•
•••
••

IR10C1 I

I R1C12 I

IR10C21

I R2C12

I

I R10C31

I R3C12

I

I R10C41

I R4C12

I

I R10C51

IR5C12 I

IR10C6j

IR6C12 I

I R10C71

I

j R10C81

j R8C12 I

j R10C91

I R9C12j

IR10C101

jR10C121

R7C12 I

•••
••
••
••
•••
•
•••
•••
••
•••
••
••
••
••
••
•••
•
••

Top

107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80

EJ

[3
[3

EJ

[3
[3

EJ

[3
[3
j R1C10 j

IR10C111

8

IR10C12j

j R1C12j

••

••
••
••
••
•••
•••
•
•••
••
••
•••
•
•••
••
••
••
•••
••
••
•••
•

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108

Note: Pad numbers (1,2, ... , 124) refer to die pads, not external device pins.
See the XC5204 pinout table beginning on page 226.

Figure 21: XC5204 CLB-to-Pad Relationship (Detail)

August 6,1996 (Version 4.01)

4-215

I

XC5200'Fieid Programmable Gate Arrays

Top

••••••••••••••••••••••••••••••••••••••••••••••••••••••••

•••
[;][;][;][;][;][;][;]1
••
•
•••
••
•••
••
•
•••
•••
•••
•=
••
••
•••
••
•• F==lF====lDF====lD
DD
••
•
•••
••
••
••
R1Cl

Left

R1C2

R1Cl0 IIR1Cll

I~II

R1C13II R1C14

1 ••••

DDDDDDDB
DDDDDDDB
DDDDDDDB
= =! = =D= =!. =DDDDDDDDB
==!
BD DDDDDDDDDB
BDDDDDDDDDDDDB
BDDDDDDDDDDDDB
DD
DDD
B
B
DDD
R9Cl

••
••

R13C14

R14C14

••
••
••
••
•••
•••
•••
••
•
•••
•
•••
••
••
••
•••
•
•••
•••
•••
•••
••
•

Right

••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Bottom

KEY:

•

IR#C# I

liD Pad
CLB, identified by R#C#

= row and column numbers

Figure 22: XC5206 CLB-to-Pad Relationship

4-216

August 6, 1996 (Version 4.01)

--

---~~~---

-

---

-----"---

~XIUNX
Left

19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56

Note:

••
••
•••
••
••
•

EJ
B
B
••
•• EJ
••• B
•••
• B
•••
• B
•••
•• B
••
• B
•••
••
••
•• B
••

I R10C1 I

•••
••
•••
••

Bottom
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88

I R12C1 I

I R13C1 I

I R14C1 j

89
90
91
92
93

••
•••
••
•••
•••
••
•
•••
•••
••
••
••
••
••
••
•••
•••
••
•••
•
•••
••
••
•••

I R14C1 I

Right
I R1C14i

I R14C21

I R2C14 I

I R14C31

I R3C14 I

I R14C41

I R4C14

I R14C51

I R5C14 I

I R14C61

I R6C14 I

I

I R14C71

I R7C14 I

I R14C81

I R8C14 I

I R14C91

I R9C14 I

IR14C101

IR10C141

IR14C111

IR11C141

IR14C121

IR12C141

IR14C131

[R13C14j

jR14C14j

jR14C141

Pad numbers (1, 2, ... , 148) refer to die pads, not external device pins.
See the XC5206 pinout table beginning on page 230.

•••
••
••
•••
•••
••
•
•••
••
••
•••
•••
•
•••
••
••
••
•••
•••
••
•
•••
••
••
•

Top

129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94

EJ
8
8
EJ
8
8
EJ
8
8
8

I R1C10 I

I R1C12 I

I R1C13j

I RiC141

•
•••
•
•••
••
••
•••
••
•••
••
••
••
••
••
••
••
•••
••
••
••
••
•••
••
••
••
••

18
17
16
15
14
13
12
11
10
9
8
7
6

5
4
3
2
1
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130

Figure 23: XC5206 CLB-to-Pad Relationship (Detail)

August 6, 1996 (Version 4.01)

4-217

I

XC5200 Field Programmable Gate Arrays

Top

••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
R1C4

R1G1B

Rles

R2C18

R3C18

R4C18

R5C18

DDD1f=====lf=====lf=====lf=====lf=====lf=====lf=====lDDDDEJ
DDDDf=====lf=====lf=====lf=====lf=====lf=====lIf=====lDDDDB
DDDDiF=9F=9:F=9F=9F=9F=9F=9DDDDEJ
DDDDEJ
DDDD
iF=9F=9F=9F=9F=9F=9F=9DDDDDB
DDDD
DDD
DDDD

R6e,

R7e1

R8Ct

Rgel

Left
Rl0e1

R1te1

Right

R11C18

R14C18

R15C18

R16G18

R17e18

R18C18

••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Bottom
KEY:
•

IR#C#I

I/O Pad
CLB, identified by R#C#

= row and column numbers

Figure 24: XC5210 CLB-to-Pad Relationship

4-218

August 6, 1996 (Version 4.01)

~:XILINX
Left

••
•
•
•

25 •
26 •
27 •
28 •
29 •

[:]

75 •
76 •

EJ

77.

30 •
31 •
32 •

\ R3C1 \

33 •
34 •
35 •

B

I

EJ
•
EJ
• [:]
••
EJ
••
EJ
•

36
37 •
38 •
39 •
40 •
41 •
42 •
43 •
44 •
45 •
46 •
47 •
48 •

49 •
50 •
51 •

I

52
53 •
54 •

•
•

55 •

56 ••
57

78 •
79 •

80 •
81 •
82 •
83 •
84 •
85 •
86 •
87 •
88 •

•

89 •
90 •

••
•
•
•
•
•
•
••
••

91 •
92 •
93 •
94 •
95 •
96 •
97 •
98 •

99 •
100 •

101 •

B

103 •
104 •
105 •

\ R12C1 \
\ R13C1 \

61 •
62 •
63 •

\ R14C11

• \ R1SC1 \
• IR16C1 I
• IR17C1 I
•• IR1SC1 I

64 •
65 •
66 •
67 •
68 •
69 •

70 •
71 •
72 • .
73 •
74 •
Note:

••
•
•
•

\ R10C1 \

58 •
59 •
60

I,

Bottom

102 •

106 •
107 •
108 •
109 •
110 •

111 •
112 •
113 •
114 •
115 •

•
•
•
••

116 •
117 •
118 •
119 •
120 •
121 •
122 •
123 •

Right

•
••

Top

•
•

171
170

•
•
•

•
•

169
168
167
166
165
164

•
•
•

163
162
161

•
•
•

160
159
158

•
•
•

157
156
155

•
•
•

154
153
152

I

•
•
•
•
••
••
••
•

• 151
.150
•
•

149
148

[:] I•
•
•

EJ
EJ
EJ
EJ
EJ

22

=~6
I•

•

19
18
17

I•
I•

•

16
15
14

•

11

•
I
••

[:] •

13
12

10

•

9

•
•
•
•

7
6
5
4

I•

•

3
21

•

196
195
194

•

EJ
EJ

24
23

I R1C101

I•

8

•
•

147
146

•

•
•
•

145
144
143

IR1C11 I

I•

193
192
191

•

190

•
•
•

142
141
140

\H1C12\

•
•
•

139
138
137

IR1C13\

I• 189
188
187
I• 186
I• 185

•
•

136
135

•
•

184
183

•
•
•

134
133
132

\ R1C1S\

•
•
•

182
181
180

•
•
•

131
130
129

IR1C16\

•
•
•

128
127
126

\ R1C17\

•

•
••
•
•
•
••
•
•

125
124

\R1C141

\R1C1S\

•
•
•
•

179
178

•

177

I•

•

176
175
174

•

173

•

172

•
••

Pad numbers (1, 2, ... , 196) refer to die pads, not external device pins.
See the XC521 0 pinout table beginning on page 235.

Figure 25: XC521 0 CLB-to-Pad Relationship (Detail)

August 6, 1996 (Version 4.01)

4-219

I

XC5200 Field Programmable Gate Arrays

Top

••••••••••••••••••••••••••••••••
R,C3 R1C4 [;][;]~[;]

••••••••••••••••••••••••••••••••

i•
R3C22

R4C22

R5C22

R6e22

Left

Right

•

DDDD
DODD
I•
DDDD
••
DDDD
I
DDDD
DDDD
1
••
=DDDD
•• =
;]G; ~ I
I

i••

i====ii====ii====iDDDDB .1
F==IF==IF==IDDDDB.
i====ii====ii====iDDDDBI
F==IF==IF==IDDDDB
DDDDgl
F==IF==IF==IDDDDgi
DDDDgl

R15C1

R16C1

R17C1

Rl8C1

R19C1

R20C1

R21C1

I

Rzzel

gggggi

R22csll R22C611 R22C711 "22CB

-

••••••••••••••••••••••••••••••••

••••••••••••••••••••••••••••••••
Bottom
KEY:
•

h#c#1

I/OPad
CLB, identified by R#C#= row and column numbers

Figure 26: XC5215 CLB·to·Pad Relationship

4-220

August 6, 1996 (Version 4.01)

- - -

---.~---

~XILINX
Bottom

Left

31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

••
••
•••
••
•••
•••
••
•••
•••
•••
••
••
••
••
•••
••
•••
••

EJ

EJ
EJ
EJ
EJ
EJ

EJ

EJ
EJ
I

R10C1 I

B

61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92

•••
•••
•••
••
•••
••
•
•••
•
•••
•
•••
•••
•••
••
••
•
•••
••

j R12C1 j

93
94

j R13C1 j

95
96
97

j R14C1 j

98
99
100

j R15C1 j

101
102
103

I R16C1 I

104
105
106

I R17C1 I

107
108
109

EJ

110
111
112

j R19C1 I

113
114
115

I R20C1 I

116
117
118

j R21C1

I

119
120
121

I

I

R22C1

122
123

•••
••
•
•••
••
•••
••
••
••
••
••
•••
•
•••
••
•••
••
••
•••
•

j R22C1 j

124
125

j R22C2j

126
127
128

j R22C3j

129
130
131

j R22C41

132
133
134

I R22C51

135
136
137

I R22C61

138
139
140

I R22C71

141
142
143

I R22C81

144
145
146

I R22C91

I R22C101

IR22C11I

147
148
149
150
151
152
153

••
•••
••
••
••
•••
•••
••
•••
•••
••
••
••
•••
••
••
•••
••
•

j R22C12j

j R22C13j

jR22C14j

j R22C15I

I R22C16I

I

IR22C171

I R22C18I

IR22C19I
I R22C201

j R22C21I

I R22C22I

Note: Pad numbers (31, 32, ... , 153) refer to die pads, not external device pins.
See the XC5215 pinout table beginning on page 241.

Figure 27: XC5215 CLB-to-Pad Relationship (Left/Bottom Detail)

August 6, 1996 (Version 4.01)

4-221

XC5200 Field Programmable Gate Arrays

Right
I R1C22 I

\ R2C22 \

\ R3C22 I

\ R4C22 \

I R5C22 I

I R6C22 I

\ R7C22 I

\ R8C22 I

I R9C22 I

\ R10C22\

IR11C221

••
••
•••
••
••
•••
•
•••
•••
••
•••
••
••
•••
••
•••
••
••
••

213
212
211
210
209
208
207

Top
I R12C22 I

\R13C22\

I R14C22I

206
205
204

I R15C22I

203
202
201

\R16C221

200
199
198

I R17C22\

197
196
195

I R18C22I

194
193
192

\ R19C22\

191
190
189

I R20C22I

188
187
186

I R21C22\

185
184

I R22C22\

•••
••

•••
•

••
•
•••
••
••
•••
••
••
••
••
••
•••
•••
••
••
••

183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154

Note: Pad numbers (1,2, ... ,244) refer to die pads, not external device pins.

EJ

B
B
EJ
B
B
B
B
B
EJ

\ R1C10 \

•••

•••
••
••
I•
••
•••
••
••
••
••
••
••
•••
••
••
••••
•••

30
29
\ R1C12 I
28
27
26

I R1C13 I

25
24
I R1C14 \
23
22
21

I R1C15 I

20
19
18

I R1C16 I

17
16
15

\ R1C17 I

14
13
12

I R1C18 I

11
10
9

\ R1C19 I

8
7
6

I R1C20 \

5
4
3

\ R1C21 I

2
1
I R1C22 \

•
•••
••
•I•
•••
•
•I•
••
•••
•
I
•
•••
•••
••
•••
•
•••
••

244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214

See the XC5215 pinout table beginning on page 241.

Figure 28: XC5215 CLB-to-Pad Relationship (RightfT!lp Detail)

4-222

August 6, 1996 (Version 4.01)

~XILINX
Device-Specific Pinout Tables
Pin Locations for XC5202 Devices

t

PC84

PQ100

VQ100

TQ144

PG156

VCC

2

92

89

128

H3

-

I/O (A8)

3

93

90

129

H1

51

2.

I/O (A9)

4

94

91

130

G1

54

3.

I/O

-

95

92

131

G2

57

Pin
1.

Description

Boundary Scan Order

4.

I/O

96

93

132

G3

63

5.

VO (A10)

5

97

94

133

F1

66

6.

I/O (A11)

6

98

95

134

F2

69

-

135*

-

-

-

136*
F3

-

-

-

-

GND

137

7.

1/0{A12)

7

8.

I/O (A13)

8

-

-

99
100

96

138

E3

97

139

C1

140*

-

~~-

-

-

141 *

78

r-----

81

-

9.

I/O (A14)

9

1

98

142

B1

90

10.

I/O (A15)

10

2

99

143

B2

93

VCC

11

144

C3

12

3
4

100

GND

1

1

C4

-

11.

GCK1 (A16, I/O)

13

5

2

2

B3

102

12.

I/O (A17)

14

6

3

3
4*

A1

105

-

-

-

-

13.

I/O (TDI)

15

7

4

6

B4

111

14.

I/O (TCK)

16

8

5

7

A3

114

-

-

8

C6

-

9*

-

GND

15.

I/O (TMS)

17

16.

I/O

18

17.
18.
19.
20.

I/O

5'

10*

-

-

9
10

6

11

A5

7

12

C7

117
123

-

-

13

B7

126

11

8

14

A6

129

I/O

19

12

15

A7

135

I/O

20

13

9
10

16

A8

138

GND

21

14

11

17

C8

110

VCC

22

15

12

18

B8

-

21.

I/O

23

16

13

19

C9

141
147

22.

I/O

24

17

14

20

B9

23.
24.

I/O
I/O

-

18

15

21

A9

150

22

B10

153

25.

I/O

25

19

16

23

C10

159

26.

I/O

26

20

17

24

A10

25*

-

-

GND
27.
28.

I/O

I/O

August 6, 1996 (Version 4.01)

-

162
.. '

-

26*

-

-

-

27

C11

-

27

21

18

28

B12

165

A13

171

I/O

29.

-

22

19

29

-

30*

-

-

28

23

20

32

-

31*
B13

174

4-223

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5202 Devices
Pin
30.
31.

32.
33.
34.
35.

36.
37.

Description t
1/0

Ml (1/0)
GNO
MO(I/O)
VCC
M2 (1/0)
GCK2 (1/0)
1/0 (HOC)

1/0
1/0 (LOC)

GNO

38.
39.
40.
41.
42.
43.

1/0
1/0
1/0
1/0
1/0
1/0 (ERR, INIT)

VCC
GND
44.
45.
46.
47.
48.
49.

1/0
1/0
1/0
1/0
1/0
1/0

PC84

PQ100

VQ100

TQ144

PG156

Boundary Scan Order

29
30
31
32
33
34
35
36

24
25
26
27
28
29
30
31

21
22
23
24
25
26
27
28

B14
A15
C13
A16
C14
B15
B16
014

177
186

192
195
204

-

-

-

-

37

32
33

29
30

-

-

E14
C16
F14

207
210

-

33
34
35
36
37
38
39
40
41*
42*
43
44
45
46*
47*
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62*
63*
64
65
66
67*
68*
69
70
71
72
73
74
75
76
77*
78*
79
80
81
82*

-

-

38
39

34
35
36
37
38
39
40
41
42
43
44
45
46
47

31
32
33
34
35
36
37
38
39
40
41
42
43
44

-

40
41
42
43
44
45

46
47

GND
50.
51.

1/0
1/0

52.
53.

ItO
1/0

54.
55.

GND
DONE
VCC
PROG
1/0 (D7)
GCK3 (1/0)

56.
57.

1/0 (D6)
1/0

GND

4-224

-

-

-

48
49

48
49

45
46

-

-

-

-

-

50
51
52
53
54
55
56
57

50
51
52
53
54
55
56
57

47
48
49
50
51
52
53
54

-

-

58
59

55
56

-

-

58

-

189

-

-

-

-

-

F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16

216
219
222
228
231
234

240
243
246
252
255
258

L14
P16
M14

264
267

N14
R16
P14
R15
P13
R14
T16
T15

-

276
279

-

288
291

-

T14
T13
Pll

300
303

-

-

-

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5202 Devices
Description

Pin

59.

1/0 (05)
1/0 (CSO)

60.

I/O

61.

1/0

62.
63.

58.

t

PC84

PQ100

VQ100

TQ144

-

-

-

83*

59

60

57

84

PG156

Boundary Scan Order

T10

306

-

61

58

85

P10

312

62

59

86

R10

315

-

63

60

87

T9

318

1/0(04)

61

64

61

88

R9

324

1/0

62

65

62

89

P9

327

-

60

VCC

63

66

63

90

R8

GNO

64

67

64

91

P8

64.

1/0(03)

65

68

65

92

T8

336

65.

1/0 (RS)
1/0
1/0
1/0(02)
1/0

66

69

66

93

T7

339

70

67

94

T6

342

95

R7

348

66.
67.
68.
69.

-

GNO

1/0 (01)
1/0 (RCLK-BUSYI

70.
71.

67

71

68

96

P7

351

68

72

69

97

T5

360

-

-

-

98*

-

-

-

100

P6

-

69

73

70

101

T3

363

70

74

71

102

P5

366

-

-

103*

-

72

105

I

99~

ROY)

72.

1/0 (00, OIN)

73.

I/O (OOUT)

72

76

73

CCLK

73

77

74

VCC

74

78

1/0 (TOO)

75

GNO

76

74.

76.

1/0 (A2, CS1)
1/0 (A3)

77.
78.

P4

372

106

T2

375

107

R2

75

108

P3

-

79

76

109

T1

80

77

110

N3

77

81

78

78

82

79

-

-

-

114*

79

83

80

115

P1

18

80

84

81

116

N1

21

-

-

117*

-

118

L3

119*

-

-

121

K3

27

71

1/0 (AO, WS)
GCK4 (A 1, 1/0)

75.

GNO

-

-

79.

1/0 (A4)

81

80.

I/O (A5)

82

81.

I/O

82.

1/0
1/0 (A6)
1/0 (A7)

83.
84.

.

GNO

-

104*

75

-

.'

85

0
--

-

R1

9

112

P2

15

113*

-

-

86

83

122

K2

30

87

84

123

K1

33

88

85

124

J1

39

83

89

86

125

J2

42

84

90

87

126

J3

45

1

91

88

127

H2

-

-

.'

--

-

120*
82

-

111

Notes: 'Indicates unconnected package pins.

t

leading numbers refer to bonded pad, shown in Figure 18 or Figure 19.

Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO

August 6, 1996 (Version 4.01)

4-225

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5204 Devices
Description

Pin

VCC
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.

I/O (A8)
I/O (A9)
I/O
I/O
I/O (A10)
I/O (A11)
I/O
I/O
GNO
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O
I/O (A14)
I/O (A15)

VCC
17.
18.
19.
20.
21.
22.

GNO
GCK1 (A16,1/0)
I/O (A17)
I/O
I/O
I/O (TOI)
I/O (TCK)

t

PC84

PQ100

VQ100

TQ144

PG156

PQ160

2
3
4

92
93
94
95
96
97
98

89
90
91
92
93
94
95

128
129
130
131
132
133
134
135
136
137

H3
H1
G1
G2
G3
F1
F2
E1
E2
F3
01
02
E3
C1
C2
03
81
82
C3
C4
83
A1
A2
C5
84
A3

142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
1
2
3
4
5
6
7
8*
9*
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30*
31*

0

5
6

0

0

0

0

0

0

0

0

0

0

7
8

99
100

96
97
0

0

0

1
2
3
4
5
6

9
10
11
12
13
14
0

0

98
99
100
1
2
3

0

15
16

7
8

4
5

·
23.
24.
25.
26.
27.
28.
29.
30.

GNO
I/O
I/O
I/O (TM$)
I/O
I/O
I/O
I/O
I/O
GNO

0

0

·
·

·

0

17
18

9
10

0

6
7

0

11
12
13
14
15
16

0

8
9
10
11
12
13
14
15

I/O
I/O
1/0

·

18

1/0

25
26

19
20

16
17

1/0

·

·

·

1/0

0

0

0

I/O
1/0

GNO

,

17
0

0

0

0

·

8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

C6
85
86
A5
C1
87
A6
A7
A8
C8
88
C9
89
A9
810
C10
A10
A11
811
C11

0

·
4·226

0

·

19
20
21
22
23
24

VCC
31.
32.
33.
34.
35.
36.
37.
38.

·
·

0

138
139
140
141
142
143
144
1
2
3
4
5
6
7

0

0

Boundary Scan Order

78
81
87
90
93
99
102
105
0

111
114
117
123
126
129
138
141
0

150
153
159
162
165
171
0

174
177
180
183
186
189
195
198

.
201
207
210
213
219
222
225
231

.

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5204 Devices
Description t

Pin

39.
40.
41.
42.
43.
44.
45.
46.
47.
48.
49.
50.
51.
52.
53.
54.
55.
56.
57.
58.
59.
60.
61.
62.
63.

64.
65.
66.
67.
68.
69.
70.
71.
72.
73.
74.
75.
76.
77.
78.
79.

I/O
I/O
I/O
I/O
I/O
I/O
Ml (I/O)
GND
MO (I/O)
VCC
M2 (I/O)
GCK2 (I/O)
I/O (HOC)
I/O
I/O
I/O
I/O (LDC)
I/O
I/O
GNO
I/O
I/O
I/O
I/O .__ .
.. __
I/O
I/O
I/O
I/O (ERR, INIT)
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
I/O
I/O
I/O
110

I/O
I/O
I/O
I/O
GNO
DONE
VCC
PROG

August 6, 1996 (Version 4.01)

PC84

PQ100

VQ100

TQ144

PG156

PQ160

Boundary Scan Order

27

21
22

18
19

28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44

812
A13
A14
C12
813
814
A15
C13
A16
C14
815
816
014
C15
015
E14
C16
E15
016
F14
F15
E16
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
M16
L15
L14
N16
M15
P16
M14
N15
P15
N14
R16
P14
R15
P13
R14

32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82

234
237
240
243
246
249
258

-

28
29
30
31
32
33
34
35
36

23
24
25
26
27
28
29
30
31

20
21
22
23
24
25
26
27
28

-

-

-

32
33

29
30

-

-

37

-

-

-

-

46
47

34
35
36
37
38
39
40
41
42
43
44
45
46
47

31
32
33
34
35
36
37
38
39
40
41
42
43
44

-

-

-

-

-

38
39

40
41
42
43
44
45

-

-

-

-

48
49

48
49

45
46

-

-

-

50
51
52
53
54
55

47
48
49
50
51
52

-

50
51
52
53
54
55

--,--

-

45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64

65
66
67
68
69
70
71
72
73
74

261
264
267
276
279
282
288
291
294
300

303
306
312
315
318
324
327
330

336
339
348
351
354
360
363
366

372
375
378
384
387
390
396
399

4-227

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5204 Devices
Pin
80.
81.
82.
83.
84.
85.

Description t
I/O (D7)
GCK3 (1/0)
I/O
I/O
1/0 (D6)
I/O

GND
86.
87.
88.
89.
90.
91.
92.
93.

94.
95.
96.
97.
98.
99.
100.
101.

1/0

PC84
56
57

PQ100
56
57

58

-

58
59

109.
110.
111.
112.
113.
114.
115.
116.
117.
118.
4-228

55
56

1/0 (D5)
1/0 (CSO)
1/0
1/0

59
60

I/O (D4)

61
62
63
64
65
66

1/0

VCC
GND
1/0 (D3)
1/0 (RS)

-

-

-

-

-

60
61
62
63
64
65
66
67
68
69
70

57
58
59
60
61
62
63
64
65
66
67

-

I/O

-

-

-

67
68

71
72

68
69

-

-

-

-

-

69
70

73
74

70
71

-

-

-

71
72
73
74
75
76

75
76
77
78
79
80
81
82

72
73
74
75
76

1/0 (D1)
1/0 (RCLK-BUSY/RDY)
1/0
1/0
1/0 (DO, DIN)
1/0 (DOUT)

CCLK
VCC
1/0 (TDO)
GND
Ifa (AO, WS)
GCK4 (A 1, 1/0)
I/O
1/0
1/0 (A2, CS1)
110 (A3)
1/0
1/0

77

78

GND
1/0
1/0

-

77

78
79

83
84

-

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

P11
R11
T11
T10
P10
R10
T9
R9
P9
R8
P8
T8
T7
T6
R7
P7
T5
R6
T4
P6

-

-

101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117

T3
P5
R4
R3
P4
T2
R2
P3
T1
N3
R1
P2
N2
M3
P1
N1
M2
M1
L3
L2
L1

-

79
80

PG156
T16
T15
R13
P12
T14
T13

-

1/0
1/0 (D2)
1/0
1/0
1/0

TQ144
75
76
77
78
79
80

-

-

108.

-

I/O

GND

102.
103.
104.
105.
106.
107.

VQ100
53
54

-

-

80
81

-

-

118
119
120

PQ160
83
84
85
86
87
88
89*
90*
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111 *
112*
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133

Boundary Sc.an Order
408
411
420
423
426
432

-

.

435
438
444
447
450
456
459
462

468
471
474
480
483
486
492
495

498
504
507
510
516
519

0

9
15
18
21
27
30
33
39

42
45

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5204 Devices
Description

t

PC84

PQ100

VQ100

TQ144

PG156

PQ160

Boundary Scan Order

119.

I/O (A4)

81

85

82

121

K3

134

51

120.

1/0 (A5)

82

86

83

122

K2

135

54

-

-

-

136'

-

84

123

K1

137

57

Pin

1/0
1/0
1/0 (A6)
1/0 (A7)

121.
122.
123.
124.

GND

-

87
88

85

124

J1

138

63

83

89

86

125

J2

139

66

84

90

87

126

J3

140

69

1

91

88

127

H2

141

Notes:' Indicates unconnected package pins.

t

leading numbers refer to bonded pad, shown in Figure 20 or Figure 21.

=

Boundary Scan Bit 0 TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 BSGAN.UPD

=

I

August 6,1996 (Version 4.01)

4-229

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5206 Devices
Pin

Description

t

PC84

PQ100

VQ100

TQ144

PQ160

TQ176

PG191

PQ208

2
3

92
93

142

183

-

4

94

143
144

J3
J2

184
185

87

I/O (A9)

129
130

155
156
157

J4

2.

89
90
91

128

1.

VCC
110 (A8)

3.
4.

I/O

145
146

158
159

Jl
Hl

186
187

-

Boundary Scan Order

90

95
96

92

131

93

132

-

-

-

-

160

H2

188

99
102

147

161
162

H3
Gl

189
190

105
111

93

5.

I/O
I/O

6.
7.

I/O
I/O (Al0)

5

97

94

133

8.

I/O (All)

6

98

95

134

148

163

G2

191

114

9.

I/O

-

135

149

164

Fl

192

117

136
137

150
151

165

El
G3

193
194

123

166

-

-

167*

195*
196*

-

152

168

Cl

197

153

169

E2

198

126
129

-

-

-

12.

I/O
I/O

-

-

-

13.
14.

I/O (A12)
I/O (A13)

7

99
100

96

138

154

170

F3

199

138

8

97

15.

I/O

-

-

-

139
140

155
156

171
172

02
Bl

200
201

141
150

16.
17.

I/O
I/O (A14)

1

98

141
142

157

173
174

18.

I/O (A15)

9
10

2

VCC

11

3

99
100

-

10.

I/O
GND

11.

-

-

-

-

GND

12

4

E3

202

153

203
204

162

175

C2
B2

160

176

03

-

-

-

-

-

205
206*

-

-

-

-

1

1

1

04

143

158
159

144

-

-

1

-

19.
20.
21.
22.

GCKl (A16, I/O)
I/O (A17)
I/O

23.
24.

I/O
I/O (TOI)
I/O (TCK)

25.

I/O

26.

I/O

GNO
27.
28.
29.

I/O
I/O
I/O (TMS)
I/O

13

5

2

2

2

2

14

6

3

-

-

3
4

3
4

3
4

5

5

15
16

7

4

8

5

6
7

6
7

-

-

-

-

-

-

-

-

207*
208*
1*
2
3*
4

165

-

-

C3
C4

174

5

177

6
7

183

5

B3
C5

6
7

A2
B4

8

8

C6

8
9
10

189
195
198

9

9

A3

-

11
12'

201

-

-

-

8

10

10

C7

13*
14

11

11

A4

15

207
210
213

186

-

-

-

-

9
10

12

12

A5

16

17

6
7

11
12

13
14

13
14

B7
A6

17
18

-

-

15

19

219
222

13

15

16
17

C8
A7
B8

20
21

225
234

18

9
10

I/O

-

-

-

32.
33.

I/O
I/O

-

-

-

-

34.

I/O

-

11

8

14

16

18

A8

22

237

35.

I/O

19

12

9

B9

I/O

20

13

10

17
18

19

36.

15
16

20

C9

23
24

249

30.
31.

4-230

246

August 6,1996 (Version 4.01)

~:XILINX
Pin Locations for XC5206 Devices
Description t

Pin

37.
38.
39.
40.
41.
42.
43.
44.
45.
46.

GNO
VCC
I/O
I/O
I/O
I/O
I/O
110
I/O
I/O
I/O
I/O
GNO

PC84

PQ100

VQ100

TQ144

PQ160

TQ176

PG191

PQ208

21
22
23
24

14
15
16
17
18

11
12
13
14
15

19
20
21
22
23
24

-

-

-

-

-

17
18
19
20
21
22

25
26

19
20

16
17

-

-

-

23
24
25
26
27

25
26
27
28
29

21
22
23
24
25
26
27
28
29
30
31
32
33

09
010
Cl0
Bl0
A9
Al0
All
Cll
Bll
A12
B12
A13
C12

-

-

-

-

-

30
31
32
33
34
35
36
37
38
39
40

34
35
36
37
38
39
40
41
42
43
44

A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18

25
26
27
28
29
30
31
32
33
34
35
36
37
38*
39*
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55
56
57
58
59
60
61
62
63
64
65*
66*
67
68
69
70
71
72
73
74
75

-

47.
48.
49.
50.
51.
52.
53.
54.
55.
56.

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Ml (I/O)
GNO
MO(I/O)

27

57.
58.
59.
60.
61.
62.
63.
64.
65.

VCC
M2 (I/O)
GCK2 (I/O)
I/O (HOC)
I/O
I/O
I/O
110 (LOC)
110
110
-

21
22

18
19

-----

28
29
30
31
32

28
29
30
31
32
33
34
35
36

23
24
25
26
27

20
21
22
23
24

-

-

-

-

-

-

33
34
35
36

28
29
30
31

25
26
27
28

-

-

-

37

32
33

29
30

37
38
39
40
--41
42
43
44

-

-

-

-

-

66.
67.
68.
69.
70.
71.
72.
73.

-

-

-

-

-

-

-

41
42
43
44
45
46
47
48
49
50

45
46
47
48
49
50
51
52
53
54

016
C16
B17
E16
C17
017
B18
E17
F16
C18

-

-

-

51
52
53
54
55

55
56
57
58
59
60
61
62
63

G16
E18
F18
G17
G18
H16
H17
H18
J18

-

1/0

-

-

-

110
I/O
I/O
110
I/O
I/O

38
39

34
35

31
32

-

-

-

-

-

-

36
37

33
34

50
51

56
57

August 6, 1996 (Version 4.01)

-

45
46
47
48
49

-

-

-

GNO
I/O

-

-

I

Boundary Scan Order

255
258
261
267
270
273
279
282
285
291

--

-~

-

-

I

294
297
303
306
309
315
318
321
330
333

-

-

336
339
348
351
354
360
363
372
375

378
384
387
390
396
399
402
408
4-231

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5206 Devices
t

Pin

Description

74.
75.

I/O
I/O (ERR, INIT)

vec
76.
77.

78.
79.
80.
81.
82.
83.
84.
85.

86.
87.
88.
89.
90.
91.
92.
93.

GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO

I/O
I/O
I/O
I/O
I/O
I/O
I/O
110
GNO

OONE

PC84

PQ100

VQ100

TQ144

PQ160

TQ176

PG19l

PQ208

Boundary Scan Order

40
41
42
43
44
45

38
39
40
41
42
43
44
45

35
36
37
38
39
40
41
42

52
53
54
55
56
57
58
59

58
59
60
61
62
63
64
65

411
414

-

-

-

46
47

43
44

-

-

60
61
62
63
64

66
67
68
69
70

J17
J16
J15
K15
K16
K17
K18
L18
L17
L16
M18
M17
N18
P18
M16

76

-

64
65
66
67
68
69
70
71
72
73
74
75
76

-

46
47

-

-

-

48
49

48
49

94.
95.
96.
97.
98.
99.
100.
101.

102.
103.
104.
105.
106.
107.
108.
4-232

PROG
1/0(07)
GCK3(1I0)
I/O
I/O
1/0(06)
I/O
I/O
I/O

GNO
I/O
I/O
I/O (05)
I/O (CSO)
I/O

77

78

-

-

-

-

-

-

-

71
73
74
75
76
77
78
79

79
80
81
82
83
84
85
86
87

T18
P17
N16
T17
R17
P16
U18
T16
R16

45
46

-

72

50
51
52

47
48
49

65
66
67
68
69
70
71

-

-

-

53

53

50

72

80

88

U17

-

-

-

-

-

-

81

89

R15

-

50
51
52

-

-

VCC

-

54
55
56
57

54

51

73

-

-

-

55
56
57

52
53
54

74
75
76

-

-

77

58
59

55
56

-

-

-

-

58

-

-

-

82
83
84
85
86
87
88
89
90

90
91
92
93
94
95
96
97
98

V18
T15
U16
T14
U15
V17
V16
T13
U14

-

-

-

-

-

99
100
101
102
103
104
105
106

T12
U13
V13
U12
V12
Tll
Ull
Vll

78
79
80

91
92
93
94
95

-

81
82
83
84
85
-

-

-

-

59

86

96

-

-

-

59
60

60
61

57
58

1/0

-

I/O

62

-

77

78
79
80
81
82
83
84
85
86
87
88
89
90
91*
92*
93
94
95
96
97
98
99
100
101
102*
103
104*
105*
106
107*
108
109
110
111
112
113
114
115
116
117*
118*
119
120
121
122
123
124
125
126

-

420
423
426
432
435
438
444
447
450
456

459
468
471
480
483
486
492
495

-

504
507
516
519
522
528
531
534

540
543
552
555
558
564
567

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5206 Devices
Description

t

PC84

PQ100

VQ100

TQ144

PQ160

TQ176

PG19l

PQ208

Boundary Scan Order

-

63

60

87

97

107

V10

127

570

I/O (04)

61

64

61

88

98

108

U10

128

576

I/O

62

65

62

89

99

T10

129

579

R10

130

R9

131

-

Pin
109.

110

110.
111.

VCC

63

66

63

90

100

109
110

GNO

64

67

64

91

101

111

112.

I/O (03)

65

68

65

92

102

112

T9

132

588

113.

I/O (AS)

66

93
94

113

104

114

U9
V9

133
134

591

I/O

66
67

103

114.

69
70

115.

I/O

-

-

95

105

115

V8

135

603

116.

I/O

-

116

U8

136

612

-

-

-

117.

I/O

-

-

118.

I/O (02)

67

71

68

96

106

72

69

97

107

119

-

98

108

120

99

109

121

100

110

-

119.

I/O

68

120.

I/O

-

121.

110

-

-

-

-

GNO

122.

I/O

-

-

600

117

T8

137

615

118

V7

138

618

U7

139

624

V6

140

627

U6

141

630

122

T7

142

-

-

-

143*

-

144*

-

-

-

111

123

U5

145

636

123.

I/O

112

124

T6

146

639

124.

I/O (01)

69

73

70

101

113

125

V3

147

642

125.

I/O (RCLK!3USY/ROY)

70

74

71

102

114

126

V2

148

648

-

-

-

103

U4

149

651

104

115
j 16

127

-

128

T5

150

654

151

660

152

663

126.

I/O

127.

110

128.

110 (00, OIN)

71

75

72

105

1.17

129

129.

I/O (OOUT)

72

76

73

106

118

130

U3
T4

CCLK

73

77

74

107

119

131

V1

153

VCC

74

78

75

108

120

132

R4

154

-

-

-

-

-

155"

-

-

-

-

-

-

-

I/O (TOO)

75

79

109

121

133

U2

159

GNO

76

80

76
77

110

122

134

R3

160

-

77

81

78

111

123

135

T3

161

78

82

79

112

124

136

U1

162

9
15

-

-

-

113

125

137

P3

163

18

114

138

R2

21

139
140

T2

164
165

27

N3

166

30

130.

-

WS)

-

156*
157"
158"

-

-

-

-

131.

I/O (AO,

132.

GCK4 (A 1, I/O)

133.

I/O

134.

I/O

135.

I/O (A2, CS1)

79

83

80

115

126
127

136.

I/O (A3)

80

84

81

116

128

-

117

129

141

P2

167

33

-

-

130

142

T1

42

-

-

-

16~

-

170*

137.

I/O

138.

110

-

GNO

-

139.

I/O

-

140.

I/O

-

141.

1I0(A4)

81

85

142.

I/O (A5)

82

86

143.

I/O

-

-

-

-

August 6, 1996 (Version 4.01)

-

-

-

169*

I

-

-

118

131

143

M3

171

119

132

144

P1

172

45

120

133

145

N1

173

51

82

121

134

146

M2

174

54

83

122

135

147

M1

175

57

-

-

148

L3

176

63

4-233

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5206 Devices
Pin

Description t

PC84

PQ100

TQ144

PQ160

TQ176

PG191

PQ208

Boundary Scan Order

-

136

149

L2

177

66

84

123

137

150

L1

178

69

85

124

138

151

K1

179

75

89

86

125

139

152

K2

180

78

90

87

126

140

153

K3

181

81

88

127

141

154

K4

182

-

I/O

145.

i/O

87

146.

I/O

88

147.

I/O (A6)

83

148.

I/O (A7)

84
1

91

GND

VQ100

-

144.

Notes:' indicates unconnected package pins.
t leading numbers refer to bonded pad, shown in Figure 22 or Figure 23.
Boundary Scan Bit 0 = TDO.T
Boundary Scan Bit 1 = TDO.O
Boundary Scan Bit 1056 = BSCAN.UPD

4-234

August 6, 1996 (Version 4.01)

~XIUNX
Pin Locations for XC521 0 Devices
Description

Pin

1.
2.
3.
4.
5.
6.

t

TQ144

PQ160

TQ176

PQ208

PG223

BG225

PQ240

2

128
129
130
131
132

142
143
144
145
146

155
156
157
158
159
160
161

183
184
185
186
187
188
189

J4
J3
J2
J1
H1
H2
H3

VCC"
E8
B7
A7
C7
07
E7

212
213
214
215
216
217
218
219'
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

VCC
I/O (A8)
I/O (A9)

;3

I/O

-

I/O

-

I/O
I/O

7.
8.

110 (A10)
I/O (A11)
VCC

9.
10.
11.
12.

I/O
I/O
I/O
. I/O

GNO
13.
14.
15.
16.
17.
18.
19.
20.
2122.
23.
24.

PC84

I/O
I/O
I/O

4

5
6

-

I/O (A13)
I/O
I/O
I/O
I/O
I/O (A14)
I/O (A15)

VCC

GCK1.(A16, I/O)
I/O (A17)
I/O
I/O
I/O (TDI)
I/O (TCK)
I/O
I/O
I/O
I/O
I/O
I/O

GNO
37.

I/O

August 6, 1996 (Version 4.01)

-

-

-

147
148

162
163

190
191

G1
G2

-

-

-

-

-

-

-

-

-

149
150
151

164
165
166

192
193
194
195
196
197
198
199
200

135
136
137

-

-

167
168
169
170
171

-

-

-

-

-

140
141
142
143
144

156
157
158
159
160

172
173
174
175
176

-

-

-

-

9
10
11

-

-

-

-

12

1

1

-

-

2
3
4
5
6
7

2
3
4
5
6
7
8
9

25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.

-

133
134

138
139

-

GNO

-

7
8

-

-

-

152
153
154
155

I/O
I/O (A12)

-

13
14

15
16

-

-

-

-

-

8
9

10
11

201
202
203
204
205
20S'
207'
208'

-

l'

1

2
3'
4
5
6

2
3
4
5
6
7
8
9

7

8
9
10
11
12
13

10
11

14
15

H4
G4
F1
E1
G3
F2
01
C1
E2
F3
02
F4
E4
B1
E3
C2
B2
03

-

A6
B6
VCC"
C6
F7
A5
B5
GNO"
06
C5
A4
E6
B4
05
A3
C4
B3
F6
A2
C3
VCC"

Boundary Scan
Order

111
114
117
123
126
129

135
138

141
150
153
162

165
171
174
177
183
186
189
195
198
201
210
213

-

-

-

-

-

-

04

GNO"

1

-

-

-

-

2
3
4
5
6
7
8
9
10
11
12
13
14
15

222
225
231
234
237
243
246
249
255
258
261
2S7

C3
C4
B3
C5
A2
B4
C6
A3
B5
BS
05
06
C7
A4

04
B1
C2
E5
03
Cl
02
G6
E4
01
E3
E2
GNO"
F5

I

-

270

4-235

XC5200 Field \?rogrammable Gate Arrays

Pin Locations for XC5210 Devices
Description t

\?in

38.
39.
40.

1/0
1/0 (TMS)
1/0

vec
41.
42.

1/0
1/0

·
43.
44.
45.
46.
47.
48.

55.
56.
57.
58.
59.
60.

74.

TQ176

\?Q208

\?G223

BG225

\?Q240

·

10
11
12

12
13
14

12
13
14

16
17
18

A5
87
A6

·
·

·
·

·
·
·

·

·
·

·

E1
F4
F3
VCC**
F2
F1

16

17
18

·
·

·

·

·
·
13
14
15
16
17
18
19
20
21
22

15
16
17
18
19
20
21
22
23
24

·
·

·

·
·
·
·

·
·
·
·

·

23
24
25
26
27

25
26
27
28
29

29
30
31
32
33

33
34
35
36
37

·

·
·

·
·

·
·

·
·

·

30
31
32
33
34
35
36
37
38
39
40

34

38
39
40
41
42
43
44
45
46
47
48
49
50
51*
52*
53*
54*
55

·

·

1/0
1/0

1/0
1/0

I/O

·
19
20
21
22
23
24

·

1/0
1/0

·

I/O
·
1/0
1/0

·
·
·
·

VCC

·

·

1/0
1/0

25
26

I/O

·

1/0

·
·

1/0
1/0
1/0
1/0

·
·
·

I/O
110

·
·

·

27

28
29
30
31
32

28
29
30
31
32
33
34
35
36

·

·

·
·
·

·

33

37

1/0
1/0
1/0
1/0
1/0
1/0

M1 (1/0)
GNO
MO(I/O)

·

·

·
VCC

·

·

I/O

·

4·236

\?Q160

·

GNO
61.
62.
63.
64.
65.
66.
67.
68.
69.
70.
71.
72.
73.

TQ144

1/0
1/0
1/0

GNO
VCC
49.
50.
51.
52.
53.
54.

\?C84

·

·

·
·

·
·
·
·

·
·

·

07
08

K4
L3
M1
K5
M2
L4
N1
M3
N2
K6
P1
N3
GNO**
P2

18
19
20
21
22*
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37*
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

·
·

·

·

·
·

·

·

15
16
17
18
19
20
21
22
23
24
25
26
27
28

19
20
21
22
23
24
25
26
27
28
29
30
31
32

C8
A7
B8
A8
B9
C9
09
010
C10
B10
A9
A10
A11
C11

G4
G3
G2
G1
G5
H3
GNO**
VCC**
H4
H5
J2
J1
J3
J4

·

·

·

011
012

J5
K1
VCC**
K2
K3
J6
L1
GNO**

·

·
·

·
35
36
37
38
39
40
41
42
43
44

·

·

·
·
·

·
·
·

41

45

·

·

B11
A12
B12
A13
C12
013
014
B13
A14
A15
C13
B14
A16
B15
C14
A17
B16
C15
015
A18
·

L2

273
279
282

·
285
291

·
294
297
306
309
318
321

·
327
330
333
339
342
345

·
351
354
357
363
366
369

·
375
378
381
387
390
393
399
402
405
411
414
417
426

·
429

·

·
016

17

Boundary Scan
Order

·

·

VCC**

61

·

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC521 0 Devices
Description t

Pin
75.
76.
77.

78.
79.
80.
81.
82.
83.
84.
85.
86.
87.
88.
89.
90.
91.
92.
93.

M2(1I0)
GCK2 (110)
110 (HOC)
I/O
I/O
I/O
I/O (LOC)
I/O
I/O
I/O
110
I/O
I/O
GNO
I/O
I/O
110
I/O
VCC
I/O
I/O

100.
101.
102.
103.
104.
105.

TQ144

PQ160

TQ176

PQ208

PG223

BG225

PQ240

34
35
36

37

38
39
40
41
42
43
44

·

·

42
43
44
45
46
47
48
49
50

46
47
48
49
50
51
52
53
54

56
57
58
59
60
61
62
63
64
65
66

C16
817
E16
C17
017
818
E17
F16
C18
018
F17
E15
F15
G16
E18
F18
G17
G18

M4
R2
P3
L5
N4
R3
P4
K7
M5
R4
N5
P5
L6
GNO*'
R5
M6
N6
P6
VCC*'
R6
M7

62
63
64
65
66
67
68
69
70
71
72
73
74
75
76

·
·

·

·
·
·
·
·
38
39
·

I/O
I/O
I/O
I/O
I/O
I/O (ERR, !NiT)
vec
GNO
I/O
I/O
I/O
I/O
I/O
I/O

108.
109.
110.
111.
112.
113.
114.
115.
, 116.

I/O
I/O
vce
110
I/O
I/O
110
GNO
I/O
I/O
I/O
110
I/O

August 6, 1996 (Version 4.01)

·

45
46
47
48
49

51
52
53
54
55

·

·

·

·

·

·

·

60
61

72
73

H16
H17

·
·
·

·

·

.

·

G15
H15
H18
J18
J17
J16
J15
K15
K16
K17
K18
L18
L17
L16

N7
P7
R7
L7
N8
P8
vce'*
GNO"
L8
P9
R9
N9
M9
LSI

·

·

40
41
42
43
44
45

·
·

·
·

'.

·

56
57
58
59
60
61
62
63
64
65

·

·

·

·

-

-

·
·

·
-

46
47

60
61
62
63
64

66
67
68
69
70

·

-

·
·

·
·
50
51
52
53
54
55
56
57
58
59

·

·

·

.

106.
107.

·
·
·
·

·

.

94.
95.
96.
97.
98.
99.

PC84

55
56
57
58
59

62
63
64
65
66
67
68
69
70
71
72
73

·
·
·
·
74
75
76
77

78

·

-

·

·

74
75
76
77

78
79
80
81
82
83
84
85

·

-

--'"

71

79

·

.

L15
M15

R10
P10
VCC*'
N10
K9
R11
P11
GNO**
M10
N11
R12
L10
P12

·

-

86
87
88
89
90

M18
M17
N18
P18
M16
N15
P15
N17
R18
T18

·
·
-

-

67
68
69
70
71

91
92
93

77

78
79
80
81
82
83'
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98'
99
100
101
102
103
104
105
106
107
108
109
110
1110

Boundary Scan
Order
432
435
444
447
450
456
459
462
468
471
474
480
483

I

·
486
492
495
504
·

507
510
·

5113
519
522
528
531
534
·

540
543
546
552
555
558
·

564
567

570
576
579
588

·
591
600
603
606
612

4-237

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5210 Devices
Description t

Pin

117.
118.
119.
120.
121.
122.
123.

1/0
1/0

I/O
1/0
1/0
1/0
1/0

GND
DONE

--

PC84

PQiS0

TQ17S

PQ208

PG223

BG225

PQ240

65
66
67
68
69
70
71

72
73
74
75
76
77
78
79

80
81
82
83
84
85
86
87

P17
N16
T17
R17
P16
U18
T16
R16

Mll
R13
N12
P13
Kl0
R14
N13
GND"

112
113
114
115
116
117
118
119

615
618
624
627
630
636
639

-

-

U17

P14

120

-

-

R15

VCC"

121

-

-

-

-

M12
P15
N14
Ll1
M13
N15
M14
Jl0
L12
M15
L13
L14
Kl1
GND"
L15
K12
K13
K14
VCC"
K15
J12

122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143'
144
145
146
147
148
149
150
151
152
153
154
155
156
157

48
49

50
51
52

-

-

-

73

81

89

82
83
84
85
86

90
91
92
93
94

94
95
96
97
98
99
100
101
102'
103
104'
105'
106
107'
108
109
110
111
112

-

-

-

87
88
89
90

95
96
97
98

-

-

-

81

91

99

113
114
115
116
117
118
119

-

-

-

53

72

-

-

VCC

54

-

-

PROG
1/0 (D7)
GCK3 (1/0)
I/O

55
56
57

74
75
76
77
78

80

88

-

-

GND

-

136.
137.
138.
139.

1/0
1/0
1/0
1/0

-

-

-

-

-

-

82
83

92
93

100
101

120
121

V18
T15
U16
T14
U15
R14
R13
V17
V16
T13
U14
V15
V14
T12
R12
Rll
U13
V13

140.
141.

1/0 (D5)
1/0 (CSO)

84
85

94
95

102
103

122
123

U12
V12

-

-

124
125
126
127
128
129
130
131
132
133
134
135
136
137

Tl1
Ull
Vll
Vl0
Ul0
Tl0
Rl0
R9
T9
U9
V9
V8
U8
T8

J13
J14
J15
Jll
H13
H14

124.
125.
126.
127.
128.
129.
130.
131.
132.
133.
134.
135.

1/0
1/0
1/0
1/0 (D6)
1/0
1/0
1/0
1/0
1/0

VCC

142.
143.
144.
145.
146.
147.

1/0
1/0
1/0
1/0
1/0 (D4)
1/0

vec
148.
149.
150.
151.
152.
153.

4-238

GND
1/0 (D3)
1/0 (RS)
1/0
1/0
1/0
1/0

-

58

-

-

79
80

59
60

-

-

61
62
63
64
65
66

-

Boundary Scan
Order

TQ144

-

-

86
87
88
89
90
91
92
93
94
95

96
97
98
99
100
101
102
103
104
105

-

-

104
105
106
107
108
109
110
111
112
113
114
115
116
117

vee"
GND"
H12
Hl1
G14
G15
G13
G12

-

648
651
660
663
666
672
675
678
684
687
690
696

699
708
711
714
720
723
726
732
735
738
744
747

756
759
768
771
780
783
. _....-

August 6,1996 (Version 4.01)

~XILINX
Pin Locations for XC521 0 Devices
Description t

Pin

154.
155.

PC84

TQ144

PQ160

TQ176

PQ208

PG223

BG225

PQ240

138

V7

Gll

158'
159

139

U7

F15
VCC'*

160

-

-

-

I/O (02)

67

96

I/O

118
119

Boundary Scan
Order

-

68

97

106
107

VCC

-

-

-

-

161

-

156.
157.

I/O

-

98

108

120

140

V6

F14

162

795

I/O

-

99

109

121

141

158.
159.

I/O
I/O
GNO

-

-

U6
R8

F13
Gl0

163
164

798
804

R7
110

122

142

165
166

160.

I/O

810

I/O

-

R5

168

816

162.
163.

I/O
I/O

143
144

V5
V4

E13
015

819
822

I/O

-

-

164.
165.

-

-

E14
F12

167

161.

-

T7
R6

E15
GNO**

807

100

166.

I/O
I/O (01)

167.
168.

I/O (RCLK-8USY/ROY)
I/O

169.

I/O

170.

I/O (00, OIN)
I/O (OOUT)

786
792

111

123

145

U5

Fll

169
170
171

124

146

T6

014

172

831

101

112
113

125

147

E12

102
103

114
115

148
149

173
174

834
840
843

-

104

116

126
127
128

V3
V2

69
70

150

U4
T5

C15
013

175

-.--.~

C14
FlO

176

846

- ..

71

105

117

129

72

106

118

130

151
152

U3
T4

73
74

107

119
120

153
154

Vl
R4

C13
VCC'*

179

108

131
132

-

-

-

-

-

-

-

157*

-

-

158*

-

-

-

155*
156*

-

I/O (TOO)
GNO
I/O (AD, WS)

75
76

109
110

121
122

133
134

159
160

U2
R3

A15
GNO'*

77

111

123

135

T3

A14

182
183

174.
175.

GCK4 (Al, I/O)

78

112

124

136

161
162

Ul

813

184

113

125

137

163

P3

Ell

185

176.
177.

I/O
I/O (CS1, A2)

79

114
115

126
127

138
139

164
165

R2
T2

C12
A13

186
187

27

178.

I/O (A3)

80

116

128

140

166

N3

812

188

30

179.

I/O
I/O

-

-

P4

F9

189

33

180.

-

-

I/O

117

129

141

39
42

182.
183.

I/O
I/O

-

130

142

-

-

167
168
169

011
A12

190

181.

N4
P2
T1
Rl

184.

I/O

-

-

170

N2

171.

CCLK
VCC

172.
173.

I/O

GNO
185.
186.
187.

I/O
I/O

-

-

-

-

I/O
VCC

189.
190.

I/O (A4)
110 (A5)

August 6,1996 (Version 4.01)

81
82

815

177
178

855
-.--~-,.,,-

858

180

181

Cl1
811

191
192
193

El0
GNO*'

194
195*

-

9
15
18
21

45
51
54

118

131

143

171

M3

-

196

-

119
120

132
133

144
145

172
173

Pl
Nl

All
010

197
198

57
66

Cl0

199

69

-

-

M4

-

L4

200

75

201

-

121
122

134

202
203

78
81

1/0

188.

135

I

828

-

-

-

810
VCC**

146
147

174
175

M2
Ml

Al0
09

4-239

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5210 Devices
Pin

Description t

191. .
192.
193.
194.
195.
196.

1/0
1/0
1/0
1/0
1/0 (A6)
1/0 (A7)
GNO

...

PC84

T0144

P0160

T0176

P0208

-

-

136

149

177

-

123

137

150

178

124

138.

151

179

83

125

139

152

84
1

126

140

127

141

-

148

176

Boundary Scan
Order

BG225

P0240

-

-

204'

-

L3

C9

205

B7

L2

B9

206

90

L1

A9

207

93

K1

E9

208

99

180

K2

CB

209

102

153

1B1

K3

BB

210

105

154

1B2

K4

GNO**

211

-

-

PG223

Notes: * Indicates unconnected package pins.

t·

leading numbers refer to bonded pad, shown in Figure 24 or Figure 25.
** Pins labeled VCC** are internally bonded to a VCC plane within the BG225 package. The external pins are: B2, 08, H15, R8,
B14, R1, H1, and R15.
Pins labeled GNO** are internally bonded to a ground plane within the BG225 package. The external pins are: A1, 012, G7,
G9, H9, HB, H10, J8, KB, A8, F8, G8, H2, H7, H9, J7, J9, M8.
Boundary Scan Sit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO

4-240

August 6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5215 Devices
Description t

Pin

1.
2.
3.
4.
5.
6.
7.
8.

VCC
I/O (A8)
I/O (A9)
I/O
I/O
I/O

BG225

BG352

Boundary Scan Order

38
37
36
35
34
33
32

VCC"
E8
B7
A7
C7
07
E7

vec"
014
e14
A15
B15
e15
015

138
141
147
150
153
159

A6
B6

A16
B16

162
165

-

147
148

190
191

-

-

I/O (Al0)
I/O (All)

I/O
1/0

I/O
I/O
I/O
I/O
GNO
I/O

-

-

149
150
151

192
193
194

I/O
I/O
I/O
I/O
I/O (A12)
I/O (A13)
I/O
I/O

152
153
154

195
196
197
198
199

-

-

155

200

-

-

1/0

I/O
110
1/0

I/O (A14)
I/O (A15)
VCC

156
157
158
159
160

-

-

GNO

1

-

-

GCKl (A16, I/O)
I/O (A17)
I/O
I/O
I/O (TOI)

2
3
4
5
6

August 6,1996 (Version 4.01)

201
202
203
204
205
206*
207*
208'
l'
2
3'
4
5
6
7
8

K2

K3
K5
K4
Jl
J2

-

-

-

222

H2
Gl
El

-

-

223
224
225
226
227

H3
G2
H4
F2
Fl
H5
G3
01
G4
E2
F3
G5

31
30
29'
28'
27
26
25
24'
23
22
21
20
19
18
17
16
15
14
13
12

-

11'

Cl
F4
E3
02
C2
F5
E4
03
C3
A2

10
9
8
7
6
5
4
3
2
1

A3
C4
B3
F6
A2
C3
VCC"

-

-

-

-

-

304

GNO'*

GNO**

-

303
302
301
300
299

04
Bl
C2
E5
03

023
C25
024
E23
C26

270
273
279
282
285

Hl
J3

-

-

-

-

1/0

-

31.
32.
33.
34.
35.

HQ304

Kl

-

VCC

22.
23.
24.
25.
26.
27.
28.
29.
30.

PG299

212
213
214
215
216
217
218
219'
220
221

-

-

15.
16.
17.
18.
19.
20.
21.

HQ240

183
184
185
186
187
188
189

1/0

-

11.
12.
13.
14.

HQ208

142
143
144
145
146

-

9.
10.

PQ160

228
229
230
231
232
233

234
235
236
237
238
239
240

1

Bl

-

-

2
3
4
5
6

04
B2
B3
E6
05

-

VCC"

e17
B18
vec"

171
174

-

C6
F7
A5
B5
GNO*'

06
C5
A4

E6
B4
05

-

C18
017
A20
B19
GNO**
C19
018
A21
B20
C20
B21
B22

177
183
._.-------_.-_.
186
189

.. _---.

-e.

I

--_.

195
198
201
207
210
213
219

C21
020
A23
021
C22
B24
C23
022
C24
vce"

222
225
234
237
243
246
249
258
261

-

-

-

-_._..,_... -

4-241

XC5200Fieid Programmable Gate Arrays

Pin Locations for XC5215 Devices
Description

Pin

36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.

1/0 (TCK)

47.
48.
49.
50.

1/0
1/0
1/0 (TMS)
1/0

1/0
1/0
1/0
1/0
1/0
1/0
1/0

110
110
GNO

1/0
1/0

-

53.
54.
55.
56.
57.
58.
59.
60.

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

GNO
VCC
61.
62.
63.
64.
65.
66.
67.
68.

69.
70.

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0

VCC
71.
72.
73.
4-242

PQ160

HQ208

HQ240

PG299

HQ304

BG225

BG352

Boundary Scan Order

7

9

7

-

298
297
296
295
294
293
292
291
290
289
288
287
286
285
284
283
282
281*
280
279

Cl

-

C4
A3
06
E7
B4
C5

294
297
303
306
309
315
318
321
327
330
333

GNO**
F5
El
F4
F3
VCC*·

E24
F24
E25
026
G24
F25
F26
H23
H24
G25
G26
GNO**
J23
J24
H25
K23
VCC··

F2
Fl

L24
K25

354
357

-

L25
L26
M23
M24
M25
M26
N24
N25
GNO*·
VCC··
N26
P25
P23
P24
R26
R25
R24
R23

363
366
369
375
378
381
390
393

110

VCC
51.
52.

t

1/0
1/0
1/0

8
9

-

10
11
12
13

-

-

-

-

-

10
11
12
13
14

14
15
16
17
18

-

8
9
10
11
12
13

14
15
16
17
18
19
20
21
22·

-

-

15
16
17
18
19
20
21
22
23
24

19
20
21
22
23
24
25
26
27
28
29
30
31
32

-

-

-

-

-

-

C8
E9

-

B8
A8
C9
B9
El0
A9
010
Cl0
Al0
All
Bl0
Bll
Cl1
Ell
011
A12
B12
A13

-

-

38
39

E12
B13

37·

-

25
26
27

23
24
25
26
27
28
29
30
31
32
33
34
35
36

-

-

-

07
C6
E8
B5
A5
B6
08
C7
B7
A6

-

-

A4

33
34
35

40
41
42
43

A16
A14
C13
B14

278*
277·
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258*
257*
256
255
254·
253
252
251
250

-

02
G6
E4
01
E3
E2

-

G4
G3
G2
Gl
G5
H3
GNO··
VCC··
H4
H5
J2
Jl
J3
J4

339
342
345
351

--

-

399
402
405
411
414
417
423
426

J5
Kl

~.

T26
T25

429
435

VCC··
K2
K3
J6

VCC··
U24
V25
V24

438
441
447

August6, 1996 (Version 4.01)

~XILINX
Pin Locations for XC5215 Devices
Description t

PQ160

HQ208

HQ240

PG299

HQ304

BG225

BG352

Boundary Scan Order

I/O

28

36

44

013

249

Ll

U23

450

GNO

29

37

45

A15

248

GNO"

GNO"

-

-

-

815

247

Y26

453

-

E13

246

-

46

C14

245

47

A17

38

48

014

49
50

Pin
74.
75.

I/O

76.

I/O

77.

110

78.

I/O

79.

I/O

80.

I/O

-

81.

I/O

30

39
40

82.

I/O.

31

41

83.

I/O

-

-

-

W25

459

W24

462

244

L2
K4

V23

465

243

L3

AA26

471

816

242

Ml

Y25

474

C15

241

K5

Y24

477

51

E14

240

M2

AA25

483

-

A18

239

-

AB25

84.

I/O

-

015

238

-

AA24

'486
489

85.

I/O

32

42

52

C16

237

L4

Y23

495

86.

I/O

33

43

53

817

236

Nl

AC26

498

87.

VO

34

44

54

818

235

M3

AA23

501

88.

I/O

35

45

55

E15

234

'. N2

AB24

507

89.

I/O

36

46

56

016

233

K6

A025

510.

90.

I/O

37

57

C17

232

Pl

AC24

513

91.

Ml (I/O)

38

47
48

58

A20

231

N3

A823

522

GNO

39

49

59

A19

230

GNO"

GNO"

MO(I/O)

40

50

60

C18

229

P2

A024

-

.' 51'

-

-

-

-

-

-

52'

-

53'
54'

-

-

-

-

-

--_... ,.
525 _...

"---

-

VCC

41

55

61

820

228

VCC"

VCC"

93.

M2(1/0)

42

56

62

017

227

M4

AC23

528

94.

GCK2(1/0)

43

57

63

819

226

R2

AE24

531

95.

I/O (HOC)

44

58

64

C19

225

P3

A023

540

96.

I/O

45

59

65

F16

224

AC22

543

97.

I/O

46

60

66

E17

223

L5
N4 .

AF24

546

98.

I/O

47

61

67

018

222

R3

A022

552

48

62

68

C20

221

P4

AE23

555

-

-

F17

220

G16

219

99,

I/O (LOC)

100,

I/O

101.

1/0

102.

1/0

103.

110

104.

VO

105.

1/0

106.
107,

I/O

1/0

108.

1/0

109.

I/O

.

,

••

.

-

AE22

558

AF23

564
567

49

63

69

019

218

K7

A020

50

64

70

E18

217

M5

AE21

570

65

71

020

216

R4

AF21

576

' 66

72

G17

. 215

N5

AC19

579

-

73

F18

214

P5

A019

582

74

H16

213

L6

AE20

588

-

E19

212

F19

211

-

.'.

-

\

-

I

-

AF20

591

AC18

594

GNO

51

67.

75

E20

210

GNO"

GNO"

-.

I/O

52

68

76

H17

209

A018

600

111.

I/O

53

69

77

G18

AE19

603

112.

1/0

54

70

78

G19

208
. 207

R5
' M6
N6

AC17

606

I/O

55

71

79

H18

·206

P6

A017

612

-

-

-

-

-

205'

-

-

80

F20

72

81

J16

110.

113.

.

VCC
114.

I/O

j

August 6, 1996 (Version 4:01)

204
. ,203

I
.•.

~

92.

,

VCC"

VCC"

-

R6

AE17

615

_.....

".

.

4-243

XC520a Field Programmable Gate Arrays

Pin Locations for XC5215 Devices
Descrfption t

Pin

115.

"PQ160

-

110

-

,

-

-

116.
117.
118.
119.
120'.
121.
122.
123.

110
1/0

110
110
110
1/0
1/0
1/0 (EF\R, fNlf)

VCC
GND
124.
125.
126.
127.
128.
129.
130'.
131.

132.
133.

1/0
I/O
1/0
1/0
1/0
1/0
1/0
1/0

1/0
1/0

VCC
134.
135.
136.
137.

1/0
1/0
1/0
1/0

GND
138.
139.
140'.
141.
142.
143.
144.
145.
146.
147.
148.
149,_
150'.
151.
152.
153.

1/0
1/0

110
1/0
1/0

110
1/0
1/0
1/0
1/0.
1/0
1/0
1/0
110
1/0
1/0

GND
4-244

,

HQ208

HQ240

PG299

HQ304

BG225

BG352

Boundary Scan Order

73

82
83'

G2D

20'2

M7

AE16

618

-

-

-

-

-

-

-

-

-

AF16
AC15
AD15
AE15
AF15
AD14
AE14
AF14
VCC"
GND"
AE13
AC13
AD13
AF12
AE12
AD12
AC12
AF11

624
627
630'
636
639
642
648
651

-

-

-

.s6
57
58
59
",60'
61
62
63
64
65

74
75
76
77
,,78
79
80'
81
82
83

84
85
86
87
88
89
90'
91
92
93
94
95
96
97

-

84

-

85

-

99
10'0'
10'1

-

-

66
67
68
69
70'

86
87
88
89
90'

10'2
10'3
104
10'5
10'6

-

-

-

-

-

98'

-

-

10'7
10'8
10'9
110'
111
112

71
72

91
92
93
94

-

.

-

-

95
96
97
98
99
10'0'
10'1

113
114
115
116
117
118
119

73
74
75
'76
77
78
79

H2O'
J18
J19
K16
J2D
K17
K18
K19
L2D
K2D
L19
L18
L16
L17
M2D
M19
N2D
M18

-

-

N19
P2D
. T2D

N18
P19
N17
' R19
R2O'
N16
P18
U2O'
P17
T19
R18
P16
V2O'
R17
T18
U19
V19
R16
T17
U18
X2D
W2D

20'1'
20'0"
199
198
197
196
195
194
193
192
191
190'
189
188
187
186
185
184
183
182

181'
180"
179
' 178
177
176'
175
174
173
172
171
170'
169
168
167
166
165
164
163
162
"161
160'
159
158
157
156
155
154

N7
P7
R7
L7
N8
P8
VCC"
GND"
L8
P9
R9
N9
M9
L9

-

-

-

R1D
P1D
VCC"

AE11
AD11
VCC"

N1D
K9
R11
P11
GND"

M1O'
N11
R12
L1D
P12
M11

R13
N12
P13
K1O'
R14
N13
GND"

AE9
AD9
AC1D
AF7
GND"
AE8
AD8
AC9
AF6
AE7
AD7
AE6
AE5
AD6
AC7
AF4
AF3
AD5
AE3
AD4
AC5
GND"

-

660'
663
672
675
678
684
687
690'

-

-

696
699

70'2
70'8
711
714

720'
723
726
732
735
738
744
747
750'
756
759
768
771
774
780'
783

-

August 6; 1996 (Version 4.01)

~XIUNX
Pin Locations for XC5215 Devices
Description t

Pin

DONE

PQ160

HQ208

HQ240

-

102·

-

80

103
104·

120

-

105·
vee

PG299

HQ304

BG225

-

-

V18

153

P14

-

-

-

-

X19

152

vee··

BG352

Boundary Scan Order

AD3

-

vee··

-

-

-

81

106
107·

121

-

-

PROG

82

108

122

U17

151

M12

Ae4

-

154.

1/0 (07)

83

109

123

W19

150

P15

AD2

792

155.

GeK3(1/0)

84

110

124

W18

149

N14

Ae3

795

156.

1/0

85

111

125

T15

148

L11

AB4

804

157.

1/0

86

112

126

U16

147

M13

AD1

807

158.

1/0

V17

146

N15

AA4

810

110

128

X18

145

M14

AA3

816

160.

1/0

-

U15

144

-

AB2

819

161.

1/0

-

127

159.

-

-

T14

143

-

Ae1

828

162.

1/0(06)

87

113

129

W17

142

J10

Y3

831

163.

1/0

88

114

130

V16

141

L12

AA2

834

-

-

164.

1/0

89

115

131

X17

140

M15

AA1

840

165.

1/0

90

116

132

U14

139

L13

W4

843

166.

1/0

-

117

133

V15

138

L14

W3

846

167.

1/0

-

118

134

T13

137

K11

Y2

852

168.

1/0

136

855

W15

135

-

Y1

1/0

-

W16

169.

-

858

91

119

135

X16

134

GNO··

V4
GND··

-

136

U13

133

L15

V3

864
867
870

GNO
170.

1/0

171.

1/0

-

-

137

V14

132

K12

W2

172.

1/0

92

120

138

W14

131

K13

U4

1/0

93

121

139

V13

130

-

-

140

X15

K14
vee··

U3
vee··

-

129
128·

-

-

173.

vee

1/0 (05)

94

122

141

T12

127

K15

V2

879

95

123

142

X14

126

J12

V1

882

143·

-

125·

-

-

-

X13

123

T1

888

176.

1/0

177.

1/0

178.

110

179.

1/0

180.

1/0

96

181.

1/0

97

182.

1/0(04)

183.

184.

-

-

-

124·

V12

122

-

R4

891

144

W12

121

J13

R3

894

125

145

T11

120

J14

R2

900

126

146

X12

119

J15

R1

903

127

147

U11

118

J11

P3

906

98

128

148

V11

117

H13

P2

912

1/0

99

129

149

W11

116

P1

915

vee

100

130

150

X10

115

H14
vee··

vee··

-

GNO

101

131

151

X11

114

GNO··

GND··

-

1/0 (03)

102

132

152

W10

113

H12

N2

924

124

185.

I/O(RS)

103

133

153

V10

112

H11

N4

927

186.

1/0

104

134

154

T10

111

G14

N3

936

187.

1/0

105

135

155

U10

110

G15

M1

939

188.

1/0

-

136

156

X9

109

G13

M2

942

189.

1/0

137

157

W9

108

G12

M3

948

August 6, 1996 (Version 4.01)

----

-

1I0(CSO)

-

.. -"

876

174.

-

_..... _" .. __ .'n •

-

175.

-

I

4-245

XC5200 Field Programmable Gate Arrays

Pin Locations for XC5215 Devices
Description

Pin

190.
191.

t

PQ160

HQ208

HQ240

-

I/O

-

1/0

-

192.
193.

1/0 (D2)
1/0

106
107

194.
195.
196.
197.
198.
199.
200.
201.
202.
203.
204.
205.
206.
207.
208.
209.
210.
211.
212.
213.

214.
215.
216.
217.
218.
219.
220.
221.
222.
223.
224.
225.
226.
227.
4-246

108
109

140
141

GND

110

142

-

-

-

-

-

143
144
145
146
147
148

-

(D1)
(RCLK-BU8Y/RDY)

(DO, DIN)
(DOUT)
CCLK
VCC

110 (TDO)
GND
110 (AO, W8)
GCK4 (A 1, I/O)
1/0
1/0
1/0 (A2, C81)

110 (A3)

111
11.2
113
114

159
160
161

W8
X7
X5

162
163
164
165
166

V8
W7
U8
W6
X6
T8
V7
X4
U7
W5
V6
T7
X3
U6
V5
W4
W3
T6
U5
V4
X1
V3
W1

167
168
169
170
171
172
173
174

-

-

-

115
116
117
118
119
120

149
150
151
152
153
154
155156157158'
159
160
161
162
163
164
165
166

175
176
177
178
179
180

121
122
123
124
125
.126
127
128

1/0
1/0
1/0
1/0
1/0
1/0

129
130

1/0

-

107
106

158*

138
139

1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0

HQ304

X8
V9

-

-

VCC

PG299

167
168
169

-

-

-

-

-

-

181
182
183
184
185
186
187
188

U4
X2
W2
V2
R5
T4
U3
V1
R4
P5
U2
T3
U1
P4
R3

189
190
191
192
193

105'
104'
103
102
101
100'
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77

-

I·

76
75
74
73
72
71
70
69
68
67
66
65
64
63
62

BG225

G11
F15
VCC**

BG352

Boundary Scan Order

M4
L1

951
954

J1
K3
VCC*'

960
963

-

-

F14
F13
G10
E15
GND**

D13
C14
F10
B15
C13
VCC--

J2
J3
K4
G1
GND**
H2
H3
J4
F1
G2
G3
F2
E2
F3
G4
D2
F4
E3
C2
D3
E4
C3
VCC"

-

-

-

-

-

-

E14
F12
E13
D15
F11
D14
E12
C15

A15
GND**
A14
B13
E11
C12
A13
B12

F9
D11
A12
C11
B11

D4
GND*B3
C4
D5
A3
D6
C6
B5
A4

C7
B6
A6
D8
B7

966
972
975
978
984
987
990
996
999
1002
1008
1011
1014
1020
1023
1032
1035
1038
1044
1047

0
9
15
18
21
27
30
33
39
42
45
51
54
57

August 6, 1996 (Version 4.01)

~:XIUNX
Pin Locations for XC5215 Devices
Description

Pin
228.
229.
230.
231.
232.
233.
234.

t

liD
liD
liD

PQ160

HQ208

HQ240

PG299

HQ304

BG225

BG352

Boundary Scan Order

-

170

194

N5

61

E10

A7

63

-

195

T2

60

-

09

66

-

R2

59

-

C9

69

-

GNO

131

171

196

T1

58

GNO"

GNO"

-

110
liD
110
110

132

172

197

N4

57

A11

88

75

133

173

78

236.

liD
liD

238.
239.
240.
241.
242.
243.
244.

1I0(A4)
liD (A5)
liD
liD
liD
liD
110 (A6)
110 (A7)
GNO

56

010

010

P2

55

C10

C10

81

200

N3

54

810

89

87

-

53'

-

201

R1

52

VCC"

VCC"

-

-

M5

51

811

90

P1

50

A11

93

-

49'

-

-

-

-

48'

-

134

174

202

N1

47

A10

012

99

135

175

203

M3

46

09

C12

102

-

-

204'

-

-

176

205

M2

45

C9

812

105

136

177

206

L5

44

89

A12

137

178

207

M1

43

A9

C13

138

179

208

L4

42

E9

813

139

180

209

L3

41

C8

A13

126

140

181

210

L2

40

88

814

129

141

182

211

L1

39

GNO"

GNO"

237.

P3

-

VCC
235.

198
199

-

-

I

~ ~~~: ~--I
117

--

I

Notes:' Indicates unconnected package pins.
t leading numbers refer to bonded pad, shown in Figure 26, Figure 27 or Figure 28.
** Pins labeled VCC" are internally bonded to a VCC plane within the 8G225 and 8G352 packages. The external pins for the
8G225 are: 82,08, H15, R8, 814, E1, and R15. The external pins for the 8G352 are: A1O, A17, 82, B25, 013, 019,D7,
G23, H4, K1, K26, N23, P4, U1, U26, W23, Y4, AC14, AC20, AC8, AE2, AE25, AF10, and AF17.
Pins labeled GNO** are internally bonded to a ground plane within the BG225 and BG352 packages. The external pins for
the BG225 are: A1, 012, G7, G9, H9, H8, H10, J8, K8, A8, F8, G8, H2, H7, H9, J7, J9, M8. The external pins for the BG352
are: A 1, A2, A5, A8, A14, A 19, A22, A25, A26, B1, B26, E1, E26, H1, H26, N1, P26, W1, W26, A81, AB26, AE1, AE26, AF1,
AF13, AF19, AF2, AF22, AF25, AF26, AF5, AF8.

Boundary Scan Bit 0 = TOO.T
Boundary Scan Bit 1 = TOO.O
Boundary Scan Bit 1056 = BSCAN.UPO

August 6, 1996 (Version 4.01)

4-247

XC5200 Field Programmable Gate Arrays

Product Availability
PINS

84

100

100

144

156

160

176

191

208

208

223

225

240

240

299

304

352

TYPE

Plast.

Plast.

Plast.

Plast.

Ceram.

Plast.

Plast.

Ceram.

Plast.

Ceram.

Plast.

High-

High-

PQFP

VQFP

TQFP

Pi3A

PQFP

TQFP

PGA

PQFP

PGA

BGA

Pert.
QFP

Plast.
PQFP

Ceram.

PLGG

HighPerf.

PGA

Perf.

Plast.
BGA

PQ208

PG223

BG225

HQ240

PQ240

PG299

HQ304

BG352

GI

QFP
GODE
XG5202

XG5204

XG5206

XG5210

XG5215

-6

PG84

PQ100

V0100

TQ144

PG156

GI

GI

GI

GI

GI

P0160

-5

GI

GI

GI

GI

GI

-4

(GI)

(GI)

(GI)

(GI)

(GI)

-3

(GI)

(GI)

(GI)

(GI)

(GI)

-6

GI

GI

GI

GI

GI

-5

GI

GI

GI

GI

GI

GI

-4

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

T0176

PG191

HQ208

QFP

GI

-3

(GI)

(GI)

(GI)

(GI)

-6

GI

GI

GI

GI

GI

GI

GI

-5

GI

GI

GI

GI

GI

GI

GI

GI

-4

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

GI

-3

(GI)

(GI)

(GI)

(GI)

-6

GI

GI

GI

GI

GI

GI

GI

GI

-5

GI

GI

GI

GI

GI

GI

GI

GI

-4

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

-3

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

(GI)

-6

GI

GI

GI

GI

GI

GI

-5

GI

GI

GI

GI

GI

GI

GI

-4

(GI)

(C)

(GI)

(GI)

(GI)

(GI)

(GI)

-3

(GI)

(G)

(GI)

(GI)

(GI)

(GI)

(GI)

Notes: Parentheses indicate future product plans

C = Commercial TJ = 0° to +85°C

1= Industrial TJ = -40°C to +100°C

User 1/0 Per Package
Package Type

Max
Device

I/O

PG84

PQ100

VQ100

TQ144

PG156

XG5202

84

65

81

81

84

84

XC5204

124

65

81

81

117

124

XC5206

148

65

81

81

117

JSG5210

196

65

117

XG5215

244

TQ176

PG191

133

148

148

133

149

PQ160

HQ208

PQ206

PG223

8G225

HQ240

PQ240

PG299

HQ304

8G352

244

244

244

124
148
164

133

164

196

196
196

196
197

Ordering Information
Example:

iT 11

XC5210-6PQ208C

I
Device Type
Speed Grade - - - - - - ' -

4-248

Temperature Range

Number of Pins
Package Type

August 6, 1996 (Version 4.01)

XC5200L
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0)

Advance Product Specification

Features

•

•
•
•
•
•

•

•
•
•
•

High-density family of Field-Programmable Gate Arrays
(FPGAs)
JEDEC-compliant 3.3 V version of XC5200 FPGA
family
Design- and process-optimized for low cost
- 0.5-l1m three-layer metal (TLM) process
SRAM-based, in-system reprogram mabie architecture
Flexible architecture with abundant routing resources
VersaBlock™ logic module
VersaRing™ I/O interface
Dedicated cell-feedthrough path
Hierarchical interconnect structure
Extensive registers/latches
Dedicated carry logic for arithmetic functions
Cascade chain for wide input functions
Dedicated IEEE 1149.1 boundary-scan logic
Internal 3-state bussing capability
- Four global low-skew clock or signal distributionnets
Output slew-rate control
4-mA sink current per output
Configured by loading binary file
- Unlimited reprogrammability
- Seven programming modes, including high-speed
Express™ mode
100% factory tested
100% architecture, pin-out and bit-stream compatible
with XC5200 families
100% footprint compatibility for common packages
5 V tolerant inputs

Fully supported by XACTstepTM Development System
Includes complete support for XACT-Performance™,
X-BLOXTM, Unified Libraries, Relationally Placed
Macros (RPMs), XDelay, and XChecker™
Wide selection of PC and workstation platforms
- Interfaces to more than 100 third-party CAE tools

Description
The XC5200L Field-Programmable Gate Array Family is
engineered to deliver the lowest cost of any FPGA family.
By optimizing the new XC5200L architecture for three-layer
metal technology and 0.5-l1m CMOS SRAM process, dramatic advances have been made in silicon efficiency.
These advances position the XC5200L family as a costeffective, high-volume alternative to gate arrays.
Building on experiences gained with three previous successful SRAM FPGA families, the XC5200L family brings a
robust feature set to high-density programmable logic
design. The VersaBlock logic module, the VersaRing I/O
interface, and a rich hierarchy of interconnect resources
combine to enhance design flexibility and reduce time-tomarket.
Complete support for the XC5200L family is delivered
through the familiar XACTstep software environment. The
XC5200L family is fully supported on popular workstation
and PC platforms. Popular design entry methods are fully
supported, including ABEL, schematic capture, and synthesis. Designers utilizing logic synthesis can use their
existing Synopsys, Viewlogic, Mentor, and Exemplar tools
to design with the XC5200L devices.

Table 1: InitialXC5200L Field-Programmable Gate Array Family Members
Device

XC5202L

XC5206L

XC5215L

3,000

10,000

23,000

2,000 - 3,000

6,000 - 10,000

15,000 - 23,000

VersaBlock Array

8x8

14 x 14

22 x22

Number of CLBs

64

196

484

256

784

1,936

148

244

16

24

Max Logic Gates
Typical Gate Range

Number of Flip-Flops
Number of I/Os

84

TBUFs per Horizontal Longline

10

June 1, 1996 (VerSion 1.0)

I

4-249

XC5200L Field Programmable Gate Arrays

XC5200L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.

XC5200L Operating Conditions
Symbol

Description

Vee
V IH
V IL

Supply voltage relative to GND

TIN

Input signal transition time

Commercial: TJ=O°C to 85°C junction

Min
3.0

High-level input voltage-CMOS configuration

2.0

Low-level input voltage-CMOS configuration

-0.3

Max
3.6
5.0
0.8
250

Units
V
V
V
ns

XC5200L DC Characteristics Over Operating Conditions
Symbol

Description

V OH

High-level output voltage @ 10H = -4 mA, Vee min

VOL

Low-level output voltage @ 10L

leeo

Quiescent FPGA supply current (Note 2)

=4 mA, Vec max (Note 1)

IlL

Leakage current

CIN

Input capacitance (sample tested)

IRIN

Pad pull-up (when selected) @ VIN = OV (sample tested)

Notes:

Min
2.4

Max

N/A

Units
V
V
mA

+10

Il A

0.4
-10
0.02

15

pF

0.25

mA

1. With 50% of the outputs simultaneously Sinking 12mA, up to a maximum of 64 pins.
2. With no output current loads, all package pins at Vec or GND, either TTL or CMOS inputs, and the FPGA configured with a
MakeBits tie option.

XC5200L Absolute Maximum Ratings
Symbol

Description

Units
V
V
V

Vee

Supply voltage relative to GND

-0.5 to +7.0

VIN
V TS

Input voltage with respect to GND

-0.5 to Vee +0.5

Voltage applied to 3-state output

T STG

Storage temperature (ambient)

-0.5 to Vee +0.5
-65 to +150

TSOL
TJ

Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)

+260

°C

Junction temperature in plastic packages

+125

°C

Junction temperature in ceramic packages

+150

°C

Note:

4- 250

°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.

June 1, 1996 (Version 1.0)

XC6200 Series Table of Contents

XC6200 Field Programmable Gate Arrays
Features ........................................................................ .
Description ...................................................................... .
Detailed Functional Description ...................................................... .
Logical and Physical Organization .............................................. .
Cells, Blocks and Tiles ....................................................... .
Routing Resources .......................................................... .
Magic Wires ........................................................... .
Global Wires ........................................................... .
Function Unit ............................................................... .
Cell Logic Functions ..................................................... .
Routing Switches ........................................................... .
Clock Distribution ........................................................... .
Clear Distribution ........................................................... .
Input/Output Blocks (lOBs) .................................................... .
110 Routing ................................................................ .
Designing with XC6200 ............................................................. .
Board Design with XC6200 .................................................... .
Logic Design with XC6200 .................................................... .
Software Design with XC6200 ................................................. .
Register Access .................................................................. .
Map Register ............................................................... .
Mask Register .............................................................. .
Programming ..................................................................... .
Parallel Programming Interface ................................................ .
Wildcard Registers .......................................................... .
Serial Programming Interface .................................................. .
Reset And Initialization ....................................................... .
Pin Descriptions .................................................................. .
Electrical Parameters .............................................................. .
XC6200 Switching Characteristics .................................................... .
XC6200 Operating Conditions ................................................. .
XC6200 DC Characteristics Over Operating Conditions ............................. .
XC6200 Absolute Maximum Ratings ............................................ .
XC6200 Power-on/Reset Timing Parameters ...................................... .
XC6200 Serial Configuration Timing ............................................. .
XC6200 Global Buffer Switching Characteristic Guidelines ........................... .
XC6200 Cell Switching Characteristic Guidelines .................................. .
XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin) ....................... .
XC6200 lOB Switching Characteristic Guidelines .................................. .
XC6200 Internal Routing Delays ................................................ .
XC6200 CPU Interface Timing ................................................. .
XC6200 Pinout Tables .............................................................. .
XC6216 Pinouts - West Side .................................................. .
XC6216 Pinouts - South Side .................................................. .
XC6216 Pinouts, East Side ................................................... .
XC6216 Pinouts - North Side .................................. , ............... .
Product Availability ................................................ , ............... .

4-253
4-254
4-254
4-254
4-254
4-256
4-257
4-257
4-257
4-258
4-259
4-261
4-261
4-261
4-263
4-265
4-265
4-265
4-267
4-267
4-268
4-268
4-268
4-268
4-270
4-271
4-272
4-273
4-274
4-275
4-275
4-275
4-275
4-276
4-276
4-276
4-276
4-277
4-277
4-278
4-278
4-282
4-282
4-283
4-284
4-285
4-286

I

4-251

XC6200 Series Table of Contents

4-252

XC6200
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0)

Advance Product Specification

Features

•

•

•

•

•

•

Advanced Processor-Compatible Architecture
FastMAPTM interface allows direct processor read/
write access to all internal registers in user design
with no logic overhead
All user registers and SRAM control store memory
mapped onto processor address space
- Programmable data bus width (8,16, 32-bits)
- Easily interfaced to most microcontrollers and
microprocessors
High-Performance Sea-of-Gates FPGA
- Up to 16K configurable cells
- Abundant registers, gates and routing resources
- Extremely high gate count for structured logic or
datapath designs
High Capacity Distributed RAM
- High speed SRAM control store
- 2 bytes of synchronous RAM per cell
High Speed Flexible Interconnect Architecture
Low delay hierarchical routing scheme gives large
number of fast 'Ionglines' (Fastlanes)
- Any cell can be connected to any other
Suited to both structured synchronous cell data path
type designs or irregular random logic
- Completely flexible clocks and clears for registers
4 Global low-skew signals
>11 OMHz flip-flop toggle rates

•

•

•

•

Extremely Flexible Cell Architecture
- Over 50 distinct logic functions per cell
- One register and gate/multiplexer possible for every
cell
Advanced Dynamic Reconfiguration Capability
High speed reconfiguration via parallel CPU
interface
Unlimited reprogrammability
Full or partial reconfiguration/context switching
possible
Ideal for custom computing applications
Flexible Pin Configuration
- All User I/O's programmable as in, out, bidirect, tri c
state or open drain.
- Configurable pull-up/down resistors
CMOS or TTL logic levels
- 8, 16, 32-bit CPU interface
Testability
- Pre-tested volume part
- JTAG capability with library macrocells
XACTstep Series 6000 Development System
- Implement designs using familiar tools like Viewlogic
and Synopsys
- Use PC or Unix workstation platforms
- Fully automatic mapping, placement and routing
- Interactive Physical Editor for design optimization
- Large Xilinx parts library for schematic capture
VHDL synthesis

Table 1: The XC6200 Family of Field-Programmable Gate Arrays
Device
Max Logic Gates
Typical Gate Range
Number of Cells
Max. No. Registers
Number lOS's
Cell Rows x Columns
Max. RAM (bits)

XC6209'
13,000

XC6216
24,000

XC6236 '
55,000

XC6264 '
100,000

9,000 - 13,000

16,000 - 24,000

36,000 - 55,000

64,000 - 100,000

2304
2304

4096

9216

16384

192

4096
256

9216
384

16384
512

48x48

64x64

96x96

128x128

36K

65K

147K

262K

Notes:, 1. Planned Product

June 1, 1996 (Version 1.0)

4-253

I

XC6200 Field Programmable Gate Arrays

Description
The XC6200 family is a new type of high performance Field
Programmable Gate Array (FPGA) from Xilinx.
The XC6200 series is a family of fine-grain, sea-of-gates
FPGAs. These devices are designed to operate in close cooperation with a microprocessor or microcontroller to provide an implementation of functions normally placed on an
ASIC. These include interfaces to external hardware and
peripherals, glue logic and custom coprocessors, including
bit level and systolic operations unsuited for standard processors.
XC6200 FPGAs can provide extremely high gate counts for
data path or regular array type designs. In these cases the
actual gate count may be considerably higher than those
given in Table 1.
An XC6200 part is composed of a large array of simple,
configurable cells. Each basic cell contains a computation
unit capable of simultaneously implementing one of a set of
logic level functions and a routing area through which intercell communication can take place. The structure is simple,
symmetrical, hierarchical and regular, allowing novice
users to quickly make efficient use of the resources available.
The nearest-neighbor interconnect of the cells is supplemented with wires of length 4, 16 and chip-length (Cl)
cells, called Fastlane-4, 16 and Cl respectively, which provide low-delay paths for longer connections. In addition
there are four global input signals which provide a low-skew
distribution path for critical high-fan-out nets such as clocks
and initialization signals.
An XC6200 part is configured by the content of an integral,
highly stable six-transistor SRAM control store. This allows
XC6200 parts to be quickly reconfigured an unlimited number of times. The SRAM control store can be mapped into
the address space of a host processor and additional support logic is provided to allow rapid reconfiguration of all or
part of the device. In addition, the outputs of function units
within the device can be read by a processor through the
RAM interface. A host processor can read or write registers
within logic implemented on the device. Data transfers can
be 8, 16 or 32 bits wide, even when register bits are distributed over a column of cells. These capabilities allow
XC6200 FPGAs to support virtualised hardware in which
circuits running on the FPGA can be saved ('swapped ou!')
to allow the FPGA resources to be assigned to a different
task, then restored ('swapped in') at a later time with the
correct internal state in their registers. Sections of the
device can be reconfigured without disturbing circuits running in other sections. Thus an XC6200 FPGA in a coprocessor application can be time-shared by several
processes running on the host computer.

4-254

Design entry and verification are carried out with Xilinx
XACTstep Series 6000 software using industry-standard
schematic capture, synthesis and simulation packages
such as Viewlogic, Synopsys and Mentor Graphics. A comprehensive library of parts, ranging from simple gate primitives to complex macro-functions, exists to make this an
easy task.
Below the top level design tools, the XC6200 product family
is supported by a number of CAD tools ranging from simple
symbolic editors to sophisticated cell-compilation tools.
These tools will ensure that the captured design is laid out
efficiently with no user intervention. Node delays can then
be back-annotated to the top level logic simulator. The tools
also allow for manual intervention in the layout process, if
desired. Incremental design is also supported: if a design is
laid out and subsequently changed, only the modified block
has to be re-Iaid out.
The functions available within each cell provide a good target for logic syntheSis programs. The simple cell architecture allows arbitrary user logic designs to be mapped onto
a number of cells, rather than having to split the design up
into medium-complexity mini-functions for mapping to a
larger configurable logic block. Because each cell can be
configured as a register, designs containing far more registers than would be possible with a larger configurable block
are achievable.

Detailed Functional Description
Logical and Physical Organization
The XC6200 architecture may be viewed as a hierarchy. At
the lowest level lies a large array of basic cells (Figure 1).
This is the 'sea-of-gates'. Each cell is individually programmable to implement a D-type register and a 2-input logic
function such as a multiplexer or gate. Any cell may also be
configured to implement a purely combinatorial function,
with no register. This is illustrated in Figure 7.

Cells, Blocks and Tiles
First generation fine-grain architectures implemented only
nearest-neighbor interconnection and had no hierarchical
routing (Figure 1). The XC6200 architecture is a second
generation fine-grain architecture, employing a hierarchical
cellular array structure. Neighbor-connected cells are
grouped into Blocks of 4x4 cells (Figure 2) that themselves
form a cellular array, communicating with neighboring 4x4
cell Blocks. A 4x4 array of these 4x4 Blocks forms a 16x16
cell Tile (Figure 3). In the XC6216 part, a 4x4 array of these
16x16 Tiles forms the central 64x64 cell array which is then
surrounded by I/O pads (Figure 4).

June 1, 1996 (Version 1.0)

~XILINX

Length 4 Fastlanes. -_ =

=: : ___-__ - - - _ _ 84

W4

'-t--+-~-

I
Figure 1: Nearest-Neighbor Interconnect Array Structure

Figure 2: XC6200 4x4 Cell Block

Each Arrow

= Sixteen Chip-Length Fastlanes

(Only 1 shown for clarity)

Figure 3: XC6200 16x16 Cell Tile

June 1, 1996 (Version 1.0)

Figure 4: XC6216 Device

4- 255

XC6200 Field Programmable Gate Arrays

Routing Resources
Each level of hierarchy (basic cells, 4x4 cell Blocks, 16x16
cell Tiles, 64x64, etc.) has its own associated routing
resources. Basic cells can route to their nearest neighbors
or through the neighbor cell to its neighbor. Note that cells
used for interconnect in this manner can still be used to provide a logic function. Wires of length four are provided to
allow 4x4 cell blocks to route across themselves without
using basic cell resources. Similarly 16x16 cell tiles provide
additional wires of length 16 cells and the 64x64 array provides wires of length 64. Larger XC6200 products extend
this process to 256x256 cell blocks and so on, scaling by a
factor of 4 at each hierarchical level as required. Intermediate array sizes (e.g. 96x96) are created by adding more
16x16 tiles. Switches at the edge of the blocks and tiles
provide for connections between the various levels of interconnect at the same position in the array (e.g. connecting
length 4 wires to neighbor wires).
The longer wires provided at each hierarchical level are
termed 'Fastlanes' because it is convenient to visualize the
structure in three dimensions with routing at each hierarchical level being conceptually above that in lower hierarchical
levels, with the cellular array as the base layer. The length-

4 Fastlanes are driven by special routing multiplexers within
the cells at 4x4 block boundaries. All routing wires are
directional. They are always labelled according to the signal
travel direction. For example, S4 is a length-4 Fastlane
heading from North to South. In Figures 2, 3 and 4 each
individual cell has a length 4, 16 and CL Fastlane above it.
However only a small number are shown for clarity.
The benefit of the additional wiring resources provided at
each level of the hierarchy is that wiring delays in the
XC6200 architecture scale logarithmically with distance in
cell units rather than linearly as is the case with the first
generation neighbor interconnect architectures. Since 4x4
cell block boundaries lie on unit cell boundaries, the switching function provided at 4x4 cell boundaries is a superset of
that provided at unit cell boundaries. i.e it provides for
neighbor interconnect between the adjacent cells as well as
additional switching options using the length 4 wires. Similarly, the switching unit on 16x16 cell tile boundaries provides a superset of the permutations available from that on
the 4x4 cell block boundaries. Further switching units are
also provided on the 64x64 cell boundaries to provide the
length CL Fastlanes.

ClK

N 8 E WN484E4N4

Naut

E
X3

N
8
E
W
N4
84
E4
W4
WaUl

X1

N
8
W
F

Function
Unit

F

NEW F

X2

N
8
E
F

N
8
E
W
N4
84
E4
W4
Eaut

8 E WF

ClR
Figure 5: XC6200 Basic Cell

4- 256

June 1, 1996 (Version 1.0)

1:XILINX
X1--------------------~

X2
Y2

0

CSMux
RP Mux

X3

F

Y3

0

Q

Clk

I
Clr
Figure 6: XC6200 Function Unit

Magic Wires
The majority of interconnections are routed using the nearest-neighbor and Fastlane wires described above. Each
cell has a further output (labelled 'Magic') which provides
an additional routing resource. A cell's Magic output is not
always available for routing. Its availability is dependent on
the logic function implemented inside the cell. More information on the physical nature of the Magic wires is given in
the section "Function Unit" on page 257.
Each cell's Magic output is routed to two distinct 4x4 block
boundary switches. The Magic wire can be driven byN, S,
E or W from adjacent cells orfrom.theN4, S4, E4 or W4
Fastlanes passing over the cell. This makes it particularly
useful for corner-turning (all other routing resources are
straight).
The Magic wires are illustrated in Figure 8.

Global Wires
The .?zE-Ro

l>oNE

-4>BUF
~
UND2

~R2Bl

~2
~R2Bl

UND2Bl

~D2

::)U.OR2

~D2Bl

::)~R2

~M2_1B1A
SEL

~M2_1B1B
SEL

~2_1B2
SEL

A
B

SEL
CLR

CLR

CLR

Figure 7: Cell Logic Functions
Figure 6 shows the implementation of the XC6200 function
unit. The design uses the fact that any function of two Boolean variables can be computed by a 2:1 multiplexer if suitable values chosen from the input variables and their
complements are placed on its inputs. The Y2 and Y3 mUltiplexers provide for this conditional inversion of the inputs.
TheCS multiplexer selects a combinatorial or sequential
output. The RP multiplexer allows the contents of the register to be 'protected' .If register protection is enabled then
only the programming interface can write to the register. It
will not change when the X inputs to the function unit
change, even if iUs clocked or cleared. This feature is useful in designs containing control registers which are only to
be written by an external microprocessor. The control
inputs of all the multiplexers, except the one switched by
Xl, come from configuration memory bits.

Cell Logic Functions
Each cell can be configured as any two-input gate function,
any flavor of 2: 1 multiplexer, constant 0 or 1, single input
functions (buffer or inverter) or any of these in, addition to a
D-typeregister. This is illustrated in Figure 7. The gate
names given correspond to standard Xilinx library part
names·for these primitives. Although three inputs are
shown entering the combinatorial 'cloud', dual and single
input functions are also possible (e.g. inverter + register or

4- 258

register alone.) The buffer symbol is available in the CAD
libraries, however the place and route software will generally optimize this out as there is no requirement for the
deSigner to buffer signals with this architecture. This is
because signals are regularly buffered by routing mUltiplexers. Symmetrical functions are also· possible but not shown
in Figure 7; e.g. A-B (AND2B1 }is shown but
(AND2B2)
is not. This is because A and B are assigned to user signals
by the logic mapping software to provide the required function. Thus, a multiplexer with inversion on the SEL in pulis
unnecessary because the. mapping software can simply
swap the signal assignments for A and B.

A-a

The sources of the X1, X2 and X3 input multiplexers are set
automatically by CAD software during the logic mapping
phase. Table 2 shows the assignments for all the cell multi"
plexers to compute the various logiC gate functions. A
NAND2B1 is equivalent to an OR2B1 with the inputs
swapped and a NOR2B1 is equivalent to an AND2B1with
the inputs swapped; therefore, these gates are not listed in
Table 2.
If the register within a cell is not used in the. design then a
special 'fast' version of most gates can be configured, using
the register to provide a constant 1 or o. For example a fast
AND gate (A-8) can be configured by setting the register to
o during configuration and assigning Q to Y3. A is routed to
X1 and B to X2. X2 is aSSigned to Y2. When Achanges to
June 1, 1996 (VerSion 1.0)

~:XILINX
Table 2: Function Derivation
Function

o (Fast)
0
1 (Fast)
1
BUF (Fast)
BUF
INV (Fast)
INV
A-B (Fast)
A-B
A-B (Fast)

Xi
X
A
X
A
A
X
A
X
A
A
A
A
A
A
A
A
A
A
A
A

X2
X
A
X

X3
X
A
X

A
X
A
X
A
B
B
X
A
B
B

A
X
A
X
A
X
A
B
B
X
A
B
B
X
A
B
B
B
B
B
B
B
B

A-B
A-B (Fast)
A-B
A+B (Fast)
MB
A+B (Fast)
A+B
A+B(Fast)
A+B
Aa3B
Aa3B
M2_1
M2_1B1A

A

A
B
B

SEL
SEL

A
A

M2,-1 B1 B
M2_1B2

SEL
SEL

A
A

A

X

A
B
B
X

0, Y3 is selected and Fis forced low as soon as the X1-controlled multiplexer switches. In the normal AND gate, there
would be an additional delay as A propagated through the
V3 multiplexer. Fast or normal gates may be specified by
the designer but,for optimal layout density, this is best left
to the logic mapping software.
The multiplexer functions have a straightforward mapping
with fixed assignments to· Xi ,X2 and X3, and Y2 and Y3
providing input inversions as required.

Routing Switches
As described earlier, each cell within a 4x4 block is able to
drive its output to its nearest neighbors to the N,S,E and W.
In addition to this, cells at 4x4 block boundaries are also
abh~ to drive their outputs onto length-4 Fastlanes. Special
switch units are provided around each 4x4 block boundary
to facilitate these connections. This is illustrated in Figure 8.
Th.ese switches also allow higher levels of hierarchical routing (e.g. length - 16 and CL Fastlanes) to be connected to
length-4 Fastlanes.

June 1, 1996 (Version 1.0)

V3
X
X3
X
X3

RP

CS

Q

X
X2
X
X2

Q

0
X
1
X

Q

Q

Q

S
C
S
C
C

X2

X3

X

X

Q

Q

Q

X2
X2
X2

X3

X

C
C
C
C

V2

Q

X2
X2
X2
Q

X2
X2
X2
Q

X2
X2
X2
X2
X2
X2
X2

X
Q

X

Q

Q

X3
X3
X3

Q

X
X

Q

Q

X3
X3
X3

X
Q

Q

Q

X3
X3
X3
X3
X3
X3
X3
X3
X3

X
X
Q

X
X
X
X
X
X
X

C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C

1
0
X
0
X

0
X

1

I

X

1
X
1
X

0
X
X
X
X
X
X
X

Figure 8 also shows the connections for each cell's Magic
output. Each Magic output is routed to two destinations for
increased routing flexibility. The .two connections are
labe"ed M and MA. The Magic wires allow cell outputs to
jump to the edge of the 4x4 block and hence onto Fastlanes
or into the. next 4x4 block. They are also a particularly effi c
cient way of making large busses turn corners.
N,S,E and W switches are similar, however the N switches
contaIn additional multiplexers to drive the register Clock
lines. The contents of the boundary switches are shown in
Figure 9 through Figure 12. The multiplexers driving the
NOut, SOut, EOut and WOul lines are actually implemented within the cell adjacent to the switch. These multiplexers take the place of the neighbor multiplexers found in
the basic cell (see Figure 5). Boundary cells contain additional RAM bits to control the larger multiplexers. An additional output is available from these multiplexers. This
output reflects the output that would have come from. the
cell's neighbor multiplexer had it been a basic non-boundaryce". To distinguish this from the output of the boundary
switch (NOut, SOut, EOut or WOut), it is suffixed with a 'C'
(Cell); e.g. NC for an Nswitch. NC will be one of Nln, E, W,

4-259

XC6200 Field Programmable Gate Arrays

or F depending on the least-significant two bits of the NOut
multiplexer select lines. Hence NC will be identical to NOut
if NOut is one of F, Nln, E or W. If NOut is one of N41n, N16,
PS4 or MN then NC will be one of F, Nln, E orW depending
on which signal is routed to NOut. The 'c' signal will be one
of the upper four inputs to the 8:1 multiplexers shown in
Figure 9 through Figure 12, the actual value being selected
by the two least-significant multiplexer select lines. Similar
'c' signals are generated in the Sswitch, Eswitch, and
WSwitch.
The 84 input to the NOut multiplexer in the Nswitch is actually the 84 input to the adjacent Sswitch in the 4x4 block
immediately to the North of this block. This should not be
confused with the S40ut signal from that block's Sswitch.
This is also true of some of the other inputs to the mUltiplexers in other boundary switches. To avoid confusion, these
inputs are prefixed with the letter 'P' (for Previous). e.g.
PS4. This feature allows Fastlane wires to perform U-turns.

r

SCln
NCl
N16
NCOut
Clkln
N41n
MNA
PS16
SCl
MN
MS

-

-

--

-

--

"l

";jJ=

N40ut

W
N41n
N16
PS4
MN

NOut

GClr~
NCl

~~

L

Clkln-+~

NOut-+
GClk-+

Nswitch

--------

.J

Figure 9: Contents of Nswitch

r

L

MN
NCl
PN16
S41n
S16
MS
MSA
SCl
SCOut
NCln-+

-

-

-

-

-

-

-

-

-

"l

F
E

w
S40ut

-

-

-

Sin
S16
PN4
S41n
MS

_S99~

SOut

Sswitch

-

.J

Figure 10: Contents of Sswitch

r

_MAnets
_Mnets

Figure 8: Routing Switches at 4x4 Block Boundary

MW
MEA
PW16
WCl
WCln
ECOut
E41n
ME
E16
ECl

-

-

E40ut

-

L

-

-

- - - - - -

"l

:ID=

Eln
S
PW4
ME
E16
E41n

- - - -

EOut

Eswitch

.J

Figure 11: Contents of Eswitch

r

ECl
W41n
WCl
MWA
MW
PE16
WCOut
ME
W16
ECln

"l

wl~r·
. . Y'l. C9.~t

S
PE4
W16
MW
W41n

WOu

Wswitch

L

.J

Figure 12: Contents of Wsw itch

4-260

June 1, 1996 (Version 1.0)

~XIUNX
Clock Distribution
As described previously, register clock inputs may be
driven from any source but it is recommended that the GClk
signal is used. GClk also has the advantage that it can be
stopped by writing to the Device Configuration Register.
The Global wires enter the part through dedicated input
pins and are distributed in a special low-skew 'H' pattern
(Figure 13). Each vertically aligned (South to North) group

faster clock) or sourced directly from the device programmable 1/0 pins.
Where a fast clock is required by only a small fraction of the
logic on the device it may be preferable to employ user
interconnect resources rather than a Global or Chip-Length
Fastlane, since limiting fast clock distribution to the area of
the device where it is required will reduce power consumption.

Clear Distribution
Register Clear inputs are routed in a similar manner to
Clock inputs. In this case vertical groups of 16 cells, within
a 16x16 tile, share a common Clear. Clear lines run in a
Southerly direction and are sourced from the Sswitch unit
of 4x4 blocks which also lie on a 16x16 boundary. All of the
boundary switches at 16x16 boundaries contain additional
switching multiplexers. These are illustrated in Figure 14.
ClrOut drives the Clr inputs to each of the sixteen cells in
the group. The Sand SCL connections allow the output of a
cell to provide a user-generated local Clear signal.
East Boundary
NCl
SCl

ECl

N161n

E161n

N41n
PS4
NCOut

Global Input
Figure 13: Low Skew 'H' Distribution Of Global Signals (XC6216)

of four cells within a 4x4 block is clocked by its own clock
source. This is driven from a multiplexer in the Nswitch
immediately to the South of the group of cells. The connections for this multiplexer are shown in Figure 9. ClkOut
drives the Clk inputs to each .of the four cells in the group.
As can be seen from Figure 9, the register clock for each
group of four cells can be driven by Clkln, NOut, GClk,
GClr, G1, G2 or NCL. Clkln is the ClkOut from the 4x4 block
to the South, allowing vertical daisy-chaining of clock signals. NOut is the N output from the Gell associated with the
Nswitch. This can be used to provide local user-generated
or gated clock signals if required. GClk is the Global Clock
signal direct from the device GClk input. Clearly this signal
only has to pass through one 4:1 multiplexer whereas GClr,
G1 and G2 have to pass through two. This is one reason
why there is less delay on GClk.
It is also possible to route North chip-length Fastlanes onto
the Clock lines. This allows up to 64 (for a XC6216 device)
locally used· clocks to be provided that can still run the
entire length of the chip with minimal skew. These local
clock signals may be generated internally (e.g. by dividing a

June 1, 1996 (Version 1 .0)

West Boundary
WCl

N160ut

PW4
E41n
WCln

SCln
MN

NCl
SCl
S161n

ECln
MW
South Boundary

GClr
Clrln
SCl

PN4

G2

S41n
NCln

GClk

SCOut
MS

SOut
G1

o

Figure 14: Additional Switches at 16x16 Boundaries

Input/Output Blocks (lOBs)
User-configurable Input/Output Blocks (lOBs) provide the
interface between external package pins and the internal
logic.
One lOB is provided for every cell position around the array
border. lOBs are connected to fixed pad locations. There
are more lOBs than available pads, hence some lOBs are
'padless'. However it is still possible to route signals. from
pad less lOBs to device pins.
Figure 15 is a simplified diagram of an lOB and its associated 10 pad. The lOB is located at the array border and the
pad is located close to its device pin, The pad may be
located some distance from its associated lOB. The map-

4- 261

I

XC6200 Field Programmable Gate Arrays

. _____________ J9!;1 ___________ .. _____ -'9 _PAP _____ .
Control Enable
ArrayEnable -I>;--:-T-1
'Slew..---'-'-----..:,
liEnable

ArrayDToPad ->1-----'---1

i

ControlDToPad -1>;------1

Array Data

Data
eighbOr Data .......' - - - - - I
DelD ta

Fastlane Data-.-I-----I

Signals From

Array-->'--I--~---"-----'

Control Data +-.--------1
L16 Output From Array-->'-'-------"----'

Figure 15: Input/Output Architecture
ping of lOBs to device pins is given in the pinout tables
starting on page 282.
The XC6200 lOB architecture incorporates a novel and
very powerful feature: every lOB has the capability of routing either an array signal or a control logic signal to/from the
device pin. Every signal, including all the control signals
(e.g. CS, RdWr, Address Bus, Data Bus, etc.), passes
through an lOB. This means that all the control signals can
be routed into the logic array for use in user designs. Similarly, user logic can control the XC6200 internal control circuitry. For example a user signal could be used to drive the
internal CS signal rather than the CS pin.
As an example of the power of this feature, an XC6200
design could include an address decoder which decoded
microprocessor read/write cycles and produced appropriately retimed signals for all the parts on a board including
itself, thereby removing the need for address decoding
PAL.:s or discrete logic.
Each lOB has an array data input and a control data input,
labelled ArrayDToPad and ControlDToPad in Figure 15.
Associated with these inputs are two enable signals - ArrayEnable and Control Enable. These signals control whether
the pad associated with this lOB is in the input or output
mode. Each lOB also supplies ArrayData and Control Data
when acting as an input.
The 'Control' signals are routed to the internal XC6200 control circuitry. If control signals are not required all the time
then these lOBs can be used to route other user signals
into the array. For example if only eight data bus bits were
continuously required, the remaining twenty-four lOBs
associated with the data bus could be used to route user
signals tolfrom the array. Control Enable comes either from
the internal XC6200 control circuitry if there is a bidirectional control signal or output signal on that lOB, or it is tied
inactive.

4-262

There are less real control signals than lOBs, hence the
three control signals on some lOBs are not connected to
the device control logic. These spare control signals are
used to route data to and from the pad less lOBs mentioned
above. The control signals on the pad less lOB are not
used. This is illustrated in Figure 16.

Ar~

'PAD LESS' lOB
Enable r - - ,

Arr~
-0

0

"

~
{?

'1

!

DToPad I--

l5

Ol

0

.ii~
6i'

:.'

:?'

~

DFromPad

NORMAL lOB
Control Data
ControlDToPad
Control Enable

"0
Ol

D-

E

e

-0

~
{?

0

DFromPadB
DToPadB
EnToPadB

Q)

l5

Ol

c:

w

0

I

10 PAD

I

Figure 16: 'Padless'IOB Configuration

June 1,1996 (Version 1.0)

1:XILINX
The 'Control' signals are also referred to as 'B' signals later
in
this
data
sheet.
ControlDToPad = DToPadB,
and
Control
Control Enable = EnToPadB
Data = DFromPadB. Also the L 16 output from the array,
which can be routed onto Control Data, is referred to as
DForPadB.
Three configuration· RAM bits within each lOB control the
programmable aspects of its 10 pad. These RAM bits have
no effect for pad less lOBs. 'PUp' and 'PDn' enable the pullup and pull-down resistors. The resistors may be used to tie
floating logic inputs to a known value. 'Slew' slows the output transition time to reduce supply noise and groundbounce. The default condition is pull-up off, pull-down off
and slew on.

ers and may be activated at any time. Only when OE is
active and there is a valid ID pattern in the ID register, do
the pull-up and pull-down RAM control bits determine the
10-pad resistor configuration.

1/0 Routing
The array signals to and from the lOBs are generally just
the signals which would have passed between two cells in
the array. The ArrayDToPad signal in Figure 15 is actually
the neighbor output from the border cell associated with the
lOB. The Array Enable signal is the length-4 Fastlane output from the same cell.

The Array Enable, Array Data and Control Data multiplexers are also controlled by configuration RAM bits. A fixed
delay may be optionally applied to Array Data inputs. This
allows the input data hold time specification to be removed.
The ArrayEnable and ArrayDToPad signals can be configured to constant 0 or 1 values within the logic array. The
constant values are particularly useful for the enable signal
when the pin is to function as an input or output rather than
a bidirectional pin. Constant values onthe data signal and a
computed value on the enable signal produce open drain
pull-up (DToPad=1) or pull-down (DToPad=O) pins.
During reset, all the output drivers are disabled and the
pull-up resistors are enabled. The pull-up and pull-down
RAM control bits have no effect. After a reset the output
drivers remain in this state. For the output drivers to be
enabled, the global OE signal must be asserted (low) and a
valid configuration must be present in the device ID register. The ID register is usually the last thing to be written during configuration and acts as a check that the programming
interface is operating correctly. More details of this are
given in the 'Programming' section on page 268. The OE
signal provides a quick way of disabling all the output driv-

June 1, 1996 (Version 1.0)

-

I

-

-

'0'

ECLOu!

PW41n

WCLIn

WCln

PW41n

MWln

WCln

PW161n

MWln

WrEn

RdEn

DataSit

ControlDToPad

DelData

DelData

-

-

-

-

I

I

E160u

ECLOut
WCLIn
PW161h
WCln
MWln

IControlDToPad

DFrompad~
EOut

PW41n

I Control Enable
DelData

L

..J

Figure 17: Array Data Sources In West lOBs

4- 263

XC6200 Field Programmable Gate Arrays

The Array Data multiplexer in Figure 15 is actually a collec,
tion of multiplexers that source the neighbor, length-4,
length-16 and chip-length wires into the array. South lOBs
(lOBs at the South edge of the array) also source the local
clock signals into the array. North lOBs source the local
clear signals. This is illustrated for a West lOB in Figure 17.
These multiplexers also allow a number of other internal
control signals to be routed into the array: WrEn and RdEn
are signals which are active during state register accesses.
'DataBit' is the state register output value for this row during
a state access. Details of the timing of these signals are
given in the "Parallel Programming Interface" on page 268.
Note that in order to provide a minimal delay signal path
into the core array, the neighbor data output from the lOB
cannot select the delayed version of DFromPad. Only the
un-delayed DFromPad and the Previous Length-4 Input
can be routed onto the neighbor data output. Therefore the
neighbor data output is unaffected by the value of the configuration memory which controls the Del Data multiplexer
in Figure 15.
The length-4 and length-16 routing multiplexers at the array
border also expect some inputs which are not available. For
example at the West edge, MEln, ECln, PE41n and PE161n
are non-existent. These inputs are tied to ground thereby
providing an abundant source of constant zeros and ones
at the array border. These can be used to provide constant
values to drive the Array Enable inputs to lOBs.

4-264

FastMAP Interface

CS

RdWr

A(15:0)

0(31:0)

**
OE
Reset
I/O

G1
G2
GClk
GClr

Figure 18: XC6216 Logic Symbol

June 1, 1996 (Version 1.0)

1:XILINX
Automatic Mapping,
Place and Route

Front End Design Entry
Data

Logic Simulation
elk

Data
load
CLR
EDlFI\E4Et
---------I-----j~

Eo

ENTITY counter IS
PORT (data: IN std_ulogic:

en: IN std_ulogic;

In-System Verification

J"lJl.J1..h..IL

Load

I

n--

Data~

EO~

O"'~
00010

10011
00011
ARCHITECTURE rtl OF counter IS ....

10011
00100

I

1Fai3d
I Si11.JaIi:I1

I Fai3d

I Test

I

Manual Place and Route
I using Physical Editor
I (optional)

I

Figure 19: XC6200 Logic Design Flow

Designing with XC6200
The designing of XC6200 FPGAs into systems may be partitioned into three distinct activities: board design, logic
design, and software design.

Board Design with XC6200
An XC6200 part may be used on a board design as a
microprocessor peripheral part, as an ASIC-type device or
as both. In the first instance the XC6200 part will have conventional SRAM data, address and control signals. In other
cases, it may only require the user defined I/O signals of an
ASIC. Packaging information for the part is shown in
Table 6. The number of user I/O signals will depend on the
exact package used.
Several XC6200 devices may be tiled together on a board
to form a larger array. The regular array structure of
XC6200 devices makes this particularly easy.
The configuration RAM bits in the lOBs allow for a number
of different programmable options to make interfacing to
other ICs easier.

Logic Design with XC6200
This can be approached as an ASIC type design using the
function and routing architecture defined in the previous
sections. An example design flow is illustrated in Figure 19.
The design may be carried out in a variety of different ways.
Hardware description languages such as VHDL may be

June 1, 1996 (Version 1.0)

used with the synthesized design targeted to the XC6200
architecture. Alternatively, schematic capture, using the
extensive Xilinx Unified Library, with commonly used front
end design tools (e.g. ViewLogic PROcaptureNiewDraw)
may be used. These tools produce an EDIF nellist which is
subsequently passed to the underlying XC6200 place and
route software. This automatically maps the user's design
to the XC6200 architecture in an efficient way and provides
individual node delays which can be passed back to the
high level simulation tools such as Viewlogic PROsim/
ViewSim for accurate simulation. Simulation may be carried
out prior to placement to check the logical correctness of
the design using nominal delays. The place and route software also has optimization capability to carry out tasks
such as redundant gate removal. A binary configuration file
that can be written to the XC6200 device via the programming interface is also produced automatically. The underlying CAD software is highly integrated with the high level
CAD tools, providing user-friendly pull-down menus and
dialog boxes to carry out all tasks.
These methods allow designers with little or no knowledge
of the XC6200 architecture to quickly produce large and
complex designs. Some designers may wish to carry out
detailed hand placement and routing to produce ultra-optimized very high-speed/small area sections in their designs.
Others may wish to generate large regular structures such
as systolic arrays or pe~orm floor-planning for extra efficiency. For these cases, a sophisticated physical editor is
available that allows designers to graphically modify the
4- 265

XC6200 Field Programmable Gate Arrays

automatic placement of gates/registers into celis and modify the routing as much as required. Alternatively this software may simply be used to see how the automatic
placement and routing software has optimized a design. If a
modification is subsequently made, then only the modified
part of the design needs to be re-Iaid out. This incremental
design process provides a very rapid change cycle during
debugging.
Ali the design tasks may be carried out on PC or Unix workstation platforms.
As an example, the simple accumulator circuit of Figure 20
is mapped onto the XC6200 architecture. Figure 21 shows
the resulting layout as displayed by the Physical Editor running under Microsoft Windows in this case. The Physical
Editor tools are also available for Unix workstations. The
boundaries of basic celis within the array are denoted by
the squares, with larger rectangles representing the switch
units on 4 celi boundaries. The wiring resources used by
the design mapped onto the array are indicated by solid
black lines. When a celi function unit is used by the design

it is annotated with the instance names of the mapped
primitives. The primary inputs and outputs are not shown in
this example.

MUXI

-r---------t-11-:: Q
M2

IN- •
CIN

1

DO

I

Ii

I

8

0

_

FDe].

FDe

,;'OR2

~~~ -l=)D-~Q
~L~

I
I
I

XOR2

XOR2

CLK

CLR

CLR~

T
I
'

I

Figure 20: Accumulator Schematic

Figure 21: Accumulator Physical Editor View

4- 266

June 1, 1996 (Version 1.0)

~:XIUNX
The inputs and outputs to the function unit are connected to
the edges of the cell box. The CAD plot shows all the routing resources available. To the left of each cell the six wires
running in a Southerly direction are: SCL, S16, Clr, S4,
Magic and S. The signal direction is indicated with arrow
heads. S, S4 and Clr are shown entering the cells on the
left edge of the cell boxes. The two outputs on the left edge
of the cell box are Magic and SOut. The inputs and outputs
on the remaining three cell box edges follow a similar pattern. The Clk input on the right hand cell box edge is
denoted with a clock '<' symbol.
The Physical Editor allows cells to be selected and moved.
The inter-cell routing rubber-bands and adapts automatically to the new placement. The routing may also be manually modified if desired.

Software Design with XC6200
This is the design of a program for the host processor which
interacts with a design running on the XC6200 FPGA. Here
various registers within the XC6200 design appear as locations within the processor's memory map. In addition, the
configuration memory. of the device appears within the
memory map and portions of the device can be reconfigured as required. Predefined device drivers and an efficient
run-time library are available to make optimal use of the
high speed reconfiguration capabilities with minimal development time.

Register Access
The XC6200 architecture supports direct accesses from
the processor to nodes within the user's circuit: the output
of any cell's function unit can be read and the flip-flop within
any cell can be written. During state reads a number of cell
outputs are routed onto the CPU data bus. The signal which
is actually read is the inverse of F in Figure 6 (= Q or D).

641/0 North

64
1/0

Row

W

e
c

S
T

0

E

0

64x64
Cell Array

d
e
Column Decode

Control
641/0 South

64
1/0

E

A
S
T

Global

110

I
Figure 22: .XC6216 Block Diagram
Figure 22 is a block diagram of the XC6216 part, showing
the row and column address decoders. Figure 23 shows
the mapping of this area of the address space: there are 64
I/O signals from each column of cells and a 6-bit column
address selects a particular column o/cellsto access. This
row and column addressing scheme puts a constraint on
the placement of registers within the user's design that are
to be accessed word-wide: they must be on the same column of cells within the array.

These accesses are carried out through the control store
interface and involve no additional wiring within the user's
design. The CPU interface signals involved in addressing
the cell state can be routed into the configurable array so
that user circuits can detect that an access has been made
and take appropriate action: for example; calculate a new
value for an output register or process a value placed in an
input register.
In many applications this access to internal nodes will be
the main path through which data is transferred to the processor and in some coprocessor type applications it may
be the only external 1/0 method: user programmable 1/0
pads may not be required at all.
To aUow high bandwidth. transfers between the processor
and internal nodes it is necessary to be able. to transfer a
complete processor data word of up to 32 bits in one memory cycle. For this reason, access bits are mapped into a
separate region of the device address space from configuration bits so that allthebits in a word contain aCCeSS bits.

June 1, 1996 (Version 1.0)

Column Address CA(5:0)

Figure 23: Memory Mapped 1/0

4- 267

XC6200 Field Programmable Gate Arrays

Map Register
The XC6200 architecture also provides a mechanism for
mapping the 64 possible cell outputs onto the 8,16 or 32·bit
external data bus, selecting only those cells that implement
bits of the register to be accessed. Without this unit the pro·
cessor would have to implement a complex sequence of
shift and mask operations to discard those bits correspond·
ing to cells not within the register, or the user would have to
constrain the layout so that the register bits were in adja·
cent cells. The mechanism provided takes the form of a 64·
bit map register, one bit for each row liD signal from the
array. This map register can be read and written through
the control store interface and is set up prior to state
accesses. A logic 0 in the map register indicates that the
cell in the corresponding row is part of the register to be
accessed. The unit maps rows from the cell array onto
external data lines starting with the least significant bit: thus
the first row with a 0 in the map register will connect to
external data bus bit 0, the second row with a 0 in the map
register to data bus bit 1 and so on.
This technique puts a further constraint on the user's layout: the cells implementing the bits of the register must be
ordered so that less significant bits occur below more significant bits. However, there are no constraints about the
relative separations of the cells. In practice these two placement constraints: cells occurring in the same column and in
order vertically are easy to meet in datapath type designs.
Normally, the map register will be set once to indicate the
placement of the user liD register that will then be
accessed many times. Therefore the two write operations
required with a 32-bit bus to set up the map register represent a small overhead. In data path type designs where
several registers are required, for example two input operand registers and a result register, it is easy to ensure that
the corresponding bits of the registers occur on the same
row but different columns of the array so that the same map
register value can be used with different column addresses
to access the various registers.
If more 'D's exist in the map registerthan there are valid
data bus bits then a form of wildcarding occurs during
writes. The data bus bits are allocated to the rows of the
array with a '0' in their map register bit. Once all of the data
bus bits have been allocated, Bit 0 of the data bus is allo·
cated to the next row whose map register bit is a '0', Bit 1 of
the data bus to the next row and so on. This feature means
that an entire column of state registers can be written with a
single 8-bit write. For example,if the map register contains
all 'D's and the CPU writes FFh to a particular column. All
the state registers in that column will be written with a '1 '.
The default state of the map register is all 'O's.
During reads, if there are more '0' bits in the map register
than data bus bits, the first rows with '0' bits are mapped
onto the bus.

4·268

If there are less 'O's in the map register than data bus bits,
the upper data bus bits, which are not mapped, will be read
as '1 's during CPU reads and ignored during CPU writes.
An example of map register operation is shown in
Figure 24. The position of the user-defined register within
the cell array is defined by the 'O's in the 64-bit map register.
Similar registers could be defined for every column in the
array if desired.
There is a delay after awrite to the map register before the
change takes effect. No state accesses should be carried
out during this time.

Mask Register
A mask unit controlled by a 32·bit register is placed
between the external data bus and the internal data connections. When the external data bus is 8 or 16 bits wide
only the bottom 8 or 16 bits of this register are significant. A
logic '1' in a bit of this register indicates that the corre·
sponding bit of the internal data bus is not relevant. Bit loca·
tions corresponding to '1's in the Mask Register will retain
their values when written. On a write operation the corresponding bit line will not be enabled and the state informa·
tion for that bit will not be changed. When the device is
reset the Mask Register will contain all logic D's corresponding to all data bus bits valid.
During CPU reads, valid register bits which are disabled will
be read as '0'. Invalid bits (bits which do not physically exist
for the register being read) may be read as '0' or '1'.
The mask register does not affect state register accesses.
In this case the map register can be used to prevent certain
bits being modified.

Programming
The binary data for configuring an XC6200 device, generated by CAD software from the textual description of a user
deSign, must be downloaded into the part itself. This may
be performed in several ways. Generally, the fastest and
most efficient way is by writing directly to the control store,
mapped into the address space of a host processor. If a
microprocessor or other parallel data source is not available, then the serial programming interface may be used.

Parallel Programming Interface
The XC6200 FPGA has a conventional programming inter·
face for static RAM, based on Chip Select (CS) and Readl
Write (RdWr) control signals. The CS signal can be used to
address a single part within an array of devices and allows
data to be read or written. Timing for these signals is illustrated in Figures 28 and 29. These figures show that the
programming interface is synchronous. The GClk input is
used to sample all the interface signals. GClk is also used
when accessing user registers as illustrated in Figure 24.
This is an important point, as only registers clocked directly
by GClk can be reliably read or written using this method.
June 1, 1996 (VerSion 1.0)

~XILINX

8-Bit Data Bus Example

XC6200 Boundary
User-defined register within array
Cell Array
Map,Register

1

. -.. •

--

.
-

1
_B1t] _________

, +------------. - 0

L

..
[' r'" __ _______
::

~

-----

- -

--

-

_B1t § _________

0

-

- - - - -I
- - - -I

~

1
,
:....."",". - - - - - - - - ,, ,,
1
, , I-1
" -------., , ,
','1, ........ __ - - _ • , ,, , I-1
,,
, , , , I-,
:-+------., ,, ,, ,
1
,
,
I-,
,
,
+-----., ,
0
, ,, , , ~ - - I-,, ,
0
, ,,,
[--0--, , , ,- -- 0
, , ,
I-, ,
1
,
,,
I-0
, , ~----. I-,
1
, ,

I
I
I
I
I

,',

Data
Bus

\

.'

/

.

-

:

,
,

\

Bus

/

..

/

_Bjt15 _________

......

I--

0
~----. I--

,-----.

\
Address

L

0

_B1t.'l _________

L:

RdWr

CS

- -

-I

_B1t? _________

- - - - -1
- - - - -I

Bit2

- - - - -I

I
------------

I
Bit 1
- - - - - - - - - - - ... - - - -I
0 --------- - - - -Bit
--I

..
..
..
..
..
.

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

• -•

I-Address
Decode

- -

..

1

-1

I

...

I

I
II

"1\
\

'\
Cells

CPU

Write Enable

Interface

Figure 24: Internal Register Access
Figure 29 shows two separate read cycles - a normal cycle
immediately followed by an extended cycle. In the normal
read cycle CS is sampled low on the first rising GClk edge
(t1) and high on the next (t2). The data bus is then driven
until the next rising GClk edge (t3)' In cases where this is
not long enough, the read cycle can be extended by keeping CS asserted beyond t2 . This is equivalent to adding wait
states. In this case the data bus is driven until CS is deasserted. CS should not be allowed to go high and low again.
This would cause another cycle to begin. CS is sampled on
every rising GClk edge. Other CPU interface signals such
as RdWr and the Address Bus are only sampled on the first
GClk edge of the cycle (t1 for the first cycle and t3 for the
second in the figure examples).
June 1, 1996 (Version 1,0)

Extended write cycles are also possible, however these are
functionally no different to normal write cycles, the data and
address busses still being sampled on the first rising GClk
edge of the cycle (t3 in Figure 28).
CS must always be sampled as a '1' before the next cycle
can begin. In Figure 29 the extended read cycle starts
immediately after the normal read cycle at time t3' A write
cycle could not start until the next rising GClk edge as the
data from the read cycle is still on the data bus.
The SRAM programming interface is supplemented by
additional hardware resources designed to minimize the
number of processor cycles required for reconfiguration.

4-269

XC6200Fieid Programmable Gate Arrays

These resources are initially inactive after a reset so the
device looks like an SRAM.

used to determine which area of the control store is to be
accessed according to Table 4.

The control store layout is designed to minimize the overhead of computations required for dynamic access while
maintaining adequate density to minimize the external storage required for device configurations. When an external
processor is used to configure the device it may be convenient to use a compressed format of the configuration information.

Table 4: Address Mode Selection

A feature of the XC6200 architecture is that a rectangular
area of cells specified as a hierarchical block within a user's
design corresponds directly with a rectangular area within
the configuration memory of the XC6200 device. This
means that a block within the user's design can be dynamically replaced with another block by the host processor,
reconfiguring only the corresponding area of the control
store. The binary data for both blocks can be pre-calculated
from the cellular design and the actual replacement can be
carried out very rapidly using a block transferoperation.
The format of the address bus to the XC6216 device is
shown in Table 3. Larger XC6200 devices have proportionally more bits allocated to row and column addresses.
Table 3: Address Bus Format (XC6216)
Column Offset<1 :0>

7:6
All the configuration memory can be accessed as 8-bit
bytes. When a 16-bit transfer occurs Address is irrelevant. When a 32-bit transfer occurs Address<1 :0> is irrelevant. Data Bus bits <7:0> are written to the address with
Address<1 :0>=00, bits <15:8> are written to the address
with Address<1 :0> = 01, etc. The Address Mode bits are

4- 270

Mode1
0
0
1

1

ModeO
0
1
0
1

Area Selected
Cell Configuration and State
East/West Switch or lOB
North/South Switch or lOB
Device Control Registers

Wildcard Registers
The wildcard register allows many cell configuration memories within the same column of cells to be written simultaneously with the same data. This is used during device
testing to allow regular patterns to be loaded efficiently into
the control memory but is more generally useful, especially
with regular bit sliced designs, since it allows many cells to
be changed simultaneously. For example, a 16-bit 2:1 mUltiplexer could be built using cell routing multiplexers and
switched between sources using a single control store
access.
Similarly, the column address decoder has a wildcard register which allows several cells on the same row to be written with the same configuration. The column address
decoder drives the word lines to enable particular columns
of RAM cells. In this case the number of columns which can
be written simultaneously is limited to 32: that is at most five
don't care bits can be set.
The row and column wildcard registers can be used simultaneously to rapidly configure regular structures onto the
device.
The address decoding for the XC6216 FPGA is summarized in Table 5.

June 1, 1996 (Version 1.0)

~XILINX
Serial Programming Interface
Table 5: XC6216 Memory Map
Address Bus

Decode
00

Cells

A[15:14]

01

East/West Switch or lOB

(Mode[1:0])

10

NorthlSouth Switch or lOB

11

Control Registers

Cell Mode - Cell column
NorthlSouth Mode - Switch column

A[13:8]
(Column[5:0])

(Column
Offset[1:0])

00

West Switch

01

West lOB (Column[5:2]=0000)

10

East lOB (Column[5:2]=1111)

11

East Switch

00

Neighbor Routing

01

Function Input Routing

10

Function

11

State Access (Cell Registers)

00

NIS Switch or NIS lOB Reg 0

01

NIS Switch or NIS lOB Reg 1

10

NIS Switch or NIS lOB Reg 2

11

NIS Secondary Clock Mux
(Column[1 :0] = 00 or 11)

00

EIW Switch or E/W lOB Reg 0

01

EIW lOB Reg 1

Cell Mode - Cell row
East/West Mode - Switch row

(Row[5:0])

Input that controls transitions between states
in serial mode state machine.

o => serial mode, 1 => parallel mode
Wait

NorthlSouth Mode Row[5:2] = 4x4 block number
Row[1 :0] decoded as:
00

South Switch

01

South lOB (Row[5:2]=0000)

10

North lOB (Row[5:2]=1111)

11

North Switch

June 1, 1996 (Version 1.0)

Input that controls transitions between states
in serial mode state machine.

o

=> continue loading, 1 => pause until Wait
deasserted
SEReset

Output from Master FPGA that resets serial
PROM address counter.

SECE

Output from Master FPGA that enables serial
PROM output.

SEClk

Output from Master FPGA that clocks serial
PROM and slave FPGAs. SEData is clocked
into the FPGAs on the rising edge of SEClk.

SEData

Serial data input to FPGA. This is sampled in
the FPGA by SEClk and rstimed by the
FPGA's own GClk.

NorthlSouth Switch Mode

East/West Switch Mode

A[5:0]

The serial PROM interface consists of 6 dedicated 110 pins:

East/West Mode Column[5:2] = 4x4 block number
Column[1 :0] decoded as:

Cell Mode

A[7:6]

All the memory mapped locations in an XC6200 device
may be written in parallel or serial mode. All the operations
which can be carried out with the parallel interface may also
be done serially. The serial interface gives random access
to all the XC6200 memory locations. The serial interface is
designed to operate with any Xilinx serial PROM. A single
serial PROM may be used to configure several FPGAs. In
this case one of the FPGAs acts as a 'Master' and the others as 'Slaves'. The Master controls the serial PROM and
the Slaves. This is illustrated in Figure 25.

In a multi-FPGA configuration a user 110 also will have to be
available to provide the Wait input to the next device in the
chain.
On Reset each FPGA examines its Serial and Wait inputs.
Any FPGA that sees both these signals low at this time
assumes it is the master and drives SEReset, SECE and
SEClk. All User I/Os are held in a high-impedance state
(with pull-up) until a valid configuration is loaded. In
Figure 25, the User I/Os will be pulled high on Reset, hence
the Wait input to the Slaves will be high and they will configure as Slaves. A valid configuration is assumed when the
device ID register is loaded with the correct ID. Programmable I/Os can only be enabled when this is present.
Serial data is loaded in address/data pairs. Once an
address/data pair has been shifted into the FPGA, the data
word is parallel written to the corresponding address inside
the FPGA just as though a parallel CPU write had occurred.
This means it is possible to do all the things which can be
accomplished with the parallel interface, e.g. use of the
mask register, writes to cell state registers, etc.

4- 271

XC6200 "Field Programmable Gate Arrays

- -SLAVE FPGA 1

MASTER FPGA
~

Serial
Gnd-~

!4-----SERIAL !4-----PROM

~

Wait

User IlL

Wait

SLAVE FPGA2
~

Serial
User IA_

Serial
Wait

etc ...

SEReset
SECE
SEClk
SEData

rr
1

SEClk
SEData

rr

SEClk
SEData

I

-- ---

Figure 25: Master-Slave Serial Configuration

The write operation is pipelined so there need be no interruption in the serial data stream. The first address/data pair
must be preceded by a Synchronization Byte = 1111_1110.
There are no starVstop bits; checksums or error check/correction bits.
The address and data are shifted in MSB first. The address
is always 16-bits. The data word is initially 8-bits but may be
increased to 16 or 32 bits by loading the device configuration register with the appropriate code. The bits are shifted
in on the rising edge of SEClk. The SEClk rate may also be
increased by writing the appropriate code to the device
configuration register. Initially SEClk is 1/16 GClk frequency. It can also be set to 1/8, 1/4 or 1/2 GClk.
An example is shown in Figure 25. Data1 is loaded into
Addr1 after the address Isb has been shifted in. In this
example the first write was to the device configuration register and the data bus width was changed from 8 to 32 bits.
Data word 2 starts immediately after Addr1 has been
shifted in. Due to the new data bus width, 32 data bits will
be shifted in. If the width had not been changed data word
2 would also have been 8 bits. Data will continue to be
loaded until Serial goes high or Wait goes low.

4-272

Reset And Initialization
When the XC6200 FPGA is powered up or after a reset, all
configuration memory is cleared and the cell state registers
are cleared. The Reset pin is not required to be active during or after power-up to initialize the FPGA. To avoid poten"tial high current random configurations, the power-up reset
is carried out automatically. The automatic power-up initialization takes 2.5 j..ls. All the XC6200 I/O pads are disabled
during this time and it is impossible to access the device.
The XC6200 may be re-initialized at any time by asserting
the Reset input for a minimum of 20 ns. This acts as a signal to the chip to initialize itself. This initialization occurs
after Reset has been deasserted. Therefore there is a 1.0
j..ls (typ.) reset recovery time when no device accesses are
possible.

June 1, 1996 (Version 1.0)

~:XILINX
Pin Descriptions

OE

The pins are labelled as follows:

When this signal is low the outputs of all programmable I/O
pads are forced into a high impedance state (independent
of the contents of the control store). All the 10-pad pull-up
resistors are also enabled. This pin is a/ways configured as
an input and cannot be used as a fully flexible User I/O like
the majority of other control signals.

Voo
Connections to the nominal +5V supply. All must be connected.

GND
Connections to ground. All must be connected.

CS
Chip Select enables the prog.!:ammingcircuitry and initiates
address decoding. When CS is low, data can be read from
or written to the control memory. This signal is intended to
be used in conjunction with address decoding· circuitry to
select one part within a larger array for programming.

Serial
Input which controls transitions between states in serial
mode state machine.

Wait
Input which controls transitions between states in serial
mode state machine.

o => continue loading, 1 => pause until Wait deasserted

D

SEReset

(d+ 1)-bit bidirectional data bus. Used for device configuration and direct cell register access.

Output from Master FPGA which resets serial PROM
address counter.

A

SECE

Address bus for CPU access of internal registers and configuration memory. 'a' varies between family members.

Output from Master FPGA which enables serial PROM output.

RdWr

SEClk

When CS is low this signal determines whether data is read
from or written to the control memory. If RdWr is high then
a read cycle takes place. If RdWr is low, then a write cycle
takes place.

Output from Master FPGA which clocks serial PROM and
slave FPGAs.

GClk, GClr, G1, G2
Global signals. GClk should be used for global user clocks,
GClr for global user clears and G1 and G2 for other global,
low-skew signals. The GClk pin is a/ways configured as an
input and cannot be used as a fully flexible User I/O like the
majority of other control signals.

Reset
When Reset is taken low the programming registers (mask
unit and address wildcard unit) are re-initialized, resulting in
the XC6200 device appearing as a conventional SRAM.
The control store of the cell array is initialized into a low
power consumption configuration. All programmable output
pad enable signals are forced inactive. All the 10-pad puliup resistors are also enabled. This signal should be taken
low immediately after power up to initialize the device. This
pin is a/ways configured as an input and cannot be used as
a fully flexible User I/O like the majority of other control signals.

SEData
Serial data input to FPGA. This is sampled in the FPGA by
SEClk and retimed by the FPGA's own GClk.

ConfigOK
Signal is active (high) when a valid pattern is present in the
10 register and inactive when the pattern is invalid.

Nx
North I/Os. Connections to I/O Blocks on the north of the
array.

Sx
South I/Os. Connections to I/O Blocks on the south of the
array.

Ex
East I/Os. Connections to I/O Blocks on the east of the
array.

Wx
West I/Os. Connections to I/O Blocks on the west of the
array

June 1,1996 (Vel'siont.O)

4- 273

I

XC6200 Field Programmable Gate Arrays

Electrical Parameters
The XC6200 series is fabricated in 0.65 micron triple metal
n-well CMOS. Foundry sources for this part have been chosen to meet or exceed relevant military standards and
industry practice.
As with all CMOS devices, care must be exercised when
handling this part as it can be damaged by static discharge,
although standard circuit design procedures have been
adopted to minimize this risk.
The power consumption ofaXC6200 device can vary from
a few tens to several h!.mdreds of milliamps depending on
its configuration and the data applied to it. The most significant sources of power consumption are I/O blocks and
dynamic disSipation within the array, both of which are
largely under user control. Dynamic power dissipation is of
most concern where the XC6200 device is used to implement highly concurrent computations. Power dissipation
must be considered carefully, not only because excessive
dissipation could result in device failure but also because
operating speed is reduced at high temperature.
A 0.22~F decoupling capacitor across Vee and GND per
part is recommended. Surface mounted, radial, plastic or
ceramic capacitors are suitable.
Where possible, user designs that could result in many output pads making a simultaneous transition in the same

4- 274

direction should be avoided. This is especially important on
heavily loaded connections to non-XC6200 parts. To minimize power dissipation, redundant connections in user
designs (which may arise in hierarchical design styles to
promote sub-block re-use) should be deleted by CAD programs prior to programming XC6200 devices. As a general
guideline, users should attempt to minimize the number of
cell resources used. Where buffers must drive heavy external loads it may be helpful to choose I/O blocks near GND
pads.
XC6200 parts automatically reset themselves after power
up, since the random values in the control store at this time
could correspond to a relatively high power dissipation configuration.
The XC6200 part distributes power using a redundant
scheme which ensures minimal voltage drop between pads
and internal circuitry. Power for pads is distributed on a separate power and ground ring.
The maximum power consumption of the XC6200 is limited
by two factors: the metal conductors supplying the part and
heat dissipation. The metal conductors can handle up to
100mA each. Heat dissipation is generally a much more
serious consideration: a full discussion of thermal characteristics for the different package options is given in section
4 of this data book.

June 1, 1996 (VerSion 1.0)

~XIUNX
XC6200 Switching Characteristics
Notice: The information contained in this data sheet pertains to products in the initial production phases of development.
These specifications are subject to change without notice. Verify with your local Xilinx sales office that you have the latest
sheet before finalizing a design.

XC6200 Operating Conditions
Parameter

Symbol
Supply voltage relative to GND

Vee
VILT
V ,HT

Commercial

Industrial
Supply voltage relative to GND
LOW-level input voltage - TTL configuration

=0° C to S5° C junction
TJ =-40° C to 1000 C junction
TJ

Max
5.25

4.50

5.50
O.SO

0

High-level input voltage - TTL configuration
LOW-level input voltage

Min
4.75

2.0
0

Vee
20%

70%

100%

- CMOS configuration

V,Le
V ,He

High-level input voltage - CMOS configuration

T,N

Input signal transition time

250

Units
V
V
V
V
V
V
ns

I

XC6200 DC Characteristics Over Operating Conditions
Symbol

Test Conditions

Parameter

10H = -S.O mA
VD D Min
10L =SmA
V DD = Min

VOH

High-level output voltage

VOL

Low-level output voltage

I,L

Input leakage current

loz

Output high-Z leakage current

C,N

Input capacitance for Input and 1/0 pins

2

=

3.86

Units
V

0.4

V

10

!!A

TBA

J.lA

15

pF

TBA

mA

10

V ,N ;: Vee or GND
V DD =5V
f = 1.0 MHz @ 25°C

Quiescent Supply Current

Icc

V DD = Max
V ,N = GND or Vee
VDD;: Max
Vo = GND or Vee
V,N = GND
f = 1.0 MHz

Max

Min

Notes: 1. Sample tested.
2. Measured with no output loads, no active input pull-up resistors and all package pins at Vcc or GND.

XC6200 Absolute Maximum Ratings
Vee
VJN
VTS
TSTG
TSOL

Value

Parameter

Symbol

-0.5 to 7.0

Supply voltage with respect to GND
DC Input voltage with respect to GND
Voltage applied to 3-stateoutput with respect to GND
Storage temperature
Maximumsoldering temperature (10s @ 1/16 in.

= 1.5 tnm)

Units
V
V
V

-0.5 to Vce+0.5
-0.5 to Vee +0.5
-65 to +150

°G

+260

°C

Warning: Stresses beyond those listed under XC6200 Absolute Maximum Ratings may cause permanent damage to the
device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those
listed under XC6200 Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.

June 1, 1996 (Version 1.0)

4-275

XC6200 Field Programmable Gate Arrays

XC6200 Power-on/Reset Timing Parameters

XC6200 Serial Configuration Timing
SEClk

XC6200 Global Buffer Switching Characteristic Guidelines

Note:

Typical loading values are used.

XC6200 Cell Switching Characteristic Guidelines

Notes:

1.Data input measured at input to X1 routing multiplexer. Clock input measured at register.
2.Data input measured at input to X21X3 routing multiplexers. Clock input measured at register.
3.Measured at the actual register in the cell.
4.Typicalloading values are used.

4- 276

June 1, 1996 (Version 1.0)

~XILINX
XC6200 Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly and guaranteed over all the operating conditions. The same parameters can also
be derived indirectly from the lOB and. Global Buffer specifications. The delay calculator software uses this indirect method.
When there is a discrepancy between these two methods, the directly tested values listed below should be used and the
derived values should be ignored.

Parameter

Notes:

I

All appropriate AC specifications tested using Figure 27 as test load circuit.
These parameters are tested directly and guaranteed over the operating conditions.
As the parameters vary between I/Os, values are given for best and worst lias. The parameters for other lias will be
somewhere between these two extremes. The delay calculator software will calculate the correct value for each 1/0 used.
All parameters assume the cell register is. the closest one to the lOB.

XC6200 lOB Switching Characteristic Guidelines
Symbol

Parameter
INPUT
Pad to Neighbor data

Notes:

Units

4

ns

As the parameters vary between lias, values are given for best and worst lias. The parameters for other lias will be
somewhere between these two extremes. The delay calculator software will calculate the correct value for each I/O used.
Typical loading values are used.

June 1, 1996 (Version 1.0)

4-277

XC6200 Field Programmable Gate Arrays

XC6200 Internal Routing Delays

Notes:

Delays vary depending on direction. Worst case figures are given here. The delay calculator software will calculate the correct
delay for each direction.
Typical loading values are used.

XC6200 CPU Interface Timing

Notes:

4- 278

1. CS must be correctly sampled as a '0' at the start of the cycle (t1) and sampled as a '1' at the end of the cycle (t2 ). Other
signals only require to be correctly sampled at t 1 .
2. The minimum time for a read or write cycle is two CPU clock periods, although the cycles shown do not start and finish at the
start of a clock period.
3. Data is removed from the bus TCKDZ after t3 unless CS is still asserted at this time. In this case, data is removed from the bus
asynchronously TCSDZ after CS goes high.

June 1i 1996 (Version 1.0)

~XILINX

SEData
....- - - - - - Synchronization

~rP.-----==~I=::j:~=++

Write Data Word 1

Figure 26: Serial Configuration Timing

Device Output

o------+----~----__o

Test Point

Device Input
Rise and Fall
Times < 3ns

Figure 27: AC Load Circuit

June 1, 1996 (Version 1.0)

4- 279

XC6200 Field Programmable Gate Arrays

GClk

1+--------0 twc - - - - - . ' ,--------

RdWr

A

O

,~--------------------------~~~------------------------------/
Write Cycle

Extended Write Cycle

Figure 28: Configuration Memory Write Cycles

4-280

June 1, 1996 (Version 1.0)

~XILINX

GClk

RdWr

A

C\
D

'~

@tCKOZ

-:

®tCKO

@te"sOZ

I

,

______________________________

~~~

Read Cycle

____________________________________-J/
Extended Read Cycle

Figure 29: Configuration Memory Read Cycles

June 1,1996 (Version 1.0)

4- 281

XC6200 Field Programmable Gate Arrays

XC6200 Pinout Tables
XC6216 Pinouts - West Side
Pin Description
DOIW1\'<:}

GND
W14
NC
D1IW3

W16
D2IWs
Wi8
D3IW7

NC
NC
NC
NC
W20
D4IW g
W22
W24
W26
D5IW 11

NC
NC
GND
W28
W30
W32
D6IW 13
Vee

D16IW33

W34
GND
NC
NC
NC
NC
D7IW 1S
D17IW35

W36
D18IW37
D8IW n

W38
Notes:

4-282

PQ240

PG299

Pin Description

PQ240

PG299

60
59
58
57(1)
56
55
54
53
52

C18
A19
A20
C17(1)
016
E15
B18
817
C16

Vee

30
29
28

-

-

A11
A10
C10
010
A9
E10
B9
C9
A8
B8
09
A7

-

51
50
49
48
47
46

-

45
44
43
42
41
40
39
38
37

36
35
34
33
32
31

015(1)
A18(1)
E14
C15
B16
014
A17
C14
E13(1)
B15\1}
A15
013
B14
C13
A14
A16
B13
E12

-

012(1)
C12(1)
A13(1)
B12(1)
A12
011
E11
C11
B11
B10

GND
D19IW39

W40
D91W 19 .
D20IW41

W42

-

D21IW43
D101W 21

25
24

W44
W46

-

D22IW45

23
22
21
20
19
18
17
16
15
14

GND
W48
WSO

..

27
26

Vee
D241W49
D11IW23
D23IW47
D25IW 51

GND
W52
W54
WS6

-

D13IW27

13
12
11
10
9
8

W60
W62
NC
NC

-

D281W57
D14IW29

7
6
5
4
3
2
1

D12IW25

W58
D26IWs3
D27IWs5

D29IWs9
D15IW 31
D30IW61
D31IW63

GND

E9
C8
A6
B7
C7
08
B6
A5
B5
E8
C6
07
A4
C5
B4
E7
06
A3

-

C4
05
E6
B3
B2
D4
81

1. Pin not connected.
2. Pins with a dual function have the 'Control' signal shown first. See section "Input/Output Blocks (lOBs)" on page 261 for
details.

June

1, 1996 (Version 1.0)

~XIUNX
XC6216 Pinouts - South Side
Pin Description

W S/S 4

PQ240
61
62
63
64
65
66
67
68

NC

-

vee
RdWrlS1

CS/S 3
W12/S o
OE/S 5
W 1O/S 2
ResetlS 7

Pin Description

820

GNO

017
819

G1/S 17
G2/S 19

C19

S42

F16

S41

E17

S44

018

S43

C20

S46

.

S4S
EoIS50
E2/S 52

PQ240
91
92
93
94
' 95

-

PG299
K20
L19
L18
L16
"L17
M20
M19
N2Q
M18

NC

·

-

W 6/S 6

69

F17

W4 /S s
W2/S 1O

70

G16

GNO

98

-

71

019

E4/S 54

99

N19

WoIS 12

72

E18

S45

100

P20

S14

73

020

Vee

101

T20

S16

74

G17

N18

-

F18

S21
SEOatalS 23

102

S1S

103

P19

H16

EslS 56

104

N17

E19

S47
GNO

105

R19

106

R20

S20

-

S22

F19

96

M17

97

M16
,

S24
GNO

75

E20

NC

·

N16

S26

76

H17

NC

-

P18

S33
Serial/S9

77

G18

ES/S 58

107

U20

'78

G19

S49

108

P17

WaitlS 11

79

H18

80

F20

109
" 110

T19

Vee

S51
8 53

S28

81

J16

S55

S35
GNO

82

G20

83

-

S30

·

S57

V20

111

R17

J17

E101S60
E 12/S 62

112

T18

-

H19

NC

H2O

NC

-

S36
GClklS13

·
·

·
·

JI8

U19

114

V19

S38

85

J19
'K16

SECElS 25
SEResetlS 27

113

84

S59

115

R16

GClrlS15

86

J20

T17

K17

117

U.18

S40

87
,', 88

S61
SEClklS29

116

Ki8

118

X20

S39

89

K19

ConfigOK/S31
GNO

119

W20

Vee

90

L20

S63

120

V18

S37

I

R18

·
·

S32
8 34

Note:

' PG299

P16

1. Pin not connected.

June 1,1996 (Version 1.0)

4- 283

XC6200 Field Programmable Gate Arrays

XC6216 Pinouts· East Side
Pin Description

P0240

PG299

Pin Description

P0240

PG299

Vee
E14
AO/E 1
E16
A1IE3
E18
A2IEs
E20

121
122
123
124
125
126
127
128

X19
U17
Wi9
W18
T15
U16
V17
X18
U15'
T14'

GND

151
152
153
154
155
156
157

X11
W10
V10
T10
U10
X9
W9
X8'
V9
U9
T9

NC
NC
NC
NC

-

A3/E7
E22
E24
E26
A4/E9
E28

129
130
131
132
133
134

NC
NC
GND
E30
E32
A5/Ell
E33
Vee
E34
ES5

GND
NC
NC
NC
NC
A6/E1S
ES6
E37
ES8
A7/E 15
ES9
Vee
Note:

4-284

-

135
136
137
138
139
140
141
142
143

-

144
145
146
147
148
149
150

-

A8/E17
E40
A9/E 19
E41
E42
E43

NC
E44
E46
E48

-

GND

W17
V16
X17
U14
V15
T13
W16'
W15'
X16
U13
V14
W14
V13
X15
T12
X14

A10/E21
Eso
Vee
E4S
ES2
A11/E23
E47

U12
W13
X13
V12
. W12
T11
X12
U11
. V11 ,
W11
X10

158
159
160
161
162
163
164
165
166

-

167
168
169
170
171
172

W8
X7
X5
V8
W7
U8
W6
X6
T8
V7
X4
U7
W5
V6
T7
X3

NC
NC

-

-

A13/E27
ES7
E60
E62
A14/E 29
ES9
A1S/Es1
E61
E6S
Vee

173
174

GND
E54
ES6
ES8
E49
A121E2S
ESI
ES3
Ess

-

175
176
177

178
179
180

-

U6
V5
W4
W3
T6
U5
V4
X1
V3
Wi

1. Pin not connected.

June 1, 1996 (Version 1.0)

~XILINX
XC6216 Pinouts - North Side
Pin Description

PQ240

PG299

Pin Description

PQ240

PG299

Vee
NC
Nl
N3
No
N2
N4
N6
N8
N10
NC
NC
N5
N7
N12
N14
N16
N18
N20
N22
GNO
N24
N26
N33
N28
Vee
N30
N32
N34
N36
N35
Ng
GNO
N11
N38
N37
N40
N39
N13
Vee

240

A2

-

-

239
238
237
236
235
234

211
210
209
208
207
206
205
204
203
202

L1
L2
L3
L4
M1
L5
M2

-

C3
03
E4
F5
C2
02
E3
F4

-

-

GNO
N15
N17
N19
N42
N41
N44
GNO
N43
N21
N46
N48
N50
NS2
Vee
N23
NS4
N4S
N56
GNO
NC
N47
NS8
N49
N51
N53
N55
NS7
N60
N62
NC
NC
N59
N25
N27
N61
N63
N29
GNO
N31

--

Note:

233
232
231
230
229
228

-

227
226
225
224
223
222

-

221
220
219
218
217
216
215
214
213
212

C1
G5
F3
E2
G4
01
G3
H5
F1
F2
H4
G2
H3
E1
G1
H2
J5
J4
J3
H1

J2
J1
K4
K5
K3
K2
K1

201
200
199
198
197
196

195
194
193
192
191
190
189

188
187
186
185
184
183
182
181

M3
N1
N2
M4
P1
M5
R1
N3
P2
P3
N4
T1
R21
T2
N5
R3
P4
U1
T3
U2
P5
R4

I

V1
U3
T4
R5
V2
W2
X2
U4

1. Pin not connected.

June 1, 1996 (Version 1.0)

4-285

XC6200 Field Programmable Gate Arrays

Product Availability
Devices are available in small and large packages. The
small packages are useful where board area is at a premium and the design can make use of the wireless I/O parallel CPU interface to determine the state of internal nodes.
The large package options give a very high user programmable I/O count where this is a prime requirement. The
available packaging options for the XC6216 are summarized in Table 6. (These options are advance information
and subject to change. Please confirm availability with Xiiinx.
Signal pins are all the non-supply pins that drive into the
array or control circuitry. Some of these pins are shared
between control signals and user I/O. The un-shared user
1/0s do not share a pin with a control signal. The number of
user 1/0s available will be somewhere between the number

4-286

of signal pins and the number of un-shared I/Os, depending
on how many of the FPGA control signals are actually
required. For example, if only an 8-bit data bus and no
serial interface were required, the number of user I/Os
would go up by 24+6=30 in a PGA299 package.
Table 6: XC6216 Package Options
Package

Pins

Signal Pins

Max Data
Bus Pins

Unshared
User 110

PLCC

84
240
299

68
199
242

16
32
32

22
137
180

PQFP
PGA

June 1, 1996 (Version 1.0)

XC3000 Series Table of Contents

XC3000 Series Field Programmable Gate Arrays
Features ........................................................................ .
Description ...................................................................... .
XC3000 Series Overview ........................................................... .
Detailed Functional Description ...................................................... .
Configuration Memory........................................................ .
I/O Block .................................................................. .
Configurable Logic Block ..................................................... .
Programmable Interconnect ................................................... .
General Purpose Interconnect ............................................. .
Direct Interconnect ..........................................•.........._•.
Longlines ............................................................. .
Internal Busses ......................................................... .
Crystal Oscillator .................................................................. .
Configuration ..............................................................•.......
Initialization Phase ....................................... , .................. .
Configuration Data .......................................................... .
Configuration Modes .......................... , .............................. .
Daisy Chain ..................................•..............................
Special Configuration Functions ................................................ .
Configuration Timing ............................................................... .
Master Serial Mode ...................................................•.... , ..
Master Parallel Mode ........................................................ .
Peripheral Mode ....................................................•........
Slave Serial Mode ........................................................... .
Program Readback Switching Characteristics ..................................... .
General XC3000 Series Switching Characteristics ................................ , ........ .
Device Performance ............................................................... .
Power ...................................................................•.......
Power Distribution .............................................•..............
Dynamic Power Consumption .................................................. .
Power Consumption ......................................................... .
Pin Descriptions .......................................................•...........
Permanently Dedicated Pins ................................................... .
User 110 Pins That Can Have Special Functions ................................... .
Unrestricted User I/O Pins .................................................... .
Pin Functions During Configuration ............................................. .
XC3000 Series Pin Assignments ..................................................... .
XC3000 Series 44-Pin PLCC Pinouts ............................................ .
XC3000 Series 64-Pin Plastic VQFP Pinouts ...................................... .
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts ..................••.....
XC3064A1XC3090AlXC3195A 84-Pin PLCC Pinouts ................................ .
XC3000 Series 100-Pin QFP Pinouts ............................................ .
XC3000 Series 132-Pin Ceramic and Plastic PGA Pinouts .......................... ' ..
XC3000 Series 144-Pin Plastic TQFP Pinouts .............................. : ...... .
XC3000 Series 160-Pin PQFP Pinouts ........................................... .
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts ........................... .
XC3000 Series 176-Pin TQFP Pinouts ........................................... .
XC3000 Series 208-Pin PQFP Pinouts ........................................... .

4-289
4-289
4-290
4-291
4-291
4-292
4-294
4-295
4-296
4-296
4-300
4-302
4-303
4-304
4-304
4-306
4-307
4-307
4-308
4-310
4-310
4-312
4-.314
4-316
4-318
4-319
4-320
4-321
4-321
4-322
4-322
4-323
4-323
4-323
4-324
4-325
4-326
4-327
4-328
4-329
4-330
4-331
4-332
4-333
4-334
4-335
4-336
4-337

I

4c287

XC3000 Series Table of Contents

XC3195A PQ208 and PG223 Pinouts ............................................ 4-338
Product Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ... 4-339
Ordering Information ............ , .. , .. , .. , .. , ...... , ...... , .. , .. , .. , .. , ......... , .,. 4-340

XC3000A Field Programmable Gate Arrays
Features .... , .... , ........ , ..... , .... , , ......... , ......... , .. , .. , .. , ......... , . ,.
Description , . , .... , .. , ......... , . , ........ , ................................. , ... ,.
XC3000A Switching Characteristics ......... , .... , .. , ......................... , . . . . . . ..
XC3000A Operating Conditions , .... , ................... , .. , .................. ,.
XC3000A DC Characteristics Over Operating Conditions , .......................... ,.
XC3000A Absolute Maximum Ratings ...... , ......................... , ..... , ... ,.
XC3000A Global Buffer Switching Characteristics Guidelines ....... ' .......... , . . . . . . ..
XC3000A CLB Switching Characteristics Guidelines. , .. , , . , ................ , .. , . . . ..
XC3000A lOB Switching Characteristics Guidelines .................... , .. , ...... , ..
Product Availability, .. , ... , . , .. , .. , .... , .. , .. , . , ........... , ... , ....... , . . . . . . . . . . ..
Ordering Information .. , ' . , .. , .. , .. , .. , . , .. , .. , ............. , ... , ....... , .. , ...... , ..

4-341
4-341
4-342
4-342
4-342
4-343
4-343
4-344
4-346
4-348
4-348

XC3000L Field Programmable Gate Arrays
Features. , .... , .... , .. , .. , ,. , , .... , ....... , . , ......... , .................. , , . , ....
Description ............. , . , , .. , .. , . , ............ , ... , ............ , .. , ............ ,
XC3000L Switching Characteristics .. , .......... , . ,. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC3000L Operating Conditions ............ , ..... , ... , .. , ............... , .. , . . ..
XC3000L DC Characteristics Over Operating Conditions .. , .. , .. , .. , ....... , .... , .. ,.
XC3000L Absolute Maximum Ratings , ............ , , .. , .. , .. , .. , ............ , .. ,.
XC3000L Global Buffer Switching Characteristics Guidelines ........... , ...... , . . . . . ..
XC3000L CLB Switching Characteristics Guidelines .. , ..... , , . , ... , ......... , .. , . . ..
XC3000L lOB Switching Characteristics Guidelines ... , ..... , , .. , ............ , .. , ....
Product Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-349
4-349
4-350
4-350
4-350
4-351
4-351
4-352
4-354
4-356
4-356

XC3100A Field Programmable Gate Arrays
Features ...................................... , ....... , . . . . . . . . . . . . . . . . . . . . . . . . ..
. Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC3100A Switching Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC3100A Operating Conditions ............................................... ,.
XC3100A DC Characteristics Over Operating Conditions .............................
XC3100A Absolute Maximum Ratings ............................................
XC3100A Global Buffer Switching Characteristics Guidelines ..........................
XC3100A CLB Switching Characteristics Guidelines .................................
XC3100A lOB Switching Characteristics Guidelines .................................
Product Availability. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

4-357
4-357
4-358
4-358
4-358
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XC3100L Field Programmable Gate Arrays
Features ................................................. '. . . .. . . . . . . . . . .. . . . . . . ..
Description .............. , .................... '.' . . .. . . . .. .. . . . . . . . . . . . . . . . . . . . . . ..
XC3100L Switching Characteristics ..... " .............................................
.
XC3100L Operating Conditions ............... " ......... , ......................
XC3100L DC Characteristics Over Operating Conditions .............................
XC3100L Absolute Maximum Ratings .................................. , .........
XC3100L Global Buffer Switching CharaCteristics Guidelines, .........................
XC31 OOL CLB Switching Characteristics Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . ..
XC3100L lOB Switching Characteristics Guidelines ... , . . . . . . . . . .. .. . . . . . . . . . . . . . . . ..
Product Availability .............................. , .. , . , ... '." . , .. , . , , . , .... ' ... , . , .,
Ordering Information. , ' . , , . , ' , , , .. , , . , .. , .... , .. , . , .. , ..... , .. , .. , .... , , .... '.' . , ... ,

4-288

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~XllINX®'

XC3000 Series
Field Programmable Gate Arrays

June 1, 1996 (Version 2.0)

Product Description

Features

•

•

•

•

•

•

•

•

Complete line of four related Field Programmable Gate
Array product families
- XC3000A, XC3000L, XC3100A, XC3100L
Ideal for a wide range of custom VLSI design tasks
Replaces TTL, MSI, and other PLD logic
- Integrates complete sUb-systems into a single
package
.
Avoids the NRE, time delay, and risk "of conventional
masked gate arrays
High-performance CMOS static memory technology
Guaranteed toggle rates of 70 to 370 MHz, logic
delays from 9 to 1.5 ns
System clock speeds over80 MHz
Low quiescent and active power consumption
Flexible FPGA architecture
Compatible arrays ranging from 1,000 to 7,500 gate
complexity
- Extensive register, combinatorial, and I/O
capabilities
High fan-out signal distribution, low-skew clock nets
- Internal 3-state bus capabilities
TTL or CMOS input thresholds
On-chip crystal oscillator amplifier
Unlimited reprogrammability
- Easy design iteration
- In-system logic changes
Extensive packaging options
Over 20 different packages
- Plastic and ceramic surface-mount and pin-gridarray packages
- Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
Ready for volume production
- Standard, off-the-shelf product availability
- 100% factory pre-tested devices
Excellent reliability record

Max logic
Gates

Device
XC3020A,3020l,3120A

1,500
2,000

XC3030A, 3030l, 3130A

~042A, 3042l, 3142A, 3142l
XC3064A, 3064l, 3164A

I

3,000
4,500

XC3090A,3090L,3190A,3190L

6,000

XC319SA

7,SOO

June 1, 1996 (Version 2.0)

Complete XACTstep Development System
Schematic capture, automatic place and route
Logic and timing simulation
- Interactive design editor for design optimization
- Timing calculator
Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others

Description
XC3000-Series Field Programmable Gate Arrays (FPGAs)
provide a group of high-performance, high-density, digital
integrated circuits. Their regular, extendable, flexible, userprogrammable array architecture is composed of a configuration program store plus three types of configurable elements: a perimeter of I/O Blocks (lOBs), a core array of
Configurable Logic Bocks (CLBs) and resources for interconnection. The general structure of an FPGA is shown in
Figure 2. The XACTstep development system provides
schematic captvreand auto place-and-route for design
entry. Logic and timing simulation, and in-circuit emulation
are available as design verification alternatives. The design
editor is used for interactive design optimization, and to
compile the data pattern that represents the configuration
program.
The FPGA user logic functions. and interconnections are
determined by the configUration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. ThecompanionXC17XX Serial Configuration PROMs provide a very simple serial configuration
program storage in a one-time programmable package.
The XC3000 Field Programmable Gate Array families provide a variety of logic capacities, package styles, temperature ranges and speed grades.

Typical Gate
ClBs
Range

Array

1,000 - 1,500
1,500 - 2,000
2,000 - 3,000

64
100

8x8
10 x 10
12 x 12

3,500 - 4,SOO

224
320
484

S,OOO - 6,000
6,SOO - 7,500

144

User I/Os
Flip-Flops
Max

Horizontal
longlines
16
20

Configuration
Data Bits
14,779

64
80

256
360
480

24

16 x 14

96
120

22,176
30,784

688

32

46,064

16x20

144

64,160

176

928
1,320

40

22x22

44

94,984

--

4-289

I

XC3000 Series Field programmable Gate Arrays

XC3000 Series Overview
Introduced in 1987/88, the XC3000 series is the industry's
most successful family of FPGAs, with over 10 million
devices shipped. In 1992/93, Xilinx introduced three additional families, offering more speed, functionality, and a new
supply-voltage option.
There are now four distinct family groupings within the
XC3000 Series of FPGA devices, with emphasis on those
listed below:
•
•
•
•

XC3000A Family
XC3000L Family
XC3100A Family
XC3100L Family

All six families share a common architecture, development
software, design and programming methodology, and also
common package pin-outs. An extensive Product Description covers these common aspects.

•

XC3100A family extends toggle rates to 370 MHz and
in-system performance to over 80 MHz. The XC3100A
family also offers one additional array size, the
XC3195A. The XC31 OOA is best suited for designs that
require the highest clock speed or the shortest net
delays.
XC3100L Family - The XC3100L is identical in
architectures and features to the XC3100A family, but
operates at a nominal supply voltage of 3.3V.

Figure 1 illustrates the relationships between the families.
Compared to the original XC3000 family, XC3000A offers
additional functionality and, coming soon, increased speed.
The XC3000L family offers the same additional functionality, but reduced speed due to its lowersupply volta.ge of
3.3 V. The XC3100A family offers substantially higher
speed and higher density with the XC3195A.

The much shorter individual Product Specifications then
provide detailed parametric information for the XC3000A,
XC3000L, XC3100A, and XC3100L product families. (The
XC3000 and XC3100 families are not recommended for
new designs, and their individual product specifications are
not included in this book.)
Here is a simple overview of those XC3000 products currently emphasized:
XC3000A Family - The XC3000A is an enhanced
version of the basic XC3000 family, featuring additional
interconnect resources and other user-friendly
enhancements. The ease-of-use of the XC3000A family
makes it the obvious choice for all new designs that do
not require the speed of the XC31 OOA or the 3-V
operation of the XC3000L.
XC3000L Family - The XC3000L is identical in
architecture and features to the XC3000A family, but
operates at anominal supply voltage of 3.3 V. The
XC3000L is the right solution for battery-operated and
low-power applications.
XC3100A Family - TheXC3100A is a performanceoptimized relative of the XC3000A family. While both
families are bitstream and footprint compatible, the

4-290

Figure 1: XC3000 FPGA Families

June 1, 1996 (Version 2.0)

~XIUNX
Detailed Functional Description
The perimeter of configurable Input/Output Blocks (lOBs)
provides a programmable interface between the internal
logic array and the device package pins. The array of Configurable logic Blocks (ClBs) performs user-specified logic
functions. The interconnect resources are programmed to
form networkS, carrying logic signals among blocks, analogous to printed circuit board traces connecting MSI/SSI
packages.

bitstream used to configure the device. The memory loading process is independent of the user logic functions.

Configuration Memory
The static memory cell used for the configuration memory
in the Field Programmable Gate Array has been designed
specifically for high reliability and noise immunity. Integrity
of the device configuration memory based on this design is
assured even under adverse conditions. As shown in
Figure 3, the basic memory cell consists of two CMOS
inverters plus a pass transistor used for writing and reading
cell data. The cell is only written during configuration and
only read during read back. During normal operation, the
cell provides continuous control and the pass transistor is
off and does not affect cell stability. This is quite different
from the operation of conventional memory devices, in
which the cells are frequently read and rewritten.

The block logic functions are implemented by programmed
look-up tables. Functional options are implemented by program-controlled multiplexers. Interconnecting networks
between blocks are implemented with metal segments
joined by program-controlled pass transistors.
These FPGA functions are established by a configuration
program which is loaded into an internal, distributed array
of configuration memory cells. The configuration program is
loaded into. the device at power-up and may be reloaded on
command. The FPGA includes logic and control signals to
implement automatic or passive configuration. Program
data may be either bit serial or byte parallel. The XACTstep
development system generates the configuration program

I~: I~:

-FAt:
-tJ=

---1111

I

1/0 Blocks

ff
.t:fyiJ

Uy-

3-Stats Buffers With Access
to Horizontal Long Lines

Configurable Logic
Blocks

y- ------------- y-

O 0
8

'. y-

~

D
c.

y-

p

.

y-

DD

y-

y-

4--

4--

Interconnect Area

p

4--

U

Uyp

P

4--

4--

0

y-

4--

4--

0

y-

~

0..
O)

E
f!!

u.

4-X3241

Figure 2: Field Programmable Gate Array Structure.
It consists of a perimeter of programmable I/O blocks, a core of configurable logic blocks and their interconnect resources.
These are all controlled by the distributed array of configuration program memory cells.

June 1, 1996 (Version 2.0)

4-291

I

XC3000 Series Field Programmable Gate Arrays

testing, no soft errors have been observed even in the presence of very high doses of alpha radiation.
Configuration
1-..---1""'-0 Control

Read or --i!------,
Write
Data

X5382

Figure 3: Static Configuration Memory Cell.
It is loaded with one bit of configuration program and controls one program selection in the Field Programmable
Gate Array.

The memory cell outputs Q and Q use ground and Vee levels and provide continuous, direct control. The additional
capacitive load together with the absence of address
decoding and sense amplifiers provide high stability to the
cell. Due to the structure of the configuration memory cells,
they are not affected by extreme power-supply excursions
or very high levels of alpha particle radiation. In reliability

OUT

DIRECT IN
REGISTERED IN

The method of loading the configuration data is selectable.
Two methods use serial data, while three use byte-wide
data. The internal configuration logic utilizes framing information, embedded in the program data by the XACTstep
development system, to direct memory-cell loading. The
serial-data framing and length-count preamble provide programming compatibility for mixes of various FPGA device
devices in a synchronous, serial, daisy-chain fashion.

I/O Block
Each user-configurable lOB shown in Figure 4, provides an
interface between the external package pin of the device
and the internal user logic. Each lOB includes both registered and direct input paths. Each lOB provides a programmable 3-state output buffer, which may be driven by a
registered or direct output signal. Configuration options
allow each lOB an inversion, a controlled slew rate and a
high impedance pull-up. Each input circuit also provides
input clamping diodes to provide electrostatic protection,
and circuits to inhibit latch-up produced by input currents.

-F---J,L../

--1-'----+-------,
-lI-"'----f-----1

R

OK

=D-

PROGRAM
CONTROLLED

MULTIPLEXER

IK

o '"

PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

Figure 4: Input/Output Block.
Each lOB includes input and output storage elements and liD options selected by configuration memory cells. A choice
of two clocks is available on each die edge. The polarity of each clock line (not each flip-flop or latch) is programmable. A
clock line that triggers the flip-flop on the rising edge is an active Low Latch Enable (Latch transparent) signal and vice
versa. Passive pull-up can only be enabled on inputs, not on outputs. All user inputs are programmed for TTL or CMOS
thresholds.

4-292

June 1, 1996 (Version 2.0)

.~XIUNX
The input-buffer portion of each lOB provides threshold
detection to translate external signals applied to the package pin to internal logic levels. The global input-buffer
threshold of the lOBs can be programmed to be compatible
with either TTL or CMOS levels. The buffered input signal
drives the data input of a storage element, which may be
configured as either a flip-flop or a latch. The clocking polarity (rising/falling edge-triggered flip-flop, High/Low transparent latch) is programmable for each of the two clock lines
on each of the four die edges. Note that a clock line driving
a rising edge-triggered flip-flop makes any latch driven by
the same line on the same edge Low-level transparent and
vice versa (falling edge, High transparent). All Xilinx primitives in the supported schematic-entry packages, however,
are positive edge-triggered flip-flops or High transparent
latches. When one clock line must drive flip-flops as well as
latches, it is necessary to compensate for the difference in
clocking polarities with an additional inverter either in the
flip-flop clock input or the latch-enable input. I/O storage
elements are reset during configuration or by the activeLow chip RESET input. Both direct input (from lOB pin I)
and registered input (from lOB pin 0) signals are available
for interconnect.
For reliable operation, inputs should have transition times
of less than 100 ns and should not be left floating. Floating
CMOS input-pin circuits might be at threshold and produce
oscillations. This can produce additional power dissipation
and system noise. A typical hysteresis of about 300 mV
reduces sensitivity to input noise. Each user lOB includes a
programmable high-impedance pull-up resistor, which may
be selected by the program to provide a constant High for
otherwise undriven package pins. Although the Field Programmable Gate Array provides circuitry to provide input
protection for electrostatic discharge, normal CMOS handling precautions should be observed.
Flip-flop loop delays for the lOB and logic-block flip-flops
are short, providing good performance under asynchronous clock and data conditions. Short loop delays minimize
the probability of a metastable condition that can result
from assertion of the clock during data transitions. Because
of the short-loop-delay characteristic in the Field Programmable Gate Array, the lOB flip-flops can be used to synchronize external signals applied to the device. Once
synchronized in the lOB, the signals can be used internally
without further consideration of their clock relative timing,
except as it applies to the internal logic and routing-path
delays.
lOB output buffers provide CMOS-compatible 4-mA
source-or-sink drive for high fan-out CMOS or TTL- com-

June 1, 1996 (Version 2.0)

patible signal levels (8 mA in the XC3100A family). The network driving lOB pin 0 becomes the registered or direct
data source for the output buffer. The 3-state control signal
(lOB) pin T can control output activity. An open-drain output
may be obtained by using the same signal for driving the
output and 3-state signal nets so that the buffer output is
enabled only for a Low.
Configuration program bits for each lOB control features
such as optional output register, logic signal inversion, and
3-state and slew-rate control of the output.
The program-controlled memory cells of Figure 4 control
the following options.
•

Logic inversion of the output is controlled by one
configuration program bit per lOB.
• Logic 3-state control of each lOB output buffer is
determined by the states of configuration program bits
that turn the buffer on, or off, or select the output buffer
3-state control interconnection (lOB pin T). When this
lOB output control signal is High, a logic one, the buffer
is disabled and the package pin is high impedance.
When this lOB output control signal is Low, a logic zero,
the buffer is enabled and the package pin is active.
Inversion of the buffer 3-state control-logic sense
(output enable) is controlled by an additional
configuration program bit.
• Direct or registered output is selectable for each lOB.
The register uses a positive-edge, clocked flip-flop. The
clock source may be supplied (lOB pin OK) by either of
two metal lines available along each die edge. Each of
these lines is driven by an invertible buffer.
• Increased output transition speed can be selected to
improve critical timing. Slower transitions reduce
capacitive-load peak currents of non-critical outputs
and minimize system noise.
• An internal high-impedance pull-up resistor (active by
default) prevents unconnected inputs from floating.

Summary of I/O Options
•

•

Inputs
- Direct
Flip-flop/latch
- CMOSITTL threshold (chip inputs)
- Pull-up resistor/open circuit
Outputs
Direct/registered
Inverted/not
- 3-state/on/off
Full speed/slew limited
3-state/output enable (inverse)

4-293

I

XC3000 Series Field Programmable Gate

Arr~ys

Configurable Logic Block
The array of CLBs provides the functional elements from
which the user's logic is constructed. The logic blocks are
arranged in a matrix within the perimeter of lOBs. For
example, the XC3020A has 64 such blocks arranged inS
rows and 8 columns. The XACTstep development system is
used to compile the configuration data which is to be
loaded into the internal configuration memory to define the
operation and interconnection of each block. User definition
of CLBs and their interconnecting networks may be done
by automatic translation from a schematic-capture logic
diagram or optionally by installing library or user macros.
Each CLB has a combinatorial logic section, two flip-flops,
and an internal control section. See Figure 5. There are:
five logic inputs (A, B, C, 0 and E); a common clock input
(K); an asynchronous direct RESET input (RD); and an
enable clock (EC). All may be driven from the interconnect

resources adjacent to the blocks. Each CLB also has two
outputs fX and V) which may drive interconnect networks.
Data input for either flip-flop within a CLB is supplied from
the function For G outputs of the combinatorial logic, or the
block irput, 01. Both flip-flops in each CLB share the asynchrondu~ RD which, when enabled and High, is dominant
over cldcked inputs. All flip-flops are reset by the active-Low
chip input, RESET, or during the configuration process. The
flip-flop~ share the enable clock (EC) which, when Low,
recirculates the flip-flops' present states and inhibits
responsE! to the data-in or combinatorial function inputs on
a CU3. The user may enable these control inputs and select
their sources. The user may also select the clock net input
(K), as well as its active sense within each CLB. This programmable inversion eliminates the need to route both
phases of a clock signal throughout the device. Flexible
routing allows use of common or individual CLB clocking.

OATAIN +-'0"-1_ _ _ _ _ _ _ _---,

OX
A

F

B
LOGIC
VARIABLES

COMBINATORIAL

C

FUNCTION

0
E

G
~

Oy

I>

X3Q32

Figure 5: Configurable Logic Block.
Each CLB includes a combinatorial logicsection, two flip-flops and a program memory controlled multiplexer selection of
function. It has the following:
- five logic variable inputs A, 8, C, 0, and E
- a direct data in 01
an enable clock EC
- a clock (invertible) K
- an asynchronous direct RESET RD
- two outputs X and V

4-294

June 1, 1996 (Version 2.0)

~XILINX
The combinatorial-logic portion of the CLB uses a 32 by 1
look-up table to implement Boolean functions. Variaples
selected from the five logic inputs and two internal block
flip-flops are used as table address inputs. The combinato,
rial propagation delay through the network is independent
of the logic function generated and is spike free for single
input variable changes. This technique can generate two
independent logic functions of up to four variables each as
shown in Figure 6a, or a single function of five variables as
shown in Figure 6b, or some functions of seven variables as
shown in Figure 6c.Figure 7 shows a modul0-8 binary
counter with parallel enable. It uses one CLB of each type.
The partial functions of six or seven variables are implemented using the input variable (E) to dynamically select
between two functions of four different variables. For the
two functions of four variables each, the independent
results (F and G) may be used as data inputs to either flipflop or either logic block output. For the single function of
five variables and merged functions of six or seven variables, the F and G outputs are identical. Symmetry of the F
and G functions and the flip-flops allows the interchange of
CLB outputs to optimize routing efficiencies of the networks
interconnecting the CLBs and lOBs.

Programmable Interconnect
Programmable-interconnection resources in the Field Programmable Gate Array provide routing paths to connect
inputs and outputs of the lOBs and CLBs into logic networks. Interconnections between blocks are composed of a
two,layer grid of metal segments. Specially designed pass
transistors, each controlled by a configuration bit, form programmable interconnect points (PIPs) and switching matrices used to implement the. necessary connections between
selected metal segments and block pins. Figure 8 is an
example of a routed net. The XACT step development system provides automatic routing of these interconnections.
Interactive routing (Editnet) is also available for design optimization. The inputs of the .GLBs or 10Bs.are multiplexers
which can be programmed to select an input network from
the adjacent interconnect· segments. Since the switch

connections to block inputs are unidirectional,as are
block outputs, they are usable only for block input connection and not for routing. Figure 9 illustrates routing
access to logic block input variables, control inputs and
block outputs. Three types of metal resources are provided
to accommodate. various network interconnect require·
ments.
•
•
•

General Purpose Interconnect
Direct Connection
Longlines (multiplexed busses and wide AND gates

June 1, 1996 (Version 2.0)

A
8
Q

C
D

~
V}-

Any Function
ofUpto4
Variables

-F

v
A
B
Q

C
D

A
8
Q

C

~
VIJ~

Any FUnction

ofUpto4
Variables

5a

Any Function
of 5 Variables

v

D

E

-G

I

{:
5b

A
8

I
Q

C
D

F
M
U
X

A
8
Q

C
D

~

Any Function
ofUpto4
Variables

L"iC

G

Any Function
ofUpto4
Variables

v

5c

FGM
Mode
X5442

Figure 6: Combinational Logic Options

6a. Combinatorial Logic Option FG generates two func·
tions of four variables each. One variable, A, must be
common to both functions. The second and third variable
can be any choice of B, C, QX and QY. The fourth vari·
able can be any choice of D or E.
6b. Combinatorial Logic Option F generates any function
of five variables: A, D, E and two choices out of B, C, QX,
QV.
6c. Combinatorial Logic Option FGM allows variable E to
select between two functions of four variables: Both have
COmmon inputs A and D and any choice out of B, C, QX
and QV for the remaining two variables. Option 3 can
then implement some functions of six or seven variables.

4·295

XC3000 Series Field Programmable Gate Arrays

Count Enable ==;-n=r=;~:::::==:::::==:::::==C>ParaUel E~~~~~

___

+;Termlnal
Count

INTERCONNECT
"PIPs·

t-

.~.:

. t- .. : / '

t-·.:

.

.. 0····
. . .....
.. .. ........... 0
0 ···
"

Dual Function of 4 Variables

SWITCHING
MATRIX

~- ..

.

:

".

.

.

"'::'

.',

:

..

~-":'

"

:.'

4-: .:
CONFIGURABLE
LOGIC BLOCK

Function 016 Variables

L--===:=======:'J

FGM

Figure 8: An XACT Design Editor view of routing
resources used to form a typical interconnection
network from CLB GA.

Mode
X5383

Figure 7: C8BCP Macro.
The C8BCP macro (moduI0-8 binary counter with parallel
enable and clock enable) uses one combinatorial logic
block of each option.

General Purpose Interconnect
General purpose interconnect, as shown in Figure 10, consists of a grid of five horizontal and five vertical metal segments located between the rows and columns of logic and
lOBs. Each segment is the height or width of a logic block.
Switching matrices join the ends of these segments and
allow programmed interconnections between the metal grid
segments of adjoining rows and columns. The switches of
an unprogrammed device are all non-conducting. The connections through the switch matrix may be established by
the. automatic routing or by using Editnet to select the
desired pairs of matrix pins to be connected or disconnected.· The legitimate switching matrix combinations for
each pin are indicated in Figure 11 and may be highlighted
by the use of the Show-Matrix command in the XACT
Design Editor.
Special buffers within the general interconnect areas provide periodic signal isolation and restoration for improved
performance of lengthy nets. The interconnect buffers are
available to propagate signals in either direction on a given
general interconnect segment. These bidirectional (bidi)
buffers are found adjacent to the switching matrices, above

4-296

INTERCONNECT
BUFFER

and to the right and may be highlighted by the use of the
ShowBIDI command in the XACT Design Editor. The other
PIPs adjacent to the matrices are accessed to or from Longlines. The development system automatically defines the
buffer direction based on the location of the interconnection
network source. The delay calculator of the XACTstep
development system automatically calculates and displays
the block, interconnect and buffer delays for any paths
selected. Generation of the simulation nellist with a worstcase delay model is provided by an XACT option.

Direct Interconnect
Direct interconnect, shown in Figure 12, provides the most
efficient implementation of networks between adjacent
CLBs or 1/0 Blocks. Signals routed from block to block
using the direct interconnect exhibit minimum interconnect
propagation and use no general interconnect resources.
For each CLB, the X output may be connected directly to
the 8 input of the CLB immediately to its right and to the C
input of the CLB to its left. The Y output can use direct interconnect to drive the D input of the block immediately above
and the A input of the block below. Direct interconnect
should be used to maximize the speed of high-performance
portions of logic. Where logic blocks are adjacent to lOBs,
direct connect is provided alternately to the lOB inputs (I)
and outputs (0) on all four edges of the die. The right edge
provides additional direct connects from CLB outputs to
adjacent 108s. Direct interconnections of lOBs with CLBs
are shown in Figure 13.

June 1, 1996 (Version 2.0)

~XILINX

'::EJ .,

:'.' '::.E}
..
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t-,,'

.0 ...

+.'

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I
CLB LOGIC INPUTS

CLB CONTROL INPUTS

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. .
. .

J. ...

....I .. ... .• . .•

...

...,..

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·
"'0"
..
..
0 ··... ····0·· ····0
+- .. '
.. ... '
..
00.

I

:

...
....

.....

J. .. .
:

.0....
....

. . . . ,

" t- .. '

'::{5

.".....

: :

:

...... ........
...,..

..

. . . . .

'"

: :

:

'::0

:

:

:

....

..

~

..

'::·0

..

........

t-'

'::C

Figure 9: XACT Design Editor Locations of interconnect access, CLB control inputs, logic inputs and outputs.The dot
pattern represents the available programmable interconnection points (PIPs).
Some of the interconnect PIPs are directional. This is indicated on the XACT Design Editor status line:
ND is a nondirectional interconnection.
D:H->V is a PIP that drives from a horizontal to a vertical line.
D:V->H is a PIP that drives from a vertical to a horizontal line.
D:C-> T is a "T" PIP that drives from a cross of a T to the tail.
D:CW is a corner PIP that drives in the clockwise direction.
PO indicates the PIP is non-conducting, P1 is on.

June 1 , 1996 (Version 2.0)

4-297

XC3000 Series Field Programmable Gate Arrays

':.-·15
: .' 1""

·W.·.·
: .' t·.~.

·U

r.:.:.· t

..... 0:·
:.-:.::.::.. 0·:· :.-:.: ...: :
..
~

:

'

t·.~.

.. ~.~~~~
.

,

'.

:: ..... .fFGl

.. :ffQ ::'::

SWITCHING
MATRIX

·:.-El
GRID OF GENERAL INTERCONNECT
METAL SEGMENTS

Figure 10: FPGA General-Purpose Interconnect.
Composed of a grid of metal segments that may be interconnected through switch matrices to form networks for
CLB and lOB inputs and outputs.

..'

1""'. ~.

~

:

.
.
t
.. 0 . . . . 0 .. . .. .
.
..::-. :
:" ..::... :" ..::-. :

..

>0

~

.. '

\~.

"

. +- .. '

.

..

~

:, :

,.=":

Figure 12: CLB X andY Outputs.
The X and Y outputs of each CLB have single contact,
direct access to inputs of adjacent CLBs

C ~~~~
7 ~~~Q
111~ ~ ~. e
Q~
~~ ~ ~ e 6
-

1

2

=1 111=

III

6

-

3

-III I ;

7

8

1= =11

::

16

II

II

17

I

5

4

II

9

I

~I::

;11 1118

IIII
10

= INI=

III

19

20

383 16

Figure 11: Switch Matrix Interconnection Options for
Each Pin.
Switch matrices on the edges are different. Use Show
Matrix menu option in the XACT Design Editor.

4-298

June 1, 1996 (Version 2.0)

~XILINX
Global Buffer Inerconnect

I

o
* Unbonded lOBs (6 Places)

Figure 13:

Alternate BufferDirect Input

XC3020A Die-Edge lOBs. The XC3020A die-edge lOBs are provided with direct access to adjacent CLBs.

June 1, 1996 (Version 2.0)

4-299

XC3000 Series Field Programmable Gate Arrays

Longlines

two vertical Longlines in each column are connectable halllength lines. On the XC3020A, only the outer Longlines are
connectable hall-length lines.

The Longlines bypass the switch matrices and are intended
primarily lor signals that must travel along distance, or
must have minimu.m skew among multiple destinations.
Longlines, shownin Figure 14, run vertically and horizontally the height or width 01 the interconnect area. Each interconnection column has three vertical Longlines, and each
interconnection row has two horizontal Longlines. Two
additional Longlines are located adjacent to the outer sets
01 switching matrices. In devices larger. than the XQ3020A,

....
GLOBAL. .
•
••
~
BUFFER~' ,,:~:,::,-:;,

3 VERTICAL LONG LINES

..· ':" bb
"'-bb
.: . ::.::0' ,:,.,:bb
.. : :.:0 -~.,,: :.:0.'

::g,) .... ~.:.:.:.: , 0
.....
'.

.
p

ON-CHIP
3-STATE
SUFFERS

t .......
·· .

Longlines can be driven by a logi9.block or lOB output on a
column-by-column basis. This cap?bility provides a common low skew control or clock line within each column 01
logic blocks; lriterconnections 01 these 'l.onglines are shown
in Figure 15..Iselation buffers are provided at each input to
a Longline and are enabl.ed al)tomaticallyby the development system wh.eri a connection is made.

•

• •• •

•

.I.' ,. . .••
. ' , . .I....
..
I.
• • • • •

• •

•

.....

.'.

PIJLL~UP

••••

,"

'. • •

• '"

: "

: "

.....

~.'

t.:··'
~ "'"

..:w.

.. ..
•

II

••

•

.',

.....
..

. t".:··

·a·:·:::
...

RESISTORS
FOR ON-CHIP
OPEN DRAIN
. SIGNALS

::0 .
::f9} .'. :
Et .':'
:

p t"';

0 ··

2 HORIZ¢NTAL LONG LINES

. ram ":':':
'U'"

.t- .;

'::'

'.'

. t-.;;

.ran
...
U ....
.' t·.:

X1243

Figure 14: Horizontal and Vertical Longlines. These Longlines provide high lan-out, low-skew signal distribution in
each row and column. The global buffer in the upper left die corner drives a common line throughout the FPGA.

4-300

June 1,1996 (Version 2.0)

~XIUNX

_

• FOUR OUTER LONG LINES ARE
CONNECTABLE HALF-LENGTH LINES

-,E~====;=~;====;~~===~~~:;==;;;;;~===;~_I/OBLOCKCLOCK NETS

~~2J;;L~~gW~4;J;4~~;L~~~g~'~:~R~.:~7

(2 PERDIE EDGE)

3-STATE
BUFFERS

I
X12¥SCAN

Figure 15: Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Threestate buffers allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two nonclock vertical Longlines per column (except XC3020A) and the outer perimeter Longlines may be programmed as
connectable half-length lines.

vcc

vcc

~

~

:'"~-

Figure 16: 3-State Buffers Implement a Wired-AND Function. When aU the buffer3-state lines are High, (high
impedance), the pull-up resistor(s) provide the High output. The buffer inputs are driven by the control signals or a Low.

KEEPER CIRCUIT

Figure 17: 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.

June 1, 1996 (Version 2.0)

XC3000 Series Field Programmable Gate Arrays

A buffer in the upper left corner of the FPGA chip drives a
global net which is available to all K inputs of logic blocks.
Using the global buffer for a clock signal provides a skewfree, high fan-out, synchronized clock for use at any or all of
the lOBs and CLBs. Configuration bits for the K input to
each logic block can select this global line or another routing resource as the clock source for its flip-flops. This net
may also be programmed to drive the die edge clock lines
for lOB use. An enhanced speed, CMOS threshold, direct
access to this buffer is available at the se.cond pad from the
top of the left die edge.

of the 3-state buffer controls allows them to implement wide
multiplexing functions. Any 3-state buffer input can be
selected as drive for the horizontal long-line bus by applying a Low logic level on its 3-state control line. See
Figure 16. The user is required to avoid contention which
can result from multiple drivers with opposing logic levels.
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND function.
A logic High .on both buffer inputs creates a high impedance, which represents no contention. A logic Low enables
the buffer to drive the Longline Low. See Figure 17. Pull-up
resistors are available at each end of the Longline to provide a High output when all connected buffers are non-conducting. This forms fast, wide gating functions. When data
drives the inputs, and separate signals drive the 3-state
control lines, these buffers form multiplexers (3-state busses), In this case, care must be used to prevent contention
through multiple active buffers of conflicting levels on a
common line. Each horizontal Longline is also driven by a
weak keeper circuit that prevents undefined floating levels
by maintaining the previous logic level when the line is not
driven by an active buffer or ap411-up resistor. Figure 18
shows 3-state buffers, Longlines and pull-up resistors.

A buffer in the lower right corner of the array drives a horizontal Longline that can drive programmed connections to
a vertical Longline in each interconnection column. This
alternate buffer also has low skew and high fan-out. The
network formed by this alternate buffer's Longlines can be
selected to drive the K inputs of the CLBs. CMOS threshold, high speed access to this buffer is available from the
third pad from the bottom of the right die edge.

Internal Busses
A pair of 3-state buffers, located adjacent to each CLB, permits logic to drive the horizontal Longlines. Logic operation

BIDIRECTIONAL
INTERCONNECT
BUFFERS

II

I

3 VERTICAL LONG
LINES PER COLUMN

GLOBAL NET

IJ,~I

~

~III

11

-

~~
y

r-

-

I

~

IO

r-

{>.

f--

~

P47
r

+

.

I

,......
'-n-

-

1

c y,;
~~

'-r-r-

lE

-

0
r;:Je;

I)

~

BCi.
~

1-"-...

:--.
---=---=--

V

OSCILLATOR
AMPLIFIER OUTPUT

V

DIRECTINPUT OF P47
TO AUXILIARY BUFFER

-Q

e:Je:J 1

3·STATE INPUT

r----.

6'
~
~

3·STATE CONTROL

1.lk

0

0

CRYSTAL OSCILLATOR
BUFFER

-=
ck

r-~ ill
11
~
0

:f

HORIZONTAL LONG LINE

KIN

I

7J

~

:I

r

r;- II

.--

HG

1/0 CLOCKS

tJ V

-dJ y

-0

}

--

-2;

II I

0

3-STATE BUFFER

~ ALTERNATE BUFFER

EJ

X1245

Figure 18: XACT DeSign Editor.
An extra large view of possible interconnections in the lower right corner of the XC3020A.

4-302

June 1, 1996 (Version 2,0)

~:XILINX
Crystal Oscillator
Figure 18 also shows the location of an internal high speed
inverting amplifier that may b.e used to implement an onchip crystal oscillator. It is associated with the auxiliary
buffer in the lower right corner of the die. When the oscillator is configured by MakeBits and connected as a signal
source, two special user lOBs are also configured to connect the oscillator amplifier with external crystal oscillator
components as shown in Figure 19. A divide by two option
is available to assure symmetry. The oscillator circuit
becomes active early in the configuration process to allow
the oscillator to stabilize. Actual internal connection is
delayed until completion of configuration. In Figure 19 the
feedback resistor R1, between the output and input, biases
the amplifier at threshold. The inversion of the amplifier,
together with the R-C networks and an AT-cut series resonant crystal, produce the 360-degree phase shift of the

Pierce oscillator. A series resistor R2 may be included to
add to the amplifier output impedance when needed for
phase-shift control, crystal resistance matching, or to limit
the amplifier input swing to control clipping at large amplitudes. Excess feedback voltage may be corrected by the
ratio of C21C1. The amplifier is designed to be used from 1
MHz to about one-half the specified CLB toggle frequency.
Use at frequencies below 1 MHz may require individual
characterization with respect to a series resistance. Crystal
oscillators above 20 MHz generally require a crystal which
operates in a third overtone mode, where the fundamental
frequency must be suppressed by an inductor acrosS C2,
turning this parallel resonant circuit to double the fundamental crystal frequency, Le., 2/3 of the desired third harmonic frequency network. When the oscillator inverter is
not used, these lOBs and their package pins are available
for general user I/O.

I
Internal

Alternate
Clock Buffer

External

XTALl

D
D

XTAL2
(IN)

Rl
Suggested Component Values
Rl 0.5-1 MQ
R2 0-1 kQ
(may be required for low frequency, phase
shift and/or compensation level for crystal Q)
Cl, C2 10-40pF
Yl 1 - 20 MHz AT-cut parallel resonant

I XTAL 1 (OUT)
I

XTAL2(IN)

44 PIN 68 PIN
PLCC PLCC
30
47
26
43

84 PIN
PLCC
PGA
57
Jl1
53
L11

100 PIN
CQFP PQFP
67
82
76
61

R2

0
Yl
ICl

132 PIN
PGA
P13
M13

IC2

160 PIN
PQFP
82
76

164 PIN
CQFP
105
99

175 PIN 176 PIN 208 PIN
PGA
TQFP
PQFP
T14
110
91
P15
85
100
X7064

Figure 19: Crystal Oscillator Inverter. When activated in the MakeBits program and by selecting an outputnetwork for
its buffer, the crystal oscillator inverter uses two unconfigured package pins and external components to implement an
oscillator. An optional divide-by-two mode is available to assure symmetry.

June 1, 1996 (Version 2.0)

4-303

XC3000 Series Field Programmable Gate Arrays

Configuration
Initialization Phase
An internal power-on-reset circuit is triggered when power
is applied. When Vee reaches the voltage at which portions
of the FPGA device begin to operate (nominally 2.5 to 3 V),
the programmable 1/0 output buffers are 3-stated and a
high-impedance pull-up resistor is provided for the user
I/O pins. A time-out delay is initiated to allow the power supply voltage to stabilize. During this time the power-down
mode is inhibited. The Initialization state time-out (about 11
to 33 ms) is determined by a 14-bit counter driven by a selfgenerated internal timer. This nominal 1-MHz timer is subject to variations with process, temperature and power supply. As shown in Table 1, five configuration mode choices
are available as determined by the input levels of three
mode pins; MO, M1 and M2.

Table 1: Configuration Mode Choices
MO M1 M2 CCLK
0 output
0
0
1 output
0
0
0
1
0 1 output
0
1
1
0
0 1 output
1
0
0 1
1
1
1
1 input

Mode
Master
Master
reserved

Data
Bit Serial
Byte Wide Addr. - 0000 up

Byte Wide Addr.
Master
reserved
Peripheral Byte Wide
reserved
Slave
Bit Serial

FFFFdown

In Master configuration modes, the device becomes the
source of the Configuration Clock (CCLK). The beginning of
configuration of devices using Peripheral or Slave modes
must be delayed long enough for their initialization to be
completed. An FPGA with mode lines selecting a Master
configuration mode extends its initialization state using four
times the delay (43 to 130 ms) to assure that all daisychained slave devices, which it may be driving, will be
ready even if the master is very fast, and the slave(s) very
slow. Figure 20 shows the state sequences. At the end of
initialization, the device enters the Clear state where it
clears the configuration memory. The active Low, opendrain initialization signal INIT indicates when the Initialization and Clear states are complete. The FPGA tests for the
absence of an external active Low RESET before it makes
a final sample of the mode lines and enters the Configuration state. An external wired-AND of one or more INIT pins
can be used to control configuration by the assertion of the
active-Low RESET of a master mode device or to signal a
processor that the FPGAs are not yet initialized.
If a configuration has begun, a re-assertion of RESET for a
minimum of three internal timer cycles will be recognized
and the FPGA will initiate an abort, returning to the Clear
state to clear the partially loaded configuration memory
words. The FPGA will then resample RESET and the mode
lines before re-entering the Configuration state.
A re-program is initiated.when a configured XC3000 series
device senses a High-to-Low transition and subsequent >6
J.ls Low level on the DONE/PROG package pin, or, if this pin
is externally held permanently Low, a High-to-Low transi-

All User 1/0 Pins 3·Stated with High Impedance Pull· Up, HDC;High, LDC;Low
A

INIT Output; Low
PWRDWN
Inactive
PWRDWN
Active

Active RESET
Operates on
User Logic

Low on DONE/PROGRAM and RESET

Power-On Delay is
214 Cycles for Non-Master Mode-11 to 33 ms
2 16 Cycles for Master Mode-43 to 130 ms

Clear Is
- 200 Cycles for the
- 250 Cycles for the
-290 Cycles for the
- 330 Cycles for the
- 375 Cycles for the

XC3020A-130 to 400
XC3030A-165 to 500
XC3042A-195 to 580
XC3064A-220 to 660
XC3090A-250 to 750

~s
~s

~s
~s
~s

X3399

Figure 20: A State Diagram of the Configuration Process for Power-up and Reprogram.

4-304

June 1, 1996 (Version 2.0)

~XILINX
tion and subsequent >6 /-ls Low time on the RESET package pin.
The device returns to the Clear state where the configuration memory is cleared and mode lines re-sampled, as for
an aborted configuration. The complete configuration program is cleared and loaded during each configuration program cycle.
Length count control allows a system of multiple Field Programmable Gate Arrays, of assorted sizes, to begin operation in a synchronized fashion. The configuration program
generated by the MakePROM program of the XACTstep
development system begins with a preamble of

11111111
0010
< 24-Bit Length Count>
1111

111111110010 followed by a 24-bit length count representing the total number of configuration clocks needed to complete loading of the configuration program(s). The data
framing is shown in Figure 21. All FPGAs connected in
series read and shift preamble and length count in on positive and out on negative configuration clock edges. A
device which has received the preamble and length count
then presents a High Data Out until it has intercepted the
appropriate number of data frames. When the configuration
program memory of an FPGA is full and the length count
does not yet compare, the device shifts any additional data
through, as it did for preamble and length count. When the
F{GA configuration memory is full and the length count

-Dummy Bits'
]
-Preamble Code
-Configuration Program Length
-Dummy Bits (4 Bits Minimum)

o  111
o  111
o  111

o  111
o  111
1111

I

Header

I

For XCB120
197 Configuration Data Frames

Program Data

(Each Frame Consists of:
A Start Bit (0)
A 71-Bit Data Field
Three Stop Bits

Repeated for Each Logic
Ceil Array in a Daisy Chain

Postamble Code (4 Bits Minimum)

*The LeA Device Require Four Dummy Bits Min; XACT Software Generates Eight Dummy Bits

Device
Gates
CLBs
Row x Col

X5300

XC3020A
XC3020L
XC3120
XC3120A

XC3030A
XC3030L
XC3130A

XC3042A
XC3042L
XC3142A
XC3142L

XC3064A
XC3064L
XC3164A

XC3090A
XC3090L
XC3190A
XC3190L

XC3195A

1,000 to 1,500

1,500 to 2,000

2,000 to 3,000

3,500 to 4,500

5,000 to 6,000

6,500 to 7,500

64

100

144

224

320

484

(8x8)

(10 x 10)

(12 x 12)

(16x 14)

(20 x 16)

(22 x 22)

lOBs

64

80

96

120

144

176

Flip-flops

256

360

480

688

928

1,320

Horizontal Longlines

16

20

24

32

40

44

TBUFs/Horizontal LL

9

11

13

15

17

23

75

92

108

140

172

188

Bits per Frame
(includingl start and 3 stop bits)
Frames

197

241

285

329

373

505

Program Data =
Bits x Frames + 4 bits
(excludes header)

14,779

22,176

30,784

46,064

64,160

94,944

PROM size (bits) =
Program Data
+ 40-bit Header

14,819

22,216

30,824

46,104

64,200

94,984

Figure 21: Internal Configuration Data Structure for an FPGA. This shows the preamble, length count and data
frames generated by the XACtstep Development System.
The Length Count produced by the MakeSits program = [(40-bit preamble + sum of program data + 1 per daisy chain
device) rounded up to multiple of 8]- (2 $; K $; 4) where K is a function of DONE and RESET timing selected. An additional
8 is added if roundup increment is less than K. K additional clocks are needed to complete start-up after length count is
reached.

June 1, 1996 (Version 2.0)

4-305

XC3000 Series Field Programmable Gate Arrays

compares, the device will execute a synchronous start-up
sequence and become operational. See Figure 22. Two
CCLK cycles after the completion of loading configuration
data, the user I/O pins are enabled as configured. As
selected in MakeBits, the internal user-logic RESET is
released either one clock cycle before or after the I/O pins
become active. A similar timing selection is programmable
for the DONE/PROG output signal. DONE/PROG may also
be programmed to be an open drain or include a pull-up
resistor to accommodate wired ANDing. The High During
Configuration (HDC) and Low During Configuration (LDC)
are two user 110 pins which are driven active while an
FPGA is in its Initialization, Clear or Configure states. They
and DONE/PROG provide signals for control of external
logic signals such as RESET, bus enable or PROM enable
during configuration. For parallel Master configuration
modes, these signals provide PROM enable control and
allow the data pins to be shared with user logic signals.
User I/O inputs can be programmed to be either TTL or
CMOS compatible thresholds. At power-up, all inputs have
TTL thresholds and can change to CMOS thresholds at the
completion of configuration if the user has selected CMOS
thresholds. The threshold of PWRDWN and the direct clock
inputs are fixed at a CMOS level.
If the crystal oscillator is used, it will begin operation before
configuration is complete to allow time for stabilization
before it is connected to the internal circuitry.

Configuration Data
Configuration data to define the function and interconnection within a Field Programmable Gate Array is loaded from
an external storage at power-up and after a re-program signal. Several methods of automatic and controlled loading of
the required data are available. Logic levels applied to
mode selection pins at the start of configuration time determine the method to be used. See Table 1. The data may be
either bit-serial or byte-parallel, depending on the configuration mode. The different FPGAs have different sizes and
numbers of data frames. To maintain compatibility between
various device types, the Xilinx product families use compatible configuration formats. For the XC3020A, configuration requires 14779 bits for each device, arranged in 197
data frames. An additional 40 bits are used in the header.
See Figure 22. The specific data format for each device is
produced by the MakeBits command of the development
system and one or more of these files can then be combined and appended to a length count preamble and be
transformed into a PROM format file by the MakePROM
command of the XACTstep development system. A compatibility exception precludes the use of an XC2000-series
device as the master for XC3000-series devices if their
DONE or RESET are programmed to occur after their outputs become active. The Tie Option of the MakeBits program defines output levels of unused blocks of a design
and connects these to unused routing resources. This prevents indeterminate levels that might produce parasitic
Postamble

-12 __

~24_

Preamble

Length Count

4



Last Frame

Data Frame

...------------.~I~.~\------------~I

1

DIN

Data

Start
Bit

Length Count'
Start
Bit

• The configuration data consists of a composite
40-blt preamble/length count, followed by one or
more concatenated FPGA programs, separated by
4-bit postambles. An additional final postamble bit
is added for each slave device and the result rounded
up to a byte boundary. The length count is two less
than the number of resulting bits.
Timing of the assertion of DONE and
termination of the INTERNAL RESET
may each be programmed to occur
one cycle before or after the I/O outputs
become active.
Heavy lines indicate the default condition

Weak Pull-Up

I
I

I/O Active

I

iii
III
I
I

Internal Reset

I
I

DONE

I
I

X5988

Figure 22: Configuration and Start-up of One or More FPGAs.

4-306

June 1, 1996 (Version 2.0)

~XILINX
supply currents. If unused blocks are not sufficient to com.
plete the tie, the Flagnet command of EditLCA can be.used
to indicate nets which must not be used to drive the remaining unused routing, as that might affect timing of user nets.
Norestore will retain the results of tie for timing analysis
with Querynet before Restore returns the design to the
untied condition. Tie can be omitted for quick breadboard
iterations where a few additional milliamps of Icc are
acceptable.
The configuration bitstream begins with eight High preamble bits, a 4-bit preamble code and a 24-bit length count.
When configuration is initiated, a counter in the FPGA is set
to zero and begins to count the total number of configuration clock cycles applied to the device. As each configuration data frame is supplied to the device, it is internally
assembled into a data word, which is then loaded in parallel
into one word of the internal configuration memory array:
The configuration loading process is complete when the
current length count equals the loaded length count and the
required configuration program data frames have been written. Internal user flip-flops are held Reset during configuration.
Two user-programmable pins are defined in the' unconfigured Field Programmable Gate Array. High During Configuration (HDC) and Low During Configuration (LDC) as well
as DONE/PROG may be used as external control signals
during configuration. In Master mode configurations it is
convenient to use LDC as an active-Low EPROM Chip
Enable. After the last configuration data bit is loaded and
the length. count compares, .the user 110 pins become
active. Options' in the MakeBits program allow . timing
choices of one clock earlier or later for the timing of the end
of the internal logic RESET and the assertion of the DONE
signal. The open-drain DONE/PROG output can be ANDtied with multiple devices and used as an active-High
READY, an active-Low PROM enable or a RESET to other
portions of the system. The state diagram of Figure 20 illustrates the configuration process.

Configuration Modes
Master Mode
In Master mode, the FPGA automatically loads configuration data from an external memory device. There are three
Master modes that use the internal timing source to supply
the configuration clock (CCLK) to time the incoming d.ata.
Master Serial mode uses serial configuration data supplied
to Data-in (DIN) frome synchronous serial source such as
the Xilinx Serial Configuration PROM shown in Figure 23.
Master Parallel Low and High modes automatically use
parallel data supplied to the DO-07 pins in response tothe
i6-bit address generated by the FPGA. Figure 25 shows
an example of the parallel Master mode connections
required. The HEX starting address is 0000 and increments
for Master Low mode and it is FFFF and decrements for

June 1, 1996 (Version 2.0)

Master High mode. These two modes provide address
compatibility with microprocessors which begin execution
from opposite ends of memory.

Peripheral Mode
Peripheral mode provides a simplified interface through
which the device may be loaded byte-wide, asa processor
peripheral. Figure 27 shows the peripheral mode connections. Processor write cycles are decoded from the common assertion of the active low Write Strobe (WS), and two
active low and one active high Chip Selects (CSO, CS1,
CS2). The FPGA generates a configuration clock from the
internal timing generator and serializes the parallel input
data for internal framing or for succeeding slaves on Data
Out (DOUT). A output High on READY/BUSY pin indicates
the completion of loading for each byte when the input register is ready for a new byte. As with Master modes, Peripheral mode may also be used as a lead device for a daisychain of slave devices.

Slave Serial Mode
Slave Serial mode provides a simple interface for loading
the Field Programmable Gate Array configuration as shown
in Figure 29. Serial data is supplied in conjunction with a
synchronizing input clock. Most Slave mode applications
are in daisy-chain configurations in which the data input is
driven from the previous FPGA's data out, while the clock is
supplied by a lead device in· Master. or Peripheral mode.
Data may also be supplied by a processor or other special
circuits.

Daisy Chain
The XACTstep development system is used to create a
composite configuration for selected FPGAs including: a
preamble, a length count for the total bitstream, multiple
concatenated data programs and a postamble plus an
additional fill bit per device in the serial chain. After loading
and passing-on the preamble and length count to a possible daisy-chain, ,a Jead device will load its configuration
data frames while providing a High OOUT to possible
down-stream devices as shown in Figure 25. Loading continues while the lead device has received its configuration
program and the current length count has not reached the
full value. The additional data is passed through the lead
device and appears on the Data Out (DOUT) pin in serial
form. The lead device also generates the Configuration
Clock (CCLK) to synchronize. the serial' output data and
data in of down-stream FPGAs. Data is read in onDIN of
slave devices by the positive edge of CCLK and shifted out
the OOUT on the negative edge of CCLK. A parallel Master
mode device uses its internal timing generator to produce
an internal CCLK 018 times its EPROM address rate, while
a Peripheral mode device produces a burst of 8 CCLKs for
each chip select and write-strobecycle ..The internal timing
generator continues to operate for general timing and synchronization of inputs in alf modes.

4-307

I

XC3000 Series Field Programmable Gate Arrays

Special Configuration Functions
The configuration data includes control over several special
functions in addition to the normal user logic functions and
interconnect.
•
•
•
•
•
•

Input thresholds
Readback disable
DONE pull-up resistor
DONE timing
RESET timing
Oscillator frequency divided by two

Each of these functions is controlled by configuration data
bits which are selected as part of the normal XACTstep
development system bitstream generation process.

Input Thresholds
Prior to the completion of configuration all FPGA input
thresholds are TTL compatible. Upon completion of configuration, the input thresholds become either TTL or CMOS
compatible as programmed. The use of the TTL threshold
option requires some additional supply current for threshold
shifting. The exception is the threshold of the PWRDWN
input and direct clocks which always have a CMOS input.
Prior to the completion of configuration the user 1/0 pins
each have a high impedance pull-up. The configuration program can be used to enable the lOB pull-up resistors in the
Operational mode to act either as an input load or to avoid
a floating input on an otherwise unused pin.

Readback
The contents of a Field Programmable Gate Array may be
read back if it has been programmed with a bitstream in
which the Readback option has been enabled. Readback
may be used for verification of configuration and as a
method of determining the state of internal logic nodes during debugging. There are three options in generating the
configuration bitstream.
•
•
•

"Never" inhibits the Readback capability.
"One-time;' inhibits Readback after one Readback has
been executed to verify the configuration.
"On-command" allows unrestricted use of Readback.

Readback is accomplished without the use of any of the
user 1/0 pins; only MO, M1 and CCLK are used. The initiation of Readback is produces by a Low to High transition of
the MO/RTRIG(Read Trigger) pin. The CCLK input must
then be driven by external logic to read back the configuration data. The first three Low-to-High CCLK transitions
clock out dummy data. The subsequent Low-to-High CCLK
transitions shift the data frame information out on the M11
RDATA (Read Data) pin. Note that the logic polarity is
always inverted, a zero in configuration becomes a one in
Readback, and vice versa. Note also that each Readback
frame has one Start bit (read back as a one) but, unlike in
configuration, each Readback frame has only one Stop bit
(read back as a zero). The third leading dummy bit men-

4-308

tioned above can be considered the Start bit of the first
frame. All data frames must be read back to complete the
process and return the Mode Select and CCLK pins to their
normal functions.
Readback data includes the current state of each CLB flipflop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the XACTstep development system In-Circuit Verifier to
provide visibility into the internal operation of the logic while
the system is operating. To readback a uniform time-sample of all storage elements, it may be necessary to inhibit
the system clock.

Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered for two
cycles of the FPGA internal timing generator. When reprogram begins, the user-programmable 1/0 output buffers are
disabled and high-impedance pull-ups are provided for the
package pins. The device returns to the Clear state and
clears the configuration memory befor,e it indicates 'initialized'. Since this Clear operation uses chip-individual internal timing, the master might complete the Clear operation
and then start configuration before the slave has completed
the Clear operation. To avoid this problem, the slave INIT
pins must be AND-wired and used to force a RESET on the
master (see Figure 25), Reprogram control is often implemented using an external open-collector driver which pulls
DONE/PROG Low. Once a stable request is recognized,
the DONE/PROG pin is held Low until the new configuration has been completed. Even if the re-program request is
externally held Low beyond the configuration period, the
FPGA will. begin operation upon completion of configuration.

DONE Pull-up
DONE/PROG is an open-drain 1/0 pin that indicates the
FPGA is in the operational state. An optional internal pullup resistor can be enabled by the user of the XACT development system when MakeBits is executed. The DONEI
PROG pins of multiple FPGAs in a daisy-chain may be connected together to indicate all are DONE or to direct them
all to reprogram.

DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MakeBits program to occur either a CCLK
cycle before, or after, the outputs going active. See
Figure 22. This facilitates control of external functions such
as a PROM enable or holding a system in a wait state.

June 1, 1996 (Version 2.0)

~XILINX
RESET Timing
As with DONE timing, the timing of the release of the internal reset can be controlled by a selection in the MakeBits
program to occur either a CCLK cycle before, or after, the
outputs going active. See Figure 22. This reset keeps all
user programmable flip-flops and latches in a zero state
during configuration.

Crystal Oscillator Division
A selection in the MakeBits program allows the user to
incorporate a dedicated divide-by-two flip-flop between the
crystal oscillator and the alternate clock line. This guarantees a symmetrical clock signal. Although the frequency
stability of a crystal oscillator is very good, the symmetry of
its waveform can be affected by bias or feedback drive.

Bitstream Error Checking
Bitstream error checking protects against erroneous configuration.

Each Xilinx FPGA bitstream consists of a 40-bit preamble,
followed by a device-specific number of data frames. The
number of bits per frame is also device-specific; however,
each frame ends with three stop bits (111) followed by a
start bit for the next frame (0).
All devices in all XC3000 families start reading in a new
frame when they find the first 0 after the end of the previous
frame. XC3000 device does not check for the correct stop
bits, but XC3000AlXC3100AlXC3000L and XC3100L
devices check that the last three bits of any frame are actually 111.
Under normal circumstances, all these FPGAs behave the
same way; however, if the bitstream is corrupted, an
XC3000 device will always start a new frame as soon as it
finds the first 0 after the end of the previous frame, even if
the data is completely wrong or out-of-sync. Given sufficient zeros in the data stream, the device will also go Done,

June 1, 1996 (Version 2.0)

but with incorrect configuration and the possibility of internal contention.
An XC3000AlXC3100AlXC3000UXC3100L device starts
any new frame only if the three preceding bits are all ones.
If this check fails, it pulls INIT Low and stops the internal
configuration, although the Master CCLK keeps running.
The user must then start a new configuration by applying a
>6 IlS Low level on RESET.
This simple check does not protect against random bit
errors, but it offers almost 100 percent protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, or PC-board level defects, such as broken lines or solder-bridges.

Reset Spike Protection
A separate modification slows down the RESET input
before configuration by using a two-stage shift register
driven from the internal clock. It tolerates submicrosecond
High spikes on RESET before configuration. The XC3000
master can be connected like an XC4000 master, but with
its RESET input used instead of INIT. (On XC3000, INIT is
output only).

Soft Start-up
After configuration, the outputs of all FPGAs in a daisychain become active simultaneously, as a result of the
same CCLK edge. In the original XC3000/3100 devices,
each output becomes active in either fast or slew-rate limited mode, depending on the way it is configured. This can
lead to large ground-bounce signals. In XC3000Al
XC3000UXC31 000AIXC31 OOL devices,
all outputs
become active first in slew-rate limited mode, reducing the
ground bounce. After this soft start-up, each individual output slew rate is again controlled by the respective configuration bit.

4-309

I

XC3000 Series Field Programmable Gate Arrays

Configuration Timing
This section describes the configuration modes in detail.

Master Serial Mode
In Master Serial mode, the CCLK output of the lead FPGA
drives a Xilinx Serial PROM that feeds the DIN input. Each
rising edge of the CCLK output increments the Serial
PROM internal address counter. This puts the next data bit
on the SPROM data output, connected to the DIN pin. The
lead FPGA accepts this data on the subsequent rising
CCLKedge.
The lead FPGA then presents the preamble data (and all
data that overflows the lead device) on its DOUT pin. There
is an internal delay of 1.5 CCLK periods, which means that

• IF AEADBACK IS
ACTIVATED, A

~

5-kn RESISTOR IS

REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kQ M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL·UP,
BUT IT ALLOWS M2 TO
BE USER 110.

L
GENERALPURPOSE
USER I/O
PINS

-

DOUT

-

HDC

L.....

TO DIN OF OPTIONAL
DAISY·CHAINED LeAs WITH

-

TO CCLK OF OPTIONAL
DAISY-CHAINED LeAs WITH
DIFFERENT CONFIGURATIONS

DIFFERENT CONFIGURATIONS

LDC

--<

INIT

-

PWRDWN

M2

--<

-

Ml

The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O. but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.

T

I I
MO

DOUT changes on the falling CCLK edge, and the next
device in the daisy-chain accepts data on the subsequent
rising CCLK edge.

···
··

OTHER
1/0 PINS

~ ~~A~~L~Cc;,: ~i;~~~~~TlCAL
CONFIGURATIONS

XC3000
FPGA
DEVICE

,.....- TO DIN OF OPTIONAL
SLAVE LeAs WITH IDENTICAL
CONFIGURATIONS

+5V

RESET

---c

II

RESET
DIN

GCLK

CLK

r-------------l

VpP

VCC
DATA

---1

SCP

Dip

CE

INIT

DE/RESET

CEO

XC17xx

(LOW RESETS THE XC17xx ADDRESS POINTER)

I

DATA

I
'-----I elK

J CE
-I

CASCADED
SERIAL
MEMORY

OElRESeT

III

IL _______________

JI

X5989

Figure 23: Master Serial Mode Circuit Diagram

4-310

June 1, 1996 (Version 2.0)

~XIUNX
eeLK
(Output)

o
Serial Data In

Serial DOUT

TCKDS

n+1

n-3

n-2

(Output) _ _ _ _ _- - - . J ' - -_ _ _ _ _ _ _J

n+2

n-1

\. _ _ _ _ _ _ _- J ' - _ _ _ _ _ _ _. J
X3223

CCLK
Notes:

Description
Data In setup
Data In hold

Symbol
1

ITDSCK

2

IC KDS

Min

60
0

Max

Units
ns
ns

1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vee has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require >6-~s High level on RESET, followed by a >6-~s Low level on RESET and DIP after
VCC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.
3. Master-serial-mode timing is based on slave-mode testing.

Figure 24: Master Serial Mode Programming Switching Characteristics

June 1, 1996 (Version 2.0)

4-311

I

XC3000 Series Field Programmable Gate Arrays

Master Parallel Mode
In Master Parallel mode, the lead FPGA directly addresses
an industry-standard byte-wide EPROM and accepts eight
data bits right before incrementing (or decrementing) the
address outputs.
The eight data bits are serialized in the lead FPGA, which
then presents the preamble data (and all data that overflows the lead device) on the DOUT pin. There is an internal

• If Readback is
Activated, a
5-kn Resistor is
Required in
Series With M1

l

+5 V

delay of 1.5 CCLK periods, after the rising CCLK edge that
aCCepts a byte of data, and also changes the EPROM
address,until the falling CCLK edge that makes the LSB
(DO) of this byte appear at DOUT. This means that DOUT
changes on the falling CCLK edge, and the next device in
the daisy chain accepts data on the subsequent rising
CCLKedge.

+5V

+5V
MO M1PWRDWN

5k!l

CCLK

CCLK

5 kQ

FPGA
Slave #1

M2

RCLK

GeneralPurpose
User 1/0
Pins
Other
I/O Pins

A15

HDC

A14

A14

LDC

A13

A13
A12 EPROM

A12

Other {
1/0 Pins

DOUT

DIN

FPGA
Slave #n

M2

A15

5 kQ

CCLK

DOUT

DOUTr------------------------1 DIN

HDC

MO M1PWRDWN

M2
HDC

GeneralPurpose
User 110
Pins

LDC

Olher{

GeneralPurpose
User 1/0
Pins

110 Pins

All

All

Al0

A9

Al0
A9

DIP

DIP

D7

AS

AS

RESET

Reset

D6

A7

A7

D5

A6

A6

D4

A5

A5

Note: XC2000 Devices Do Not

D3

A4

A4

D2

A3

A3

Dl

A2

A2

Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LeA CCLK
Variations in Clear State Time.

DO

Al

Al

Dl

AO

AO

DO

FPGA
Master

INIT

INIT

Have INIT to Hold Off a Master

DIP
RESET

~--+-----~------------

Reprogram

+5V

__..,...,'--------'

Open
Collector

5 kQ Each

X5990

Figure 25: Master Parallel Mode Circuit Diagram

4-312

June 1, 1996 (Version 2.0)

~XILINX

x

AO-A15
(output)

_________
A_dd_r_es_s_IO_r_B_Yt_e_n_ _ _ _ _ _ _

-

Address lor Byte n + 1

l-CDTRAC

00-07

RCLK
(output)

/

1:======~'r7-CC-L-K:S-=--=--=--=--=--=--=--=--=-~+_---

CCLK
(output)

OOUT
(output)

06

07

Byten-1

RCLK

Notes:

Description
To address valid
To data setup
To data hold
RCLK High
RCLK Low

1
2
3

Symbol
T RAC
T ORC
T RCO
T RCH
T RCL

X5380

Min
0
60
0
600
4.0

Max
200

Units
ns
ns
ns
ns
I1s

1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require a >6-l1s High level on RESET, followed by a >6-l1s Low level on RESET and DIP after
Vee has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
High.

This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.

Figure 26: Master Parallel Mode Programming Switching Characteristics

June 1, 1996 (Version 2.0)

4-313

I

XC3000 Series Field Programmable Gate Arrays

Peripheral Mode
Peripheral mode uses the trailing edge of the logic AND
condition of the CSO, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead
FPGA, this data is loaded into a double-buffered UART-like
parallel-to-serial converter and is serially shifted into the
internal logic. The lead FPGA presents the preamble data
(and all data that overflows the lead device) on the DOUT
pin.

when the byte-wide input buffer has transferred its information into the shift register, and the buffer is ready to receive
new data. The length of the BUSY signal depends on the
activity in the UART. If the shift register had been empty
when the new byte was received, the BUSY signal lasts for
only two CCLK periods. If the shift register was still full
when the new byte was received, the BUSY signal can be
as long as nine CCLK periods.

The Ready/Busy output from the lead device acts as a
handshake signal to the microprocessor. RDY/BUSY goes
Low when a byte has been received, and goes High again

Note that after the last byte has been entered, only seven of
its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-Iast bit) of the last byte entered.

CON TROL
SIG NALS

ADDRESS
BUS

8

MO
DO-7

"-"-+5

v

~

+5 V

l+l

DATA
BUS

CCLK

DOUT
ADDRESS
DECODE
LOGIC

P-----<:

5

M1 PWR
DWN

DO-7

r--

rHDC rM2

CSO

FPGA

LDC

P-

CS1
CS2
WS

OTHER

~
V

-

f---+-

OPTIONAL
DAISY-CHAINED
FPGAs WITH DIFFERENT
CONFIGURATIONS

GENERA LPURPOS E
USER I/O
PINS

r-

~OPINS

RDY/BUSY

REPROGRAM

{

• IF READBACK IS
ACTIVATED, A
5-kQ RESISTOR IS
REQUIRED IN SERIES
WITHM1

r--

INIT
D/P
RESET
X5991

Figure 27: Peripheral Mode Circuit Diagram

4-314

June 1, 1996 (Version 2.0)

~XIUNX
WRITE TO FPGA

WS,CSO,CSl

CS2

00-07

CCLK

._.'

,,

,

,

'.......'

,,

'00 .. _.'
i

RDY/BUSY

:

......................... '

..'
I'

OOUT

"

.

( »

!

,"

,

,. ,

...

• i

..

I

«'

j(5992

WRITE

Description
Effective Write time required
(Assertion of CSO, CS1, CS2, WS)
DIN Setup time required
DIN Hold time required
ROY/BUSY delay after end of WS

1

Symbol
TeA

Min
100

2

Toe
Teo

60
0

3
'4

60

TWTRB

Units
ns
ns
ns
ns

,

,d

ROY

Max

Earliest next WS after end of BUSY

5

TRBWT

0

BUSY Low time generated

6

TBUSV

2.5

ns
>

9

CCu<
periods

Notes: 1. At poweRu~ Vcc must rise from 2.0 V to Vce min in less than 25 ms. If this is not possible, configuration can be delayed by
holding E ET Low until Vee has reached 4.0 V (2.5 V for the XC3000L).A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require a >6-~s High level on RtSET, followed by a >6-~s Low level on RESET and DIp after
Vee has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and the
phase of the internal timing generator for CCLK.
4. CCLK and DOUT liming is tested in slave mode.
5. TBUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest TBUSY
occurs when a byte is loaded into an empty parallel-to-serial converter. The longest TSUSY occurs when a new word is
loaded into the input register before the second-level buffer has started shifting out data.

Note: This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will
go active within 60 nsafter the end ofWS. BUSY will stay active for several microseconds. WS may be asserted immediately
.
after the end of BUSY.
Figure 28: Peripheral Mode Programming Switching Characteristics

June 1; 1996 (Version 2;0)

4-315

XC3000 Series Field Programmable Gate Arrays

Slave Serial Mode
In Slave Serial mode, an external signal drives the CCLK
input(s) of the FPGA(s). The serial configuration bitstream
must be available at the DIN input of the lead FPGA a short
set-up time before each rising CCLK edge. The lead device
then presents the preamble data (and all data that over-

flows the lead device) on its DOUT pi!). There is an internal
delay of 0.5 CCLK periods, which means that DOUT
changes on the falling CCLK edge, and the next device in
the. daisy-chain accepts data on the subsequent rising
CCLKedge.

If Readback Is

+5V

I
MO

M1

Activated, a
5-kn Resistor Is
Required in

1

Serles with M1

PWROWN

Micro

5kn

Computer

,---STRB

CCLK

OO
01

VO

02

Port

M2

DDUT

OIN

-

03

-

D4

-

05

-

. . HOC
LOC

--< RESET

c...-

--

Optional
Daisy-Chained
LCAswith
Oifferent

Configurations

General·
Purpose

User IIo
Pins

+5V
FPGA

-{

IIOPins

06
07
'---

r---

011'
INIT
RESET

X5993

Figure 29: Slave Serial Mode Circuit Diagram

4-316

June· 1, 1996 (Version 2.0)

~XILINX
DIN

Bit n + 1

---}-----

CCLK

DOUT
(Output) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _B_it_n_-_1_ _ _ _ _ _ _ _ _ _ _--'

Bit n
X5379

Description

CCLK

Notes:

Symbol

To DOUT

3

TCCO

DIN setup
DIN hold
High time
Low time (Note 1)
Frequency

1
2

T DCC

4
5

TCCD
TCCH
TCCL
Fcc

Min

60
0
0.05
0.05

Max
100

Units
ns

5.0
10

ns
ns
ns
I1s
MHz

1. The max limit of CCLK Low time is caused by dynamic circuitry inside the FPGA.
2. Configuration must be delayed until the INIT of all FPGAs is High.
3. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until VCC has reached 4.0 V (2.5 V for the XC3000L). A very long Vee rise time of >100 ms, or a nonmonotonically rising Vee may require a >6-l1s High level on RESET, followed by a >6-l1s Low level on RESET and Dip after
Vee has reached 4.0 V (2.5 V for the XC3000L).

Figure 30: Slave Serial Mode Programming Switching Characteristics

June 1, 1996 (Version 2.0)

4-317

I

XC3000 Series Field Programmable Gate Arrays

Program Readback Switching Characteristics

DONE/PROG
(OUTPUT)

------~~--------------------------------------1
------\~---------------

J

+-CDTRTH

RTRIG (MO)

®TRTCC

CCLK(1)

....__
M1Input!
RDATA Output

HI-Z

VALID
READBACK OUTPUT

VALID
READBACK OUTPUT
X6116

Description

Symbol

RTRIG

RTRIG High

1

CCLK

RTRIG setup
RDATA delay
High time
Low time

2
3
4
5

Notes:

4-318

1.
2.
3.
4.

TRTH
T RTCC
TCCRD
TCCHR
TCClR

Min

Max

100

ns
ns

5

I-lS
I-ls

200
0.5
0.5

Units
ns

250

During Readback, CCLK frequency may not exceed 1 MHz.
RETRIG (MO positive transition) shall not be done until after one clock following active 1/0 pins.
Readback should not be initiated until configuration is complete.
TCCLR is 5 I-ls min to 15 I-ls max for XC3000L.

June 1, 1996 (Version 2.0)

~XILINX
General XC3000 Series Switching Characteristics

f~-------,>r/'r--)-----,i-(4)TMRW)~_ _

RESET
MOiM1iM2 _ _ _

~ri),,,~ f_0_

3_ T
_R_M_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

r0TPGW~
DONEIPROG

INIT
(Output)

-.1'-J-0TPG'.
User State

~'-._ _ _ _ _ _ _e_le-'a~\/'r:-ta-te---------.J/

Configuration State

I

PWRDWN

1- Note 3 --+j

Vee (Valid) ----------------------------~\

J~,,.----

._--------.

~

Description
RESET (2)

2
3

RESET Width (Low) req, for Abort

4
5

DONEIPROG

Width (Low) required for Re-config.
INIT response after DIP is pulled Low

PWRDWN (3)

Power Down Vee

Notes:

Symbol

MO, Ml, M2 setup time required
MO, M1, M2 hold time required

6

TMR
TRM
T MRW
T pGW
T pGI
V eePD

Min

/

VCCPD
X5387

Max

Units

1

4.5
6
6

7
2.3

Ils
Ils
Ils

..

1

Ils
IlS
V

1. At power-up, Vee must rise from 2.0 V to Vee min in less than 25 ms. If this is not possible, configuration can be delayed by
holding RESET Low until Vcc has reached 4.0 V (2.5 V for XC3000L). A very long Vcc rise time of> 100 ms, or a nonmonotonically rising Vee may require a >1-lls High level on RESET, followed by a >6-lls Low level on RESET and Dip after
Vcc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (MO, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while Vee >4.0 V(2.5 V for XC3000L).

June 1, 1996 (Version 2:0)

4-319

XC3000 Series Field Programmable Gate Arrays

Device Performance

logic block is a function of supply voltage and temperature.
See Figure 32.

The XC3000 families of FPGAs can achieve very high performance. This is the result of
•

•

•

Interconnect performance depends on the routing
resources used to implement the signal path. Direct interconnects to the neighboring CLB provide an extremely fast
path. Local interconnects go through switch matrices
(magic boxes) and suffer an RC delay, equal to the resistance of the pass transistor multiplied by the capacitance of
the driven metal line. Longlines carry the signal across the
length or breadth of the chip with only one. access delay.
Generous on-chip signal buffering makes performance relatively insensitive to signal fan-out; increasing fan-out from
1 to 8 changes the CLB delay by only 10%. Clocks can be
distributed with two low-skew clock distribution networks.

A sub-micron manufacturing process, developed and
continuously being enhanced for the production of
state-of-the-art CMOS SRAMs.
Careful optimization of transistor geometries, circuit
design, and lay-out, based on years of experience with
the XC3000 family.
A look-up table based, coarse-grained architecture that
can collapse multiple-layer combinatorial logic into a
single function generator. OneCLB can implement up
to four layers of conventional logic in as little as 1.5 ns.

Actual system performance is determined by the timing of
critical paths, including the delay through the combinatorial
and sequential logic elements within CLBs and lOBs, plus
the delay in the interconnect routing. The AC-timing specifications state the worst-case timing parameters for the various logic resources available in the XC3000-families
architecture. Figure 31 shows a variety of elements
involved in determining system performance.

The tools in the XACTstep Development System used to
place and route a design in an XC3000 FPGA automatically calculate the actual maximum worst-case delays
along each signal path. This timing information can be
back-annotated to the design's nellist for use in timing simulation or examined with X-Delay, a static timing analyzer.
Actual system performance is applications dependent. The
maximum clock rate that can be used in a system is determined by the critical path delays within that system. These
delays are combinations of incremental logic and routing
delays, and vary from design to design. In a synchronous
system, the maximum clock rate depends on the number of
combinatorial logic layers between re-synchronizing flipflops. Figure 33 shows the achievable clock rate as a function of the number of CLB layers.

Logic block performance is expressed as the propagation
time from the interconnect point at the input to the block to
the output of the block in the interconnect area. Since combinatorial logic is implemented with a memory lookup table
within a CLB, the combinatorial delay through the CLB,
called T ILO, is always the same, regardless of the function
being implemented. For the combinatorial logic function
driving the data input of the storage element, the critical
timing is data set-up relative to the clock edge provided to
the flip-flop element. The delay from the clock source to the
output of the logic block is critical in the timing signals produced by storage elements. Loading of a logic-block output
is limited only by the resulting propagation delay of the
larger interconnect· network. Speed performance of the
Clock to Output

Combinatorial

Setup

I-TcKO-I-TILo-I+·---TICK---....·1
CLB

CLB

Logic

------i>

1....'---TOp---·1
CLB

I

I

Logic

lOB

l

J

(K)

PAD

-I>
(K)

CLOC K

I

lOB

I-TcKo-1

-t>--

PAD

I - TpID

.1

I·

TOKPO

·1
X3178

Figure 31: Primary Block Speed Factors. Actual timing is a function of various block fact~rs co~bine~ with routing.
factors. Overall performance can be evaluated with the XDelay timing calculator or by an opllonal Simulation.

4-320

June 1,1996 (Version 2.0)

~:XILINX
SPECIFIED WORST-CASE VALUES

~
...
:-( 14.,.'(l."

1.00

\\..I"I":t'.' •

\II"~Y'.' •
-- ........

..

0.80

..
.. ..

5
w

o

o

~ 0.60
::i

~
~

.. ' .. '
.. ' .. '

..

'

'

..

'

'

'

'

TYPICAL COMMERCIAL

(+ 5.0 V, 25°C)

•
•

TYPICAL MILITARY

0.40

MIN COMMERCIAL

_~~

MINC

0.20

..... - ......

~ ... -----------

-55

-40

- - -

__

:.~; ~

------ --------

.... - ..... -

ll'tt"..MJIJ1J'BY i 4•5•V1 •• '

--~ •• - - - - - .

:

5V)'
MIN MILI'IA.!IY 5_ - - ' - ' -

1

-_ ............ ----

I

-20

25

40

70

80

100

125

TEMPERATURE (0C)

X6094

Figure 32: Relative Delay as a Function of Temperature, Supply Voltage and Processing Variations

Power
Power Distribution

300

~

250

;;'200

:s
()

150

E

~ 100

If)

XC3100..,-~3_------

50
0L-X_C_30_oo~A~-~~____~____~____~_L_ _~~

CLB Levels:
Gate Levels:

4 CLBs

(4-16)

_ 3 CLBs
(3-12)

2CLBs
(2-8)

lCLB
(1-4)

Toggle
Rate
X7065

Figure 33: Clock Rate as a Function of Logic
Complexity (Number of Combinational Levels between
Flip-Flops)

June 1,1996 (Version 2,0)

Power for the FPGA is distribl.Jted through a grid to achieve
high noise immunity and isolation between logic and 1/0.
Inside the FPGA, a dedicated Vee and ground ring surrounding the logic array provides powertothe 1/0 drivers_
An independent matrix of Vee and groundlinessupplies the
interior logic of the device. This power distribution grid provides a stable supply and ground for all internal logic, providing the exterr)alpackage power pins are all COnnected
and appropriately decoupled.Jypicaily a 0.1-I-lF capacitor
connected near the Vee and ground pins will provide adequate decoupling.
Output buffers capable of driving the specified 4- or 8-mA
loads under worst-case conditions may be capable of driving as much as 25 to 30 times that current in a best case.
Noise can be reduced by minimizing external load capacitance and reducing simultaneous output transitions in the
same direction. It may also be beneficial to locate heavily
loaded output buffers near the ground pads. The I/O Block
output buffers have a slew-limited mode which should be
used where output rise and fall times are not speed critical.
Slew-limited outputs maintain their dc drive capability, but
generate less external reflections and internal noise.

4-321

XC3000 Series Field Programmable Gate Arrays

Dynamic Power Consumption
One CLB driving three local interconnects
One global clock buffer and clock line
One device output with a 50 pF load

XC3042A
0.25
2.25
1.25

XC3042L
0.17
1.40
1.25

XC3142A
0.25
1.70
1.25

mWperMHz
mW per MHz
mW per MHz

Power Consumption
The Field Programmable Gate Array exhibits the low power
consumption characteristic of CMOS ICs. For any design,
the configuration option of TTL chip input threshold
requires power for the threshold reference. The power
required by the static memory cells that hold the configuration data is very low and may be maintained in a powerdown mode.
Typically, most of power dissipation is produced by external
capacitive loads on the output buffers. This load and frequency dependent power is 25 J.lW/pF/MHz per output.
Another component of 110 power is the external dc loading
on all output pins.
Internal power dissipation is a function of the number and
size of the nodes, and the frequency at which they change.
In an FPGA, the fraction of nodes changing on a given
clock is typically low (10-20%). For example, in a long
binary counter, the total activity of all counter flip-flops is
equivalent to that of only two CLB outputs toggling at the
clock frequency. Typical global clock-buffer power is
between 2.0 mW/MHz for the XC3020A and 3.5 mW/MHz
for the XC3090A. The internal capacitive load is more a
function of interconnect than fan-out. With a typical load of
three general interconnect segments, each CLB output
requires about 0.25 mW per MHz of its output frequency.
Because the control storage of the FPGA is CMOS static
memory, its cells require a very low standby current for data
retention. In some systems, this low data retention current
characteristic can be used as a method of preserving configurations in the event of a primary power loss. The FPGA

4-322

has built in powerdown logic which, when activated, will disable normal operation of the device and retain only the configuration data. All internal operation is suspended and
output buffers are placed in their high-impedance state with
no pull-ups. Different from the XC3000 family which can be
powered down to a current consumption of a few microamps, the XC31 OOA draws 5 mA, even in power-down. This
makes power-down operation less meaningful. In contrast,
leePD for the XC3000L is only 10 J.lA.
To force the FPGA into the Powerdown state, the user must
pull the PWRDWN pin Low and continue to supply a retention voltage to the Vee pins. When normal power is
restored, Vee is elevated to its normal operating voltage
and PWRDWN is returned to a High. The FPGA resumes
operation with the same internal sequence that occurs at
the conclusion of configuration. Internal-I/O and logic-block
storage elements will be reset, the outputs will become
enabled and the DONE/PROG pin will be released.
When Vee is shut down or disconnected, some power
might unintentionally be supplied from an incoming signal
driving an 1/0 pin. The conventional electrostatic input protection is implemented with diodes to the supply and
ground. A positive voltage applied to an input (or output)
will cause the positive protection diode to conduct and drive
the Vee connection. This condition can produce invalid
power conditions and should be avoided. A large series
resistor might be used to limit the current or a bipolar buffer
may be used to isolate the input Signal.

June 1,1996 (Version 2.0)

~XIUNX
Pin Descriptions
Permanently Dedicated Pins

Once configuration is done, a High-to-Low transition of this
pin will cause an initialization of the FPGA and start a
reconfiguration.

Vee

MO/RTRIG

Two to eight (depending on package type) connections to
the positive V supply voltage. All must be connected.

As Mode 0, this input is sampled on power-on to determine
the power-on delay (214 cycles if MO is High, 2 16 cycles if MO
is Low). Before the start of configuration, this input is again
sampled together with M1, M2 to determine the configuration mode.to be used.

GND
Two to eight (depending on package type) connections to
ground. All must be connected.
PWRDWN
A Low on this CMOS-compatible input stops all internal
activity, but retains configuration. All flip-flops and latches
are reset, all outputs are 3-stated, and all inputs are interpreted as High, independent of their actual level. When
PWDWN returns High, the FPGA becomes operational with
DONE Low for two cycles of the internal 1-MHz clock.
Before and during configuration, PWRDWN must be High.
If not used, PWRDWN must be tied to Vee.
RESET
This is an active Low input which has three functions.
Prior to the start of configuration, a Low input will delay the
start of the configuration process. An internal circuit senses
the application of power and begins a minimal time-out
cycle. When the time-out and RESET are complete, the levels of the M lines are sampled and configuration begins.
If RESET is asserted during a configuration, the FPGA is
re-initialized and restarts theconfiguration at the termination of RESET.
If RESET is asserted after configuration is complete, it provides a global asynchronous RESET of all lOB and CLB
storage elements of the FPGA.

CCLK
During configuration, Configuration Clock is an output of an
FPGA in Master mode or Peripheral mode, but an input in
Slave mode. During Readback, CCLK is a clock input for
shifting configuration data out of the FPGA.
CCLK drives dynamic circuitry inside the FPGA. The Low
time may, therefore, not exceed a few microseconds. When
used as an input, CCLK must be "parked High". An internal
pull-up resistor maintains High when the pin is not being
driven.
DONEIPROG (DIP)
DONE is an open-drain output, configurable with or without
an internal pull-up resistor of 2 to 8 kn. At the completion of
configuration, the FPGA circuitry becomes active in a synchronous order; DONE is programmed to go active High
one cycle either before or after the outputs go active.

June 1, 1996 (Version 2.0)

A Low-to-High input transition, after configuration is complete, acts as a Read Trigger and initiates a Readback of
configuration and storage-element data clocked by CCLK.
By selecting the appropriate Readback option when generating the bitstream, this operation may be limited to a single
Readback, or be inhibited altogether.
M1/RDATA
As Mode 1, this input and MO, M2 are sampled before the
start of configuration to establish the configuration mode to
be used. If Readback is never used, M1 can be tied directly
to ground or Vee. If Readback is ever used, M1 must use a
5-kQ resistor to . ground or V~e, to accommodate the
RDATA output.
As an active-Low Read Data, after configuration is complete, this pin is the output of the Readback data.

User I/O Pins That Can Have Special
Functions
M2
During configuration, this input has a weak pull-up resistor.
Together with MO and M1, it is sampled before the start of
configuration to establish the configuration mode to be
used. After configuration, this pin is a user-programmable
I/O pin.

HOC
During configuration, this output is held at a High level to
indicate that configuration is not yet complete. After configuration, this pin is a user-programmable I/O pin.

During Configuration, this output is held at a Low level to
indicate that the configuration is not yet complete. After
configuration, this pin is a user-programmable I/O pin. LDC
is particularly useful in Master mode as a Low enable for an
EPROM, but it must then be programmed as a High after
configuration.

This is an active Low open-drain output with a weak pull-up
and is held Low during the power stabilization and internal
clearing of the configuration memory. It can be used to indicate status to a configuring microprocessor or, as a wired

4-323

XC3000 Series Field Programmable Gate Arrays

AND of several slave mode devices, a hold-off signal for a
master mode device. After configuration this pin becomes a
user-programmable 1/0 pin.

BClKIN
This is a direct CMOS level input to the alternate clock
buffer (Auxiliary Buffer) in the lower right corner.

XTl1
This user 1/0 pin can be used to operate as the output of an
amplifier driving an external crystal and bias circuitry.

XTl2
This user 1/0 pin can be used as the input of an amplifier
connected to an external crystal and bias circuitry. The 1/0
Block is left unconfigured. The oscillator configuration is
activated by routing a net from the oscillator buffer symbol
output and by the MakeBits program.

CSO, CS1, CS2, WS
These four inputs represent a set of signals, three active
Low and one active High, that are used to control configuration-data entry in the Peripheral mode. Simultaneous
assertion of all four inputs generates a Write to the internal
data buffer. The removal of any assertion clocks in the 00D7 data. In Master-Parallel mode, WS and CS2 are the AO
and A 1 outputs. After configuration, these pins are userprogrammable 1/0 pins.
ROY/BUSY

During Peripheral Parallel mode configuration this pin indicates when the chip is ready for another byte of data to be
written to it. After configuration is complete, this pin
becomes a user-programmed 1/0 pin:

RClK
During Master Parallel mode configuration, each change
on the AO-15 outputs is preceded by a rising edge on
RCLK, a redundant output signal. After configuration is
complete, this pin becomes a user-programmed 1/0 pin.

00-07
This set of eight pins represents the parallel configuration
byte for the parallel Master and Peripheral modes. After
configuration is complete, they are user-programmed 1/0
pins.

AO-A15
During Master Parallel mode, these 16 pins present an
address output for a configuration EPROM. After configuration, they are user"programmable 1/0 pins.

DIN
During Slave or Master Serial configuration, this pin is used
as a serial-data input. In the Master or Peripheral configuration, this is the Data 0 input. After configuration is complete, this pin becomes a user-programmed I/O pin.
OOUT

During configuration this pin is used to output serial-configuration data to the DIN pin of a daisy-chained slave. After
configuration is complete, this pin becomes a user-programmed 1/0 pin.

TClKIN
This is a direct CMOS-level input to the global clock buffer.
This pin can also be configured as a user programmable
1/0 pin. However, since TCLKIN is the preferred input to the
global clock net, and the global clock net should be used as
the primary clock source, this pin is usually the clock input
to the chip.

Unrestricted User 1/0 Pins
I/O
An 1/0 pin may be programmed by the user to be an Input
or an Output pin following configuration. All unrestricted 1/0
pins, plus the special pins mentioned on the following page,
have a weak pull-up resistor of 50 kO to 100 kO that
becomes active as soon as the device powers up, and
stays active until the end of configuration.

Note: Before and during configuration, all outputs that are not used for the configuration process are 3-stateri with a 50 kQ.
to 100 kQ. pull-up resistor.

4-324

June 1, 1996 (Version 2.0)

~XILINX
Pin Functions During Configuration
SLAVE
SERIAL
<1:1:1>

MASTERSERIAL
<0:0:0>

User

I

Notes:

-

Generic I/O pins are not shown.
For a detailed description of the configuration modes, see page 310 through page 319.
For pinout details, see page 327 through page 338.
Represents a 50-kQ to toO-kQ pull-up before and during configuration.
INIT is an open drain output during configuration.
Represents an input.
Pin assignment for the XC3064A1XC3090A and XC3195A differ from those shown.
Peripheral mode and master parallel mode are not supported in the PC44 package.
Pin assignments for the XC3195A PQ208 differ from those shown.
Pin assignments of PGA Footprint PlCC sockets and PGA packages are not indentical.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.

Note:

Before and during configuration, all outputs that are not used for the configuration process are 3-stated with a 50-kW to 10D-kW pull-up
resistor.

(I)

June 1, 1996 (Version 2.0)

XC3000 Series Field Programmable Gate Arrays

XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package types, with pin counts from 44 to 223.
Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology. Most package types are also offered with different
chips to accommodate design changes without the need for
PC board changes.

Note that there is no perfect match between the number of
bonding pads on the chip and the number of pins on a
package. In some cases, the chip has more pads than
there are pins on the package, as indicated by the information ("unused" pads) below the line in the following table.
The lOBs of the unconnected pads can still be used as
storage elements if the specified propagation delays and
set-up times are acceptable.
In other cases, the chip has fewer pads than there are
pins on the package; therefore, some package pins are
not connected (n.c.), as shown above the line in the following table.

Number of Unbounded or Unconnected Pins
Number of Package Pins
Device Pads

44

64

68

84

3020A

74

3030A

98

3042A

118

3064A

142

50 u

3090A

166

82 u

3195A

100

132

144

160

175

176

208

223

6u
54 u

34 u

30 u
14 n.c. 26 n.c.

198

10 u

2u

18 n.c.
6u

9 n.c
9 n.c.
32 u

114 u

10 n.c. 42 n.c.
10 n.c. 25 n.c.

n.C. ; Unconnected package pin
u ; Unbonded device pad

X7066

Number of Available 1/0 Pins
Number of Package Pins

MaxVO
XC3020AIXC3120A
XC3030AIXC3130A
XC3042AIXC3142A
XC3064A1XC3164A
XC3090AIXC3190A
XC3195A

64
80
96
120
144
176

44

64

68

84 100 120 132 144 156 160 164 175 176 191 196 208 223 240

34

54

58
58

64
74
74
70
70
70

64
80
82

96 96
110 110
120

120
138 144 144 144
138
144

144
176 176
X7067

4-326

June 1, 1996 (Version 2.0)

~XILINX
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Pin No.

XC3030A

Pin No.

XC3030A

1

GND

GND

2

1/0
1/0
1/0
1/0
1/0

23
24

3
4
5

25

1/0
1/0

26

XTL2(IN)-1/0

27

RESET
DONE-PGM

6
7

PWRDWN

8

TCLKIN-I/O

9
10
11

1/0
1/0
1/0

33

1/0
1/0
1/0

12

VCC

34

VCC

13

I/O

35

I/O

14

1/0
1/0

36

I/O

37

1/0

16
17

M1-RDATA

38

DIN-I/O

MO-RTRIG
M2-1/0

39
40

DOUT-I/O

18
19

HDC-I/O

41

1/0

20
21

LDC-I/O

42

I/O

1/0

43

22

INIT-I/O

44

1/0
1/0

15

28
29
30
31

I/O
XTL 1(OUT)-8CLK-I/O

32

I

CCLK

Peripheral mode and Master Parallel mode are not supported in the PC44 package

June 1, 1996 (Version 2.0)

4-327

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 64-Pin Plastic VQFP Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Pin No.

XC3030A

Pin No.

1
2

AO-WS-I/O
A1-CS2-1/0

33
34

3
4

A2-1/0

35

I/O

A3-1/0

36
37

LOC-I/O
I/O
I/O
INIT-I/O

4-328

5

A4-1/0

6
7

A14·1/0
A5-1/0

XC3030A
M2-1/0
HOC-I/O

I/O

8

GND

38
39
40

9

A13-1/0

41

GND

10

A6-1/0

42

I/O

11
12

A12-1/0
A7-1/0

43
44

I/O
I/O

13

A11-1/0

45

I/O

14

A8-1/0

15
16

A10-1/0

46
47

I/O
XTAL2(IN)-1/0

17

A9-1/0
PWRON

48
49

RESET
OONE-PG
XTAL 1(OUT)-BCLKIN-I/O

18

TCLKIN-I/O

19

I/O

50
51

20
21

I/O

52

06-1/0

I/O

22

I/O

53
54

05-1/0
CSO-I/O

23
24

I/O

55

04-1/0

VCC

56

25
26

I/O
I/O

57
58

VCC
03-1/0

27

I/O

59

28

I/O

60

01-1/0

29

I/O

61

ROY/BUSY -RCLK·I/O

30
31

I/O
M1-ROATA

62

~O-DIN-I/O

OOUT-I/O

32

MO-RTRIG

63
64

07-1/0

CS1-1/0
02-1/0

CCLK

June 1, 1996 (Version 2.0)

~XILINX
XC3000 Series 68-Pin PLCC, 84-Pin PLCC and PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
68 PLCC
XC3030A XC3020A

XC3020A, XC3030A,
XC3042A

84 PLCC

84PGA

68 PLCC
XC3030A
XC3020A

XC3020A, XC3030A, XC3042A

84
PLCC

84PGA

XC3020A

10

10

PWiml\I

12

B2

44

RESn

54

K10

44

11

11

TCLKIN-I/O

13

C2

45

OONE-PG

55

J10

45

12

-

I/O'

14

B1

46

07-1/0

56

K11

46

13

12

I/O

15

C1

47

XTL 1(OUTj-BCLKIN-I/O

57

J11

47

14

13

I/O

16

02

48

06-1/0

58

H10

48

-

-

I/O

17

01

-

I/O

59

H11

-

15

14

I/O

18

E3

49

05-1/0

60

F10

49

16

15

I/O

19

E2

50

~-I/O

61

G10

50

-

16

I/O

20

E1

51

04-1/0

62

G11

51

17

17

I/O

21

F2

-

I/O

63

G9

,.-

18

18

VCC

22

F3

52

VCC

64

F9

52

19

19

I/O

23

G3

53

03-1/0

65

F11

53

-

-

I/O

24

G1

54

CST-I/O

66

E11

54

20

20

I/O

25

G2

55

02-1/0

67

E10

55

-

21

I/O

26

F1

-

21

22

I/O

27

H1

22

-

-

I/O

28

H2

23

23

I/O

29

J1

24

24

I/O

30

25

25

M1-ROATA

26

26

MO-RTRIG

27

27

M2-1/0

33

K2

61

28

28

HOC-I/O

34

K3

62

I/O

68

E9

-

I/O'

69

011

-

56

01-1/0

70

010

56

57

ROY/BUSY-ReO<-I/O

71

C11

57

K1

58

OO-OIN-I/O

72

B11

58

31

J2

59

OOUT-I/O

73

C10

59

32

L1

60

CCLK

74

A11

60

AO-WS-I/O

75

B10

61

A1-CS2-1/0

76

B9

62

29

29

I/O

35

L2

63

A2-1/0

77

A10

63

30

30

LOC-I/O

36

L3

64

A3-1/0

78

A9

64

-

31

-

31

I/O

37

K4

79

B8

38

L4

-

I/O'

I/O'

I/O'

80

A8

-

I/O

39

J5

65

A15-1/0

81

B6

65
66

32

32

33

I/O

40

K5

66

A4-1/0

82

B7

33

-

I/O'

41

L5

67

A14-1/0

83

A7

67

34

34

Tiii1i:1/0

42

K6

68

A5-1/0

84

C7

68

35

35

GNO

43

J6

1

GNO

1

C6

1

36

36

I/O

44

J7

2

A13-1/0

2

AS

2

37

37

I/O

45

L7

3

A6-1/0

3

A5

3

38

38

I/O

46

K7

4

A12-1/0

4

B5

4

39

39

I/O

47

L6

5

A7-1/0

5

C5

5

-

40

I/O

48

L8

-

I/O'

6

A4

-

I/O

49

K8

-

I/O'

7

B4

40

I/O'

50

L9

6

A11-1/0

8

A3

6

41

I/O'

51

L10

7

AS-I/O

9

A2

7

41

42

42

I/O

52

K9

8

A10-1/0

10

B3

8

43

43

XTL2(1N)-1/0

53

L11

9

A9-1/0

11

A1

9

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for un bonded or unused lOBs.
Programmed outputs are default slew-rate limited.
This table describes the pinouts of three different chips in three different packages. The pin-description column lists 84 of the
118 pads on the XC3042A (and 84 of the 98 pads on the XC3030A) that are connected to the 84 package pins. Ten pads,
indicated by an asterisk, do not exist on the XC3020A, which has 74 pads: therefore the corresponding pins on the 84-pin
packages have no connections to an XC3020A. Six pads on the XC3020A and 16 pads on the XC3030A, indicated by a
dash (-) in the 68 PLCC column, have no connection to the 68 PLCC, but are connected to the 84-pinpackages.

June 1, 1996 (Version 2.0)

4-329

I

XC3000 Series Field Programmable Gate Arrays

XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PLCC Pin Number

XC3064A, XC3090A, XC3195A

PLCC Pin Number

XC3064A,XC3090A,XC3195A

12

PWRON

54

RESET

13

TCLKIN-I/O

55

OONE-PG

14

I/O

56

07-1/0

15

I/O

57

XTL 1(OUT)-BCLKIN-I/O

16

I/O

58

06-1/0

17

I/O

59

I/O

18

I/O

60

05-1/0

19

I/O

61

CSO-I/O

20

I/O

62

04-1/0

21

GNO'

63

I/O

22

VCC

64

VCC

23

I/O

65

GNO'

24

I/O

66

03-1/0'

25

I/O

67

CST-I/O'

26

I/O

68

02-1/0'

27

I/O

69

I/O

28

I/O

70

OH/O

29

I/O

71

RPY/BUSY-RCLK-I/O

30

I/O

72

OO-DIN-I/O

31

M1-ROATA

73

DOUT-I/O

32

MO-RTRIG

74

CCLK

33

M2-1/0

75

AO-ViS-I/O

34

HOC-I/O

76

A1-CS2-1/0

35

I/O

77

A2-1/0

36

LDC-I/O

78

A3-1/0

37

I/O

79

I/O

38

I/O

80

I/O

39

I/O

81

A15-1/0

40

I/O

82

A4-1/0

41

INIT/I/O'

83

A14-1/0

42

VCC'

84

A5-1/0

43

GNO

1

GNO

44

I/O

2

VCC'

45

I/O

3

A13-1/0'

46

I/O

4

A6-1/0'

47

I/O

5

A12-1/0'

48

I/O

6

A7-1/0'

49

I/O

7

I/O

50

I/O

8

A11-I/O

51
52 .

I/O

9

AS-I/O

I/O

10

A10-1/0

XTL2(IN)-1/0

11

A9-1/0

53

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
, In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020AlXC3030AlXC3042A.

4-330

June 1, 1996 (Version 2.0)

~XIUNX
XC3000 Series 100-Pin QFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin No.
TQFP
CQFP PQFP VQFP

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34

16
17

18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49

13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

XC3020A
XC3030A
XC3042A

GNO
A13-1/0
A6-1/0

A12-1/0
A7-1/0
1/0'
1/0'
A1H/O

AS-I/O
A10-1/0
A9-1/0

VCC'
GNO'
PWRON
TCLKIN-I/O
1/0"
1/0'
1/0'
1/0
1/0
1/0
1/0
1/0
1/0
1/0

VCC
1/0

I/O
1/0
1/0
1/0
1/0
1/0
1/0

Pin No.
TQFP
CQFP PQFP VQFP

35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68

50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83

47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70.
71
72
73
74
75
76
77

78
79
80

XC3020A
XC3030A
XC3042A

1/0'
1/0'

M1-RO
GNO'
MO-RT
VCC'
M2-1/0
HOC-I/O
I/O
LOC-I/O
1/0'

I/O'
1/0
1/0
1/0

INIT-I/O
GNO
1/0
1/0
1/0

I/O
I/O
1/0
1/0

I/O'
1/0'

XTL2-I/O
GNO'
RESET
VCC'
OONE-PG
07-1/0
BCLKIN-XTL 1-1/0
06-1/0

Pin No.
TQFP
CQFP PQFP VQFP

69
70
71
72
73
74
75
76
77

78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

84
81
85
82
86
83
87
84
88
85
89
86
90
87
91
88
92
89
93
90
94
91
95
92
96
93
97
94
98
95
99
96
100 . 97
1
98
2
99
100
3
4
1
2
5
6
3
7
4
8
5
9
6
10
7
11
8
12
9
13
10
14
11
15
12

XC3020A
XC3030A
XC3042A

1/0'
1/0'
1/0

05-1/0
CSO-I/O
04-110
1/0

VCC
03-1/0
CSH/O

02-1/0
1/0
1/0'
1/0'
OHIO

ROY/BUSY-RCLK-I/O
OO-DIN-I/O
OOUT-I/O
CCLK
VCC'
GNO'
AO-WS-I/O
A1-CS2-1/0
1/0"

A2-1/0
A3-1/0
1/0'
1/0'
A15-1/0
A4-1/0

A14-1/0
AS-I/O

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

* This table describes the pinouts of three different chips in three different packages. The pin-description column lists 100 of
the 118 pads on the XC3042A that are connected to the 100 package pins. Two pads, indicated by double asterisks, do not
exist on the XC3030A, which has 98 pads; therefore the corresponding pins have no connections. Twenty-six pads, indicated
by single or double asterisks, do not exist on the XC3020A, which has 74 pads; therefore, the corresponding pins have no
connections. (See table on page 326.)

June 1, 1996 (Version 2.0)

4-331

XC3000 Series .Fleld Programmable Gate Arrays '.

XC3000 Series 132·Pin Ceramic and· Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
PGA.
Pin'

Number
C4
A1
C3
82
83
A2
B4
C5
A3
A4
B5
C6
A5
B6
A6
B7
C7
C8
A7
B8
A8
A9
B9
C9
A10
B10
A11
C10
B11
A12
B12
A13
C12

XC3042A
XC3064A
.GNO
PWRON
I/O-TCLKIN
I/O
I/O
I/O·
I/O
I/b
I/O·
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GNO
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O·
I/O
I/O
I/O·
I/O
I/O·
I/O

PGA
Pin

Number
813
C11
A14
012
C13
B14
C14
E12
013
014
E13
F12
E14
F13
F14
G13
G14
G12
H12
H14
H13
J14
J13
K14
,J12
K13
L14
L13
K12
M14
N14
M13
L12

PGA
Pin

XC3042A
XC3064A
M1-RO
GNO
MO-RT
VCC
M2-1/0
HOC-I/O
I/O
I/O
I/O
0'5C'-1/0
I/O·
I/O
I/O
I/O
I/O
I/O
TNJT-I/O
VCC
GNO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O·
I/O
I/O
I/O
I/O
XTL2(IN)-1/0
GNO

.

XC3042A
XC3064A
RESET
VCC
OONE-PG
07-1/0
XTL H/O-BCLKIN

Number
P14
M11
N13
M12
P13
N12
I/O
I/O
P12
06-1/0
N11
M10
I/O
I/O·
P11
N10
I/O
P10
I/O
M9
05-1/0
N9
O'SO-I/O
I/O·
P9.
I/O·
P8
04-1/0
N8
P7
I/O
M8
VCC
M7
GNO
N7
03-1/0
CST~I/O
P6
I/O·
N6
I/O·
P5
02-110
M6
N5
I/O
P4
I/O
P3
I/O
M5
OHIO
ROY/BUSY-RCiJ(-1/0
N4
P2
tlO
N3
I/O
N2
OO"OIN-I/O

PGA
Pin

Number
M3
P1
M4
L3
M2
N1
M1
K3
L2
L1
K2
J3
K1
J2
J1
H1
H2
H3
G3
G2
G1
F1
F2
E1
F3
E2
01
02
E3
C1
B1
C2
.. 03"

XC3042A
XC3064A'·
OOUT-I/O
CCLK

vce
GND
AO-WS-I/O
A1-CS2-1/0
I/O
I/O
A2-1/0
A3-1/0
I/O
I/O
A15-1/0
)\4-1/0
I/O·
A14-1/0
A5-1/0
GNO
VCC
A13-1/0
A6-1/0
I/O·
A12-1/0
A7-1/0
<

I/O
I/O

A11-1/0
AS-I/O
I/O
I/O
A10-1/0
A9-1/0
... VeC

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or Linlised lOBs.
Programmed outputs 'are default slew-rate limited.
'

·Indicat~s unconnected package pins (14) fortheXC3042A.

4-332

June 1, 1996 (Version 2.0)

F.:XILINX
XC3000 Series 144-Pin PlasticTQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
XC3042A
XC3064A
XC3090A

Pin
Number

Pin
Number

XC3042A
XC3064A
XC3090A

Pin
Number

XC3042A
XC3064A
XC3090A

1

PWRDN

49

I/O

97

1/0

2

1/0-TClKIN

50

1/0'

98

I/O
1/0'

3

1/0'

51

I/O

99

4

1/0

52

1/0

100

1/0

5

1/0

53

1NTi-1/0

101

1/0'

6

1/0'

54

VCC

102

D1-I/0

7

I/O

55

GND

103

RDY/BUSY-RClK-I/O

8

1/0

56

1/0

104

1/0

9

1/0'

57

I/O

105

1/0

10

I/O

58

1/0

106

DO-DIN-I/O

11

1/0

59

1/0

107

DOUT-I/O

12

1/0

60

1/0

108

CClK

13

1/0

61

1/0

109

VCC

14

1/0

62

1/0

110

GND

15

1/0'

63

1/0'

111

AO-~/O

16

1/0

64

I/O'

112

Al-CS2-1/0
1/0

17

I/O

65

1/0

113

18

GND

66

1/0

114

1/0

19

VCC

67

1/0

115

A2-1/0

20

1/0

68

1/0

116

A3-1/0

21

1/0

69

XTL2(IN)-IIO

117

1/0

22

1/0

70

GND

118

1/0

23

1/0

71

RESET

119

A15-1/0

24

1/0

72

VCC

120

A4-1/0

25

1/0

73

DONE-PG

121

1/0'

26

1/0

74

D7-1/0

122

1/0'

27

I/O

75

XTll (OUn-BClKIN-I/O

123

A14-1/0

28

I/O'

76

I/O

124

A5-1/0

29

1/0

77

1/0

125

1/0 (XC3090 only)

GND

30

1/0

78

D6-1/0

126

31

1/0'

79

1/0

127

VCC

32

1/0'

80

1/0'

128

A13-1/0
A6-1/0

33

1/0

81

1/0

129

34

1/0'

82

1/0

130

1/0'

35

I/O

83

1/0'

131

1/0 (XC3090 only)

36

M1-RD

84

D5-1/0

132

1/0'

37

GND

85

<:;SO-I/O

133

A12-1/0

MO-RT

86

1/0'

134

A7-1/0

VCC

87

1/0'

135

1/0

40

M2-1/0

88

D4-1/0

136

1/0

41

HDC-I/O

89

1/0

137

All-I/O

42

1/0

90

VCC

138

A8-1/0

43

1/0

91

GND.

139

1/0

44

1/0

92

D3-1/0

140

1/0

45

lDC-I/O

93

CST-I/O

141

Al0-1/0

46

1/0'

94

1/0'

142

A9-1/0

47

1/0

95

1/0'

143

VCC

48

1/0

96

D2-1/0

144

GND

38
39

I

I

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level· for un bonded or unused lOBs.
Programmed outputs are default slew-rate limited.
* Indicates unconnected package pins (24) for the XC3042A.

June 1, 1996 (Version 2.0)

4-333

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 160-Pin PQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100Lfamilies have identical pinouts
PQFP Pin

Number

XC3064A, XC3090A,
XC3195A

PQFP Pin

Number

XC3064A, XC3090A,
XC3195A

PQFP Pin

Number

XC3064A, XC3090A,
XC3195A

PQFP Pin

Number

XC3064A, XC3090A,
XC3195A
CCLK

1

I/O'

41

GND

81

D7-1/0

121

2

I/O

42

MO-RTRIG

82

XTL 1-1/0-8CLKIN

122

VCC

3

I/O

43

VCC

83

I/O'

123

GND

4

I/O

44

M2-1/0

84

I/O

124

AO-WS-I/O

5

I/O

45

HDC-I/O

85

I/O

125

A1-CS2-1/0
I/O

6

I/O

46

I/O

86

D6-1/0

126

7

I/O

47

I/O

87

I/O

127

I/O

8

I/O

48

I/O

88

I/O

128

A2-1/0

9

I/O

49

[DC-I/O

89

I/O

129

A3-1/0

10

I/O

50

I/O'

90

I/O

130

I/O

11

I/O

51

I/O'

91

I/O

131

I/O

12

I/O

52

I/O

92

D5-1/0

132

A15-1/0

13

I/O

53

I/O

93

CSO-I/O

133

A4-1/0

14

I/O

54

I/O

94

I/O'

134

I/O

15

I/O

55

I/O

95

I/O'

135

I/O

16

I/O

56

I/O

96

I/O

136

A14-1/0

17

I/O

57

I/O

97

I/O

137

AS-I/O

18

I/O

58

I/O

98

D4-1/0

138

I/O'

19

GND

59

lliIli-l/o

99

I/O

139

GND

20

VCC

60

VCC

100

VCC

140

VCC

21

I/O'

61

GND

101

GND

141

A13-1/0

22

I/O

62

I/O

102

D3-1/0

142

AS-I/O

23

I/O

63

I/O

103

~-I/O

143

I/O'

24

I/O

64

I/O

104

I/O

144

I/O'

25

I/O

65

I/O

105

I/O

145

I/O

26

I/O

I/O

106

I/O'

146

I/O

27

I/O

66
; 67

I/O

107

I/O'

147

A12-1/0

28

I/O

68

I/O

108

D2-1/0

148

A7-1/0

29

I/O

69

I/O

109

I/O

149

I/O

30

I/O

70

I/O

110

I/O

150

I/O

31

I/O

111

I/O

151

A11-1/0

I/O

71
, 72

I/O

32

I/O

112

I/O

152

A8-1/0

33

I/O

73

I/O

113

I/O

153

I/O

34

I/O

74

I/O

114

D1-1/0

154

I/O

35

I/O

75

I/O'

115

RDV!BCJSY-RcrK-I/O

155

A10-1/0

36

I/O

76

XTL2-1/0

116

I/O

156

AS-I/O

37

I/O

77

GND

117

I/O

157

VCC

38

I/O'

78

RESET

118

I/O'

158

GND

39

I/O'

79

VCC

119

DO-DIN-I/O

159

~

40

M 1-l1I5A'i'A

80

DONEiI'G

120

DOUT-I/O

160

TCLKIN-I/O

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed lOBs are default slew-rate limited.
'Indicates unconnected package pins (18) for the XC3064A.

4-334

June 1, 1996 (Version 2.0)

~XILINX
XC3000 Series 175-Pin Ceramic and Plastic PGA Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts

XC3090A, XC3195A

PGA Pin
Number

XC3090A, XC3195A

PGA Pin
Number

XC3090A, XC3195A

013

1/0

R14

OONE-PG

N4

OOUT-I/O

814

Ml-ROATA

N13

07-1/0

R2

CCLK

1/0

C14

GNO

T14

XTL 1(OUT)-8CLKIN-1/0

P3

VCC

C4

1/0

815

MO-RTRIG

P13

1/0

N3

GNO

PGAPin
Number

XC3090A, XC3195A

PGAPin
Number

82

PWRON

04

TCLKIN-I/O

83
84

1/0

014

VCC

R13

1/0

P2

AO-WS-I/O

A4

1/0

C15

M2-1/0

T13

1/0

M3

Al·CS2-1/0

1/0

05

1/0

E14

HOC-I/O

N12

1/0

Rl

C5

1/0

816

1/0

P12

06-1/0

N2

1/0

85

1/0

015

1/0

R12

1/0

Pl

A2-1/0

A5

1/0

C16

1/0

T12

I/O

Nl

A3-1/0

C6

I/O

016

LDC-I/O

Pll

1/0

L3

1/0

06

1/0

F14

1/0

Nl1

I/O

M2

1/0

86

1/0

E15

1/0

Rll

I/O

Ml

A15-1/0

A6

1/0

E16

I/O

Tl1

05-1/0

L2

A4-1/0

87

1/0

F15

1/0

Rl0

CSO-I/O

Ll

1/0

C7

1/0

F16

I/O

Pl0

I/O

K3

07

1/0

G14

1/0

Nl0

1/0

K2

1/0
A14-1/0

A7

110

G15

1/0

Tl0

1/0

Kl

A5-1/0

A8

1/0

G16

1/0

T9

1/0

Jl

1/0

88

110

H16

1/0

R9

04-1/0

J2

1/0

C8

110

H15

INIT-I/O

P9

1/0

J3

GNO

08

GNO

H14

VCC

N9

VCC

H3

VCC

09

VCC

J14

GNO

N8

GNO

H2

A13-1/0

C9

1/0

J15

1/0

P8

03-110

H1

A6-1/0

89

110

J16

1/0

RS

CSH/O

Gl

110

A9

1/0

K16

110

T8

1/0

G2

1/0

Al0

1/0

K15

1/0

T7

1/0

G3

110

010

1/0

K14

1/0

N7

I/O

Fl

1/0

C10

1/0

L16

1/0

P7

1/0

F2

A12-1I0

810

1/0

L15

1/0

R7

02-110

El

A7-1/0

All

1/0

M16

1/0

T6

1/0

E2

1/0

811

1/0

M15

1/0

R6

1/0

F3

1/0

011

1/0

L14

1/0

N6

1/0

01

Al1-1I0

Cll

1/0

N16

1/0

P6

1/0

Cl

AS-I/O

A12

1/0

P16

1/0

T5

1/0

02

I/O

812

110

N15

110

R5

OHIO

81

1/0

C12

I/O

R16

1/0

P5

ROY/BUSY-RCLK-I/O

E3

Al0-1/0

012

110

M14

1/0

N5

1/0

C2

A9-1/0

A13

110

P15

XTL2(IN)-1/0

T4

1/0

03

VCC

813

1/0

N14

GNO

R4

1/0

C3

GNO

C13

1/0

R15

RESET

P4

1/0

A14

110

P14

vee

R3

OO-OIN-I/O

I

~

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for un bonded or unused lOBs.
Programmed outputs are default slew-rate limited.
Pins A2, A3, A 15, A 16, T1 , T2, T3, T15 and T16 are not connected. Pin A 1 does not exist.

June 1, 1996 (Version 2.0)

4-335

XC3000 Series Field Programmable Gate Arrays

XC3000 Series 176-Pin TQFP Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Pin
Number

XC3090A

Pin
Number

XC3090A

Pin
Number

XC3090A

Pin
Number

1

PWRDWN

45

M1-RDATA

89

DONE-PG

133

VCC

2

TCLKIN-I/O

46

GND

90

D7-1/0

134

GND

3

liD

47

MO-RTRIG

91

XTAl1 (OUT)-BClKIN-I/O

135

AO-WS-I/O

4

liD

48

VCC

92

liD

136

A1-CS2-1/0

5

liD

49

M2-1/0

93

liD

137

-

6

liD

50

HDC-I/O

94

liD

138

I/O

-

XC3090A

7

liD

51

liD

95

liD

139

liD

8

liD

52

liD

96

D6-1/0

140

A2-1/0

9

liD

53

liD

97

liD

141

A3-1/0

10

I/O

54

lDC-I/O

98

liD

142

11

liD

55

-

99

liD

143

-

12

I/O

56

liD

100

liD

144

liD

13

liD

57

I/O

101

liD

145

liD

14

I/O

58

liD

102

D5-1/0

146

A15-1/0

15

liD

59

I/O

103

CSO-I/O

147

A4-1/0

16

liD

60

liD

104

liD

148

liD

17

liD

61

liD

105

liD

149

liD

18

liD

62

liD

106

liD

150

A14-1/0

19

liD

63

I/O

107

liD

151

AS-liD

20

liD

64

liD

108

D4-1/0

152

I/O

21

liD

65

IN IT-liD

109

liD

153

liD

22

GND

66

VCC

110

VCC

154

GND

23

VCC

67

GND

111

GND

155

VCC

24

I/O

68

liD

112

D3-1/0

156

A13-1/0

25

liD

69

liD

113

CS1-1/0

157

AS-li~

26

I/O

70

liD

114

I/O

158

I/O

27

liD

71

liD

115

I/O

159

liD

28

I/O

72

liD

116

I/O

160

29

liD

73

liD

117

I/O

161

-

30

I/O

74

liD

118

D2-1/0

162

liD

31

liD

75

I/O

119

I/O

163

liD

32

liD

76

liD

120

liD

164

A12-1/0

33

liD

77

liD

121

liD

165

A7-1/0

34

liD

78

liD

122

liD

166

liD

35

liD

79

liD

123

liD

167

liD

36

liD

80

liD

124

D1-1/0

168

-

37

liD

81

liD

125

RDY/BUSY-RCLK-I/O

169

A11-1/0

38

liD

82

liD

170

AS-li~

liD

83

-

126

39

127

liD

171

liD

40

I/O

84

liD

128

liD

172

I/O

41

liD

85

XTAL2(IN)-1/0

129

liD

173

A10-1/0

42

liD

86

GND

130

DO-DIN-I/O

174

A9-1/0

43

liD

87

RESET

131

DOUT-I/O

175

VCC

44

-

88

VCC

132

CCLI(

176

GND

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.

4-336

June 1, 1996 (Version 2.0)

~XILINX
XC3000 Series 20B-Pin PQFP Pinouts
XC3000A, and XC3000L families have identical pinouts
Pin Number

XC3090A

1

-

Pin Number

XC3090A

53

-

.~

2

GNO

54

Pin Number
105
106

XC3090A

Pin Number

XC3090A

-

157

VCC

158

-

3

PWRDWN

55

VCC

107

DIP

159

-

4

TCLKIN-I/O

56

M2-1I0

108

-

160

GNO

5

1/0

57

HDC-I/O

109

D7-1/0

161

WS-AO-I/O

6

1/0

58

110

110

XTL 1-BCLKIN-1I0

162

CS2-A1-1/0

7

110

59

1/0

111

1/0

163

1/0

8

1/0

60

1/0

112

1/0

164

1/0

9

1/0

61

I:iJC-1/0

113

110

165

A2-1/0

10

1/0

62

1/0

114

1/0

166

A3-1/0

11

1/0

63

1/0

115

D6-1I0

167

110

12

1/0

64

-

116

1/0

168

1/0

13

1/0

65

110

169

1/0

66

-

117

14

118

1/0

170

15

-

67

-

119

-

171

-

16

1/0

68

110

120

110

172

A15-1/0

17

1/0

69

1/0

121

1/0

173

A4-1/0

18

1/0

70

1/0

122

05-110

174

1/0
1/0

--- --

19

110

71

1/0

123

CSO-IIO

175

20

1/0

72

124

110

176

-

21

1/0

73

-

125

1/0

177

-

22

1/0

74

110

126

1/0

178

A14-1I0

23

1/0

75

1/0

127

110

179

A5-1/0

24

1/0

76

110

128

D4-1/0

180

1/0

25

GND

77

fNiT-I/O

129

110

181

1/0

26

VCC

78

VCC

130

VCC

182

GND

-Ifc)-~

79

GNO

131

GNO

183

VCC

28

1/0

80

1/0

132

03-1/0

184

A13-1/0
A6-1I0

27
29

1/0

81

110

133

CS1-1/0

185

30

1/0

82

1/0

134

1/0

186

I/O

31

110

83

135

110

187

110

32

110

84

-

136

110

188

33

1/0

85

1/0

137

1/0

189

34

110

86

110

138

D2-1/0

190

35

1/0

87

1/0

139

1/0

191

110

36

1/0

88

1/0

140

110

192

A12-1/0

--

1/0

37

-

89

1/0

141

1/0

193

A7-1/0

38

1/0

90

-

142

-

194

39

1/0

91

143

I/O

195

40

1/0

92

-

144

1/0

196

-

41

1/0

93

110

145

OHIO

197

110

42

1/0

94

1/0

146

ROY/BUSY-RCLK-I/O

198

110

43

1/0

95

110

147

1/0

199

A11-I/O

44

1/0

96

110

148

1/0

200

A8-1/0

45

1/0

97

1/0

149

1/0

201

110

46

1/0

98

110

150

1/0

202

1/0

47

1/0

99

1/0

151

DIN-DO-I/O

203

A10-1I0

48

M1-RDATA

100

XTL2-I/O

152

DOUT-I/O

204

A9-1/0

49

GND

101

GNO

153

CCLK

205

VCC

50

MO-RTRIG

102

RESET

154

VCC

206

-

-

103

-

155

-

207

-

51
----;0;--

52

--

104

156

208

I

-

Unprogrammed lOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused lOBs.
Programmed outputs are default slew-rate limited.
'In PQ208, XC3090A and XC3195A have different pinouts.

June 1, 1996 (Version 2.0)

4-337

XC3000 Series Field Programmable Gate Arrays

XC3195A PQ208 and PG223 Pinouts

Pin Description

PG223 PQ208

Pin Description

PG223 PQ208

Pin Description

PG223 PQ208

Pin Description

110

C2

203

1/0
110

Cl

202

110
110
1/0

02

201

ROY/BUSY-RCLK-I/O

U4

149

U5

148

110
110
110
110
1/0

N15

96

R6

147

110

R18

95

T5

146

110

P17

94

U6

145

110

N17

93

T6

144

110

N16

92

V7

141

110

M15

89

R7

140

110

M18

88

U7

139

M17

87

L18

86

L17

85

L15

84

L16

83

K18

82

K17

81

110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110
110

K16

80

110

A9-1/0

Bl

206

DO-DIN-I/O

U3

154

110

U18

102

Al0-1/0

E3

205

I/O

V3

153

110

P15

101

1/0

E4

204

R5

152

T17

100

T4

151

T18

99

V4

150

P16

98

R17

97

A8-1/0

E2

200

A11-IIO

F4

199

110
110
110
110

F3

198

G2

194

A7-1/0

G4

193

A12-1J0

Gl

192

DH/O
110
110
110
1/0
110
110
110

1/0
110
1/0

H2

191

D2-1I0

V8

138

H3

190

110

U8

137

Hl

189

110

T8

136

110

H4

188

R8

135

110
1/0

J3

187

V9

134

J2

186

A6-1I0

Jl

185

110
110
CSH/O
D3-1/0

A13-1/0

K3

184

VCC

J4

GND

Dl

197

F2

196

PG223 PQ208
A16

48

D14

47

C15

46

B15

45

A15

44

C14

43

D13

42

B14

41

C13

40

B13

39

B12

38

D12

37

A12

36

Bll

35

Cll

34

All

33

Dll

32

U9

133

T9

132

110
110
110
110
1/0
110
110
110

GND

R9

131

GND

K15

79

VCC

Dl0

183

VCC

Rl0

130

VCC

J15

78

GND

D9

26

K4

182

Tl0

129

INIT

J16

77

110

B9

25

110
110

K2

181

Ul0

128

110

J17

76

110

A9

24

Kl

180

Vl0

127

110

J18

75

110

C8

23

Rll

126

H16

74

110

D8

22

Tll

125

H15

73

110

B8

21

Ull

124

H17

72

110

A8

20

H18

71

110

B7

19

G17

70

A7

18

G18

69

D7

17

G15

68

F16

67

M2

174

110
D4-1/0
110
1/0
110
110
CSO-I/O
D5-1/0
110

R12

121

A4-1/0

M4

173

110

V12

120

A15-1/0

N2

172

T13

119

U13

118

110
110
110
110
110
1/0
110
110
110

F17

66

T14

117

110

E17

63

R13

116

C18

62

U14

115

F15

61

U15

114

110
110
110

D17

60

V15

113

IJ)C-I/O

E16

59

C17

58

B18

57

AS-li~

L2

179

A14-1/0

L4

178

110
110
110
110

L3

177

Ll

176

Ml

175

Vll

123

U12

122

110

P3

164

110

T15

112

110

T2

163

110

R14

111

110

P4

162

110

V16

110

110
110
1/0

E15

56

1/0

Ul

161

XTLX1 (OUT)8CLKN-I/O

U16

109

HDC-I/O

A18

55

110
110
110
110
110
110
110
1/0
110
110
110
110
110
110

Al-CS2-1/0

Vl

160

T16

108

M2-1/0

A17

54

AO-WS-I/O

T3

159

D7-1/0
DIP

V17

107

VCC

D16

53

GND

R3

158

VCC

R15

106

MO-RTIG

B17

52
51

110

N3

171

110
110
110

P2

169

Rl

168

N4

167

A3-1/0

Tl

166

A2-1/0

R2

165

110
110
110
110
110
D6-1/0
110

VCC

R4

157

RES8

U17

105

GND

D15

CCLK

U2

156

GND

R16

104

Ml/RDATA

C16

50

DOUT-I/O

V2

155

XTL2(IN)-1I0

V18

103

1/0

B16

49

Al0

31

Bl0

30

Cl0

29

C9

28
27

B6

14

C6

13

B5

12

A4

11

D6

10

C5

9

B4

8

B3

7

C4

6

D5

5

C3

4

A3

3

TCLKIN-IJO

A2

2

PWRDN
GNO
VCC

B2

1

04
03

208
207

Unprogrammed lOBs have a default pUll-up. This prevents an undefined pad level for un bonded or unused lOBs. Programmed outputs are
default slew-rate limited.
In thePQ208 package. pins 15. 16. 64, 65. 90, 91.142.143.170 and 195 are not connected.
In the PG223 package. the following pins are not connected: A5. A6, A 13. A 14. 018. El. Et8. Fl. FlB. Nl. N18. Pl. P18, V5. V6, V13. and
V14.
*In PQ208, XC3090A and XC3195A have different pinouts.

4-338

June 1. 1996 (Version 2.0)

~XILINX
Product Availability
Pins

44

Type

Code

XC3020A
XC3030A
XC3042A
XC3064A
XC3090A
XC3020L
XC3030L
XC3042L
XC3064L
XC3090L

XC3120A

XC3130A

XC3142A

XC3164A

XC3190A

XC3195A

64

68

84

132

100

Plast.
TOFP

Plast.
POFP

PP132

PG132

TOl44

P0160 CB164

CI

PLCC

Plast.
PLCC

Cer.
PGA

Plast.P
OFP

Plast.
TOFP

Plast.
VOFP

PC44

V064

PC68

PC64

PG84

POl 00

T0100

VOl 00 CB100

CI

CI

CI

CI

-6

175

164

176

208

223

TopPGA

Plast.
VOFP

-7

160

Plast.
PGA

Plast.
PLCC

Plast.

144

TopBrazed
COFP

Cer.

Brazed Plast.
COFP

Cer.
PGA

Plost.
TOFP

Plast.
POFP

PGA

PP175

PG175

T0176

P0208

PG223

C

C

C

C

-7

CI

CI

CI

CI

CI

CI

-6

C

C

C

C

C

C

C

-7

CI

CI

CI

CI

CI

CI

-6

C

C

C

C

C

C

C

-7

CI

CI

CI

CI

-6

C

C

C

C

C

-7

CI

CI

CI

CI

CI

CI

CI

-6

C

C

C

C

C

C

C

-8
-8
-8
-8
-8

C
C

CI

C

C

C

C

C

C

C

-5

CI

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

-2

CI

CI

CI

CI

-1

C

C

C

C

-09

C

C

C

C

CI

I

C

C

-4

Cer.

PGA

C

CI

-5

CI

CI

CI

CI

CI

CI

CI

-4

CI

CI

CI

CI

CI

CI

CI

-3

CI
CI

CI
CI

CI

CI

CI

CI
CI

CI

-2

CI
CI

CI

CI

-1

C

C

C

C

C

C

C

-09

C

C

C

C

C

C

C

-5

CI

CIMS

CI

C

C

CIMS

-4

CI

CI

CI

C

C

CI

CI

-3
-2

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

-1

C

C

C

C

C

C

C

-09

C

C

C

C

C

C

C

MS

CI

-5

CI

CI

CI

CI

-4

CI

CI

CI

CI

CI

-3
-2

CI

CI

CI

CI

CI

CI

CI

CI

CI

CI

-1

C

C

C

C

C

-09

C

C

C

C

-5

CI

CI

CI

CIMS

CI

CI

-4

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

CI

-2

CI

CI

CI

CI

CI

CI
C

CI

C
MS

-1

C

C

C

C

C

-09

C

C

C

C

C

-5

CI

CI

CI

CIMS

CI

-4

CI

CI

CI

CI

CI

CI

-3

CI

CI

CI

CI

CI

CI

-2
-1

CI

CI

CI

CI

CI

CI

C

C

C

C

C

C

-09

C

C

C

C

C

C

June 1, 1996 (Version 2;0)

MS

C
CIMS

4-339

XC3000Series Field Programmable Gate Arrays

44

Pins

Type
Code

XC3142L
XC3190L
Notes.

64

68

84

100
PI.51.
TQFP

132
Top·
Brazed
CQFP

Plast.
PGA

pP132

Plast.
PLCC

Pisst.
VQFP

Plast.
PLCC

Plast.
PLCC

Cer.
PGA

Plast.P
QFP

PC44

VQ64

PC6S

PC84

PG84

PQ100 TQ100 VQ100 CB100

Plast.
VQFP

144

160

164

Plast.
PQFP

Top·
Brazed
CQFP

Plast.
PGA

PG132 TQ144 PQ160 CB164

PP175

Cer.
PGA

Plast.
TQFP

175
Cer.
PGA

176

208

223

Plast.
TQFP

Plast.
PQFP

Cer.
PGA

PG175 TQ176 PQ208 PG223

·3'

C

C

C

·2'

C

C

C

·3'

C

C

C

C

C

C

·2'

.

Advance Information

C = Commercial, T J= 0° to +85°C
M=Military Temp, T c= ·55° to +125°C

I = Industrial, T J = ·40° to +100°C
B = MIL·STD·883C Class B

Ordering Information
Example:

XC3030A-3 PC44C

JT~
TL

Device T y p e _J- - - I
Speed Grade

-

Temperature Range
Number of Pins
Package Type

4·340

June 1, 1996 (Version 2.0)

XC3000A
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0)

Product Specification

Features

Description

•

The XC3000A family offers the following enhancements
over the popular XC3000 family:

•

•

•

•
•

Enhanced, high performance FPGA family with five
device types
Improved redesign of the basic XC3000 FPGA
family
- Logic densities from 1,000 to 6,000 gates
- Up to 144 user-definable II0s
Superset of the industry-leading XC3000 family
- Identical to the basic XC3000 in structure, pin out,
design methodology, and software tools
- 100% compatible with all XC3000, XC3000L, and
XC3100A bitstreams
- Improved routing and additional features
Additional programmable interconnection points (PIPs)
Improved access to longlines and CLB clock enable
inputs
- Most efficient XC3000-class solution to bus-oriented
designs
Advanced 0.8 Jl and 0.6 Jl CMOS static memory
technology
- Low quiescent and active power consumption
Performance specified by logic delays, faster than
corresponding XC3000 versions
XC3000A-specific features
4 mA output sink and source current
Error checking of the configuration bitstream
Soft startup starts all outputs in slew-limited mode
upon power-up
Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production.
"--

Device
XC3020A
XC3030A
XC3042A
XC3064A
XC3090A

Max Logic
Gates
1,500
2,000
3,000
5,000
6,000

June 1, 1996 (Version 1.0)

Typical Gate
Range
1,000 - 1,500
1,500 - 2,000
2,000 - 3,000
4,000 - 5,000
5,000 - 6,000

eLBs
64
100
144
224
320

The XC3000A family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000A devices check the bitstream format for stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.
When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew
rate of the individual outputs is, as in the XC3000 family,
determined by the individual configuration option.
The XC3000Afamily is a superset of the XC3000family.
Any bitstream used to configure an XC3000, XC3100 or
XC3100A device configures an XC3000A device exactly
the same way.

Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20

User I/Os
Max
64
80
96
120
144

Flip-Flops
256
360
480
688
928

Horizontal Configuration
Longlines
Data Bits
16
14,779
20
22,176
24
30,784
32
46,064
40
64,160

4-341

I

XC3000A Field Programmable Gate Arrays

XC3000A Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.

XC3000A Operating Conditions
Symbol

Min

Max

Units

Vee

Supply voltage relative to GND Commercial O°C to +85°C junction

4.75

5.25

4.5

5.5

V
V

V IHT

Supply voltage relative to GND Industrial-40°C to + 100°C junction
High-level input voltage .-:- TTL configuration

2.0

V ILT

Low-level input voltage - TTL configuration

0

Vcc
0.8

V IHe

High-level input voltage -

CMOS configuration

70%

100%

Vee

VILe

Low-level input voltage

CMOS configuration

0

20%

TIN

Input signal transition time

Vee
ns

Note:

Description

~

250

V
V

At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.

XC3000A DC Characteristics Over Operating Conditions
Symbol

Description

V OH

High-level output voltage (@ IOH = -4.0 mA, Vee min)

VOL
V OH

Low-level output voltage (@ IOL = 4.0 mA, Vee min)

VOL
VeePD
leePD

Iceo
IlL

C IN

IRIN
IRLL

High-level output voltage (@ IOH =-4.0 mA, Vee min)
Low-level output voltage(@ IOL = 4.0 mA, Vec min)
Power-down supply voltage (PWRDWN must be Low)
Power-down supply current
(VeC(MAX) @ T MAX)

Min
Commercial
Industrial

0040

V

0040

V
V
V

2.30
3020A
3030A
3042A
3064A
3090A

-10

Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
Pad pull-up (when selected) @ VIN = 0 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low

Units
V

3.76

Quiescent FPGA supply current in addition to leePD
Chip thresholds programmed as CMOS levels
Chip thresholds programmed as TTL levels
Input Leakage Current

Max

3.86

100
160
240
340
500

!!A
!!A
!!A
!!A
!!A

500
10

!!A
!!A

+10

!!A

10
15

pF
pF
..

0.02

16
20

pF
pF

0.17

mA
mA

304

Notes: 1. With no output current loads, no active input or Longline pull-up resistors, all package pins at Vcc or GND, and the FPGA
device configured with a MakeBits tie option.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
too mA per Vce pin. The number of ground pins varies from the XC3020A to the XC3090A.

4-342

June 1, 1996 (Version 1.0)

~XILINX
XC3000A Absolute Maximum Ratings
Vee
V IN

Supply voltage relative to GND

VTS

Voltage applied to 3-state output

T STG
TSOL
TJ
Note:

Units

Description

Symbol

-0.5 to +7.0
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
+260
+125
+150

Input voltage with respect to GND
Storage temperature (ambient)
Maximum soldering temperature (10 s @ 1/16 in.)
. Junction temperature plastic
Junction temperature ceramic

V
V
V
°C
°C
°C
°C

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.

I

XC3000A Global Buffer Switching Characteristics Guidelines
Description

Speed Grade

-7

-6

Symbol

Max

Max

Units

Global and Alternate Clock Distribution'
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input

T plD

7.5

7.0

ns

TplDe

6.0

5.7

ns

TBUF driving a Horizoqtal Longline (L.L.)'
I to L.L. while T is Low (buffer active)
T -J, to L.L. active andvalid with single pull-up resistor
T -J, to L.L. active and valid with pair of pull-up resistors
Tt to L.L. High with single pull-up resistor
Tt to L.L. High with pair of pull-up resistors

T IO
TON
TON
Tpus
T pUF

4.5
9.0
11.0
16.0
10.0

4.0
8.0
10.0
14.0
8.0

ns
ns
ns
ns
ns

T61DI

1.7

1.5

ns

BIOI
Bidirectional buffer delay
Note:

1. Timing is based on the XC3042A, for other devices see XACT timing calculator.

June 1, 1996 (Version 1.0)

XC3000A Field·Programmable Gate Arrays

XC3000A CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.

-7

Speed Grade
Description
Combinatorial Delay
Logic Variables

A, 8, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode

Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode

Symbol

Max

Units

5.1
5.6

4.1
4.6

ns
ns

8

TCKO

4.5

4.0

ns

TOLO

9.5
10.0

8.0
8.5

ns
ns

TICK

4
6

Hold Time after clock K
Logic Variables
A,8,C,D,E
DI2
Data In
Enable Clock
EC

Global Reset (RESET Pad)1
RESET width (Low)
delay from RESET pad to outputs X or Y

Min

T llO

2

Reset Direct (RD)
RD width
delay from RD to outputs X or Y

-6
Max

1

Set-up time before clock K
A,8,C,D,E
Logic Variables
FG Mode
F and FGM Mode
DI
Data In
Enable Clock
EC

Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate

Min

T DICK
T ECCK

4.5
5.0
4.0
4.5

3.5
4.0
3.0
4.0

ns
ns
ns
ns

3
5
7

TCKI
TCKDI
T CKEC

0
1.0
2.0

0
1.0
2.0

ns
ns
ns

11
12

TCH
TCl
FClK

4.0
4.0
113.0

3.5
3.5
135.0

ns
ns
MHz

13
9

T RPW

6.0

T MRW
TMRO

5.0
6.0

TRIO
16.0

5.0

ns
ns

17.0

ns
ns

14.0
19.0

Notes: 1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

4-344

June 1, 1996 (Version 1.0)

~:XILINX
XC3000A CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y)
(Combinatorial)

CLB Input (A,B,C,DiE)

2

-

T ICK _

CLB Clock

3

TCKI_

~

J
@TCL

_evTDICK_

_0

TCKDI

-0

TCKEC

CLB Input
(Direct In)

.I-@
CLB Input
(Enable Clock)

.. ~

.. _@TCH

T ECCK----..

i

I

;(

----------------------------~-------*~---I-@TCKO_

CLB Output
(Flip-Flop)

CLB Input
(Reset Direct)

-'1\

~------------------------

@ T RIO -t+--~
CLBOutput
(Flip-Flop)

i

X5424

June 1, 1996 (Version 1.0)

4-345

XC3000A Field Programmable Gate Arrays

XC3000A lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recomrnended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.

Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (0) with latch transparent
Clock (IK) to Registered In (0)
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad
(fast)
same
(slew rate limited)
Output (0) to Pad
(fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z
(fast)
same
(slew-rate limited)
3-state to Pad active and. valid (fast)
same
(slew -rate limited)
Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In
(0)
RESET Pad to output pad
(fast)
(slew-rate limited)
Notes:

4-346

Speed Grade
Symbol
3

-6

-7
Min

Max

Min

4.0
15.0
3.0

Max

Units

3.0
14.0
2.5

ns
ns
ns

4

TplD
T pTG
TIKRI

1

T plCK

7
7
10
10
9
9
8
8

T OKPO
T OKPO
T OPF
Tops
TTSHZ
TTSHZ
TTSON
TTSON

5
6

TOOK
TOKO

8.0
0

7.0
0

ns
ns

11
12

TIOH
TIOl
FClK

4.0
4.0
113.0

3.5
3.5
135.0

ns
ns
MHz

13
15
15

TRRI
T RPO
T RPO

14.0

12.0
8.0
18.0
6.0
16.0
10,0
20.0
11.0
21.0

24.0
33.0
43.0

ns
7.0
15.0
5.0
13.0
9.0
12,0
10.0
18.0

ns
ns
ns
ns
ns
ns
ns
ns

23.0
29.0
37.0

ns
ns
ns

1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
riselfall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T PID, T PTG, and T PICK are 3 ns higher for XTL2 when the pin is configures as a user input.

June 1 i 1996 (Version 1.0)

~XILINX
XC3000A lOB Switching Characteristics Guidelines (continued)
110 Block (I)

liD Pad Input

i

110 Clock (lK/OK)

_

1 T PICK--+-

i=="@TIOL _ _ _ _

•

@

TIOH - - - - + -

.x

110 Block (RI)

_@T,KR,_I

....-0

TOOK----+-

-+-0 TOK0..::j

@Top ....

\
_1@TRPol_

1I

.I-+-

.x

lIO Pad Output
(Direct)

.....

'-0

--------------~*~---

110 Pad Output
(Registered)

110

.I--@

.x

110 Block (0)

'--

ToKPO

j---1r-0-~-oN--~®-T~-.1 1--------~(~__________~r--

PadTS

liD Pad Output

X5425

PROGRAM"CONTROLLED MEMORY CELLS

OUT _--I-°"---IL/

DIRECT IN

REGISTERED IN

-+----+--------,
-+Q'-------+---1 Q 01---"-+-----<:" 1--------1
FLIP
FLOP

0'
LATCH

=DJune 1, 1996 (Version 1 .0)

PROGRAM
CONTROLLED

MULTIPLEXER

o=

TTL or
CMOS
INPUT
THRESHOLD

PROGRAMMABLE INTERCONNECTION POINT or PIP

X3029

4-347

XC3000A Field Programmable Gate Arrays

Product Availability
PINS

44

64

68

TYPE

PlAST.
PlCC

PlAST.
VQFP

PlAST.
PlCC

PlAST.
PlCC

CERAM
PGA

PlAST.
PQFP

PlAST.
TQFP

PlAST.
VQFP

TOPBRAZED
CQFP

PC44

VQ64

PC68

PC84

PG84

PQ100

TQ100

VQ100

CB100

CI

CI

CI

CI

CODE
XC3020A
--

XC3030A
XC3042A
XC3064A
XC3090A

-7
-6

84

100

-7

CI

CI

C
CI

C
CI

C
CI

C
CI

CI

-6
-7

C

C

C

C
CI

C
CI

C
CI

CI

-6
-7

C
CI

C

C

C

-6
-7

C
CI

-6

----

PINS

132

144

160

TYPE

PlAST.
PGA

CERAM.
PGA

PlAST.
TQFP

PlAST.
PQFP

CODE

PP132

PG132

TQ144

PQ160

-7

CI

CI

CI

-6

C
CI

C
CI

C
CI

C

C

C

C

164
175
TOPPlAST. CERAM.
BRAZED
PGA
PGA
CQFP
CB164

PP175

176

208

223

PlAST.
TQFP

PlAST.
PQFP

CERAM.
PGA

PG175

TQ176

PQ208

PG223

-7
XC3020A
-6
XC3030A
XC3042A
XC3064A
XC3090A

-7
-6

-7
-6
-7

--

-6

CI

- - I-----~--

C

C

CI

CI

CI

CI

CI

CI

C

C

C

C

C

C

--,

--~

Note:

C

=Commercial, TJ =0° to +B5"C

I =Industrial, T J

=-40° to +100°C

Ordering Information
Example:
XC3020A-6PC84C

Dev;,e Type

I

TTTL

Speed Grade-------lJ

Tempe,,'u," Range
Number of Pins
Package Type

4-348

June 1,1996 (Version 1,O}

XC3000L
Field Programmable Gate Arrays
June 1, 1996 (Version 1.0)

Product Specification

Features

family is in all respects identical with the XC3000A family,
and is a superset of the XC3000 family.

•

•

•

•

•

Part of the Zero+ family of 3.3 V FPGAs
JEDEC-compliant 3.3 V version of theXC3000A
FPGA family
- Logic densities from 1,000 to 6,000 gates
Up to 144 user-definable II0s
Advanced, low power 0.8 ~ and 0.6 ~ CMOS static
memory technology
Very low quiescent current consumption, ~ 20~A
Operating power consumption 56% less than
XC3000A, 66% less than previous generation 5 V
FPGAs
Superset of the industry-leading XC3000 family
Identical to the basic XC3000A in structure, pinout,
design methodology, and software tools
100% compatible with.all XC3000, XC3000A,
XC3100L and XC3100A bitstreams
Improved routing and additional features
Additional programmable interconnection points (PIPs)
Improved access to Longlines and CLB clock enable
inputs
Most efficient XC3000-class solution to bus-oriented
designs
XC3000L-specific features
Guaranteed over the 3.0 to 3.6 V Vcc range
- 4 mA output sink and source current
Error checking of the configuration bitstream
- Soft startup starts all outputs in slew-limited mode
upon power-up
- Easy migration to the XC3400 series of HardWire
mask programmed devices for high-volume
production

The operating power consumption of Xilinx FPGAs is
almost exclusively dynamic, and it changes with the square
of the supply voltage. For a given complexity and clock
speed, the XC3000L consumes, therefore, only 44% of the
power used by the equivalent XC3000A device. In accordance with its use in battery-powered equipment, the
XC3000L family was designed for the lowest possible
power-down and quiescent current consumption.
In mixed supply-voltage systems, the XC3000L, fed by a
3.3 V (nominal) supply, can directly drive any device with
TTL-like input thresholds. When a 5 V device drives the
XC3000L, a current-limiting resistor (1 kQ) or a voltage
divider is required to prevent excessive input current.
Like the XC3000A family, XC3000L offers the following
functional improvements over the popular XC3000 family:
The XC3000L family has additional interconnect resources
to drive the I-inputs of TBUFs driving horizontal Longlines.
The CLB Clock Enable input can be driven from a second
vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are
used for data bussing.
During configuration, the XC3000L devices check the bitstream format for stop bits in the appropriate positions. Any
error terminates the configuration and pulls INIT Low.

Description
The XC3000L family of FPGAs is optimized for operation
from a nominally 3.3 V supply. Aside from the electrical and
timing parameters listed in this data sheet, the XC3000L

Device

XC3020L
XC3030L
XC3042L
XC3064L
XC3090L

Max Logic
Gates

Typical Gate
Range

1,500
2,000
3,000

1,000 - 1,500
1,500 - 2,000
2,000 - 3,000

5,000
6,000

4,000 - 5,000
5,000 - 6,000

June 1, 1996 (Version 1.0)

When the configuration process is finished and the device
starts up in user mode, the first activation of the outputs is
automatically slew-rate limited. This feature, called Soft
Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew
rate of the individual outputs is, as in the XC3000 family,
determined by the individual configuration option.
The XC3000L family is a superset of the XC3000family.
Any bitstream used to configure an XC3000 device configures an XC3000L device the same way.

CLBs

Array

User 1I0s
Max

Flip-Flops

64
100
144
224
320

8x8
10 x 10
12 x 12
16 x 14
16 x20

64
80
96
120
144

256
360
480
688
928

Horizontal Configuration
Data Bits
Longlines

16
20
24
32
40

14,779
22,176
30,784
46,064
64,160

4-349

I

XC3000L Field Programmable Gate Arrays

XC3000L Switching Characteristics
Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released
device performance parameters, please request a copy of the current test-specification revision.

XC3000L Operating Conditions
Symbol
Vee
V IH
V IL
TIN

Description
Supply voltage relative to GND Commercial O°C to +85°C junction

Min

Max

Units

3.0

3.6

V

High-level input voltage -

2.0
-0.3

Ve e+0.3
0.8
250

V
ns

TTL configuration

Low-level input voltage - TIL configuration
Input signal transition time

V

Notes: 1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.
2. Although the present (1996) devices operate over the full supply voltage range from 3.0 to 5.25 V, Xilinx reserves the right to
restrict operation to the 3.0 to 6.0 V range later, when smaller device geometries might preclude operation at 5V. Operating
conditions are guaranteed in the 3.0 - 3.6 V Vee range.

XC3000L DC Characteristics Over Operating Conditions
Symbol
V OH
VOL
V OH
VOL
VeePD
leePD
leeo
IlL

C IN

IRIN
IRLL

Description

=-4.0 mA, Vee min)
Low-level output voltage (@ IOL =4.0 mA, Vee min)
High-level output voltage (@ IOH =-4.0 mA, Vee min)
Low-level output voltage (@ IOL =4.0 mA, Vee min)

High-level output voltage (@ IOH

Power-down supply voltage (PWRDWN must be Low)

Min

V
V
V

Vee -0.2
0.2

V
V

10

llA

2.30

-10

Input capacitance, PGA 175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2
Pad pull-up (when selected) @ V IN =0 V (sample tested)
Horizontal Longline pull-up (when selected) @ logic Low

Units

0.40

Power-down supply current (Vee(MAX) @ T MAX)
Quiescent FPGA supply current in addition to leePD 1
Chip thresholds programmed as CMOS levels
Input Leakage Current
Input capacitance, all packages except PGA175
(sample tested)
All Pins except XTL 1 and XTL2
XTL 1 and XTL2

Max

2.40

0.02

20

llA

+10

llA

10
15

pF
pF

15
20
0.17

pF
pF
mA

2.50

mA

Notes: 1. With no output current loads, no active input o(Longline pull-up resistors, all package pins at Vee or GND, and the FPGA
device configured with a MakeBits tie option. leeo is in addition to leepo.
2. Total continuous output sink current may not exceed 100 mA per ground pin. Total continuous output source may not exceed
100 mA perVce pin. The number of ground pins varies from the XC3020L to the XC3090L.

4-350

June 1, 1996 (Version 1.0)

~XILINX
XC3000L Absolute Maximum Ratings
Symbol

Description
Supply voltage relative to GND

Vee
V IN
VTS

Input voltage with respect to GND
Voltage applied to 3-state output

T STG

Storage temperature (ambient)

TSOL

Maximum soldering temperature (10 s @ 1/16 in.)

TJ

Junction temperature plastic
Junction temperature ceramic

-0.5 to +7.0
-0.5 to Vee +0.5
-0.5 to Vee +0.5
-65 to +150
+260
+125
+150

Units
V
V
V
°C
°C
°C
°C

~-.----.--""

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended
periods of time may affect device reliability.

I

XC3000L Global Buffer Switching Characteristics Guidelines
Description
Global and Alternate Clock Distribution 1
Either: Normal lOB input pad through clock buffer
to any CLB or lOB clock input
Or: Fast (CMOS only) input pad through clock
buffer to any CLB or lOB clock input
TBUF driving a Horizontal Longline (L.L.)1
I to L.L. while T is Low (buffer active)
T J. to L.L. active and valid with single pull-up resistor
Ti to L.L. High with single pull-up resistor
BIOI
Bidirectional buffer delay

Speed Grade
Symbol

-8
Max

Units

TplD

9.0

ns

T plDe

7.0

ns

TIO
TON
Tpus

5.0
12.0
24.0

ns
ns
ns

TSIDI

2.0

ns

1. Timing is based on the XC3042A, for other devices see XACT timing calculator.
2. The use of two pull-up resistors per Longline, available on other XC3000 devices, is not a valid option for XC3000L devices.

June 1, 1996 (Version 1.0)

4-351

XC3000L Field Programmable Gate Arrays

XC3000L CLB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.

-8

Speed Grade
Description
Combinatorial Delay
Logic Variables

A, B, C, D, E, to outputs X or Y
FG Mode
F and FGM Mode

Sequential delay
Clock k to outputs X or Y
Clock k to outputs X or Y when Q is returned
through function generators F or G to drive X or Y
FG Mode
F and FGM Mode
Set-up time before clock K
A,B,C,D,E
Logic Variables
FG Mode
F and FGM Mode
DI
Data In
Enable Clock
EC
Hold Time after clock K
A,B,C,D,E
Logic Variables
DI2
Data In
Enable Clock
EC
Clock
Clock High time
Clock Low time
Max. flip-flop toggle rate
Reset Direct (RD)
RD width
delay from RD to outputs X or Y
Global Reset (RESET Pad)'
RESET width (Low)
delay from RESET pad to outputs X or Y

Symbol

Min

Max

Units

1

T llO

6.7
7,5

ns
ns

8

TCKO

7.5

ns

T OlO

14.0
14.8

ns
ns

2

TICK

4
6

T DICK
TECCK

5 ..0
5.8
5.0
6.0

ns
ns
ns
ns

3
5
7

TCKI
TCKDI
T CKEC

0
2.0
2.0

ns
ns
ns

11
12

TCH
TCl
FCLK

5.0
5.0
80.0

ns
ns
MHz

13
9

T RPW

7.0
7.0

ns
ns

TRIO
TMRW
T MRO

16.0
23.0

ns
ns

Notes: 1. Timing is based on the XC3042L, for other devices see XACT timing calculator.
2. The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the
Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

4-352

June 1, 1996 (Version 1.0)

~XILINX
XC3000L CLB Switching Characteristics Guidelines (continued)

CLB Output (X, Y)
(Combinatorial)

CLB Input (A,B,C,D,E)

CLB Clock

t-----@ TCl - - -.....~I_@ T CH--------!~I
CLB Input
(Direct In)

CLB Input
(Enable Clock)

-------,.

t----@

T E C C K _ - 0 TCKEC

CLBOutput
(Flip-Flop)

CLB Input
(Reset Direct)

,

® T RIO _+---;~
CLB Output
(Flip-Flop)

X5424

June 1, 1996 (Version 1.0)

4-353

XC3000l Field Programmable Gate Arrays

XC3000L lOB Switching Characteristics Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-3851 0/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark
timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more
detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and
used in the simulator.

Speed Grade
Symbol

Description
Propagation Delays (Input)
Pad to Direct In (I)
Pad to Registered In (Q) with latch transparent
Clock (IK) to Registered In (Q)
Set-up Time (Input)
Pad to Clock (IK) set-up time
Propagation Delays (Output)
Clock (OK) to Pad
same
Output (0) to Pad
same
3-state to Pad begin hi-Z
same
3-state to Pad active and valid
same

(fast)
(slew rate limited)
(fast)
(Slew-rate limited)
(fast)
(slew-rate limited)
(fast)
(slew -rate limited)

Set-up and Hold Times (Output)
Output (0) to clock (OK) set-up time
Output (0) to clock (OK) hold time
'croCk
Clock High time
Clock Low time
Max. flip-flop toggle rate
Global Reset Delays (based on XC3042A)
RESET Pad to Registered In
(Q)
RESET Pad to output pad
(fast)
(slew-rate limited)

Notes:

4-354

3

-8

Min

Max

Units

5.0
24.0
6.0

ns
ns
ns

4

T plD
TpTG
TIKRI

1

TplCK

7
7
10
10
9
9
8
8

ToKPO
T OKPO
T OPF
Tops
TrsHz
TrsHz
TrsoN
TrsoN

5
6

TOOK
ToKO

12.0
0

ns
ns

11
12

TIOH
T IOl
FClK

5.0
5.0
80.0

ns
ns
MHz

13
15
15

TRRI
TRPo
T RPO

22.0

ns
12.0
28.0
9.0
25.0
12.0
28.0
16.0
32.0

ns
ns
ns
ns
ns
ns
ns
ns

25.0
35.0
51.0

ns
ns
ns

1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Typical slew rate limited output
rise/fall times are approximately four times longer.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal
pull-up resistor or alternatively configured as a driven output or driven from an external source.
3. Input pad set-up time is specified with respect to the internal clock (ik). In order to calculate system set-up time, subtract
clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (ik) is
negative. This means that pad level changes immediately before the internal clock edge (ik) will not be recognized.
4. T PID, T PTG, and r PICK are 3 ns higher for XTL2 when the pin is configures as a user input.

June 1, 1996 (Version 1.0)

~XILINX
XC3000L lOB Switching Characteristics Guidelines (continued)
VO Block (I)

1/0 Pad Input
~ 1

\

va Clock (lK/OK)

T PICK----.

r
@TIOL

'''--

@TIOH _

I

X

VO Block (RI)

_0 TIKRI":'1
~®TOOK--'- _ 0

.I+-@
\

TOK':.:::I

-I@TRPOI-

X····

va Q10ck (0)

.r.:-.

@T?p.,.

1

"'
____~________~i~~__
,

I/O P~d Output
. (Direct)

VO plid Output
(Registered)

X

"

,:'

:
~0

~t~-1----:-0-TTSO-N--~®::--TT-SHzj

VOPadTS

-------:-----<'(

VO Pad Output

I

".' '<

ToKPO ,

.

I-

'IX5425

OUT _+O"-_-IL....

DIRECT IN
REGISTERED IN

--t'------t--------,
-+'Q'-----+---I Q 0 t--'-ir-:---------o.IICE

OEIRESET

:
Cascaded
Serial
Memory

1 OEIRESET

1
1

I
1

1______ -'-_11

(low Resets the Address Pointer)

CClK
(OUTPUT)

DIN

DOl.JT
(OUTPUT)
X5090

Figure 2: Master Serial Mode. The one-time-programmable Serial Configuration PROM supports automatic loading of
configuration programs. Multiple devices can be cascaded to support additional FPGA. An early Dip inhibits the
PROM data output one CCLK cycle before the FPGA 1I0s become active.

5-4

June 1, 1996 (Version 1.0)

~XILINX
Standby Mode
The PROM enters a low-power standby mode whenever
CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input.
(A technique for further reducing the standby current of a
Serial Configuration PROM is described in the XCELL journal, Issue 11, page 13.)

Programming the XC1700 Family
Serial PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and
voltages are used. Different product types use different
algorithms and voltages, and the wrong choice can permanently damage the device.

Table 1: Truth Table for XC1700 Control Inputs
Control Inputs
CE

RESET
Inactive

Low

Active
Inactive
Active

Low
High
High

Outputs

Internal Address
DATA
if address5 TC: increment
if address> TC: don't change
Held reset
Not changing
Held reset

active
3-state
3-state
3-state
3-state

CEO
High
Low
High
High
High

Icc
active
reduced
active
standby
standby

I

Notes: 1. The XC1700 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC+ 1 = address O.

Table 2: Data 1/0 Programmer Locations for Programming RESET Polarity
Device
XC1718D or L
XC17360
XC17650 or L
XC171280 or L
XC172560 or L

Hex Address
80C through
11 B8 through
2000 through
4000 through
8000 through

80F
11 BB
2003
4003
8003

IMPORTANT: Always be sure to use the proper programming algorithm. "0" series PROMs will not program properly using
"A" -series algorithms. Always tie the Vpp pin to Vee in your application. Never leave Vpp floating.

June 1, 1996 (Version 1.0)

5-5

XC1700DFamiiy of Serial Configuration PROMs

XC1718D,XC1736D, XC1765D, XC17128D and XC17256D
Absolute Maximum Ratings
Symbol

Description

Units

Vee

Supply voltage relative to GND

-0.5 to+7.0

V

V pp

Supply voltage relative. to GND

-0.5 to + 12.5

V

V 1N

Input voltage relative to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to 3-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +125

°C

TSOL

Maximum soldering temperCiture (10 s @ 1/16 in.)

+260

°C

Note:

Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under
Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may
affect device reliability.

Operating Conditions
Symbol
Vee

Description

Min

Max

Units

Commercial

Supply voltage relative to GND O°C to +70°C junction

4.75

5.25

V

Industrial

Supply voltage relative to GND -40°C to +85°C junction

4.50

5.50

V

Military

Supply voltage relative to GND -55°C to +125°C case

4.50

5.50

V

DC Characteristics Over Operating Condition
Symbol

Description

Min

Max

Units

V 1H

High-level input voltage

2.0

Vee

V

V 1L

Low-level input voltage

0

0.8

V

V OH

High-level output voltage (lOH

Commercial

VOL

=-4 mAl
Low-level output voltage (IOL =+4 mAl
High-level output voltage (lOH = -4 mAl
Low-level output voltage (l0L =+4 mAl

VOH

High-level output voltage (IOH = -4 mAl

Military

VOL

Low-level output voltage (IOL = +4 mAl

0.4

V

ICCA

Supply current, active mode

10.0

mA

lees

Supply current, standby mode, XC17128D, XC17256D

50.0

IlA

1.5

mA

10.0

IlA

VOL
VOH

3.86
0.32

Industrial

3.76

Input or output leakage current

3.7

-10.0

V
V

0.37

Supply current, standby mode, XC1718D, XC1736D, XC1765D
IL

V

V
V

Note: During normal read operation V pp must be connected to Vcc

5-6

June 1, 1996 (Version 1.0)

~.XIUNX
XC1718L, XC1765L, XC17128L and XC17256L
Absolute Maximum Ratings
Description

Symbol

Units

Vee

Supply voltage relative to GND

-0.5 to +6.0

V

V pp

Supply voltage relative to GND

-0.5 to + 12.5

V

V 1N

Input voltage with respect to GND

-0.5 to Vee +0.5

V

VTS

Voltage applied to 3-state output

-0.5 to Vee +0.5

V

TSTG

Storage temperature (ambient)

-65 to +150

°C

TSOL

Maximum soldering temperature (10 s@ 1/16 in.)

+260

°C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating
Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device
reliability.

Operating Conditions
Symbol
Vee

Description
Commercial

Min

Max

Units

3.0

3.6

V

Supply voltage relative to GND O°C to +70°C junction

DC Characteristics Over Operating Condition
Symbol

Description

Min

Max

Units

V 1H

High-level input vQltage

2.0

Vee

V

V 1L

Low-level input voltage

0

0.8

V

VOH

High-level output voltage (IOH

VOL

=-4 mAl
Low-level output voltage (l0L =+4 mAl

leeA

Supply current, active mode.

Ices

Supply current, standby mode, XC1718L, XC1765L
Supply current, standby mode, XC17128L, XC17265L

IL

Input or output leakage current

2.4

-10.0

V
0.4

V

5.0

mA

1.5
50.0

mA
flA

10.0

flA

Note: During normal read operation V pp must be connected to Vec

June 1, 1996 (Version 1.0)

5-7

I

XC1700D Family of Serial Configuration PROMs

AC Characteristics Over Operating Condition
CE

\

\

.

®

TSCE

\

RESET/OE

I
I\

ClK

TLC --.

+-

®

TOE

+-CD

TCE

+-

CD
j

.....
DATA

I~
® ~@)
..... TSCE
T HCE .....

-+

@THC

®
TCAC

r-

.....

THOE-

@TCYC=t

V

\

@

0
TOH

K

)

r-

.-

I+-

@T DF

'-I;

.....

+-

0

ToH
X2634

Symbol

Description

XC1718D
XC1736D
XC1765D

XC1718L
XC1765L

Min
Max
Min
Max
OE
to
Data
Delay
45
45
TOE
CE to Data Delay
60
60
TCE
TCAC ' ClK to Data Delay
150
200
Data Hold From CE, OE, or ClK
0
0
TOH
CE or OE to Data Float Delay2
50
50
TOF
200
400
TcyC Clock Periods
ClK low Time 3
100
100
7 TlC
8 THC CLK High Time3
100
100
9 TSCE CE Setup Time to ClK (to guarantee
25
40
proper counting)
10 THCE CE Hold Time to ClK (to guarantee
0
0
proper counting)
11 THO E OE Hold Time (guarantees counters are 100
100
reset)
Notes: 1. AC test load = 50 pF
2. Float delays are measured with minimum tester ac load and maximum de load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V1l = 0.0 V and V1H = 3.0 V.

1
2
3
4
5
6

5-8

XC17128D
XC17256D

XC17128L
XC17256L

Min

Min

Max

25
45
50

Units

Max

30
60
60

80
20
20
20

100
25
25
25

ns
ns
ns
ns
ns
ns
ns
ns
ns

0

0

ns

20

25

ns

0

0
50

50

June 1, 1996 (Version 1.0)

~XILINX
AC Characteristics Over Operating Condition (continued)
7'-

RESET/OE

~
,..----,.

elK

7
@TCDF-"

i-

I
\

~t-

DATA

last Bit

@TOCK

.~

,f--

!--

-..

Jt@ToCE-

Symbol

Description

XC1718D
XC1736D
XC1765D
Min

12
13
14
15

TCDF
TOCK
TOCE
TOOE

ClK to Data Float Delay2
ClK to CEO Delay
CE to CEO Delay
RESET/OE to CEO Delay

7
.....

Max
50
65
45
40

-

i-@TOOE

,~

~

I

i-@ToCE
X3183

XC1718L
XC1765L
Min

First Bit

Max
50
65
45
40

XC17128D
XC17256D

XC17128L
XC17256L

Min

Min

Max
50
30
35
30

Units

Max
50
30
35
30

ns
ns
ns
ns

Notes: 1. AC testload '" 50 pF
2. Float delays are measured with minimum tester ae load and maximum de load.
3. Guaranteed by design, not tested.
4. All AC parameters are measured with V1l = 0.0 V and V1H '" 3.0 V.

June 1, 1996 (Version 1.0)

5-9

XC1700D·Family of Serial Configuration PROMs

Ordering Information

XC17360 - PC20 C

Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L

______-'I~ T<-______
Package Type
= 8-Pin Plastic DIP
= 8-Pin CerDIP
= 8-Pin Plastic Small-Ou!line Package
= 8-Pin Plastic Small-Outline Thin Package
= 20-Pin Plastic Leaded Chip Carrier

PD8
DD8
S08
V08
PC20

Operating Range/Processing
C =
I =
M =
B =

Commercial (0° to +70°C)
Industrial (-40° to +85°C)
Military (-55° to + 125°C)
Military (-55° to +125°C)
MIL-STD-883 Level B compliant

Valid Ordering Combinations
XC17128DPD8C
XC17128DV08C

XC1718DPD8C
XC1718DS08C

XC17256DPD8C
XC17256DV08C

XC17128DPC20C

XC1718DV08C

XC17128DPD81

XC1718DPC20C
XC1718DPD81

XC17256DPC20C
XC17256DPD81

XC17128DV081
XC17128DPC201
XC17128DDD8M

XC17256DV081

XC1718DS081
XC1718DV081

XC17256DPC201
XC17256DDD8M

XC1718DPC201

XC17256DDD8B

XC1736DPD8C
XC1736DS08C
XC1736DV08C
XC1736DPC20C

XC1765DPD8C
XC1765DS08C
XC1765DV08C
XC1765DPC20C

XC1736DPD81
XC1736DS081

XC1765DPD81

XC1736DV081
XC1736DPC201

XC1765DV081
XC1765DPC201
XC1765DDD8M

XC1736DDD8M

XC1765DS081

XC1765DDD8B
XC1718LPD8C

.'

XC17256LPD8C

XC1765LPD8C

XC1718LS08C
XC1718LV08C

XC17256LV08C
XC17256LPC20C

XC1765LS08C
XC1765LV08C

XC17128LPD81

XC1718LPC20C

XC17128LV081
XC17128LPC201

XC1718LPD81
XC1718LS081

XC17256LPD81
XC17256LV081

XC17128LPD8C
XC17128LV08C
XC17128LPC20C

XC1765LPC20C
XC1765LPD81
XC1765LS081

XC17256LPC201

XC1718LV081

XC1765LV081

XC1718LPC201

XC1765LPC201

Marking Information
Due to the small size of the serial PROM package, the complete ordering part number cannot be marked on the package.
The XC prefix is deleted and the package code is simplified. Device marking is as follows.

J

17360
Device Number
XC1718D
XC1718L
XC1736D
XC1765D
XC1765L
XC17128D
XC17128L
XC17256D
XC17256L

5-tO

_I

P

C

T,-----

Package Type
P
D
S
V

J

8-Pin Plastic DIP
8-Pin CerDIP
8-Pin Plastic Small-Outline Package
8-Pin Plastic Small-Outline Thin Package
20-Pin Plastic Leaded Chip Carrier

Operating Range/Processing
C
I
M
B

=
=
=
=

Commercial (0° to +70°C)
Industrial (-40° to +85°C)
Military (-55° to +125°C)
Military (-55° to + 125'C)
MIL-STD-883 Level B compliant

June 1, 1996 (Version 1.0)

3V Products

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

3V Products Table of Contents

3.3 V and Mixed Voltage Compatible Products
FPGAs ...........................................................................
The Zero+ Family of Ultra Low Power Devices: XC3000L, XC4000L .....................
3 V PCI-Compliant FPGA: XC3100L .............................................
High-Density FPGAs With On-Chip RAM: XC4000L and XC4000XL. ....................
High-Density FPGAs Without On-chip RAM: XC5200L ...............................
5 V Compatible Inputs on 3.3 V Devices ..........................................
5 V SRAM FPGAs for Mixed-Voltage Systems: XC4000E and XC4000EX ................
CPLDs ............................ '" ...... , .....................................
5 V CPLDs for Mixed-Voltage Systems: XC7300 and XC9500 .........................
Supply Voltage Options .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Interfacing Between 5 V and 3.3 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
3.3 V Devices Driving Inputs on 5 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
5 V Devices Driving Inputs on 3.3 V Devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC4000EJEX is Fully Compatible With 3.3 V Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . ..

6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-1
6-2
6-2
6-2
6-2
6-3
6-4

3.3 V and Mixed Voltage
Compatible Products
August

6, 1996 (Version 1.1)

In anticipation of the market shift from 5 V to 3.3 V products,
Xilinx introduced the Zero+ product line, the industry's first
3.3 V FPGAs, in 1993. The number of 3.3 V product offerings has since tripled and includes high-performance
devices with system clock speeds of 85 MHz, high-density
devices, and mixed-voltage devices.
Complete data sheets for the products mentioned below
can be found in Chapters 3, 4, and 5 of this Data Book.
3.3 V versions of the Serial PROM devices also are available (see Chapter 6).

FPGAs
The Zero+ Family of Ultra low Power
Devices: XC3000l, XC4000l
The Zero+ Product Line includes two major families: the
XC3000L and XC4000L FPGAs. These devices have quiescent supply currents below 1mA, with some below 50 ILA.
This is important in systems where prolonged battery life is
critical.

3 V PCI-Compliant FPGA: XC3100l
The XC3100L is the highest performance 3.3 V FPGA, and
is the only 3.3 V FPGA family that meets the stringent specifications of 3.3 V PCI applications.

High-Density FPGAs With On-Chip RAM:
XC4000l and XC4000Xl
Ranging from 5,000 to over 60,000 gates, the XC4000L
and XC4000XL FPGA families represent the broade.st 3.3 V
product line in the industry.

High-Density FPGAs Without On-chip RAM:
XC5200L

5 V Compatible Inputs on 3.3 V Devices
Conventional 3.3 V device inputs cannot or should not be
driven substantially higher than 3.6 V. The new XCS200L
inputs can, however, be driven up to 5.5 V, provided that the
5 V supply voltage is connected to one dedicated bias supply pin, called VTT, on the 3.3 V device.
All Xilinx device inputs maintain their .excellent protection
against Electro-Static Discharge (ESD), typically 10,000 V,
even in mixed-voltage applications.

5 V SRAM FPGAs for Mixed-Voltage
Systems: XC4000E and XC4000EX
While the market slowly shifts from 5V systems to 3.3V systems, a need exists for devices to function in dual environments. The 5 V XC4000E and XC4000EX FPGA families
feature a unique output structure which makes them suitable for mixed-voltage system· applications. When configured in TIL mode, the XC4000E and XC4000EX can be
directly mixed with 3.3 V devices without the aid of external
components such as current limiting resistors. This is
described in more detail under, "Interfacing Between 5 V
and 3.3 V Devices" on page 7-2.

CPLDs
5 V CPlDs for Mixed-Voltage Systems:
XC7300 and XC9500
Xilinx CPLDs are an excellent fit for·5 V only and mixedvoltage systems. The Input/Output (1/0) ring can be poweredbyeither a 5 V VCCIO or a 3.3 V Vcclo.lndependent of
the VCCIO voltage level, the inputs can accept 5 V and.3.3 V
inputs. The rail-to-rail output level is defined by VCCIO'
These single-chip·solutions function extremely well in
mixed-voltage systems without any performance penillty.

The XC5200L family features 5 V compatible inputs and
densities from 2,000 to 23,000 gates.

August 6, 1996 (Version 1.1)

6-1

I

3.3 V and Mixed Voltage Compatible Products

Supply Voltage Options
Mixed-Voltage Applications
CoreVCC = 5V VCC=5V VCC = 3.3V
Single Single
VOVCC=3.3V Inputs are Inputs are
5V
Dual Inputs are 5 V
3.3V
3.3V
5V
Availability Supply Supply Supply Compatible Compatible Compatible 1

Key Features

Yes

Reconfigurable
FPGAs
XC3000A

Now

XC3000L

Now

XC31 bOA

Now

XC3100L

Now

XC4000E

Now

XC4000L

Now

XC4000EX

2H96

XC4000XL

2H96

XC5200

Now

XC5200L

4H96

Low quiescent current

Yes

flA powerdown current and

Yes
Yes

Yes

Yes

Yes

/lA quiescent current
Highest performance 5 V FPGA
Highest performance 3.3 V FPGA

Yes

Mixed voltage system capable
High Density 3.3 V FPGAs

Yes
Note 2

Note 2

Yes

Yes

Highest Density 3.3 V FPGA
Best value and broadest density
FPGAs

Yes

Yes
Yes

Mixed voltage system capable

Yes

Yes
Yes

Best 3.3 V FPGA value

CPLDs
XC7300

Now

Yes

Yes

Yes

Yes

Mixed voltage system capable

XC9500

2H96

Yes

Yes

Yes

Yes

Mixed voltage system capable

Notes:

1. Provided VTT pin is connected to 5 V supply.
2. Initial XC4000XL devices do not have 5 V tolerant inputs. Future XC4000XL devices will have 5 V tolerant inputs. Contact the
factory.

Interfacing Between 5 V and 3.3 V Devices
This section discusses the compatibility issues between
devices with different supply voltages, and explains how 5 V
XC4000E/EX devices are directly compatible with 3.3 V
devices.
'
In the past, almost all digital logic devices used a 5 V supply
voltage. To reduce chip size and meet the demand for
higher integration and lower power consumption, the semiconductor industry has started the transition to 3.3 V logic.
In the future, 3.3 V will become the dominant sUpply voltage. Today, many designs must accommodate both types
of ICs on the same board. Since both types of supply share
a common ground, there are no problems interfacing logic
Low levels in either direction, but there are compatibility
issues for the logic High levels.

3.3 V Devices Driving Inputs on 5 V Devices
The lowest output High voltage (VOH) of the 3.3 V device must
exceed the VIH requirements of the 5 V device. This is not a
problem if the 5 V device uses TTL-compatible input thresholds,
available on all Xilinx devices. If, however, the 5 V device has
CMOS input thresholds, an external pull-up resistor to 5 V on
each such input will assure a sufficiently high input voltage. The
resistor should be somewhere between 10 kQ and 1 kQ in
value. The upper limit causes the riSing input transition to be
slow; the lower limit is set by the output current sinking capability of the 3.3 V device output. In the High state, the voltage will
be clamped by the ESD protection diode of the 3.3 V device, as

6-2

described later in this application note. With less than 1.5 V
across this resistor, the current will be fairly small, but care
should be taken that the sum of these pull-up currents does not
exceed the 3.3 V supply current, thereby reverse-biasing the
power supply and raising the 3.3 V supply voltage to an undefined .Ievel (but obviously lower than the 5 V Vee minus a diode
drop of -0.7 V).

5 V Devices Driving Inputs on 3.3 V Devices
The highest 5 V device output voltage must not force excessive current into the input of the 3.3 V device. If the 5 V device
has a truly complementary CMOS output (like all Xilinx
FPGAs and CPLDS except the' XC4000 family devices
have), then the input current must be limited bya series
resistor of no less than 150 Q.This guarantees an input current below 10 mA, flowing through the ESD input protection
diode backwards into the 3.3 V supply. That amount of input
current is generally considered safe, causing neither metal
migration nor latch-Up problems. Care must be taken to
avoid forcing the nominally 3.3 V supply voltage above its
3.6 V maximum whenever a large number of active High
inputs drive the 3.3 V device, potentially causing the 3.3 V
supply current to go negative.
If the 5 V device has "totem-pole" n-channel-only outputs,
VOH is reduced by one threshold and the series resistor
can be eliminated, provided the nominally 5 V supply does

August6, 1996 (Version 1.1)

~XIUNX

A worst-case analysis of the interface might assume the
(unrealistic) condition where the 5 V supply is at its max
value (5.25 V for commercial applications), while the
3.3 V supply is at its min value of 3.0 V. Under these
conditions, the interface violates the conventional specification, and drives current into the input of the 3.3 V
device, as shown in figure 2. The following paragraphs
explain that this interface is nevertheless reliable.
For protection against electro-static discharge (ESD), all
CMOS inputs and 1/0 pins usually have a diode between
the pin and the nearest Vee connection. This diode prevents the input from going substantially more positive than.
Vee, which might destroy the input transistor by rupturing
its gate oxide. At room temperature, this ESD protection
diode conducts negligible current at < 0.6 V forward bias,
and conducts -1 mA at -0.7 V forward bias, typical for any
silicon junction diode. These voltages have a predictable
negative temperature coefficient of -2 mV per degree C. At
85 degrees C, these voltages are, therefore 120 mV lower.
Figure 1 superimposes the output characteristic of the
XC4000E/EX and the input current characteristic of a typical 3.3 V device input. Both supply voltages are at their
nominal value, but the die temperatures are at their worstcase value of 85 degrees C, and worst-case processing is
assumed.
Figure 2 shows the same curves, but with 5.25 V and 3.0 V
Vee respectively. The intersection of the two curves defines
the worst-case operating point of 3.8 V and 6 mA. That

August 6, 1996 (Version 1.1)

Nominal
Supply Voltages

lOUT

85°C

8

7

6
5
4

3

____
4.0

____
4.5

____
5.0

Vee

~

______

3.3 3.5

~

__

3.0

~

2

~

If both 5 V and 3.3 V supply voltages track reasonably
between their max and min values, there will never be any
additional input current in excess of 1 ~ at any commercial
or industrial operating temperature.

9

~

At a nominal 5.0 V Vee, the unloaded output High voltage
VOH is <3.7 V. When applied to the input of a device with a
nominal 3.3 V Vee, there is no additional input current, and
the input level does not violate the conventional specification that prohibits input voltages more than 0.5 V above
Vee. See Figure 1.

rnA

10

~

As a default option, all XC4000E/EX have a TIL-like input
threshold (compatible with 3.3 V output levels) and an nchannel-only "totem-pole" or TTL-like output structure with
an n-channel transistor pulling the output to a VOH level
that is one threshold below Vee.

L

XC4000ElEX is Fully Compatible With 3.3 V
Logic

means that the XC4000E output drives 6 mA into the forward-biased ESD protection diode, raising the input voltage
0.8 V above 3.0 V, the assumed lowest value of the nominally 3.3 V supply voltage.

-

not exceed 5.25 V. This is described in detail in the following
section.

5.5
X59S9

Figure 1: XC4000E Output in "TTL-Mode" driving
3.3 V Device Input with Both Supplies at Nominal
Voltage (5.0 V and 3.3 V)

rnA

10
9
8
7

6
5
4

3
2

~~------~--~---------.5.0
.--~--I
3.0
3.5
4.0
4.5
5.5 vee
X5970

Figure 2: XC4000E Output in "TTL-Mode" driving
3.3 V Device Input with Both Supplies at Extreme
Values (5.25 V and 3.0 V)

6-3

I

3.3V and Mixed Voltage Compatible Products

Although this input condition is not covered by the conventional specification, it does not cause any harm and does
not affect reliability. ESD protection diodes are designed to
conduct hundreds of mA, and the absolute value of the
input voltage with respect to ground will. never exceed 3.9 V.
I! the input pin is part of an 1/0 structure, there is theoretically possibility of causing latch-up, but all reputable IC
manufacturers design their circuits such that latch-up does
not occur below 100 mA of input current per pin.
The system designer must estimate the sum of all maximum input currents, and calculate the impact of this current
flowing backwards towards the 3.3 V supply. But even if the
total 3.3 V supply current goes to zero, Vee for the 3.3 V
device is still limited to < 3.6 V (the highest output voltage of
the 5 V device minus the forward voltage drop of the ESD
diode).

Conclusion
5 V XC4000E/EX devices can be freely mixed with 3.3 V
devices, without any current or voltage limiting interface
resistors, if the following conditions are met:
•

•

•

The 5 V XC4000E/EX devices are in their default "TTL
mode" with respect to input thresholds and output
levels.
The upper limit on the 5 V Vee is 5.25 V and the lower
limit on the 3.3 V supply is 3.0 V, as per standard
commercial specifications.
For industrial operating conditions with higher Vcc max,
the user must make sure that the absolute difference
between the two supply voltages does not exceed 2.20 V.
Specifically, if the nominally 5 V Vee is at its max value of
5.50 V, the nominally 3.3 V Vee must not be lower than
3.30 V.

6-4

August6; 1996 (Version 1.1)

HardWire Products

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

HardWire Products Table of
Contents

Xilinx HardWire™ Array Overview
Features .........................................................................
Advantages of Using Xilinx HardWire Arrays .............................................
HardWire versus Full ASIC Gate Array Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Reverifying the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Fault Coverage and Test Vectors. . . . . . . . . . . . . . . . . . . . .. . . .. . . . . . . . . . . . . . . . . . .. . ..
Packaging and Silicon Considerations ..................................................
Support for the Enti re Product Life Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
The HardWire Product Series. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

7-1
7-1
7-1
7-2
7-2
7-3
7-3
7-3

Xilinx HardWire™ Array Overview
August 6, 1996 (Version 1.1)

Features
•

•

Mask-programmed versions of Xilinx programmable
devices
- Specifically designed for easy conversions
Significant cost reduction for high-volume
applications
Same specifications and architecture as the
programmable devices
- On-chip scan path test registers
High-performance CMOS process
Easy conversion with guaranteed results
"Design Once Methodology" requires no customer
engineering resources for conversion
Fully pin-for-pin compatible with the programmable
device
Support for most popular package types
PLD database file used to generate productionready prototypes
Automatic test vector generation with >95% fault
coverage
Prototypes built on production line

The following is an overview of the Xilinx HardWire device
product line. Product specifications for the HardWire
devices and additional information are available in a separate publication - The HardWire Data Book.
HardWire Arrays are mask-programmed versions of the
popular XC2000, XC3000, XC4000, and XC5000 series
FPGAs, as well as the XC9500 CPLDs. The HardWire
devices provide a transparent migration path from a programmable logic device to a cost-reduced device without
the engineering burden associated with conventional gatearray re-design.
In standard programmable logic, the functions and interconnections are determined by configuration data stored in
memory cells. In the HardWire components, the memory
cells and the logic they cOntrol are replaced by metal connections. All other circuitry in the HardWire devices is identical to the corresponding programmable logic's internal
circuitry. Thus, a HardWire device is a semicustom device
manufactured to provide a specific functionality, yet is completely compatible with the programmable device it
replaces.

August 6, 1996 (Version 1.1)

Advantages of Using Xilinx
HardWire Arrays
Xilinx offers an easy, seamless process for achieving the
shortest Time-to-Volume solution possible. Simply stated,
our unique Design Once methodology allows engineers to
develop their design in a programmable device, then switch
to a lower cost mask-programmed product without utilizing
additional internal resources.
Production is often started using the same programmable
logic in which the application was designed. This flexibility
allows the product to be introduced to the market quickly.
Later in the production process, the PLD can be replaced
with a HardWire Array without expending additional engineering time and effort to redesign either the FPGA's circuit
or the printed circuit board. Other conversion methodologies introduce risk at each project milestone of the conversion process. Only the Xilinx Design Once Methodology
can offer this no risk, 100% pin-for-pin compatible path to
dramatic cost reductions.
Whenever a system incorporating Xilinx PLDs ramps to
high production volumes, the HardWire mask-programmed
solution should be the first consideration for cost reduction.
Because the HardWire implementation dramatically
reduces the die size by removing programmable elements,
the resulting device is much smaller than the equivalent
PLD. This smaller die provides a no-risk path to achieve
dramatic cost reductions.

HardWire versus Full ASIC Gate Array
Implementation
Converting a device from programmable logic to a HardWire Array has many advantages over generic gate array
redesign. The most important is that the Xilinx HardWire
methodology requires no additional customer engineering
to convert the programmable logic design into a fully tested,
completely verified mask-programmed design.
This ease of conversion is available only through Xilinx
because the PLD database file is the actual physical data
base previously created and verified in the process of
developing the PLD design. Xilinx has the only methodology that preserves all attributes of the original physical data
base file. If the design is mapped to a third party library for
conversion at the schematic level to another technology,
the design must be verified and prototyped. Third party
implementation will change the placement and routing,
thereby changing the design's performance characteristics.

7-1

I

Xilinx HardWire™ Array Overview
Thus, the revised device needs to be re-verified and retested in the system to be certain both the functionality and
the performance still meet the application's requirements.

coverage. However, they often settle for significantly less
because the iterative process is extremely time consuming
and increases exponentially as fault coverage is increased.

A comparison of the activities required to convert a HardWire Array versus a standard array is shown in Figure 1.

Any third-party conversion from a Xilinx FPGA or CPLD to a
gate array or other similar technology will require test vector
generation. Typically, the original designers create the test
vectors, since they are most familiar with the design implementation. This method ties up valuable design resources
and reverses the value of the original decision to use programmable logic for their ease of design and time-to-market advantages. Another alternative is to contract with the
conversion or gate array vendor to create the test vectors.
This method can be both time-consuming and expensive,
since vendors usually charge by the vector. In some cases,
conversion or gate array vendors will accept a design without test vectors, but the customer accepts all the liability of
determining whether the resulting device is production worthy. In today's competitive market, many projects can not
afford the risk of possible respins if the design doesn't work.

Reverifying the Design
In conventional gate array conversion (redesign), the
design must be re-verified after the schematic is translated
or recaptured. The process of reverifying a design is rigorous and time-consuming. Functional simulation vectors
need to be created, and the device must be exhaustively
simulated before and after place and route. A suitable test
methodology must be considered and implemented.
In contrast, no additional effort is required when converting
to Xilinx HardWire Arrays. The HardWire design is self-verifying because the actual PLD database file is used for the
conversion.

Fault Coverage and Test Vectors
All designs need to be testable. In a traditional mask-programmed gate array, the designer is required to build in
testability and generate test vectors that verify chip performance by exercising as much of the device's circuitry as
possible. Most designers strive for greater than 95% fault

Converting from a Xilinx programmable to a HardWire
device requires no test vector generation. Xilinx guarantees
greater than 95% fault coverage through a proprietary
Automatic Test Vector Generation methodology. All HardWire Arrays are 100% fully guaranteed to work in the user's
application exactly like the programmable logic.

------ ----Working Xilinx FPGA Design

Generic Gate Array

• Convert netlist to G/A format
·,Logic changes for design compatibility
• Logic changes for pin compatibility
• Logic changes for configuration emulation
• Logic changes for Boundary Scan
• Design Check
• Functional Simulation
• Place and Route
• Back-Annotation
• Timing simulation and new models

Xilinx HardWire Array
• Design Check

• Design Conversion

• Custom Mask

• Test Vector generation
• Create 2~4 custom masks
X5945

Figure 1: Steps Involved in Converting a PLD Design to a Gate Array as Compared to a Hard Wire Array

7-2

August 6, 1996 (Version 1.1)

~XILINX
Packaging and Silicon
Considerations
All of the physical attributes of the HardWire Arrays are virtually identical to the programmable logic devices. Xilinx
uses the same qualified fabrication facilities for both the
PLD and HardWire devices. The same IC process, as well
as packaging, assembly, and test facilities, are used. This
allows users to circumvent costly and time-consuming
requalification efforts.
Converting from a Xilinx programmable logic device to anything but a Xilinx HardWire Array means a change to silicon, packaging, assembly and test. Each of these changes
adds an element of risk into the qualification process.

Support for the Entire Product Life Cycle
Figure 2 shows the typical life cycle of a high-volume product, and illustrates the optimal way for using the programmable and HardWire devices.
During the development, prototype, and initial production
stages, the programmable device is the best choice. Later
in the life-cycle, when the design is stable and in high volume production, the HardWire Array can be used in place
of the original programmable device.
Since the circuit board was designed initially for a programmable device, production can be switched back from the
HardWire Array to the programmable device if the situation
warrants. For example, if demand for the product increases
dramatically, production can be increased in days or weeks

by using programmable devices. In addition, a change can
be quickly made to the product, since there is no manufacturing lead-time for an off-the-shelf programmable device.
Production can be switched to programmable devices as
the product nears the end of the life cycle, avoiding end-oflife buys and the risk of obsolescence.
Furthermore, designs implemented with multiple static
RAM-based FPGAs can be cost reduced incrementally,
converting one or more of the programmable devices while
leaving the others for future conversion. As each PLD is
converted to a Xilinx HardWire Array, the user enjoys a
lower cost for that unit, while maintaining the ease-of-use of
off-the-shelf programmable logic in the other sockets.
When all of the devices are converted, the storage element
can then be removed, giving even further cost reductions.
This flexibility is unique to Xilinx, and allows OEMs to
achieve cost reductions quickly with minimal effort.

The HardWire Product Series
As listed in Table 1, the HardWire product chart, there is a
range of products available for Xilinx FPGAs and XC9500
CPLDs. For designs developed using the Xilinx XC4000
family, there are two HardWire options. The XC4400 family
is based on Xilinx advanced technology. It is most beneficial for higher volume applications, as well as XC4000E
designs utilizing Xilinx's Select-RAMTM features, and low
power 3.3 volt designs. For an application with low annual
volumes (as low as 1500 units) and where a low NRE is
required, the XC4300 family provides the best fit. Xilinx also
supports the low-power3.3 volt XC2000L and XC3000L.

Programmable Logic Volume
HardWire Array Volume

Unplanned Upside
Production
Ramp-Up

v

o
L
U
M

E

HardWire
Array

X5946

Figure 2: Typical High Volume Product Life Cycle

August 6, 1996 (Version 1.1)

7-3

I

Xilinx HardWire™ Array Overview

Table 1: HardWire ProductChart1
PLD Family

HIW Equivalent

XC2000

XC2300
XC3330

XC3000/A
XC3100A
XC3195

XC4000/E 2

XC3342
XC3390

2

XC4305
XC431 0

6
4
1,5

2
1
0.4

XC4313

1,5

0.4

XC4403/H
XC4405/H

10

2
2

Notes:

7-4

Now

5

1
1

XC4413
XC4425

5
3,5
2,5

1
0,5
0,5

XH4028EX

2,5

0,5

04/96

XH4036EX

2,5

0,5

04/96

XH4044EX

0.5
0,5
0,5

01/97

XH4062EX

2.5
2,5
2,5

XC5402
XC5404

10
10

2

XC5406

5

1

XC541 0
XC5415

5
3,5

1
0,5

XC95144

10

10

XC95180

10

XC95216

10

10
10

XC95288

10

10

XH4052EX

XC9500

10

Production
Availability

5

XC441 0

XC5200

6
4

Minimum
Shipment (KU)
2
2
1
0,5

10

Xc:4495T
XC4303

XC4406
"XC4408

XC4000EX

Minimum Order
Quantity (KU)
7
10

01/97
01/97

2
Now

02/97

1, Industrial temperature grades are available for all products,
2, The XC4300 supports the XC4000 design features, The XC4400 supports both the XC4000 and XC4000E design features,

August 6, 1996 (Version 1,1)

Military Products

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

Military Products Table of Contents

High-Reliability and Military Products
Unmatched Hi-Rei Product Offering .................................................... 8-1
Committed to the Hi-Rei Market ....................................................... 8-1
Xilinx Hi-Rei Products ............................................................... 8-1

---------~--~---

---

High.;Reliability and Military
Products
June 1, 1996 (Version 1.0)
Xilinx is the world's leading supplier of High-Reliability Programmable Logic Devices (Hi-REL PLDs) to the aerospace, military, defense electronics, and related markets.
These devices are' being used in a wide variety of programs, including applications suCh as electronic warfare,
missile guidance anq targeting, RADAR/SONAR, communications, signal processing, aerospace and avionics.

Unmatched Hi-Rei Product Offering
Xilinx offers a, wide variety of devices, delivering the fastest
and biggest Hi-Rei deVices available. Products with up fo
25,000 gates are available today, with even higher densities
to corne. Xilinx offers multiple product families to allow you
to select the righl device to meetyour design requirements.
This broad range of devices is available in a wide variety of
speed and package Qptions. Both military temperature
rangear:ld fuIlI\llIL"STD-883B/SMD versions are available
as standard. Qff-the-shelf products. in through-hole and
'
surface meuntpackages.

Committed to the Hi-Rei Market,
Xilinx understands that you' need, to be able to' cOunt, on
your Hi-Rel'supplier. Xilinx is committed to our customers,
and we are expanding our Hi-Rei support and product portfolio. The unique caplj.bilities of the Xilinx FPGA solution
provide increased design ,flexibility, field-upgradability and
system feature integratiOn, while eliminating the NREs,
lead-time and inventory problems of custom logic and gate
arrays. Now more than ever, Xilinx is your Hi-Rei logic solution.,'
" ,,'
,

Xilinx Hi'!'RetProducts
Table J summarizes)JC

8 JC is measured in a 3M Flourinert (FC:40) isothermal circulating fluid stabilized at 25°C. The Device Under Test
(DUT) is completely immersed in the fluid and initial stable
conditions are recorded. Pd is then applied. Case temperature (T is measured at the primary heat-flow path of the
particular package, Junction temperature (TJ) is calculated
from the diode forward-voltage drop from the initial stable
condition before power was applied.

c>

8 JC

= (TJ - Tcl/Pd

The junction-to-isothermal-1Iuid measurement (8JI)is also
calculated from the same data.

August 6, 1996 (Version 1.2)

,~XILINX
The latter data is considered as the ideal 8JA data for the
package that can be obtained with the most efficient heat
removal scheme. Other schemes such as airflow, heatsinks, use of copper clad board, or some combinati(m of all
these will tend towards this ideal figure. Since this is not a
widely used parameter in the industry, and' it Is not very
realistic for normal application of Xilinx packages, the 8 J1
data is not published. The thermal lab keeps such data for
package comparisons.

JunctiOri-to-Ambient Measurement -

8JA

8JA is measured on FR4 based PC boards measuring 4.5"
x 6.0",x .0625" (114.3mm x 152.4mm x 1.6mm) with edge
connectors., There are two main board types.

Type I, 2UOP board, is single layer with 2 signal planes
(one on each surface) and no internal Power/GND planes.
The trace density on this board is less than 10% per side.
Type II, the 4U2P board, has 2 internal copper planes (one
power, one ground) and 2 signal trace layers on both surfaces.
Data may be taken with the package'mounted in a socket or
witli the package mounted directly on the board. Socket
measurements typically use the 2UOP boards. SMT
devices may use either board. Published data always
reflects the board and mount conditions used.
Data is, taken at the prevailing temperature and pressure
conditions (22°C to 25°C ambient). The board with the DUT
is mounted in a cylindrical enclosure. The power application
and signal monitoring are the same as 8 J C measurements.
The enclosure (ambient) thermocouple is substituted for
the fluid thermocouple and two extra thermocouples
brought irito monitor room and board temperatures. The

August. 6,1996 (Version 1.2)

junction to ambient thermal resistance is calculated as follows: '
8JA

= (TJ - TA)/Pd

, The setup described herein lends itself to the application of
various airflow velocities from 0 - 800 Linear Feet per
Minute (LFM), i.e., 0 - 4:06 m/s. Since the board selection
(copper trace density, absence or presence of ground
planes, etc.) affects the rl;lsults of the thermal resistance,
the data from these tests shall always be qualified with the
board mounting information.

Data Acquisition and Package Thermal
Database
Xilinx gathers data for a package type in die sizes, power
levels and cooling modes (air flow and sometimes heatsink
effects) with a Data Acquisition and Control system (PAS).
The DAS controls the power supplies and other ancillary
equipment for hands-free data taking. Different setups
,."within the PAS software are used to run calibration, 8JA,
8JC, fan tests, as well as the power effect characteristi9s of
a package.
A package is characterize,d with respect to the major variables that influence the thermal resistance. The results are
,', stored in a database. Thermal resistance data is interpolated as typical values forthe individual Xilinx devices that
are assembled in the characterized package. Table 1
shows the 'typical values for different packages. Specific
device data may not be the same as the typical data. However, the data will fall within the given minimum and maximum ranges, The more widely used packages will have a
wider range. CustC/mers may contact the Xilinx application
group for specific device, data.

10·07

I

Packages and Thermal Characteristics

Table 2: Summary of Thermal Resistance for Packages
PKG·CODE

BG225
CB100
CB164
CB196
CB228
CQ100
008
HQ208
HQ240
HQ304
MQ208
MQ240
PC20
PC44
PC68
PC84
P048
P08
PG120
PG132
PG144
PG156
PG175
PG191
PG223
PG299
PG411
PG68
PG84
PP132
PP175
PQ100
PQ160
PQ208
PQ240
PQ44
S08
TQ100
TQ144
TQ176
V08
VQ100
VQ44
VQ64

10-8

8 JA at 07

8 JA at 07

8JA at 07

8 JA at 2506

(Max)
°C/Watt
37
44

(Typ)

(Min)

(Typ)

°C/Watt
30
41

°C/Watt
24

°C/Watt
19

38
25
24
17
44
97
14
12
10
17
16

25
17
15
11
37
90
10
9
7
14
12

76
42
38
28
43
73
25
24
23
21

63
35
31
25
33
60
19
20
17
15
14
15
15
10
9
26
24
23
19
29
24
23
17
40
112

29
25
19
46
114
15
13
11
18
17
86
51
46
41
43
82
32
32
26
25
25
24
24
18
16
39
37
35
29
35
37
35
28
52
147
37
35
29
162
47
44
44

26
24
18
45
109
14
12
11
18
17
84
46
42
33
43
79
27
28
25
23
23
21
20
17
15
37
34
34
29
33
32
32
23
51
147
31
32
28
162
38
44
41

20
18
18
16
14
34
31
33
28
32
22
26
19
51
147
31
30
27
162
32
44
39

8 JA at 5006 8 JA at 7506

(Typ)
°C/Watt
17
19
12
11
8
30
73
8
7

8 JC

(Typ)

(Typ)

°C/Watt
16
17

°C/Watt
3.3
5.1
3.6
1.8
1.3
7.1
8.2
1.7
1.5
0.9
1.2

11
10
7
25
60
7

5
13
11

6
5
12
10

56
31
28
21
29
54
15
17
14
11
11
12
12
9
8
20
18
18
15
28
21
21
15

53
29
26
17
27
50
13
15
13
10
10
11
11
8
7
17
16
17
13
27
20
19
14

26
25
21
123

36
105
24
21
18
116

35
98
23
20
17
108

32
36
34

30
34
32

29
33
31

1.2
25.8
13.7
9.3
5.3
11.6
22.2
3.6
2.8
3.7
2.6
2.6
1.5
1.5
1.9
1.2
7.8
5.8
6.0
2.5
5.5
4.6
4.3
2.8
12.4
48.3
7.5
5.3
5.3
48.3
9.0
8.2
8.2

Comments

Various
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
4U2P-SMT
4U2P-SMT
4U2P-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Socketed
Estimated
Socketed
Socketed
Socketed
Socketed
4U2P-SMT
2UOP-SMT
2UOP-SMT
2UOP-SMT
4U2P-SMT
IEEE-(Ref}
4U2P-SMT
4U2P-SMT
4U2P-SMT
Estimated
4U2P-SMT
4U2P-SMT
4U2P-SMT

August 6, 1996 (Version 1.2)

~XILINX
Table 2: Summary of Thermal Resistance for Packages (Continued)
PKG-CODE

WB144
WB225
WC44
WC68
WC84

8JA at 07
(Max)

8JA at 07
(Typ)

8 JA at 07
(Min)

°ClWatt.
28

°ClWatt.
28
28
46
43
41

°ClWatt

°ClWatt

°ClWatt

°ClWatt

28

-

-

-

28
47
46
43

8JA at 2506 8JA at 5006 8JA at 7506
(Typ)
(Typ)
(Typ)

2&
45
40

38
" 31

38

29

-

~

31
26
24

Comments

-

8JC
(Typ)
°ClWatt
6.0
6.0

25
.23
21

9.1
7.0
3.9,

Socketed
Socketed
Socketed

2UOP-SMT
2UOP-SMT

.'

Notes: 1. Maximum, typical and minimum numbers are based on numbers for all the devices in the specific package at the time, of
compilation. The numbers do not necessarily reflect the absolute limits of that packages. Specific device data should lie
within the limits. Packages used for a broader spectrum of devices have a wider range in the table. Specific device data ina
package may be obtained from the factory.
2. Package configuratiOns and drawings are in the package section of the data book.
3. 2UOP - SMT: the data is from a s.urface mount type I board -- no internal planes on the .board .•
4. 4U2P - SMT: the data is from a 4 layer SMT board incorporating 2 internal planes. Socketed data is taken in socket.
5. Thermal data is in degree Celsius/watt.
6. Airflow is reported in Linear Feet per minute (LFM).
7. Columns 1,2 and 3 are for 8 JA in still air.
.

Application of Thermal Resistance Data .
Thermal'resistance data gauges the IC package thermal
performance. 8 JC measures the internal package resistance to heat conduction from the die surface, through the
die mount material to the package exterior. 8 JC strongly
depends on the package's heat conductivity, architecture
and geometrical considerations.
8 JA measures the total package thermal resistance including 8JC' 8JA depends on the package material properties
and such external conditions as convective efficiency and
board mount conditions. For example, a package mounted
on a socket may have a 8 JA value 20% higher than the
same package mounted on a 4 layer board with power and
ground planes.
By specifying a few constraints, devices are ensured to
operate within the intended temperature range. This also
ensures device reliability and functionality. The system
ambient temperature needs to be specified. A maximum TJ

August 6, 1996 (Version 1.2)

also needs to be established for the system. The following
inequality will hold.
.
'TJ(max»

8 JA* Pd +TA

The following two examples illustrates the use of this inequality.

Example 1:
The manufacturer's goal is TJ (max) < 100°C
A module is designed for a TA = 45°C max.
A XC3042 in a PLCC 84 has a 8JA= 32°C/watt..
Given a XC3042 with a logic design with a rated power
Pd of O.75watt..
With this information, the maXimum die temperature
can be calculated as:
TJ

= 45 + (32 x .75) ==>

6goC.

The system manufacturer's goal of TJ < 100°C is met.

I

Pa~kage!i and Thermal Characteristics

Example 2:

power of 2.50 watts. The module manufacturers goal is
TJ(max.)< 100°C.
Table 3 sho~s the package and thermal enhancement
combinations required ,to meet the goal ofTJ < 100°C.

A module has a TA = 55°C max.
The Xilinx XC4013E is in aPq240 package (HQ240 is
also considered),
,
,
A XC4013E, in an example logic design,has a rated

Table 3: Thermal Resistance for XC4013E in PQ240 and HQ240 Packages

DevName
XC4013E
XC4013E

Package
PQ240
HQ240

9JA
still air
23.7
12.5

9JA
(250 LFM)
17.5
K6

9JA
9JA
9JC
(500 LFM) (750 LFM)
14.3
2.7
15.4
6.9
6.2
1.5

Comments
Cu, SMT2UOP
4 Layer .Board data

Possible Solutions to meet the module requirements of 100°C:
1a.

Using the standard PQ240;

1b.
2a.
2b.

Usin~ standard PQ240 with 250LFM forced air

T J = 55 + (23.7 x 2.50) ::=> 114.25 °C.
TJ = 55 + (17.5 x 2.50) ==> 98.75 °C

Using standard HQ240
Using HQ240 with 250 LFM forced air

TJ = 55 + (12.5 x 2.50) ==> 86.25 °C
TJ = 55 + (8.6 x 2.50) ==> 76.5 °C

For all solutions, the junction temperature is calculated as:
T J = Power x 9JA + TA
All solutions meet the module requirement of less than
100°C, with the exception of the PQ240 package in still air.

In general, depending on ambient and board temperatures
conditions, and' most importantly the total power dissipation, thermal enhancements -- such as forced air cooling,
heat sinking, etc. may be necessary to meet the TJ(max)
conditions set.

August 6, 1996 (Version 1.2)

~XIUNX
PQ/HQ Thermal Data Comparison

HQ/PQ Thermal Data
Size effect on 8JA

35

30

25

%
~

-e-

HQ208
-e-HQ240

20

E«
....,

(!J

--iii-

15
[3

B

HQ304

B

B

-till-

El

PQ208

10

-till-

PQ240
5
200

300

400

500

600

700

Die size (mils)

August 6,. 1996 (Version 1.2)

10-11

Packages and Thermal Characteristics

BGA Thermal Resistance
Effect of Air Flow on 0JA
40

35

30

i?
Cll

~...,«
CD

25

20

"~

~~r-----

-

~
~~
~'""'!r------.

-,

15

10

o

200

- - XC4010E-BG225 (2L)
--!EI-

XC73108-BG225(2L)

400
Air Flow - LFM

600

800

-e- XC73144-BG225(4L)

-II- XC4013E-BG225(4L)

- - XC5210-BG225(2L)

PG299 Thermal Resistance
Effects of Active & Passive Heat sinks
20 ,--------,--------,--------,--------,--------,--------,

15

5

o

A

BCD

E

F

PG299 - Various Enhancements
A

Standard Pkg

B Pkg+Finned HS (Passive)
C Pkg+Active Fan (V=O)

10-12

D Pkg+Active Fan (V=12)
E Std Pkg +250LFM
F Pkg+Finned HS+ 250LFM

August 6, 1996 (Version 1.2)

~XILINX

PGA 299 Thermal Resistance
Effect of Air Flow on 0JA
25

,

20
[

~
......
~~
..............

~

~~

~ ........
~

5

~

~~
-~

a
a

100

200

400

300

500

600

700

Air Flow - LFM
-

PG191-XC4010E

...,... PG299-XC4025E

-

PG223-XC4013E

-fB-

PG299-FHS(XC4025E)

I

August 6, 1996 (Version 1.2)

10-13

Packages and Thermal Characteristics

Some Power Management Options
FPGA devices are usually not the dominating power consumers in a system, and do not have a big impact on power
supply designs. There are obvious exceptions. When the
actual or estimated power dissipation appears to be more
than the specification of the chosen package, some options
can be considered. Details on the engineering designs and
analysis of some of these suggested considerations may
be obtained from the references listed at the end of the section. The options include:
o

o

o

o

o

A Xilinx low power (L) version of the circuit in the same
package. With the product and speed grade of choice,
up to a 40% power reduction can be anticipated. For
more information, contact the Xilinx Hotline group.
Explore thermally enhanced package options available
for the same device. As illustrated above, the HQ240
package has a thermal impedance of about 50% of the
equivalent PQ240. Besides, the 240 lead, the 208 lead
and the 304 lead Quad packages have equivalent
heatsink enhanced versions. Typically 25% to 40%
improvement in thermal performance can be expected
from these heatsink enhanced packages. Most of the
high gate count devices above the XC4013 level come
either exclusively in heat enhanced packages or have
these packages as options. If the use of a standard PQ
appears to be a handicap in this respect, a move to the
equivalent HQ package if available may resolve the
issue. The heat enhanced packages are pin to pin
compatible and they use the same board layout.
The use of forced air is an effective way to improve
thermal performance. As seen on the graphs and the
calculations above, forced air (200 -- 300 LFM) can
reduce junction to ambient thermal resistance by 30%.
If space will allow, the use of finned external heatsinks
can be effective. If implemented with forced air as well,
the benefit can be a 40% to 50% reduction. The HQ304,
all cavity down PGAs, and the BG352 with exposed
heatsink lend themselves to the application of external
heatsinks for further heat removal efficiency.
Outside the package itself, the board on which the
package sits can have a significant impact. Board
designs may be implemented to take advantage of this.

10-14

Heat flows to the outside of a board mounted package
and is sunk into the board to radiate. The effect of the
board will, be dependent on the size and how it
conducts heat. Board size, the level of copper traces on
it, the number of buried copper planes all lower the
junction-to-ambient thermal resistance for a package.
Some of the heatsink packages with the exposed
heatsink on the board side can be glued to the board
with thermal compound toenhance heat removal.

References
Forced Air Cooling Application Engineering
COMAIRROTRON
2675 Custom House Court
San Ysidro, CA 92173
1-619-661-6688
Heatsink Application Engineering
The following facilities provide heatsink solutions for industry standard packages.
AAVID Thermal Technologies
1 Kool Path
Box 400
Laconia, NH 03247-0400
1-603-528-3400
Thermalloy, Inc.
2021 W. Valley View Lane
Box 810839
Dallas, TX 75381-0839
1-214-243-4321
Wakefield Engineering, Inc.
60 Audubon Road
Wakefield MA 01880-1255
1-617-245-5900
Xilinx does not endorse these vendors nor their products.
They are listed here for reference only. Any materials or
services received from the vendors should be evaluated for
compatibility with Xilinx components.

August 6, 1996 (Version 1.2)

~XILINX
Component Mass (Weight) by Package Type
JEDEC Outline #
MO-151-CAL
MO-151-BAR
MO-151-BAU
MO-113
MO-113
MO-113-AA
MO-113-AA
MO-113-AB
MO-113

Xilinx#

Package
BG225

Description
MOLDED BGA 27mm- ANAM

BG352

SUPERBGA - 35X35MM AMKOR

BG432

SUPERBGA - 40X40MM AMKOR

CB100

NCTB TOP BRAZE 3K VER

CB100

NCTB TOP BRAZE 4K VER

CB164
CB164

NCTB TOP BRAZE 3K VER
NCTB TOP BRAZE 4K VER

CB196

NCTB TOP BRAZE 4K VER

CB228

NCTB TOP BRAZE 4K VER

CC20

CERAMIC LEADED CHIP CARRIER

N/A

OCQ0011

008

.300 CERDIP PACKAGE

MO-036-AA

OBGOO01
OBGOO08
OBGOOOfj
OCQOO08
OCQOO06
OCQOO03
OCQOO07
OCQOO05
OCQ0012

Mass (g)
2.2
7.1
9.1
10.8
10.8
11 ..5
11.5
15.3
17.6
8.4
1.1
10.8
15.0
26.2
6.1
8.0

HQ208

METRIC 28 X 28 - HIS DIE UP

MO-143-FA1

OPDOO05
OPQ0020

HQ240

METRIC QFP 32 32 - HIS DIE UP

MO-143-GA

OPQ0019

HQ304

METRIC QFP 40 40-H/S DIE DOWN

MO-143-JA

OPQ0014

MQ208

METAL QUAD EIAJ

MQ240
PC20

METAL QUAD
PLCC JEDEC MO-047

N/A
N/A

OPQOO06
OPQ0011

MO-047-AA

OPCOO06

PC28

PLCC JEDEC MO-047

MO-047-AB

OPCOO01

0.8
1.1

PC44

PLCC JEDEC MO-047

MO-047-AC

PC68
PC84

PLCC JEDEC MO-047

MO-047-AE

OPCOO05
OPCOO01

4.8

MO-047-AF

OPCOO01

6.8

PD48

DIP .600

N/A

OPDOO01

7.9

PLCC JEDEC MO-047

..

1.2

PD8

DIP .300 STANDARD

MO-001-AA

OPDOO02

0.5

PG120

CERAMIC PGA 13 X 13 MATRIX

MO-067-AE

OPG0012

11.5

PG132
PG144

CERAMIC PGA 14 X 14 MATRIX
CERAMIC PGA 15 X15 CAVITY UP

MO-067-AF
MO-067-AG

OPGOO04
OPG0017

11.8
16.9

PG156

CERAMIC PGA 16 X 16 MATRIX

MO-067-AH

OPGOO07

17.1

PG175

CERAMIC PGA 16X16 STD VER.

MO-067-AH

OPGOO09

17.7

PG184

CERAMIC PGA 15 X15 CAVITY UP

MO-067-AG

OPG0019

17.5

PG191

CERAMIC PGA 18 X 18 STD - ALL
CERAMIC PGA 18 X 18 TYPE

OPGOO08
OPG0016

21.8

PG223

MO-067-AK
MO-067-AK

PG299

CERAMIC PGA 20 X 20 HEATSINK

OPG0022

37.5

PG299
PG411

CERAMIC PGA 20 X 20 TYPE

MO-067-AK
MO-067-AM

CERAMIC PGA 39 X 39 STAGGER

MO-128-AM

OPG0015
OPG0019

29.8
36.7

PG68
PG84

CERAMIC PGA CAV UP 11X11
CERAMIC PGA CAV UP 11X11

MO-067-AC
MO-067-AC

OPGOO02
OPGOO03

7.0
7.2
8.1

26.0

PP132

PLASTIC PGA 14 X 14 MATRIX

MO-83-AF

OPGOO01

PP175

PLASTIC PGA 16X16 BURRI ED

MO-83-AH

EIAJ 14X20 QFP - 1.60

MO-108-CC1

OPGOO06
OPQ0013

11.1

PQ100
PQ160
PQ208

EIAJ 28X28 .65MM 1.60
EIAJ 28X28 .5MM 1.30

MO-108-DD1
MO-143-FAI

OPQOO02
OPQOO03

PQ240

EIAJ 32 X 32 .5MM

MO-143-GA

OPQ0010

5.8
5.3
7.1

PQ44

EIAJ 10 X 10 X 2.0

MO-108-AA2

OPQ0015

0.5

S08

VERSION 1 - .150/55MIL

MO-150

OPDOO06

TQ100

THIN QFP 1.4mm thick

MS-026-BDE

OPQOO04

0.1
0.7

1.6

~

August 6, 1996 (Version 1.2)

10-15

I

Packages and Thermal Characteristics

Component Mass (Weight) by Package Type (Continued)
Package
T0144
T01?6
V08
V0100
V044
V064
WC44
WC68
WC84
Notes:

10-16

Description
THINOFP 1.4mm thick
THIN OFP 1.4mm thick
THIN SOIC-1I
THIN OFP 1.0 thick
EIAJ 10 X 10 X 1.0
THIN OFP 1.0 thick
JEDEC WINDOWED COUAD
WINDOWED CEROUAD
WINDOWED CEROUAD

JEDEC Outline #
MS-026-BFB
MS-026-BGA
N/A
MS-026-AED
MS-026-ACB
MS-026-ACD
MO-08?
MO-08?
MO-08?

Xilinx #
OPOOOO?
OPOOO08
OPDOOO?
OPOO012
OPOO01?
OPOOO09
OCOOO04
OCOOO09
OCOO010

Mass (g)
1.4
0.9
0.1
0.6
0.4
0.5
2.9
?3
11.0

1. Data represents. average values for typical packages with typical devices. The accuracy is between 7% to 10%.
2. More preCise numbers (below 5% accuracy) for specific devices may be obtained from Xilinx through a factory
representative or by calling the Xilinx Hotline.

August 6, 1996 (Version 1.2)

~XILINX
Xilinx Thermally Enhanced Packaging
The Package Offering
Heatsink
Location

Xilinx Code

Body (mm)

THK(mm)

Mass (gm)

JEDEC No.

Xilinx No.

H0304

40x40

3.80

26.2

H0240

32x32

15.0

TOP
DOWN

MO-143-GA

OPOOO19

H0208

28x28

3.40
3.37

MO-143-JA

OPOOO14

10.0

DOWN

MO-143-FA

OPOO020

Overview

Mass Comparison

Xilinx offers thermally enhanced quad flat pack packages
on certain devices. This section discusses the performance
and usage of these packages (designated HO). In summary:

Because of the copper heatsink, the HO series of packages
are about twice as heavy as the equivalent PO. Here is a
quick comparison.

•
•
•
•

The HO-series and the regular PO packages conform
to the same JEDEC drawings.
The HO and PO packages use the same PCB land
patterns.
The HO packages have more mass
Thermal performance is better for the HO packages

Where and When Offered
-

-

-

HO packages are offered as the thermally enhanced
equivalents of PO packages. They are used for high
gate count or high 1/0 count devices in packages,
where heat dissipation without the enhancement
may be a handicap for device performance. Such
devices includeXC4013E, XC4020E, XC4025E, and
XC5215.
They are also being used in place of MOUAD (MO)
packages of the same lead count for new devices.
The HO series at the 240 pin count level or below
are offered with the heatsink at the bottom of the
package. This was done to ensure pin to pin
compatibility with the existing PO and MO packages.
At the 304 pin count level, the HO is offered with the
heatsink up. This arrangement offers a better potential
for further thermal enhancement by the designer.
A

Die UplHeatsink Down

Jfi.~
B Die DownlHeatsink Up

~~
A - Heatsink down orientation
B - Heatsink up orientation

PQ (gm)

MQ (gm)

208 Pin

5.3

6.1

10.0

240 Pin

7.1

8.0

15.0

304 Pin

N/A

N/A

26.2

Thermal Data for the HQ
The data for individual devices may be obtained from Xilinx.
Still Air Data Comparison
HQ
MQ
PQ
8JA COClWatt) 8 JA re/watt) 8 JA eC/watt)
208 Pin

10-14

17-19

240 Pin

1H4
10-12

15-17

25-32
18-28

N/A

N/A

304 Pin
Note:

8 JC is typically between 1 and 2 °C/Watt for HO
and MO Packages. For PO's, it is between 2 and 7
°C/Watt.

Data Comparison at Airflow - 250 LFM
HQ
MQ
PQ
8 JA (OC/watt) 8JA(OC/watt) 8JA (OC/watt)
208 Pin

9-10

14-15

240 Pin

8-9

304 Pin

6.5-8

11-13
N/A

19-25
14-20
N/A

Other Information
-

-

August 6, 1996 (Version 1.2)

HQ (gm)

Leadframe: Copper EFTEC-64 or C7025
Heat Slug: Copper - Nickel plated ..... Heatsink metal
is Grounded
Lead Finish 85/15 Sn/Pb 300 microinches minimum
D/A material- Same as PO; Epoxy 84-1LMISR4
Mold Cpd. Same as PO - EME7304LC
Packed in the same JEDEC trays

10-17

I

Packages and Thermal Characteristics

Moisture Sensitivity of PSMCs
Moisture Induced Cracking During Solder
Reflow
The surface mount refloW processing step subjects the
Plastic Surface Mount Cornponents (PSMC) to high thermal exposure and chemicals from solder fluxes and cleaning fluids during user's board mount assembly. The plastic
mold compounds used for device encapsulati"on are, universally, hygroscopic and absorb moisture at a level determined by storage environment and other factors.
Entrapped· moisture can vaporize during rapid heating in
the solder reflow process generating internal hydrostatic
pressure. Additional stress is added due to thermal mismatch, and the Thermal Coefficient of Expansion (TCE) of
plastic, metal lead' frame, and silicon die. The resultant
pressure may be sufficient to cause delamination within the
package, or worse, an internal or external crack in the plastic package. Cracks in the plastic package can allow high
moisture penetration, inducing transport of ionic contaminants to the die surface and increasing the potential for
early device failure.
How the effects of moisture in plastic packages and the critical moisture content result in package damage or failure is
a complex function of several variables. Among them are
package construction details -- materials, design, geometry, die size, encapsulant thickness, encapsulant properties, TCE, and the amount of moisture absorbed. The
PSMC moisture sensitivity has, in addition to package
cracking, been identified as a contributor to delaminationrelated package failure artifacts. These package failure artifacts include bond lifting and breaking, wire neckdown,
bond cratering, die passivation, and metal breakage.
Because of the importance of the PSMC moisture sensitivity, both device suppliers and device users have ownership
and responsibility. The background for present conditions,
moisture sensitivity standardized test and handling proce-

10-18

dUres have been published by two national organizations.
Users and suppliers are urged to obtain copies of both documents (listed below) and use them· rigorously. Xilinx
adheres to both.
•

JEDEC STANDARD JESD22-A112. Test Method A112
"Moisture-Induced Stress Sensitivity for Plastic Surface
Mounted Devices".
Available through Global Engineering Documents
Phone: USA and Canada 800-854-7179, International
1-303-792-2181

•

IPC Standard IPC-SM-786A "Procedures for
Characterizing and Handling of Moisture/Reflow
Sensitive ICs".
Available through IPC
Phone: 1-708-677-2850

None of the previously stated or following recommendations apply to parts in a socketed application. For board
mounted parts careful handling by the supplier and the user
is vital. Each of the above publications has addressed the
sensitivity issue and has established 6 levels of sensitivity
(based on the variables identified). A replication of those
listings, including the preconditioning and test requirements, and the factory floor life conditions for each level are
outlined in Table 4. Xilinx devices are characterized to their
proper level as listed. This information is conveyed to the
user via special labeling on the Moisture Barrier Bag
(MBB).
In Table 4, the level number is entered on the MBB prior to
shipment. This establishes the user's factory floor life conditionsas listed in the time column. The soak requirement
is the test limit used by Xilinx to determine the level number.
This time includes manufacturer's exposure time or the time
it will take for Xilinx to bag the product after baking.

August 6, 1996 (Version 1.2)

~XILINX
Table 4: Package Moisture Sensitivity Levels per JEDEC A112
Level

1
2

Soak Requirements (Preconditioning)
Time
Conditions
168 hours
85°C 1 85% RH

Factory Floor Life
Conditions
Time
:s;30°C 1 90%
Unlimited
RH
:s;30°C 1 60%
1 year
RH

168 hours

85°C 1 60% RH

. Time (hours)
3

:S;30°C/60%
RH

168 hours

X +
24

4

:s;30°C/60%
RH

72 hours

5

:s;30°C 160%
RH
:s;30°C 1 60%
RH

6
Notes:

X

=

Y

Z

168

192

:S;30°C /60% RH

12

72

84

:S;30°C 1 60% RH

24 hours

6

24

30

:s;30°C 1 60% RH

6 hours

0

6

6

:S;30°C 1 60% RH

=Default value of semiconductor manufacturer's time between bake and bag. If the semiconductor manufacturer's

actual time between bake and bag is different from the default value, use the actual time.
Y = Floor life of package after it is removed from dry pack bag.
Z = Total soak time for evaluation.

Factory Floor Life
Factory floor life conditions for Xilinx devices are clearly
stated on MBB containing moisture sensitive PSMCs.
These conditions have been ascertained by following Test
Methods outlined in JEDEC JESD22-A 112 and are replicated in Table 4. If factory floor conditions are outside the
stated environmental conditions (85°C/85% RH for level 1,
and 30°C/60% RH for Levels 2-6) or if time limits have been
exceeded, then recovery can be achieved by baking the
devices before the reflow step. Identified in the next section
are two acceptable bake schedules. Either can be used for
recovery to the required factory floor level.

Dry Bake Recommendation and Dry Bag
Policy
Xilinx recommends, as do the mentioned publications and
other industry studies, that all moisture sensitive PSMCs
be baked prior to use in surface mount applications, or
comply strictly with requirements as specified on the MBB.
Tape and Reeled parts are universally dry packed. Level 1
parts are shipped without the need for, or use of, an MBB.
Two bake schedules have been identified as acceptable
and equivalent. The first is 24 hours in air at 125°C., in shipping media capable of handling that temperature. The second bake schedule is for 192 hours in a controlled
atmosphere of 40°C, equal to or less than 5% RH.
Dry Devices are sealed in special military specification
Moisture Barrier Bags (MBB). Enough desiccant pouches

August 6,1996 (Version 1.2)

are enclosed in the MBB to maintain contents at less than
20% RH for up to 12 months from the date of seal. A reversible Humidity Indicator Card (HIC) is enclosed to monitor
the internal humidity level. The loaded bag is then sealed
shut under a partial vacuum with an impulse heat sealer.
Artwork on the bags provides storage, handling and use
information. There are areas to mark the seal date, quantity, and moisture sensitivity level and other information.
The following paragraphs contain additional information on
handling PSMCs.

Handling Parts in Sealed Bags
Inspection
Note the seal date and all other printed or hand entered
notations. Review the content information against what was
ordered. Thoroughly inspect for holes, tears, or punctures
that may expose contents. Xilinx strongly recommends that
the MBB remain closed until it reaches the actual work station where the parts will be removed from the factory shipping form.

Storage
The sealed MBB should be stored, unopened, in an environment of not more than 90% RH and 40°C. The enclosed
HIC is the only verification to show if the parts have been
exposed to moisture. Nothing in part appearance can verify
moisture levels.

10-19

I

Packages and Thermal Characteristics

Expiration Date

Other Conditions

The seal date is indicated on the MBB. The expiration date
is 12 months from the seal date. If the expiration date has
been exceeded or HIC shows exposure beyond 20% upon
opening the bag bake the devices per the earlier stated
bake schedules. The three following options apply after
baking:

Open the MBB when parts are to be used. Open the bag by
cutting across the top as close to the seal as possible. This
provides room for possible resealing and adhering to the
reseal conditions outlined above. After opening, strictly
adhere to factory floor life conditions to ensure that devices
are maintained below critical moisture levels.

Use the devices within time limits stated on the MBB.
Reseal the parts completely under a partial vacuum
with an impulse sealer (hot bar sealer) in an approved
MBB within 12 hours, using fresh desiccant and HIC,
and label accordingly. Partial closures using staples,
plastic tape, or cloth tape are unacceptable.

Bags opened for less than one hour (strongly dependent on
environment) may be resealed with the original desiccant. If
the bag is not resealed immediately, new desiccant or the
old one that has been dried out may be used to reseal, if
the factory floor life has not been exceeded. Note that
factory floor life is cumulative. Any period of time when
MBB is opened must be added to all other opened periods.

Store the out-of-bag devices in a controlled atmosphere
at less than 20% RH. A desiccator cabinet with controlled dry air or dry nitrogen is ideal.

Both the desiccant pouches and the HIC are reversible.
Restoration to dry condition is accomplished by baking at
125°C for 10-16 hours, depending on oven loading conditions.

10-20

August 6, 1996 (Version 1.2)

~XILINX
Tape and Reel
Xilinx offers a tape & reel packing for PLCC, BGA, QFP, and
SO packages. The packing material is made of black conductive Polystyrene and protects the packages from
mechanical and electrical damage. The reel material provides a suitable medium for pick and place equipment.
The tape & reel packaging consists of a pocketed carrier
tape, sealed with a protective cover. The device sits on pedestals (for PLCC, QFP packages) to protect the leads from
mechanical damage. All devices loaded into the tape carriers are baked, lead scanned before the cover tape is
attached and sealed to the carrier. In-line mark inspection
for mark quality and package orientation is used to ensure
shipping quality.

Benefits
o

o

o
o

o
o

o

o

o

Increased quantity of devices per reel versus tubes
improves cycle time and reduces the amount of time to
index spent tubes.
Tape & reel packaging enables automated pick and
place board assembly.
Reels are uniform in size enabling equipment flexibility.
Transparent cover tape allows device verification and
orientation.
Anti-static reel materials provides ESD protection.
Carrier design include a pedestal to protect package
leads during shipment.
Bar code labels on each reel facilitate automated
inventory control and component traceability.
All tape & reel shipments include desiccant pouches
and humidity indicators to insure products are safe from
moisture.
Compliantto Electronic Industries.Association (EIA)
481.

Material and Construction
Carrier Tape
o

o

The pocketed carrier Tape is made of conductive
polystyrene material, or equivalent, with a surface
resistivity level of less than 106 ohms per square inch.
Devices are loaded 'live bug' or leads down, into a
device pocket.

August 6, 1996 (Version 1.2)

o

o

Each carrier pocket has a hole in the center for
automated sensing of whether a unit is in the pocket or
not.
Sprocket holes along the edge of the carrier tape
enable direct feeding into an automated board
assembly equipment.

Cover Tape
o

o

An anti-static, transparent, polyester cover tape, with
heat activated adhesive coating, sealed to the carrier
edges to hold the devices in the carrier pockets.
Surface resistivity on both sides is less than 1011 ohms
per square inch.

Reel
o

o

•
•

The reel is made of ant i-static Polystyrene material. The
loaded carrier tape is wound onto this conductive
plastic reel.
A protective strip made of conductive Polystyrene
material is placed on the outer patt of the reel to protect
the devices from external pressure in shipment.
Surface resistivity is less than 1011 ohms per square
inch.
Device loading orientation is in compliance with EIA
Standard 481.

Bar Code Label
o

o

o

o

The bar code label on each reel provides customer
identification, device part number, date code of the
product and quantity in the reel.
Print quality are in accordance with ANSI X3.182-1990
Bar Code Print Quality Guidelines. Presentation of Data
on labels are EIA-556-A compliant.
The label is an alphanumeric, medium density Code 39
labels.
This machine-readable label enhances inventory
management and data input accuracy.

Shipping Box
o

The shipping container for the reels are in a 13" x 13" x
3" C-flute, corrugated, # 3 white 'pizza' box, rated to
200 Ib test.

10-21

I

Packages and Thermal Characteristics

Table 5: Tape & Reel Packaging
Package Type
PLCC (Plastic Leaded Chip Carrier)

SO (Plastic Small Outline)
QFP (Plastic Quad Flat Pack)
BGA (Plastic Ball Grid Array)
Notes:

Pin Count
20
20
44
68
84
8
100
160
225

Carrier
Width
16mm
16mm
32 mm
44mm
44mm
12 mm
44mm
44mm
44mm

Cover
Width
13.3 mm
13.3 mm
25.5 mm
37.5 mm
37.5 mm
9.2mm
37.5 mm
37.5 mm
37.5 mm

Pitch
12mm
12 mm
24mm
32mm
36mm
8mm
32mm
40mm
32mm

Reel Size
7 inch
13 inch
13 inch
13 inch
13 inch
7 inch
13 inch
13 inch
13 inch

Qty per
Reel
250
750
500
250
250
750
250
200
500

1.A minimum of 230mm of empty pockets are provided at the beginning (leader) of each reel.
2.A minimum of 160mm of empty pockets are provided at the end (trailer) of each reel.
3.Tape leaderfTrailer requirements are in compliance to EIA Standards 481.
4.Peel Strength between 20 and 120 grams ensures consistency during de-reeling operations and is compliant to EIA
Standard 481 .
5.Each reel is subject to peel back strength tests.
6.For packages not listed above, please contact your Xilinx sales representative for updated information.

Standard Bar Code Label Locations

bI

~

10-22

August 6, 1996 (Version 1;2)

F.:XILINX
Reflow Soldering Process Guidelines
In order to implement and control the production of surface
mount assemblies, the dynamics of the solder reflow process, and how each element of the process is related to the
end result, must be thoroughly understood.
The primary phases of the reflow process are as follows:
1. Melting the particles in the solder paste
2. Wetting the surfaces to be joined
3. Solidifying the solder into a strong metallurgical bond

Each phase of a surface mount reflow profile has min/max
limits that should be viewed as a process window. The process requires a careful selection and control of the materials, geometries of the mating surfaces' (package footprint
vs. PCB land pattern geometries) and the time temperature
of the profile. If all of the factors of the process are sufficiently optimized, there will be good solder wetting and fillet
formation (between component leads and the land patterns
on the substrate). If factors are not matched and optimized
there can be potential problems as summarized in Figure 3.

The sequence of five actions that occur during this process
is shown in Figure 2.
Potential Reflow Soldering Issues

Reflow Soldering Phases

200

~
~

150

::J

"§

'"c.E
'"

100
Time

f-

50

Time

Figure 2:

August 6, 1996 (Version 1.2)

X5975

1. Insufficient Temperature to Evaporate Solvent
2. Component Shock and Solder Splatter
3. Insufficient Flux Activation
4. Excessive Flux Activity and Oxidation
5. Trapping.ofSolvent and Flux, Void Formation
6. Component and/or Board Damage

X5976

Figure 3:

10-23

I

Packages and Thermal Characteristics

Figure 4 and Figure 5 show typical conditions for solder
reflow processing using Vapor Phase or IR Reflow. The
moisture sensitivity of Plastic Surface Mount Components
(PSMCs) must be verified prior to surface mount flow. See
the preceding sections for a more complete discussion on
PSMC moisture sensitivity.
.

~
.

215·219'C
=45smax
~Rampdown
~

2_4°C/s

Ct183
Dwell=30·60s
Preheat & drying dwell

.

T·Max (leads)
220', 235'C

_-+-----. I- 120 s min between

&,

95' • 180'C

/
2'4'C/S~

------...

Temp = 183'C

Ramp down

~2.4'C/s

•

Time

I-I
t ,
183

-7""-------1Preheat & drying dwell
120·180s
~
~een 95' • 180'C ~

"'- 60s <1183 < 120s

(5)

X5974

Figure 5: Typical conditions for vapor phase reflow
soldering

applies to lead area

'Time(s)

X5973

Figure 4: Typical conditions for IR reflow soldering
Notes:
1. Max temperature range = 220°C-235°C (leads)
Time at temp 30-60 seconds
2. Preheat drying transition rate 2-4°C/s
3. Preheat dwell 95-180°C for 120-180 seconds
4. IR rellow shall be performed on dry packages

Notes:
1. Solvent - FC5312 or equivalent - ensures temperature
range of leads @ 215-219°C
2. Transition rate 4-5°C/s
3. Dwell is intended for partial dryout and reduces the
difference in temperature between leads and PCB
land patterns.
4. These guidelines are for reference. They are based on
laboratory runs using dry packages. It is
recommended that actual packages with known loads
be checked with the commercial equipment prior to
mass production.

The IR process is strongly dependent on equipment and
loading differences. Components may overheat due to lack
of thermal constraints. Unbalanced loading may lead to
significant temperature variation on the board. This
guideline is intended to assist users in avoiding damage to
the components; the actual profile should be determined by
the users using these guidelines.

10-24

August 6, .1996 (Version 1.2)

~XILINX
Sockets
ment by Xilinx. Each user has the responsibility to evaluate
and approve a particular socket manufacturer.

Table 6 lists manufacturers known to offer sockets for Xilinx
Package types. This summary does not imply an endorseTable 6: Socket Manufacturers

Packages
Manufacturer

PQ
HQ
TQ
VQ

DIP
SO
VO

PC
WC

AMP Inc.
470 Friendship Road
Harrisburg, PA 17105-3608
(800) 522-6752

X

X

X

Augat Inc.
452 John Dietsch Blvd.
P.O. Box 2510
Attleboro Falls, MA 02763-2510
(508) 699-7646

X

X

X

McKenzie Socket Division
910 Page Avenue
Fremont, CA 94538
(510) 651-2700

X

X

X

3M Textool
6801 River Place Blvd.
Austin, TX 78726-9000
(800) 328-0411
(612) 736-7167
Wells Electronics
1701 South Main Street
South Bend, IN 46613-2299
(219) 287-5941
Yamaichi Electronics Inc.
2235 Zanker Road
San Jose, CA 95131
(408) 456-0797

August 6, 1996 (Version 1.2)

PG
PP

X

CB

BG
CG

X

X

X

X

X

X

I

X

10-25

Packages and Thermal Characteristics

Physical Dimensions
Plastic DIP Packages SOIC Packages -

PD8, PD48 ............................................................... 27

S08 ......................................................................... 29

TSOP Packages - V08 ........................................................................ 30
PLCC Packages - PC20, PC28, PC44, PC68, PC84 .................................................. 31
PQFP Packages -

PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208, HQ240, HQ304 ..... 32

TQFP Packages - TQ44, TQ1 00, TQ144, TQ176, HT100, HT144, HT176 ................................. 38
VQFP Packages BGA Packages -

VQ44, VQ64, VQ1 00 ........................................................... 42
BG225, BG352, BG432 .......................................................... 45

Ceramic DIP Packages -

008 ................................................................... 48

Ceramic PGA Packages - PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175, PG191, PG223, PG299,
PG411 ...................................................................................... 49
Ceramic Brazed QFP Packages CLCC Packages -

Plastic PGA Packages -

PP132, PP175 ........................................................... 68

Windowed CLCC Packages Metal Quad Packages -

10-26

CB100, CB164, CB196, CB228 ....................................... 61

CC20 ....................................................................... 67

WC44, WC68, WC84 .................................................. 70

MQ208, MQ240 ........................................................... 71

August 6, 1996 (Version 1.2)

£XILINX
Plastic DIP Packages -

8

PD8, PD48

7

5

6
I

I

---+---I

E1

I

I
I

PIN 1 INOE;X
(OPTION)

I----E-----I

~---O----~

I:

I

I
/
/

BASE PLANE-SEATING PLANE

/

L

t
b3

/I
/I
/I
/I
/I
/I
/I
/I
/I

b~

01

~
~
A
AI
A2
b

b2
b3
<'

C

D

Dt
E
El
e

eA
eB
L
N

N
0

INCHES
MIN,

MAX,

~

0,181

0,019
0,122
0,014
0,045

0,161
0,022

~

,~"

,0,045
0,U12
0,382

~

0,009
0,355
0,005 I'.~:
0,303
0,323
0,240
0,272
0,100 BSC
0,300 BSC

I

T
E

NOJES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
• TO ANSt Y14,5M-1982,
2,. DIMENSIONS "0" AND "Ei" DO NOT INCLUDE MOLD
PROTRUSIONS. ALLOWABLE MOLD PROTRUSION SHALL
NOT EXCEED .010" PER SIDE.
3. L~D FINISH: (85±5%)Sn-Pb SOLDER PLA1E
4, CONFORMS TO JEDEC.MS-D01-BA

0.430
0,150

~

0,115
8

8-PIN PLASTIC DIP (PD8)

AugustS/199S (Version 1.2)

10-27

Packllges and Thermal Characteristics .

N

PIN 1 INDEX
0

--..
A

~

-

~HHHJ-{HHH

~B1

;
L

A
Ai
A2
B

Bi
C
D

Dt
E
Ei
e

eA
eB
L
N

HHHHHHHHJ-{HHHHH

~~

- - Le

I

L1
t

1-- 01

~

'-----1f----'

"
""

[1-",

c

LeB:--~

BASE PLANE---o.,l.--j
SEATING PLANE - - -

INCHES

...,.,...

~

-

I--B

MIN,

• r
A2!

MAX;

0.190
...,.,...
0,015
0.125
0.195
0,014
0,022
0,030
0,070
0,008
0,015
2,480
2,385
... ...,.,....
0,005
0,625
0,600
0,485
0,580
0.100 BSC
0,600 BSC
...,.,...
0,700
0,115
0,200
48

DETAIL 'A'

NOTES:
1. All DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. "0" AND "E1" DIMENSIONSD()NOlINClUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH or PROTRUSIONS SHAll
NOT EXCEED .010".
3. lEAD FINISH: SOLDER PLAtE
4. CONFORMS TO JEDEC MS-011-AD

48-PIN PLASTIC DIP (PD48)

10-28

August. 6, 1996 (Version 1.2)

~XILINX
sOle Packages - S08

TOP.· VIE'W

BOTTOM VIE'W
PIN #1 ID


~'-l~
-tt---

+

---1-1-

H

r

i~+

®

~~8J!

1-4---1-n-I-----.J

AI

~DB]

SEATING PLANE

END VIE'W

SIDE VIE'W

I

s

y
M
B

0
L

A

A,
A.
B

INCHES
MIN,
,059
,004
,055
,013
,0075
,189
.150

C
D
E
e
H ,229
h ,010
L ,016
a:

NOM,
,064
,006
,058
,016
,008
.194
.155

MAX,
,068
,0098
,061
,020
,0098
.196
.157

,050BSC

O·

,236
,013
,025
5·

,244
,019
,035
8·

DETAIL A
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M':'1982.
2. DIMENSION "0" DOES NOT INCLUDE MOLD PROTRUSION.
AlLOWABLE MOLD PROTRUSION SHALL NOT EXCEED
.006" PER SIDE.
3. DIMENSION "r DOES NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED
.010" PER SIDE.
4. LEAD FINISH: SOLDER PLATE
5. CONFORMS TO JEDEC MS-012

8 LEADSOIC (S08)

August 6, 1996 (Version 1.2)

10-29

Packages and.Thermal Characteristics

TSOP Packages - V08

TOP VIEW'

BOTTOM VIEW'

-l:

PIN 111 ID
(OPTIONAl)

r------+-'-~'
+

HI-

~~J!
SEA TING PLANE

,END VIEW'

SIDE VIEW'

sy

INCHES

M

B
D

L

A

MIN,
~

Al ,002

Az. ,037
B
C

D
E

,0138
,0075
,189
.150

e
H
h
L
LI

,230
,010
,016

a:

0°

NOM,

MAX,
,047
,006
,044
,0192
,0089
,196
.157

...,.,....

,004
,039

...,.,....

...,.,....
,194
,155

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-'1982

,050 BSC

,236
.013
,025

,244
,019
,035

0,010 BSC

...,.,....

'I

8°

2.

~~~~~~~E o~~LgO~~o~~~s\~L~~~O~g/~~~~ION.
.006" PER SIDE.

'

3. DIMENSION or' DOES NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED
.010" PER SIDE.
.
4. lEAD FINISH: SOLDER PLATE

8 LEAD TSOP (V08)

10-30

August 6, 1996 (Version 1.2)

~:XILINX
PLCC Packages -

PC20, PC28, PC44, PC68, PC84

TOP VIEIJ

BOTTOM VIEIJ

0

PIN 1

I

1.0."

;J ~
32 1 N

t-'-[±]""-Al::-.l..---Dl-----1

.056

.048/.042 J

+

L

L

~

~--

D

+

-----fll~

.032/.026

s

INCHES

y

"•

D
L

.165 .180
.090 .120
.385 .395

.165
.099
.485

.180
.110
.495

.165
.090
.685

.180
.120
.695

.985

.165
.200
.130 .090
.130
.995 1.185 1.195

.350 .356
D.IE, .290 .330

.450
.35)0

.456
.430

.650
.590

.656
.630

.950
.890

.958
.930

1.150 1.158
1.090 1.130

.800 REF .
.050 BSC

1.000 REF .
.050 BSC

68

84

A
A.
.020 MIN.

L.0211~13

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.I MIN. MAX.

DIE
D./E.

D,/E.

.200 REF.

.300 REF.

.500 REF .

e

.050 BSC
20

.050 BSC

.050 BSC
44

N

28

.165
.090

.200

I

DETAIL 'A'

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1982.
2. DIMENSIONS 'DIu AND 'EI' DO NOT INCLUDE MOLD FLASH DR
PROTRUSIONS. MOLD FLASH DR PROTRUSIONS SHALL NOT
EXCEED .010 PER SIDE.
3. 'N' IS NUMBER OF TERMINALS.
4. CONFORM TO JEDEC MO-047
5. TOP OF PACKAGE MAY BE SMALLER THAN
BOTTOM BY .010'.

20. 28, 44, 68 and 84-PIN PLCC (PC20 THRU PC84)

August 6, 1996 (Version 1.2)

10-31

Packages and Thermal Characteristics

PQFP Packages HQ240, HQ304

PQ44, PQ100, PQ160, PQ208, PQ240, PQ304, HQ100, HQ160, HQ208,

BOTTOM VIEW

TOP VIEW

22

b

12

~II----'---r=.-----=r::-r:~:::_:;;;;:,
1$10.0.0. ~lclA -B 01D01
LEAD FINISH, SOLDER PLATE

c

o ccc -C-

sy

MILLIMETERS

M

~

A
A!
Ae

MIN.

NOM.

MAX.

~

2.15

2.35

0.05

~

0.25

1.95
DIE 12.95
D!/E! 9.90

"

2.00
13.20

2.10
13.45

10.00

10.10

8.00 BSC

D3/E 3
L

Ai

0.73

0.88
1.03
0.80 BSC.

10

0.30

~

c

0.13

~

0.0.0.

~

0.20

~

ccc

~

~

0.10

0.45

DETAIL 'A'
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982.
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF
PACKAGE BY 0.15mm.
4. CONFORMS TO JEDEC MO-l0B-M2

0.23

44-PIN PLASTIC PQFP (PQ44)

10-32

August 6, 1996 (Version 1.2)

~XILINX

BOlTOM VIEW

TOP VIEW

+
SEE DETAIL 'A'~

5'-16'

LEAD FINISHI SOLDER PLATE

rA

a~OJ!lmJ!.Qnlln.JJIIIDJlIUIJIDO~'-'-';----,---,--""""
~
,_~r f
K:J

I-'

5'-16'

s
~

MILLIMETERS

B

0
L

MIN,

A
AI
Ae
D

~

Dl
D3
E

El
E3
L

c
ccc
ddd

MAX,

~
3.40
~
0,25 ~
2,55
2,80
3,05
22,95 23,20 23.45
19,90 20,00 20,10
18,85 REF,
16,95 17,20 17.45
13,90 14,00 14.10
12,35 REF,

0,73

e
10

NOM,

0,88

1.03

0,65 BSC
0,22

~

0,38

0.13

~

~

~

0,23
, 0.10

~

~

0.12

lei eeel cl

I

A1

DETAIL 'A'

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14,5M-1982,
2. DIMENSIONS "01" AND "El" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS 0.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE EQUAL TO OR SMALLER THAN
THE BOTTOM OF PACKAGE BY 0.15 MILLIMETERS.
4. PACKAGE CONFORMS TO JEDEC OUTUNE MO-l0B-CCl

& THE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".

100-PIN PQFP (PQ100)
100-PIN HEAT SINK PQFP (HQ100)

August 6, 1996 (Version 1.2)

10-33

Packages and Thermal Characteristics

BOTTOM VIEW

SEE DETAIL 'A'

12"-16"

lm.oo.~.-a
'--

LEAD FINISH: SOLDER PLATE

c::.G
s

y
M
B

101 cccici

AI

0
L

MIN.

NOM.

MAX.

A

~

3.70

4.10

A1

0.25

0.33

~

A2

3.20

3.40

3.60

DIE
DETAIL 'A'

30.95

31.20 31.45

Dt/E1 27.90

28.00 28.10

1. ALL .DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982.
2. DIMENSIONS "Dr AND "E1" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN THE BOTTOM
DIMENSIONS .BY 0.20mm.
4. PACKAGE CONFORMS TO JEDEC MO-108-DD1
THE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".

25.35 REF.

D3/E3
L

NOTES:

MILLIMETERS

0.88

0.73

e

1.03

0.65 BSC.

b

0.22

~

0.38

c

0.13

~

0.23

ccc

~

0.10

~

010101

~

0.12

~

&.

160-PIN PQFP (PQ160)
160-PIN HEAT SINK PQFP (HQ160)

10-34

August 6,1996 (Version 1.2)

EXILINX
TOP VIEW

BOTTOM VIEW

+

+

E1-

/

/
I

1$ldclcl®lcIA-B~ID~

SEE DETAIL 'A'~

5'-16'

LEAD FINISH: SOLDER PLATE

11ll",d,DI+UIII,dHIII",UQJ)I-.;_r;EQ:3<""1
~

M
B
0
L

MILLIMETERS

--

NOM.

MAX.

A

3.70

4.10

Ai

0.25

0.33

--

3.40

3.60

A2

MIN.

3.20

DIE

30.60 ESC

DliEl

28.00 BSC

.. D3 /E 3.

25.50 REF.

L

0.50

e
b

c

rO.60

. cc:c

--

ddd

--

0.22\

--

---

I

----- t -1-iY~? ---

'lo-'l-cc-c"TlcIr----1-~======+~S;;:::::a.·
7l

.25
~
. GAGE

A

...

PLANE

1.30 REF.---I----t

DETAIL 'A'
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI YI4.SM- Hl82.

0.75 (

0.50 ESC.
0.17
0.09

c

0.27
. 0.20

0.08

2. DIMENSIONS "01" AND "El" DO NOT INCLUDE MOLD PROTRUSIONS.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED .O.2Smm· PER SIDE.
3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN THE BOTTOM
DIMENSIONS BY 0.20mm.
4. DRAWING CONFORMS TO JEDEC MO-143-FA-l
.&.:THE sAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".

0.08

208-PIN PQFP (PQ208)
208-PIN HEAT· SINK PQFP (HQ208)

August 6, t996 (Version 1.2)

10-35

Packages and Thermal Characteristics

TOP VIE'w'

BOTTOM VIE'w'

,a,

-I

DI

illillilililllillilliliUllli

,eo

EEl

,

@)

PIN I !.D.

'l-i!IiIiIt-----

+ ---

+

EI -

EEl/

12'

r

Ef)

a,

'20

'" """ ... ~

~lInIDIDIIIDIQI~
12-16"

~

M

B

.J.

eo

1"1'" !IlJlcli@-© I.., I
LEAD FINISH. Solder Ple. te

MILLIMETERS

~

MIN.

A

~

NOM.

MAX.

3.78

4.10

AI

0.25

0.38

~

A2
10

3.20

3.40

3.60

0.17

~

0.27

c

0.09

~

0.20

rITill

+
___

l..L..G~E ~ANE

1.30 REF. - - l - - - - - i

NOTES:

DETAIL 'A'

DIE

34.60 BSC

DIIEI

32.00 BSC

1. ALL DIMENSIONS AND TOLERANCES CONFORM

29.50 REF.

2. DIMENSIONS "of' AND "El" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.

D3 /E3
L

e

0.50

0.60
0.50 BSC.

dclcl

0.08

ccc

0.08

0.75

TO ANSI Y14.5-1982.

3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN BOTTOM
DIMENSIONS BY 0.2mm.
4. CONFORMS TO JEDEC MO-143-GA

&. THE

SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".

240-PIN PQFP (PQ240)
240-PIN HEAT SINK PQFP (HQ240)

10-36

August 6, 1996 (Version 1.2)

~XILINX
TOP VIEW

r - - - - - f - - -......

BonOM VIEW

~

0

+

E1-!1-----

153

~~
b

5·-16·

+

-I-

f$lddd@lcIA - B01D(s)1

LEAD FINISH: SOLDER PLATE

~AJE0FIN~

JI-H-I .~i==~=*

s

y
M
B

0

MILLIMETERS

l

MIN.

NOM.

A

""*-'

4.23

4.50

A!

0.25

0.43

""*-'

A2

3.60

3.80

4.00

DIE

42.60 BSC

DI/E!

40.00 BSC

D2/E2
L

e

0.75

0.60
0.50 BSC.

b

0.17

""*-'

0.27

bl

""*-'

0.20

""*-'

ccc

0.08

ddd

0.07

1.30 REF , : - - - 1 - - - - . . ,

NOTES:

37.50 REF.
0.45

I

MAX.

DETAIL 'A'

1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED
O.25mm PER SIDE.
3. PACKAGE TOP DIMENSIONS MAY BE SMALLER THAN BOTTOM
DIMENSIONS BY O.15mm.
4. CONFORMS TO JEDEC OUTLINE MO-143-JA

.& THE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "HQ".

304-PIN PQFP (PQ304)
304-PIN HEAT SINK PQFP (HQ304)

August 6, 1996 (Version 1.2)

10-37

Packages and Thermal Characteristics

TQFP Packages - TQ44, TQ1 00, TQ144, TQ176, HT1 00, HT144, HT176
BonOM VIEW

1~ - - \ - - - .

[38

Ic Iccc I -c- I

1

DATUM
A2 PLANE--

jBB
s

~

Al

MILLIMETERS

B

0
L

MIN,

NOM,

MAX,

A
Al
A2
DIE

~

~

1.60
0,15

0,05
1.35

0.10

1.40
1.45
12,00 ESC

NOTES:

10,00 ESC

DI/EI

10

0,30

0,37

0.45

c

0,09

~

0,20

0,80 ESC,

e
0.45

0,60

ccc

~

~

0,75
0.10

ddd

~

~

0,20

L

DETAIL "A"

1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1982,
2. DIMENSIONS "01" AND "E1· DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED O.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BonOM OF
PACKAGE BY 0.15mm.
4. CONFORMS TO JEDEC MS-026-BCB

44-PIN PLASTIC TQFP (TQ44)

10-38

August 6, 1996 (Version 1.2)

~XILINX

TOP VIEW

BonOM VIEW

~--------D~----~~

-1; .

1$lcIcici (f3) lelA - B iSllD01

11'-13

SEE DETAIL 'A' \

) ...mM.mt·..·""''''

(sf

LEAD FINISH: SOLDER PLATE

A

B3
c

s

y
M
B
0
L

MILLIMETERS

A

~

~

Al

0.05

~

1.60
0.15

1.35 1.40
1.45
16.00 sse
14.00Bse
DIIEI
L
0.45 0,60
0.75
0.50 sse
e
0.17 0.22 0.27
b
A2

DIE

c

I

MIN, NOM, MAX,

0.09

~

0.20

ccc

~

~

0,08

eIeIeI

~

-x,<...

0,08

DETAIL "A'
NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982
2. DIMENSIONS" 01" AND' E1" DO NOT INCLUDE MOLD PROTRUSION. AlLOWABLE
MOLD PROTRUSION SHALL NOT EXCEED O.25mm PER SIDE.
3. PACKAGE TOP DIMENSION MAY BE SMALLER THAN THE BOTTOM
DIMENSION BY O.15mm.
4. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95
REGISTRATION MS-026-BED
TRE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "Hf.

.&.

100-PIN TQFP (TQ100)
100-PIN HEAT SINK TQFP (HT100)

August 6, 1996 (Version 1.2)

10-39

Packages and Thermal Characteristics

BOTTOM VIEW

TOP VIEW

01

PIN 1 1.0.

"I
mmmn mir

+

c

~

~

L

A
A,
A2
DIE
DyE,
L
e
b
G

DETAIL 'A'

MILLIMETERS

MIN.

NOM.

MAX.

~

~

0.05
1.35

0.10
1,40

1.60
0.15
1,45

22.00 BSC
20.00 BSC
0,45
0.60 0.75
0.50 BSC
0.17
0.22 0.27
0.09 ~ 0.20

GGG

~

~

0.08

ddd

~

~

0.08

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982.
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDL

3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE. BOTTOM
OF PACKAGE BY O.lSmm.
4. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95
REGISTRATION MS-026-BFB
&lTHE SAME PACKAGE DIMENSIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS "Hl".

144-PIN TQFP (T0144)
144-PIN HEAT SINK TQFP (HT144)

10-40

August6, 1996 (Version 1.2)

~XILINX

BOTTOM VIEW

SEE DETAIL 'A' ~

11'-13·

1$lclclcl ®lclA -B 01D01

~
~

MILLIMETERS

MIN,

NOM,

A

~

~

1.60

Al
Ae

0,05

0.10
1,40

0.15
1,45

L

DIE
DllEl
L

e
10

c

LEAD FINISH: SOLDER PLATE

MAX,

1.35
26,00 BSC
24,00 BSC
0,45
0,60 0,75
0,50 BSC
0.17
0,22 0,27
0,09 ~ 0,20

ccc

~

~

clolcl

~

~

0,08
0,08

1,00 REF,

DETAIL 'A'
NOTES:
1. AlL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982.
2. DIMENSIONS 01 AND E1 DO NOT INCLUDE MOLD PROTRUSION.
AlLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
OF PACKAGE BY O.lSmm.
4. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95
REGISTRATION MS-026-BGA
THE SAME pACKAGE DIMESIONS APPLY FOR THERMALLY ENHANCED
PRODUCTS. HEAT SINK IS ADDED. THE PACKAGE CODE IS • Hl".

.&

176-PIN TOFP (TO 176)
176-c-PIN HEAT SINK TOFP (HT176)

August 6, 1996 (Version 1.2)

10-41

Packages and Thermal Characteristics

VQFP Packages - VQ44, VQ64, VQ1 00
BOn-OM VIEW
f-------i D

1----..,

l~ --+---...

+---Jaiaia---

LEAD FINISH, SOLDER PLATE

~

~ccc

I-c-I

I

DATUM
A2 PLANE--

I[±]

Al
S

~

MILLIMETERS

B

0

MIN,

NOM,

MAX,

A
AI
A2
DIE

~

~

0,05

~

1.20
0.15

L

0,95

Dj/El
L

0.45

e

1.00
1.05
12,00 ESC
10,00 ESC
0,60
0,75
0,80 ESC,

b

0,30

0,37

c
ccc

0,09

~

~

~

0.45
,020
0.10

ddd

~

~

0,20

DETAIL» tI'

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982.
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD PROTRUSION
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM OF
PACKAGE BY 0,15mm.
4, CONFORMS TO JEDEC MS-026-ACB

44-PIN PLASTIC VQFP (VQ44)

10-42

August 6,. 1996 (Version 1.2)

--

-~

-~---

~-~

--

--

~----

~:XILINX

TOP VIEW'

BOTTOM VIEW'

1+ ddd ®Icl A-B ~I D ~I
LEAD FINISH: SOLDER PLATE

O· MIN.

c

1.00 REF.
S

Y
M
B

~

A
Al
A2
DIE
DI/E!

~

NOM,
~

MAX,
1.20

0,05

0.10

0.15

0,95

1.00

1.05

12,00 BSC,

b

10,00 BSC.
0.17
0.22 0,27

c

0.09

e

0.50 BSC,
0,45 0.60
0,75

L

~

I

DETAIL I AI

MILLIMETERS
MIN,

-1----1

0.20

ccc

~

~

0.08

ddd

~

~

0.08

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982.
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD PROTRUSION.
ALLOWABLE MOLD PROTRUSION IS O.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOnOM
OF PACKAGE BY 0.15mm.
4. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95
REGISTRATION MS-026-ACD

64-PIN PLASTIC VQFP (VQ64)

August 6, 1996 (Version 1.2)

10-43

Packages and Thermal Characteristics

BOTTOM VIE'W

TOP VIE'W

rf

Dl~

6

PIN

75

E1

1

+ ----E~

u~
SEE DETAIL 'A'"\
')

11·-13·

®I IA-B

1-+

~nnnnnnnnn~nnnnnnncuu~.9

25

ddd
c
~I D ~
LEAD FINISH: SOLDER PLATE

t
c

r::-r::c-::-::r;;-r--=:======-===::::::::.....+--~=!

rfD.25I
L ~-GAGE

t

L

s

Y

M
B

~

7

PLANE

0·- r

1.00 REF, -1-----1
MILLIMETERS
MIN,

NOM,

A

~

AI

0,05

0,10

0.15

A2

0,95

1.00

1.05

~

1.20

DIE

16,00 BSC,

DIIE!
b

14,00 BSC,
0.17 0,22 0,27

c

0,09

e

~

0,20

0,50 BSC,
0,60

DETAIL 'A'

MAX,

0,75

L

0.45

ccc

~

~

0,08

cIcici

~

~

0,08

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO ANSI Y14.5M-1982.
2. DIMENSIONS "01" AND "E1" DO NOT INCLUDE MOLD PROTRUSION,
ALLOWABLE MOLD PROTRUSION SHALL NOT EXCEED 0.25mm PER SIDE.
3. THE TOP OF PACKAGE MAY BE SMALLER THAN THE BOTTOM
OF PACKAGE BY 0.15mm.
4. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95
REGISTRATION MS-026-AED.

100-PIN PLASTIC VQFP (VQ100)

10-44

August 6,1996 (VerSion 1.2)

~XILINX
BGA Packages -

BG225, BG352, BG432

BOTTOM VIEW

TOP VIEW

01
1~ 14 13 12 11 10 9

7

6

5

4

3

r

2

0

·1

PIN 1 I.D.

/
$000000
000000$
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
000000000000000
000000*000000
o
0
0000000
0000000
000000000000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
000000$

~

B

c
D

/cf

E
F

+

G

E1

E

J
K

L

"
N

p

~
~

R .050 TYP.

SEATING PLANE

liT"Ieee ICI At L
III

~&
-cs

y
M
B
0

MILLIMETERS

~

2.15
0,50
0,60
DIE 26,80 27,00

3,50
0,70
27,20

~

~

DliEI

MIN,

c/c/ci

21.00
1.50 ESC
0,60
0,90
0.75
0,35
~
~
0,30
~
~

M

15

e
¢b
ccc

'Jro°;.;:iC
:is

~

...

\

1-E17I¢ddd01 c I A I B I

SOLDER BALLS

N

I

0

MAX,

A
AI

t

I

¢b

NOM,

L

24.70MAX.

45 CHAM TYP.

T
E

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-151-CAL (DEPOPULATED)

225-BALL PLASTIC BGA (BG225)

August 6, 1996 (Version 1.2)

10-45

Packages and Thermal Characteristics

BOTTOM VIEW
PIN 1 I.D.

D1
el25242322!120191817161S141312UI0'31 8 7 6 ' 4 3 at

$000000000000 000000000000$ l..-0000000000000 0000000000000
0000000000000 0000000000000 e
0000000000000 0000000000000 D
0000
0000 t
0000 r
0000
0000
0000 G
0000 H
0000
0000 J
0000
0000 K
0000
0000 L
0000
0000 H
0000
0000
0000 N
E1
0000
0000 p
0000
0000
0000 T
0000
0000 U
0000
0000 v
0000
0000 v
I
0000 y
0000

"\

+

1gggggggggg
0000

0000

~

+

E

•

I

0000

0000
000 OOOOOOOO~OOOO
000 OOOOOOOO~OOOO
OOOOpOOOOO 000 OOOOOOOOCOOOO
OOOOpOOOOO 000 OOOOOOOOCOOO$

I

'0

•

I

rn

D

.
AA

Ae
AD
At

f0r-

A

P
(EXTENT OF ENCAPSULATION)

I

A2

::rt"IO~OOOO:OOO""OO
~b

fSW clcld 01cI A rBI
SOLDER BALLS

s

y
M

MILLIMETERS

0
L

A
AI
Aa
A3

MIN.

NOM.

MAX.

1.10
0.50
0.60

1.38
~

1.65
0.70
0.95

0.25

~

~

0.60

DIE 34.80 35.00 35.20
DIIE!

~

e

31.75
1.27 BSC

~

!Ilb

0.60

0.75

0.90

p

~

~

25.70
0.15

aaa

~

~

bbb

~

~

0.20

eee

~

~

ddd

~

~

0.25
0.30

M

N

0

B

T

E

SEcnON A-A
(NOT TO SCALE)

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-1S1-BAR (DEPOPULATED)

26

352-BALL PLASTIC BGA (BG352)
CAVITY DOWN

10-46

August 6, 1996 (Version 1.2)

,,~XILINX

BOTTOM VIEW

TOP VIEW
PIN 1 I.D.

. .. .,

1

.u I

$00000000000000
'000000000000000
000000000000000
000000000000000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000

i

"I r- '\

D1
III 14131111

00000000000000$
000000000000000

oooooooooooooooc

00000

000000000

oooooqOOOOOOOOO

"I

I~

00001
0000'
0000 &

0000

K

0000

J

0000
0000

L

II:

000011

0000

, E1

0000 u
0000 v
0000 v

I
I

0000

H

II

0000'
0000'

+

E

I"

0000 M
00000\11
0000 o\C
0000 AD
0000 lIE
0000 ~

"

dOOOO~ooooooooo

I-A-I

000000000000000.

+

0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
000009000000000

D

'

0000

ggggggggg~ggggg

.

~

.

~

ggggggggg~gggg~ ,.--

-

A
P

"

(EXTENT OF ENCAPSULATION)

I

A2

s

y
M
B
0
L

A
AI
A2
Aa
DIE
DIlEI

"

{lib

p
0.00.'

bbb

ccc
ddd

M

MILLIMETERS

N

0

MIN.

NOM.

MAX.

1.10
1.38
1.65
0.50
0.60
0.70
...,.,.... 0.95
0.60
...,.,.... ...,.,....
0.25
39.80 40.00 40.20
38.00 38.10 38.20
1.27 BSC'
0.60
0.75
0.90
...,.,.... ...,.,.... 26.40
...,.,.... ...,.,.... 0.15 ..
...,.,.... ...,.,.... 0.20
...,.,.... ..,.,,;. 0.25
...,.,.... ...,.,.... 0.30

.

I

I~~~am~

T

E

SECTION A-A

A3

J

(NOT TO SCALE)

NOTES:
1. ALL DIMENSIONS AND JOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-151-SAU (DEPOPULATED)

31

432-BALL PLASTIC BGA (BG432)
CAVITY DOWN

August 6, 1996 (Version 1.2)

10-47

pa6kages and Thermal Characteristics

Ceramic DIP Packages - DDS

--+---

n

+ ---/-

E1

'--1F-T--r--rt-.,.-,--,-"

U .

PIN 1 INDEX

~.
rrr------+--------,

BASE PLANESEATING PLANE
GAUGE PLANE

~

l
/I

II

\\

\1

1/

\\

1/

~

V

J .b-

81

15
MAX.

e1

;
L

A
Al
B
BI
c
D
E

EI.

el
eA
L
L2
Ql

eA

c:t-

INCHES
MIN.

MAX.

0.150
0.170
0.020
0.050
0.015
0.020
0.050
0.060
0.009
0.012
0.375
0.405
.0.320
0.300
0.280
0.300
0.100 BSC
0.300 BSC
0.125
0.150
0
0.030
0,075
0.040

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.SM-1982.
.
2. LEAD FINISH: SOLDER DIPPED
3. CONFORMS TO JEDEC MO-CIO 1-AN EXCEPT BODY WIDTH.

8-PIN CERAMIC DIP (008)

10-48

August 6, 1996 (VerSion 1.2)

~XILINX
Ceramic PGA Packages - PG68, PG84, WG84, PG120, PG132, PG144, PG156, PG175,
PG191, PG223, PG299, PG411

BODOM VIEW

TOP VIEW

D

L~GGGG
KGGGGG
JGG
HGG
GGG

I
P=l
I

+

El

EGG
INDEX PIN
D G0 G0 ~&.
cGGo
8GGGGG
A0GGGG
1 2 3 4 5

-A-

E

GG
GG

+

GG
GGGGG

GGGG~
7

8

9 10 11

LID

PIN 1 INDEX

s

y
M
B
0
L

MIN,

A

~

INCHES

NOM,

N
0

MAX,

.145
1.090 1.100 1.115
1.000 BSC
Dl/El
L
.120
.130 .140
Q
~
,045
,060
.100 BSC
e

(6,050 TYP,

T
E

~

DIE

alb

M

,016

,018
11

,020

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL" M" IS THE PIN MATRIX SIZE.
PIN C3 MAY OR MAY NOT BE ELECTRICALLY CONNECTED .

&

4. LEAD FINISH: GOLD PLATED PINS
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
5. PACKAGE CONFORMS TO JEDEC MO-66-AC

68-PIN CERAMIC PGA (PG68)

August 6, 1996 (Version 1.2)

10-49

Packages and Thermal Characteristics

BOTTOM VIEW

TOP VIEW
~_______ D__~-A~-~~

I

~

I

E

o0 0
0

0

0

+

2 3

000
00
0
00
00000
0000$

+

----tt---_t_

-JNDEX PIN

00 /&
C000 0
800000
A00000
D

1

E -+------ill--E1

4 5

7

8

9 10 11

LID

PIN 1 INDEX

s
y

INCHES

M
B

0
L

MIN,

NOM,

N

MAX,

.145
1.090 1.100 1.115
DllEl
1.000 BSC
,120
L
.130 .140
Q
~
,045
,060
,100 BSC
EO'
A

~

¢,050 TYP,

0
T
E

~

DIE

¢b
M

,016

,018

11

,020

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1982
2, SYMBOL "M" IS THE PIN MATRIX SIZE.
PIN C3 MAY OR MAY NOT BE ELECTRICALLY CONNECTED,
4, CONFORMS TO JEDEC MO-066-AC
5, LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN,)
- MILITARY (50 MICROINCHES MIN,)

.&:.

84-PIN CERAMIC PGA (PG84)

10-50

August 6; 1996 (Version 1,2)

1:XllINX

BOTTOM VIEW

TOP VIEW

D
L

G

-I
LID

00000
0
00
00
000

H

I-A-I

I

!Xl

I

E1

E

000
00

E

D
C

\IlAOO
UV LENS

PIN 1 INDEX

s

y
M

INCHES

N

NOM,

0
T
E

B

0
L

A

DIE

MIN,
~

1.100

1.000

D!/E!
L

.120

Q

,045

.145
1.135

BSC

,130

.140
,06.0

~

,100 BSC

e
11'>10

~

1.090

MAX,

,016

,018

M

,020

I
NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
~. CONFORMS TO JEDEC MO-066-AC
&. PIN C3 MAY OR MAY NOT BE ELECTRICALLY CONNECTED.
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)

11

84-PIN WINDOWED PGA (WG84)

August 6,1996 (Version 1.2)

10-51

Packages and Thermal Characteristics

BOTTOM VIEW'

TOP VIEW'

1------D1---.............,~

(£)(V@@@@
@@@@@®
M@®@@@@ @@@@~@
l@@@@@@ 0@@@0@
K @@@ r====!===",,@ @ @
J @@@
@@@
H @@@
@0@

[:=J

N

-lI-+:l+:1-~--

+

----1H"'*~Ht-

+

E

E1

@@@
@@@

J==f===I==='@ @ @

~

@@@@@@
@@@@®@
@@@@@®
8

9

10

11

12

13

LID

PIN #1 INDEXI~

I

SEATING PLANE

,

[=E]

L

ttrtflTIH
!" t f
~

j til, ~
Q ,050 TYP,j

I

1I

Q1

f

¢b-l

s

y
M
B
0
L

INCHES
MIN,

NOM,

N

MAX,

~
,145
1.360 1.380
1.200 BSC
D!/E!
L
.140
.130
.120
Q ,045
~
,060
~
~
Q! ,025
.100 BSC
e

0
T
E

~
A
DIE 1.340

¢b
M

,016

,018
13

,

,020

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AE
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)

120-LEAD CERAMIC PGA (PG120)

10-52

August 6; 1996 (Version 1.2)

~XIUNX

BOTTOM VIEW'

TOP VIEW'

--Dl---I"I

f-I"

Pl\&@@@@@@ @@@@@@e t @@@@@@l@
u@@)@@@@@ @@@@@@@
l@@@
@@@
K @ @ @
@@@
J@@@
@@@
H@@@
@@@
N@@@@@@@

+

G@@@

····u
r

@@@

U-It----+
...J
@@@
@@@

E@@@

I

C@@@@

@@@@@@@@@

@@@

B@@@@@@@@@@@@@@
AJi!@@
@@@@@@@@@41
1

:J'

•

5

7

8

•

10

11 12

13

14

PlN 1 INDEX

LID

s

y
M
B

0
L

A

INCHES

MIN,

NOM,

~

~

DIE 1.440

1.460

MAX,
.145
1.480

1.300 ESC

D!/EI
L

.120

.130

.140

Q

,045

~

,060

QI

,025

~

~

.100 ESC

e
Illb

,016

,018

M

I

N

0
T
E

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AF
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MiLITARY (50 MICROINCHES MIN.)

,020

14

132-PIN CERAMIC PGA (PG 132)

August 6,1996 (Version 1.2)

10-53

PaCkages and Thermal Characteristics

TOP VIE\,!

BOTTOM VIE\,!

~

DI

I

I

R .®®®®®®~ ~®®®®®®.
p ®®®®®®®~ ~®®®®®®®
N ®®®®®®®~ ~®®®®®®®
M
L

K
J

G

®®®
®®®
®®®
®®®
"''''''''

f-

¢,039 NOMINAL
UV LENS

®®®
®®®
®®®
®®®

+

@@@

""""""
@@@

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9

10 11 12 13 14 15

LID

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I

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PLANE~r=c=J~'QdJJi~J!i~~1m~ln~~f~'~H'rrHiil?-~tr~
.

¢,050 TYP,

I-~

J

L

¢b

s
Y
M
B
0
L

INCHES

MIN,

NOM,

N

MAX,

A
~
~
.145
DIE 1.540 1.560 1.580
1.400 BSC
DIIEI
L
.120
.130 ,140
Q

,050

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M

~

,060

.100 BSC

e

,016

,018
15

,020

0
T
E

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE .
3. CONFORMS TO JEDEC MO-067-AG
4, LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN,)
- MILITARY (50 MICROINCHES MIN,)

144-PIN WINDOWED PGA (PG144)

10-54

August 6, 1996 (Version 1.2)

~XILINX

BOTTOM VIE\v'

TOP VIE\v'

I-----DI---~

D

-

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"I
'~00000000000000~

'0e00000000000000
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.000
000
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000
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000
K 000
000
J 000
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'000
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,000
000
0000
000
c00000·0000000000
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+

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P
PN 1 I N D E X /

LID

R8

SEATING PLANE ---==~::::::j~~ifilT""'IF!FiiF"'iilFlfn~~

s

y
M

B
0
L

A

INCHES

MIN,

NOM,

N

MAX,

~
.145
1.660 1.680
1.500 BSC
,140
.120
.130
~

DIE 1.640
DliEI

L
Q

,045

~

,060

QI

,025

~

~

.100 BSC

e
(Die
M

,016

,018

,020

I

0
T
E

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067 -AH
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)

16

156-PIN CERAMIC PGA (PG156)

August 6, 1996 (Version 1.2)

10-55

Packages and Thermal Characteristics

BOTTOM VIEW'

TOP VIEW'

1f-------DI-----I
1

$00000000000000E!l'0®000000000000@0
.0000000000000000
.0000000000000000
.000
000
l000
000
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c00000·0000000000
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+
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IT

+

E

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LlDJ

I

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j I lif~ ~ ~ m1i~rm ~ ~ rir
,050

JL

TYP,~ ~

¢bj
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s
y

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M
B

0

Ql

N

0

L

MIN,

A

~

NOM,

MAX,

~
.145
1.660 1.680
1.500 BSC
DliEI
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.120
.130
.140
Q ,045
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QI ,025
~
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e
¢b ,016
,018
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M
16

DIE 1.640

T
E

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AH
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICRO INCHES MIN.)
- MILITARY (50 MICROINCHES MIN,)

175-PIN CERAMIC PGA (PG175)

10-56

August6; 1996 (Version 1.2)

~XIUNX

BOTTOM VIEW'

TOP VIEW'

DI

I

D

I

v@@@@@@@@@ @@@@@@@@@
u@S@@@@@@@ @@@@@@@~@
T@@@@@@@@@ @@@@@@@@@
R@@@@
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A @@@@@ @@ @@@@@@@@@

EI

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2'

•

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10111213 , . " " 17"

-

+

E

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PASS
PADS

.& CA PAJfoR

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SEATING PLANE

S
Y
M
B
0
L

INCHES

N

0

MIN,

NOM,

MAX,

,115
,145
1.860 1.880
1.700
BSC
DllEl
,120
,130 ,140
L
A

~

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Q

,045

~

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Ql

,025

~

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e
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,016

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M

18

,020

T
E

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982.
2. SYMBOL .. M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AK
BYPASS CAPACITOR PADS - GOLD PLATED.
MAY OR MAY NOT BE PRESENT ON ALL PACKAGES.
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)

.&

191-PIN CERAMIC PGA (PG191)

August 6, 1996 (Version 1.2)

10-57

Packages and Thermal Characteristics

BOTTOM VIEW'

TOP VIEW'

1~------D1------~1
V@@@@@@@@@@@@@@@@@@r-

c::::::J

u@~@@@@@@@@@@@@@@~@

T@@@@@@@@@@@@@@@@@@
.@@@@@@@@@@@@@@@@@@
p@@@@
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N@@@@
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.@@@@
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L@@@@
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K @@@@
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J@@@@
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H@@@@
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+

El

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7

8

9

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1 2

"'1 I"

~

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'I

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10 11 12 13 14 15 10 17 18

~

PASS
CAPAC! TOR PADS

LID.-I

PIN 1 INDEX

J

I

L

==QJ~f~'n
U~ IMTunnT~"i~n~Ti~~n~T~nHTnn~~~*t~rQl

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---II-cv-J

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r-~~~~~~~

s
y

M

B
0
L

MIN,

A

~

INCHES

N

NOM,

0
T
E

MAX,

,115
.145
1.860 1.880
1.700
BSC

DIE 1.840
Dl!El
L

.120

Q

,045

Ql

,Q25

M

.130

.140

~

,060

~

~

.100 BSC

e

¢b

j

,016

,018
18

,020

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1982
2, SYMBOL "M" IS THE PIN MATRIX SIZE.
3, CONFORMS TO JEDEC MO-067-AK
&. BYPASS CAPACITOR PADS - GOLD PLATED.
MAY OR MAY NOT BE PRESENT ON ALL PACKAGES.
5. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICRO INCHES MIN.)
- MILITARY (50 MICROINCHES MIN ..)

223-PIN CERAMIC PGA (PG223)

10-58

August 6, 1996 (Version 1.2)

~XILINX

BOTTOM VIE \v

TOP VIE\v

D1

,

•

I
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D

I

=

@@@@@@@@@@ I-@~@@@@@@@@ @@@@@@@@~@

@@@@@@@@@@ @@@@@@@@@@
u @@@@@@@@@@ @@@@@@@@@@
T @@@@@@@@@@ @@@@@@@@@@
R @@@@@
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H @@@@@
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r @@@@@
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• @@@@@@ 0 @@@ @@@@@@@@@@
c @@@@@@ @@@ @@@@@@@@@@
• @~@@@ @@@@ @@@@@@@@~@
A @@@@O@@@@ @@@@@@@@@@ I-v

+
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,

I

,

2:J'

7

• • ,.

If

S
Y

MIN,

A

~

I

0

T

NOM,

MAX,

.145
2,040 2,060 2,080
1.900 BSC
DIIEI
L
.120
.130 .140
~

DIE

,045
,025

~

,060

~

~

.100 BSC

e
M

+

N

INCHES

B
0
L

¢Io

E

PIN 1 INDEX

M

Q

I
/Xl
I

""1+"10171819,.

LID

QI

RB

,016

,018
20

,020

E

5

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL" M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO-067-AM
4. LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)
OPTION - HEAT SINK MAY BE ADDED FOR HIGH POWER
DEVICES BUT DIMENSION 'A' REMAINS .145" MAX.

1&

299-PIN CERAMIC PGA (PG299)

August 6, 1996 (Version 1.2)

10-59

Packages and Thermal Characteristics

BOTTOM VIE'w'

TOP VIE'w'
- -

D

·1

=

IT

+

E

P

,050X45+CHAM, TYP,

PINIINDEX~

LID

L

A3

SEATING PLANE

83

Q

HEA TSINK

JIf 'fm~~mllml~~lIIlm~~~

,050X,025 TYP,

r6b

j

L

s

y
M

B
0
L

INCHES

N

0

MIN,

NOM,

MAX,

~
~
,145
,015
,020
,025
DIE 2,040 2,060 2,080
1.900 BSC
DI/EI

A

A3

L

.170

Q

,045
,025

QI

M
!Ilb

,016

.180

.190

~

,060

~

~

39
,018

T
E

NOTES:
1. ALL DIMENSIONING AND TOLERANCING CONFORM
TO ANSI Y14,5M-1982
3. SYMBOL "M" IS THE PIN MATRIX SIZE.
4. CONFORMS TO JEDEC MO-128.
5, LEAD FINISH: GOLD PLATED
- COMMERCIAL (35 MICROINCHES MIN.)
- MILITARY (50 MICROINCHES MIN.)

,020

411-PIN CERAMIC PGA (PG411)

10-60

August 6, 1996 (Version 1.2)

~XILINX
Ceramic Brazed QFP Packages -

CB100, CB164, CB196, CB228

NON LID SIDE

LID SIDE

r

E2

-+Ol----~

L

-t-c
SECTION P-P

DETAIL 'A'

~
sjL
DETAIL '8'

NOTES:

s

y
M

B
0

MIN.

NOM.

A

~

~

AI
A2

~

~

~

~

.135
.115
.020

.006
.005
.740

.008
.006
.750

.012
.009
.765

L

B

c

1. ALL DIMENSIONING AND TOLERANCING CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "N" IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICROINCHES MINIMUM)
OVER NICKEL PER MIL -1-38535

INCHES

DliEl
D2/E2

F
H

J
K
L
L1

L2

MAX.

I

.600 SSC
.425 I .450 .475
2.300 SSC
.030
.035
.040
~
~
.020
~

~

2.490 2.500
1.480 1.500

N

2.580
2.510
1.520

100

100-PIN CERAMIC BRAZED CQFP (CB100)
(XC3000 VERSION)

August 6, 1996 (Version 1.2)

10-61

Packages and Thermal Characteristics

NON LID SIDE

LID SIDE

r

E2~'---

l

-I-c
SECTION P-P

I

~

DETAIL 'A'

B-Jl-

DETAIL 'B'

NOTES:

s

y

c

MIN.

NOM.

A

~

~

L

MAX.

At

~

~

A2

~

~

.135
.115
.020

B

.006
.005

.008
.006

.012
.009

c

1. ALL DIMENSIONING AND TOLERANCING CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "N" IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICROINCHES MINIMUM)
OVER NICKEL PER MIL-I-38535

INCHES

M
B

DlIEI .740
.750 .765
D2/E2
.600 BSC
F
.425 .450 .475
H
2.300 BSC
J
.030
.035
.040
K
~
~
.020
L
2.580
~
~
L1 2.490 2.500 2.510
L2 1.480 1.500 1.520
N
100

100-PIN CERAMIC BRAZED CQFP (CB100)
(XC4000 VERSION)

10-62

August 6, 1996 (Version 1.2)

~XIUNX

NON LID SIDE

SECTION p-p

rI-M,
~
DETAIL 'A'

,2
DETAIL '8'

sy
B
D

l.

A
AI
A2
B

NOTES:

c
DlIEI

1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Yl4.5M-1982
2. SYMBOL "Nil IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICROINCHESMINIMUM)
OVER NICKEL PER MIL-1-38535

INCHES

M

D2/E2
F
H
J,

K
L
L1
L2
N

MIN.

NOM.

-.... ,..,.,
-.... -....
-.... ,..,.,

,..,.,

MAX.
.130
.110
.020

I

.007
.012
.005
.006 .009
1.120 1.130 1.145
1.000 BSC
.175
.2QO .225
2.300 BSC
.030 .035 .040
.020
~
2.580
2.485 2.500 2.505
1.480 1.500 1.520

-....

-.... -....
1~4

164-PIN CERAMIC BRAZED CQFP (CB164):
(XC3000 VERSrON)
.

August 6,1996 (VerSion 1:2)

10>-63

Pac~ges and Thermal Characteristics

NON LID SIDE

J

L
K

SECTION p-p

. DETAIL 'A'

sI

DETAIL '8'

sy
B

L

MIN.

NOM.

A
AI
A2

-;.,....

".,.,

B

NOTES:

C

1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "N" IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICROINCHES MINIMUM)
.
OVER NICKEL PER MIL-1-38535

INCHES

M

c

DIIEI
D2/E2
F
H

J
K

L
L1

L2
N

MAX.

.130
".,.,
".,.,
,110
".,.,
".,.,
.020
".,.,
,007
,012
,005
.006
,009
1.120 1.130 1.145
1.000 BS,C
,175
,200 ,225
2.300 BSC
,030
,035 ,040
".,.,
".,.,
,020
".,.,
".,.,
2580
2.485 2,500 2,505
1.480 1.500 1.520
164

164-PIN CERAMIC BRAZED CQFP (CB164)
(XC4000 VERSION)

10-64

August.6, 1996 (Vel'$ion 1,2)

~XILINX

LID SIDE

I I

n

NON LID SIDE

SECTION p-p

jAl A
A2

s

y
M

t t

B
0

DETAIL 'A'
DETAIL '8'

NOTES:

1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "N"IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICROINCHES MINIMUM)
OVER NICKEL PER MIL -1-38535

INCHES

L

MIN.

A
Al
A2

"""'" ,090
"""'"
"""'" """'
,007
"""'""

B

NOM.

,081

MAX.

I

.130
.105
,020

. ,012
,009
.006
DlIEl 1.336 1.350 1.364
D2/E2
1.200 ESC
,225
,200
F
.175
H
2.,300 ESC
J
,030
,035
,040
K
,020
L 2,500
2,580
C

,005

L1

"""'" """'"
"""'"
2.470 2,500

L2

1.700

1.720

N

2,530
1.740

196

196-PIN CERAMIC BRAZED CQFP (CB196)

August 6, 1996 (Version 1.2)

10-65

packages and Thermal Characteristics

LID SIDE

NON LID SIDE

r
E2

1
SEE DETAIL 'A'
SEE DETAIL '8'

SECTION p-p

DETAIL 'A'

a

B~lDETAIL '8'

s

y
M

B
0

MIN.

NOM.

MAX.

A

~

~

Al

~

~

A2

~

~

,130
,110
,020

L

B

c

NOTES:

INCHES

~

,007
,005

D1IEI 1.534

1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. SYMBOL "N" IS THE NUMBER OF TERMINALS.
3. PACKAGES ARE SHIPPED UNFORMED.
4. LEAD FINISH: GOLD (50 MICR01NCHES MINIMUM)
OVER NICKEL PER MIL -1-38535

D2/E2

,006

,012
,009

1.550

1.570

F

1.400 BSC
,150 ·.175
.125

H
J

,030

K
L

2,300 BSC
,035
,040

~

~

,020

L2

2,580
2.480 2,500 2,530
1.900 1.920 1.940

N

228

L1

~

~

228-PIN CERAMIC BRAZED CQFP (CB228)

10-66

August 6, 1996 (Version 1.2)

~XILINX
CLCC Packages -

CC20

TOP VIEW

BOTTOM VIEW

"'"

r
\

.020X45' CHAM.

SEE DETAIL 'P

SEATING PLANE

/

R .010 MIN

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. LEAD FINISH: SOLDER DIP
3. LEAD WIDTH DIMENSION INCLUDES LEAD TRIM OFFSET.
4. "N" IS THE NUMBER OF TERMINALS.

i----D1---00i

;

MIN

NOM

MAX

A
A1

.140
.080

.150
.090

.155
.100

C

.006

.007

.010

D/E

.395

.400

.405

01/El

.370

.375

.380

02/E2 .145

.160

.175

D3/E3

INCHES

I

.200 REF.

e

.050 Bse

N

20

20-PIN CLCC .(CC20)

August 6, 1996 (Version 1.2)

10-67

Packages and Thermal Characteristics

Plastic PGA Packages -

PP132, PP175

BOTTOM VIE\J

TOP VIE\J

t------Dl-----l

LID

p

'*@@@@@@@@@@@@*l
N@@@@@@@@@@@@@@
o@@@@@@@@@@@@@
L@
@
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K@@
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J@@@
@@@

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

J

El

0

0

0

0

0

0

H

0

0

0

0

0

0

G

0

0

0

0

0

0

r

0

0

0

0

0

0

0

0

0

0

0

0

,

0

0

0

0

0

0

0

0

0

0

c

0

0

0

0

0

0

0

0

0

0

0

0

0

0

13

12

11

10

H

+

@@@

G@@@
F@@)@
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D@)@@

C@@@@@@@@@@@@@@
B@@@@@@@@@@@@@@
A@@@@@@@@@@@@@*
1 2
3 " 5 a 7
8 9 10 11 12 1 14

..

+
0

,

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0

0

0

0

,
,
L

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0

0

0

0

0

0

0

0

0

0

0

0

0

0

"7

,039X4S' TYP,

SEATING PLANE

_____&;~~iF~imiFwrTi?=i~ER8~I
L

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s

y
M
B
0
L

INCHES
MIN,

NOM,

MAX,

A ~ ~
,165
Al .110
.120
.135
DIE 1.440 1.460 1.480
1.300 BSC
DIIEI
L .125
~
.150
Ql

,025

¢b
M

~

,070

.100 BSC

e
,016

,018

,020

NOTES:
1, ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14,5M-1982
2, SYMBOL "M" IS THE PIN MATRIX SIZE.
3, CONFORMS TO JEDEC MO-083-AF"
4, LEAD FINISH: SOLDER (90j10-Sn Pb) 50microinches
MINIMUM COAT.

14

132-PIN PLASTIC PGA (PP132)

10-68

August 6, 1996 (Version 1.2)

E:XILINX

TOP VIEW

BonOM VIEW

~1'-------D----~G8~-~'1

1------01-----1
UD

T@00000000000000@

0

0

0

0

0

0

0

0

0

0

0

0

0

0

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T

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0

00

0

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0

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0

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0

0

0

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R

p

0

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0

0

0

0

0

0

o.

0

0

0

0

0

0

0

p

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

•

0000000000000000
.0 00000000000000
.00
.000
L 000
000
K000
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000
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@0000@.00000@00@

+

E

H

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•
,

0·. 0

0

0

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0

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r

0

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+
o.

0

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0

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0

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a

0

0

"

"

1. ,.

12

11 1.

:.

0

L

K

"
<
D

0

....,. ~••
0

PIN 1 INDEX

sy.
M
B
IJ
L

INCHES:

MIN,

A ...,.,..,
AI ,110
DIE 1,640

NOM,

MAX,

I

N
IJ

T
E

...,.,..,

,165
,120
,i35
1.660 1.680
l.~OO BSC
DiIE!
L
,125
.150·
...,.,.., ,070
QI
.025
.100 BSC
e
9lb ;016
;020
.018
M
16

...,.,..,

. NOTES:
1. All DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982.
2. SYMBOL "M" IS THE PIN MATRIX SIZE.
3. CONFORMS TO JEDEC MO'--083-AH
4. LEAD FINISH: SOLDER (90/10-Sn Pb) 50microinches
MINIMUM COAT.

175---PIN PLASTIC PGA (PP175)

August 6, 1996 (Version

1;~)

10-69

Pae:'-ges 'and Thermal Characteristics

Windowed CLCC Packages - WC44, WC68, WC84

BOTTOM VIEW'

TOP VIE",

~~------Dl--------~

.040X45'

s

y

DIMENSION IN INCHES

M

e

0
L
A

MIN

NOM

MAX

MIN

NOM

MAX

.155

.172

.190

.155

.172

.190

.172

.190

AI

.090

---

.120

.090

---

.155

.120

.090

---

.120

e

.026
.017

.032
.022
.012
.695

.026
.017
.006
.985
.930
.«0

.032
.022
.012

.026
.017
.006
1.185
1.130
.540

.028
' .019
,.007

.032
.022
.012

bl
c
DIE
D1/El
D2/E2
D3/E3

.006
.685

.690

.630
.290

•

N
W

.028
.019
.007

"

.650
.305
.500 REf.
.050 esc
«
'.350

.665
.320

.028
.019
.007
.990
.950
.455
.800 REP.
.050 esc
66
•.390 REf.

.995
.965
.470

MIN

NOM

MAX

1.190
1.195
1.150
1.165
.555
.570
1.000 REf•
,050 SSe
8§

.450 SQ. REf

NOTES:
1. AU. DIMENSIONS AND TOLERANCES CONFORM TO ANSI YI4.5M-1982.,
2. LEAD WIDTH DIMENSION INCLUDE LEAD TRIM OFFsET and LEAD FINISH, '
LEAD FiNISH: (HOT SOLDER DIP)
3. SYMBOL 'N' IS THE NUMBER OF TERMINALS.
4. SYMBOL 'W' IS THE DIMENSION OF THE EPROM WINDOW.
5. THESE PACKAGES MEET DIMENSIONAL REQUIREMENTS
OF JEDEC MO-087, VARIATIONS - AB(WC44); AO(WC68); AE(WC84).

44, 68, and 84-PIN WINDOWED CLCC (WC44, 68 and 84)

10-70

AugustS, 1995(Version 1.2)

~XILINX
Metal Quad Packages -

MQ208, MQ240

TOP VIEW

PIN 1 1.0.

BOTTOM VIEW

'j

2J"

1------D1------i

~

VENT SEAL

E3

~
SEE DETAIL 'A'

(J

BLACK ANODIZED
ALUMINUM BODY

~IIIIUIDDIIIIDIIIDlIIIIII~Af
-.j

1
M
B
0
L

MIN,

NOM,

MAX,

3.50

3.68

4.10

Ai

0.25

0.38

0.53

A2

3.20

3.40

3.60

30.35

30.85

30.60

D1/E1 27,58 27,64 27,79
25,50 REF,

D3IE3

L

0.50

e

0.60

0.75

0,50 ESC,

b

0.17

0.22

0.27

c

0.09

0.20

ccc

---

----

cicici

E.Qd

MILLIMETERS

A

DIE

+

E1

101 eeel cl

A1

I

1.48 MAX.

DETAIL 'A'

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM TO
ANSI Y14.5M-1982.
2. DIMENSIONS "D1" AND "E1" DO NOT INCLUDE EPOXY
PROTRUSION. ALLOWABLE PROTRUSION SHALL NOT EXCEED
O.25mm ON EACH SIDE.
3. DRAWING CONFORMS TO JEDEC MO-143-FA1
EXCEPT BODY DIMENSIONS "D1/El" and COPLANARITY.
4. LEAD FINISH: SOLDER PLATE

DolO

0.08

208-PIN METAL QUAD (MQ208)

August 6, 1996 (Version 1.2)

10-71

Packages and Thermal Characteristics

TOP VIE'W

BOTTOM VIE'W
Dl

S.)
181

1IIIIIiIIUllllllllilillilifI

1

180

J
E3

J
VENT SEAL

SEE DETAIL 'A'

~

B
L

MIN.

NOM.

/

.,

80

l±J

MAX.

3.45

~

4.10

AI

0.25

0.38

~

Ae

3.40

3.50

10

3.30
0.17

~

0.27

c

0.09

~

0.20

DIE

34.35

34.60

34.85

DI/EI

31.59

31.64

31.79

D3 /E 3
e

120

MILLIMETERS

A

L

121

BLACK ANODIZED
ALUMINUM BODY

lI1I11U'IIDI'llllllllmjIlD'BUI'_~
M

+

El-

29.50 REF.
0.50

0.60
0.50 BSC.

ddd

0.08

ccc

0.10

0.75

DETAIL 'AN

NOTES:
1. ALL DIMENSIONS AND TOLERANCES CONFORM
TO ANSI Y14.5M-1982
2. DIMENSIONS "Dr AND "E1" DO NOT INCLUDE EPOXY
PROTRUSION. ALLOWABLE PROTRUSION SHALL NOT EXCEED
O.25mm ON EACH SIDE.
3. CONFORMS TO JEDEC .MO-143-GA, EXCEPT IN
BODY DIMENSIONS AND COPLANARITY.
4. LEAD FINISH: SOLDER PLATE

240-PIN METAL QUAD (MQ240)

10-72

August 6, 1996 (Version 1.2)

Testing, Quality, and Reliability

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-8ased FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability

12 Technical Support
13 Product Technica' Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

Testing, Quality, and Reliability
Table of Contents

Quality Assurance and Reliability
Quality Assurance Program ..........................................................
Device Reliability. . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Description of Tests .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Die Qualification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Package Integrity and Assembly Qualification ...............•. ",' ...••........•....
Testing Facilities ............................................... : .... '.......... '.....
Data Integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Memory Cell Design in the FPGA Device .....................................' .....
Electrostatic Discharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Latchup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
High Temperature Performance .......................................................

11-1
11,-2
11-2
11-2
11-2
11-3
11-6
11-6
11-7
11-8
11-8

Quality Assurance and ReliabHity
June 1, 1996 (Version 1.0)

Quality Assurance Program
All aspects of the Quality Assurance Program at Xilinx have
been designed to eliminate the root cause of defects, rather
than to try to remove them by inspection. A quality system
was put in place which is in full compliance with the requirements of 1809002. Xilinx was found to be in full compliance
of the requirements of 1809002:1994 by an independent
auditor in October, 1995. At that time Xilinx was registered
.for "the manufacturing and testing of programmable logic
devices".
The aspects of ISO compliance in place atXilinx include
the following seventeen points:
•

Management Review: a comprehensive system of
management attention and direction for all aspects of
company performance that directly affect our
customers. These include (among others) Xilinx
performance in the areas of Quality, Reliability and OnTime Delivery. Management assures that this quality
policy is understood, implemented and maintained at all
levels in the organization.
• Quality Systems: are in place to ensure that product
conforms to customer specifications. These systems
facilitate, measure and continuously improve Xilinx
performance in those areas that affect customer
satisfaction. Xilinx remains committed to achieving
100% customer satisfaction.
• Contract Review: is conducted to ensure each
contract adequately defines and documents
requirements, that differences between customer and
Xilinx standard specifications are mutually satisfactorily
resolved, and that Xilinx has the capability to meet
contract requirements.
• Document Control: procedures are established and
maintained to control all documents and data that relate
to the performance of Xilinx business and processing
requirements. All organizations who need access t~
such documentation during the performance of their
functions are assured availability of the latest,
controlled versions of that documentation.
• Purchasing: procedures are in place to ensure that all
purchased products conform to the specified
requirements. As Xilinx is a "fabless" manufacturing
company, special attention is paid to our subcontract
partners. They are required to demonstrate the type of
control and capabilities that our customers require. All
key Xilinx subcontract partners are 180 certified.

June

t, 1996 (Version 1.0)

Product Identification &Traceability: is maintained
throughout the manufacturing process. Traceability back
to the starting materials is available through unique
product identification techniques and markings
throughout the manufacturing process.
• Process Control: is assured by identifying and
controlling those processes that directly affect the
quality of our products, whether those processes are
performed directly by Xilinx, or by our subcontract
partners.
• Inspection &Test: is performed to ensure that
incoming product is not used or processed until it has
been verified as conforming to required specifications.
This inspection is done. jointly by Xilinx and by its
subcontract partners.
• Inspection, Measuring and Test Equipment: is
calibrated in conformance with the requirements of Mil
Ref45662 and/or other international standards.
Equipment is maintained in such a manner to ensure
that measurement uncertainty is known and is
consistent with specification requirements.
• Inspection &Test Status: of product is uniquely
identified throughout the manufacturing process both at
Xilinx and at our subcontract partners; Records are kept
to identify the authority responsible for the releaSe of
conforming production.
• Control of Non-Conforming Product: is assured
through disposition procedures that are defined in such
a manner as to prevent the shipping of non-conforming
products, The responsibifity and authority for the
disposition of such products are well defined.
• Corrective Action: processes are documented and
implemented to prevent the recurrence of
nonconforming product. These processes are the key to
implementing the Xilinx strategy of eliminating the root
causes of nonconformity, rather that to apply inspection
to try to remove nonconformity.
• Handling, Storage, Packing & Delivery: procedures
are defined and implemented to prevent damage or
deterioration of product once the manufacturing
process is complete.
• Quality Records: procedures are established and
maintained for the identification, collection, indexing,
filing, storage, maintenance and disposition of quality
records.
• Internal Quality Audits: are carried out to verify
whether quality activities comply with planned
arrangements and to determine the effectiveness of the
quality system. These audits are regularly
•

11-1

I

Quality Assurance and Reliability

supplemented by quality audits performed by our
customers, and by.our independent ISO auditors.
• Training: procedures have been established and are
maintained to identify the training needs of all personnel
affecting quality during the production of Xilinx
products. Personnel performing such activities are
qualified based lIpon appropriate education, training
and/or experience.
• Statistical Techniques: are in place at Xilinx and at our
subcontract partners for verifying the acceptability of
process capabilities and product characteristics.

Description of Tests
Die Qualification
1. High Temperature Life: This test is performed to evaluate the long-term reliability and life characteristics of the
die. It is defined by the Military Standard from which it is
derived as a "Die-Related Test" and is contained in the
Group C Quality Conformance Tests. Because of the
acceleration factor induced by higher temperatures,
(typically 125°C and/or 145°C) datarepresenting a large
number of equivalent hours at a normal temperature of
25°C can be accumulated in a reasonable period of
time.

These key requirements are in place at Xilinx and at our
subcontract partners to ensure our ability to achieve customer satisfaction through the on-time delivery of quality
products that meet customer requirements and are reliable.

2. Biased Moisture Life: This test is performed to evaluate the reliability of the die under conditions of long-term
exposure to severe, high-moisture environments that
could cause corrosion. Although it clearly stresses the
package as well, this test is typically grouped under. the
die-related tests. The device is operated at maximumrated voltage, 5.5 Vdc, and is exposed to a temperature
of 85°C and a relative humidity of 85% throughout the
test.

Device Reliability
Device reliability is'often expressed in a measurement
called Failures in Time (FITs). In th.is measure one FIT
equals one failure per billion (10 9 ) device operating hours.
A failure rate in FITS must include the operating temperature to be meaningful. Hence failure rates are often
expressed in FITS at 70°C (or some other temperature in
excess of the application).

Package Integrity and Assembly
Qualification

Since one bill.ion hours is well in excess of 100,000 years,
the FIT rate of modern ICs can only be measured by accelerating the failure rate by testing at a higher junction temperature (usually 125°C or 145°C). Extensive testing of
Xilinx devices (performed on actual production devices
taken directly from finished goods) has been accomplished
continuously since 1989 and reported quarterly. Quarterly
reports on the reliability of Xilinx products are available
through your Xilinx sales representative. During the .Iast two
years, over 20,000 devices have accumulated a total of
over 36,000,000 hours of both static and dynamic operation
at 125°C (equivalent) to yield the FIT rates shown in
Figure 1.

1. Unbiased Pressure Pot: This test is performed at a
temperature of 121°C and a pressure of 2 atm Of saturated steam to evaluate the ability of the plastic encapsulating material to resist water vapor. Moisture
penetrating the package could induce corrosion of the
bonding wires and nonglassivated metal areas of the die
(bonding pads only for FPGA devices). Under extreme
conditions, moisture could cause drive-in and corrosion
under the glassivation. Although it is difficult to correlate
this test to actual field conditions, it provides a wellestablished method for relative comparison of plastic
packaging materials and assembly and molding techniques.

Failure Rate in FITs

@

70°C

50
40
Q)

til

II:
~

30
20

.2

'ai
LL

10
0

-.10
6/94

9/94

10/94

3/95
Time

6/95

9195

12/95
X5977

Figure 1: Failure Rates in FITs

11-2

June 1, 1996 (Version 1.0)

~:XILINX
2, Thermal Shock: This test is performed to evaluate the
resistance of the package to cracking and resistance of
the bonding wires and lead frame to separation or damage,.lt involves nearly instantaneous change in temperature from -65°C to + 150°C (condition "C"),
3, Temperature Cycling: This test is performed to evaluate the long-term resistance of the package to damage
from alternating exposure to temperature extremes, The
range of temperatures is -65°C to +150°C (condition
"C"), The transition time is longer than that in the Thermal Shock test but the test is conducted for many more
cycles,
4, Salt Atmosphere: This test was originally designed by
the US Navy to evaluate resistance of military-grade
ship-board electronics to corrosion from sea water. It is
used more generally for non-hermetic industrial and
commercial products as a test of corrosion resistance of
the package marking and finish,

5, Resistance to Solvents: This test is performed to evaluate the integrity of the package marking during exposure to a variety of solvents, This is an especially
important test, since an increasing number of boardlevel assemblies are subjected to severe conditions of

automated cleaning before system assembly, This test is
performed according to the methods specified by MILSTD-883,
6, Solderability: This test is performed to evaluate the solderability of the leads under conditions of low soldering
temperature following exposure to the aging effects of
water vapor.
7, Lead Fatigue: This test is performed to evaluate the
resistance of the completed assembly to vibrations during storage, shipping, and operation,

Testing Facilities
Xilinx has complete capability to perform High Temperature
Life Testing, Thermal Shock, Temperature Cycling, Biased
Moisture Life Test, Unbiased Pressure Pot, Solderability
and Hermeticity, as well as complete Failure Analysis in
house, Table 1 and Table 2 show typical qualification
requirements for new and/or changed process flows,
Table 3 is a list of current failure analysis capabilities, These
laboratories are dedicated exclusively to increasing customer satisfaction through continuous improvements in our
processes and technologies,

I

June 1, 1996 (Version 1,0)

11-3

Quality Assurance and Reliability

Table 1: Plastic Package/Product Qualification Requirements
New Assy Techniques (Mat'I/ProcessiMethod
Test Description
(note 1)

Test
Seq

Acc#
S.Size
(note 2)

New
Assy
Plant

B1

• Phy. Dimension

0/5

X

B2

• Resist. to Solvents

0/3

X

B3

• Solderability Test (note 7)

0/5

X

B4

Solder Heat Test (Optn'l)

0/15

New
New
Pkg
Pkg
Type I Type II
(note3) (note4)

X

New
Lead
Die
Pkg
Frame Attach
Type
III LF
Design
(noteS)

X
X

)(

X

X

Auto Clave (SPP)(Optn'l) 0/76

0/76

X

X

• Ball Shear/Bond Pull (note 7)

0/5

X

X

B7

•• X-Ray (note 7)

0/5

X

X

X

X

B8

• SAT/Dye Pen Test (note 7)

0/10

X

X

X

X

B9

• Adhesion of UFinish (Optn'l)

X

X

0/3

X

B10 • External Visual (note 7)

0/25

X

X

X

B11

0/5

X

X

X

0/5

X

B13 Flammability Test (note 7)

OfT6

Cl·B Low Temp Life Test (note 7)

0/22

OfT6

New
Fab
Proc

X

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X

X

X
X

X

X

X

X

X

X

Full
Qual

X

X

X

X

New
Lead
Finish Device
Mask
(noteS)

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

Per lot

Cl-A High Temp Life Test

Mold
CLP

X

B5

B12 • Die Shear (note 7)

Wire
Bond

X

B6

Internal Visual (note 7)

Die
Coat

X

X

X

C2

C2-A:HAST (0/22) or C2-B: 85/85

C3

ESD (HBM)

C4

High Temp Storage (Optn'l)

Dl

• Lead Integrity

0/3

D2

Thermal Shock (Optn'l)

0/76

D3

Temp Cycle

0/76

X

X

E1

Electrical Test & Data Log

0/30

X

X

X

E2

Electrical Characterization

0/30

X

X

X

E3

T.D.D.B (note 7)

-

X

X

X

0/9

X

X

X

-

X

X

X

E4

Latch-up

E5

Electromigration (note 7)

X

X

X

X

X

X

0/3

OfT7

X
X

X

X

X

X

X
X

X

X

X

X

X

X

X

X

E6

Photosensitivity (Optn'l)

0/11

X

X

X

E7

Data Retention Bake EPLD & EPR

0/22

X

X

X

E8

Input/Output Capacitance

0/5

X

X

X

E9

Power Cycling (Optn'l)

0/22

X

X

X
636

Qty required per lot

Notes:

11-4

E.Good

239

238

162

248

248

157

314

86

325

0

393

464

E.Reject

63

48

43

35

43

5

5

5

43

29

10

10

64

Total

302

286

205

283

291

162

319

91

368

29

403

474

700

1) Test method and stress conditions available upon request.
2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is
required.
3) Any new package which has not been qualified in the qualified assembly facility.
4) Any new package where the same body size with different lead pitch has been qualified.
5) New leadframe design whereby the paddle size is larger than the existing leadframe paddle size used in the same qualified
package.
6) For new mask from same device family, only high temp life test, ESD, Latch & Capacitance are required.
7) In-process monitor data may be used to satisfy this requirement.
*) Electrical rejects can be used as test sample.
**) This is a non-destructive test, sample can be re-used.

June 1, 1996 (Version 1.0)

~XILINX
Table 2: Hermetic Package/Product Qualification Requirements (Commercial)
New Assy Techniques (Mat'VProcesslMethod
Test

Test Description
(note 1)

Seq

Ace#
S,Size
(note 2)

New
Assy
Plant

X

B1

Solder Heat Test (Optn'l)

0/15

B2

• Resist. to Solvents (note 7)

0/3

X

B3

• Solderability Test (note 7)

0/3

X

B4

• Die Shear/Stud Pull (note 7)

0/5

X

B5

• Bond Pull (note 7)

B6

• External Visual (note 7)

B7

Internal Visual (note 7)

Cl-A High Temp life Test
C1-B Low Temp Life Test (note 7)
C2

High Temp Storage (Optn'l)

C3

ESD(HBM)

Dl

• Phy. Dimension

New
New
Lead
Die
Pkg
Pkg
Frame Attach
Family Qual
(note3) Family
(note4)

Die
Coat

Wire Typeof Lead
Seal
Finish
Bond

X

X

X

New
Fab
Proc

X

X

X

X

X

X

X

X

0/2

X

X

X

X

0/25

X

X

X

X

0/5

X

X

X

0/76

X

X

I

X

X

X
X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

--"----

X

X

X

X

X

X

X

0/3

X

X

X

X

X

X

D2

• Lead Integrity

0/3

X

X

X

X

D3

Thermal Shock + Temp Cycl +
Moisture Resistance

0/32

X

X

X

X

X

D4

Mech. Shock + Vibration + Constant Acceleration

0/32

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

• Salt Atmosphere

0/15

X

X

X

• Internal Vapor Content (note 7)

0/3

X

X

X

D7

• Adhesion of UFinish (Optn'l)

0/2

X

X

X

D8

• Lid Torque

0/5

X

X

X

D9

Temp Cycle

0/45

X

X

X

El

Electrical Test & Data Log

0/30

E2

Electrical Characterization

0/30

X

E3

T.D.D.B (note 7)

E4

Latch-up

X
X

X
X

X

X

X
X

X

D5

X

X
X

X

D6

X

X
X

X

0/15

X

X

0/22
0/77

Full
Qual

X

X

X
I

New
New
Cavity Device
Size (note6)
(note6)

-

X

X

X

0/9

X

X

X

E5

Electromigration (note 7)

-

X

X

X

E6

Photosensitivity (Optn'l)

0/11

X

X

X

E7

Data Retention Bake

0/22

X

X

X

E8

InpuVOutput CapaCitance

0/5

X

X

X
414

Qty required per lot

Notes:

E.Good

190

205

129

69

114

235

190

124

32

124

399

399

E.Reject

81

81

75

50

8

5

2

33

41

48

7

50

81

Total

271

286

204

119

122

240

192

157

73

172

406

449

495

1) Test method and stress conditions available upon request.
2) For any QUAL which does not meet the standard requirements, approval from Product Engineering and Product QA is
required.
.
3) Package Family - A set of package type with the same package, material, Package construction techniques, terminal pitch,
lead shape, row spacing and with identical package assembly tech.
4) Package Type - A package with a unique case outline, configuration, material, piece parts and assembly process.
5) Application to new piece parts or leadframe where cavity size is larger than the largest cavity size for the same package.
6) For new mask from same device family, only high temp life test, ESP, Latch & Capacitance are required.
7) In-process monitor data may be used to satisfy this requirement, for Qual data, data from Assy. lot traveler maybe used .
•) Electrical rejects can be used as test samples

June 1, 1996 (Version 1_0)

11-5

I

Quality Assurance and Reliability

Table 3: Failure Analysis Equipment List
Item

Equipment

1

Scanning Electron Microscope

2

Gold Sputter (SEM Sample
Prep)
Energy Dispersive X-Ray

3
4
5
6
7

I

Vendor

Model
Number

JEOL

JMS-6401 F

ANATECH

Hummer VIII

OXFORD
INST.

LINK ISISL200C

F.I.B. - Focused Ion Beam
F.E.1.
I FIB-600
Workstation
Real-Time X-Ray Imaging Sys- FEIN Foc·us7xs-100.iOtem
Scanning Acoustic Microscopy
Sonix
Micro-Scan
4HF-200
-Ball Shear Strength Tester
KELLER
MBS-200

---=-8

Equipment

Vendor

Model
Number

17 Die-Shear Tester
18 Steam Aging System

KELLER

see #7

Item

19 Solder Wave/Pot
20 Lead Fatigue Tester
21

Conventional Oven (C.D.A.)

22 Drill-bit to open MQUADS
+ Decapping vise
23 Color Printer

XRF Lead Finish/Composition Twin City, Inc.
Measurement System
9 Liquid Crystal Hot Spot Detec- Technology
tion System/Kit, with 3 temp.
Associates
Hypervision
10 Emission Microscope for
Multilayer Inspection (EMMI)
BID Services
11 Curve Tracer

XRF-5500

24 Stud Pull Tester

PIN 4330

25 Work Benches

Visionary
2000

26 Cabinets

12 Metallurgical High Power
Microscope

see quote
(various)

13 Stereozoom Low Power
Microscope - video camera +
monitor
14 Micro-Etcher System
15 Viseco Camera Interface with
High Power Microscope
16 Herrneticity Test System
- Fine Leak
- Gross Leak

Scientific
Instrument
Company
Scientific
Instrument
Company
TM Associates

·-~l~~~Z~~

Robotic
Systems
B&G

ST2D
RPS-202
004-012-00

BID Services

Tektronic
B&G

Tektronic
Phaser IISD
003-010-00

27 Facilities (Lab Area and

see quote
(various)

Computer
Modules
BID Services -Trio-tech 486
- Veeco MS170

Equipment Installation Costs)
28 Tool Maker Microscope

--

29 Flowhood & Rinse Station

30 .Precision X-Sectioning Equipment
31 Plasma Etcher
32 E-Beam IDS-3000

March

CS-1701

1''''"''0' i

Data Integrity
Memory Cell Design in the FPGA Device
An important aspect of SRAM-based FPGA device reliability is the robustness of the static memory cells used to store
the configuration program.
The basic cell is a single-ended 5-transistor memory element (Figure 2). By eliminating a sixth transistor, which
would have been used as a pass transistor for the complementary bit line, a higher circuit density is achieved. During
normal operation, the outputs of these cells are fixed, since
they determine the user configuration. Write and read back
times, which have no relation to the device performance
during normal operation, will be slower without the extra
transistor. In return, the user receives more functionality
per unit area.
This explains the basic cell, but how is the FPGA user
assured of high data integrity in a noisy environment? Con-

11-6

sider three different situations: normal operation, a Write
operation and a Read operation. In the normal operation,
the data in the basic memory element is not changed.
Since the two circularly linked inverters that hold the data
are physically adjacent, supply transients result in only
small relative differences in voltages. Each inverter is truly
a complementary pair of transistors. Therefore, whether the
output is High or Low, a low-impedance path exists to the
supply rail, resulting in extremely high noise immunity.
Power supply or ground transients of several volts have no
effect on stored data.
The transistor driving the bit line has been carefully
designed so that whenever the data to be written is opposite the data stored, it can easily override the output of the
feedback inverter. The reliability of the Write operation is
guaranteed within the tolerances of the manufacturing process.

June 1, 1996 (Version 1.0)

,~XIUNX

Vee
vee~1-

ConfiQ1Jration Data Shift Regiater

ON·l . - - - - - - - - - - I D s

a

DR

Data Clock -- - -

Os

a

DR

-----+-+--+--+--+--+--+--t--

WRIRi'i ---- -----+---+--+--+--+---.o-.o-+--

~CloCk:

: Address QN.1

,, ,,

a
P,echarge ---Word N

------O----+---+---t-___
I-

~ ~ - -1p.:;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;~8

=r=__

Memory
, ConVguration
Address
Shift Regiate,

, Cell

Circuit

X3'124

BltM+l

Figure 2: Configuration Memory Cell
In the Read mode, the bit line, which has a significant
amount of parasitic capacitance, is precharged to a logic
one. The pass transistor is then enabled by driving the word
line High. If the stored value is a zero, the line is then discharged to ground. Reliable reading of th,e memory cell is
achieved by reducing the word line High level during reading to a level that insures that the cell will not be disturbed.

Electrostatic Discharge
Electrostatic-discharge (ESD) protection for each pad is
provided by circuitry that uses distributed transistors and/or
diodes, represented by the circles in Figure 3. In older
devices, these protection circuits are conventional diffused
structures. In newer designs, Xilinx utilizes proprietary
device structures which exhibit substantially enhanced
ESD performance (see Table 4).

June 1, 1996 (Version 1.0)

Whenever the voltage on',a pad apptoaches}a dangerous
level, current flows through fheprotective structl!res to or
from a power supply rail (Vee or ground). In addition, the
capacitances in these structures integrate the pulse to provide sufficient time for the protection networks to clamp the
input, 'avoiding damage to the circuit being protected.
Geometries and doping levels are chosen to provide ESD
protection on all pads for both positive and negative voltages;
Table 4: ESD Performance of Xilinx Components
Circuit
Family

Human Body
Model

883D
Method 3015

Machine
Model
EIAJ
Method 20

Charged
Device
ModelCDM
>2,000 V

XC1?00D

>6,000 V

8ooV-900V

XC2000

2,000 V - 2,500 V

250V-280V

XC3000A

3,000 V - 8,000 V

600V-700V

XC31 00

2,500 V - 3,500 V

6OOV-700V

>2,000 V

XC4000

4,000 V - 9,000V

800V-900V

>2;000 V

XC4000E

4,000 V- 5,000 V

600V-9OOV

>2,00QV

XC5200

3,000 V- 5,000 V

tbd

XC7000

2,000 V- 4,000 V

250V-300V

, >2,000 V

11-7

I

Quality Assur..nce and Reliability
--~--------------~~r-V~

Vee

I
Output

.,,"

Pad

T

Input

---+----,.."..-<>----,----------....j.....- Ground

o =Symbol for electrosta~discharge protection circuit
Figure 3:

InpUtJO~tPl,lt pro~ect~cm Circuity

~

X1825

X3132

Figure 4: .SCR Model

Latchup
Latchup is a condition in which parasiti9 bipolar transistors
form a positive feedback loop' (Figure 4), which quickly
reaches current levels that per,manently da.mage the
device. Xilinx uses techni.ques based on doping levels and
circuit placement to avc;>id this phenomenon, The beta of
each parasitic transistor is n!linimized by increasing the
base width. This is achieved with large physical spaCings.
The butting contacts effectively short ~he n+ and p+ regions
for both wells, which makes the,VBE of each parasitic very
close to zero. This also makes the parasitic transistors very
hard to forward bias. Finally, each well is surrounded by a
dummy collector, which forces the VeE of each parasitic
almost to zero and creates a structure in which the base
width of each parasitic ,is ,Iarge,thusmaking latchup
extremely difficult to induce.

11-8

At elevated temperatures, 100 mA will not cause latchup. At
room temperature, the FPGA can withstand more than 300
mA without latchup; the EPLD device can withstand more
than 200 mA without ·Iatchup. However, to avoid metalmigration problems, continuous currents in excess of 10
mA are not recommended.

High Temperature Performance
Although Xilinx guarantees parts to perform only within the
specifications of the data sheet, extensive high temperature life testing t]as been done at 145°C with excellent
results.

June 1, 1996 (Version 1.0)

Technical Support

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index
15 Sales Offices, Sales Representatives, and Distributors

Technical Support Table of Contents

Technical Support
Technical Support Hotlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hotline Support, U.S ..........................................................
Hotline Support, Japan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hotline Support, Europe .......................................................
X-TALX: The Xilinx Network of Electronic Services ........................................
WebLiNX World Wide Web Site
(www.xilinx.com) .............................................................
XDOCs E-mail Document Server. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XFACTS Document Server. ....................................................
Xilinx Technical Bulletin Board Service ............................................
E-mail addresses for questions related to specific applications .........................
Technical Support E-mail addresses .............................................
Technical Literature .................................................................
AppLiNX ...................................................................
XCELL Newsletter ..................................................................
Programmable Logic Training Courses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
What You Will Learn ..........................................................
Prerequisites. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Benefits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
The Training Classes .........................................................
Hands-On Experience .........................................................
Instructors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Course Materials .............................................................
Product Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Schematic-Based Course Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synthesis-Based Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Synthesis-Based Course Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Update and Advanced Training Classes ...........................................
Training Locations ............................................................
Customer-Site Classes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . ..
Registration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

12-2
12-2
12-2
12-2
12-3
12-3
12-3
12-3
12-3
12-4
12-4
12-5
12-5
12-5
12-6
12-6
12-6
12-6
12-6
12-6
12-6
12-6
12-6
12-7
12-7
12-7
12-7
12-8
12-8
12-9

Technical Support
June 1, 1996 (Version 1.0)
A complete and uniquely accessible offering of worldwide
technical support services is available to Xilinx users.
Xilinx Field Application Engineers, located at sales offices
and technical support centers worldwide, provide local
engineering support, including design evaluation of new
projects, close consultation throughout the design process,
special training assignments, and new product presentations. Because their role as advisors and troubleshooters
keeps them constantly on the go, they are best used, not for
general questions, but for more targeted queries such as
those related to architectural recommendations. The worldwide network of Xilinx sales representatives and distributors also provide local technical support for Xilinx users.
More general queries can be directed to the telephone "hotlines". Permanent teams of expert Technical Support Engineers located in the United States, United Kingdom,
France, Germany, and Japan can handle problems and
answer questions right on the spot, ensuring that the
design process keeps moving forward.
In addition, Xilinx has several automated services, collectively referred to as X-TALX, to provide answers to user's
queries 24 hours a day. These include a world wide web
site, E-mail server, automated FAX system, bulletin board
system, and special interest E-mail groups.

Many different publications assist users in completing
designs quickly and efficiently, including technical manuals,
data sheets, the AppLiNX CD-ROM (a regularly-updated
collection of the latest application notes and design hints),
and the quarterly XC ell newsletter.
For more in-depth support and instruction, a dedicated
training organization conducts technical training classes
worldwide. Courses geared for both novice and experienced users are available.
The following Technical Support Services are discussed in
more detail in this chapter:
•
•

Technical Support Hotline
X-TALX: The Xilinx Network of Electronic Services
- WebLiNX World Wide Web Site
- XDOCs E-mail document server
- XFACTS document server
Xilinx Technical Bulletin Board Service
• Technical Literature
• AppLiNX CD-ROM
• XCELL newsletter
• Training Courses

I

June 1, 1996 (Version 1.0)

12-1

Technical Support

Technical Support Hotlines
The technical support hotlines give Xilinx users direct telephone access to Xilinx Technical Support Engineers worldwide, providing a quick resolution to any problem that
occurs during the design process. Technical questions also
may be submitted via FAX or E-mail.

~

Customer Support
Hotline

B00-255-7778

Customer Support
Fax Number
E-mail Address

408-879-4442
Avail: 24 hrs/day-7 days/week
hotline@xilinx.com

Electronic Technical
Bulletin Board

408-559-9327

--_._-------

12-2

telephone: (81) 3-3297-9163
fax: (81) 3-3297-0067
e-mail: jhotline@xilinx.com

Hotline Support, Europe

Hotline Support, U.S.
Hrs: 8:00 a.m. - 5:00 p.m. Pacific
time

408-559-7778,
Customer Service
(Call for software up- Ask for customer service
dates, authorization
codes, documentation
updates, etc.)

Hotline Support, Japan

UK, London Office
telephone: (44) 1932820821
fax: (44) 1932828522
Bulletin Board Service: (44) 1932333540
e-mail: ukhelp@xilinx.com
France, Paris Office
telephone: (33) 1 34630100
fax: (33) 1 34630959
e-mail: frhelp@xilinx.com
Germany, Munich Office
telephone: (49) 89 991 54930
fax: (49) 89 904 4748
e-mail: dlhelp@xilinx.com

June 1, 1996 (Version 1.0)

~XIUNX
X-TALX: The Xilinx Network of Electronic Services
WebLINX World Wide Web Site
(www.xilinx.com)

New bulletin board users must answer a questionnaire
when they first access the BSS. After answering the questionnaire, callers can browse through the file areas or
upload files. A caller with a valid XACT protection key or
valid host ID will be given full user privileges within 24
hours.

Our World Wide Web site provides access to current information, including product data sheets, application notes,
press releases, financial status, employment opportunities,
and an on-line technical support database. SmartSearch™,
our industry-wide search engine, is the definitive resource
for programmable logic information. SmartSearch™ Agents
will watch the Web for you and inform you, via e-mail, when
new or updated information is found. An FTP site also is
available to facilitate the quick and easy transfer of design
and data files (ftp.xilinx.com).

The software and hardware requirements for accessing the
BBS are as follows:

XDOCs E-mail Document Server

The XilinxTechnical Support BSS is a menu-driven system.
To choose a menu command, simply type the highlighted
first letter of the command. Most commands are "hot keys"
and do not require you to press the return key: Here is a
quick description of the available menu commands:

The XDOCS E-mail system provides 24-hour a day, 7 days
a week access to the same database that the Technical
Support Engineers use. This database is updated regularly
with information on bugs, workarounds, and helpful hints.
Via E-mail, users can search for a specific record, or supply
keywords to trigger a search of the database; XDOCS will
send the requested information by return E-mail. Automated updates also can be sent on a periodic basis notifying users of new additions to the system. To subscribe to
XDOCS, send an E-mail to xdocs@xilinx.com with "help"
as the only word in the subject header.

Baud Rate
Character Format

8 data bits, no parity, 1 stop bit

Transfer Protocols

ASCII, Xmodem, Yrnodem, Zmodeffi

Main
U)pload

Upload a file to the Technical Support
group.

D)ownload

Download a file. This assumes you
already know the filename, otherwise
select the File Manager.

F)ile Manager

Takes you to the File Manager menu.
This menu is for locating files.

S)ystem Folder

Takes you to the System menu. This
menu is for changing your password,
display options, etc.

XFACTS Document Server
The XFACTS automated FAX system provides the same
information as XDOCS, but uses a phone/FAX interface
instead of E-mail. Using a touch-tone telephone, users can
request documents that are sent to their FAX machine.
Located in San Jose, California, the XFACTS system can
be reached at 408-879-4400.

28.8K or less bps

File Manager
F)lag

Flag files for download.

L)ocate Files

Use wildcards to search for files.

N)ew Files

Lists recently added files.

Z)ippy DIR scan

Searches for text in file descriptions.

Xilinx Technical Bulletin Board Service
(408) 559-9327

#'s

Chooses a file area to browse.

To provide users with up-to-date information and software
support, Xilinx provides a 24-hour electronic bulletin board
system (BBS). The Xilinx Technical Support BBS is available to all registered Xilinx development system users.
Users with full privileges can browse files on the bulletin
board, download those of interest, or upload files to Technical Support Engineers.

M)ode of display

Toggles between text and graphics
display

P)age length

Changes the number of printed Iiries
between "More?" prompts.

T)ransfer Protocol

Changes the default transfer protocol.

V)iew Settings

Shows current settings and user information.

W)rite User Info

Changes current user settings.

All BBS files can be accessed through the Xilinx Web and
FTP locations.

System

12-3

I

Technical Support

E-mail addresses for questions related to
specific applications
Digital Signal Processing
applications
PCI-bus applications
Plug and PlaylSA applications
PCMCIA card applications
Asynchronous Transfer Mode
applications
Reconfigurable Computing
applications

dsp@xilinx.com
pci@xillnx.com
PnP@xilinx.com
pcmcia@xilinx.com
atm@xilinx.com
reconfig@xilinx.com

Technical Support E-mail addresses
hotline@xilinx.com
ukhelp@xilinx.com
frhelp@xilinx.com
dlhelp@xilinx.com
jhotline@xilinx.com

12-4

USA, Xilinx Headquarters
United Kingdom
France
Germany
Japan

June 1, 1996 (Version 1.0)

1:XILINX
Technical Literature

XCELL Newsletter

Xilinx offers many different publications to assist users in
completing designs quickly and efficiently. These include
technical manuals, Data Books, data sheets, application
notes, AppLiNX CD, and the XCELL newsletter. Many of
these publications are available on-line at the Xilinx
WebLiNX World Wide Web site.

XCELL, the quarterly journal for Xilinx programmable logic
users, is dedicated to supplying up-to-date information for
system designers. A typical issue includes descriptions of
new products, updates on component and software availability and revision levels, application ideas, design hints
and techniques, and answers to frequently-asked questions.

As part of the development system products, Xilinx provides manuals and supporting documents for the development system tools, libraries, CAE tool interfaces, and
related software tools. Many of these manuals are available
on the CD that holds the software as well as hardcopy format. On-line help facilities also are an integral part of the
development system products.

To add your name to the XCELL subscription list, please
send your name, company affiliation, and mailing address
to Brad Fawcett, XCELL editor, via FAX at 408-879-4676 or
via e-mail senttobrad.fawcett@xilinx.com.

AppLlNX
AppLiNX is a collection of current application notes and
other new technical documentation provided on a CD-ROM
for easy· reference by the design engineer. All the material
on the CD is provided in Adobe Acrobat format for easy
viewing and printing. The AppLiNX CD is updated regularly
as new material becomes available.

I

June 1; 1996 (Version 1.0)

12-5

Technical Support

Programmable Logic Training
Courses
All users of Xilinx products should attend one of our Training Courses. Attending a Xilinx Training Course is one of
the fastest and most efficient ways to learn how to design
with FPGA or CPLD devices from Xilinx. Hands-on expert
instruction with the latest information and software will
allow you to implement your own designs in less time with
more effective use of the devices.
Xilinx offers a variety of classes to meet your specific
needs. Training centers around the world schedule classes
on a regular basis, and the classes can even be brought to
your own facility.

What You Will Learn
Not only will you learn about our products, but we will recommend the best ways to use the software based on our
years of experience with thousands of designs. You will
learn how to efficiently enter, implement, and verify your
design. The powerful yet easy-to-use Xilinx development
system allows you to utilize the Xilinx automatic mode, or
take a power-user approach and direct the automatic tools
to the best implementation of your design.

Prerequisites

Instructors

Students need only have a background in digital logic
design. Basic familiarity with the PC or workstation is helpful but not required. It will benefit you to learn your design
entry tool of choice before attending the Xilinx class, including an HDL language for the synthesis-based classes.
Update or Advanced classes require previous experience
with the Xilinx products.

Xilinx Training Courses have been successfully held worldwide for over six years. The instructors are Xilinx experts
who are skilled at passing that knowledge on to fellow engineers. A dedicated Training organization at Xilinx works
closely with the Applications and Engineering groups to
keep the classes up-to-date with the latest improvements
and recommendations for Xilinx and third-party tools.

Benefits

Course Materials

•
•
•
•
•
•

All course materials are supplied by Xilinx. Every student
gets an excellent reference tool in the form of course notes,
that include all the material presented during the class. The
course notes are bound for easy use and include additional
reference material beyond what is covered in the class.

Start or Complete Your Design During the Class
Reduce Your Learning Time
Make Fewer Design Iterations
Get to Market Faster
Lower Production Costs
Increase Quality

The Training Classes
Xilinx offers classes for both schematic entry users and
synthesis users, and both new and experienced users. All
Xilinx classes focus on the Xilinx products, independent of
the specific design entry tool.

Product Coverage
Xilinx classes will cover the latest released versions of our
devices and development systems. While all available products are covered, emphasis is placed on the more popular
and/or recommended solutions. New products are added to
the class as they become available.

Hands-On Experience
Each class includes over two hours each day for hands-on
labs. There is at least one computer for every two people in
the class.

12-6

June 1, 1996 (Version 1.0)

~XILINX
Schematic-Based Course Outline

Synthesis-Based Course Outline

The schematic-based Xilinx Training Class lasts three days.
All North American training sites, and most international
locations, teach the same class.

The following is a complete outline of the three-day synthesis-based class:

•

•

•

•

•
•
•

•

•

Introduction
- Development System Overview
- Architecture Overview
Xilinx Design Flow
- Schematic Entry Guidelines
- Design Manager
- Flow Engine Automatic Translation
Timing Specification
- XACT-Performance Delay Specification
- Static Timing Analyzer
Designing for Xilinx FPGAs
Combinatorial Logic
- Registered Logic
- Memory Design
- 1/0 Design
- X-BLOX Module Generation
Designing for Xilinx CPLDs
Text Entry Guidelines
- Xilinx-ABEL software
Floorplanning
- Incremental Design
- XACT-Floorplanner
- Relationally-Placed Macros
Timing Analysis
- Good Design Practices
- Simulation Guidelines
Configuration
Programming Modes
Bitstream Generator
- PROM File Formatter
- Hardware Debugger Download & Readback

Synthesis-Based Classes
Designing with high-level languages (VHDL and Verilog)
and synthesis tools can be very different from using schematic entry. As a result,· Xilinx offers classes that focus On
VHDL and Veri log design entry for Xilinx products. Xilinx
highly recommends the synthesis-based class for anyone
using VHDL or Verilog for design entry. Synthesis-based
classes include the following additional topics, using HDL
code for design entry:
•
•
•
•

Good coding styles
Hierarchy within synthesis
Synthesis design flow
Controlling Xilinx implementation tools with synthesis

June 1, 1996 (Version 1.0)

•
•
•

•

•
•
•

•
•

•

Introduction
FPGA Architecture
Xilinx-Synopsys Design Flow
Good Coding Styles
Synopsys Scripts
Design Manager
Automatic Translation
Timing SpeCification
- XACT-Performance Delay Specification
- Static Timing Analyzer
Simulation Guidelines
Good Design Practices
Coding. for Xilinx FPGAs
- Combinatorial Logic
Carry Logic and X-BLOX Module Generation
Registered Logic
I/O Design
Memory Design
Hierarchy
Floorplanning
- Incremental Design
- XACT-Floorplanner
Configuration
Programming Modes
- Bitstream Generator
- PROM File Formatter
- XChecker Download & Readback

Update and Advanced Training Classes
If you have already attended a Xilinx class or have experience using Xilinx products, consider attending a one-day
Update or Advanced Training session. These sessions will
be most useful if you hiwe the latest software.

Update Classes
One-day Update classes focus on the latest released products from Xilinx, describing them in relation to previous versions. For example, an Update Class is available describing
the new features in XACTstep 6.0. The class will be offered
for a limited time at regional sites, or can be brought to your
facility. Browse the Xilinx web site (www.xilinx.com) for the
latest information regarding special Update classes on new
products from Xilinx.

I

Technical Support

Advanced Training Classes

Customer-Site Classes

If you have already attended a Xilinx class or have experience using Xilinx products, consider attending a one-day
Advanced Training session. Advanced Training classes are
offered at no charge to current in-warranty Xilinx customers; otherwise tuition is $200. Advanced Training sessions
can vary according to the interests of the students. Popular
topics include:

Xilinx can bring a Training Course to your own facility for the
greatest convenience to your company.

•
•
•
•
•
•

Example Logic Design Techniques
Timing Analysis and Avoiding Timing Hazards
Design Methodology for Tough Designs
Details of Advanced Optimization Capabilities
XACT Design Editor
Floorplanning

Advanced Training classes are held regularly at Xilinx
headquarters, and sometimes at regional locations, but are
replaced by Update Classes when appropriate. See the
web site (www.xilinx.com) for scheduled classes, or contact
Xilinx Training to hold an Advanced Training session at your
site.

On-Site Classes Provide Additional Benefits:
No Travel Costs
On-site Xilinx training classes eliminate travel time and
expenses:
-

No airfare
No hotel bills
No car rental

Classes Tailored To Your Needs
On-site classes can be tailored to meet the specific needs
of your company:
Convenient class time and location
Projects of a proprietary nature can be discussed
openly
. Students can use their own equipment and begin an
actual design right in class

Training Locations

Costs: North America

Xilinx Headquarters
Classes are held regularly at Xilinx headquarters in San
Jose, California. During the class, you may elect to meet
one-on-one with Xilinx Applications engineers to discuss
specific issues not covered in the class. Topics may include
using a specific third-party tool, optimizing your particular
design, or more advanced issues beyond the coverage of
the class.

Prices start at $4,500 for a minimum class size of six students.

Costs: International
-

Included in class fees:
-

North American Distributor Locations
Xilinx distributors sponsor training classes jointly with Xilinx, using the same material as the headquarters classes.
Since the distributor sponsors the class, the tuition cost is
often reduced to $495 for customers of the sponsoring distributor. Check with the distributor when registering. Locations include over fifty cities across North America.

International Locations
Xilinx classes are held throughout Europe, Asia, India,
Israel, South Africa, Australia, South America, and other
international locations. Classes vary in length and tuition,
but are based on the same material used in North America.
Contact your local Xilinx sales office or representative for
classes in your area.

12-8

Prices vary; contact your local Xilinx sales
representative.

-

A Xilinx-certified instructor
Training materials for each student
PC for every two students (or if you prefer, the
training labs can be done on your PCs or
workstations)

Scheduling a Class
To schedule a training class at your facility and determine
pricing, call the Xilinx sales office nearest you, or your local
Xilinx sales representative. On-site training classes are
popular, so the more advanced notice we have, the better
our ability to schedule your class exactly when you want it.

June 1, 1996 (Version 1.0)

~XILINX
Registration

Enrollment

Tuition

To enroll, call the registrar for the location where you would
like to attend a class. Or you may call the Training Registrar
at Xilinx headquarters at (800) 231-3386 or contact your
local sales office. You may also register on-line at www.xilinx.com.

Class tuition in North America is $1,000 per student for the
three-day classes, including the synthesis-based and workstation-based classes at Xilinx headquarters. The distributor-sponsored, schematic-based classes are offered at a
reduced rate of $495 for customers of the sponsoring distributor. On-site classes start at $4500 per class, and vary
according to the class and the number of students. For
international locations, call the local registrar for priCing.
Most classes include a full lunch, with morning and afternoon snacks. Let the registrar know if you have any special
dietary needs when registering for the class.

Money-back Guarantee

Xilinx Training Registrar
Training Registrar
Xilinx, Inc.
2100 Logic Drive
San Jose, CA 95124
Phone: (800) 231-3386 x1
Fax: (408) 879-4676, attn: Customer Training Registrar
E-mail: customer.training@xilinx.com
Register on-line: www.xilinx.com

We are so confident you will be satisfied with the benefits of
a Xilinx training class that we offer the following guarantee:

Full refund of the class cost if you are not
completely satisfied.
. _ " - - " - ... _-_._.-

Location
Xilinx Headquarters

North America

Distributor Locations
Customer Site
Update

International

Tuition
$1,000

$495
Starts at $4,500
Typically $100

Advanced
International Locations

Varies

Free

Customer Site

Varies

·•
··
··
··
·•
··

Benefits
Can meet with applications engineers
Classes held frequently
All class types available
Lower cost for distributor's customers
Local
Convenience; can focus on specific issues
One day, focus on new products
For experienced, in-warranty users
Offered in over 21 countries
Native language
Convenience
Can focus on specific issues

I

June 1, 1996 (Version 1.0)

12-9

Technical Support

12-10

June 1, 1996 (Version 1.0)

Product Technical Information··

1

Introduction

2

Development System Products

3

CPLD Products

4

SAAM-Based FPGA Products .

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information

14 Index
15 Sales Offices, Sales Representatives, and Distributors

Product Technical Information Table
of Contents

Product Technical Information Table of Contents (Detailed) ..................... 13-1
Choosing a Xilinx Product Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-3
XC4000 Series Technical Information .......................................... 13-9
XC3000 Series Technical Information .......................................... 13-13
FPGA Configuration Guidelines ............................................. "

13-25

Configuring Mixed FPGA Daisy Chains ....................................... "

13-33

Configuration Issues: Power-up, Volatility, Security, Battery Back-up .................. 13-35
Dynamic Reconfiguration .................................................. "

13-39

Metastable Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-41
Set-up and Hold Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-45
Overshoot and Undershoot .................................................. 13-47
Boundary Scan in XC4000 and XC5000 Series Devices ............................ 13-49

Product Technical Information Table
of Contents

Choosing a Xilinx Product Family
Introduction ...................................................................... .
SRAM-BasedFPGAs .............................................................. .
SRAM-Based FPGAs (XC2000, XC3000, XC3100, XC4000, XC5200) .................. .
Overview of SRAM-Based FPGA Families ........................................ .
Partially-Reconfigurable SRAM-Based FPGA with Bus Interface (XC6200) .............. .
EPROM- and FLASH-Based CPLDs (XC7300, XC9500) ................................... .
Overview of CPLD Families ................................................... .
Selecting the Appropriate Xilinx Family ................................................. .
Type of Logic .............................................................. .
Special Features Required .................................................... .
Further Information ................................................................ .

13-3
13-3
13-3
13-4
13-5
13-5
13-5
13-6
13-6
13-6
13-8

XC4000 Series Technical Information
Voltage/Current Characteristics of XC4000-Family Outputs ................................. .
Additional Output Delays When Driving Capacitive Load ................................... .
Ground Bounce in XC4000 Devices . .................................................. .
Test Method ............................... ; ............................... .
Interpretation of the Results ................................................... .
Guidelines for Reducing Ground-Bounce Effects ................................... .
Ground-Bounce vs Delay Trade-Off ................................................... .
XC4000 and XC4000E Power Consumption ............................................•

13-9
13-10
13-10
13-10
13-11
13-11
13-11
13"12

XC3000 Series Technical Information
Contents ..... , .............. , ................................................... .
Introduction ................................................•......................
Configurable Logic Blocks ........................................................... .
Function Generator Avoids Glitches ............................... ; ......... " .. .
Input/Output Blocks ............................................................. , .. .
Inputs .................................................................... .
Outputs ................................................................... .
I/O Clocks ....... , ...... , ......... " " ..................................... .
Routing. . . . . . . . . . . . . . . . . .. . .................................................... .
Horizontal Longlines .......... , .. , ... , .... , ................ , , .. , .. , , ..... , ... .
Internal Bus Contention , .. , .. , .. , .... , ......... , ...... , . , .. , ...... , ...... , ... .
Vertical Longlines , ' ...... , .......... , .................. , .. , ................ , .
Clock Buffers .. , .. , . , ... , , . , , . , .. , , . , .... , ...... , . , .. , . , .......... , ....... , , .
Power Dissipation .... , ....... , , , . , , . , .. , ......... , ...... , . , .. , .......... , ........ , .
Crystal Oscillator .. , .. , ..... , .. , .. , .. , ... , ... , . , .. , ................ , .. , .. , .. , .. , , .. .
Crystal-Oscillator Considerations. , ... , .. , , ............. , .. , .......... , ......... .
CCLK Frequency Variation ... , .. , ... , . , ...... , , .... , . , . , . , ......... , , . , , .. , , . , . , . , .. .
CCLK Low-Time Restriction .. , , , , ...... , , ... , , . , . , .... , ... , .. , ... , , ., ..... ; .. , ,
Battery Back-up ... , . , ; ... , . , .......... , . , .. , , ... , .... , ........ , ,. , .. , .... , . " ..... ,
Powerdown Operation ... , .. , ...... , ... , . , ....... , , , . , .... , . , ... , , . , , ........ ,
Configuration and Start-up . , ...... , .. , ............ , , , , . , ...... , . , ...... , .. , ......... .
Start-Up ..... , .. , ... , .... , ..... , .. , . , ...... , ................. , . , . , , ........ .
Beware of a Slow-Rising XC3000 Series RESET Input .• ' .. , ........ , ........ , , . , .. , ...... .

13-13
13-13
13-13
13-14
13-15
13-15
13-16
13-17
13-17
13-17
13-17
13-18
13-18
13-18
13-19
13-19
13-21
13-21
13-21
13-22
13-22
13-22
13-23

I

13-1

Product Technical Information Table of Contents

FPGA Configuration Guidelines
Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Protection Against Data or Format Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Daisy-Chain Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Start-Up Procedure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Configuration Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Selecting the Best Configuration Mode ............................................
When Configuration Fails. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for all Families. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for the XC2000 and XC3000 Families. . . . . . . . . . . . . . . . . . . . . . ..
General Debugging Hints for the XC4000 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Additional Mode-Specific Debugging Hints for All Families .......... , . . . . . . . . . . . . . . . ..
Daisy Chain Debugging Hints ...................................................
Potential Length-Count Problem in Parallel or Peripheral Modes ........................
Miscellaneous Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

13-25
13-26
13-26
13-26
13-28
13-29
13-29
13-29
13-30
13-30
13-30
13-31
13-32
13-32

Configuring Mixed FPGA Daisy Chains
Configuration Issues: Power-up, Volatility, Security, Battery Back-up
Power-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Sensitivity to Vee Glitches ....................................................... ; . "
Design Secu rity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Design Security when Configuration Data is Accessible ..............................
Design Security by Hiding the Configuration Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Battery Back-up and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Powerdown Operation '" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

13-35
13-35
13-36
13-36
13-37
13-37
13-38

Dynamic Reconfiguration
Important Considerations ............................................................
Reconfiguration Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Initiating Reconfiguration in Different Xilinx Device Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
XC2000 and XC3000 Series ....................................................
XC4000 Series and XC5200 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

13-39
13-40
13-40
13-40
13-40

Metastable Recovery
Metastability Measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-42
Metastability Calculations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13-42

Set-up and Hold Times .. ...................... " .............................. 13-45
Overshoot and Undershoot ... ................................................ 13-47
Boundary Scan in XC4000 and XC5000 Series Devices
Overview of XC4000/XC5000 Boundary-Scan Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Deviations from the IEEE Standard ....................................................
Boundary-Scan Hardware Description ............................ ; .....................
Test Access Port .............................................................
TAP Controller ............................................................ "
The Boundary-Scan Data Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
The Bypass Register ..........................................................
User Registers .......................................................... ; . ..
Using Boundary Scan. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Boundary Scan Description Language Files ............. , . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

13-2

13-49
13-50
13-51
13-51
13-51
13-51
13-53
13-53
13-54
13-57
13-57

Choosing a Xilinx Product Family
August 6, 1996 (Version 1.1)

Application Note By PETER ALFKE

Summary

This Application Note describes the various Xilinx product families. Differences between the families are highlighted. The
focus of the discussion is how to choose the appropriate family for a particular application.
Xilinx Families

Demonstrates

XC2000, XC3000, XC4000, XC5000, XC6000, XC7000,
XC9000

Choosing an appropriate Xilinx family based on the
intended application

Table of Contents

SRAM-Based FPGAs

SRAM-Based FPGAs

Xilinx SRAM-based FPGAs fall into two distinct categories.
All are reconfigurable and can be programmed in-system;
only the XC6200 family can be partially reconfigured and
offers a built-in microprocessor interface. The two categories of devices are separately described below.

EPROM and FLASH-Based CPLDs
Selecting the Appropriate Xilinx Family

Introduction
Xilinx offers Field-Programmable Logic circuits, mass-produced standard integrated circuits that the user can customize for the specific application.
Xilinx products offer the following advantages:
•

•

•
•

High integration (less space, lower power, higher
reliability, lower cost) than solutions based on existing
standard devices like MSI and PALs.
No non-recurring engineering charges and associated
risk, typically required for mask-programmed gate array
.
solutions.
Fast design time .and easy design modification,
important for early time-to-market.
Designs can be upgraded in the field for added
functionality.

Some potential users might be confused by the wide diversity of Xilinxproduct offerings. This application note provides a broad. overview from the user's perspective.
Xilinx offers programmable logic circuits in two distinctly different technologies.
•

•

SRAM-based FPGAs, the original Xilinx offering, now
encompassing the XC2000, XC3000, XC4000,
XC5200, and XC6200 series and their sub-families, like
theXC3000A, XC300QL, XC31 00, XC3100A,
XC4000A,XC4000H,XC4000E,XC4000L,XC4000EX,
and XC4000XL.
Complex PLDsor EPLDs, XC7300,and XC9500
families.

August 6, 1996 (Version 1.1)

SRAM-8ased FPGAs (XC2000, XC3000,
XC31 00, XC4000, XC5200)
These families represent an ongoing evolution of the original Xilinx FPGA architecture, characterized by structural
flexibility and an abundance of flip-flops. Logic is implemented in look-up tables, and is interconnected by a hierarchy of metal lines controlled by pass transistors.
Attractive systems features include on-chip bidirectional
busses and individual output 3-state and slew-rate control,
common reset for all flip-flops, and multiple global low-skew
clock networks.

The configuration can be loaded while the devices are connected into a system, and can be changed an unlimited
number oftimes by reloading the "bitstream,"the series·of
bits used to program the device .. Configuration must be
reloaded whenever Vcc is re-applied. Reconfiguration
takes 20 to 200 ms, during which time all outputs are inactive.
Static power consumption is very low,down to microwatts
for some of the families. Dynamic power consumption is
proportional to the clock frequency, and depends on the
logic activity inside the device and on the outputs.
The description "SRAM-based" refers primarily to the standard high-volume manufacturing process, and secondarily
to the fact that configuration data is stored in latches. Different from typical SRAMs, these latches use low-impedance
active pull-up and pull-down transistors. An on-chip voltage
monitor 3-states ,the outputs and initiates reconfiguration
when Vcc drops significantly (to 3.2V in a 5-V system).

13-3

I

Choosing a Xilinx Product Family

These FPGAs are available in different sizes and many different packages. Usually each device type is available in
many package types. Any package can accommodate different sized devices with compatible pinouts, so the user
can migrate to a larger or smaller device without changing
the PC-board layout.

Overview of SRAM-Based FPGA Families
XC2000: Oldest, simplest, smallest, and lowest-cost FPGA
family; not recommended for new designs
•
•

Used for simple, very cost-sensitive applications.
Accept limited logic flexibility, 3-input look-up tables, no
clock enables, no output slew-rate c~ntrol, only two
device types covering the narrow complexity range of
600 to 1500 gates.

The XC5200 FPGA family or the XC7300 and XC9500
EPLD families, may often be a better alternative.
XC2000L: 3.3-V version of XC2000; not recommended for
new designs
• Used for simple, battery-operated applications.
• Accept significantly slower speed at 3.3 V, compared to
XC2000 at 5 V.
XC3000: Superseded
Don't use this venerable family for new designs, since it has
been superseded by the improved, but fully backwards
compatible, XC3000A family.
XC3000A: Newest version of the popular XC3000 family
Five device types cover a complexity range from 1,300 to
7,500 gates, with 256 to 928 flip-flops. Logic is implemented in 4-input look-up tables; two tables can be combined to implement any logic function of five variables with
only one combinatorial delay of 4 or 5 ns. Flip-flop toggle
rate is over 110 MHz.
Global choice of input thresholds (1.2 V or 2.5 V), output
slew-rate control, and an on-chip crystal oscillator circuit
are attractive system features.
•
•

Use for medium-speed, medium-complexity
applications.
Accept lack of dedicated carry circuits, resulting in less
efficient and slower arithmetic and counters than in
XC4000E families. No on-chip RAM; data storage is
thus limited to the available 256 to 928 flip flops.

XC3000L: 3.3-V version of XC3000A
•
•

Use for battery-operated applications.
Accept significantly slower speed at 3.3 V, compared to
XC3000A at 5 V.

XC3100A: Newest version of the popular high-speed
XC3100 family
XC3100A devices are functionally and bitstream identical
with the XC3000A, and are available in the same packages
with the same pinouts. The only difference is the higher
speed of the XC31 OOA, with a look-up table delay of 1.5 to
4 ns, and the slightly higher standby current of 8 to 14 mA.
One additional high-end family member, the XC3195A, can
implement up to 9,000 gates and 1,320 flip-flops.
•
•

XC3100L: 3.3-V version of XC3100A
•
•

13-4

Use for 3.3-V applications.
Accept significantly slower speed at 3.3 V, compared to
XC3100A at 5 V, as well as higher quiescent power and
much higher powerdown current than XC3000L at 3.3 V.

XC4000: Superseded
Don't use this family for new designs, since it has been
superseded by the improved, but fully backwards compatible XC4000E family.
XC4000A: Superseded
Don't use this family for new designs, since it has been
superseded by the improved, faster, less expensive, and
pinout-compatible - but not bitstream-compatible XC4000E family.
XC4000E: Enhanced superset of the XC4000 family
The XC4000E family is recommended for new designs.
The ten devices in this family stretch from 2,000 to 25,000
gate complexity. The emphasis is on systems features and
speed. The function generators are more versatile than in
the XC3000-Series parts, and there is a dedicated carry
network to speed up arithmetic and counters and make
them more efficient. Most importantly, the function generators can be used as user RArv'I with asynchronous or synchronous write addressing, even as dual-port RAMs. This
capability makes register files, shift registers and especially
FIFOs faster and much more efficient than in any other
FPGA.
Logic speed is not as. fast as XC3100,but dedicated carry
logic can speed up wide arithmetic and long counters even
above XC31 00 speed.
•

XC3100: Superseded
Don't use this family for new designs, since it has been
superseded by the improved, but fully backwards compatible XC31 OOA family.

Use for high performance design with system clock
rates up to 100 MHz.
Accept lack of dedicated carry circuits, resulting in less
efficient and possibly slower arithmetic and counters
than in XC4000E. No on-chip RAM; data storage is thus
limited to the available 256 to 1,320 flip-flops.

•

Use for general-purpose logic and data-path logic that
can take advantage of internal busses and fast
arithmetic carry logic. Use for on-chip distributed RAMs,
e.g. 50 c MHz FIFOs up to 64 deep,.32 bits wide.
Accept lack of crystal oscillator circuitry and lack of
Powerdown feature.

August 6, 1996 (Version 1.1)

~XIUNX
XC4000EX: Larger version of the XC4000E family, largest
devices made by Xilinx

Extension of the XC4000E family from 28k to 125k gates,
with greatly increased routing resources, faster clocking
options and more versatile output logic.
•

Use for designs beyond 20,000 gate complexity.

XC4000H: High 1/0 version of XC4000, not recommended
for new designs

Variations of XC4003 and XC4005, with significantly
increased number of I/0s. Internal functionality identical to
XC4003 and XC4005, but number of I/Os increased from
80 to 160 for XC4003H, from 112 to 192 for XC4005H. No
input or output flip-flOps in the lOBs, but 24 mA sink current
and sophisticated· slew-rate control that can minimize
ground bounce.
•

•

Used for I/O-intensive applications, but also consider
XC5200 as a lower-cost alternative when internal RAM
is not required.
Accept lack of I/O flip-flops, thus larger output delay,
larger uncertainty in input set-up time.

•

•

Use for innovative reconfigurable-processor solutions,
and for general purpose solutions where fast
(re)configuration is an advantage, or for registerintensive, datapath-oriented, highly structured designs.
Accept product availability starting later in 1996.

EPROM- and FLASH-Based CPLDs
(XC7300, XC9500)
These device families are extensions of the popular PAL
architecture, implementing logic as wide AND gates, ORed
together, driving either a flip-flop or an output directly. The
simple logic structure makes these devices easy to understand, and results in both fast design compilation and short
pin-to-pin delays. Wide input gating and fast system clock
rates up to 150 MHz are attractive features for state
machines and complex synchronous counters.
The XC7300 CPLDs use EPROM technology.
The new XC9500 in-system programmable family, based
on FLASH technology, eliminates the need for a separate
programmer. These new devices also offer boundary scan
(JTAG) to simplify board testing.

XC5200: Low-cost FPGA

New architecture optimized for low cost, good routability,
and the ability to lock pinout while internal logic is being
modified. Dedicated carry structure similar to XC4000, but
no RAM. Four-input function generators avoid the XC3000
input constraints. lOBs are less rigidly coupled to the internal matrix of CLBs and interconnects, which greatly
improves the flexibility of pin-locked designs. lOBs have no
flip-flops.

Overview of CPLD Families
XC7200A: Superseded

Not recommended for new designs. Use XC7300 instead.
XC7300: EPROM-Based CPLD

Six devices cover the range from 18 to 144 macrocells in
44- to 225-pin packages.
•

The XC5200 family offers the lowest cost per gate of all XiIinx FPGAs, whenever RAM is not required.
Performance is similar to XC3000A, but dedicated carry
logic can speed up wide arithmetic and long counters.
•

•

Use for medium-speed general-purpose logic, and for
data-path logic that can take advantage of internal
busses and fast arithmetic carry logic. Alternative to
XC3000A at lower cost, and with additional benefits,
such as dedicated carry for arithmetic and. counters,
improved routing, and ability to cope with locked pinout.
High 1/0 count. Package pinout compatible with
XC4000.
Accept lack of internal RAM and lack of crystal
oscillator circuitry.

Partially-Reconfigurable SRAM-Based
FPGA with Bus Interface (XC6200)
This new fine-grained architecture is very different from the
other Xilinx families. It offers partial and very fast reconfigurability, supported by an 8/16/32 bit wide microprocessor
bus interface. This interface can directly write to and read
from any internal cell, and can even treat part of the internal
configuration as user RAM.

August 6, 1996 (Version 1.1)

•

•

Use for high-speed logic, short pin-to-pin delays, for
state machines and flexible address decoding, and as
PAL replacement. Dedicated carry logic offers fast and
efficient adders, subtractors, comparators, and
counters.
Accept higher power consumption and fewer available
flip-flops compared to SRAM-based or antifuse-based
FPGAs.
The XC7318, XC7336/0, and XC7354 are very
effective as PAL replacements. The XC73360 boasts
significantly reduced power consumption.

Delays are deterministic, and compile times are very short.
XC9500: FLASH-Based CPLD

Nine devices cover the range from 36 to.575 macrocells.
The new XC9500 family provides advanced in-system programming and test capabilities for high performance,general purpose logic integration.
•
•

Use XC9500 for CPLD applications requiring fast pinto-pin speeds.
Accept higher power consumption and fewer aVailable
flip-flops compared to SHAM- or antifuse-based FPGA.

13-5

I

Choosing a Xilinx Product Family

Selecting the Appropriate Xilinx
Family

XC9500 achieves fast compilation through the simplicity of
its PAL-like architecture.
XC6200 achieves fast compilation through its ASIC-like
small granularity, which requires no logic partitioning effort.

It is not always obvious which Xilinx family is the "right"
choice for a particular application. To make a decision, start
with the known data, the target application. Then address
the following questions:

6. For lowest cost per gate, when on-chip RAM is not
required:

•
•

Use XC5200, XC3000A (XC2000 for small devices in high
volume).

What type of logic is used in the application?
What special features are required?

Type of Logic
All Xilinx devices are general-purpose. Any family can
implement any type of logic. There are, however, some features that make certain families more appropriate than others. The following items should be interpreted as "soft"
suggestions, not as absolute, unequivocal choices.

1. For shortest pin-to-pin delays and fastest flip-flops:
Use XC9500, XC7300, or, if fan-in is sufficient, XC3100A,
XC4000E/EX.
XC9500 and XC7300 CPLDs have a PAL-like AND/OR
structure that is inherently very fast. XC31 00 has extremely
fast logic blocks, but the single-level fan-in is limited to five.
XC4000E/EX have slower logic blocks, but a wider fan-in of
nine. XC4000EX FPGAs offer a very fast pin-to-pin path
using a FastClk buffer and a 2-input function generator in
the lOB.

2. For fastest state machines:
For encoded state machines, use XC9500, XC7300.
For "one-hot" state machines, use XC31 00, XC4000E/EX,
XC5200.

3. For fast counters/adders/subtractors/accumulatorsl
comparators:
Use XC4000E/EX, XC5200 or XC7300 for wide functions.
Use XC3100A for very fast, but short or simple counters.
XC4000E/EX and XC5200 have dedicated carry-logic that
is most effective over the range of 8 to 32 bits.
XC7300 has dedicated carry within a function block, and
can implement unlimited carry look-ahead in the Universal
Interconnect Matrix.
XC3100Aachreves high speed for short word-length and
simple operations (such as non-Ioadable counters) through
its extremely fast logic blocks.

7. For pinout compatibility within and between families:
Use XC4000E/EX, XC5200.
These three families are carefully deSigned to fit the same
pinout in any given available package. This allows easy
migration to different device sizes or families in the same
package. The user can add logic or streamline the design
or even use a less costly or faster family without any need
to change the existing PC-board layout.

8. For Digital Signal Processing multiply-accumulate)
applications:
Use XC4000E/EX.
The look-up-table architecture and the dedicated carry
structure are very efficient for distributed arithmetic, a fast
and effective way to implement fixed-point multiplication in
digital filters.

Special Features Required
The sixteen items below describe specific features and
characteristics available only in the listed families. These
are, therefore, "hard" selection criteria.

9. For on-chip RAM:
Use XC4000E, XC4000EX, or XC6200.

XC4000E/EX has many 16x1 or 32x1 RAMs with synchronous or asynchronous write and dual-port capability.
XC6200 can implement an arbitrary portion of the configuration-memory space as user RAM.

10. For on-chip (bidirectional) bussing:
Use XC3000A, XC3100A, XC4000E, XC4000EX,XC5200,
XC7300, XC9500 (i.e., use any Xilinx family except
XC2000).
XC3000A, XC3100A, XC4000, and XC5200familieshave
horizontal Longlines that can be driven by internal 3-state
drivers.

4. For I/O-intensive applications with a high ratio of 1/0
to gates:

XC9500 and XC7300 devices implement busses indirectly
using the wired-AND capability in the switch matrix.

Use XC5200.

11. For on.chip crystal oscillator circuitry:

5. For shortest design compilation time:

Use XC2000/L, XC3000AlL, XC3100AlL.

Use XC9500, or XC6200.

13-6

August 6, 1996 (Version 1.1)

~XIUNX
The on-chip circuit is just a dedicated single-stage inverting
amplifier that can be configured between two dedicated
pins. It is not recommended for designs requiring very low
power consumption or crystal frequencies below 1 MHz.
12. For very fast or partial reconfiguration, and for a
dedicated microprocessor interface:
Use XC6200.
All other SRAM-based families must be completely reconfigured.
13. For non-volatile single-chip solutions:
Use XC9500, XC7300, or any HardWire device.

XC4000E/EX can be configl,lred with a global choice of
either totem-pole or rail-to-rail outputs.
XC4000H has this option per individual pin.
18. For 3.3-V operation:
Use XC2000L, XC3000L, XC4000L, XC4000XL.
19. For 5-V operation Interfacing with 3.3-V devices:
Use XC9500, XC7300 or XC4000E/EX.
Any XC4000ElEX "totem-pole" output drives 3.3-V inputs
safely, and the TTL-like input threshold can be driven from
3.3-V logic.

The SRAM-based devices require an external configuration
source, which may be contained in the microprocessor's
memory. XC3000A and XC3000L devices can be used with
a baUery-backed-up supply, thus eliminating the need for
external configuration storage.

20. For In-system programmability:

14. For lowest possible static power consumption at 5V:

Target and Initiator designs are available for theXC4000E.

Use XC2000, XC3000A and, to a lesser extent, XC5200,
XC4000E, XC4000EX.

XC31 00 and XC7300 can implement target-only interfaces.

For Icc down to a few microamps, use XC2000/L or
XC3000AlL in powerdown. The other families consume a
few milliamps.
Configurations for CMOS input thresholds on all inputs
reduce supply current significantly.
15. For avoiding pin-locking problems with routingintensive designs:
Use XC9500, XC7300, XC4000EX, XC5200.
XC9500 and XC7300 have special architectural features to
enable pin locking.
XC4000EX and XC5200 provide additional routing channels, called VersaRing, between the core logic and the 110.
16. For Boundary-Scan support:
Use XC4000E, XC4000EX, XC5200, XC9500.
17. For rail-to-rail output vOltage swing at 5 V Vcc:
Use XC2000, XC3000A, XC3100A, XC4000H, XC4000E,
XC4000EX, XC5200, XC6200.
(In XC4000H/E/EX, rail-to-rail is a user-option.)
XC4000, XC7300, and XC9500 have a ''totem-pole'' output
structure with lower Voh.

August 6, 1996 (Version 1.1)

Use all Xilinx families except XC7300.
21. For PCI compatibility:
Use XC4000E/EX and XC9500.

22. For Hi-Rei, military, or mil temperature-range
applications:
Use XC2018, XC3000, XC3100A, XC4003A, XC4005,
XC4010, XC4013.
23. For battery-operated applications requiring low
stand-by current:
Use XC2000/L,
XC6200.

XC3000AlL,

XC4000E/EX,

XC5200,

XC2000L and XC3000Lhave inherently very low static
power consumption.
XC2000 and XC3000A can use powerdown to ignore all
input activity and tolerate Vcc down to 2.3 V, while maintaining configuration.

XC4000E/EX must be configured for CMOS input thresholds, and must shut down clock and logic activities externally.

I

24. For best protection against Illegal copying of a
design (design security):
Use XC7300, XC9500 with security bit activated.
Use XC2000, XC2000L, XC3000A, XC3000L with powerdown baUery-backed-up configuration.

13-7

Choosing a Xilinx Product Family

Further Information
For further information on any of the Xilinx products discussed in this application note, see the Xilinx WEBLINX at
http://www.xilinx.com. or call your local sales office.
Table 1: Selecting a Xilinx Family
<

..J

c
c
cC')
0

><

<

><

c
c
c

0

><

><
W

..J

<:t

<:t

c
c
c

c
c
c

0

0

><

><

1. Shortest pin-to-pin

X

X

X

2. Fastest state machines

X

X

X

3. Fastest arithmetic counters

X

X

><
c
c

C

0

><

c
c

N
In

0

><

><

In
01

0

X

X

X

X

X

X
X

9. RAM
10. Bidirectional busses

X

X

X

X

11. Crystal oscillator

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X
X

X
X

X

X

X

X

X

X

X
X
X
X

12. Fast/partial configuration
X

X

X

15. Tolerates pin-locking
X

16. Boundary scan
18. 3.3 V operation

X

20. In-system programmable

X

X

21. PCI-compatible
22. Hi-rei, mil, mil-temp

X

23. Low standby current

X

X

24. Design security

X

X

X
X

X

X

X

X
X

X

X

X

option
X

X
X

X

option

X

X

19. 5 V out drives 3.3 V

13-8

><

0

X

X

7. Footprint compatible families
8. DSP (multiply/accumulate)

17. Full-swing 5 V output

><

c
c

X

5. Fastest compilation

13. Non-volatile/single chip
14. Low power @ 5 V

0

c
cC')
r-.

X

4. High I/O to gate ratio
6. Lowest cost, no RAM

c
c

N
\0

option
X

X

X

X

X

X

X

X

X
option
X

X
X

X

X

X
X
X

X

X

X
X

X

X

X

X

X

August 6, 1996 (Version 1.1)

XC4000 Series
Technical Information
June 1, 1996 (Version 1.0)

Application Note

Summary
This Application Note contains additional information that may be of use when designing with XC4000 Series devices. This
information supplements the product descriptions and specifications, and is provided for guidance only.
Xilinx Family
XC4000lXC4000A/XC4000H/XC4000E/XC4000L

Introduction
This application note describes the electrical characteristics of the output drivers, their static output characteristics
or IN curves, the additional delay caused by capacitive
loading, and the ground bounce created when many outputs switch simultaneously.

Voltage/Current Characteristics- of
XC4000-Family Outputs
Figures 1 and 2 show the output source and sink currents,
both drawn as absolute values. Note that the XC4000ElEX
families offer a configuration choice between an n-channel
only, totem-pole like output structure that pulls a High output
to a voltage level that is one threshold drop lower than Vee,
and a conventional complementary output with a p-channel
transistor pulling to the positive supply rail. When driving
inputs that have a 1.4-V threshold, the lower VOH of the
totem-pole (''TTL') output offers faster speed and more symmetrical switching delays.

These curves represent typical devices. Measurements
were taken at Vee= 5 V, T = 25°C. These characteristics
vary by manufacturing lot, and will be affected by future
changes in minimum device geometries. These characteristics are not production-tested as part of the normal device
test procedure; they can, therefore, not be guaranteed.
Although these measurements show that the output sink
and source capability far exceeds the guaranteed data
sheet limits, continuous high-current operation beyond the
data sheet limits can cause metal migration of the on-chip
metal traces, permanently damaging the device. Output
currents in excess of the data-sheet limits are, therefore,
not recommended for continuous operation. These output
characteristics can, however, be used to calculate or model
output transient behavior, especially when driving transmission lines or large capacitive loads.

200

------+-

180
160
140
120
rnA 100

I I -

8

I

i

I

40
20 /

o
Volts

3

4

5
X5291

Figure 1: Output Voltage/Current Characteristics
for XC4000E

June 1, 1996 (Version 1.0)

Figure 2: Output Voltage/Current Characteristics
for XC4000L

13-9

XC4000 Series Technical Information

Additional Output Delays When
Driving Capacitive LQad

Ground Bounce in XC4000 Devices

Xilinx Product Specifications in chapter 4 give guaranteed
worst-case output delays with a 50-pF load.
The values below are based on actual measurements on a
small number of mid-93 production XC4005-5, all in PQ208
packages, measured at room temperature and Vee =5.5 V.
Listed is the. additional output delay, measured crossing 1.5
V, relative to the delays specified in this Data Book.
These parameters are not part of the normal production
test flow, and can, therefore, not be guaranteed.
Table 1: Increase in Output Delay When Driving Light
Capacitive Loads «150 pF)
High-to-Low

,

XC4000
Note:

Slew
Mode
Slow
Fast

10

Low-to-High

50 100 10

50 100 pF

O'
O·

O'
O·

-1.6
-1.6

1.4 -1.4
1.2 -1.2

1.4
1.1

ns
ns

'Zeroby definition

Table 2: Increase in Output Delay When Driving Heavy
Capacitive Loads (>150 pF)
Slew Mode
XC4000

Slow
Fast

High-toLow
1.7
1.5

Low-toHigh
1.2
1.2

~-

nsltOO pF
nsl100 pF

~T High-to-Low for XC4005-5 with Fast-mode output driving 250 pF:

1.2 ns (from Table 1) plus (250-100) pF • 1.5 nsl100 pF
= 1.2 ns + 2.25 ns = 3.45 ns

TOKPOF + 3.45 ns

= 7.0 ns + 3.45 ns = 10.45 ns

Vee bounce is not as important as ground bounce,
because it is of lower magnitude due to the weaker pull-up
transistors. Also, the noise. immunity in the High state is
usually better than in the Low state, and input levels are referenced to ground, not Vee. All this is the result of our
industry's TTL heritage.

Test Method

Example:

Total propagation delay, clock to pad:

Ground-bounce is a problem with high-speed digital ICs,
when multiple outputs change state simultaneously causing undesired transient behavior on an output, or in the
internal logic. This is also referred to as the Simultaneous
Switching Output (SSO) problem. Ground bounce is primarily due to current changes in the combined inductance of
ground pins, bond wires, and ground metallization. The ICinternal ground level deviates from the external system
ground level for a short duration (a few nanoseconds) after
multiple outputs change state simultaneously. Ground
bounce affects outputs that are supposed to be stable Low,
and it also affects all inputs since they interpret the incoming level by referencing it to the internal ground. If the
ground bounce amplitude exceeds the actual instantaneous noise margin, then a non-changing input will be
interpreted as a short pulse with a polarity opposite to the
ground bounce.

Data was taken on XC4005-5, devices in the PQ208 package, soldered to the Xilinx Ground Bounce Test Board. Pin
82, two pins away from the nearest ground pin, was configured as a permanently Low output driver, effectively monitoring the internal ground level. The simultaneously
switching outputs were on pins 80 and 83, for two outputs
switching; additionally, pins 80 and 86 were used for four
outputs switching. The closest ground pins are 79 and 90.
Four ground-bounce parameters were measured at room
temperature, with Vcc set at 5.5 V as shown in Figure 3.
•
•
•
•

VOLP-HLPeak ground noise when switching High-to-Low
VOLV-HLValley ground noise when switching High-to-Low
VOLP_LHPeak ground noise switching Low-to-High
VOLV-LHValley ground noise switching Low-to-High

All four parameters can affect system reliability.

~------V~Q,\~____________________________~~r-----------VOH
VOLP_lH

'--------- VOL

VOLV-lH
X5299

Figure 3: Ground Bounce
13-10

June 1, 1996 (Version 1.0)

1:XILINX
The two positive peak values can cause problems with a
signal leaving the ground bounce chip, driving another chip.
The positive ground bounce voltage is added to the VOL,
and may exceed the receiving input's noise margin. A continuously logic Low input may thus be interpreted as a
short-duration High pulse.

the slew-rate mode of these outputs. Switching outputs
closer to the monitoring output also cause larger peaks and
valleys than outputs further away.

The two negative valley parameters can cause problems
with a signal arriving at the ground-bounce chip,reducing
the Low-level noise immunity. The incoming voltage may
not be Low enough, and may, therefore, be interpreted as a
short-duration High input pulse.

•

Guidelines for Reducing
Effects

Minimize the impedance of the system ground
distribution network and its connection to the IC pins.
PQFPs are best suited, PGAs are worst, and PLCCs are
in-between.
Use PC-boards with ground- and Vee-planes, connected
directly to the ICs' supply pins: Place decoupling
capacitors very close to these ground and Vee pins.
Keep the ground plane as undisturbed as possible. A row
of vias can easily cause a dynamic ground-voltage drop.
Keep the clock inputs physically away from the outputs
that create ground bounce, and connect clocks to input
pins that are close toa ground pin. Make sure that all
clock and'asynchronous inputs have ample noise
margin, especially in the Low state.
If PQssible,av~id simultaneous switching by.staggering
output delays, e.g. through additional local routing of
signals or clocks.
Spread simultaneously switching,outputs around the IC
periphery. For a 1S-bit bus, use two outputs each on
either side of four ground pins.

•

Table 3: Ground Bounce, 16 Outputs SWitching, Each
With 50 or 150 pF Load, Vee = 5.5V
•
High-to-Low

Load

Slew
Rate

VOlP

16 x 50 pF

Slow
Fast

670
480
1,170 ' 710

16 x 150pF

Slow
Fast

740
1,180

VOlV

330
420

Low-to-High

VOlP

VOlV

240
480
210
350

240
660
280
710

Unit

•

mV
mV
mV
mV

•

Interpretation of the Results
Ground bounce is a linear phenomenon. When multiple outputs sWitch, the total ground bounce is the sum of the
ground-bounce values caused by individual outputs switching. Since the actual switching of multiple outputs is usually
not quite simultaneous, small timing differences, between the,
switching outputs, caused by routing delays, can indirectly
affect the amplitude. With low capacitive loading, < 50pF, the
peaks,and valleys might even partially cancel each other.
With larger e<:Ipacitive loads, the tendency is .for valleys to
combine with .valleys and .peaks \0 combine with peaks.

Ground~Bounce

•

Ground~Bounce

vs Delay Trade-Off

Afte~

the external sourc.es of ground bounce have been
reduced or eliminated. the designer can trade reduced
ground bounce for additional delay by selecting between
families and slew-rate options. Figure 4 shows the trade-off
for 16 outputs switching simultaneously High-to-Low.

In most devices tested, the load capacitance does not
directly affect the ground-bounce amplitude,but it does
affect the duration of the ground-bounce signals.
1800

On the fastest outputs, minimal load capacitance created a
ground"bounce resonant frequency of 340 MHz, with. a
half-cycle time of 1,5 ns. Such a signal exceeds 90% of its
peak amplitude for about 0.4 ns.

i

With a 50 pF load' on the switching outputs, the .ground
bounce resonant frequency is 90 MHz, with a half-cycle
time of 5 ns, staying 1.7 ns above 90% of peak amplitude.

~

With a 150 pF load on the switching outputs, the ground
bounce resonant frequency is 40 to 60 MHz, with a halfcycle time of 8 to 12 ns, staying 3 ns above 90% of peak
amplitude.
The main problem with large load capacitances is not an
increase in amplitude, but rather an increase in duration of
the ground-bounce sigrial. The amplitude is mainly affected
by the number of outputs switching simultaneously, and by

June 1, 1996 (Version 1.0)

1600

800

",

§

e

"

FAST SLEW RATE

1400

"
:g 1000
g
~ 1200

600

16xSOpF

•

16xlSOpF

•
•

SLOW SLEW RATE

••

16x50pF

16x 1!50pF

400
, 200

I

I •

5 Additional 6
Delay (ns)
X5981

Figure 4: Ground-Bounce vs. Delay Trade-off for 16
Outputs Switching 50 and 150 pF Each

13-11

I

XC4000 Series Technical Information

XC4000 and XC4000E Power
Consumption
Below are the dynamic power consumption values for typical design elements in XC4000 and XC4000E.

The following elements are obviously device-size dependent:
•

One Global Clock driving all CLB flip-flops, but no flipflop changing:
in XC4005: 4 mW/MTps = 8 mW/MHz
in XC4010: 8 mW/MTps = 16 mW/MHz
in XC4013: 12 mW/MTps = 24 mW/MHz
in XC4020: 16 mW/MTps = 32 mW/MHz
in XC4025: 20 mW/MTps = 40 mW/MHz

•

One full-length horizontal or vertical Longline with one
driving CLB source and one driven CLB load:
. in XC4005: 0.10 mW/MHz = 0.20 mW/MHz
in XC4010: 0.15 mW/MTps = 0.30 mW/MHz
in XC4013: 0.18 mW/MTps = 0.36 mW/MHz
in XC4020: 0.20 mW/MTps = 0.40 mW/MHz
in XC4025: 0.24 mW/MTps = 0.48 mW/MHz

The differences between XC4000 and XC4000E are too
small to be statistically relevant:
Global clocks in XC4000E are 3% higher, and Longlines
and unloaded outputs in XC4000E are 5 to 10% lower than
in XC4000.
Power consumption is given at nominal 5.0-V supply and
25"C.
Power is proportional to the square of the supply voltage,
but is almost constant over temperature changes. Power is
given as "mW per million transitions per second",since the
more commonly used "MHz" can be ambiguous. When a
1O-MHz clock toggles a flip-flop, the clock line obviously
makes 20 MTps, the flip-flop output only 10 MTps.
The first six elements are device-size independent, i.e. they
are applicable to all XC4000 or XC4000E devices operating
.
at 5-VVcc.
•

One CLB flip-flop driving nothing but a neighboring flipflop in the same or adjacent CLB (a typical shift register
design):
0.1 mW per million transitions per second =
0.1 mW/MTps

These numbers do not account for the 10 mA of static
power consumption when all device inputs are configured·
in TIL mode, which is always the default mode, and in
XC4000 is actually the only user-accessible mode.
These numbers assume short rise and fall times on all
inputs, avoiding the cross-current when both the n-channel
pull-down and the p-channel pull-up transistor in the input
buffer might conduct simultaneously.
Tutorial Comments:
In its pure form, a CMOS output driving a capacitive load
has a power consumption that is independent of drive
impedance or rise and fall time. For a fUll-swing signal, the
power consumed when charging the capacitor is C x V2 X f
where f is the frequency of charge operations. In each
charge operation, half the total energy consumed ends up
On the capacitor, and the other half of the energy is dissipated in the current-limiting resistor or transistor,. whatever
its value may be.

•

One CLB flip-flop driving its neighbor plus 9 lines of .
interconnect:
0.2 mW per million transitions per second =
0.2 mW/MTl?s

•

One unloaded or unbonded TIL-level output:
0.25 mW per million transitions per second =
0.25 mW/MTps

•

50 pF on a TIL-level output: add 0.5 mW/MTps = 1.0
mW/MHz

The subsequent discharge cycle does not take any· new
energy from the power supply, but dissipates in the currentlimiting resistor/transistor all the energy that was formerly
stored in the capacitor.

•

One unloaded or unbonded XC4000E CMOS-level
output:
0.31mW per million transitions per second =
0.31 mW/MTps

It is assumed here that the frequency is low enough so that
the capacitors are completely charged and discharged in
each half-cycle.

•

50 pF on a CMOS-level output: add 0.625 mW/MTps =
1.25 mW/MHz

13-12

June 1, 1996 (Version 1 .0)

XC3000 Series
Technical Information
June 1, 1996 (Version 1.0)

Application Note By Peter Alfke and Bernie New

Summary
This Application Note contains additional information that may be of use when designing with the XC3000 series of FPGA
devices. This information supplements the data sheets, and is provided for guidance only.
XilinxFamily
XC3000IXC3000A/XC3000UXC31 00IXC31 00A/XC31 OOL

Contents

Configurable Logic Blocks

CLBs
Function Generators
Flip-flops
Longline Access
lOBs
Inputs
Outputs
Routing
Horizontal Longlines
Bus contention
Vertical Longlines
Vertical Longlines
Clock Buffers
Vertical Longlines
Clock Buffers
Power Dissipation
Crystal Oscillator
CCLKFrequency Stability and Low-time restriction
PowerdoWn and Battery-BaCkup
Configuration and Start-Up
Reset
Beware of slow rise-time

The XC3000IXC3100 CLB, shown in Figure 1, contains a
combinatorial function generator and two Ootype flip-flops.
Two output pins may be driven by either the function generators or the fUp-flops. The flip-flop outputs may be routed
directly back .to the function· generator inputs without gOing
outside of the CLB.

Introduction
Ttw background information provided in this Application
Note supplements the XC3000, XC3000A, XC3000L,
XC3100A and XC3100L dati:! ,sheets. It covers a.wide
range of topics, including a number of electrical parameters
not specified in the data sheets" and unless otherwise
noted, applies to al! six families. These additional parameters are sufficie~tlyaccurate for most design purposes;
unlike the parameters specified in the data sHeets, however, theyare not worst-case yalues over temperature and
voltage, and are not' 100% production tested. They can,
therefore,not be guaranteed.
0

June .1;1996 (Version 1.0)

'0

The function generator consists· of two 4-input look-up
tables that may be used separately or combined into a single function. Figure 2, shows. the three available options.
Since the CLB only has five inputs .to the function generator, inputs must be shared between the two look-up tables.
In the FG mode, the function generator provides any two 4input functions of A, Band. C plus 0 or E; thecnoice
between 0 and E is made separately for: each function. In
the 'Fmode, all five inputs are combined into a singleSinput function of A, B, C, 0 and E. AnyS-input fUnction may
be emulafetL The FGMmOcle is a supersetoftheF mode,
where two 4-input functions of A, B, C and 0 are multi.
plexed together according to the fifth variable, E.
In aI/modes, either.of the Band C inputs may be selectively
replaced by QXand QY, ~he flip-flop outputs. In the. FG
mQde, this Selection i.s made separately for the two look-up
tables~ext~nding thefunctk>nality tC?anytwo fUnctions of
four variables chosen from seven, provided two of the variables are stored in the fJip-flops.:rhis is particularly useful in
state-machine-Iike applications.,' .
.
In the F mode, the function generators implement a single
function of five variables that may.be chosen from seven,.as
described above. The. selection. of OX and·OY is constrained to be the same;for.both look-up. tables. The FGM
mode differs from the F mode in that OX and QY maybe
selected separately for the two look-up tables, as in the FQ
mode. This addedflexibiUtypermits the emulation of
selected furictionsthat can include all seven possible
inputs:

13-13

I

XC3000 Series Technlcellnformatlon

Data In

I"'-DI--~====1!--

A

Log.

v,.....

~~.~~~
C

__J..j

ax
Combinatorial
Function

av

EnabIlCIock+""EC'--_ _ _ _ _ _ _ _- !

co'" +"---~-_---+
Reset

RD

Direct

Figure 1: Configurable Logic
Block (CLB)

Function Generator Avoids Glitches
The combinatorial logic in all CLBs is implemented as a
function generator in the form of a multiplexer, built out
of transfer gates. The logic inputs form the select inputs
to this mUltiplexer, while the configuration bits drive the
data inputs to the multiplexer.
The Xilinx circuit designers were very careful to achieve
a balanced design with similar (almost equal) propagation delays from the various select inputs to the data
output.
The delay from the data inputs to the output is, of
course, immaterial, since the data inputs do not change
dynamically: They are only affected by configuration.
This balanced design minimizes the duration of possible decoding glitches when more tnan one select input
changes. Note that there can never be a decoding glitch
when only one select input changes. Even a nOli-overlapping decOder cannot generate a glitch problem,
since the node capacitance will retain the previous logic
level until the. new transfer gate is activated. about
nanosecond later.
When more than one inpllt changes "simultaneously;
the user should analyze the logic output for any possible intermediate code. If any such code permutation
produces a different result, the user must assume that
such a glitch might occur and must make the system
design immune to it. The glitch might be only a few
nanoseconds long, butthatis long enough to upset an
.asynchronous design.
If none of the possible address sequences produces a
different result, the user can be sure that there will be
no glitch.
The designer of synchronous systems generally
doesn't worry about such glitches, since synchronous
designs are fundamentally immune to glitches on all
signals except clocks or direct SET/RESET inputs.

a

13-14

~XILINX \
Input/Output Blocks

The automatic logic-partitioning software in the XACTstep
development system only uses the FG and F modes. However, all three modes are available with manual partitioning,
which may be performed in the schematic. If FG or F
modes are required, it is simply a matter of including in the
schematic CLBMAP symbols that define the inputs and
outputs of the CLB.

The XC3000IXC3100 108, shown in Figure 3, includes a 3state output driver that may be driven directly or registered.
The polarities of both the output data and the 3-state control are determined by configuration bits. Each output buffer
may be configured to have either a fast or a slow slew rate.

The FGM mode is only slightly more complicated. Again, a
CLBMAP must be, used, with the signal that multiplexes
between the two 4-input functions locked onto the E pin.
The CLB will be configured in the FGM mode if the logic is
drawn such that the gates forming the multiplexer are
shown explicitly with no additional logic merged into them.

The 108 input may also be direct or registered. Additionally,
the input flip-flop may be configured as a latch. When an
108 is used exclusively as. an input, an optional pull-up
resistor is available, the value of which is 40-150 kf.!. This
resistor cannot be used when the 108 is configured as an
output or as a bidirectional pin.

The two D-type flip-flops share a common clock, a common
clock enable, and a common asynchronous reset signal.
An asynchronous preset can be achieved using the asynchronous reset if data is stored in active-low form; the Low
created by reset corresponds to the bit being asserted. The
flip-flops cannot be used as latches.

Unused lOBs should be left unconfigured. They default to
inputs pulled High with the internal resistor.

If input data to a CLB flip-flop is derived directly from an
input pad, without an intervening flip-flop, the data-pad-toclock-pad hold time will typically be non-zero. This hold time
is equal the delay from the clock pad to the CLB, but may
be reduced according to the 70% rule, described later in
the lOB Input section of this Application Note. Under this
rule, the hold time is reduced by 70% of the delay from the
data pad to the CLB, excluding the CLB set.up time. The
minimum hold time is zero, even when applying the 70%
rule results in a negative number.
The CLBpins to whiph ,Longlines nave direct access are
shown in Table 1. Note that the clock enable pin (EC} and
theTBUF control pin are both driven from to the same vertical. Long Line. Consequently, EC cannot easily be used to
enable a, register tt:lat must be, 3-stated onto a bus. Similarly, EC cannot easily be used in a register that uses the
Reset Direct pin (AD).

Table 1: Longline to, CLB Direct Access
CLB

Longline

A

Left Most Vertical
(GCLK)
Left Middle Vertical

S

D E

TBUF

K EC RD

T

X
X

X

Right Middle Vertical
Right Most Vertical
(ACLK)
Upper Horizontal' ,
Lower Horizontal

C

X

X

X

X
X

X

June 1, 1996 (Version 1.0)

X

X

Inputs
All inputs have limited hysteresis, typically in excess of 200

mV for TTL input thresholds and in excess of 100 mV for
CMOS thresholds. Exceptions to this are the PWRDWN
pin, and the XTL2 pin when it is configured as the crystal
oscillator input.
Experiments show that the input rise and fall times should
not exceed 250 ns. This value was established through a
worshcase test using internal ring oscillators to drive all 1/0
pins 'except two, thus generating a maximum of on-chip
noise, One of the remaining 1/0 pins was configur~d as an
input, and 'tested for. single-edge response; the other JlO
. was used as an output to monitor the response.
'
These test conditions, are, perhaps, o\(erly demanding,
although it was assumed that the PC bOard had, negligible
ground noise ,and,gooq power-supply, decoupling. While
conservative, the resulting specification is, in most
instances, easily satisfied.

108 input flip-flops, are guaranteed to operate correctly
without data hold times (with respect to the device clockinput pad) provided that the dedicatt;ld CMOS clock input
pad and the GCLK buffer ar.e used. The use of a TTL clock
ora different clock pad will result in a data-hold-time
requirement. The length of this hold time is equaUo the
delay from the actual clock pad to the GCLK buffer minus
the delay from the dedicated CMOS clock pad to the GCLK
buffer.
To ensure that the input flip-flop has a zero hold time, delay
is incorporated in the D input oUhe flip-flop, causing it to
have a relatively long set-up time. However, the set-uptime,
specified in the data sheet is with respect to the clock
reaching the 108. Since there is an unavoidable delay
between the clock pad and the 108, the input~pad~to-cJock­
pad set-up time is actually less than the data sheet number.

13-15

I

XC3000 Series Technical Information

3·5tat.

('' 'OUCMT'DiPU'' T""''EN'' A' ' BLi:..
E)

Out

Directln
Registered In

--P---I------J1.J---j-,
-F----JL/

--;I-'----t------,
--;t-=----t---;
Flip-

Flop
or
Latch

TTL or
CMOS
Input
Threshold

R

OK

IK

CK1.

=D"

Program
Controlled
Multiplexer

CK2

o

= Programmable Interoonneotlon Point or PIP

X321e'

Figure 3: Input/Output Block (lOB)
Part of the clock delay can be subtracted from the internal
set-up time. Ideally, all of the clock delay could be subtracted, but it is possible for the clock delay to be less than
its maximum while the internal set-uptime is at its maximum value. Consequently, it is recommended that, in a
worst-case design, only 70% of the clock delay is subtracted.
The clock delay can only be less than 70% of ,its maximum
if the internal set-up time requirement is also less than its
maximum. In this case, the pad-to-pad set-up time actually
required will be less than that calculated~
For example, in the XC3000-t25, the input set~up time with
respect to the clock reaching the lOB is 16 ns. If the delay
from the clock pad to the lOB is 6 ns, then 70% of this delay,
4.2 ns, can be subtracted to arrive at a maximum pad-topad set-up time of -12 ns.
The 70%, rule must be applied whenever one delay is subtractedfrom another. However, iUs recommended that
delay compensation only' be used routinely in connection
with input hol<;l times. Delay compensation in asynchronous
circuits is specifically not recommended. In any case, the
compensated delay must not become negative. If 70% of
the compensating delay is greater, than the delay from
which it is deducted, the resulting delay is zero.

13-16

The 70% rule in no way defines the absolute minimum values delays that might be encountered from chip to chip,
and with temperature and power-supply variations. It sim~
ply indicates the relative variations that might be found
within a specific chip over the range of operating conditions.
Typically, all delays will be less than their maximum, with
some delays being disproportionately faster than others.
The 70% rule, describes the spread in the scaling factors;
the delay that decreases the most will be no less than 70%
of what it would have been if it had scaled in proportion to
the delay that decreased the least In particular, in a worstcase design where it is assumed that any delay might not
have scaled at all, and remains at its maximum value, other
delays Will be no Jess than 70% of their maximum.

Outputs
All XC3000/XC3100 FPGA outputs are true CMOS with nchannel transistors pulling down and p-channel transistors
pulling up. Unloaded, these outputs pull rail-to-rail. Some
additional ac characteristics of the output are listed in
Table 2. Figure 4 and Figure 5 show output current/voltage
curves for typical XC3000 and XC31 00 devices.
Output-short-circuit-current values are given only to indicate the capability to charge and discharge capacitive

June 1,1996 (Version 1.0)

1:XIUNX
lOB latches have active-Low Latch Enables; they are transparent when the clock input is Low and are closed when it is
High. The latch captures data on what would otherwise be
the active clock edge, and is transparent in the half clock
period before the active clock edge.

200

L

180

160
140
120

L

80

.L

40

o

._-f-:....

/'

60

~O

Routing

J.--

rnA 100

....... " I H
b-..

lL

2

Volts

~

4

5
X5294

Figure 4: Output CurreritNoltage Characteristics for
XC3000, XC3000A, XC31 00 arid XC3100A Devices

Horizontal Longlines
As shown in 'fable 3, there are two horizontal Longlines
(HLLs) per rOW of CLBs. Each HLL is driven by one TBUF
for each column of CLBs, plus an additional. TSUF at the left
end of the Longline. This additiona.1 TSUF is convenient for
driving lOB data onto the Longline. In general,.the routing
resqurces to the T and I pins of TBUFs are somewhat limited ..
Table 3: Number of Horizontal longlines

loads. In accordance withcomll1on industry practice for
other logic devices, only one output at a time may be short
circuited, a.nd the duration of this short circuit to Vee or
ground may not exceed one secorid. Xilinx does not recom. mend a continuous output or clamp current in excess of 20
rnA on anyone' output pin; The data sheet guarantees the
outputs for no more than 4mA at 320 mVto avoid problems
when many outputs are sinking.current simultaneously;
The aclive-High3-11lale control(T) is the same as an
active-Low outputenable.,(OE).lnother words, a Hig\1 on
tbe T-pin of an OSUFZ places theoutputin a high imped,
ance state, and a Low enables theotJlPutThe same naming convention is used forTBUFs within the FPGA device.

va Clocks
Internally, up to eig\1tdistinctl/Oclocks can be ljsed, two on
each of the four edges of the die.. While the lOB does not
provide pros ram mabie clock polarity, the two clock fines
serving an lOB can be used forlrue and inverted clock, and
the appropriate polarity connected 10 the lOB. This. does,
however, limit all lOBs on tha(edgeof the die to using only
the two edges of the onecIOC~:.
Table 2: Additional

AC Output.Cha~acterisiic:s

.AC Parameters'
Unloaded OutputSlew Rate
UnloadedTl'snsitio(j nme .
Additional rise time for 812 pF
normalized
Additional fall time for 812 pF
norl']lalized

.• )=ast"
~.8 Vlns
O1.450s
lOOns
O.l~ris/pF

50.ns
0.06.ns/pF

Plut
Name'

Rows x
Columns

XC3020
XC3030

8x8
10 x 10

100

XC3Q42
XC3064

12 x 12
16 x 14

144
224

XC30$O
XC3195

20j(t6
22x22

320
484

ClBs
64

Horizontal
longlines

TBUFs
per HLl

16
20

9
11

24

13
15

32
40
44

17
23

Optionally, HLLs can be pulled up at either end, or at both
ends. ThevaltJe of each pull-up resistor' is S-lQ ill
In addition, HlLsare permanently driven by low~powered
latches. tAat are, easily overriddetlby active output~ or pullup resistors. These. latches maintain the logiC leliels on
HLls that are not pulled up and temporarily are not driven.
The logic level maintained is the last level actively driven
onto the line.
.
Wh~n using 3-state HLLs for multiplexing, the use of fewer
than four TBUFs.can waste .resources. Multiplexers With
four or' fewer inptJtscan· be implemented more efficiently
usingCLBs.

Internal Bu.s. Contention

Slow"
0:5 V/ns
7.9n$
100ns

XC3000 and XC4000 Series devices have internal 3-state
bus drivers (TBUFs). As in any other bus deSign, such bus
drivers must be enabled carefully in order to aVoid, or at
least minimize, bus contention. (Blls contention means that
one driver tries to drive the bus High.while. a second dr,iver
tiies toarive it LOW).
.' ' . ,
.

0.12 ns/PF
64.l'Is
0.08 ns/pF

Since the potential overlap of the enable signalsdslay-out
dependent, bus contention is the responsibility of the FPGA
user. Weeanonly supply the following intormation:

* Fast and Slow refer to the output programming option.

While two internal blJffersdrive cOl1flictlngdata, they Create

a cLlrrent path of typica]ly 6 mA Thiscurr.ent is tolerable,

b~t should not last indefinitely, since it exceedE; our (conservative) current density rules. A continuous contention

June 1, 1996 (VerSion 1.0)

13-17

I

XC3000 Series Technical Information

could, after thousands of hours, lead to metal migration
problems.

local interconnect should only be considered for individual
flip-flops.

In a typical system, 10 ns of internal bus contention at 5
MHz would just result in a slight increase in Icc.

Power Dissipation

16 bits x 6 rnA x 10 ns x 5 MHz x 50% probability

=2.5 mAo

There is a special use of the 3-state control input: When it is
directly driven by the same signal that drives the data input
of the buffer, i.e. when D and T are effectively tied togethEir,
the 3-state buffer becomes an "open collector" driver. Multiple drivers of this type can be used to implement the ''wiredAND" function, using resistive pull-up.
In this situation there cannot be any contention, since the 3state control input is designed to be slow in activating and
fast in deactivating the driver. Connecting D to ground is an
obvious alternative, but may be more difficult to route.

Vertical Longlines
There are four vertical longlines per routing channel: two
general purpose, one for the global' clock net and one for
the alternate clock net.

Clock Buffers
XC3000/XC3100 devices each contain two high-fan-out,
low-skew Clock-distribution networks. The global-clock net
originates from the GClK buffer in the upper left corner of
the die, while the alternate clOCk net originates from the
AClK buffer in the lower right corner of the die,
The global and alternate clock networks each have optional
fast CMOS inputs, called TClKIN and BClKIN, respectively. Using these inputs provides the fastest path from the
PC board to the internal flip-flops and latches. Since the
signal bypasses the input buffer, well-defined CMOS levels
must be guaranteed on these clock pins.
To specify the use of TClKIN or BClKIN in a schematic,
connect an IPAD symbol directly to the GClK or AClK
symbol. Placing an IBUF between the IPAD and the clock
buffer will prevent TClKIN or BClKIN from being lJsed.
The clock buffer output nets only drive ClB and lOB clock
pins. They do not drive any other CLB inputs. In rare cases
where a clock needs to be connected to a logic input or a
device output; a signal should be tapped off the clock buffer
input, and routed to the logicinput. This is not possible with
clocks using TClKIN or BClKIN.
The clock skew created by routing clocks through local
interconnect makes safe designs very difficult to' achieve,
and this.practice is not recommended.ln general, the fewer
clocks that are used, the safer,the design. High fan-out
clocks should always use GClK or AClK. If more than two
clocks are required, the AClKnet can be segmented into
individu\ll vertic;:allines that can be driven by PIPs at the top
and bottom of each column. Clock signals routed through

13-18

AS in most CMOS ICs, almost all FPGA power dissipation
is dynamic, and is caused by the charging and discharging
of internal capacitances. ,EaCh node in the device dissipates power according to the capacitance in the node,
which is fixed for each type of node, and the frequency at
which the particular node is switching, which can be different from the clock frequency. The total dynamic power is
the sum of the power dissipated in the individual nodes.
While the Clock line frequency is easy to specify, it is usually
more difficult to estimate the average frequency of other
nodes. Two extreme case.s <:ire binary counters, where half
the total power is .dissipated in the .first flip-flop, and shift
registers with alternating zeros and ones, where the whole
circuit is exercised at the clocking speed.
A popular assumption is that, on average, each node is exercised at 20% of the clock rate; a major EPlD vendor uses a
16-bit counter as a model, where the effective percentage is
only 12%. Undoubtably, there are extreme cases, where the
ratio is much lower or muCh higher,. but 15 to 20% may be a
valid approximation for most normal designs. Note that global clock lines must always be entered with their real, and
obviously well-known, frequency.
Consequently, most power consumption estimates only
serve as guidelines based on gross approximations. Table
4 shows the dynamic power dissipation, in mW per MHz, for
different types of XC3000 nodes. While not precise, these
numbers are sufficiently, aocurate for the calculations in
which they are used, and may be used for any XC3000/
XC31 00 device. Table 5 shows a sample power calculation.
Table 4:

Dynamic Power Dissipation

One CLB driving1hree local interconnects,
One device output with a
50 ;
pFload
One Global Clock Buffer and line
One Longlinewilhdu! driver'

TableS:

XC3020 XC3090
0.25,
·0.25
mW/MHz
1.25

1,25

mW/MH,z

2,.00
0.10

3,50
0.15

mW/MHz
mW/MHz

Sample P~wei" CaicuiationfodtC3020

2

"

Quantity

•Node

MHz

mW/MHz

~1..

Clock Buffer
CLBs

40
40
20
10
20

2~00

5
10
40
8

20

CLI'!s
CLBs
Longliries
Outputs ;

~O

,mW

,.80,
0.25
50
0.25
50
0.25
100
'16'
0.10
1,25
50P
.
Total Power -800

J.une t, 1996 (Version 1.0)

l::XILINX
Crystal Oscillator
XC3000 and XC3100 devices contain an on-chip crystal
oscillator circuit that connects'to the ACLK buffer, This circuit, Figure 5, comprises a high-speed, high-gain inverting
amplifier' with its input connected to the dedicated XTL2
pin; and its output connected to the XTL 1 pin. An external
biasing resistor, R1, with a value of 0.5 to 1 Mn is required.
A crystal, Y1, and additional phase-shifting components,
R2, C1 and C2, complete the circuit. The capacitors, C1
and C2, in series form the load on the crystal. This load is
specified by the crystal manufacturer, and is typically 20 pF.
The capacitors should be approximately equal: 40 pF each
for a 20 pF crystal.
Either series- or parallel-resonant crystals may be used,
since they differ only in their specification. Crystals constrain oscillation to a narrow band of frequencies, the width
of which is «1% of the oscillating frequency; the exact frequency of oscillation within this band depends on the components surrounding the crystal. Series-resonant crystals
are specified by their manufacturers according to the lower
edge of the frequency band, parallel-resonant crystals
according to the upper edge;
The resistor R2 controls the loop gain and its value must be
established by experimentation. If it is too small, the oscillation will be distorted; if it is too large; the oscillation will fail
to start, or only start slowly. In most cases, the value of R2
is non-critical, and typically is 0 to.1 1<0.
Once the g>mponent values. have been chosen, it is good
practice to test the oscillatorwith a resistor. (:c 1· ill) in series
with the crystal. If the oscillator stil/starts reliably, independent of whether the power supply turns on quickly or sLowly,
it will always work without the resistor.
For operation above 20 to 25 ,MHz, the crystal "must be
operated at its third harmonic. The capaCitor C2 is replaced
by a parallel~resonant LC tank circuit tuned to -213 'of the
desired frequency, i:e., twice the fundamental frequency of
the crystal. Table 6 shows typical component values for the
tank circuit

XTAL..OUT

R1
R2
~--~D~--~--~~
V1

r

--~-I

"l-J~M
"='

Only

X6128

Figure 5: Crystal Oscillator

Table 6:Third-Harmonic Crystal Oscillator Tank-Circuit
LCTank
Frequency
(MHz)
L(~H) C2 (pF) Freq (MHz) R2 (n) C1 (pF)
20,6
60
430
32
1
23
35
1
44
24.0
23
310
31
28.6
190
23
49
1
72
1
18
37.5
150
12

Crystal-Oscillator Considerations
There is nothing Xilinx-specific about the oscillator circuit.
It's a wide-band inverting amplifier, as used in all popular
microcontroliers.When ,a crystal and some passive components close the feedback path, this circuit becomes a reliable and stable clock source.
The path from XTAL2 to XTAL 1 inside the LCA device is a
single-stage inverting amplifier; which means it has a lowfrequency phase response of 180', increasilig by 45' at the
3-d8 frequency.
Input impedance is 10-15 pF,input threshold is CMOS,but
dc bias must be supplied externally through a megohm
reSistor from XTAL 1 toXTAL2.
Low-frequency gain is about 1D,rolling off 3dBl;it 125 MHz.
Output impedance is between 50 and 100n and the capacitance.on the output pin is 10 to 15 pF.
Pulse response is a delay of about 1.5 ns and a rise/fall
time of about 1.5 ns.

June 1, 1996 (Version. 1.0)

13-19

I

XC3000 Series Technical Information

For stable oscillation,
• the loop gain must be exactly one, i.e., the internal gain
must be matched by external attenuation, and
• the phase shift around the loop must be 360 or an
integer multiple thereof. The external network must,
therefore, provide 180 of phase shift.
0

0

A crystal is a piezoelectric mechanical resonator that can
be modeled by a very high-Q series LC circuit with a small
resistor representing the energy loss. In parallel with this
series-resonant circuit is unavoidable parasitic capacitance
inside and outside the crystal package, and usually also
discrete capacitors on the board.
The impedance as a function of frequency of this whole
array starts as a small capacitor at low frequencies
(Figure 6). As the frequency increases, this capacitive
reactance decreases rapidly, until it reaches zero at the
series resonant frequency.

circuit equals the gain in the. FPGA device, and where the
total phase shift, internal plus external, equals 360
0

•

Figure 7 explains the function. At the frequency of oscillation, the series-resonant circuit is effectively an inductor,
and the two capacitors act as a capacitive voltage divider,
with the center-point grounded. This puts a virtual ground
somewhere along the inductor and Cl;luses the non-driven
end of the crystal to be 180 out of phase with the driven
end, which is the external phase shift required for oscillation. This circuit is commonly known as a Pierce oscillator.
0

XC2000IXC3000

Inductiv,e
,

,
,

jmL

Series:

:Parallet
:Resonance

Resonrnce

X5321

,

I--'--~~---+----"Frequency

C~W

r

Practical Considerations

rc~
,~-

-- -- -- -i f -- -- --- --'

X2818

Figure 6: Reactance as a Function of Frequency
At slightly higher frequencies, the reactance is inductive,
starting with a zero at series resonance, and increasing
very rapidly with frequency. It reaches infinity when the
effective inductive impedance of the series LC .. oircuit
equals the reactance of the parallel capacitor. The parallel
resonance frequency is a fraction of a percent above the
. .
series-resonance frequency.
Overthis very narrow frequency range between series.and
parallel resOnance, the crystal Impedance is .inductive and
changes all the way from zero to. infinity. The energy loss
represented by the series resistor prevents the impedance
from actually reaching zero· and .infinitY,·butit comes very
close.
Microprocessor- and FPGA-based crystal oscillators all
operate in this narrow frequency band, where the crystal
impedance can be any inductive value. The circuit oscillates at a frequency where the attenuation in the external

13-20

Figure 7: Pierce Oscillator

• The series resonance resistor is a critical parameter. To
assure reliable operation with worst-case crystals, the
user should experiment with a discrete series resistor
roughly equal to the max internal resistance specified
by the crystal vendor. If the circuit tolerates this
additional loss,. it should operate reliably with a worst· .
case crystal wi.thout the additional resistor.
• The two capacitors affect the frequency of oscillation
and the start-up conditions. The series connection of
the two capacitorsis.the effective capacitive load. seen
by the crystal, usually specified by the crystal vendor. ,
• The two capacitors also determine the minimum gain
required for oscillation. if the capacitors are too small,
more gain is needed, and the oscillator may be
unstable. If the capacitors are too large, oscillation is
stable but the required gain may again be higher. There
is an optimum capacitor value, where oscillation is
stable, and the required gain is at a minimum. For most
crystals, this capacitive load is around. 20 pF, i.e., each
of the two capacitors should be around 40 pF.
• Crystal dissipation is usually around 1 mW, and thus of
no concern. Beware of crY$tals with "drive-level
dependence" of the series resistor. They may not start
up. Proper drive level can be checked by varying Vcc.
The frequency should increase slightly with an increase
in Vcc. A decreasing frequency or unstable amplitude
indicate an over-driven crystal. Excessive swing at the
June 1, 1996 (Version 1.0)

~XILINX

o

o

XTAl2 input results in clipping near Vcc and ground. An
additional 1 to 2 kQ series resistor at the XTAl1 output
usually cures that distortion problem. It increases the
amplifier output impedance and assures additional
phase margin, but results in slower start-up.
Be especially careful when designing an oscillator that
must operate near the specified max frequency. The
circuit needs excess gain at small signal amplitudes to
supply enough energy into the crystal for rapid start-up.
High-frequency gain may be marginal, .and start-up may
be impaired.
Keep the whole oscillator circuit physically as compact
as possible, and provide a single ground connection.
Grounding the crystal can is not mandatory but may
improve stability.

and fastest Xilinx FPGA is compatible with the oldest and
slowest device ever manufactured. The CClK frequency is
fairly insensitive to changes in Vee, varying only 0.6% for a
10% change in Vee. It is, however, very temperature
dependent, increasing 40% as the temperature drops from
25°C to -30°C, (Table 7.)

Table 7: Typical CCLK Frequency Variation
Temp

Vee
4.5V
5.0V
5.5 V
4.5V
4.5V

25°0
25°C
25°0
-30°C
+130°0

Frequency
687
691
695
966
457

kHz
kHz
kHz
kHz
kHz

CCLK Low-Time Restriction
Series Resonant or Parallel Resonant? .
Crystal manufacturers label some crystals' as seriesresonant, others as parallel-resonant, but there really is
no difference between these two types of crystals, they
all operate in the sameway. Everycrystalhas a series
resonance, where the impedance' of . the crystal is
extremely low, much lower than at any other frequency.
At a slightly higher frequency, the crystal is inductive
and in parallel resonance with the unavoidable stray
capacitance or the deliberate capacitance between its
pins.
The only differenc,e between the two types of crystal is
the manufacturer's choice of specifying either of the two
frequel!cies. It series resonance is specified, theactuai
frequency of oscillation isa little higher than the specified value. If parallel resonance is specified,' the. fre-,
quency of oscillation is a' little lower. ,In most cases,
.
these small deviations are irrelevant.

CCLK Frequency Variation
The on-chip R-C oscillator that is brought out as CClKalso
performs several other internal functions.'lt generates the
power-on delay, 2 16 = 65,536 periods for a master)
214 = 16,31;14 periods for a slave Or peripheral device. It generates the·shift pulses for clearing the configuration array,
using one clqck period per frame, and it is the clock source
for several small shift regi~ters acting as low-pass filters for
a variety of input signals.
The nominal frequency of this oscillator is 1 MHz with a
max deviation of +25% to -10%. The clock frequency, t.herefore, is between 1.25 MHz and 0.5 MHz. In the XC4000
family, the1~MHz clock is derived from an internal 8-MHz
'clock that also can be used as. CClK Source.
Xilinx circuit designers make sure that the internal clOlfk frequency does: not get faster as devices are migrated to
smaller geometries and faster processes. Even the newest

June 1,1996 (Version 1.0)

When used as an input in Slave Serial and Readback
modes, CClK does not tolerate a low time in excess of 5
ILs. For very low speed operation, the CClK High time can
be stretched to any value, but the' low time must be kept
short. XC4000 and XC5200 devices do not have this
restriction.

Battery Back-up
Since SRAM-based FPGAs are manufactured using a
high-performance low~power CMOS process, they can preserve the configuration data siored iii the' internal static
memory cells even during a loss of prImary power. This is
accomplished by forcing the device into a low-power nonoperational state, while supplying the minimal current
requirement of Vee from a battery.
Circuil techniques used in XC3100, XC4000 and XC5200
devices prevent Ice from being reduced to the level need
for battery back-up. Consequently, battery back-up should
only
used for XC2000, XC2000l, XC3000; XC30POA
and XC3000l devices.

be

There are two prim~yconsiderationsfor battery backup
which must be accompli~hed by external circuits.
o
o

Control of the Power-Down (PWRDWN) pin
Switching between the primaryVee supply and the
battery.

Important cqnsiderations include the following.
o

o

•

Ins.ure that PWRDWN is asserted logic low prior to Vee
tailing, is held low while the primaryVee is absent, and
returned High after Vee has returned to a hormallevel.
PWRDWN edges'must not rise or fall slowly.
Insure "glitch-free" SWitching of the power connections
to the FPGA device from the prirnafyVee to the battery
and back.
.
Insure that, during normal operation, the FPGAVee is
maintaiti~d at qcGeptable leyef,5:0 V ± 5%(±1 0% for
Industrial and Military).

an

.13-21

I

XC3000 Series Technical Information

Figure 8 shows a power-down circuit developed by She I
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2V primary supply or a 3 V Lithium battery. A Seiko 58054 3-terminal
power
monitor circuit monitors Vcc and pulls PWRDWN low
whenever Vcc falls below 4 V..

vee
IN5817

Seiko S8054 Specifications
Detect Voltage 3.995 V min
4.305 V max
208 mVlyp
Hysteresis
Temp. Coetl, 0.52mVrC
2.6!1A Iyp
'Icc @ +6V

During powerdown, the Vcc monitoring circuit is disabled, It
is then up to the user to prevent Vcc dips below 2.3 V, which
wouid corrupt the stored configuratiori.

IN5817

B35
Lithium
Battery

X5997

Figure 8: Battery Back-up Circuit

Powerdown Operation
A low level on the PWRDWN input, while Vcc remains
higher than 2.3 V, stops all internal activity, thus, reducing
Icc to a very low level:
•
•
•
•
•
•
•

All internal pull-ups (on long lines as well as on the I/O
pads) are turned off.
The crystal oscillator is turned off
All package outputs are three-stated.
AII,package inputs ignore the actual input level, and
present a High to the internal logic.
All internal flip-flops or latches are permanently reset.
The internal configuration is retained.
When PWRDWN is returned High, after Vcc is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and Dip as'at the
completion of configuration.

Things to Remember
Powerdown retains the. configuration, but loses all data
stored in the device. Powerdown three-states al\ outputs
and ignores alt inputs. No Clock signal will be recognized;
and the crystal oscillator is stopped. All. internal flip-flops
and latches are permanently reset and aU inputs are interpreted as High, but the internal combinatorial logic is fully
functional.
.
'

Things to Watch Out For
Make sure that the combination of all inplJts High and all
internal flip-flop outputs low in your design will not generate internal oscillations or create permanent bus contention

13-22

by activating internal bus drivers with conflicting data onto
the same longline. These two situations are farfetched, but
they are possible and will result in considerable power consumption: It is quite easy to simulate these conditions since
all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function
generators.

During configuration, the PWRDWN pin must be High,
since configuration uses It)e internal oscillator. Whenever
Vcc goes below 4 V, PWRDWN must already Qe low in
order to prevent automatic reconfiguration at low Vcc .. For
the same reason, Vcc must first be restored to 4 V or more,
before PWRDWN can be made High.
PWRDWN has rio pull-up resistor. A pull-up resistor would
draw supply ,current wl'len the pin is low, which would
defeat the idea of powerdown, where Icc is only microamperes.

Corifiguration and Start-up
Start-Up
Start-up is the transition from the configuration process to
the intended user operation. This means a change from
one clock source to another, and a change from interfacing
parallel or serial confi.guration data where most outputs are
3-stated, to normal operation with 1/0 pins active in the
user-system. Start-up must make sure that the user-logic
"wakes up" gracefully, that the outputs become active without causingcoritention with the configuration Signals, and
that the internal flip-flops are released from the global
Reset cir Set at the right time.
Figure 10 describes Start-up timing for the XC3000 families
in detail.
.
.
DONE can be programmed to go High one CClK period
before or after the lID become active. Independent of
DONE, the internal global Resetis de-activated one CClK
period before or after the 1/0 become active ..
The default opti()n, and the most practical one, is for Do'NE
to go High first, disconnedingthe configuration data source
and avoiding any contention wilen the I/0sbecome' actiVe
orie clock later. Reset Isthen released anotherclcick period
later to make sure that user-operation starts from stable
internal conditions. This is the most common sequence,
shown with heavy lines in Figure 11, but the designer can
modify it to meet particular requirements.
Until the cllip goes active after configuratioh, all 1/0 pins not
involved in the configuration process remain' in' a highimpedance state with weak pull-up resistors; .all internal
flip-flops and latches are held reset. Multiple FPGA devices
hooked up in a daisy chain will all go active simultaneously

June 1, 1996 (Version 1.0)

~XIUNX

CCLK

unasserted, but 0 remains High since the function generator acts as an R-S latch; Q stays Low, and RESET is still
pulled High by the external resistor. On the first system
clock after configuration ends, Q is clocked High, resetting
the latch and enabling the output driver. which forces
RESET Low. This resets the whole chip until the Low on Q
permits RESET to be pulled High again.
The whole chip has thus been reset by a short pulse instigated by the system clock. No further pulses are generated, since the High on LOC prevents the R-S latch from
becoming set.

Figure 9: Start-up Timing
on the same CCLK edge. This is well documented in the
data sheets.
Not documented, however, is how the internal combinatorial logic comes alive during configuration: As configuration
data is shifted in and reaches its destination, it activates the
logic and also "looks at" the lOB inputs. Even the crystal
oscillator starts operating as soon as it receives its configuration data. Since all flip-flops and latches are being held
reset, and all outputs are being held in their high-impedance state, there is no danger in this "staggered awakening" of the internal logic. The operation of the logic prior to
the end of configuration is even useful; it ensures that clock
enables and output enables are correctly defined before
the elements they control become active.
Once configuration is complete, the FPGA device is activated. This occurs on a rising edge of CCLK, when all outputs and clocks that are enabled become active
simultaneously. Since the activation is triggered by CCLK, it
is an asynchronous event with respect to the system clock.
To avoid start-up problems caused by this asynchronism,
some designs might require a reset pulse that is synchronized to the system clock.
The circuit shown in Figure 10 generates a short Global
Reset pulse in response to the first system clock after the
end of configuration. It uses one CLB and one lOB, and
also precludes the use of the LOC pin as I/O.
During Configuration, LOC is asserted Low and holds the
O-input of the flip-flop High, while Q is held Low by the internal reset, and RESET is kept High by internal and external
pull-up resistors. At the end of configuration, the LOC pin is

Beware of a Slow-Rising XC3000
Series RESET Input
It is a wide-spread habit to drive asynchronous RESET
inputs with a resistor-capacitor network to lengthen the
reset time after power-on. This can also be done with Xilinx
FPGAs, but the user should question the need, and should
beware of certain avoidable problems.
Xilinx FPGAs contain an internal voltage-monitoring circuit,
and start their internal housekeeping operation only after
Vee has reached -3.5 V. The internal housekeeping and
configuration memory clearing operation then takes
between about 10 and 100 ms, depending on configuration
mode and processing variations. Any RC delay shorter
than 40 ms for a device in master configuration mode, or
shorter than 10 ms for a device in slave configuration mode,
is clearly redundant.
A significantly longer RC delay can be used to hold off configuration. Without the use of an external Schmitt trigger circuit, the rise time on the RESET input will be very slow, and
is likely to cross the threshold of -1.4 V several times, due
to external or internal noise. This can cause the FPGA to
start configuration, then immediately abort it, then start it
again, after having automatically cleared the configuration
memory once more.
This is no problem for the FPGA, but it requires that the
source of configuration data, especially an XC1700 serial
PROM, be reset accordingly. This is another reason to use
the INIT output of the lead FPGA, instead of LOC, to drive
the RESET input of the XC1700 serial PROMs.

Figure 10: Synchronous Reset

June 1, 1996 (Version 1.0)

13-23

I

XC3000 Series Technical Information

13-24

June 1, 1996 (Version 1.0)

FPGA Configuration Guidelines
Application Note By PETER ALFKE

June 1, 1996 (Version 1.0)

Summary
These guidelines describe the configuration process for XC2000, XC3000 and XC4000-Series FPGA devices. The average
user need not understand all details, but should refer to the debugging hints when problems occur.

The XC2000, XC3000, and XC4000 series FPGAs share a
basic configuration concept, and can be combined in a
common configuration bitstream, but there are small differences among the three families as described below.
Following their initial power-on configuration-memory initialization, these Xilinx FPGAs are configured by a serial configurationbitstream. The byte-parallel configuration modes just
activate an internal parallel-to-serial converter, and then use
the serial bitstream internally. Express mode in XC4000EX
operates on 8 bits in parallel. This mode is not covered in this
application note. The software generates a bitstream that
starts with a 40-bit header, see Figure 1.
Each device uses a few of the leading 1s to prepare forconfiguration, then detects the 0010 pattern and stores thefollowing 24 bits as a length-count value in an internal
register. The content of· this register is continuously com·
pared against a running counter that increments on every
rising CCLK edge. CCLK is either an output (in Master and
Asynchronous Peripheral modes) or an input (in Slave
Serial and Synchronous Peripheral modes). In all modes, it
is the externally observable Low-to-High transition on the
CCLK pin that causes the internal action. Every CCLK rising edge that oCcurs while INIT and RESET are High is
counted, even during the preamble. Note that XC2000 and
XC3000 use quasi-static circuitry which imposes a 5 IlS
max limit on the CCLK Low time, while XC4000 is completely static. and has no max CCLK time limit. This is, of
course, only of interest in XC2000 and XC3000 Slave
Serial mode, where CCLK is g.enerated by the user.
While it is permissible, although not meaningful, to modify
the number of leading ones by adding additional ones, or
subtracting up to four ones, this would inevitably affect the
number of CCLK pulses received by the counter, and thus
change the moment when the internal counter is equal to
the.value stored in the length-count register. Don't add or

delete preamble-leading ones!

I

1111111111 0010 (MS8) 24-8;t Length Count(LS8) 111111 Data
X5553

Figure 1: 40-8it Header

June 1, 1996 (Version 1.0)

Each device passes the incoming header, including the
length-count value, on to the DOUT pin, delayed by half a
CCLK period, i.e. the bits are clocked out on a falling CCLK
edge. In this way, the header is passed on to all devices that
might be connected in a daisy-chain. After the length-count
data has been passed on, DOUT goes active High and
stays High until the device. has been filled with the appropriate number of configuration frames. After that, DOUT again
passes all incoming configuration data on to other devices
that might .be part of the daisy chain.
DOUT is thus the best observation point to see whether the
configuration process has started properly.
Immediately following the header, configuration data is
received, formatted in a device-specific sequence of
frames. Each frame starts with a single 0 as start bit, followed by a device-specific number of configuration bits per
frame, followed by three is as stop bits (XC2000, XC3000)
or, in XC4000, by four bits that are either 0110, orfour bits
of a running 16-bit CRC error-checking code. (The choice is
made in Makebits, where the default is "CRC disabled").
The header is not included in the CRC calculation.
Each frame is physically shifted into a serial shift register
that had been preset to all ones. When the zero start bit hits
the far end of this shift register, the data frame is transferred
in parallel into the configuration memory, as addressed by
the pOSition of an internal token or pointer. The three stop or
four error-check bits provide ample time for this transfer,
even at the 10 MHz CCLK rate ailowedforXC3000 and
XC4000 devices. After this transfer, the shift-in procedure
continues with the following frame. Note that there is no
counter for the number of bits in the frame or for the number
of frames. The operation is self-synchronized by detecting
the presence of a start bit at the far end of the shift register,
and by moving the frame pointer.
Each Xilinx FPGA requires a number of configuration bits
that is device-dependent, but independent ofthe configuration content, and independent of the configuration mode.
The number of configuration bits per device varies from
12,038 for the XC2064 to 422,168 for the XC4025, roughly
20 bits per gate. The exact numbers of configuration bits
are.listed in the specific family data sheets.

13-25

I

FPGA Configuration Guidelines

Protection Against Data or Format
Errors
The serial configuration scheme has proven reliable in
thousands of designs and millions of devices, but there
have been cases where an erroneous bitstream was
loaded accidentally. The original XC2000and XC3000
devices provide no effective protection against this type of
error. If long enough, any random sequence of Os and 1s
will configure a device. This inevitably takes more CCLK
pulses than specified in the length-count value. This means
that the CCLK counter equals the length-count value before
the FPGAs are filled. This comparison is, therefore,
ignored, and an additional 16 million CCLK pulses are
required to roll the 24-bit length counter and finish the configuration. Such a configuration will, of course, be wrong
and might result in excessive power consumption due to
internal or external contentions.
XC3000A, XC3100A, XC3000L and XC3100L devices use
a simple and effective method to protect against erroneous
configuration files or against loss (or gain) of CCLK pulses:
All Xilinx FPGA devices recognize a new frame when its
leading zero reaches the end of the shift register. XC2000,
XC3000, and XC3100 devices do not check for the presence of valid stop bits, but XC3000NXC3100NXC3000U
XC3100L devices always check whether the three bits at
the end of the defined frame length are 111. If this check
fails, INIT is pulled Low and the internal configuration is
stopped, although a master CCLK keeps running. The user
must recognize this state and start a new configuration by
applying a >6 Ils Low level on RESET. .
This simple check does not protect against single-bit random errors, but it offers almost 100% protection against
erroneous configuration files, defective configuration data
sources, synchronization errors between configuration
source and FPGA, as well as PC-board defects, such as
broken lines or solder bridges.
The XC4000 series uses, optionally, four bits of a running
16-bit cyclic redundancy check code at the end of each
frame, combined with additional CRC bits at the end of the
bit stream. These error-detecting CRC codes provide
excellent protection against errors, even those that do not
change the frame structure. When an error is detected,
INIT goes Low and stays Low until the user initiates a
reconfiguration. (A master device does, however, continue
generating CCLK pulses and incrementing or decrementing the parallel PROM address).

Daisy-Chain Operation
Multiple FPGAs can be configured by a single concatenated bitstream. The device daisy chain is formed by connecting DOUT to the next device's DIN, and connecting all
CCLK pins in parallel. Since DOUT goes active on a falling
clock edge, and DIN is used on the subsequent rising clock
edge, each DOUT-to-DIN connection adds one extra bit of
delay to the bitstream. Since the header is passed through
all devices, they all receive this information almost simultaneously (staggered by one bit per device), but all devices
maintain perfect synchronism between their CCLK
counters.
Xilinx recognizes the need for all devices in a daisy chain to
finish their configuration and begin user operation simultaneously, as a result of one common CCLK edge. Therefore,
all devices in a daisy-chain need a common timing reference. They cannot rely on the start pattern received
through the pipelined chain, but must all count the common
CCLK pulses exactly the same way. This explains the
importance of well-defined configuration clocking.

Start-Up Procedure
The transition from configuration to user operation faces
several difficulties. During configuration, all outputs that are
not involved in the configuration process are 3-stated,
although the crystal oscillator circuit is activated as soon as
possible. All internal flip-flops and latches are held reset
(set or reset in XC4000), and the DONE output is held Low.
At the end of configuration, these three conditions must
change: As shown in detail in Figure 2, the three families
offer different options:
XC2000 has no options; the Il0s go active one CCLK
period after length-count match. DONE goes active and the
global reset is released one CCLK period later.
XC3000 makes the Il0s go active two CCLK periods after
length-count match; but DONE and the release of the global reset can each occur either one CCLK period before or
after the II0s go active: The default is "early DONE and late
release of the global reset". This makes the outputs go
active while the internal logic is still held reset. The other
Makebits option, "early release of global reset", lets the
internal logic be clocked out of its reset state before the outputs go active.

Normally, there is no defined timing relationship between
the last configuration events triggered by the rising edge of
CCLK, and the subsequent events that are controlled by
the system clock. The user must be aware of the potential
problems of this asynchronous relationship. See the
XC4000 solution described below.
XC4000 has more options for the relative timing of 1I0s,
DONE and GSR, the release of the global set or reset.

13-26

June 1, 1996 (Version 1.0)

·~XILINX

CCLK

XC2000

XC3000

.XC40001
XC5200

I
-'---'-'-l~~::~=~
Note: Thick lines are ~fauJt-option

Figure 2: Start-up Timing

June1, 1996 (Version 1.0)

UYJ-K Period

=

F Fir:tished. no more
configuration clocks needed
Daisy-chain lead device
must hav.e latest F
Heavy lines describe
.default timing

X5972

FPGA C~nflguratlon Guidelines
XC4000 can also use DONE as an input to hold off the activation of the I/Os and the release of GSR, until DONE is no
longer pulled Low. The change then takes place either
immediately upon the release of DONE, or as a result of the
next CCLK rising edge. When all DONE pins in a daisy
chain are interconnected, this start-up mode guarantees
that all devices in the daisy chain will go active only when
all of them have reached the DONE state, another protection against configuration errors.
XC4000 can' also be configured to employ the system
(user) clock instead of CCLK, again either using DONE as
an output, or as a bidirectional pin.
The user clock provides a properly synchronized and racefree transition from the end of configuration to the beginning of user operation. The unspecified on-chip delay in the
release of GSR (about 100 ns in XC4013) requires some
caution, however, when using a high clock frequency for
configu ration.
While XC2000, XC3000, and XC4000 can be arbitrarily
interspersed in a daisy-chain, there is one restriction: the
lead device must belong to the highest family in the chain. If
the chain contains XC4000 devices, the lead device cannot
be XC2000 or XC3000; if the chain contains XC3000, then
the lead device cannot be XC2000. The reason is shown in
Figure 2. Since all devices in the chain store the sarrie
length-count value and generate or receive one common
sequence of CCLK pulses, they all recognize length-count
match on the same CCLK edge. The master device then
generates additional CCLK pulses until it reaches its finish
point F. As shown in Figure 2, the different families generate
and require different numbers of additional CCLK pulses
until they reach F. Not reaching F means that the device
has not really finished its configuration process, although
DONE may have gone' High, the outputs became active,
and the internal reset has been released. For XC4000, not
reaching F means'that READBACKc~nnot be initiated, and
most boundary scan instructions cannot be used. This limitation has been criticized by designers who want to use an
inexpensive lead device in Peripheral Mode, and save the
more precious XC4000 I/O pins. Here is a solution for that
case (Figure 3):
One CLB and one lOB in the lead XC3000 device are used
to generate the additional CCLKpuise required by the
XC4000 devices. When the lead device releases its internal
reset signal, the 2-bit shift register starts responding to its
clock input, and it generates an active Low output signal for
the duration of one clock period. An external connection
between this lOB pin and the CCLK pin thus creates the
extra CCLK pulse. This solution requires one CLB,. one lOB
and pin, and an internal clock SOurce with a frequency of up
to 5 MHz. Obviously, the XC3000 lead device must be configured with late internal reset, which happens to be the
default option.

13-28

Output
Reset
o 0
1
0
1
1
o 1
o 1
etc

'-----'----.,. Connected
to CCLK

Active Low Output
Active High Output
3-Stated Output
3-Stated Output
X5552

Figure 3: Addlticmal CCLK-Pulse Generator

Configuration Modes
There are six different configuration modes, hardwareselected by applying logic levels to the three mode inputs,
MO, M1, and M2. The six modes are: Master Serial, Master
Parallel Up, Master Paralfel Down, Synchronous Peripheral
(XC4000 only), Asynchronous Peripheral, and Slave Serial.
In Master modes, the FPGA addresses an external PROM
or EPROM storage device, and reads data from it. No additional timing or control signals are used.
In Peripheral mode, the FPGA accepts byte-wide data (bitserial in XC2000), and interacts with the source of data,
usually a microprocessor, with a Ready/Busy handshake.
In Slave mode, the FPGA receives bit-serial data and a
clock from an external data and timing source, either from a
microprocessor, or from the lead device in an FPGA-daisy
chain.
The modes are selected by putting the appropriate logic
levels on the three mode inputs, MO, M1, and M2 prior to
the. beginning of configuration. These three pins can be
hardwired to Vee or Ground, but they can then never be
used as user I/O. It is better to force a mode pin Low with a
3 kQ pull-down resistor to ground, acting against the 50 to
100 kQ internal pull-up resistor, and to rely on the built-in
pull-up resistor to establish a High level on the M1, M2
mode pins, and a50 kQ external pull-up resistor on MO.
This eliminates the restrictions on using M2 as logic output
on XC2000 and XC3000, or M1 on XC4000, and the use of
M1 as readback data output in XC2000 and XC3000.
When mode pin levels are driven by external logic, these
levels must be established very soon after power-up.
Establishing a mode level later might eliminate the extra
master power-on delay that makes a master wait for slave
devices to be ready after power-on. Delaying mode levels
until the beginning of configuration will obviously cause the
configuration to fail. Note that some EPLD devicesha.ve
surprisingly long. power-up delays. Be very careful when
controlling mode levels in creative ways.

June 1, 1996 (Version 1.0)

~XILINX
Selecting the Best Configuration Mode

•

The selection of the most appropriate configuration mode is
influenced by many factors, like

•

•
•
•
•

the need for interface simplicity,
the need for rapid configuration,
the need for multiple configuration sources,
the availability of a microprocessor-based configuration
driver.

The simplest interface is Master Serial, using only two
FPGA pins, CCLK and DIN, and no external timing or control signals.
The fastest configuration mode is Slave Serial or XC4000
Synchronous Peripheral. In these modes, the user can supply a well-defined CCLK frequency of up to 10 MHz for all
XC3000 and XC4000 5-Volt devices. No other configuration
mode is that fast. For prototyping and rapid configuration
change, the PC can configure the FPGA directly in Slave
Serial mode, using the Xilinx-provided Download Cable or
XChecker.

•

•

•

Multiple configuration codes are most conveniently stored
in a microprocessor memory, using Peripheral mode to
configure the FPGA. For field upgrades, Peripheral mode
offers the greatest flexibility. New files can be supplied via
diskette or modem, and can be downloaded by the microprocessor.

When Configuration Fails
General Debugging Hints for all Families
If the DONE output does not go High, there are several
things to check.
•

•

•

•

•

Checking all supply and configuration-related pins with
an oscilloscope or logic analyzer can reveal wiring
errors, bad socket pins, noisy ground, noisy CCLK, a
serial configuration PROM V pp pin not connected to
Vee, PWRDWN not pulled High, poor or noisy RESET,
missing pull~up resistors on DONE (or INIT in the
XC3000), etc.
Monitor the DOUT pin of the lead device, i.e. the FPGA
that is either configured alone, or forms the beginning of
adaisy chain. At the start of configuration, you should
see the 40-bit header shOwn in Figure 1. After this
sequence, the DOUT pin remains High until the device
has received all its data. Then, the device becomes
transparent and passes additional data (provided there
is a daisy chain) through the DOUT pin to the Slave
devices. If you don't see this pattern, you have a gross
error somewhere. Check the following items:
INIT going Low again after configuration start indicates
a configuration bitstream or framing error in XC3000A,
XC3000L or XC4000 families.
If RESET is used to delay configuration, make sure it
has a rise time of <100 ns and that it is glitch-free.

June 1,1996 (Version 1.0)

Ringing on the CCLK line can cause spurious clocking
and loss of frame synchronization in the FPGA.
Configuration functions can be disrupted by Signal
contention between configuration inputs and the FPGA
user outputs which become active at the end of
configuration. This change is indicated by I/O pins going
active and HDC/LDC no longer at their configuration
levels. Contention can be avoided by rearranging pinouts, maintaining additional 3-state control of user-I/O
outputs, or matching start-up output levels to the
configuration input levels on inputs other than chipselect. It is also possible to use a series resistor (1-10
kQ) to provide isolation between conflicting signal
sources that could occur after configuration is complete.
If an FPGA heats up significantly, this is usually the
result of applying the wrong bitstream, e.g. the
bitstream for a different device, causing contention.
During reprogramming, user logic must generate a
time-out that insures all devices have completed the
Clear cycle before any configuration data is sent.
Removing the FPGA supply voltage while externally
powered signals continue to drive input pins, might
keep the FPGA Vee pins at a 0.5-to-2.0 V level, which
can leave the FPGA in an invalid state. The FPGA
input-protection diodes are there to clamp input-voltage
excursions to the two supply connections. When the
FPGA supply voltage falls more than 0.5 V below an
active input signal, this input signal will supply
degenerate Vee levels. If the input signals are not
current-limited, the FPGA inputs can even be damaged
by the excessive input current.
If extraneous CCLK pulses are applied after Clear but
before the beginning of the header, the internal clock
count will. equal the stored length-count value before the
configuration data is completely loaded. In .this case,
the DONE output does not become active until the clock
counter equals length count a second time. This
requires 224 extra clocks, or about 20 s at the typical
rate of 0.7 MHz.

Whenever configuration. takes. 15 to 25 seconds, this is
due to a mismatch between length count and the number of CCLK pulses received.
•

•

XChecker or the XACT Download Cable provide an
alternate method of configuration to verify configuration
data and to isolate wiring errors, such as interchanged
or inverted configuration data or control signals.
Try a different device. Although the chips are 100%
factory-tested, an individual device might have been
damaged later.

13-29

I

~XILINX
Asynchronous Peripheral Mode
o
o

Review the general debugging hints.
Check the mode pin levels.

Slave Serial Mode
o
o

MO = 1, Ml = 0, M2 = 1 for Peripheral mode
o
o

See schematics on pages 2-40 and 2-128.
Verify that'the FPGA is receiving data at its input pin(s)
and that it is receiving valid Write-Strobe and ChipSelect signals. If not, check the device driving the
FPGA. Make sure that these signals meet the timing
requirements listed in the product family
documentation.
XC3000 Family: Check that the minimum W~ite-Strobe
active time (TCA min = 100 ns) is met and observe the

MO =1, Ml = 1, M2 = 1 for Slave Serial mode
o
o

o

ROY/BUSY signal.
XC2000 Family: Be sure maximum and minimum
Write-Strobe active times (TCA max = 5.01LS, min= 0.25

IlS) are met.
o

o

Make sure that the FPGA is ready to receive data.
XC3000 Family: On power up, make sure that the INIT
pin has gone High, or wait at least 34 ms before you
begin sending data to the FPGA. Make sure that the
ROY/BUSY signal is High before sending each data
byte.
XC2000 Family: On power up, make sure that the.
FPGAhas had time to "wake up;' at least 34 ms, before
sending it data,
Check for contention between the Chip .Select and
Write Strobe signals and monitor the levels on those
pins after configuration. It is best to use the.Chip Select
, pins only as. inputs after configuration. Avoid .contention
if they are used as outputs. With XC2000 family
devices, the I/Os become active before the FPGA
receives its final data bits and clocks, and also before
the DONE pin goes High. If the user function for any of
the Chip Selects or the Write Strobe become outputs
after configuration, they could contend and, in effect,
de-select the FPGA so that it never receives its final
data bits. See also next page, left column. Beware of

contention/
o

Check for contention between the FPGA pins and other
signals on the board.
XC4000 and XC3000 Families: Data is received as
eight bits in parallel. Make sure bit 0 is connected to the
00 pin, bit 1 to 01 pin, etc.
XC2000 Family: Data is received serially. If a PROM
file is used as a data source, check that data is properly
serialized LSB first. Data must be LSB first, although
length count is MSB first.

June 1,1996(Version 1.0)

Review the general debugging hints.
Check the mode pin levels.

o

o

See schematics on pages 2-35 and 2-130.
Make sure Vcc, RESET, and PWRDWN are at 5 V, and
ground pins are at 0 V. '
Verify that the FPGA is receiving data on DIN and that it
.
is receiving a valid clock signal on CCLK.
Check the device sending the data.
Check the device sending the clock signal, and make
sure the clock meets the timing requirements specified
in the product family documentation. A CCLK generated
by a Master FPGA always meets the timing requirements.
Don't violate the XC3000 andXC2000 CCLK Low time
specification 015.0 IlS.
Make sure the FPGAis ready to receive data.
XC3000 Family: On power up, make sure the INIT pin
is High or wait at least 34 ms before you begin sending
data to the FPGA.
XC2000 Family: On power up, make sure that the
FPGA has had time to "wake up" at least 34 ms, before
sending it data.
At power uP. make sureVCC rises from.2.0 V.to 4.5 V in
less than 25 ms. If it does not, hold RESET Low until
the VCC pins reach 4.5 V.

Daisy Chain Debugging Hints
o

•

o

o

•

The key to debugging daisy-chain configurations is to
isolate the problem and attempt to configure a single
FPGA. Remove all but the first device from the board
and configure it. Then insert the second device and
configure both. Repeat as you add one device at a time
until they all configure.
The first device in the chain can be in any of the
configuration modes. Debug it first, using the hints
provided for the appropriate mode.
All devices after the first one are in Slave Serial mode,
so refer to the Slave Serial mode debugging hints above
to solve any problems with Slave device.
Monitor the DOUT pin of each device in the chain and
verify that the 40-bit header appears at the beginning of
configuration, staggered by one CCLK period per
device:
If the Master device in the chain is an XC2000-family
device and the Slaves are XC3000-family, make sure
the XC3000-family devices are configured with early
DONE.

13-31

I

FPGA Configuration Guidelines

Potential Length-Count Problem in Parallel
or Peripheral Modes
It is highly desirable that the complete change from configuration to user operation occur as the result of one single
byte-wide input. The activation of outputs and DONE, the
de-activation of the global reset (set/reset in XC4000), and
the progression to the "finished" state F (see Figure 2)
should all occur as a result of one common byte input.
Under normal circumstances, the software achieves this by
manipulating the length-count value appropriately, taking
into account the additional bits between devices, and
adjusting for the fact that byte-wide interfaces always leave
the last bit sitting in the P-S converter, shifting it out at the
beginning of the next byte. These complexities, combined
with the many possible daisy-chain arrangements have
occasionally led to problems, where the device outputs go
active before the last required byte had been received.This
can lead to contention on the address outputs or data
inputs and might prevent the device from going DONE, or
reaching the real end of its configuration sequence. Not
reaching this "finished" state limits the use of Jeadback and
boundary scan. A new Makebits option solves this problem:
Since XACT 5:0, the default option is "Length-Count
aligned" which adjusts the length-count value such that
length-count match occurs during the first bit in the last
configuration byte. This assureS sufficient CCLK pulses to
complete any selected type of start-up sequence. The other
option is "DONE-aligned", which adjusts length count value
to make DONE go active at the end of a configuration data
byte, which can cause problems in Peripheral mode.

Only Peripheral modes seem to be sensitive to the dif·
ference between these two options.

Miscellaneous Notes
CCLK is the most important configuration signal. Once the
INIT output is High, each device counts every Low-to-High
transition of this configuration clock. In all modes except
Slave Serial and XC4000 Synchronous Peripheral, CCLK is
a very fast Ol-!tput that cannot be made slew-rate limited.
When distributing this clock, the u.ser should pay special
attention to glitches, overshoots, and unders!'lOots. In severe
cases, a 33 n reSistor in series with the CCLK output might
improve the signal integrity. In other cases, it might pe better
to provide a pull-up resistor at the far end of the CCLK net.
Since the clock net has a transmiSsion-line characteristic
impedance of always less than 100
the limited output
drive capability of the CCLK output precludes proper parallel
termination.

n.

DOUT is an exc.ellent observation point, since every device
must output the preamble on this pin, irrespective of the
selected configuration mode, and irrespective of the position in, or the existence of, a daisy chain.
INIT of all XC4000 and XC3000 devices in a daisy chain
should be interconnected to prevent the configuration from
starting before all devices are ready. A 10 kn pull-up resistor is recommended. The parallel INIT of. the daisy-chained
devices must be connected to the INIT of the lead XC4000
device, or to the RESET input of the lead XC3000 device.
This is especially important for re-configuration, where the
master does not have a four-times longer wait period.
The DONE output indicates the end of the configuration
process. In XC2000 and XC3000 systems, it makes sense
to ground DONE permanently. The RESET input then
becomes the reconfiguration input, and cannot be used as
the dedicated asynchronous user RESET input. LDC can
be used to .indicate end of configuration.
PWRDWN (on XC2000 and XC3000 devices) must be High
before and during the configuration process.

Don't let PWRDWN float!

13-32

June 1, 1996 (Version 1.0)

Configuring Mixed FPGA
Daisy Chains
June 1, 1996 (Version 1.0)

Application Note by PETER ALFKE

Xilinx FPGAs can be configured in a common daisy-chain
structure, where the lead device generates CCLK puls~s
and feeds serial configuration information into the next
downstream device, which in turn feeds data into the next
downstream device; etc. There is no limit to the number of
devices in a daisy chain, and XC2000, XC3000, XC4000,
and XC5200 series devices can be mixed freely with only
one constraint: the lead device must be a member of the
highest-order family used in the chain. (For the purposes of
this discussion, there is no difference between the XC4000
series and the XC5200 family, when XC5200 is used in any
configuration mode except Express Mode). The lead device
must generate a sufficient number of CCLK pulses after
length-count-match was achieved, but XC3000-series
devices generate fewer CCLK pulses than XC4000-series
or XC5200-family devices require, and XC2000 devices
generate even fewer· CCLK pulses after length-count
match. See Figure 1.
In a daisy-chain, all CCLK pins are interconnected, and
DOUT of any upstream device feeds the. DIN ippu! of its
downstream neighbor. Those are the basic connections.
For control purposes, it is advisable to jnterconnec:t all the
slave INIT pins (the XC2000 does not have this pin) and
connect them to the INIT pin of the lead XC4000IXC5200
device or the RESET input of the lead XC3000 device.
Interconnected INIT pins prevent the. master from starting
the configuration process until all slaves are ready. For
power-up this is assured automatically, since the master
uses four times as many internal clocks for the power-up as
any slave does, but, when re-configuring, master and slave
devices consume the same number of clocks to clear a
frame, and a fast master might be ready before a slow slave
is. Interconnecting INITs solves this problem.
The DONE/PROG (DiP) and RESET pins· (XC2000,
XC3000) and the XC40DOIXC5200 PROGRAM pins can be
used in different ways, depending on the desigoer'spreferences regarding reconfiguration, pin .utilization, and need
for a global RESET input. . -..
.
If there is no need for a global logic RESET input, then it is
best to permanently ground the XC2000/30DD Dff> pin,
which means that the RESET input functions as the Reconfigure input, and should be connected to all XC40001
XC5200 PROGRAM inputs.

I
Note: Thick lines are default option

F = Finished" no more

configuration clocks n~ded
Dalsy-chain lead device
must have latest F
'

Heavy Jine-a pescribe

~ de~ulfti.~ing

>'

?<5972

Figure1: Starf-up Timing .

June 1;1996 (Version 1.0)

13-33

Configuring Mixed FPGA Daisy Chains
put) and that, if Serial mode is chosen for the lead device,
the XC1700 device(s) store only one configuration for the
whole daisy chain. The serial PROM(s) must, therefore, be
reset before the daisy chain is to be (re)programmed.

Vee
REPROGRAM

>-_4----. To
All DIP
Wired Together
)0-"'-- To All RESET, Except
Lead Device

From AIlINIT

Pins Wired -

. ~~-:L.J<>--" To RESET of

Lead Device

Together

X59B2

Figure 2:
If there is a need for a global logic RESET input that can
reset all flip-flops in the user logic without causing reconfiguration, then external logic .f)1ust combine RESET and DIP
in such a way, that pulling Low RESET does not affect DIP.
but pulling Low Dip also pulls down RESET. See Figure 2.
The following simple recommendations guarantee a welldefined beginning for any FPGA configuration or reconfiguration process, after the initialization and clearing of the
configuration memory in all FPGAs has been completed,
and the address counter in the serial PROM(s) has been
reset.
The connections described below guarantee reliable operation even under adverse operating conditions such as Vee
glitches.
The lead device can use any configuration mode available.
In all modes except Slave Serial, its CCLK pin is the output
that clocks all other devices.

There are three possible types of daisy chains using
XC3000 and XC4000IXC5200 devices. Here are the recommended connections for the configuration control pins.
Case 1:
Daisy chain consists of nothing but XC300o-series
devices:
Use lead device's LDC to drive XC1700 CE.
Use lead device's INIT to drive XC1700 RESET.
Interconnect all slave INITs and connect them to the lead
RESET input.
Interconnect all DONE pins.
Interconnect all slave RESET inputs
Instigate Reprogram by pulling the slave RESET net Low
for at least 6 ~s while all DONE pins are Low.
(DONE can be permanently wired Low, but that sacrifices
the use of RESET as a global reset of the user logic. If
DONE is not wired Low, reprogram must pull DONE Low
with an open-collector or open-drain driver):
Case 2:
Lead device is XC4000-series or XC5200 family, driving
any mixture of XC3000, XC4000 and XC5200 devices:
Use lead device's LDC to drive XC1700 CE.
Use lead device's INIT to driveXC1700 RESET.

Obviously, all CCLK and XC1700 CLK pins must be interconnected, the DATA outputs from multiple XC1700 serial
PROMs must be interconnected and connected to the DIN
input of the lead device, and the daisy-chain must be established by connecting each DOUT output10 the downstream
DIN input.

Interconnect all XC3000 RESET inputs.

Configuration control pins are:

Combine these two nets into one PROGRAM/RESET net

XC3000, XC3000A, XC3000L, XC31 00, XC3100A:

Instigate Reprogram by pulling the combined PROGRAMI
RESET Low.

DONE/PROGRAM (open-drain outpuVinput)
RESET (input)
INIT (open-drain output)
XC4000 Series (XC4000, XC40POA, XC4000D,
XC4000E, XC4000EX, XC4000H) andX~5200-family:
DONE (open-drain output I input)
PROGRAM (input)
INIT (open-drain output I input)
XC1700:
RESET (inputwith programmable polarity)
The following recommendations assume that there are. no
XC2000 devices in the daisy chain (they lack the INIT out-

13-34

Interconnect alilNIT pins.
Interconnect all DONE pins.
Interconnect all XC4000/XC5200 PROGRAM inputs.

Case 3:
Daisy chain consists of nothing but XC40001 and
XC5200-type devices:
Use lead device's LDC to drive XC1700 CE.
IJse .Iead device'slNIT to drive XC1700 RESET.
Interconnect all INIT pins:
Interconnect all DONE pins (only required for UCLK-SYNC
option).
Interconnect all XC4000IXC5200 PROGRAM inputs.
Instigate Reprogram by pulling PROGRAM Low.

June 1, 1996 (Version 1 .0)

Configuration Issues:
Power-up, Volatility, Security,
Battery Back-up
Application Note by PETER ALFKE

June 1, 1996 (Version 1.0)

Summary
This application note covers several related subjects: How does a Xilinx FPGA power up, and how does it react to powersupply glitches? Is there any danger of picking up erroneous data and configuration? What can be done to maintain
configuration during loss of primary power? What can be done to secure a design against illegal reversecengineering?

Xilinx Famiiies
XC2000, XC3000, XC4000, XC5200

Power-Up
Here is a detailed description of XC3000 'Series, XC4000
Series and XC5200 !leviee behavior during supply ramp-up
and ramp~down.
When Vee is first applied and is still below about 3 V, the
device wakes up in the pre-initialization mode. HDCis High;
INIT, LDC and DONE or DONEIPHOG (DIP) are Low, and
all other outputs are 3~stafed with aweak pull-up resistor.
When Vee has risen to a value above -3 V, anda 1 and a 0
have been successfully written into two special cells in the
configuration memory, the ihitialization power-on time delay
IS started. This delay compensates for differences in Vee
detect threshold ahd infernar CCLK oscillator frequency
between different devices in a daisy chain. The initialization
delay counts clock periods of an on-chip oscilfator'(CCLK)
which has a 3:1 frequency uncertainty depending on processing, voltage' and temperature. Time-out,therefore,
takes between 11 and 33 ms for a slave device, four times
longer for a master device.
This factor of four makessurs that even the fastest m'aster
will always take longer Ihahany slave. We'assume that the
worst- case differente' between 33 ms and 4 11 ms is
enough to compensate for the Vee rise lime spentbetween
threshold differences (max 2 V) of,devicesin a daisy chain.
Only in cases·of very slow Vee rise time (;-25 ms), must the
user hold RESET Low,until Vee has reached a proper level,
Interconnecting tile INIT pins of. all devices in a daisy-chain
is a better method of synchronizing start-up, but cannot be
used with XC2000 devices; since they lack an INIT pin.

x

After the end of the initializatioh time-out, each device
clears i!sconfiguration memory in a fraction of a millisecond, then tests for inactive RESET or PROGRAM, stOres
the MODE value and starts the configuration process, as
described in the Data Sheet. After the device is configured,
the 5-V Vee may dip to about 3.5 V without any Significant
consequences beyond an increase in delays (circuit speed
is proportional to Veel, and a reduction in output drive. If Vcc
drops into the 3-V range, it triggers a sensor that forces the

June 1, ,1996 (Version 1.0)

device back to the pre-initialization mode described above.
All flip-flops are r~set, HDC goes High; INIT, LDC and Dip
or DONE go LOW,and all other outputs' are 3-stated with a
weak resistive pull-up. If Vee dips substantially lower, the
active outputs become weaker; but the device stays in this
preinitialization mode. When Vee rises again, a normal
configuration process is initiated, as described abOVe.

Sensitivity to Vee Glitches
The user need not be concerned about powersupply dips:
The XC3000/xC4000/XC5200 devices stay configured for
small dips and they are "smart: .enough" to reconfigure
themselves (if a master). or to askforreconfiguration by
pulling INIT and Dip or DONE Low (if a slave). The devices
will not lock up; the USer can.initiate r~-configuration at any
time just by pulling DIP or PROGRAM Low or,ifD/P isLow,
by forcing a High-to-Low transition on RESET.
Any digital lOgic de"icewith internal data storage in latches
or flip-flops is sensitive to power glitChes. This. includes
every RAM, microprocessor, microcontroller, and peripheral circuit. Ohly' purely combinatorial circuits can be guaranteed to survive a severe power glitch without 'any
problem.
Xilinx SRAM-based FPGAs store their C'6nfigur'ation' in
latches. that lose their date! when the supplylfoltags drops
below a critical value (which is'subsfantially below 3 V for
the 5-V devices), but configuration data is extremely robust
and reliable while Vee.stays above .3 V. All Xilinx configuration latches are implemented as cross"ooupled complementary inverters with C1ctive pull-down n-channel
transistors and' active pull-upp:channel ·transist()r~. Both
High and Low logic levels have an impedal1ce of less than
5kf.l with respect to their respective supply rail.
.

"

\

.

TypiCal SRAM memOry devices use paSsive poly-silicon
pull:up re,sistors with an impedance.of abol!!5,QOO'.Mfl fA
curr!!nt of one nanoamp(!) js sufficient to upset the Iypical
SRAM cen, Whereas it takes a mi.liion times more current t.q
upsenhe x.iHnxconfigurati0rilatch,

13-35

I

Configuration Issues: Power-up, Volatility, Security, Battery Back-up

This does not mean that SRAMs are unreliable, it just
shows that the levels in Xilinx configuration latches are six
orders of magnitude more resistant to upsets caused by
external events, like cosmic rays or alpha particles. Xilinx
has never heard about any occurrence of a spontaneous
change in the configuration store in any of its -50 million
FPGA devices sold over the past twelve years.
Whereas most digital circuits rely on Vee staying within
specification, Xilinx FPGAs have an internal voltage monitoring circuit. For example, in the 5-Volt devices, whenever
the supply voltage dips below 3 V, the internal monitoring
circuit causes the Xilinx FPGA to stop normal operation. All
outputs go 3-state, and the device waits for the supply voltage to rise closer to 4 V, when it either demands (slave or
peripheral mode) or initiates (master mode) a reconfiguration.ln the range between 5.5 and 3 V, ali typical CMOS
devices maintain their functionality and their data storage,
they just get slower as the voltage goes down.
Xilinx has made sure that the FPGA cannot be corrupted by
a power glitch. The most sensitive circuit is the low-voltage
detector. It kicks in while all other configuration storage and
user logic is still guaranteed to be functional. The voltagemonitoring feature in the Xilinx device can even be used to
protect other circuitry, or it can be coordinated with external
monitoring circuits.
There is no possibility of a Vee dip causing the device to
malfunction, i.e., to operate with erroneous configuration
information.
o

o

If Vee stays above the trip point, the device functions
normally, albeit at reduced speed, like any other CMOS
device.
If Vee dips below the trip point, the device 3-states all
outputs and waits for reconfiguration.

Xilinx production-tests the Vee-dip tolerance of all XC3000
devices in the following way.
After the device is configured, Vee is reduced to 3.5 V, and
theil, raised back to. 5.0 V. Configuration data is then read
back and compared agains;t the original Gonfiguration bit
stream. Any discrepancy results in rejection of the device.
Subsequently, Vee is reduced to 1.5 V and then raised to
5.0 V. The device must first go 3-state, then respond with a
request for reconfiguration.
Both these tests are performed at high temperature (>85°C
for commercial parts, > 100°C for military). Any part failing
any of these tests is rejected as a functional failure.

operation. A Xilinx FPGA detects the power glitch and
always plays it safe by flagging the problem.
No complex system of any kind can function reliably when
Vee is unreliable. Xilinx FPGAs do the safest thing possible,
whenever such problems occur.

Design Security
SomeXilinx customers are concerned about the security of
their designs. How can they protect their designs against
unauthorized copying or reverse-engineering?
We must distinguish between two very different situations:
o

o

Configuration data in accessible from a serial or parallel
EPROM or in a microprocessor's memory. This is the
normal case.
Configuration data is hidden from the user, since the
design does not permanently store a source of
configuration data. After the FPGA was configured, the
EPROM or other source was removed from the system,
and configuration is kept alive in the FPGA through
battery-back-up.

Design Security when Configuration Data is
Accessible
In the first case, it is obviously very easy to make an identical replica of the design by copying the configuration data
and the pc~board interconnect pattern of the standard
devices, but it is virtually impossible to interpret the bitstream in order to understand the design or make intelligent
modifications to it. Xilinx keeps the interpretation of the bitstream a closely guarded secret. Reverse-engineering an
FPGA would require an enormously tedious analysis of
each individual configuration bit, which would still only generate an XACT view of the FPGA, not a usable schematic.
The best protection against a mindless copy is legal. The
bitstream is easily protected by c;:opyright laws that have
proven to be more successfully enforced than the intellectual property rights of circuit designs.
The combination of copyright protection, and the almost
insurmountable difficulty of creating any design variation for
the intended function, provides good design security. The
recent successes of small companies in reverse-engineering microprocessors and microprocessor support circuits
show that a non-programmable device can actually be
more vulnerable than an FPGA. For advice on legal protection of the configuration bitstream, see the following paragraphs.

As a result of these careful precautions, we contend that
Xilinx FPGAs are safer than ali other types of circuitry
(except purely combinatori,al' circuits). A microprocessor
can loose the content of its address register, its accumulator or other control register due to an undetected power
glitch, with disastrous consequences to the subsequent

13-36

June 1, 1996 (Version 1.0)

~XIUNX
Legal Protection of Configuration Bit-Stream Programs
The bit-stream program loaded into the FPGA may
qualify as a "computer program" as defined in Section
101, Title 17 of the United States Code, and as such
may be protectable under the copyright law. It may also
be protectable as a trade secret if it is identified as
such. We suggest that a user wishing to claim copyright and/or trade secret protection in the bit stream
program consider taking the following steps.
Place an appropriate copyright notice on the .FPGA
device or adjacent to it on the PC board to give notice
to third parties of the copyright. For example, because
of space limitations, this notice on the FPGA device
could read "©1996 XYZ Company" or, if on the PC
board, could read "Bit Stream ©)1996 XYZ Company".
File an application to register the copyright claim for the
bit-stream program with the U.S. Copyright Office.
If· practicable, given the size of the PC board, notice
should also be given that the user is claiming that the
bit- stream program is the user's trade secret. A statement could be added to the PC board such as: "Bitstream proprietary' to XYZ Company. Copying or. other
use of the bitstream program except as expressly au- ..
thorized by XYZ Company is prohibited."
To the extent that documentation, data books. or other
literature accompanies the FPGA-based design, appropriate wording should be added to this literature providing third parties with notice of the user's claim of
copyright and trade secret in the bit-stream program.
For example, this notice could read: "Bit-Stream©)1996
XYZ Company. All rights reserved. The bit-stream program is proprietary to XYZ Company and copying or
other use of the bit- stream program except as expressly authorized by XYZ Company is expressly prohibited."
To help prove unauthorized copying by a third party, additional nonfunctional code should be included at the
end of the bit-stream program. Therefore, should a third
party copy the bit-stream program without proper authorization, if the non-functional code is present in the
copy, the copier cannot claim that the bit-stream program was independently developed.
These are only suggestions, and Xilinx makes no representations or warranties with respect to the legal
effect or consequences of the above suggestions.
Each user is advised to consult legal counsel with
respect to seeking protecti6n of a bit-stream program
and to determine the applicability of these suggestions
to the specific circumstances.
If the user has any questions, contact the Xilinx legal
department at 408-879-4984.

June 1, 1996 (Version 1.0)

Design Security by Hiding the
Configuration Data
If the design does. not contain the source of configuration
data, but relies on battery-back-up of the FPGA configuration, then there is no conceivable way of copying this
design. Opening up the package and probing thousands of
latches in undocumented positions to read out their data
without ever disturbing the configuration is impossible.
This mode of operation offers the ultimate design security. It
is being used by several Xilinx customers who have reason
to be concerned about illegal pirating of their designs,

Battery Back-up and Powerdown
Since SRAM-based FPGAs are manufactured using a
high-performance low-power CMOS process, they can preserve the configuration data stored in the internal static
memory cells even during a loss of primary power. This is
accomplished by forcing the device into a low.power nonoperational state, while supplying the minimal Current
requirement of Vee from a battery.
Circuit techniques used in XC3100, XC4000 and XC5200
devices prevent Icc from being reduced to the level needed
for battery back~up. Consequently, battery back-up should
only be used for XC2000, XC2000L, XC3000, XC3000A
and XC3000L devices.
There are two primary considerations for battery backup
which must be accomplished by external circuits.
•
•

Control of the Power-Down (PWRDWN) pin
Switching between the primary Vee supply and the
batte.ry.

Important considerations include the following:
•

•

•

Insure that PWRDWN is asserted logic Low prior to Vee
falling, is held Low while the primary Vee is absent, and
returned High after Vee has returned to a normal level.
PWRDWN edges must not rise or. fall slowly.
Insure "glitch-free" switching of the power connections
to the FPGA device from the primary Vee to the battery
and back.
Insure that, during normal operation, the FPGA Vee is
maintained at an acceptable level, 5.0 V ± 5% (±1 0% for
Industrial and. Military).

Figure 1 shows a power-down circuit developed by Shel
Epstein of Epstein Associates, Wilmette, IL. Two Schottky
diodes power the FPGA from either the 5.2 V primary supply or a 3 V Lithium battery. A Seiko S8054 3-terminal
power monitor circuit monitors Vee and pulls PWRDWN
Low whenever Vee falls below 4 V.

13-37

I

Configuration Issues: Power-up, Volatility, Security, Battery Back-up

Things to Remember:

Vee
IN5817

Seiko S8054 Specificalions
Delec1 Vollage 3.995 V min
4.305 V max
Hysleresis
208 mV 1yp
Temp. Coeff. 0.52·mV/oC
Icc @ + 6V
2.6 I'A lyp

IN5817

835
Lilhium
Battery

X5997

Figure 1: Battery Back-up Circuit

Powerdown Operation
A Low level on the PWRDWN input, while Vee remains
higher than 2.3 V, stops all internal activity, thus reducing
lee to a very low level:
• All internal pull-ups (on Long lines as well as on the 110
pads) are turned off.
• The crystal oscillator is turned off
• All package outputs are three-stated.
• All package inputs ignore the actual input level, and
present a High to the internal logic.
• All internal flip-flops or latches are permanently reset.
• The internal configuration is retained.
• When PWRDWN is returned High, after Vee is at its
nominal value, the device returns to operation with the
same sequence of buffer enable and Dip as at the
completion of configuration.

13-38

Powerdown·· retains the configuration, but loses all .data
stored in the device. Powerdown .three-states all outputs
and ignores all inputs. No clock signal will be recognized,
and the crystal oscillator is stopped. All internal flip- flops
and latches are permanently reset and all inputs are interpreted as High, but the internal combinatorial lOgic. is fully
functional.

Things to Watch Ouf for:
Make sure that the combination of all inputs High and ali
'internal flip-flop outputs Low in your design will not generate internal oscillations or create permanent bus contention
by activating internal bus drivers With conflicting data onto
the same long line. These two situations are farfetched, but
they are possible and will result in considerable power con.sumption. It is quite easy to simulate these conditions since
all inputs are stable and the internal logic is entirely combinatorial, unless latches have been made out of function
generators.
During powerdown, the Vee monitoring circuit is disabl.ed.lt
is then up to the user to prevent Vee dips below 2.3 V, which
would corrupt the stored configuration:
During configuration, the PWRDWN pin must be High,
Since configuration uses the internal oscillator. Whenever
Vee goes below 4 V, PWRDWN must already be Low in
order to prevent automatic reconfiguration at low Vce. For
the same reason, Vee must first be restored to 4 V or more,
before PWRDWN can be made High.
PWRDWN has no pull-up resistor. A pull-up resistor would
draw supply current when the pin is Low, which would
defeat the idea of powerdown, where lee is only microamperes.

June 1, 1996 (Version 1.0)

Dynamic Reconfiguration
June 1, 1996 (Version 1.0)

Application Note By PETER ALFKE.

All Xilinx SRAM-based FPGAs can be in-systemconfigured and re-configured an unlimited number of times. The
XC6200 family has additional features that allow partial and
very fast (re-)configuration from a microprocessor bus. See
the XC62000 product documentation for details.

•

This application note describes the procedures for reconfiguring the more traditicmal Xilinx FPGAs of the XC2000,
XC3000, XC31 00, XC4000, and XC5200 families.
All configuration information is stored in. latches that are
loaded'serially,conceptually like a shift register. There are
several different bit-serial or byte-parallel configuration data
interfaces, selected by logic levels on three mode inputs,
but - with the exception of the XC5200 Express mode they all result in the bit-serial loading of the configuration
latches. The byte-parallel interfaces in Master 'Parallel and
Peripheral modes act j\Jst as an 8-bit parallel-to-serial converter. Between devices in a daisy-chain, theconfiguratioh
information is transmitted bit~seriallywith a common Con-'
figuration Clock (CCLK). In Master and Peripheral modes,
CCLK is generated by the lead FPGA device,in Slave
Serial mode,' CCLK comes from an external source.
Reconfiguration of an operational deVice, or a daisy~chain
of devices, goes through the following sequence of events:
•
•
•

•

•
•

Reconfiguration is initiated by pulling a specific device
pin Low.
First,all outputs are 3-stated, except HOC = High, [DC
and DONE = Low
Then, all internal registers, flip-flops and,latches, as
well as the configuration storage latches are cleared.
During this time, the INIT output is being pulled Low.
Then, the Mode inputs and RESET or PROGRAM
inputs are sampled to determine the selected
configuration mode and whether to start the new
configuration process, or to wait
Then configuration data is accepted and loaded into the
internal latches and distributed through the daisy-chain.
When all configuration information has been entered,
the user outputs are activated, DONE goes High and
the internal reset is released, all in the order specified in
the configuration bitstream. All devices in a daisy-chain
perform each of these operations in synchronism.

June 1,1996 (Version 1.0)

Important Considerations
Reconfiguration is "all or noihing".There is no way to
restrict reconfiguration to a part of the chip (Note that
XC6200devices do not have this limitaticm).
• Reconfiguration takes a specific time, determined only
by device type, size and clock speed, independent of
the particular configuration pattern. Configuration takes
from tens to hundreds of milliseconds. Durlngtliat time,
all user-outputs of the device, or the wholedaisy.chain
of devices, are 3-stated with weilk internal pull-ups,
except for HOC and LDC, which are active High or Low
respectively.
.' All user-data stored in registers, flip~flops or latches is
erased. There is no way.to retain data inside the device
from on'e configuration to thenext.
"

,

These limitations, are absolute. If they are not acceptable,
the user must resort to creative solutions, like piggy-backing multiple devic~s.
The designer of reconfigurable applications should be
familiar with the' normal configuratiohprocess of each
device, as described in the individual product descriptions.
There is also pertinent inforinaijonabout daisy-Chain operation, especially about mixed daisy chains, on previous
pages.
Interconnecting the INIT pinsofall devices in a Claisy-chain
is mandatory for reconfiguration, since this is the only way
to guarantee that the master device does wait for the rest of
the daisy-chain to be cl~red, pefore starting the, reconfiguration. Only t,he first configuration after power-up' makes the
. master device spend foLir times as many clock periods as
any slave during the initial clear operation, so that the master cannot possibly get ahead oftl1e slaves. Reconfiguration, however, does not slow down the master this way, so
the interconnection of all INIT pins must serve that same
purpose.
Note that the XC2000-fCimily devices do not have an INIT
pin.
In Master Serial mode, .it is highly recommended that the
active Low level of INIT be used to reset the XC1700-family
Serial PROM.

13-39

I

Dynamic Reconfiguratlon

Reconfiguration Time

Initiating Reconfiguration .in
Different Xilinx Device Families

Reconfiguration time is usually more critical than the original power-on configuration time, which is often masked by
the general power-on delays.

XC2000 and XC3000 Series

Here are some suggestions to reduce reconfiguration time.

There are three alternatives:

•

1. Pull RESET Low while DONE is permanently grounded
externally.

A daisy-chain is obviously not,conducive to fast
configuration, it should be broken up into shorter blocks,
perhaps single devices. Multiple devices can be
configured in parallel, but can still use a common
CCLK, and can also be made to start up together. If the
devices differin size or family, they should all be given
the same length count as the largest device in the
group.
• Configuration Mode
Parallel and Peripheral modes are not any faster than
Master Serial mode, since all modes (with the exception
of XC4000EX and XCS200 Express mode) internally
operate on serial data. The internally generated CCLK
frequency is guard-banded te> never approach the upper
limit of what the device can tolerate. Therefore, the fastest possible configuration mode for XC3000 and
XC4000-series devices is Slave Serial, with an external
well-controlled source forCCLK. Its frequency can be
up to 10 MHz for aIlS-V devices, and there are ways to
increase the average clock rate well beyond that, but
. they require dynamic clock frequency changes and an
intimate understanding of the configuration frame structure.
At 10 MHz, configuratiol) time per device ranges from
1.S ms for the XC3020A to 42 ms for the XC402SE and
143 ms for the XC4062EX.
• Possible Contention Problems:
Certain user outputs become active during the configuration process:
Address outputs during Master Parallel mode, Chip
Select and Ready/Busy during peripheral modes.
The designer must make sure that these active outputs
do not cause contention with other logic that might use
the same pins as device ihputs.

13-40

this is the simplest scheme, but it precludes the use of
RESET to clear the flip-flops and latches. in the operating
user-design. RESET must be pulled Low for more than six
microseconds to overcome its internal low-pass filtering.
Configuration starts when RESET has gone High again.
2. Pull DONE Low with an open"drain ("open-collector")
output. This assumes that DONE was High, i.e. that the
previous configuration was successful. Reconfiguration
starts as soon as the internal memory has been cleared.
DONE can be released anytime.
3. Pull DONE Low with an open-drain ("open-collector")
output and pull. RESET Low. Keep RESET Low for at least
, six microseconds. while DONE is Low. DONE can be
released anytime after that, or not released at all. See alternative 1.

XC4000 Series and XC5200 Family
Pull the PROGRAM input Low for at least 0.3 microseconds
to initiate clearing the configuration memory, then pull
PROGRAM up to start the new configuration process.
While PROGRAM is held Low, a Low level on INIT indicates
that the device is continuously clearing the configuration
memory. When PROGRAM has been pulled up, TNfT stays
Low during one more clear operation, then goes High.
All device families, except the original XC4000, have a continuouslyactive pull-up resistor on the PROGRAM pin.

June 1, 1996 (Version 1.0)

Metastable Recovery
August 10, 1996 (Version 2.1)

Application Note By PETER ALFKE and BRIAN PHILOFSKY

Whenever a clocked flip-flop synchronizes an asynchronousinput, there is a small probability that the flip-flop output will exhibit an unpredictable delay. This happens when
the input transition,not only violates the setup and hold-time
specifications, but actually occurs within the tiny timing window where the flip-flop accepts the new input. Under these
circumstances, the flip-flop can enter a symmetrically balanced transitory state, called metastable (meta between).

With the help of a self-contained circuit, Xilinx evaluated the
XC4000 ,and XC3000-series flip-flops. The result of this
evaluation shows the Xilinx flip-flop to be superior in metastable performance to many popular MSI and PLD devices.

=

While the slightest deviation from perfect balance will
cause the output to revert to one of its two stable states, the
delay in doing so depends not only on the gain-bandwidth
product of the circuit; but also on how perfect the balance
iS,and on the noise level within the circuit; the delay can,
therefore,only be described in statistical terms.
The problem for the system designer is not the illegal logic
level in the balanced state (it's easy enough to translate
that to either a 0 or a 1); but the unpredictable timing of the
final change to a valid logic state. If the metastable flip-flop
drives two destinations with differing path delays, one destination might clock in the final data state while the other
does not.

Since metastability can only be measured statistically, this
data was obtained by configuring several different Xilinx
FPGAs with a detector circuit shown in Figure 1. The flipflop under test receives the asynchronous -1-MHz signal
on its D input, and is clocked by a much higher manually
adjustable frequency. The output QA feeds two flip-flops in
parallel, one (OB) being clocked by the same clock edge,
the other (QC) being clocked by the opposite clock edge.
When clocked at a low frequency, each input change gets
captured,by the rising clock edge and appears first on QA,
then, after the falling clock edge, on QC, and finaliy, after
the subsequent rising clock edge, on QB.
If a metastable event in the fitst flip-flop increases the settling time on QA so much thatQC misses the change, but
QB still captures it on the next rising clock edge,thfs error
can be detecteq by feeding the XOR otQB and QC into a
falling-edge triggered flip-flop. Its output (QD) is normally

Mynch,; Input

Clock~_~-+--~---URE, "
READBACK, "

X6076

Figure 4: Start-up Sequence

13-54

June 1, 1996 (Version 2.0)

~XIUNX
BSCAN

>-------lTOI

TOO j-------1TDO

;>-------lTMS

DRCK

:>-----lTCK

IDLE

TOOl

SELl

TD02

SEL2

From~

User
Logic

TDO
OBUFT

)(2676

Figure 6: Typical Non-Boundary-Scan TOO
Connection

4k BSCAN Syntax for BSCAN after configure symbol
BSCAN
~-,....----.TOI
,~-,....----.TMS
,~-,....----.TCK

TDOr----..r--.
DRCK
IDLE

TOOl

SELl

T002

SEL2

5k BSCAN Syntax for BSCAN after configure symbol

X59El6

Figure 5: Boundary-Scan Schematic

From
Previous
. Cell

---:l--+--+--~-,---;"'i

DRCK

To
Next
Cell

Update- DR

T ------+--+--+---------~---+--~~~

. System

L0 9ic

I

o

X2677

Figure 7: EXTEST.Oata Flow

June 1, 1996 (Version 2.0)

13-55

Boundary Scan in XC4000 and XC5000 Series Devices

The IEEE definition of EXTEST only requires that test data
be driven onto outputs, that 3·state output controls be overridden, and that input data be captured. The capture of output data and 3-state controls and the forcing of test data
into the system logic is normally performed during INTEST.

update-IR state, the FPGA is now in the JTAG configuration mode and will start clearing the configuration
memory.
At this point, the user should be in the update-IR state
in the TAP.

The XC4000 effectively performs EXTEST and INTEST
simultaneously. This added functionality permits the testing
of internal logic, and compensates for the absence of a
separate INTEST instruction. However, when performing
an EXTEST, care must be taken over what signals are
driven into the system logic; data captured from internal
system logic must be masked out of the test-data stream
before performing check-sum analysis.

4. Once the Xilinx Configure instruction has been made
current, the user must go from the update-IR state to the
shift-DR state before the FPGA has finished clearing it's
configuration memory.

SAMPLEIPRELOAD - The SAMPLE/PRELOAD instruction permits visibility into system operation by capturing the
state of the 1/0. It also permits valid data to be loaded into
the update register before commencing an EXTEST.

If the user doesn't get to the shift-dr state before INIT
goes high, then the bitstream will not be shifted into the
FPGA in the right sequence and the device will not configure as expected.

The DR and update latch operate exactly as in EXTEST
(see above). However, data flows through the I/O unmodified.

5. Once INIT has gone high, the TAP should already be in
the shift-DR state.

BYPASS - The BYPASS instruction permits data to be
passed synchronously to the next device in the boundaryscan path. There is a 1-bit shift register between the TDI
and TOO flip-flop.
USER1, USER2 - These instructions permit test logic,
designed by the user and implemented in CLBs, to be
accessed through the TAP. Test clocks and paths to TOO
are provided, together with two signals that inc;:licate that
user instructions have been loaded. For details, see the
User Registers section above.
User tests depend upon CLBs and interconnect that must
be configured to operate. Consequently, they may only be
performed after configuration.
CONFIGURE - Steps to Follow to configure a Xilinx
XC4000, XC4000E, or XC5200 via JTAG:

1. Turn 'on' the boundary scan circuitry.
This can be done one of two ways, either via powerup
or via a configured device with boundary scan enabled.
If you want to do this via powerup, then just hold the
INiT pin low when power is turned on. When Vee has
reached Vec(min), then the TAP can be toggled to enter
JTAG instructions. If you want to do this from a configured device, then just start toggling the JTAG port pins
to go from test-logic-reset to run-test-idle.
2. Load the Xilinx Configure instruction into the IR.
The Xilinx Configure instruction is 101 (12 11 lo). 10 is the
bit shifted in first into the IR.
3. After shifting in the Xilinx Configure instruction, make
the Configure instruction the current JTAG instruction by
going to the update-IR state. When TCK goes low in the

13-56

The approximate time it takes to clear an FPGA's configuration memory is: 2 " 1 us" (# of frames per device
bitstream).

In the shift-DR state, start shifting in the bitstream. Continue shifting in the bitstream until DONE has gone high
and the startup sequence has finished.
During the time you are shifting in the bitstream via the
TAP, the configuration pins LDC. HOC, INIT, PROGRAM, etc. all function as they normally do during nonJTAG configuration.
Some Additional Notes:

(8) If you want to power-up the FPGA in JTAG mode,
this can be done by placing a pulldown of approximately
4.7 Kohms on the INIT pin. This pulldown has the merit
of holding TNTf low to allow the user to get into JTAG,
"and" allow the user during JTAG configuration to 'see'
the INIT pin; With the pulldown attached to INIT, the
user will see a drop of approximately 0.5V if INIT drops
low.
The alternative to using a pulldown on the INIT pin on
powerup is for the 'user' to hold INIT low during powerup, and once the TAP is in run-test-idle, release the INIT
pin and pull it.up to Vee.
(b) It is possible to configure several 4K, 4KE, andlor 5K
devices in a JTAG chain. But unlike non-JTAG daisychain configuration, this doesn't mean. merging all the
bitstreams into one bitstr.aam. In the case of JTAG configuration of Xilinx devices in a JTAG chain, all devices,
except the one being configured, will be placed in
BYPASS mode. The one device in CONFIGURE will
have its bitstream downloaded to it. After configuring
this device it will .be placed in BYPASS, and another
device will be taken out of BYPASS into CONFIGURE.
(c) In general for the XC4000, XC4000E, and XC5200,
if you are configuring these devices via JTAG; finish
configuring the device first before executing any other

June 1, 1996 (Version 2,0)

E:XILINX
JTAG instr.uctions. If the bitstream has not finished loading, then if you decide to execute some other JTAG
instructions, then the configuration process via JTAG
must be re-started from test-Iogic,reset.
(d) If boundary scan is not available after the FPGA is
configured, then make sure that the release of II0s is
the last event in the startup sequence.
If boundary scan is not available, the FPGA is configured, and the I/Os are released before the startup
sequence is finished, the FPGA will not respond to
input signals and outputs won't respond at all.
READBACK - Readback through the TAP allows the user
to access the readback features of the device, which would
normally need to be accessed through user-specified pins.
All limits of 'normal' readback are the same with read back
through the TAP. Like regular readback, readback through
the TAP is at a minimum of 10KHz and at a maximum of 1
MHz. Like regular readback, the read back bistream
through boundary scan has the same format.
Unlike regular readback, which can be done over and over
again, readback through the TAP requires the following circuit:
1. In your schematic, or top-level synthesis design, instantiate the BSCAN and READBACK symbols.
2. Connect the BSCAN symbol pins TDI, TMS, TCK, and
TDO to the boundary scan pads TDI, TMS, TCK, and
TDO, respectively.
3. Next, connect the net between the TCK pad and TCK
pin on the BSCAN symbol to an IBUF. Take the output of
the IBUF and connect it to the ClK pin of the READBACK symbol. See Figure 8.
4. After entering the above circuit, compile the design to an
.Ica file.
.
5. Make the .bit file for the .Iea file by using the following
option with makebits:

7. After performing the first readback, .another read back
can be performed by going to the test-logic-reset state,
and re-Ioading the READ BACK instruction and performing theREADBACK as described in the previous paragraph.
In summary, consecutive readbacks are performed by
starting from test-logic-reset, loading the IR with the
RI;ADBACK instruction, shifting out the read back bitstream· plus three additional TCK's, and then going back
to the test-logic-reset state.
Alternatively, if you do not want to go back to the testlogic-reset state, realize that after shifting out read back
bitstream, a minimum of 3 additional clocks are needed
on the readback register. So, after dOing a readback,
instead of going back to test-logic-reset, a user can opt
to execute some other JTAG instruction, and then perform another read back.
Also, this above procedure is only needed if you intend
to do more than 1 readback, If you intend only to do a
readback once, then connection between the BSCAN
symbol and the READBACK symbol is not needed. In
that case, all that is needed is the BSCAN symbol
instantiated with the boundary scan pads (TDI, TMS,
TCK, & TDO) on the top-level of the design.
BSCAN

>----hT~OI~~~T:;;OO~--___ITDO
>------lTMS

ORCK

>-_----lTCK
TOOl
TDD2

• 4k BSCAN Symbolsewp for multiple REAOBACKS lhrough TAP
• For1he 5k, add IBUFsl0 TOI, TMS, and TCK. For TOO, add an OBUF.
(see figure 5)

X""'8

Figure 8: Symbol Setup for Multiple Readbacks

-f readclk:rdbk
For example, at a unix prompt:
% makebits -f readclk:rdbk designame

6. Now the FPGA is ready to perform consecutive readbacks.
READ BACK is performed by .loading the IR with the
READBACK instruction and then shifting out the cap.
tured data from the shift-dr state in the TAP.

Boundary Scan Description
Language Files

I

Boundary Scan Description language (BSDl) files
describe boundary-scan-capable parts in a standard format used by automated test-generation software. The order
and function of bits in the boundary-sean data register are
included in this description.
BSDLfiles are available via the Xilinx BBS (408-559-9327)

Perform the first readback by loading the IR with the
READBACK instruction. This first readback must be finished, which means shifting out the 'entire' readback
bitstream. To be safe, shift out the entire bitstream and
then send three additional TCK'.s.

June 1, 1996 (Version 2;0)

Bibliography
The following publications contains information about the
IEEE Standard 1149.1, and should be consulted for gen-

13-57

Boundary Scan in XC4000 and XCSOOO Series Devices

eral boundary-scan information beyond the scope of this
application note.

GenRad Inc. Meeting the Challenge of Boundary Scan.
GenRad Inc., 300 Baker Ave., Concord, MA 01742-2174.

Colin M. Maunder & Rodham E. Tulloss. The Test Access
Port and Boundary Scan Architecture. IEEE Computer
Society Press, 10662 Los Vaqueros Circle, P.O. BOX 3014,
Los Alamitos, CA 90720-1264.

Ken Parker. The Boundary. Scan Handbook. Kluwer Academic Publications, (617) 871-6600.

John Fluke Mfg. Co. Inc. The ABC of Boundary Scan Test.
John' Fluke Mfg. Co. Inc., P.O. BOX 9090, Everett, WA
98206.

13-58

June 1, 1996 (Version 2.0)

---"""~--------------~-----

Index

1

Introduction

2

Development System Products

3

CPLD Products

4

SRAM-Based FPGA Products

5

SPROM Products

6

3V Products

7

HardWire Products

8

Military Products

9

Programming Support

10 Packages and Thermal Characteristics
11 Testing, Quality, and Reliability
12 Technical Support
13 Product Technical Information
14 Index

15 Sales Offices, Sales Representatives, and Distributors

Index

Numerics
3-state buffer
XC3000 Series 4-293,4-302,13-17
XC4000 Series 4-29
XC5200 4-191
3-state net, global. See Global 3-State
5-input function
XC3000 Series 13-13
XC5200 4-188
70% rule 13-16
7400 equivalents
XC4000 Series 4-10

A
ABEL 2-6,2-7
See also XABEL-CPLD
See also Xilinx ABEL
absolute maximum ratings
overshoot and undershoot 13-47
specifications
XC1700D 5-6
XC3000A 4-343
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-81
XQ5200 4-207
XC5200L 4-250
XC6200 4-275
ACLK symbol 13-18
adaptor selector for programmer 9-2
address pins
pin descriptions
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
XC6200 4-273
advance specifications, definition ()f 1-1,4-80,40206
algorithms, programmer 9-1
Alliance Program 2-7
Alliance Series 2-6,2-7,2-9 .
Base System
OrCAD (PC) 2-14
Viewlogic (PC) 2-16
Viewlogic Stand-Alone. (PC) 2-18
Extended System

Viewlogic Stand-Alone (F,lG) 2-20 •
Standard System
•
Cadence (Workstation) 2024
Mentor V8 (Workstation) 2-22·
OrCAD (PC) 2-15
Synopsys (Workstation) 2-23 ..
third party 2-25
.
Viewlogic (PC) 2-17
Viewlogic (Workstation) 2-21
Viewlogic Stand-Alone (PC) 2-19
ALU, XC7300 3-74
.
AppUNX CD-ROM 12-1,12-5
array data multiplexer, XC6200. 4-264
asynchronous peripheral configuration mod~
debugging hints 13-31 "
specifications
XC3000 Series A-315
XC4000 Series 4-75
XC6200 4-278
XC3000 Series 4-314
XC4000 Series 4-49,4-74
XC6200 4-268
asynchronous RAM 4-19
attribute
DECODE 4-31
INIT 4-19
LOC 4-41, 4-43, 4-45
MEDDELAY 4~26, 4-27 ...
NODELAY 4-26,4-27 .
available products
HardWire 7-3
high-reliability 8-1
software 2-1
XC1700D 5-10
XC3000 Series. 4-339
XC3000A 4~348
XC3000L 4-356
XC3100A 4-364
XC3100L 4-372
XC4000 Series 4-174
XC5200 4-248
XC6200 4-286
XC7300 3-71
XC9500 3-4

I

B
bar code 10-22

14-1

Index

Base System
Alliance Series
OrCAD (PC) 2-14
Viewlogic (PC) 2-16
Viewlogic Stand-Alone (PC) 2-18
Foundation Series (PC) 2-10
with VHDL2c11
basic moisture life test 11-2
battery backup in XC3000 Series 13-21, 13-37
BBS bulletin board 1-5, 12-3
command summary' '12-3
BClKIN 13-18
pin description
XC3000 Series 4-324
BG packages
package drawings 10-45
thermal resistance 10-12
BG225 package
package drawing 10-45
pinout table
XC4000 Series 4-152
BG352 package
package drawing 10-46
pinout table
XC4000 Series 4-163
BG432 package
package drawing 10-47
pinout table
XC4000 Series 4-170
BGA packages
package drawings 10-45
thermal resistance 10-12
bidirectional (bidi) buffer
XC3000 Series 4-296
bitstream
combinihg with MakePROM 4-55, 4-305
copyrighting 13-37
format for configuration
XC4000 Series 4-56
XC5200 4-200
boundary scan
access to 13-54
avoiding inadvertent activation 4'53
bypass register 13-53
configuration with 4-64
daisy chain configuration 13-56
data register 13-51
effect on GTS 4-28
implementing in schematic 4-53
XC4000 Series 4-53
library symbol 4-48, 4-53
pin descriptions
XC4000 Series 4-48
XC5200 4-197
specifications
XC4000E 4-96

14-2

TAP controller 13-51
test access port (TAP) 13-51
user registers 13-53
XC4000 Series 4-29, 4-50, 13-49
XC5200 4-191,13-49
XC9500 3-14
Boundary Scan Description language. See BSDl
BSCAN symbol 4-48, 4-53
BSDl files
XC4000 Series 4-53, 13-57
XC5200 13-57
BUFFClK symbol' 4-45, 4-48
buffer, 3-state
XC3000 Series 4-293,4-302,13-17
XC4000 Series 4-29
XC5200 4-191
buffer, bidirectional
XC3000 Series 4-296
buffered switch matrix 4-36
BUFG symbol 4-194
BUFGE symbol 4-45,4-48
BUFGlS symbol 4-43, 4-48
BUFGP symbol 4-41
BUFGS symbol 4-41
BUFT symbol 4-30
bulletin board (BBS) 1-5, 12-3
command summary 12-3
bus contention, internal 13-17
bypass register 13-53

c
cable
XChecker 2-8, 2-34
Cadence 2-2,2-7
software 2-24
carry logic
XC4000 Series 4-21
XC5200 4-189
carry lookahead
XC7300 3-75
cascade logic
XC5200 4-190
CB100 package
package drawing
XC3000 Series 10-61
XC4000 Series 10-62
CB164 package
package drawing
XC3000 Series 10-63
XC4000 Series 10-64
CB196 package
package drawing 10-65
CB228 package
package drawing 10-66 .
CC packages

~XILINX
package drawings 10-67
CC20 package
package drawing 10-67
CCLK
frequency variation
XC3000 Series 13-21
in configuration debug 13-32
low-time restriction in XC3000 Series 13-21
pin description
XC3000 Series 4-323
XC4000 Series 4-47
XC5200 4-197
setting frequency
XC4000 Series 4-56
use as configuration clock 13-25
XC3000 Series 4-307
XC4000 Series 4-54
XC5200 4-199
ceramic packages
brazed CQFP
package drawings 10-61
DIP
package drawings 10-48
PGA
package drawings 10-49
windowed
package drawings 10-51
characterization data
XC7300 3-135
CLB. See configurable logic block.
CLB-to-pa.d diagram
XC5200 4-212
XC5202 4-212
XC5204 4-214
XC5206 4-216
XC5210 4-218
XC5215 4-220
CLCC packages
package drawings 10-67
clock diagram
.
XC4000E 4-42
XC4000EX 4-42
XC6200 4-261
CMOS input
XC3000 Series 4-293
XC4000 Series 4-24
XC5200 4-196
CMOS output
XC3000 Series 4-293,13-16
XC4000 Series 4-27, 13-12
XC5200 4-196
ConfigOK
pin description
XC6200 4-273
configurable logic block (CLB)
block diagram

XC3000 Series 4-294
XC4000 Series 4-12
XC5200 4-188
carry logic
XC4000 Series 4-21
XC5200 4-189
cascade logic
XC5200 4-190
flip-flop
XC3000 Series 4-294,13-15
XC4000 Series 4-12
XC5200 4-188
function generator
XC3000 Series 4-295,13-13
XC4000 Series 4-11
XC5200 4-188
latch
XC4000EX 4-12
XC52004-188
RAM 4-14
routing associated with
XC3000 Series 13-15
XC4000 Series 4-32
specifications
XC3000A 4-344
XC3000L 4-352
XC3100A 4~360
XC3100L 4-368
XC4000E 4-85
XC5200 4-209
XC3000 Series 4-294, 13-13
XC4000 Series 4-11
XC5200 4-184,4-188
differences from XC4000 and XC3000 4-182
XC6200. See function unit
configuration 13-25, 13-39
asynchronous peripheral mode
debugging hints 13-31
XC3000 Series 4-314
XC3000 Series specifications 4-315
XC4000 Series 4-49,4-74
XC4000 Series specifications 4-75
XC6200 4-268
bitstream copyrighting 13c37
bitstream format
XC4000 Series 4-56
XCS200 4-200
boundary scan pins, using 4-64, 13-56
clock. See CCLK
.
configuration sequence
XC4000 Series 4-59
XC5200 4-203
control pins 13-34
daisy chain 13-26
debugging hints 13-31
mixed family 4-55, 13-33

14-3

I

Index

XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
debugging 13-29
error protection 13-26
express mode
daisy chain 4-56, 4-200
XC4000 Series specifications 4-77
XC4000EX 4-47,4-55,4-56,4-62,4-76
XC5200 4-197,4·200
XC5200 specifications 4-201
guidelines 13-25
initiating reconfiguration 13-40
length count 4-56,4-62,4-203,4-305,13-25,13-29
master modes, general 13-28
XC3000 Series 4-304, 4-307
XC4000 Series 4-54, 4-62
XC4000 Series specifications 4-79
XC5200 4-199
XC5200 specifications 4-205
XC6200 4-271
XC6200 specifications 4-276
master parallel mode
debugging hints 13-30
XC3000 Series 4-312
XC3000 Series speCifications 4-.313
XC4000 Series 4-47,4-70
XC4000 Series specifications 4-71
XC5200 4-197
master serial mode
debugging hints 13-30
XC3000 Series 4-310
XC3000 Series specifications 4-311
XC4000 Series 4"66
XC4000 Series speCifications 4-67
memory cell 4-291, 13-35
mode 13-28
selection of 13-28,13-29
modes, table of
XC3000 Series 4-304
XC4000 Series 4-54
XC5200 4-199
peripheral mode
XC3000 Series 4-314
XC3000 Series specifications 4-315·
peripheral modes, general 13-28
debugging hints 13-32
XC3000 Series 4-307
XC4000 Series 4-47,4-54
XC5200 4-197,4-199
pin descriptions
XC3000 4-323
XC4000 Series 4-47
XC5200 4-197
pin functions during
XC3000 Series .4-325

14-4

XC4000 Series 4-78
XC5200 4-204
power-on reset
XC3000 Series 4-304
preamble 13-25
reducing time 13-40
slave serial mode 13-28
debugging hints 13-31
XC3000 Series 4-307, 4-316
XC3000 Series specifications 4-317
XC4000 Series 4-47,4-55,4-68
XC4000 Series specifications 4-69
XC5200 4-199
XC6200 4-271
specifications
XC3000 Series 4-310
XC4000 Series 4-66
start-up sequence 13-26
XC3000 Series 13-22
XC4000 Series 4-60
XC5200 4-203
switching characteristics
XC4000 Series 4-79
XC5200 4-205
,synchronous peripheral mode
XC4000 Series 4-47,4-72
XC4000 Series specifications ·4-73
XC5200 4-197
XC3000 Series 4-304, 13-22
XC4000 Series 4-54
XC5200 4-199
differences from XC4000 and XC3000 4-183
XC6200 4-268
copyrighting bitstream 13-37
CPLD
available 1/0 10-1
core software 2-29
design flow 2-5
EPROM-based 13-5
FLASH-based 13-5
overview 1-2, 1-4, 13-5
product selection guide 1-8, 13-3,13-5, 13-6
programmer 9-1
CQ packages
package drawings 10-61
CQ100 package
pinout table
XC3000 Series 4-331
CQFP packages
package drawings 10-61'
CRC error checking
selecting with MakeBits 4-57
XC4000 Series 4-56, 4-57
crystal oscillator
XC3000 Series 4-303, 4c309, 13·19
CS

!
in configuration debug 13-30
pin description
XC6200 4-273
CSO, CS1
pin descriptions
XC4000 Series 4-49
XC5200 4-198
CSO, CS1, CS2
pin descriptions
XC3000 Series 4-324
customer support. See technical support
cyclic redundancy check (CRC)
XC4000 Series 4-57

o
daisy chain 13-26
creating bitstream 4-55, 4-305
debugging hints 13-31
express mode
XC4000EX 4-56
XC5200 4-200
mixed family 4-55, 13-33
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
data integrity .11-6
data pins
pin descriptions
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
XC6200 4-273 .
data register 13-51
data stream. See bitstream
DC characteristics
specifications
XC3000A 4-342
XC3000L 4-350
XC3100A 4-358
XC3100L 4-366
XC4000E 4-80
XC5200 4-206
XC5200L 4-250
XC6200 4-275
008 package
package drawing 10-48
debugging
configuration 13-29
DECODE attribute 4-31
decode logic. See cascade logic, edge decoder
.
decouplingcapacitor
XC6200 4-274
delay
input delay 13-45
XC3000 Series 13-15

~XIUNX
of configuration after power-up
XC4000 Series 4-60
optional input delay
XC4000 Series 4-26
output
XC4000 Series 13-10
with fast capture latch 4-27
demoboard
FPGA 2-8, 2-34
design flow
CPLD 2-5
DS-502 software package 2-4
DS-560 software package 2-5
FPGA 2-4
software 2-2
Design Manager 2-1
design security
XC7300 3-78
XC9500 3-14
development system 2-1
overview 1-5
DIN
in daisy chain
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
pin description
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
DIP package
ceramic 10-48
plastic 10-27
direct interconnect
XC3000 Series 4-296
XC4000EX 4-37
XC5200 4-184,4-192
XC6200 4-256
disk space requirements
programmer 9-1
See also hardware requirements
DONE
during power-up 13-35
express mode configuration 4-56
going High after configuration
XC3000 Series 4-308
XC4000 Series 4-62
in configuration debug 13-30
not going High after configuration 13-29
pin description
.
XC4000 Series 4~47
XC5200 4-197
DONEIPROG
during power-up 13-35
pin description
XC3000 Series 4-323.

I

14-5

Index

double-length routing
XC4000 Series 4-35
XC5200 4-194
OOUT 13-25
in daisy chain
express mode 4-56
XC3000 Series 4-307
XC4000 Series 4-55
XC5200 4-199
pin description
XC3000 Series 4-324
XC4000 Series 4-49
XC5200 4-198
dry bag 10-19
dry bake 10-19
OS-290 software package 2-30
OS-344 software package 2-30
OS-35 software package 2-30
OS-371 software package 2-31
OS-380 software package 2-30
OS-390 software package 2-30
OS-391 software package 2-30
OS-401 software package 2-33
OS-502 software package 2-28
design flow 2-4
OS-560 software package 2-29
design flow 2-5
OS-571 software package 2-32
dual-port RAM 4-17

E
edge .decoder 4-31
edge-triggered RAM 4-16
advantages of 4-14
EOIF 2-6
EIAJ standards 10-4
electrical parameters
programmer 9-1
XC6200 4-274
electrostatic discharge (ESO) 11-7
E-mail addresses 12-4
endurance, XC9500 3-14
EPROM-based CPLO
overview 13-5
error checking, bitstream 4-57,4-309
XC3000 Series 4-309
XC4000 Series 4~57
express configuration mode
CRC not supported 4-56
specifications
XC4000 Series 4-77
XC5200 4-201
synchronized to DONE
XC4000EX 4-62
XC4000EX 4-47,4-55,4-56,4-62,4-76

14-6

XC5200 4-197, 4-200
Extended System
Alliance Series
Viewlogic Stand-Alone (PC) 2-20

F
factory floor life 10-19
failure analysis 11-3, 11-6
failures in time 11-2
fast capture latch 4-26
fast carry logic. See carry logic
fast function blocks, XC7300 3-72
FastCLK buffer (BUFFCLK) 4-29, 4-45, 4-48
fast pin-to-pin path 4-28
with fast capture latch 4-26
FastCONNECT switch matrix 3-11
FastFlash technology
XC9500 3-16
fastlane routing, XC6200 4-256
FCLK1 - FCLK4
clock diagram 4-42
pin descriptions
XC4000EX 4-48
FOCE symbol 4-13
FIFO
implementing in XC4000 Series RAM 4-14
FITs 11-2
FLASH-based CPLO
overview 13-5
flip-flop
inCLB
XC3000 Series 4-294,13-15
XC4000 Series 4-12,4-13
XC5200 4-188
in lOB
metastability 13-41
none in XC5200 4-196
XC3000 Series 4-293,13-15
XC4000 Series 4-24, 4-27
in XC6200 function unit 4-258
Floorplanner 2-1
Flow Engine 2-1
forced air cooling vendors 10-14
Foundation Series 2-6, 2-9
Base System (PC) 2-10
with VHOl 2-11
Standard System (PC) 2-12
with VHOL 2-13
FPGA
advantages of 13-3
available 1/0 10-1
core software 2-28
data integrity 11-6
demoboard 2-8, 2-34
design flow 2-4

~XILINX
overview 1-2, 1-4
product selection guide 1-6,13-3,1.3-6
security 13-36
function block
XC7300 3-72, 3-74
XC9500 3-5
function generator
in CLB
XC3000 Series 4-295, 13-13
XC4000 Series 4-11
XC5200 4-188
in lOB
XC4000EX 4-28
in XC6200 function unit 4-258
using as RAM 4-14
function unit 4-257
block diagram 4-258
flip-flop 4-258
specifications 4-276

G
G1, G2 4-257
pin description
XC6200 4-273
gate array
advantages of FPGAs 1-3
advantages of HardWire 7-1
GCK1- GCK4
pin descriptions 4-197
GCK1 - GCK8
clock diagram 4-42
pin descriptions
XC4000EX 4-48
GClk 4-257,4-261,4-268,4-272
pin description
XC6200 4-273
GCLK symbol 13-18
GClr 4-257, 4-261
pin description
XC6200 4-273
general routing matrix (GRM)
XC5200 4-184,4-185; 4-192;4-194
glitch
avoidance in XC3000 Series 13"14
power supply 13-35
Global 3-State (GTS)
XC4000 Series 4-28, 4-46
global buffer
specifications
XC3000A 4-343
XC3000L 4-351
XC3100A 4-359
XC3100L 4-367
XC4000E 4-82 '
XC5200 4-207

XC6200 4-276
XC3000 Series 4-302, 13-18
XC4000 Series 4-41
XC4000E 4-41
XC4000EX 4-43
XC5200 4-194
XC6200 4-257,4-261
Global Early buffer (BUFGE) 4-29, 4-44,4-48
fast pin-to-pin path 4-28
with fast capture latch 4-26
Global Low-Skew buffer (BUFGLS) 4-43, 4-48
with fast capture latch 4-26
Global Reset (GR)
inCLB
XC5200 4-191
Global Set/Reset (GSR)
inCLB
XC4000 Series 4-13
in lOB
XC4000 Series 4-29
GR. See Global Reset
GRM. See general routing matrix
ground bounce
XC4000 Series 13-10
GSA. See Global Set/Reset
GTS. See Global 3-state

·H
Hardware Debugger 2-1
hardware requirements
Alliance Series
Base System OrCAD (PC) 2-14
Base System Viewlogic (PC) 2-16
Base System Viewlbgic Stand-Alone (PC) 2-18
Extended System Viewlogic Stand-Alone
(PC) 2-20
Standard System Cadence (Workstation) 2-24
Standard System Mentor V8 (PC) 2.~22 '
Standard System OrCAD (PC) 2-15
Standard System Syhopsys (Workstati
Source Exif Data: 
File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:11:01 16:44:33-08:00
Modify Date                     : 2017:11:01 17:18:22-07:00
Metadata Date                   : 2017:11:01 17:18:22-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:80cb2703-0009-814d-ad1b-c13d8d4455fe
Instance ID                     : uuid:6b396482-ab05-b449-bb4d-cd8fac021fdd
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 834


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