1997_Temic_8 Bit_Microcontroller_Handbook 1997 Temic 8 Bit Microcontroller Handbook
1997_Temic_8-Bit_Microcontroller_Handbook 1997_Temic_8-Bit_Microcontroller_Handbook
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TEMIC
Semiconductors
8-bit Microcontroller
Databook - 1997
MATRAMHS
TEMIC
Semiconductors
AboutTEMIC
TEMIC is the microelectronics enterprise of
Daimler-Benz. Organized into four divisions
Semiconductors,
Microsystems,
Automotive
Electronics, and Airbag Inflators - TEMIC offers
products for
the
computer,
communications,
auto-motive, consumer, industrial as well as aerospace
and defense markets. Sales are handled by the
worldwide TEMIC network and by regional sales
representatives and distributors.
processes, TEMIC Semiconductors provides a unique
set of components and solutions. The company's
facilities include wafer fabrication operations in
Reilbronn and Itzehoe, Germany; Nantes, France; and
Santa Clara, California in the United States. Assembly
and test facilities are located in Vocklabruck, Austria;
Manila, Philippines; Kaohsiung, Taiwan; and Shanghai,
China. The member companies of TEMIC
Semiconductors are Telefunken Semiconductors,
Siliconix, Matra MRS, and Dialog Semiconductor.
With a technology portfolio which includes RF, bipolar,
BiCMOS, GaAs, CMOS, BiC/DMOS, and DMOS
Daimler-Benz
I
I
I
Mercedes-Benz
TEMIC
ABB Daimler-Benz
Transportation
AEG Electrocom
I
I
I
Daimler-Benz
Aerospace
Daimler-Benz
InterServices
I
I
TEMIC
Semiconductors
II
Microsystems
-l
Integ~a!e.d Circuits
-1
Discret~ ~?mponentsl
---4
Worldwide Sales
DIvIsIOn
I
DIVISIOn
I
II
Automotive
Electronics
Airbag Inflator
Systems
"
TEMIC
Semiconductors
TEMIC Semiconductors
Integrated Circuits Division
The IC Division of TEMIC Semiconductors, with its
headquarters in Heilbronn, Germany, is organized into
business centers that synergize the company's technical
and marketing skills to provide the highest level of
service to customers.
Automotive ICs
Based in Heilbronn, Germany, this business center is the
European market leader for stand-alone control ICs
dedicated to the harsh automotive environment.
Offerings include embedded control ICs for airbag and
anti-lock braking system (ABS) electronics, as well as
RF and IR solutions for safety and convenience, such as
keyless entry and immobilizer chip sets.
Communication ICs
Consisting of strong expert teams in the German cities
of Heilbronn and Ulm, this business center is focused on
high-frequency front-end solutions for handy phones
and cordless phones, as well as analog and digital TV
and radio receivers for worldwide markets. Current
products are based on bipolar silicon high-speed
technologies. Future products will also be based on a
silicon germanium technology offering higher RF
performance and lower power consumption, but at a cost
very comparable to silicon.
Microcontrollers and Digital ICs
Located in Nantes, France, this business center's
products are based on the powerful 80C51 and 80C251
cores licensed from Intel and comple-mented by a rich
cell library, from ElE2PROM through a wide range of
digital and mixed-signal functions and interfaces.
Together, these provide a toolbox for the design of
advanced embedded solutions for minimal system cost
and maximum functionality. A line of high-performance
SRAMs, digital ASICs and the Universal Logic Circuit
(ULC) family of FPGA replacements completes this
product offering. Hardened processes and fully certified
quality flows enable to serve aerospace and defense
applications.
PowerICs
Located in Santa Clara, California, in the heart of
Silicon Valley, products from this business center
combine low on-resistance power MOS transistors on a
single chip with high-speed CMOS functions. The result
is a range of product families such as high-frequency
dc-to-dc converter ICs or highly integrated motor
controller solutions which bothshare a unique
combination of high power efficiency, low system cost,
and small size.
Mixed-Signal ASICs
Succsessfully combining analog and digital functions on
the same ASIC (Application-Specific-Integrated
Circuit) is the key to true system integration. TEMIC
Semiconductors' years of experience in mixed-signal
ASIC technology gives our customers the ability to
achieve the integrated solutions their systems need.
Based in Swindon, United Kingdom, this business
center supports all types of mixed-signal solutions in
CMOS for a range of markets and applications, from the
initial idea through to volume production.
TEMIC
Semiconductors
TEMIC Semiconductors Discrete
Components Division
The TEMIC Semiconductors Discrete Components
Division combines TEMIC's expertise in power, IR data
transmission, optoelectronic, analog signal processing,
and bipolar technologies in a way that creates a clear
focus on product lines and an efficient interface with
target markets. With headquarters in Santa Clara,
California, the Discrete Components Division includes
product units focused on power MOSFETs, IrDA
modules, optoelectronics, RFlbipolar transistors and
diodes, and signal processing products.
Power MOS Devices
TEMIC Semiconductors is the silicon technology and
packaging leader for 60-V- and -below power
MOSFETs. Now in their third generation, TEMIC's
TrenchFET'M power MOSFETs continue to break
industry records, with the latest devices offering
maximum on-resistance as low as 6 milliohms.
TrenchFETs™ and advanced planar devices are
available from TEMIC in through-hole and
surface-mount packages, including the popular LITTLE
FOOT® S08, TSSOP8, and TSOP6.
IrDA Modules
For many years the industry leader in IR photo-module
technology, TEMIC Semiconductors has quickly
emerged as a top supplier of integrated transceivers and
discrete components for data transmission solutions
meeting the standards of the Infrared Data Association
(IrDA). TEMIC provides a full range of
IrDA-compatible components, from transceiver
modules with 115.2 kbitls and 4 Mbitls transmiSSIOn
rates to a family of discrete IREDs and photomodules
that were used in the original implementations that
formed the basis for the IrDA standard.
Optoelectronic Components
TEMIC Semiconductors has been a major supplier of
optoelectronic devices for more than 20 years. In 1996,
the company will supply upwards of 80 million IR
photo modules for remote control applications. The
photo pin diodes and GaAIAs infrared emitting diodes
at the heart of these devices are available as discrete
components to provide maximum flexibility for
customer designs. Visible LEDs and displays, along
with a distinguished line of opto sensors, opto couplers,
and opto switches, complete TEMIC's optoelectronic
product
offering.
TEMIC
Semiconductors'
Optoelectronics Product Unit is located in Heilbronn,
Germany.
Signal Processing
Offerings from the Signal Processing Product Unit
include analog switches and multiplexers, JFETs, and
DMOS FETs. A high-voltage silicon-gate process
(versus the standard high-voltage metal-gate process)
allows TEMIC to manufacture analog switches and
multiplexers with lower analog channel leakages, higher
accuracy, and faster operation than any other
industry-standard products. TEMIC Semiconductors'
Signal Processing Product Unit is located in Singapore.
Bipolar Transistors and Diodes
Products in this category, such as our no-roll-away
MicroMELF diodes, provide the quality that customers
expect plus the extra measure of ingenuity that sets
TEMIC apart from its competitors. Our exclusive MOS
Monolithic Circuits eliminate the need, e.g., in radio and
TV tuners, for several external resistors and capacitors.
Families of MOS and bipolar RF transistors, bipolar
high-voltage switches, small-signal and zener diodes, as
well as standard and ultra-fast rectifiers, complete the
offerings of TEMIC Semiconductors' Bipolar
Transistors and Diodes Business Unit located in
Viicklabruck, Austria.
TEMIC
Quality
Semiconductors
TEMIC Quality Policy
Our goal is to achieve total customer satisfaction
through everything we do. Therefore, the quality of our products and
services is our
number one priority.
Quality comes first!
AU of us at TEMIC are part of the process of
continuous improvement.
Total Customer Satisfaction
In this report, our methodology to achieve total customer
satisfaction is shown. Furthermore, quality figures and
future targets are given.
Total customer satisfaction as stated in the 'TEMIC
Quality Policy' means that the customer comes first.
This applies throughout the organization, as we all strive
to understand and meet the changing needs of our
customers.
•
World-class excellence
• Benchmarking
• EFQM approach
• Measurement of customer satisfaction - QFD
•
Corporate customer service policy
• Cost of quality'
• TEMIC worldwide ISO 9000 certification
• FMEA-DOE
• Supplier partnership
• Empowered improvement teams
•
Statistical process control
• External! internal customer partnership
• TQM training and education
TEMIC
Quality
Semiconductors
Quality System
Quality Program
At the heart of the quality process is TEMIC's
worldwide quality program, TEMIC Quality
Movement (TQM). This program, which has been in
place since the early 90's, is specifically designed to
meet rapidly increasing customer quality demands now
and in the future. The quality program is controlled by
the TEMIC Quality Committee (TQC). The committee
implements the Quality Policy and translates its
requirements for use throughout the worldwide
organization.
•
Built-in Quality
Quality is built into all TEMIC products by using
qualified materials, suppliers and processes.
Fundamental to this is the use of SPC techniques by
both TEMIC and its suppliers. The use of these
techniques, as well as tracking critical processes,
reduces variability, optimizing the process with
respect to the specification. The target is defect
prevention and continuous improvement.
•
Qualification
All new products are qualified before release by
submitting them to a series of mechanical, electrical
and environmental tests. The same procedure is used
for new or changed processes or packages.
•
Monitoring
A selection of the same or similar tests used for
qualification is also used to monitor the short- and
long-term reliability of the product.
•
SPC (Statistical Process Control)
SPC is an essential part of all TEMIC process
control. It has been established for many years and
is used as a tool for the continuous improvement of
processes by measuring, controlling and reducing
variability.
•
TEMIC's Quality System
All TEMIC's facilities worldwide are approved to
IS09000. In addition, some TEMIC companies hold
approval to recognized international and industry
standards such as MIL-STD-883, MIL-I-38535,
SCC9000, AQAPl, Ford QIOl, QS 9000.
The TQC has defined a roadmap with specific targets
along the way. The major target is to achieve world-class
excellence throughout TEMIC Semiconductors
worldwide by 1999.
TEMIC Quality Committee
The TEMIC Quality Committee (TQc) defines and
implements the TEMIC quality policy at a corporate
level. It acts to harmonize the quality systems of the
constituent divisions and to implement Total Quality
Management throughout the company worldwide.
Quality Goals and Methods
The goals are straightforward: Customer satisfaction
through continuous improvement towards zero defects
in every area of our operation. We are committed to
meeting our customers' requirements in terms of quality
and service. In order to achieve this, we build excellence
into our product from concept to delivery and beyond.
•
Design-in Quality
Quality must be designed into products. TEMIC uses
optimized design rules based on statistical
information. This is refined using electrical, thermal
and mechanical simulation together with techniques
such as FMEA and DOE.
The procedures used are based upon these standards and
laid down in an approved and controlled Quality
Manual.
TEMIC
Quality
Total Quality Management
Semiconductors
•
Total Quality Management is a management system
combining the resources of all employees, customers
and suppliers in order to achieve total customer
satisfaction, The fundamental elements of this system
are:
Management commitment
EFQM assessment methodology
Empowered Improvement Teams (EITs)
Supplier development and partnership
Quality tools
Training
Quality System
All TEMIC employees from the senior management
downwards are trained in the understanding of TQM,
Every employee plays its own part in the continuous
improvement process which is fundamental to TQM and
our corporate commitment to exceed customers'
expectations in all areas including design, technology,
manufacturing, human resources, marketing, and
finance, Everyone is involved in fulfilling this goaL The
management believes that this can only be achieved by
employee empowerment.
The TEMIC corporate core values; leadership by
example,
employee
empowerment,
continuous
improvement, total customer satisfaction and business
excellence are the very essence of the TEMIC Quality
Movement process.
•
Training
TEMIC maintains that it can only realize its aims if
the employees are well-trained. It therefore invests
heavily in courses to provide all employees with the
knowledge they need to facilitate continuous
improvement. A trammg profile has been
established for all employees with emphasis being
placed on Total Quality Leadership. Our long-term
aim is to continuously improve our training so as to
keep ahead of projected changes in business and
technology.
EFQM Assessment Methodology
From 1995, TEMIC has started to introduce the
EFQM (European Foundation for Quality
Management) methodology for structuring its Total
Quality Management approach. This methodology,
similar to the Malcolm Baldrige process, consists in
self-assessing the various TEMIC divisions and
facilities according to nine business criteria:
•
•
Leadership
People management
Policy and strategy
Resources
Processes
People satisfaction
Customer satisfaction
Impact on society
Business results
The assessments are conducted on a yearly basis by 40
trained and empowered, internal TEMIC assessors. This
permits the identification of key-priority improvement
projects and the measurement of the progress
accomplished.
The EFQM methodology helps TEMIC to achieve
world-class business excellence and will very soon bring
either a Malcolm Baldrige- or an EFQM Award
recognition.
•
Empowered Improvement Teams (EITs)
At TEMIC we believe that every person in the
company has a contribution to make in meeting our
target of customer satisfaction. Management
therefore empowers employees to higher and higher
levels of motivation, thus achieving higher levels of
effectiveness
and
productivity.
Empowered
improvement teams, which are both functional and
cross-functional, combine the varied talents from
across the breadth of the company. By taking part in
training, these teams are continually searching for
ways to improve their jobs, achieving satisfaction for
themselves, the company and - most important of
all - the customer.
TEMIC
Quality
Semiconductors
Leadership
10%
Processes
14%
Results 50%
Enablers 50 %
TQMTools
•
Failure Mode and Effect Analysis (FMEA)
FMEA is a technique for analyzing the possible
methods of failure and their effect upon the
performancelreliability of the product/process.
Process FMEAs are performed for all processes. In
addition, product FMEAs are performed on all
critical or custom products.
•
Design of Experiments (DOE)
There is a series of tools which may be used for the
statistical design of experiments. It consists of a
formalized procedure for optimizing and analyzing
experiments in a controlled manner. Taguchi and
factorial experiment design are included in this.
They provide a major advantage in determining the
most important input parameters, making the
experiment more efficient and promoting common
understanding amongst team members of the
methods and reasoning used .
•
Gauge Repeatability and Reproducibility
(GR&R)
This technique is used to determine an equipment's
suitability for purpose. It is used to make certain that
all equipment is capable of functioning to the
required accuracy and repeatability. All new
equipment is approved before use by this technique.
As part of its search for excellence, TEMIC employs
many different techniques and tools. Some of them are
listed here:
•
Cost of Quality
Cost of Quality is used as a performance indicator. It
is defined as the sum of the costs of:
•
•
•
Internal failure
External failure
Exceeding requirements
Lost opportunities
Prevention
Appraisal
The goals are set as part of the company goals, initially
at director level. All employees and EIT are expected to
be aware of, determine, and track their associated costs.
•
Auditing
As well as third-party auditing employed for
approval by ISO 9000 and customers, TEMIC
carries out its own internal and external auditing.
There is a common auditing procedure for suppliers
and sub-contractors between the TEMIC entities.
This procedure is also used for inter-company
auditing between the facilities within TEMIC. It is
based on the "Continuous Improvement" concept
with heavy emphasis on the use of SPC and other
statistical tools for the control and reduction of
variability. Internal audits are carried out on a routine
basis. They include audits of satellite facilities (i.e.,
sales offices, warehousing etc.). Audits are also used
widely to determine attitudes and expectations both
within and outside the company.
Business
results 15%
TEMIC
Quality
•
Quality Function Deployment (QFD)
QFD is a method for translating customer
requirements into recognizable requirements for
TEMIC's
marketing,
design,
research,
manufacturing and sales (including aftersales), QFD
is a process which brings together the life cycle of a
product from its conception, through design,
manufacture, distribution and use until it has served
its expected life.
Quality Service
TEMIC believes that quality of service is equally as
important as the technical ability of its products to meet
their required performance and reliability. Our
objectives therefore include:
On-time delivery
Short reaction time to customers' requests for
information
Rapid and informed technical support
• Fast handling of complaints
A partnership with our customers
Semiconductors
If there is a technical reason for complaint, a sample is
sent to the Sales Office for forwarding to the Failure
Analysis department of the supplying facility. The
device's receipt will be acknowledged and a report
issued on completion of the analysis. The cycle time for
this analysis has set targets and is constantly monitored
in order to improve the turnaround time. Failure analysis
normally consists of electrical testing, functional
testing, mechanical analysis (including X-ray),
decapsulation, visual analysis and electrical probing.
Other specialized techniques (i.e. LCD, thermal
imaging, SEM, acoustic microscopy) may be used if
necessary.
If the analysis uncovers a quality problem, a CAR
(Corrective Action Report - in -8D format if required)
will be issued. Any subsequent returns are handled with
the RMA procedure.
•
Change Notification
All product and process changes are controlled and
released
via
ECN
(Engineering
Change
Notification). This requires the approval of the
relevant departments. In the case of a major change,
the change is forwarded to customers via Sales/
Marketing before implementation. Where specific
agreements are in place, the change will not be
implemented unless approved by the customer.
•
Ship-to-Stock/Ship-to-Line (STS/STL)
There are very low levels of rejects being delivered
to customers. Many customers now require devices
to be shipped direct to stock or to the production line
by omitting any goods inwards inspection. TEMIC
welcomes such agreements as part of its customer
partnership program which promises an open
approach in every aspect of its business.
A product will only be supplied as STS or STL if
there is a valid agreement in place between the two
companies. Such an agreement details the quality
level targets agreed upon between the companies and
the methods to be used in case of problems.
We have therefore implemented a customer service plan
and charter which details our service targets. This is
detailed in our brochure The Business of Customer
Service. "The customer comes first" is a fundamental
part of this charter.
•
Customer Complaints
Complaints fall mainly into two categories:
Logistical
Technical
TEMIC has a procedure detailing the handling of
complaints. Initially complaints are forwarded to the
appropriate sales office where in-depth information
describing the problem is of considerable help in giving
a fast and accurate response. If it is necessary to send
back the product for logistical reasons, the Sales Office
issues an RMA (Returned Material Authorization)
number. On receipt of the goods in good condition,
credit is automatically issued.
TEMIC
Semiconductors
TEMIC reserves the right to make changes in the products or specifications contained in this document in order to
improve design or performance and to supply the best possible products. TEMIC also assumes no responsibility for
the use of any circuits described herein, conveys no license under any patents or other rights, and makes no
representations that the circuits are free from patent infringement. Applications for any integrated circuits contained
in this publication are for illustration purposes only and TEMIC makes no representation or warranty that such
applications will be suitable for the use specified without further testing or modification. Reproduction of any portion
hereof without the prior written consent of TEMIC is prohibited.
Definition of Terms
The product datasheets contained in this document are referring to the following possible status:
Preview
This datashect contains the targeted specifications, all electrical parameters correspond to either
targeted or simulated values.
Specifications may change in any manner without notice.
Preliminary
This datasheet contains final functional specification. The electrical parameters given are based
either on simulated values or on preliminary product characterization results.
Specifications may change in any manner without notice.
No indication (blank)
This datasheet contains final specifications.
TEMIC reserves the right to make changes at any time, according to TEMIC Quality Assurance
procedures, in order to improve design and supply the best possible product.
On line information
World Wide Web:
http://www.temic.de
E-mail C51 products:
c51@temic.fr
E-mail C251 products:
c251@temic.fr
Publisher
MATRA MHS S.A.
La Chantrerie Route de Gachet,
BP70602
44306 NANTES Cedex 03
France
Fax: +33 24018 1960
Copyright TEMIC Semiconductors 1997.
TEMIC
Semiconductors
TEMIC 8-bit Microcontrollers: A Long Term Commitment
In the world of 8-bit microcontrollers, the 80C51 architecture has become an industry standard in embedded
applications. Introduced in the early's 1980's by TEMIC/Matra MHS under Intel License, the 80C51 is still a market
leader.
For over 15 years, TEMIC has been a leading provider of 80C51 microcontrollers to major embedded markets. Today,
TEMIC is ranked number 3 in worldwide sales of 80C5! devices, representing over 20% market share. This
unsurpassed experience is at the service of TEMIC customers in every application.
TEMIC now enlarges its product range by adding one time programmable (OTP) versions of standard products and
the highly increased number of product derivatives for applications mainly targeted in the Communication, Computer
and Automotive area.
Also the market is in need for a more powerful solution to meet the requirements of increasingly sophisticated
embedded applications. High growth markets, including applications in communication, automotive and personal
computing are driving these requirements. Therefore TEMIC has introduced in 1996 the first two products of the
Intel-licensed TSC8025! 8-bit extended architecture.
Our long-term commitment means you'll enjoy through C5! and C25! support for years to come.
This 8-bit Microcontroller Databook 1997 intends to provide you the latest information on the growing TEMIC offer.
All available technical information of the C5! family is included while the literature for the TSC80251 family is
available separately:
- TSC80251 Programmer's Guide
- TSC80251 Al Datasheet
- TSC80251Gl Design Guide
TEMIC
Semiconductors
8-bit Microcontroller
Section I: C51 Architecture Information
II
Section II: Product Information
E
Section III: C51 Application Notes
I
Section IV: Introduction to C251 Architecture
I
Section V: Packaging
I
Section VI: Quality Flows
I
Section VII: TEMIC Sales Locations
I
TEMIC
Semiconductors
8-bit Microcontroller
Table of Contents
Section I: CSt Architecture Information
CSI Family: Architectural Overview of the CSI Family
1.1.1
CSI Family: Hardware Description of the CSI Family Products .................. 1.2.1
CSI Family: CSI Family Programmer's Guide and Instruction Set ................ 1.3.1
Section II: Product Information
Product Selection .......... ............................................. .. 11.1.0
Product by Application Domain ............................................... II.l.l
ProductslPeripheral Selection Tables ............................................ II.l.2
Military and Space Products .................................................. II.I.S
CSI General Purpose Products .............................................. 11.2.0
TSCSOC311S0CSl : CMOS 0 to 44 MHz Single-Chip S Bit Microcontroller ............ 11.2.1
TSCSOCL3I1TSCSOCLSl : CMOS 1.S Volt Single-Chip S Bit Microcontroller .......... 11.3.1
SOC32/S0CS2 : CMOS 0 to 44 MHz Single Chip S-bit Microntroller .................. I1A.l
SOClS4/S3ClS4: CMOS 0 to 36 MHz Single Chip S-bit Microcontroller .............. II.S.I
S3C lS4D : CMOS 0 to 30 MHz Single Chip S-bit Microcontroller .................... 11.6.1
CSI Computer/Communication Products ..................................... 11.7.0
TSCSOSICI : S-Bit Microcontroller for Digital Computer Monitors ................... 11.7.1
TSCSOSIC2: S-Bit Microcontroller for Digital Computer Monitors ................... 1I.S.1
CSI Automotive Products .................................................. 11.9.0
TSCSOSI AI: CMOS Single Chip S-bit Microcontroller with Analog Interface .......... 11.9.1
TSCSOSI A2 : CMOS Single Chip S-bit Microcontroller with Analog Interfaces ........ 11.10.1
TSCSOSI All : CMOS Single chip S-bit Microcontroller with CAN Controller ......... 11.11.1
TSCSOSI A30 : CMOS Single chip S-bit Microcontroller with VAN Controller ......... I1.12.1
8-bit Microcontroller
TEMIC
Semiconductors
Section III: CSt Application Notes
ANM031 : Secret Tag on 80C51 Family Microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . IlL1.1
ANM032 : How to use a Third Overtone Crystal
with a 80C51 Family Microcontroller .......................................... III.2.1
ANM033 : How to Read Out the Internal Memory Code
of a 80C51 Microcontroller Family ............................................ IlI.3.1
ANM034 : Compatibility between 80Cx2 and 8xC154 Microcontrollers .............. I1I.4.1
ANM053 : Encryption on 80C51 Family Microcontrollers ......................... IlL5.1
ANM055 : How to Get a Second Asynchronous Serial Interface
on a 80C51 Microcontroller Family ........................................... IIL6.1
ANM059 : How to Recognize Video Mode and Generate Free Running
Synchronization Signals Using TSC8051ClIC2 Microcontroller ..................... IlL7.1
Section IV: Introduction to C2St Architecture
C2S1 OverviewlBenefits vs CS1 ............................................. IV.1.0
C251 Architecture Overview: ................................................ IV1.1
TSC80251 : AC/DC Characteristics ........................................... IV2.1
Extended 8-bit TSC802S1 Products Overview ................................. IV.3.0
TSC 80251 AI: Extended 8-bit Microcontroller with Analog Interfaces . . . . . . . . . . . . . .. IV3.1
TSC 80251 G 1 : Extended 8-bit Microcontroller
with Serial Communication Interfaces ......................................... IV.4.1
Section V: Packaging
Section VI: Quality Flows
Section VII: TEMIC Sales Locations
Sales Offices Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 3 to 4
Representatives Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5 to 7
Distributors Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 8 to 22
TEMIC
Semiconductors
II
Section I
cst Architecture Information
CS1 Family: Architectural Overview of the CS1 Family ......................... 1.1.1
CS1 Family: Hardware Description of the CS1 Family Products .................. 1.2.1
CS1 Family: CS1 Family Programmer's Guide and Instruction Set ................ 1.3.1
TEMIC
Semiconductors
cst Family
Architectural Overview of the CS1 Family
a
Summary
1. Introduction ............................................................ 1.1.2
1.1. TSCSOCS1I80CSI/SOC31 .................................................................
1.2. SOCS2/80C32 ..........................................................................
1.3. 83CIS4/80CIS4 ....................................................................
1.4. 83C1S4D ............... " .............................................................
I.1.3
I.1.3
I. 1.3
I.1.3
2. Memory Organization in CSI Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.1.3
2.1. Logical Separation Of Program And Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. I.1.3
2.2. Program Memory ....................................................................... I.l.4
2.3. Data Memory .......................................................................... U.S
3. The CSI Instruction Set .................................................. 1.1.7
3.1. Program Status Word .................................................................... 1.1.7
3.2. Addressing Modes ...................................................................... I.1.9
3.3. Arithmetic Instructions .................................................................. l.1.10
3.4. Logical Instructions .................................................................... l.1.ll
3.5. Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. l.1.I2
3.6. External RAM ......................................................................... l.1.13
3.7. Lookup Tables ......................................................................... l.1.14
3.8. Boolean Instructions .................................................................... 1.1.14
3.9. Jump Instructions ...................................................................... 1.1.15
4. CPU Timing ........................................................... 1.1.17
4.1. Machine Cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.1.18
4.2. Interrupt Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.1.21
MATRAMHS
Rev. E (14 Jan. 97)
1.1.1
TEMIC
cst Family
Semiconductors
1. Introduction
•
•
•
•
•
The TEMIC CSI microcontroller family is based on the
gOCSI core which features are:
•
•
•
•
•
•
8-bit CPU optimized for control applications
Extensive boolean processing (single-bit logic) capabilities
64 K Program Memory address space
64 K Data Memory address space
4 K bytes of on chip Program Memory
128 bytes of on chip data RAM
32 bidirectionnal and individually addressable 1/0 lines
two 16-bit timerslcounters
Full duplex UART
6 sources I 5-vector interrupt structure with 2 priority levels
on chip clock oscillators
The basic architectural structure of
microcontroller family is shown in figure I.
the
CSI
Figure 1. Block Diagram
INTO
INT1
r-L--1-___ TF1
L..-,...__-
TF2
TFO
RI/TI
TXD
RXD
~P1
P3
ADDRESS/DATA
Each device of the CSI family is listed in Table I.
Table 1: CS1 Family of Microcontrollers.
80C51, TSC80C51
4K
128
2
44 MHz
CMOS
80C52
80C32
8K
256
44 MHz
CMOS
83CI54
80CI54
16K
256
36 MHz
CMOS
36 MHz
CMOS
12 MHz
CMOS
83CI54D
80C51PX
1.1.2
80C31
32 K
256
1281256
2/3
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
1.1. TSCSOC511S0C511S0C31
1.3. S3C154/S0C154
The 80C51 is the CMOS version of the 8051.
Functionally, it is fully compatible with the 8051, but
being CMOS it draws less current than its HMOS
counterpart. To further exploit the power savings
available in CMOS circuitry, two reduced power modes
are added;
• Software-invoked Idle Mode, during which the CPU
is turned off while the RAM and other onchip
peripherals continue operating. In this mode, current
draw is reduced to about 15 % of the current drawn
when the device is fully active.
• Software-invoked Power Down Mode, during which
all on-chip activities are suspensed. The on-chip
RAM continues to hold its data. In this mode the
device typically draws less than 10 !-lA.
The 83Cl54 is an enhanced 80C52. It is produced with
CMOS technology, and is compatible with the 80C5! and
80C52. Its enhancements over the 80C5! are as follows:
Although the 80C51 is functionally compatible with its
HMOS counterpart, specific differences between the two
types of devices must be considered in the design of an
application circuit if one wishes to ensure complete
interchangeability between the HMOS and CMOS
devices.
The ROMless version of the 83C 154 is the 80C 154.
The ROMless version of the 80C5l is the 80C3l.
TSC80C51 is a core optimized version fully compatible
with 80C5l (See product datasheets for electrical
parameters) .
1.2. SOC52/S0C32
The 80C52 is an enhanced 80C5!. It is produced with
CMOS technology, and is compatible with the 80C5!. Its
enhancements over the 80C5l are as follows:
• 256 bytes of on-chip RAM
• Three timer/counters
• 6-source interrupt structure
• 8 K bytes of on-chip Program ROM
The ROMless version of the 80C52 is the 80C32.
•
•
256 bytes of on-chip data RAM
Three timer/counters (included watchdog and 32 bits
timer/counters)
•
•
•
•
•
•
6 source interrupt structure
Serial reception error detection
New modes of power reduction consumption
Programmable impedance port
16 K bytes of on-chip ROM
Asynchronous Counter/Serial port mode during
power-down
1.4. S3C154D
The 83CI54D is an enhanced 80C154. It is produced with
CMOS technology, and is compatible with the 83C154.
Its enhancements over the SOC5l are as follows:
•
•
256 bytes of on-chip data RAM
Three timer/counters (included watchdog and 32 bits
timer/counters)
•
•
•
•
6 source interrupt structure
Serial reception error detection
New modes of power reduction consumption
Programmable impedance port
•
•
32 K bytes of on-chip ROM
Asynchronous Counter/Serial port mode during
power-down.
2. Memory Organization in CSt Devices
2.1. Logical Separation Of Program And
Data Memory
All C5l devices have separated address spaces for
program and Data Memory, as shown in figure 2. The
logical separation of Program and Data Memory allows
the Data Memory to be accessed by 8-bit addresses, which
can be more quickly stored and manipulated by an 8-bit
CPU. Nevertheless, 16-bit Data Memory addresses can
also be generated through the DPTR register.
.
MATRAMHS
Rev. E (14 Jan. 97)
Program Memory can only be read, not written to. There
can be up to 64 K bytes of program Memory. In the ROM
versions of these devices the lowest 4 K, S K, 16 K or 32
K bytes of Program Memory are provided on-chip. Refer
to Table I for the amount of on-chip ROM, on each
device. In the ROMless versions all Program Memory is
external. The read strobe for external Program Memory
is the signal PSEN (Program Store Enable).
1.1.3
II
TEMIC
cst Family
Semiconductors
Figure 2. TEMIC CS1 Memory Structure.
PROGRAM MEMORY
(READ ONLy)
.------------1
FFFFH:
1
1
1
1
DATA MEMORY
(READtWRITE)
,-------------FFFFH:
EXTERNAL
I
I
EXTERNAL
1
I
I
1
EA= a
EXTERNAL
'--_,.---" 0000
I
I
I
I
:
--1--------PSEN
INTERNAL
FFH:CO
ooU
0000
.....,.-----r-'
RD
WR
Data Memory occupies a separate address space from
Program Memory. Up to 64 K bytes of external RAM can
be addressed in the external Data Memory space. The
CPU generates read and write signals, RD and WR, as
needed during external Data Memory accesses. External
Program Memory and external Data Memory may be
combined if desired by applying the RD and PSEN signals
to the inputs of an AND gate and using the output of the
gate as the read strobe to the external Program/Data
memory.
2.2. Program Memory
Figure 3 shows a map of the lower part of the Program
Memory. After reset, the CPU begins execution from
location OOOOH.
1.1.4
As shown in Figure 3, each interrupt is assigned a fixed
location in Program Memory. The interrupt causes the
CPU to jump to that location, where it commences
execution of the service routine. External Interrupt 0, for
example, is assigned to location 0003H. If External
Interrupt 0 is going to be used, its service routine must
begin at location 0003H. If the interrupt is not going to be
used, its service location is available as general purpose
Program Memory.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 3.
cst Program Memory.
Figure 4. Executing
Memory.
from
External
EPROM
MHS
P1
C51
Program
k::==;-;::::======lINSTR.
(0033H)
002BH
LATCH
0023H
INTERRUPT
LOCATIONS
II
INTERNAL
ROM
001BH
1;; BYTES
PS
P2~============~
0013H:L
PSEN~----------------~OE
OOOBH
0003H
OOOOH
The interrupt service locations are spaced at 8-byte
intervals : 0003H for External Interrupt 0, OOOBH for
Timer 0, 0013H for External Interrupt I, OOIBH for Timer
1, etc. If an interrupt service routine is short enough (as
is often the case in control applications), it can reside
entirely within that 8-byte interval. Longer service
routines can use a jump instruction to skip over
subsequent interrupt locations, if other interrupts are in
use.
The lowest 4 K (or 8 K in the 80C52 or 16 K in the 83C154
or 32 K in the 83C154D) bytes of Program Memory can
be either in the on-chip ROM or in an external ROM. This
selection is made by strapping the EA (External Access)
pin to either V cc or Vss. In the 80C51 and its derivatives,
if the EA pin is strapped to Vcc, then program fetches to
addresses OOOOH through OFFFH are directed to the
internal ROM. Program fetches to addresses 1000H
through FFFFH are directed to external ROM.
In the 80C52, EA = Vcc selects addresses OOOOH through
IFFFH to be internal, and addresses 2000H through
FFFFH to be external.
In the 83C154, EA = Vce selects addresses OOOOH
through 3FFFH to be internal, and addresses 4000H to
FFFFH to be external.
In the 83C154D, EA = Vcc selects addresses OOOOH
through 7FFFH to be internal and addresses 8000H to
FFFFH to be external.
If the EA pin is strapped to Vss, then all program fetches
are directed to external ROM. The ROMless parts must
have this pin externally strapped to V ss to enable them to
execute from external Program Memory.
The read strobe to external ROM. PSEN. is used for all
external program fetches. PSEN is not activated for
internal program fetches.
MATRAMHS
Rev. E (14 Jan. 97)
The hardware configuration for external program
execution is shown in figure 4. Note that 16 I/O lines
(Ports 0 and 2) are dedicated to bus functions during
external Program Memory fetches. Port 0 (PO in Figure 4)
serves as a multiplixed address/data bus. It emits the low
byte of the Program Counter (PCL) as an address, and
then goes into a float state awaiting the arrival of the code
byte from the Program Memory. During the time that the
low byte of the Program Counter is valid on PO, the signal
ALE (Address Latch Enable) clocks this byte into an
address latch. Meanwhile, Port 2 (P2 in Figure 4) emits
the high byte of Program Counter (PCH). Then PSEN
strobes the EPROM and the code byte is read into the
microcontroller.
Program Memory addresses are always 16 bits wide, even
though the actual amount of Program Memory used may
be less than 64 K bytes. External program execution
sacrifices two of the 8-bit ports, PO and P2, to the function
of addressing the Program Memory.
2.3. Data Memory
The right half of Figure 2 shows the internal and external
Data Memory spaces available to the C51 user. Figure 5
shows a hardware configuration for accessing up to 2 K
bytes of external RAM. The CPU in this case is executing
from internal ROM. Port 0 serves as multiplexed
address/data bus to the RAM, and 3 lines of Port 2 are
being used to page the RAM. The CPU generates RD and
WR signals as needed during external RAM accesses.
There can be up to 64 K bytes of external Data Memory.
External Data Memory addresses can be either I or 2
bytes wide. One-byte address is often used in conjunction
with one or more other I/O lines to page the RAM, as
shown in Figure 5. Two-byte addresses can also be used,
in which case the address byte is emitted at Port 2.
U.5
TEMIC
cst Family
Semiconductors
Figure 5. Accessing External Data Memory. If the Program Memory is external, the other bits of P2 are
available as 110.
I¢=:::;-;======:~ DATA
P1
MHS
C51
I
INTERNAL
ROM
o
OOOOH
ALEf----~
~
RAM
ADDR
I/O
Internal Data Memory is mapped in figure 6. The memory
space is shown divided into three blocks. which are
generally referred to as the lower 128, the Upper 128, and
SFR space.
Internal Data Memory addresses are always one byte
wide, which implies an address space of only 256 bytes.
However, the addressing modes for internal RAM can in
fact accomodate 384 bytes, using a simple trick. Direct
addresses higher than 7FH access one memory space, and
indirect addresses higher than 7FH access a different
memory space. Thus figure 6 shows the Upper 128 and
SFR space occupying the same block of addresses, 80H
through FFH, although they are physically separate
entities.
Figure 7. The Lower 128 Bytes of Internal RAM.
7FH
BANK
SELECT
BITS IN
2FH
~
o·
BIT·ADDRESSABLE SPACE
(BIT ADDRESSABLE 7F)
20H
1FH
FFH
-
I
I
-
-
A~ESS~LE
"T""-------.FFH
ACCESSIBLE
BY INDIRECT
BY DIRECT
ADDRESSING
ADDRESSING
80H
ONLY
70HI-------I--.,-----....I80H
LOWER
128
The Lower 128 bytes of RAM are present in all C51
devices as mapped in Figure 7. The lowest 32 bytes are
grouped into 4 banks of 8 registers. Program instructions
call out these registers as RO through R7. Two bits in the
Program Status Word (PSW) select which register bank
is in use. This allows more efficient use of code space,
since register instructions are shorter than instructions
that use direct addressing.
PSW~
Figure 6. Internal Data Memory.
UPPER
128
PAGE
BITS
ACCESSIBLE
A~61~~I~~1T
ADDRESSING
O~----~
tSPECIAL
}
FUNCTION
REGISTERS
PORTS
STATUS AND
~I~~OL BITS
11{ 18H
10{
01{
oo{
17H
4 BANKS OF
8 REGISTERS
RD-A?
10H
OFH
08H
07H ~
0
J
RESET VALUE OF
STACK POINTER
~ifb~T~~~TER
ACCUMULATOR
(ETC.)
1.1.6
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
The next 16 bytes above the register banks form a block
of bit-addressable memory space. The CSI instruction set
includes a wide selection of single-bit instructions. and
the 128 bits in this area can be directly addressed by these
instructions. The bit addresses in this area are OOH
through 7FH.
All of the bytes in the Lower 128 can be accessed by either
direct or indirect addressing. The Upper 128 (Figure 8)
can only be accessed by indirect addressing. The Upper
128 bytes of RAM are not implemented in the 80CSI but
are in the 80CS2, 83CIS4 and 83CIS4D.
Figure 8. The Upper 128 Bytes of Internal RAM.
Sixteen addresses in SFR space are both byte-and
bit-addressable. The bit-addressable SFRs are those
whose address ends in 0, 8 or 9. The bit addresses in this
area are 80H through FFH.
Figure 9. SFR Space.
FFH
EOH
I
I
ACC
:
BOH
PORT 3
I
FFH
REGISTER-MAPPED PORTS
ADDRESSES THAT END IN
O. S OR 9
ARE BIT-ADDRESSABLE
I
NO BIT-ADDRESSABLE
SPACES
AOH
PORT 2
90H
PORT 1
SOH
PORTO
:
AVAILABLE AS STACK
SPACE IN SOC52/
SOC154 AND 83C154D
NOT IMPLEMENTED
IN SOC51
- PORT PINS
- ACCUMULATOR
- PSW
(ETC.)
SOH
Figure 9 gives a brief look at the Special Function
Register (SFR) space. SFRs include the Port latches,
timers, peripheral controls, etc. These registers can only
be accessed by direct addressing. In general, all CSI
microcontrollers have the same SFRs as the 80CS1, and
at the same addresses in SFR space. However,
enhancements to the 80CSl have additional SFRs that are
not present in the 80CS1, nor perhaps in other
proliferation of the family.
3. The CSt Instruction Set
All members of the CSI family execute the same
instruction set. (except code ASH, skip opcode in
CSI/CS2). The CSI instruction set is optimized for 8-bit
control applications. It provides a variety of fast
addressing modes for accessing the internal RAM to
facilitate byte operations on small data structures. The
instruction set provides extensive support for one-bit
variables as a separate data type, allowing direct bit
manipulation in control and logic systems that require
Boolean processing.
An overview of the CSI instruction set is presented below,
with a brief description of how certain instructions might
be used.
MATRAMHS
Rev. E (14 Jan. 97)
3.1. Program Status Word
The Program Status Word (PSW) contains several status
bits that reflect the current state of the CPU. The PSW,
shown in Figure 10, resides in SFR space. It contains the
Carry bit, the Auxiliary Carry (for BCD operations), the
two register bank select bits, the Overflow flag, a parity
bit, and two user-definable status flags.
The Carry bit, other than serving the functions of a Carry
bit in arithmetic operations, also serves as the
"Accumulator" for a number of Boolean operations.
1.1.7
II
cst Family
The bits RSO and RSI are used to select one of the four
register banks shown in Figure 7. A number of
instructions refer to these RAM locations as RO through
R7. The selection of which of the four banks is being
referred to is made on the basis of the bits RSO and RS I
at execution time.
1.1.8
TEMIC
Semiconductors
The parity bit reflects the number of I s in the
Accumulator: P = I if the Accumulator contains an odd
number of I s, and P = 0 if the Accumulator contains an
even number of I s. Thus the number of I s in the
Accumulator plus P is always even.
Two bits in the PSW are uncommitted and may be used
as general purpose status flags.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 10. PSW (Program Status Word) Register in C51 Devices.
PSW7
CARRY FLAG RECEIVES CARRY OUT
FROM BIT 1 OF ALU OPERANDS
PSW6
AUXILIARY CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
ADDITION OPERANDS
PSW5 _ _ _---'
GENERAL PURPOSE STATUS FLAG
PSW4
REGISTER BANK SELECT 1 BIT - - - - - - - - '
PSWO
PARITY OF ACCUMULATIOR SET
BY HARDWARE TO 1 IF IT CONTAINS
AN ODD NUMBER OF 1S, OTHERWISE
IT IS RESET TO 0
PSW1
USER DEFINABLE FLAG
L-_ _ _ PSW2
OVERFLOW FLAG SET BY
ARITHMETIC OPERATIONS
PSW3
L------REGISTER BANK SELECT BIT 0
3.2. Addressing Modes
3.2.4. Register-specific instructions
The addressing modes in the CSt instruction set are as
follows:
Some instructions are specific to a certain register. For
example, some instructions always operate on the
Accumulator, or Data Pointer, etc., so no address byte is
needed to point to it. The opcode itself does that.
Instructions that refer to the Accumulator as A assemble
as accumulator-specific opcodes.
3.2.1. Direct addressing
In direct addressing the operand is specified by an 8-bit
address field in the instruction. Only 128 Lowest bytes of
internal Data RAM and SFRs can be directly addressed.
3.2.5. Immediate constants
3.2.2. Indirect addressing
The value of a constant can follow the opcode in Program
Memory. For example,
In indirect addressing the instruction specifies a register
which contains the address of the operand. Both internal
and external RAM can be indirectly addressed.
The address register for 8-bit addresses can be RO or RI
of the selected register bank, or the Stack Pointer.
The address register for 16-bit addresses can only be the
16-bit "data pointer" register, DPTR.
3.2.3. Register instructions
The register banks, containing registers RO through R7,
can be accessed by certain instructions which carry a 3-bit
register specification within the opcode of the instruction.
Instructions that access the registers this way are code
efficient, since this mode eliminates an address byte.
When the instruction is executed, one of the eight
registers in the selected bank is accessed. One of four
banks is selected at execution time by the two bank select
bits in the PSW.
MATRAMHS
Rev. E (14 Jan. 97)
MOV A,# 100
loads the Accumulator with the decimal number 100. The
same number could be specified in hex digits as 64H.
3.2.6. Indexed addressing
Only Program Memory can be accessed with indexed
addressing, and it can only be read. This addressing mode
is intended for reading look-up tables in Program
Memory. A 16-bit base register (either DPTR or the
Program Counter) points to the base of the table, and the
Accumulator is set up with the table entry number. The
address of the table entry in Program Memory is formed
by adding the Accumulator data to the base pointer.
Another type of indexed addressing is used in the "case
jump" instruciion. In this case the destination address of
a jump instruction is computed as the sum of the base
pointer and the Accumulator data.
1.1.9
II
TEMIC
cst Family
Semiconductors
3.3. Arithmetic Instructions
The menu of arithmetic instructions is listed in Table 2.
The table indicates the addressing modes that can be used
with each instruction to access the operand. For
example, the ADD A, instruction can be written
as:
(direct addressing)
ADD A,
7FH
@RO
ADD A,
(indirect addressing)
(register addressing)
ADD A,
R7
(immediate constant)
ADD A,
# 127
Table 2: A Jist of the TEMIC CS1 Arithmetic Instructions.
1...-
'.i
i.?» '. '.' '" ,,",
i......."":
c;;c
;"""\')iii lii~~ . .
':
:.X:'
ii.'
Dir
Ind
Reg
ADD A, e
A = A +
X
X
X
X
ADDC A,
A = A + + C
X
X
X
X
I
SUBB A,
A = A- - C
X
X
X
J
INCA
A=A+ I
INC
= + I
INC DPTR
DPTR = DPTR + I
DEC A
A=A-I
DEC
= - I
X
Accumulator only
X
X
X
Data Pointer only
Accumulator only
X
X
X
Imm
I
I
2
I
I
MULAB
B:A=B xA
ACC and B only
4
DlV AB
A = lot [AlB]
B=Mod [AlB]
ACC and B only
4
DAA
Decimal Adjust
Accumulator only
I
The execution times listed in Table 2 assume a 12 MHz
clock frequency. All of the arithmetic instructions
execute in 1 fls except the INC DPTR instruction, which
takes 2 fls, and the Multiply and Divide instructions,
which take 4 fls.
Note that any byte in the internal Data Memory space can
be incremented or decremented without going through
the Accumulator.
One of the INC instructions operates on the 16-bit Data
Pointer. The Data Pointer is used to generate 16-bit
addresses for external memory, so being able to increment
it in one 16-bit operation is a useful feature.
:I~\>
The DIY AB instruction divides the Accumulator by the
data in the B register and leaves the 8-bit quotient in the
Accumulator, and the 8-bit remainder in the B register.
Oddly enough, DIY AB finds less use in arithmetic
"divide" routines than in radix conversions and
programmable shift operations. An example of the use of
DIY AB in a radix conversion will be given later. In shift
operations, dividing a number by 2n shifts its n bits to the
right. Using DIY AB to perform the division completes
the shift in 4 fls leaves the B register holding the bits that
were shifted out.
The MULAB instruction multiplies the Accumulator by
the data in the B register and puts the 16-bit product into
the concatenated B and Accumulator registers.
1.1.10
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
The DA A instruction is for BCD arithmetic operations.
In BCD arithmetic ADD and ADDC instructions should
always be followed by a DAA operation, to ensure that
the result is also in BDC. Note that DAA will not convert
a binary number to BCD. The DA A operation produces
a meaningful result only as the second step in the addition
of two BCD bytes.
will leave the Accumulator holding OOOlOOOlB.
The addressing modes that can be used to access the
operand are listed in Table 3. Thus, the ANL A,
instruction may take any of the forms.
3.4. Logical Instructions
All of the logical instructions that are Accumulator
specific in I ~s (using a 12 MHz clock). The others take
ANL
ANL
ANL
ANL
Table 3 shows the list of TEMIC C51 logical instructions.
The instructions that perform Boolean operations (AND,
OR, Exclusive OR, NOT) on bytes perform the operation
on a bit-by-bit basis. That is, if the Accumulator contains
OOllOlOlB and contains OIOIOOllB, then
ANL A,
A,7FH
A, @Rl
A, R6
A,#53H
(direct addressing)
(indirect addressing)
(register addressing)
(immediate constant)
II
2 ~s.
Table 3: A list of the TEMIC CS1 Logical Instructions.
',':·:'7
;.
i·y····.····.····
."'~.
~';,.;;\!.< :A.DDRE$S.Il\lG-MODES
EXEC1.JTJJ>N'l'lME·(!-ls)
Dir
Ind
Reg
Imm
ANL A,
A = A AND
X
X
X
X
ANL , A
= AND A
X
I
ANL , # data
= AND # data
X
2
I
ORL A,
A = A OR
X
ORL , A
= OR A
X
I
ORL , # data
= OR # data
X
2
XRL A,
A = A XOR
X
XRL , A
= XOR A
X
I
XRL , # data
= XOR # data
X
2
CLRA
A=OOH
Accumulator only
I
CLPA
A=NOTA
Accumulator only
I
RLA
Rotate ACC Left I bit
Accumulator only
I
RLCA
Rotate Left through Carry
Accumulator only
I
RRA
Rotate ACC Right I bit
Accumulator only
I
RRCA
Rotate Right through Carry
Accumulator only
I
SWAP A
Swap Nibbles in A
Accumulator only
I
Note that Boolean operations can be performed on any
byte in the internal Data Memory space without going
through the Accumulator. The XRL , # data
instruction, for example, offers a quick and easy way to
invert port bits, as in
X
X
X
X
X
X
I
I
If the operation is in response to an interrupt, not using the
Accumulator saves the time and effort to stack it in the
service routine.
XRL PI, #OFFH
MATRAMHS
Rev. E (14 Jan. 97)
Ll.lI
TEMIC
cst Family
The Rotate instructions (RLA, RLCA, etc.) shift the
Accumulator 1 bit to the left or right. For a left rotation,
the MSB rolls into the LSB position. For a right rotation,
the LSB rolls into the MSB position.
The SWAP A instruction interchanges the high and low
nibbles within the Accumulator. this is a useful operation
in BCD manipulations. For example, if the Accumulator
contains a binary number which is known to be less than
100, it can be quickly converted to BCD by the following
code:
MOV
DIV
SWAP
ADD
B, #10
AB
A
A,B
Dividing the number by 10 leaves the tens digit in the low
nibble of the Accumulator, and the ones digit in the B
register. The SWAP and ADD instructions move the tens
digit to the high nibble of the Accumulator, and the ones
digit to the low nibble.
Semiconductors
3.5. Data Transfers
3.5.1. Internal RAM
Table 4 shows the menu of instructions that are available
for moving data around within the internal memory
spaces, and the addressing modes that can be used with
each one. With a 12 MHz clock, all of these instructions
execute in either 1 or 2 Ils.
The MOV , instruction allows data to be
transfered between any two internal RAM or SFR
locations without going through the Accumulator.
Remember the Upper 128 bytes of data RAM can be
accessed only by indirect, and SFR space only by direct
addressing.
Note that in all CSI devices, the stack resides in on-chip
RAM, and grows upwards. The PUSH instruction first
increments the Stack Pointer (SP), then copies the byte
into the stack. PUSH and POP use only direct addressing
to identify the byte being saved or restored, but the stack
itself is accessed by indirect addressing using the SP
register. This means the stack can go into the Upper 128,
if they are implemented, but not into SFR space.
Table 4: A list of the TEMIC CS1 Data Transfer Instructions that Access Internal Data Memory Space.
The Upper 128 are not implemented in the 80CSI, nor in
their ROMless. With these devices, if the SP points to the
Upper 128 PUSHed bytes are lost, and POPped bytes are
indeterminate.
The XCH A, instruction causes the Accumulator
and addressed byte to exchange data.
The XCHD A, @ Ri instruction is similar, but only the
low nibbles are involved in the exchange.
The Data Transfer instructions include a l6-bit MOV that
can be used to initialize the Data Pointer (DPTR) for
look-up tables in Program Memory, or for 16-bit external
Data Memory accesses.
I.1.12
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
The see how XCH and XCHD can be used to facilitate
data manipulations, consider first the problem of shifting
an 8-digit BCD number two digits to the right. Figure II
shows how this can be done using direct MaYs, and for
comparison how it can be done using XCH instructions.
To aid in understanding how the code works, the contents
of the registers that are holding the BCD number and the
content of the Accumulator are shown alongside each
instruction to indicate their status after the instruction has
been executed.
After the routine has been executed, the Accumulator
contains the two digits that were shifted out on the right.
Doing the routine with direct MaYs uses 14 code bytes
and 9 ~s of execution time (assuming a 12 MHz clock).
The same operation with XCHs uses less code and
executes almost twice as fast.
Figure 12. Shifting a BCD Number One Digit to the
Right.
2A
2B
2C
2D
2E
ACC
MOVRI,#2EH
00
12
34
56
XX
MOVRO,#2DH
00
12
34
56
78
78
loop for RI =2EH :
LOOP: MOV A, @RI
00
12
34
XCHDA,@RO
00
12
34
56
58
78
76
SWAP A
00
12
34
58
MOV@RI,A
00
12
34
58
78
78
78
67
67
DECRI
00
12
34
58
67
67
DECRO
00
12
34
58
67
67
MOV A,2EH
MOV2EH.2DH
MOV2DH.2CH
MOV2CH.2BH
MOV2BH.#0
2A
2B
2C
2D
2E
ACC
00
00
00
00
00
12
12
12
12
00
34
34
34
12
12
56
56
34
34
34
78
56
56
56
56
78
78
78
78
78
(a) Using direct MOVs : 14 bytes, 9
CLRA
XCH A,2BH
XCHA,2CH
XCHA.2DH
XCHA.2EH
~s
2A
2B
2C
2E
2E
ACC
00
00
00
00
00
12
00
00
00
00
34
34
12
12
12
56
56
56
34
34
78
78
78
78
56
00
12
34
56
78
(b) Using XCHs : 9 bytes. 5
~s
67
CJNE R I, #2AH, LOOP
loop for RI
loop for RI
loop for RI
Figure 11. Shifting a BCD Number Two Digits to the
Right.
XX
=2DH:
=2CH:
=2BH:
CLRA
XCHA,2AH
00
12
38
45
67
45
00
18
23
45
67
23
I 08 I 01 I 23 I 45 I 67 I 01
1 08 1 0 I 1 23 145 1 67 1 00
00
01
23
45
67
08
To right-shift by an odd number of digits, a one-digit shift
must be executed. Figure 12 shows a sample of code that
will right-shift a BCD number one digit, using the XCHD
instruction. Again, the contents of the registers holding
the number and of the Accumulator are shown alongside
each instruction.
First, pointers Rl and RO are set up to point to the two
bytes containing the last four BCD digits. Then a loop is
executed which leaves the last byte, location 2EH,
holding the last two digits of the shifted number. The
pointers are decremented, and the loop is repeated for
location 2DH. The CJNE instruction (Compare and Jump
if Not Equal) is a loop control that will be described later.
The loop is executed from LOOP to CJNE for Rl =2EH,
2DH, 2CH and 2BH. At that point the digit that was
originally shifted out on the right has propagated to
location 2AH. Since that location should be left with Os,
the lost digit is moved to the Accumulator.
3.6. External RAM
Table 5 shows a list of the Data Transfer instructions that
access external Data Memory. Only indirect addressing
can be used. The choice is whether to use a one-byte
address, @Ri, where Ri can be either RO or RI of the
selected register bank, or a two-byte address, @DPTR.
The disadvantage to using 16-bit addresses if only a few
K bytes of external RAM are involved is that 16-bit
addresses use all 8 bits of Port 2 as address bus. On the
other hand, 8-bit addresses allow one to address a few K
bytes of RAM, as shown in Figure 5, without having to
sacrifice all of Port 2.
MATRAMHS
Rev. E (14 Jan. 97)
1.1.13
II
TEMIC
cst Family
Semiconductors
All of these instructions execute in 2 Ils, with a 12 MHz
clock,
Note that in all external Data RAM accesses, the
Accumulator is always either the destination or source of
the data.
The read and write strobes to external RAM are activated
only during the execution of a MOVX instruction.
Normally these signals are inactive, and in fact if they're
not going to be used at all, their pins are available as extra
I/O lines. More about that later.
Table S: A list of the TEMIC CSI Data Transfer Instructions that Access External Data Memory Space.
8 bits
MOVXA.@Ri
Read external
RAM@Ri
8 bits
MOVX@Ri.A
Write external
RAM@Ri
2
16 bits
MOVX A. @ DPTR
Read external
RAM@DPTR
2
16 bits
MOVX
Write external
RAM@DPTR
2
@
DPTR. A
3.7. Lookup Tables
Table 6 shows the two instructions that are available for
reading lookup tables in Program Memory. Since these
instructions access only Program Memory, the lookup
tables can be read, not updated. The mnemonic is MOVC
for "move constant".
If the table access is to external Program Memory, then
the read strobe is PSEN.
The first MOVC instruction in Table 6 can accomodate a
table of up to 256 entries, numbered 0 through 255. The
number of the desired entry is loaded into the
Accumulator, and the Data Pointer is set up to point to
beginning of the table. Then
MOVC A, @A + DPTR
copies the desired table entry into the Accumulator.
The other MOVC instruction works the same way, except
the Program Counter (PC) is used as the table base, and
the table is accesses through a subroutine. First the
number of the desired entry is loaded into the
Accumulator, and the subroutine is called:
A, ENTRY_NUMBER
MOV
CALL
TABLE
The subroutine "TABLE" would look like this:
MOVC A, @A + PC
TABLE:
RET
The table itself immediately follows the RET (return)
instruction in Program Memory. This type of table can
have up to 255 entries, numbered I through 255. Number
o can not be used, because at the time thc MOVC
instruction is executed, the PC contains the address of the
RET instruction. An entry numbered 0 would be the RET
opcode itself.
Table 6: The CS1 Lookup Table Read Instructions.
MOVC A, @A+DPTR
Read Pgm Memory at (A + DPTR)
MOVC A. @A+PC
Read Pgm Memory at (A + PC)
3.8. Boolean Instructions
C51 devices contain a complete Boolean (single-bit)
processor. The internal RAM contains 128 addressable
bits, and the SFR space can support up to 128 other
addressable bits. All of the port lines are bit-addressable,
and each one can be treated as a separate single-bit port.
The instructions that access these bits are not just
conditional branches, but a complete menu of move, set,
clear, complement, OR and AND instructions. These
kinds of bit operations are not easily obtained in other
architectures with any amount of byte-oriented software.
1.1.14
2
The instruction set for the Boolean processor is shown in
Table 7. All bit accesses are by direct addressing. Bit
addresses OOR through 7FH are in the Lower 128, and bit
addresses 80H through FFR are in SFR space.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Table 7: A list of the CSt Boolean Instructions.
OPERATION
C
~
C AND (NOT bit)
C
~
C OR (NOT bit)
C~bit
bit~C
C~O
bit~O
C~I
bit~
I
C~NOTC
bit = NOT bit
Jump ifC ~ I
Jump ifC ~ 0
Jumpifbit~
Jump if bit ~
Jump if bit ~
C,FLAG
PLO,C
The Carry bit in the PSW is used as the single-bit
Accumulator of the Boolean processor. Bit instructions
that refer to the Carry bit as C assemble as Carry-specific
instructions (CLR C, etc). The Carry bit also has a direct
address, since it resides in the PSW register, which is
bit-addressable.
Note that the Boolean instruction set includes ANL and
ORL operations, but not the XRL (Exclusive OR)
operation. An XRL operation is simple to implement in
software. Suppose, for example, it is required to form the
Exclusive OR of two bits:
C =bitl XRL bit2
The software to do that could be as follows:
C, bitl
bit2, OVER
C
OVER: (continue)
First, bit I is moved to the Carry. If bit 2 = 0, then C now
contains the correct result. That is, bit I XRL bit2 = bitl
if bit2 =0. On the other hand, if bit2 = I C now contains
the complement of the correct result. It need only be
inverted (CPL C) to complete the operation.
MATRAMHS
Rev. E (\4 Jan. 97)
2
1
0
1 ; CLR bit
In this example, FLAG is the name of any addressable bit
in the lower 128 or SFR space. An I/O line (the LSB of
Port 1, in the case) is set or cleared depending on whether
the flag bit is I or 0.
MOV
JNB
CPL
II
C~CORbit
Note how easily an internal flag can be moved to a port
pin:
MOV
MOV
EX'ECU1'ION
C~CANDbit
ANLC,bit
ANLC,/bit
ORLC,bit
ORLC,/bit
MOVC,bit
MOVbit,C
CLRC
CLRbit
SETBC
SETB bit
CPLC
CPLbit
JC rei
JNC rei
JB bit,rel
JNB bit,rel
JBC bit,rel
2
2
This code uses the JNB instruction, one of a series of
bit-test instructions which execute a jump if the addressed
bit is set (JC, JB, JBC) or if the addressed bit is not set
(JNC, JNB). In the above case, bit2 is being tested, and if
bit2 = the CPL C instruction is jumped over.
°
JBC executes the jump if the addresed bit is set, and also
clears the bit. Thus a flag can be tested and cleared in one
operation.
All the PSW bits are directly addressable, so the Parity
bit, or the general purpose flags, for example, are also
available to the bit-test instructions.
3.8.1. Relative offset
The destination address for these jumps is specified to the
assembler by a label or by an actual address in Program
Memory. However, the destination address assembles to
a relative offset byte. This is a signed (two's complement)
offset byte which is added to the PC in two's complement
arithmetic if the jump is executed.
The range of the jump is therefore -128 to + 127 Program
Memory bytes relative to the first byte following the
instruction.
3.9. Jump Instructions
Table 8 shows the list of unconditional jumps.
I. 1.15
TEMIC
cst Family
Semiconductors
Table 8: Unconditional Jumps in TEMIC CS1.
JMP addr
JMP@A+DPTR
CALLaddr
RET
RET!
NOP
Jump to addr
Jump to A + DPTR
Call subroutine at addr
Return from subroutine
Return from interrupt
2
2
2
2
2
No operation
1
The table lists a single "IMP addr" instruction, but in fact
there are three -SJMP, LJMP, AJMP -which differ in the
format of the destination address, JMP is a generic
mnemonic which can be used if the programmer does not
care which way the jump is encoded,
The SJMP instruction encodes the destination address as
relative offset, as described above. The instruction is 2
bytes long, consisting of the opcode and the relative offset
byte. The jump distance is limited to range of -128 to
+ 127 bytes relative to the instruction following the
SJMP.
The LJMP instruction encodes the destination address as
a I6-bit constant. The instruction is 3 bytes long,
consisting of the opcode and two address bytes. The
destination address can be anywhere in the 64K Program
Memory space.
The AJMP instruction encodes the destination address as
an II-bit constant. The instruction is 2 bytes long,
consisting of the opcode, which itself contains 3 of the II
address bits, followed by another byte containing the low
8 bits of the destination address. When the instruction is
executed, these II bits are simply substituted for the low
II bits in the PC. The high 5 bits stay the same. Hence the
destination has to be within the same 2K block as the
instruction following the AJMP.
In all cases the programmer specifies the destination
address to the assembler in the same way: as a label or as
a I6-bit constant. The assembler will put the destination
address into the correct format for the given instruction.
If the format required by the instruction will not support
the distance to the specified destination address, a
"Destination out of range" message is written, into the list
file.
The JMP @ A + DPTR instruction supports case jumps.
The destination address is computed at execution time as
the sum of the 16-bit DPTR register and the Accumulator.
Typically, DPTR is set up with the address of a jump table,
and the Accumulator is given an index to the table. In a
5-way branch, for example, an integer 0 through 4 is
loaded into the Accumulator.
The code to be executed might be as follows:
1.1.16
DPTR, # JUMP_TABLE
MOV
A, INDEX_NUMBER
MOV
RL
A
@A+DPTR
JMP
The RLA instruction converts the index number (0
through 4) to an even number on the range 0 through 8,
because each entry in the jump table is 2 bytes long:
JUMP_TABLE:
AJMPCASE_O
AJMPCASE_I
AJMPCASE_2
AJMPCASE_3
AJMPCASE_4
Table 8 shows a single "CALLaddr" instruction, but there
are two of them -LCALL and ACALL -which differ in the
format in which the subroutine address is given to the
CPU. CALL is a generic mnemonic which can be used if
the programmer does not care which way the address is
encoded.
The LCALL instruction uses the 16-bit address format,
and the subroutine can be anywhere in the 64K Program
Memory space. The ACALL instruction uses the II-bit
format, and the subroutine must be in the same 2K block
as the instructon following the ACALL.
In any case the programmer specifies the subroutine
address to the assembler in the same way: as a label or as
a 16-bit constant. The assembler will put the address into
the correct format for the given instructions.
Subroutines should end a RET instruction, which returns
execution following the CALL.
RETI is used to return from an interrupt service routine.
The only difference between RET and RETI is that RETI
tells the interrupt control system that the interrupt in
progress is done. If there is no interrupt in progress at the
time RETI is executed, then the RETI is functionnally
identical to RET.
Table 9 shows the list of conditional jumps available to
the T.EMIC C51 user. All of these jumps specify the
destination address by the relative offset method, and so
are limited to a jump distance of -128 to + 127 bytes from
the instruction following the conditional jump
instruction. Important to note, however, the user specifies
to the assembler the actual destination address the same
way as the other jumps: as a label or a 16-bit constant.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Table 9: Conditional Jumps in TEMIC CS1 Devices.
JZ rei
Jump if A
JNZ rei
Jump if A" 0
DJNZ ,rel
Decrement and jump if not zero
X
CJNZ A,,rel
Jump if A ~
X
CJNE ,#data,rel
Jump if
~
0
Accumulator only
~
#data
There is no Zero bit in the PSW. The JZ and JNZ
instructions test the Accumulator data for that condition,
LOOP:
MOV
(begin loop)
D
Accumulator only
X
2
X
X
2
2
X
The DJNZ instruction (Decrement and Jump if Not Zero)
is for loop control. To execute a loop N times, load a
counter byte with N and terminate the loop with DJNZ to
the beginning of the loop, as shown below for N = 10 :
COUNTER, # \0
*
*
*
(end loop)
COUNTER, LOOP
DJNZ
(continue)
The CJNE instruction (Compare and Jump if Not Equal)
Another application of this instruction is in "greater than,
can also be used for loop control as in Figure 12, Two
less than" comparisons, The two bytes in the operand
bytes are specified in the operand field of the instruction, field are taken as unsigned integers, If the first is less than
The jump is executed only if the two bytes are not equal.
the second, then the Carry bit is set (1), If the first is
In the example of Figure 12, the two bytes were the data
greater than or equal to the second, then the Carry bit is
cleared,
in Rl and the constant 2AH, The initial data in Rl was
2EH, Every time the loop was executed, Rl was
decremented, and the looping was to continue until the R 1
data reached 2AH,
4. CPU Timing
All C51 microcontrollers have an on-chip oscillator
which can be used if desired as the clock source for the
CPU, To use the on-chip oscillator, connect a crystal or
ceramic resonator between the XTALI and XTAL2 pins
of the microcontroller, and capacitors to ground as shown
in Figure 13,
Figure 13. Using the On-Chip Oscillator.
.----+----1
QUARTZ CRYSTAL
OR CERAMIC
RESONATOR
XTAL2
MHS C51
FAMILY
_+-I XTAL1
L - _....
VSS
MATRAMHS
Rev. E (14 Jan, 97)
I.1.17
TEMIC
cst Family
Semiconductors
Examples of how to drive the clock with an external
oscillator are shown in Figure 14. In the TEMIC C51
devices the signal at the XTALI pin drives the internal
clock generator. If only one pin is going to be driven with
the external oscillator signal, make sure it is the right pin.
The internal clock generator defines the sequence of
states that make up the TEMIC C51 machine cycle.
Figure 14. Using an External Clock.
XTAL2
4.1. Machine Cycles
A machine cycle consists of a sequence of 6 states,
numbered S 1 through S6. Each state time lasts for two
oscillator periods. Thus a machine cycle takes 12
oscillator periods or 1 !ls if the oscillator frequency is 12
MHz.
Each state is divided into a Phase 1 half and a Phase 2 half.
Figure 15 shows the fetch/execute sequences in states and
phases for various kinds of instructions. Normally two
program fetches are generated during each machine
cycle, even if the instruction being executed doesn't
require it. If the instruction being executed doesn't need
more code bytes, the CPU simply ignores the extra fetch,
and the Program Counter is not incremented.
EXTERNAL
CLOCK·_.......- - I XTAL 1
SIGNAL
VSS
MHSC51
1.1.18
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 15. State Sequences in TEMIC C51.
OSC
(XTAL2)
II
ALE
READ OPCODE
I
+~"""':-:-T"'::-""""L..,,-.,......,.....,...-+ :~
NEXT OPCODE AGAIN
(A) 1-byte, 1-cycle instruction, e.g., INC A.
+::-:-......,:-:-T"'::-r::L..,~.....,.....,...-+
f::
NEXT OPCODE
(C) 1-byte, 2-cycle instruction, e.g., INC DPTIjl.
I
I
I
I
I
I
I
READ OPCODE
(MOVX).
READ NEXT
OPCODE (DISCARD).
ACCESS EXTERNAL MEMORY
Execution of a one-cycle instruction (Figure l5A and B)
begins during State I of the machine cycle, when the
opcode is latched into the Instruction Register. A second
fetch occurs during S4 of the same machine cycle.
Execution is completed at the end of State 6 of this
machine cycle.
MATRAMHS
Rev. E (14 Jan. 97)
The MOVX instructions take two machine cycles to
execute. No program fetch is generated during the second
cycle of a MOVX instruction. This is the only time
program fetches are skipped. The fetch/execute sequence
for MOVX instructions is shown in Figure 15 (D).
Ll.19
TEMIC
CSt Family
Semiconductors
The fetch/execute sequences are the same whether the
Program Memory is internal or external to the chip.
Execution times do not depend on whether the Program
Memory is internal or external.
If an access to external Data Memory occurs, as shown in
Figure 16 (B), two PSENs are skipped, because the
address and data bus are being used for the Data Memory
access.
Figure 16 shows the signals and timing involved in
program fetches when the Program Memory is external.
If Program Memory is external, then, the Program
Memory read strobe PSEN is normally activated twice
per machine cycle, as shown in Figure 16 (A).
Figure 16. Bus Cycles in TEMIC CSI Devices Executing from External Program Memory.
ALE
PSEN
RD
--------+-----------;-----------+-----------+-----------7-----
P2
(A)
WITHOUT A
MOVX.
PO
PCLOUT
VALID
PCLOUT
VALID
PCLOUT
VALID
CYCLE2~
r---CYCLE1
I
S1
PCLOUT
VALID
I S2 I S3 I S4 I
S5
I
I S2 I S3 I S4 I S5 I
S6
I
ALE
PSEN
RD
--------+-----------;-----,
(8)
WITH A
MOVX.
P2
PO
t
PCLOUT
VALID
ADDROUT
VALID
t
PCLOUT
VALID
Note that a Data Memory bus cycle takes twice as much
time as a Program Memory bus cycle. Figure 16 shows the
relative timing of the addresses being emitted at ports 0
and 2, and of ALE and PSEN. ALE is used to latch the low
address byte from PO into the address latch.
1.1.20
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
When the CPU is executing from internal Program
Memory, PSEN is not activated, and program addresses
are not emitted. However, ALE continues to be activated
twice per machine cycle and SO is available as a clock
output signal. Note, however, that one ALE is skipped
during the execution of the MOVX instruction.
What follows is an overview of the interrupt structure for
these devices. More detailed information for specific
members of the TEMIC C51 family is provided in the
chapters of this handbook that describe the specific
devices.
4.2.1. Interrupt Enables
4.2. Interrupt Structure
The 80C51 and his ROMless version provide 5 interrupt
sources: 2 external interrupts, 2 timer interrupts, and the
serial port interrupt. the 80C52, 83C154 and 83C154D
and their ROMless version provide these 5 plus a sixth
interrupt that is associated with the third timer/counter
which is present in those devices.
Each of the interrupt source can be individually enabled
or disabled by setting or clearing a bit in the SFR named
IE (Interrupt Enable). This register also contains a global
disable bit, which can be cleared to disable all interrupts
at once. Figure 17 shows the IE register for the 80C51,
80C52 and 83C154 or the 83C154D.
Figure 17. IE (Interrupt Enable) Register in the 80C51, 80C52, 83C154 and 83C154D.
(MSB)
(LSB)
x
EA
ET2
ES
ETl
EXI
ETO
EXO
Symbol
Position
EA
IE.?
IE.6
reserved
ET2
IE.5
enables or disables the Timer 2 overflow or capture interrupt. If ES = 0, the Timer 2
interrupt is disabled.
ES
IE.4
enables or disables the Serial Port interrupt. If ES
disabled.
ETl
IE.3
enables or disables the Timer I Overflow interrupt. If ETl = 0, the Timer I interrupt is
disabled.
EXI
IE.2
enables or disables External Interrupt I. If EXI = O. External Interrupt I is disabled.
ETO
IE. I
enables or disables the Timer 0 Overflow interrupt. If ETO = 0, the Timer 0 interrupt is
disabled.
EXO
IE.O
enables or disables External Interrupt O. If EXO = 0, External Interrupt 0 is disabled.
Function
disables all interrupts. If EA =0, no interrupt will be acknowledged. If EA = I, each
interrupt source is individually enabled or disabled by setting or clearing its enable bit.
4.2.2. Interrupt priorities
Each interrupt source can also be individually
programmed to one of two priority level by setting or
clearing a bit in the SFR named IP (Interrupt Priority).
Figure 18 shows the IP register in the 80C5!, 80C52,
*83C154 and 83C154D.
A low-priority interrupt can be interrupted by a
high-priority interrupt, but not by another low-priority
interrupt.
MATRAMHS
Rev. E (14 Jan. 97)
= 0, the Serial Port interrupt is
A high-priority interrupt can't be interrupted by any other
interrupt source.
If two interrupt requests of different priority levels are
received simultaneously, the request of higher priority
level is serviced. If interrupt requests of the same priority
level are received simultaneously, an internal polling
sequence determines which request is serviced. Thus
within each priority level there is a second priority
structure determined by the polling sequence.
1.1.21
II
TEMIC
cst Family
Semiconductors
Figure 18. IP (Interrupt Priority) Register in the 80C51, 80C52, 83C154 and 83C154D.
(MSB)
(LSB)
x
PCT
PT2
PS
PTI
PXI
PTO
PXO
Functiou
Symbol
Position
PCT
IP.7
83CI54/CI54D only.
Priority interrupt circuit control bit.
The priority register contents are valid and priority assigned interrupts can be processed
when this bit is "0". When the bit is "I", the priority interrupt circuit is stopped, and
interrupts can only be controlled by the interrupt enable register (IE).
IP.6
reserved
PT2
IP.5
defines the Timer 2 interrupt priority level. PT2 = I programs it to the higher priority
level.
PS
IP.4
defines the Serial Port interrupt priority level. PS = 1 programs it to the higher priority
level.
PTI
IP.3
defines the Timer I interrupt priority level. PTI = I programs it to the higher priority
level.
PXI
IP.2
defines the External Interrupt I priority level. PXI = I programs it to the higher priority
level.
.
PTO
IP.I
defines the Timer 0 interrupt priority level. PTO = I programs it to the higher priority
level.
PXO
IP.O
defines the External Interrupt 0 priority level. PXO
level.
Figure 19 shows, for the 80C51, 80C52, 83Cl54 and
83C 154D, how the IE and IP registers and the polling
sequence work to determine which interrupt will be
serviced.
In operation, all the interrupt flags are latched into the
interrupts control system during State 5 of every machine
cycle. The samples are polled during the following
machine cycle. If the flag for an enabled interrupt is found
to be set (1), the interrupt system generates an LCALL to
the appropriate location in Program Memory. unless some
other condition blocks the interrupt. Several conditions
can block an interrupt, among them that an interrupt of
equal or higher priority level is already in progress.
=I programs it to the higher priority
Only the Program Counter is automatically pushed onto
that stack, not the PSW or any other register. Having only
the PC be automatically saved allows the programmer to
decide how much time to spend saving which other
registers. This enhances the interrupt response time,
albeit at the expense of increasing the programmer's
burden of responsability. As a result, many interrupt
functions that are typical in control applications-toggling
a port pin, for example, or reloading a timer, or unloading
a serial buffer can often be completed in less time than it
takes other architectures to commence them.
The hardware-generated LCALL causes the contents of
the Program Counter to be pushed onto the stack, and
reloads the PC with the beginning address of the service
routine. As previously noted (Figure 3), the service
routine for each interrupt begins at a fixed location.
1.1.22
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 19. 80C51, 80C52, 83C154 and 83C154D Interrupt Control System.
IP REGISTER
INTO
II
o--o"(r>-I---l--<>--
I
I
TFO
----------~~~~~--~~~+---~
INTERRUPT
POLLING
SEQUENCE
I
I
~o-+--+---oI
~~--~~
I
0-4C>-1--1---<>.-
TF1
I
I
~4---~~
Jo+--I-o.... 0--+----'.,
RI
TI
I
I
I
~O+--I-o....
TF2
EXF2
I
L-4----T~
INDIVIDUAL
ENABLES
L-,-~
GLOBAL
DISABLE
4.2.3. Simulating a third priority level in software
Some applications require more than the two priority
levels that are provided by on-chip hardware in C51
devices. In these cases, relatively simple software can be
written to produce the same effect as a third priority level.
First, interrupts that are to have higher priority than I are
assigned to priority 1 in the IP (Interrupt Priority) register.
The service routines for priority I interrupts that are
supposed to be interruptible by "priority 2" interrupts are
written to include the following code:
PUSH
MOV
CALL
IE
IE, # MASK
LABEL
~4-----~
'--_---'!.
LOW PRIORITY
INTERRUPT
As soon as any priority 1 interrupt is acknowledged, the
IE (Interrupt Enable) register is redefined so as to disable
all but "priority 2" interrupts. Then, a CALL to LABEL
executes the RETI instruction, which clears the priority
I interrupt-in-progress flip-flop. At this point any priority
1 interrupt that is enabled can be serviced, but only
"priority 2" interrupts are enabled.
POPping IE restores the original enable byte. Then a
normal RET (rather than another RETI) is used to
terminate the service routine. The additional software
adds 10 j.l.s (at 12 MHz) to priority I interrupts.
**********
(execute service routine)
LABEL:
POP
RET
RETI
MATRAMHS
Rev. E (14 Jan. 97)
********
IE
11.23
TEMIC
Semiconductors
cst Family
Hardware Description of the CS1 Family Products
II
Summary
1. Common Features Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.2
1.1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.2
1.2. Oscillator and Clock Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.4
1.3. CPU Timing ........................................................................... 1.2.S
1.4. Port Structures and Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.6
1.S. Accessing External Memory .............................................................. 1.2.10
1.6. Timer/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.13
1.7. Serial Interface (80CSI and 80CS2 only) .................................................... 1.2.18
1.8. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.29
1.9. Single Step Operation ................................................................... 1.2.33
1.10. Reset ............................................................................... 1.2.33
1.11. Power-Saving Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.2.34
1.12. More about the On-chip Oscillator ........................................................ 1.2.36
1.13. Internal Timing ....................................................................... 1.2.37
1.14. CSI Pin Description ................................................................... 1.2.38
2. More Features for C154 Parts ............................................ 1.2.41
2.1. I/O Port Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.2 Watchdog and 32-bit Timer/Counter Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
2.3 Power-Reducing Mode ..................................................................
2.4 Frame and Overrun Error Serial Link Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
MATRAMHS
Rev. E (14 Jan. 97)
1.2.41
1.2.42
1.2.4S
1.2.46
1.2.1
TEMIC
cst Family
Semiconductors
1. Common Features Description
1.1. Introduction
This chapter presents a comprehensive description of the
on-chip hardware features of the TEMIC C51
microcontrollers. Included in this description are :
• The port drivers and how they function both as ports
and, for Ports 0 and 2, in bus operations
•
•
•
•
•
The Timer/Counters
The serial Interface
The Interrupt System
Reset
The reduced Power Modes
Figure 1. CS1 Architecture Block Diagram.
POO-P07
P20-P27
-------l
vee
vs:?,
~
I
I
I
I
I
r--..1-...L..--:/L...-~ I
I
I
I
I
I
I
I
I
I
I
I
I
I
PSEN
ALE
EA
RST
-----I
P1 O-P1 7
P30-P37
* 83C154 and 83C154D only.
1.2.2
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Table 1. The TEMIC CSt Family of Microcontrollers.
··NAME.
DEVICE
ROMLESS
VERSION
8OC51, TSC80C51
80C31
·t(f;;.BIT
TIMf';RS·
4K
128
CMOS
8OC52
80C32
8K
256
83CI54
8OCl54
16K
256
3*
CMOS
32K
256
3*
CMOS
83CI540
II
CMOS
* included watchdog and Timer 32 bits.
The devices under consideration are listed in Table I. As
it becomes unwieldy to be constantly referring to each of
these devices by their individual names, we will adopt a
convention of refering to them generically as 80C5l s,
8OC52s and 83C154s, unless a specific member of the
group is being refered to, in which case it will be
specifically named. The 80C51 s include the TSC8OC51,
8OC51 and 80C3!. The 80C52s are the 80C52 and 80C32.
The 83CI54s are the 83C154, the 80CI54 and the
83C154D.
Figure I. shows a functionnal block diagram of the
80C51s, 80C52s and 83C154s.
Special Function Registers
A map of the on-chip memory area called SFR (Special
Function Register) space is shown in Figure 2. SFRs
marked by parentheses are resident in the 80C52s and
83C154s but not in the 80C51s. IOCON marked by a star
is only resident in the 83C 154s.
Note that not all of the addresses are occupied.
Unoccupied addresses are not implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.
Figure 2. SFR Map. (...) Indicates Resident in 80CS2s and 83ClS4s, not in 80CSls.
8 Bytes
F8
*lOCON
FO
B
FF
F7
EF
E8
EO
E7
ACC
OF
08
DO
PSW
C8
(T2CON)
D7
(RCAP2L)
(RCAP2H)
(TL2)
CF
(TH2)
CO
C7
BF
B8
IP
BO
P3
B7
A8
IE
AF
AO
P2
98
SCON
A7
9F
SBUF
97
90
PI
88
TCON
TMOO
TLO
TLi
80
PO
SP
OPL
OPH
THO
THI
8F
PCON
87
* 83CI54s only.
MATRAMHS
Rev. E (14 Jan. 97)
1.2.3
TEMIC
cst Family
User software should not write Is to theses
unimplemented locations, since they may be used in
future TEMIC C51 products to invoke new features. In
that case the reset or inactive values of the new bits will
always be 0, and their active values will be 1.
Semiconductors
1.1.8. Timer registers
Register pairs (THO, TLO), (TH1, TLl), and (TH2, TL2)
are the 16-bit counting registers for Timer/Counters 0, 1,
and 2, respectively.
The functions of the SFRs are described as below.
1.1.9. Capture registers
1.1.1. Accumulator
The register pair (RCAP2H, RCAP2L) are the capture
register for the Timer 2 "capture mode." In this mode, in
response to a transition at the 80C52' s T2EX pin, TH2 and
TL2 are copied into RCAP2H and RCAP2L. Timer 2 also
has a 16-bit auto-reload mode, and RCAP2H and
RCAP2L hold the reload value for this mode. More about
Timer 2's features in Section 1.6.
ACC is the Accumulator register. The mnemonics for
accumulator-specific instructions, however, refer to the
accumulator simply as A.
1.1.2. B Register
The B register is used during multiply and divide
operations. For other instructions it can be treated as
another scratch pad register.
1.1.3. Program status word
The PSW register contains program status information as
detailed in Figure 3.
1.1.4. Stack pointer
The Stack Pointer register is 8 bits wide. It is incremented
before data is stored during PUSH and CALL executions.
While the stack may reside anywhere in on-chip RAM,
the Stack Pointer is initializcd to 07H after a reset. This
causes the stack to begin at location 08H.
1.1.5. Data pointer
The Data Pointer (DPTR) consists of a high byte (DPH)
and a low byte (DPL). Its intended function is to hold a
l6-bit address. It may be manipulated as a 16-bit register
or as two independent 8-bit registers.
1.1.6. Ports 0 to 3
PO, PI, P2 and P3 are the SFR latches of Ports 0,1, 2 and
3, respectively.
1.1.7. Serial data buffer
The Serial Data Buffer is actually two separate registers,
a transmit buffer and a receive buffer register. When data
is moved to SBUF, it goes to the transmit buffer where it
is held for serial transmission. (Moving a byte to SBUF
is what initiates the transmission.) When data is moved
from SBUF, it comes from the receive buffer.
1.2.4
1.1.10. Control registers
Special Function Registers IP, IE, TMOD, TCON,
T2CON, SCON, and PCON contain control and status
bits for the interrupt system, the timer/counters, and the
serial port. They are described in later sections.
1.2. Oscillator and Clock Circuit
XTALI and XTAL2 are the input and output of a
single-stage on-chip inverter, which can be configured
with off-chip components as a Pierce oscillator, as shown
in Figure 4. The on-chip circuitry, and selection of
off-chip components to configure the osci llator are
discussed in Section 1.12.
r
Figure 3. Crystal/Ceramic Resonator Oscillator.
30 pi +/- 10 pi FOR CRYSTALS
40 pi +/-10 pi FOR CERAMIC RESONATORS
18
t-----..--CJ----'-=-i XTAL2
JLr-_+___
-i XTAL1
19
30 pi +/- 10 pi FOR CRYSTALS
40 pi +/- 10 pi FOR CERAMIC RESONATORS
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
Figure 4. PSW : Program Status Work Register.
(MSB)
CY
(LSB)
AC
FO
RSI
RSO
OV
P
II
Symbol
Position
CY
AC
PSW7
PSW6
FO
PSW.5
RSI
PSW.4
RSO
PSW3
Symbol
Position
OV
PSW2
PSWI
PSWO
p
Note:
Carry nag
Auxiliary Carry nag.
(For BCD operations.)
Flag 0
(Available to the user for general purposes.)
Register bank Select control bits 1 & O. Set/cleared by software to
determine working register bank (see Note).
Name and Significance
Overflow nag.
(reserved)
Parity nag.
Set/cleared by hardware each instruction cycle to indicate and odd/even
number of "one" bits in the accumulator, i.e., even parity.
the contents of (RS I. RSO) enable the working register banks as follows
(O.Q)-Bank 0
(OOH-07H)
(OSH-OFH)
(O.I)-Bank I
(I.O)-Bank 2
(IOH-I7H)
(1.l)-Bank 3
(lSH-IFH)
The oscillator, in any case, drives the internal clock
generator. The clock generator provides the internal
clocking signals to the chip. The internal clocking signals
are at half the oscillator frequency, and define the internal
phases, states, and machine cycles, which are described
in the next section.
MATRAMHS
Rev. E (14 Jan. 97)
Name and Significance
1.3. CPU Timing
A machine cycle consists of 6 states (12 oscillator
periods). Each state is divided into a Phase I half, during
which the Phase I clock is active, and a Phase 2 half,
during which the Phase 2 clock is active. Thus, a machine
cycle consists of 12 oscillator periods, numbered SIPI
(State I, Phase I), through S6P2 (State 6, Phase 2). Each
phase lasts for one oscillator period. Each state lasts for
two oscillator periods. Typically, arithmetic and logical
operations take place during Phase I and internal
register-to-register transfers take place during Phase 2.
1.2.5
cst Family
The diagrams in Figure S show the fetch/execute timing
referenced to the internal states and phases. Since these
internal clock signals are not user accessible, the XTAL2
oscillator signal and the ALE (Address Latch Enable)
signal are shown for external reference. ALE is normally
activated twice during each machine cycle: once during
S I P2 and S2PI, and again during S4P2 and SSPI.
Execution of one-cycle instruction begins at S I P2, when
the opcode is latched into the Instruction Register. If it is
a two-byte instruction, the second byte is read during S4
of the same machine cycle. If it is one-byte instruction,
there is still a fetch at S4, but the byte read (which would
be the next opcode), is ignored, and the Program Counter
is not incremented. In any case, execution is complete at
the end of S6P2. Figures I-SA and I-SB show the timing
for a I-byte, I-cycle instruction and for a 2-byte, I-cycle
instruction.
Most 80CSI instructions execute in one cycle. MUL
(multiply) and DIV (divide) are the only instructions that
take more than two cycles to complete. They take four
cycles.
I.2.6
TEMIC
Semiconductors
Normally, two codes bytes are fetched from Program
Memory during every machine cycle. The only exception
to this is when a MOVX instruction is executed. MOVX
is a I-byte 2-cycle instruction that accesses external Data
Memory. During a MOVX, two fetches are skipped while
the external Data Memory is being addressed and strobed.
Figure I-SC and l-SD show the timing for a normal
I-byte, 2-cycle instruction and for a MOVX instruction.
1.4. Port Structures and Operation
All four ports in the 80CSI are bidirectional. Each
consists of a latch (Special Function Register PO through
P3), an output driver, and an input buffer.
The output drivers of Ports 0 and 2, and input buffers of
Port 0, are used in accesses to external memory. In this
application, Port 0 outputs the low byte of the external
memory address, time-multiplexed with the byte being
written or read. Port 2 outputs the high byte of the external
memory address when the address is 16 bits wide.
Otherwise the Port 2 pins continue to emit the P2 SFR
content.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 5. 80CSI fetchlExecute Sequences.
I ~I~I~I~I~I%I~I~I~I ~I~I%I~
~~~~~~~~~~~~~~~~~~~~~~~~~~
OSC
(XTAL2)
a
ALE
READ NEXT
OPCODE
(DISCAR~:~_
J=
,
READ NEXT OPCODE A r IN .
T-~~--~-'~-'-S~5-r~S-6~
,
(A) 1-byte, 1,-cycle instruction, e.g., INCA.
READ 2ND BYTE.
L_
+-'l-T-::-'-r-::-'-'~-'~-'-::-:--;! ____
READ NEXT OPCODE.
(B) 2-byte, 1'-cycle instruction, e.g., ADD A, #data:
":-=-=-"'-''''-'~-r"--_R_E_A_D_N_E_X_T,OPCODE AGT_J__
___________
S6
~~_-L_'----'-_....L_!--_L--~_-L_'----'----'
(C) 1-byte, 2~cycle instruction, e.g., INC DPTR.
:
:
:
READ OPCODE
(MOVX).
READ NEXT
OPCODE (DISCARD).
READ NEXT OPCODEAGAIN n :
:
'NO
'
: FETCH
NO FETCH
:
:
(D) MOVX (1-byte, 2-cycle).
!__
J __
DATA
L--~
__
-v-_ _- _ - J
ACCESS EXTERNAL MEMORY
All the Port 3 pins, and (in the 80C52) two Port I pins are
multifunctional. They are not only port pins, but also
serve the functions of various special featurcs as listed
below:
Port Pin
*PI.O
*PI.!
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
Alternate Function
T2 (Timer/Counter 2 external input)
T2EX (Timer/Counter 2 capture/reload
trigger)
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt)
INTI (external interrupt)
TO (Timer/Counter 0 external input)
TI (Timer/Counter 1 external input)
P3.6
WR (external Data memory write strobe)
P3.7
RD (external Data memory read strobe)
* PI.O and Pl.l serve these alternate functions only on the 80C52,
83CI54 and 83C154D.
MATRAMHS
Rev. E (14 Jan. 97)
The alternate functions can only be activated if the
corresponding bit latch in the port SFR contains a 1.
Otherwise the port pin is stuck at O.
1.4.1. I/O Configurations
Figure 6. shows a functional diagram of a typical bit latch
and 1/0 buffer in each of the four ports. The bit latch (one
bit in the port's SFR) is represented as a Type D flip-flop,
which will clock in a value from the internal bus in
response to a "write to latch" signal from the CPU. The
Q output of the flip-flop is placed on the internal bus in
response to a "read latch" signal from the CPU. The level
of the port pin itself is placed on the internal bus in
response to a "read pin" signal from the CPU. Some
instructions that read a port activate the "read latch"
signal, and others activate the "read latch" signal, and
others acti vale the "read pin" signal.
1.2.7
TEMIC
cst Family
Semiconductors
Figure 6. 80CS1 Port Bit Latches and 110 Buffers.
Vee
Vee
WRITE
TO
LATCH
(A) PORT 0 BIT
(B) PORT 1 BIT
ALTERNATE
OUTPUT
FUNCTION
Vee
READ
LATCH
ADDR
CONTROL
READ
LATCH
--1-1
INT. B""U",S
INT. BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
(e) PORT 2 BIT
(D) PORT 3 BIT
* See Figure 7. for details of the internal pullup.
As shown in Figure 6., the output drivers of Ports 0 and
2 are switchable to an internal ADDR and ADDRIDATA
bus by an internal CONTROL signal for use in external
memory accesses. During external memory accesses, the
P2 SFR remains unchanged, but the PO SFR gets Is
written to it.
Also shown in Figure 6., is that if a P3 bit latch contains
a I, then the output level is controlled by the signal
labeled "alternate output function." The actual P3.X pin
level is always available to the pin's alternate input
function, if any.
Ports 1, 2, and 3 have internal pull-ups. Ports 0 has
open-drain outputs. Each 110 line can be independently
used as an input or an output. (Ports 0 and 2 may not be
used as general purpose I/O when being used as the
ADDRIDATA BUS). To be used as an input, the port bit
latch must contain a 1, which turns off the output driver
FET. Then, for Ports 1,2, and 3, the pin is pulled high by
the internal pull-up, but can be pulled low by an external
source.
1.2.8
Port 0 differs in not having internal pullups. The pullup
FET in the PO output driver (see Figure 1-6A) is used only
when the Port is emitting Is during external memory
accesses. Otherwise the pullup FET is off. Consequently
PO lines that are being used as output port lines are open
drain. Writing a 1 to the bit latch leaves both output FETs
off, so the pin floats. In that conditions it can be used as
a high-impedance input.
Because Ports 1, 2, and 3 have fixed internal pull ups they
are sometimes called "quasi-bidirectional" ports. When
configured as inputs they pull high and will source current
(ilL, in the data sheets) when externally pulled low. Port
0, on the other hand, is considered "true" bidirectional,
because when configured as an input it floats.
All the port latches in the 80C51 have 1s written to them
by the reset function. If a 0 is subsequently written to a
port latch, it can be reconfigured as an input by writing a
I to it.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
1.4.2. Writing to a Port
In the execution of an instruction that changes the value
in a port latch, the new value arrives at the latch during
S6P2 of the final cycle of the instruction. However, port
latches are in fact sampled by their output buffers only
during Phase I of any clock period. (During Phase 2 the
output buffer holds the value it saw during the previous
Phase I). Consequently, the new value in the port latch
won't actually appear at the output pin until the next
Phase I, which be at S I PI of the next machine cycle.
If the change requires a 0-to-1 transition in Port I, 2, or
3, an additional pull-up is turned on during S IPI and
SIP2 of the cycle in which the transition occurs. This is
done to increase the transition speed. The extra pull-up
can source about 100 times the current that the normal
pull-up can. It should be noted that the internal pull-ups
are field-effect transistors, not linear resistors. The
pull-up arrangements are shown in Figure 7.
In the CMOS versions, the pull-up consists of three
pFETs. It should be noted that an n-channel FET (nFET)
is turned on when a logical I is applied to its gate, and is
turned off when a logical 0 is applied to its gate. A
p-channel FET (pFET) is the opposite: it is on when its
gate sees a 0, and off when its gate sees a I.
pFET I in Figure 7. is the transistor that is turned on 2
oscillator periods after a O-to-I transition in the port latch.
While it's on, it turns on pFET 3 (a weak pull-up), through
the inverter. This inverter and pFET form a latch which
hold the I.
Note that if the pin is emitting a I, a negative glitch on the
pin from some external source can turn off pFET 3,
causing the pin to go into a float state, pFET 2 is a very
weak pull-up which is on whenever the nFET is off, in
traditional CMOS style. It's only about III 0 the strenght
of pFET3. Its function is to restore a I to the pin in the
event the pin had a I and lost it to a glitch.
Figure 7. Ports 1 and 3 CMOS Internal Pull-up Configurations.
Port 2 is similar except that it holds the strong pullup on while emitting Is that are address bits.
(See test, "Accessing External Memory".)
CMOS Configuration. pFET 1 is turned on
for 2 osc. periods after Q makes a I-to-O
transition. During this time, pFET 1 also turns
on pFET 3 through the inverter to form a
latch which holds the 1. pFET 2 is also on.
FROMQpORT·D---~-----~'-----+F::..'C..
LATCH
1~~~Io------<><
READ
PORT PIN
1.4.3. Port loading and interfacing
Figure 8. Port Interfacing.
The output buffer of Ports I, 2 and 3 can each drive 3LS
TIL inputs. The pins can be driven by open-collector and
open-drain outputs, but note that O-to-l transition will not
be fast. In the CMOS device, an input 0 turns off pullup
P3, leaving only the weak pullup P2 to drive the transistor.
The Figure 8. shows an example where the port is driven
by an open drain transistor tN. The parasitic capacitance
is equal to 100pP.
MATRAMHS
Rev. E (14 Jan. 97)
1.2.9
II
TEMIC
cst Family
Semiconductors
The Figure 9. shows the behaviour of the port during
O-to-1 transition.
In the area A only pullup P2 sinks the capacitor and takes
5 I.ls to switch from 0 volt to 2 volts. In the area B, pullup
P2 and P3 feed the capacitor and the time to charge the
capacitor is divide roughly by ten. So this figure shows it
takes some machine cycles before having a true high level
during a O-to-l transition.
The reason that read-modify-write instructions are
directed to the latch rather than the pin is to avoid a
possible misinterpretation of the voltage level at the pin.
For example, a port bit might be used to drive the base of
a transistor. When a I is written to the bit, the transistor
is turned on. If the CPU then reads the same port bit at the
pin rather than the latch, it will read the base voltage of
the transistor and interpret it as a O. Reading the latch
rather than the pin will return the correct value of I.
Further details are given in the next chapter concerning
the powerful functions of the 83CI54 I/O PORTS.
Figure 9. Port Behaviour During O-to-l
Transition.
1.5. Accessing External Memory
Accesses to external memory are of two types : accesses
to external Program Memory and accesses to external
Data Memory. Accesses to external Program Memory use
signal PSEN (program store enable) as the read strobe.
Accesses to external Data Memory use RD or WR
(alternate function of P3.7 and P3.6) to strobe the
memory.
B
IL--t--t-...L..-t--t--t--+-+-+--~t("")
10
12
14
16
1.4.4. Read-Modify-Write Feature
Some instructions that read a port read the latch and
others read the pin. Which ones do which ? The
instructions that read the latch rather than the pin are the
ones that read a value, possibly change it, and then rewrite
it to the latch. These are called "read-modify-write"
instructions. The instructions listed below are
read-modify-write instructions. When the destination
operand is a port, or a port bit, these instructions read the
latch rather than the pin:
ANL
(logical AND, e.G., ANL PI ,A)
ORL
(logical OR, e.g., ORL P2,A)
XRL
(logical EX-OR, e.g., XRL P3,A)
JBC
(jump if bit = I and clear bit, e.g., JBC
Pl.1, LABEL)
(complement bit, e.g., CPL P3.0)
CPL
(increment, e.g., INC P2)
INC
DEC
(decrement, e.g., DEC P2)
DJNZ
(decrement and jump if not zero, e.g.,
DJNZ P3, LABEL)
MOVPX.Y,C
(move carry bit to bit Y of Port Xl
(clear bit Y of Port X)
CLRPX.Y
SETB PX.Y
(set bit Y of Port X)
Fetches from external Program memory always use a
16-bit address. Accesses to external Data Memory can
use either a 16-bit address (MOVX @DPTR) or an 8-bit
address (MOVX @Ri).
Whenever a 16-bit address is used, the high byte of the
address comes out on Port 2, where it is held for the
duration of the read or write cycle. Note that the Port 2
drivers use the strong pullups during the entire time that
they are emitting address bits that are 1s. This is during
the execution of a MOVX @DPTR instruction. During
this time the Port 2 latch (the Special Function register)
does not have to contain I s, and the contents of the Port
2 SFR are not modified. If the external memory cycle is
not immediately followed by another external memory
cycle, the undisturbed contents of the Port 2 SFR will
reappear in the next cycle.
If an 8-bit address is being used (MOVX @Ri), the
contents of the Port 2 SFR remain at the Port 2 pins
throughout the external memory cycle. This will facilitate
paging.
It is not obvious that the last three instructions in this list
are read-modify-write instructions, but they are. They
read the port byte, all 8 bits, modify the addressed bit, then
write the new byte back to the latch.
1.2.10
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
In any case, the low byte of the address is
time-multiplexed with the data byte on Port O. The
ADDRIDATA signal drives both FETs in the Port 0 output
buffers. Thus, in this application the Port 0 pins are not
open-drain outputs, and do not require external pull-ups.
Signal ALE (address latch enable) should be used to
capture the address byte into an external latch. The
address byte is valid at the negative transitions of ALE.
Then, in a write cycle, the data byte to be written appears
on Port 0 just before WR is activated, and remains there
until after WR is deactivated. In a read cycle, the
incoming byte is accepted at Port 0 just before the read
strobe is desactivated.
During any access to external memory, the CPU writes
OFFH to the Port 0 latch (the Special Function Register),
thus obliterating whatever information the Port 0 SFR
may have been holding.
External program Memory is accessed under two
conditions:
I) Whenever signal EA is active; or
2) Whenever the program counter (PC) contains a
number that is larger than OFFFH (lFFFH for the
80C52, 3FFFH for the 83CI54 and 7FFFH for the
83C154D.
This requires that the ROMless versions have EA wired
low to enable the lower 4K (8K for the 80C32, 16K for the
80CI54 and 32K for the 80C154D) program bytes to be
fetched from external memory.
MATRAMHS
Rev. E (14 Jan. 97)
When the CPU is executing out of external Program
Memory, all 8 bits of Port 2 are dedicated to an output
function and may not be used for general purpose I/O.
During external program fetches they output the high byte
of the Pc. During this time the Port 2 drivers use the
strong pull ups to emit PC bits that are Is.
PSEN
The read strobe for external fetches is PSEN. PSEN is not
activated for internal fetches. When the CPU is accessing
external Program Memory, PSEN is activated twice every
cycle (except during a MOVX instruction) whether or not
the byte fetched is actually needed for the current
instruction. When PSEN is activated its timing is not the
same as RD. A complete RD cycle, including activation
and deactivation of ALE and RD, takes 12 oscillator
periods. A complete PSEN cycle, including activation
and deactivation of ALE and PSEN, takes 6 oscillator
periods. The execution sequence for these two types of
read cycles are shown in Figure 10 for comparison.
I.2.11
II
TEMIC
cst Family
Semiconductors
Figure 10. External Program Memory Execution.
ALE
:
P2
P~ I
PCH OUT
,
X:
X:
I
PCH OUT
PCH OUT
X:
w
,WITHOUT A
PCH OUT
~UT
MOv)(.
PO
ALE
PSEN
(B)
WITH A
RD
MOVX.
P2 PCH OU
'PCH OUT
,
DPH OUT OR P2 OUT
tPCLOUT
VALID
tADDROUT
VALID
, PCHOUT
CHOUT
PO
ALE
The main function of ALE is to provide a properly timed
signal to latch the low byte of an address from PO to an
external latch during fetches from external Program
Memory. For that purpose ALE is activated twice every
machine cycle. This activation takes place even when the
cycle involves no external fetch. The only time an ALE
pulse doesn't come out is during an access to external
Data Memory. The first ALE of the second cycle of a
MOVX instructions is missing (see Figure 10.).
Consequently, in any system that does not use external
Data Memory, ALE is activated at a constant rate of 1/6
the oscillator frequency, and can be used for external
clocking or timing purposes.
1.2.12
tPCLOUT
VALID
Overlapping External Program and Data Memory
Spaces
In some applications it is desirable to execute a program
from the same physical memory that is being used to store
data. In the 80CS1, the external Program and Data
Memory spaces can be combined by ANDing PSEN and
RD. A positive-logic AND of these two signals produces
an active-low read strobe that can be used for the
combined physical memory. Since the PSEN cycle is
faster than the RD cycle, the external memory needs to be
fast enough to accomodate the PSEN cycle.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
In addition to the "timer" or "counter" selection, Timer
1.6. Timer/Couuters
The 80C51 has two 16-bit timerlcounter registers: Timer
o and Timer 1. The 80C52, 83Cl54 and 83Cl54D have
these two plus one more : Timer 2. All three can be
configured to operate either as timers or event counters.
o and Timer I have four operating modes from which to
select. Timer 2, in the 80C52, 83CI54 and 83C154D has
three modes of operation: "capture," "auto-reload" and
"baud rate generator."
II
In the "timer" function, the register is incremented every
machine cycle. Thus, one can think of it as counting
machine cycles. Since a machine cycle consists of 12
oscillator periods, the count rate is 1112 of the oscillator
frequency.
In the "counter" function, the register is incremented in
response to a I-to-O transition at its corresponding
external input pin, TO, T1 or (in the 80C52, 83C154 and
83C154D) T2. In this function, the external input is
sampled during S5P2 of every machine cycle. When the
samples show a high in one cycle and a low in the next
cycle, the count is incremented. The new count value
appears in the register during S3Pl of the cycle following
the one in which the transition was detected. Since it takes
2 machine cycles (24 oscillator periods) to recognize a
I-to-O transition, the maximum count rate is 1124 of the
oscillator frequency. There are no restrictions on the duty
cycle of the external input signal, but to ensure that a
given level is sampled at least once before it changes, it
should be held for at least one full machine cycle.
Figure 11. TMOD : Timer/Counter Mode Control Register.
(LSB)
(MSB)
I GATE
err
MI
TIMER 1
GATE
eiT
err
Ml
MO
TIMER 0
Gating control When set. Timer/counter "x" is enabled only while "INTx" pin is high and "TRx" control pin is
set. When cleared Timer "x" is enabled whenever "TRx" control bit is set.
Timer or Counter Selector Cleared for Timer operation (input from internal system clock.) Set for Counter
operation (input from "Tx" input pin).
Ml
MO
o
o
o
MATRAMHS
Rev. E (14 Jan. 97)
MO
o
Operatong Mode
MCS-48 Timer "TLx" serves as five-bit prescaler.
16 bit Timer/Counter "THx" and "TLx" are cascaded; there is no prescaler
8 bit auto-reload timer-counter "THx" holds a value which is to be reloaded into ''TLx''
each timer it overflows.
(Timer 0)
TLO is an eight bit timer counter-controlled by the standard Timer 0 control
bits THO is an eight-bit timer only controlled by Timer I control bits.
(Timer I)
Timer-counter I stopped.
I.2.13
TEMIC
cst Family
Semiconductors
Timer 0 and Timer I
These timer/counter are. present in both the 80C51, the
80C52, the 83CI54 and the 83C154D. The "timer" or
"counter" function is selected by control bits CIT in the
Special Function Register TMOD (Figure I!,). These two
timer/counters have four operating modes, which are
selected by bit-pairs (MI, MO) in TMOD. Modes 0, I, and
2 are the same for both timer/counters. Modes 3 is
different. The four operating modes are described below.
The 13-bit register consists of all 8 bits of THI and the
lower 5 bits of TLI. The upper 3 bits of TLI are
indeterminate and should be ingored. Setting the run flag
(TRI) does not clear the registers.
Mode 0 operation is the same for Timer 0 as for Timer I.
Substitute TRO, TFO and INTO for the corresponding
Timer I signals in Figure 12. There are two different
GATE bits, one for Timer I (TMOD.7) and one for Timer
o (TMOD.3).
Model
Mode 0
Putting either Timer into mode 0 makes it look like an
8048 Timer, which is an 8-bit counter with a divide-by-32
prescaler. Figure 12. shows the mode operation as it
applies to Timer I.
°
In this mode, the timer register is configured as a 13-bit
register. As the count rolls over from all I s to all Os, it sets
the timer interrupt flag TFI. The counted input is enabled
to the Timer when TRI = I and either GATE = 0 or
INTI = 1. (Setting GATE =1 allows the Timer to be
controlled by external input INTI, to facilitate pulse
width measurements). TRI is a control bit in the Special
Function register TCON (Figure 1-10). GATE is in
TMOD.
Mode I is the same as Mode 0, except that the Timer
register is being run with all 16 bits.
Mode 2
Mode 2 configures the timer register as an 8-bit counter
(TLI) with automatic reload, as shown in Figure 14.
Overflow from TLI not only sets TFI, which is preset by
sofware. The reload leaves THI unchanged.
Mode 2 operation is the same for Timer/Counter O.
Mode 3
Timer I in Mode 3 simply holds its count. The effect is the
same as setting TRI = O.
Figure 12. Timer/Counter I Mode 0 : 13-bit Counter.
clf; 0
T1 Pin
I.2.14
____--'t c1f;
-
INTERRUPT
1
CONTROL
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 13. TCON : Timer/Counter Control Register.
(MSB)
TFI
(LSB)
TRI
TFO
TRO
lEI
ITI
lEO
ITO
II
Symbol
Position
TFI
TCON.7
TRI
TCON.6
TFO
TCON.5
TRO
TCON.4
Symbol
Position
lEI
TCON.3
ITI
TCON.2
lEO
TCON.I
ITO
TCON.O
Timer 0 in Mode 3 establishes TLO and THO as two
separate counters. The logic for Mode 3 on Timer 0 is
shown in Figure IS. TLO uses the Timer 0 control bits:
CIT, GATE, TRO, INTO, and TFO. THO is locked into a
timer function (counting machine cycles) and takes over
the use of TRI and TFI from Timer 1. Thus THO now
controls the "Timer I" interrupt.
Name and Significance
Timer I overflow Flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer 1 Run control bit. Set/cleared by software to turn timerlcounter
on/off.
Timer 0 overt1ow Flag. Set by hardware on timer/counter overflow.
Cleared by hardware when processor vectors to interrupt routine.
Timer 0 Run control bit. Set/cleared by software to turn timer/counter
on/otT.
Name and Significance
Interrupt I Edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt I Type control bit. Set/cleared by software to specify falling
edge/low level triggered external interrupts.
Interrupt 0 Edge flag. Set by hardware when external interrupt edge
detected. Cleared when interrupt processed.
Interrupt 0 Type control bit. Set/cleared by software to specify faIling
edge/low level triggered external interrupts.
Timer 2
Timer 2 is a 16-bit timer/counter which is present only in
the 80CS2, 83CIS4 and 83CIS4D. Like Timers 0 and I,
it can operate either as a timer or as an event counter.
Mode 3 is provided for applications requiring an extra
8-bit timer or counter. With Timer 0 in Mode 3, an 80CSI
can look like it has three timer/counters, and an 80CS2,
an 83CIS4 and 83CIS4D, like it has four. When Timer 0
is in Mode 3, Timer 1 can be turned on and off by
switching it out of and into its own Mode 3, or can still be
used by the serial port as a baud rate generator, or in fact,
in any application not requiring an interrupt.
MATRAMHS
Rev. E (14 Jan. 97)
1.2.IS
TEMIC
CS1 Family
Semiconductors
Figure 14. Timer/Counter 1 Mode 2: 8-bit Auto-reload.
cif = 0
INTERRUPT
____--->t- cif = 1
T1 Pin
TR1----\
GATE
Figure 15. Timer/Counter 0 Mode 3 : Two 8-bit Counters.
8--G----
1/12fOSC
1/12fOSC
INTERRUPT
TO Pin - - - - - - '
CONTROL
GATE
1/12fosc
R:
'~INTERRUPT
FNTROL
TR1 - - - - - - - '
1.2.16
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 16. T2CON : Timer/Counter 2 Control Register.
(MSB)
TF2
(LSB)
EXF2
I
RCLK
TCLK
I
EXEN2
I
TR2
Cm
I CP/RL2 I
Symbol
Position
Name and Significance
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not
be set when either RCLK = 1 or TCLK = I
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX and EXEN2 = I. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK
T2CON.5
Receive clock nag. When set, causes the serial port to use Timer 2 overflow pulses for its
receive clock in modes 1 and 3. RCLK:::: 0 causes Timer I overflow to be used for the receive
clock.
TCLK
T2CON.4
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for its
transmit clock in modes 1 and 3. TCLK = 0 causes Timer I overllows to be used for the
transmit clock.
EXEN2
T2CON.3
Timer 2 external enable tlag. When set, allows a capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 == 0
causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic I starts the timer.
Cm
T2CON.l
Timer or counter select. (Timer 2) 0 == Internal timer (OSCIl2) J == External event counter
(falling edge triggered).
CPIRL2
T2CON.O
CapturelReload flag. When set, captures will occur on negative transitions at T2EX if EXEN2
= I. When cleared, auto reloads will occur either with Timer 2 overflows or negative
transitions at T2EX when EXEN2 = I. When either RCLK = I or TCLK = I, this bit is ignored
and the timer is forced to auto-reload on Timer 2 overllow.
This is selected by bit Cff2 in the Special Function
Register T2CON (Figure 16), It has three operating
modes: "capture," "autoload" and "baud rate generator,"
which are selected by bits in T2CON as shown in Table 2,
Table 2. Timer 2 Operating Modes.
o
o
x
MATRAMHS
Rev. E (14 Jan. 97)
o
Hi-bit auto-reload
l6--bit capture
x
x
baud rate generator
o
(oft)
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then
Timer 2 is a 16-bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt If EXEN2 = I, then
Timer 2 still does the above, but with the added feature
that a I-to-O transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,
respectively, (RCAP2L and RCAP2H are new Special
Function Registers in the 80C52, 83CI54 and 83C154D.
In addition, the transition at T2EX causes bit EXF2 in
T2CON to be set, and EXF2, like TF2, can generate an
interrupt
The capture mode is illustrated in Figure 17.
1.2.17
II
TEMIC
cst Family
Semiconductors
Figure 17. Timer 2 in Capture Mode.
t
c!f2= 1
T2 Pin - - - - - - - ' -
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If EXEN2 =
0, then when Timer 2 rolls over it not only sets TF2 but
also causes the Timer 2 registers to be reloaded with the
l6-bit value in registers RCAP2L and RCAP2H, which
are preset by software. If EXEN2 = 1, then Timer 2 still
does the above, but with the added feature that a I-to-O
transition at external input T2EX will also trigger the
16-bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 18.
The baud rate generator mode is selected by RCLK = I
and/or TCLK = I. It will be described in conjunction with
the serial port.
1.2.18
1.7. Serial Interface (80CS1 and 80CS2 only)
The serial port is full duplex, meaning it can transmit and
receive simultaneously. It is also receive-buffered,
meaning it can commence reception of a second byte
before a previoulsy received byte has been read from the
receive register. (However, if the first byte still hasn't
been read by the time reception of the second byte is
complete, one of the bytes will be lost). The serial port
receive and transmit registers are both accessed at Special
Function Register SBUF. Writing to SBUF loads the
transmit register, and reading SBUF accesses a physically
separate receive register.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 18. Timer 2 in Auto-Reload Mode.
em 0
_____--'_i em = 1
T2 Pin
=
II
TIMER 2
INTERRUPT
T2EX PIN
EXEN2
The serial port can operate in 4 modes:
1.7.1. Multiprocessor Communications
Mode 0: Serial data enters and exits through RXD. TXD
outputs the shift clock. 8 bits are transmitted/received: 8
data bits (LSB first). The baud rate is fixed at III 2 the
oscillator frequency.
Modes 2 and 3 have a special provision for
multiprocessor, communications. In these modes, 9 data
bits are received. The 9th one goes into RB8. Then comes
a stop bit. The port can be programmed such that when the
stop bit is received, the serial port interrupt will be
activated only if RB8 = l. This feature is enabled by
setting bit SM2 in SCaN. A way to use this feature in
multiprocessor systems is as follows.
Mode 1 : 10 bits are transmitted (through TXD) or
received (through RXD) : a start bit (0), 8 data bits (LSB
first), and a stop bit (I). On receive, the stop bit goes into
RB8 in Special Function Register SCaN. The baud rate
is variable.
Mode 2 : II bits are transmitted (through TXD) or
received (through RXD) : a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit, and a stop bit (I). On
transmit, the 9th data bit (TB8 in SCaN) can be assigned
the value of 0 or I. Or, for example, the parity bit (P, in the
PSW) could be moved into TB8. On receive, the 9th data
bit goes into RB8 in Special Function register SCaN,
while the stop bit is ignored. The baud rate is
programmable to either 1/32 or 1/64 the oscillator
frequency.
When the master processor wants to transmit a block of
data to one of several slaves, it first sends out an address
byte which identifies the target slave. An address byte
differs from a data byte in that the 9th bit is I in an address
byte and 0 in a data byte. With SM2 = I, no slave will be
interrupt by a data byte. An address byte, however, will
interrupt all slaves, so that each slave can examine the
received byte and see if it is being addressed. The
addressed slave will clear its SM2 bit and prepare to
receive the data bytes that will be coming. The slaves that
weren't being addressed leaved their SM2s set and go on
about their business, ignoring the coming data bytes.
SM2 has no effect in Mode 0, and in Mode I can be used
to check the validity of the stop bit. In a Mode I reception,
if SM2 = 1, the receive interrupt will not be activated
unless a valid stop bit is received.
Mode 3 : 11 bits are transmitted (through TXD) or
received (through RXD) : a start bit (0), 8 data bits (LSB
first), a programmable 9th data bit and a stop bit (1). In
fact, Mode 3 is the same as Mode 2 in all respects except
the baud rate. The baud rate in Mode 3 is variable.
Serial port Control Register
In all four modes, transmission is initiated in Mode 0 by
the condition RI = 0 and REN = l. Reception is initiated
in Mde 0 by the condition RI = 0 and REN = 1. Reception
is initiated in the other modes by the incoming start bit if
REN= l.
The serial port control and status register is the Special
Function Register SCaN, shown in Figure 19. This
register contains not only the mode selection bits, but also
the 9th data bit for transmit and receive (TB8 and RB8),
and the serial port interrupts bits (TI and RI).
MATRAMHS
Rev. E (14 Jan. 97)
1.2.19
TEMIC
cst Family
Semiconductors
Figure 19. SCON : Serial Port Control Register.
(MSB)
(LSB)
SMO
SMI
SM2
REN
where SMO, SM I specify the serial port mode, as follows:
SMO
SMI
Mode
Description
Baud Rate
0
0
0
shift register
fOSC'/1 2
8bitUART
variable
0
0
• SM2
9bitUART
fosc./64 or
fosc./ 32
9bitUART
variable
enables the mUltiprocessor communication feature in
modes 2 and 3. In mode 2 or 3, if SM2 is set to I then RI
will not be activated if the received 9th data bit (RBS) is O.
In mode I, if SM2 = I then RI will not be activated if a
valid stop bit is not received. In mode 0, SM2 should be O.
• REN
• TB8
RBS
TI
RI
is the 9th data bit that will be transmitted in modes 2 and 3 .
Set or clear by software as desired.
• RBS
in modes 2 and 3, is the 9th data bit that was received. In
mode I, if SM2 = 0, RBS is the stop bit that was received.
• TI
is transmit interrupt flag. Set by hardware at the end of the
8th bit time in mode 0, or at the beginning of the stop bit in
the other modes, in any serial transmission. Must be
cleared by software.
In mode 0, RB8 is not used.
·Rl
is receive interrupt flag. Set by hardware at the end of the
8th bit time in mode 0, or halfway through the stop bit time
in the other modes, in any serial reception (except see
SM2). Must be cleared by software.
enables serial reception. Set by software to enable
reception. Clear by software to disable reception.
1.7.2. Baud Rates
The baud rate in Mode 0 is fixed:
M d 0B d R
_ Oscillator Frequency
o e
au
ate 12
The baud rate in Mode 2 depends on the value of bit
SMOD in Special Function Register PCON. If SMOD =
(which is its value on reset), the baud rate is 1/64 the
oscillator frequency. If SMOD I, the baud rate is 1/32
the oscillator frequency.
o
TB8
=
2SMOD x (Oscillator Frequency)
Mode 2 Baud Rate = ~
In the 80C51, the baud rates in Modes 1 and 3 are
determined by the Timer I overflow rate. In the 80C52,
83CI54 and 83C154D, these baud rates can be
determined by Timer I, or by Timer 2, or by both (one for
transmit and the other for receive).
The Timer I interrupt should be disabled in this
application. The Timer itself can be configured for either
"timer" or "counter" operation, and in any of its 3 running
modes. In the most typical applications, it is configured
for "timer" operation, in the auto-reload mode (high
nibble of TMOD = OOlOB). In that case, the baud rate is
given by the formula
Modes 1,3
2SMOD
Oscillator Frequency
Baud rate = 32 x 12 x [256 - (THI)l
One can achieve very low baud rates with Timer I by
leaving the Timer I interrupt enabled, and configuring the
Timer to run as a 16-bit timer (high nibble of TMOD =
OOOIB), and using the Timer 1 interrupt to do a 16-bit
software reload.
Figure 20. lists various commonly used baud rates and
how they can be obtained from Timer L
1.7.3. Using Timer 1 to Generate Baud Rates
When Timer I is used as the baud rate generator, the baud
rates in Modes 1 and 3 are determined by the Timer 1
overflow rate and the value of SMOD as follows:
Modes 1, 3
2SMOD
Baud rate = ---:l2- X (Timer 1 Overflow rate)
1.2.20
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 20. Timer 1 Generated Commonly Used Baud
Rates.
MODE 0 MAX : IMHZ
MODE 2 MAX: 375K
MODES 1.3 : 62.5K
19.2K
9.6K
4.SK
2.4K
UK
137.5
110
110
12MHZ
12MHZ
12 MHZ
11.059 MHZ
I 1.059 MHZ
I 1.059 MHZ
11.059 MHZ
11.059 MHZ
I 1.986 MHZ
6MHZ
12MHZ
1.7.4. Using Timer 2 to Generate Baud Rates
In the 80C52, 83Cl54 and 83C154D, Timer 2 is selected
as the baud rate generator by setting TCLK and/or RCLK
in T2CON (Figure 16.). Note then the baud rates for
transmit and receive can be simultaneously different.
Setting RCLK and/or TCLK puts Timer 2 into its baud
rate generator mode, as shown in Figure 21.
FFH
FDH
FDH
FAH
F4H
ESH
IDH
72H
FEEBH
0
0
0
0
0
0
Figure 21. Timer 2 in Baud Rate Generator Mode.
TIMER 1
OVERFLOW
NOTE
~
OSC
OSC.FREQ IS DIVIDED BY2. NOT 12
+2
cm
_____--'_t cm
T2 PIN
=
0
,-----,,------,
= 1
RXCLOCK
TX CLOCK
"TIMER 'Z
INTERRUPT
T2EX PIN
EXEN2
L
NOTE AVAILABI L1TY OF ADDITIONNAL EXTERNAL INTERRUPT
The baud rate generator mode is similar to the auto-reload
mode, in that a rollower in TH2 causes the Timer 2
registers to be reloaded with the 16-bit value in registes
RCAP2H and RCAP2L, which are preset by software.
Now, the baud rates in Modes I and 3 are determined by
Timer 2's overflow rate as follows:
Modes 1, 3 Baud Rate
MATRAMHS
Rev. E (14 Jan. 97)
=
Timer 2 O~~rflow rate
The Timer can be configured for either "timer" or
"counter" operation. In the most typical applications, it is
configured for "timer" operation (CIT2 = 0). "Timer"
operation is a little different for Timer 2 when it's being
used as a baud rate generator. Normally as a timer it would
increment every machine cycle (thus at 1112 the oscillator
frequency). As a baud rate generator, however, it
increment every state time (thus at 112 the oscillator
frequency). In that case the baud rate is given by the
formula
1.2.21
II
TEMIC
cst Family
Modes 1,3
Baud rate
32
X
Oscillator Frequency
[65536-(RCAP2H, RCAP2L)]
where (RCAP2H, RCAP2L) is the content of RCAP2H
and RCAP2L taken as a 16-bit unsigned integer,
Timer 2 as a baud rate generator is shown in Figure 21.
This Figure is valid only if RCLK + TCLK = I in T2CON,
Note that a rollover in TH2 does not set TF2, and will not
generate an interrupt Therefore, the Timer 2 interrupt
does not have to be disabled when Timer 2 is in the baud
rate generator mode, Note too, that if EXEN2 is set, a
I-to-O transition in T2EX will set EXF2 but will not cause
a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus
when Timer 2 is in use as a baud rate generator, T2EX can
be used as an extra external interrupt, if desired.
It should be noted that when Timer 2 is running (TR2 =
I) in "timer" function in the baud rate generator mode,
one should not try to read or write TH2 or TL2. Under
these conditions the Timer is being incremented every
state time, and the results of a read or write may not be
accurate. The RCAP registers may be read, but shouldn't
be written to, because a write might overlap a reload and
cause write andlor reload errors. Turn the Timer off (clear
TR2) before accessing the Timer 2 or RCAP registers, in
this case.
More About Mode 0
Serial data enters and exits through RXD. TXD outputs
the shift clock. 8 bits are transmittedlreceived: 8 data bits
(LSB first). The baud rate is fixed at 1112 the oscillator
frequency.
Figure 22. shows a simplified functional diagram of the
serial port in mode 0, and associated timing.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal at S6P2 also loads a I into the 9th bit position of the
transmit shift register and tells the TX Control block to
commence a transmission. The internal timing is such
that one full machine cycle will elapse between "write to
SBUF", and activation of SEND.
SEND enables the output of the shift register to the
alternate output function line of P3.0, and also enables
SHIFT CLOCK to the alternate output function line of
P3.1. SHIFT CLOCK is low during S3, S4, and S5 of
every machine cycle, and high during S6, S I and S2. At
S6P2 of every machine cycle in which SEND is active,
the contents of the transmit shift register are shifted to the
right one position.
1.2.22
Semiconductors
As data bits shift out to the right, zeros come in from the
left When the MSB of the data byte is at the output
position of the shift register, then the I that was initially
loaded into the 9th position, is just to the left of the MSB,
and all positions to the left of that contain zeros. This
condition flags the TX Control block to do one last shift
and then deactivate SEND and set TI. Both of these
actions occur at SIPI of the 10th machine cycle after
"write to SBUF."
Reception is initiated by the condition REN = I and RI =
O. At S6P2 of the next machine cycle, the RX Control unit
writes the bits 11111110 to the receive shift register, and
in the next clock phase activates RECEIVE.
RECEIVE enables SHIFT CLOCK to the alternate output
function line of P3.1. Shift CLOCK makes transitions at
S3PI and S6Pl of every machine cycle. At S6P2 of every
cycle in which RECEIVE is active, the contents of the
receive shift register are shifted to the left one position.
The value that comes in from the right is the value that
was sampled at the P3.0 pin at S5P2 of the same machine
cycle.
As data bits come in from the right, I s shift out to the left.
When the 0 that was initially loaded into the rightmost
position arrives at the leftmost position in the shift and
load SBUF. At SIPI of the 10th machine cycle after the
write to SCON that cleared RI, RECEIVE is cleared and
RI is set
More About Mode 1
Ten bits are transmitted (through TXD), or received
(through RXD) : a start bit (0), 8 data bits (LSB first), and
a stop bit (l). On receive, the stop bit goes into RB8 in
SCON. In the 80C51 the baud rate is determined by the
Timer I overflow rate. In the 80C52, 83CI54 and
83CI54D it is determined either by the Timer I overflow
rate, or the Timer 2 overflow rate, or both (one for
transmit and the other for receive).
Figure 23. shows a simplified functional diagram of the
serial port in Mode I, and associated timings for transmit
and receive.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads a I into the 9th bit position of the
transmit shift register and flags the TX Control unit that
a transmission is requested. Transmission actually
commences at SIPl of the machine cycle following the
next rollower in the divide-by-16 counter. (Thus, the bit
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
Semiconductors
times are synchronized to the divide-by-16 counter, not to
the "write to SBUF" signal).
The transmission begins with activation of SEND, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TXD. The fisrt shift pulse occurs one bit
time after that.
cst Family
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever baud rate has been established. When a
transition is detected, the divide-by-16 counter is
immediately reset, and IFFH is written into the input shift
register. Resetting the divide-by-16 counter aligns its
rollovers with the boundaries of the incoming bit times.
As data bits shift out to the right, zeros are clocked in from
the left. When the MSB of the data byte is at the output
position of the shift register, then the I that was initially
loaded into the 9th position is just to the left of the MSB,
and all positions to the left of that contain zeroes. This
condition flags the TX Control unit to do one last shift and
then deactivate SEND and set TI. This occurs at the 10th
divide-by-16 rollower after "write to SBUF".
MATRAMHS
Rev. E (14 Jan. 97)
1.2.23
II
TEMIC
cst Family
Semiconductors
Figure 22. Serial Port Mode O.
WRITE
TO
SBUF
-----r---~~~~~--~~~----l_.-------~--~} -_ _
RXD
P3.0ALT
OUTPUT
FUNCTION
TXCONTROL
SERIAL
PORT
INTERRUPT
L-________-+I
TXD
P3.1 ALT
OUTPUT
FUNCTION
RX CLOCK
RECEIVE
RXCONTROL
SHIFT
REN
~----~START
RI----L--'
L-----~~-T_r~~~~
RXD
P3.0ALT
INPUT
FUNCTION
S4S5S6~1 S2S3S4S5S~1 525354555*1 S2S3S4S5S4s, S2S3S4S5S<$1 S2S3S4S5S~1 S2S3S4S5S~1 S2S3S4S5S6~1 S2S3S4S5S6~1 S2S3S4S5S~1 S2S3S4S5seisl
ALE
:::-'£
SEND
WRITE TO SBUF
S6P2
I
L-
SHIFT
RDX (DATA OUT)
}'M_n
TXD (SHIFT CLOCK)
TI
--Il
WRITE TO SCON (CLEAR RI)
Ail
RECEIVE
SHIFT
RDX (DATA IN)
1.2.24
r----
}~a~
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 23. Serial Port Mode 1. TCLK, RCLK, and Timer 2 are present in the SOC32/S0C52, SOC154/S3C154
and S3C154D.
TIMER 1
OVERFLOW
TIMER 2
OVERFLOW
TO
WRITE
SBUF
II
--~r-;:::::~~i:::1--""":~:""---'-----f-'"
TXD
·0·
TCLK·-
RCLK
----f1
WRITE TO SBUF
,CLOCK.
•
,
'!
~=======lc.
TRANSMIT
STOP BIT
TI
START BIT
RX CLOCK
MATRAMHS
Rev. E (14 Jan. 97)
• 16 RESET
1.2.25
cst Family
The 16 states of the counter divide each bit time into
16ths. At the 7th, 8th, and 9th counter states of each bit
time, the bit detector samples the value of RXD. The
value accepted is the value that was seen in at least 2 of
the 3 samples. This is done for noise rejection. If the value
accepted during the first bit time is not 0, the receive
circuits are reset and the unit goes back to looking for
another I-to-O transition. This is to provide rejection of
false start bits. If the start bit proves valid, it is shifted into
the input shift register, and reception of the rest of the
frame will proceed.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the
shift register, (which in mode 1 is a 9-bit register), it flags
the RX Control block to do one last shift, load SBUFF and
RBS, and set RI. Will be generated if, and only if, the
following conditions are met at the time the final shift
pulse is generated.
1) RI = 0, and
2) Either SM2
=0, or the received stop bit = 1
If either of these two confitions is not met, the received
frame is irretrievably lost. If both conditions are met, the
stop bit goes into RBS, the 8 data bits go into SBUF, and
RI is activated. At this time, whether the above conditions
are met or not, the unit goes back to looking for a I-to-O
transition in RXD.
More About Modes 2 and 3
Eleven bits are transmitted (through TXD), or received
(through RXD) : a start bit (0), S data bits (LSB first), a
programmable 9th data bit, and a stop bit (l). On transmit,
the 9th data bit goes into RBS is SCaN. The baud rate is
programmable to either 1132 or 1164 the oscillator
frequency in mode 2. Mode 3 may have a variable baud
rate generated from either Timer 1 or 2 depending on the
state of TCLK and RCLK.
Figures 1-24 A and B show a functional diagram of the
serial port in modes 2 and 3. The receive portion is exactly
the same as in mode I. The transmit portion differs from
mode I only in the 9th bit of the transmit shift register.
Transmission is initiated by any instruction that uses
SBUF as a destination register. The "write to SBUF"
signal also loads TBS into the 9th bit position of the
transmit shift register and flags the TX Control unit that
a transmission is requested. Transmission commences at
S IPI of the machine cycle following the next rollover in
the divide-by-16 counter. (Thus, the bit times are
synchronized to the divide-by-16 counter, not to the
"write to SBUF" signa1.)
1.2.26
TEMIC
Semiconductors
The transmission begins with activation of SEND, which
puts the start bit at TXD. One bit time later, DATA is
activated, which enables the output bit of the transmit
shift register to TXD. The first shift pulse occurs one bit
time after that. The first shift clocks a 1 (the stop bit) into
the 9th bit position of the shift register. Thereafter, only
zeroes are clocked in. Thus, as data bits shift out to the
right, zeroes are clocked in from the left. When TBS is at
the output position of the shift register, then the stop bit
is just to the left of TBS, and all positions to the left of that
contain zeroes. This condition flags the TX Control unit
to do one last shift and then deactivate SEND and set TI.
This occurs at the 11th divide-by-16 rollover after "write
to SBUF".
Reception is initiated by a detected I-to-O transition at
RXD. For this purpose RXD is sampled at a rate of 16
times whatever is detected, the divide-by-16 counter is
immediately reset, and lFFH is written to the input shift
register.
At the 7th, 8th and 9th counter states of each bit time, the
bit detector samples the value of RXD. The value
accepted is the value that was seen in at least 2 of the 3
samples. If the value accepted during the first bit time is
not 0, the receive circuits are reset and the unit goes back
to looking for another l-to-O transition. If the start bit
proves valid, it is shifted into the input shift register, and
reception of the rest of the frame will proceed.
As data bits come in from the right, 1s shift out to the left.
When the start bit arrives at the leftmost position in the
shift register (which in modes 2 and 3 is a 9-bit register),
it flags the RX Control block to do one last shift, load
SBUF and RBS, and set RI. The signal to load SBUF and
RBS, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift
pulse is generated:
I) RI = 0, and
2) Either SM2 = 0 or the received 9th data bit = I
If either of these conditions is not met, the received frame
is irretrievably lost, and RI is not set. If both conditions
are met, the received 9th data bit goes into RBS, and the
first S data bits go into SBUF. One bit time later, whether
the above conditions were met or not, the unit goes back
to looking for a I-to-O transition at the RXD input.
Note that the value of the received stop bit is irrelevant to
SBUF, RBS, or RI.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 24. Serial Port Mode 2.
TXD
PHASE 2 CLOCK
(1/210sc)
MODE 2
(SMOD IS PCON.?)
RXD
.CLOCK.
TX
~L_ _...Jl_ _--,,_ __
n~L____L-__-A____~__~
---II WRITE TO SBUF
------CSEND
DATA
SHIFT
{SlP1
TRANSMIT
r-____________________________
~
:D~X====~~~~::D:O==r-c=====
____________
================================~r----START BIT
TI
STOP BITGEN
RECEIVE
RI
MATRAMHS
Rev. E (14 Jan. 97)
1.2.27
II
TEMIC
CSt Family
Semiconductors
Figure 25. Serial Port Mode 3. TCLK, RCLK and Timer 2 are present in the 80C32/80C52, 80C154/83C154 and
in the 83C154D.
TIMER 1
OVERFLOW
TIMER 2
OVERFLOW
TO
WRITE-----r-~=i5t~:r--~~~--_,r_------_f
SBUF
TXD
"0"
TCLK .-
RXD
TX
_'LC_L_O_C_K~I~__-A____- L____~____~ftL-__-L____-L____JL____L-__--'
....11 WRITE TO SBUF
TRANSMIT
=T:I:::;::ST:AR::T:B:IT::::~____________________________________________~r----STOP BIT GEN
---'r-----
' -__________________________________________
+
~RI
1.2.28
16 RESET
__________________________________________________~~
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
1.8. Interrupts
The 80C51 provides 5 interrupt sources. The 80C52
83C154 and 83CI54D provide 6. Theses are shown in
Figure 25.
Figure 26. TEMIC CS1 Interrupt Sources.
The Serial Port Interrupt is generated by the logical OR
of RI and TI. Neither of these flags is cleared by hardware
when the service routine is vectored to. In fact, the service
routine will normally have to determine whether it was RI
or TI that generated the interrupt, and the bit will have to
be cleared in software.
TFO------------
INTERRUPT
SOURCES
TFL1_ _ _ _ _ _ _ _ _ _ __
TI~
RI--L/------~
TF2~
EXF2--L/
(80C52, 83C154
and 83C154D only)
The Timer 0 and Timer I Interrupts are generated by TFO
and TFI, which are set by a rollover in their respective
timer/counter registers (except see Section 1.6 for Timer
o in mode 3). When a timer interrupt is generated, the flag
that generated it is cleared by the on-chip hardware when
the service routine is vectored to.
-
In the 80C52, 83Cl54 and 83C154D, the Timer 2
Interrupt is generated by the logical OR of TF2 and EXF2.
Neither of these flags is cleared by hardware when the
service routine is vectored to. In fact, the service routine
may have to determine whether it was TF2 or EXF2 that
generated the interrupt, and the bit will have to be cleared
in software.
All of the bits that generate interrupts can be set or cleared
by sofware, with the same result as though it had been set
or cleared by hardware. That is, interrupts can be
generated or pending interrupts can be canceled in
sofware.
Each of these interrupt sources can be individually
enabled or disabled by setting or clearing a bit in Special
Function Register IE (Figure 26.). Note that IE contains
also a global disable bit, EA, which disables all interrupts
at once.
The external interrupts INTO and INTI can each be either
level-activated or transition-activated, depending on bits
ITO and IT! in Register TCON. The flags that actually
generate these interrupts are bits lEO and lEI in TCON.
When an external interrupt is generated, the flag that
generated it is cleared by the hardware when the service
routine is vectored to only if the interrupt was
transition-activated. If the interrupt was level-activated,
then the external requesting source is what controls the
request flag, rather than the on-chip hardware.
MATRAMHS
Rev. E (14 Jan. 97)
1.2.29
II
TEMIC
cst Family
Semiconductors
Figure 27. IE : Interrupt Enable Register.
(LSB)
(MSB)
EA
x
ET2
ES
ETl
EXI
ETO
EXO
Symbol
Position
EA
IE.7
disables all interrupts. If EA = O. no interrupt will be acknowledged. If EA = I. each interrupt
source is individually enabled or disabled by setting or clearing its enables bit.
IE.6
reserved.
IE.5
enables or disables the Timer 2 overflow or capture interrupt. If ET2 = 0, the Timer 2 interrupt is
disabled.
ET2
Fuuction
ES
IE.4
enables or disables the Serial Port interrupt is disabled.
ETl
IE.3
enables or disables the Timer I Overtlow interrupt. If ETl = 0, the Timer I interrupt is disabled.
EXI
IE.2
enables or disables External Interrupt I. If EX I = 0, External interrupt I is disabled.
ETO
IE. I
enables or disables the Timer 0 Overtlow interrupt. If ETO = 0, the Timer 0 interrupt is disabled.
EXO
IE.O
enables or disables External Interrupt O. If EXO = 0, External Interrupt 0 is disabled.
Priority Level Structure
Each interrupt source can also be individually
programmed to one of two priority levels by setting or
clearing a bit in Special Function Register IP (Figure 27.).
A low-priority interrupt can itself be interrupted by a
high-priority interrupt, but not by another low-priority
interrupt. A high-priority interrupt can't be interrupted by
any other interrupt source.
Figure 28. IP : Interrupt Priority Register.
(MSB)
(LSB)
X
X
Symbol
1.2.30
PT2
Position
PS
PTl
PXI
PTO
PXO
Function
!P.7
reserved
IP.6
reserved
PT2
IP.5
defines the Timer 2 interrupt priority level. PT2 = I programs it do the higher priority level.
PS
IP.4
defines the Serial Port Interrupt priority level. PS = I programs it to the higher priority level.
defines the Timer 1 interrupt priority level. PT 1 = 1 programs it to the higher priority leve1.
PTl
1P.3
PXl
IP.2
defines the external interrupt I priority level. PXI = I programs it to the higher priority level.
PTO
IP.1
defines the Timer 0 interrupt priority level. PTO = I programs it to the higher priority level.
PXO
IP.O
defines the External Interrupt 0 priority level. PXO = I programs it to the higher priority level.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
If two requests of different priority levels are received
simultaneoulsy, the request of higher priority level is
serviced. If requests of the same priority level are
received simultaneously, an internal polling sequence
determine which request is serviced. Thus within each
priority level is a second priority structure determined by
the polling sequence, as follows:
l.
2.
3.
4.
5.
6.
II
SOURCE
PRIORITY WITHIN LEVEL
lEO
(highest)
TFO
lEI
TFI
RI +TI
TF2+ EXF2
(lowest)
Note that the "priority within level" structure is only used
to resolve simultaneous requests of the same priority
level.
How Interrupts Are Handled
The interrupt flags are sampled at SSP2 of every machine
cycle. The samples are polled during the following
machine cycle. If one of the flags was in a set condition
at SSP2 of the preceding cycle, the polling cycle will find
it and the interrupt system will generate an LCALL to the
appropriate
service
routine,
provided
this
hardware-generated LCALL is not clocked by any of the
following conditions:
1. An interrupt of equal or higher priority level is already
in progress.
2. The current (polling) cycle is not the final cycle in the
execution of the instruction in progress.
3. The instruction in progress is RETI or any access to the
IE or IP registers.
The polling cycle is repeated with each machine cycle,
and the values polled are the values that were present at
S5P2 of the previous machine cycle. Note then that if an
interrupt flag is active but not being responded to for one
of the above conditions, if the flag is not still active when
the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the facts that the
interrupt flag was once active but not serviced is not
remembered. Every polling cycle is new.
The polling cycle/LCALL sequence is illustrated in
Figure 28.
Note that if an interrupt of higher priority level goes
active prior to S5P2 of the machine cycle labeled C3 in
Figure 28., then in accordance with the above rules it will
be vectored to during C5 and C6, without any instruction
of the lower priority routine having been executed.
Figure 29. Interrupt response Timing Diagram.
-------·--··-·-·---Cl---...I~.---C2-2-------.....
1.>----C3---~.+OI.>----C4---~.141
.. - - - C 5 - · · · · · · · .. ···
15SP2156
I
--LJLf1SlL___----1'f;~-------'---------1'O.~-------L---____1l_
.. - - - - - ' - - - - - - -
M
INTERRUPTS
GOES
ACTIVE
INTERRUPTS
LATCHED
MATRAMHS
Rev. E (14 Jan. 97)
INTERRUPTS
ARE POLLED
LONG CALL TO
INTERRUPT
VECTOR ADDRESS
INTERRUPT ROUTI NE
This is the fastest possible response when C2 is the final cycle of
an instruction other than RETI or an access to IE or IP
I.2.31
TEMIC
cst Family
Semiconductors
Thus the processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the
appropriate servicing routine. In some cases it also clears
the flag that generated the interrupt, and in other cases it
doesn't. It never clears the Serial Port or Timers 2 flags.
This has to be done in the user's software. It clears an
external interrupt flag (lEO or lEI) only if it was
transition-activated. The hardware-generated LCALL
pushes the contents of the Program Counter onto the stack
(but it does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to, as shown below.
lEO
TFO
lEi
TFI
Rl+Tl
TF2+ EXF2
0003H
OOOBH
0013H
OOIBH
0023H
002BH
Execution proceeds from that location until the RET!
instruction is encountered. The RET! instruction informs
the processor that this interrupt routine is no longer in
progress, then pops the top two bytes from the stack and
reloads the Program Counter. Execution of the
interrupted program continues from where it left off.
Note that a simple RET instruction would also have
returned execution to the interrupted program, but it
would have left the interrupt control system thinking an
interrupt was still in progress.
External Interrupts
The external sources can be programmed to be
level-activated or transition-activated by setting or
clearing bit ITl or ITO in Register TCON. If ITx = 0,
external interrupt x is triggered by a detected low at the
INTx pin. If ITx = I, external interrupt x is
edge-triggered. In this mode if successive samples of the
INTx pin show a high in one cycle and a low in the next
cycle, interrupt request flag lEx in TCON is set. Flag bit
lEx then requests the interrupt.
1.2.32
Since the external interrupt pins are sampled once each
machine cycle, an input high or low should hold for at
least 12 osciJJator periods to ensure sampling. If the
external interrupt is transition-activated, the external
source has to hold the request pin high for at least one
cycle, and then hold it low for at least one cycle to ensure
that the transition is seen so that interrupt request flag lEx
will be set. lEx wiJJ be automatically cleared by the CPU
when the service routine is called.
If the external interrupt is level-activated, the external
source has to hold the request active until the requested
interrupt is actually generated. Then it has to deactivate
the request before the interrupt service routine is
completed, or else another interrupt will be generated.
Response Time
The INTO and INTl levels are inverted and latched into
lEO and lEI and S5P2 of every machine cycle. The values
are not actually polled by the circuitry until the next
machine cycle. If a request is active and conditions are
right for it to be acknowledged, a hardware subroutine
call to the requested service routine wiJJ be the next
instruction to be executed. The call itself takes two
cycles. Thus, a minimum of three complete machine
cycles elapse between activation of an external interrupt
request and the beginning of execution of the service
routine. Figure 28. shows interrupt response timings.
A longer response time would result if the request is
blocked by one of the 3 previously listed conditions. If an
interrupt of equal or higher priority level is already in
progress, the additional wait time obviously depends on
the nature of the other interrupt's service routine. If the
instruction in progress is not in its final cycle, the
additional wait time cannot be more than 3 cycles, since
the longest instructions (MUL and DIY) are only 4 cycles
long, and if the instruction in progress is RET! or an
access to IE or IP, the additional wait time cannot be more
than 5 cycles (a maximum of one more cycle to complete
the instruction in progress, plus 4 cycles to complete the
next instruction if the instruction is MUL or DIY).
Thus, in a single-interrupt system, the response time is
always more than 3 cycles and less than 8 cycles.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
1.9. Single Step Operation
The 80C5l interrupt structure allows single-step
execution with very little software overhead. As
previously noted, an interrupt request will not be
responded to while an interrupt of equal priority level is
still in progress, nor will it be responded to after RETI
until at least one other instruction has been executed.
Thus, once an interrupt routine has been entered, it cannot
be re-entered until at least once instruction of the
interrupted program is executed. One way to use this
feature for single-step operation is to program one of the
external interrupts (say, INTO) to be level-activated. The
service routine for the interrupt will terminate with the
following code:
JNB
JB
WAIT HERE TILL INTO
GOES HIGH
NOW WAIT HERE TILL
IT GOES LOW
GO BACK AND EXECUTE
ONE INSTRUCTION
P3.2,$
P3.2,$
RETI
Now, if the INTO pin, which is also the P3.2 pin, is hold
normally low, the CPU will go right into the External
interrupt 0 routine and stay there until INTO is pulsed
(from low to high to low). Then it will execute RETI, go
back to the task program, execute one instruction, and
immediately re-enter the External Interrupt 0 routine to
await the next pUlsing of P3.2. One step of the task
program is executed each time P3.2 is pulsed.
1.10. Reset
The reset input is the RST pin, which is the input to a
Schmitt Trigger.
Figure 30. Power on Reset Circuit.
A reset accomplished by holding the RST pin high for at
least two machine cycles (24 oscillator periods), while the
oscillator is running. The CPU responds by executing an
internal reset. It also configures the ALE and PSEN pins
as inputs. (They are quasi-bidirectional). The internal
reset is executed during the second cycle in which RST
is high and is repeated every cycle until RST goes low. It
leaves the internal registers as follows:
REGISTER
PC
ACC
B
PSW
SP
DPTR
PO-P3
IP (80C51)
IP (80C52, 83Cl54 and 83C154D)
IE (80C51)
IE (80C52, 83Cl54 and 83C154D)
TMOD
TCON
T2CON (80C52, 83C154 and 83C154D)
THO
CONTENT
OOOOH
OOH
OOH
OOH
07H
OOOOH
OFFH
XXXOOOOOB
XXOOOOOOB
OXXOOOOOB
OXOOOOOOB
OOH
OOH
OOH
OOH
OOH
TLO
OOH
THI
OOH
TLI
OOH
TH2
OOH
TL2
OOH
RCAP2H (80C52 83C154 and 83C154D)
OOH
RCAP2L (80C52, 83C154 and 83C154D)
OOH
SCON
Indeterminate
SBUF
OOH
IOCON
OXXXOOOOB
PCON (80CSI and 80CS2)
OOOXOOOOB
PCON (83C154 and 83C154D)
The internal RAM is not affected by reset. When VCC is
turned on, the RAM content is indeterminate unless the
part is returning from a reduced power mode of operation.
vee
+
1fd_r-
vee
80e51
RST
+
MATRAMHS
Rev. E (14 Jan. 97)
VSS
1.2.33
II
TEMIC
cst Family
Semiconductors
Power-on reset
Idle Mode
An automatic reset can be obtained when VCC is turned
on by connecting the RST pin to VCC through a I Ilf
capacitor providing the VCC risetime does not exceed a
millisecond and the oscillator start-up time does not
exceed 10 milli-seconds. This power-on reset circuit is
shown in Figure 1-29. When power comes on, the current
drawn by RST commences to charge the capacitor. The
voltage at RST is the difference between VCC and the
capacitor voltage, and decreases from VCC as the cap
charges. The larger the capacitor, the more slowly VRST
decreases. VRST must remain above the lower threshold
of the Schmitt Trigger long enough to effect a complete
reset. The time required is the oscillator start -up time,
plus 2 machine cycles.
An instruction that sets PCON.O causes that to be the last
instruction executed before going into the Idle mode. In
the Idle mode, the internal clock signal is gated off to the
CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data
during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at
logic high levels.
1.11. Power-Saving Modes of Operation
For applications where power consumption is a critical
factor, the TEMIC C5l parts provide two power mode:
power-down and idle mode. The first one reduces the
consumption up to few microamperes and the second one
divides the consumption roughly by 25 %. Both of the
modes are controlled by software via the PCON register.
In Power-Down mode (PD = 1, PCON = 87H => XXXX
XXIX) the oscillator is frozen. In idle mode (IDL = 1,
PCON = 87H => XXXX XXOI). The oscillator
continues to run and the interrupt, serial port, and timer
blocks continue to be clocked but the clock signal is gated
off the CPU. The activities of the CPU no longer exists
unless waiting for an interrupt request. Both Power-Down
and Idle mode are explained below. Further function
concerning the TEMIC C154 parts will be explain in the
next chapter.
There are two ways to terminate the Idle. Activation of
any enabled interrupt will cause PCON.O to be cleared by
hardware, terminating the Idle mode. The interrupt will
be serviced, and following RET! the next instruction to be
executed will be the one following the instruction that put
the device into idle.
The flag bits OFO and OF! can be used to give and
indication if an interrupt occured during normal operation
or during and Idle. For example, an instruction that
activates Idle can also set one or both flag bits. When Idle
is terminated by an interrupt, the interrupt service routine
can examine the flag bits.
The over way of terminating the Idle mode is with a
hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two
machine cycles (24 oscillator periods) to complete the
reset.
Figure 31. PCON : Power Control Register.
(LSB)
(MSB)
SMOD
GFI
GFO
PD
IDL
Symbol
Position
Name and Fnnction
SMOD
PCON.7
Double Baud rate bit. When set to a I, the baud rate is doubled when the serial port is being used in
either modes 1,2 or 3.
PCON.6
(Reserved)
PCON.5
(Reserved)
PCON.4
(Reserved)
GFI
PCON.3
General-purpose flag bit.
GFO
PCON.2
General-purpose flag bit.
PD
PCON.I
Power Down bit. Setting this bit activates power down operation.
IDL
PCON.O
Idle mode bit. Setting this bit activates idle mode operation.
If I s are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is (OXXXOOOO).
I.2.34
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Power Down Mode
An instruction that sets peON. I causes that to be the last
instruction executed before going into the Power Down
mode. In the Power Down mode, the on-chip oscillator is
stopped. With the clock frozen, all functions are stopped,
but the on-chip RAM and Special Function Registers are
held. The port pins output the values held by their
respective SFRs. ALE and PSEN output lows.
II
Figure 32. Idle and Power Down Hardware.
XTAL2
XTAL 1
1----1.----t:>
INTERRUPT,
SERIAL PORT,
TIMER BLOCKS
CPU
The only exit from Power Down is a hardware reset. Reset
redefines all the SFRs, but does not change the on-chip
RAM.
In the Power down mode of operation, vee can be
reduced to minimize power consumption. eare must be
taken, however, to ensure that vee is not reduced before
the Power Down mode is invoken, and that vee is
restored to its normal operating level, before the Power
Down mode is terminated. The reset that terminates
Power Down also frees the oscillator. The reset should not
be activated before vee is restored to its normal
operating level, and must be held active long enough to
allow the oscillator to restart and stabilize (normally less
than 10 msec).
MATRAMHS
Rev. E (14 Jan. 97)
I.2.35
TEMIC
cst Family
Semiconductors
This table shows the state of ports during idle and power-down modes.
1.12. More about the On-chip Oscillator
The on-chip oscillator circuitry for 80CS1's family,
shown in Figure 32., consists of a single stage linear
inventer for use as a crystal-controlled, positive reactance
oscillator.
The on-chip oscillator is able to run with a crystal or with
ceramic resonnator. The Figure 33. shows the schematic
to work which a crystal and a ceramic resonnator working
on a fundamental mode.
Figure 33. On-chip oscillator Circuit.
VCC
TO INTERNAL
TIMINGCKTS
D1
R1
XTAl2
XTAL1
400Q
D2
PD----------~~----~
1.2.36
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
The TEMIC-5l parts can by controlled by an external
clock. In this case the external clock signal is connected
directly on XTALI input and XTAL2 in left floating
(Figure 35.).
Figure 34. Fundamental Resonance.
crystal or
ceramic resonnateur
+------1
Df-------.,
The Figure 34. shows the use of a crystal working on an
overtone 3 resonance.
An overtone 3 crystal doesn't work on its fundamental
resonance but on its third overtone. So it's necessary to
catch in its fundamental frequency. The trap consists of
the inductor L and the capacitance C. The trap frequency
is the running frequency of the crystal divides by 3. An
external resistor of I MQ is connected on the both side of
the crystal to decrease the gain on the amplifier. Cause the
equivalent inductor for a overtone 3 crystal is more larger
than a fundamental crystal, the oscillator needs less
energy. Without external resistor the level on pin XTALI
isn't enough to control the internal clock circuitry.
Figure 35. Overtone 3 Resonance.
.---t-------i
D1-------1
1 M(l
overtone 3
f _~ _ _1_
T- 3 -6n ..JT]5
MATRAMHS
Rev. E (14 Jan. 97)
1.13. Internal Timing
Figure 36. through Figure 39. show when the various
strobe and port signals are clocked internally. The figures
do not show rise and fall times of the signals, nor do they
show propagation delays between the XTAL2 signal and
events at other pins.
Figure 36. Driving the CS1 parts with an external
clock source.
80C51
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
><)-----1 XTAL1
r
CMOS GATE
Rise and gall times are dependent on the external loading
that each pin must drive. They are often taken to be
something in the neighborhood of 10 nsec, measured
between 0.8 V and 2.0 V.
Propagation delays are different for different pins. For a
given pin they vary with pin loading, temperature, VCC,
and manufacturing lot. If the XTAL2 waveform is taken
as the timing reference, prop delays may vary from 25 to
125 nsec .
The AC Timings section of the data sheets do not
reference any timing to the XTAL2 waveform. Rather,
they relate the critical edges of control and input signals
to each other. The timing published in the data sheets
include the effects of propagation delays under the
specified test conditions.
I.2.37
II
cst Family
1.14. CSI Pin Description
VCC : Supply voltage.
VSS : Circuit ground potential.
Port 0 : Port 0 is an 8-bit open drain bidirectional I/O
Port. As an open drain output port it can sink 8 LS TTL
loads. Port 0 pins that have I s written to them float, and
in that state will functions as high-impedance inputs. Port
o is also the multiplexed low-order address and data bus
during accesses to external memory. In this application it
uses strong internal pullups when emitting I s. Port 0 also
emits code bytes during program verification. In that
application, external pullups are required.
Port 1 : Port I is an 8-bit bidirectional I/O port with
internal pullups. The port I output buffers can sink/source
4 LS TTL loads. Port I pins that have Is written to them
are pulled high by the internal pullups, and in that state
can be used as inputs. As inputs, Port I pins that are
externally being pulled low will source current (IlL, on
the data sheet) because of the internal pullups.
In the 80C52, 83Cl54 and 83CI54D pins PI.O and Pl.l
also serve the alternate functions of T2 and T2EX. T2 is
the Timer 2 external input. T2EX is the input through
which a Timer 2 "capture" is triggered.
Port 2 : Port 2 is an 8-bit bidirectional I/O port with
internal pull ups. The port 2 output buffers can sink/source
4 LS TTL loads. Port 2 emits the high-order addres byte
during accesses to external memory that use 16-bit
addresses. In this application it uses the strong internal
pullups when emitting Is.
Port 3 : Port 3 is an 8-bit bidirectional I/O port with
internal pullups. It also serves the functions of various
special features of the TEMIC-C51 Family, as listed
below:
1.2.38
TEMIC
Semiconductors
PORT PIN
ALTERNATE FUNCTION
P3.0
RXD (serial input port)
P3.1
TXD (serial output port)
P3.2
INTO (external interrupt 0)
P3.3
INTI (external interrupt I)
P3.4
TO (Timer 0 external input)
P3.5
Tl (Timer I external input)
P3.6
WR (external data memory write strobe)
P3.7
RD (external data memory read strobe)
The Port 3 output buffers can source/sink 4 LS TTL loads.
RST : reset input. A high on this pin for two machine
cycles while the oscillator is running resets the device.
ALE: Address Latch Enable output pulse for latching the
low byte of the address during accesses to external
memory. ALE is emitted at a constant rate of 1/6 of the
oscillator frequency, for external timing or clicking
purposes, even when there are no accesses to external
memory. (However, one ALE pulse is skipped during
each access to external Data Memory).
PSEN: Program Store Enable is the read strobe to
external Program Memory. When the device is executing
out of external Program Memory, PSEN is activated twice
each machine cycle (except that two PSEN activations
are skipped during accesses to external Data Memory).
PSEN is not activated when the deviced is executing out
of internal Program Memory.
EA: When EA is held high, the CPU executes out of
internal Program Memory (unless the Program Counter
exceeds OFFFH in the 80C5!, or !FFFH in the 80C52, or
3 FFFH in the 83CI54 or 7FFFH in the 83C!54D).
Holding EA low forces the CPU to execute out of external
memory regardless of the Program Counter value. In the
80C3!, 80C32 and 80C 154. EA must be externally wired
low.
XTALl : Input to the inverting oscillator amplifier.
XTAL2 : Output from the inverting oscillator amplifier.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
Figure 37. External Program Memory Fetches.
I
STATE 1
P1
P2
I
I
STATE 21 STATE 31 STATE 41 STATE 51 STATE 61 STATE 1
P1
P2 P1
P2 P1
P2 P1
P2 P1
P2 P1
P2
I
I
I
I
I
I
I
STATE 21
P1
P2
I
XTAL2:
L
L
ALE:
PSEN:
po:
P2:
PCH OUT
PCHOUT
PCH OUT
Figure 38. External Data Memory Read Cycle.
I
STATE 41 STATE 51 STATE 61 STATE 1
P1
P2 P1
P2 P1
P2 P1
P2
I
I
I
I
I
STATE 21 STATE 31 STATE 41 STATE 51
P1
P2 P1
P2 P1
P2 P1
P2
I
I
I
I
XTAL2:
L
ALE:
RD:
DATA SAMPLED
FLOAT
po:
P2:
PCLOUT IF
PROGRAM MEMORY
IS EXTERNAL
PCHOR
P2SFR
MATRAMHS
Rev. E (14 Jan. 97)
DPH OR P2 SFR OUT
PCHOR
P2SFR
1.2.39
TEMIC
cst Family
Semiconductors
Figure 39. External Data Memory Write Cycle.
I
STATE 41 STATE 51 STATE 61 STATE 1
P1
P2 P1
P2 P1
P2 P1
P2
I
I
I
I
I
STATE 21 STATE 31 STATE 41 STATE 51
P1
P2 P1
P2 P1
P2 P1
P2
I
I
I
I
XTAl2:
L
ALE:
WR:
PCLOUT IF
PROGRAM MEMORY
IS EXTERNAL
po:
P2:
DATA OUT
PCH OR
P2SFR
PCHOR
P2SFR
DPH OR P2 SFR OUT
Figure 40. Port Operation.
41 STATE 51 STATE 61 STATE 1 ISTATE 21 STATE 31 STATE 41 STATE 51
I P1STATE
I P2 P1 I P2 P1 I P2 P1 I P2 P1 I P2 P1 I P2 P1 I P2 P1 I P2
XTAl2:
-Lt
0'P1
INPUTS SAMPLED:
~
PO, P1
P2, P3, RS;
P2, P3, RST
MOV PORT, SRC :
SERTIAL PORT
SHIFT CLOCK
(MODE 0)
1.2.40
OLD DATA
I+- RXD PIN SAMPLED
--I L
NEW DATA
,--------------,I
RXD SAMPLED
---.f
I+-
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
C5t Family
Semiconductors
2. More Features for C154 Parts
This chapter explains, in details, the new features of the
83C154 and 83C154D. The only one difference between
83CI54 and 83CI54D is the internal ROM size
(respectively 16 K bytes and 32 K bytes long).
The major new features ofTEMlCCl54 is listed below:
•
•
I/O part impedance selection
Watchdog and 32-Bit TIMER/Counter Mode
•
Power-down mode
• Software control
• Hardware control
•
Frame and Overrun error serial link detection.
All these new features are controlled via the IOCON
register (new one) and the PCON register.
2.1. 110 Port Impedance
The structure and behaviour of the 83Cl54s'ports PI, P2
and P3 are indentical to those of the 80C52. Only the
control block for the different pull ups and pulldowns has
been changed. The pullup resistance value can be
programmed by means of the IOCON register.
There are three possible values:
- three states (PI, P2, P3 and N are OFF),
- high impedance (100 kQ, P2 =ON),
- low impedance (10 kQ, P3 =ON).
Figure 41. is a functional diagram of the PORT.
Figure 42. shows the configuration of the IOCON register
which is used to set the right value of the impedance port.
Figure 41. 110 Port Block Diagram.
vee
PDALF
PnHZ
Ize_---c::_------+-------------'
vss
MATRAMHS
Rev. E (14 Jan. 97)
1.2.41
1
TEMIC
cst Family
Semiconductors
Figure 42. IOCON Register Configuration.
(MSB)
WDT
(LSB)
T32
SERR
IZC
P3HZ
P2HZ
I
PIHZ
I
Symbol
Position
ALF
IOCON.O
- Set to I and in Power mode PORTS I, 2 and 3 are floating,
PIHZ
laCON.!
- If PIHZ = and IZC = 0, PORT PI is at low impedance,
- If PIHZ = and IZC = 0, PORT PI is at high impedance.
- If PIHZ = I, PORT PI is floating.
P2HZ
IOCON.2
- If P2HZ = and IZC = 0, PORT P2 is at low impedance.
- If P2HZ = and IZC = 0, PORT P2 is at high impedance.
-Ifp2HZ= I, PORT P2 is floating.
P3HZ
IOCON.3
- If P3HZ = and IZC = 0, PORT P3 is at low impedance.
- If P3HZ = and IZC = 0, PORT P3 is at high impedance.
-If P3HZ = I, PORT P3 is floating.
IZC
IaCONA
- In conjunction with PnHZ selects the output pullup value.
ALF
Function
°°
°°
°°
Low impedance
This mode is the default mode upon a reset and it is
compatible with C51 parts. The configuration ofIOCON
is explained by the Figure 42, Whenever PnHZ and IZC
are equal to zero, PI, P2 and P3 are in this mode. In this
case 3 LS TTL loads can be interfaced,
High impedance
This mode is invoked by setting PnHZ = 0 and IZC = I,
Only the transistor PZ of the Figure 41. is on and one LS
TTL load can be interfaced,
Three states mode
Two different modes can be used. The first one allows to
set each of the 3 ports in three states during a normal
operation. The second one allows to set all the 3 parts in
three states by entering in the Power-Down mode.
1.2.42
I
Whenever PnHZ is set to I, the part is in three states
mode. If ALF is set to 1, at each time the Power-Down
mode is called all the three parts are in the three states.
When the CI54 part exist from the Power-Down mode,
the part impedance is the impedance just before entering
in this mode (the part switches as soon as the interrupt
request is generated, not after the oscillator start-up). The
three states mode switch-off all the transistor.
2.2 Watchdog and 32-bit Timer/Counter
Mode
TIMER/COUNTER of C51 family can be configured in
four modes. With CI54 parts, two new modes can be used.
Both of them use TIMERO and/or TIMER I. The first one
is used like a 32-Bit Timer/Counter and the second one is
used like a 8/13116/32-Bit Watch-Dog. Both of this two
modes is programmed by software by using the laCON
register. The 32-Bit mode is on by setting the Bit T32. The
Watchdog mode is on by setting the bit WDT. The
Figure 43. shows the configuration of the register
laCON.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 43. 32 BitIWatchdog Mode.
(MSB)
WDT
(LSB)
I
T32
I
SERR
IZC
I
P3HZ
I
P2HZ
I
PIHZ
I
ALF
II
Symbol
Position
T32
IOCON.6
Function
- If T32 = I and if crro = 0, Tl and TO are programmed as a 32 bit TIMER.
- IfT32 = 1 and if crro = I, Tl and TO are programmed as a 32 bit COUNTER.
WDT
IOCON.7
- If WDT 1 and according to the mode selected by TMOD, and 8 bit or 32 bit WATCHDOG
is configured from TIMERS 0 and I.
=
Figure 44. 32 Bit Mode.
crro------------------------~
TO PIN
----------------------------L.....--
32 Bit Mode
32 Bit Timer
T32 = I enables access to this mode, As shown in Figure
44. this 32 bit mode consists in cascading TIMER 0 for the
LSBs and TIMER I for the MSBs.
Figure 45 illustrates the 32 Bit TIMER mode.
T32 = I starts the timer/counter and T32 = 0 stops it.
It should be noted that as soon as T32 =0, TIMERs 0 and
I assume the configuration specified by register TMOD.
Moreover, if TRO = I or if TR I = I, the content of the
TIMERs evolves. Consequently, in 32 bit mode, if the
TIMER/COUNTER must be stopped (T32 = 0). TRO and
TR 1 must be set to O.
Figure 45.
L-_O_S_C~~----~~~------~
In this mode, T32 = I and CfTO = 0, the 32 bit timer is
incremented on each S3PI state of each machine cycle.
An overflow of TIMER 0 (TFO has not been set to I)
increments TIMER I and the overflow of the 32 bit
TIMER is signalled by setting TFI (S5PI) to 1.
MATRAMHS
Rev. E (14 Jan. 97)
TIMER
I
TIMER
1--------'6
The following formula should be used to calculate the
required frequency:
OSC
f = 12 x (65536-(TO,
TI»
1.2.43
TEMIC
cst Family
Semiconductors
32 Bit Counter
Figure 46. illustrates the 32 BIT COUNTER mode.
Figure 46. 32 Bit Counter Configuration.
fEXT
GI--------II
TIMER
01 TIMER 111----E]
In this mode, T32 = 0 and CITO = 1. Before it can make
an increment, the 83C154 must detect two transitions on
its TO input. As shown in Figure 47. input TO is sampled
on each S5P2 state of every machine cycle or, in other
words, every OSC + 12.
Figure 47. Counter Incrementation Condition.
• TO PIN
Lmm.----'
READING OF INPUT TO
Ci-1t
Ci",
S5P2 .......... .1 S5P2
COUNTER INCREMENTATION
The counter will only evolve if a level 1 is detected during
state S5P2 of cycle Ci and if a level 0 is detected during
state S5P2 of cycle Ci + n.
Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or equal
to two machine cycles. The following formula should be
used to calculate the operating frequency.
fEXT
f = (65536-(TO, Tl))
fEXT :s
1.2.44
Ci+n+
iS5P2
tS3P1
watchdog Mode
WDT = 1 enables access to this mode. As shown in
Figure 48. all the modes of TIMERs 0 and 1, of which the
overflows act on TFl (TFI = 1), activate the watchdog
Mode.
If CIT = 0, the watchdog is a TIMER that is incremented
every machine cycle. If CIT = 1, the watchdog is a
counter that is incremented by an external signal of which
the frequency cannot exceed OSC + 24.
°2~C
MATRAMHS
,Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
The overflow of the TIMER/COUNTER is signalled by
raising flag TFI to 1. The reset of the 83Cl54/83Cl54D
is executed during the next machine cycle and lasts for the
next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal RAM
is not affected and the special register assume the values
shown in Table 2.
Table 3. Content of the SFRs after a reset
triggered by the WATCHDOG.
REGISTER
PC
ACC
B
PSW
SP
DPTR
PO-P3
IP
IE
TMOD
TCON
T2CON
THO
TLO
THI
TLi
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
IOCON
CONTENT
OOOOH
OOH
OOH
OOH
OOH
DOOOH
OFFH
DOH
OXOODOOOB
DOH
OOH
DOH
OOH
DOH
OOH
DOH
OOH
DOH
OOH
DOH
DOH
Indeterminate
DOH
As there are no precautions for protecting bit WDT from
spurious writing in the laCON register, special care must
be taken when writing the program. In particular, the user
should use the laCON register bit handing instructions:
- SETB and CLR x
in preference to the byte handling instructions:
- MaY laCON, # XXH, ORL laCON, # XXH,
- ANL laCON, # XXH,
External Counting in Power-down Mode
(PD = PCON.] = 1)
In the power-down mode. the oscillator is turned off and
the 83Cl54s'activity is frozen. However, if an external
clock is connected to one of the two inputs, TIITO,
TIMER/COUNTERS 0 and I can continue to operate. In
this case, counting becomes asynchronous and the
maximum, admissible frequency of the signal is OSC : 24.
The overflow of either counter TFO or TFI causes an
interrupt to be serviced or forces a reset if the counter is
in the watchdog MODE (T32 = ICON.7 = I).
MATRAMHS
Rev. E (14 Jan. 97)
2.3 Power-Reducing Mode
Basically the Power-Reducing Mode of the TEMIC CI54
parts are 100 % compatible with the 80C51 and 80C52
parts. However both Idle and Power-Down mode are
improved with some new powerful features.
Idle mode is improved by giving the software possibility
to execute or not the software interrupt routine when an
interrupt request occurs (Recover Power Mode).
Power-Down mode is now more powerful because an
interrupt request can avake the TEMIC Cl54 parts. In
addition an external hardware signal can control entirely
the mode (Hardware Power Mode).
Details on these new features are given below.
Idle Mode
This mode is basically compatible with the TEMIC C51
parts (refer to the chapter 1.11). The new feature concerns
the way to exit from this mode. Now with the Recover
Power Mode, the software interrupt routine is or not
executed when the interrupt routine occurs. This mode is
activated by setting the bit RPD in PCON register. In this
case the next instruction executed is the next following
the IDLE instruction (MaY PLaN, # 0 I).
Power-Down Mode
Software control
This mode is basically compatible with the C51 parts
(refer to the chapter 1.11). The new features concern the
way to exit from this mode.
With the C51 parts the only way to complete this mode is
to apply an hardware reset. The newest thing is the
possibility to exist from this mode by an interrupt request
coming from the both external interrupts and the both
counter 0 and I if an external clock is connected on pin
T1 or TO.
Likewise IDLE mode, it is possible to execute or not the
software interrupt routine. By setting the RPD bit the next
instruction executed. after the interrupt request has been
processed, will be the instruction following the
POWER-DOWN intruction. If the RPD bit is not set, the
program will continue by executing the software interrupt
routine. The Figure 48. shows the behaviour of the
Recover Power Mode.
1.2.45
II
TEMIC
CSt Family
Semiconductors
Figure 48. Example in Recover Power Mode.
ex:
; The Recover Mode is enable
; The Power-Down is enable
Adr n MOV PCON, #OOIXXXIO ...
; The CPU waits for an asynchronous
; event
; An interrupt request occurs and
; the instruction located at the
; address Adr n + I is executed
Adrn+ I
Hardware control
This mode is new and controls the Power-Down by an
external hardware signal connected on pin Tl (P3.5). This
mode is called by setting HPD bit in the PCON register.
The 83CI54 will be in Power-Down as soon as
TI input will be drive by a falling edge and will remain
in this state until TI input will be drive by a rising edge.
The Figure 49. shows the behaviour of the Hardware
Power Mode.
Figure 49. Behaviour of the Hardware Power Mode (HPD = 1).
T1
~S-----<'~'r-~
-------»)
The clock is stopped
on the falling edge
XTAL2
The time takes by the oscillator to restart depends of the
crystal and the capacitors connected on both side of the
crystal (typically 10 ms).
Software and hardware control
This two modes can be mixed to control the Power-Down
Mode. Entry to the mode can be made either by setting PD
bit to 1 or by setting HPD bit to I and presenting a falling
edge on Tl input. Exit from this mode can be made if the
software and hardware conditions are met: a rising edge
on Tl input and an interrupt request. If these two
conditions are not satisfied, only an hardware reset can
complete the mode.
1.2.46
The clock
resta~
_ _ _ _ __
on the rising edge
2.4 Frame and Overrun Error
Serial Link Detection
This feature is new and allows to the user to detect a serial
link error. Two kinds of error can be detected during a
reception : OVERRUN ERROR and FRAME ERROR.
Both of them set the SERR bit in the IOCON register at
the half of the stop bit. This must be cleared by software.
Frame error
This error occurs when the format of the received Data is
wrong. The Figure 50. shows an example of a Frame error.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Figure 50. FRAME ERROR example, STOP BIT is missing.
RXD ---:__-'-_0_-'-__-'-_2_"'--_3_--'--_4_-'-_5_"'--_6_-'-_7_->.'::::::::::::::::::
a
t
STOP BIT is missing
SERR----------------------------------------------~r-In this example the receiver waits for a STOP BIT to
complete the frame reception. Unfortunately the stop bit
isn't there and the receiver indicates the frame error by
setting to 1 the SERR bit in the IOCON register.
Overrun Error
This error occurs, when a character received and not read
by the c.P. U, is overwritten by a new one. The Figure 51.
shows an example of OVERRUN ERROR.
Figure 51. OVERRUN ERROR example.
RXD
RI ____________________
SERR
S~L.._-'--_C_H_A_R_A_CT_E_R_2__'
CHARACTER 1
~~S
----------------~~~----------~I
--'t
Character 2 is overwritten _ _ _ _
by the first
In this example the character 1 is received and the RI bit
is set to 1. A second character is sent before the CPU reads
the first one. The character 1 is overwritten and SERR bit
is set to I to indicate the loss of the first character.
MATRAMHS
Rev. E (14 Jan. 97)
Note
With the C154 parts the RI bit isn't set on the same time
than the C51 parts. With the C51 parts the RI bit is set on
the last data bit. With the C154 the RI bit is set on the stop
bit.
1.2.47
TEMIC
Semiconductors
CS1 Family
CSt Family Programmer's Guide and Instruction Set
a
Summary
1. Memory Organization ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1.3.2
1.1. Program Memory .......................................................................
1.2. Data Memory ..........................................................................
1.3. Indirect Address Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
1.4. Direct And Indirect Address Area ..........................................................
1.5. Special Function Registers ................................................................
1.3.2
I.3.3
1.3.3
I.3.3
I.3.4
2. SFR Memory Map ..................................................... .. I.3.6
2.1. What do the SFRs Contain just after Power-on or a Reset? ...................................... I.3.6
2.2. Interrupts .............................................................................. 1.3.8
2.3. Assigning Higher Priority to one More Interrupts .............................................. 1.3.9
2.4. Priority Within Level .................................................................... 1.3.9
2.5. Timer Set-up " . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. I.3.11
2.6. Timer/Counter 0 ....................................................................... 1.3.11
2.7. Timer/Counter 1 ....................................................................... 1.3.12
2.8. Timer/Counter 2 Set-up ................................................................. I.3.12
2.9. Serial Port Set-Up ........... " ......................................................... I.3.14
2.1 O. Generating Baud Rates ..... . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . .. . . . . .. .. . . .. . . . . . . . . . . .. . .. 1.3 .14
2.11. Using Timer/Counter I to Generate Baud Rates ............................ " ................ 1.3.14
2.12. Using Timer/Counter 2 to Generate Baud Rates ............................................. 1.3.14
2.13. Serial Port in Mode 2 .................................................................. 1.3.14
2.14. Serial Port in Mode 3 .................................................................. 1.3.14
3. Instruction Definitions . .................................................. 1.3.19
MATRAMHS
Rev. E (14 Jan. 97)
1.3.1
TEMIC
CSt Family
Semiconductors
1. Memory Organization
1.1. Program Memory
Figure 3. The 83C154 Program Memory.
The TEMIC C51 Microcontroller Family has separate
address spaces for program Memory and Data Memory.
The program memory can be up to 64 K bytes long. The
lower 4 K for the 80C5l (8 K for the 80C52, 16 K for the
83 C154 and 32 K for the 83C154D) may reside on chip.
Figure 1 to 4 show a map of 80C51, 80C52, 83C154 and
83C154D program memory.
,- FFFF .....- - - - - ,
FFFF
48K
BYTES
EXTERNAL
or ~
4000
Figure 1. The 80C51 Program Memory.
64K
BYTES
EXTERNAL
3FFF
FFFF .....- - - - - ,
FFFF
0000
60K
BYTES
EXTERNAL
or ~
1000
16K BYTES
INTERNAL
64K
BYTES
EXTERNAL
-
0000 ' - - - - - - '
Figure 4. The 83C154D Program Memory.
-
FFFF
FFFF,-----,
OFFF
32K
BYTES
EXTERNAL
4K BYTES
INTERNAL
0000 ' - - - - - - '
0000
Figure 2. The 80C52 Program Memory.
FFFF .....- - - - ,
FFFF
or
~
64K
BYTES
EXTERNAL
7FFF
32K BYTES
INTERNAL
56K
BYTES
EXTERNAL
2000
8000
0000
or~
-
0000 ' - - - - - - '
64K
BYTES
EXTERNAL
1FFF
8K BYTES
INTERNAL
0000
1.3.2
0000 '--------'
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
1.2. Data Memory
The C51 Microcontroller Family can address up to 64 K
bytes of Data Memory to the chip. The "MOYX"
instruction is used to access the external data memory
(refer to the C51 instruction set, in this chapter, for
detailed description of instructions).
The 80CSI has 128 bytes of on-chip-RAM (256 bytes in
the 80C52, 83CI54 and 83C154D) plus a number of
Special Function Registers (SFR). The lower 128 bytes of
RAM can be accessed either by direct addressing (MOY
data addr). or by indirect addressing (MOY @Ri). Figure
5 and 6 show the 80C51, 80C52, 83CI54 and 83CI54D
Data Memory organization.
Figure 6. The 80C52, 83C154 and 83C1S4D
Data Memory Organisation.
INTERNAL
FFFF , - - - - - - - ,
II
INDIRECT
ADDRESSING ONLY
80HTO FFH
FFI
FF
80
7F
SFRs
DIRECT
ADDRESSING
ONLY
64K
BYTES
EXTERNAL
AND--
DIRECT &
INDIRECT
ADDRESSING
Figure 5. The 80CS1 Data Memory Organisation.
00
0000
OFFF , - - - - - - - ,
INTERNAL
FF
80
7F
64K
BYTES
EXTERNAL
SFRs
DIRECT
ADDRESSING
ONLY
AND -DIRECT &
INDIRECT
ADDRESSING
00
0000
1.3. Indirect Address Area
1.4. Direct And Indirect Address Area
Note that in Figure 6 - the SFRs and the indirect address
RAM have the same addresses (80H-OFFH).
Nevertheless, they are two separate areas and are
accessed in two different ways. For example the
instruction
The 128 bytes of RAM which can be accessed by both
direct and indirect addressing can be divided into 3
segments as listed below and shown in figure 7.
writes OBBH in location 80H of the data RAM. Thus,
after execution of both of the above instructions Port 0
will contain OAAH and location 80 of the RAM will
contain OBBH.
1. Register Banks 0.3 : Locations 0 through IFH (32
bytes). ASM-51 and the device after reset default to
register bank O. To use the other register banks the user
must select them in the software. Each register bank
contains 8 one-byte registers, 0 through 7.
Reset initializes the Stack Pointer to location 07H and it
is incremented once to start from location 08H which is
the first register (RO) of the second register bank. Thus,
in order to use more than one register bank, the SP should
be initialized to a different location of the RAM where it
is not used for data storage (ie, higher part of the RAM).
Note lhat the stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are
available as stack space in those devices which
implement 256 bytes of internal RAM.
2. Bit Addressable Area : 16 bytes have been assigned
for this segment, 20H-2FH. Each one of the 128 bits of
this segment can be directly addressed (0-7FH).
The bits can be referred to in two ways both of which are
MOY 80H, #OAAH
writes OAAH to Port 0 which is one of the SFRs and the
instruction
MOY RO,# 80H
MOV @ RO, # OBBH
MATRAMHS
Rev. E (14 Jan. 97)
1.3.3
TEMIC
cst Family
Semiconductors
acceptable by the ASM-S1. One way is to refer to their
addresses, ie, 0 to 7FH. The other way is with reference
to bytes 20H to 2FH. Thus, bits 0-7 can also be referred
to as bits 20.0-20.7, and bits 8-FH are the same as
21.0-21.7 and so on.
Each of the 16 bytes in this segment can also be addresses
as a byte.
3. Scratch Pad Area : Bytes 30H through 7FH are
available to user as data RAM. However, if the stack
pointer has been initialized to this area, enough number
of bytes should be left aside to prevent SP data
destruction.
Figure 7. 128 Bytes of RAM Direct and Indirect Addressable.
8 Bytes
78
7F
70
77
68
6F
60
67
58
SF
50
57
48
4F
40
47
38
3F
30
37
SCRATCH
PAD
... 7F
28
2F
AREA
BIT
ADDRESSABLE
20
27
0 ...
18
3
1F
10
2
17
08
1
OF
00
0
07
SEGMENT
REGISTER
BANKS
1.5. Special Function Registers
Table 1 contains a list of all the SFRs and their addresses.
Comparing table 1 and figure 8 shows that all of the SFRs
that are byte and bit addressable are located on the first
column of the diagram in figure 8.
I.3.4
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Table 1.
/: ~ ~,'
v.':.:.• •'.,"." SYMBOL
NAME
ADDRESS'
*ACC
Accumulator
*B
B Register
OFOH
*PSW
Program Status Word
ODaH
SP
Stack Pointer
DPTR
OEOH
a
8tH
Data Pointer 2 Bytes
DPL
Low Byte
82H
DPH
High Byte
83H
*PO
PortO
80H
*PI
Port t
90H
*P2
Port 2
OAOH
*P3
Port 3
OBOH
*IP
Interrupt Priority Control
OB8H
OA8H
*IE
Interrupt Enable Control
TMOD
Timer/Counter Mode Control
89H
*TCON
Timer/Counter Control
88H
*+T2CON
Timer/Counter 2 Control
OC8H
THO
Timer/Counter 0 High Byte
8CH
TLO
Timer/Counter 0 Low Byte
8AH
THI
Timer/Counter I High Byte
8DH
TLI
Timer/Counter I Low Byte
8BH
+TH2
Timer/Counter I High Byte
OCDH
+TL2
Timer/Counter 2 Low Byte
OCCH
+RCAP2H
T/C 2 Capture Reg. High Byte
OCBH
OCAH
+RCAP2L
T/C 2 Capture Reg. Low Byte
*SCON
Serial Control
98H
SBUF
Serial Data Buffer
99H
PCON
Power Control
87H
*IOCON (I)
10 Control
F8H
+ 8OC52, 83CI54 and 83CI54D only
(I) 83CI54 and 83C154D only
MATRAMHS
Rev, E (14 Jan, 97)
* bit addressable
13.5
TEMIC
cst Family
Semiconductors
2. SFR Memory Map
FigureS.
8 Bytes
F8
IOCON
FF
FO
B
F7
EF
E8
EO
E7
ACC
DF
D8
DO
PSW
C8
T2CON
D7
RCAP2L
RCAP2H
TL2
TH2
CF
C7
CO
B8
lP
BF
BO
P3
B7
A8
IE
AF
AO
P2
98
SCON
90
PI
88
TCON
TMOD
TLO
TLI
80
PO
SP
DPL
DPH
A7
SBUF
9F
97
THO
THI
8F
PCON
87
~ bit addressable
2.1. What do the SFRs Contain just after
Power-on or a Reset?
Table 2 lists the contents of each SFR after a power-on
reset or a hardware reset.
Table 2. Contents of the SRFs after reset.
*ACC
*B
*psw
SP
DPTR
*po
*PI
*P2
*P3
*IP
*IE
TMOD
00000000
00000000
00000000
00000111
00000000
11111111
1111 1111
1111 1111
1111 1111
XXXO 0000 80C51
XXXO 0000 80C52
OXOO 0000 83CI54/CI54D
OXXO 0000 80CSI
OXOOO 0000 83CI54/CIS4D
and 80C52
00000000
* : bit addressable.
+ : 80C52, 83CI54 and 83CI54D only.
-: 83CI54 and 83CI54D only.
X : Undefined.
1.3.6
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
These SFRs that have their bits assigned for various
functions are listed in this section. A brief description of
each bit is provided for quick reference. For more detailed
information refer to the Architecture chapter of this book.
}Ui:{7(lS1;ji;R •.. ...VA.LllE IN BINA.RY
*TCON
+*T2CON
THO
TLO
THI
TLl
+TH2
+TL2
+ RCAP2L
+ RCAP2H
'SCON
SBUF
PCON
00000000
00000000
00000000
00000000
00000000
00000000
00000000
0000 0000
00000000
00000000
00000000
Indeterminate
OXXX 0000 SOC5 I and 80C52
OOOX 0000 83C I 54 and 83C I 54D
00000000
-*IOCON
II
PSW: Program Status Word (Bit Addressable)
Cy
AC
FO
RSI
RSO
CY
PSW,7
AC
FO
PSW,6
Carry Flag.
Auxiliary Carry Flag.
PSW,5
PSW,4
Flag 0 available to the user for general purpose.
Register Bank selector bit I (SEE NOTE).
RSI
RSO
OV
PSW,3
Register Bank selector bit 0 (SEE NOTE).
PSW,2
Overflow Flag.
OV
FI
p
FI
PSW,I
Flag FI available to the user for general purpose.
P
PSW,O
Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number
of "I" bits in the accumulator.
Note:
The value presented by RSO and RSI selects the
corresponding register bank.
o
o
o
o
* User software should not write Is to reserved bits. These
bits may be used in future TEMIC C51 products to invoke
new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1.
OOH-07H
08H-OFH
o
IOH-I7H
18H-IFH
MATRAMHS
Rev. E (14 Jan. 97)
I.3.7
TEMIC
cst Family
Semiconductors
PC ON : Power Control Register (Not Bit Addressable)
I
SMOD
HPD
RPD
GFI
GFO
PD
IDL
= I, the baud rate is doubled when the serial part is used in mode
SMOD
PCON.7
Double baud rate bit. If SMOD
1,2 and 3.
HPD
PCON.6
Hard Power Down. (83CIS4 and 83CIS4D only). The falling/rising edge of a signal connected
on pin P3.S Starts/Stops the Power-Down mode. A reset can also stop this mode.
RPD
PCON.S
Recover Power Down bit. (83ClS4 and 83CIS4D only). It's used to cancel a Power-Down/IDLE
mode. If it's set, an interrupt (enable or disable) can cancel this mode. A reset can also stop this
mode (see Note 1).
PCON.4
Not implemented, reserved for futur used*
GFI
PCON.3
General purpose bit.
GFO
PCON.2
General purpose bit.
PD
PCON.I
Power Down bit. If set, the oscillator is stopped. A reset or an interrupt (83ClS4 and 83ClS4D
only) can cancel this mode (Note I).
IDL
PCON.O
IDLE bit. If set the activity CPU is stopped. A reset or an interrupt can cancel this mode (See
Note I).
* User software should not write Is to reserved bits. These
bits may be used in future TEMIC CSI products to invoke
new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be I.
Note 1 (83C154 and 83C154D only) :
- if RPD = 0 and if an interrupt cancels the mode
Power-Down/IDLE, the next instruction to execute is a
LCALL at the interrupt routine.
2.2. Interrupts
In order to use any of the interrupts in the CSI, the
following three steps must be taken.
I. Set the EA (enable all) bit in the IE register to I.
2. Set the corresponding individual interrupt enable bit in
the IE register to I.
3. Begin the Interrupt service routine at the corresponding
Vector Address of that interrupt. See Table below.
- if interrupt request is enable the next
- RPD = I
instruction to execute is a LCALL at the interrupt routine.
- if interrupt request is disable, the program
continue with the instruction immediately after the
Power-DownlIdle instruction.
'INTEltIlUrT S911Itc:'E'
.' '•.......•'.
.•....
lEO
TFO
IEI
TFI
RI & Tl
TF2 & EXF2
In addition, for external interrupts, pins INTO and INTI
(P3.2 and P3.3) must be set to I, and depending on
whether the interrupt is to be level or transition activated,
bits ITO or ITI in the TCON register may need to be set
to 1.
1.3.8
····...V~(;TQR;~~n~S
'" •.••.. . ••. '.' .... . .'
0003H
OOOBH
0013H
OOIBH
0023H
002BH
ITX
ITX
=0 level activated
= I transition activated
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
IE: Interrupt Enable Register (Bit Addressable)
If the bit is 0, the corresponding interrupt is disabled. If
the bit is 1, the corresponding interrupt is enabled.
ET2
EA
ETI
ES
EXI
ETO
EXO
IE.7
Disables all interrupts. If EA = 0, no interrupt will be acknowledged. If EA = I, interrupt source
is individually enable or disabled by setting or clearing its enable bit.
IE.6
Not implemented, reserved for future use*.
ET2
IE.5
Enable or disable the Timer 2 overflow or capture interrupt (80C52, 83C154 and 83CI54D only).
ES
IEA
Enable or disable the Serial port interrupt.
ETl
IE.3
Enable or disable the Timer I overflow interrupt.
EXI
IE.2
Enable or disable External interrupt I.
ETO
IE.1
Enable or disable the Timer
EXO
IE.O
Enable or disable External Interrupt 0.
EA
°
overflow interrupt.
* User software should not write Is to reserved bits. These
bits may be used in future TEMIC C51 products to invoke
new features. In that case, the reset or inactive value of the
new bit will be 0, and its active value will be 1.
2.4. Priority Within Level
2.3. Assigning Higher Priority to one More
Interrupts
lEO
TFO
IEI
TFI
RI or TI
TF20rEXF2
In order to assign higher priority to an interrupt the
corresponding bit in the IP register must be set to I.
Remember that while an interrupt service is in progress,
it cannot be interrupted by a lower or same level interrupt.
Priority within level is only to resolve simultaneous
requests of the same priority level. From high to low,
interrupt sources are listed below:
IP: Interrupt Priority Register (Bit Addressable)
If the bit is 0, the corresponding interrupt has a lower
priority and if the bit is the corresponding interrupt has a
higher priority.
peT
PCT
PT2
IP.7
PT2
PS
PTl
PXl
PTO
PXO
Defines the same priority level for all the source interrupt (83C154 and 83C154D only).
IP.6
Not implemented, reserved for future use*.
IP.5
Defines the Timer 2 interrupt priority level (80C52, 83Cl54 and 83C154D only).
Defines the Serial Port interrupt priority level.
PS
IPA
PTl
IP.3
Defines the Timer 1 Interrupt priority level.
PXl
IP.2
Defines External Interrupt priority level.
PTO
IP.!
Defines the Timer
pxo
IP.O
°
interrupt priority level.
°
Defines the External Interrupt priority level.
* User software should not write Is to reserved bits. These
bits may be used in future TEMIC C51 products to invoke
new features. In that case, the reset or inactive value of the
now bit will be 0, and its active value will be l.
MATRAMHS
Rev. E (14 Jan. 97)
1.3.9
II
TEMIC
cst Family
Semiconductors
IOCON : Input/Output Control Register (83C154 and 83C154D only)
WDT
WDT
T32
SERR
IZC
P3HZ
P2HZ
PlHZ
ALF
T32
SERR
IZC
P3HZ
PIHZ
P2HZ
ALF
=
IOCON.7 Watch Dog Timer bit. Set when Timer I is overflow (TF I). The CPU is reset and the program
is executed from address O.
IOCON.6 Timer 32 bits. The Timer I and Timer 0 are connected together to form a 32 bits Timer/Counter.
If CfTO = 0, it's a Timer. If CfTO = I, it's a counter.
IOCON.5 Serial Port Reception Error flag. Set when an overrun on frame error is received.
IOCON.4 Set/Cleared by software to select 100/10 K pull up resistance for Port I, 2 and 3.
IOCON.3 When Set, Port 3 becomes a tri-state input. When cleared, the pull-up resistance value is selected
by IZC.
IOCON.2 When Set, Port 2 becomes a tri-state input. When cleared, the pull-up resistance value is selected
by IZC.
IOCON.I When Set, Port I becomes a tri-state input. When cleared, the pull-up resistance value is selected
by IZC.
IOCON.O All Port tri-state. When Set and CPU in Power-Down mode, port I, 2 and 3 are tri-state.
TCON: Timer/Counter Control Register (Bit Addressable)
TFI
TFI
TCON.7
TRI
TFO
TCON.6
TCON.5
TRO
IEI
TCON.4
TCON.3
IT!
TCON.2
IEO
TCON.I
ITO
TCON.O
TRI
TFO
TRO
IEI
IT!
lEO
ITO
Timer I overflow flag. Set by hardware when the Timer/Counter
overflows. Cleared by
hardware as processor vectors to the interrupt service routine.
Timer I run control bit. Set/cleared by software to turn Timer/Counter ON/OFF.
Timer 0 overflow flag. Set by hardware when the Timer/Counter 0 overflows. Cleared by
hardware as processor vectors to the service routine.
Timer 0 run control bit. Set/cleared by software to turn Timer/Counter 0 ON/OFF.
External Interrupt I edge flag. Set by hardware when External interrupt edge is detected. Cleared
by hardware when interrupt is processed.
Interrupt I type control bit. Set/cleared by software to specify falling edgelflow level triggered
External Interrupt.
External Interrupt 0 edge flag. Set by hardware when External Interrupt edge detected. Cleared
by hardware when interrupt is processed.
Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered
External Interrupt.
TMOD : Timer/Counter Mode Control Register (Not Bit Addressable)
GATE
CIT
Ml
TIMER 1
GATE
CIT
MI
MO
1.3.10
MO
GATE
CIT
MI
MO
TIMER 0
When TRx (in TCON) is set and GATE = I, TIMER/COUNTERx will run only while INTx pin is high
(hardware control). When GATE = 0, TIMERICOUNTERx will run only while TRx = 1 (software
control).
Timer or Counter selector. Cleared for Timer operation (input from internal system clock). Set for
Counter operation (input from Tx input pin).
Mode selector bit (NOTE I).
Mode selector bit (NOTE 1).
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Note 1:
Ml
MO
0
0
0
1
0
1
OPERATING MODE
o
1
2
3
13-bit Timer
16-bit Timer/Counter
8-bit Auto-Reload Timer/Counter
(Timer 0) TLO is an 8-bit Timer/Counter controlled by the standard Timer 0 control
bits, THO is an 8-bit Timer and is controlled by Timer I control bits.
(Timer I) Timer/Counter I stopped.
2.5. Timer Set-up
Table 4. As a Counter
Tables 3 through 6 give some values for TMOD which can
be used to set up Timer 0 in different modes.
It is assumed that only one timer is being used at a time.
It is desired to run Timers 0 and 1 simultaneously, in any
mode, the value that in TMOD for Timer 0 must be ORed
with the value shown for Timer 1 (Tables 5 and 6).
For example, if it is desired to run Timer 0 in mode I
GATE (external control) and Timer 1 in mode 2
COUNTER, then the value must be loaded into TMOD is
69H (09H from Table 3 ORed with 60H from Table 6).
Moreover, it is assumed that the user, at this point, is not
ready to tum the timers on and will do that a different
point in the program by setting bit TRx (in TCON) to 1.
2.6. Timer/Counter 0
Table 3. As a Timer
Notes: 1. The Timer is turned ON/OFF by setting/clearing bit TRO in the software.
2. The Timer is turned ON/OFF by the I to 0 transition on INTO (P3.2) when TRO = I (hardware control).
MATRAMHS
Rev. E (14 Jan. 97)
1.3.11
II
TEMIC
cst Family
Semiconductors
2.7. Timer/Counter 1
Table 6. As a Counter
Table 5. As a Timer
Notes: 1. The Timer is turned ON/OFF by setting/clearing bit TR 1 in the software.
2. The Timer is turned ON/OFF by the 1 to 0 transition on INTI (P3.2) when TR 1 : I (hardware control).
T2CON : Timer/Counter 2 Control register (Bit Addressable)
(80C52, 83C154 and 83C154D only)
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
crf2
CPIRL2
TF2
T2CON.7 Timer 2 overflow flag set by hardware and cleared by software. TF2 cannot be set when either
RCLK= 1 or CLK = 1
EXF2 T2CON.6 Timer 2 external flag set when either a capture or reload is caused by a negative transition on
T2EX, and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to
vector to the Timer 2 interrupt routine. EXF2 must be cleared by software.
RCLK T2CON.5 Receive clock flag. When set, causes the Serial Port to use Timer 2 overflow pulses for its receive
clock in modes 1 & 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK T2CONA Transmit clock flag. When set, causes the Serial Port use Timer 2 overflow pulses for its transmit
clock in modes 1 & 3, TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 T2CON.3 Timer 2 external enable flag. When set, allows a capture or reload to occur as a result of negative
transition on T2EX if Timer 2 is not being used to clock the Serial Port. EXEN2 = 0 causes Timer
2 to ignore events as T2EX.
TR2
T2CON.2 Software START/STOP control for Timer 2. A logic 1 starts the Timer.
CIT2
T2CON.1 Timer or Counter select.
CPIRL2 T2CON,O CapturelReload flag. When set, captures will occur on negative transitions at T2EX if
EXEN2 = 1. When cleared, Auto-Reloads will occur either with Timer2 overflows or negative
transitions at T2EX when EXEN2 = 1. When either RCLK = I or TCLK = I, this bit is ignored
and the Timer is forced to Auto-Reload on Timer 2 overflow.
2.8. Timer/Counter 2 Set-up
Except for the baud rate generator mode, the values given
for T2CON do not include the setting of the TR2 bit.
Therefore, bit TR2 must be set, separately, to tum the
Timer on.
1.3.12
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Table 7. As a Timer
Table 8. As a Counter
INTERNAL
CONTROL \1<·(;()~ItR'
MODE
I]
(NOTE~J"'"
16-bit Auto-Reload
16-bit Capture
BAUD rate generator
receive & transmit same
baud rate
receive only
transmit only
OOH
OIH
08H
09H
34H
24H
14H
36H
26H
16-bit Auto-Reload
16-bit Capture
OAH
OBH
02H
03H
16H
Notes: 1. Capture/Reload occurs only Timer/Counter overtlow.
2. Capture/Reload occurs on Timer/Counter ovclilow and a I to 0 transition on T2EX (Pl.!) pin except when Timer 2 is used
in the baud rate generating mode.
SCON : Serial Port Control Register (Bit Addressable)
SMO
SMO
SMl
SM2
SCON.7
SCON.6
SCON.S
SMI
SM2
REN
TN8
RB8
TI
RI
Serial Port mode specifier (NOTE I).
Serial Port mode specifier (NOTE I).
Enables the multiprocessor communication feature in mode 2 & 3. In mode 2 or 3, if SM2 is set
to I then RI will not be activated if the received 9th data bit (RB8) is 0. In mode I, if SM2 = 1
then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be (See
table 9).
Set/Cleared by software to Enable/Disable reception.
The 9th bit that will be transmitted in modes 2 & 3. Set/Cleared by software.
In modes 2 & 3, is the 9th data bit that was received. In mode 1, if SM2 = 0, RB8 is the stop bit
that was received. In mode 0, RB8 is not used.
Transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning
of the stop bit in the other modes. Must be cleared by software.
Receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or half way through
the stop bit time in the other modes (except see SM2). Must be cleared by software.
°
REN
TB8
RB8
SCONA
TI
SCON.l
RI
SCON.O
SCON.3
SCON.2
Note 1 :
o
o
I
MATRAMHS
Rev. E (14 Jan. 97)
o
o
SHIFT REGISTER
Fosc.!12
I
I
2
8 bitUART
8 bitUART
8bitUART
Fosc./64 OR Fosc./32
Variable
o
Variable
1.3.13
TEMIC
cst Family
Semiconductors
=
2.9. Serial Port Set-Up
THI
Table 9.
THI must be integer value. Rounding off THI to the
nearest integer may not produce the desired baud rate. In
this case, the user may have to choose another crystal
frequency.
1···/·1\10D1': •.•·• •· · •· ... SCON<.Sl\1:zYA~1:\:ri6t1i
o
IOH
o
SOH
Single Processor
90H
Environment
DOH
(SM2 =0)
NA
2
70H
Multiprocessor
BOH
Environment
FOH
(SM2= I)
2.10. Generating Baud Rates
Serial Port in Mode 0 :
Mode has a fixed baud rate which is 1112 of oscillator
frequency. To run serial port in this mode none of the
Timer/Counters need to be set up. Only the SCON register
needs to be defined.
°
Baud Rate
=
Osc Freq
--1-2-
Serial Port in Mode 1 :
Mode I has a variable baud rate. The baud rate can be
generated by either Timer I or Timer 2 (80C52, 83C 154
and 83CI54D only).
2.11. Using Timer/Counter 1 to Generate
Baud Rates
For this purpose, Timer I is used in mode 2
(Auto-Reload). Refer to Timer Setup section of this
chapter.
K x Oscillator freq.
Baud Rate
if SMOD
=
32 x 12 x [256-(THl)]
=0, then K = 1.
If SMOD = I, then K =2. (SMOD is the PCON register).
Most of the time the user knows the baud rate and needs
to know the reload value for THI. Therefore, the equation
to calculate THI can be \lritten as :
1.3.14
256 _ K x Oscillator freq.
384 x baud rate
Since the PCON register is not bit addressable, one way
to set the bit is logical ORing the PCON register (ie, ORL
PCON, #80H). The address of PCON is 87H.
2.12. Using Timer/Counter 2 to Generate
Baud Rates
For this purpose, Timer 2 must be used in the baud rate
generating mode. Refer to Timer 2 Setup Table in this
chapter. If Timer 2 is being clocked through pin T2 (P 1.0)
the baud rate is :
B
au
d R t - Timer 2 Overflow Rate
ae 16
And if it being clocked internally the baud rate is :
Baud Rate
=
32
X
Osc. Freq
[65536 - (RCAP2H, RCAP2L)]
To obtain the reload value for RCAP2H and RCAP2L the
above equation can be written as :
RCAP2H, RCAP2L
=
Osc. Freq
65536 - 32 x Baud rate
2.13. Serial Port in Mode 2
The baud rate is fixed in this mode and 1/32 or 1/64 of the
oscillator frequency depending on the value of the SMOD
bit in the PCON register.
In this mode none of the Timers are used and the clock
comes from the internal phase 2 clock.
SMOD
= I, Baud Rate = 1132 Osc Freq.
SMOD = 0, Baud Rate = 1/64 Osc Freq.
To set the SMOD bit: ORL PCON, #80H. The address of
PCONis 87H.
2.14. Serial Port in Mode 3
The baud rate in mode 3 is variable and sets up exactly the
same as in mode I.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
C5t Family
Semiconductors
Table 10. TEMIC CSI Instruction Set
loten-upt Response time: Refer to Hardware Description
Chapter.
Instructions that Affect Flag Settings (I)
INSTRUC.
ADD
ADDC
SUBB
MUL
DIV
DA
RRC
RLC
SETBC
FLAG
FLAG
INSTRUC.
C
OV
AC
X
X
X
0
0
X
X
X
X
X
X
X
X
X
X
X
C
CLRC
CPL C
ANL C, bit
ANLC,/bit
ORLC, bit
ORLC, bit
MOVC, bit
CJNE
OV
AC
0
X
X
X
X
X
X
X
(I) note that operations on SFR byte address 208 or hit addresses 209-215 (i.e., the PSW or bits in the PSW) will also affect nag settings.
Note on instruction set and addressing modes :
Rn
- Register R7-RO of the currently selected Register Bank
direct
- 8-bit internal data location's address. This could be an Internal Data RAM location (0-127) or a SFR (i.e., 1/0
port, control register, status register, etc. (128-255)).
@Ri
- 8-bit internal data RAM location (0-255) addresses indirectly through register RI or RD.
# data
- 8¥bit constant included in instruction.
# data 16
- 16-bit constant included in instruction.
addr 16
- 16-bit destination address. Used by LCALL & LJMP. Abranch can be anywhere within the 64K-byte Program
memory address space
addr II
- II-bit destination address. Used by ACALL & AJMP. The branch will be within the same 2K-byte page of
program memory as the first byte of the following instruction
reI
- Signed (two's complement) 8-bit offset byte. Used by SJMP and all conditionnal jumps. Range is -128 to +
127 bytes relative to first byte of the following instruction.
bit
- Direct Addressed bit in internal Data RAM or special Function Register.
MATRAMHS
Rev. E (14 Jan. 97)
1.3.15
a
TEMIC
cst Family
Semiconductors
ARITHMETIC OPERATIONS
LOGICAL OPERATIONS
ADDA,Rn
Add register to
Accumulator
ADD A, direct
Add direct byte to
Accumulator
ADD A, @Ri
Add indirect RAM to
Accumulator
ADD A, #data
Add immediate data to
Accumulator
ADDCA, Rn
Add register to
Accumulator with Carry
ADDCA, direct
Add direct byte to
Accumulator with Carry
ADDCA,@Ri
Add indirect RAM to
Accumulator with Carry
ADDCA, #data
Add immediate data to
Ace with Carry
SUBB A, Rn
Subtract Register from
Ace with bonow
12
SUBB A, direct
Subtract direct byte from
Ace with borrow
12
SUBB A, @Ri
Subtract indirect RAM
12
2
2
12
ANLA,Rn
AND Register to
Accumulator
12
ANL A, direct
AND direct byte to
Accumulator
12
ANLA,@Ri
AND indirect RAM to
Accumulator
ANLA,#data
AND immediate data to
Accumulator
ANL direct, A
AND Accumulator to
direct byte
12
ANL direct, #data
AND immediate data to
direct byte
24
ORLA, Rn
OR register to
12
12
12
2
12
12
2
2
12
12
2
12
Accumulator
ORL A, direct
OR direct byte to
Accumulator
ORLA,@Ri
OR indirect RAM to
Accumulator
12
ORLA, #data
OR immediate data to
Accumulator
12
ORL direct, A
OR Accumulator to direct
byte
12
ORL direct, #data
OR immediate data to
24
12
from ACe with borrow
12
2
12
direct byte
SUBB A, #data
Subtract immediate data
from Ace with borrow
12
INCA
Increment Accumulator
12
INCRn
Increment register
12
INC direct
Increment direct byte
2
XRLA,Rn
Exclusive-OR register to
Accumulator
XRL A, direct
Exclusive-OR direct byte
to accumulator
12
XRLA,@Ri
Exclusive-OR indirect
RAM to Accumulator
12
XRLA, #data
Exclusive-OR
immediate data to
Accumulator
12
XRL direct, A
Exclusive-OR
Accumulator to direct
byte
12
XRL direct, #data
Exc1usi ve-OR
immediate data to direct
byte
24
CLRA
Clear Accumulator
12
CPLA
Complement
Accumulator
12
RLA
Rotate Accumulator Left
12
RLCA
Rotate Accumulator Left
through the Carry
12
RRA
Rotate Accumulator
Right
12
RRCA
Rotate Accumulator
Right through the Carry
12
SWAP A
Swap nihbles within the
Accumulator
12
1NC@Ri
Increment direct RAM
12
DEC A
Decrement Accumulator
12
DECRn
Decrement Register
12
DEC direct
Decrement direct byte
12
DEC@Ri
Decrement indirect RAM
12
INC DPTR
Increment Data Pointer
24
MULAB
Multiply A&B
48
DIV AB
Divide A by B
48
DAA
L3,16
Decimal Adjust
Accumulator
12
12
2
12
MATRAMHS
Rev, E (14 Jan, 97)
TEMIC
cst Family
Semiconductors
I,.L,;:·•.·
DESCRIPTION
i.i.···.>.· •.•.
BYTE·OSq L.
PERIOD
DATA TRANSFERT
MaY A,Rn
MNEMONIC
DATA TRANSFERT (continued)
Move Register to
Accumulator
MaY A, direct
Move direct byte to
2
12
XCHA, Rn
Exchange register with
Accumulator
12
XCH A, direct
Exchange direct hyte
with Accumulator
Exchange indired RAM
Accumulator
MaY A, @Ri
Move indirect RAM to
Accumulator
12
XCH A, @Ri
MaY A,#data
Move immediate data to
12
XCHDA,@Ri
12
Move Accumulator to
register
MaY Rn, direct
Move direct byte to
register
24
MaY Rn, #data
Move immediate data to
12
register
12
Move Accumulator to
direct byte
MaY direct, Rn
Move register to direct
2
24
byte
MaY direct, direct
Move direct byte to direct
24
MaY direct, @Ri
Move indirect RAM to
direct byte
24
MaY direct, #data
MaY @Ri,direct
12
12
Exchange lawarder Digit
Move immediate data to
Move Accumulator to
indirect RAM
Move direct by to indirect
2
Move immediate data to
indirect RAM
2
Clear Carry
CLRbit
Clear direct bit
SETB C
Set Carry
SETB bit
Set direct bit
CPLC
Complement Carry
CPLbit
Complement direct bit
ANLC, bit
AND direct bit to Carry
ANLC,/bit
AND complement of
12
2
12
12
2
12
2
12
2
24
12
24
direct bit to Carry
ORLC, bit
OR direct bit to Carry
24
24
ORLC,/bit
OR complement of direct
bit to Carry
24
12
MOYC,bit
Move direct bit to Carry
MaY bit. C
Move Carry to direct bit
2
24
JC rei
Jump if Carry is set
2
24
JNC rei
Jump if Carry not set
2
JB bit, rei
Jump if direct Bit is set
24
24
RAM
MaY @Ri, #data
12
BOOLEAN VARIABLE MANIPULATION
direct byte
MOY@Ri,A
2
indirect RAM with Ace
CLRC
MaY direct, A
12
with Accumulator
Accumulator
MaY Rn, A
DESCRIPTION
12
12
24
MaY DPTR,
#datal6
Load Data Pointer with a
16-bit constant
24
JNB bit, rei
Jump if direct Bit is Not
set
24
MOYCA
@A+DPTR
Move Code byte relative
24
JBC bit, rei
Jump if direct Bit is set &
clear bit
24
MOYCA@A+PC
Move Code byte relative
to PC to Acc
24
MOYXA, @Ri
Move External RAM
24
to DPTR to Ace
(8~bit
MOYXA, @DPTR
addr) to Ace
(16~bit
MOYX@Ri,A
(8~bit
24
addr)
24
Move Acc to External
RAM
PUSH direct
addr) to Ace
Move Ace to External
RAM
MOYX@DPTR.A
24
Move External RAM
(l6~bit
addr)
Push direct byte only
2
24
2
24
stack
POP direct
Pop direct byte from
stack
MATRAMHS
Rev. E (14 Jan. 97)
1.3.17
II
TEMIC
cst Family
Semiconductors
PROGRAM BRANCHING
ACALLK addrll
Absolute Subroutine Call
24
CNJE A, direct, rei
Compare direct byte to
Ace and Jump if Not
Equal
24
CJNE A, #data, reI
Compare immediate to
Acc and Jump if Not
Equal
24
CJNE Rn, #data, reI
Compare immediate to
register and Jump if Not
Equal
24
CJNE @Ri, #data,
reI
Compare immediate to
indirect and Jump if Not
Equal
24
LCALL addr 16
Long Subroutine Call
24
RET
Return from Subroutine
24
RETI
Return from interrupt
AJMPaddr11
Absolute Jump
LJMPaddrl6
Long Jump
24
SJMP reI
Short Jump (relative
addr)
24
DJNZRn, reI
Decrement register and
Jump if Not Zero
JMP@A+DPTR
Jump direct relative to the
DPTR
24
DJNZ direct, reI
Decrement direct byte
and Jump if Not Zero
24
JZ reI
Jump if Accumulator is
zero
2
24
NOP
No Operation
12
JNZ rei
Jump if Accumulator is
2
24
24
2
24
2
24
not Zero
1,3,18
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semic.:onductors
3. Instruction Definitions
ACALL addr 11
Function:
Description:
Example:
Bytes:
Cycles:
Absolute Call
ACALL unconditionally calls a subroutine located at the indicated address. The instruction
increments the PC twice to obtain the address of the following instruction. then pushes the 16-bit
result onto tbe stack (low-order byte first) and increments the Stack Pointer twice. The destination
address is obtained by successively concatenating the five high-order bits of the incremented PC,
opcode bits 7-5, and the second byte of the instruction. The subroutine called must therefore start
within the same 2 K block of the program memory as the first byte of the instruction following
ACALL. No flags are affected.
Initially SP equals 07H. The labs " SUBRTN " is at program memory location 0345 H. After
executing the instruction,
ACALL SUBRTN
at location 0123H, SP will contain 09H, internal RAM locations 08H and 09H will contain 25H and
OIH, respectively, and the PC will contain 0345H.
2
2
10 0 0 t i l a7
Encoding:
la 10 a9 a8
Operation:
ACALL
(PC) ~ (PC) + 2
(SP) ~ (SP) + I
[(SP)] ~ (PC7-0)
(SP) ~ (SP) + 1
[(SP)] ~ (PC15-S)
(PC 10-0) ~ page address
MATRA MHS
Rev. E (14 Jan. 97)
a6
as
a41 a3 a2
at
aO
1
1.3.19
II
TEMIC
cst Family
Semiconductors
ADD a,
Function:
Description:
Example:
Add
ADD adds the byte variable indicated to the Accumulator, leaving the result in the Accumulator. The
carry and auxiliary-carry flags are set, respectively, if there is a carry-out from bit 7 or bit 3, and
cleared otherwise. When adding unsigned integers, the carry flag indicates an overflow occured.
OV is set there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not bit 6 ; otherwise
OV is cleared. When adding signed integers, OV indicates a negative number produced as the sum
of two positive operands, or a positive sum from two negative operands.
Four source operand addressing modes are allowed: register, direct, register-indirect, or immediate.
The Accumulator holds OC3H (I100001lB) and register 0 holds OAAH (I010101OB). The
instruction,
ADDA,RO
will leave 6DH (0110110lB) in the Accumulator with the AC flag cleared and both the carry flag and
OV set to 1.
ADD A, Rn
Byte:
Cycle:
0
o
II
Encoding:
10
Operation:
ADD
(A) f- (A) + (Rn)
ADD A, direct
Bytes:
Cycle:
2
Encoding:
I
Operation:
0
0
o
I
0
r
0
I
II I
direct address
ADD
(A) f- (A) + (direct)
ADD A, @RI
Byte:
Cycle:
0
o
II
Encoding:
10
Operation:
ADD
(A) f- (A) + ((RI))
ADD A, # data
Bytes:
Cycle:
2
Encoding:
10
Operation:
ADD
(A) f- (A) + # data
1.3.20
0
01 0
o
i
I
0
I
Immediate data
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
ADDe A,
Function:
Description:
Example:
Add with Carry
ADDC simultaneously adds the byte variable indicated, the carry flag and the Accumulator contents,
leaving the result in the Accumulator. The carry and auxiliary-carry or bit flags are set, respectively,
if there is a carry-out from bit 7 or bit 3, and cleared otherwise. When adding unsigned integers, the
carry flag indicates an overflow occured.
OV is set if there is a carry-out of bit 6 but not out of bit 7, or a carry-out of bit 7 but not out of bit
6 ; otherwise OV is cleared. When adding signed intergers, OV indicates a negative number produced
as the sum of two positive operands or a positive sum from two negative operands.
Four source operand addressing mode are allowed; register, direct, register-indirect, or immediate.
The Accumulator holds OC3H (lIOOOOIIB) and register 0 holds OAAH (lOIOIOIOB) with the carry
flag set. The instruction,
ADDCA,RO
will leave 6EH (OIIOIIIOB) in the Accumulator with AC cleared and both the Carry flag and OV
set to l.
ADDCA,RN
Byte:
Cycle:
Encoding:
10
Operation:
ADDC
0
1 11
L -_ _ _ _ _ _ _ _L -_ _ _ _ _ _
(A)
f-
r
I
I
I
i
I
0
I
~
(A) + (C) + (Rn)
ADDC A, direct
Bytes:
2
Cycle:
Encoding:
Operation:
10
0
1
I0
0
I
direct address
ADDC
(A) f- (A) + (C) + (direct)
ADDCA,@RI
Byte:
Cycle:
Encoding:
Operation:
1
0
0
1
I0
ADDC
(A) f- (A) + (C) + «Ri))
ADDC A, #data
Bytes:
2
Cycle:
Encoding:
I0
Operation:
ADDC
(A) f- (A) + (C) + # data
0
I0
0
L -_ _ _ _ _ _ _ _L -_ _ _ _ _ _
MATRA MHS
Rev. E (14 Jan. 97)
~
immediate data
1.3.21
II
TEMIC
CSt Family
Semiconductors
AJMP addrll
Function:
Description:
Example:
ADD A, direct
Bytes:
Cycles:
Absolute Jump
AJMP transfers program execution to the indicated address, which is formed at run-time by
concatenating the high-order five bits of the PC (after incrementing the PC twice), opcode bits 7-5,
and the second byte of the instruction. The destination must therefore be within the same 2 K block
of program memory as the first byte of the instruction following AJMP.
The label" JMPADR " is at program memory location 0123H. The instruction,
AJMPJMPADR
is a location 0345H and will load the PC with 01 23H.
2
2
I
a a a
Encoding:
lalo a9
Operation:
AJMP
(PC) r (PC) + 2
(PCIO-O) r page address
a8
0
I
I I
a7
.6 as
a4
1.3
.2 al
aO
I
ANL ,
Function:
Description:
Example:
Logical-AND for byte variables
ANL performs the bitwise logical-AND operation between the variables indicated and stores the
results in the destination variable. No flags are affected. The two operands allow six addressing mode
combinations. When the destination is the Accumulator, the source can use register, direct,
register-indirect, or immediate addressing; when the destination is a direct address, the source can
be the Accumulator or immediate data. Note: When this instruction is used to modify an output port,
the value used as the original port data will be read from the output data latch, not the input pins.
If the Accumulator holds OC3H (110000I1B) and register 0 holds 55H (01010101B) then the
instruction,
ANLA,RO
will leave 41H (OIOOooOIB) in the Accumulator.
When the destination is a directly addressed byte, this instruction will clear combinations of bits in
any RAM location or hardware register. The mask byte determining the pattern of bits to be cleared
would either be a constant contained in the instruction or a value computed in the Accumulator at
run-time. The instruction,
ANL PI, #Ol11001lB
will clear bits 7, 3, and 2 of output port I.
ANLA,Rn
Bytes:
Cycles:
Encoding:
Operation:
ANL A, direct
Bytes:
Cycles:
Encoding:
Operatiou:
I.3.22
1
0
0
I II
r
I
ANL
(A) r (A) /\ (Rn)
2
I
1
0
0
1
I
0
a
1
II
direct address
ANL
(A) r (A) /\ (direct)
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
ANLA, @RI
Byte:
Cycle:
Encoding:
Operation:
ANL
(A) f- (A)
II
((Ri))
A
ANLA,#DATA
Bytes:
2
Cycle:
Encoding:
Operation:
ANL direct, A
Bytes:
Cycle:
Encoding:
Operation:
I0
o
ANL
(A) f- (A)
I
A
I0
o
0
I LI___
o
I LI___
im_m_ed_ia_le_d_a_la_ __
# data
2
I
~_o
ANL
(direct)
f-
1100
(direct)
A
d_i_re_cl_a_dd_r_es_s_ __
(A)
ANL direct, # data
Bytes:
Cycles:
Encoding:
Operation:
3
2 _ _ _-,--_ _- ,
I~0
I
0
1 . 0
f-
(direct)
0
I
I IL _ _-==-_____
direct address
I I
---.!
-===--_____
L __ immediate data
ANL
(direct)
MATRAMHS
Rev. E (14 Jan. 97)
A
# data
1.3.23
TEMIC
cst Family
Semiconductors
ANL C,
Function:
Description:
Example:
ANLC,bit
Bytes:
Cycles:
Logical-AND for bit variables
If the Boolean value of the source bit is logical 0 then clear the carry flag; otherwise leave the carry
t1ag in its current state. A slash (" I ") preceding the operand in the assembly language indicates that
the logical complement of the addressed bit is used as the source value, but the source bit itself is not
affected. No other t1ags are affected.
Only direct addressing is allowed for the source operand.
Set the carry flag if, Pl.O = 1, ACC.7 = 1. and OV = 0 :
MOV C, Pl.O
; LOAD CARRY WITH INPUT PIN STATE
; AND CARRY WITH ACCUM. BIT 7
ANL C, ACC.7
; AND WITH INVERSE OF OVERFLOW FLAG
ANLC,IOV
2
2
II
0
L -________
Operation:
ANL
(C)
ANL C,/bit
Bytes:
Cycles:
f-
I
0
o~0________
o~1
0
Encoding:
(C)
A
b_it_a_d_dr_es_s______
L I_ _ _ _ _ _ _
~
(bit)
2
2
Encoding:
II
Operation:
ANL
(C)
II
0
f-
(C)
A
0
0
0
o
I
bit address
(bit)
CJNE, , rei
Function:
Description:
Example:
1.3.24
Compare and Jump if Not Equal
CJNE compares the magnitudes of the first two operands, and branches if their values are not equal.
The branch destination is computed by adding the signed relative-displacement in the last instruction
byte to the PC, after incrementing the PC to the start of the next instruction. The carry t1ag is set if
the unsigned integer value of is less than the unsigned integer value of ;
otherwise, the carry is cleared. Neither operand is affected.
The first two operands allow four addressing mode combinations : the Accumulator may be
compared with any directly addressed byte or immediate data, and any indirect RAM location or
working register can be compared with an immediate constant.
The Accumulator contains 34H, register 7 contains 56H. The first instruction in the sequence,
CJNE
R7, #60H, NOT_EQ
; R7 =60H
JC
; IFR7 <60H
; R7 >60H
sets the carry t1ag and branches to the instruction at label NOT-EQ. By testing the carry t1ag, this
instruction determines whether R7 is greater or less than 60H.
If the data being presented to Port I is also 34H, then the instruction,
WAIT: CJNE A, PI, WAIT
clears the carry t1ag and continues with the next instruction in sequence, since the Accumulator does
equal the data read from PI. (If some other value was being input on PI, the program will loop at this
point until the PI data changes to 34H).
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
CJNE A, direct, reI
Bytes:
3
Cycles:
2
Encoding:
1'-]-0---]-'-1-0---0-]---'1
Operation:
(PC) ~ (PC) + 3
IF (A) <> (direct)
LI___d_ire_c_la_d_dr_es_s_ _-----'1 LI____re_l._ad_d_rc_ss_'_ _-----'
II
THEN
(PC) ~ (PC) + relative offset
IF (A) < (direct)
THEN
(C)
~
(C)
~O
1
ELSE
CJNE A, # data, reI
Bytes:
3
Cycles:
2
Encoding:
1'1-0--]---'--10--0-0-'1
1
immediate data
rel. address
~-------------'
Operation:
(PC) ~ (PC) + 3
IF (A) <> (data)
THEN
(PC) ~ (PC) + relative offset
IF (A) < data
THEN
(C)
~
1
ELSE
(C)~O
CJNE Rn, # data, reI
Bytes:
3
Cycles:
2
Encoding:
Operation:
1'--,-0---]-,-1-1----r---.1
LI___iffi_ffi_e_di_al_e_da_ta_ _-----'1 LI____re_l._ad_d_re_ss_ _ _-"
(PC) ~ (PC) + 3
IF (Rn) <> data
THEN
(PC) ~ (PC) + relative offset
IF (Rn) < data
THEN
eC)
~
1
~
0
ELSE
(C)
CJNE @Ri, # data, reI
Bytes:
3
Cycles:
2
Encoding:
Operation:
rl-'-O---l---rl-O
-----.1 LI___iffi_ffi_e_di_al_e_da_ta_ _-----'I IL-___rc_l._ad_d_rc_ss_ _ _---'
j
(PC) ~ (PC) + 3
IF (Ri) <> data
THEN
(PC) ~ (PC) + relative offset
IF ((Ri)) < data
THEN
(C)
~
(C)
~O
1
ELSE
MATRAMHS
Rev. E (14 Jan. 97)
1.3.25
TEMIC
cst Family
Semiconductors
CLRA
Function:
Description:
Example:
Bytes:
Cycles:
Clear Accumulator
The Accumulator is cleared (all bits set on zero). No flags are affected.
The Accumulator contains 5CH (OIOIIIOOB). The instruction,
CLRA
Will leave the Accumulator set to OOH (OOOOOOOOB).
I
Encoding:
LI_I___1--,-1_0__0_0-,1
Operation:
CLR
(A) (- 0
CLR bit
Function:
Description:
Example:
Clear bit
The indicated bit is cleared (reset to zero). No other flags are affected. CLR can operate on
the carry flag or any directly addressable bit.
Port 1 has previously been written with 5DH (OlOllIOIB). The instruction,
CLR P1.2
will leave the port set to 59H (OIOllOOlB).
CLRC
Bytes:
Cycles:
Encoding:
IL--l___0_0--,1_o__o___1-,1
Operation:
CLR
(C) (- 0
CLR bit
Bytes:
Cycles:
Encoding:
Operation:
2
II
° °I° °
L -_ _ _ _ _ _ _ _L -_ _ _ _ _ _
°I
~
I
bit address
L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
~
CLR
(bit) (- 0
CPLA
Function:
Descritpion:
Example:
Bytes:
Cycles:
Complement Accumulator
Each bit of the Accumulator is logically complemented (one's complement). Bits which
previously contained a one are changed to a zero and vice-versa. No flags are affected.
The accumulator contains 5CH (OIOIIIOOB). The instruction,
CPLA
will leave the Accumulator set to OA3H (lOIOOOllB).
1
Encoding:
LII____I--'-I_o__o_o-'I
Operation:
CPL
(A) (- (A)
1.3.26
MATRA MHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
CPL bit
Function:
Description:
Example:
Complement bit
The bit variable specified is complemented. A bit which had been a one is changed to zero
and vice-versa. No other flags are affected. CLR can operate on the carry or any directly
addressable bit.
Note: When this instruction is used to modify an output pin, the value used as the original
data will be read from the output data latch, not the input pin.
Port 1 has previously been written with 5BH (OIOIIIOIB). The instruction sequence.
CPL PI.I
CPL Pl.2
will leave the port set to 5BH (010110118).
II
CPLC
Bytes:
Cycles:
Encoding:
11
Operation:
CPL
0
I0
0
1
I0
0
oI
I
(C) f- (C)
CPL bit
Bytes:
Cycles:
2
Encoding:
11
Operation:
CPL
(bit) f- (bit)
MATRAMHS
Rev. E (14 Jan. 97)
0
1
hit address
1.3.27
cst Family
TEMIC
Semiconductors
DAA
Function:
Description:
Example:
Bytes:
Decimal-adjust Accumulator for Addition
DA A adjusts the eight-bit value in the Accumulator resulting from the earlier addition of two
variables (each in packed-BCD format), producing two four-bit digits, Any ADD or ADDC
instruction may have been used to perform the addition,
If Accumulator bits 3-0 are greater than nine (xxxxIOIO-xxxxllll), or if the AC flag is one, six is
added to the Accumulator producing the proper BCD digit in the low-order nibble, This internal
addition would set the carry flag if a carry-out of the low-order four-bit field propagated through all
high-order bits, but it would not clear the carry flag otherwise.
If the carry flag is now set, or if the four high-order bits now exceed nine (lOlOxxxx -III xxxx), these
high-order bits are incremented by six, producing the proper BCD digit in the high-order nibble.
Again, this would set the carry flag if there was a carry-out of the high-order bits, but wouldn't clear
the carry. The carry flag thus indicates if the sum of the original two BCD variables is greater than
100, allowing multiple precision decimal. OV is not affected.
All of this occurs during the one instruction cycle. Essentially, this instruction performs the decimal
conversion by adding OOH, 06H, 60H, or 66H to the Accumulator, depending on initial Accumulator
and PSW conditions.
Note: DA A cannot simply convert a hexadecimal number in the Accumulator to BCD notation, nor
does DA A apply to decimal substraction.
The Accumulator holds the value 56H (OIOIOIlOB) representing the packed BCD digits of the
decimal number 56. Register 3 contains the value 67H (OIlOOllIB) representing the packed BCD
digits of the decimal number 67. The carry flag is set. The instruction sequence.
ADDCA,R3
DA
A
will first perform a standard twos-complement binary addition, resulting in the value OBEH
(10 IIIII 0), in the Accumulator. The carry and auxiliary carry flags will be cleared.
The decimal Adjust instruction will then after the Accumulator to the value 24H (OOIOOIOOB)
indicating the packed BCD digits of the decimal number 24, the low-order two digits of the decimal
sum of 56,67, and the carry-in. The carry flag will set by the Decimal Adjust instruction, indicating
that a decimal overflow occured. The true sum 56,67, and I is 124. BCD variables can be incremented
or decremented by adding 0 IH or 99H. If the Accumulator initially holds 30H (representing the digits
of 30 decimal), then the instruction sequence,
ADD A,#99H
DA A
will leave the carry set and 29H in the Accumulator, since 30 + 99 = 129. The low-order byte of the
sum can be interpreted to mean 30 -I =29.
I
Cycles:
Encoding :1L _1___0__1.. 11_0___0_°-,1
Operation:
1.3.28
DA
- contents of Accumulator are BCD
IF [[(A3 _ 0) > 9J V [(AC) = IlJ
THEN (A3 _ 0) f- (A3 - 0) + 6
AND
IF [[(A7 -4) > 9] V [(C) = I]]
THEN (A7-4) f- (A7-4) + 6
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
DEC byte
Function:
Description:
Example:
Decrement
The variable indicated is decremented by I. An original value of OOH will undertlow to OFFH. No
tlags are affected. Four operand addressing modes are allowed: accumulator, register, direct, or
register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original port data
will be read from the output data latch, not the input pins.
Register 0 contains 7FH (Ol111111B). Internal RAM locations 7 EH and 7FH contain OOH and 40H,
respectively. The instruction sequence.
DEC@RO
DECRO
DEC@RO
will leave register 0 set to 7EH internal RAM locations 7EH and 7FH to OFFH and 3FH.
DEC A
Bytes:
Cycles:
Encoding:
1000110
Operation:
DEC
CA) <- (A) - 1
o
0
I
r
I
1
II
DECRn
Bytes:
Cycles:
Encoding:
I0
Operation:
DEC
CRn) <- (Rn) - 1
DEC direct
Bytes:
Cycles:
0
0
1 11
2
Encoding:
I0
Operation:
DEC
(direct) <- (direct) - 1
0
0
1
I0
o
L ______d_il_·e_cl_a_dd_r_es_s____
~
DEC@RI
Bytes:
Cycles:
Encoding:
Operation:
LIo___o___o__~I_O________i---,1
DEC
((Ri» <- ((Ri» - 1
MATRA MHS
Rev. E (14 Jan. 97)
1.3.29
IJ
TEMIC
cst Family
Semiconductors
DIVAB
Function:
Description:
Example:
Bytes:
Cycles:
Divide
DIV AB divides the unsigned eight-bit integer in the Accumulator by the unsigned eight-bit integer
in register B. The Accumulator receives the integer part of the quotient; register B receives the
integer remainder. The carry and OV flags will be cleared. Exception: If B had originally contained
OOH ; the values returned in the Accumulator and B-register will be undefined and the overflow flag
will be set. The carry flag is cleared in any case.
The Accumulator contains 251 (OFBH or IllllOllB) and B contains 18 (I2H or 000 I00 lOB). The
instruction,
DIVAB
will leave 13 in the Accumulator (ODH or OOOOIlOIB) and the value 17 (IIH or OOOlOOOIB) in B,
since 251 =(13 x 18) + 17. Carry and OV will both be cleared.
I
4
Encoding:
I1
Operation:
DIV
(Ab-8
(- (A)/(B)
0
0
0
I0
o
0
I
(B)7 - 0
DJNZ ,
Function:
Description:
Example:
1.3.30
Decrement and Jump if Not Zero
DJNZ decrements the location indicated by 1, and branches to the address indicated by the second
operand if the resulting value is not zero. An original value of OOH will underflow to OFFH. No nags
are affected. The branch destination would be computed by adding the signed relative-displacement
value in the last instruction byte to the PC, after incrementing the PC to the first byte of the following
instruction.
The location decremented may be a register or directly addressed byte.
Note: When this instruction is used to modify an output port, the value used as the original port data
will be read from the output data latch, not the input pins.
Internal RAM locations 40H, SOH, and 60H contain the values OIH, 70H, and ISH, respectively. the
instruction sequence,
DJNZ 40H, LABEL_l
DJNZ SOH, LABEL_2
DJNZ 60H, LABEL_3
will cause a jump to the instruction at label LABEL2 with the values DOH, 6FH, and ISH in the three
RAM locations. The first jump was not taken because the result was zero.
This instruction provides a simple way of executing a program loop a given number of times, or for
adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. The
instruction sequence,
MOV R2,#8
TOGGLE:
CPL P1.7
DJNZ R2, TOGGLE
will toggle P1.7 eight times, causing four output pulses to appear at bit 7 of output Port 1. Each pulse
will last three machine cycles; two for DJNZ and one to after the pin.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
DJNZRn,rel
Bytes:
Cycles:
2
2
Encoding:
Operation:
r
I
a
reI. address
DJNZ
(PC) ~ (PC) + 2
(Rn) ~ (Rn) - I
IF (RN) > 0 or (Rn) < 0
THEN
(PC) ~ (PC) + rei
DJNZ direct, reI
Bytes:
3
Cycles:
2
Encomng:1r-l-----o---l~I-O------O--l-.1
Operation:
LI______d_il_.ec_.t_a_dd_re_s_s____~1
LI_______r_el_.a_d_dr_e_ss______~
DJNZ
(PC)
~
(PC) + 2
(direct) ~ (direct) - I
IF (direct) > 0 or (direct) < 0
THEN
(PC)
~
(PC) + rei
INC
Function:
Description:
Example:
Increment
INC increments the indicated variable by I. An original value of OFFH will overt1ow to OOH. No t1ags
are affected. There addressing modes are allowed: register, direct, or register-indirect.
Note: When this instruction is used to modify an output port, the value used as the original port data
will be read from the output data latch, not the input pins.
Register 0 contains 7EH (011111110B). Internal locations 7EH and 7FH contain OFFH and 40H,
respectively. The instruction sequence,
INC @RO
INCRO
INC @RO
will leave register 0 set to 7FH and internal RAM locations 7EH and 7FH holding (respectively) OOH
and 41H.
INCA
Bytes:
Cycles:
Encoding:
I0
Operation:
INC
(Al ~ (A) + I
0
0
0
I0
o
0
I
r
I
INCRn
Bytes:
Cycles:
Encoding:
I0
0
0
Operation:
INC
(Rn)
~
(Rn) + I
MATRAMHS
Rev. E (14 Jan. 97)
0
II
1.3.31
TEMIC
cst Family
INC direct
Bytes:
Cycles:
Semiconductors
2
Encoding:
I0
Operation:
INC
(direct)
0
0
f-
o I0
0
1
I
direct address
(direct) + I
INC@RI
Bytes:
Cycles:
Encoding:
Operation:
1000010
INC
«Ri»
f-
il
«Ri» + I
INC DPTR
Function:
Description:
Example:
Bytes:
Cycles:
Increment Data Pointer
Increment the 16-bit data pointer by I.A 16-bit increment (modulo 2 16) is performed; an overflow
of the low-order byte of the data pointer (DPL) from OFFH to OOH will increment the high-order byte
(DPH). No flags are affected.
This is the only 16-bit register which can be incremented.
Registers DPH and DPL contain 12H and OFEH, respectively. The instruction sequence,
INC DPTR
INC DPTR
INC DPTR
will change DPH and DPL to 13H and OlH.
I
2
Encoding:
IL-l_0_ _ _0--,-1_o__o___1--,1
Operation:
INC
(DPTR)
f-
(DPTR) + I
JB bit, rei
Function:
Descritpion :
Example:
1.3.32
Jump if Bit set
If the indicated bit is a one, jump to the address indicated ; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in the
third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The
bit tested is not modified. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data will be
read from the output data latch, not the input pin.
The data present at input port I is llOOlOlOB. The Accumulator holds 56 (OlOlOllOB). The
instruction sequence.
JB PI.2, LABEL I JB ACC.2, LABEL 2
will cause program execution to branch to the instruction at label LABEL 2.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
Bytes:
Cycles:
3
2
Encoding:
I0
Operation:
m
01 0000 1
0
hit address
reI. address
II
(PC) r (PC) + 3
IF (bit) = I
THEN
(PC) r (PC) + reI
JBC bit, rei
Function:
Description:
Example:
Bytes:
Cycles:
Jump if Bit is set and Clear bit
If the indicated bit is a one, branch to the address indicated ; otherwise proceed with the next
instruction. The bit will not be cleared if'it is already a zero. The branch destination is computed by
adding the signed relative-displacement in the third instruction byte to the PC, after incrementing the
PC to the first byte of the next instruction. No flags are affected.
Note: When this instruction is used to test an output pin, the value used as the original data will be
read from the output data latch, not the input pin.
The Accumulator holds 56H (010101 lOB). The instruction sequence,
mc ACC.3, LABEL I
mc ACC.2, LABEL 2
will cause program execution to continue at the instruction identified by the label LABEL2, with the
Accumulator modified to 52H (OIOIOOIOB).
3
2
Encoding:
I
Operation:
mc
0
0
0
I
I
0
0
0
0
I I
bit address
I I
reI. address
(PC) r (PC) + 3
IF (bit) = 1
THEN
(bit) r 0
(PC) r (PC) + reI
JC rei
Function:
Description:
Jump if Carry is set
Example:
If the carry flag is set, branch to the address indicated; otherwise proceed with the next instruction.
The branch destination is computed by adding the signed relative-displacement in the second
instruction byte to the PC, after incrementing the PC twice. No flags are affected.
The carry flag is cleared. The instruction sequence,
Bytes:
Cycles:
JC
LABEL I
CPL C
JC
LABEL 2
will set the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
2
2
Encoding:
Operation:
I0
o
0
I
0
0
0
0
I I'---___
re_'_.a_d_df_es_·s_ _ __
JC
(PC) r (PC) + 2
IF (C) = I
THEN
(PC) r (PC) + reI
MATRA MHS
Rev. E (14 Jan. 97)
1.3.33
TEMIC
cst Family
Semiconductors
JMP@A+DPTR
Function:
Description:
Example:
Bytes:
Cycles:
Jump indirect
Add the eight-bit unsigned contents of the Accumulator with the sixteen-bit data pointer, and load
the resulting sum to the program counter. This will be the address for subsequent instruction fetches.
Sixteen-bit addition is performed (modulo 2'6) : a carry-out from the low-order eight bits propagates
through the higher-order bits. Neither the Accumulator nor the Data Pointer is altered. No flags are
affected.
An even number from 0 to 6 is in the Accumulator. The following sequence of instructions will branch
to one of four AJMP instructions in a jump table starting at JMP-TBL :
MOV
DPTR, #JMP_TEL
JMP
@A+DPTR
JMP_ TBL :
AJMP
LABELO
AJMP
LABELl
AJMP
LABEL2
AJMP
LABEL3
If the Accumulator equals 04H when starting this sequence, execution will jump to label LABEL2.
Remembers that AJMP is a two-byte instruction, so the jump instructions start at every other address.
I
2
Encoding:
ILo____, .1. 1_0_O_ _'-.JI
Operation:
JMP
(PC)
f--
(A) + (DPTR)
JNB bit, rei
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
1.3.34
Jump if Bit not set
If the indicated bit is a zero, branch to the indicated address ; otherwise proceed with the next
instruction. The branch destination is computed by adding the signed relative-displacement in the
third instruction byte to the PC, after incrementing the PC to the first byte of the next instruction. The
bit tested is not modified. No flags are affected.
The data present at input port 1 is 1l00101OB. The Accumulator holds 56H (010101 lOB). The
instruction sequence,
JNB P1.3, LABELl
JNB ACC3, LABEL2
will cause program execution to continue at the instruction at label LABEL2.
3
2
1
0
0
, 10 0 0 0 1
JNB
(PC) f-- (PC) + 3
IF (bit) = 0
THEN (PC)
f--
IL_ _ _ _h_it_a_dd_re_s_s_ _ _-....JI
LI____re_'_.a_d_dr_es_s_ _ _--.J
(PC) + reI
MATRA MHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
JNC reI
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Jump if Carry not set
If the carry flag is a zero, branch to the address indicated; otherwise proceed with the next instruction.
The branch destination is computed by adding the signed relative-displacement in the second
instruction byte to the PC, after incrementing the PC twice to point to the next instruction. The carry
flag is not modified.
The carry flag is set. The instruction sequence,
JNCLABELI
CPLC
JNCLABEL2
will clear the carry and cause program execution to continue at the instruction identified by the label
LABEL2.
2
2
rl-o- - -o--,
'1-0--0--0-0--'1
reI. address
JNC
(PC) (- (PC) + 2
IF (C) = 0
THEN (PC) (- (PC) + rei
JNZ reI
Function:
Description:
Example:
Bytes:
Cycles:
Jump if Accumulator Not Zero
If any bit of the Accumulator is a one, branch to the indicated address; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not
modified. No flags are affected.
The Accumulator originally holds OOH. The instruction sequence,
JNZLABELI
INCA
JNZLABEL2
will set the Accumulator to 0 I H and continue at label LABEL2.
2
2
,I
II
Encoding:
I0
Operation:
JNZ
(PC) (- (PC) + 2
IF (A);tO
THEN (PC) (- (PC) + rei
MArRA MHS
Rev. E (14 Jan. 97)
0
0
0
0
L _ _ _ _f_C'_.a_d_df_CS_'S_ _ _--.J
1.3.35
II
TEMIC
cst Family
Semiconductors
JZ rei
Function:
Description:
Example:
Bytes:
Cycles:
Encoding
Jump if Accumulator Zero
If all bits of the Accumulator are zero, branch to the address indicated; otherwise proceed with the
next instruction. The branch destination is computed by adding the signed relative-displacement in
the second instruction byte to the PC, after incrementing the PC twice. The Accumulator is not
modified. No flags are affected.
The Accumulator originally contains OlH. The instruction sequence.
JZ
LABELl
DEC
A
JZ
LABEL2
will change the Accumulator to OOH and cause program execution at the instruction identified by the
label LABEL2.
2
2
:1 _°_ _ _ _°-'1_°__°_°__°- -'1
Operation:
L
JZ
(PC) ~ (PC) + 2
IF (A) =0
THEN (PC)
~
reI. address
(PC) + reI
LCALL addr16
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Long call
LCALL calls a subroutine located at the indicated address. The instruction adds three to the program
counter to generate the address of the next instruction and then pushes the 16-bit result onto the stack
(low byte first), incrementing the Stack Pointer by two. The high-order and low-order bytes of the
PC are then loaded, respectively, with the second and third bytes of the LCALL instruction. Program
execution continues with the instruction at this address. The subroutine may therefore begin
anywhere in the full 64K-byte program memory address space. No flags are affected.
Initially the Stack Pointer equals 07H. The label " SUBRTN " is assigned to program memory
location 1234H. After executing the instruction,
LCALL SUBRTN
at location 0123H, the Stack Pointer will contain 09H, internal RAM locations 08H and 09H will
contain 26H and OIR, and the PC will contain 1235H.
3
2
1° ° ° I 1° °
°
1
ad_d_rl_5_-a_dd_r_8_ _-----.!
L I_ _ _ _
addr7 -addrO
LCALL
(PC) ~ (PC) + 3
(SP) ~ (SP) + I
((SP» ~ (PC7-0)
(SP) ~ (SP) + 1
((SP» ~ (SPI5 - 8)
(PC) ~ addf) 5 -
°
1.3.36
MATRA MHS
Rev. E (14 Jan. 97)
TEMIC
cst Family
Semiconductors
LJMP addr16
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Long Jump
LJMP causes an unconditional branch to the indicated address, by loading the high-order and
low-order bytes of the PC (respectively) with the second and third instruction bytes. The destination
may therefore be anywhere in the full 64K program memory address space. No flags are affected.
The label " JMPADR " is assigned to the instruction at program memory location 1234H. The
instruction,
LJMPJMPADR
at location 0 123H will load the program counter with 1234H.
3
2
rl-o-o--o--o'l-o--o---o-'1
-'1
IL_ _ _a_d_df_I_5-_ad_d_fs_ _ _
LI____ad_d_f7_"_ad_d_fo_ _ _- '
LJMP
(PC) f- addrlS"O
MOV ,
Function:
Description:
Example:
Move byte variable
The byte variable indicated the second operand is copied into the location specified by the first
operand. The source byte is not affected. No other register or flag is affected.
This is by far the most flexible operation. Fifteen combinaisons of source and destination addressing
modes are allowed.
Internal RAM location 30H holds 40H. The value of RAM location 40H is IOH. The data present at
input port I is I 100 10 lOB (OCAH).
MOY
RO, #30H
; RO <= 30h
MOY
A, @ RO
; A <= 40H
MOY
RI,A
;RI<=40h
MOY
R,@RI
;B<=lOh
MOY
@RI,PI
; RAM (40H) <= OCAH
MOY
P2, PI
; P2 # OCAH
leaves the value 30H in register 0,40H in both the Accumulator and register I,IOH in register B, and
OCAH (I 100 10 lOB) both in RAM location 40H and output on port 2.
MOYA,Rn
Bytes:
Cycles:
Encoding:
11
Operation:
MOY
(A) f- (Rn)
° 11
f
I
*MOY A,direct
Bytes:
2
Cycles:
Encoding:
II
o
I0
0
1
I
direct address
Operation:
MOY
(A) f- (direct)
*MOY A, ACC is not valid instruction.
MATRAMHS
Rev. E (14 Jan. 97)
1.3.37
II
TEMIC
cst Family
Semiconductors
MOVA,@RI
Bytes:
Cycles:
01 0
Encoding:
11
Operation:
MOV
(A) ~ (Ri)
i
I
MOV A, # data
Bytes:
2
Cycles:
1I0
Encoding:
10
Operation:
MOV
CA) ~#data
0
oI
immediate data
MOVRn,A
Bytes:
Cycles:
Encoding:
11
Operation:
MOV
(Rn) ~ (A)
111
r
I
o 11
r
I
r
I I
MOV Rn, direct
Bytes:
2
Cycles:
2
Encoding:
11 0
Operation:
MOV
(Rn) ~ (direct)
direct addr.
MOV Rn, # data
Bytes:
2
Cycles:
1I
Encoding:
10
Operation:
MOV
(Rn) ~#data
immediate data
MOV direct, A
Bytes:
2
Cycles:
1I0
Encoding:
11
Operation:
MOV
(direct)
~
0 1I I
direct address
I I
direct address
(A)
MOV direct, Rn
Bytes:
2
Cycles:
2
Encoding:
11
Operation:
MOV
(direct)
1.3.38
0
0
~
o 11
r
(Rn)
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
MOV direct, direct
Bytes:
3
Cycles:
2
Encoding:
II
Operation:
MOV
(direct)
0
0
f-
0
1
0
o
I
I ~I______
d_il_-.a_d_dr_._(S_rr_)____~1
~I
______
d_ir_.a_d_dr_.(_d_cs_t)____~
(direct)
MOV direct, @ Ri
Bytes:
2
2
Cycles:
I0
Encoding:
II
Operation:
MOV
(direct) f- (Ri)
0
0
o
i
I I
direct addr.
MOV direct, # data
Bytes:
3
Cycles:
2
Encoding:
Operation:
1
I I0
0
MOV
(direct)
f-
0
II
direct address
immediate data
# data
MOV@Ri,A
Bytes:
Cycles:
Encoding:
Operation:
LII___---"-I_O___i-.J1
MOV
«Ri» f- (A)
MOV @ Ri, direct
Bytes:
2
Cycles:
2
Encoding:
Operation:
II
0
0
I0
L -_ _ _ _ _ _ _ _L -_ _ _ _ _ _
i
I
direct addr.
i
I
immediate data
~
MOV
«Ri» f- (direct)
MOV @ Ri*, data
Bytes:
2
Cycles:
Encoding:
Operation:
I0
I I0
L -_ _ _ _ _ _ _ _L -_ _ _ _ _ _
~
MOV
«Ri» f- # data
MATRA MHS
Rev. E (14 Jan. 97)
1.3.39
II
TEMIC
cst Family
Semiconductors
MOV ,
Function:
Description:
Example:
MOVC,bit
Bytes:
Cycles:
Encoding:
Operation:
More bit data
The Boolean variable indicated by the second operand is copied into the location specified by the
first operand. One of the operands must be the carry flag; the other may be any directly addressable
bit. No other register or flag is affected.
The carry flag is originally set. The data present at input Port 3 is 1I000101B. The data previously
written to output Port I is 35H (OOIlOIOIB).
MOV
PI.3,C
MOV
C,P3.3
MOV
PI.2,C
will leave the carry cleared and change Port I to 39H (00111001B).
2
°
MOV
II
(C)
MOVbit, C
Bytes:
Cycles:
2
2
Encoding:
II
Operation:
~
°
bit address
°
°
bit
(bit)
°°
MOV
(bit)
° 10 °
~
10
address
(C)
MOV DPTR, # data 16
Function:
Description:
Example:
Bytes:
Cycles:
Load Data Pointer with a 16-bit constant
The Data Pointer is loaded with the 16-bit constant indicated. the 16-bit constant is loaded into the
second and third bytes of the instruction. The second byte (DPH) is the high-order byte, while the
third byte (DPL) holds the low-order byte. No flags are affected.
This is the only instruction which moves 16-bits of data at once.
The instruction,
MOV DPTR, 1234H
will load the value 1234H into the Data Pointer: DPH will hold 12H and DPL will hold 34H.
3
2
Encoding:
LI_I_o__o_---'I_o__o__o_o-.J
Operation:
MOV
(DPTR) ~ # datals_o
DPH DPL ~ # datals_8 # data7_o
1.3.40
i_ill_ill_ed_._d_at_a_IS_-_8_ _-.J1
L -_ _
1L-_ _l_·ill_ill_e_d_.d_a_ta_7_-o_ _~
MATRA MHS
Rev. E (14 Jan. 97)
TEMIC
Semiconductors
CS1 Family
Move A, @ A +
Function:
Descriptiou :
Example:
Move Code byte
The MOVC instructions load the Accumulator with a code byte, or constant from program memory.
The address of the byte fetched is the sum of the original unsigned eight-bit. Accumulator contents
and the contents of a sixteen-bit base register, which may be either the Data Pointer or the Pc. In the
latter case, PC is incremented to the address of the following instruction before being added with the
Accumulator ; otherwise the base register is not altered. Sixteen-bit addition is performed so a
carry-out from the low-order eight bits may propagate through higher-order bits. No flags are
affected.
A value between 0 and 3 is in the Accumulator. The following instructions will translate the value
in the Accumulator to one of four values defined by the DB (define byte) directive.
RELPC:
INC
A
MOVC
A, @ A + PC
RET
DB
66H
CB
77H
CB
88H
DB
99H
If the subroutine is called with the Accumulator equal to OIH, it will return with 77H in the
Accumulator. The INC A before the MOVC instruction is needed to " get around " the RET
instruction above the table. If several bytes of code separated the MOVC from the table, the
corresponding number would be added to the Accumulator instead.
MOVC A, @ A + DPTR
Bytes:
I
Cycles:
2
Encoding:
'1-1-0--0---'1-0--0---1-'1
Operation:
MOVC
(A) +-- «A) + (DPTR))
MOVC A, @ A + PC
Bytes:
Cycles:
2
Encoding : 1,.-1-0--0--0'1-0
- -0-----.
Operation:
MOVC
(PC) +-- (PC) + I
(A) +-- «A) + (PC))
MATRA MHS
Rev. E (14 Jan. 97)
1.3.41
a
TEMIC
cst Family
Semiconductors
MOVX ,
Function:
Description:
Example:
Move External
The MOVX instructions transfer data between the Accumulator and a byte of external data memory,
hence the "X" appended to MOY. There are two types of instructions, differing in whether they
provide an eight-bit or sixteen-bit indirect address to the external data RAM.
In the first type, the contents of RO or RI in the current register bank provide an eight-bit address
multiplexed with data on PO. Eight bits are sufficient for external I/O expansion decoding or for a
relatively small RAM array. For somewhat larger arrays, any output port pins can be used to output
higher-order address bits. These pins would be controlled by an output instruction preceding the
MOVX.
In the second type of MOVX instruction, the Data Pointer generates a sixteen-bit address. P2 outputs
the high-order eight address bits (the contents of DPH) while PO multiplexes the low-order eight bits
(DPL) with data. The P2 Special Function Register retains its previous contents while the P2 output
buffers are emitting the contents of DPH. This form is faster and more efficient when accessing very
large data arrays (up to 64K bytcs), since no additional instructions are needed to set up the output
ports.
It is possible in some situation to mix the two MOVX types. A large RAM array with its high-order
address lines driven by P2 can be addressed via the Data Pointer, or with code to output high-order
address bits to P2 followed by a MOVX instruction using RO or Rl.
An external 256 byte RAM using multiplexed address/data lines is connected to the 80C51 Port O.
Port 3 provides control lines for the external RAM. Ports 0 and 2 are used for normal 110. Registers
o and I contain 12H and 34H. Location 34H of the external RAM holds the value 56H. The instruction
sequence
MOVX
A,@RI
MOVX
@RO,A
copies the value 56H into both the Accumulator and external RAM location 12H.
MOVXA,@Ri
Bytes:
1
Cycles:
2
Encoding:
Operation:
11
0
10
0
i
I
1
I
0
0
i
I
10
0
0
01
0
0
o
MOVX
(A) f- ((Ri»
MOVX@Ri,A
Bytes:
I
Cycles:
2
Encoding:
Operation:
11
MOVX
((Ri» f- (A)
MOVX A, @ DPTR
Bytes:
I
Cycles:
2
Encoding:
Operation:
II
0
MOVX
(A) f- ((DPTR»
MOVX @ DPTR, A
Bytes:
I
Cycles:
2
Encoding:
Operation:
1.3.42
II
I
I
0
I
MOVX
(DPTR) f- (A)
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CS1 Family
Semiconductors
MULAB
Function:
Description:
Example:
Bytes:
Cycles:
Multiply
MUL AB mUltiplies the unsigned eight-bit integers in the Accumulator and register B. The low-order
byte of the sixteen-bit product is left in the Accumulator, and the high-order byte in B. If the product
is greater than 255 (OFFH) the overflow flag is set; otherwise it is cleared. The carry flag is always
cleared.
Originally the Accumulator holds the value 80 (50H). Register B holds the value 160 (OAOH). The
instruction,
MULAB
will give the product 12,800 (3200H), so B is changed to 32H (001100IOB) and the Accumulator is
cleared. The overflow flag is set, carry is cleared.
I
4
Encoding:
LI_l_O___o-,I_O___O_0-.J1
Operation:
MOL
(Ah _of- (A) x (B)
(B)15-8
NOP
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
No Operation
Execution continue at the following instruction. Other than the PC, no registers or flags are effected.
It is desired to produce a low-going output pulse on bit 7 of Port 2 lasting exactly 5 cycles. A simple
SETB/CLR sequence would generate a one-cycle pulse, so four additional cycles must be inserted.
This may be done (assuming no interrupts are enable) with the instruction sequence.
P2.7
CLR
Nap
Nap
Nap
Nap
SETP
P2.7
1
I°
° ° ° I° ° ° ° I
Nap
(PC) f- (PC) + 1
MATRA MHS
Rev. E (14 Jan. 97)
1.3.43
1
TEMIC
cst Family
Semiconductors
ORL
Function:
Description:
Example:
Logical-OR for byte variables
ORL perfonns the bitwise logical-OR operation between the indicated variables, storing the results
in the destination byte, No flags are affected. The two operands allow six addressing mode
combinaisons. When the destination is the Accumulator, the source can use register, direct,
register-indirect, or immediate addressing; when the destination is a direct address, the source can
be the Accumulator or immediate data. Note: When this instruction is used to modify an output port,
the value used as the original port data will be read from the output data latch, not the input pins.
If the Accumulator holds OC3H (11000011 B) and RO holds 55H (OlOlOlOIB) then the instruction,
ORLA,RO
will leave the Accumulator holding the value OD7H (l1OlOllIB).
When the destination is a directly addressed byte, the instruction can set combinations of bits in any
RAM location or hardware register. The pattern of bits to be set is determined by a mask byte, which
may be either a constant data value in the instruction or a variable computed in the Accumulator at
run-time. The instruction.,
ORL PI, # 001 100 lOb
will set bits 5, 4, and I of output Port 1.
ORLA, Rn
Bytes:
Cycles:
Encoding:
Operation
° ° 11
I°
rI
ORL
(A) ~ (A) V (Rn)
ORL A, direct
Bytes:
Cycles:
2
I
Encoding:
10
Operation:
ORL
(A) ~ (A) V (direct)
° ° 10
°
1I I
direct address
ORLA,@ Ri
Bytes:
Cycles:
Encoding:
LI0___0_0...LI_o___i-!1
Operation:
ORL
(A)
~
(A) V ((Ri))
ORLA,#data
Bytes:
2
Cycles:
I
Encoding:
Operation:
I~o---o-o--rl-o---o--o-"'I
ORL direct, A
Bytes :
Cycles:
2
I
Encoding:
10
Operation:
ORL
(direct) ~ (direct) V (A)
1.3.44
LI___iffi_ffi_e_d_ia_te_d_a_t.__---'
ORL
(A) ~ (A) V # data
° ° 10 °
°I
direct address
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
ORL direct, # data
Bytes:
3
Cycles:
2
Encoding:
Operation:
L°______o__o~l_o___o_____I_"11
d_ir_e_ct_a_dd_re_s_s____~1
L ______
LI______im__m_ed_ia_te_d_a_ta____~
ORL
(direct) <- (direct) V # data
ORL C,
Function:
Description:
Example:
ORLC, bit
Bytes :
Cycles:
Encoding:
Operation:
Logical-OR for bit variable
Set the carry flag if the Boolean value is a logical I ; leave the carry in its current state otherwise.
A slash (" I ") preceding the operand in the assembly language indicates that the logical complement
of the addressed bit is used as the source value, but the source bit it self is not affected. No other flags
are affected.
Set the carry flag if and only if PI.O = I, ACC. 7 = 1, or OV =0 :
MOV
C, P1.0
; LOAD CARRY WITH INPUT PIN PIO
ORL
C, ACC.7
; OR CARRY WITH THE ACe. BIT7
ORL
C/OV
; OR CARRY WITH THE INVERSE OF OV
2
2
10
10
ORL
°
°I I
bit address
(C) <- (C) V (bit)
ORL C,lbit
Bytes :
Cycles:
Encoding:
Operation:
2
2
II °
ORL
°I° ° ° °
bit address
(C) <- (C) V (bit)
POP direct
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Pop from stack.
The contents of internal RAM location addressed by the Stack Pointer is read, and the Stack Pointer
is decremented by one. The value read is then transferred to the directly addressed byte indicated.
No flags are affected.
The Stack Pointer originally contains the value 32H, and internal RAM locations 30H through 32H
contain the values 20H, 23H, and OIH, respectively. The instruction sequence,
POPDPH
POPDPL
will leave the Stack Pointer equal to the value 30H and the Data Pointer set to 0123H. At this point
the instruction, POP SP
will leave the Stack Pointer set to 20H. Note that in this special case the Stack Pointer was
decremented to 2FH before being loaded with the value popped (20H)
2
2
LI_I___o_I--'...I_o_o__o_o--,1
direct address
POP
(direct) <- «SP))
(SP) <- (SP) - 1
MATRA MHS
Rev. E (14 Jan. 97)
1.3.45
II
TEMIC
cst Family
Semiconductors
PUSH direct
Function:
Description:
Example:
Bytes:
Cycles:
push onto stack.
The Stack Pointer is incremented by one. The contents fo the indicated variable is then copied into
the internal RAM location addressed by the Stack Pointer. Otherwise no flags are affected.
On entering interrupt routine the Stack Pointer contains 09H. The Data Pointer holds the value
0123H. The instruction sequence,
PUSHDPL
PUSHDPH
will leave the Stack Pointer set to OBH and store 23H and OIH in internal RAM location OAH and
OBH, respectively.
2
2
Encoding:
1.. 1_1___0__0. . 1_0
. __0__0_0-,1
Operation:
PUSH
(SP) f- (SP) + I
«SP)) f- (direct)
direct address
RET
Function:
Description:
Example:
Bytes:
Cycles:
Encoding:
Operation:
Return from subroutine
RET pops the high-and low-order bytes of the PC successively from the stack, decrementing the
Stack Pointer by two. Program execution continues at the resulting address, generally the instruction
immediately following en ACALL or LCALL. No flags are affected.
The Stack Pointer originally contains the value OBH. Internal RAM locations OAH and OBH contain
the values 23H, and OIH, respectively. The instruction,
RET
will leave the Stack Pointer equal to the value 09H. Program execution will continue at location
0123H.
I
2
10
°
RET
01
0
°
°
(PCIS _8) f- «SP))
(SP) f- (SP) - I
(PC7-0) f- «SP))
(SP) f- (SP) - I
RETI
Function:
Description:
Example:
1.3.46
Return from interrupt
RET! pops the high-and low-order bytes of the PC successively from the stack, and restores the
interrupt logic to accept additional interrupts at the same priority level as the one just processed. The
Stack Pointer is left decremented by two. No other registers are affected ;the PSW is not
automatically restored to its pre-interrupt status. Program execution continues at the resulting
address, which is generally the instruction immediately after the point at which the interrupt request
was detected. If a lower-or-same-level interrupt had been pending when the RET! instruction is
executed, that one instruction will be executed before the pending interrupt is processed.
The Stack Pointer originally contains the value OBH. An interrupt was detected during the instruction
ending at location 0122H. Internal RAM locations OAH and OBH contain the values 23H and OIH,
respectively. The instruction,
RETI
will leave the Stack Pointer equal to 09H and return program execution to location 0123H.
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
Semiconductors
Bytes:
Cycles:
Encoding:
Operation:
cst Family
2
-0-0---1-'1-0- 0- - -0-'1
rl
RET!
(PCIS _8) f- «SP»
(SP) f- (SP) - I
(PC7 _ 0) f- «SP»
(SP) f- (SP) I
II
RLA
Function:
Description:
Example:
Bytes:
Cycles:
Rotate Accumulator Left
The eight bits in the Accumulator are rotated one bit to the left. Bit 7 rotated into the bit 0 position.
No flags are affected.
The Accumulator holds the value OC5H (11000101 B). The instruction,
RLA
leaves the Accumulator holding the value 8BH (lOOOOIOIIB) with the carry unaffected.
I
Encoding:
LI0_ _
0 __
0....LI_o_o_ _'.....J1
Operation:
RL
(An + 1)f-(An)n=0-6
(AO) f- (A7)
RLCA
Function:
Description:
Example:
Bytes:
Cycles:
Rotate Accumulator Left through the Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the left. Bit 7 moves
into the carry flag; the original state of the carry flag moves into the bit 0 position. No other flags
are affected.
The Accumulator holds the value OC5H (llOOOlOIB), and the carry is zero. The instruction,
RCLA
leaves the Accumulator holding the value 8BH (lOOOIOlOB) with the carry set.
I
I
Encoding:
LI0_ _
0 _ _I....LI_o_o_ _I.. . J1
Operation:
RLC
(An + I) f- (An) n = 0 - 6
(AO) f- (C)
(C) f- (A7)
MATRA MHS
Rev. E (14 Jan. 97)
1.3.47
CS1 Family
TEMIC
Semiconductors
RRA
Function:
Description:
Example:
Bytes:
Cycles:
Rotate Accumulator Right
The eight bits in the Accumulator are rotated one bit to the right. Bit 0 is rotated into the bit 7 position.
No flags are affected.
The Accumulator holds the value OC5H (lIOOOIOIB). The instruction,
RRA
leaves the Accumulator holding the value OE2H (II 1000 lOB) with the carry unaffected.
I
I
Encoding:
rl-o-o--o--o'l-o--o-----,
Operation:
RR
(An)
(A7)
ff-
(An + I) n =0 - 6
(AO)
RRCA
Function:
Description:
Example:
Bytes:
Cycles:
Rotate Accumulator Right through Carry flag
The eight bits in the Accumulator and the carry flag are together rotated one bit to the right. Bit 0
moves into the carry flag; the original value of the carry flag moves into the bit 7 position. No other
flags are affected.
The Accumulator holds the value OC5H (llOOOlOlB), and the carry is zero. The instruction,
RRCA
leaves the Accumulator holding the value 62 (01 1000 lOB) with the carry set.
I
Encoding:
,-1_0_0__0_-->1_0__0_ _ _1->1
Operation:
RRC
(An) f- (An + 1)n = 0 - 6
(A7) f- (C)
(C) f- (AO)
1.3.48
MATRA MHS
Rev. E (14 Jan. 97)
TEMIC
CSt Family
Semiconductors
SETB
Function:
Description:
Example:
Set bit
SETB sets the indicated bit to one. SETB can operate on the carry flag or any direct addressable bit.
No other flags are affected.
The carry flag is cleared. Output Port I has been written with the value 34H (001 10 IOOB). The
instructions,
SETB C
SETB Pl.O
will leave the carry flag set to 1 and change the data output on Port I to 35H (OOIIOIOIB).
SETBC
Bytes:
Cycles:
Encoding:
11
Operation:
SETB
(C) <-- I
SETB bit
Bytes:
Cycles:
0
1
I0
0
1
I
0
1
I0
0
o
I I
2
Encoding:
11
Operation:
SETB
(bit) <-- I
bit address
SJMP rei
Function:
Description:
Example:
Bytes:
Cycles:
Short Jump
Program control branches unconditionally to the address indicated. The branch destination is
computed by adding the signed displacement in the second instruction byte to the PC, after
incrementing the PC twice. Therefore, the range of destinations allowed is from 128 bytes preceding
this instruction to 127 bytes following it.
The label "RELADR" is assigned to an instruction at program memory location 0123H. The
instruction,
SJMPRELADR
will assemble into location 0l00H. After the instruction is executed, the PC will contain the value
0123H.
(Note: Under the above conditions the instruction following SJMP will be at 102H. therefore, the
displacement byte of the instruction will be the relative offset (0123H - 0102H) = 21H. Put another
way, an SJMP with a displacement of OFEH would be an one-instruction infinite loop).
2
2
Encoding:
1100010000
Operation:
SJMP
(PC) <-- (PC) + 2
(PC) <-- (PC) + rei
MATRA MHS
Rev. E (14 Jan. 97)
reI. address
1.3.49
II
TEMIC
cst Family
Semiconductors
SETB
Function:
Description:
Example:
Subtract with borrow
SUBB subtracts the indicated variable and the carry flag together from the Accumulator, leaving the
result in the Accumulator. SUBB sets the carry (borrow) flag if a borrow is needed for bit 7, and clears
C otherwise. (If C was set before executing a SUBB instruction, this indicates that a borrow was
needed for the previous step in a multiple precision substraction so the carry is subtracted from the
Accumulator along with the source operand). AC is set if a borrow is needed for bit 3, and cleared
otherwise. OV is set if a borrow is needed into bit 6, but not into bit 7, or into bit 7, but not bit 6. When
subtracting signed integers OV indicates a negative number produced when a negative value is
subtracted from a positive value, or a positive result when a positive number is subtracted from a
negative number. The source operand allows four addressing modes : register, direct,
register-indirect, or immediate.
The Accumulator holds OC9H (llOOIOOIB), register 2 holds 54H (OIOIOIOOB), and the carry flag
is set. the instruction,
SUBBA,R2
will leave the value 74H (OillOIOOB) in the accumulator, with the carry flag and AC cleared but OV
set.
Notice that OC9H minus 54H is 75H. The difference between this and the above result is due to the
carry (borrow) flag being set before the operation. If the state of the carry is not known before starting
a single or multiple-precision substraction, it should not be explicity cleared by a CLRC instruction.
SUBBA, Rn
Bytes:
Cycles:
1 11
Encoding:
11
Operation:
SUBB
(A) <-- (A) - (C) - (Rn)
0
0
r
I
SUBB A, direct
Bytes:
2
Cycles:
1I0
Encoding:
11
Operation:
SUBB
(A) <-- (A) - (C) - (direct)
0
0
0
1[
I
direct address
SUBBA,@Ri
Bytes:
Cycles:
Encoding:
[I
Operation:
SUBB
(A) <-- (A) - (C) - (Ri)
0
0
J [ 0
i
I
SUBB A, # data
2
Bytes:
Cycles:
1
1 [0
Encoding:
[I
Operation:
SUBB
(A) <-- (A) - (C) - # data
1.3.50
0
0
0
0
immediate data
MATRAMHS
Rev. E (14 Jan. 97)
TEMIC
C5t Family
Semiconductors
SWAP A
Function:
Description:
Example:
Bytes:
Cycles:
Swap nibbles within the Accumulator
SWAP A interchanges the low-and high-order nibbles (four-bit fields) of the Accumulator (bits 3 - 0
and bits 7 - 4). The operation can also be thought of a four-bit rotate instruction. No flag are affected.
The Accumulator holds the value OC5H (lIOOOIOIB). The instruction,
SWAP A
leave the Accumulator holding the value 5CH (OIOIIIOOB).
I
Encoding:
LI_l___O__
o--,l_o___o_o-,
Operation:
SWAP
(A 3o ) ~ (A'_4)
XCH A,
Function:
Description:
Example:
Exchange Accumulator with byte variable
XCH loads the Accumulator with the contents of the indicated variable, at the same time writing the
original Accumulator contents to the indicated variable. The source/destination operand can use
register, direct, or register-indirect addressing.
RO contains the addres 20H. The Accumulator holds the value 3FH (OOllllIIB). Internal RAM
location 20H holds the value 75H (OIIIOIOIB). The instruction,
XCHA,@RO
will leave RAM location 20H holding the values 3FH (001 II IllB) and 75H (OlllOIOIB) in the
Accumulator.
XCHA,Rn
Bytes:
Cycles:
Encoding:
11
Operation:
XCH
° ° 11
r
I
(A)~(Rn)
XCH A, direct
Bytes :
2
Cycles:
Encoding:
11
Operation:
XCH
° ° 10
° I I
1
direct address
(A) ~ (direct)
XCHA,@Ri
Bytes:
Cycles:
MATRAMHS
Rev. E (14 Jan. 97)
1.3.51
II
TEMIC
Semiconductors
Section II
Product Information
Product Selection .•.••.••••.•...•••••..•......•.........•...••.••.•..•..•• 11.1.0
CSI General Purpose Products. . • • . • • • • • . • • • . • . • • • . . • • . . • . • • . • • • • • • • • • • • . • •• 11.2.0
CSI Computer/Communication Products ..•••.•.•••..••..•.•..••••.•.••••.••• 11.7.0
CSI Automotive Products .........•.....•...............•..••••••••••••.••• 11.9.0
TEMIC
Semiconductors
B
Product Selection
Product by Application Domain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11.1.1
Products/Peripheral Selection Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11.1.2
Military and Space Products. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 11.1.5
TEMIC
Product Selection
Semiconductors
Products by Application Domain
General Purpose C51 Microcontrollers:
• TSC80C31 I TSC80C51
• TSC80CL31 I TSC80CL51
• 80C32 I 80C52
General Purpose C51 Microcontrollers:
• TSC80C31 I TSC80C51
• TSC80CL31 I TSC80CL51
• 80C32 I 80C52
•
80C154/83C154
•
80C154/83C154
•
83C154D
•
83C154D
Extended 8-bit TSC8025I Microcontrollers:
• TSC80251 Gl
• TSC80251G2 (2)
B
Dedicated C51 Microcontrollers:
• TSC805lAIl/TSC875lAll (I)
• TSC805lA30 I TSC875lA30 (I)
• TSC805lAI/TSC8751Al (I)
• TSC805lA21 TSC875lA2 (I)
Extended 8-bit TSC8025I Microcontrollers:
• TSC8025I Al
• TSC8025lA2 (2)
• TSC80251All (2)
General Purpose C51 Microcontrollers:
• TSC80C31 I TSC8OC51
• TSC80CL31 I TSC80CL51
• 8OC32 I 80C52
•
80C154/83C154
•
83C154D
General Purpose C51 Microcontrollers:
• TSC80C31 I TSC80C51
• TSC8OCL31 I TSC80CL51
• 80C32 I 80C52
• 80Cl54/83Cl54
• 83Cl54D
Dedicated Microcontrollers:
• TSC8051Cl
• TSC8051C2 (I)
Extended 8-bit TSC80251 Microcontrollers:
• TSC8025lGI
• TSC8025I G2 (2)
General Purpose C51 Microcontrollers:
• TSC80C31 I TSC80C51
• TSC80CL31 I TSC80CL51
•
80C32/8OC52
•
•
80Cl54/83Cl54
83Cl54D
General Purpose C5lMicrocontrollers:
• TSC8OC31 I TSC80C51
• TSC8OCL31 I TSC80CL51
• 80C32 I 80C52
• 80Cl54/83Cl54
• 83Cl54D
Dedicated C51 Microcontrollers:
• TSC805lAll /TSC8751All (1)
• TSC805lAI/TSC875lAI (I)
Extended 8-bit TSC8025I Microcontrollers:
• TSC8025I Gl
• TSC8025lG2 (2)
(I)
(2)
Available during 1997. Please check with your TEMIC sales office.
Planned.
MATRAMHS
Rev. A (14 Jan. 97)
II.l.1
TEMIC
Product Selection
Semiconductors
ProductslPeripheral Selection Tables
CS1 8-bit Microcontrollers Selection Table
General Purpose - Very Low Voltage: 1.8 Volt
-NEW-
TSC80CL31
Application Specific Microcontrollers
TSC8751C2
Q2-97
4K
OTP
256
16
32
UART
TSC8051All
98
24K
512
20
48
UART, SPI,
11.1.2
~Wire
2
•
2+CCU
•
12x 8-bit PWM
•
CAN2.0B
controller
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
Product Selection
Semiconductors
Application Specific Microcontrollers (continued)
TSC8751All
Q3-97
24K
OTP
512
20
48
UART, SPI,
~Wire
2+CCU
•
•
CAN 2.0B
•
•
VAN controller
TSC8051A30
98
16 K
256
20
32
UART, SPI,
~Wire
2+CCU
TSC8751A30
Q4-97
16 K
OTP
256
20
32
UART, SPI,
~Wire
2+CCU
•
•
TSC805IAI
98
24 K
512
20
48
UART, SPI,
~Wire
2+CCU
•
•
TSC8751Al
Q3-97
24 K
OTP
512
20
48
UART, SPI,
~Wire
2+CCU
•
•
TSC8051A2
98
16K
256
20
32
UART, SPI,
~Wire
2+CCU
Q4-97
16 K
OTP
256
20
32
UART, SPI,
~Wire
2+CCU
•
•
•
TSC8751A2
Abbreviations
SPI: Serial Peripheral Interface
PWM: Pulse Width Modulation
r2c: Inter-Integrated Circuit Communication Bus
WD: Watchdog Timer
ADC: Analog-to-Digital Converter
control1er
VAN controller
•
SR: Secret ROM
encrypted ROM option to secure the ROM against piracy.
ST: Secret Tag
a 64-Bit identifier can be customized in order to serialize each
microcontroller with a unique number.
PMU: Pulse Measurement Unit
CCU: 8 channels input Capture, output Compare timing Unit
VAN: Vehicle Area Network
CAN: Controller Area Network
MATRAMHS
Rev. A (14 Jan, 97)
ILL3
•
TEMIC
Product Selection
Semiconductors
TSC80251 Extended 8-bit Microcontrollers Selection Table
TSC80251G1
now
1K
16
32
UART, I2C, SPI,
EWC
~Wire
TSC83251Gl
now
16K
1K
16
32
EWC
UART, I2C, SPI,
~Wire
TSC87251Gl
TSC80251G2
now
16K
OTP
Planned
1K
16
32
UART, I2C, SPI,
EWC
~Wire
1K
16
32
UART, I2C, SPI,
EWC
~Wire
TSC83251G2
Planned
32 K
1K
16
32
UART, I2C, SPI,
EWC
~Wire
TSC87251G2
Planned
TSC80251A1
now
TSC8725IA1
now
TSC80251A2
Planned
32 K
OTP
24K
OTP
IK
16
32
EWC
UART, I2C, SPI,
~Wire
1K
16
32
UART
2
PMU,EWC
1K
16
32
UART
PMU,EWC
1K
16
48
UART, I2C, SPI,
PWM,EWC
~Wire
TSC83251A2
Planned
32 K
1K
16
48
UART, I2C, SPI,
2
PWM,EWC
2
PWM,EWC
~Wire
TSC8725IA2
Planned
TSC80251All
Planned
TSC83251All
Planned
TSC8725IAll
Planned
32K
OTP
1K
16
48
UART, I2CI, SPI,
~Wire
4K
16
48
UART
3+CCU
PWM, CAN 2.0B
controller
64K
4K
16
48
UART
3+CCU
PWM, CAN 2.0B
controller
64K
OTP
4K
16
48
UART
3+CCU
PWM, CAN 2.0B
controller
Abbreviations
SPI: Serial Peripheral Interface
PWM: Poise Width Modulation
12C: Inter-Integrated Circuit Communication Bus
WO: Watchdog Timer
AOC: Analog-to-Oigital Converter
PMU: Pulse Measurement Unit
CCU: 8 channels input Capture, output Compare timing Unit
EWC: Event and Waveform Controller
VAN: Vehicle Area Network
CAN: Car Area Network
11.1.4
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
Product Selection
Semiconductors
Military and Space Products
The main characteristics of the TEMIC 8-bit
microcontrollers available in military and space grades
can be found on the product datasheets.
More details on military and space compliant flows are
described inn the Quality Flow Section.
Standard Military Drawings (SMD)
The following products are registred by the DESC under
SMD numbers.
They are manufactured by TEMIC in military
temperature range according to Mil 883 compliant
quality flows.
5962-8506403MQA
5962-8506403MXC
5962-8506404MQA
Space Qualified Parts
The following product are available in space grade,
processed on Radiation Tolerant technology. The SCC
MATRAMHS
Rev. A (14 Jan. 97)
numbers indicates the qualification by
Componants groups of the device/package.
ESA's
11.1.5
B
TEMIC
Semiconductors
cst General Purpose Products
TSC80C31/80C51 : CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller . . . . . . . .. 11.2.1
TSC80CL31ITSC80CL51 : CMOS 1.8 Volt Single-Chip 8 Bit Microcontroller ...... 11.3.1
80C32/80C52 : CMOS 0 to 44 MHz Single Chip 8-bit Microntroller ....•...•....• 11.4.1
80C154/83C154 : CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller •.•....... 11.5.1
83C154D : CMOS 0 to 30 MHz Single Chip 8-bit Microcontroller ...•...•..•....• 11.6.1
TEMIC
TSCSOC31/S0C51
Semiconductors
CMOS 0 to 44 MHz Single-Chip 8 Bit Microcontroller
Description
The TSC80C31180C51 is high performance SCMOS
versions of the 8051 NMOS single chip 8 bit IlC.
The fully static design of the TSC80C31 /80C51 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TSC80C31/80C51 retains all the features of the
8051 : 4 K bytes of ROM; 128 bytes of RAM; 32110
lines; two 16 bit timers ; as-source, 2-level interrupt
structure; a full duplex serial port; and on-chip oscillator
and clock circuits.
• TSC80C31180C51-Ll6: Low power version
Vcc: 2.7-5.5 V Freq: 0-16 MHz
• TSC80C31180C51-L20: Low power version
Vee: 2.7-5.5 V Freq: 0-20 MHz
• TSC80C31/80CS1-12: 0 to 12 MHz
• TSC80C3 1/8OCS 1-20 : 0 to 20 MHz
• TSC80C31180C51-2S: 0 to 25 MHz
In
addition,
the
TSC80C31180C51
has
two
software-selectable modes of reduced activity for further
reduction in power consumption. In the Idle Mode the
CPU is frozen while the RAM, the timers, the serial port,
and the interrupt system continue to function. In the
Power Down Mode the RAM is saved and all other
functions are inoperative.
The TSC80C31180C51 is manufactured using SCMOS
process which allows them to run from 0 up to 44 MHz
with VCC = 5 V. The TSC80C31180C51 is also available
at 20 MHz with 2.7 V < Vce < 5.5 V.
•
•
•
•
TSCSOC31180CSI-30:
TSCSOC31/80CSI-36:
TSCSOC311SOC51-40:
TSCSOC311S0C51-44:
0 to 30 MHz
0 to 36 MHz
0 to 40 MHz
0 to 44 MHz'
* Commercial and Industrial temperature range only. For other speed
and range please consult your sale office.
Features
•
•
•
•
•
•
•
Power control modes
128 bytes of RAM
4 K bytes of ROM (TSC80C31/S0C51)
32 programmable I/O lines
Two 16 bit timer/counter
64 K program memory space
64 K data memory space
•
•
•
•
•
•
Fully static design
O.S 11m CMOS process
Boolean processor
S interrupt sources
Programmable serial port
Temperature range: commercial, industrial, automotive and
military
Optional
• Secret ROM: Encryption
• Secret TAG: Identification number
MATRAMHS
Rev. E (14 Jan.97)
11.2.1
TEMIC
TSCSOC31/S0C51
Semiconductors
Interface
Figure 1. Block Diagram
PoO-P07
vee
r
vs?,
-:
1
P20-P27
l
1
1
1
1
1
1_ _ 1
1
1
1
1
1
1
1
1
1
I~_J..:;.....J
:~
t:~:r
II.2.2
1
1
1
_ _ _ _ -l
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
Figure 2. Pin Configuration
vee
P1.0
P1.1
2
PO.O/AO
P1.2
3
P1.3
4
PO.1/A 1 INDEX
PO.2/A2 CORNER
P1A
5
PO.3/A3
P1.5
6
POA/A4
P1.6
7
PO.5/AS
P1.7
8
RST
9
P3.0/RXD
10
P3.1/TXD
11
":
'"
OJ
..,
~
'<
PO.4JA4
pO.5JAs
PO.6iA6
PO.6/A6
DIL40
~
PO.7/A 7
PO.7/A?
EA
EA
ALE
NC
P3.2/INTO
12
PSEN
ALE
P3.3/INT1
13
P2.7/A15
PSEN
P2.7/A15
P3A{T0
14
P2.6/A14
P3.5{T1
15
P2.5/A13
P2.6/A14
P3.6/WR
16
P2A/A12
P2.S/A13
P3.7/RD
17
P2.3/A11
XTAL2
18
P2.2/A10
XTAL1
19
P2.1/A9
VSS
20
21
0
z
x
0
~
~
40 39 38 37 38 35
P04 /A4
P05/AS
Poa/A6
P07 /A ?
RST
EA
RxD/P30
NC
PQFP44
NC
TXO/P31
ALE
INTO/P32
PSEN
INTl/P33
P27 /A15
TO/P34
P26 /A14
T1/P35
P25 /A13
Diagrams are for reference only. Packages sizes are not to scale.
MATRAMHS
Rev. E (14 Jan.97)
II.2.3
I
TEMIC
TSCSOC31/S0C51
Semiconductors
Pin Description
VSS
Circuit ground potential.
vee
Supply voltage during normal, Idle, and Power Down
operation,
PortO
Port 0 is an 8 bit open drain bi-directional 1/0 port. Port 0
pins that have l's written to them float, and in that state
can be used as high-impedance inputs,
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory, In this application it uses strong internal pullups
when emitting 1's, Port 0 also outputs the code bytes
during program verification in the TSC80C31180C5 L
External pullups are required during program
verification, Port 0 can sink eight LS TTL inputs,
It also receives the high-order address bits and control
signals
during
program
verification
in
the
TSC80C31180C5 L Port 2 can sink or source three LS
TTL inputs. It can drive CMOS inputs without external
pullups.
Port 3
Port 3 is an 8 bit bi-directional 110 port with internal
pullups. Port 3 pins that have 1's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the TEMIC C51 Family, as
listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
Port 1
Port I is an 8 bit bi-directional 110 port with internal
pullups, Port I pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs, As inputs, Port I pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups,
Port I also receives the low-order address byte during
program verification, In the TSC80C31180C51, Port I
can sink or source three LS TTL inputs, It can drive
CMOS inputs without external pullups,
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INTI (external interrupt I)
TD (Timer 0 external input)
TI (Timer I external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to Vee. As soon as the Reset is
applied (Vin), PORT I, 2 and 3 are tied to one. This
operation is achieved asynchronously even if the
oscillator does not start -up.
Port 2
Port 2 is an 8 bit bi-directional 110 port with internal
pullups. Port 2 pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOVX @DPTR). In
this application, it uses strong internal pullups when
emitting 1'so During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
Il.2.4
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
116 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
If desired, ALE operation can be disabled by setting bit
o of SFR location AFh (MSCON). With the bit set, ALE
is active only during MOVX instruction and external
fetches. Otherwise the pin is pulled low. MSCON SFR is
set to XXXXXXXO by reset.
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
XTALI
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink or source 8 LS TIL inputs. It can drive
CMOS inputs without an external pullup.
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator is
used.
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds
3 FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Idle And Power Down Operation
Figure 3. shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function, while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is
87H. PCON is not bit addressable.
PCON: Power Control Register
(MSB)
(LSB)
GFI
ISMODI
GFO
PD
IDL
Symbol
Position
Name and Function
SMOD
PeON.7
GFi
GFO
PD
PCON.6
PeON.S
PeON.4
PeON.3
PeON.2
PeON. I
IDL
PeON.O
Double Baud rate bit. When set to
ai, the baud rate is doubled when
the serial port is being used in
either modes 1,2 or 3.
(Reserved)
(Reserved)
(Reserved)
General-purpose flag bit.
General-purpose flag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
Figure 3. Idle and Power Down Hardware.
If 1's are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(OOOXOOOO).
Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. Table 1 describes the status of the
external pins during Idle mode.
MATRAMHS
Rev. E (14 Jan.97)
There are three ways to tenninate the Idle mode.
Activation of any enabled interrupt will cause PCON.O to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.O.
11.2.5
TEMIC
TSCSOC31/S0C51
The flag bits GFO and GFI may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
Semiconductors
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
Power Down Mode
The instruction that sets PCON.I is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The hardware reset initiates the Special Fucntion
Register. In the Power Down mode, VCC may be lowered
to mi-nimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which freezes the
oscillator. Reset should not be released until the oscillator
has restarted and stabilized. A hardware reset is the only
way of exiting the power down mode.
Table I describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a I, the port
pin is held high during the power down mode by the
strong pullup, n, shown in Figure 4.
Thble 1. Status of the external pins during idle and power down modes.
Stop Clock Mode
Due to static design, the TSC80C31180C51 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Figure 4. I/O Buffers in the TSC80C31/80C51 (Ports
1,2,3).
Q
I/O POrts
FROM
PORT
LATCH
The VO buffers for Ports 1,2 and 3 are implemented as
shown in Figure 4.
n.2.6
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
When the port latch contains a 0, all pFETS in Figure 4.
are off while the nFET is turned on. When the port latch
makes a O-to-I transition, the nFET turns off. The strong
pFET, Tl, turns on for two oscillator periods, pulling the
output high very rapidly. As the output line is drawn high,
pFET T3 turns on through the inverter to supply the IOH
source current. This inverter and T form a latch which
holds the I and is supported by T2.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a 1 will have his strong pullup turned on for the
entire duration of the external memory access.
When an I/O pin son Ports 1, 2, or 3 is used as an input,
the user should be aware that the external circuit must
sink current during the logical I-to-O transition. The
maximum sink current is specified as ITL under the D.C.
Specifications. When
the
input goes
below
approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical I, T2 is the only internal
pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Oscillator Characteristics
XTALI and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in Figure 5. Either a quartz
crystal or ceramic resonator may be used.
Figure 5. Crystal Oscillator.
To drive the device from an external clock source,
XTALI should be driven while XTAL2 is left
unconnected as shown in Figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
XTAL2: 18
Figure 6. External Drive Configuration.
XTAL1 : 19
NC
XTAL2: 18
EXTERNAL
OSCILLATOR -----iXTAL1 : 19
SIGNAL
+--------1 VSS : 20
.----lVSS : 20
TSC80C51 with Secret ROM
TEMIC offers TSC80C31180C51 with the encrypted
secret ROM option to secure the ROM code contained in
the TSC80C31180C51 microcontrollers.
-
The clear reading of the program contained in the ROM
is made impossible due to an encryption through several
random keys implemented during the manufacturing
process.
-
The keys used to do such encryption are selected
randomwise and are definitely different from one
microcontroller to another.
Every time a byte is addressed during a verify of the
ROM content, a byte of the encryption array is
selected.
MOVC instructions executed from external program
memory are disabled when fetching code bytes from
internal memory.
EA is sampled and latched on reset, thus all state
modification are disabled.
For further information please refer to the application
note (ANM053) available upon request.
This encryption is activated during the following phases:
MATRAMHS
Rev. E (14 Jan.97)
11.2.7
II
TSCSOC31/S0C51
TEMIC
Semiconductors
TSCSOC31/S0C51 with Secret TAG
TEMIC offers special 64-bit identifier called "SECRET
TAG" on the microcontroller chip.
The Secret Tag option is available on both ROMless and
masked microcontrollers.
The Secret Tag feature allows serialization of each
microcontroller for identification of a specific
equipment. A unique number per device is implemented
in the chip during manufacturing process. The serial
number is a 64-bit binary value which is contained and
addressable in the Special Function Registers (SFR) area.
II.2.8
This Secret Tag option can be read-out by a software
routine and thus enables the user to do an individual
identity check per device. This routine is implemented
inside the microcontroller ROM memory in case of
masked version which can be kept secret (and then the
value of the Secret Tag also) by using a ROM Encryption.
For further information, please refer to the application
note (ANM03I) available upon request.
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
Electrical Characteristics
* Notice
Absolute Maximum Ratings*
Ambiant Temperature Under Bias:
C = commercial
O°C to 70°C
I = industrial.
-40'C to 85'C
Storage Temperature
. -65°C to + ISOaC
Voltage on VCC to VSS ........................ -0.5 V to + 7 V
.. -0.5 V to Vee + 0.5 V
Voltage on Any Pin to VSS
Power Dissipation
I W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under" Absolute Maximum Ratings"
1n((V cause permanent damage to the device. This is a stress ratinK only
andfunctionai operation qj'the device at these or any other conditions
above those indicated in the operational sections (~rthis .\'pec~ticlllion is
flot implied. Exposure to absolute maximum rating conditions may q!feet
device reliabili(v.
II
DC Parameters
TA =ooe to 70 0 e ; VSS =0 V ; vee =5 V ± 10 % ; F =0 to 44 MHz
TA =-40 o e + 85°e ; VSS =0 V ; vee =5 V ± 10 % ; F =0 to 44 MHz
I';;,),·:', ·.;i:
Typ (3)
I:'{';m?,i~li:;j:,,·t·~·'··::";·;·
Min
.....
....
,::),
Max
Unit
-0.5
0.2 Vee - 0.1
V
0.2 Vee + 0.9
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
i'c<::';··,··,
VIL
Input Low Voltage
Test Conditions
VIH
Input High Voltage (Exeept XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port I, 2 and 3) (4)
0.3
0.45
1.0
V
V
V
IOL= 100 llA
10L = 1.6 rnA (2)
IOL=3.5 rnA
VOLl
Output Low Voltage (Port 0, ALE, PSEN) (4)
0.3
0.45
1.0
V
V
V
10L= 200 llA
10L = 3.2 rnA (2)
IOL=7.0rnA
VOH
Output High Voltage Port I, 2, 3
Vee - 0.3
V
10H=-10IlA
Vee - 0.7
V
IOH=- 3O IlA
Vee -1.5
V
IOH=- 60 11A
VCC=5V±10%
Vee -0.3
V
10H = -200 IlA
Vee - 0.7
V
IOH =-3.2 rnA
Vee - 1.5
V
IOH=-7.0mA
VCC=5V±10%
VOHI
Output High Voltage (Port 0, ALE, PSEN)
IlL
Logieal 0 Input Current (Ports 1,2 and 3)
-50
llA
Yin = 0.45 V
ILl
Input leakage Current
±10
llA
0.45 < Yin < Vee
ITL
Logical 1 to 0 Transition Current (Ports 1, 2 and 3)
!PD
Power Down Current
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freq = 1 MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq;" 12 MHz Icc op max = 0.9 Freq (MHz) + 5
\cc idle max = 0.3 Freq (MHz) + 1.7
Freq <; 20 MHz Icc op typ = 0.7 Freq (MHz)
Freq ;" 20 MHz Icc op typ = 0.5 Freq (MHz) + 4
Freq <; 20 MHz Ice idle typ = 0.16 Freq (MHz) + 0.4
Freq;" 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2
MATRAMHS
Rev. E (14 Jan.97)
50
-650
llA
Vin=2.0 V
5
30
llA
Vee = 2.0 V to 5.5 V (I)
90
200
KQ
\0
pF
1.8
I
9
3.5
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
fe = I MHz, Ta = 25'C
Vce=5.5V
0.7
0.5
4.2
1.4
II.2.9
TEMIC
TSC80C31/80C51
Semiconductors
,,":0 This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias:
A
= Automotive
-40'C to + 125 'C
...... .
Storage Temperature ........................ -65'C to + 150'C
Voltage on VCC to VSS ........................ -0.5 V to + 7 V
Voltage on Any Pin to VSS ............... -0.5 V to VCC + 0.5 V
Power Dissipation ................................... I W**
Sfres.'Ies above those listed under" Absolute Maximum RatinKs" may
(:{luse permanent damaf{e to the del'ice. Thi,\' is a stress ratinf.: only lind
./il11ctiol111i operatioll (~f the derice at the.lie or lilly other cOllditions above
those indicated ;n the operational sections (~f this spec{jication is not
implied. Exposure to absolute mllximum rating conditions for extended
periods may affect device reliability.
DC Parameters
TA = -40 o e + 125°e ; VSS = 0 V ; vee = 5 V ± 10 % ; F = 0 to 40 MHz
;;'0'"
";',,
VIH
1;;i,igj;i,";i;;!L,.i'y'.
' Voltage
!
Input
I
Input High Voltage (Except XTAL and RST)
';"i,
I;",!y!~ii • •i'
g
.{;!.iiiiCUi(:;li
1
~;;;
'.1
0 .2
0.2 Vee· 0.9
Vee·O.5
V
0.7 Vee
Vee + 0.5
V
VIHI
!Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port 1, 2 and 3) (4)
0.3
0.45
1.0
V
V
V
IOL= 100~
IOL = 1.6 rnA (2)
IOL= 3.5 rnA
VOLI
Output Low Voltage (Port 0, ALE, PSEN) (4)
0.3
0.45
1.0
V
V
V
IOL= 200llA
10L = 3.2 rnA (2)
IOL=7.0mA
VOH
Output High Voltage Port I, 2 and 3
VOHI
Output High Voltage (Port 0, ALE, PSEN)
I
Logical Iinput
I
Input leakage
ITL
I
Logical
IPD
I
Power Down Current
I
RST Pull down Resistor
RRST
CIO
ICC
II.2.10
Ir,
(ports I,
I, :
lilA
10H
lilA
V
IOH=- 6O IlA
VCC=5V± 10%
Vee· ·0.3
V
10H
200~
Vee··0.7
V
10H
·3.2mA
Vee - 1.5
V
IOH=-7.0mA
VCC=5 V± 10%
and 3)
·750
50
Il A
Yin
Il A
0.45
Il A
Yin ,2.0
5
75
Il A ,Vee ,2.0V .5.5V(I)
90
200
KQ
, of 110 Buffer
Power Supply Current
Freq = I MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq;" 12 MHz Icc op max = 0.9 Freq (MHz) + 5
Icc idle max = 0.3 Freq (MHz) + 1.7
Freq"; 20 MHz Icc op typ = 0.7 Freq (MHz)
Freq;" 20 MHz Icc op typ = 0.5 Freq (MHz) + 4
Freq,.;20MHz Icc idle typ = 0.16 Freq (MHz) + 0.4
Freq;" 20 MHz Icc idle typ = 0.12 Freq (MHz) + 1.2
10H
Vee-1.5
13)
• 0 Transition Current (Ports
'i"',!!,
i',i",'
10
pF ,fe ; 1 MHz, Ta ,25°C
1.8
I
9
3.5
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
Vee=5.5V
0.7
0.5
4.2
1.4
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias:
M = Military. . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -55"e to +125'e
..... --{;5"e to + l50'e
Storage Temperature
.. -0.5 V to + 7 V
Voltage on vee to vss .
... -0.5 V to vee + 0.5 V
Voltage on Any Pin to VSS
1 W**
Power Dissipation
Stresses at or above those listed under" Absolute Maximum Ratings"
may cause permanent danUlKe to the device. This is a stress rating only
and.timctional operation ql'the device at these or any other conditions
above those indicated in the operational sections ql'thi.\· spec(tication is
not implied. Exposure to absolute maximum ratinR conditions ma}' affect
device reliability.
DC Parameters
TA =-55°C + t25°C ; Vss
VOHI
ICC
=0 V; Vee =5 V ± 10 % ; F =0 to 40 MHz
lEI
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
Vcc=5.5V
Power Supply Current
Freq = I MHz
Freq = 6 MHz
Freq" 12 MHz
Freq <; 20 MHz
Freq ,,20 MHz
Freq <; 20 MHz
Freq" 20 MHz
MATRAMHS
Rev. E (14 Jan.97)
Icc op
Icc idle
Icc op
Icc idle
Icc op max = 0.9 Freq (MHz) + 5
Icc idle max = 0.3 Freq (MHz) + 1.7
Icc op typ = 0.7 Freq (MHz)
Icc op typ = 0.5 Freq (MHz) + 4
Icc idle typ = 0.16 Freq (MHz) + 0.4
Icc idle typ = 0.12 Freq (MHz) + 1.2
0.7
0.5
4.2
1.4
1.8
I
9
3.5
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
rnA
11.2,11
TEMIC
TSCSOC31/S0C51
Semiconductors
* Notice
Absolute Maximum Ratings*
Ambient Temperature Under Bias:
ooe to 70°C
C = Commercial .
-40 oe to 8Soe
I = Industrial ...
...... -6Soe to + ISO'e
Storage Temperature
. . -O.S V to + 7 V
Voltage on vee to vss ....
Stresses at or above those listed under" Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
andfunctional operation a/the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
. -O.S V to vee +0.5 V
Voltage on Any Pin to VSS ..
Power Dissipation .,
I W**
** This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Characteristics: Low Power Version
TA =O°C to 70°C; Vee = 2.7 V to 5.5 V; Vss =0 V; F =0 to 20 MHz
TA =-40°C to 85°C; Vee = 2.7 V to 5.5 V ; F =0 to 20 MHz
Icc (rnA)
Freq> 12MHz (Vee = s.s V)
II.2.12
=
Icc op max (rnA) 0.9 x Freq (MHz) + S
Icc Idle max (rnA) = 0.3 x Freq (MHz) + 1.7
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
Idle ICC is measured with all output pins disconnected;
XTALl driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 0.5 V, VIH = VCC - 0.5 V ; XTAL2 N.C ; Port 0 =
VCC ; EA = RST = VSS.
Figure 7. ICC Test Condition, Idle Mode.
Power Down ICC is measured with all output pins
disconnected; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST=VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports I and 3. The noise is due to external bus
capacitance discharging into the Port a and Port 2 pins
when these pins make I to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
with maxi VOL peak 0.6 V. A Schmitt Trigger use is not
necessary.
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 8. ICC Test Condition, Active Mode.
Note 3 : Typicals are based on a limited number of
samples and are not guaranteed. the values listed are at
room temperature and 5Y.
Note 4 : Under steady state (non-transient)) conditions,
IOL must be externally limited as follows:
Maximum IOL per port pin:
10 rnA
Maximum IOL per 8-bit port :
PortO:
26 rnA
15 rnA
Ports 1, 2 and 3 :
71 rnA
Maximum total IOL for all output pins:
EA
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 9. ICC Test Condition, Power Down Mode.
If IOL exceed the test condition, VOL may exceed the
related specification. Pins are not guaranteed to sink
current greater than the listed test conditions.
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
All other pins are disconnected.
Figure 10. Clock Signal Waveform for ICC Tests in Active and Idle Modes.
TCHCL
i4------TCLCL.--------..j
TCLCH = TCHCL = 5 ns.
MATRAMHS
Rev. E (14 Jan.97)
11.2.13
I
TEMIC
TSCSOC31/S0C51
Semiconductors
Explanation of the A C Symbol
Each timing symbol has 5 characters. The first character
is always a "T" (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
Example:
TAVLL =Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
Q : Output data.
R : READ signal.
T:Time.
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
AC Parameters
TA=Oto+70°C; Vss=OV; Vcc=5 v± 10% ;F=Oto44MHz
TA= 0 to +70°C; Vss= 0 V; 2.7 V ---<
INSTR IN
ADDRESS Ae-A15
PORT2 _ _ _ _"
11.2.14
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
External Data Memory Characteristics (values in ns)
I
External Data Memory Write Cycle
TWHLH
"
ALE
I
~
_TLLWL~
PORTO
PORT 2
>--<
ADDRESS
ORSFR-P2
_-TAVWL
"-TLLAX+f
AO-A?
)<
TWLWH
1':J
D<
TOVWX
/
""'TWHOX..I
TOVWH
J
DATA OUT
I
ADDRESS AB-A15 OR SFR-P2
External Data Memory Read Cycle
~_ _- . . . 4.. - - - T L L D V - - - -.....
~1
ALE
RD
- - - - - - - - f - - - - - -.....
I~----+TRLRH----_.V==TRHDX
PORTO
DATA IN
PORT 21
MATRAMHS
Rev. E (14 Jan.97)
11.2.15
TEMIC
TSCSOC31/S0C51
Semiconductors
Serial Port Timing - Shift Register Mode (values in ns)
TQVXH
Output Data Setup to Clock
Rising Edge
563
480
380
300
220
170
140
TXHQX
Output Data Hold after Clock
Rising Edge
90
90
65
50
45
35
25
TXHDX
Input Data Hold after Clock
Rising Edge
0
0
0
0
0
0
0
TXHDV
Clock Rising Edge to Input Data
Valid
563
450
350
300
250
200
7
8
160
Shift Register Timing Waveforms
INSTRUCTION
0
2
3
4
5
6
CLOCK
OUTPUT DATA
~O
WRITE
SBUF
TXHDVI--l
INPUT DATA.,,----,.
...
CLEAR RI
1I.2.16
1
...
SETIN
TXHDX
...
SETIN
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSCSOC31/S0C51
Semiconductors
External Clock Drive Characteristics (XTALl)
~~{,;,,~~i~' .~
MIN
PARAMETER
FCLCL
Oscillator Frequency
MAX
44
.~J~,'<;;<'\'\:,
MHz
TCLCL
Oscillator period
22.7
ns
TCHCX
High Time
5
ns
TCLCX
Low Time
5
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
ns
I
External Clock Drive Waveforms
TCHCL
~-------------TCLCL.--------------~
AC Testing Input/Output Waveforms
=X
INPUT/OUTPUT
O 5V
VCC- ,
0,45 V
0,2Vcc + 0,9
)C
_...;O;;.;,2;..V;.:;c~c_-...;O.:..;,1_ _ _ _-..;
AC inputs during testing are driven at Vcc - 0.5 for a logic
"1" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "1" and VIL max for a logic
"0".
Float Waveforms
FLOAT
.-.-------- FLOAT - - - - - - - - - . j
VLOAD
VLOAD+O,1 V
VLOAD-O,1 V
For timing purposes as port pin is no longer floating when
a 100 mV change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOHNOL
level occurs. IoilIoH ~ ± 20 rnA.
MATRAMHS
Rev. E (14 Jan.97)
II.2.17
TEMIC
TSCSOC31/S0C51
Semiconductors
Clock Waveforms
INTERNAL
CLOCK
I
STATE 4
I
P11P2
STATE 51
STATE 6
P11P2
I
P11P2
STATE 1
I
P11P2
STATE 21
STATE 3
STATE 4
1
P11P2
P11P2
I
P11P2
STATE 5
I
P11P2
XTAL2
ALE
' """'" THESE
1
1
SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
...------,
PSEN
PO
P2 (EX1)
READ CYCLE
_ _ _ _--'hNDICATESADDRESS TRANSITIONSIL _ _ _ _ _ _ _ _ _ _- '
RD
OOH IS EMITIED
DURING THIS PERIOD
PO
_ _ _ _~~D=P~L~O~R~R~i~I~I,,
______~~~~___-'I
iJ.1..
OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
FLOAT SAMPLED
...
1
i t
~
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
WR
1 peL OUT (EVEN IF PROGRAM
' - - - - - - - - - - - - - - ' MEMORY IS INTERNAL)
DP~~fRi I..
PO
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
P2
5fi..1~LOUT:~OGRAM
IMEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT SRC
_ _ _ _ _ _ _ _ _O_L_D_D_A_1:-1A1 NEW DATA
~
MOV DEST PO
MOV DEST PORT-(P-1-.P-2-.-P3-)--'
(INCLUDES INTO. INT1. TO. T1)
SERIAL PORT SHIFT CLOCK
TXD
(MODE 0)
APO PINS SAMPLED
PO PINS SAMPLED
~
=
~
ITJ'-----------------'ITL
I
P1. P2. P3 PINS SAMPLED
- - - - - - - . . : . - . . .•.......,1
.,
RXD SAMPLED
I
P1. P2. P3
PINS SAMPLED
yI
RXD SAMPLED
This diagram indicates when signals are clocked
internally. The time it takes the signals to propagate to the
pins, however, ranges from 25 to 125 ns. This propagation
delay is dependent on variables such as temperature and
pin loading. Propagation also varies from output to output
and component. Typically though (TA = 25°C fully
loaded) RD and WR propagation delays are
approximately 50 ns. The other signals are typically 85
ns. Propagation delays are incorporated in the AC
specifications.
IL2.18
MATRAMHS
Rev. E (14 Jan.97)
TEMIC
TSC80C31/80C51
Semiconductors
Ordering Information
TSC
xxx
SOCS1
T
Part Number
SOC31: External ROM
SOC51: 4KxS Mask ROM
SOC5IC: Secret ROM version
SOC51 T: Secret Tag version
-20
C
T
-12: 12 MHz version
-16: 16 MHz version
-20: 20 MHz version
-25: 25 MHz version
-30: 30 MHz version
-36: 36 MHz version
-40: 40 MHz version
-44: 44 MHz version
-Ll6: Low Power
(VCC: 2.7-5.5V,
Freq.: 0-16 MHz)
-L20: Low Power
(VCC: 2.7-5.5V,
Freq.: 0-20 MHz)
B
T
Packaging
A: POlL 40
B: PLCC44
C: PQFP 44 (fp 13.9mm)
D: PQFP 44 (fp 12.3mm)
E: VQFP 44 (1.4mm)
F: TQFP 44 (lmm)
G: COIL 40 (.6)
H: LCC44
I: CQPJ 44
T
Blank: Standard
/S83: MIL 883
Compliant
P883: MIL S83
Compliant
with
PINDtest.
Die form:
W: Wafer
X: Dice Form
Y: Wafer on Ring
Customer ROM Code
(Not used for external ROM Device)
TEMIC Semiconductor
Microcontroller Product Line
R
Temperature Range
C : Commercial 0° to 70°C
I : Industrial -400 to S5°C
A : Automotive -40° to 125°C
M : Military -55° to 125°C
Conditioning
R : Tape & Reel
D: Dry Pack
B : Tape & Reel and
Dry Pack
Examples :
Mask ROM version XXX, POlL 40, 20 MHz version, Commercial Temperature Range . TSCSOC3I1S0C5IXXX-2OCA
(I) Ceramic of multi-layer packages: contact TEMIC Sales office
Product Marking:
For PDIL 40, PLCC 44 & QFP 44 Packages
TEMIC
Customer PIN
TemicPIN
© Intel SO, 82
YYWW Lot Number
MATRAMHS
Rev. E (14 Jan.97)
II.2.19
I
TEMIC
Semiconductors
TSC80CL31ITSC80CL51
CMOS 1.8 Volt Single-Chip 8 Bit Microcontroller
Description
TEMIC's SOC31 and SOCSI are high perfonnance
SCMOS versions of the S051 NMOS single chip S bit IlC.
The
fully
static
design
of
the
TEMIC
TSCSOCL31 rrSCSOCL51 allows to reduce system
power consumption by bringing the clock frequency
down to any value, even DC, without loss of data.
The TSCSOCL51 retains all the features of the S051 : 4 K
bytes of ROM; 12S bytes of RAM ; 32 I/O lines; two 16
bit timers; a 5-source, 2-level interrupt structure; a full
duplex serial port ; and on-chip oscillator and clock
circuits.
In addition, the TSCSOCL51 has two software-selectable
modes of reduced activity for further reduction in power
consumption. In the Idle Mode the CPU is frozen while
the RAM, the timers, the serial port, and the interrupt
system continue to function. In the Power Down Mode the
RAM is saved and all other functions are inoperative.
The TSCSOCL3l is identical to the TSCSOCL51 except
that it has no on-chip ROM.
TEMIC's TSCSOCL3lrrSCSOCL5l are manufactured
using SCMOS process which allows them to run from 0
up to 4 MHz with VCC = I.S V.
The TSCSOCL51 is a general purpose microcontroller
especially suited for battery-powered applications. This
very low voltage version fits in all applications using two
battery cells.
Available Products
• Very Low Voltage version
Vcc: 1.8-S.S V Freq : 0-4 MHz
• TSC8OCL3I-V4: ROMless version
• TSC8OCLSI-V4: 4K x 8 Mask ROM version
Features
•
•
•
•
•
•
Power control modes
128 bytes of RAM
4 K bytes of ROM (TSC8OCLSl)
32 programmable I/O lines
Two 16 bit timer/counter
64 K program memory space
• 64 K data memory space
•
•
•
•
•
•
Fully static design
0.8 J.1m CMOS process
Boolean processor
S interrupt sources
Programmable serial port
Temperature range: commercial
Optional
• Secret ROM: Encryption
• Secret TAG: Identification number
MATRAMHS
Rev. A (14 Jan. 97)
II.3.!
I
TEMIC
TSC80CL31ITSC80CL51
Semiconductors
Interface
Figure 1. Block Diagram
POO-P07
vee
I
P20 P27
-----
vs?,
-:-
I
---
1
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-l
Po 0 Po 7
II.3.2
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
TSC80CL31/TSC80CL51
Semiconductors
Figure 2. Pin Configuration
40
vee
P1.1
2
39
PO.O/AO
P1.2
3
38
P1.3
4
37
PO.1/A 1 INDEX
PO.2/A2 CORNER
P1A
5
36
PO.3/A3
P1.5
6
35
POA/A4
P1.6
7
34
PO.5/A5
PO.S/AS
P1.7
8
33
PO.6/A6
PO.6JA6
P1.0
RST
9
P3.0/RXD
10
DIL40
~
~
"!
'C
~
0
~
~
PO.4/A4
32
PO.7/A 7
PO.7/A7
31
EA
EA
P3.1/TXD
11
30
ALE
NC
P3.2/INTO
12
29
PSEN
ALE
P3.3/INT1
13
28
P2.7/A15
PSEN
P3AjTO
14
27
P2.6/A14
P2.7/A15
P3.5/T1
15
26
P2.5/A13
P2.6/A14
P3.6/WR
16
25
P2A/A12
P2.5/A13
P3.7/Ro
17
24
P23/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
P2.0/A8
....
M
~
l~ l~
x
<0
M
C)
z
~
oj
l: I;'(~>' :pli:rameter
VIL
Input Low Voltage
Min
Max
Unit
-0.5
0.2 Vee-O.l
v
Test COnditions
VIH
Input High Voltage (Except XTAL and RST)
0.2 Vee + 1.4
Vee + 0.5
V
VIH2
Input High Voltage to RST for Reset
0.7 Vee
Vee + 0.5
V
VIHI
Input High Voltage to XTALI
0.7 Vee
Vee +0.5
V
VPD
Power Down Voltage to Vcc in PD Mode
1.8
5.5
V
VOL
Output Low Voltage (Ports 1,2,3)
0.45
V
IOL
~
0.8 rnA (2)
~
1.6 rnA (2)
VOLI
Output Low Voltage Port 0, ALE, PSEN
V
IOL
VOH
Output High Voltage (Port I, 2 and 3)
0.9 Vcc
V
10H~-1O
VOHI
Output High Voltage (Port 0 in External Bus Mode),
ALE,PSEN
0.9 Vce
V
IOH~
IlL
Logical 0 Input Current Ports I, 2, 3
0.45
-50
J-lA
Vin
~
J-lA
-40J-lA
0.45 V
ILl
Input Leakage Current
±1O
J-lA
0.45 < Yin < Vee
ITL
Logical I to 0 Transition Current (Ports 1,2,3)
-650
J-lA
Vin
IPD
Power Down Current
10
50
J-lA
J-lA
Vee~1.8Vt02.2V(I)
200
kQ
10
pF
RRST
CIO
RST Pull down Resistor
50
Capacitance of 1/0 Buffer
~
Vee
fc
~
2.0 V
~
2.2 V to 5.5 V (I)
I MHz, TA
~
25'C
Maximum Icc (rnA)
t.·'·.·,.·~Z}":".!,'·~,
.•i"i'
., •• ,. ,..••... ,•.•., ··~f'at~(~)./.i.
" '..,., . . . ',' ....•... .......... ,. ildlt' (1)
Frequency/Vee
1.8 V
2.2V
3.3 V
5.5 V
1.8 V
2.2 V
32KHz
60J-lA
80 J-lA
200 J-lA
400J-lA
25 J-lA
30 J-lA
455 KHz
200 J-lA
250 J-lA
350 J-lA
I rnA
50J-lA
3.58 MHz
1.5 rnA
2 rnA
3 rnA
6 rnA
300 J-lA
4 MHz
2mA
2.5 rnA
3.5 rnA
7 rnA
400 J.lA
600 J-lA
MATRAMHS
Rev. A (14 Jan. 97)
.
.... .':
.
.:.c'..•:.:..
3.3 V
5.5 V
75 J-lA
150J-lA
400J-lA
500J-lA
I rnA
2.5 rnA
1.2 rnA
3mA
11.3.9
TEMIC
TSC80CL31ITSC80CL51
Note1: ICC is measured with all output pins
disconnected; XTALI driven with TCLCH, TCHCL =
5 ns, VIL = VSS + 0.5 V, VIH = VCC - 0.5 V ; XTAL2
N.C. ; EA = RST = Port 0 = VCC. ICC would be slighty
higher if a crystal oscillator used.
Idle ICC is measured with all output pins disconnected;
XTALI driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 0.5 V, VIH = VCC - 0.5 V ; XTAL2 N.C ; Port 0 =
VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected ; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST=VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
with maxi VOL peak 0.6 V. A Schmitt Trigger use is not
necessary.
Semiconductors
Figure 8. ICC Test Condition, Active Mode.
All other pins are disconnected.
VCC
RST
(NC)
CLOCK
SIGNAL
XTAl2
XTAl1
VSS
Figure 9. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
RST
Figure 7. ICC Test Condition, Idle Mode.
All other pins are disconnected.
RST
(NC)
CLOCK
SIGNAL
(NC)
CLOCK
SIGNAL
XTAl2
XTAl1
VSS
EA
XTAl2
XTALl
VSS
Figure 10. Clock Sigual Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
J.4------TCLC~_------_+I
Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character
is always a ''T'' (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
11.3.10
Example:
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
MATRA MHS
Rev. A (14 Jan. 97)
TEMIC
Semiconductors
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH
I: Instruction (program memory contents).
L : Logic level LOW. or ALE.
P:PSEN.
TSC80CL31ITSC80CL51
Q : Output data.
R : READ signal.
T:Time.
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
A C Parameters
TA =0 to +70°C; Vss =0 V; 1.8 V < Vee < 5.5 V; F =0 to 4 MHz
(Load Capacitance for PORT 0, ALE and PSEN = 100 pF ; Load Capacitance for all other outputs =80 pF)
External Program Memory Characteristics (values in ns)
External Program Memory Read Cycle
ALE
NJ·A7
ADDRESS AB·A15
PORT 2 _ _ _ _./
MATRAMHS
Rev. A (14 Jan. 97)
11.3.11
TEMIC
TSC80CL31/TSC80CL51
Semiconductors
External Data Memory Characteristics (values in ns)
External Data Memory Write Cycle
L
TWHLH
~
'\
ALE
I--- TLLWL---!
PORTO
PORT 2
>---<
ADDRESS
OR SFR-P2
_f--TAVWL
!.TLLAX+j
AO-A?
)<
lX
I
TWLWH
~
TQVWX
/
""'TWHQX..I
TQVWH
t
DATA OUT
ADDRESSAS-A15 OR SFR-P2
External Data Memory Read Cycle
~_ _--...I~.<-----
T L L D V - - - -......~I
TWHLH
ALE
RD
-------t-----"I~----+TRLRH---~~V~~TRHDX
PORTO
DATA IN
TRLAZ
PORT21
11.3.12
ADDRESSA8-A15 OR SFR-P2
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
TSC80CL31/TSC80CL51
Semiconductors
Serial Port Timing - Shift Register Mode (values in ns)
TXLXL
Serial PorI Clock Cycle Time
12Clk
TQVXH
Output Data Setup to Clock Rising Edge
2370
TXHQX
Output Data Hold after Clock Rising Edge
390
TXHDX
Input Data Hold after Clock Rising Edge
TXHDV
Clock Rising Edge to Input Data Valid
o
2370
Shift Register Timing Waveforms
INSTRUCTION
o
2
3
4
5
6
7
8
OUTPUT DATA
&
~
SETIN
WRITE TO SBUF
INPUT DATA
&
&
SET IN
CLEAR RI
MATRAMHS
Rev. A (14 Jan. 97)
II.3.l3
TEMIC
TSC80CL31ITSC80CL51
Semiconductors
External Clock Drive Characteristics (XTALl)
External Clock Drive Waveforms
TCHCL
i4------TCLCl-------I-.j
AC Testing Input/Output Waveforms
=X
INPUT/OUTPUT
O 5V
VCC- ,
0,45 V
O,2Vcc + 0,9
)C
_-'O;.:.,2_V-'c"'c_-_O-'-,1_ _ _ __
AC inputs during testing are driven at Vcc - 0.5 for a logic
"I" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic "\" and VIL max for a logic
"0".
Float Waveforms
FLOAT
1-----
FLOAT - - - - . . . ;
VLOAD
VLOAD + 0,1 V
VLOAD-O,l V
For timing purposes as port pin is no longer floating when
a 100 m V change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOHNOL
level occurs. Iol/IoH ?! ± 20 rnA.
11.3.14
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
TSC80CL31/TSC80CL51
Semiconductors
Clock Waveforms
STATE 4
INTERNAL
CLOCK
P1
I
I P2
STATE
51
STATE 6
P1 I P2
P1
I P2
I
STATE 1
P1
I
I P2
STATE
P1
21
I P2
STATE 3
P1
1
I P2
STATE 4
I
P1 I P2
STATE
5
I
P1 I P2
XTAL2
'""'" THESE
I SIGNALS ARE NOTI
ALE
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
r------,
PSEN
II
PO
P2 (EXT)
READ CYCLE
RD
OOH IS EMITIED
DURING THIS PERIOD
PO
_____
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
Ji-D~P~L~O~R~R~i~11Iro------------~~~~---~!
U.I..
OUT
FLOAT SAMPLED
..
i
r
t
L-
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
WR
I PCL OUT (EVEN IF PROGRAM
' - - - - - - - - - - - - - ' MEMORY IS INTERNAL)
DP~~f I..
PO
Ri
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
P2
:sg.I~LOUT:F~OGRAM
IMEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT SRC
_ _ _ _ _ _ _ _ _ _O_LD_DA_:T:_A..JI NEW DATA
~
MOV DEST PO
MOV DEST PORT-(P-1-.P-2-.P-3-)--..J
(INCLUDES INTO.INT1. TO. T1)
~
IYlL----------------------'Ff!-I
I
-----~-*A--'I
SERIAL PORT SHIFT CLOCK
TXD
(MODE 0)
PO PINS SAMPLED
PO PINS SAMPLED
P1. P2. P3 PINS SAMPLED
RXD SAMPLED
P1. P2. P3
PINS SAMPLED
"ri
RXD SAMPLED
This diagram indicates when signals are clocked
internally. The time it takes the signals to propagate to the
pins, however, ranges from 25 to 125 ns. This propagation
delay is dependent on variables such as temperature and
pin loading. Propagation also varies from output to output
and component. Typically though (TA = 25°C fully
loaded) RD and WR propagation delays are
approximately 50 ns. The other signals are typically 85
ns. Propagation delays are incorporated in the AC
specifications.
MATRAMHS
Rev. A (14 Jan. 97)
II.3.15
TEMIC
TSC80CL31ITSC80CL51
Semiconductors
Ordering Information
Commercial Temperature Range
TSC80CL3I-V4CA
ROMless version
4 MHz
PDIL40
15.50mm
Smm
TSC80CL3I-V4CB
ROMless version
4 MHz
PLCC 44
17.50mm
4.40mm
TSC80CL31-V4CC
ROMless version
4 MHz
PQFP44
13.90mm
2mm
TSC80CL31-V4CD
ROMless version
4 MHz
PQFP44
12.30mm
2mm
TSC80CL31-V4CE
ROMless version
4 MHz
VQFP44
12mm
lAO mm
TSC80CL31-V4CF
ROMless version
4 MHz
TQFP44
12mm
Imm
TSC80CL51 xxx-V4CA
MASKROM version
4 MHz
PDIL40
15.50 mm
5mm
TSC80CL5Ixxx-V4CB
MASKROM version
4 MHz
PLCC44
17.S0mm
4AO mm
TSC80CLSI xxx-V4CC
MASKROM version
4MHz
PQFP44
13.90 mm
2mm
TSC80CLSlxxx-V4CD
MASKROM version
4 MHz
PQFP44
12.30 mm
2mm
TSC80CL51 xxx-V4CE
MASKROM version
4 MHz
VQFP44
12mm
lAO mm
TSC80CL5Ixxx-V4CF
MASKROM version
4 MHz
TQFP44
12mm
I mm
Options: Tape and Reel & Dry Pack, Secret ROM, Secret Tag and Die offering.
Please consult your sales office.
Product Marking:
For PDIL 40, PLCC 44 & QFP 44 Packages
TEMIC
Customer PIN
Temic PIN
© Intel 80, 82
YYWW Lot Number
11.3.16
MATRAMHS
Rev. A (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
CMOS 0 to 44 MHz Single Chip 8-bit Microntroller
Description
TEMIC's 80C52 and 8OC32 are high performance CMOS
versions of the 8052/8032 NMOS single chip 8 bit lie.
The fully static design of the TEMIC 8OC52/8OC32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC, without
loss of data.
The 80C52 retains all the features of the 8052 : 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers ; a 6-source, 2-level interrupt structure ; a full
duplex serial port ; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2 software-selectable
• 8OC32: Romless version of the 8OC52
• 8OC32/8OC52-Ll6: Low power version
Vcc:2.7-5.5V
Freq:0-16MHz
• 8OC32/8OC52-12: 0 to 12 MHz
• 8OC32/8OC52-16: 0 to 16 MHz
• 8OC32/8OC52-20: 0 to 20 MHz
• 8OC32/8OC52-25: 0 to 25 MHz
• 8OC32/80C52-30: 0 to 30 MHz
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial port and the interrupt
system continue to function. In the power down mode the
RAM is saved and all other functions are inoperative.
The 80C32 is identical to the 8OC52 except that it has no
on-chip ROM. TEMIC's 80C52/8OC32 are manufactured
using SCMOS process which allows them to run from 0
up to 44 MHz with Vcc = 5 V.
TEMIC's 80C52 and 8OC32 are also available at 16 MHz
with 2.7 V < Vee < 5.5 V.
•
•
•
•
8OC32/80C52-36: 0 to 36 MHz
8OC32-40: 0 to 40 MHz*
8OC32-42: 0 to 42 MHz*
8OC32-44: 0 to 44 MHz*
* 0 to 70'e temperature range.
For other speed and temperature range availability please consult your
sales office.
Features
•
•
•
•
•
•
•
Power control modes
256 bytes of RAM
8 Kbytes of ROM (8OC52)
32 programmable 110 lines
Three 16 bit timer/counters
64 K program memory space
64 K data memory space
•
•
•
•
•
•
Fully static design
0.811 CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
Temperature range: commercial, industrial, automotive,
military
Optional
• Secret ROM: Encryption
• Secret TAG: Identification number
MATRAMHS
Rev. G (14 Jan. 97)
H.4.1
II
TEMIC
80C32/80C52
Semiconductors
Interface
Figure 1. Block Diagram
POO-P07
vee
r
P20-P27
~~~~r------
vs?,
"'"
-1
1
I
I
I
1
1
1/'----.1
1
1
I
I
I
1
1
I
1
1
I
1
Pl0-P17
II.4.2
P30-P37
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
Figure 2. Pin Configuration
vee
T2/P1.0
1
40
T2EX/11
2
39
POO/AO
P1.2
3
38
POi/Ai
P1.3
4
37
PiA
5
36
PO.2/A2 INDEX
CORNER
PO.3/A3
P1.5
6
35
POA/A4
P1.6
7
34
PO.5/A5
P1.7
8
RST
9
P3.0/RXD
10
P3.1(fXD
11
C\J
P3.2/INTO
12
P3.3/INT1
13
P3.4(f0
C\J
u
""
0
!"?
C')
u
0
co
14
33
P06/AS
32
PO.7/A 7
31
EA
30
ALE
29
PSEN
28
P2.7/A15
27
15
26
P2.5/A13
P3.6/WR
16
25
P2A/A12
P37/RD
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
VSS
20
21
~
N
0:
0:
0
z
0
0
>
~ 0~ ~ 0~'"
0
CL
CL
0
CL
CL
P1.5
POAIA4
P1.6
PO.S/AS
P1.7
PO.6/A6
RST
PO.7/A?
RxO/P3.0
EA
NC
NC
ALE
TxO/P3.1
PSEN
lNTO/P3.2
P2.6/A14
P3.5(f1
" '"
0:: CL
INT1/P3.3
P2.7/A 14
TO/P3.4
P2.6/A13
T1/P3.5
P2.5!A 12
"cO
:'l
-'
I~ I~
x
X
<0
cO
CL
P2.0/A8
CL
;0 ;0
if)
if)
>
0
Z
"-
0-°
r!:0
~ ;;:
CLi'J
OJ
if>
>
0
Z
ro
~
CL~
m
~
0
N
J' ~ ~ ~
CL~
CL~
CL~
Flat Pack
Diagrams are for reference only. Package sizes arc not to scale.
MATRAMHS
Rev. G (14 Jan. 97)
Ir.4.3
II
TEMIC
SOC32/S0C52
Semiconductors
Pin Description
VSS
Circuit ground potential.
vee
Supply voltage during normal, Idle, and Power Down
operation,
Memory that use 16 bit addresses (MOYX @DPTR). In
this application, it uses strong internal pullups when
emitting I's. During accesses to external Data Memory
that use 8 bit addresses (MOYX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 80C52. Port 2
can sink/source three LS TTL inputs. It can drive CMOS
inputs without external pullups.
Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have I 's written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pull ups
when emitting I's. Port 0 also outputs the code bytes
during program verification in the 80C52. External
pull ups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal
pull ups. Port 3 pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pull ups. It also serves the functions
of various special features of the TEMIC 51 Family, as
listed below.
Port Pin
P3.0
P3.1
P3.2
P3.3
P3.4
P3.S
P3.6
P3.7
Port 1
Port I is an 8 bit bi-directional I/O port with internal
pullups. Port I pins that have I's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port I pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups.
Port I also receives the low-order address byte during
program verification. In the 80C52, Port I can sink/
source three LS TTL inputs. It can drive CMOS inputs
without external pull ups.
2 inputs of PORT I are also used for timer/counter 2 :
PI.O [T2) : External clock input for timer/counter 2. P 1.1
[T2EX) : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INTI (external interrupt 1)
TD (Timer 0 external input)
Tl (Timer I external input)
WR (external Data Memory write strohe)
RD (external Data Memory read strobe)
Port 3 can sink/source three LS TTL inputs. It can drive
CMOS inputs without external pull ups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to Ycc. As soon as the Reset is
applied (Yin), PORT 1, 2 and 3 are tied to one. This
operation is achieved asynchronously even if the
oscillator does not start-up.
Port 2
Port 2 is an 8 bit bi-directional I/O port with internal
pullups. Port 2 pins that have I's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Il.4.4
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
116 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink/source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
I FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pullup.
XTALl
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
osci llator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator is
used.
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds
Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
function, while the clock to the CPU is gated off.
These special modes are activated by software via the
Special Function Register, PCON. Its hardware address is
87H. PCON is not bit addressable.
Figure 3.IdIe and Power Down Hardware.
Symbol
Position
Name and Fnnction
SMOD
PCON.7
GFI
GFO
PD
PCON.6
PCON.S
PCON.4
PCON.3
PCON.2
PCON.l
IDL
PCON.O
Double Baud rate bit. When set to
ai, the baud rate is doubled when
the serial port is being used in
either modes 1, 2 or 3.
(Reserved)
(Reserved)
(Reserved)
General-purpose tlag bit.
General-purpose flag hit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
If I's are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(OOOXOOOO).
Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. Table I describes the status of the
external pins during Idle mode.
IDL
PCON,' Power Control Register
(LSB)
(MSB)
I
MATRAMHS
Rev. G (14 Jan. 97)
GFI
I
GFO
I
PD
I
IDL
I
II.4.5
B
TEMIC
SOC32/S0C52
Semiconductors
There are three ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.a to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote I to PCON.a.
The flag bits GFO and GFI may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
Power Down Mode
The instruction that sets PCON.1 is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The hardware reset initiates the Special Fucntion
Register. In the Power Down mode, VCC may be lowered
to minimize circuit power consumption. Care must be
taken to ensure the voltage is not reduced until the power
down mode is entered, and that the voltage is restored
before the hardware reset is applied which freezes the
oscillator. Reset should not be released until the oscillator
has restarted and stabilized.
Table I describes the status of the external pins while in
the power down mode. It should be. noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the data is a I, the port
pin is held high during the power down mode by the
strong pull up, Tl, shown in Figure 4.
Table 1. Status of the external pins during idle and power down modes.
Idle
Internal
Port Data
Port Data
Port Data
Port Data
Idle
External
Floating
Port Data
Address
Port Data
Power Down
Internal
o
o
Port Data
Port Data
Port Data
Port Data
Power Down
External
o
o
Floating
Port Data
Port Data
Port Data
Stop Clock Mode
Due to static design, the TEMIC 80C32/C52 clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
Figure 4.1/0 Buffers in the 80C52 (Ports 1,2, 3).
Q
FROM
PORT
LATCH
110 Ports
The I/O buffers for Ports 1, 2 and 3 are implemented as
shown in figure 4.
II.4.6
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
When the port latch contains a 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a O-to-I transition, the nFET turns off. The strong
pFET, TI, turns on for two oscillator periods, pulling the
output high very rapidly. As the output line is drawn high,
pFET T3 turns on through the inverter to supply the IOH
source current. This inverter and T form a latch which
holds the I and is supported by T2.
When Port 2 is used as an address port, for access to
external program of data memory, any address bit that
contains a I will have his strong pullup turned on for the
entire duration of the external memory access.
When an I/O pin on Ports I, 2, or 3 is used as an input, the
user should be aware that the external circuit must sink
current during the logical 1-10-0 transition. The
maximum sink current is specified as ITL under the D.C.
Specifications.
When
the
input
goes
below
approximately 2 Y, T3 turns off to save ICC current. Note,
when returning to a logical I, T2 is the only internal
pull up that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
Figure 5. Crystal Oscillator.
XTAL2: 18
XTAL1: 19
~------------~VSS:20
To drive the device from an external clock source,
XTALI should be driven while XTAL2 is left
unconnected as shown in figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
Figure 6. External Drive Configuration.
NC
XTAL2: 18
EXTERNAL
OSCILLATOR-------iXTAL1 : 19
SIGNAL
Oscillator Characteristics
XTALI and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in figure S. Either a quartz
crystal or ceramic resonator may be used.
r------ivss: 20
Hardware Description
Same as for the 80CS1, plus a third timer/counter:
TimerlEvent Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and I, it
can operate either as a timer or as an event counter. This
is selected by bit C/T2 in the Special Function Register
T2CON (Figure I). It has three operating modes :
"capture", "autoload" and "baud rate generator", which
are selected by bits in T2CON as shown in Table 2.
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON; If EXEN2 = 0, then
Timer 2 is a 16 bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt. If EXEN2 = I, then
Timer 2 still does the above, but with the added feature
MATRAMHS
Rev. G (14 Jan. 97)
that a I-to-O transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,
respectively, (RCAP2L and RCAP2H are new Special
Function Register in the 80CS2). In addition, the
transition at T2EX causes bit EXF2 in T2CON to be set,
and EXF2, like TF2, can generate an interrupt.
Table 2. Timer 2 Operating Modes.
RCLK+
TCLK
0
0
1
X
CP/RL2
TR2
MODE
...
0
1
X
X
1
1
1
0
16 bit auto-reload
16 bit capture
haud rate generator
(oft)
11.4.7
E
TEMIC
SOC32/S0C52
Semiconductors
The capture mode is illustrated in Figure 7.
with the 16 bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = I, then Timer
2 still does the above, but with the added feature that a
I-to-O transition at external input T2EX will also trigger
the 16 bit reload and set EXF2.
Figure 7. Timer 2 in Capture Mode.
The auto-reload mode is illustrated in Figure 8.
Figure 8. Timer in Auto-Reload Mode.
: CONTf-10L
FXFN2
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.If
EXEN2 = 0, then when Timer 2 rolls over it does not only
set TF2 but also causes the Timer 2 register to be reloaded
: CONTROL
EXEN2
(MSB)
(LSB)
The baud rate generator mode is selected by : RCLK = I and/or TCLK = I.
II.4.8
Symbol
Position
TF2
T2CON.7
Timer 2 overtlow flag set by a Timer 2 overflow and must be cleared by software. TF2
will not be set when either RCLK = 1 OR TCLK = I.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
software.
RCLK
T2CON.5
Receive clock flag. When set, causes the serial POlt to use Timer2 overflow pulses for its
receive clock in modes 1 and 3. RCLK : : : 0 causes Timer I overflow to be used for the
receive clock.
TCLK
T2CONA
Transmit clock flag. When set, causes the serial port to use Timer 2 overflow pulses for
its transmit clock in modes 1 and 3. TCLK:= 0 causes Timer 1 overflows to be used for
the transmit clock.
EXEN2
T2CON.3
Timer 2 external enable flag. When set, allows capture or reload to occur as a result of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic I starts the timer.
C/TI
T2CON.I
Timer or counter select. (Timer 2) 0 = Internal timer (OSCI12)
I = External event counter (falling edge triggered).
CP/RL2
T2CON.O
Capture/Reload flag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 := I. When cleared, auLo reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = I, this
bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
Name and Significance
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
Semiconductors
SOC32/S0C52
80C52 with Secret ROM
80C52 with Secret TAG
TEMIC offers 80C52 with the encrypted secret ROM
option to secure the ROM code contained in the 80C52
microcontrollers.
TEMIC offers special 64-bit identifier called "SECRET
TAG" on the microcontroller chip.
The clear reading of the program contained in the ROM
is made impossible due to an encryption through several
random keys implemented during the manufacturing
process.
The keys used to do such encryption are selected
randomwise and are definitely different from one
microcontroller to another.
This encryption is activated during the following phases:
- Every time a byte is addressed during a verify of the
ROM content, a bytc of the encryption array is
selected.
- MOVC instructions executed from external program
memory are disabled when fetching code bytes from
internal memory.
- EA is sampled and latched on reset, thus all state
modification are disabled.
The Secret Tag option is available on both ROMless and
masked microcontrollers.
The Secret Tag feature allows serialization of each
microcontroller for identification of a specific
equipment. A unique number per device is implemented
in the chip during manufacturing process. The serial
number is a 64-bit binary value which is contained and
addressable in the Special Function Registers (SFR) area.
This Secret Tag option can be read-out by a software
routine and thus enables the user to do an individual
identity check per device. This routine is implemented
inside the microcontroller ROM memory in case of
masked version which can be kept secret (and then the
value of the Secret Tag also) by using a ROM Encryption.
For further information, please refer to the application
note (ANM03I) available upon request.
For further information please refer to the application
note (ANM053) available upon request.
MATRAMHS
Rev. G (14 Jan. 97)
lI.4.9
B
TEMIC
SOC32/S0C52
Semiconductors
Electrical Characteristics
* Notice
Absolute Maximum Ratings*
Arnbiant Temperature Under Bias:
C = commercial
...................... O°C to 70°C
I = industrial. . . . . . . . . . . . .
. .... -40°C to 85°C
Storage Temperature
_65°C to + 150°C
Voltage on VCC to VSS ........................ -0.5 V to + 7 V
Voltage on Any Pin to VSS
-0.5 V to Vee + 0.5 V
1W
Power Dissipation
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
Stresses at or above those listed under" Absolute Maximum Ratings"
nUlY cause permanent damage to the device. This is a stress rating on!:}!
lind functional operation of the device at these or (Iny other conditions
above those indicated in the operational sections (~l this spec{fication is
not implied. Exposure to absolute maximum rating conditions may ({fteet
device reliability.
DC Parameters
TA
TA
=ooe to 70 e ; VSS =0 V ; vee =5 V ± 10% ; F =0 to 44 MHz
=-40 o e + 85°e ; VSS =0 V ; vee =5 V ± 10 % ; F =0 to 36 MHz
0
..
".,,,,.
.;....,: « . •.•. .•. .•.•. ••.. . < . .•. . . •
VIL
Input Low Voltage
···i ... l\1]N . . •
· ·. .······L·.· . .· · ·.· · .
··.·.·>···.·····.···.·
I·····.··••
M~ .••·. · ·•.·• I~l'l' ......
-0.5
0.2 Vee-O.I
V
0.2 Vee + 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
:",..,.
"'' ' .
VIH
Input High Voltage (Except XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port I, 2 and 3)
0.3
0.45
1.0
V
V
V
10L= 100flA
10L = 1.6 rnA (note 2)
10L = 3.5 rnA
VOLI
Output Low Voltage (Port 0, ALE, PSEN)
0.3
0.45
1.0
V
V
V
10L = 200 flA
10L = 3.2 rnA (note 2)
IOL=7.0mA
VOH
Output High Voltage Port I, 2, 3
VOHI
Output High Voltage (P0l1 0, ALE, PSEN)
Vee - 0.3
V
10H=-IOflA
Vee - 0.7
V
10H =-30 flA
Vee - 1.5
V
10H =-60 flA
VCC=5V±10%
Vee - 0.3
V
10H = -200 flA
Vee - 0.7
V
IOH=-3.2 rnA
Vee - 1.5
V
IOH=-7.0mA
VCC=5 V± 10%
ilL
Logical 0 Input Current (Ports I, 2 and 3)
-50
flA
Yin = 0.45 V
ILl
Input leakage Current
±10
flA
0.45 < Yin < Vee
ITL
Logical I to 0 Transition Current (Ports 1,2 and 3)
-650
flA
Yin = 2.0 V
IPD
Power Down Current
50
flA
Vee = 2.0 V to 5.5 V (note I)
200
KOhm
10
pF
1.8
I
10
4
rnA
rnA
rnA
rnA
RRST
RST Pulldown Resistor
CIO
Capacitance of 1/0 Buffer
ICC
Power Supply Current
Freg = I MHz Icc op
Icc idle
Freg = 6 MHz Icc op
Icc idle
Freg;' 12 MHz Icc or = 1.25 Preg (MHz) + 5 mA
Icc idle = 0.36 Freq (MHz) + 2.7 rnA
II.4.IO
50
fe = I MHz, Ta = 25"C
Vee=5.5V
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
* Notice
Absolute Maximum Ratings*
Ambient Temperature Under Bias:
.......... -40°C to + 125°C
A::: Automotive
_65°C to + 150°C
Storage Temperature
Voltage on VCC to VSS ........................ -0.5 V to + 7 V
. -0.5 V to VCC + 0.5 V
Voltage on Any Pin to VSS
Stresses llbove lhos(-' listed Linder" Absolute Maximum Ratings" may
("llU.\C pemlllnenl danwKc to the dn,;c:e. This is (f stress rei/in;.: only and
.tltl1ctiona/ operation qlthe device at these or allY other conditions above
those indicated in the operatiollal sections of rhis specUicaliol1 i..o not
implied. Exposure to absolute maximulJI rating cOl1ditiol1s.tor extended
periods may qffeet device reliability.
IW
Power Dissipation
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA =-40 o e + 125°e ; VSS
SYM8(jL
VIL
PARAMETER
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port I, 2 and 3)
VOLI
Output Low Voltage (Port 0, ALE, PSEN)
VOH
Output High Voltage Port I. 2 and 3
VOHl
II
=0 V ; vee =5 V ± 10 % ; F =0 to 36 MHz
Output High Voltage (Port 0, ALE. PSEN)
MIN
MAX
UNIT
-0.5
0.2 Vee - 0.1
V
TEST CONDITIONS
0.2 Vee + 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
0.3
0.45
1.0
V
V
V
IOL~
0.3
0.45
1.0
V
V
V
IOL= 200 /lA
10L = 3.2 rnA (note 2)
IOL=7.0rnA
10L~
IOL
~
100/lA
1.6 rnA (note 2)
3.5 rnA
Vee - 0.3
V
10H = -10 /lA
Vee - 0.7
V
IOH =-30 /lA
Vee - 1.5
V
IOH=-60/lA
VCC=5V± 10 %
Vee - 0.3
V
IOH = - 200 J.lA
Vee - 0.7
V
IOH=-3.2mA
Vee - 1.5
V
IOH=-7.0 mA
VCe=5 V± 10 %
ilL
Logical 0 Input Current (Ports 1,2 and 3)
-75
/lA
Yin = 0.45 V
ILl
Input leakage Current
±IO
J.lA
0.45 < Yin < Vee
ITL
Logical I to 0 Transition Current (Ports I, 2 and 3)
-750
/lA
Yin = 2.0 V
IPD
Power Down Current
75
J.lA
Vee = 2.0 V to 5.5 V (note I)
200
KOhrn
10
pF
1.8
I
10
4
rnA
rnA
rnA
rnA
RRST
RST Pulldown Resistor
CIO
Capacitance of 110 Buffer
ICC
Power Supply Current
Freq = I MHz Icc op
Icc idle
Freq = 6 MHz Icc op
Icc idle
Freq" 12 MHz Icc op = 1.25 Freq (MHz) + 5 rnA
Icc idle = 0.36 Freq (MHz) + 2.7 rnA
MATRAMHS
Rev. G (14 Jan, 97)
50
fc = I MHz, Ta = 25'C
Vce=5.5 V
11.4.11
TEMIC
SOC32/S0C52
Semiconductors
* Notice
Absolute Maximum Ratings*
Stresses at or above those listed under" Absolute Maximum Ratings"
Ambient Temperature U ndef Bias:
lIlay c({use permanent dO!1wge to the device. This is l/ stress rating onl.r
M = Military ............................... -55"C to +12S"C
Storage Temperature
-65"C to + 150"C
([ndfuncfional operation (~l the device at these or un}' other conditions
above those indicated in the opermioJ1a/ sections (~f'this spec~ric(/ti()n is
. -0.5 V to + 7 V
not implied. E'K{'osure to absolute maximum rating conditions may affect
Voltage on VCC to VSS .
Voltage on Any Pin to VSS
. -0.5 V to VCC + 0.5 V
Power Dissipation
dC1".;ce reliahility,
IW
* This value is based on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA = -55°C + 125°C; Vss
= 0 V; Vee = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
Input High Vnltage (Except XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
MIN
MAX
UNIT
-0.5
0.2 Vec - 0.1
V
0.2 Vcc+ 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
TEST CONDITJONS
Output Low Voltage (Port 1,2 and 3)
0.45
V
IOL = 1.6 mA (note 2)
VOLI
Output Low Voltage (Port 0, ALE, PSEN)
0.45
V
IOL = 3.2 mA (note 2)
VOH
Output High Voltage (Port I, 2 and 3)
2.4
V
IOH =-60 ~A
Vee=5V±IO%
0.75 Vee
V
IOH =- 25
~A
~A
VOL
VOHI
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
0.9 Vee
V
IOH=-1O
2.4
V
IOH=-400~A
Vee=5 V± 10%
0.75 Vee
V
IOH=-150~A
0.9 Vee
V
IOH=-40~A
IlL
Logical 0 Input Current (Ports I, 2 and 3)
-75
~A
Yin = 0.45 V
ILl
Input leakage Current
+/-10
~A
0.45 < Yin < Vee
ITL
Logical I to 0 Transition Current (Ports I, 2 and 3)
-750
~A
Yin = 2.0 V
IPD
Power Down Current
75
~A
Vee = 2.0 V to 5.S V (note I)
200
Kfl
10
pF
1.8
I
10
4
rnA
rnA
rnA
rnA
RRST
RST Pull down Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freg = I MHz lec op
Icc idle
Freg = 6 MHz lee op
Icc idle
Freg" 12 MHz Icc op = 1.25 Freg (MHz) + 5 mA
Icc idle = 0.36 Freg (MHz) + 2.7 rnA
11,4,12
50
fe = I MHz, Ta = 25'C
Vcc=5.5V
MATRAMHS
Rev, G (14 Jan, 97)
TEMIC
SOC32/S0C52
Semiconductors
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias:
Stresses at or above those listed under" Absolute Maximum Ratings"
may ("lIuse permanent damage to the device. This is {/ stress rating only
C::::: Commercial ................................
I = Industrial ............
lIIU/jtlf1cti01W/ operatio/l (l the dCTice (If these OF any other conditions
(//Jove those indico/ed il1 the operational sections (d this specUlcatiol1 is
1101 i1l1/}{ied. E\posure to ahsolute I1ll1ximlfl11 rating cOIulif;OI7S f7wy affect
device reliahility.
-65"C to + 150"C
Storage Temperature
Voltage on VCC to
ooe to 70°C
-40 to 85"C
vss .
..... -0.5 V to + 7 V
Voltage on Any Pin to VSS
.. -0.5 V to VCC + 0.5 V
I w*·'
This value is based on the maximum allowahle die temperature and
the thermal resistance of thc package
Power Dissipation
':,*
B
DC Characteristics
TA = oce to 70 o e; Vee = 2.7 V to 5.5 V ; Vss = 0 V; F = 0 to 16 MHz
TA = -40 o e to 85°e ; Vee = 2.7 V to 5.5 V
SYMBOL
PARAMETER
VIL
Input Low Voltage
MIN
MAX
UNIT
-0.5
0.2 Vee -0.1
V
VIH
Input High Voltage (Except XTAL and RST)
0.2 Vee + 1.4
Vee + 0.5
V
VIH2
Input High Voltage to RST for Reset
0.7 Vee
Vee +0.5
V
VIHI
Input High Voltage to XTALI
0.7 Vee
Vee +0.5
V
TEST CONDITIONS
VPD
Power Down Voltage to Vec in PO Mode
5.5
V
VOL
Outpot Low Voltage (Ports 1,2,3)
0.45
V
10L ~ O.S rnA (note 2)
VOLI
Output Low Voltage Port 0, ALE, PSEN
0.45
V
10L
VOH
Output High Voltage Ports 1. 2, 3
0.9 Vee
V
10H~-lOflA
VOHI
Output High Voltage (Port 0 in External Bus
Mode), ALE, PSEN
0.9 Vee
V
IOH~
ilL
20
Logical 0 Input Current Ports I, 2. 3
-50
flA
Yin
~
~
1.6 rnA (note 2)
-40flA
0.45 V
ILl
Input Leakage Current
±IO
flA
0.45 < Yin < Vee
ITL
Logical 1 to 0 Transition Current
(Ports 1.2,3)
-650
flA
Vin~
VCC
IPD
Power Down Current
RRST
CIO
RST Pulldown Resistor
50
Capacitance of 110 Butfer
50
flA
200
kQ
10
pF
2.0 V
~
2.0 V to 5.5 V (note 1)
fc = I MHz, TA = 25"C
Maximum Icc (rnA)
.:
.··c'
.:.c..·.<
::
OPERATING (NOTE 1)
IDLE (NOTE 1 ) ' ; c
e
FREQUENCYN ee
2.7V
3V
3.3 V
5.5 V
2.7 V
3V
3.3 V
I MHz
O.SmA
ImA
l.l rnA
I.SmA
400flA
500 flA
600 flA
I rnA
6MHz
4mA
SmA
6mA
1.5mA
I.7 rnA
2 rnA
4mA
12MHz
SmA
lOrnA
12mA
2.5 rnA
3mA
3.5mA
16MHz
lOrnA
12mA
14mA
3mA
3.S rnA
4.5 rnA
Freq> 12 MHz (Vee = 5.5 V)
MATRAMHS
Rev. G (14 Jan. 97)
lOrnA
5.5 V
Icc (rnA) ~ 1.25 x Freq (MHz) + 5
Icc Idle (rnA) ~ 0.36 x Freq (MHz) + 2.7
IIA.13
TEMIC
SOC32/S0C52
Semiconductors
Notel: ICC is measured with all output pins
disconnected ; XTALl driven with TCLCH, TCHCL =
5 ns, VIL = VSS + .5 V, VIH = VCC -.5 V ; XTAL2
N.e. ; EA = RST = Port 0 = VCe. ICC would be slighty
higher if a crystal oscillator used.
Figure 9. ICC Test Condition, Idle Mode.
All other pins are disconnected.
Idle ICC is measured with all output pins disconnected;
XTALl driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 5 V, VIH = VCC -.5 V ; XTAL2 N.C ; Port 0 =
VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST= VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports 1 and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make I to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
may exceed 0.45 V with maxi VOL peak 0.6 V. A Schmitt
Trigger use is not necessary.
RST
(NC)
CLOCK
SIGNAL
EA
XTAL2
XTAL1
VSS
Figure 10. ICC Test Condition, Active Mode.
All other pins are disconnected.
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 11. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 12. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL
=5 ns.
TCHCL
~------TCLCL.-------+1
11.4.14
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
Explanation of the AC Symbol
Each timing symbol has 5 characters. The first character
is always a "T" (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
A: Address.
C: Clock.
D : Input data.
H: Logic level HIGH
I : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
Example:
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
Q : Output data.
R : READ signal.
T: Time.
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
II
AC Parameters
TA = 0 to + 70°C; V 5S = 0 V ; Vcc = 5 V ± 10 % ; F = 0 to 44 MHz
TA = 0 to +70°C; Vss = 0 V; 2.7 V < Vcc < 5.5 V; F = 0 to 16 MHz
TA=-40° (0+ 85°C; Vss=OV; 2.7 V
··.16~FlZ· 20.MHi!: 25 MHz
i
....•....... "ARAMETER.
..
'
.....
....
30 MHz 36 MHz 40 MHz 4ZMHz 44 MHz
min max min max min max min IlIlIx min max min IlIlIX min
......
max min max
TLHLL
ALE Pulse Width
110
90
70
60
50
40
35
TAVLL
Address valid to ALE
40
30
20
15
10
9
8
7
TLLAX
Address Hold After ALE
35
35
35
35
35
30
25
17
TLLIV
ALE to valid instr in
TLLPL
ALEtoPSEN
45
TPLPH
PSEN pulse Width
165
TPLIV
PSEN to valid instr in
TPXIX
Input instr Hold After PSEN
TPXIZ
Input instr Float After PSEN
TPXAV
PSEN to Address Valid
185
170
40
130
125
0
50
45
35
30
35
60
45
0
54
40
25
35
0
0
20
25
30
65
12
13
65
50
0
65
70
15
75
65
0
40
80
20
80
85
0
50
100
25
100
110
0
55
130
30
30
15
20
10
15
-~
TAVIV
Address to Valid instr in
TPLAZ
PSEN low to Address Float
230
210
170
l30
90
80
75
70
10
10
8
6
5
5
5
5
External Program Memory Read Cycle
ALE
PORT 2 _ _ _ _o f
MATRAMHS
Rev. G (14 Jan. 97)
11.4.15
TEMIC
SOC32/S0C52
Semiconductors
External Data Memory Characteristics (values in ns)
. .·.·>.i.i······.·.·. . . . . . . . •. ·. · . ·. . ·.·.·.·.· . . i . . . . . 16lVl~..
••• i.
SBb~-. ··~AT>l~~~~D··i
.: ........ ...........
1.~iJ
~....
1ll!}~
. .....
min m!}X mill m!}x
36MIIz .40MIIz
........
I.
Initl 1Jl1~"
.... ....,{
2~Mflz
2SMJ:1z 3& MHz
1<
'::"
"'-
-',-.
~,
4~lVl~z ."".Mllz
mi~ lit!}X .lI)in IntU
TRLRH
RD pulse Width
340
270
210
180
120
100
90
TWLWH
WR pulse Width
340
270
210
180
120
100
90
80
TLLAX
Address Hold After ALE
85
85
70
55
35
30
25
25
TRLDV
RD to Valid Data in
TRHDX
Data hold after RD
210
TRHDZ
Data float after RD
TLLDV
ALE to Valid Data In
TAVDV
Address to Valid Data IN
TLLWL
ALE to WR or RD
150
TAVWL
Address to WR or RD
180
TQVWX
Data valid to WR transition
35
35
30
20
15
10
TQVWH
Data Setup to WR transition
380
325
250
215
170
160
TWHQX
Data Hold after WR
40
TRLAZ
RD low to Address Float
TWHLH
RD or WR high to ALE high
240
0
0
135
110
0
90
0
0
80
70
0
0
90
90
80
70
50
45
40
35
435
370
290
235
170
150
140
130
480
250
400
135
170
180
35
90
320
120
130
140
0
35
60
260
90
20
45
60
15
175
170
90
55
50
60
55
150
140
20
6
0
40
15
85
6
10
0
40
95
65
0
20
180
100
70
75
0
25
190
115
115
30
0
35
175
0
80
35
0
13
0
33
13
33
External Data Memory Write Cycle
L
TWHLH
£
"\
ALE
I--- TLLWL---!
.hJ
TAVWL
I-fPORTO
PORT 2
>--<
ADDRESS
OR SFR·P2
~TLLAX+j
AO·A7
~
TWLWH
TQVWX
/
TQVWH
I.e TWHQX~
!
DATA OUT
I
)<
ADDRESSA8·A15 OR SFR·P2
External Data Memory Read Cycle
r----,..
1·..,......- - - - T L L D V - - - -.....~I
TWHLH
~
ALE
PSEN
RD
-------~-----~ I~~---+TRLRH----__·~~~--TRHDX
PORTO
DATA IN
PORT21
II.4.16
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
Serial Port Timing - Shift Register Mode (values in ns)
•. . •. • >.. ~ . . . .
••..~~ ...
..•.
16 MHz 20 MHz 25 MHz 30 MHz 36 MHz 40 MHz 42MlU #MlU
PARAMETER
min max min max min max min max min max min max min max min max
TXLXL
Serial Port Clock Cycle Time
750
600
480
400
330
250
230
227
TQVXH
Output Data Setup to Clock
Rising Edge
563
480
380
300
220
170
150
140
TXHQX
Output Data Hold after Clock
63
90
65
50
45
35
30
25
0
0
0
0
0
0
0
0
Rising Edge
TXHDX
Input Data Hold after Clock
B
Rising Edge
TXHDV
Clock Rising Edge to Input
Data Valid
350
450
563
300
250
200
180
6
7
8
160
Shift Register Timing Waveforms
INSTRUCTION
o
3
2
4
5
CLOCK
OUTPUT DATA
WRITE
~O
INPUT
SBUF
TXHDVI--l
DATA~=====~"
...
CLEAR RI
MATRAMHS
Rev. G (14 Jan. 97)
~~
...
SETIN
TXHDX
...
SET IN
IIA.17
TEMIC
SOC32/S0C52
Semiconductors
External Clock Drive Characteristics (XTALl)
SYMBOL
.....
PARAM£1'ER . .•.•.
FCLCL
Oscillator Frequency
TCLCL
Oscillator period
TCHCX
TCLCX
<
MIN
..
.... i
.
.....•..•..
.....
{lNl! . ...
MAX·.·.···.·.·•. ·•..
MHz
44
22.7
os
High Time
5
os
Low Time
5
os
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
os
External Clock Drive Waveforms
TCHCL
~------TCLCL--------+I
AC Testing Input/Output Waveforms
=X
INPUT/OUTPUT
vec-
o,5V
0,45 V
0,2 Vee + 0,9
)C
_.,.;0;,:;,2;;,.V,;,,;c"'c_-.,.;0;:,.,1;,..-_ _ __
AC inputs during testing are dri ven at Vcc - 0.5 for a logic" I" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic" I" and VIL max for a logic "0".
Float Waveforms
FLOAT
foooO.---- FLOAT - - - - - - I
VLOAD
VLOAD + 0,1 V
VLOAD-O,1 V
For timing purposes as port pin is no longer tloating when a 100 mV change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOHIVOL level occurs. IollIoH ~ ± 20 mA.
ILl.! X
MAfRAMHS
Rev. G (14 Jan. 97)
TEMIC
SOC32/S0C52
Semiconductors
Clock Waveforms
STATE 4
INTERNAL
CLOCK
I
STATE 5
STATE 6
STATE 1
STATE 21
STATE 3
STATE 4 1 STATE 5 1
1
P1
I P2
P1
I P21 P1
I P2 1 P1
I P21 P1
I P2
P1
I P2
P1
I
P2
P1
I P2
XTAL2
"
ALE
PSEN
,
L-
I
B
'--_ _~DATA
PO
P2 (EXl)
I
" " THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
,----------,
'-----_--L-_----'
1_
J
Fi~~~L~
1-
_ _ _ _--'IINDICATES ADDRESS TRANSITIONSIL-_ _ _ _ _ _ _ _ _--'
READ CYCLE
RD
OOH IS EMITTED
DURING THIS PERIOD
PO
____
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
~-D-P-L-O-R-R-i~lrT~-,-----~~~~---~1
I..!..I.
OUT
.1
FLOAT SAMPLED
t
+
~
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
L _ _ _ _ _ _ _ _ _ _--'I PCLOUT (EVEN IF PROGRAM
WR
MEMORY IS INTERNAL)
DPLORRi
OUT
PO
~
I
I.
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
P2
·L
'I
~I--~CLOUT(IFPROGRAM
I MEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT SRC
__________
O_LD_D_AT_A-.JI NEW DATA
MApO
MOVDESTPO
MOV DEST PORT-(P-1-,P-2-,P-3-)--'
(INCLUDES INTO, INT1, TO, T1)
~
ITI'-----------------------'FTL
____________I~*.~I
SERIAL PORT SHIFT CLOCK
TXD
(MODE 0)
PINS SAMPLED
PO PINS SAMPLED
P1 P2, P3 PI NS SAMPLED
RXD SAMPLED
I
P1. P2, P3
PINS SAMPLED
~rRXD SAMPLED
This diagram indicates when signals arc clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
MATRAMHS
Rev. (J (14 Jan. 97)
[[.4.19
TEMIC
SOC32/S0C52
Semiconductors
Ordering Information
S
T
Temperature Range
blank : Commercial
I
: Industrial
A
: Automotive
M
: Military
80C52C
xxx
-36
T
Part Number
80C52 Rom 8 K x 8
80C32 External ROM
80C52C Secret ROM version
80C52T Secret Tag version
80C32E Radiation Tolerant
80C52E Radiation Tolerant
-12
-16
-20
-25
-30
-36
-40
-42
-44
-Ll6
Package Type
P: POlL 40
S: PLCC44
FI: PQFP 44 (Foot print 13.9 mm)
F2: PQFP 44 (Foot print 12.3 mm)
Y: YQFP (1.4 mm)
T: TQFP (1.0 mm)
D: COIL 40
Customer Rom Code
Q: CQFP44
R: LCC44
C: Side Braze 40 (.6)
D
T
: 12 MHz version
: 16 MHz version
: 20 MHz version
: 25 MHz version
: 30 MHz version
: 36 MHz version
: 40 MHz version (1)
: 42 MHz version (I)
: 44 MHz version (1)
: Low Power
(Vcc : 2.7-5.5 V
Freq: 0-16 MHz)
R : Tape and Reel
D: Dry Pack
Flow
/883 MIL compliant
PS83 MIL compliant with PIND test
SB SCC9000 level B
SC SCC9000 level C
(I) Only for 80C31 at commercial range.
II.4.20
MATRAMHS
Rev. G (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
CMOS 0 to 36 MHz Single Chip 8-bit Microcontroller
Description
TEMIC's 80CI54 and 83CI54 are high performance
CMOS single chip ]lc. The 83CI54 retains all the
features of the 80C52 with extended ROM capacity (16
K bytes), 256 bytes of RAM, 32 1/0 lines, a 6-source
2-level interrupts, a full duplex serial port, an on-chip
oscillator and clock circuits, three 16 bit timers with extra
features: 32 bit timer and watchdog functions, Timer 0
and I can be configured by program to implement a 32 bit
timer, The watchdog function can be activated either with
timer 0 or timer 1 or both together (32 bit timer).
In addition, the 83C 154 has 2 software-selectable modes
of reduced activity for further reduction in power
•
•
•
•
•
•
SOC 154 : ROMless version of the 83C 1541l
80CI54/83CI54-12: a to 12 MHz
80CI54/S3CI54-l6: a to 16 MHz
SOCI54/S3CI54-20: a to 20 MHz
SOC l54/83C 154-25 : a to 25 MHz
80Cl 54/83C I 54-30 : a to 30 MHz
consumption. In the idle mode the CPU is frozen while
the RAM is saved, and the timers, the serial port and the
interrupt system continue to function. In the power down
mode the RAM is saved and the timers, serial port and
interrupt continue to function when driven by external
clocks. In addition as for the TEMIC 80C51/80C52, the
stop clock mode is also available.
The 80C 154 is identical to the 83C 154 except that it has
no on-chip ROM. TEMIC's 80C 154 and 83C 154 are
manufactured using SCMOS process which allows them
to run from 0 up to 36 MHz with Vec = 5 V.
• SOC I54/83C I54-36 : a to 36 MHz
• 80C I54/83C I 54-L16 : Low power version
VCC: 2.7-5.5 V Fre'!: 0-16 MHz
For other speed and temperature range availability please consult your
sales office.
Features
• Power control modes
• 256 bytes of RAM
• 16 Kbytes of ROM (83CI54)
• 32 Programmable I/O lines (programmable impedance)
• Three 16 bit timer/counters (including watchdog and 32 bit
timer)
• 64 K program memory space
• 64 K data memory space
•
•
•
•
•
•
Fully static design
0.81l CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
Temperature range: commercial, industrial, automotive,
military
Optional
• Secret ROM: Encryption
• Secret TAG: Identification number
MATRAMHS
Rev.F (14 Jan. 97)
II.5.1
2
TEMIC
80C154/83C154
Semiconductors
Interface
Figure 1. Block Diagram
POO-P07
P20-P27
---l
r
vs?,
vee
"
I
I
I
I
I
I
I
I
I
I
I
I.---~
PSEN
ALE
EA
RST
I'---.I.=-.J
:~
t:;~f'
IIS2
____
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-1
P30-P37
MATRAMHS
Rev.F(l4 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Figure 2. Pin Configuration
x
w
T2/P1.0
T2EX/1.1
P1.2
P1.3
4
P1A
P1.5
6
P1.6
.q>n
P1.7
U
RST
C')
00
P3.0/RXD
10
P3.1(TXD
11
>n
P3.2/1 NTO
12
U
P3.3/1 NT1
13
~
0
00
40
vee
39
PO.O/AO
38
PO.1/A 1
37
PO.2/A2
36
PO.3/A3
35
POA/A4
34
PO.5/A5
v
'"
0: 0:
INDEX
CORNER
N
~
g
0: 0: 0:
0
2;
i?
N
'"
~
fOx fO
x
--'
u
z
0
oj
0..
"
~
:;;: §!
0..°
?l
fO
X
0
Z
00
m
'" 'f"
o..N
0
N
~ o..N
~ o..N
~
o..N
Flat Pack
Diagrams arc for reference only. Package sizes arc not to scale
MATRAMHS
Rcv.F (14 Jan. 97)
11.5.3
II
TEMIC
80C154/83C154
Semiconductors
Pin Description
vss
Port 2
Circuit Ground Potential.
Port 2 is an 8 bit bi-directional 110 port with internal
pullups. Port 2 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pullups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOYX @DPTR). In
this application, it uses strong internal pull ups when
emitting I's. During accesses to external Data Memory
that use 8 bit addresses (MOYX @Ri), Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C 154. Port
2 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
vee
Supply voltage during normal, Idle, and Power Down
operation.
PortO
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have I 's written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pull ups
when emitting I's. Port 0 also outputs the code bytes
during program verification in the 83C154. External
pull ups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port 1
Port I is an 8 bit bi-directional I/O port with internal
pull ups. Port 1 pins that have 1's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 1 pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups.
Port 3
Port 3 is an 8 bit bi-directional 110 port with internal
pullups. Port 3 pins that have l's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the TEMIC 51 Family, as
listed below.
Port Pin
Port I also receives the low-order address byte during
program verification. In the 83C154, Port I can sink or
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
2 inputs of PORT I are also used for timer/counter 2 :
P 1.0 [T2] : External clock input for timer/counter 2. PI.I
[T2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INTI (external interrupt I)
TO (Timer 0 external input)
Tl (Timer I external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to YCe. As soon as the result is
applied (Yin), PORT I, 2 and 3 are tied to I. This
operation is achieved asynchronously even if the
oscillator is not start up.
11.5.4
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
ALE
XTALl
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time one ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator,
and input to the internal clock generator. This pin should
be floated when an external oscillator is used.
B
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pull up.
When EA is held high, the CPU executed out of internal
Program Memory (unless the Program Counter exceeds
3FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
Idle and Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. The interrupt, serial port, and timer
blocks continue to function only with external clock
(INTO, INTI, TO, TI).
Figure 3. Idle and Power Down Hardware.
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
IDL
MATRAMHS
Rev.F (14 Jan. 97)
II.S.S
TEMIC
80C154/83C154
Semiconductors
PCON: Power Control Register
(MSB)
(LSB)
ISMOD I HPD I RPD I
I GFI
I GFO I PD
I IDL
Symbol
Position
Name and Fnnction
SMOD
PCON.7
HPD
PCON.6
Double Baud rate bit. When set to
a I, the baud rate is doubled when
the serial port is being used in
either modes 1,2 or 3.
Hard power Down bit. Setting this
bit allows CPU to enter in Power
Down state on an external event
(I to 0 transition) on bit TI
(p. 3.5) the CPU quit the Hard
Power Down mode when bit T 1
p. 3.5) goes high or when reset is
aClivated.
Recover from Idle or Power Down
bit. When 0 RPD has no elfetc.
When I, RPD permits to exit Irom
idle or Power Down with any non
enabled interrupt source (except
lime 2). In this case the program
start at the next address. When
interrupt is enabled, the
appropriate interrupt routine is
serviced.
General-purpose nag bit.
General-purpose nag bit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activates idle mode operation.
RPD
PCON.S
GFI
GFO
PD
PCON.3
PCON.2
PCON.I
IDL
PCON.O
I
If 1's are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(OOOXOOOO).
Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. In the idle mode, the internal clock signal
is gated off to the CPU, but interrupt, timer and serial port
functions are maintained. Table 1 describes the status of
the external pins during Idle mode. There are three ways
to terminate the Idle mode. Activation of any enabled
interrupt will cause PCON.O to be cleared by hardware,
terminating Idle mode. The interrupt is serviced, and
following RET!, the next instruction to be executed will
be the one following the instruction that wrote 1 to
PCON.O.
11.5.6
The flag bits GFO and GFI may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
The third way to terminate the Idle mode is the activation
of any disabled interrupt when recover is programmed
(RPD = 1). This will cause PCON.O to be cleared. No
interrupt is serviced. The next instruction is executed. If
interrupt are disabled and RPD = 0, only a reset can
cancel the Idle mode.
Power Down Mode
The instruction that sets PCON.l is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The three ways to terminate the Power Down mode
are the same than the Idle mode. But since the onchip
oscillator is stopped, the external interrupts, timers and
serial port must be sourced by external clocks only, via
INTO, INTI, TO, Tl.
In the Power Down mode, VCC may be lowered to
minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power down
mode is entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator. Reset
should not be released until the oscillator has restarted
and stabilized.
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the VCC
specification limits.
Table I describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port data that is held in the Special Function
Register P2 is restored to Port 2. If the port switches from
o to 1, the port pin is held high during the power down
mode by the strong pull up, TI, shown in figure 4.
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Table 1. Status of the external pins during idle and power down modes.
MODE
PROGRAM MEMORY
ALE
PSEN
PORTO
PORT!
PORT2
PO.RT~
IdIe
Internal
I
I
Port Data
Port Data
Port Data
Port Data
Port Dala
IdIe
External
I
I
Floating
Port Data
Address
Power Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power Down
External
0
0
Floating
Port Data
Port Data
Port Data
Figure 4. I/O Buffers in the 83C154 (Ports 1, 2, 3).
vee vee
FLOAT
Q
vee
--t:====.J
FROM
iii~~
C>--t--:ft------1IL
FLOAT
FLOAT
-----.J.,.,;>--;;i'uT:;::::;::=:::/
Stop Clock Mode
Due to static design, the TEMIC 83C154 clock speed can
be reduced until 0 MHz without any data loss in memory
or registers. This mode allows step by step utilization, and
permits to reduce system power consumption by bringing
the clock frequency down to any value. At 0 MHz, the
power consumption is the same as in the Power Down
Mode.
I/O Ports
The I/O drives for PI, P2, P3 of the 83CI54 are
impedance programmable. The 110 buffers for Ports I, 2
and 3 are implemented as shown injigure 4.
When the port latch contains 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a O-to-I transition, the nFET turns off. The strong
pullup pFET, TJ, turns on for two oscillator periods,
pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the 10H source current. This inverter and T3 form
a latch which holds the I and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains a
I will have his strong pull up turned on for the entire
duration of the external memory access.
When an I/O pin on Ports 1,2, or 3 is used as an input, the
user should be aware that the external circuit must sink
current during the logical I-to-O transition. The
MATRAMHS
Rev.F (14 Jan. 97)
maximum sink current is specified as ITL under the D.C.
Specifications.
When
the
input
goes
below
approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical I, T2 is the only internal
pull up that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
The input impedance of Port I, 2, 2 are programmable
through the register IOCON. The ALF bit (IOCONO) set
all of the Port I, 2, 3 floating when a Power Down mode
occurs. The PIHZ, P2HZ, P3HZ bits (lOCONI,
IOCON2, IOCON3) set respectively the Ports PI, P2, P3
in floating state. The IZC (lOCON4) allows to choose
input impedance of all ports (PI, P2, P3). When IZC = 0,
T2 and T3 pull up of I/O ports are active; the internal input
impedance is approximately 10K. When IZC = I only T2
pull-up is active. The T3 pull-up is turned off by IZC. The
internal impedance is approximately 100 K.
Oscillator Characteristics
XTALI and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in figure 5. Either a quartz
crystal or ceramic resonator may be used.
Figure 5. Crystal Oscillator.
XTAL2: 18
XTAL1 : 19
r-------------~VSS:20
To drive the device from an external clock source,
XTALl should be driven while XTAL2 is left
unconnected as shown in figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
II.S.7
B
TEMIC
80C154/83C154
Semiconductors
Figure 6. External Drive Configuration.
NC
XTAL2: 18
EXTERNAL
OSCILLATOR----lXTAL1: 19
SIGNAL
.------lVSS: 20
Hardware Description
Same as for the 80CSI, plus a third timer/counter:
TimerlEvent Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and I, it
can operate either as a timer or as an event counter, This
is selected by bit C/T2 in the Special Function Register
T2CON (Figure I), It has three operating modes :
"capture", "autoload" and "baud rate generator", which
are selected by bits in T2CON as shown in Table 2.
EXEN2 = 0, then when Timer 2 rolls over it does not only
set TF2 but also causes the Timer 2 register to be reloaded
with the 16 bit value in registers RCAP2L and RCAP2H,
which are preset by software. If EXEN2 = I, then Timer
2 still does the above, but with the added feature that a
I-to-O transition at external input T2EX will also trigger
the 16 bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 8.
Figure 7. Timer 2 in Capture Mode.
Table 2.Timer 2 Operating Modes.
RCLK+
TC:LK
0
0
1
X
..
CPIRLZ
TR2
.
()
I
1
I
0
1
X
X
MODE
16 bit auto-reload
16 bit capture
baud rate generator
(off)
: CONTROL
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON; If EXEN2 = 0, then
Timer 2 is a 16 bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt. If EXEN2 = I, then
Timer 2 still does the above, but with the added feature
that a I-to-O transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 and TH2, to
be captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit
EXF2 in T2CON to be set, and EXF2, like TF2, can
generate an interrupt.
EXEN2
Figure 8. Timer 2 in Auto-Reload Mode.
The capture mode is illustrated in Figure 7.
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON.If
II.S.S
EXEN2
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
(LSB)
(MSB)
TF2
EXF2
RCLK
TCLK
EXEN2
crf2
TR2
CPIRL2
The baud rate generator mode is selected by : RCLK = I and/or TCLK = I.
Name and Significance
Symbol
Position
TF2
T2CON.7
Timer 2 overflow flag set by a Timer 2 overflow and must be dearcd by software. TF2
will not be set when either RCLK = I OR TCLK = I.
EXF2
T2CON.6
Timer 2 external nag set when either a capture or reload is caused by a negative
transition on T2EX and EXEN2 = I. When Timer 2 interrupt is enabled. EXF2 = I will
cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by
soflware.
RCLK
T2CON.5
Receive clock nag. When set, causes the serial port to usc Timer2 overflow pulses for its
receive clock in modes I and J. RCLK :::: 0 causes Timer 1 overflow to he used for the
receive clock.
TCLK
T2CON.4
Transmit clock nag. When set, causes the serial port to usc Timer 2 overflow pulses for
its transmit clm:k in modes I and 3. TCLK::: 0 causes Timer I overilows to be used for
the transmit dock.
EXEN2
T2CON.3
Timer 2 external enable flag. When set allows capture or reload to occur as a resull of a
negative transition on T2EX if Timer 2 is not being used to clock the serial port.
EXEN2 ::: 0 causes Timer 2 to ignore events at T2EX.
TR2
T2CON.2
Start/stop control for Timer 2. A logic I starts the timer.
crT2
T2CON.I
Timer or counter select. (Timer 2) a = Internal timer (OSC!l2)
I ::: External event counter (falling edge triggered).
CP/RL2
T2CON.O
Capture/Reload tlag. When set, captures will occur on negative transitions at T2EX if
EXEN 2 = I. When cleared, auto reloads will occur either with Timer 2 overflows or
negative transition at T2EX when EXEN2 = I. When either RCLK = I or TCLK = I. this
bit is ignored and the timer is forced to auto-reload on Timer 2 ovcrllow.
Timer Functions
In fact. timer 0 & I can be connected by a software
instruction to implement a 32 bit timer function. Timer 0
(mode 3) or timer I (mode 0, I, 2) or a 32 bit timer
consisting of timer 0 + timer I can be employed in the
watchdog mode, in which case a CPU reset is generated
upon a TF I flag.
The internal pull-up resistances at ports 1-3 can be set to
a ten times increased value simply by software.
32 Bit Mode and Watching Mode
Figure 9.
Watchdogtimer
RESET
i:~~~ ~g8~g)1~~IT
32-BIT TIMER MODE
BIT7,WDT
32 bit timer [IOCON bit 6 (T32)
=1]
The 83C 154 has two supplementary modes. They are
accessed by bits WDT and T32 of register IOCON. Figure
10 showns how laCON must be programmed in order to
have access to these functions
MATRAMHS
Rev.F (14 Jan. 97)
II.5.9
B
TEMIC
80C154/83C154
Semiconductors
(MSB)
(LSB)
WDT
132
SERR
IZC
P3HZ
P2HZ
PIHZ
ALF
Symbol
Position
132
IOCON.6
-
If 132 ~ I and if ciro ~ 0, T I and TO are programmed as a 32 bit TIMER.
If T32 ~ I and if ciro ~ I, TI and TO arc programmed as a 32 bit COUNTER.
WDT
IOCON.7
-
If WDT ~ I and according to the mode selected by TMOD, an 8 bit or 32 bit
WATCHDOG is configured from TIMERS 0 and 1.
Name and Significance
32 Bit Mode
•
T32 = I enables access to this mode. As shown in
figure II, this 32 bit mode consists in cascading
TIMER 0 for the LSBs and TIMER I for the MSBs
Figure 10.32 Bit Timer/counter.
T32
= I starts the timer/counter and T32 =0 stops it.
It should be noted that as soon as T32 =O. TIMERs 0 and
I assume the configuration specified by register TMOD.
Moreover, if TRO
=I
or if TR I
TIMERs evolves. Consequently, in 32 bit mode, if the
TIMER/COUNTER muste be stopped (T32 = 0), TRO
and TR I must be set to O.
= !, the content of the
32 Bit Timer
•
Figure 12 illustrates the 32 bit TIMER mode.
Figure 11. 32 Bit Timer Configuration.
lose 11----11 121 ---~_T_IM_E_R_0___L_T_IM_E_R_1__'H
+
•
I-
In this mode, T32 = I and CfTO =0, the 32 bit timer
is incremented on each S3P I state of each machine
cycle. An overflow of TIMER 0 (TFO has not been set
to !) increments TIMER ! and the overflow of the
32 bit TIMER is signalled by setting TF! (SSP!) to 1.
11.5.10
•
TF1
I
The following formula should be used to calculate the
required frequency:
f =
OSC
12 x (6s536-(TO, Tl))
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
32 Bit Counter
Figure 13 illustrates the 32 bit COUNTER mode.
Figure 12. 32 Bit Counter Configuration.
I
f EXT
•
TIMER 0
TO
In this mode, T32 = 0 and CfTO = I. Before it can
make an increment, the 83C 154~ must detect two
transitions on its TO input. As shown in figure 14,
TIMER I
TF1
input TO is sampled on each S5P2 state of every
machine cycle or, in other words, every OSC -<- 12.
II
Figure 13. Counter Incrementation Condition.
-TO PIN
READING OF INPUT TO
Ci-1
t
t
Ci
S5P2 ......... S5P2
Ci+n
t
S5P2
r
COUNTER INCREMENTATION
S3P1
•
•
The counter will only evolve if a level I is detected
during state S5P2 of cycle Ci and if a level 0 is
detected during state S5P2 of cycle Ci + n.
Consequently, the minimal period of signal fEXT
admissible by the counter must be greater than or
equal to two machine cycles. The following formula
should be used to calculate the operating frequency.
f
Figure 14. The Different Watchdog Configurations.
TIMERO
Mode3
8 bits
TIMER1
MODE 0,1,2
13-16 bits
TIMERO,1
MODE 32bits 32 bits
fEXT
65536-(TO, T1)
=
fEXT < OSC
24
WDT
Watchdog Mode
•
WDT = I enables access to this mode. As shown in
figure 15, all the modes of TIMERS 0 and I, of which
the overflows act on TFI (TFI = I), activate the
WATCHDOG Mode.
MATRAMHS
Rev.F (14 Jan. 97)
RESET - - - - - - ,
II.S.11
TEMIC
80C154/83C154
•
•
Semiconductors
If clf = 0, the WATCHDOG is a TIMER that is
incremented every machine cycle, If CIT = I, the
WATCHDOG is a counter that is incremented by an
external signal of which the frequency cannot exceed
OSC+ 24.
The overflow of the TIMER/COUNTER is signalled
by raising flag TFI to 1. The reset of the 83CI54 is
executed during the next machine cycle and lasts for
the next 5 machine cycles. The results of this reset are
identical to those of a hardware reset. The internal
RAM is not affected and the special register assume
the values shown in Table 3.
Table 3. Content of the SFRS after a reset triggered
by the watchdog.
REGISTER
PC
ACC
B
PSW
SP
DPTR
PO·P3
IP
IE
TMOD
TCON
T2CON
THO
TLO
THI
TLI
TH2
TL2
RCAP2H
RCAP2L
SCON
SBUF
IOCON
PCON
11.5.12
•
External Counting in Power-down Mode
(PD =PCON.l =1)
•
CONTENT
OOOH
OOH
OOH
OOH
07H
OOOOH
OFFH
OXOOOOOOB
OXOOOOOOB
OOH
OOH
OOH
OOH
DOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
Indelerminale
OOH
OOOXOOOOB
As there are no precautions for protecting bit WDT
from spurious writing in the IOCON register, special
care must be taken when writing the program. In
particular, the user should use the IOCON register bit
handling instructions:
- SETB and CLR x
in preference to the byte handling instructions:
- MOV IOCON, # XXH, ORL IOCON, #XXH,
- ANL IOCON, #XXH
•
In the power-down mode, the oscillator is turned off
and the 83C154's activity is frozen. However, if an
external clock is connected to one of the two inputs,
TlITO, TIMER/COUNTERS 0 and I can continue to
operate.
In this case, counting becomes asychronous and the
maximum, admissible frequency of the signal is
OSC: 24.
The overflow of either counter TFO or TFI causes an
interrupt to be serviced or forces a reset if the counter
is in the WATCHDOG MODE (T32 = ICON.7 = I).
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
Semiconductors
80C154/83C154
83C154 with Secret ROM
83C154 with Secret TAG
TEMIC offers 83C 154 with the encrypted secret ROM
option to secure the ROM code contained in the R3C154
microcontrollers.
TEMIC offers special 64-bit identifier called "SECRET
TAG" on the microcontroller chip.
The clear reading of the program contained in the ROM
is made impossible due to an encryption through several
random keys implemented during the manufacturing
process.
The keys used to do such encryption are selected
randomwise and are definitely different from one
microcontroller to another.
This encryption is activated during the following phases:
- Every time a byte is addressed during a verify of the
ROM content, a byte of the encryption array is
selected.
- MOVC instructions executed from external program
memory are disabled when fetching code bytes from
internal memory.
- EA is sampled and latched on reset, thus all state
modification are disabled.
The Secret Tag option is available on both ROMless and
masked microcontrollers.
The Secret Tag feature allows serialization of each
microcontroller for identification of a specific
equipment. A unique number per device is implemented
in the chip during manufacturing process. The serial
number is a 64-bit binary value which is contained and
addressable in the Special Function Registers (SFR) area.
This Secret Tag option can be read-out by a software
routine and thus enables the user to do an individual
identity check per device. This routine is implemented
inside the microcontroller ROM memory in case of
masked version which can be kept secret (and then the
value of the Secret Tag also) by using a ROM Encryption.
For further information, please refer to the application
note (ANM03I) available upon request.
For further information please refer to the application
note (ANM053) available upon request.
MATRAMHS
Rev.F (14 Jan. 97)
11.5.13
TEMIC
80C154/83C154
Semiconductors
Electrical Characteristics
Absolute Maximum Ratings*
* Notice
Ambiant Temperature Under Bias:
C = commercial
Stresses at or above those listed under" Absolute Maximum RatinKS"
/1/(/.\' couse permanent damage to the device. This is II stress rating 011(1,.'
and functional operation (4 the device at these or (lny other conditions
above those indicated in the operatimwl sections (~lth;s specUication is
not implied. Exposure to absolute maximum rating condiliolls may affect
device reliability.
O°C to +70"C
I :::: industrial ..
-40°C to +85"C
Storage Temperature
.. -65"C to + 150'C
Voltage on VCC to VSS .
. . -0.5 V to + 7 V
....... -0.5 V to VCC + 0.5 V
Voltage on Any Pin to VSS
Power Dissipation
I W*'"
This value is hased on the maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA = ooe to 70 oe; Vee = 0 V; Vee = 5 V ± 10 % ; F = 0 to 36 MHz
TA = -40 o e + 85°e; Vee = 0 V; Vee = 5 V ± 10 % ; F = 0 to 36 MHz
SYMBOL
PARAMETER
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port I, 2 and 3)
VOLI
VOH
MIN
MAX
UNIl'
-0.5
O.2Vce-O.1
V
0.2 Vee + 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
0.3
0.45
1.0
V
V
V
IOL
IOL
0.3
0.45
1.0
V
V
V
IOL
IOL
IOL
Vee-0.3
V
[OH~-IOIlA
Vee - 0.7
V
IOH
Vee - 1.5
V
IOH~-60flA
Vee - 0.3
V
IOH
~-200
flA
Vee - 0.7
V
IOH
~-3.2
rnA
Vee - 1.5
V
IOH~-7.0rnA
Output Low Voltage (Port 0, ALE, PSEN)
Output High Voltage Port 1,2 and 3
TEST CONDITIONS
IOL~
~
~
~
~
~
1(J0IlA
1.6 rnA (note 2)
3.5 rnA
200 ~A
3.2 rnA (note 2)
7.0 rnA
~~
30 flA
VCC~5
VOHI
Output High Voltage (Port 0, ALE, PSEN)
VCC~5
ilL
Logical 0 Input Current (Ports 1,2 and 3)
-50
flA
Yin
~
V± 10 %
V± 10 %
0.45 V
III
Input leakage Current
+/-10
flA
0.45 < Yin < Vce
ITL
Logical I to 0 Transition Current
(Ports I, 2 and 3)
- 650
~A
Yin
~
2.0 V
IPD
Power Down Current
Vee
~
2.0 V to 5.5 V (note 1)
RRST
RST Pulldown Resistor
CIO
Capacitance of I/O Buffer
ICC
Power Supply Current
Freg ~ I MHz lee op
Icc idle
Freg ~ 6 MHz Icc op
Icc idle
Freg;' 12 MHz kc op ~ 1.3 Frcg (MHz) + 4.5 rnA
Icc idle ~ 0.36 Prcq (MHz) + 2.7 rnA
11.5.14
50
50
~A
200
KOhrn
10
pF
fe
~
I MHz, Ta
Vee~5.5
1.8
I
10
4
~
25'C
V
rnA
rnA
rnA
rnA
MATRAMHS
Rcv.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias:
Stresses (tl Of ahove those fisted ullder " Abso/llfe Maximum RalinRs"
lIIay cause perm({nent dlllllllge /0 the device. This is {/ stress ratin;: only
wullunctiOlw{ opemtiol7 (~r the device (/1 these or lIny other conditions
above thost! indicated ill rhe ol'uatiol1al se£'fions of'this S[u!cUfcatiol1 is
l10t implied. Exposure to absolute maximum mting cOlldiriol1.\' may (!ffec/
device relia/JWly.
A = Automotive
Storage Temperature
-40°C to +125°C
.... -65"e to + 150'e
Voltage on vee to VSS .
. ........ -0.5 V to + 7 V
Voltage on Any Pin to VSS
. . -0.5 V to vee + 0.5 V
Power Dissipation
IW
This value is based on the maximum allowable die temperature and
the thermal resistance of the pm:kage
DC Parameters
TA
;2.,
=-40°C + 12SoC ; V ss =0 V ; Vee =S V ± 10 % ; F =0 to 36 MHz
....
;;.;
.• <
PkR.AMETEit
MIN
...
.:·07
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIHI
Input High Voltage (for XTAL and RST)
VOL
Output Low Voltage (Port 1,2 and 3)
VOLI
VOH
TEST CONDITIONS
UNIT
-0.5
0.2 Vee-D.I
V
0.2 Vee + 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
0.3
0.45
1.0
V
D.3
0.45
1.0
V
Output Low Voltage (Port 0, ALE, PSEN)
Output High Voltage Port I, 2 and 3
I
MAX
IOL~
IOL
IOL
~
~
IDOIlA
1.6 mA (note 2)
3.5 mA
IOL~200
IOL
~
IlA
3.2 mA (note 2)
IOL~7.0mA
Vee - 0.3
V
IOH
~-10
IlA
Vee - 0.7
V
IOH
~-30
IlA
Vee - 1.5
V
IOH
~-60
IlA
Vee~5V±IO%
VOHI
Output High Voltage (Port 0, ALE, PSEN)
Vee - n.3
V
IOH
Vee - 0.7
V
IOH~-3.2mA
Vee - 1.5
V
IOH~-7.0mA
~-
200 IlA
Vee~5V±IO(!C
ilL
Logical 0 Input Current (Ports 1,2 and 3)
- 50
Il A
Yin
---
ILl
Input leakage Current
ITL
Logical I to 0 Transition Current
(Ports I. 2 and 3)
IPD
Power Down Current
RRST
RST Pulldown Resistor
eIO
Capacitance or 110 BulTer
ICC
Power Supply Current
Freg ~ I MHz Icc op
Icc idle
Freg ~ 6 MHz Icc op
Icc idle
Freg" 12 MHz Icc op ~ 1.3 Freq (MHz) + 4.5 mA
Icc idle ~ 0.36 Freq (MHz) + 2.7 mA
MATRAMHS
Rev.F (14 Jan. 97)
50
~
0.45 V
±IO
Il A
0.45 < Yin < Vee
-750
Il A
Yin
~
2.0 V
75
Il A
Vee
~
2.0 V to 5.5 V (note I)
200
KOhm
10
pF
1.8
I
10
4
mA
mA
mA
mA
fe
~
Vee
I MHz. Ta ~ 25°C
~
5.5 V
II.S.IS
TEMIC
80C154/83C154
Semiconductors
* Notice
Absolute Maximum Ratings*
Stresses at or ahove those listed under" Absolute Maximum Ratinfts"
may cause permanent damage to the device. This is (/ stress ratil1R only
andfuncti01w/ operation (~(the device (It these or allY other conditions
above those indicated in the operational sections qtthis spec{fication is
not implied. Exposure to absolute maximum raring conditions may affect
device reliability.
Ambient Temperature Under Bias:
-55"C to + 125"C
M = Military.
Storage Temperature
.. -65"C to + 150'C
Voltage on VCC to VSS .
. ... -0.5 V to + 7 V
.... -0.5 V to VCC + 0.5 V
Voltage on Any Pin to VSS
Power Dissipation
IW
** This value is based on the
maximum allowable die temperature and
the thermal resistance of the package
DC Parameters
TA =-55°C + 125°C; Vss = 0 V; Vee
SYMBOL
....•...
.....
....•.
=5 V ± 10 % ; F =0 to 36 MHz
.•.•.. PA~ME'I'Elt
.•••.••• • . J
VIL
Input Low Voltage
VIH
Input High Voltage (Except XTAL and RST)
VIHI
Inpu! High Voltage (for XTAL and RST)
MIN
I·····.·M~.
-0.5
0.2 Vee -0.1
V
0.2 Vee + 1.4
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
I.···
r.~~l'l'
l'Jl:S'I' COl\fQITIOl\fB
VOL
Output Low Voltage (Port 1,2 and 3)
0.45
V
IOL = 1.6 rnA (note 2)
VOLI
Output Low Voltage (P0I1 0, ALE, PSEN)
0.45
V
10L = 3.2 rnA (note 2)
VOH
Output High Voltage (Port 1,2,3)
2.4
V
10H =-60 ~A
Vee=5V± 10%
0.75 Vee
V
10H =-25
0.9 Vee
V
10H
2.4
V
IOH = -400 JJA
Vee=5V±10%
0.75 Vee
V
IOH=-150JJA
0.9 Vee
V
IOH=-40~A
VOHI
Output High Voltage
(Port 0 in External Bus Mode, ALE, PEN)
IlL
Logical 0 Input Current (Ports I, 2 and 3)
III
Input leakage Current
ITL
Logical I to 0 Transition Current
(Ports 1,2 and 3)
IPD
Power Down Current
RRST
RST Pulldown Resistor
CIO
Capacitance of 1/0 Buffer
ICC
Power Supply Current
Freg = I MHz lee op
lee idle
Freg = 6 MHz Icc op
lee idle
Freq<: 12 MHz Icc op = 1.3 Freq (MHz) + 4.5 rnA
lee idle = 0.36 Freq (MHz) + 2.7 rnA
11,5,16
50
~A
=-IO~A
-75
!lA
Yin = 0.45 V
±IO
!lA
0.45 < Yin < Vee
-750
JJA
Yin = 2.0 V
75
!lA
Vee = 2.0 V to 5.5 V (note I)
200
KOh
rn
10
pF
1.8
I
10
4
rnA
mA
rnA
rnA
fc = I MHz, Ta = 25'C
Vee=5.5V
MATRAMHS
Rev,F (14 Jan, 97)
TEMIC
80C154/83C154
Semiconductors
Absolute Maximum Ratings*
* Notice
Ambient Temperature Under Bias:
Stresses (//
I ::::: Industrial ..
.. -65°C
Voltage
vce to VSS .
00
to
U/JOI'('
+ 15()()C
-O.S V to
d(//JI(/ge !o IIie tier/ce. This is ({ stress ruting only
cilidjilllclio/iili oj/cmlio/l 0/ rhe c/cl'ice
-411'C to X5'C
Storage Temperature
({/Jore those listed ulltier " A!Jso{l/le Maximum RUlings"
Of
III({Y C{I/(se 1)('1"11/(111011
II"C to +70"C
C::::: Commercial.
1101
lhose illd;c({!cti ill Ihl'
(If
these or (lilY olher condilions
ofJcmlioll(// sec/iulls (~{'!his
spccijj('ulim/
is
il/fjJlicd. I ..".\"j}()SII/"(' to (//J.I'o/we III11Xillllfl1l mfillg (,(Jllt/iliolls moy (!!I(-'C{
device rdi(//)i!ily.
+7V
-U.S V to vce + U.S V
Voltage on Any Pill to VSS
IW
Power Dissipation
This value is hascd on the maximum allowahlc die tCTlIpcratun.: and
the thermal resistance
or the package
II
DC Parameters
TA = ooe to 70°C; Vee = 2.7 V to 5.5 V ; Vss
TA =-40 o e to 85°C; Vee = 2.7 V to 5.5 V
SYMBOL
= 0 V ; F = 0 to
PARAMETER
VIL
Input Low Voltage
VIH
Inpul High Vohage (Except XTAL and RST)
16 MHz
MIN
MAX
UNIT
-0.5
0.2 vce - 0.1
V
0.2 vee
+ 1.4 V
vee + 0.5
V
TEST CONDITIONS
VIHl
Input High Voltage to XTALI
0.7 vee
vee + 0.5
V
VIH2
Input High Voltage to RST for Reset
0.7 vee
vee +0.5
V
VPD
Power Down Voltage to Vcc in PD Mode
2.0
6.0
V
VOL
Output Low Voltage (Pnrts 1,2,3)
0.45
V
IOL = 0.8 mA (note 2)
VOLI
Output Low Voltage Port O. ALE, PSEN
V
IOL = 1.6 mA (note 2)
VOH
Output High Voltage Ports I, 2, 3
0.9 Vee
V
IOH=-IO~A
VOHI
Output High Voltage (Port 0 in External Bus
Mode). ALE. PSEN
0.9 Vee
V
IOH = -40
-50
~A
Yin = 0.45 V
0.45
~A
IlL
Logical 0 Input Current Ports 1, 2. 3
ILl
Input Leakage Current
±IO
~A
0.45 < Yin < vee
ITL
Logical I to 0 Transition Current
(Ports 1,2,3)
-650
~A
Yin = 2.0 V
vee = 2 V to 5.5 V (note I)
IPD
Power Down Current
RRST
50
RST Pulldown Resistor
Capacitance of 110 Buffer
CIO
50
~A
200
Hl
10
pF
fe = I MHz, TA = 25°e
Maximum Icc (rnA)
IF'>
••·•· · · • •· •· ·.•·. . .
FREQUENeY/Vee
..
OPEltAT1NG(NO'tEl)
'
••
.
. ..
IDLE(NO:fEi)
..
2.7 V
3V
3.3 V
5.5 V
2.7 V
3V
3.3 V
lMHz
0.8 mA
I mA
1.1 mA
1.8mA
400~A
500~A
600 ~A
I mA
6 MHz
4mA
SmA
6mA
IOmA
1.5mA
J.7 rnA
2mA
4mA
12MHz
8mA
10mA
12mA
2.5 rnA
3 rnA
3.5mA
16MHz
lOrnA
12 rnA
14 rnA
3 rnA
3.8 rnA
4.5mA
Freq> 12 MHz (Vee = 5.5 V)
MATRAMHS
Rev.F (14 Jan, 97)
5.5 V
Icc (rnA) = 1.3 x Freq (MHz) + 4.5
Icc Idle (rnA) = 0.36 x Froq (MHz) + 2.7
11.5,17
TEMIC
80C154/83C154
Semiconductors
Notel: ICC is measured with all output pins
disconnected;
XTALI
driven
with
TCLCH,
TCHCL = 5 ns, VIL = VSS + .5 V, VIH = VCC -.5 V ;
XTAL2 N.C. ; EA = RST = Port 0 = VCe. ICC would be
slighty higher if a crystal oscillator used.
Figure 15. ICC Test Condition, Idle Mode.
All other pins are disconnected.
Idle ICC is measured with all otput pins disconnected;
XTALI driven with TCLCH, TCHCL = 5 ns, VIL =
VSS + 5 V, VIH = VCC -.5 V ; XTAL2 N.C ; Port
o =VCC; EA= RST= VSS.
Power Down ICC is measured with all output pins
disconnected; EA = PORT 0 = VCC ; XTAL2 N.e. ;
RST=VSS.
Note 2 : Capacitance loading on Ports 0 and 2 may cause
spurious noise pulses to be superimposed on the VOLS of
ALE and Ports I and 3. The noise is due to external bus
capacitance discharging into the Port 0 and Port 2 pins
when these pins make 1 to 0 transitions during bus
operations. In the worst cases (capacitive loading 100
pF), the noise pulse on the ALE line may exceed 0.45 V
may exceed 0,45 V with maxi VOL peak 0.6 V A Schmitt
Trigger use is not necessary.
RST
(NC)
CLOCK
SIGNAL
EA
XTAL2
XTAL1
VSS
Figure 16. ICC Test Condition, Active Mode.
All other pins are disconnected.
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 17. ICC Test Condition, Power Down Mode.
All other pins are disconnected.
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 18. Clock Signal Waveform for ICC Tests in Active and Idle Modes. TCLCH = TCHCL = 5 ns.
TCHCL
ioot------TCLCL.-------.!
II.5.18
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Explanation of the AC Symbol
Example:
Each timing symbol has 5 characters. The first character
is always a "Tn (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
TAVLL = Time for Address Valid to ALE low.
TLLPL =Time for ALE low to PSEN low.
Q : Output data.
A: Address.
C: Clock.
D : Input data.
H : Logic level HIGH
[ : Instruction (program memory contents).
L : Logic level LOW, or ALE.
P: PSEN.
R : READ signal.
T:Time.
V: Valid.
W : WRITE signal.
X : No longer a valid logic level.
Z: Float.
E
AC Parameters
TA =0 to + 70°C; Vss =0 V ; Vcc = 5 V ± 10 % ; F = 0 to 36 MHz
TA=-55° + 125°C; Vss = 0 V; 2.7 V < Vce < 5.5 V; F= 0 to 16 MHz
TA = _55 0 + 125°C; Vss = 0 V ; Vec = 5 V ± 10 % ; F = 0 to 36 MHz
(Load Capacitance for PORT n, ALE and PSEN
= 100 pF ; Load Capacitance for all other outputs =80 pF)
External Program Memory Characteristics
'.
'"
.....
16MHt
SYMBOL
PARAMETER
20 MHz
25 MHz
30 MHz
36 MHz
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
TLHLL
ALE Pulse Width
110
90
70
60
TAVLL
Address valid to ALE
40
30
20
15
10
TLLAX
Address Hold After ALE
35
35
35
35
35
TLLlV
ALE to valid instr in
TLLPL
ALE to PSEN
45
TPLPH
PSEN pulse Width
165
TPLIV
PSEN to valid instr in
TPXIX
Input instr Hold After PSEN
TPXIZ
Input instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid instf in
TPLAZ
PSEN low to Address Float
185
170
40
0
0
35
40
50
75
65
0
0
45
50
55
85
80
20
80
100
110
100
25
30
130
125
130
50
50
0
30
35
25
30
230
210
170
130
90
10
10
8
(,
5
External Program Memory Read Cycle
ALE
ADDRESSAB-A15
PORT 2 _ _ _ _/
MATRAMHS
Rev.F (14 Jan. 97)
II.5.19
TEMIC
80C154/83C154
Semiconductors
External Data Memory Characteristics
.
.......... .....
....
. SYMBOL
•••••••
·.·• · •.•·•••.•.·PA
........
......... 16MIJi
...
..•..........
n
20 MHz.
MIN MAX MIN MAX
;30Mflz ..... .• j~l\l!lz.
MAX MIN MAx MIN MAX
25.MHZ
MINi
TRLRH
RD pulse Width
340
270
210
180
120
TWLWH
WR pulse Width
340
270
210
180
120
TLLAX
Address Hold After ALE
85
85
70
55
TRLDV
RD to Valid in
TRHDX
Data hold after RD
TRHDZ
Data float after RD
90
90
80
70
50
TLLDV
ALE (0 Valid Data In
435
370
350
235
170
TAVDV
Address to Valid Data IN
TLLWL
ALE
(0
240
a
0
150
250
400
135
170
0
0
300
120
110
135
0
480
WR or RD
35
175
210
260
130
90
190
115
70
TAVWL
Address to WR or RD
180
180
140
115
TQVWX
Data valid to WR transition
35
35
30
20
15
TQVWH
Data Setup to WR transition
380
325
250
215
170
TWHQX
Data Hold after WR
40
TRLAZ
RD low to Address Float
TWHLH
RD or WR high to ALE high
35
30
0
35
0
90
35
75
20
15
0
60
25
0
45
100
20
0
40
20
40
External Data Memory Write Cycle
I
TWHLH
~
"-
ALE
_TLLWL---.!.
PORTO
PORT 2
>---<
ADDRESS
ORSFR·P2
.TLLAX~
AO-A?
')(
TWLWH
"h-I
1+--- TAVWL
I><
I
TOVWX
/
TOVWH
~TWHOX.I
t
DATA OUT
ADDRESSA8-A15 OR SFR·P2
External Data Memory Read Cycle
4_------- TLLDV ----------'J..~I
.,_------.... 1-..
TWHLH :.
ALE
PSEN
RD
.yr::::---
---------------r----------~ 14~------+TRLRH--------__
TRHDX
PORTO
DATA IN
TRLAZ
PORT 21
II.5.20
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Serial Port Timing - Shift Register Mode
16MHz
PARAMETER
SYMBOL
MIN
20 MHz
25 MHz
MAX MIN MAX MIN
30 MHz
MAX MIN
36 MHz
MAX MIN MAX
TXLXL
Serial Port CloL'k Cycle Time
7S0
600
4RO
40()
330
TQVXH
Output Data Setup to Clock Rising
563
480
380
}()(j
220
Edge
TXHQX
Output Data Hold after Clock Rising
Edge
63
90
65
50
45
TXHDX
Inrut Data Hold after Clock Rising
Edge
0
()
0
0
0
TXHDV
Clock Rising Edge to Input Data Valid
}OO
}50
450
563
250
Shift Register Timing Waveforms
INSTRUCTION
o
2
3
4
5
6
7
8
CLOCK
OUTPUT DATA
~O
WRITE
SBUF
TXHDV!--I
INPUT DATA""---""
...
CLEAR RI
MATRAMHS
Rev.F (14 Jan. 97)
1
...
SETIN
TXHDX
...
SET IN
11.5.21
II
TEMIC
80C154/83C154
Semiconductors
External Clock Drive Characteristics (XTALl)
Ip,<§y-,n" •.. . . .•. ••.•.•.•.•.
PA.IlAME1'#.··<·.[···········.········'·lVl~~ii
.· ·. ·f·······•··•.·.•.•·.l\tJAX·> •••••••·•· ·•·• · .· ·......••.••...•.•.... UNIT
FCLCL
Oscillator Frequency
TCLCL
Oscillator period
TCHCX
High Time
ns
TCLCX
Low Time
ns
TCLCH
Rise Time
TCHCL
Fall Time
•.. ••'•. ,
MHz
36
27.8
ns
5
ns
ns
External Clock Drive Waveforms
TCHCL
~------------TCLCL--------------~
=x:
AC Testing Input/Output Waveforms
INPUT/OUTPUT
Vcc -O,5V
0,45 V
0,2 Vcc + 0,9
)C
_..;0;;.;,2;;..V.;.:c;;;;c;..-.....;.;0,:.;.1_ _ _ __
AC inputs during testing are driven at Vcc - 0.5 for a logic "I" and 0.45 V for a logic "0". Timing measurements are
made at VIH min for a logic" I" and VIL max for a logic "0".
Float Waveforms
FLOAT
. - - - - - - - - FLOAT - - - - - . . - I
VLOAD
VLOAD+ 0,1 V
VLOAD - 0,1 V
For timing purposes as port pin is no longer floating when a 100 m V change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOHIVOL level occurs. Iol/IoH ~ ± 20 rnA.
II.5.22
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
80C154/83C154
Semiconductors
Clock Waveforms
STATE 4
INTERNAL
CLOCK
P1
I
I P2
STATE 51
STATE 6
P1 I P2
P1
I P2
I
STATE 1
P1
I
I P2
STATE 2
STATE 3
STATE 4
1
P1
I P21 P1
I P2
I
P1 I P2
STATE 5
P1 I P21
XTAL2
"
ALE
EXTERNAL PROGRAM MEMORY FETCH
I
L-
I
"'" THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
.-------,
PSEN
L -_ _~DATA
PO
SAMPLED
I
FLOAT ---.I
I_
P2(EXT)
READ CYCLE
_ _ _ _---'IINDICATES ADDRESS TRANSITIONSL..I_ _ _ _ _ _ _ _ _ _---'
RD
DOH IS EMITTED
DURING THIS PERIOD
PO
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
_ _ _ _~-D-P-L-O-R-~-'I~I_.-----------~~
I
OUT
FLOAT SAMPLE"=D:-------....J1
U.I..
r
~
..
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
WR
I PCLOUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
L -_ _ _ _ _ _ _ _ _ _--'
DP~S~ ~ I..
PO
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
P2
"i'\i.1~CLOUT:h~OGRAM
I MEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT SRC
_ _ _ _ _ _ _ _ _ _O_L_D_D_A_TA-II NEW DATA
M
MOVDESTpo
MOV DEST PORT-(P-1-P-2-.-P3-)-..J
(INCLUDES INTO. INH TO. T1)
SERIAL PORT SHIFT CLOCK
TXD
(MODE 0)
Ffl
APO PINS SAMPLED
I
PO PINS SAMPLED
~
FfL
P1L...-P-2.-P-3-P-IN-S-SA-M-PL-E-D----------------'I
--------~~
RXD SAMPLED
P1. P2 P3
PINS SAMPLED
ill
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though eTA =25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns. Propagation delays are
incorporated in the AC specifications.
MATRAMHS
Rev.F (14 Jan. 97)
11.5.23
TEMIC
80C154/83C154
Semiconductors
Ordering Information
S
T
83Cl54C
xxx
-36
T
Temperature Range
blank : Commercial
I
: Industrial
A
: Automotive
M
: Military
Part Number
83CI54 Rom 16 K x 8
80CI54 External ROM
83C 154C Secret ROM version
83CI54T Secret Tag version
T
-12
-16
-20
-25
-30
-36
-Ll6
Package Type
P: POlL 40
S: PLCC 44
F I: PQFP 44 (Foot print 13.9 mm)
F2: PQFP 44 (Foot print 12.3 mm)
V: VQFP (1.4 mm)
T: TQFP (1.0 mm)
0: CDlL40
Q: CQFP44
R: LCC 44
Customer Rom Code
11.5.24
D
: 12 MHz version
: 16 MHz version
: 20 MHz version
: 25 MHz version
: 30 MHz version
: 36 MHz version
: Low Power
(Vee: 2.7-5.5 V
Freq: 0-16 MHz)
R : Tape and Reel
D: Dry Pack
Flow
/883: MIL 883 Compliant
P883: MIL 883 Compliant
with PIND test.
MATRAMHS
Rev.F (14 Jan. 97)
TEMIC
83C154D
Semiconductors
CMOS 0 to 30 MHz Single Chip 8-bit Microcontroller
Description
In addition, the 83C 154D has two software selectable
The TEMIC 83C 154D retains all the features of the
TEMIC 80C52 with extended ROM capacity (32 K
bytes), 256 bytes of RAM, 32 I/O lines, a 6-source 2-level
interrupts, a full duplex serial port, an on-chip oscillator
and clock circuits, three 16 bit timers with extra features:
32 bit timer and watch dog functions. Timer 0 and I can
be configured by program to implement a 32 bit timer.
The watchdog function can be activated either with
timer 0, or timer I or both together (32 bit timer).
modes of reduced activity for further reduction of power
consumption. In the Idle Mode, the CPU is frozen while
the RAM is saved, anl the timers, the serial port, and the
interrupt system continue to function. In the Power Down
Mode, the RAM is saved and the timers, serial port and
interrupts continue to function when driven by external
clocks. In addition as for the TEMIC SOC51 /C52, the stop
clock mode is also available.
•
•
•
•
• 83CI54D-30: 0 to 30 MHz
(commercial and industrial only)
• 83CI54D-Ll6: 0 to 16 MHz with 2,7 V < Vee < 5,5 V
(commercial only)
83CI54D-12: 0 to
83CI54D-16: 0 to
83CI54D-20: 0 to
83CI54D-25: 0 to
12 MHz
16 MHz
20 MHz
25 MHz
Features
•
•
•
•
•
Power Control Mode
256 bytes RAM
32 K bytes of ROM
32 programmable I/O lines (programmable impedance)
Three 16 bit timer/counters (including watch dog and 32 bit
timer)
• 64 K program memory space
• Fully static design
0.8 ~ CMOS process
Boolean processor
6 interrupt sources
Programmable serial port
• 64 K data memory space
• Temperature range: commercial, industrial, automotive,
military
•
•
•
•
Optional
• Secret ROM: Encryption
• Secret TAG: Identification number
MATRAMHS
Rev. D (14 Jan. 97)
II.6.1
2
TEMIC
83C154D
Semiconductors
Interface
Figure 1. Block Diagram
P20 P27
vee
r
1
vs?,
7
I
I
I
I
I
I
I~_I
I
I
I
I
I
I
I
I
I
I
I
I
PSEN
ALE
EA
RST
IL-------L=__
:~
e~:r'-
11.6.2
P30-P37
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
83C154D
Semiconductors
Figure 2. Pin Configuration
40
vee
T2EX/U
2
39
PO.O/AO
P1.2
3
38
PO.1/A 1
P1.3
4
37
PO.2/A2
P1A
5
36
PO.3/A3
T2/P1.0
INDEX
CORNER
PO.4/A4
PO.5/A5
35
POA/A4
P16
34
PO.5/A5
P1.7
33
PO.6/A6
PO.7/A?
32
PO.7/A 7
EA
P1.5
6
RST
9
P3.0/RXD
10
P3.1(fXD
11
P3.2/INTO
12
P3.3/INT1
13
Q
~
lI"l
U
«';
00
PO.6/A6
31
EA
30
ALE
29
PSEN
28
P2.7/A15
NC
ALE
PSEN
P3A(fO
14
27
P2.6/A14
P2.7/A14
P35(f1
15
26
P2.5/A13
P2.6/A13
P3.6/WR
16
25
P2A/A12
P2.5/A12
P37/RD
17
24
P2.3/A11
XTAL2
18
23
P22/A10
XTAL1
19
22
P21/A9
VSS
20
21
P2.0/A8
~ ~ ~ ~
~ ~
DIL
LCC
x
w
cL cL
P'5
P'6
cL
~
t ~
rf cL
()
z
0
0
>
0:
0
""
8
Q;;,0
0-
;;:
OJ
~g
""
42 41 40 39 38 37 36 35
•
Po4 JA4
Pos/AS
P17
P06/A6
RST
P07 /A ?
EA
RxD/P30
83Cl54D
NC
NC
TxD/P31
ALE
INTO/P32
PSEN
lNT1/P33
P27 /A15
TO/P34
P26!A14
T1/P35
P2s /A13
rf'
,
rf'
I~ l§l
:::
fO
x
~
X
m
m
>
()
z
'1
O-N
dO
~
0
N
~ O-N
~ O-N
~
.f O-N
Flat Pack
Diagrams are for reference only_ Package sizes are not to scale
MATRAMHS
Rev. D (14 Jan. 97)
11.6.3
II
TEMIC
83C154D
Semiconductors
Pin Description
vss
Port 2
Circuit Ground Potential.
Port 2 is an 8 bit bi-directional I/O port with internal
pull ups. Port 2 pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 2 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the internal pull ups. Port 2 emits the
high-order address byte during fetches from external
Program Memory and during accesses to external Data
Memory that use 16 bit addresses (MOVX @DPTR). In
this application, it uses strong internal pull ups when
emitting I's. During accesses to external Data Memory
that use 8 bit addresses (MOVX @Ri). Port 2 emits the
contents of the P2 Special Function Register.
It also receives the high-order address bits and control
signals during program verification in the 83C 154. Port
2 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pullups.
vee
Supply voltage during normal, Idle, and Power Down
operation.
PortO
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0
pins that have I's written to them tloat, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during accesses to external Program and Data
Memory. In this application it uses strong internal pullups
when emitting I's. Port 0 also outputs the code bytes
during program verification in the 83C154D. External
pull ups are required during program verification. Port 0
can sink eight LS TTL inputs.
Port 1
Port I is an 8 bit bi-directional I/O port with internal
pullups. Port I pins that have I's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port I pins that are externally
being pulled low will source current (IlL, on the data
sheet) because of the internal pullups.
Port 3
Port 3 is an 8 bit bi-directional I/O port with internal
pullups. Port 3 pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 3 pins that are externally
being pulled low will source current (ILL, on the data
sheet) because of the pullups. It also serves the functions
of various special features of the TEMIC 51 Family, as
listed below.
Port Pin
Port I also receives the low-order address byte during
program verification. In the 83C154D, Port I can sink or
source three LS TTL inputs. It can drive CMOS inputs
without external pullups.
P3.0
P3.1
P3.2
P3.3
P3.4
P3.S
P3.6
P3.7
2 inputs of PORT I are also used for timer/counter 2 :
PI.O [T2] : External clock input for timer/counter 2. Pl.I
lT2EX] : A trigger input for timer/counter 2, to be
reloaded or captured causing the timer/counter 2
interrupt.
Alternate Function
RXD (serial input port)
TXD (serial output port)
INTO (external interrupt 0)
INTI (external interrupt I)
TD (Timer 0 external input)
TI (Timer t external input)
WR (external Data Memory write strobe)
RD (external Data Memory read strobe)
Port 3 can sink or source three LS TTL inputs. It can drive
CMOS inputs without external pull ups.
RST
A high level on this for two machine cycles while the
oscillator is running resets the device. An internal
pull-down resistor permits Power-On reset using only a
capacitor connected to vce. As soon as the reset is
applied (Vin), PORT I, 2 and 3 are tied to I. This
operation is achieved asynchronously even if the
oscillator is not start up.
Il.6.4
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
83C154D
Semiconductors
ALE
Address Latch Enable output for latching the low byte of
the address during accesses to external memory. ALE is
activated as though for this purpose at a constant rate of
1/6 the oscillator frequency except during an external
data memory access at which time on ALE pulse is
skipped. ALE can sink or source 8 LS TTL inputs. It can
drive CMOS inputs without an external pullup.
Program Store Enable output is the read strobe to external
Program Memory. PSEN is activated twice each machine
cycle during fetches from external Program Memory.
(However, when executing out of external Program
Memory, two activations of PSEN are skipped during
each access to external Data Memory). PSEN is not
activated during fetches from internal Program Memory.
PSEN can sink/source 8 LS TTL inputs. It can drive
CMOS inputs without an external pull up.
When EA is held high, the CPU executes out of internal
Program Memory (unless the Program Counter exceeds
7 FFFH). When EA is held low, the CPU executes only out
of external Program Memory. EA must not be floated.
XTALl
Input to the inverting amplifier that forms the oscillator.
Receives the external oscillator signal when an external
oscillator is used.
XTAL2
Output of the inverting amplifier that forms the oscillator.
This pin should be floated when an external oscillator is
used.
Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration.
As illustrated, Power Down operation stops the oscillator.
The interrupt, serial port, and timer blocks continue to
function only with external clock (INTO, INTI, TO, TI).
Idle Mode operation allows the interrupt, serial port, and
timer blocks to continue to function with internal or
external clocks, while the clock to CPU is gated off. The
special modes are activated by software via the Special
Function Register, PCON. Its hardware address is 87H.
PCON is not bit addressable.
Figure 3. Idle and Power Down Hardware.
MATRAMHS
Rev. D (14 Jan. 97)
II.6.S
TEMIC
83C154D
Semiconductors
PCON: Power Control Register
(MSB)
ISMOD I HPD
(LSB)
I
RPD I
I GFI
I GFO
I PD
I IDL
Symbol
Position
Name and Function
SMOD
PCON.7
Double Baud rate bil. When set to
a I, the baud rate is doubled when
the serial port is being used in
HPD
PCON.6
RPD
PCON.5
GFI
GFO
PD
PCONA
PCON.3
PCON.2
PCON.I
IDL
PCON.O
I
either modes I, 2 or 3.
Hard power Down bit. Setting this
bit allows CPU to enter in Power
Down state on an external event
(I to 0 transition) on bit TI
(p. 3.5) the CPU quit the Hard
Power Down mode when hit TI
(p. 3.5) goes high or when reset is
activated.
Recover from Idle or Power Down
bit. When 0 RPD has no effecl.
When I, RPD permits to exit from
idle or Power Down with any non
enabled interrupt source (except
timer 2). In this case the program
start at the next address. When
interrupt is enabled, the
appropriate interrupt routine is
serviced.
(Reserved)
General-purpose '/lag hit.
General-purpose flag hit.
Power Down bit. Setting this bit
activates power down operation.
Idle mode bit. Setting this bit
activate.s power down operation.
If l's are written to PD and IDL at the same time. PD
takes, precedence. The reset value of PCON is
(OOOXOOOO).
Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their
data during idle. In the idle mode, the internal clock signal
is gated off to the CPU, but interrupt, timer and serial port
functions are maintained. Table I describes the status of
the external pins during Idle mode.
There are three ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.O to
be cleared by hardware, terminating Idle mode. The
interrupt is serviced, and following RETI, the next
instruction to be executed will be the one following the
instruction that wrote I to PCON.O.
II.6.6
The flag bits GFO and GFI may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear one
or both flag bits. When Idle mode is terminated by an
enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of terminating the Idle mode is with a
hardware reset. Since the oscillator is still running, the
hardware reset needs to be active for only 2 machine
cycles (24 oscillator periods) to complete the reset
operation.
The third way to terminate the Idle mode is the activation
of any disabled interrupt when recover is programmed
(RPD = I). This will cause PCON.O to be cleared. No
interrupt is serviced. The next instruction is executed. If
interrupt are disabled and RPD = 0, only a reset can
cancel the Idle mode.
Power Down Mode
The instruction that sets PCON.I is the last executed prior
to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM and
the Special Function Register is saved during power down
mode. The three ways to terminate the Power Down mode
are the same than the Idle Mode. But since the onchip
oscillator is stopped, the external interrupts, timers and
serial port must be sourced by external clocks only, via
INTO, INTI, TO, Tl.
In the Power Down mode, Vcc may be lowered to
minimize circuit power consumption. Care must be taken
to ensure the voltage is not reduced until the power down
mode is entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator. Reset
should not be released until the oscillator has restarted
and stabilized.
When using voltage reduction : interrupt, timers and
serial port functions are guaranteed in the Vcc
specification limits.
Tahle I describes the status of the external pins while in
the power down mode. It should be noted that if the power
down mode is activated while in external program
memory, the port datu that is held in the Special Function
Register P2 is restored to Port 2. If the port switches from
o to I, the port pin is held high during the power down
mode by the strong pull up, T I, shown in figure 4.
MATRAMHS
Rev. D (14 Jan. 97)
TEMIe
83C154D
Semiconductors
Table l.Status of the external pins during idle and power down modes.
MODE
PROGRAM MEMORY
ALE
PSEN
PORTO
PORT!
PORT2
PORT3
Idle
Internal
I
I
Port Data
Port Data
Port Data
Port Data
Idle
External
I
I
Floating
Port Data
Addrcs~
Port Datu
Power Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Power Down
External
0
0
Floating
Port Data
Port Data
Port Data
Figure 4.1/0 Buffers in the 83C154D (Ports 1, 2, 3).
vee vee
FLOAT
Q
vee
--1=====.1
FROM
~~~
C>-t-::fl-----IC
FLOAT
FLOAT
----L/--..vr::;::::::;=~
Stop Clock Mode
Due to static design, the TEMIC 83C 154D clock speed
can be reduced until 0 MHz without any data loss in
memory or registers. This mode allows step by step
utilization, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. At 0 MHz, the power consumption is the same
as in the Power Down Mode.
I/O Ports
The 1/0 drives for PI. P2, P3 of the 83CI54D are
impedance programmable. The I/O buffers for Ports I, 2
and 3 are implemented as shown in figure 4.
When the port latch contains 0, all pFETS in figure 4 are
off while the nFET is turned on. When the port latch
makes a O-to-I transition, the nFET turns off. The strong
pullup pFET, T I, turns on for two oscillator periods,
pulling the output high very rapidly. As the output line is
drawn high, pFET T3 turns on through the inverter to
supply the IOH source current. This inverter and T3 form
a latch which holds the I and is supported by T2. When
Port 2 is used as an address port, for access to external
program of data memory, any address bit that contains a
I will have his strong pullup turned on for the entire
duration of the external memory access.
When an I/O pin on Ports I, 2, or 3 is used as an input, the
user should be aware that the external circuit must sink
current during the logical I-to-O transition. The
MATRAMHS
Rev. D (14 Jan. 97)
maximum sink current is specified as ITL under the D.C.
Specifications.
When
the
input
goes
below
approximately 2 V, T3 turns off to save ICC current. Note,
when returning to a logical I, T2 is the only internal
pullup that is on. This will result in a slow rise time if the
user's circuit does not force the input line high.
The input impedance of Port I, 2, 3 are programmable
through the register laCON. The ALF bit (IaCONO) set
all of the Port I, 2, 3 floating when a Power Down mode
occurs. The PIHZ, P2HZ, P3HZ bits (laCON I ,
IOCON2, IOCON3) set respectively the Ports PI, P2, P3
in floating state. The IZC (lOCON4) allows to choose
input impedance of all ports (PI, P2, P3). When IZC = 0,
T2 and T3 pullup of 1/0 ports are active; the internal input
impedance is approximately 10 K. When IZC = I only T2
pull-up is active. The T3 pull-up is turned off by IZC. The
internal impedance is approximately 100 K.
Oscillator Characteristics
XTAL I and XTAL2 are the input and output respectively,
of an inverting amplifier which is configured for use as an
on-chip oscillator, as shown in figure 5. Either a quartz
crystal or ceramic resonator may be used.
To drive the device from an external clock source,
XTALI should be driven while XTAL2 is left
unconnected as shown in figure 6. There are no
requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is
through a divide-by-two flip-flop, but minimum and
maximum high and low times specified on the Data Sheet
must be observed.
Figure 5. Crystal Oscillator.
XTAL2: 18
XTAL1 : 19
~-------------IVSS:20
11.6.7
2
TEMIC
83C154D
Semiconductors
Figure 6. External Drive Configuration.
NC
XTAL2: 18
EXTERNAL
OSCILLATOR
SIGNAL
XTAL1 : 19
VSS: 20
-:-
Hardware Description
Same as for the 80CSI except for the following:
TimerlEvent Counter 2
Timer 2 is a 16 bit timer/counter like Timers 0 and I, it
can operate either as a timer or as an event counter. This
is selected by bit C/T2 in the Special Function Register
T2CON (Figure 1). It has three operating modcs :
"capture", "autoload", and "baud rate generator", which
are selected by bits in T2CON as shown in Table 2.
Figure 7. Timer 2 in Capture Mode.
Table 2. Timer 2 Operating Modes.
_RC~K+
TCLK.
0
0
I
X
crmo
,
-
0
I
X
X
In the auto-reload mode there are again two options,
which are selected by bit EXEN2 in T2CON. If EXEN2 =
0, then when Timer 2 rolls over it not only sets TF2 but
also causes the Timer 2 registers to be reloaded with the
16 bit-value in registers RCAP2L and RCAP2H, which
are preset by software. If EXEN2 = I, then Timer 2 still
does the above, but with the added feature that a I-to-O
transition at external input T2EX will also trigger the 16
bit reload and set EXF2.
The auto-reload mode is illustrated in Figure 8.
i
TR2
MODE
--
I
I
I
0
16 bit auto-reload
16 bit capture
baud capture generator
(oft)
In the capture mode there are two options which are
selected by bit EXEN2 in T2CON. If EXEN2 = 0, then
Timer 2 is a 16 bit timer or counter which upon
overflowing sets bit TF2, the Timer 2 overflow bit, which
can be used to generate an interrupt. If EXEN2 = I, then
Timer 2 still does the above, but with the added feature
that a I-to-O transition at external input T2EX causes the
current value in the Timer 2 registers, TL2 ans TH2, to be
captured into registers RCAP2L and RCAP2H,
respectively. In addition, the transition at T2EX causes bit
EXF2 in T2CON to be set, and EXF2, like TF2, can
generate an interrupt.
The capture mode is illustrated in Figure 7.
: CONTROL
EXEN2
Figure 8. Timer in Auto-Reload Mode.
: CONTROL
EXEN2
11.6.8
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
83C154D
Semiconductors
(lSB)
(MSB)
The baud rate generator mode is selected by : RCLK = I and/or TCLK = I.
Name and Signilicance
Symbol
Position
TF2
T2CON.7
Timer 2 overflow flag :-oct oy a Timer 2 overflow and 11111'-,1 be clcarcu by :-;ufLwarc. TF2
will not be set when either RClK ~ 1 OR TClK ~ I.
EXF2
T2CON.6
Timer 2 external flag set when either a capture or reload is caused hy a negative
transition on T2EX and EXEN2::: 1. When Timer 2 interrupt j:-. cnahlcu., EXF2:;:: 1 will
cau:-,e the CPU to veclOr to the Timer 2 interrupt routine. EXF2 Illu:-.t be cleared hy
software.
RClK
T2CON.5
Receive clock /lag. When set, callses the :-.crial port to usc Timcr2 ovcrllow pul<.;cs 1'01' its
receive clock in moues I and 3. RCLK :::: () cau:-.c<.; Timer I overflow to be used ror the
receive clock.
TClK
T2CONA
Trammit clock flag. When set, causes thc ~crial port to U 12 MHz (Vcc = 5.5 V)
MATRAMHS
Rev. D (14 Jan. 97)
Icc (rnA) = 1.14 x Freq (MHz) + 12.2
Icc Idle (rnA) = 0.36 x Freq (MHz) + 2.7
II.6.17
TEMIC
83C154D
Semiconductors
Note 1:
ICC is measured with all output pins disconnected ;
XTALI driven with TCLCH, TCHCL = 5 ns, VIL = VSS
+ .5 V, VIH = VCC -.5 V ; XTAL2 N.C. ; EA = RST =
Port 0 = VCC. ICC would be slightly higher if a crystal
oscillator used. Idle ICC is measured with all output pins
disconnected; XTAL I driven with TCLCH, TCHCL = 5
ns, VIL = VSS + .5 V, VIH = VCC -.5 V ; XTAL2 N.C ;
Port 0 = VCC ; EA = RST = VSS.
Power Down ICC is measured with all output pins
disconnected; EA = PORT 0 = VCC ; XTAL2 N.C. ;
RST=VSS.
Note 2 :
Capacitance loading on Ports 0 and 2 may cause spurious
noise pulses to be superimposed on the VOLS of ALE and
Ports 1 and 3. The noise is due to external bus capacitance
discharging into the Port 0 and Port 2 pins when these pins
make 1 to 0 transitions during bus operations. In the worst
(capacitive loading 100 pF), the noise pulse on the ALE
line may exceed 0.45 V with maxi VOL peak 0.6 V. A.
Schmitt Trigger use is not necessary.
Figure 14. ICC Test Condition, Idle Mode.
All Other Pins Are Disconnected.
Figure 16. ICC Test Condition, Power Down Mode.
All Other Pins Are Disconnected.
RST EA
(NC)
CLOCK
SIGNAL
RST
XTAL2
XTAL1
(NC)
XTAL2
XTAL1
VSS
VSS
Figure 15. ICC Test Condition, Active Mode.
All Other Pins Are Disconnected.
VCC
RST
(NC)
CLOCK
SIGNAL
XTAL2
XTAL1
VSS
Figure 17. Clock Signal Waveform for ICC Tests in Active And Idle Modes. TCLCH = TCHCL = 5 ns.
TCHCL
!4------TCLCL-------I"'i
11.6.18
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
83C154D
Semiconductors
Explanation of the AC Symbol
Example:
Each timing symbol has 5 characters. The first character
is always a "T" (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
Q : Output data.
A: Address.
C: Clock.
R : READ signal.
T: Time.
V: Valid.
W : WRITE signal.
X ; No longer a valid logic level.
Z: Float.
o : Input data.
H : Logic level HIGH
I : Instruction (program memory conlents).
L : Logic level LOW, or ALE.
P: PSEN.
AC Parameters
TA = 0 to + 70°C; Vss = 0 V; Vec = 5 V ± 10 % ; F = 0 to 30 MHz
TA = 0° + 70°C ; V ss = 0 V ; 2.7 V < V cc < 5.5 V ; F = 0 to 16 MHz
TA=-55° + 125°C; Vss =OV; Vcc = 5 V± 10 %; F=O to 25 MHz
(Load Capacitance for PORT O. ALE and PSEN
= 100 pF ; Load Capacitance for al1 other outputs = 80 pF)
External Program Memory Characteristics
.. ",:"
SVMJ)O:L
'-,
'
TLHLL
.
PARAMETER
.',
l6MHz
MIN
ALE Pulse Width
110
MAX
20MHt
MIN
MAX
25 MHz
MIN
90
70
MAX
30 MHz
MIN
TAVLL
Address valid to ALE
40
30
20
15
TLLAX
Address Hold After ALE
35
35
35
35
TLLTV
ALE to valid instr in
TLLPL
ALEtoPSEN
45
TPLPH
PSEN pulse Width
165
TPLTV
PSEN to valid instr in
TPXTX
Input instr Hold After PSEN
TPXTZ
Input instr Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid instr in
TPLAZ
PSEN low to Address Float
170
185
40
0
80
85
0
45
50
65
0
35
40
50
100
25
100
110
0
55
130
30
130
125
MAX
60
30
35
230
210
170
130
10
10
8
6
External Program Memory Read Cycle
ALE
PORT2 _ _ _ _../
MATRAMHS
Rev. D (14 Jan. 97)
II.6.19
TEMIC
83C154D
Semiconductors
External Data Memory Characteristics
External Data Memory Write Cycle
I
TWHLH
~
"
ALE
_TLLWL----l_
PORTO
PORT 2
>--<
_-TAVWL
.TLLAX+j
AO-A7
)<
ADDRESS
OR SFR-P2
IX
I
TWLWH
~
TOVWX
/
TQVWH
IoorTWHQX~
J
DATA OUT
ADDRESS AS-A15 OR SFR-P2
External Data Memory Read Cycle
~
_ _ _ I".If---- TLLDV-----J
TWHLH ,..
ALE
RD
------------i---~~~~J_------_+TRLRH------~~V~~-TRHDX
PORTO
DATA IN
TRLAZ
PORT 21
11.6.20
MATRAMHS
Rev_ D (14 Jan_ 97)
TEMIC
83C154D
Semiconductors
Serial Port Timing - Shift Register Mode
16 MHz
PARAMETER
SYMBOL
MIN
MAX
20 MHz
MIN
25 MHz
MAX
MAX
MIN
30 MHz
MIN
TXLXL
Serial Port Clock Cycle Time
750
600
480
400
TQVXH
Output Data Setup to Clock Rising Euge
563
480
380
300
TXHQX
Output Data Hold after Clock Rising Edge
63
90
65
50
TXHDX
Input Data Hold aftcr Clock Rising Edge
0
0
()
TXHDV
Clock Rising Edge to Input Data Valid
563
MAX
0
450
350
300
Shift Register Timing Waveforms
INSTRUCTION
o
2
3
4
5
6
7
8
CLOCK
OUTPUT DATA
1
WRITE TO SBUF
INPUT DATA_-'-_ _J
...
CLEAR RI
MATRAMHS
Rev. D (14 Jan. 97)
...
SETIN
11.6.21
B
TEMIC
83C154D
Semiconductors
External Clock Drive Characteristics (XTALl)
SYMBOL
PAR~METER
;'
,
MIN ;
UNIT ,',
MAX
"
30
;
",
MHz
FCLCL
Oscillator Frequency
TCLCL
Oscillator period
TCHCX
TCLCX
TCLCH
Rise Time
5
ns
TCHCL
Fall Time
5
ns
333
ns
High Time
5
ns
Low Time
5
ns
External Clock Drive Waveforms
TCHCl
----'TClCX
\4-------TClCl,--------IOot
AC Testing Input/Output, Float Waveforms
=X:
INPUT/OUTPUT
VCC-o,
5V
0,45 V
0,2 Vcc - 0,9
)C
__0..;.,2_V;;;cc,;...-_0;..,1_ _ _ _ __
AC inputs during testing are driven at Vcc - 0,5 for a logic "I" and 0,45 V for a logic "0", Timing measurements are
made at VIH min for a logic" I" and VIL max for a logic "0".
Float Waveforms
FLOAT
~---- FLOAT----~
VLOAD
VLOAD + 0,1 V
VLOAD + 0,1 V
For timing purposes as port pin is no longer floating when a 100 m V change from load voltage occurs and begins to
float when a 100 mV change from the loaded VOHNOL level occurs. IollIoH > ± 20 rnA.
11.6.22
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
83C154D
Semiconductors
Clock Waveforms
I
INTERNAL
CLOCK
STATE 4
I
P1 I P2
STATE
51
P1 I P2
STATE 6
P1
I P2
I
STATE 1
P1
I
I P2
STATE 2
P1
I
I P2
STATE 3
P1
I
I P2
STATE 4
I
P1 I P2
STATE
5I
P1 I P2
XTAL2
'- I
ALE
I
' " THESE SIGNALS ARE NOT
ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
,.----...,
PSEN
PO
P2 (EXT)
READ CYCLE
B
'--_ _-::-'DATA
I
SAMPLED
I
_
FLOAT-----+I
I
~
____-,1 INDICATES ADDRESS TRANSITIONSLI_ _ _ _ _ _ _ _ _ _-'
RD
OOH IS EMITTED
DURING THIS PERIOD
PO
______
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
--'r--D~P-LO~R~R~i--,~I~.~----------~~~~------~1
OUT
~I..
FLOAT SAMPLED
.. I
I
~
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
WRITE CYCLE
L _ _ _ _ _ _ _ _ _ _.....I PCLOUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
WR
DP~~f
PO
Ri
I..
DATA OUT
INDICATES DPH OR P2 SFR TO PCH TRANSITIONS
P2
1'i. I~CLOUT:~OGRAM
1MEMORY IS EXTERNAL)
PORT OPERATION
MOV PORT SRC
__________
O_LD_D_AT._A-'I NEW DATA
~
PO PINS SAMPLED
MOVDESTPO
MOV DEST PORT-(P-1-,P-2-,-P3-)---'
PO PINS SAMPLED
~
(INCLUDES INTO, INT1, TO, T1)
ITIL--------------------FfL
SERIAL PORT SHIFT CLOCK
I
TXD
(MODE 0)
P1, P2, P3 PINS SAMPLED
--------1H~
RXD SAMPLED
I
P1, P2, P3
PINS SAMPLED
jll
RXD SAMPLED
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (TA = 25°C fully loaded) RD
and WR propagation delays are approximately 50 ns. The other signals are typically 85 ns, Propagation delays are
incorporated in the AC specifications.
MATRAMHS
Rev. D (14 Jan. 97)
11.6.23
TEMIC
83C154D
Semiconductors
Ordering Information
s
T
-30
T
Part Number
83C154D Rom 32 K x 8
83C154DC Secret ROM version
83C154DT Secret Tag version
Temperature Range
blank : Commercial
I
: Industrial
A
: Automotive
M
: Military
Package Type
P: PDIL40
S: PLCC44
Fl: PQFP 44 (Foot print 13.9 mm)
F2: PQFP 44 (Foot print 12.3 mm)
V: VQFP (1.4 mm)
T: TQFP (1.0 mm)
D: CDIL40
Q: CQFP44
R: LCC44
11.6.24
xxx
83C154DC
D
T
-12
-16
-20
-25
-30
-L16
: 12 MHz version
: 16 MHz version
: 20 MHz version
: 25 MHz version
: 30 MHz version
: Low Power
(Vcc : 2.7-5.5 V
Freq: 0-16 MHz)
T
R : Tape and Reel
D: Dry Pack
Flow
1883: MIL 883 Compliant
P883: MIL 883 Compliant
with PIND test.
Customer Rom Code
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
Semiconductors
B
CS1 Computer/Communication Products
TSCS051C1 : S-Bit Microcontroller for Digital Computer Mouitors ...•........... 11.7.1
TSCS051C2: S-Bit Microcontroller for Digital Computer Mouitors •.•.••.•••.•... II.S.1
TEMIC
TSC8051Cl
Semiconductors
8-Bit Microcontroller for Digital Computer Monitors
1. Introduction
The TSC8051CI is a stand-alone high performance
CMOS 8-bit embedded microcontroller and is designed
for use in CRT monitors. It is also suitable for automotive
and industrial applications.
In addition, the TSC8051Cl has 2 software selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial ports, and the interrupt
The TSC8051CI includes the fully static 8-bit "80C51" system continue to function. In the power down mode the
CPU core with 256 bytes of RAM; 8 Kbytes of ROM; two RAM is saved and all other functions are inoperative.
16-bit timers; 12 PWM Channels; a 6 sources and 2-level The TSC8051 C 1 enables the users reducing a lot of
interrupt controller; a full duplex serial port; a full 12CTM* external discrete components while bringing the
interface; a watchdog timer and on-chip oscillator.
maximum of flexibility.
2. Features
•
Boolean processor
•
Watchdog reset
•
Fully static design
•
On chip oscillator for crystal or ceramic resonator
•
8K bytes of ROM
•
2 power saving control modes:
• Idle mode
• Power-down mode
•
Controlled HSYNC & VSYNC outputs
•
Up to 12 programmable PWM channels with 8-bit
resolution
•
Up to 32 programmable 110 lines depending on the
package
•
40 pins DIP, 44 pins PQFP, 44 and 52 pins PLCC
packages
•
•
Commercial and industrial temperature ranges
Operating Frequency: 12 MHz to 16 MHz
•
256 bytes of RAM
•
2 x 16-bit timer/counter
•
Programmable serial port
•
Programmable Multimaster I2C controller
•
6 interrupt sources:
• External interrupts (2)
• Timers interrupt (2)
• Serial port interrupt
• I2C interrupt
* 12C is a trademark of PHILIPS Corporation
MATRAMHS
Rev. D (14 Jan. 97)
11.7.1
II
TEMIC
TSC8051Cl
Semiconductors
3. Block Diagram
TI
TO INTO
VCC
0
.........................
~
L
~
:
~"
2
::
7L
"
PARALLELIJO
PORTS AND
EXTERNAL BUS
v
<~
~
~
""
..
"
PO
..
7-
7'"
PI
DATA
MEMORY
256 x 8 RAM
;.
L
;.
7-
"
7-
8-BIT INTERNAL BUS
7-
~Y'-
PROGRAM
MEMORY
8kx8ROM
;.
7-
;.
~
I
CPU
;. 8OC51 CORE
EXCLUDING
ROM/RAM
"
~
:
t
TWOI6-BIT
T1MERIEVENT
COUNTER
~
.. - .. ---- .... ------.- .... -.-
rnTil
TO
~
~
.~........................... L...... ...l.
+
~
vss
P2
;.
7-
"
SERIAL
UART
PORT
:.
"" ... [0... 0
7-
L
TxD
~ ALTERNATE FUNCTION OF PORTO
~ ALTERNATE FUNCTION OF PORTl
I
SPECIAL
EXTERNAL
INPUTS
L
"
SERIAL]2c
PORT
;.
L
7-
;.
7-
"
7
.; 7-
--------------------
_ _ OM
RxD
,
..... _....
7
;.
CONTROLLED
HSYNC & VSYNC
OUTPUTS
12 x 8-bitPWM
CHANNELS
----
;.
"
L
7'
P3
_ _ MO •
L
~
SCL
0 0 0 .. 0
;.
WATCHDOG
TIMER
...
SDA
~········~r
PWMO
P~8
PW~17
PWMll
o0
0
VSYNC
HSYNC
VOUT
HOUT
~ ALTERNATE FUNCTION OF PORT2
o
ALTERNATE FUNCTION OF PORT3
Figure 1. TSC8051C1 block diagram.
II.7.2
MA1RAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
4. Pin Configurations
u
~"'oo
PI.OIPWMR
vee
PI.IIPWM9
PO.O/ADO
PI.2IPWMIO
PO.I/ADI
PI.3IPWMII
'1:
INDEX
CORNE
PO.2/AD2
PI.4
PO.3/AD3
PI.5
PI.5
PO.4/AD4
PI.6
PI.6
P0.5/AD5
PI.7
PI.7
PO.6/AD6
RST
RST
PO.7/AD7
j::
:8::
:9::
io:
P3.0/RXD
"ii'
NC
"ii'
P3.lrrXD
PWM6':'
i"3'
14:
15:
'ii,:
PWM5'
it"
P3.0/RXD
EA
P3.I/TXD
ALE
P3.2IINTONSYNC
PSEN
P3.2/INTO/VSYNe
PWM7"
P3.3IINTINOUT
P3.4rrOIHSYNC
PWM6"
P3.5fT1/HOUT
PWM5'
P3.6IWRlSCL
PWM4"
P3.7IRD/SDA
PWM3"
XTAL2
XTALI
PWM2"
PWMI ,.
vss
PWMO'
PWMT'
:E;:: ::s::s
::s
;::;:: ;::
e: e:e:: ~
'"
r-~
u
u u
>
0
N
0: 0:
0..0..
Z
0 0 0 ""
ci
0.. 0.. 0.. "-
:6: :5:
.4~3~ :2~ :I:
<14 :~j 42 41: ~q
-:
0:
39
PO.4
38
37
PO.5
36
35.
PLCC44
PO.6
PO.7
EA
34
NC
~3,
ALE
32
PSEN
PWMT
PWM6"
PWM5*
is
*PWMx or P2.x depending on option (see ordering information)
INDEX
CORNER
PO.5
PO.6
PO.7
EA
ALE
PSEN
PLCCS2
P2.7
PWM7
P2.6
PWM6
P2.5
NC
'.i!!:
P3.6IWRISCL
20:
PWM5
PWM4
~j ~:i '2j
..:
'"
I~'"
N
:2.1 :2$ :26
'">
~ ~ '"
...l
:J
><: ><:
r:::
0
N
0..
~
:2i
:~ ~~ :j~ ,jj
N
:E
0..
~
N
N
0..
::s . ..,
N
~ ~
0..
~
'1:
~
,.;
0..
Figure 2. TSC8051Cl pin configurations.
MATRAMHS
Rev. D (14 Jan. 97)
11.7.3
II
TEMIC
TSC8051Cl
Semiconductors
5. Pin Description
vee
Port 2 emits the high-order 8-bit address during fetches
from external Program Memory and during accesses to
external Data Memory that use 16-bit addresses. In this
application it uses strong internal pull-up when emitting
I's.
Power supply voltage.
Port 2 can sink and source 3 LS TTL loads.
RST
PORT 3 (P3.O-P3.7)
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal
pulldown resistor permits power-on reset using only a
capacitor connected to VCC.
Port 3 is an 8-bit bidirectional 110 port with internal
pullups. Port 3 pins that have l's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pullups.
VSS
Circuit ground.
PORT 0 (PO.O-PO.7)
Port 0 is an 8-bit open-drain bidirectional 1/0 port. Port
opins that have I's written to them float, and in that state
Each line on this port has 2 or 3 functions either a general
110 or special control signal, as listed below:
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during access to external Program and Data memory.
In this application it uses strong internal pull-up when
emitting I's.
P3.0
RXD: serial input port.
P3.1
TXD: serial output port.
P3.2
INTO: external interrupt O.
VSYNC: vertical synchro input.
P3.3
INTI: external interrupt 1.
VOUT: buffered V-SYNC output.
P3.4
TO: Timer 0 external input.
HSYNC: horizontal synchro input.
P3.5
TI: Timer I external input.
HOUT: buffered H-SYNC output.
P3.6
WR: external data memory write strobe.
SCL: serial port clock line I2C bus.
P3.7
RD: external data memory read strobe.
SDA: serial port data line I2C bus.
Port 0 can sink and source 8 LS TIL loads.
PORT 1 (Pl.O-Pl.7)
Port I is an 8-bit bidirectional 110 port with internal
pullups. Port I pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port I pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pullups.
Port 1 also serves 4 programmable PWM open drain
outputs, as listed below:
Port 3 can sink and source 3 LS TTL loads.
Pl.O
PWM8: Pulse Width Modulation output 8.
Pl.l
PWM9: Pulse Width Modulation output 9.
PI.2
PWMIO: Pulse Width Modulation output 10.
PI.3
PWMII: Pulse Width Modulation
II.
Port 1 can sink and source 3 LS TTL loads.
PORT 2 (P2.O-P2.7)
Port 2 is an 8-bit bidirectional 1/0 port with internal
pullups. Port 2 pins that have l's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pullups.
11.7.4
PWM0-7
These eight Pulse Width Modulation outputs are true
open drain outputs and are floating after reset.
ALE
The Address Latch Enable output signal occurs twice
each machine cycle except during external data memory
access. The negative edge of ALE strobes the address
into external data memory or program memory. ALE
can sink and source 8 LS TIL loads.
If desired, ALE operation can be disabled by setting bit
o of SFR location AFh (MSCON). With the bit set, ALE
is active only during MOVX instruction and external
fetches. Otherwise the pin is pulled low.
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
XTALl
When the External Access input is held high, the CPU
executes out of internal program memory (unless the
Program Counter exceeds IFFFh). When EA is held low
the CPU executes only out of external program memory.
must not be left floating.
Input to the inverting oscillator amplifier and input to the
external clock generator circuits.
XTAL2
Output from the inverting oscillator amplifier. This pin
should be non-connected when external clock is used.
The Program Store Enable output signal remains high
during internal program memory. An active low output
occurs during an external program memory fetch. PSEN
can sink and source 8 LS TTL loads.
MATRAMHS
Rev. D (14 Jan. 97)
E
II.7.S
TEMIC
TSC8051Cl
Semiconductors
6. Basic Functional Description
6.1. Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
operate while the clock to the CPU is gated off.
F~1
XTAL2
XTALI
These special modes are activated by software via the
Special Function Register, its hardware address is 87h.
PCON is not bit addressable.
H----
INTERRUPT
SERIAL PORT
TIMER BLOCKS
CPU
Figure 3, Idle and Power Down Hardware.
PCON: Power Control Register
MSB
SFR 87h
LSB
GFI
SMOD
PD
GFO
lDL
PCON.O
Idle mode bit. Setting this bit activates idle mode operation.
PO
PCON.I
Power Down bit. Setting this bit activates power down operation.
GFO
PCON.2
General-purpose nag bit.
GFI
PCON.3
General-purpose flag bit.
PCON.4
(Reserved).
PCON.S
(Reserved).
SMOD
lDL
PCON.6
(Reserved).
PCON.7
Double Baud rate bit. Setting this bit causes the baud rate to double when the serial port
is being used in either modes 1,2 or 3.
If I 's are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is OXXXOOOOb.
6.1.1. Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM, and all other register maintain their
data during Idle Table I describes the status of the
external pins during Idle mode.
There are two ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.O
to be cleared by hardware terminating Idle mode. The
interrupt is serviced, and following RET!, the next
instruction to be executed will be the one following the
instruction that wrote 1 to PCON.O.
11.7.6
The flag bits OFO and OFl may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear
one or both flag bits. When Idle mode is terminated by
an enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of
hardware reset. Since
hardware reset needs
cycles (24 oscillator
operation.
terminating the Idle is with a
the oscillator is still running, the
to be active for only 2 machine
periods) to complete the reset
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
6.1.2. Power Down Mode
The instruction that sets PCON.I is the last executed
prior to entering power down. Once in power down, the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register are saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. The hardware reset
initiates the Special Function Register. In the Power
Down mode, VCC may be lowered to minimize circuit
power consumption. Care must be taken to ensure the
voltage is not reduced until the power down mode is
entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator.
Reset should not be released until the oscillator has
restarted and stabilized. Table I describes the status of
the external pins while in the power down mode. It
should be noted that if the power down mode is activated
while in external program memory, the port data that is
held in the Special Function Register P2 is restored to
Port 2. If the data is a I, the port pin is held high during
the power down mode by the strong pull up transistor.
I
Table 1. Status of the external pins during Idle and Power Down modes.
~ • • Mode ',' . program,
I:.>
ALE
Memory
Idle
Internal
I
,,'
,
PSEN
PortO
Port 1
Port 2
Port 3
PWMx
I
Port Data
Port Data
Port Data
Port Data
Floating
Idle
External
I
I
Floating
Port Data
Address
Port Data
Floating
Power Down
Internal
0
0
Port Data
Port Data
Port Data
Port Data
Floating
Power Down
External
0
0
Floating
Port Data
Port Data
Port Data
Floating
6.2. Stop Clock Mode
6.4. 110 Configurations
Due to static design, the TSC8051CI clock speed can be
reduced down to 0 MHz without any data loss in memory
or register. This mode allows step by step code
execution, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. When the clock is stopped, the power
consumption is the same as in the Power Down Mode.
Figure 4. shows a functional diagram of the generic bit
latch and 110 buffer in each of the four ports. The bit
latch, (one bit in the port SFR) is represented as a D type
flip-flop. A 'write to latch' signal from the CPU latches
a bit from the internal bus and a 'read latch' signal from
the CPU places the Q output of the flip-flop on the
internal bus. A 'read pin' signal from the CPU places the
actual pin logical level on the internal bus.
Some instructions that read a port read the actual pin,
and other instructions read the latch (SFR).
6.3. 110 Ports Structure
The TSC8051CI has four 8-bit ports. Each port consist
of a latch (special function register PO to P3), an input
buffer and an output driver. These ports are the same as
in 80C51, with the exception of the additional functions
of port I and port 3 (see Pin Description section).
MATRAMHS
Rev. D (14 Jan. 97)
II.7.7
TEMIC
TSC8051Cl
ADDRIDATA
Semiconductors
VCC
PWMX
INT
BUS
INT.
BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
VCC
READ
PIN
PIN
J PORT I BI11
* Internal pull-up not pre~ent on Pl.O to PI.3 when PWM8 10 PWM II
J PORTO BITJ
are enabled
ADDR
CONTROL
ALTERNATE
VCC
OUTPUT
SlOl
FUNCTION CONTROL'
VCC
INT.
BUS
INT.
BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
READ
PIN
READ
PIN
JPORT2 BIT J
J PORT 3 BI11
of:
Internal pull-up not present on P3.6 and P3.7 when SIOI
i~
enabled.
Figure 4. Port Bit Latches and 110 buffers
6.5. Reset Circuitry
The reset circuitry for the TSC80SlCl is connected to
the reset pin RST. A Schmitt trigger is used at the input
for noise rejection (see Figure S. ).
A reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while
the oscillator is running. The CPU responds by
executing an internal reset. It also configures the ALE
and PSEN pins as inputs (they are quasi-bidirectional).
A Watchdog timer underflow if enabled, will force a
reset condition to the TSC80S1 Cl by an internal
connection.
The internal reset is executed during the second cycle in
which reset is high and is repeated every cycle until RST
goes low. It leaves the internal registers as follows:
11.7.8
Register
Content
ACC
OOh
B
lJOh
DPTR
OOOOh
EICON
OOh
HWDR
OOh
IE
OXOlJOlJOOb
IP
XXOOOOOOb
MSCON
XXXXXXXOb
MXCRO-I
OOh
PO-P3
FFh
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
0000
Rj!gister
VCC __
Content
~
________
~
1'0
PC
OOOOh
PCON
OXXXOOOOb
PSW
OOh
PWMO-II
OOh
PWMCON
XXXXXXXOb
SICON
OOh
SlOAT
OOh
SlSTA
F8h
SBUF
OOh
SCON
OOh
SOCR
OOh
SP
07h
TCON
OOh
THO, THI
OOh
TLO, TLl
OOh
TMOD
OOh
Figure 6. Power-on Reset Circuit
XTALI and XTAL2 are respectively the input and
output of an inverting amplifier which is configured for
use as an on-chip oscillator. As shown in Figure 7. ,
either a quartz crystal or ceramic resonator may be used.
To drive the device from an external clock source,
XTALI should be driven while XTAL2 is left
unconnected as shown in Figure 8.
The internal RAM is not affected by reset At power-on
reset, the RAM content is indeterminate,
RST~t----l
E
6.6. Oscillator Characteristics
There are no requirements on the duty cycle of the
external clock signal, since the input to the internal
clocking circuitry is through a divide-by-two flip-flop.
The minimum high and low times specified on the data
sheet must be observed however.
Re.\et
Circuitry
XTAL2
On--chip
resistor
XTALI
Watchdog
Reset
1------------------1 vss
Figure 5. On-Chip Reset Configuration.
Figure 7. Crystal Oscillator
An automatic reset can be obtained when vec is turned
on by connecting the RST pin to vce through a lJ.1F
capacitor providing the vee setting time does not
exceed lms and the oscillator start-up time does not
exceed lOms, This power-on reset circuit is shown in
Figure 6, When power comes on, the current drawn by
RST starts to charge the capacitor. The voltage at RST
is the difference between vee and the capacitor
voltage, and decreases from vce as the capacitor
charges, VRST must remain above the lower threshold of
the Schmitt trigger long enough to effect a complete
reset The time required is the oscillator start-up time,
plus 2 machine cycles.
MATRAMHS
Rev. D (14 Jan. 97)
NC
EXTERNAL
OSCILLATOR
SIGNAL
XTAL2
XTALI
-.-l
vss
Figure 8. External Drive Configuration
II.7.9
TSC8051Cl
6.7. Memory organization
The memory organisation of the TSC8051CI is the same
as in the 80C51, with the exception that the TSC8051CI
has 8k bytes ROM, 256 bytes RAM, and additional
SFRs. Details of the differences are given in the
following paragraphs.
In the TSC805ICI, the lowest 8k of the 64k program
memory address space is filled by internal ROM.
Depending on the package used, external access is
available or not. By tying the EA pin high, the processor
fetches instructions from internal program ROM. Bus
expansion for accessing program memory from 8k
upward is automatic since external instruction fetches
occur automatically when the program counter exceeds
I FFFh. If the EA pin is tied low, all program memory
fetches are from external memory. The execution speed
is the same regardless of whether fetches are from
external or internal program memory. If all storage is
on-chip, then byte location 1FFFh should be left vacant
to prevent an undesired pre-fetch from external program
memory address 2000h.
Certain locations in program memory are reserved for
specific purposes. Locations OOOOh to 0002h are
reserved for the initialisation program. Following reset,
the CPU always begins execution at location OOOOh.
Locations 0003h to 0032h are reserved for the six
interrupt request service routines.
II.7.lO
TEMIC
Semiconductors
The internal data memory space is divided into a
256-bytes internal RAM address space and a 128 bytes
special function register address space.
The internal data RAM address space is 0 to FFh. Four
8-bit register banks occupy locations 0 to IFh. 128 bit
locations of the internal data RAM are accessible
through direct addressing. These bits reside in 16 bytes
of internal RAM at location 20h to 2Fh. The stack can
be located anywhere in the internal data RAM address
space by loading the 8-bit stack pointer (SP SFR).
The SFR address space is lOOh to IFFh. All registers
except the program counter and the four 8-bit register
banks reside in this address space. Memory mapping of
the SFRs allows them to be accessed as easily as internal
RAM, and as such, they can be operated on by most
instructions. The mapping in the SFR address space of
the 43 SFRs is shown in Table 2. The SFR names in
italic are TSC805lCl new SFRs and are described in
Peripherals Functional Description section. The SFR
names in bold are bit addressable.
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
Table 2. Mapping of Special Function Register
'oi3o .i, 1"'6/8
00
0'
i7lir°
41C
SID
PWM8
PWM9
PWMIO
PWMll
B
PWM4
PWM5
PWM6
PWM7
PWMO
PWMI
PWM2
PWM3
0100
ACC
EICON
SOCR
HWDR
D8
SlCON
DO
psw
1/9
2/A
31B
I00,00'l7S : 000.
I~
l)tlf
::: 00
00_ 00_
SlSTA
6/E}
SlDAT
MXCRO
PWMCON
MXCRI
·CS
CO
I:
DB
IP
DO
P3
A8°
IE
, AtL,
P2
0 98
SCON
00 9~
PI
88
0'00
MSCON
SBUF
TCON
TMOD
TLO
TLI
PO
SP
DPL
DPH
THO
THI
PCON
6.8. Interrupts
6.8.1. Interrupt Enable Register:
The TSC80S1 C I has six interrupt sources, each of which
can be assigned one of two priority levels. The five
interrupt sources common to the 80CSI are the external
interrupts (INTO and INTI), the timer 0 and timer I
interrupts (ITO and ITI), and the serial I/O interrupt (RI
or TI). In the TSC80SlCI, the standard serial I/O is
called SIOO.
Each interrupt source can be individually enabled or
disabled by setting or clearing a bit in the interrupt
enable register (IE SFR). All interrupts sources can also
be globally enabled or disabled by setting or clearing the
EA bit in IE register.
The SIO I (I2C) interrupt is generated by the SI flag in
the control register (S I CON SFR). This flag is set when
the status register (SISTA SFR) is loaded with a valid
status code.
MATRAMHS
Rev. D (14 Jan. 97)
II.7.11
TEMIC
TSC8051Cl
Semiconductors
IE: Interrupt Enable Register
MSB
ESI
EA
Sywool :'
.. '
.
'
LSB
SFRA8h
c.'
.,
..
.:
~q$itlQn
ETl
ESO
.. :
'.'
.. :.'.
. ... :
..•....
'
EX!
Nam~a"dFtructl~;'; . y
lEO
Enable external interrupt O.
ETO
IE. I
Enable timer 0 interrupt.
EXI
1E.2
Enable external interrupt 1.
ET!
1E.3
Enable timer 1 interrupt.
ESO
lEA
Enable SIOO (UART) interrupt.
ESI
IE.S
Enable SIO I (l2C) interrupt.
-
1E.6
(Reserved).
1E.7
Enahle all
EA
/
'
EXO
EXO
ETO
T.
.:
..
interrupt~.
6.8.2. Interrupt Priority Structure:
Each interrupt source can be assigned one of two priority
levels. Interrupt priority levels are defined by the
interrupt priority register (rp SFR). Setting a bit in the
interrupt priority register selects a high priority
interrupt, clearing it selects a low priority interrupt.
IP: Interrupt Priority Register
MSB
PSI
PSO
PT!
PXl
Position
PXO
IP.O
External interrupt 0 priority level.
PTO
IP.I
Timer 0 interrupt priority level.
PXI
lP.2
External interrupt 1 priority level.
PTI
IP.3
Timer 1 interrupt priority level.
PSO
IPA
SIOO (UART) interrupt priority level.
PSI
IP.5
SIOI (T2C) intel1llpt priority level.
-
IP.6
(Reserved).
-
IP.7
(Unused).
.
PTO
PXO
N!lI1W !lnd FUnction
Symbol
A low priority interrupt service routine may be
interrupted by a high priority interrupt. A high priority
interrupt service routine cannot be interrupted by any
other interrupt source.
11.7.12
LSB
SFR B8h
If two requests of different priority levels occur
simultaneously, the high priority level request is
serviced. If requests of same priority are received
simultaneously, an internal polling sequence determines
which request is serviced. Thus, within each priority
level, there is a second priority structure determined by
the polling sequence, as follows:
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
Order
Source
Priority Within Level
I
INTO
(highest)
2
Timer 0
l'
3
INTI
4
Timer 1
5
SIOO
1
6
SIal
(lowest)
6.8.3. Interrupt Handling:
The interrupt flags are sampled at S5P2 of every
machine cycle. The samples are polled during the
following machine cycle. If one of the flags was in a set
condition at S5P2 of the previous machine cycle, the
polliug cycle will find it and the interrupt system will
generate a LCALL to the appropriate service routine,
provided this hardware-generated LCALL is not
blocked by any of the following conditions:
1. An interrupt of higher or equal priority is
already in progress.
2. The current (polling) cycle is not the final
cycle in the execution of the instruction in progress.
The processor acknowledges an interrupt request by
executing a hardware-generated LCALL to the
appropriate service routine. In some cases it also clears
the flag that generated the interrupt, and in other case it
does not. It clears the timer 0, timer I, and external
interrupt flags. An external interrupt flag (IEO or IE I) is
cleared only if it was transition-activated. All other
interrupt flags are not cleared by hardware and must be
cleared by the software. The LCALL pushes the
contents of the program counter onto the stack (but it
does not save the PSW) and reloads the PC with an
address that depends on the source of the interrupt being
vectored to, as listed below:
3. The instruction in progress is RET! or any
access to the IE or IP SFR.
Any of these three conditions will block the generation
of the LCALL to the interrupt service routine. Note that
if an interrupt is active but not being responded to for one
of the above conditions, if the flag is not still active when
the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the facts that the
interrupt flag was once active but not serviced is not
memorized. Every polling cycle is new.
Source
Vector Address
lEO
0003h
TFO
OOOBh
lEI
OOl3h
TFI
OOIBh
RI+Tl
0023h
SI
002Bh
Execution proceeds from the vector address until the
RETI instruction is encountered. The RET! instruction
clears the 'priority level active' flip-flop that was set
when this interrupt was acknowledged. It then pops two
bytes from the the top of the stack and reloads the
program counter with them. Execution of the interrupted
program continues from where it was interrupted.
MATRAMHS
Rev. D (14 Jan. 97)
11.7.13
B
TEMIC
TSC8051Cl
Semiconductors
7. Peripherals Functional Description
For detailed functionnal description of standard 80C51
peripherals, please refer to C51 Family, Hardware
Description and Programmer's Guides.
The 4-bit timer is decremented every 't' seconds, where:
t = 12 x 131072 x lIfosc. (131.072ms at fosc = 12MHz).
Thus, the interval may vary from 131.072ms to
2097 .152ms in 16 possible steps (see Table 3. ).
7.1. Watchdog Timer
The watchdog timer has to be reloaded (write to HWDR
SFR) within periods that are shorter than the
programmed watchdog interval, otherwise the
watchdog timer will underflow and a system reset will
be generated which will reset the TSC8051 C 1.
The watchdog timer consists of a 4-bit timer with a
17-bit prescaler as shown in Figure 9. The prescaler is
fed with a signal whose frequency is 1112 the oscillator
frequency (lMHz with a 12MHz oscillator).
HWDR: Hardware WatchDog Register
SFRE6h
MSB
WTE
LSB
WT3
S~ol
......•.
...
WTO
Position
.,
.. '.
."
HWDR.O
..
'
WT2
WTI
WTO
•'. Nam~ andFu0
dfun
..':'
Watchdog Timer Interval bit O.
WTl
HWDR.I
Watchdog Timer Interval bit 1.
WT2
HWDR.2
Watchdog Timer Interval bit 2.
WT3
HWDR.3
Watchdog Timer Interval bit 3.
-
HWDRA
Reserved for test purpose, must remain to 0 for normal operation.
-
HWDR.5
(Reserved).
-
HWDR.6
(Reserved) .
HWDR.7
Watchdog Timer Enable bit. Setting this bit activates watchdog operation.
WTE
Table 3. Watchdog timer interval value format.
.wT3 ·. W'I'2
~rf
WTO
.lnt~rvaJ.·
0
tx 16
0
0
0
0
0
0
0
0
tx I
0
HWDR is a write only register. Its value after reset is OOh
which disables the watchdog operation.
HWDR is using TSC8051Cl Special Function Register
address, E6h.
fosc/12
tx 2
Internal
reset
tx 15
Once the watchdog timer enabled setting WTE bit, it
cannot be disabled anymore, except by a system reset.
Figure 9. Watchdog timer block diagram
The watchdog timer is frozen during idle or power down
mode.
11.7.14
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
7.2. Pulse Width Modulated Outputs
The TSC8051CI contains twelve pulse width
modulated output channels (see Figure 10. ). These
channels generate pulses of programmable duty cycle
with an 8-bit resolution.
The 8-bit counter counts modulo 256 by default i.e ..
from 0 to 255 inclusive but can count modulo 254 i.e ..
from 0 to 253 inclusive by programming the bit 0 of the
PWMCON register. The counter clock is supplied by the
oscillator frequency. Thus, the repetition frequency
fpwm is constant and equals to the oscillator frequency
divided by 256 or 254 (fpwm=46.875KHz or
47.244KHz with a 12MHz oscillator). The 8-bit counter
is common to all PWM channels. its value is compared
to the contents of the twelve registers: PWMO to
PWM II. Provided the content of each of these registers
is greater than the counter value, the corresponding
output is set low. If the contents of these registers are
equal to, or less than the counter value the output will be
high.
The pulse-width ratio is therefore defined by the
contents of these registers, and is in the range of 0 (all '0'
written to PWM register) to 255/256 or I (all' I ' written
to PWM register) and may be programmed in
increments of 1/256 or 1/254. When the 8-hit counter
counts modulo 254, it can never reach the value of the
PWM registers when they are loaded with FEh or FFh.
II
PWMx: Pulse Width Modulator x Register
LSB
MSB
D7
D6
D5
D4
When a compare register (PWMO to PWMII) is loaded
with a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. All the PWM outputs are
open-drain outputs with standard current drive and
standard maximum voltage capability. When they are
disabled, eight of them (PWMO to PWM7) are in high
impedance while the other four (PWM8 to PWMll) are
standard Port outputs with internal pullups.
D3
D2
Dl
DO
Table 4. PWM SFR register addresses
....
Channel
SFR. address
PWMO
ECh
PWMI
EDh
PWM2
EEh
PWM3
EFh
PWMO to PWMII are write only registers. Their value
after reset is OOh.
PWM4
F4h
PWM5
F5h
PWMO to PWMll are using TSC8051Cl Special
Function Registers addresses as detailed in Table 4.
PWM6
F6h
PWM7
F7h
PWMS
FCh
PWM9
FDh
PWMlO
FEh
PWMll
FFh
Two 8-bit control registers: MXCRO and MXCRI are
used to enable or disable PWM outputs.
MXCRO is used for PWMO to PWM7. MXCRI is used
for PWM8 to PWMll, these PWMs are multiplexed
with PORT 1 (see Table 5. )
MATRAMHS
Rev. D (14 Jan. 97)
II.7.15
TEMIC
TSC8051Cl
Semiconductors
MXCRO: PWM Multiplexed Control Register 0
'. cN. . . jnn
. •· • .·. ·~.~.c.d
. .··.~.·.lmu.:
. . ~o... ,i.··.. ·......
:
~ :~ " ~
"
PEx
MXCRO.x
,
PWMx Enable bit. Setting this bit enables PWMx output. Clearing this bit disables
PWMxoutput.
MXCRI: PWM Multiplexed Control Register I
MSB
LSB
SFRD7h
PEll
PElO
PE9
PES
synibol
PEx
MXCRl.x
PWMx+x Enable bit. Setting this bit enables PWMx output. Clearing this bit disables
PWMx output and activates the 1/0 pin (sec Table 5).
MXCRO and MXCRI are read/write registers. Their
value after reset is OOh which corresponds to all PWM
disabled.
PWM will not operate in idle and power down modes
(frozen counter). When idle or power down mode is
entered, the PWMO to PWM7 output pins are floating
and PWM8 to PWM I I pins are set to general purpose PI
port with the value of PI SFR.
MXCRO and MXCRI are using TSC8051CI Special
Function Register addresses, E7h and D7h respectively.
Table 5. PWM alternate pin.
PWM8
PLO
PWM9
Pl.l
PWMIO
P1.2
PWMll
P1.3
PWMCON is used to control the PWM counter.
PWMCON: PWM Control Register
MSB
SFRDFh
LSB
CMOD
CMOD
PWMCON.O
Counter modulo. Setting this bit sets the modulo to 254. Clearing this bit sets the
modulo to 256.
PWMCON is a write only register. Its value after reset
is OOh which sets the PWM counter modulo to 256.
PWMCON is using TSC8051Cl Special Function
Register address, DFh.
11.7.16
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
Note: when packaging P2,X is selected, PWMO to
PWM7 are not available. Please refer to ordering
information.
Internal
7.3. Controlled
Outputs
PWMX
HSYNC
and
VSYNC
SOCR is used to configure P3.3 and P3.5 pins as
buffered HSYNC and VSYNC outputs or as general
purpose I/Os. When either HSYNC or VSYNC is
selected, the output level can be respectively
programmed as P3.4 or P3.2 input level (inverted or
not), or as a low level if not enabled. Figure 12. shows
the programmable HSYNC and VSYNC output block
diagram.
Figure 10. Pulse width modulated outputs block
diagram
Figure II. shows a PWM programming example with
PWM register content 55h and counter modulo 256.
k-- 55h
f/,~~t
i.>
. ....
CR2
CRI
CRO
6MHz
0
0
0
0
0
1
0
1
0
1
I
0
....,....... '... ,...;, ... :;;J:::~':
...... c:v · -/""~
'.
ii:';,; '. .,. •. . ',:.;:,,;,.·.··l·::'··:~:·:
12MHz
rose divided by
23.5
47
256
27
53.5
224
0
31.25
62.5
192
I
37.5
75
160
0
6.25
12.5
960
I
0
1
50
100
120
1
1
0
100
-
60
1
I
I
0.25<62.5
0.5<62.5
Timer 1 overflow
96 x (256 - reload value)
value: 0-254 in mode 2
S I STA contains a status code which reflects the status
of SIOI and the I2C bus. The three least significant bits
are always zero. The five most significant bits contains
the status code. There are 12 possible status code. When
SISTA contains F8h, no relevant state information is
available and no serial interrupt is requested. A valid
status code is available in SISTA one machine cycle
after SI is set by hardware and is still present one
machine cycle after SI has been reset by software.
Table 7. to Table 9. give the status for the operating
modes and miscellaneous states.
SISTA: Synchronous Serial Status Register
MSB
SFRD9h
SC4
SC3
SC2
SCI
o
SCO
SISTA.3
Status Code bit O.
SCI
SISTA.4
Status Code bit I.
SC2
SISTA.5
Status Code bit 2.
SC3
SISTA.6
Status Code bit 3.
SC4
SISTA.7
S 1STA is a read only register. Its value after reset is F8h.
11.7.20
LSB
SCO
o
o
Status Code bit 4.
SlSTA is using TSC8051CI Special Function Register
address, D9h.
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
Table 7. Status for master transmitter mode .
Table 9. Status for miscellaneous states
.. •. . Status. ot12c bus ·a.nd SIOlhardware
Status\:ode
08h
A START condition has been transmitted.
OOh
Bus error.
IOh
A repeated START condition has been
transmitted
F8h
No relevant state information available.
18h
SLA+W has been transmitted; ACK has been
S I DAT contains a byte of serial data to be transmitted or
a byte which has just been received. It is addressable
while it is not in process of shifting a byte. This occurs
when SIOI is in a defined state and the serial interrupt
flag is set. Data in S I DAT remains stable as long as SI
is set. While data is being shifted out, data on the bus is
simultaneously shifted in; SIDAT always contains the
last byte present on the bus.
received.
SLA+ W has been transmitted; NOT ACK has
20h
been received.
28h
Data byte has been transmitted; ACK has been
received.
30h
Data byte has been transmitted; NOT ACK has
been received.
38h
Arbitration lost in SLA+R/W or data bytes.
Table 8. Status for master receiver mode
. ··.Uti·.()U2Cbu~.;ln~$~Ol~ar-<
ADDRESS
OR SFR-P2
TWLWH
T
/
~TQVWX
AO-A7
T\VHQX~
TQVWH
I.--TLLA'::::!i
DATA OUT
i
TAVWL
)<
ADDRESS AS-A 15 OR SFR P2
8.8. External Data Memory Read Cycle
TWHLH~
I+------TLLDV-------.J
ALE
!
TLLWL-__*------+TRLRH------~
PORTO
TRLAZ
PORT 2
ADDRESS
OR SFR-P2
8.9. Serial Port Timing-Shift Register Mode
TXLXL
Serial port clock cycle time
TQVHX
TXHQX
12TCLCL
ns
Output data set-up to clock rising edge
I OTCLCL-I 33
ns
Output data hold after clock rising edge
2TCLCL-1l7
ns
TXHDX
Input data hold after clock rising edge
TXHDV
Clock rising edge to input data valid
1I.7.26
0
ns
IOTCLCL-133
ns
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
8.10. Shift Register Timing Waveforms
4
INSTRUCTION
ALE
CLOCK
OUTPlITDATA
+
WRITE to SBUF
INPUT DATA
+
CLEARRI
8.11. SIOI (I2C) Interface Timing
I···.\ 14 TCLCL
> 4.0fts
Tww
SCL low time
;> 16 TCLCL
> 4.7fts (Ii
THIGH
SCL high time
;> 14 TCLCl.
> 4.0fts
TRC
SCL rise time
,; I fts
Tec
SCL rail time
,; O.3fts
Tsu.DATI
Data set-up time
;> 250ns
III
(I)
_ (2)
< O.3fts
(3)
> 20 TCLCL - TRD
> Ifts
Tsu.DAT2
SDA set-up time (before repeated START condition)
;> 250ns
Tsu, DAT3
SDA set-up time (before STOP condition)
;> 250ns
> 8 TeLCL
THD,DAT
Data hold time
:?: Ons
> 8 TCLCL - Tec
(I)
Tsu; STA
Repeated START set-up time
;> 14 TCLCL
>4.7fts
(I)
TS(J, STO
STOP condition set-up time
;> 14 TCLCL
> 4.0fts
(I)
TBU!'
Bus free time
;> 14 TeLeL
>4.7fts
(I)
TRD
SDA rise time
,; Ifts
TFD
SDA rail time
,; O.3fts
_(2)
< O.3fts
(3)
Notes:
1. At 100 kbitls. At other bit-rates this value is inversely proportional
to the bit-rate of lOa kbitls.
2. Determined by the external bus-line capacitance and the external
bus-line pull-up resistor, this must be < l~s.
MATRAMHS
Rev. D (14 Jan. 97)
3. Spikes on the SDA and SCL lines with a duration of less than 3
TCLCL will be filtered out. Maximum capacitance on bus-lines
SDA and SCL = 400pF.
II.7.27
TEMIC
TSC8051Cl
Semiconductors
8.12. SI01 (12C) Timing Waveforms
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
8.13. External Clock Drive Characteristics (XTAL1)
Synibol
,.
Para).'lleter
TCLCL
Oscillator Period
TCHCX
' Max·
Min
Units
83,3
ns
High Time
5
os
TeLCX
Low Time
5
TCLCH
Rise Time
5
os
TCHCL
Fall Time
5
os
ns
8.14. External Clock Drive Waveforms
VCC-~O'5V
.,.,. ..
O.7Vcc
OA5V
-
O,2V cc-D, 1
LTCHCX
TCI-ICL
~TCLCX
~TCLCI-l
_ _ _ _ _ TCLCL _ _ _ _ _ _~
1oII~1--
8.15. AC Testing Input/Output Waveforms
Vee -0.5 V
INPUT/OUTPUT
OA5 V
X~O_'2_VC_C_+O_'9
0.2 Vee-O.l
>C-
______
--~
AC inputs during testing are driven at Vee - 0.5 for a
logic "1" and 0.45V for a logic "0". Timing
measurement are made at VIH min for a logic "1" and
VIL max for a logic "0".
II.7.28
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
8.16. Float Waveforms
FLOAT
1 + - - - - - FLOAT
VOH - 0.1 V
VLOAO
.VOL+O.I V
I -V-L-O-A-O-+-O.I V
.VLOAO-O.I V
For timing purposes as port pin is no longer floating
when a 100 mV change from load volt~ge occurs and
begins to float when a 100 mV change from the loaded
VOHIVOL level occurs. IOLIIOH ;,. ± 20mA.
MATRAMHS
Rev. D (14 Jan. 97)
B
II.7.29
TEMIC
TSC8051Cl
Semiconductors
8.17. Clock Waveform
INTERNAL
CLOCK
STATE4
STATE5
STATE6
STATE I
STATE2
STATE3
STATE4
STATES
PI
PI
PI
PI
PI
PI
PI
PI
I P2
I P2
I P2
I P2
I P2
I P2
I P2
I P2
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
PO
P2 (EXT)
INDICATES ADDRESS TRANSITIONS
REAP CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OOH IS EMITTED
r-;===."".;D;;;U:..:R::;ING THIS PERIOD
PO
DPL OR Rt OUT
i
I
1~-+-~----------------~S~MPL.g~Drr-----------~
fi5A'i'Al
\4.......I'-r~*I.._ _ _ _ _ FLOAT
~I
•
L
INDICATES DPH OR P2 SFR TO PCH TRANSlTlON
P2
WRITE CYCLE
WR
PO
DPL OR Rt OUT
I--------------DATA OUT
ioIl
..
INDICATES DPH OR P2 SFR TO PCH TRANSlTlON
P2
PORT OPERATION
MOVPORTSRC
OLD DATA
I NEW DATA
__________.....I~INS SAMPLED
I+L+I
MOV DEST _PO
MOV DEST P_O_R_T_(_P_I._P_2._P_3)______--'~P2, P3 PINS SAMPLED
I+L+I
(INCLUDES INTO. INTI. TO TI)
SERIAL PORT SHIFT CLOCK
~
______________~___
RX~DSAMPLED
TXD (MODE_0)
_
This diagram indicates when signals are clocked
internally. The time it takes the signals to propagate to
the pins, however, ranges from 25 to 125ns. This
propagation delay is dependent on variables such as
temperature and pin loading, Propagation also varies
11.7.30
PO PINS SAMPLEQL-______
PI, P2, P3 PINS SAMPLE~
"O"M'~
from output to output and component. Typically though
(TA=25°C fully loaded) RD and WR propagation delays
are approximately 50ns, The other signals are typically
85ns. Propagation delays are incorporated in the AC
specifications.
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
TSC8051Cl
Semiconductors
9. Ordering Information
12
xxx
StCt
TSC
-A
T
t6
C
T
Part Number
8051 C 1: Romless version
5ICI: 8Kx8 Mask ROM
-12: 12 MHz version
-16: 16 MHz version
Bounding Option
-none: 12 PWM
-A : 4 PWM & P2x
Customer Rom Code
TEMIC Semiconductor
Microcontroller Product Line
...... ··ParfN~mbel'
......
... .....
••••••
... .
...
R
T
Packaging
A: PDIL40
B: PLCC44
C: PQFP44
D: SSOP44
E: PLCC 52
G: CDIL40
H: LCC44
I: CQPJ 44
Temperature Range
C : Commercial 0 0 to 70°C
I : Industrial -40° to 85°C
Examples
I···.··.··..• ·
B
B
Conditioning
R : Tape & Reel
D: Dry Pack
B : Tape & Reel
and Dry Pack
Description
•
•••
....
TSC5IClXXX-12CA
Mask ROM XXX, 12 MHz, POlL 40, 0 to 70°C
TSC8051CI-16CER
ROMless, 16 MHz, PLCC 52, 0 to 70°C, Tape and Reel
ANM059
Application Note: "How to recognize video mode and generate free running
synchronization signals using TSC805J Cl/C2 Microcontroller"
IM-80C5J-RB-400-40
Emulator Base
PC-TSC805ICI-RB-16
Probe card for TSC8051 C I. These products are released by Metalink. Please consult the
local tools distributor or your sales office.
Product Marking:
TEMIC
Customer PIN
Temic PIN
© Intel 80, 82
YYWW Lot Number
MATRAMHS
Rev. D (14 Jan. 97)
II.7.31
TEMIC
TSC8051C2
Semiconductors
8-Bit Microcontroller for Digital Computer Monitors
1. Introduction
The TSC8051 C2 is a stand-alone high performance
CMOS 8-bit embedded microcontroller and is designed
for use in CRT monitors. It is also suitable for automotive
and industrial applications.
In addition, the TSC8051 C2 has 2 software selectable
modes of reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the RAM, the timers, the serial ports, and the intermpt
The TSC8051 C2 includes the fully static 8-bit "80C51" system continue to function. In the power down mode the
CPU core with 256 bytes of RAM; 4 Kbytes of ROM; two RAM is saved and all other functions are inoperative.
l6-bit timers; 12 PWM Channels; a 5 sources and 2-level The TSC8051 C2 enables the users reducing a lot of
intermpt controller; a full duplex serial port; a watchdog external discrete components while bringing the
timer; power voltage monitor and on-chip oscillator.
maximum of flexibility.
2. Features
•
Boolean processor
•
Fully static design
•
4K bytes of ROM
•
256 bytes of RAM
•
2 x 16-bit timer/counter
•
Programmable serial port
•
•
•
2 power saving control modes:
•
•
Idle mode
Power-down mode
•
SYNC Processor
• Controlled HSYNC & VSYNC outputs
• Controlled HSYNC & VSYNC inputs
• Clamp pulse output
5 intermpt sources:
• External intcrmpts (2)
•
Up to 12 programmable PWM channds with 8-bit
resolution
•
Timers interrupt (2)
•
•
Serial port intermpt
Up to 32 programmable I/O lines depending on the
package
•
40 pins DIP, 44 pins PQFP, 44 and 52 pins PLCC
packages
•
Commercial and industrial temperature rangcs
•
Operating Frequency: 12 MHz to 16 MHz
Watchdog reset
•
Power Fail reset
•
On chip oscillator for crystal or ceramic resonator
MATRAMHS
Rev. A (10 Jan. 97)
11.8.1
Preview
TEMIC
TSC8051C2
Semiconductors
3. Block Diagram
TI
TO INTO
~
----_ ..
-
... _._--
~
TWO I6--BIT
TIMER/EVENT
COUNTER
~
~
~
, ;.
~
~
:
[~L.
:
<
AS-IS
80C51 CORE L
EXCLUDING
ROM/RAM
.L ..... 1. .....
.
, 7'
L
,.
,
;.
L
v
PARALLEL 110
PORTS AND
EXTERNAL BUS
SERIAL
UART
PORT
,
DATA
MEMORY
256x 8 RAM
:
:
<
:
:
L
,.
7'
~
,
7'
POWER
VOLTAGE
MONITOR
~~ : ~ :~ i'j~
PO
PI
P2
~
TxD
~ ALTERNATE FUNCTION OF PORTO
[Q ALTERNATE FUNCTION OF PORT I
~~
.... .. _.- -_ ....
SPECIAL
EXTERNAL
INPUTS
:..
".
WATCHDOG
TIMER
-----
CPO
I.~
I
:
".
, 7'
... ...
I:
PROGRAM
MEMORY
4k x 8 ROM
CPU
VSS
8-BIT INTERNAL BUS
~-~
:
~
TO
~
~
VCC
RxD
L
,.
CLAMP
PULSE
L
,.
~
, 7'
12 x 8-bit PWM
CHANNELS
CONTROLLED
HSYNC & VSYNC
OUTPUTS
........ (Ii... l'l l'l l'lli'j
PWMO
PWM8
PWM7
PWMII
VSYNC
HSYNC
VOUT
HOUT
o
ALTERNATE FUNCTION OF PORT2
~ ALTERNATE FUNCTION OF PORT3
Figure 1. TSC8051C2 block diagram.
MATRAMHS
11.8.2
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
4. Pin Configurations
u
- 0''''''
0 ~ ~~ ~
(,,!
~~
"" ::: :::::: :::
PI.OIPWM8
VCC
PI.I/PWM9
PO.O/ADO
P1.2/PWMIO
PO.I/ADI
PI.3/PWMII
PO.2/AD2
":
~
~-:
~
0:: 0:: 0:0: 0::
INDEX
CORNER
U 0
u u
Z
>
0
N
ci ci '"
ci
"" "" "" ""
PI,4/CPO
PO.3/ADJ
PI.S
PI.S
P0,4/AD4
PI.6
POS
Pl.6
PO.S/ADS
PI.7
PO.6
PI.7
PO.6/AD6
RST
EA
P3.lrrXD
ALE
P3.2/INTO/VSYNC
PO.7
RST
PO.7/AD7
P3.0/RXD
PDA
EA
PJ.O/RXD
NC
NC
PLCC44
P3.I/TXD
PSEN
P3.3/INT l/VOUT
PWM7"
P3.4/TO/HSYNC
PWM6*
P3.S/TI/HOUT
PWM5
P3.6/WR
PWM4
P3.7/RD
PWMJ
XTAL2
PWM2
XTALI
PWM1"
VSS
PWMO"
ALE
P3.2/1NTO/VSYNC
PWM7"
PWM6"
~.
PWM5*
ii
Cii
Cij'
Cia
PSEN
29'
PWMS'"
~Jl,8~~LrLTLfCJ~~rLrLf>i~~
PWM7'"
PWM6'
*PWMx or P2.x depending on option (see ordering information)
0
0
INDEX
CORNER
u
Z
~
'"
00
~ ~ ~
::: :::
"" :::e: ::: S
~
~ ~
'"
0:: 0:: 0:: 0:: 0::
u
u u
Z
>
C
ci ci
N
cr,
"" "" "" "" ""
7:.6 ' S : 4 3 : 2 I ' 5 ? 'SiSQ494&
NC
.".
ci ci ci
e·,
PI.S
PI.6
P1.7
~7
,:4'
PO.5
,:4'
PO.6
,'4'
,:4'
EA
PO.7
ALE
RST
PSEN
P3.0/RXD
PLCC 52
'J.'
P2.7
P3.2/INTO/vSYNC
,j'
PWM7
P3.3/INT I /VOUT
,j'
P2.6
P3,4/TO/HSYNC
''.f
PWM6
P3.5/T I /HOUT
,j'
P2.S
NC
,j'
PWMS
P3.IITXD
PWM4
P3.6/WR
Figure 2. TSC8051C2 pin configurations.
11.8.3
MATRAMHS
Rev. A (10 Jan. 97)
Preview
B
TEMIC
TSC8051C2
Semiconductors
s. Pin Description
VSS
PORT 2 (P2.0-P2.7)
Circuit ground.
Port 2 is an 8-bit bidirectional 110 port with internal
pullups. Port 2 pins that have I's written to them are
pulled high by the internal pull ups, and in that state can
be used as inputs. As inputs, Port 2 pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pull ups.
vee
Power supply voltage.
RST
A high level on this pin for two machine cycles while the
oscillator is running resets the device. An internal
pull down resistor permits power-on reset using only a
capacitor connected to VCe.
Port 2 emits the high-order 8-bit address during fetches
from external Program Memory and during accesses to
external Data Memory that use 16-bit addresses. In this
application it uses strong internal pull-up when emitting
I's.
Port 2 can sink and source 3 LS TTL loads.
PORT 0 (PO.O-PO.7)
Port 0 is an 8-bit open-drain bidirectional VO port. Port
opins that have I 's written to them float, and in that state
can be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data
bus during access to external Program and Data memory.
In this application it uses strong internal pull-up when
emitting l's.
Port 0 can sink and source 8 LS TTL loads.
PORT 3 (P3.0-P3.7)
Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have I's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 3 pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pullups.
Each line on this port has 2 or 3 functions either a general
110 or special control signal, as listed below:
PORT 1 (P1.0-P1.7)
Port 1 is an 8-bit bidirectional 1/0 port with internal
pUllups. Port 1 pins that have 1's written to them are
pulled high by the internal pullups, and in that state can
be used as inputs. As inputs, Port 1 pins that are
externally being pulled low will source current (IlL on
the data-sheet) because of the internal pullups.
Port 1 also serves 4 programmable PWM open drain
outputs and programmable open drain CPO, as listed
below:
Pl.O
PWM8: Pulse Width Modulation output 8.
Pl.l
PWM9: Pulse Width Modulation output 9.
Pl.2
PWMlO: Pulse Width Modulation output 10.
PI.3
PWM II: Pulse Width Modulation output II.
PI.4
CPO: Clamp Pulse Output.
Port 1 can sink and source 3 LS TTL loads.
P3.1
TXD: serial output port.
P3.2
INTO: external interrupt O.
VSYNC: vertical synchro input.
P3.3
INTI: external interrupt l.
VOUT: buffered V-SYNC output.
P3.4
TO: Timer 0 external input.
HSYNC: horizontal syncbro input.
P3.5
Tl: Timer 1 external input.
HOUT: buffered H-SYNC output.
P3.6
WR: external data memory write strobe.
P3.7
RD: external data memory read strobe.
Port 3 can sink and source 3 LS TTL loads.
PWM0-7
These eight Pulse Width Modulation outputs are true
open drain outputs and are floating after reset.
11.8.4
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
ALE
The Address Latch Enable output signal occurs twice
each machine cycle except during external data memory
access. The negati ve edge of ALE strobes the address
into external data memory or program memory. ALE
can sink and source 8 LS TTL loads.
The Program Store Enable output signal remains high
during internal program memory. An active low output
occurs during an external program memory fetch. PSEN
can sink and source 8 LS TTL loads.
If desired, ALE operation can be disabled by setting bit
o of SFR location AFh (MSCON). With the bit set, ALE
is active only during MOVX instruction and external
fetches. Otherwise the pin is pulled low.
XTALl
Input to the inverting oscillator amplifier and input to the
external clock generator circuits.
XTAL2
When the External Access input is held high, the CPU
executes out of internal program memory (unless the
Program Counter exceeds lFFFh). When EA is held low
the CPU executes only out of external program memory.
must not be left floating.
Output from the inverting oscillator amplifier. This pin
should be non-connected when external clock is used.
1I.8.5
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
6. Basic Functional Description
~1
6.1. Idle And Power Down Operation
Figure 3 shows the internal Idle and Power Down clock
configuration. As illustrated, Power Down operation
stops the oscillator. Idle mode operation allows the
interrupt, serial port, and timer blocks to continue to
operate while the clock to the CPU is gated off.
XTAL2
XTALI
H----
These special modes are activated by software via the
Special Function Register, its hardware address is 87h.
PCON is not bit addressable.
INTERRUPT
SERIAL PORT
TIMER BLOCKS
CPU
Figure 3. Idle and Power Down Hardware.
PCON: Power Control Register
SFR87h
MSB
SMOD
PFRE
LSB
GFl
GFO
PD
IDL
IDL
PCON.a
PD
PCON.l
Power Down bit. Setting this bit activates power down operation.
GFO
PCON.2
General-purpose Hag bit.
GFl
PCON.3
General-purpose flag bit.
PFRE
PCONA
Power Fail Reset Enable bit. Setting this bit enables the power voltage monitor. The
only way to clear this bit is to apply an external reset.
PCON.5
(Reserved).
PCON.6
(Reserved).
PCON.7
Double Baud rate bit. Setting this bit causes the baud rate to double when the serial port
is being used in either modes 1, 2 or 3.
SMOD
Idle mode bit. Setting this bit activates idle mode operation.
If l's are written to PD and IDL at the same time, PD takes precedence. The reset value of PCON is OXXO OOOOb.
6.1.1. Idle Mode
The instruction that sets PCON.O is the last instruction
executed before the Idle mode is activated. Once in the
Idle mode the CPU status is preserved in its entirety: the
Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM, and all other register maintain their
data during Idle Table I describes the status of the
external pins during Idle mode.
There are two ways to terminate the Idle mode.
Activation of any enabled interrupt will cause PCON.O
to be cleared by hardware terminating Idle mode. The
interrupt is serviced, and following RET!, the next
instruction to be executed will be the one following the
instruction that wrote I to PCON.O.
The t1ag bits GFO and GFI may be used to determine
whether the interrupt was received during normal
execution or during the Idle mode. For example, the
instruction that writes to PCON.O can also set or clear
one or both t1ag bits. When Idle mode is terminated by
an enabled interrupt, the service routine can examine the
status of the flag bits.
The second way of
hardware reset. Since
hardware reset needs
cycles (24 oscillator
operation.
II.S.6
terminating the Idle is with a
the oscillator is still running, the
to be active for only 2 machine
periods) to complete the reset
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
6.1.2. Power Down Mode
The instruction that sets PCON.I is the last executed
prior to entering power down. Once in power down. the
oscillator is stopped. The contents of the onchip RAM
and the Special Function Register are saved during
power down mode. A hardware reset is the only way of
exiting the power down mode. The hardware reset
initiates the Special Function Register. In the Power
Down mode, VCC may be lowered to minimize circuit
power consumption. Care must be taken to ensure the
voltage is not reduced until the power down mode is
entered, and that the voltage is restored before the
hardware reset is applied which frees the oscillator.
Reset should not be released until the oscillator has
restarted and stabilized. Table I describes the status of
the external pins while in the power down mode. It
should be noted that if the power down mode is activated
while in external program memory, the port data that is
held in the Special Function Register P2 is restored to
Port 2. If the data is a I, the port pin is held high during
the power down mode by the strong pullup transistor.
•
Table 1. Status of the external pins during Idle and Power Down modes.
Idle
Internal
Port Data
Port Data
Port Data
Port Data
Floating
Idle
External
Floating
Port Data
Address
Port Data
Floating
Power Down
Internal
o
o
Port Data
Port Data
Port Data
Port Data
Floating
Power Down
External
o
o
Floating
Port Data
Port Data
Port Data
Floating
6.2. Stop Clock Mode
6.4. 110 Configurations
Due to static design, the TSC8051 C2 clock speed can be
reduced down to 0 MHz without any data loss in memory
or register. This mode allows step by step code
execution, and permits to reduce system power
consumption by bringing the clock frequency down to
any value. When the clock is stopped, the power
consumption is the same as in the Power Down Mode.
Figure 4. shows a functional diagram of the generic bit
latch and I/O buffer in each of the four ports. The bit
latch, (one bit in the port SFR) is represented as a D type
flip-flop. A 'write to latch' signal from the CPU latches
a bit from the internal bus and a 'read latch' signal from
the CPU places the Q output of the flip-flop on the
internal bus. A 'read pin' signal from the CPU places the
actual pin logical level on the internal bus.
Some instructions that read a port read the actual pin,
and other instructions read the latch (SFR).
6.3. 110 Ports Structure
The TSC8051C2 has four 8-bit ports. Each port consist
of a latch (special function register PO to P3), an input
buffer and an output driver. These ports are the same as
in 80C51, with the exception of the additional functions
of port 1 and port 3 (see Pin Description section).
II.8.7
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
ADDR/DATA
Semiconductors
VCC
PWMX
INT.
BUS
INT.
BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
VCC
I PORT I BIT
I PORT 0 BIT
* Internal pull-up not present on P 1.0 to P 1.4 when PWM8 to PWM [ I
and CPO are enabled
ADDR
CONTROL
ALTERNATE
OUTPUT
FUNCTION
VCC
INT.
BUS
INT.
BUS
WRITE
TO
LATCH
WRITE
TO
LATCH
VCC
IPORT 2 BIT
I PORT 3 BIT
Figure 4. Port Bit Latches and I/O buffers
6.5. Reset Circuitry
The reset circuitry for the TSC8051 C2 is connected to
the reset pin RST. A Schmitt trigger is used at the input
for noise rejection (see Figure 5. ).
A reset is accomplished by holding the RST pin high for
at least two machine cycles (24 oscillator periods) while
the oscillator is running. The CPU responds by
executing an internal reset. It also configures the ALE
and PSEN pins as inputs (they are quasi-bidirectional).
A Watchdog timer underflow or a power Fail condition
if enabled, will force a reset condition to the
TSC8051C2 by an internal connection.
The internal reset is executed during the second cycle in
which reset is high and is repeated every cycle until RST
goes low. It leaves the internal registers as follows:
11.8.8
ACC
OOh
B
OOh
DPTR
OOOOh
EICON
OOh
HWDR
OOh
IE
OXXO OOOOb
IP
XXXO OOOOb
MSCON
XXXXXXXOb
MXCRO-l
OOh
PO-P3
FFh
PC
OOOOh
PCON
OXXO OOOOh
PSW
OOh
PWMO-ll
DOh
PWMCON
XXXXXXXOh
SBUF
DOh
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
Rl!gister
Content
SCON
OOh
SOCR
OOh
SP
07h
TCON
OOh
THO, THI
OOh
TLO. TLI
()Oh
TMOD
OOh
6.6. Oscillator Characteristics
XTAL I and XTAL2 are respectively the input and
output of an inverting amplifier which is configured for
usc as an on-chip oscillator. As shown in Figure 7. ,
either a quartz crystal or ceramic resonator may he used.
To drive the device from an external clock source,
XTALl should he driven while XTAL2 is left
unconnected as shown in Figure 8.
The internal RAM is not affected by reset. At power-on
reset, the RAM content is indeterminate.
There are no requirements on the duty cycle of the
external clock signal, since the input to the internal
clocking circuitry is through a divide-hy-two t1ip-t1op.
The minimum high and low times specified on the data
sheet must be observed however.
XTAL2
XTALI
RST_o__---l
On-chip
resi~tor
1 - - - - - - - - - - 1 vss
RRST
Watchdog
Reset
Figure 7. Crystal Oscillator
L._ _ _ Power Fail
Reset
-----1
XTAL2
--------l
XTALi
NC
EXTERNAL
OSCILLATOR
SIGNAL
Figure 5. On-Chip Reset Configuration.
~"--------1 vss
An automatic reset can be obtained when VCC is turned
on by connecting the RST pin to VCC through a I~F
capacitor providing the VCC setting time does not
exceed I ms and the oscillator start-up time does not
exceed IOms. This power-on reset circuit is shown in
Figure 6. When power comes on, the current drawn by
RST starts to charge the capacitor. The voltage at RST
is the difference between VCC and the capacitor
voltage, and decreases from VCC as the capacitor
charges. VRST must remain above the lower threshold of
the Schmitt trigger long enough to effect a complete
reset. The time required is the oscillator start-up time,
plus 2 machine cycles.
VCC_-+_ _ _ _~
Figure 6. Power-on Reset Circuit
Figure 8. External Drive Configuration
6.7. Memory organization
The memory organisation of the TSC8051C2 is the same
as in the 80C51, with the exception that the TSC8051 C2
has 4k bytes ROM, 256 bytes RAM, and additional
SFRs. Details of the differences are given in the
following paragraphs.
In the TSC8051 C2, the lowest 4k of the 64k program
memory address space is filled by internal ROM.
Depending on the package used, external access is
available or not. By tying the EA pin high, the processor
fetches instructions from internal program ROM. Bus
expansion for accessing program memory from 4k
upward is automatic since external instruction fetches
occur automatically when the program counter exceeds
IFFFh. If the EA pin is tied low, all program memory
fetches are from external memory. The execution speed
is the same regardless of whether fetches are from
external or internal program memory. If all storage is
on-chip, then byte location OFFFh should be left vacant
to prevent an undesired pre-fetch from external program
memory address IOOOh.
11.8.9
MATRAMHS
Rev. A (10 Jan, 97)
Preview
I
TEMIC
TSC8051C2
Semiconductors
Certain locations in program memory are reserved for
specific purposes. Locations OOOOh to 0002h are
reserved for the initialisation program. Following reset,
the CPU always begins execution at location OOOOh.
Locations 0003h to 002Ah are reserved for the five
interrupt request service routines.
The internal data memory space is divided into a
256-bytes internal RAM address space and a 128 bytes
special function register address space.
The internal data RAM address space is 0 to FFh. Four
8-bit register banks occupy locations 0 to lFh. 128 bit
locations of the internal data RAM are accessible
through direct addressing. These bits reside in 16 bytes
of internal RAM at location 20h to 2Fh. The stack can
be located anywhere in the internal data RAM address
space by loading the 8-bit stack pointer (SP SFR).
The SFR address space is 100h to IFFh. All registers
except the program counter and the four 8-bit register
banks reside in this address space. Memory mapping of
the SFRs allows them to be accessed as easily as internal
RAM, and as such, they can be operated on by most
instructions.The mapping in the SFR address space of
the 40 SFRs is shown in Table 2. The SFR names in
italic are TSC8051C2 new SFRs and are described in
Peripherals Functional Description section. The SFR
names in bold are bit addressable.
Table 2. Mapping of Special Function Register
1·····.·.·• Jl:8/·.
......·E;O .•.
ACC
PWMO
PWMJ
PWM2
EfCON
SOCR
HWDR
PWM3
MXCRO
PWMCON
psw
MXCRJ
.i 2 machine
cycles
Figure 11. Power Fail Reset timing diagram
7.3. Pulse Width Modulated Outputs
The TSC8051C2 contains twelve pulse width
modulated output channels (see Figure 10. ). These
channels generate pulses of programmable duty cycle
with an 8-bit resolution.
1I.8.14
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
The 8-bit counter counts modulo 256 by default i.e.,
from 0 to 255 inclusive but can count modulo 254 i.e.,
from 0 to 253 inclusive by programming the bit 0 of the
PWMCON register. The counter clock is supplied by the
oscillator frequency. Thus, the repetition frequency
fpwm is constant and equals to the oscillator frequency
divided by 256 or 254 (fpwm=46.875KHz or
47.244KHz with a 12MHz oscillator). The 8-bit counter
is common to all PWM channels, its value is compared
to the contents of the twelve registers: PWMO to
PWMII. Provided the content of each of these registers
is greater than the counter value, the corresponding
output is set low. If the contents of these registers are
equal to, or less than the counter value the output will be
high.
The pulse-width ratio is therefore defined by the
contents of these registers, and is in the range of 0 (all '0'
written to PWM register) to 255/256 or I (all' I' written
to PWM register) and may be programmed in
increments of 11256 or 1/254. When the 8-bit counter
counts modulo 254, it can never reach the value of the
PWM registers when they are loaded with FEh or FFh.
B
PWMx: Pulse Width Modulator x Register
MSB
D7
LSB
D6
D5
D4
When a compare register (PWMO to PWM II) is loaded
with a new value, the associated output is updated
immediately. It does not have to wait until the end of the
current counter period. All the PWM outputs are
open-drain outputs with standard current drive and
standard maximum voltage capability. When they are
disabled, eight of them (PWMO to PWM7) are in high
impedance while the other four (PWM8 to PWMll) are
standard Port outputs with internal pullups.
D3
D2
Dl
DO
Two 8-bit control registers: MXCRO and MXCR I are
used to enable or disable PWM outputs.
MXCRO is used for PWMO to PWM7. MXCRI is used
for PWM8 to PWM II, these PWMs are multiplexed
with PORT I (see Table 5. )
PWMO to PWMII are write only registers. Their value
after reset is OOh.
PWMO to PWMll are using TSC8051C2 Special
Function Registers addresses as detailed in Table 4.
Table 4. PWM SFR register addresses
Cham'lel.,
SFRaddress
PWMO
ECh
PWMI
EDh
PWM2
EEh
PWM3
EFh
PWM4
F4h
PWM5
F5h
PWM6
F6h
PWM7
F7h
PWM8
FCh
PWM9
FDh
PWMIO
FEh
PWMII
FFh
MATRAMHS
Rev. A (10 Jan. 97)
II.S.15
Preview
TEMIC
TSC8051C2
Semiconductors
MXCRO: PWM Multiplexed Control Register 0
MSB
..
Symbol
PEx
Na~e
position
MXCRO.x
and Function·.
PWMx Enable bit. Setting this bit enables PWMx output. Clearing this bit disables
PWMx output.
MXCRI: PWM Multiplexed Control Register 1
MSB
SFRD7h
LSB
PEll
PElO
PE9
PE8
Symbol
Position
Name aq.d Function
PEx
MXCRI.x
PWMx+8 Enable bit. Setting this bit enables PWMx output. Clearing this bit disables
PWMx output and activates the 110 pin (see Table 5).
MXCRO and MXCR I are read/write registers. Their
value after reset is OOh whieh corresponds to all PWM
disabled.
Table 5. PWM alternate pin.
PWM will not operate in idle and power down modes
(frozen counter). When idle or power down mode is
entered, the PWMO to PWM7 output pins are floating
and PWM8 to PWMll pins are set to general purpose PI
port with the value of PI SFR.
MXCRO and MXCRI are using TSC8051C2 Special
Function Register addresses, E7h and D7h respectively.
Channel
Pin assignll1Cnt
PWM8
Pl.O
PWM9
Pl.I
PWMIO
PI.2
PWMll
P1.3
PWMCON is used to control the PWM counter.
PWMCON: PWM Control Register
MSB
LSB
SFRDFh
CMOD
Symbill
CMOD
..
....
PWMCON.O
...
Counter modulo. Setting this bit sets the modulo to 254. Clearing this bit sets the
modulo to 256.
PWMCON is a write only register. Its value after reset
is OOh which sets the PWM counter modulo to 256.
PWMCON is using TSC8051C2 Special Function
Register address, DFh.
11.8.16
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
Figure 13. shows a PWM programming example with
PWM register content 55h and counter modulo 256.
{j
Internal
SSh
PWMX
-~------11L --
~ABh=1
Figure 13. PWM programming example.
Note: when packaging P2.x is selected, PWMO to
PWM7 are not available. Please refer to ordering
information.
Figure 12. Pulse width modulated outputs block
diagram
7.4. SYNC Processor
7.4.1. HSYNC and VSYNC Outputs
SOCR is used to configure P3.3 and P3.5 pins as
buffered HSYNC and VSYNC outputs or as general
purpose IIOs. When either HSYNC or VSYNC is
selected, the output level can be respectively
programmed as P3.4 or P3.2 input level (inverted or
not), or as a low level if not enabled. Figure 14. shows
the programmable HSYNC and VSYNC output block
diagram.
SOCR: Syncbronisation Output Control Register.
LSB
SFRESh
MSB
VOS
Syinbol
Position
HOE
SOCR.O
HOS
VOP
VOE
HOP
HOE
Name and Function
HSYNC Output Enable bit. Setting this bit enables the HSYNC signal.
HOP
SOCR.1
HSYNC Output Polarity bit. Setting this bit inverts the HSYNC output.
VOE
SOCR.2
VSYNC Output Enable bit. Setting this bit enables the VSYNC signal.
VOP
SOCR.3
VSYNC Output Polarity bit. Setting this bit inverts the VSYNC output.
HOS
SOCR.4
HSYNC Output Selection bit. Setting this bit selects the VSYNC output. clearing it selects
P3.5 SFR bit.
VOS
SOCR.5
VSYNC Output Selection bit. Setting this bit selects the VSYNC output, clearing it selects
P3.3 SFR bit.
CPE
SOCR.6
Clamp Pulse Enable bit. Setting this bit enables the CPO output.
CPP
SOCR.7
Clamp Pulse Polarity bit. Setting this bit selects positive clamp pulses, clearing it selects
negative clamp pulses.
SOCR is a write only register. Its value after reset is OOh
which enables P3.3 and P3.5 general purpose 1/0 pins.
SOCR is using TSC805lC2 Special Function Register
address, E5h.
II.8.17
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
P3.5/HOUT
PIN
P3.3IVOUT
PIN
Figure 14. Buffered HSYNC and VSYNC block
diagram
7.4.2. HSYNC and VSYNC Inputs
EICON is used to control INTOVSYNC input. Thus, an
interrupt on either falling or rising edge and on either
high or low level can be requested. Figure IS. shows the
programmable INTO/vSYNC input block diagram.
EICON is also used to control TO/HSYNC input as short
pulses input capture to be able to count them with timer
O. Pulse duration shorter than 1 clock period is rejected;
depending on the position of the sampling point in the
pulse, pulse duration longer than 1 clock period and
shorter than 1.5 clock period may be rejected or
accepted; and pulse duration longer than 1.5 clock
period is accepted. Moreover selection of negative or
positive pulses can be programmed.
Accepted pulse is lengthened up to I cycle period to be
sampled by the 8051 core (one time per machine cycle:
12 clock periods), this implies that the maximum pulse
frequency is unchanged and equal to foscl24.
Figure 16. shows the programmable TO/HSYNC input
block diagram. The Digital Timer Delay samples
TO/HSYNC pulses and rejects or lengthens them.
EICON: External Input Control Register
MSB
SFRE4h
LSB
TOL
IOL
TOS
IOL
EICON.O
INTOIVSYNC input Level bit. Setting this bit inverts INTOIVSYNC input signal.
Clearing it allows standard use of INTOIVSYNC input.
TOS
ElCON.l
TO/HSYNC input Selection bit. Setting this bit allows short pulse capture. Clearing it
allows standard use of TO/HSYNC input.
TOL
EICON.2
TO/HSYNC input Level bit. Setting this bit allows positive pulse capture. Clearing it
allows negative pulse capture.
EICON is a write only register. Its value after reset is OOh
which allows standard INTO and TO inputs feature.
EICON is using TSC8051C2 Special Function Register
address, E4h.
TOL
INTO
fose
Figure 16. TO/HSYNC input block diagram
lOL
Figure 15. INTO/vSYNC input block diagram
11.8.18
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
7.4.3. Clamp Pulse Output
The TSCS05lC2 provides fully programmable clamp
pulse output to pre-amplifier IC. User can program a
pulse with positive or negative polarity at either the
falling or rising edge of the HSYNC signal depending on
its polarity.
The clamp pulse duration depends on the oscillator
frequency by the following formula:
Tcpo = (I/fosc ) X 7.5 ± (l/foscl/2
(542ns ± 42ns at fose = 12 MHz)
Figure 17. shows the CPO block diagram. CPE bit in
SOCR is used to configure P 1.4 pin as general purpose
I/O or as open drain clamp pulse output, so enables the
CPO. CPP bit in SOCR is used to select the clamp pulse
signal polarity. Depending on the HSYNC polarity
selected by the TOL bit, Clamp pulse is generated on the
falling edge (negative polarity) or on the rising edge
(positive polarity) as shown in Figure IS.
CPO/PIA
PIN
HSYNC
TOL
CPP
CPE
Figure 17. Clamp Pulse Output block diagram
HSYNC
TOL bit=1
CPO
cpp bit::::l
CPO
cpp bit=O
HSYNC
TOL bit=O
CPO
CPPbit=1
CPO
CPPbit=O
Figure 18. Clamp Pulse Output waveform
II.S.19
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
8. Electrical Characteristics
Absolute Maximum Ratings(l)
Operating Temperature:
Voltage on VCC to VSS .............. -O.SV to +7V
Commercial ........................ O°C to 70°C Voltage on Any Pin to VSS .... -O.SV to VCC + O.SV
Industrial ....................... -40°C to +8Soe
Power Dissipation ........................ I W(2l
Storage Temperature ............. -6Soe to + ISO°C
2. This value is based on the maximum allowable die temperate
and the thermal resistance of the package.
Notice:
I. Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
8.1. DC Characteristics
TA
TA
= ooe to +70°C; VSS = OV; vce = sv ± 10%; F = 0 to 16MHz.
= -40 e to +8SoC; VSS = OV; vee = 5V ± 10%; F = 0 to 16MHz.
0
Symbol
Paral1l,ehlr"
TYp
M~x
Unit
0.2 Vee - 0.1
V
0.2 Vee + 0.9
Vee + 0.5
V
0.7 Vee
Vee + 0.5
V
Min
Test Conditions . '.
Inpnts
VfL
Input Low Voltage
VfH
Input High Voltage except XTALl. RST
VfHl
Input High Voltage, XTALl, RST
-0.5
ilL
Logical 0 Input Current ports I, 2 and 3
-50
flA
Yin = 0.45V
ILl
Input Leakage Current
±IO
~
0.45 < Yin < Vee
-650
flA
Yin = 2.0V
TBD
V
ITL
VLOW
Logical I to 0 Transition Current, ports 1, 2, 3
Power Fail Reset Low Voltage
TBD
3.5(5)
Ontputs
VOL
Output Low Voltage, ports 1,2,3,
PWMO-7(')
0.3
0.45
1.0
V
V
V
10L = 100flAl4)
IOL = 1.6mA(4)
IOL = 3.5mA(4)
VOLl
Output Low Voltage, port 0, ALE, PSEN (6)
0.3
0.45
1.0
V
V
V
IOL = 2OOflA(4)
[01. = 3.2mA(4)
IOL = 7.0mA(4)
VOH
Output High Voltage, ports 1,2,3
Vee - 0.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH=-IOjlA
IOH=-30jlA
IOH=-60jlA
Vec=5V±10%
VOH!
Output High Voltage, port 0, ALE, PSEN
Vee-O.3
Vee - 0.7
Vee - 1.5
V
V
V
IOH=-2OOflA
IOH=-3.2mA
[OH=-7.0mA
Vee=5V± 10%
RRST
RST Pulldown Resistor
CIO
50
Capacitance of I/O Buffer
11.8.20
90
(5)
200
kQ
10
pF
fc = IMHz, TA = 25°C
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
Symbol
ICC
IPD
Parameter
Power Supply Current
Active Moue 12MHI
12MHL
Idle Mode
Min
." Test Conditions
Typ
Max
Unit
TBD
TBD
TBD
TBD
mA
mA
Vee
Vee
5 (51
30
flA
Vee ~ 2.0V to 5.5V(11
(7)
Power Down Current
Notes for DC Electrical Characteristics
1. ICC is measureu with all output pins disconnecleu: XTALI driven
with TCLCH, TCHCL ~ 5 ns (see Figure 20. I, VIL ~ VSS +
0.5V, VIH ~ VCC - O.5V: XTAL2 N.C.: EA ~ RST ~ Port () ~
vee. ICC would be slightly higher if a crystal oscillator used
(sec Figure 19. ).
2. Idle lee is measured with all output pins di"connccted; XTALI
driven with TCLCH, TCHCL ~ 5ns, VIL ~ VSS + O.5V, VIH ~
VCC-O.5V; XTAL2 N.C: Port 0 ~ VCC; EA ~ RST ~ VSS (sec
Figure 20. ).
3. Power Down ICC is measured with all output pin~ di~conncctcd;
EA ~ PORT a ~ VCC: XTAL2 NC.; RST ~ VSS (sec
Figure 21. ).
4. Capacitance loading on Ports 0 and 2 may calise spuriolls noise
pulses to be superimposed on the VOLs of ALE and Ports 1 and
3. The noise is due to external bus capacitance discharging into
the Port a and P0l1 2 pins when these pins make I to a
transitions during bus operation. In the worst cases (capacitive
loading 10OpF), the noise pulse on the ALE line may exceed
OA5V with maxi VOL peak 0.6V A Schmitt Trigger usc is not
necessary.
5. Typicals are based on a limited number of samples and arc not
guarantecd. The values listed are at room tempcrature and Sv.
6. Under steady state (non-transient) conditions, IOL must be
externally limited as follows:
Maximum IOL per port pin:
10 rnA
Maximum IOL per 8-bit port:
porta:
26 rnA
Ports 1, 2 and 3:
15 rnA
Maximum total IOL for all output pins:
71 rnA
If IOL exceeds the test condition, VOL may exceed the related
specification. Pins are not guaranteed to sink current greater than
the listed tcst conditions.
7. For other values. please contact your sales office.
VCC
~
~
5.5VII)
5.5V(21
vee
RST
(NCI
CLOCK SIGNAL
E7\
XTAL2
XTALI
VSS
L -_ _ _- '
All other pins arc di:-.connccted.
Figure 20. ICC Test Condition, Idle Mode.
VeC
RST
(NC)
EA
XTAL2
XTALI
VSS
L -_ _ _- '
All other pins are disconnected.
Figure 21. ICC Test Condition, Power Down Mode.
VCC
PO
VCC
RST
(NC)
EA
XTAL2
XTALI
CLOCK SIGNAL
VSS
-=-
All other pins are disconnected.
Figure 19. ICC Test Condition, Active Mode.
MATRAMHS
11.8.21
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
Vcc-O.5V
O.7Vcc
O.2Vcc-O.!
0.45V
TCHCL
TCLCH
TCLCH =TCHCL =5ns.
Figure 22. Clock Signal Waveform for ICC Tests in Active and Idle Modes.
8.2. Explanation Of The AC Symbol
Each timing symbol has 5 characters. The first character
is always a "T" (stands for time). The other characters,
depending on their positions, stand for the name of a
signal or the logical status of that signal. The following
is a list of all the characters and what they stand for.
Example:
TAVLL = Time for Address Valid to ALE low.
TLLPL = Time for ALE low to PSEN low.
A: Address.
Q: Output data.
R: READ signal.
C: Clock.
D: Input data.
T:Time.
H: Logic level HIGH.
V: Valid.
I: Instruction (Program memory contents).
W: WRITE signal.
L: Logic level LOW, or ALE.
X: No longer a valid logic level.
P: PSEN.
Z: Float.
8.3. AC Parameters
(Load Capacitance for PORT 0, ALE and PSEN = IOOpf;
Load Capacitance for all other outputs = SO pF.)
TA = 0 to +70°C; VSS = OV VCC = 5V±1O%; 0 to
12MHz
TA = -40°C to +S5°C; VSS = OV; VCC = 5V ± 10%; F
=0 to 12MHz.
8.4. External Program Memory Characteristics
......
..
liyjnboL
.•..
........
:. :.
"
TLHLL
.
.. '.:.:
.•......
.:......
Paraln~U!r':'
.
....
",:
..':':.
'"
....
:
...:
.:
'.:
.:
...
ilto f2MHz
1\{iO
ALE pulse width
2TCLCL-40
'
..>
i.Max
............ : ..•...'.'
.
: I'
'
Unit~
:
."
.1
.
ns
TAVLL
Address Valid to ALE
TCLCL-40
os
TLLAX
Address Hold After ALE
TCLCL-30
ns
TLLIV
ALE to Valid Instruction In
4TCLCL -100
ns
TLLPL
ALEtoPSEN
TCLCL-30
os
TPLPH
PSEN Pulse Width
3TCLCL-45
ns
TPLIV
PSEN to Valid Instruction In
3TCLCL - 105
II.S.22
.
ns
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
!
';'.'••',.,:< Iri','!
oto 12MHz
"
!
ScymbOi,
Parameter
':,'• ,i"
Max
Min
TPXIX
Input Instruction Hold After PSEN
TPXIZ
Input Instructioo Float After PSEN
TPXAV
PSEN to Address Valid
TAVIV
Address to Valid Instruction In
TPLAZ
PSEN Low to Address Float
'i'i.,i,i !~<, ",,'i'O"
os
0
TCLCL-25
ns
TCLCL-8
ns
5TCLCL-I05
ns
10
ns
8.5. External Program
Memory Read Cycle
__________________________ 12TCLCL __________________________
~
II
~
ALE
PSEN
PORTO
PORT 2
INSTRIN
ADDRESS
ORSFR-P2
ADDRESS AS-A 15
8.6. External Data Memory Characteristics
_"7
TRLRH
r{,c;,i',j!J);:j/:1~:·f·.'i• · '· '·
I.'<:,} •• · . ; } ) :
RD Pulse Width
TWLWH
WR Pulse Width
TRLDV
RD to Valid Data 10
TRHDX
Data Hold After RD
:,...:-<
PORTO
PORT 2
TWLWH
ADDRESS
OR SFR-P2
/
.-TQVWX
~TLLA~
TWHQX_~
TQVWH
AO-A7
DATA OUT
.1
TAVWL
)<
ADDRESS A8-A 15 OR SFR P2
8.8. External Data Memory Read Cycle
TWHLH
~----------TLLDV--
ALE
________~
PSEN
---I~-----------+
TRLRH------------+I
RD
TRHDX
PORTO
DATA IN
TRLAZ
PORT 2
ADDRESS
OR SFR-P2
8.9. Serial Port Timing-Shift Register Mode
Oto12MHz
S~nib()1
.......
Parameter
..
I
...
...
Min
.
..
...
..
....
Mai ...
Units
TXLXL
Serial port clock cycle time
12TCLCL
ns
TQVHX
Output data set-up to clock rising edge
IOTCLCL-133
ns
TXHQX
Output data hold after clock rising edgc
2TCLCL-1l7
ns
TXHDX
Input data hold after clock rising edge
0
ns
TXHDV
Clock rising edge to input data valid
1OTCLCL-l 33
ns
MATRAMHS
Rev. A (10 Jan. 97)
11.8.24
Preview
TEMIC
TSC8051C2
Semiconductors
8.10. Shift Register Timing Waveforms
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
•
•
WRITE to SBUF
INPUT DATA
CLEAR RI
8.11. External Clock Drive Characteristics (XTAL1)
.. SymbOI ..
Parameter
....
Max
Min
Units
TCLCL
Oscillator Period
TCHCX
High Time
5
ns
TCLCX
Low Time
5
os
TCLCH
Rise Time
5
ns
TCHCL
Fan Time
5
ns
83.3
os
8.12. External Clock Drive Waveforms
Vcc-O.5V
O.7Vcc
O.45V _ _---.J- O.2Vcc-O.!
TCHCL
8.13. AC Testing Input/Output Waveforms
Vee
-o.S V
INPUT/OUTPUT
0.45 V
~0.2VCC+0.9
X
0.2 Vee-D.l
x=
' - - - -
~
AC inputs during testing are driven at Vcc - 0.5 for a
logic "I" and 0.45V for a logic "0". Timing
measurement are made at VIR min for a logic "1" and
VIL max for a logic "0".
MATRAMRS
Rev. A (10 Jan. 97)
II.S.25
Preview
TEMIC
TSC8051C2
Semiconductors
8.14. Float Waveforms
FLOAT
~----FLOAT
KVOH-O.l V
VLOAD
- - _ / ,jLVOL+O.l V
fLVLOAD+O.l V
i';:VLOAD-O.l V
For timing purposes as port pin is no longer floating
when a 100 mV change from load voltage occurs and
begins to float when a 100 mV change from the loaded
VOHIVOL level occurs. IOLIIOH ~ ± 20mA.
8.15. Clock Waveform
This diagram indicates when signals are clocked
internally. The time it takes the signals to propagate to
the pins, however, ranges from 25 to 125ns. This
propagation delay is dependent on variables such as
temperature and pin loading. Propagation also varies
from output to output and component. Typically though
(TA=25°C fully loaded) RD and WR propagation delays
are approximately 50ns. The other signals are typically
85ns. Propagation delays are incorporated in the AC
specifications.
11.8.26
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semiconductors
INTERNAL
CLOCK
STATE4
PI
1 P2
STATES
STATE6
STATE I
PI
PI
PI
1 P2
1 P2
1 P2
STATE2
PI
1 P2
STATE,
STATE4
PI
PI
1 P2
STATES
1 P2
PI
1 P2
XTAL2
ALE
EXTERNAL PROGRAM MEMORY FETCH
PSEN
I
PO
P2(EXT)
INDICATES ADDRESS TRANSITIONS
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
OOH IS EMITTED
Ii
r-;=-ru:=rniD~U:.oR::;ING THIS PERIOD
PO
DPL OR Rt OUT
I
[i5A'fA]
~-+-~----------------~S~MPL.ERDn-----------~
~4~........1 4 r - - - -_ _ FLOAT
P2
t L
.1
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRJTECYCLE
WR
PO
PCL OUT (EVEN IF PROGRAM
DPL OR Rt OUT
11oI4f--------------DATA OUT
P2
R~:i~::k~,
________3-+1'G,..·f'o....
r-----~~I~N~D~IC~X~TE~S~D~P~H~O~R~P2~S~FR~TO~PC~H~TRAN~~S~ITI~O~N-------------,
PORT OPERATION
MOV PORT SRC
OLD DATA
I NEW DATA
SAMPLED
_ __________...J~INS
MOVDESTPO
~
MOV DEST PORT (PI. P2. P3)
(INCLUDES INTO. INTI. TO TI)
SERIAL PORT SHIFT CLOCK
r;8
W'--_____
PO PINS SAMPLE
P2, P3 PINS SAMPLED
PI, P2, P3 PINS SAMPLE~
=~
~
______________~~_RX~DSAMPLED
TXD (MODE_ 0)
_
11.8.27
MATRAMHS
Rev. A (10 Jan. 97)
Preview
TEMIC
TSC8051C2
Semicondnctors
9. Ordering Information
TSC
xxx
51C2
12
16
-A
T
T
-12: 12 MHz version
-16: 16 MHz version
Part Number
8051 C2: Romless version
51 C2: 4Kx8 Mask ROM
Bounding Option
-none: 12 PWM
-A : 4 PWM & P2x
Customer Rom Code
TEMIC Semiconductor
Microcontroller Product Line
PC-TSC8051CI-RB-16
C
B
R
T
Packaging
A: PDIL40
B: PLCC44
C: PQFP44
D: SSOP44
E: PLCC52
G: CDIL40
H: LCC44
I: CQPJ 44
Temperature Range
C : Commercial 0° to 70°C
I : Industrial-40° to 85°C
Conditioning
R : Tape & Reel
D: Dry Pack
B : Tape & Reel
and Dry Pack
Probe card for TSC8051 Cl. These products are released by Metalink. Please consult the
local tools distributor or your sales office.
Product Marking:
TEMIC
Customer PIN
TemicPIN
© Intel 80, 82
YYWW Lot Number
MATRAMHS
Rev. A (10 Jan. 97)
1I.8.28
Preview
TEMIC
Semiconductors
cst Automotive Products
TSC8051A1 : CMOS Single Chip 8-bit Microcontroller with Analog Interface ..... 11.9.1
TSC8051A2 : CMOS Single Chip 8-bit Microcontroller with Analog Interfaces. . .. 11.10.1
TSC8051All : CMOS Single chip 8-bit Microcontroller with CAN Controller. . . .. 11.11.1
TSC8051A30: CMOS Single chip 8-bit Microcontroller with VAN Controller ..... 11.12.1
TEMIC
TSC8051Al
Semiconductors
CMOS Single chip 8-bit Microcontroller with Analog
Interface
Description
The TSC805lAI is a stand-alone, high performance
CMOS microcontroller designed for use in automotive
and industrial applications.
The TSC80All retains all features of the TSC80C51
with extended EPROM capacity (24K bytes), 256 bytes
of internal RAM, a 14-source 2-level interrupt, a full
duplex serial port, an on-chip oscillator, and two 16 bits
timers.
In addition, the TSC8051AI has an 8-bit 8-channel NO
converter, a serial synchronous port compatible with SPI
and mWire protocols, an advanced 8 channels CCU
(Capture & Compare Unit), an additional on-chip
XRAM of 256 bytes and a high security Watchdog timer
with an embedded oscillator.
The fully static design of the TSC805lAI allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The design is done with a specific care to reduce EMC
emission and susceptibility.
This circuit is manufactured using SCMOS process and
is available in commercial, industrial, military and
automotive ranges: it runs from 0 up to 20 MHz in the
automotive temperature range -40°C to +125°C.
Features
•
•
•
•
80C51 core architecture:
• 256 bytes of RAM
• 256 bytes of XRAM
• 24 Kilobytes of EPROM, OTP or ROM
14-source 2-level interrupt
• Two 16-bit timerlcounter
• Full duplex UART compatible with standard
80C51 with its own baud rate generator
6 8-bit 80C51 I/O Ports bit to bit configurable
2 ports with programmable interrupt for keyboard
function
A 8 channels 16-bit CCU with:
• Rising andlor falling edge capture (pulse
measurement capability)
Software timer, high speed output and multiple
PWMshapes
•
•
•
•
•
A 8-bit resolution analog to digital converter with 8
multiple inputs
An high security watch-dog timer with an embedded
oscillator
A master/slave synchronous serial peripheral
interface (SPI or mWire)
Several power reduction modes with enhanced
wake-up capabilities
PQFP64 or PLCC68 packages
MATRAMHS
Rev. B (14 Jan. 97)
II.9.1
Preview
B
TEMIC
TSC8051Al
Semiconductors
Block Diagram
~~
=
=
~ ~
I ______
--
tl
~
i>
_t __________ -
....·..• ft
;':,,\,> ,..
PQJJ1I PL{:C
P.
......<;;!lCW)~.;.(i
AD.7 I POKB.7
(i4
liS
;,'
•.· ...c.
c... c:·....
c
c··c
I'
;C
INTI
TO
T1
-
11
20
PL7
SS
42
54
P5.0
P5KB.0
12
21
PL6
SCK
43
55
P5.1
P5KB.1
13
22
PL5
MOSI
44
56
P5.2
P5KB.2
liltllj!I~I~l1
23
(n.e)
45
57
P5.3
P5KB.3
14
24
PIA
46
58
P5A
P5KB.4
IS
25
PI.3
47
59
P5.5
P5KB.5
16
26
PL2
-
48
60
P5.6
P5KB.6
17
27
P1.1
-
49
61
P5.7
P5KB.7
18
28
PLO
50
62
(n.e)
19
29
P4.7
ANA.7
51
63
RESET
20
30
P4.6
ANA.6
52
64
PSEN
MISO
II
-
21
31
P4.5
ANA.5
53
65
ALE/PROG
22
32
P4A
ANA.4
54
66
EA/Vpp
23
33
ANAVss
55
67
Vss
24
34
ANAVee
1~';:~i:W!;l1
68
(n.e)
25
35
ANAref+
56
1
Vee
t;!lI~i:~~tl
36
Vss
57
2
P2.0
26
37
P4.3
ANA.3
58
3
P2.1
A.9/CeU.I
27
38
P4.2
ANA.2
59
4
P2.2
A.1O I CeU.2
28
39
P4.1
ANA.l
60
5
P2.3
A.II I CCU.3
29
40
P4.0
ANA.O
61
6
P2.4
A.121 CeUA
30
41
P3.0
RXD
62
7
P2.5
A. 13 I CCU.5
31
42
P3.1
TXD
63
8
P2.6
A.14/CCU.6
32
43
P3.2
INTO
64
9
P2.7
A.15 I CCU.7 I ECI
A.8/CeU.0
11.9.5
MATRAMHS
Rev. B (14 Jan. 97)
Preview
TEMIC
TSC8051Al
Semiconductors
General Signal Description
Vss
PORTO
Digital ground
Port 0 can act the part of address/data bus or standard I/O
port.
Its dedicated alternate function is a S-bit keyboard
interface.
In the default configuration, port 0 operates the same as
it does in the SOCSI, with open-drain outputs.
Vee
Digital supply voltage
ANAVss
Analog ground
PORT!
ANAVee
Port I can act the part of standard I/O port.
This port dedicated alternate functions are P.l [4:7] for
synchronous serial link (SPI or mWIRE) interface.
In the default configuration, port 1 operates the same as
it does in the SOCSl, with internal pullups. Port 1 type
CS1 is sometimes called "quasi-bidirectional" due to the
internal pullups.
Analog supply voltage
EA/Vpp
External Access enable must be strapped to Vss in order
to enable any device plugged on port 0 / port 2 to fetch
code from 0 up to 24K. EA must be strapped to Vcc for
internal program execution.
This pin also receives the 12V programming supply
(Vpp input) to program the internal EPROM.
PORT 2
It is the output from the inverting oscillator amplifier.
Port 2 can act the part of address bus or standard I/O port.
Its dedicated alternate function is the CCU (Capture &
Compare Unit) interface.
In the default configuration, port 2 operates the same as
it does in the SOCSI, with internal pull-ups.
RESET
PORT 3
An active level (low) on this pin, while the oscillator is
running, resets the device. An internal pull-up resistor
permits power-on reset only using only an capacitor
connected to Vss.
The active level of the RESET pin is the opposite to the
one of CSI standard.
Port 3 can act the part of standard I/O port.
Its dedicated alternate functions are those of the CSI
standard (RxD, TxD, INTO, INTl, TO, Tl, WR & RD).
In the default configuration, port 3 operates the same as
it does in the CS1, with internal pull-ups. Port 3 type CS1
is sometimes called "quasi-bidirectional" due to the
internal pull-ups.
XTAL2
ALE I PROG
The Address Latch Enable output signal is used to latch
the low order byte of the address during accesses to
external memory. ALE can sink and source S LS TTL
loads.
If desired, ALE buffer can be disable. Then, ALE is
pulled low.
This pin is also used (program pulse input) to program
the internal EPROM.
PORT 4
Port 4 can act the part of standard I/O port.
Its dedicated alternate functions are 8 inputs for ADC
module.
In the default configuration, port 4 operates as a
"quasi-bidirectional" port type CS1 with internal
pUllups.
ANAref+
Program Store Enable is the read strobe to external
program memory, else it remains high. PSEN can sink
and source S LS TTL loads.
Positive voltage for the ADC module.
MATRAMHS
Rev. B (14 Jan. 97)
II.9.6
Preview
TEMIC
TSC8051Al
Semiconductors
PORTS
Port 5 can act the part of standard I/O port.
Its dedicated alternate function is a 8-bit keyboard
interface.
In the default configuration, port 5 operates as a
"quasi-bidirectional" port type C5l with internal
pull-ups.
Electro-Magnetic Compatibility (EMC)
Primary attention is paid to the reduction of
electro-magnetic emission of the TSC805lAl. The
following features reduce the electro-magnetic emission
and additionally improve the electro-magnetic
susceptibility:
• The TSC805lAI provides one analog supply voltage
pin and one analog ground pin. Placed on the middle
of one side of the package, this pair (ANAVcC/
ANAVss) has short bounding wires, thus reducing
the generated noise.
In order to reduce the radiation loop area, the two
pins are adjacent.
• The TSC805lAI provides three groups of digital
supply voltage and digital ground, in pairs of pins
(VssNcc). Placed on the middle of the three other
sides of the package, these groups have short
bounding wires, thus reduces the generated noise.
In order to reduce the radiation loop area, pins are
adjacent inside group.
• External capacitors should be connected across
associated pins (ANAVcC/ANAVss or VccNss).
Lead length should be as short as possible. Ceramic
CMS capacitors are recommended, lOnF + lOOnF.
•
•
Several internal decoupling capacitors improve the
EMC radiation behavior and the EMC immunity.
In order to reduce the spectrum of the TSC805IAI,
many signals has been treated, principally the
periodic signals. The current provided for external
signals, the period of clocks and the raising/falling
edges are the major points which has been nursed.
• For application that never (or temporarily)
requires external memory resources, the ALE
buffer can be disable.
• Once the oscillator is started, the gain is reduce
by 2 (6 dB).
• Peripherals receiving XTAL clock have, each
one, their own prescaler to produce the operating
clock they need.
• The output buffers are especially designed to
control rising and falling edges.
11.9.7
MATRAMHS
Rev. B (14 Jan. 97)
Preview
m
IIriI
TEMIC
TSC8051A2
Semiconductors
CMOS Single Chip 8-bit Microcontroller
with Analog Interfaces
Description
The TSC80Sl A2 is a stand alone, high performance
CMOS microcontroller designed for use in automotive
and industrial applications.
The TSC80S1A2 retains all features of the 80CSI with
extended ROM capacity (l6K bytes), 2S6 bytes of
RAM, a lO-source 2-level interrupt, a full duplex serial
port, an on-chip oscillator and clock and two 16 bits
timers.
In addition, the TSC8051 A2 has an 8-bit 8-channel AID
converter, a serial peripheral interface compatible with
SPI, a high security watchdog and an advanced 8
channel Capture and Compare timer Unit.
The fully static design of the TSC805lA2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The design is done with a specific care to reduce EMC
emission and suceptibility.
This circuit is manufactured using SCMOS process and
is available in commercial, industrial, military and
automotive ranges; it runs from 0 up to 20 MHz in the
automotive temperature range -40°C to + 12SoC.
Features
•
•
•
•
•
•
256 bytes of RAM
16 K bytes of ROM or OTP
Four 8-bit I/O ports ; each bit can be:
TTL I/O
Push-pull output
CMOS input trigger with or without pull-down
Two 16 bit timer/counter
A programmable window watch-dog with
integrated low power RC oscillator; basic period 20
ms typical, maximum period 128 times 20 ms
A eight channels 16 bits Capture and Compare Unit
with:
input capture
output compare and PWM
•
•
•
•
•
•
•
A 8-bit resolution analog to digital converter with
eight multiplex inputs; conversion time 48 machine
cycles.
One port with programmable interrupt for keyboard
function
Several power reduction modes with enhanced wake
up capabilities
Power fail detection, Power on reset bit
Full duplex UART compatible with standard 80CSI
A serial peripheral interface (SPI+MW)
PQFP, PLCC or SSOP 44 package ; PQFP 64 for
emulation
MATRAMHS
Rev. A (14 Jan. 97)
Il.10.1
Preview
m
IIIriiiI
TEMIC
TSC8051A2
Semiconductors
Block Diagram
XTALI
XTAL2
ALE!
PROG
PSEN
EANpp
Power
RD
Monitor
Key
Board
WR
_ J
(0) -
'"
~
(I): Alternate function of Port 1
(2): Alternate function of Port 2
(3): Alternate function of Port 3
(0): Alternate function of Port 0
Figure 1. TSC8051A2 Block Diagram
11.10.2
MATRAMHS
Rev. A (14 Jan. 97)
Preview
TEMIC
TSC8051A2
Semiconductors
Pin Configuration
a
OJ
0
INDEX
CORNER
'"
~
a
a: 'a:" a: "'a: a:
N
'"'"
~
Z
()
()
~
Z
'" '"
"'"0
""-'0"
N
iii OJ
lE OJ
Cl
'0"
;3 ~
0
"- Ii'
N
OJ
~
0
'"
iil
0
"-
-PO.6IAD6IKB6
PO.7IAD7IKB7
ENVPP
VSS
TSC8051A2
ALEIPROG
PSEN
P2.7IA15ICCU7/ECI
P2.61A14ICCU6
P2.5IA13/CCU5
:26: :27: :28:
:; OJ OJ'" OJ
;18: :-19: :"20: :21: :'22: f23: :24: :25:
!l'Z
'-
'"
Z
I~ Iga:
~ ~
"-
'"
"-
:'I -' !f;"
fOX fOX
~
a
::>
()
()
ro
~
N
"-
..
N
" "
~ "~ 2~ ;;:
()
()
()
()
OJ
~
~
N
"-
Ii'
N
"-
n.lO.3
MATRAMHS
Rev. A (14 Jan. 97)
Preview
TEMIC
TSC8051A2
39
40
41
42
17
23
VCC
VCC
Pl.O
18
24
P2.0/A08/CCUO
Address bus high order or
CCU module I external va
Pl.l
19
25
P2.1/A09/CCUI
Address bus high order or
CCU module I external va
P1.2
20
26
P2.2/AIO/CCU2
Address bus high order or
CCU module 2 external va
P1.3
21
27
P2.3/AllICCU3
Address bus high order or
CCU module 3 external 110
ANAVSS
2
4
43
Semiconductors
VSS Analog
P1.4/MISO
SPI master in ,slave out
22
28
P2.4/A l2/CCU4
Address bus high order or
CCU module 4 external I/O
P1.5/MOSI
SPI master out, slave in
23
29
P2.5/A13/CCU5
Address bus high order or
CCU module 5 external va
P1.6/SCK
SPI serial clock I/O
24
30
P2.6/A14/CCU6
Address bus high order or
CCU module 6 external va
9
P1.7/SS
srI slave select
25
31
P2.7/A15/CCU7/
ECI
Address bus high order or
CCU module 7 external va
or CCU count input
10
RST
Reset
26
32
PSEN
Program store enable
11
P3.0/RXD/ANAO
Serial receive port or
Keyboard
27
33
ALE/PROG
Address latch enable/Program
pulse
12
AVREF+
Analog positive reference
28
34
VSS
13
P3.1ITXD/ANAI
Serial transmit port or
Analog Input 1
29
35
EAIVPP
External access
enable/Programming supply
voltage
14
P3.2IINTO/ANA2
External interrupt 0 or
Analog Input 2
30
36
PO.7/AD7/KB7
Mux. low order address &
data bus or Keyboard
9
15
P3.3/INTl/ANA3
External interrupt 1 or
Analog Input 3
31
37
PO.6/AD6/KB6
Mux. low order address &
data bus or Keyboard
10
16
P3.41T0/ANA4
Timer/counter 0 input or
Analog Input 4
32
38
PO.5/AD5/KB5
Mux. low order address &
data bus or Keyboard
11
17
P3.5lTlIANA5
Timer/counter 1 input or
Analog Input 5
33
39
PO.4/AD4/KB4
Mux. low order address &
data bus or Keyboard
12
18
P3.6/WRlANA6
External data memory write
strobe or Analog Input 6
34
40
PO.3/AD3/KB3
Mux. low order address &
data bus or Keyboard
13
19
P3.7/RD/ANA7
External data memory read
strobe or Analog Input 7
35
41
PO.2/AD2/KB2
Mux. low order address &
data bus or Keyboard
14
20
XTAL2
Crystal output
36
42
PO.lIAD IIKB 1
Mux. low order address &
data bus or Keyboard
15
21
XTALl
Crystal input
37
43
PO.O/ADO/KBO
Mux. low order address &
data bus or Keyboard
16
22
VSS
VSS
38
44
44
6
2
4
6
11.10.4
ANAVCC
VCCAnalog
MATRAMHS
Rev. A (14 Jan. 97)
Preview
TEMIC
TSC8051A2
Semiconductors
Pin Functions
XTALI
XTAL2
ENVpp
ALE/PROG
PSEN
RESET
PORTO
~'"
ADI
AD2
AD3
AD4
ADS
AD6
AD7
ANAVcc
ANAVss
AVREF+
ANA()~RXD
TXD ~
~
ANAl
ANA2
INTO
ANA.1
ANA4
ANA5
ANA6
ANA7
INTI
TO
TJ
WR
RD
~
PORT:!
PORT I
~
+--
El
Low
order
addre~s
& data
bu~
li
KBO
KB!
KB2
KB3
KB4
KB5
KB6
KB7
11
M!SOf
MOSI SPIIrn"YIRE
SCK
interface
SS
PORT 2
~
A8
A9
AIO
High
All
Al2
order
address
AI3
AI4
AIS
hus
~
ccuo
CeUl
CCU2
CeU3
CCU4
ceus
CCU6
CCU7/ECI
" ' - - - - - - 44-pin package
Figure 2. TSC8051A2 Pin Functions
II.lO.S
MATRAMHS
Rev. A (14 Jan. 97)
Preview
TEMIC
TSC8051A2
Semiconductors
General Signal Description
Vss
Digital ground
Program Store Enable is the read strobe to external
program memory, else it remains high. PSEN can sink
and source 8 LS TTL loads.
Vee
Digital supply voltage
PORTO
ANAVss
Port 0 can act the part of address/data bus or standard VO
port. Its dedicated alternate function are the inputs of the
keyboard interrupt. In the default configuration, port 0
operates the same as it does in the 80C51, with
open-drain outputs.
Analog groundl
ANAVee
Analog supply voltage
PORTl
EA/Vpp
External Access enable must be strapped to Vss in order
to enable any device plugged on port 0 / port 2 to fetch
code from 0 up to 16K. EA must be strapped to Vcc for
internal program execution.
This pin also receives the 12V programming supply
(Vpp input) to program the internal EPROM.
XTALl
It is the input to the inverting oscillator amplifier and the
input for external clock generator.
Port 1 cal) act the part of standard I/O port. This port
dedicated alternate functions are P.1 [4:7] for the
synchronous serial link (SPI or mWIRE) interface.
In the default configuration, port 1 operates the same as
it does in the 80C51, with internal pullups. Port 1 type
C51 is sometimes called "quasi-bidirectional" due to the
internal pullups.
PORT 2
It is the output from the inverting oscillator amplifier.
Port 2 can act the part of address bus or standard VO
port.lts dedicated alternate function is the CCU (Capture
& Compare Unit) interface.In the default configuration,
port 2 operates the same as it does in the 80C51, with
internal pull ups.
XTAL2
RESET
PORT 3
The active level of the RESET pin is low. An active level
on this pin, while the oscillator is running, resets the
device. An internal resistor permits power-on reset only
using an external capacitor. The reset pin is
bidirectional; it acts as an output when a rcset is issued
by the watch-dog function.
Port 3 can act the part of standard VO port. This port has
two types of alternate functions:
• The first ones are the same than in C51 (Rxd, TxD,
... , WR,RD),
• The second type of alternate functions are 8 inputs
for the 8-bit AID converter.
ALE I PROG
In the default configuration, port 3 operates the same as
it does in the C51, with internal pullups. Port 3 type C51
is sometimes called "quasi-bidirectional" due to the
internal pUllups.
The Address Latch Enable output signal is used to latch
the low order byte of the address during accesses to
external memory. ALE can sink and source 8 LS TTL
10ads.If desired, ALE buffer can be disable. Then, ALE
is pulled low. This pin is also used (program pulse input)
to program the internal EPROM.
AVREF+
•
Positive reference voltage for the ADC module.
MATRAMHS
Rev. A (14 Jan. 97)
II. 10.6
Preview
TEMIC
TSC8051A2
Semiconductors
Electro-Magnetic Compatibility (EMC)
•
Primary attention is paid to the reduction of
electro-magnetic emission of the TSC8051A2. The
following features reduce the electro-magnetic emission
and additionally improve the electro-magnetic
susceptibility:
• The TSC805lA2 provides one analog supply voltage
pin and one analog ground pin. Placed on the middle
of one side of the package, this pair (ANAVccl
ANAVss) has short bounding wires, thus reducing
the generated noise.
In order to reduce the radiation loop area, the two
pins are adjacent.
• The TSC8051A2 provides one group of digital
supply voltage and digital ground, in pairs of pins
(Vss/Vcc). Placed on the middle of the sides of the
package, this group have short bounding wires, thus
reduces the generated noise. In order to reduce the
radiation loop area, pins are adjacent inside group.
•
•
External capacitors should be connected across
associated pins (ANAVcc/ANAVss or Vcc/Vss).
Lead length should be as short as possible. Ceramic
CMS capacitors are recommended, 10nF + 100nF.
Several internal decoupling capacitors improve the
EMC radiation behaviour and the EMC immunity.
In order to reduce the spectrum of the TSC8051A2,
many signals has been treated, principally the
periodic signals. The current provided for external
signals, the period of clocks and the raisinglfalling
edges are the major points which has been nursed.
For application that never (or temporarily)
requires external memory resources, the ALE
buffer can be disable .
Once the oscillator is stable, the gain is reduce by
2 (6 dB).
Peripherals receiving XTAL clock have, each
one, their own prescaler toproduce the operating
clock they need.
The output buffers are especially designed to
control rising and falling edges.
11.10.7
MATRAMHS
Rev. A (14 Jan. 97)
Preview
B
TEMIC
TSC8051All
Semiconductors
CMOS Single chip 8-bit Microcontroller with CAN
Controller
Description
The TSC8051A11 is a stand-alone, high performance
CMOS microcontroller designed for use in automotive
and industrial applications.
The TSC80A11 retains all features of the TSC80C51
with extended EPROM capacity (24K bytes), 256 bytes
of internal RAM, a 14-source 2-level interrupt, a full
duplex serial port, an on-chip oscillator, and two 16 bits
timers.
In addition, the TSC805lAli has an 8-bit 8-channel
AID converter, a serial synchronous port compatible
with SPI and mWire protocols, an advanced 8 channels
CCU (Capture & Compare Unit), an additional on-chip
XRAM of 256 bytes, a high security Watchdog timer
with an embedded oscillator and a CAN network line
controller.
The CAN controller is fully compliant with the BOSCH
CAN standard rev 2.0 part B. It implements all features
of a full CAN controller able to handle all frames of the
protocol with 14 predefined messages (channels). It
includes 14 sets of channel registers. Each channel has
its own identifier tag, its own identifier mask and up to
8 bytes (mailbox) to store the received and transmitted
message.
The fully static design of the TSC8051A 11 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The design is done with a specific care to reduce EMC
emission and susceptibility.
This circuit is manufactured using SCMOS process and
is available in commercial, industrial, military and
automotive ranges: it runs from 0 up to 20 MHz in the
automotive temperature range AO°C to +125°C.
Features
•
•
•
•
•
80C51 core architecture:
256 bytes of RAM
256 bytes of XRAM
24 Kilobytes of EPROM, OTP or ROM
l4-source 2-level interrupt
Two 16-bit timer/counter
Full duplex UART compatible with standard
80C51 with its own baud rate generator
6 8-bit 80C5l I/O Ports bit to bit configurable
2 ports with programmable interrupt for keyboard
function
A 8 channels 16-bit CCU with:
Rising and/or falling edge capture (pulse
measurement capability)
Software timer, high speed output and multiple
PWM shapes
A 8-bit resolution analog to digital converter with 8
multiple inputs
•
•
•
•
•
An high security watch-dog timer with an embedded
oscillator
A master/slave synchronous serial peripheral
interface (SPI or mWire)
Full CAN controller:
Fully compliant with CAN standard rev 2.0 A
and 2.0B
Optimized
structure
for
communication
management
14 channels with individual tag and mask filters
on 29 identifier-bit
Line wake-up capability
Automatic reply mode
1 Mbitls maximum transfer rate
Integrated line interface circuitry (output drivers,
input comparators, Vcc/2 generator)
Several power reduction modes with enhanced
wake-up capabilities
PQFP64 or PLCC68 packages
MATRAMHS
Rev. D (14 Jan. 97)
II.ll.1
Preview
TEMIC
TSC8051All
Semiconductors
Block Diagram
ti
B
XTALl
XTAL2
ALE!
PROG
PSEN
UART
RAM
EPROM
XRAM
256x8
24Kx8
256x8
C51
CORE
IB-bus
EANpp
RD
Timer 0
Timer 1
INT
Watch
Power
Key
Ctrl
Dog
Monitor
Board
WR
_ J
(1): Alternate function of Port 1
(2): Alternate function of Port 2
(3): Alternate function of Port 3
(4): Alternate function of Port 4
Figure 1. TSC8051All block diagram
II.ll.2
MATRAMHS
Rev. D (14 Jan. 97)
Preview
TEMIC
TSC8051All
Semiconductors
Pin-Out
Pin Functions
XTALI
XTAL2
-WOf
. . . . . . AD.1
. . . . AD.2
. . . . . . AD.3
EANpp
ALE/PROG
PSEN
RESET
CRXO
CRXI
CAN CTXO
CTXl
MISO
MOSI
SPUmWIRE SCK
1
1
SS
UART
External
[nterrupt
Timer
Input
Ext. RAM
Control
-------------------
PortO . . . . . . AD 4
.
. . . . . . AD.5
. . . . . . AD.6
. . . . AD.7
Port 1
Port 2
-----... A.IO
-----. A.II
-----. A.12
- - - . A.13
- - - - . A.14
High
order
address
bus
~A.15
....-- ANA.O
......-- ANA. I
RXD -----.
TXD~
---- ""'Of
---------- -POKB.l
POKB.2
POKB.3
POKBA
POKB.S
POKB.6
POKB.7
B
Port 0
Keyboard
ceu.o
- - - - . A.8
_____ A.9
lN11) _____
11) -----.
_____
INTI
Low
order
address
& data
bus
CeU.l
CeU.2
CeU.3
CeU.4
CCU.5
CCU.6
CeU.7
f C~"
Compare
VmL
Eel
~ANA.2
Port 3
-----
Tl _ _
WR
RD _ _
~ ANA.3
PORT 4 ......-- ANA.4
. . . - - ANA.S
...-ANA.fi
......--ANA.7
Analog
Digital
.......
Converter
ANAVref+
P5KB.O -----...
P5KB.l - - - - .
PSKB.2 - - . .
PortS
Keyboard
~;~::~
=:
ANAVcc
ANAVss
PORT 5
P5KB.5 _________
P5KB.6 -----...
PSKB.7 -----...
Figure 2. TSC80S1All pin functions
MATRAMHS
Rev. D (14 Jan. 97)
ILlI.3
Preview
TEMIC
TSC8051All
Semiconductors
Pin Configuration
PO.O/POKB.O
PO. I/POKB. !
PO.2/POKB.2
POJ/POKB.3
POA/POKBA
PO.5/POKB.S
PO.6/POKB.6
Vee
TSC8051All
PQFP64
v"
PO.7/POKB.7
P1.7/SS
Pl.6/SCK
P1.5IMOSI
PI.4/MISO
P1.3/CTXl
Top View
PI.2!CTXO
9 8 7 6 5 4 3 2
CD
6tl 67 66 65 64 63 62 61
PO.OIPOKB.O
PO.llPOKB.l
PO,2/POKB.2
PO.3/POKB.3
rDA/PQKBA
P0.5IPOKB.5
PO.6/POKB.6
TSC8051All
PLCC68
Vee
Vss
PO.7/POKB.7
Top View
P1.7/SS
P5.6/P5KB.6
P5.5/PSKB.5
P5,4/P5KBA
P5.3/PSKB.3
P5.21P5KB.2
PS.IIPSKB.l
P5.0/PSKB.O
XTAL2
XTALI
Vee
Vss
P3.7/RD
P3.61WR
P3.5/TI
P3AlTO
P3JIINTI
PI.6/SCK
PS.6/P5KB.6
P5.5/P5KB.5
PS.4/P5K8A
P5.3/P5KB.3
PS.2fPSKB,2
P5,1IPSKB.1
P5.0/P5KB.O
XTAL2
XTALI
Vee
Vss
(n.c)
P1.5/MOSI
P3.7/RD
(n.c)
P3.6fWR
P3.S{n
PIA/MISO
Pl.3/CTXl
PL2/CTXO
44
2728 2930 31 32 33 34 35 36 37 38 39 40 41 42 43
P3.4rrO
P3.3IINTl
Figure 3. TSC8051All pin configuration
II.l1.4
MATRAMHS
Rev. D (14 Jan. 97)
Preview
TEMIC
TSC8051All
Semiconductors
._c.
Pin Assignment
Table 2. Pin assignment
,;!..;
,;:c ;~
".
:........;i:i li:)<. ....~~CtiO!l/: •. •. • / .> 1~~tiP~j"""'" . ..) • ii,i.i. . ·)~i~;f~i . ·.i •
1""".;;;;j/h'«J
<',
..~ ..*~"
.
'n....."
TNTI
1
10
PO.O
AD.O I POKB.O
33
44
P3.3
2
II
PO.I
AD.I I POKB.I
34
45
P3.4
TO
3
12
PO.2
AD.2 I POKB.2
35
46
P3.5
T1
4
13
PO.3
AD.3 I POKB.3
36
47
P3.6
WR
5
14
POA
ADA I POKBA
37
48
P3.7
RD
6
15
PO.5
AD.5 I POKB.5
,,
49
(n.c)
7
16
PO.6
AD.6 I POKB.6
38
50
Vss
8
17
Vee
39
51
Vee
9
18
Vss
40
52
XTALl
•........... .. .............
10
19
PO.7
AD.7 I POKB.7
41
53
XTAL2
11
20
P1.7
SS
42
54
P5.0
12
21
P1.6
SCK
43
55
P5.1
P5KB.l
13
22
PI.5
MOST
44
56
PS.2
P5KB.2
,W1HtAl,\'li
23
(n.c)
45
57
P5.3
P5KB.3
14
24
PI.2
MlSO
46
58
P5A
P5KB.4
15
25
P1.3
CTXl
47
59
P5.5
P5KB.5
16
26
PI.2
CTXO
48
60
P5.6
P5KB.6
17
27
Pl.1
CRXI
49
61
P5.7
P5KB.7
18
28
PI.O
CRXO
50
62
(n.c)
19
29
P4.7
ANA.7/Cref
51
63
RESET
II
PSKB.O
20
30
P4.6
ANA.6
52
64
PSEN
21
31
P4.5
ANA.5
53
65
ALE/PROG
22
32
P4.4
ANA.4
54
66
EA/Vpp
23
33
ANAVss
55
67
Vss
24
34
ANAVcc
i,.,i.
68
(n.c)
25
35
ANAref+
56
1
Vcc
:\Wl,\\;'.
36
Vss
57
2
P2.0
26
37
P4.3
ANA.3
58
3
P2.1
A.9/CCU.l
27
38
P4.2
ANA.2
59
4
P2.2
A.l0ICCU.2
28
39
P4.1
ANA. 1
60
5
P2.3
A.11 I CCU.3
29
40
P4.0
ANA.O
61
6
P2A
A.12/CCUA
30
41
P3.0
RXD
62
7
P2.5
A.13 I CCU.5
31
42
P3.1
TXD
63
8
P2.6
A.14/CCU.6
32
43
P3.2
INTO
64
9
P2.7
A.15 I CCU.7 I ECl
A.8/CCU.0
II.l1.5
MATRAMHS
Rev. D (14 Jan. 97)
Preview
TEMIC
TSC80S1All
Semiconductors
General Signal Description
Vss
PORTO
Digital ground
Port 0 can act the part of address/data bus or standard 110
port.
Its dedicated alternate function is a S-bit keyboard
interface.
In the default configuration, port 0 operates the same as
it does in the SOCSl, with open-drain outputs.
Vee
Digital supply voltage
ANAVss
PORT!
Analog ground
ANAVee
Analog supply voltage
EA/Vpp
External Access enable must be strapped to Vss in order
to enable any device plugged on port 0 / port 2 to fetch
code from 0 up to 24K. EA must be strapped to Vcc for
internal program execution.
This pin also receives the 12V programming supply
(Vpp input) to program the internal EPROM.
Port I can act the part of standard I/O port.
This port has two dedicated alternate functions:
P.I[O:3] for CAN (Controller Area Network)
interface.
P.I [4:7] are for synchronous serial link (SPI or
mWIRE) interface, In the default configuration,
port I operates the same as it does in the SOCS1,
with internal pullups. Port I type CSI is
sometimes called "quasi-bidirectional" due to
the internal pullups.
PORT 2
Port 2 can act the part of address bus or standard I/O port.
Its dedicated alternate function is the CCU (Capture &
Compare Unit) interface.
XTAL2
It is the output from the inverting oscillator amplifier.
In the default configuration, port 2 operates the same as
it does in the SOCS1, with internal pull-ups.
RESET
An active level (low) on this pin, while the oscillator is
running, resets the device. An internal pull-up resistor
permits power-on reset only using only an capacitor
connected to Vss.
The active level of the RESET pin is the opposite to the
one of CSI standard.
ALE/PROG
PORT 3
Port 3 can act the part of standard 110 port.
Its dedicated alternate functions are those of the CSI
standard (RxD, TxD, INTO, INTI, TO, TI, WR & RD).
In the default configuration, port 3 operates the same as
it does in the CSI, with internal pull-ups. Port 3 type CSI
is sometimes called "quasi-bidirectional" due to the
internal pull-Ups.
The Address Latch Enable output signal is used to latch
the low order byte of the address during accesses to
external memory. ALE can sink and source S LS TTL
loads.
If desired, ALE buffer can be disable. Then, ALE is
pulled low.
This pin is also used (program pulse input) to program
the internal EPROM.
PORT 4
Program Store Enable is the read strobe to external
program memory, else it remains high. PSEN can sink
and source S LS TTL loads.
ANAref+
Port 4 can act the part of standard 110 port.
This port has two types of alternate functions:
• The first ones are S inputs for ADC module,
• The second type of alternate functions is the
reference voltage, Cref for CAN module.
In the default configuration, port 4 operates as a
"quasi-bidirectional" port type CSI with internal
pullups.
Positive voltage for the ADC module.
11.11.6
MATRAMHS
Rev. D (14 Jan. 97)
Preview
TEMIC
TSC8051All
Semiconductors
PORTS
In the default configuration, port 5 operates as a
"quasi-bidirectional" port type C51 with internal
pull-ups.
Port 5 can act the part of standard 110 port.
Its dedicated alternate function is a 8-bit keyboard
interface.
Electro-Magnetic Compatibility (EMC)
Primary attention is paid to the reduction of
electro-magnetic emission of the TSC80SlAll. The
following features reduce the electro-magnetic emission
and additionally improve the electro-magnetic
susceptibility:
• The TSC80S1All provides one analog supply
voltage pin and one analog ground pin. Placed on the
middle of one side of the package, this pair
(ANAVcc/ ANAVss) has short bounding wires, thus
reducing the generated noise.
In order to reduce the radiation loop area, the two
pins are adjacent.
• The TSC8051All provides three groups of digital
supply voltage and digital ground, in pairs of pins
(VssNcc). Placed on the middle of the three other
sides of the package, these groups have short
bounding wires, thus reduces the generated noise.
In order to reduce the radiation loop area, pins are
adjacent inside group.
• External capacitors should be connected across
associated pins (ANAVcc/ANAVss or VccNss).
•
•
Lead length should be as short as possible. Ceramic
CMS capacitors are recommended, I OnF + 100nF.
Several internal decoupling capacitors improve the
EMC radiation behavior and the EMC immunity.
In order to reduce the spectrum of the TSC8051A 11,
many signals has been treated, principally the
periodic signals. The current provided for external
signals, the period of clocks and the raising/falling
edges are the major points which has been nursed.
For application that never (or temporarily)
requires external memory resources, the ALE
buffer can be disable.
Once the oscillator is started, the gain is reduce
by 2 (6 dB).
Peripherals receiving XTAL clock have, each
one, their own prescaler to produce the operating
clock they need.
The output buffers are especially designed to
control rising and falling edges.
MATRAMHS
Rev. D (14 Jan. 97)
II.11.7
Preview
B
TEMIC
TSC8051A30
Semiconductors
CMOS Single Chip 8-bit Microcontroller with VAN
Controller
Description
The TSC8051A30 is a stand alone, high performance
CMOS microcontroller designed for use in automotive
and industrial applications.
The TSC8051A30 retains all features of the MHS 8OC51
with extended ROM capacity (16K bytes), 256 bytes of
RAM, a 100source 2-level interrupt, a full duplex serial
port, an on-chip oscillator and clock and two 16 bits
timers.
In addition, the TSC8051A30 has an 8-bit 8-channel
AID converter, a serial peripheral interface compatible
with SPI, a high security watchdog, an advanced 8
channel Capture and Compare timer Unit, a VAN
network line controller with a 128 bytes extra RAM used
to store the VAN messages.
The VAN controller is fully compliant with the ISO
standard ISO/I1519-3. It implements all features of the
TSS461C VAN data link controller, including a 128
bytes data dual port RAM to store the received and
transmitted messages.
The fully static design of the TSC8051A30 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The design is done with a specific care to reduce EMC
emission and suceptibility.
This circuit is manufactured using SCMOS process and
is available in commercial, industrial, military and
automotive ranges; it runs from 0 up to 20 MHz in the
automotive temperature range -40°C to + 125°C.
Features
•
•
•
•
•
•
•
•
256 bytes of RAM
16 K bytes of ROM or OTP
Four 8-bit I/O ports ; each bit can be:
• TTLI/O
• Push-pull output
• CMOS input trigger with or without pull-down
Two 16 bit timerlcounter
A programmable window watch-dog with
integrated low power RC oscillator; basic period 20
ms typical, maximum period 128 times 20 ms
A eight channels 16 bits Capture and Compare Unit
with:
• input capture
• output compare and PWM
A 8-bit resolution analog to digital converter with
eight multiplex inputs; conversion time 48 machine
cycles.
One port with programmable interrupt for keyboard
function
•
•
•
•
•
•
Several power reduction modes with enhanced wake
up capabilities
Power fail detection, Power on reset bit
Full duplex UART compatible with standard 8OC51
A serial peripheral interface (SPI+MW)
VAN controller with 128 bytes data RAM
• Fully
Compliant
with
VAN standard
ISO/11519-3.
14 Identifier Registers with all bits individually
maskable
I Mbitsls Maximum Transfer Rate
• 3 Separate line inputs with automatic diagnosis
and selection
• Idle and sleep modes
• Manchester Enhanced or Impulsed Coding
PQFP, PLCC or SSOP 44 package ; PQFP 64 for
emulation
II.12.1
MATRAMHS
Rev. E (14 Jan. 97)
Preview
2
TEMIC
TSC8051A30
Semiconductors
Block Diagram
.;!;
~ ~
!j
~
~ ~
~ ~
-< -< -<
~
;.
;. ;.
~
-<
-------_#- --
tl
O;l
B
U
O~~
'"'"
~ou
::;:'"
. ~~~
~
;. ;. ;. ;.
XTALl
XTAL2
RAM
256x8
EPROM
16Kx8
ALE!
PROG
PSEN
EAlVpp
RD
Power
Key
Monitor
Board
WR
- - - - - - - - - - - - - - - - - (0) -
(1): Alternate function of Port 1
(2): Alternate function of Port 2
(3): Alternate function of Port 3
(0): Alternate function of Port 0
Figure 1. TSC8051A30 Block Diagram
11.12.2
MATRAMHS
Rev. E (14 Jan. 97)
Preview
TEMIC
TSC8051A30
Semiconductors
Pin Configuration
OJ
0
0
0
X
X X
~, a:I a:I a:I
z z z en
en
en z
:!i
INDEX
CORNER
'0:"
~ ~ ~
0:
gz
0: 0: 0:
0
III
()
".. .~
z
'"0
co
OJ
III
OJ
III
¥
'"0OJ
Cl '"
0
1§ ~ ~ ~
'"
0;
IL
'"
0;
IL
0
IL
0
IL
PO.4JAD4IKB4
PO.5IAD5IKB5
PO.61AD6IKB6
PO.7IAD7IKB7
ENVPP
VSS
TSC8051A30
ALEIPROG
PSEN
P2.71A 151CCU71ECI
P2.61A14ICCU6
P2.5IAl31CCU5
:II ~ ~ -'
z z i'! i'!
I~ I~a: x x
~
'"
IL
;:::
~
:;
()
~ (jl
0
::J
()
.
'~"
~
~
'" ...
g g (;l
~ ~ ~
OJ
::J
::J
()
()
~
OJ
IL
~
()
::J
II.l2.3
MATRAMHS
Rev. E (14 Jan. 97)
Preview
TEMIC
TSC8051A30
40
2
41
Semiconductors
PI.ONAN_RXO
VANRXO
18
24
P2.0/A08/CCUO
Address bus high order or
CCU module I external I/O
Pl.lNAN_RXI
VANRXI
19
25
P2.11A09/CCUI
Address bus high order or
CCU module I external I/O
42
4
P1.2NAN_RX2
VANRX2
20
26
P2.21AIO/CCU2
Address bus high order or
CCU module 2 external I/O
43
5
P1.3NAN_TXO
VANTXI
21
27
P2.3/A11/CCU3
Address bus high order or
CCU module 3 external I/O
44
6
P1.4/MISO
SPI master in ,slave out
22
28
P2.4/A I 2/CCU4
Address bus high order or
CCU module 4 external I/O
7
P1.5IMOSI
SPI master out, slave in
23
29
P2.5IA13/CCU5
Address bus high order or
CCU module 5 external I/O
P1.6/SCK
SPI serial clock I/O
24
30
P2.6/A14/CCU6
Address bus high order or
CCU module 6 external I/O
9
P1.7/SS
SPI slave select
25
31
P2.7/A I 5/CCU71
ECI
Address bys high order or
CCU module 7 external I/O
or CCU count input
13
P3. IffXD/ANA I
Serial transmit port or
Analog Input I
29
35
EANPP
External access
enable!Programming supply
voltage
14
P3.2lINTO/ANA2
External interrupt 0 or
Analog Input 2
30
36
PO.7/AD7/KB7
Mux. low order address &
data bus or Keyboard
9
15
P3.3/INTIIANA3
External interrupt 1 or
Analog Input 3
31
37
PO.6/AD6/KB6
Mux. low order address &
data bus or Keyboard
10
16
P3.4ITOIANA4
Timer/counter 0 input or
Analog Input 4
32
38
P0.51AD5/KB5
Mux. low order address &
data bus or Keyboard
11
17
P3.5ff1/ANA5
Timer/counter 1 input or
Analog Input 5
33
39
PO.4/AD4/KB4
Mux. low order address &
data bus or Keyboard
12
18
P3.61WR1ANA6
External data memory write
strobe or Analog Input 6
34
40
PO.3/AD3/KB3
Mux. low order address &
data bus or Keyboard
13
19
P3.7IRD/ANA7
External data memory read
strobe or Analog Input 7
35
41
PO.21AD2/KB2
Mux. low order address &
data bus or Keyboard
14
20
XTAL2
Crystal output
36
42
PO. 1/ADlIKB 1
Mux. low order address &
data bus or Keyboard
IS
21
XTALI
Crystal input
37
43
PO.O/ADO/KBO
Mux. low order address &
data bus or Keyboard
2
7
MATRAMHS
Rev. E (14 Jan. 97)
11.12.4
Preview
TEMIC
TSC8051A30
Semiconductors
Pin Functions
XTALI
XTAL2
EAJVpp
ALEIPROG
I
2
!
' f PORTO
PSEN
RESET
S
6
7
ANAVcc
ANAVss
AVREF+
ANAO
ANAl
ANA2
ANA3
ANA4
ANA5
ANA6
ANA7
~ RXD
TXD --:--+
+----:INTO
INTI
TO
§f
I
2
Of
3
4
PORT 1
56
TJ
WR ~
RD . . . - -
7
I
2
Of
3
4
PORT 2
S
6
7
~~
AD!
AD2
~
i
ADS
AD6
AD?
Low
order
address
& data
bu,
~
KBO
KBI
KB2
KB3
KB4
KBS
KB6
KB7
VRXI
VRX2
VRXO}
VTXO
MISO
VAN
MOSI} S~UmWIRE
mterface
SCK
SS
~A8
A9
AIO
All
Al2
A13
A14
A15
High
order
address
bu,
~
CCUO
CCUI
CCU2
CCU3
CCU4
CCUS
CCU6
CCU7/ECI
" ' - - - - - - - 44-pin package
Figure 2. TSC8051A30 pin functions
II.12.5
MATRAMHS
Rev. E (14 Jan. 97)
Preview
TEMIC
TSC8051A30
Semiconductors
General Signal Description
Vss
Program Store Enable is the read strobe to external
program memory, else it remains high. PSEN can sink
and source 8 LS TTL loads.
Digital ground
Vee
Digital supply voltage
PORTO
Port 0 can act the part of address/data bus or standard 110
port. Its dedicated alternate function are the inputs of the
keyboard interrupt. In the default configuration, port 0
operates the same as it does in the 80CSl, with
open-drain outputs.
ANAVss
Analog groundl
ANAVee
Analog supply voltage
PORTl
EA/Vpp
Port 1 can act the part of standard 110 port. This port has
two dedicated alternate functions:
External Access enable must be strapped to Vss in order
to enable any device plugged on port 0 / port 2 to fetch
code from 0 up to 16K. EA must be strapped to Vcc for
internal program execution.
This pin also receives the 12V programming supply
(Vpp input) to program the internal EPROM.
XTALl
It is the input to the inverting oscillator amplifier and the
input for external clock generator.
XTAL2
It is the output from the inverting oscillator amplifier.
RESET
eP.l[O:3] for VAN (Vehicle Area Network) interface.
ep.l[4:7] are for synchronous serial link (SPI or
mWIRE) interface.
In the default configuration, port 1 operates the same as
it does in the 80C51, with internal pullups. Port 1 type
C51 is sometimes called "quasi-bidirectional" due to the
internal pullups.
PORT 2
Port 2 can act the part of address bus or standard 110
port.lts dedicated alternate function is the CCU (Capture
& Compare Unit) interface.ln the default configuration,
port 2 operates the same as it does in the 80CSl, with
internal pullups.
PORT 3
The active level of the RESET pin is low. An active level
on this pin, while the oscillator is running, resets the
device. An internal resistor permits power-on reset only
using an external capacitor. The reset pin is
bidirectional; it acts as an output when a reset is issued
by the watch-dog function.
ALE I PROG
The Address Latch Enable output signal is used to latch
the low order byte of the address during accesses to
external memory. ALE can sink and source 8 LS TTL
loads.lf desired, ALE buffer can be disable. Then, ALE
is pulled low. This pin is also used (program pulse input)
to program the internal EPROM.
Port 3 can act the part of standard 110 port. This port has
two types of alternate functions:
• The first ones are the same than in C51 (Rxd, TxD,
... , WR,RD),
• The second type of alternate functions are 8 inputs
for the 8-bit AID converter.
In the default configuration, port 3 operates the same as
it does in the CSl, with internal pullups. Port 3 type C51
is sometimes called "quasi-bidirectional" due to the
internal pullups.
AVREF+
•
Positive reference voltage for the ADC module.
11.12.6
MATRAMHS
Rev. E (14 Jan. 97)
Preview
TEMIC
TSC8051A30
Semiconductors
Electro-Magnetic Compatibility (EMC)
Primary attention is paid to the reduction of
electro-magnetic emission of the TSC80S1A30. The
following features reduce the electro-magnetic emission
and additionally improve the electro-magnetic
susceptibility:
• The TSC80SIA30 provides one analog supply
voltage pin and one analog ground pin. Placed on the
middle of one side of the package. this pair
(ANAVcc/ ANAVss) has short bounding wires. thus
reducing the generated noise.
In order to reduce the radiation loop area, the two
pins are adjacent.
• The TSC8051A30 provides one group of digital
supply voltage and digital ground, in pairs of pins
(Vss/Vcc). Placed on the middle of the sides of the
package, this group have short bounding wires, thus
reduces the generated noise. In order to reduce the
radiation loop area, pins are adjacent inside group.
• External capacitors should be connected across
associated pins (ANAVcc/ANAVss or Vcc/Vss).
Lead length should be as short as possible. Ceramic
CMS capacitors are recommended, IOnF + IOOnF.
•
•
Several internal decoupling capacitors improve the
EMC radiation behaviour and the EMC immunity.
In order to reduce the spectrum of the TSC8051 A30,
many signals has been treated, principally the
periodic signals. The current provided for external
signals, the period of clocks and the raising/falling
edges are the major points which has been nursed.
For application that never (or temporarily)
requires external memory resources, the ALE
buffer can be disable.
Once the oscillator is stable, the gain is reduce by
2 (6 dB).
Peripherals receiving XTAL clock have, each
one, their own prescaler toproduce the operating
clock they need.
The output buffers are especially designed to
control rising and falling edges.
II.12.7
MATRAMHS
Rev. E (14 Jan. 97)
Preview
II
TEMIC
Semiconductors
Section III
cst Application Notes
ANM031 : Secret Tag on 80C51 Family Microcontrollers ...........•.•.••••••..• 111.1.1
ANM032 : How to use a Third Overtone Crystal
with a 80C51 Family Microcontroller .••••.•.•..•.....•.........•........•.•. JII.2.1
ANM033 : How to Read Out the Internal Memory Code
of a 80C51 Microcontroller Family .•.••••.•.•.......••..•......•............ 111.3.1
ANM034 : Compatibility between 80Cx2 and 8xC154 Microcontrollers .•.•••.•...• 111.4.1
ANM053 : Encryption on 80C51 Family Microcontrollers •.••.•••.••••..•••••..• 111.5.1
ANM055 : How to Get a Second Asynchronous Serial Interface
on a 80C51 Microcontroller Family ••.•••.••••..•••••••.••.•.•.••••..••••...• 111.6.1
ANM059 : How to Recognize Video Mode and Generate Free Running
Synchronization Signals Using TSC8051C1/C2 Microcontroller ..•..•.....•...... 111.7.1
•
TEMIC
ANM031
Semiconductors
Secret Tag on 80eS1 Family Microcontrollers
Overview
The Secret Tag is a feature which allows serialization of
each microcontroller for identification of a specific
equipment.
permits personalization of any electronic equipment
using a 80C51 architecture.
The coding of the different registers allows TEMIC to
guarantee that each value of the Secret Tag is UNIQUE.
For instance, on a network, each terminal equipment can
be identified by comparing the identifier sent via network
with the identification number stored in the
microcontroller.
For confidentiality on secret tag value, no special
marking is written neither on the die nor on the final
package. This value can be read out by classical
instruction set routine. This routine is implemented inside
the microcontroller ROM memory which can be kept
secret (and then the value of the secret tag also) by using
a ROM ENCRYPTION.
One unique number per device is implemented. This
serial number is a 64-bit binary value, which is contained
and addressable in SFR (Special Function Registers) area.
This value can be used as an identification number, and
Description
The secret tag register is composed of two groups of four
consecutive bytes in the Special Function Register (SFR)
area. One is placed at the FCh to FFh addresses and the
other at the ECh to EFh addresses.
•
These registers are used as follows:
• Lot number (LO-Ll5) : number from 0 to 65535
referring to TEMIC fab lot number.
• Lot Number Extension (EO-E3): = 0
A
=1
o
= 15
ADDRESS
b7
Customized number (CO-C 11) : fixed number from 0
to 4095 given by the customer.
•
Year (YO-Y3): 1994 is 0,1995 is I, and so on.
•
•
•
Month (MO-M3) : number from 1 to 12.
Wafer Number (WO-W7) : number of Wafer.
Serial Number (SO-SI5) : number from 0 to 65535
incremented step by step.
b6
b4
b5
bl
b2
b3
bO
TAGl
ECh
IL7
I L6
I LS
I L4
1L3
1L2
ILI
ILO
TAG2
EDh
I LIS
1L14
1L13
I LI2
ILll
ILIO
IL9
I L8
TAG3
EEh
I C3
I C2
ICl
I co
IE3
I E2
lEI
I EO
TAG4
EFh
I Cl1
IClO
I C9
I C8
I C7
I C6
I CS
IC4
TAGS
FCh
IY3
I Y2
I Yl
Iyo
1M3
1M2
IMI
IMO
TAG6
FDh
IW7
IW6
Iws
IW4
IW3
IW2
IWI
Iwo
TAG7
FEh
I S7
I S6
Iss
I S4
I S3
I S2
lSI
I SO
TAG8
FFh
I SIS
I S14
IS13
I S12
I Sl1
I S10
I S9
I S8
MATRAMHS
Rev. D (14 Jan. 97)
IILl.1
TEMIC
ANM031
Semiconductors
•
•
Lot Number
Lot Number Extension
= 1025
•
•
Production Year
Production Month
= 1995 (1)
=2
•
Customized Number
=0
•
Serial Number
= 291
= August (8)
80eS1 Routine to Read Out the Secret Tag
The eight secret tag registers are mapped into 80C51 SFR area (Special Function Registers). The routine listed hereafter
reads the Secret Tag Registers and sends it on the serial data link.
Main_Program:
========= UART Initialization ==============
Mov
SCON, #53H ; 8-bit UART Variable/REN
1
TI / RI =1.
Mov
TMOD, #20H ; 8-bit auto-reload mode for
baud rate generator.
Mov
TH1, #OE8H ; 1200bds at 11.059MHZ.
Setb
TR1
Somewhere in the program the routine is
called to transfer the Secret tag registers.
Call
========= Character Sending Routine
Send_Char:
Jnb
TI,$
Clr
TI
Mov
SBUF,A
test if the transmitter is free to
send a new character.
send the new character.
Ret
======== Secret Tag Transfer Routine =========
Secret_Tag_Transfer:
Mov
A,TAG1
Call
Send_Char
Mov
A,TAG2
Call
Send_Char
Mov
A,TAG3
Call
Send_Char
111.1.2
MATRAMHS
Rev. D (14 Jan. 97)
TEMIC
ANM031
Semiconductors
Mov
A,TAG4
Call
Send_Char
Mov
A,TAG5
Call
Send_Char
Mov
A,TAG6
Call
Send_Char
Mov
A,TAG7
Call
Send_Char
Mov
A,TAG8
Call
Ret
Send_Char
II
0
+5 V
"
u
31
lEA
9
RST
11
10
ITXD
;;
C3
IRXD
80eS1
MAX233
12
CI
27pF
~Q'
-=-
12MHzD
19
18
P3.2
XTALI
P2.7
P2.6
P2.5
P2.4
P2.3
P2.2
P2.1
P2.0
PO.7
PO.6
PO.5
PO.4
PO.3
PO.2
PO.I
PO.O
P3.3
28
27
Pl.7
Pl.6
Pl.5
PI.4
P1.3
P1.2
Pl.l
PI.O
C2
27pF
Additional Information
For additional information on Microcontrollers, and
Ordering Information, please refer to the product
datasheets available upon request.
MATRAMHS
Rev. D (14 Jan. 97)
111.1.3
TEMIC
ANM032
Semiconductors
How to use a Third Overtone Crystal with a soCst Family
Microcontroller
Description
For cost reason using an overtone crystal is 5 to 6 times
cheaper than a fundamental one. Using this type of crystal
is slightly different comparing to a fundamental one. The
frequency of an overtone crystal is adjusted on the
fundamental one and this one must be trapped by a LC
pass-band filter. The typical schematic is shown below.
CPl and CP2 are the parasitic capacitors due to the
packaging and the PCB lay-out. L1 and Cl is the
iT
=
~Q
passe-band filter used to trap the fundamental frequency.
C2 is a small capacitor to increase a little bit the
open-loop gain given by:
A x B = A x CP2 + C2
CPl
where A is the gain a the operating frequency and B is the
gain of the feed-back. The frequency of the filter is given
below:
1
L=
1
(2
X 3l
II
= 36.:64 = 12.288 MHz
x 12.288
X
1 6
10 )
Where C3 = 33 pF
X
(39
X
10
12)
=43H
. Ii
The standard one is 4.7J..lH and not critical because the
bandwidth is large enough . C2 is chosen to be equal to
lOpf (a larger value break-down the amplifier and the
open loop gain) .
CPl
CP2
T
T
L....---I0 I---.L--r---.
Q = 36.864MHZ
C2
Ll
C3
T
Figure 1. Typical application with a third overtone crystal
MATRAMHS
Rev. D (14 Jan. 97)
III.2.1
TEMIC
ANM033
Semiconductors
How to Read Out the Internal Memory Code of a socst
Microcontroller Family
Overview
A single chip microcontroller is a controller with a ROM
memory storing the program code of the specific
application. The program is masked during the
processing of the integrated circuit. The great advantage
is that no 110 ressource is consumed to interface the
external code memory. 110 line possibilities consequently
are increased.
This application note describes a solution to dump the
internal ROM and is based on a specific TEST MODE
(TEST MODE VER) used to test the microcontroller in
production.
In this note a member of TEMIC's 80CSI family will be
named 80Cxxx .
In order to test or to check this internal ROM, some
solutions can be implemented.
TEST MODE VER to dump the ROM
The TEST MODE VER can be used by setting some
80Cxxx inputs shown in figure I . The PORTs PI and P2
receive respectively the low address lines and the high
address lines. The code program in that condition is read
from PO . The lines of PORTO is open drain and must be
tied with lOkohm pull-up resistors.
+5V
+5V
EA
10 Kohms
ALE
PSEN
PO.7
PO.O
D7-DO
P3.6
P3.7
Reset
RST
Al5-A8
P2.7
P2.0
A7-AO
Pl.7
PI.O
Xta12
T
Xtall
T
Figure 1. Configuration for the TEST MODE VER
To activate and to dump the ROM a specific timing must
be applied, it is shown in figure 2.
Before generating the first Read cycle a delay at least
equal to 24 clock periods has to be waited. This time is
needed to reset correctly the 8OCxxx. At this time the first
MATRAMHS
Rev. B (14 Jan. 97)
address is read by the 80Cxxx from the PORT 1 and 2. To
read the first data it is necessary to wait again 12 clock
periods. This is due to the internal synchronisation and the
internal ROM access time. So the data only appears 36
clock periods after the reset is applied.
111.3.1
11
TEMIC
ANM033
Semiconductors
I1 f \ J V V V \ 1
XTAL2
(\J\J\JV\J\
----------------
~------------~~I
Reset
ALE, PSEN, P27--6
------r-------~~I------------------r-------~~I-------------
------r-------~~---,r-------~
A.x-AO _ _ _ _+-_..:.AD=R::;:O_ _ ~
ADRI
~
lreset> 24 clock periods
D7-DO _ _ _ _
ADR2
tread> 12 clock periods
- - "D~/'i. : :;I:. :;f\X: . . _ ~ ~:____...JX
DATAO
~ ~,--_ _ _D: :;/'i.:. :.T: :;f\~I_ ___
Figure 2. Timings to dump the ROM
Example Dump ROM Application
Figure 3 shows the schematic of this typical application
using a 87C51 (01P version). The main idea is to control
the 80Cxxx by another one in order to generate all the
signals we need and to output the dumped data on a serial
line or to trace the dumped data on PORTO with a logical
analyser.
0
.".
+5V
31
lEA
C3
9
RST
11
ITXD
IRXD
ALE
lEA
80Cxxx
12
TRIG
P3.2
XTALI
18
IPSEN
9
CI
27pF
~
C,.!D
C2
27pF
19
XTALI
P3.7
18
P3.6
~ ~----~~-----~~
Figure 3. Typical application
111.3.2
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
ANM033
Semiconductors
Flow chart of the program
Figure 4 shows the flow chart of the program .The
program starts with the serial line configuration
(2400bds, 8-bit of data) and the set-up of target 80Cxxx
for the DUMP operation. Then read operation of the ROM
is performed and the read data is transmitted on the serial
line. In the same time, the TRIG signal is active low to
synchronize an external logical analyser.
Serial Line, Dump set-up
Read Operation of the ROM
Transmission of the data
Trigger for the logical Analyse
II
Same Operation for the entire ROM
Figure 4. Flow chart for the dump ROM program
Subroutine of the Initialization Sequence
;=== initialization ==============================
Speed = 2400bds , Format = 8 bits
;=======================================
;---Set-up the Baud Rate Generator--------------SetB
Target under Reset
MOV TMOD,#Baud_Rate_Timer
TIMERl = 20H
MOV TH1,#Speed
Speed = OF3H
Setb TRl
;------Set-up the UART-----------------------MOV SCON,#FORMAT
FORMAT =42H
;===ROM Dump operation Set-Up==============
Size_Rom = 4095 bytes
MOV DPL,#OO
MATRAMHS
Rev. B (14 Jan. 97)
starts with first address
III.3.3
TEMIC
ANM033
Semiconductors
Subroutine of the dump ROM operation
;===ROM Read Operation====================
Dump operation:
MOV PO,DPL
Address of the Read
MOV P2,DPH
CLR
Trig
Analyser TRiggering
MOV A,Pl
Call Serial trans
Serial transmission
SETB Trig
INC DPTR
Next address
MOV A,#Size_ROM_Low
CJNE A,DPL,Dum_operation
MOV A,#Size_ROM_High
CJNE A,DPH,Dump_operation
JMP $
Serial trans :
JNB TI,Serial_trans
CLR TI
MOV SBUF,A
RET
Timings analysis
Two parameters are critical in the dump ROM application
(figure 2) : treset and tread.
Treset parameter is the minimum time required from the
active Reset to the output of the first data. The minimum
value of this parameter is 24 clock periods.
In this application, the first data appears 168 clock
periods after the first address.
To determine when data coming from the ROM can be
read, tread parameter must be taken into account.
The minimum value of this parameter is 12 clock periods
measured when the address is stable and the data can be
read.
In this application, tread will be read 72 clock periods
after the address is driven. So, both of the parameters are
not critical .
Conclusion
This application based on a TEMIC piggy-back is easy
to implement and requires only few components.
Furthermore this basic application can be improved by
adding a software interface developed on a Personal
Computer to compare the dumped ROM and the original
one.
Additional Information
For additional information on Microcontrollers, and
Ordering Information, please refer to the product
datasheets available on request.
III. 3.4
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
ANM034
Semiconductors
Compatibility between 80Cx2 and 8xC154 Microcontrollers
Description
An application based on 80C52/80C32 can be replaced by
83CI54/80CI54 if some precautions have been taken in
order to not activate special features of the 8XCI54
contained in one common register. This note gives details
about the differences.
Features
The 8XCI54 is an enhanced version of the 80C52/80C32.
The main differences are mainly due to Internal Program
memory, the Power-Down mode, the serial link and the
Programmable port impedance.These differences are
summarized in Table 1.
Table 1. Main Differences Between Microcontrollers
'·:·'n'··.·,·· ,)re;:lt9;t!!S :
.. .' ........... ..... .'.,'.
'
'"
".'
ROM (80C52 & 83C154)
, ·~fC~2I$OCS2
..' ...... ,:; .~.
",
....
:,
'.
" ·81lClS4/S3eis4
",<,'t,::,
"",,,
'~:;i
' I ' -',
8 Kbytes
16 Kbytes
Frame Error Detection
No
Yes
Overrun Error Detection
No
Yes
Recover Mode
No
Yes
Hardware Power-Down Mode
No
Yes
Programmable 1/0 Port Impedance
No
Yes
,',
....
Programmable Port Impedance
The impedance of the port 1,2 and 3 can be programmed
in one of the three impedance modes through the laCON
register ( OF8H) shown in table 2. The impedance can be
normal, high or floating .This mode is not supported by
the 80C32/80C52 and a program written on
80C32/80C52 never accesses to this register.
Table 2. laCON register description
I/OCON (OF8h)
I/O Control register
MATRAMHS
Rev. B (14 Jan. 97)
WDT
T32
SERR
IZC
P3HZ
P2HZ
PlHZ
IZC=1
Set by software to select High impedance for Port I. 2 and 3.
When cleared, Port 1, 2 and 3 have a normal impedance.
PxHZ= I
When set by software. the Port (1. 2 and 3) become a floating input.
When cleared, the impedance is selected by IZC bit.
ALF=1
When set by software, all the Ports (1, 2 and 3) become floating when the
power-down mode is activated
ALF
III. 4. 1
TEMIC
ANM034
Semiconductors
Power Reduction modes There are basically four power
reduction modes in the SxC154:
•
•
•
Idle
Recover
Software
•
Hardware
All these modes are activated with the four bits
PD,HPR,RPD and IDL in the PCON register shown in
table 3.
.
The SOC52/32 has only two power reduction modes: Idle
and software power-down modes. All these modes are
controlled by the two bits PD and IDL in the PCON
register shown in Table 3.
Table 3. PC ON register description
peON (87h) register L..1_S_M_O_D---'_H_P_D_"-_R_P_D_-'-_ _ _-'-_G_F_l_-'-_G_F_O_"'--_P_D_-'-_I_D_l_-,
IZC= I
Set by software to select High impedance for Port I, 2 and 3.
When cleared, Port I, 2 and 3 have a normal impedance.
Power-Down Mode
Hardware Power Down Mode
This software mode is used to reduce to the minimum the
power consumption (50 i!A) . This mode is activated by
software by setting to one the bit PD in the PCON register
and the way to cancel it depends on the controller used:
• SOC32/S0C52: Only a hardware reset can cancel this
mode.
• SXC154: A hardware reset or an external interrupt
(INTO or INTI) can cancel this mode.
This mode allows to control the Power-Down mode by an
external signal through the TI pin (P3.5). When a falling
is applied on this pin and if the HPD bit of the PCON
register is set to one, the controller stops the clock and
goes in power-down mode. A rising edge on TI pin
awakes the controller, restarts the oscillator and the
execution of the program. This mode works
independantly of the software mode. This mode is not
supported by the SOC52/S0C32 part and is an
enhancement of the SXC154.
Idle Mode
This mode is used to reduces the power consumption
down to 25% of the nominal consumption and to maintain
a minimum of CPU activities (TIMER/COUNTER,
UART). This mode is activated by setting to one the bit
IDL in the PCON register.The way to cancel it can be
done either by an hardware reset or by all the interrupt
request sources.
Recover Mode
Overrun and Frame Errors
These errors are detected when a problem has been
detected on the serial link. If it is the case, the SERR bit
in the IOCON register is set to one. The overrun error
occured when a new character is received and overwrites
the last one which has not been read. The frame error
occurs when the length of the data received is not correct
(a stop bit is missing). This mode is supported by the
SOC32/S0C52 .
This mode is used only on the SXCI54 and is enabled by
setting to one the bit RPD in the PCON register. This
mode controls the way to cancel the power reduction
mode (Power-Down and IDLE) and can be either an
hardware reset or external interrupt requests (INTO and
INTI). The RECOVER mode allows two ways of
cancelling mode :RPD = 0 , the power reduction mode is
cancelled by the external interruptions only if they are
enabled (EXO=l, EXI=I in IE register) , RPD = I , the
power reduction mode is cancelled even if the external
interrupts are disabled and if there is an interrupt request.
This mode is not supported by the SOC52/S0C32 part
and is an enhancement of the SXC154.
111.4.2
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
Semiconductors
ANM034
Conclusions
Replacing a SOC32/S0C52 by a SXCl54 can be done
easily but the programmer must take care of the
RECOVER mode and the HARDWARE power--down
mode, which are not to be set in the program. If no
precautions are taken, the application can be disturbed as
detailed below:
• Hardware mode: If a rising edge is applied on pin TI,
the controller will enter in power-down.
• Recover mode: If the RPD bit is set to one and if the
PD bit is set to one as well, the controller will enter in
power-down mode and will be cancelled as soon as an
interrupt request will be set. If an interrupt is pending,
the power-down will be cancelled immediately. In
that case it looks like the power-down mode has never
been executed.
All other differences will be transparent for the software.
Additional Information
For additional information on Microcontrollers, and
Ordering Information, please refer to the following
datasheets available on request.
II
MATRAMHS
Rev. B (14 Jan. 97)
IlIA. 3
TEMIC
ANM053
Semiconductors
Encryption on 80eS1 Family Microcontrollers
Introduction
TEMIC provides a hardware encryption mechanism in
order to protect the program memory against piracy.
For this purpose, an encryption array is scrambled within
the ROM matrix.
This array is programmed by the factory at the same time
as the program memory, its content being different for
each application, and is totally secure from outside.
The size of the encryption array depends on the size of the
ROM matrix :
• 128 bytes for 80C5l
•
•
•
256 bytes for 80C52
512 bytes for 83C154
1024 bytes for 83C154D
When the internal code is read out at a given address, this
address selects one byte of the ROM memory map and
one byte of the encrypted array following an algorithm.
These two bytes are combined to create an encrypted byte
at the output port.
This will be reproduced for each address.
Design Considerations
When the program verification is performed, or when
MOVC instructions are executed from external memory
for accessing internal memory, each byte of internal ROM
is exclusive-nor'ed with an encryption byte, in order to
provide on Port 0 an encrypted byte.
The algorithm for selecting one encryption byte uses a
combinaison of the internal memory address lines :
•
•
•
•
7 address lines for 80C51
8 address lines for 80C52
9 address lines for 83C154
10 address lines for 83C154D
Readout
encrypted code
ROM
Code
4 Kbytes
8 Kbytes
16 Kbytes
32 Kbytes
MATRAMHS
Rev. D (14 Jan. 97)
Encrypted
Array
Internal
adelress bus
128 Kbytes
256 Kbytes
512 Kbytes
1024 Kbytes
III.5.1
II
TEMIC
ANM053
Semiconductors
Adding Features
The External Access pin (EA) is sampled and latched on
RESET, and any further switching of this pin is not
recognized,
It is always possible to use external memory, but the state
of EA during RESET will ascertain what is enabled.
• EA=O
• Code memory is exclusively external
• MOVC instructions access external ROM and
return non encrypted data.
•
EA= 1
• Code memory is internal for the lower 4K, and
external for the upper bytes for SOC51 (limit is SK
for SOC52, 16K for S3C154 and 32K for
S3CI54D).
• MOVC instructions in external ROM code that
access internal ROM return encrypted data.
This ensures full protection of ROM content, as detailed
in the table below:
Table 1. Use of MOVe intruction to access data in ROM code.
0
<4K
<4K
Internal
Internal
Internal fetches during internal MOVe instruction:
data not encrypted
<4K
>4K
Internal
External
External fetches during internal MOVC
instruction: data not encrypted
>4K
<4K
External
Internal
Internal fetches during external
instruction: data encrypted
>4K
>4K
External
External
External fetches during external MOVe
jnstruction: data not encrypted
X
X
External
External
External fetches during external MOVC
instructions: data not encrypted
Move
* : 4K value is for 80C5!. Replace by 8K for 80C52, by 16K for 83Cl54D and by 32K for 83C154D
Additional Information
For additional information on Microcontrollers, and
Ordering Information, please refer to the product
datasheets available upon request.
III.5.2
MATRAMHS
Rev, D (14 Jan. 97)
TEMIC
ANM055
Semiconductors
How to Get a Second Asynchronous Serial Interface
on a 80eS1 Microcontroller Family
Receiver part:
Description
The SOC51 family has only one asynchronous serial
interface.
However some users would like to have a low cost
solution to get two in their applications.
This solution exists and is described in this application
note.
The goal of this note is to present a very low cost software
solution to realise this second asynchronous serial
interface.
Features
No external hardware added;
On each TIMER 1 overflow interrupt, RxD input is
sampled. Start of transmission is recognised by a
transition of I to 0 on this pin. So a second sample is made
half a bit later to be sure that it is a start bit. Then sampling
is made in the middle of the received bits, nine times to
get the S data bits. The stop bit must have level I.
Transmitter part:
The operation of the transmitter is nearly the same as for
the receiver: start bit is written on TxD output followed
by the 8 data bits and the stop bit and so on. Time of bit
writing is calculated by counting timer interrupts.
Efficiency
Full duplex;
Dissymetrical baud rate in reception and in transmission
available;
Number of
sub-routine:
1200 bauds limitation of the internal serial interface
(hardware).
•
•
Resources used
The measures hereafter have been done with a
11.059MHz crystal, and same baud rate in emission and
in reception, and a hardware serial baud rate of 1200
bauds.
A time reference with interrupt capability is needed and
it can be TIMER 1 even if it is already used as baud rate
generator for the internal serial interface. In this case a 32
time speed transmission is obtained on TIMER 1
overflow (TIMER I is in mode 2 : 8-bit auto-reload, and
serial interface is in mode 1 : S-bit variable baud rate).
Only two I/O pins are needed: one for RxD and one for
TxD (for instance P 1.0 and Pl.1). Few bytes of memory
are used and finally a portion of the CPU time is used to
serve TIMER 1 interrupt. Three functions: initialisation,
transmission and reception, are allowed to use this serial
interface.
Method
Transmission
of
the
machine
cycles
spent
10
interrupt
Minimum: 10 cycles ;
Maximum: 49 cycles (transmission and reception) ;
Percentage of CPU usage:
•
•
41.7% if there is no traffic;
50% with continuous transmission or reception, and
1200 baud rate;
•
57.4% with continuous transmission and reception,
and 1200 baud rate;
•
6S.5% with continuous transmission and reception,
and 9600 baud rate.
The hardware serial baud rate is limited to 1200 bauds,
increasing it induces an increase of TIMER 1 interrupts
frequency, and so an increase of percentage of CPU
usage.
character
OlOOOOOlb 'A'
""~st'ari
~t
I
I
I
I
stop
Sample points
MATRAMHS
Rev. B (14 Jan. 97)
III. 6. 1
II
ANM055
TEMIC
Semiconductors
Demonstration Program
The demonstration program (listed in the following
pages) allows transmission on Pl.l of all characters
received on Pl.O without checking receive error.
The function TXD_S starts transmission of the character
placed in accumulator when the transmitter is ready.
The function RXD_S waits for reception of a character
and return it in accumulator.
Additional Information
For additional information on Microcontrollers, and
Ordering Information, please refer to the product
datasheets.
III. 6. 2
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
Semiconductors
ANM055
Program Listing
$TITLE (Software serial interface)
Software serial interface
with programmable speed
$NOMOD5l
$INCLUDE (reg5l.inc)
RSEG PROG
NAME UARTSOFT
Constant definition
RxDl
EQU
PI. 0
TxDl
PLI
EQU
Segment definition
PROG
SEGMENT CODE
VARI
SEGMENTDATA
BITVAR SEGMENTBIT
STACK SEGMENTIDATA
RSEG STACK
DS lOH
16 Bytes Stack
vectors definition
Reset vector
CSEG AT OOOOH
jmp MAIN
CSEG AT 00lBH
Timer 1 vector
jmp ITIM1
; bits definition
RSEG BITVAR
TXRDY: DBIT 1
1 if transmitter ready
RXRDY: DBIT 1
1 i f receiver ready
RXERR DBIT 1
1 if receiver error
INCOM: DBIT 1
1 if character received
; vars definition
RSEG VAR1
; Receiver
speed in reception
RXSPD: DS 1
RXCH:
DS 1
character in reception
internal counter
RXCNT: DS 1
receiver status
RXSTAT:DS 1
RXCH2: DS 1
last character received
; Transmitter
speed in transmission
TXSPD: DS 1
character in transmission
TXCH:
DS 1
internal counter
TXCNT: DS 1
TXSTAT:DS 1
transmitter status
software serial interface demonstration program
characters received on P1.0 are transmitted on Pl.l
RSEG PROG
; Main routine
SP,#STACK-1
MAIN:
mov
lcall SEINIT
interfaces init.
lcall RXD_S
LOOP:
lcall TXD S
sjmp LOOP
MATRAMHS
Rev. B (14 Jan. 97)
III.6.3
TEMIC
ANM055
Semiconductors
Initialize serial interfaces
desired speed is 32 for 1200 bauds, 4 for 9600 bauds
Oscillator frequency = 11.059 MHz
SEINIT:mov
mov
mov
mov
mov
mov
mov
setb
setb
setb
clr
mov
ret
TCON,#40H
TMOD,#20H
TH1,#OE8H
SCON,#52H
A,#32
RXSPD,A
TXSPD,A
PT1
TXRDY
RXRDY
RXERR
IE,#10001000B
Transmission of a character on TxD1
TXD_S: jnb
TXRDY, TXD_S
mov
C,P
mov
ACC.7,C
TXCH,A
mov
mov
A,TXSPD
rr
A
TXCNT,A
mov
mov
TXSTAT,#O
clr
TXRDY
ret
Timer 1 enabled
= 0 , mode = 2
1200 bauds
serial port mode 1
1200 bauds
CIT
; high priority It.
;transmitter ready
receiver ready
no error
It. timer 1 enabled
set parity
character to send
1 bit duration
1/2 bit duration
set counter
init. status
start transmission
Reading of the received character on RxD1
RXD_S: jnb
INCOM,RXD_S
mov
A,RXCH2
char. received
clr
INCOM
char. readed
ret
III.6.4
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
ANM055
Semiconductors
; Interrupt routine
RXRDY,RX1
ITIM1: jnb
; receiver not busy
jb
RxD1,TRANS
clr
RXRDY
push
ACC
mov
A,RXSPD
rr
A
RXCNT,A
mov
mov
RXSTAT,#O
pop
ACC
sjmp
TRANS
djnz
RXCNT, TRANS
RX1:
push
ACC
push
PSW
mov
A,RXSTAT
jnz
RX3
RxD1, ERRFRM
jb
RX2:
inc
RXSTAT
mov
RXCNT,RXSPD
sjmp
RX5
ERRFRM:setb
RXRDY
RXERR
setb
sjmp
RX5
cjne
A,#9,$+3
RX3 :
mov
C,RxD1
A,RXCH
mov
rrc
A
RXCH,A
mov
sjmp
RX2
RxD1 , ERRFRM
RX4:
jnb
RXCH2,RXCH
mov
setb
RXRDY
INCOM
setb
pop
RX5:
PSW
pop
ACC
TRANS:
; transmission part
TXRDY,TX5
jb
TXCNT,TX5
djnz
push
ACC
push
PSW
A,TXSTAT
mov
jnz
TX1
clr
TxD1
TXCNT,TXSPD
mov
TXSTAT
inc
sjmp
TX4
MATRAMHS
Rev. B'(14Jan. 97)
start bit ?
1 bit duration
1/2 bit duration
load counter
init. status
sample point ?
II
start bit OK (0) ?
receiver error
8 bits + stop bit
bit sampling
stop bit OK (1)
jnc
RX4
?
1 char. received
sample point ?
start ?
set start bit
ill.6.S
TEMIC
ANMOSS
TX1:
TX2:
TX3:
TX4:
TX5:
cjne
jnc
mov
rrc
mov
mov
mov
inc
sjmp
cjne
setb
sjmp
setb
mov
inc
pop
pop
reti
A,#9,$+3
TX2
A,TXCH
A
TXCH,A
TxDl,C
TXCNT,TXSPD
TXSTAT
TX4
A,#lO,TX3
TXRDY
TX4
TxDl
TXCNT, TXSPD
TXSTAT
PSW
ACC
Semiconductors
8 bits + stop bit
bit to send in carry
transmission of bit
init. counter
end of character ?
set stop bit
END
III.6.6
MATRAMHS
Rev. B (14 Jan. 97)
TEMIC
ANM059
Semiconductors
How to Recognize Video Mode and Generate Free Running
Synchronization Signals Using TSC8051CI/C2 Microcontrollers
Description
The TSC8051Cl
is an application specific
microcontroller for autosync monitor and digital control
application. It includes the TEMIC static 8-bit 8OC5l
CPU core with 8 Kbytes of ROM and 256 bytes of RAM,
l2x8-bit PWM channels, buffered HSYNC and VSYNC
outputs, a watchdog timer and a multimaster I2C
controller.
This application note describes how to automatically
recognize video mode by measuring the period and
polarity of horizontal and vertical synchronization
signals; it also explains how to generate free running
synchronization signal for burn-in purpose.
In the rest of the application note, the use of words Hsync
and Vsync means horizontal synchronization signal and
vertical synchronization signal respectively.
Typical Autosync Monitor Application
The introduction of the TSC8051Cl in CRT monitors
allows manufacturer and final user to get maximum
flexibility.
• Automatic parameters adjustment during factory
set-up.
• Auto-alignment capabilities.
• Saving of factory default parameters.
• Versatile frequency range up to 100KHz.
• More adjustment parameters are available to the user.
VIDEO
BOARD
Synchronization
Separator
~
•
•
Automatic video mode recognition that allows
automatic monitor adjustment to the values
previously saved by user.
On chip I2C bus controller allows Access bus
implementation and so monitor adjustment by the
PC's Keyboard.
Figure 1 shows a block diagram of a typical autosync
monitor designed with the TSC8051Cl.
Horizontal Deflection
Hshift: beam position
Hamp: picture amplitude
B
FJW: East/West pincushion
Hlin: S correction capacitors
TEST
11
1....!::::--'---I-t0f
Vertical Deflection
Vshift: beam position
Vamp: picture amplitude
Vlin: linearity
11Video Amplifiers
Of Brightness Contrast
*
ILCDPaneij
RlGIB cut-<>ff
RlGIB gain
White balance
KeyboardlDisplay
Figure 1. Autosync monitor block diagram with the TSC8051Cl
MATRAMHS
Rev.B (10 Jan. 97)
111.7.1
m
•
TEMIC
ANM059
Semiconductors
Hardware Description
TSC8051Cl implements some special features to allow
video mode recognition without adding any external
components.
• Special Hsync and Vsync inputs.
• V sync can generate an interrupt on either falling
or rising edge. As 8051 core samples inputs one
time per machine cycle, pulse duration less than
Tosc x 12 (If!s using 12 MHz crystal) are not 100%
detected. To allow Hsync pulses counting
(duration>150ns), pulses are lengthened up to 1
cycle period to be sampled by the 8051 core.
Figure 2 and Figure 3 show the VSYNC and
HSYNC input block diagrams.
• These features are programmable through EICON
SFR (address E4h).
INTOIVSYNC
IOL
Figure 2. INTONSYNC input block diagram
EICON SFR E4h
MSB
TOL
TOS
TaL
IOL
EICON.O
INTOIVSYNC input Level bit. Setting this
bit inverts INTOIVSYNC input signal.
Clearing it allows standard use of
INTOIVSYNC input.
TOS
EICON.l
TOIHSYNC input Selection bit. Setting
this bit allows short pulse capture.
Fosc
TOS
Figure 3. TOIHSYNC input block diagram
Clearing it allows standard use of
TO/HSYNC input.
TOL
EICON.2
TO/HSYNC input Level bit. Setting this
bit allows positive pulse capture. Clearing
it allows
HOP
HOE
HOS
VOP
VOE
vas
•
•
Special Hsync and Vsync outputs.
TSC8051Cl implements programmable Hsync and
Vsync outputs. User can disable and can invert these
outputs to provide good polarity to deflection stages.
• These features are programmable through SOCR SFR
(address E5h).
MSB
SOCRSFRESh
I
I
I vos I HOS I vOP I VOE I HOP
HOE
SOCR.O
HSYNC Output Enable bit. Setting this bit
enables the HSYNC signal.
HOP
SOCR.l
HSYNC Output Polarity bit. Setting this
bit inverts the HSYNC output.
VOE
SOCR.2
VSYNC Output Enable bit. Setting this bit
enables the VSYNC signal.
VOP
SOCR.3
VSYNC Output Polarity bit. Setting this
bit inverts the VSYNC output.
HOS
SOCR.4
HSYNC Output Selection bit. Setting this
bit selects the VSYNC output, clearing it
selects P3.5 SFR bit.
vas
SOCR.5
VSYNC Output Selection bit. Setting this
bit selects the VSYNC output, clearing it
selects P3.3 SFR bit.
III.7.2
Figure 4. HSYNC and VSYNC outputs block
diagram
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
Video Mode Recognition Description
V sync input is programmed to generate an interrupt each
time a falling edge appears on Vsync.
Vsync period measurement, Vsync polarity detection and
Hsync pulse counting are performed using Timer O.
Figure 5 shows the Timer 0 block diagram in mode I.
TO/HSYNC
__---Jt CIT
Interrupt
=I
TRO------------I
I
GATE
lNTOIVSYNC#
Figure 5. Timer/Counter 0 in mode 1: 16-bit Counter
The measurement cycle is divided in 3 operations (3
Hsync frames):
•
•
Vsync polarity detection:
In the second interrupt of the cycle, timer 0 is
programmed to be used as gated timer with foscll2
clock. GATE bit is set and timer counts only during
Vsync high level. In the third interrupt, TRO bit is reset
to stop counting. At this time, THO and TLO registers
contain a representative value of the V sync high level
duration (in /-!s if l2MHz crystal is used). If this
duration is higher than the Vsync period divided by 2
then, Vsync has a negative polarity else it has a
positive polarity (see Figure 7).
Timer 0 is reset and Vsync interrupt is enabled.
• Vsync frequency measurement:
• In first interrupt of the cycle, timer 0 is programmed
to be used as free running timer with foscl12 clock.
TRO bit is set to start counting (GATE bit is reset). In
the second interrupt, TRO bit is reset to stop counting.
At this time, THO and TLO registers contain a
representative value of the V sync period (in /-!s if
l2MHz crystal is used) (see Figure 6).
Positive polarity
~i:e_p~l
t...
~el_p:ri~d~
J
Period
Negative polarity
~h-Ie~e~p~
Negative polarity
-u----~
t..
t
Period
J
Interrupt points
Figure 6. Vsync frequency measurement
MATRAMHS
Rev.B (10 Jan. 97)
Figure 7. Vsync polarity detection
•
•
Hsync polarity detection:
In the second interrupt of the cycle, during the V sync
high level duration measurement, the Hsync signal is
sampled 16 times, if number of high level samples is
greater than 8 then, Hsync has a negative polarity else
III.7.3
TEMIC
ANM059
it has a positive polarity (see Figure 8). Hsync input
filter is then set to accept negative pulses or positive
pulses respectively.
Semiconductors
,,~~ .. ~
rI
rI
PositivepoJarity
Yll!!£...J
~ ...... - - - - - - - . J
I--11111111111111111111111111111111111 _ _ _ 11111111111111111111111111111111111
Hsync
:..
Counting Period
Negative polarity
~
16 sampling points
Negative polarity
___ -----'L-
11111111111111111111111111111111111 - - - 1IIIIIIIIIIIIIIIIIIIIIIIIilIIIIIIII
Hsync
: ..
Counting Period
.. :
Figure 9. Hsync frequency measurement
16 sampling points
Figure 8. Hsync polarity detection
•
•
Hsync frequency measurement:
In the third interrupt of the cycle, timer 0 is
programmed to be used as external event counter with
Hsync clock. TRO bit is set to start counting. In the
fourth interrupt (last of the measurement cycle), TRO
bit is reset to stop counting. At this time, THO and TLO
registers contain a representative value of the Hsync
period that is the number of Hsync pulses during a
Vsync period (see Figure 9). A flag is set to inform
main program of the end of cycle.
When one cycle is completed, the main program checks
the values and determines whether if the video mode has
changed or not. If yes, the actions to take are listed
hereafter:
• Depending on the Hsync frequency, S correction
capacitors have to be updated.
• Some PWM values are updated.
• Video mute is activated.
• A research is made in EEPROM to find if the same
video mode is already stored.
• If yes recall user set-up (update PWM values) from
EEPROM, else default set-up is applied and the video
mute is released.
Free Running Generation Description
During manufacturing burn-in, monitors are powered,
but no video source is connected to the monitor. To force
deflection stages' activity, free running Hsync and Vsync
are output.
The software solution for free running generation, offers
to the user a maximum of flexibility to program the best
frequencies according to the deflection stages.
Two examples are proposed. In the first one, Vsync is a
60.lHz negative polarity signal with 66!-!s pulses and
Hsync is a 41.7KHz negative polarity signal with 2!-!s
pulses, in the second one Vsync is a 72Hz positive
polarity signal with 58!-!s pulses and Hsync is a 62.5KHz
positive polarity signal with l!-!s pulses.
Software Description
The software proposed hereafter is divided in two main
routines:
• The Vsync Interrupt service routine.
• The HsyncN sync free running generation routine.
mov
mov
cpl
mov
mov
cpl
mov
mov
III.7.4
All the routines are based on a 12MHz oscillator
operation; so 1 machine cycle has exactly l!-!s duration.
In the example, deflection stages are considered having
a negative polarity synchronization input. User can
program positive HsyncNsync outputs, by modifying the
software as follows:
C,Vpol_m
C
; set VOP bit for positive
ACC.3,C
; polarity on Vout
C,Hpol_ffi
C
; set HOP bit for positive
ACC.l,C
polarity on Hout
SOCR,A
; update Vout/Hout polarity
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
Vsync interrupt service routine has the highest priority.
Due to the sampling clock, the Vsync period has a basic
precision of Ills. Depending on the instruction executed
during the interrupt activation the measured period may
be increased up to 41ls. The validation of a new detected
video mode is effective only when the difference between
the new measured and the previously saved
period/counting is significant. This is achieved by the
Check_diff subroutine.
The reception of a character on serial port activates one
of the two HsyncN sync free running generation routine:
'1' for the first example, '2' for the second one.
The listing includes the file reg51cl.inc that is the
TSC8051Cl register declarations.
After a new video mode recognition, parameters are
stored in the following variables:
Vpol_s
Hpol_s
Vperl_s
Vperh_s
Hcntl s
Hcnth- s
Vsync
Hsync
Vsync
Vsync
Hsyne
Hsync
polarity
polarity
period high order byte
period low order byte
count high order byte
count low order byte
The table hereafter presents different video modes and
their associated parameters.
As the generation of the synchronization signals uses
100% of the CPU time, the only ways to disable
generation are to clear the activation flag during an
interrupt service routine (in the example, the flag is
cleared in Vsync interrupt when a video source is input)
or to apply a reset.
MATRAMHS
Rev.B (10 Jan. 97)
III.7.5
TEMIC
ANM059
Semiconductors
TEMIC 1996.
Demonstration program for video mode recognition
and free running generation with TSC 8051Cl
1
2
3
4
5
6
7
0080
0090
OOAD
OOBO
OODO
OOEO
OOFO
0081
0082
0083
0087
0088
0089
008A
008B
008C
008D
00A8
00B8
0098
0099
00D8
00D9
OODA
OODB
OOAF
00E4
00E5
00E6
OODF
00E7
00D7
OOEC
OOED
OOEE
OOEF
00F4
00F5
00F6
00F7
OOFC
OOFD
OOFE
OOFF
00D7
III.7.6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
$RB (0,1)
; bank 0 and 1 reserved
$ INCLUDE
(reg51cl.inc)
; register declarations
TEMIC 1996.
Register declarations for TSC 8051Cl microcontroller
Rev. A
DATA
DATA
DATA
DATA
OBOH
090H
OAOH
OBOH
SP
DPL
DPH
PCON
TCON
TMOD
TLO
TLl
THO
THl
IE
IP
SOCON
SOBUF
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
ODOH
OEOH
OFOH
081H
082H
083H
087H
088H
089H
08AH
OBBH
08CH
08DH
OA8H
OB8H
09BH
099H
SlCON
SlSTA
SlDAT
SlADR
DATA
DATA
DATA
DATA
ODBH
OD9H
ODAH
ODBH
MSCON
EICON
SOCR
HWDR
PWMCON
MXCRo
MXCR1
PWMO
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWMB
PWM9
PWM10
PWM11
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
OAFh
OE4h
OE5h
OE6h
ODFh
OE7h
OD7h
OECh
OEDh
OEEh
OEFh
OF4h
OF5h
OF6h
OF7h
OFCh
OFDh
OFEh
OFFh
; BIT Registers
; PSW
Cy
BIT
OD7H
Pl
P2
P3
PSW
ACC
B
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
00D6
ODDS
00D4
00D3
00D2
DODO
008F
008E
008D
008C
008B
008A
0089
0088
OOAF
GOAD
OOAC
OOAB
OOAA
00A9
00A8
OOBD
OOBC
OOBB
OOBA
00B9
00B8
00B7
00B7
00B6
00B6
00B5
00B5
00B4
00B4
00B3
00B3
00B2
00B2
00B1
OOBO
009F
009E
009D
009C
009B
009A
0099
0098
00D85
00D9
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
126
MATRAMHS
Rev.B (10 Jan. 97)
AC
FO
RS1
RSO
OV
P
BIT
BIT
BIT
BIT
BIT
BIT
OD6H
OD5H
OD4H
OD3H
OD2H
ODOH
TCON
TF1
TR1
TFO
TRO
IE1
IT1
lEO
ITO
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
08FH
08EH
08DH
08CH
08BH
08AH
089H
088H
; IE
EA
ES1
ESO
ET1
EX1
ETO
EXO
BIT
BIT
BIT
BIT
BIT
BIT
BIT
OAFH
OADH
OACH
OABH
OAAH
OA9H
OA8H
; IPO
PS1
PSO
PT1
PXl
PTO
PXO
BIT
BIT
BIT
BIT
BIT
BIT
OBDH
OBCH
OBBH
OBAH
OB9H
OB8H
; P3
RD
SDA
WR
SCL
T1
HOUT
TO
HSYNC
INT1
VOUT
INTO
VSYNC
TXD
RXD
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
OB7H
OB7H
OB6H
OB6H
OB5H
OB5H
OB4H
OB4H
OB3H
OB3H
OB2H
OB2H
OB1H
OBOH
; SOCON
SMO
SM1
SM2
REN
TB8
RB8
TI
RI
BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT
09FH
09EH
09DH
09CH
09BH
09AH
099H
098H
; SlCON
CRO
CR1
BIT
BIT
OD8H
OD9H
I
III.7.7
TEMIC
ANM059
OODA
OODB
OODC
OODD
OODE
0080
00D7
0035
OOCF
0002
0006
0008
0002
0020
0021
0022
0023
0024
0025
0030
0031
0032
0033
0034
0035
0036
0037
0038
0039
0000
0000 0106
0003
0003 0200FC
III.7.8
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
Semiconductors
AA
SI
STO
STA
ENS1
ODAH
ODBH
ODCH
ODDH
ODEH
BIT
BIT
BIT
BIT
BIT
; CONSTANT DEFINITION
EQU
80h
2s watchdog period
HOUT_VOUT_SET
HOUT_VOUT_CLR
HOUT_VOUT_ENA
HOUT_VOUT_DIS
EQU
EQU
EQU
EQU
00101000b
1l010111b
001l0101b
1l001111b
Hout/Vout~l
Hout/Vout enabled
Hout/Vout disabled
EICON_H_NEG
EICON_H_POS
EQU
EQU
00000010b
OOOOOllOb
negative Hsyne selection
positive Hsyne selection
VSYNC_DIFF
HSYNC_DIFF
EQU
EQU
8
2
7us~Vsync
Hout/Vout~O
1
diff authorised
diff authorised
pulse~Hsync
BIT VARIABLE DEFINITION
BSEG AT 20h
DBIT
1
DBIT
1
DBIT
1
DBIT
1
DBIT
1
DBIT
1
measured Vsync polarity
measured Hsyne polarity
saved Vsync polarity
saved Hsyne polarity
measuring end cycle flag (1)
Free running generation flag (1)
DATA VARIABLE DEFINITION
-----------------------DSEG AT 30h
Isr- state:
1
DS
Vper1_m:
DS
1
Vperh_m:
DS
1
Hcntl_m:
DS
1
Hcnth_m:
DS
1
Vperl_s:
DS
1
Vperh_s:
DS
1
Hcntl s:
DS
1
Hcnth- s:
DS
1
Interrupt state flag
measured period high order byte
measured period low order byte
measured count high order byte
measured count low order byte
saved period high order byte
saved period low order byte
saved count high order byte
saved count low order byte
Stack:
16 bytes stack
Vpol_m:
Hpol_m:
Vpol_s:
Hpol_s:
End_cycle:
Free- run:
DS
10h
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
BEGIN CODE
;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
USING
CSEG
ORG
ajmp
0
RBO used by default
OOOOh
Reset
reset address
ORG
ljmp
0003h
Vsync_isr
VSYNC (INTO)
interrupt
MATRA MRS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
0006 758138
0009 78FF
OOOB 7600
OOOD D8FC
OOOF
0012
0015
0018
758DE6
758BOO
758921
758841
001B 758700
001E 759852
0021 75A881
0024 75B801
0027 75E680
002A 202410
002D 75E680
0030 3098F7
0033 C298
0035 E599
0037 B43104
003A llB3
003C 012A
003E B432E9
0041 3104
0043 012A
0045
0046
0048
004A
004C
004E
E4
A220
92EO
A222
9400
702A
0050
0052
0054
0056
0058
A221
92EO
A223
9400
7020
005A A831
005C A932
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
MATRAMHS
Rev.B (10 Jan. 97)
;~~~~~~~=~==~~==~=~~~=~~=~~==~==~~===~~~===~~=~~==~=======~===~=======
INITIALISATION
;====~======================~========~~~=~=~~=~==~========~===~==~==~=
Reset:
mov
SP,#Stack-1
stack pointer initialisation
mov
mov
djnz
RO,#OFFh
@RO,#OOH
RO,Ram_init
Internal RAM initialisation
Ram_init:
mov
mov
mov
mov
TH1,#OE6h
TL1,#00h
TMOD,#21h
TCON,#41h
T1
at
TO
T1
mov
mov
PCON,#OOh
SOCON,#52h
SMOD~O
mov
mov
IE,#81h
IP,#Olh
lEO enabled
lEO high priority
mov
HWDR,#WDT_PER
watchdog activation
used as baud rate generator
1200 bauds with 12MHz crystal
16b counter, T1 8b autoreload
run, INTO falling edge
8-bit UART, Rx enabled
II
;============~=~=~~======~======~================~~=========~=====~=~====
MAIN PROGRAM
;===~===~=~==~===~=======~=~====~=================================~======
Wait_sync:
jb
mov
End_cycle, Check_mode
HWDR,#WDT_PER ; watchdog refresh
here must be inserted the
man-machine interface control
jnb
clr
mov
RI,Wait_sync
RI
A,SOBUF
example for free running
cjne
acall
ajmp
A,#'l' ,test_car
H_V_sync_gen_l; Free running generation
Wait_sync
cjne
acall
A,#'2' ,Wait_sync
H_V_sync_gen_2
; Free running generation
ajmp
Check_mode:
clr
mov
mov
mov
subb
jnz
C,Vpol_m
ACC.O,C
C,Vpol_s
A, #00
Mode_changed
Vsync polarity changed
mov
mov
mov
subb
jnz
C,Hpol_ffi
ACC.O,C
C,Hpol_s
A, #00
Mode_changed
Hsync polarity changed
mov
mov
RO,Vperl_m
R1,Vperh_m
A
III.7.9
TEMIC
ANM059
005E
0060
0062
0064
0066
AA35
AB36
7C08
11AO
7012
0086
0088
008A
008D
A220
9222
853135
853236
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
0068
006A
006C
006E
0070
0072
0074
A833
A934
AA37
AB38
7C02
11AO
7004
0090
0092
0094
0097
A221
9223
853337
853438
286
287
288
289
290
0076 C224
0078 012A
007A
007A 7435
007C A220
007E 92E3
0080 A221
0082 92El
0084 F5E5
009A 31F9
009C C224
009E 012A
III.7.10
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
Semiconductors
mov
mov
mov
acall
jnz
R2,Vperl_s
R3,Vperh_s
R4,#VSYNC_DIFF
Check_diff
Mode_changed
mov
RO,Hcntl_m
compare new & old period
Vsync period changed
mov
Rl,Hcnth_ID
mov
R2,Hcntl_s
mov
mov
acall
jnz
R3,Hcnth_s
R4,#HSYNC_DIFF
Check_diU
Mode_changed
clr
ajmp
End_cycle
Wait_sync
a new cycle can start
setb
acall
Video_mute
Cs select
video mute during mode change
S correction capacitors update
depending on Vsync period
mov
mov
mov
mov
mov
mov
A,#HOUT_VOUT_ENA
C,Vpol_m
set VOP bit for negative
ACC.3,C
polarity on Vout
C,Hpol_m
set HOP bit for negative
ACC.1, C
polarity on Hout
SOCR,A
update Vout/Hout polarity
mov
mov
mov
mov
C,Vpol_ffi
compare new & old counting
Vsync period changed
Mode_changed:
user define
user define
mov
mov
mov
mov
Vpol_s,C
save new Vsync polarity
Vperl_s,Vperl_m
Vperh_s, Vperh_m
save new vsync period
C,Hpol_m
Hpol_s,C
save new Hsyne polarity
Hcntl _s,Hcntl_m
Hcnth_s,Hcnth_m
save new Hsyne period
Here must be inserted the research of this video mode in EEPROM
if it is already stored, then recall user's screen parameters
if not, recall factory default screen parameters.
This new mode will be stored in EEPROM after user adjustments
user define
acall
Out results
send results tCl serial port
clr
clr
ajmp
Video_mute
End_cycle
Wait _sync
end of video mute
a new cycle can start
SUBROUTINES
This subroutine checks if the absolute difference of two words
is less than a given byte value
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
313
314
315
316
317
318
319
320
OOAO
00A1
00A2
00A3
C3
E9
9B
700D
00A5 E8
00A6 9A
00A7 5003
00A9 C3
OOAA EA
OOAB 98
OOAC B50400
OOAF 5001
00B1 E4
00B2
00B3
00B5
00B7
00B9
ESE5
54CF
FSE5
D225
OOBB
OOBE
OOBF
00C1
00C3
53BOD7
00
D2B5
790A
D9FE
00C5
00C7
00C8
OOCA
OOCC
C2BS
00
D2BS
790A
D9FE
OOCE
OODO
00D1
00D3
OODS
00D7
C2B5
00
D2B5
7907
D9FE
D2B3
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
3S9
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
MATRAMHS
Rev.B (10 Jan. 97)
Inputs:
RO:
R1:
R2:
R3:
R4:
word 1 low order byte
word 1 high order byte
word 2 low order byte
word 2 high order byte
limit of difference
Outputs:
A:
if A = 0 the difference is less than the limit
else the difference is greater than or equal to
the limit
c1r
mov
subb
jnz
C
A,R1
A,R3
End check
mov
subb
jnc
A,RO
A,R2
Check...:pos
clr
mov
subb
C
A,R2
A,RO
cjne
jnc
clr
ret
A,AR4,$+3
End_check
A
Check...:pos:
A=MSB difference
MSB not equal
A=LSB difference
negative difference
A=LSB difference
This subroutine generates free Running synchronization Signals
Hout
Vout
41.7KHz with 2us negative pulses
60.1Hz with 66us negative pulses
H_V_sync_gen_l:
clr
mov
anI
mov
setb
A,SOCR
A,#HOUT_VOUT_DIS
SOCR,A
select P3.3/P3.5 as Vout/Hout
Free_run
i set flag (cleared in Vsync isr)
anI
nop
setb
mov
djnz
HOUT
R1,#10
R1,$
2us neg pulse on Hout
HOUT
nop
setb
mov
djnz
HOUT
R1, #10
R1,$
2us neg pulse on Hout
clr
nop
setb
mov
djnz
setb
20us tempo
20us tempo
HOUT
ROUT
R1,#7
R1,$
VOUT
2us neg pulse on Hout
14us tempo
66us neg pulse on Vout
III. 7 .11
TEMIC
ANM059
00D9
OODB
OODC
OODD
78E6
00
00
75E680
OOEO
00E2
00E3
00E5
00E7
C2B5
00
D2B5
790A
D9FE
00E9
OOEB
OOEC
OOEE
OOFO
C2B5
00
D2B5
790A
D9FE
00F2
00F4
00F5
00F7
00F9
C2B5
00
D2B5
7906
D9FE
OOFB 302505
OOFE
0100
0101
0103
D8DB
00
01BB
22
0104
0106
0108
010A
E5E5
54CF
F5E5
D225
010C
010F
0111
0112
0114
53BOD7
D2B5
00
7906
D9FE
0116
0118
011A
011B
011D
C2B5
D2B5
00
7906
D9FE
011F
0121
0123
0124
C2B5
D2B5
00
7906
III.7.12
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
Semiconductors
H-pulse_1:
mov
nop
nop
mov
RO,#230
clr
nop
setb
mov
djnz
HOUT
clr
nop
setb
mov
djnz
HOUT
clr
nop
setb
mov
djnz
jnb
230 * 3 Hsync pulses
watchdog refresh
HOUT
R1,#10
R1,$
HOUT
R1,#10
R1,$
2us neg pulse on Hout
20us tempo
2us neg pulse on Hout
20us tempo
HOUT
HOUT
R1,#6
R1,$
2us neg pulse on Hout
12us tempo
Free_run, End_gen_l
; Free running enabled
400
djnz
401
402
nop
403
ajmp
404
End_gen_1:
ret
405
406
407;--------------------------------------------------------------------------408
409
This subroutine generates free Running synchronization Signals
410
411
Hout
62.5KHz with 1us positive pulses
412
72Hz with 58us positive pulses
Vout
413
414;--------------------------------------------------------------------------415
416
H_V_sync_gen_2: mov
A,SOCR
A,#HOUT_VOUT_DIS
417
anI
418
SOCR,A
mov
select P3.3/P3.5 as Vout/Hout
419
setb
Free run
; set flag (cleared in Vsync isr)
420
421
V-pulse_2:
orl
422
clr
HOUT
; lus pos pulse on Hout
423
nop
R1,#6
424
mov
djnz
Rl,$
12us tempo
425
426
427
HOUT
setb
428
clr
HOUT
lus pos pulse on Hout
429
nop
430
mov
R1,#6
431
djnz
12us tempo
Rl,$
432
433
setb
HOUT
434
HOUT
clr
lus pos pulse on Hout
435
nap
R1,#6
436
mov
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
0126 D9FE
0128
012A
012C
012D
012F
0131
C2B5
D2B5
00
7903
D9FE
D2B3
0133
0135
0136
0137
78D8
00
00
75E680
013A
013C
013E
013F
0141
C2B5
D2B5
00
7906
D9FE
0143
0145
0147
0148
014A
C2B5
D2B5
00
7906
D9FE
014C
014E
0150
0151
0153
C2B5
D2B5
00
7906
D9FE
0155
0157
0159
015A
015C
C2B5
D2B5
00
7902
D9FE
015E 302505
0161
0163
0164
0166
D8D2
00
210C
22
0167 C225
0169 302401
016C 32
016D COEO
016F CODO
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
H-pul se_2:
djnz
Rl, $
12us tempo
setb
c1r
nop
mov
djnz
clr
HOUT
HOUT
1us pas pulse on Hout
R1,#3
R1,$
VOUT
6us tempo
58us pos pulse on Vout
RO,#216
216 * 4 Hsync pulses
mov
nop
nop
mov
setb
clr
nop
mov
djnz
HWDR,#WDT_PER ;watchdog refresh
HOUT
HOUT
Ius pas pulse on Haut
Rl, #6
Rl, $
12us tempo
setb
clr
nop
mov
djnz
HOUT
HOUT
Ius pcs pulse on Haut
R1,#6
R1,$
12us tempo
setb
clr
nop
mov
djnz
HOUT
HOUT
Ius pas pulse on Haut
Rl, #6
R1,$
12us tempo
HOUT
HOUT
1us pos pulse on Hout
setb
clr
nap
mov
djnz
jnb
Rl,#2
Rl, $
;
II
4us tempo
Free_run, End_gen_2
; Free running enabled
476
477
djnz
RO,H-pulse_2
478
nop
ajmp
V-pulse_2
479
End_gen_2:
480
ret
481
482
483
484
485;--------------------------------------------------------------------------486
487
This routine is the VSYNC interrupt service routine
488
489;--------------------------------------------------------------------------490
USING
1
RBI used in interrupt
491
Vsync_isr:
492
clr
Free run
stop Free running
493
jnb
End_cyc1e,Vsync_beg_isr
; Cycle not yet treated
494
reti
495
Vsync_beg_isr:
496
push
ACC
497
push
PSW
MATRAMHS
Rev.B (10 Jan. 97)
III.7.13
TEMIC
ANM059
0171 75D008
0174 E530
0176
0179
017C
017F
0182
0184
0186
B4000F
758921
758AOO
758COO
D28C
0530
21F3
0188
018B
018C
018D
018E
018F
0191
0194
0197
019A
019D
01AD
B40133
00
00
00
00
C28C
858A31
858C32
758929
758AOO
758COO
D28C
01A2
01A3
01A5
01A7
01A9
01AB
01AE
01BO
01B2
E4
7810
A2B4
3400
D8FA
B40800
9221
4005
75E402
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
01B5 21BA
01B7 75E406
531
532
01BA 0530
01BC 21F3
OlBE
01Cl
01C4
01C7
01C9
01CC
B4021B
758925
758ADO
A88C
758COO
D28C
01CE
01DO
01Dl
01D2
01D5
01D6
01D8
01DA
E532
C3
13
B50800
B3
9220
0530
21F3
01DC
01DD
01DE
01DF
OlEO
01El
00
00
00
00
00
00
III.7.14
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
Semiconductors
State 0:
mav
mav
P8W,#08h
A,Isr_state
cjne
A,#OO,state_l
TMOD,#21h
TLO,#OOh
THO,#OOh
TRO
Isr_state
Vsync_end_isr
mav
mav
mav
setb
inc
ajmp
State 1:
cjne
nap
nap
nap
nap
clr
mov
setb
clr
A
81 1:
81 2:
mav
mav
addc
djnz
cjne
mav
jc
mav
ajmp
TO
free running 16-bit timer
start measuring Vsync period
nap are inserted for timing
compensation between start
and stop counting
TRO
Vperl_m,TLO
Vperh_m, THO
TMOD,#29h
TLO,#OOh
THO,#OOh
TRO
mav
mav
mav
mav
RBl selection
load 18R state
stop TO
store Vsync period
TO : gated 16-bit timer
start measuring Vsync high level
Hsync polarity detection
RO,#16
16 samples
C,H8YNC
read pin level
A,#OO
store state
RO,81_1
A,#08,81_2
Hpal_m,C
; store Hsyne polarity (0
neg)
Sl 3
EICON,#EICON_H_NEG
i negative Hsyne pulses selection
Sl 4
EICON,#EICON_H_POS
; positive Hsyne pulses selection
Sl 3:
mav
Sl 4:
inc
ajmp
Isr_state
Vsync_end_isr
State 2:
cjne
mov
mov
mov
mov
setb
A,#02,state_3
TMOD,#25h
TLO,#OOh
RO,THO
THO,#OOh
TRO
mov
clr
rrc
cjne
cpl
mov
inc
ajmp
A,Vperh_m
C
Vsync polarity detection
A
A = Vsync period / 20
test only high order byte
82 1:
state 3:
nap
nop
nop
nop
nop
nap
A,ARO,S2_1
TO : 16-bit counter
save MSB
start counting Hsyne pulses
C
Vpal_m,C
Isr_state
store Vsync polarity (0
=
neg)
Vsync_end_isr
nop are inserted for timing
compensation between start
and stop counting
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
ANM059
Semiconductors
01E2
01E3
01E4
01ES
01E6
01E8
01EB
01EE
00
00
00
00
C28C
858A33
858C34
753000
01Fl D224
01F3 DODO
01F5 DOEO
01F7 32
01F8
01FB
01FD
01FF
0201
0203
0205
0207
0209
020B
020D
020F
0211
0213
0216
0218
021A
021C
021E
0220
0222
0224
0226
0228
022A
022C
022E
900256
512F
E536
5139
E535
5139
7420
514E
742D
A222
5002
742B
514E
90025F
512F
E538
5139
E537
5139
7420
514E
742D
A223
5002
742B
514E
22
559
560
561
562
563
564
565
566
nop
nop
nop
nop
clr
mov
mov
mov
567
568
569
570
571
572
573
574
575
576
577
578
setb
Vsync_end_isr:
TRO
Hcntl_m,TLO
Hcnth_m, THO
Isr_state, #00
pop
pop
reti
PSW
ACC
USING
o
stop TO
store Hsync pulse count
reset ISR state to start a new
cycle
; set flag for the main program
REO used by default
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
The subroutines hereafter are only used for
demonstration program+
579
+
580
j++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
MATRAMHS
Rev.B (10 Jan. 97)
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Send measured parameters on serial port
; Vsync period, polarity
; Hsync counting, polarity
+
+
+
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Out_results:
Vpol_neg:
Hpol_neg:
mov
acall
mov
acall
mov
acall
mov
acall
mov
mov
jnc
mov
acall
DPTR, #Vsync_msge
Out_msge
i display Vsync message
A,Vperh_s
Out_byte
A,Vperl_s
Out_byte
display Vsync period
A,#' ,
Out_char
A,#'-'
c,Vpol_s
Vpol_neg
A,#'+'
Out_char
; display Vsync polarity
mov
acall
mov
acall
mov
acall
mov
acall
mov
mov
jnc
mov
acall
ret
DPTR,#Hsync_msge
Out_msge
; display Hsync message
A,Hcnth_s
Out_byte
A,Hcntl_s
Out_byte
display Hsync count
A,#' ,
Out_char
A,#'-'
c,Hpol_s
Hpol_neg
A,#'+'
Out_char
display Hsync polarity
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Send a message on serial port
DPTR is the message address
a NUL character is the end of message
+
+
+
III.7.15
II
TEMIC
ANM059
620
621
622
623
624
625
626
627
628
629
630
631
632
0239 CO EO
633
023B C4
634
023C 5143
635
023E DOEO
636
0240 5143
637
0242 22
638
639
640
641
642
643
0243 540F
644
0245 2490
645
0247 D4
646
0248 3440
647
024A D4
648
024B 514E
649
024D 22
650
651
652
653
654
655
024E 3099FD 656
0251 C299
657
0253 F599
658
0255 22
659
660
661
662
663
0256 OAOD5673 664
025A 796E6320
025E 00
025F OAOD4873 665
0263 796E6320
0267 00
022F
0230
0231
0233
0234
0236
0238
III.7.16
E4
93
6005
A3
514E
412F
22
Semiconductors
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Out_msge:
clr
move
jz
inc
acall
ajmp
ret
A
A,@A+DPTR
Out - end
DPTR
Out - char
Out_msge
last character
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
; Send a hexadecimal byte on serial port
; A is the byte to send
+
+
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Out_byte:
PUSH
SWAP
ACALL
POP
ACALL
ret
ACC
A
Out nib
ACC
Out_nib
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
; Send a hexadecimal nibble on serial port
; A is the nibble to send
+
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Out_nib:
ANL
ADD
DA
ADDC
DA
acall
ret
A,#OFH
A,#90H
A
A,#40H
A
Out - char
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;Send an ASCII character on serial port
; A is the character to send
+
j+++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++
Out char:
jnb
clr
mov
ret
TI,Out char
TI
SOBUF,A
j+++++++++++++++++++++++++++++++++++++++++++++++++++++ +++++++++++++++++++
Messages definition
+
i
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
DB
OAh, ODh, 'Vsync ',0
DB
OAh,ODh, 'Hsync ',0
MATRAMHS
Rev.B (10 Jan. 97)
TEMIC
Semiconductors
Section IV
Introduction to C251 Architecture
C2S1 OverviewlBenefits vs CS1 .......•.•....•.........•.••...•....••.••..•. IV.1.0
Extended 8-bit TSC802S1Products Overview .•..•.........•••.•...•.••••...•• IV.3.0
II
TEMIC
Semiconductors
C2S1 Overview/Benefits vs CS1
C251 Architecture Overview: .............................................. IV.I.1
Extended 8-bit microcontroller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IV1.1
TSC80251 Derivatives ...................................................... IVl.1
TSC80251 Documentation .................................................. IVl.2
Microcontroller Architecture ................................................. IVl.3
TSC80251: ACIDC Characteristics .......................................... IV.2.1
AC Characteristics ......................................................... IY.2.1
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. IV2.6
II
TEMIC
Semiconductors
C251 Architecture Overview
C251 Architecture Overview
Extended 8-bit microcontroller
In the world of 8-bit microcontrollers, the C51
Architecture has become an industry standard for
embedded applications. For over 15 years, TEMIC has
been a leading provider of this microcontroller family.
This unsurpassed experience is the driving force as
TEMIC takes this proven family to the next level of
performance: the TSC80251 family!
This new C251 Architecture at its lowest performance
level (binary mode), is binary code compatible with the
80C51 microcontrollers, hence, attaining an increase in
performance has never been easier.
Due to a 3-stage pipeline, the CPU-performance is
increased by a factor 5, using existing C51 code without
modifications.
The 24-bit address bus will allow to access up to 16
Mbytes in a single linear memory space. Please see each
individual TSC80251 Product Datasheet for the effective
addressable memory range.
Programming flexibility and C-code efficiency are both
increased through a Register-based Architecture, the
64-Kbyte extended stack space combining with the new
instruction set.
C251 C-compilers are some of the most efficient
available (nearly no overhead), coupled with the final
codesize which could be a factor of 3 down when
compared with the C51 C-compilers.
U sing the new C251 instruction set, the performance will
increase up to 15 times at the same clock rate. This
performance enhancement is based on the 16-bit
instruction bus, allowing for more powerful instructions
and additional internal instruction bus, 8-bit and 16-bit
data busses.
II
TSC80251 Derivatives
TEMIC is rapidly developing a full family of application
specific TSC80251 derivatives. Please see the detailed
Datasheet of each product for further information.
•
Communication:
Cordless phones
Cellular phones
High speed modems
High-end feature phones
ISDN phones
• Line cards
Network termination
•
Computer:
High-end monitors
CD-ROM
Card-reader
Disk drives
Computer telephony
•
Broadcast media:
Set top boxes
Audio/video control
Signal processing
These products are designed to help you getting
high-performance products to market faster.
Due to the high instruction throughput, the TSC80251
derivatives are focussing on all high-end 8-bit to 16-bit
applications.
TSC80251 derivatives are also used in mid-range and
lower-end microcontroller applications, where a very
low operation frequency is needed, without decreasing
the level of CPU-power.
This feature is ideal for today portable applications and
EMC sensitive systems.
Typical applications for this family are:
• Automotive:
Airbag
ABS
Gearbox
Climate control
Car radio
Car navigation
MATRAMHS
Rev. C (14 Jan. 96)
IV. 1.1
C251 Architecture Overview
TEMIC's TSC80251 derivatives are designed around the
C251 core, using standard peripherals dedicated to a
targetted range of applications.
Here is a selection of peripheral blocks:
•
Serial interfaces:
• UART (Universal Asynchronous
Transmitter)
• 12C (Inter-Integrated Circuit)
• SPI (Serial Protocol Interface)
• fJ.Wire (Synchronous Serial Interface)
• CAN (Control Area Network)
• J1850
• USB (Universal Serial Bus)
•
Receiver
GCI
TEMIC
Semiconductors
•
Special interfaces:
• ADC (Analog to Digital Converter)
• DAC (Digital to Analog Converter)
• PCA (Programmable Counter Array)
• PWM (Pulse Width Modulator)
• Smart Sensor Interfaces
• Control functions:
• Watchdog Timer
• Timers/Counters
• Power monitoring and management
• Interrupt handler
• Memories:
• RAM
• ROM
• OTPROM
• EPROM
Most of TEMIC's TSC80251 derivatives are available as
ROMless, OTPROM, EPROM and Mask ROM version.
TSC80251 Documentation
The following documentation and Starter tools are
available to allow the full evaluation of the TEMIC's
TSC80251 derivatives:
• "TSC80251 Design Guides" (for each derivative)
Contains all information about the products (Block
Diagram, Configuration and Memory Mapping,
Ports, Peripheral Description, Electrical and
Mechanical Information, Ordering Information) and
Application Notes.
• "TSC80251 Programmer's Guide"
Contains all information for the programmer
Programming,
(Architecture, Instruction Set,
Development Tools).
• "TSC80251 Product Starter Kit"
This kit enables the product to be evaluated by the
IY.1.2
designer.
Its contents is:
• C-Compiler (limited to 2 Kbytes of code)
• Assembler
• Linker
• Product Simulator
• Optionally TSC80251 Product Evaluation Board
with ROM-Monitor
• Please visit our WWW for updated versions in ZIP
format.
•
World Wide Web
Please contact our WWW for possible updated
information at http://www.temic.de
•
TSC80251 e-mail hotline:C251@temic.fr
MATRAMHS
Rev. C (14 Jan. 96)
TEMIC
C251 Architecture Overview
Semiconductors
Microcontroller Architecture
The TSC802Sl family of 8-bit microcontrollers is a
high-performance upgrade of the widely-used 80CSI
microcontrollers. It extends features and performance
while maintaining binary-code compatibility, so the
impact on existing hardware and software is minimal.
All TSC802Sl microcontrollers share a set of common
features:
• 24-bit linear addressing and up to 16 Mbytes of
memory
• a register-based CPU with registers accessible as
bytes, words, and double words
• a page mode for accelerating external instruction
fetches
• an instruction pipeline
• an enriched instruction set, including 16-bit
arithmetic and logic instructions
• a 64-Kbyte extended stack space
• a minimum instruction-execution time of two clocks
(vs. 12 clocks for 80CS1 microconlrollers)
•
binary-code
compatibility
microcontrollers
with
80CSI
Several benefits are derived from these features:
•
80CSI
preservation of code
written
for
microcontrollers
a significant increase in core execution speed in
comparison with 80CSI microcontrollers at the same
clock rate
•
•
support for larger programs and more data
increased efficiency for code written in C
•
Figure 1. is a functional block diagram of TSC802S1
microcontrollers. The core, which is common to all
TSC802S1 microcontrollers, is described in the next
paragraph. Each derivative in the family has its own
on-chip peripherals, I/O Ports, external bus, size of
on-chip RAM, type and size of on-chip ROM.
Clock
PORTS
EPROM
ROM
II
RAM
Reset
Peripherals
~"
!rl
>'I
=
<.l
u
~
:::
~
0
.s
oil
~
;::
!rl
>'I
..."
~
:E
ob
..Q
..lN
CPU
Figure 1. TSC80251 Product Block Diagram
MATRAMHS
Rev. C (14 Jan. 96)
IV. 1.3
TEMIC
C251 Architecture Overview
Semiconductors
Microcontroller Core
The TSC80251 microcontroller core contains the CPU,
the clock and reset unit, the interrupt handler, the bus
interface and the peripheral interface (See Figure 1. ).
The CPU contains the instruction sequencer, ALU,
register file and data memory interface (See Figure 2. ).
CPU
The TSC80251 fetches instructions from on-chip code
memory two bytes at a time or from external memory in
single bytes. The instructions are sent over the 16-bit
code bus to the execution unit. You can configure the
TSC80251 to operate in page mode for accelerated
instruction fetches from external memory. In page mode,
if an instruction fetch is to the same 256-byte "page" as
the previous fetch, the fetch requires one state (two
clocks) rather than two states (four clocks). For
information regarding the page or non-page mode
selection, see Product Datasheet.
The TSC8025I register file has forty registers, which can
be accessed as bytes, words and double words. As in the
C51 Architecture, registers 0-7 consist of four banks of
eight registers each, where the active bank is selected by
the program status word (PSW) for fast context switches
(See "Programming" chapter).
The TSC8025I is a single-pipeline machine. When the
pipeline is full and code is executing from on-chip code
memory, an instruction is completed every state time.
When the pipeline is full and code is executing from
external memory (with no wait states and no extension of
the ALE signal) an instruction is completed every two
state times.
address
code
Instruction Sequencer
. ._ _ _ Interrupt
Handler
SRCI
8
SRC2
8
14--::8".e;..... . .
24
data
address
Figure 2. Central Processor Unit Block Diagram
IV. 1.4
MATRAMHS
Rev. C (14 Jan. 96)
TEMIC
C251 Architecture Overview
Semiconductors
Clock and Reset Unit
The timing source for the TSC80251 microcontroller can
be an external oscillator or an internal oscillator with an
external crystal/resonator. The basic unit of time in
TSC80251 is the state time (or state), which is two
oscillator periods. The state time is divided into phase 1
and phase 2 (See Figure 3. ).
Phase I
PI
Phase 2
P2
XTALl
I:
State I
PI
I P2
State 2
PI I
P2
Tosc
~
~I
2 Tosc = State Time
State 3
PI
State 4
I P2
PI
I P2
State 5
PI
I P2
State 6
PI
I P2
Figure 3. Clocking Definitions
The TSC80251 peripherals operate on a peripheral cycle,
which is six state times. (This peripheral cycle is not a
characteristic of the C251 Architecture.) A one-clock
interval in a peripheral cycle is denoted by its state and
phase.
The reset unit places the TSC80251 into a known state. A
chip reset is initiated by asserting the RST pin or allowing
the Watchdog Timer to time out when the TSC80251 has
one.
Interrupt Handler
The interrupt handler can receive interrupt requests from
many sources: maskable sources and TRAP instruction.
When the interrupt handler grants an interrupt request, the
CPU discontinues the normal flow of instructions and
branches to a routine that services the source that
requested the interrupt. You can enable or disable the
interrupts individually (except for TRAP which cannot be
disabled) and you can assign one of four priority levels to
each interrupt.
MATRAMHS
Rev. C (14 Jan. 96)
IV.1.5
II
TEMIC
TSC80251
Semiconductors
A C/DC Characteristics
AC Characteristics
Table
1. AC
Characteristics (Capacitive Loading
12 MHz
Symbol
Parameter
Min
Max
= 50 pF)
16 MHz
Min
. Max
Fosc
,Min
Max
Units.
Tose
IIFose
83
63
TLHLL
ALE Pulse Width
73
53
Tose -10
ns (2)
ns (2)
ns
TAVLL
Address Valid to ALE Low
63
43
Tose- 20
TLLAX
Address hold after ALE Low
63
43
Tose- 20
ns
TRLRH
(I)
RD# or PSEN# Pulse Width
65
45
Tose- 18
ns (3)
TWLWH
WR# Pulse Width
65
45
Tose- 18
ns (3)
TLLRL
(I)
ALE Low to RD# or PSEN# Low
73
53
Tosc- 10
ns
TRHRL
ALE High to RD# or PSEN# High
73
53
Tose 10
ns
TLHAX
ALE high to Address hold
147
2Tose - 20
ns (2)
Tose- 50
ns (3)
0
ns
TRLDV(I)
RD# or PSEN# Low to Valid
Data/Instruction.
TRHDX (1)
Data!Instruct. hold After RD# or
PSEN#high
105
13
33
0
0
TRLAZ(I)
RD#IPSEN# Low to Address Float
2
2
2
ns
TRHDZ(1)
Data/Instruct. Float After RD# or
PSEN#high
63
43
Tose- 20
ns
TRHLHI
(I)
RD#IPSEN# high to ALE high
(Instruction)
68
48
Tose - 15
ns (1)
TRHLH2
(I)
RD#/PSEN# high to ALE high
235
173
3Tose- 15
ns (I)
TWHLH
WR# high to ALE high
TAVDVI
Address (PO) Valid to Valid
Data/Instruction In
190
128
3Tose - 60
ns
(2,3,4)
TAVDV2
Address (P2) Valid to Valid
Data/Instruction In
273
190
4Tose - 60
ns
(2,3,4,)
TAVDV3
Address (PO) Valid to Valid
Instruction In
128
88
2Tose - 38
ns
TAVRL
(Data)
Address Valid to RD#IPSEN# Low
235
173
ns
3Tose - 15
143
!OI
2Tose - 24
ns (2)
TAVWLl
Address (PO) Valid to WR# Low
143
101
2Tose - 24
ns (2)
TAVWL2
Address (P2) Valid to WR# Low
220
158
3Tose - 30
ns (2)
TWHQX
Data hold after WR# high
63
43
Tose- 20
ns
TQVWH
Data Valid to WR# high
58
38
Tose- 25
ns (3)
TWHAX
WR# high to Address hold
147
105
2Tose - 20
ns
TXLXL
Serial Port Clock Cycle Time
1000
750
12 Tose
ns
MATRAMHS
Rev, C (14 Jan.
IV.2,)
96)
II
TEMIC
TSC80251
Semiconductors
TQVSH
Output Data Setup to Clock Rising
Edge
870
620
12 TOSC - 133
ns
TXHQX
Output Data hold after Clock Rising
Edge
720
510
10 Tosc - 117
ns
TXHDX
Input Data Hold after Clock Rising
Edge
0
0
o
ns
TXHDV
Clock Rising Edge to Input Data
Valid
700
500
10 TosC - 133
ns
Notes:
I. Specifications for PSEN# are identical to those for RD#.
2. If a wait state is added by extending ALE, add 2TOSC.
3. If a wait state is added by extending RD#IPSEN#IWR#, add 2Tosc.
4. If wait states are added as described in both Note 2 and Note 3, add a total of 4Tosc.
ALE
PSEN#
PO
P2
'-.r
--<'-------~
A15:8
* The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 1. External Instruction Bus Cycle in Non-Page Mode
IY.2.2
MATRAMHS
Rev. C (14 Jan. 96)
TEMIC
TSC80251
Semiconductors
ALE
PSEN#
PO
P2
I..
--<~
__________
V
A_15_:8________~~
* The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 2. External Data Read Cycle in Non-Page Mode
II
ALE
WR#
PO
P2
*The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 3. External Write Data Bus Cycle in Non-Page Mode
MATRAMHS
Rev. C (14 Jan. 96)
IV.2.3
TEMIC
TSC80251
Semiconductors
ALE
PSEN#
P2
....I----TAVDV'*
TAVDV2*
PO
A7:0
Pagehit**
Page Miss **
* The value of this parameter depends on wait states. See the table of AC characteristics.
** A page hit (i.e., a code fetch to the same 256-byte "page" as the previous code fetch) requires one state
(2Toscl; a page miss requires two states (4Toscl.
Figure 4. External Instrnction Bus Cycle in Page Mode
ALE
RD#PSEN#
T
P2
D7:0
I~
PO
--<~
_____________
A_7:0__________
~>-<~
___
* The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 5. External Read Data Bus Cycle in Page Mode
IV.2.4
MATRAMHS
Rev. C (14 Jan. 96)
TEMIC
TSC80251
Semiconductors
ALE
WR#
P2
PO
A7:0
* The value of this parameter depends on wait states. See the table of AC characteristics.
Figure 6. External Write Data Bus Cycle in Page Mode
TXLXL
----u----u----u----u----u----u----u
TXD __
II
TXHQX
TQVXH
RXD
(Out)
RXD
(Tn)
* TT and RI are set during S IPI of the peripheral cycle following the shift of the eight bit.
Figure 7. Serial Port Waveform - Shift Register Mode
Notation for timing parameters name
A = Address
D = Data
Q = Data out
S = Supply (VPP )
MATRAMHS
Rev. C (14 Jan. 96)
E = Enable
V = Valid
G=PROG#
X = No Longer Valid
H = high
L=Low
z= Floating
IY.2.5
TEMIC
TSC80251
Semiconductors
DC Characteristics
Table 2. Absolute Maximum Ratings
• Ambient Temperature Under Bias
Commercial
Industrial
o to +70°C
--40 to +85°C
oto +125°C
Automotive
• Storage Temperature. ,
-65 to + 150°C
.......... .
• Voltage on EA#NPP Pin to VSS ..
o to +13.0 V
• Voltage on any other Pin to VSS
-0.5 to +6.5 V
• IOLper 1/0 Pin
ISmA
• Power Dissipation
1.5W
Note:
Stresses at or above those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Table 3. DC Characteristics
Parameter values applied to all devices unless otherwise indicated.
Commercial
Industrial
Automotive
TA = 0 to 70°C
VSS =OV
VDD=5V± 10%
TA = --40 to +85°C
VSS =OV
VDD=SV±IO%
TA = --40 to + 125°C
VSS =OV
VDD=SV± 10%
VIL
Input Low Voltage
(except EA#)
-D.5
0.2VDD-0.l
V
VILl
Input Low Voltage
(EA#)
0
0.2VDD- 0.3
V
VIH
Input high Voltage
(except XTALl, RST)
0.2VDD +0.9
VDD + 0.5
V
VIHl
Input high Voltage
(XTALl)
0.7VDD
VDD + 0.5
V
VOL
Output Low Voltage
(Ports I, 2, 3)
0.3
0.45
1.0
V
VRST+
Reset threshold on
3.7
V
VRST-
Reset threshold off
3.3
V
VRET
VDD data retention limit
2
V
VOLI
Output Low Voltage
(Ports 0, ALE, PSEN#)
VOH
Output high Voltage
(Ports I, 2, 3, ALE, PSEN#)
IY.2.6
0.3
0.45
1.0
VDD-O.3
VDD-0.7
VDD-1.5
IOL= 100 IlA
IOL= 1.6 rnA
IOL= 3.S rnA
(1,2)
V
IOL= 200 IlA
10[,= 3.2mA
IOL=7.0mA
(1,2)
V
IOH = -10 IlA
IOH= -30 IlA
IOH = -60 IlA
(3)
MATRAMHS
Rev. C (14 Jan. 96)
TEMIC
TSC80251
Semiconductors
VOH]
Output high Voltage
(Pbrt 0 in External Address)
VDD-O.3
VDD-0.7
VDD-1.5
V
IOH=-200 I1A
IOH =-3.2 rnA
IOH=-7.0 rnA
VOH2
Output high Voltage
(Port 2 in External Address during
Page Mode)
VDD-0.3
VDD-0.7
VDD-1.5
V
IOH= -200 I1A
IOH=-3.2 rnA
IOH = -7.0 rnA
IlL
- 50
- 75
I1A
Input Leakage Current
(Port 0)
±lO
I1A
0.45
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